target-arm queue: I have a lot more still in my to-review

queue, but my rule of thumb is when I get to 50 patches or

so to send out what I have.

thanks

-- PMM

The following changes since commit 9a7beaad3dbba982f7a461d676b55a5c3851d312:

Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20210304' into staging (2021-03-05 10:47:46 +0000)

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210305

for you to fetch changes up to 2c669ff88ec6733420a000103a2b8b9e93df4945:

hw/arm/mps2: Update old infocenter.arm.com URLs (2021-03-05 15:17:38 +0000)

* sbsa-ref: remove cortex-a53 from list of supported cpus

* sbsa-ref: add 'max' to list of allowed cpus

* target/arm: Add support for FEAT_SSBS, Speculative Store Bypass Safe

* npcm7xx: add EMC model

* xlnx-zynqmp: Remove obsolete 'has_rpu' property

* target/arm: Speed up aarch64 TBL/TBX

* virtio-mmio: improve virtio-mmio get_dev_path alog

* target/arm: Use TCF0 and TFSRE0 for unprivileged tag checks

* target/arm: Restrict v8M IDAU to TCG

* target/arm/cpu: Update coding style to make checkpatch.pl happy

* musicpal, tc6393xb, omap_lcdc, tcx: drop dead code for non-32-bit-RGB surfaces

* Add new board: mps3-an524

Doug Evans (3):

hw/net: Add npcm7xx emc model

hw/arm: Add npcm7xx emc model

tests/qtests: Add npcm7xx emc model test

Marcin Juszkiewicz (2):

sbsa-ref: remove cortex-a53 from list of supported cpus

sbsa-ref: add 'max' to list of allowed cpus

Peter Collingbourne (1):

target/arm: Use TCF0 and TFSRE0 for unprivileged tag checks

Peter Maydell (34):

hw/arm/musicpal: Remove dead code for non-32-bit-RGB surfaces

hw/display/tc6393xb: Remove dead code for handling non-32bpp surfaces

hw/display/tc6393xb: Expand out macros in template header

hw/display/tc6393xb: Inline tc6393xb_draw_graphic32() at its callsite

hw/display/omap_lcdc: Expand out macros in template header

hw/display/omap_lcdc: Drop broken bigendian ifdef

hw/display/omap_lcdc: Fix coding style issues in template header

hw/display/omap_lcdc: Inline template header into C file

hw/display/omap_lcdc: Delete unnecessary macro

hw/display/tcx: Drop unnecessary code for handling BGR format outputs

hw/arm/mps2-tz: Make SYSCLK frequency board-specific

hw/misc/mps2-scc: Support configurable number of OSCCLK values

hw/arm/mps2-tz: Correct the OSCCLK settings for mps2-an505 and mps2-an511

hw/arm/mps2-tz: Make the OSCCLK settings be configurable per-board

hw/misc/mps2-fpgaio: Make number of LEDs configurable by board

hw/misc/mps2-fpgaio: Support SWITCH register

hw/arm/mps2-tz: Make FPGAIO switch and LED config per-board

hw/arm/mps2-tz: Condition IRQ splitting on number of CPUs, not board type

hw/arm/mps2-tz: Make number of IRQs board-specific

hw/misc/mps2-scc: Implement CFG_REG5 and CFG_REG6 for MPS3 AN524

hw/arm/mps2-tz: Correct wrong interrupt numbers for DMA and SPI

hw/arm/mps2-tz: Allow PPCPortInfo structures to specify device interrupts

hw/arm/mps2-tz: Move device IRQ info to data structures

hw/arm/mps2-tz: Size the uart-irq-orgate based on the number of UARTs

hw/arm/mps2-tz: Allow boards to have different PPCInfo data

hw/arm/mps2-tz: Make RAM arrangement board-specific

hw/arm/mps2-tz: Set MachineClass default_ram info from RAMInfo data

hw/arm/mps2-tz: Support ROMs as well as RAMs

hw/arm/mps2-tz: Get armv7m_load_kernel() size argument from RAMInfo

hw/arm/mps2-tz: Add new mps3-an524 board

hw/arm/mps2-tz: Stub out USB controller for mps3-an524

hw/arm/mps2-tz: Provide PL031 RTC on mps3-an524

docs/system/arm/mps2.rst: Document the new mps3-an524 board

hw/arm/mps2: Update old infocenter.arm.com URLs

Philippe Mathieu-Daudé (4):

hw/arm/xlnx-zynqmp: Remove obsolete 'has_rpu' property

hw/i2c/npcm7xx_smbus: Simplify npcm7xx_smbus_init()

target/arm: Restrict v8M IDAU to TCG

target/arm/cpu: Update coding style to make checkpatch.pl happy

Rebecca Cran (3):

target/arm: Add support for FEAT_SSBS, Speculative Store Bypass Safe

target/arm: Enable FEAT_SSBS for "max" AARCH64 CPU

target/arm: Set ID_PFR2.SSBS to 1 for "max" 32-bit CPU

target/arm: Speed up aarch64 TBL/TBX

schspa (1):

virtio-mmio: improve virtio-mmio get_dev_path alog

docs/system/arm/mps2.rst | 24 +-

docs/system/arm/nuvoton.rst | 3 +-

hw/display/omap_lcd_template.h | 169 --------

hw/display/tc6393xb_template.h | 72 ----

include/hw/arm/armsse.h | 4 +-

include/hw/arm/npcm7xx.h | 2 +

include/hw/arm/xlnx-zynqmp.h | 2 -

include/hw/misc/armsse-cpuid.h | 2 +-

include/hw/misc/armsse-mhu.h | 2 +-

include/hw/misc/iotkit-secctl.h | 2 +-

include/hw/misc/iotkit-sysctl.h | 2 +-

include/hw/misc/iotkit-sysinfo.h | 2 +-

include/hw/misc/mps2-fpgaio.h | 8 +-

include/hw/misc/mps2-scc.h | 10 +-

include/hw/net/npcm7xx_emc.h | 286 +++++++++++++

include/ui/console.h | 10 -

target/arm/cpu.h | 15 +-

target/arm/helper-a64.h | 2 +-

target/arm/internals.h | 6 +

hw/arm/mps2-tz.c | 632 +++++++++++++++++++++++-----

hw/arm/mps2.c | 5 +

hw/arm/musicpal.c | 64 ++-

hw/arm/npcm7xx.c | 50 ++-

hw/arm/sbsa-ref.c | 2 +-

hw/arm/xlnx-zynqmp.c | 6 -

hw/display/omap_lcdc.c | 129 +++++-

hw/display/tc6393xb.c | 48 +--

hw/display/tcx.c | 31 +-

hw/i2c/npcm7xx_smbus.c | 1 -

hw/misc/armsse-cpuid.c | 2 +-

hw/misc/armsse-mhu.c | 2 +-

hw/misc/iotkit-sysctl.c | 2 +-

hw/misc/iotkit-sysinfo.c | 2 +-

hw/misc/mps2-fpgaio.c | 43 +-

hw/misc/mps2-scc.c | 93 ++++-

hw/net/npcm7xx_emc.c | 857 ++++++++++++++++++++++++++++++++++++++

hw/virtio/virtio-mmio.c | 13 +-

target/arm/cpu.c | 23 +-

target/arm/cpu64.c | 5 +

target/arm/cpu_tcg.c | 8 +

target/arm/helper-a64.c | 32 --

target/arm/helper.c | 39 +-

target/arm/mte_helper.c | 13 +-

target/arm/translate-a64.c | 70 +---

target/arm/vec_helper.c | 48 +++

tests/qtest/npcm7xx_emc-test.c | 862 +++++++++++++++++++++++++++++++++++++++

hw/net/meson.build | 1 +

hw/net/trace-events | 17 +

tests/qtest/meson.build | 3 +-

49 files changed, 3098 insertions(+), 628 deletions(-)

delete mode 100644 hw/display/omap_lcd_template.h

delete mode 100644 hw/display/tc6393xb_template.h

create mode 100644 include/hw/net/npcm7xx_emc.h

create mode 100644 hw/net/npcm7xx_emc.c

create mode 100644 tests/qtest/npcm7xx_emc-test.c

From: Rebecca Cran <rebecca@nuviainc.com>

Add support for FEAT_SSBS. SSBS (Speculative Store Bypass Safe) is an

optional feature in ARMv8.0, and mandatory in ARMv8.5.

Signed-off-by: Rebecca Cran <rebecca@nuviainc.com>

Message-id: 20210216224543.16142-2-rebecca@nuviainc.com

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

target/arm/cpu.h | 15 ++++++++++++++-

target/arm/internals.h | 6 ++++++

target/arm/helper.c | 37 +++++++++++++++++++++++++++++++++++++

target/arm/translate-a64.c | 12 ++++++++++++

4 files changed, 69 insertions(+), 1 deletion(-)

#define SCTLR_TE (1U << 30) /* AArch32 only */

#define SCTLR_EnIB (1U << 30) /* v8.3, AArch64 only */

#define SCTLR_EnIA (1U << 31) /* v8.3, AArch64 only */

+#define SCTLR_DSSBS_32 (1U << 31) /* v8.5, AArch32 only */

#define SCTLR_BT0 (1ULL << 35) /* v8.5-BTI */

#define SCTLR_BT1 (1ULL << 36) /* v8.5-BTI */

#define SCTLR_ITFSB (1ULL << 37) /* v8.5-MemTag */

@@ -XXX,XX +XXX,XX @@ void pmu_init(ARMCPU *cpu);

#define SCTLR_TCF (3ULL << 40) /* v8.5-MemTag */

#define SCTLR_ATA0 (1ULL << 42) /* v8.5-MemTag */

#define SCTLR_ATA (1ULL << 43) /* v8.5-MemTag */

-#define SCTLR_DSSBS (1ULL << 44) /* v8.5 */

+#define SCTLR_DSSBS_64 (1ULL << 44) /* v8.5, AArch64 only */

#define CPTR_TCPAC (1U << 31)

#define CPTR_TTA (1U << 20)

@@ -XXX,XX +XXX,XX @@ void pmu_init(ARMCPU *cpu);

#define CPSR_IL (1U << 20)

#define CPSR_DIT (1U << 21)

#define CPSR_PAN (1U << 22)

+#define CPSR_SSBS (1U << 23)

#define CPSR_J (1U << 24)

#define CPSR_IT_0_1 (3U << 25)

#define CPSR_Q (1U << 27)

@@ -XXX,XX +XXX,XX @@ void pmu_init(ARMCPU *cpu);

#define PSTATE_A (1U << 8)

#define PSTATE_D (1U << 9)

#define PSTATE_BTYPE (3U << 10)

+#define PSTATE_SSBS (1U << 12)

#define PSTATE_IL (1U << 20)

#define PSTATE_SS (1U << 21)

#define PSTATE_PAN (1U << 22)

@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa32_dit(const ARMISARegisters *id)

return FIELD_EX32(id->id_pfr0, ID_PFR0, DIT) != 0;

}

+static inline bool isar_feature_aa32_ssbs(const ARMISARegisters *id)

+{

+ return FIELD_EX32(id->id_pfr2, ID_PFR2, SSBS) != 0;

+}

+

/*

* 64-bit feature tests via id registers.

*/

@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_dit(const ARMISARegisters *id)

return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, DIT) != 0;

}

+static inline bool isar_feature_aa64_ssbs(const ARMISARegisters *id)

+{

+ return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, SSBS) != 0;

+}

+

/*

* Feature tests for "does this exist in either 32-bit or 64-bit?"

*/

@@ -XXX,XX +XXX,XX @@ static inline uint32_t aarch32_cpsr_valid_mask(uint64_t features,

if (isar_feature_aa32_dit(id)) {

valid |= CPSR_DIT;

}

+ if (isar_feature_aa32_ssbs(id)) {

+ valid |= CPSR_SSBS;

+ }

return valid;

}

@@ -XXX,XX +XXX,XX @@ static inline uint32_t aarch64_pstate_valid_mask(const ARMISARegisters *id)

if (isar_feature_aa64_dit(id)) {

valid |= PSTATE_DIT;

}

+ if (isar_feature_aa64_ssbs(id)) {

+ valid |= PSTATE_SSBS;

+ }

if (isar_feature_aa64_mte(id)) {

valid |= PSTATE_TCO;

}

diff --git a/target/arm/helper.c b/target/arm/helper.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/helper.c

+++ b/target/arm/helper.c

@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo dit_reginfo = {

.readfn = aa64_dit_read, .writefn = aa64_dit_write

};

+static uint64_t aa64_ssbs_read(CPUARMState *env, const ARMCPRegInfo *ri)

+{

+ return env->pstate & PSTATE_SSBS;

+}

+

+static void aa64_ssbs_write(CPUARMState *env, const ARMCPRegInfo *ri,

+ uint64_t value)

+{

+ env->pstate = (env->pstate & ~PSTATE_SSBS) | (value & PSTATE_SSBS);

+}

+

+static const ARMCPRegInfo ssbs_reginfo = {

+ .name = "SSBS", .state = ARM_CP_STATE_AA64,

+ .opc0 = 3, .opc1 = 3, .crn = 4, .crm = 2, .opc2 = 6,

+ .type = ARM_CP_NO_RAW, .access = PL0_RW,

+ .readfn = aa64_ssbs_read, .writefn = aa64_ssbs_write

+};

+

static CPAccessResult aa64_cacheop_poc_access(CPUARMState *env,

const ARMCPRegInfo *ri,

bool isread)

@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)

if (cpu_isar_feature(aa64_dit, cpu)) {

define_one_arm_cp_reg(cpu, &dit_reginfo);

}

+ if (cpu_isar_feature(aa64_ssbs, cpu)) {

+ define_one_arm_cp_reg(cpu, &ssbs_reginfo);

+ }

if (arm_feature(env, ARM_FEATURE_EL2) && cpu_isar_feature(aa64_vh, cpu)) {

define_arm_cp_regs(cpu, vhe_reginfo);

@@ -XXX,XX +XXX,XX @@ static void take_aarch32_exception(CPUARMState *env, int new_mode,

env->uncached_cpsr &= ~(CPSR_IL | CPSR_J);

env->daif |= mask;

+ if (cpu_isar_feature(aa32_ssbs, env_archcpu(env))) {

+ if (env->cp15.sctlr_el[new_el] & SCTLR_DSSBS_32) {

+ env->uncached_cpsr |= CPSR_SSBS;

+ } else {

+ env->uncached_cpsr &= ~CPSR_SSBS;

+ }

+ }

+

if (new_mode == ARM_CPU_MODE_HYP) {

env->thumb = (env->cp15.sctlr_el[2] & SCTLR_TE) != 0;

env->elr_el[2] = env->regs[15];

@@ -XXX,XX +XXX,XX @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs)

new_mode |= PSTATE_TCO;

}

+ if (cpu_isar_feature(aa64_ssbs, cpu)) {

+ if (env->cp15.sctlr_el[new_el] & SCTLR_DSSBS_64) {

+ new_mode |= PSTATE_SSBS;

+ } else {

+ new_mode &= ~PSTATE_SSBS;

+ }

+ }

+

pstate_write(env, PSTATE_DAIF | new_mode);

env->aarch64 = 1;

aarch64_restore_sp(env, new_el);

diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/translate-a64.c

+++ b/target/arm/translate-a64.c

@@ -XXX,XX +XXX,XX @@ static void handle_msr_i(DisasContext *s, uint32_t insn,

tcg_temp_free_i32(t1);

break;

+ case 0x19: /* SSBS */

+ if (!dc_isar_feature(aa64_ssbs, s)) {

+ goto do_unallocated;

+ }

+ if (crm & 1) {

+ set_pstate_bits(PSTATE_SSBS);

+ } else {

+ clear_pstate_bits(PSTATE_SSBS);

+ }

+ /* Don't need to rebuild hflags since SSBS is a nop */

+ break;

+

case 0x1a: /* DIT */

if (!dc_isar_feature(aa64_dit, s)) {

goto do_unallocated;

2.20.1

Fix some minor coding style issues in the template header,

so checkpatch doesn't complain when we move the code.

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

Message-id: 20210215103215.4944-8-peter.maydell@linaro.org

hw/display/omap_lcd_template.h | 6 +++---

1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/hw/display/omap_lcd_template.h b/hw/display/omap_lcd_template.h

--- a/hw/display/omap_lcd_template.h

+++ b/hw/display/omap_lcd_template.h

@@ -XXX,XX +XXX,XX @@ static void draw_line2_32(void *opaque, uint8_t *d, const uint8_t *s,

b = (pal[v & 3] << 4) & 0xf0;

((uint32_t *) d)[0] = rgb_to_pixel32(r, g, b);

d += 4;

- s ++;

+ s++;

width -= 4;

} while (width > 0);

}

@@ -XXX,XX +XXX,XX @@ static void draw_line4_32(void *opaque, uint8_t *d, const uint8_t *s,

b = (pal[v & 0xf] << 4) & 0xf0;

((uint32_t *) d)[0] = rgb_to_pixel32(r, g, b);

d += 4;

- s ++;

+ s++;

width -= 2;

} while (width > 0);

}

@@ -XXX,XX +XXX,XX @@ static void draw_line8_32(void *opaque, uint8_t *d, const uint8_t *s,

g = pal[v] & 0xf0;

b = (pal[v] << 4) & 0xf0;

((uint32_t *) d)[0] = rgb_to_pixel32(r, g, b);

- s ++;

+ s++;

d += 4;

} while (-- width != 0);

2.20.1

From: Peter Collingbourne <pcc@google.com>

Section D6.7 of the ARM ARM states:

For the purpose of determining Tag Check Fault handling, unprivileged

load and store instructions are treated as if executed at EL0 when

executed at either:

- EL1, when the Effective value of PSTATE.UAO is 0.

- EL2, when both the Effective value of HCR_EL2.{E2H, TGE} is {1, 1}

and the Effective value of PSTATE.UAO is 0.

ARM has confirmed a defect in the pseudocode function

AArch64.TagCheckFault that makes it inconsistent with the above

wording. The remedy is to adjust references to PSTATE.EL in that

function to instead refer to AArch64.AccessUsesEL(acctype), so

that unprivileged instructions use SCTLR_EL1.TCF0 and TFSRE0_EL1.

The exception type for synchronous tag check faults remains unchanged.

This patch implements the described change by partially reverting

commits 50244cc76abc and cc97b0019bb5.

Signed-off-by: Peter Collingbourne <pcc@google.com>

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Message-id: 20210219201820.2672077-1-pcc@google.com

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

---

target/arm/helper.c | 2 +-

target/arm/mte_helper.c | 13 +++++++++----

2 files changed, 10 insertions(+), 5 deletions(-)

@@ -XXX,XX +XXX,XX @@ static uint32_t rebuild_hflags_a64(CPUARMState *env, int el, int fp_el,

if (FIELD_EX32(flags, TBFLAG_A64, UNPRIV)

&& tbid

&& !(env->pstate & PSTATE_TCO)

- && (sctlr & SCTLR_TCF)

+ && (sctlr & SCTLR_TCF0)

&& allocation_tag_access_enabled(env, 0, sctlr)) {

flags = FIELD_DP32(flags, TBFLAG_A64, MTE0_ACTIVE, 1);

}

diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/mte_helper.c

+++ b/target/arm/mte_helper.c

@@ -XXX,XX +XXX,XX @@ static void mte_check_fail(CPUARMState *env, uint32_t desc,

reg_el = regime_el(env, arm_mmu_idx);

sctlr = env->cp15.sctlr_el[reg_el];

- el = arm_current_el(env);

- if (el == 0) {

+ switch (arm_mmu_idx) {

+ case ARMMMUIdx_E10_0:

+ case ARMMMUIdx_E20_0:

+ el = 0;

tcf = extract64(sctlr, 38, 2);

- } else {

+ break;

+ default:

+ el = reg_el;

tcf = extract64(sctlr, 40, 2);

@@ -XXX,XX +XXX,XX @@ static void mte_check_fail(CPUARMState *env, uint32_t desc,

env->exception.vaddress = dirty_ptr;

is_write = FIELD_EX32(desc, MTEDESC, WRITE);

- syn = syn_data_abort_no_iss(el != 0, 0, 0, 0, 0, is_write, 0x11);

+ syn = syn_data_abort_no_iss(arm_current_el(env) != 0, 0, 0, 0, 0,

+ is_write, 0x11);

raise_exception(env, EXCP_DATA_ABORT, syn, exception_target_el(env));

/* noreturn, but fall through to the assert anyway */

2.20.1

The AN505 and AN521 have the same device layout, but the AN524 is

somewhat different. Allow for more than one PPCInfo array, which can

be selected based on the board type.

Message-id: 20210215115138.20465-16-peter.maydell@linaro.org

hw/arm/mps2-tz.c | 16 ++++++++++++++--

1 file changed, 14 insertions(+), 2 deletions(-)

diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c

--- a/hw/arm/mps2-tz.c

+++ b/hw/arm/mps2-tz.c

@@ -XXX,XX +XXX,XX @@ static void mps2tz_common_init(MachineState *machine)

MemoryRegion *system_memory = get_system_memory();

DeviceState *iotkitdev;

DeviceState *dev_splitter;

+ const PPCInfo *ppcs;

+ int num_ppcs;

int i;

if (strcmp(machine->cpu_type, mc->default_cpu_type) != 0) {

@@ -XXX,XX +XXX,XX @@ static void mps2tz_common_init(MachineState *machine)

* + wire up the PPC's control lines to the IoTKit object

*/

- const PPCInfo ppcs[] = { {

+ const PPCInfo an505_ppcs[] = { {

.name = "apb_ppcexp0",

.ports = {

{ "ssram-0", make_mpc, &mms->ssram_mpc[0], 0x58007000, 0x1000 },

@@ -XXX,XX +XXX,XX @@ static void mps2tz_common_init(MachineState *machine)

},

};

- for (i = 0; i < ARRAY_SIZE(ppcs); i++) {

+ switch (mmc->fpga_type) {

+ case FPGA_AN505:

+ case FPGA_AN521:

+ ppcs = an505_ppcs;

+ num_ppcs = ARRAY_SIZE(an505_ppcs);

+ break;

+ default:

+ g_assert_not_reached();

+ for (i = 0; i < num_ppcs; i++) {

const PPCInfo *ppcinfo = &ppcs[i];

TZPPC *ppc = &mms->ppc[i];

DeviceState *ppcdev;

2.20.1

The AN505 and AN521 have the same layout of RAM; the AN524 does not.

Replace the current hard-coding of where the RAM is and which parts

of it are behind which MPCs with a data-driven approach.

Message-id: 20210215115138.20465-17-peter.maydell@linaro.org

hw/arm/mps2-tz.c | 175 +++++++++++++++++++++++++++++++++++++----------

1 file changed, 138 insertions(+), 37 deletions(-)

diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c

--- a/hw/arm/mps2-tz.c

+++ b/hw/arm/mps2-tz.c

@@ -XXX,XX +XXX,XX @@

#include "qom/object.h"

#define MPS2TZ_NUMIRQ_MAX 92

+#define MPS2TZ_RAM_MAX 4

typedef enum MPS2TZFPGAType {

FPGA_AN505,

FPGA_AN521,

} MPS2TZFPGAType;

+/*

+ * Define the layout of RAM in a board, including which parts are

+ * behind which MPCs.

+ * mrindex specifies the index into mms->ram[] to use for the backing RAM;

+ * -1 means "use the system RAM".

+ */

+typedef struct RAMInfo {

+ const char *name;

+ uint32_t base;

+ uint32_t size;

+ int mpc; /* MPC number, -1 for "not behind an MPC" */

+ int mrindex;

+ int flags;

+} RAMInfo;

+/*

+ * Flag values:

+ * IS_ALIAS: this RAM area is an alias to the upstream end of the

+ * MPC specified by its .mpc value

+ */

+#define IS_ALIAS 1

+

struct MPS2TZMachineClass {

MachineClass parent;

MPS2TZFPGAType fpga_type;

@@ -XXX,XX +XXX,XX @@ struct MPS2TZMachineClass {

uint32_t fpgaio_num_leds; /* Number of LEDs in FPGAIO LED0 register */

bool fpgaio_has_switches; /* Does FPGAIO have SWITCH register? */

int numirq; /* Number of external interrupts */

+ const RAMInfo *raminfo;

const char *armsse_type;

};

@@ -XXX,XX +XXX,XX @@ struct MPS2TZMachineState {

MachineState parent;

ARMSSE iotkit;

- MemoryRegion ssram[3];

- MemoryRegion ssram1_m;

+ MemoryRegion ram[MPS2TZ_RAM_MAX];

MPS2SCC scc;

MPS2FPGAIO fpgaio;

TZPPC ppc[5];

- TZMPC ssram_mpc[3];

+ TZMPC mpc[3];

PL022State spi[5];

ArmSbconI2CState i2c[4];

UnimplementedDeviceState i2s_audio;

@@ -XXX,XX +XXX,XX @@ static const uint32_t an505_oscclk[] = {

25000000,

};

+static const RAMInfo an505_raminfo[] = { {

+ .name = "ssram-0",

+ .base = 0x00000000,

+ .size = 0x00400000,

+ .mpc = 0,

+ .mrindex = 0,

+ }, {

+ .name = "ssram-1",

+ .base = 0x28000000,

+ .size = 0x00200000,

+ .mpc = 1,

+ .mrindex = 1,

+ }, {

+ .name = "ssram-2",

+ .base = 0x28200000,

+ .size = 0x00200000,

+ .mpc = 2,

+ .mrindex = 2,

+ }, {

+ .name = "ssram-0-alias",

+ .base = 0x00400000,

+ .size = 0x00400000,

+ .mpc = 0,

+ .mrindex = 3,

+ .flags = IS_ALIAS,

+ }, {

+ /* Use the largest bit of contiguous RAM as our "system memory" */

+ .name = "mps.ram",

+ .base = 0x80000000,

+ .size = 16 * MiB,

+ .mpc = -1,

+ .mrindex = -1,

+ }, {

+ .name = NULL,

+ },

+};

+

+static const RAMInfo *find_raminfo_for_mpc(MPS2TZMachineState *mms, int mpc)

+ MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms);

+ const RAMInfo *p;

+

+ for (p = mmc->raminfo; p->name; p++) {

+ if (p->mpc == mpc && !(p->flags & IS_ALIAS)) {

+ return p;

+ /* if raminfo array doesn't have an entry for each MPC this is a bug */

+ g_assert_not_reached();

+static MemoryRegion *mr_for_raminfo(MPS2TZMachineState *mms,

+ const RAMInfo *raminfo)

+ /* Return an initialized MemoryRegion for the RAMInfo. */

+ MemoryRegion *ram;

+

+ if (raminfo->mrindex < 0) {

+ /* Means this RAMInfo is for QEMU's "system memory" */

+ MachineState *machine = MACHINE(mms);

+ return machine->ram;

+

+ assert(raminfo->mrindex < MPS2TZ_RAM_MAX);

+ ram = &mms->ram[raminfo->mrindex];

+

+ memory_region_init_ram(ram, NULL, raminfo->name,

+ raminfo->size, &error_fatal);

+ return ram;

/* Create an alias of an entire original MemoryRegion @orig

* located at @base in the memory map.

*/

@@ -XXX,XX +XXX,XX @@ static MemoryRegion *make_mpc(MPS2TZMachineState *mms, void *opaque,

const int *irqs)

TZMPC *mpc = opaque;

- int i = mpc - &mms->ssram_mpc[0];

- MemoryRegion *ssram = &mms->ssram[i];

+ int i = mpc - &mms->mpc[0];

MemoryRegion *upstream;

- char *mpcname = g_strdup_printf("%s-mpc", name);

- static uint32_t ramsize[] = { 0x00400000, 0x00200000, 0x00200000 };

- static uint32_t rambase[] = { 0x00000000, 0x28000000, 0x28200000 };

+ const RAMInfo *raminfo = find_raminfo_for_mpc(mms, i);

+ MemoryRegion *ram = mr_for_raminfo(mms, raminfo);

- memory_region_init_ram(ssram, NULL, name, ramsize[i], &error_fatal);

-

- object_initialize_child(OBJECT(mms), mpcname, mpc, TYPE_TZ_MPC);

- object_property_set_link(OBJECT(mpc), "downstream", OBJECT(ssram),

+ object_initialize_child(OBJECT(mms), name, mpc, TYPE_TZ_MPC);

+ object_property_set_link(OBJECT(mpc), "downstream", OBJECT(ram),

&error_fatal);

sysbus_realize(SYS_BUS_DEVICE(mpc), &error_fatal);

/* Map the upstream end of the MPC into system memory */

upstream = sysbus_mmio_get_region(SYS_BUS_DEVICE(mpc), 1);

- memory_region_add_subregion(get_system_memory(), rambase[i], upstream);

+ memory_region_add_subregion(get_system_memory(), raminfo->base, upstream);

/* and connect its interrupt to the IoTKit */

qdev_connect_gpio_out_named(DEVICE(mpc), "irq", 0,

qdev_get_gpio_in_named(DEVICE(&mms->iotkit),

"mpcexp_status", i));

- /* The first SSRAM is a special case as it has an alias; accesses to

- * the alias region at 0x00400000 must also go to the MPC upstream.

- */

- if (i == 0) {

- make_ram_alias(&mms->ssram1_m, "mps.ssram1_m", upstream, 0x00400000);

- }

-

- g_free(mpcname);

/* Return the register interface MR for our caller to map behind the PPC */

return sysbus_mmio_get_region(SYS_BUS_DEVICE(mpc), 0);

}

@@ -XXX,XX +XXX,XX @@ static MemoryRegion *make_i2c(MPS2TZMachineState *mms, void *opaque,

return sysbus_mmio_get_region(s, 0);

}

+static void create_non_mpc_ram(MPS2TZMachineState *mms)

+{

+ /*

+ * Handle the RAMs which are either not behind MPCs or which are

+ * aliases to another MPC.

+ */

+ const RAMInfo *p;

+ MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms);

+

+ for (p = mmc->raminfo; p->name; p++) {

+ if (p->flags & IS_ALIAS) {

+ SysBusDevice *mpc_sbd = SYS_BUS_DEVICE(&mms->mpc[p->mpc]);

+ MemoryRegion *upstream = sysbus_mmio_get_region(mpc_sbd, 1);

+ make_ram_alias(&mms->ram[p->mrindex], p->name, upstream, p->base);

+ } else if (p->mpc == -1) {

+ /* RAM not behind an MPC */

+ MemoryRegion *mr = mr_for_raminfo(mms, p);

+ memory_region_add_subregion(get_system_memory(), p->base, mr);

+ }

+ }

+}

+

static void mps2tz_common_init(MachineState *machine)

{

MPS2TZMachineState *mms = MPS2TZ_MACHINE(machine);

@@ -XXX,XX +XXX,XX @@ static void mps2tz_common_init(MachineState *machine)

qdev_connect_gpio_out_named(iotkitdev, "sec_resp_cfg", 0,

qdev_get_gpio_in(dev_splitter, 0));

- /* The IoTKit sets up much of the memory layout, including

+ /*

+ * The IoTKit sets up much of the memory layout, including

* the aliases between secure and non-secure regions in the

- * address space. The FPGA itself contains:

- *

- * 0x00000000..0x003fffff SSRAM1

- * 0x00400000..0x007fffff alias of SSRAM1

- * 0x28000000..0x283fffff 4MB SSRAM2 + SSRAM3

- * 0x40100000..0x4fffffff AHB Master Expansion 1 interface devices

- * 0x80000000..0x80ffffff 16MB PSRAM

- */

-

- /* The FPGA images have an odd combination of different RAMs,

+ * address space, and also most of the devices in the system.

+ * The FPGA itself contains various RAMs and some additional devices.

+ * The FPGA images have an odd combination of different RAMs,

* because in hardware they are different implementations and

* connected to different buses, giving varying performance/size

* tradeoffs. For QEMU they're all just RAM, though. We arbitrarily

- * call the 16MB our "system memory", as it's the largest lump.

+ * call the largest lump our "system memory".

*/

- memory_region_add_subregion(system_memory, 0x80000000, machine->ram);

/*

* The overflow IRQs for all UARTs are ORed together.

@@ -XXX,XX +XXX,XX @@ static void mps2tz_common_init(MachineState *machine)

const PPCInfo an505_ppcs[] = { {

.name = "apb_ppcexp0",

.ports = {

- { "ssram-0", make_mpc, &mms->ssram_mpc[0], 0x58007000, 0x1000 },

- { "ssram-1", make_mpc, &mms->ssram_mpc[1], 0x58008000, 0x1000 },

- { "ssram-2", make_mpc, &mms->ssram_mpc[2], 0x58009000, 0x1000 },

+ { "ssram-0-mpc", make_mpc, &mms->mpc[0], 0x58007000, 0x1000 },

+ { "ssram-1-mpc", make_mpc, &mms->mpc[1], 0x58008000, 0x1000 },

+ { "ssram-2-mpc", make_mpc, &mms->mpc[2], 0x58009000, 0x1000 },

},

}, {

.name = "apb_ppcexp1",

@@ -XXX,XX +XXX,XX @@ static void mps2tz_common_init(MachineState *machine)

create_unimplemented_device("FPGA NS PC", 0x48007000, 0x1000);

+ create_non_mpc_ram(mms);

+

armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename, 0x400000);

}

@@ -XXX,XX +XXX,XX @@ static void mps2tz_an505_class_init(ObjectClass *oc, void *data)

mmc->fpgaio_num_leds = 2;

mmc->fpgaio_has_switches = false;

mmc->numirq = 92;

+ mmc->raminfo = an505_raminfo;

mmc->armsse_type = TYPE_IOTKIT;

}

@@ -XXX,XX +XXX,XX @@ static void mps2tz_an521_class_init(ObjectClass *oc, void *data)

mmc->fpgaio_num_leds = 2;

mmc->fpgaio_has_switches = false;

mmc->numirq = 92;

+ mmc->raminfo = an505_raminfo; /* AN521 is the same as AN505 here */

mmc->armsse_type = TYPE_SSE200;

}

2.20.1

Add support for the mps3-an524 board; this is an SSE-200 based FPGA

image, like the existing mps2-an521. It has a usefully larger amount

of RAM, and a PL031 RTC, as well as some more minor differences.

In real hardware this image runs on a newer generation of the FPGA

board, the MPS3 rather than the older MPS2. Architecturally the two

boards are similar, so we implement the MPS3 boards in the mps2-tz.c

file as variations of the existing MPS2 boards.

Message-id: 20210215115138.20465-21-peter.maydell@linaro.org

hw/arm/mps2-tz.c | 139 +++++++++++++++++++++++++++++++++++++++++++++--

1 file changed, 135 insertions(+), 4 deletions(-)

diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c

--- a/hw/arm/mps2-tz.c

+++ b/hw/arm/mps2-tz.c

@@ -XXX,XX +XXX,XX @@

* This source file covers the following FPGA images, for TrustZone cores:

* "mps2-an505" -- Cortex-M33 as documented in ARM Application Note AN505

* "mps2-an521" -- Dual Cortex-M33 as documented in Application Note AN521

+ * "mps2-an524" -- Dual Cortex-M33 as documented in Application Note AN524

*

* Links to the TRM for the board itself and to the various Application

* Notes which document the FPGA images can be found here:

@@ -XXX,XX +XXX,XX @@

* http://infocenter.arm.com/help/topic/com.arm.doc.dai0505b/index.html

* Application Note AN521:

* http://infocenter.arm.com/help/topic/com.arm.doc.dai0521c/index.html

+ * Application Note AN524:

+ * https://developer.arm.com/documentation/dai0524/latest/

*

* The AN505 defers to the Cortex-M33 processor ARMv8M IoT Kit FVP User Guide

* (ARM ECM0601256) for the details of some of the device layout:

* http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ecm0601256/index.html

- * Similarly, the AN521 uses the SSE-200, and the SSE-200 TRM defines

+ * Similarly, the AN521 and AN524 use the SSE-200, and the SSE-200 TRM defines

* most of the device layout:

* http://infocenter.arm.com/help/topic/com.arm.doc.101104_0100_00_en/corelink_sse200_subsystem_for_embedded_technical_reference_manual_101104_0100_00_en.pdf

*

@@ -XXX,XX +XXX,XX @@

#include "hw/qdev-clock.h"

#include "qom/object.h"

-#define MPS2TZ_NUMIRQ_MAX 92

+#define MPS2TZ_NUMIRQ_MAX 95

#define MPS2TZ_RAM_MAX 4

typedef enum MPS2TZFPGAType {

FPGA_AN505,

FPGA_AN521,

+ FPGA_AN524,

} MPS2TZFPGAType;

/*

@@ -XXX,XX +XXX,XX @@ struct MPS2TZMachineState {

TZPPC ppc[5];

TZMPC mpc[3];

PL022State spi[5];

- ArmSbconI2CState i2c[4];

+ ArmSbconI2CState i2c[5];

UnimplementedDeviceState i2s_audio;