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[PULL v2 00/19] riscv-to-apply queue

Alistair Francis posted 19 patches 3 years, 2 months ago
Test checkpatch passed
Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/20210304144651.310037-1-alistair.francis@wdc.com
Maintainers: Alistair Francis <Alistair.Francis@wdc.com>, Palmer Dabbelt <palmer@dabbelt.com>, Kevin Wolf <kwolf@redhat.com>, Bastian Koppelmann <kbastian@mail.uni-paderborn.de>, Sagar Karandikar <sagark@eecs.berkeley.edu>, Max Reitz <mreitz@redhat.com>, Alistair Francis <alistair@alistair23.me>
There is a newer version of this series
docs/system/riscv/sifive_u.rst                 | 336 +++++++++++++++++++++++
docs/system/target-riscv.rst                   |  72 +++++
docs/system/targets.rst                        |  20 +-
include/hw/riscv/sifive_u.h                    |   9 +-
include/hw/ssi/sifive_spi.h                    |  47 ++++
target/riscv/cpu.h                             |   6 +-
target/riscv/cpu_bits.h                        |   1 +
hw/block/m25p80.c                              |  57 +++-
hw/misc/sifive_u_otp.c                         |  13 +-
hw/riscv/microchip_pfsoc.c                     |   9 +-
hw/riscv/opentitan.c                           |   9 +-
hw/riscv/sifive_e.c                            |   9 +-
hw/riscv/sifive_u.c                            | 102 ++++++-
hw/riscv/spike.c                               |   9 +-
hw/riscv/virt.c                                |  68 +++--
hw/rtc/goldfish_rtc.c                          |   2 +
hw/ssi/sifive_spi.c                            | 358 +++++++++++++++++++++++++
target/riscv/arch_dump.c                       | 202 ++++++++++++++
target/riscv/cpu.c                             |   2 +
MAINTAINERS                                    |   9 +
hw/riscv/Kconfig                               |   3 +
hw/ssi/Kconfig                                 |   4 +
hw/ssi/meson.build                             |   1 +
pc-bios/opensbi-riscv32-generic-fw_dynamic.bin | Bin 62144 -> 78680 bytes
pc-bios/opensbi-riscv32-generic-fw_dynamic.elf | Bin 558668 -> 727464 bytes
pc-bios/opensbi-riscv64-generic-fw_dynamic.bin | Bin 70792 -> 75096 bytes
pc-bios/opensbi-riscv64-generic-fw_dynamic.elf | Bin 620424 -> 781264 bytes
roms/opensbi                                   |   2 +-
target/riscv/meson.build                       |   1 +
29 files changed, 1286 insertions(+), 65 deletions(-)
create mode 100644 docs/system/riscv/sifive_u.rst
create mode 100644 docs/system/target-riscv.rst
create mode 100644 include/hw/ssi/sifive_spi.h
create mode 100644 hw/ssi/sifive_spi.c
create mode 100644 target/riscv/arch_dump.c
[PULL v2 00/19] riscv-to-apply queue
Posted by Alistair Francis 3 years, 2 months ago 
The following changes since commit cb90ecf9349198558569f6c86c4c27d215406095:

  Merge remote-tracking branch 'remotes/dgilbert-gitlab/tags/pull-virtiofs-20210304' into staging (2021-03-04 10:42:46 +0000)

are available in the Git repository at:

  git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20210304

for you to fetch changes up to 19800265d407f09f333cf80dba3e975eb7bc1872:

  hw/riscv: virt: Map high mmio for PCIe (2021-03-04 09:43:29 -0500)

----------------------------------------------------------------
RISC-V PR for 6.0

This PR is a collection of RISC-V patches:
 - Improvements to SiFive U OTP
 - Upgrade OpenSBI to v0.9
 - Support the QMP dump-guest-memory
 - Add support for the SiFive SPI controller (sifive_u)
 - Initial RISC-V system documentation
 - A fix for the Goldfish RTC
 - MAINTAINERS updates
 - Support for high PCIe memory in the virt machine

----------------------------------------------------------------
Alistair Francis (1):
      MAINTAINERS: Add a SiFive machine section

Bin Meng (16):
      target/riscv: Declare csr_ops[] with a known size
      hw/misc: sifive_u_otp: Use error_report() when block operation fails
      roms/opensbi: Upgrade from v0.8 to v0.9
      hw/block: m25p80: Add ISSI SPI flash support
      hw/block: m25p80: Add various ISSI flash information
      hw/ssi: Add SiFive SPI controller support
      hw/riscv: sifive_u: Add QSPI0 controller and connect a flash
      hw/riscv: sifive_u: Add QSPI2 controller and connect an SD card
      hw/riscv: sifive_u: Change SIFIVE_U_GEM_IRQ to decimal value
      docs/system: Sort targets in alphabetical order
      docs/system: Add RISC-V documentation
      docs/system: riscv: Add documentation for sifive_u machine
      hw/riscv: Drop 'struct MemmapEntry'
      hw/riscv: virt: Drop the 'link_up' parameter of gpex_pcie_init()
      hw/riscv: virt: Limit RAM size in a 32-bit system
      hw/riscv: virt: Map high mmio for PCIe

Laurent Vivier (1):
      goldfish_rtc: re-arm the alarm after migration

Yifei Jiang (1):
      target-riscv: support QMP dump-guest-memory

 docs/system/riscv/sifive_u.rst                 | 336 +++++++++++++++++++++++
 docs/system/target-riscv.rst                   |  72 +++++
 docs/system/targets.rst                        |  20 +-
 include/hw/riscv/sifive_u.h                    |   9 +-
 include/hw/ssi/sifive_spi.h                    |  47 ++++
 target/riscv/cpu.h                             |   6 +-
 target/riscv/cpu_bits.h                        |   1 +
 hw/block/m25p80.c                              |  57 +++-
 hw/misc/sifive_u_otp.c                         |  13 +-
 hw/riscv/microchip_pfsoc.c                     |   9 +-
 hw/riscv/opentitan.c                           |   9 +-
 hw/riscv/sifive_e.c                            |   9 +-
 hw/riscv/sifive_u.c                            | 102 ++++++-
 hw/riscv/spike.c                               |   9 +-
 hw/riscv/virt.c                                |  68 +++--
 hw/rtc/goldfish_rtc.c                          |   2 +
 hw/ssi/sifive_spi.c                            | 358 +++++++++++++++++++++++++
 target/riscv/arch_dump.c                       | 202 ++++++++++++++
 target/riscv/cpu.c                             |   2 +
 MAINTAINERS                                    |   9 +
 hw/riscv/Kconfig                               |   3 +
 hw/ssi/Kconfig                                 |   4 +
 hw/ssi/meson.build                             |   1 +
 pc-bios/opensbi-riscv32-generic-fw_dynamic.bin | Bin 62144 -> 78680 bytes
 pc-bios/opensbi-riscv32-generic-fw_dynamic.elf | Bin 558668 -> 727464 bytes
 pc-bios/opensbi-riscv64-generic-fw_dynamic.bin | Bin 70792 -> 75096 bytes
 pc-bios/opensbi-riscv64-generic-fw_dynamic.elf | Bin 620424 -> 781264 bytes
 roms/opensbi                                   |   2 +-
 target/riscv/meson.build                       |   1 +
 29 files changed, 1286 insertions(+), 65 deletions(-)
 create mode 100644 docs/system/riscv/sifive_u.rst
 create mode 100644 docs/system/target-riscv.rst
 create mode 100644 include/hw/ssi/sifive_spi.h
 create mode 100644 hw/ssi/sifive_spi.c
 create mode 100644 target/riscv/arch_dump.c
Re: [PULL v2 00/19] riscv-to-apply queue
Posted by Peter Maydell 3 years, 1 month ago 
On Thu, 4 Mar 2021 at 14:47, Alistair Francis <alistair.francis@wdc.com> wrote:
>
> The following changes since commit cb90ecf9349198558569f6c86c4c27d215406095:
>
>   Merge remote-tracking branch 'remotes/dgilbert-gitlab/tags/pull-virtiofs-20210304' into staging (2021-03-04 10:42:46 +0000)
>
> are available in the Git repository at:
>
>   git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20210304
>
> for you to fetch changes up to 19800265d407f09f333cf80dba3e975eb7bc1872:
>
>   hw/riscv: virt: Map high mmio for PCIe (2021-03-04 09:43:29 -0500)
>
> ----------------------------------------------------------------
> RISC-V PR for 6.0
>
> This PR is a collection of RISC-V patches:
>  - Improvements to SiFive U OTP
>  - Upgrade OpenSBI to v0.9
>  - Support the QMP dump-guest-memory
>  - Add support for the SiFive SPI controller (sifive_u)
>  - Initial RISC-V system documentation
>  - A fix for the Goldfish RTC
>  - MAINTAINERS updates
>  - Support for high PCIe memory in the virt machine


Applied, thanks.

Please update the changelog at https://wiki.qemu.org/ChangeLog/6.0
for any user-visible changes.

-- PMM

Patchew 2.1-devel-0870f84

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