[PATCH 00/27] tcg patch queue
[PULL 00/72] tcg patch queue
1
Pulling together some cleanups, fixes, and prepatory tci stuff.
1
The following changes since commit aa3a285b5bc56a4208b3b57d4a55291e9c260107:
2
Most of this has been reviewed, but not all.
3
2
4
Those lacking review:
3
Merge tag 'mem-2024-12-21' of https://github.com/davidhildenbrand/qemu into staging (2024-12-22 14:33:27 -0500)
5
4
6
01-tcg-aarch64-Fix-constant-subtraction-in-tcg_out_adds.patch
5
are available in the Git repository at:
7
02-tcg-aarch64-Fix-I3617_CMLE0.patch
8
03-tcg-aarch64-Fix-generation-of-scalar-vector-operatio.patch
9
04-tcg-tci-Use-exec-cpu_ldst.h-interfaces.patch
10
06-tcg-Manage-splitwx-in-tc_ptr_to_region_tree-by-hand.patch
11
23-accel-tcg-rename-tb_lookup__cpu_state-and-hoist-stat.patch
12
24-accel-tcg-move-CF_CLUSTER-calculation-to-curr_cflags.patch
13
25-accel-tcg-drop-the-use-of-CF_HASH_MASK-and-rename-pa.patch
14
26-include-exec-lightly-re-arrange-TranslationBlock.patch
15
27-accel-tcg-Precompute-curr_cflags-into-cpu-tcg_cflags.patch
16
6
17
Alex, the last patch is a re-write and extension of one that
7
https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20241224
18
you did review.
19
8
9
for you to fetch changes up to e4a8e093dc74be049f4829831dce76e5edab0003:
20
10
21
r~
11
accel/tcg: Move gen_intermediate_code to TCGCPUOps.translate_core (2024-12-24 08:32:15 -0800)
22
12
13
----------------------------------------------------------------
14
tcg/optimize: Remove in-flight mask data from OptContext
15
fpu: Add float*_muladd_scalbn
16
fpu: Remove float_muladd_halve_result
17
fpu: Add float_round_nearest_even_max
18
fpu: Add float_muladd_suppress_add_product_zero
19
target/hexagon: Use float32_muladd
20
accel/tcg: Move gen_intermediate_code to TCGCPUOps.translate_core
23
21
24
Alex Bennée (4):
22
----------------------------------------------------------------
25
accel/tcg: rename tb_lookup__cpu_state and hoist state extraction
23
Ilya Leoshkevich (1):
26
accel/tcg: move CF_CLUSTER calculation to curr_cflags
24
tests/tcg: Do not use inttypes.h in multiarch/system/memory.c
27
accel/tcg: drop the use of CF_HASH_MASK and rename params
28
include/exec: lightly re-arrange TranslationBlock
29
25
30
Richard Henderson (23):
26
Pierrick Bouvier (1):
31
tcg/aarch64: Fix constant subtraction in tcg_out_addsub2
27
plugins: optimize cpu_index code generation
32
tcg/aarch64: Fix I3617_CMLE0
33
tcg/aarch64: Fix generation of "scalar" vector operations
34
tcg/tci: Use exec/cpu_ldst.h interfaces
35
tcg: Split out tcg_raise_tb_overflow
36
tcg: Manage splitwx in tc_ptr_to_region_tree by hand
37
tcg/tci: Merge identical cases in generation (arithmetic opcodes)
38
tcg/tci: Merge identical cases in generation (exchange opcodes)
39
tcg/tci: Merge identical cases in generation (deposit opcode)
40
tcg/tci: Merge identical cases in generation (conditional opcodes)
41
tcg/tci: Merge identical cases in generation (load/store opcodes)
42
tcg/tci: Remove tci_read_r8
43
tcg/tci: Remove tci_read_r8s
44
tcg/tci: Remove tci_read_r16
45
tcg/tci: Remove tci_read_r16s
46
tcg/tci: Remove tci_read_r32
47
tcg/tci: Remove tci_read_r32s
48
tcg/tci: Reduce use of tci_read_r64
49
tcg/tci: Merge basic arithmetic operations
50
tcg/tci: Merge extension operations
51
tcg/tci: Merge bswap operations
52
tcg/tci: Merge mov, not and neg operations
53
accel/tcg: Precompute curr_cflags into cpu->tcg_cflags
54
28
55
accel/tcg/tcg-accel-ops.h | 1 +
29
Richard Henderson (70):
56
include/exec/exec-all.h | 19 +-
30
tcg/optimize: Split out finish_bb, finish_ebb
57
include/exec/tb-lookup.h | 26 +-
31
tcg/optimize: Split out fold_affected_mask
58
include/hw/core/cpu.h | 2 +
32
tcg/optimize: Copy mask writeback to fold_masks
59
accel/tcg/cpu-exec.c | 34 ++-
33
tcg/optimize: Split out fold_masks_zs
60
accel/tcg/tcg-accel-ops-mttcg.c | 3 +-
34
tcg/optimize: Augment s_mask from z_mask in fold_masks_zs
61
accel/tcg/tcg-accel-ops-rr.c | 2 +-
35
tcg/optimize: Change representation of s_mask
62
accel/tcg/tcg-accel-ops.c | 8 +
36
tcg/optimize: Use finish_folding in fold_add, fold_add_vec, fold_addsub2
63
accel/tcg/tcg-runtime.c | 6 +-
37
tcg/optimize: Introduce const value accessors for TempOptInfo
64
accel/tcg/translate-all.c | 18 +-
38
tcg/optimize: Use fold_masks_zs in fold_and
65
linux-user/main.c | 1 +
39
tcg/optimize: Use fold_masks_zs in fold_andc
66
linux-user/sh4/signal.c | 8 +-
40
tcg/optimize: Use fold_masks_zs in fold_bswap
67
linux-user/syscall.c | 18 +-
41
tcg/optimize: Use fold_masks_zs in fold_count_zeros
68
softmmu/physmem.c | 2 +-
42
tcg/optimize: Use fold_masks_z in fold_ctpop
69
tcg/tcg.c | 29 +-
43
tcg/optimize: Use fold_and and fold_masks_z in fold_deposit
70
tcg/tci.c | 526 ++++++++++----------------------
44
tcg/optimize: Compute sign mask in fold_deposit
71
tcg/aarch64/tcg-target.c.inc | 229 +++++++++++---
45
tcg/optimize: Use finish_folding in fold_divide
72
tcg/tci/tcg-target.c.inc | 204 +++++--------
46
tcg/optimize: Use finish_folding in fold_dup, fold_dup2
73
18 files changed, 526 insertions(+), 610 deletions(-)
47
tcg/optimize: Use fold_masks_s in fold_eqv
48
tcg/optimize: Use fold_masks_z in fold_extract
49
tcg/optimize: Use finish_folding in fold_extract2
50
tcg/optimize: Use fold_masks_zs in fold_exts
51
tcg/optimize: Use fold_masks_z in fold_extu
52
tcg/optimize: Use fold_masks_zs in fold_movcond
53
tcg/optimize: Use finish_folding in fold_mul*
54
tcg/optimize: Use fold_masks_s in fold_nand
55
tcg/optimize: Use fold_masks_z in fold_neg_no_const
56
tcg/optimize: Use fold_masks_s in fold_nor
57
tcg/optimize: Use fold_masks_s in fold_not
58
tcg/optimize: Use fold_masks_zs in fold_or
59
tcg/optimize: Use fold_masks_zs in fold_orc
60
tcg/optimize: Use fold_masks_zs in fold_qemu_ld
61
tcg/optimize: Return true from fold_qemu_st, fold_tcg_st
62
tcg/optimize: Use finish_folding in fold_remainder
63
tcg/optimize: Distinguish simplification in fold_setcond_zmask
64
tcg/optimize: Use fold_masks_z in fold_setcond
65
tcg/optimize: Use fold_masks_s in fold_negsetcond
66
tcg/optimize: Use fold_masks_z in fold_setcond2
67
tcg/optimize: Use finish_folding in fold_cmp_vec
68
tcg/optimize: Use finish_folding in fold_cmpsel_vec
69
tcg/optimize: Use fold_masks_zs in fold_sextract
70
tcg/optimize: Use fold_masks_zs, fold_masks_s in fold_shift
71
tcg/optimize: Simplify sign bit test in fold_shift
72
tcg/optimize: Use finish_folding in fold_sub, fold_sub_vec
73
tcg/optimize: Use fold_masks_zs in fold_tcg_ld
74
tcg/optimize: Use finish_folding in fold_tcg_ld_memcopy
75
tcg/optimize: Use fold_masks_zs in fold_xor
76
tcg/optimize: Use finish_folding in fold_bitsel_vec
77
tcg/optimize: Use finish_folding as default in tcg_optimize
78
tcg/optimize: Remove z_mask, s_mask from OptContext
79
tcg/optimize: Re-enable sign-mask optimizations
80
tcg/optimize: Move fold_bitsel_vec into alphabetic sort
81
tcg/optimize: Move fold_cmp_vec, fold_cmpsel_vec into alphabetic sort
82
softfloat: Add float{16,32,64}_muladd_scalbn
83
target/arm: Use float*_muladd_scalbn
84
target/sparc: Use float*_muladd_scalbn
85
softfloat: Remove float_muladd_halve_result
86
softfloat: Add float_round_nearest_even_max
87
softfloat: Add float_muladd_suppress_add_product_zero
88
target/hexagon: Use float32_mul in helper_sfmpy
89
target/hexagon: Use float32_muladd for helper_sffma
90
target/hexagon: Use float32_muladd for helper_sffms
91
target/hexagon: Use float32_muladd_scalbn for helper_sffma_sc
92
target/hexagon: Use float32_muladd for helper_sffm[as]_lib
93
target/hexagon: Remove internal_fmafx
94
target/hexagon: Expand GEN_XF_ROUND
95
target/hexagon: Remove Float
96
target/hexagon: Remove Double
97
target/hexagon: Use mulu64 for int128_mul_6464
98
target/hexagon: Simplify internal_mpyhh setup
99
accel/tcg: Move gen_intermediate_code to TCGCPUOps.translate_core
74
100
75
--
101
include/exec/translator.h | 14 -
76
2.25.1
102
include/fpu/softfloat-types.h | 2 +
77
103
include/fpu/softfloat.h | 14 +-
78
104
include/hw/core/tcg-cpu-ops.h | 13 +
105
target/alpha/cpu.h | 2 +
106
target/arm/internals.h | 2 +
107
target/avr/cpu.h | 2 +
108
target/hexagon/cpu.h | 2 +
109
target/hexagon/fma_emu.h | 3 -
110
target/hppa/cpu.h | 2 +
111
target/i386/tcg/helper-tcg.h | 2 +
112
target/loongarch/internals.h | 2 +
113
target/m68k/cpu.h | 2 +
114
target/microblaze/cpu.h | 2 +
115
target/mips/tcg/tcg-internal.h | 2 +
116
target/openrisc/cpu.h | 2 +
117
target/ppc/cpu.h | 2 +
118
target/riscv/cpu.h | 3 +
119
target/rx/cpu.h | 2 +
120
target/s390x/s390x-internal.h | 2 +
121
target/sh4/cpu.h | 2 +
122
target/sparc/cpu.h | 2 +
123
target/sparc/helper.h | 4 +-
124
target/tricore/cpu.h | 2 +
125
target/xtensa/cpu.h | 2 +
126
accel/tcg/cpu-exec.c | 8 +-
127
accel/tcg/plugin-gen.c | 9 +
128
accel/tcg/translate-all.c | 8 +-
129
fpu/softfloat.c | 63 +--
130
target/alpha/cpu.c | 1 +
131
target/alpha/translate.c | 4 +-
132
target/arm/cpu.c | 1 +
133
target/arm/tcg/cpu-v7m.c | 1 +
134
target/arm/tcg/helper-a64.c | 6 +-
135
target/arm/tcg/translate.c | 5 +-
136
target/avr/cpu.c | 1 +
137
target/avr/translate.c | 6 +-
138
target/hexagon/cpu.c | 1 +
139
target/hexagon/fma_emu.c | 496 ++++++---------------
140
target/hexagon/op_helper.c | 125 ++----
141
target/hexagon/translate.c | 4 +-
142
target/hppa/cpu.c | 1 +
143
target/hppa/translate.c | 4 +-
144
target/i386/tcg/tcg-cpu.c | 1 +
145
target/i386/tcg/translate.c | 5 +-
146
target/loongarch/cpu.c | 1 +
147
target/loongarch/tcg/translate.c | 4 +-
148
target/m68k/cpu.c | 1 +
149
target/m68k/translate.c | 4 +-
150
target/microblaze/cpu.c | 1 +
151
target/microblaze/translate.c | 4 +-
152
target/mips/cpu.c | 1 +
153
target/mips/tcg/translate.c | 4 +-
154
target/openrisc/cpu.c | 1 +
155
target/openrisc/translate.c | 4 +-
156
target/ppc/cpu_init.c | 1 +
157
target/ppc/translate.c | 4 +-
158
target/riscv/tcg/tcg-cpu.c | 1 +
159
target/riscv/translate.c | 4 +-
160
target/rx/cpu.c | 1 +
161
target/rx/translate.c | 4 +-
162
target/s390x/cpu.c | 1 +
163
target/s390x/tcg/translate.c | 4 +-
164
target/sh4/cpu.c | 1 +
165
target/sh4/translate.c | 4 +-
166
target/sparc/cpu.c | 1 +
167
target/sparc/fop_helper.c | 8 +-
168
target/sparc/translate.c | 84 ++--
169
target/tricore/cpu.c | 1 +
170
target/tricore/translate.c | 5 +-
171
target/xtensa/cpu.c | 1 +
172
target/xtensa/translate.c | 4 +-
173
tcg/optimize.c | 857 +++++++++++++++++++-----------------
174
tests/tcg/multiarch/system/memory.c | 9 +-
175
fpu/softfloat-parts.c.inc | 16 +-
176
75 files changed, 866 insertions(+), 1009 deletions(-)
diff view generated by jsdifflib
New patch
[PULL 01/72] tests/tcg: Do not use inttypes.h in multiarch/system/memory.c
1
From: Ilya Leoshkevich <iii@linux.ibm.com>
1
2
3
make check-tcg fails on Fedora with the following error message:
4
5
alpha-linux-gnu-gcc [...] qemu/tests/tcg/multiarch/system/memory.c -o memory [...]
6
qemu/tests/tcg/multiarch/system/memory.c:17:10: fatal error: inttypes.h: No such file or directory
7
17 | #include <inttypes.h>
8
| ^~~~~~~~~~~~
9
compilation terminated.
10
11
The reason is that Fedora has cross-compilers, but no cross-glibc
12
headers. Fix by hardcoding the format specifiers and dropping the
13
include.
14
15
An alternative fix would be to introduce a configure check for
16
inttypes.h. But this would make it impossible to use Fedora
17
cross-compilers for softmmu tests, which used to work so far.
18
19
Fixes: ecbcc9ead2f8 ("tests/tcg: add a system test to check memory instrumentation")
20
Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com>
21
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
22
Message-ID: <20241010085906.226249-1-iii@linux.ibm.com>
23
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
24
---
25
tests/tcg/multiarch/system/memory.c | 9 ++++-----
26
1 file changed, 4 insertions(+), 5 deletions(-)
27
28
diff --git a/tests/tcg/multiarch/system/memory.c b/tests/tcg/multiarch/system/memory.c
29
index XXXXXXX..XXXXXXX 100644
30
--- a/tests/tcg/multiarch/system/memory.c
31
+++ b/tests/tcg/multiarch/system/memory.c
32
@@ -XXX,XX +XXX,XX @@
33
34
#include <stdint.h>
35
#include <stdbool.h>
36
-#include <inttypes.h>
37
#include <minilib.h>
38
39
#ifndef CHECK_UNALIGNED
40
@@ -XXX,XX +XXX,XX @@ int main(void)
41
int i;
42
bool ok = true;
43
44
- ml_printf("Test data start: 0x%"PRIxPTR"\n", &test_data[0]);
45
- ml_printf("Test data end: 0x%"PRIxPTR"\n", &test_data[TEST_SIZE]);
46
+ ml_printf("Test data start: 0x%lx\n", (unsigned long)&test_data[0]);
47
+ ml_printf("Test data end: 0x%lx\n", (unsigned long)&test_data[TEST_SIZE]);
48
49
/* Run through the unsigned tests first */
50
for (i = 0; i < ARRAY_SIZE(init_ufns) && ok; i++) {
51
@@ -XXX,XX +XXX,XX @@ int main(void)
52
ok = do_signed_reads(true);
53
}
54
55
- ml_printf("Test data read: %"PRId32"\n", test_read_count);
56
- ml_printf("Test data write: %"PRId32"\n", test_write_count);
57
+ ml_printf("Test data read: %lu\n", (unsigned long)test_read_count);
58
+ ml_printf("Test data write: %lu\n", (unsigned long)test_write_count);
59
ml_printf("Test complete: %s\n", ok ? "PASSED" : "FAILED");
60
return ok ? 0 : -1;
61
}
62
--
63
2.43.0
diff view generated by jsdifflib
New patch
[PULL 02/72] plugins: optimize cpu_index code generation
1
From: Pierrick Bouvier <pierrick.bouvier@linaro.org>
1
2
3
When running with a single vcpu, we can return a constant instead of a
4
load when accessing cpu_index.
5
A side effect is that all tcg operations using it are optimized, most
6
notably scoreboard access.
7
When running a simple loop in user-mode, the speedup is around 20%.
8
9
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
10
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
11
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12
Message-ID: <20241128213843.1023080-1-pierrick.bouvier@linaro.org>
13
---
14
accel/tcg/plugin-gen.c | 9 +++++++++
15
1 file changed, 9 insertions(+)
16
17
diff --git a/accel/tcg/plugin-gen.c b/accel/tcg/plugin-gen.c
18
index XXXXXXX..XXXXXXX 100644
19
--- a/accel/tcg/plugin-gen.c
20
+++ b/accel/tcg/plugin-gen.c
21
@@ -XXX,XX +XXX,XX @@ static void gen_disable_mem_helper(void)
22
23
static TCGv_i32 gen_cpu_index(void)
24
{
25
+ /*
26
+ * Optimize when we run with a single vcpu. All values using cpu_index,
27
+ * including scoreboard index, will be optimized out.
28
+ * User-mode calls tb_flush when setting this flag. In system-mode, all
29
+ * vcpus are created before generating code.
30
+ */
31
+ if (!tcg_cflags_has(current_cpu, CF_PARALLEL)) {
32
+ return tcg_constant_i32(current_cpu->cpu_index);
33
+ }
34
TCGv_i32 cpu_index = tcg_temp_ebb_new_i32();
35
tcg_gen_ld_i32(cpu_index, tcg_env,
36
-offsetof(ArchCPU, env) + offsetof(CPUState, cpu_index));
37
--
38
2.43.0
diff view generated by jsdifflib
New patch
[PULL 03/72] tcg/optimize: Split out finish_bb, finish_ebb
1
Call them directly from the opcode switch statement in tcg_optimize,
2
rather than in finish_folding based on opcode flags. Adjust folding
3
of conditional branches to match.
1
4
5
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
---
8
tcg/optimize.c | 47 +++++++++++++++++++++++++++++++----------------
9
1 file changed, 31 insertions(+), 16 deletions(-)
10
11
diff --git a/tcg/optimize.c b/tcg/optimize.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/tcg/optimize.c
14
+++ b/tcg/optimize.c
15
@@ -XXX,XX +XXX,XX @@ static void copy_propagate(OptContext *ctx, TCGOp *op,
16
}
17
}
18
19
+static void finish_bb(OptContext *ctx)
20
+{
21
+ /* We only optimize memory barriers across basic blocks. */
22
+ ctx->prev_mb = NULL;
23
+}
24
+
25
+static void finish_ebb(OptContext *ctx)
26
+{
27
+ finish_bb(ctx);
28
+ /* We only optimize across extended basic blocks. */
29
+ memset(&ctx->temps_used, 0, sizeof(ctx->temps_used));
30
+ remove_mem_copy_all(ctx);
31
+}
32
+
33
static void finish_folding(OptContext *ctx, TCGOp *op)
34
{
35
const TCGOpDef *def = &tcg_op_defs[op->opc];
36
int i, nb_oargs;
37
38
- /*
39
- * We only optimize extended basic blocks. If the opcode ends a BB
40
- * and is not a conditional branch, reset all temp data.
41
- */
42
- if (def->flags & TCG_OPF_BB_END) {
43
- ctx->prev_mb = NULL;
44
- if (!(def->flags & TCG_OPF_COND_BRANCH)) {
45
- memset(&ctx->temps_used, 0, sizeof(ctx->temps_used));
46
- remove_mem_copy_all(ctx);
47
- }
48
- return;
49
- }
50
-
51
nb_oargs = def->nb_oargs;
52
for (i = 0; i < nb_oargs; i++) {
53
TCGTemp *ts = arg_temp(op->args[i]);
54
@@ -XXX,XX +XXX,XX @@ static bool fold_brcond(OptContext *ctx, TCGOp *op)
55
if (i > 0) {
56
op->opc = INDEX_op_br;
57
op->args[0] = op->args[3];
58
+ finish_ebb(ctx);
59
+ } else {
60
+ finish_bb(ctx);
61
}
62
- return false;
63
+ return true;
64
}
65
66
static bool fold_brcond2(OptContext *ctx, TCGOp *op)
67
@@ -XXX,XX +XXX,XX @@ static bool fold_brcond2(OptContext *ctx, TCGOp *op)
68
}
69
op->opc = INDEX_op_br;
70
op->args[0] = label;
71
- break;
72
+ finish_ebb(ctx);
73
+ return true;
74
}
75
- return false;
76
+
77
+ finish_bb(ctx);
78
+ return true;
79
}
80
81
static bool fold_bswap(OptContext *ctx, TCGOp *op)
82
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
83
CASE_OP_32_64_VEC(xor):
84
done = fold_xor(&ctx, op);
85
break;
86
+ case INDEX_op_set_label:
87
+ case INDEX_op_br:
88
+ case INDEX_op_exit_tb:
89
+ case INDEX_op_goto_tb:
90
+ case INDEX_op_goto_ptr:
91
+ finish_ebb(&ctx);
92
+ done = true;
93
+ break;
94
default:
95
break;
96
}
97
--
98
2.43.0
diff view generated by jsdifflib
New patch
[PULL 04/72] tcg/optimize: Split out fold_affected_mask
1
There are only a few logical operations which can compute
2
an "affected" mask. Split out handling of this optimization
3
to a separate function, only to be called when applicable.
1
4
5
Remove the a_mask field from OptContext, as the mask is
6
no longer stored anywhere.
7
8
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
---
11
tcg/optimize.c | 42 +++++++++++++++++++++++++++---------------
12
1 file changed, 27 insertions(+), 15 deletions(-)
13
14
diff --git a/tcg/optimize.c b/tcg/optimize.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/tcg/optimize.c
17
+++ b/tcg/optimize.c
18
@@ -XXX,XX +XXX,XX @@ typedef struct OptContext {
19
QSIMPLEQ_HEAD(, MemCopyInfo) mem_free;
20
21
/* In flight values from optimization. */
22
- uint64_t a_mask; /* mask bit is 0 iff value identical to first input */
23
uint64_t z_mask; /* mask bit is 0 iff value bit is 0 */
24
uint64_t s_mask; /* mask of clrsb(value) bits */
25
TCGType type;
26
@@ -XXX,XX +XXX,XX @@ static bool fold_const2_commutative(OptContext *ctx, TCGOp *op)
27
28
static bool fold_masks(OptContext *ctx, TCGOp *op)
29
{
30
- uint64_t a_mask = ctx->a_mask;
31
uint64_t z_mask = ctx->z_mask;
32
uint64_t s_mask = ctx->s_mask;
33
34
@@ -XXX,XX +XXX,XX @@ static bool fold_masks(OptContext *ctx, TCGOp *op)
35
* type changing opcodes.
36
*/
37
if (ctx->type == TCG_TYPE_I32) {
38
- a_mask = (int32_t)a_mask;
39
z_mask = (int32_t)z_mask;
40
s_mask |= MAKE_64BIT_MASK(32, 32);
41
ctx->z_mask = z_mask;
42
@@ -XXX,XX +XXX,XX @@ static bool fold_masks(OptContext *ctx, TCGOp *op)
43
if (z_mask == 0) {
44
return tcg_opt_gen_movi(ctx, op, op->args[0], 0);
45
}
46
+ return false;
47
+}
48
+
49
+/*
50
+ * An "affected" mask bit is 0 if and only if the result is identical
51
+ * to the first input. Thus if the entire mask is 0, the operation
52
+ * is equivalent to a copy.
53
+ */
54
+static bool fold_affected_mask(OptContext *ctx, TCGOp *op, uint64_t a_mask)
55
+{
56
+ if (ctx->type == TCG_TYPE_I32) {
57
+ a_mask = (uint32_t)a_mask;
58
+ }
59
if (a_mask == 0) {
60
return tcg_opt_gen_mov(ctx, op, op->args[0], op->args[1]);
61
}
62
@@ -XXX,XX +XXX,XX @@ static bool fold_and(OptContext *ctx, TCGOp *op)
63
* Known-zeros does not imply known-ones. Therefore unless
64
* arg2 is constant, we can't infer affected bits from it.
65
*/
66
- if (arg_is_const(op->args[2])) {
67
- ctx->a_mask = z1 & ~z2;
68
+ if (arg_is_const(op->args[2]) &&
69
+ fold_affected_mask(ctx, op, z1 & ~z2)) {
70
+ return true;
71
}
72
73
return fold_masks(ctx, op);
74
@@ -XXX,XX +XXX,XX @@ static bool fold_andc(OptContext *ctx, TCGOp *op)
75
*/
76
if (arg_is_const(op->args[2])) {
77
uint64_t z2 = ~arg_info(op->args[2])->z_mask;
78
- ctx->a_mask = z1 & ~z2;
79
+ if (fold_affected_mask(ctx, op, z1 & ~z2)) {
80
+ return true;
81
+ }
82
z1 &= z2;
83
}
84
ctx->z_mask = z1;
85
@@ -XXX,XX +XXX,XX @@ static bool fold_extract(OptContext *ctx, TCGOp *op)
86
87
z_mask_old = arg_info(op->args[1])->z_mask;
88
z_mask = extract64(z_mask_old, pos, len);
89
- if (pos == 0) {
90
- ctx->a_mask = z_mask_old ^ z_mask;
91
+ if (pos == 0 && fold_affected_mask(ctx, op, z_mask_old ^ z_mask)) {
92
+ return true;
93
}
94
ctx->z_mask = z_mask;
95
ctx->s_mask = smask_from_zmask(z_mask);
96
@@ -XXX,XX +XXX,XX @@ static bool fold_exts(OptContext *ctx, TCGOp *op)
97
98
ctx->z_mask = z_mask;
99
ctx->s_mask = s_mask;
100
- if (!type_change) {
101
- ctx->a_mask = s_mask & ~s_mask_old;
102
+ if (!type_change && fold_affected_mask(ctx, op, s_mask & ~s_mask_old)) {
103
+ return true;
104
}
105
106
return fold_masks(ctx, op);
107
@@ -XXX,XX +XXX,XX @@ static bool fold_extu(OptContext *ctx, TCGOp *op)
108
109
ctx->z_mask = z_mask;
110
ctx->s_mask = smask_from_zmask(z_mask);
111
- if (!type_change) {
112
- ctx->a_mask = z_mask_old ^ z_mask;
113
+ if (!type_change && fold_affected_mask(ctx, op, z_mask_old ^ z_mask)) {
114
+ return true;
115
}
116
return fold_masks(ctx, op);
117
}
118
@@ -XXX,XX +XXX,XX @@ static bool fold_sextract(OptContext *ctx, TCGOp *op)
119
s_mask |= MAKE_64BIT_MASK(len, 64 - len);
120
ctx->s_mask = s_mask;
121
122
- if (pos == 0) {
123
- ctx->a_mask = s_mask & ~s_mask_old;
124
+ if (pos == 0 && fold_affected_mask(ctx, op, s_mask & ~s_mask_old)) {
125
+ return true;
126
}
127
128
return fold_masks(ctx, op);
129
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
130
}
131
132
/* Assume all bits affected, no bits known zero, no sign reps. */
133
- ctx.a_mask = -1;
134
ctx.z_mask = -1;
135
ctx.s_mask = 0;
136
137
--
138
2.43.0
diff view generated by jsdifflib
New patch
[PULL 05/72] tcg/optimize: Copy mask writeback to fold_masks
1
Use of fold_masks should be restricted to those opcodes that
2
can reliably make use of it -- those with a single output,
3
and from higher-level folders that set up the masks.
4
Prepare for conversion of each folder in turn.
1
5
6
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
---
9
tcg/optimize.c | 17 ++++++++++++++---
10
1 file changed, 14 insertions(+), 3 deletions(-)
11
12
diff --git a/tcg/optimize.c b/tcg/optimize.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/tcg/optimize.c
15
+++ b/tcg/optimize.c
16
@@ -XXX,XX +XXX,XX @@ static bool fold_masks(OptContext *ctx, TCGOp *op)
17
{
18
uint64_t z_mask = ctx->z_mask;
19
uint64_t s_mask = ctx->s_mask;
20
+ const TCGOpDef *def = &tcg_op_defs[op->opc];
21
+ TCGTemp *ts;
22
+ TempOptInfo *ti;
23
+
24
+ /* Only single-output opcodes are supported here. */
25
+ tcg_debug_assert(def->nb_oargs == 1);
26
27
/*
28
* 32-bit ops generate 32-bit results, which for the purpose of
29
@@ -XXX,XX +XXX,XX @@ static bool fold_masks(OptContext *ctx, TCGOp *op)
30
if (ctx->type == TCG_TYPE_I32) {
31
z_mask = (int32_t)z_mask;
32
s_mask |= MAKE_64BIT_MASK(32, 32);
33
- ctx->z_mask = z_mask;
34
- ctx->s_mask = s_mask;
35
}
36
37
if (z_mask == 0) {
38
return tcg_opt_gen_movi(ctx, op, op->args[0], 0);
39
}
40
- return false;
41
+
42
+ ts = arg_temp(op->args[0]);
43
+ reset_ts(ctx, ts);
44
+
45
+ ti = ts_info(ts);
46
+ ti->z_mask = z_mask;
47
+ ti->s_mask = s_mask;
48
+ return true;
49
}
50
51
/*
52
--
53
2.43.0
diff view generated by jsdifflib
New patch
[PULL 06/72] tcg/optimize: Split out fold_masks_zs
1
Add a routine to which masks can be passed directly, rather than
2
storing them into OptContext. To be used in upcoming patches.
1
3
4
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
---
7
tcg/optimize.c | 15 ++++++++++++---
8
1 file changed, 12 insertions(+), 3 deletions(-)
9
10
diff --git a/tcg/optimize.c b/tcg/optimize.c
11
index XXXXXXX..XXXXXXX 100644
12
--- a/tcg/optimize.c
13
+++ b/tcg/optimize.c
14
@@ -XXX,XX +XXX,XX @@ static bool fold_const2_commutative(OptContext *ctx, TCGOp *op)
15
return fold_const2(ctx, op);
16
}
17
18
-static bool fold_masks(OptContext *ctx, TCGOp *op)
19
+/*
20
+ * Record "zero" and "sign" masks for the single output of @op.
21
+ * See TempOptInfo definition of z_mask and s_mask.
22
+ * If z_mask allows, fold the output to constant zero.
23
+ */
24
+static bool fold_masks_zs(OptContext *ctx, TCGOp *op,
25
+ uint64_t z_mask, uint64_t s_mask)
26
{
27
- uint64_t z_mask = ctx->z_mask;
28
- uint64_t s_mask = ctx->s_mask;
29
const TCGOpDef *def = &tcg_op_defs[op->opc];
30
TCGTemp *ts;
31
TempOptInfo *ti;
32
@@ -XXX,XX +XXX,XX @@ static bool fold_masks(OptContext *ctx, TCGOp *op)
33
return true;
34
}
35
36
+static bool fold_masks(OptContext *ctx, TCGOp *op)
37
+{
38
+ return fold_masks_zs(ctx, op, ctx->z_mask, ctx->s_mask);
39
+}
40
+
41
/*
42
* An "affected" mask bit is 0 if and only if the result is identical
43
* to the first input. Thus if the entire mask is 0, the operation
44
--
45
2.43.0
diff view generated by jsdifflib
New patch
[PULL 07/72] tcg/optimize: Augment s_mask from z_mask in fold_masks_zs
1
Consider the passed s_mask to be a minimum deduced from
2
either existing s_mask or from a sign-extension operation.
3
We may be able to deduce more from the set of known zeros.
4
Remove identical logic from several opcode folders.
1
5
6
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
---
9
tcg/optimize.c | 21 ++++++---------------
10
1 file changed, 6 insertions(+), 15 deletions(-)
11
12
diff --git a/tcg/optimize.c b/tcg/optimize.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/tcg/optimize.c
15
+++ b/tcg/optimize.c
16
@@ -XXX,XX +XXX,XX @@ static bool fold_const2_commutative(OptContext *ctx, TCGOp *op)
17
* Record "zero" and "sign" masks for the single output of @op.
18
* See TempOptInfo definition of z_mask and s_mask.
19
* If z_mask allows, fold the output to constant zero.
20
+ * The passed s_mask may be augmented by z_mask.
21
*/
22
static bool fold_masks_zs(OptContext *ctx, TCGOp *op,
23
uint64_t z_mask, uint64_t s_mask)
24
@@ -XXX,XX +XXX,XX @@ static bool fold_masks_zs(OptContext *ctx, TCGOp *op,
25
26
ti = ts_info(ts);
27
ti->z_mask = z_mask;
28
- ti->s_mask = s_mask;
29
+ ti->s_mask = s_mask | smask_from_zmask(z_mask);
30
return true;
31
}
32
33
@@ -XXX,XX +XXX,XX @@ static bool fold_bswap(OptContext *ctx, TCGOp *op)
34
default:
35
g_assert_not_reached();
36
}
37
- s_mask = smask_from_zmask(z_mask);
38
39
+ s_mask = 0;
40
switch (op->args[2] & (TCG_BSWAP_OZ | TCG_BSWAP_OS)) {
41
case TCG_BSWAP_OZ:
42
break;
43
@@ -XXX,XX +XXX,XX @@ static bool fold_bswap(OptContext *ctx, TCGOp *op)
44
default:
45
/* The high bits are undefined: force all bits above the sign to 1. */
46
z_mask |= sign << 1;
47
- s_mask = 0;
48
break;
49
}
50
ctx->z_mask = z_mask;
51
@@ -XXX,XX +XXX,XX @@ static bool fold_count_zeros(OptContext *ctx, TCGOp *op)
52
g_assert_not_reached();
53
}
54
ctx->z_mask = arg_info(op->args[2])->z_mask | z_mask;
55
- ctx->s_mask = smask_from_zmask(ctx->z_mask);
56
return false;
57
}
58
59
@@ -XXX,XX +XXX,XX @@ static bool fold_ctpop(OptContext *ctx, TCGOp *op)
60
default:
61
g_assert_not_reached();
62
}
63
- ctx->s_mask = smask_from_zmask(ctx->z_mask);
64
return false;
65
}
66
67
@@ -XXX,XX +XXX,XX @@ static bool fold_extract(OptContext *ctx, TCGOp *op)
68
return true;
69
}
70
ctx->z_mask = z_mask;
71
- ctx->s_mask = smask_from_zmask(z_mask);
72
73
return fold_masks(ctx, op);
74
}
75
@@ -XXX,XX +XXX,XX @@ static bool fold_extu(OptContext *ctx, TCGOp *op)
76
}
77
78
ctx->z_mask = z_mask;
79
- ctx->s_mask = smask_from_zmask(z_mask);
80
if (!type_change && fold_affected_mask(ctx, op, z_mask_old ^ z_mask)) {
81
return true;
82
}
83
@@ -XXX,XX +XXX,XX @@ static bool fold_qemu_ld(OptContext *ctx, TCGOp *op)
84
int width = 8 * memop_size(mop);
85
86
if (width < 64) {
87
- ctx->s_mask = MAKE_64BIT_MASK(width, 64 - width);
88
- if (!(mop & MO_SIGN)) {
89
+ if (mop & MO_SIGN) {
90
+ ctx->s_mask = MAKE_64BIT_MASK(width, 64 - width);
91
+ } else {
92
ctx->z_mask = MAKE_64BIT_MASK(0, width);
93
- ctx->s_mask <<= 1;
94
}
95
}
96
97
@@ -XXX,XX +XXX,XX @@ static bool fold_setcond(OptContext *ctx, TCGOp *op)
98
fold_setcond_tst_pow2(ctx, op, false);
99
100
ctx->z_mask = 1;
101
- ctx->s_mask = smask_from_zmask(1);
102
return false;
103
}
104
105
@@ -XXX,XX +XXX,XX @@ static bool fold_setcond2(OptContext *ctx, TCGOp *op)
106
}
107
108
ctx->z_mask = 1;
109
- ctx->s_mask = smask_from_zmask(1);
110
return false;
111
112
do_setcond_const:
113
@@ -XXX,XX +XXX,XX @@ static bool fold_tcg_ld(OptContext *ctx, TCGOp *op)
114
break;
115
CASE_OP_32_64(ld8u):
116
ctx->z_mask = MAKE_64BIT_MASK(0, 8);
117
- ctx->s_mask = MAKE_64BIT_MASK(9, 55);
118
break;
119
CASE_OP_32_64(ld16s):
120
ctx->s_mask = MAKE_64BIT_MASK(16, 48);
121
break;
122
CASE_OP_32_64(ld16u):
123
ctx->z_mask = MAKE_64BIT_MASK(0, 16);
124
- ctx->s_mask = MAKE_64BIT_MASK(17, 47);
125
break;
126
case INDEX_op_ld32s_i64:
127
ctx->s_mask = MAKE_64BIT_MASK(32, 32);
128
break;
129
case INDEX_op_ld32u_i64:
130
ctx->z_mask = MAKE_64BIT_MASK(0, 32);
131
- ctx->s_mask = MAKE_64BIT_MASK(33, 31);
132
break;
133
default:
134
g_assert_not_reached();
135
--
136
2.43.0
diff view generated by jsdifflib
[PATCH 23/27] accel/tcg: rename tb_lookup__cpu_state and hoist state extraction
[PULL 08/72] tcg/optimize: Change representation of s_mask
1
From: Alex Bennée <alex.bennee@linaro.org>
1
Change the representation from sign bit repetitions to all bits equal
2
to the sign bit, including the sign bit itself.
2
3
3
Having a function return either and valid TB and some system state
4
The previous format has a problem in that it is difficult to recreate
4
seems excessive. It will make the subsequent re-factoring easier if we
5
a valid sign mask after a shift operation: the "repetitions" part of
5
lookup the current state where we are.
6
the previous format meant that applying the same shift as for the value
7
lead to an off-by-one value.
6
8
7
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
9
The new format, including the sign bit itself, means that the sign mask
8
Message-Id: <20210224165811.11567-2-alex.bennee@linaro.org>
10
can be manipulated in exactly the same way as the value, canonicalization
11
is easier.
12
13
Canonicalize the s_mask in fold_masks_zs, rather than requiring callers
14
to do so. Treat 0 as a non-canonical but typeless input for no sign
15
information, which will be reset as appropriate for the data type.
16
We can easily fold in the data from z_mask while canonicalizing.
17
18
Temporarily disable optimizations using s_mask while each operation is
19
converted to use fold_masks_zs and to the new form.
20
21
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
22
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
---
23
---
11
include/exec/tb-lookup.h | 18 ++++++++----------
24
tcg/optimize.c | 64 ++++++++++++--------------------------------------
12
accel/tcg/cpu-exec.c | 10 ++++++++--
25
1 file changed, 15 insertions(+), 49 deletions(-)
13
accel/tcg/tcg-runtime.c | 4 +++-
14
3 files changed, 19 insertions(+), 13 deletions(-)
15
26
16
diff --git a/include/exec/tb-lookup.h b/include/exec/tb-lookup.h
27
diff --git a/tcg/optimize.c b/tcg/optimize.c
17
index XXXXXXX..XXXXXXX 100644
28
index XXXXXXX..XXXXXXX 100644
18
--- a/include/exec/tb-lookup.h
29
--- a/tcg/optimize.c
19
+++ b/include/exec/tb-lookup.h
30
+++ b/tcg/optimize.c
20
@@ -XXX,XX +XXX,XX @@
31
@@ -XXX,XX +XXX,XX @@ typedef struct TempOptInfo {
21
#include "exec/tb-hash.h"
32
QSIMPLEQ_HEAD(, MemCopyInfo) mem_copy;
22
33
uint64_t val;
23
/* Might cause an exception, so have a longjmp destination ready */
34
uint64_t z_mask; /* mask bit is 0 if and only if value bit is 0 */
24
-static inline TranslationBlock *
35
- uint64_t s_mask; /* a left-aligned mask of clrsb(value) bits. */
25
-tb_lookup__cpu_state(CPUState *cpu, target_ulong *pc, target_ulong *cs_base,
36
+ uint64_t s_mask; /* mask bit is 1 if value bit matches msb */
26
- uint32_t *flags, uint32_t cf_mask)
37
} TempOptInfo;
27
+static inline TranslationBlock * tb_lookup(CPUState *cpu,
38
28
+ target_ulong pc, target_ulong cs_base,
39
typedef struct OptContext {
29
+ uint32_t flags, uint32_t cf_mask)
40
@@ -XXX,XX +XXX,XX @@ typedef struct OptContext {
41
42
/* In flight values from optimization. */
43
uint64_t z_mask; /* mask bit is 0 iff value bit is 0 */
44
- uint64_t s_mask; /* mask of clrsb(value) bits */
45
+ uint64_t s_mask; /* mask bit is 1 if value bit matches msb */
46
TCGType type;
47
} OptContext;
48
49
-/* Calculate the smask for a specific value. */
50
-static uint64_t smask_from_value(uint64_t value)
51
-{
52
- int rep = clrsb64(value);
53
- return ~(~0ull >> rep);
54
-}
55
-
56
-/*
57
- * Calculate the smask for a given set of known-zeros.
58
- * If there are lots of zeros on the left, we can consider the remainder
59
- * an unsigned field, and thus the corresponding signed field is one bit
60
- * larger.
61
- */
62
-static uint64_t smask_from_zmask(uint64_t zmask)
63
-{
64
- /*
65
- * Only the 0 bits are significant for zmask, thus the msb itself
66
- * must be zero, else we have no sign information.
67
- */
68
- int rep = clz64(zmask);
69
- if (rep == 0) {
70
- return 0;
71
- }
72
- rep -= 1;
73
- return ~(~0ull >> rep);
74
-}
75
-
76
-/*
77
- * Recreate a properly left-aligned smask after manipulation.
78
- * Some bit-shuffling, particularly shifts and rotates, may
79
- * retain sign bits on the left, but may scatter disconnected
80
- * sign bits on the right. Retain only what remains to the left.
81
- */
82
-static uint64_t smask_from_smask(int64_t smask)
83
-{
84
- /* Only the 1 bits are significant for smask */
85
- return smask_from_zmask(~smask);
86
-}
87
-
88
static inline TempOptInfo *ts_info(TCGTemp *ts)
30
{
89
{
31
- CPUArchState *env = (CPUArchState *)cpu->env_ptr;
90
return ts->state_ptr;
32
TranslationBlock *tb;
91
@@ -XXX,XX +XXX,XX @@ static void init_ts_info(OptContext *ctx, TCGTemp *ts)
33
uint32_t hash;
92
ti->is_const = true;
34
93
ti->val = ts->val;
35
- cpu_get_tb_cpu_state(env, pc, cs_base, flags);
94
ti->z_mask = ts->val;
36
- hash = tb_jmp_cache_hash_func(*pc);
95
- ti->s_mask = smask_from_value(ts->val);
37
+ hash = tb_jmp_cache_hash_func(pc);
96
+ ti->s_mask = INT64_MIN >> clrsb64(ts->val);
38
tb = qatomic_rcu_read(&cpu->tb_jmp_cache[hash]);
97
} else {
39
98
ti->is_const = false;
40
cf_mask &= ~CF_CLUSTER_MASK;
99
ti->z_mask = -1;
41
cf_mask |= cpu->cluster_index << CF_CLUSTER_SHIFT;
100
@@ -XXX,XX +XXX,XX @@ static void finish_folding(OptContext *ctx, TCGOp *op)
42
101
*/
43
if (likely(tb &&
102
if (i == 0) {
44
- tb->pc == *pc &&
103
ts_info(ts)->z_mask = ctx->z_mask;
45
- tb->cs_base == *cs_base &&
104
- ts_info(ts)->s_mask = ctx->s_mask;
46
- tb->flags == *flags &&
105
}
47
+ tb->pc == pc &&
48
+ tb->cs_base == cs_base &&
49
+ tb->flags == flags &&
50
tb->trace_vcpu_dstate == *cpu->trace_dstate &&
51
(tb_cflags(tb) & (CF_HASH_MASK | CF_INVALID)) == cf_mask)) {
52
return tb;
53
}
106
}
54
- tb = tb_htable_lookup(cpu, *pc, *cs_base, *flags, cf_mask);
107
}
55
+ tb = tb_htable_lookup(cpu, pc, cs_base, flags, cf_mask);
108
@@ -XXX,XX +XXX,XX @@ static bool fold_const2_commutative(OptContext *ctx, TCGOp *op)
56
if (tb == NULL) {
109
* The passed s_mask may be augmented by z_mask.
57
return NULL;
110
*/
111
static bool fold_masks_zs(OptContext *ctx, TCGOp *op,
112
- uint64_t z_mask, uint64_t s_mask)
113
+ uint64_t z_mask, int64_t s_mask)
114
{
115
const TCGOpDef *def = &tcg_op_defs[op->opc];
116
TCGTemp *ts;
117
TempOptInfo *ti;
118
+ int rep;
119
120
/* Only single-output opcodes are supported here. */
121
tcg_debug_assert(def->nb_oargs == 1);
122
@@ -XXX,XX +XXX,XX @@ static bool fold_masks_zs(OptContext *ctx, TCGOp *op,
123
*/
124
if (ctx->type == TCG_TYPE_I32) {
125
z_mask = (int32_t)z_mask;
126
- s_mask |= MAKE_64BIT_MASK(32, 32);
127
+ s_mask |= INT32_MIN;
58
}
128
}
59
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
129
60
index XXXXXXX..XXXXXXX 100644
130
if (z_mask == 0) {
61
--- a/accel/tcg/cpu-exec.c
131
@@ -XXX,XX +XXX,XX @@ static bool fold_masks_zs(OptContext *ctx, TCGOp *op,
62
+++ b/accel/tcg/cpu-exec.c
132
63
@@ -XXX,XX +XXX,XX @@ static void cpu_exec_exit(CPUState *cpu)
133
ti = ts_info(ts);
64
134
ti->z_mask = z_mask;
65
void cpu_exec_step_atomic(CPUState *cpu)
135
- ti->s_mask = s_mask | smask_from_zmask(z_mask);
66
{
67
+ CPUArchState *env = (CPUArchState *)cpu->env_ptr;
68
TranslationBlock *tb;
69
target_ulong cs_base, pc;
70
uint32_t flags;
71
@@ -XXX,XX +XXX,XX @@ void cpu_exec_step_atomic(CPUState *cpu)
72
g_assert(!cpu->running);
73
cpu->running = true;
74
75
- tb = tb_lookup__cpu_state(cpu, &pc, &cs_base, &flags, cf_mask);
76
+ cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags);
77
+ tb = tb_lookup(cpu, pc, cs_base, flags, cf_mask);
78
+
136
+
79
if (tb == NULL) {
137
+ /* Canonicalize s_mask and incorporate data from z_mask. */
80
mmap_lock();
138
+ rep = clz64(~s_mask);
81
tb = tb_gen_code(cpu, pc, cs_base, flags, cflags);
139
+ rep = MAX(rep, clz64(z_mask));
82
@@ -XXX,XX +XXX,XX @@ static inline TranslationBlock *tb_find(CPUState *cpu,
140
+ rep = MAX(rep - 1, 0);
83
TranslationBlock *last_tb,
141
+ ti->s_mask = INT64_MIN >> rep;
84
int tb_exit, uint32_t cf_mask)
85
{
86
+ CPUArchState *env = (CPUArchState *)cpu->env_ptr;
87
TranslationBlock *tb;
88
target_ulong cs_base, pc;
89
uint32_t flags;
90
91
- tb = tb_lookup__cpu_state(cpu, &pc, &cs_base, &flags, cf_mask);
92
+ cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags);
93
+
142
+
94
+ tb = tb_lookup(cpu, pc, cs_base, flags, cf_mask);
143
return true;
95
if (tb == NULL) {
144
}
96
mmap_lock();
145
97
tb = tb_gen_code(cpu, pc, cs_base, flags, cf_mask);
146
@@ -XXX,XX +XXX,XX @@ static bool fold_exts(OptContext *ctx, TCGOp *op)
98
diff --git a/accel/tcg/tcg-runtime.c b/accel/tcg/tcg-runtime.c
147
99
index XXXXXXX..XXXXXXX 100644
148
ctx->z_mask = z_mask;
100
--- a/accel/tcg/tcg-runtime.c
149
ctx->s_mask = s_mask;
101
+++ b/accel/tcg/tcg-runtime.c
150
- if (!type_change && fold_affected_mask(ctx, op, s_mask & ~s_mask_old)) {
102
@@ -XXX,XX +XXX,XX @@ const void *HELPER(lookup_tb_ptr)(CPUArchState *env)
151
+ if (0 && !type_change && fold_affected_mask(ctx, op, s_mask & ~s_mask_old)) {
103
target_ulong cs_base, pc;
152
return true;
104
uint32_t flags;
153
}
105
154
106
- tb = tb_lookup__cpu_state(cpu, &pc, &cs_base, &flags, curr_cflags());
155
@@ -XXX,XX +XXX,XX @@ static bool fold_sextract(OptContext *ctx, TCGOp *op)
107
+ cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags);
156
s_mask |= MAKE_64BIT_MASK(len, 64 - len);
108
+
157
ctx->s_mask = s_mask;
109
+ tb = tb_lookup(cpu, pc, cs_base, flags, curr_cflags());
158
110
if (tb == NULL) {
159
- if (pos == 0 && fold_affected_mask(ctx, op, s_mask & ~s_mask_old)) {
111
return tcg_code_gen_epilogue;
160
+ if (0 && pos == 0 && fold_affected_mask(ctx, op, s_mask & ~s_mask_old)) {
161
return true;
162
}
163
164
@@ -XXX,XX +XXX,XX @@ static bool fold_shift(OptContext *ctx, TCGOp *op)
165
ctx->z_mask = do_constant_folding(op->opc, ctx->type, z_mask, sh);
166
167
s_mask = do_constant_folding(op->opc, ctx->type, s_mask, sh);
168
- ctx->s_mask = smask_from_smask(s_mask);
169
170
return fold_masks(ctx, op);
112
}
171
}
113
--
172
--
114
2.25.1
173
2.43.0
115
116
diff view generated by jsdifflib
New patch
[PULL 09/72] tcg/optimize: Use finish_folding in fold_add, fold_add_vec, fold_addsub2
1
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
2
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
3
---
4
tcg/optimize.c | 9 +++++----
5
1 file changed, 5 insertions(+), 4 deletions(-)
1
6
7
diff --git a/tcg/optimize.c b/tcg/optimize.c
8
index XXXXXXX..XXXXXXX 100644
9
--- a/tcg/optimize.c
10
+++ b/tcg/optimize.c
11
@@ -XXX,XX +XXX,XX @@ static void finish_ebb(OptContext *ctx)
12
remove_mem_copy_all(ctx);
13
}
14
15
-static void finish_folding(OptContext *ctx, TCGOp *op)
16
+static bool finish_folding(OptContext *ctx, TCGOp *op)
17
{
18
const TCGOpDef *def = &tcg_op_defs[op->opc];
19
int i, nb_oargs;
20
@@ -XXX,XX +XXX,XX @@ static void finish_folding(OptContext *ctx, TCGOp *op)
21
ts_info(ts)->z_mask = ctx->z_mask;
22
}
23
}
24
+ return true;
25
}
26
27
/*
28
@@ -XXX,XX +XXX,XX @@ static bool fold_add(OptContext *ctx, TCGOp *op)
29
fold_xi_to_x(ctx, op, 0)) {
30
return true;
31
}
32
- return false;
33
+ return finish_folding(ctx, op);
34
}
35
36
/* We cannot as yet do_constant_folding with vectors. */
37
@@ -XXX,XX +XXX,XX @@ static bool fold_add_vec(OptContext *ctx, TCGOp *op)
38
fold_xi_to_x(ctx, op, 0)) {
39
return true;
40
}
41
- return false;
42
+ return finish_folding(ctx, op);
43
}
44
45
static bool fold_addsub2(OptContext *ctx, TCGOp *op, bool add)
46
@@ -XXX,XX +XXX,XX @@ static bool fold_addsub2(OptContext *ctx, TCGOp *op, bool add)
47
op->args[4] = arg_new_constant(ctx, bl);
48
op->args[5] = arg_new_constant(ctx, bh);
49
}
50
- return false;
51
+ return finish_folding(ctx, op);
52
}
53
54
static bool fold_add2(OptContext *ctx, TCGOp *op)
55
--
56
2.43.0
diff view generated by jsdifflib
[PATCH 03/27] tcg/aarch64: Fix generation of "scalar" vector operations
[PULL 10/72] tcg/optimize: Introduce const value accessors for TempOptInfo
1
For some vector operations, "1D" is not a valid type, and there
1
Introduce ti_is_const, ti_const_val, ti_is_const_val.
2
are separate instructions for the 64-bit scalar operation.
3
2
4
Tested-by: Stefan Weil <sw@weilnetz.de>
5
Buglink: https://bugs.launchpad.net/qemu/+bug/1916112
6
Fixes: 14e4c1e2355 ("tcg/aarch64: Add vector operations")
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
---
4
---
9
tcg/aarch64/tcg-target.c.inc | 211 ++++++++++++++++++++++++++++++-----
5
tcg/optimize.c | 20 +++++++++++++++++---
10
1 file changed, 181 insertions(+), 30 deletions(-)
6
1 file changed, 17 insertions(+), 3 deletions(-)
11
7
12
diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc
8
diff --git a/tcg/optimize.c b/tcg/optimize.c
13
index XXXXXXX..XXXXXXX 100644
9
index XXXXXXX..XXXXXXX 100644
14
--- a/tcg/aarch64/tcg-target.c.inc
10
--- a/tcg/optimize.c
15
+++ b/tcg/aarch64/tcg-target.c.inc
11
+++ b/tcg/optimize.c
16
@@ -XXX,XX +XXX,XX @@ typedef enum {
12
@@ -XXX,XX +XXX,XX @@ static inline TempOptInfo *arg_info(TCGArg arg)
17
I3606_BIC = 0x2f001400,
13
return ts_info(arg_temp(arg));
18
I3606_ORR = 0x0f001400,
19
20
+ /* AdvSIMD scalar shift by immediate */
21
+ I3609_SSHR = 0x5f000400,
22
+ I3609_SSRA = 0x5f001400,
23
+ I3609_SHL = 0x5f005400,
24
+ I3609_USHR = 0x7f000400,
25
+ I3609_USRA = 0x7f001400,
26
+ I3609_SLI = 0x7f005400,
27
+
28
+ /* AdvSIMD scalar three same */
29
+ I3611_SQADD = 0x5e200c00,
30
+ I3611_SQSUB = 0x5e202c00,
31
+ I3611_CMGT = 0x5e203400,
32
+ I3611_CMGE = 0x5e203c00,
33
+ I3611_SSHL = 0x5e204400,
34
+ I3611_ADD = 0x5e208400,
35
+ I3611_CMTST = 0x5e208c00,
36
+ I3611_UQADD = 0x7e200c00,
37
+ I3611_UQSUB = 0x7e202c00,
38
+ I3611_CMHI = 0x7e203400,
39
+ I3611_CMHS = 0x7e203c00,
40
+ I3611_USHL = 0x7e204400,
41
+ I3611_SUB = 0x7e208400,
42
+ I3611_CMEQ = 0x7e208c00,
43
+
44
+ /* AdvSIMD scalar two-reg misc */
45
+ I3612_CMGT0 = 0x5e208800,
46
+ I3612_CMEQ0 = 0x5e209800,
47
+ I3612_CMLT0 = 0x5e20a800,
48
+ I3612_ABS = 0x5e20b800,
49
+ I3612_CMGE0 = 0x7e208800,
50
+ I3612_CMLE0 = 0x7e209800,
51
+ I3612_NEG = 0x7e20b800,
52
+
53
/* AdvSIMD shift by immediate */
54
I3614_SSHR = 0x0f000400,
55
I3614_SSRA = 0x0f001400,
56
@@ -XXX,XX +XXX,XX @@ static void tcg_out_insn_3606(TCGContext *s, AArch64Insn insn, bool q,
57
| (imm8 & 0xe0) << (16 - 5) | (imm8 & 0x1f) << 5);
58
}
14
}
59
15
60
+static void tcg_out_insn_3609(TCGContext *s, AArch64Insn insn,
16
+static inline bool ti_is_const(TempOptInfo *ti)
61
+ TCGReg rd, TCGReg rn, unsigned immhb)
62
+{
17
+{
63
+ tcg_out32(s, insn | immhb << 16 | (rn & 0x1f) << 5 | (rd & 0x1f));
18
+ return ti->is_const;
64
+}
19
+}
65
+
20
+
66
+static void tcg_out_insn_3611(TCGContext *s, AArch64Insn insn,
21
+static inline uint64_t ti_const_val(TempOptInfo *ti)
67
+ unsigned size, TCGReg rd, TCGReg rn, TCGReg rm)
68
+{
22
+{
69
+ tcg_out32(s, insn | (size << 22) | (rm & 0x1f) << 16
23
+ return ti->val;
70
+ | (rn & 0x1f) << 5 | (rd & 0x1f));
71
+}
24
+}
72
+
25
+
73
+static void tcg_out_insn_3612(TCGContext *s, AArch64Insn insn,
26
+static inline bool ti_is_const_val(TempOptInfo *ti, uint64_t val)
74
+ unsigned size, TCGReg rd, TCGReg rn)
75
+{
27
+{
76
+ tcg_out32(s, insn | (size << 22) | (rn & 0x1f) << 5 | (rd & 0x1f));
28
+ return ti_is_const(ti) && ti_const_val(ti) == val;
77
+}
29
+}
78
+
30
+
79
static void tcg_out_insn_3614(TCGContext *s, AArch64Insn insn, bool q,
31
static inline bool ts_is_const(TCGTemp *ts)
80
TCGReg rd, TCGReg rn, unsigned immhb)
81
{
32
{
82
@@ -XXX,XX +XXX,XX @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
33
- return ts_info(ts)->is_const;
83
unsigned vecl, unsigned vece,
34
+ return ti_is_const(ts_info(ts));
84
const TCGArg *args, const int *const_args)
35
}
36
37
static inline bool ts_is_const_val(TCGTemp *ts, uint64_t val)
85
{
38
{
86
- static const AArch64Insn cmp_insn[16] = {
39
- TempOptInfo *ti = ts_info(ts);
87
+ static const AArch64Insn cmp_vec_insn[16] = {
40
- return ti->is_const && ti->val == val;
88
[TCG_COND_EQ] = I3616_CMEQ,
41
+ return ti_is_const_val(ts_info(ts), val);
89
[TCG_COND_GT] = I3616_CMGT,
42
}
90
[TCG_COND_GE] = I3616_CMGE,
43
91
[TCG_COND_GTU] = I3616_CMHI,
44
static inline bool arg_is_const(TCGArg arg)
92
[TCG_COND_GEU] = I3616_CMHS,
93
};
94
- static const AArch64Insn cmp0_insn[16] = {
95
+ static const AArch64Insn cmp_scalar_insn[16] = {
96
+ [TCG_COND_EQ] = I3611_CMEQ,
97
+ [TCG_COND_GT] = I3611_CMGT,
98
+ [TCG_COND_GE] = I3611_CMGE,
99
+ [TCG_COND_GTU] = I3611_CMHI,
100
+ [TCG_COND_GEU] = I3611_CMHS,
101
+ };
102
+ static const AArch64Insn cmp0_vec_insn[16] = {
103
[TCG_COND_EQ] = I3617_CMEQ0,
104
[TCG_COND_GT] = I3617_CMGT0,
105
[TCG_COND_GE] = I3617_CMGE0,
106
[TCG_COND_LT] = I3617_CMLT0,
107
[TCG_COND_LE] = I3617_CMLE0,
108
};
109
+ static const AArch64Insn cmp0_scalar_insn[16] = {
110
+ [TCG_COND_EQ] = I3612_CMEQ0,
111
+ [TCG_COND_GT] = I3612_CMGT0,
112
+ [TCG_COND_GE] = I3612_CMGE0,
113
+ [TCG_COND_LT] = I3612_CMLT0,
114
+ [TCG_COND_LE] = I3612_CMLE0,
115
+ };
116
117
TCGType type = vecl + TCG_TYPE_V64;
118
unsigned is_q = vecl;
119
+ bool is_scalar = !is_q && vece == MO_64;
120
TCGArg a0, a1, a2, a3;
121
int cmode, imm8;
122
123
@@ -XXX,XX +XXX,XX @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
124
tcg_out_dupm_vec(s, type, vece, a0, a1, a2);
125
break;
126
case INDEX_op_add_vec:
127
- tcg_out_insn(s, 3616, ADD, is_q, vece, a0, a1, a2);
128
+ if (is_scalar) {
129
+ tcg_out_insn(s, 3611, ADD, vece, a0, a1, a2);
130
+ } else {
131
+ tcg_out_insn(s, 3616, ADD, is_q, vece, a0, a1, a2);
132
+ }
133
break;
134
case INDEX_op_sub_vec:
135
- tcg_out_insn(s, 3616, SUB, is_q, vece, a0, a1, a2);
136
+ if (is_scalar) {
137
+ tcg_out_insn(s, 3611, SUB, vece, a0, a1, a2);
138
+ } else {
139
+ tcg_out_insn(s, 3616, SUB, is_q, vece, a0, a1, a2);
140
+ }
141
break;
142
case INDEX_op_mul_vec:
143
tcg_out_insn(s, 3616, MUL, is_q, vece, a0, a1, a2);
144
break;
145
case INDEX_op_neg_vec:
146
- tcg_out_insn(s, 3617, NEG, is_q, vece, a0, a1);
147
+ if (is_scalar) {
148
+ tcg_out_insn(s, 3612, NEG, vece, a0, a1);
149
+ } else {
150
+ tcg_out_insn(s, 3617, NEG, is_q, vece, a0, a1);
151
+ }
152
break;
153
case INDEX_op_abs_vec:
154
- tcg_out_insn(s, 3617, ABS, is_q, vece, a0, a1);
155
+ if (is_scalar) {
156
+ tcg_out_insn(s, 3612, ABS, vece, a0, a1);
157
+ } else {
158
+ tcg_out_insn(s, 3617, ABS, is_q, vece, a0, a1);
159
+ }
160
break;
161
case INDEX_op_and_vec:
162
if (const_args[2]) {
163
@@ -XXX,XX +XXX,XX @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
164
tcg_out_insn(s, 3616, EOR, is_q, 0, a0, a1, a2);
165
break;
166
case INDEX_op_ssadd_vec:
167
- tcg_out_insn(s, 3616, SQADD, is_q, vece, a0, a1, a2);
168
+ if (is_scalar) {
169
+ tcg_out_insn(s, 3611, SQADD, vece, a0, a1, a2);
170
+ } else {
171
+ tcg_out_insn(s, 3616, SQADD, is_q, vece, a0, a1, a2);
172
+ }
173
break;
174
case INDEX_op_sssub_vec:
175
- tcg_out_insn(s, 3616, SQSUB, is_q, vece, a0, a1, a2);
176
+ if (is_scalar) {
177
+ tcg_out_insn(s, 3611, SQSUB, vece, a0, a1, a2);
178
+ } else {
179
+ tcg_out_insn(s, 3616, SQSUB, is_q, vece, a0, a1, a2);
180
+ }
181
break;
182
case INDEX_op_usadd_vec:
183
- tcg_out_insn(s, 3616, UQADD, is_q, vece, a0, a1, a2);
184
+ if (is_scalar) {
185
+ tcg_out_insn(s, 3611, UQADD, vece, a0, a1, a2);
186
+ } else {
187
+ tcg_out_insn(s, 3616, UQADD, is_q, vece, a0, a1, a2);
188
+ }
189
break;
190
case INDEX_op_ussub_vec:
191
- tcg_out_insn(s, 3616, UQSUB, is_q, vece, a0, a1, a2);
192
+ if (is_scalar) {
193
+ tcg_out_insn(s, 3611, UQSUB, vece, a0, a1, a2);
194
+ } else {
195
+ tcg_out_insn(s, 3616, UQSUB, is_q, vece, a0, a1, a2);
196
+ }
197
break;
198
case INDEX_op_smax_vec:
199
tcg_out_insn(s, 3616, SMAX, is_q, vece, a0, a1, a2);
200
@@ -XXX,XX +XXX,XX @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
201
tcg_out_insn(s, 3617, NOT, is_q, 0, a0, a1);
202
break;
203
case INDEX_op_shli_vec:
204
- tcg_out_insn(s, 3614, SHL, is_q, a0, a1, a2 + (8 << vece));
205
+ if (is_scalar) {
206
+ tcg_out_insn(s, 3609, SHL, a0, a1, a2 + (8 << vece));
207
+ } else {
208
+ tcg_out_insn(s, 3614, SHL, is_q, a0, a1, a2 + (8 << vece));
209
+ }
210
break;
211
case INDEX_op_shri_vec:
212
- tcg_out_insn(s, 3614, USHR, is_q, a0, a1, (16 << vece) - a2);
213
+ if (is_scalar) {
214
+ tcg_out_insn(s, 3609, USHR, a0, a1, (16 << vece) - a2);
215
+ } else {
216
+ tcg_out_insn(s, 3614, USHR, is_q, a0, a1, (16 << vece) - a2);
217
+ }
218
break;
219
case INDEX_op_sari_vec:
220
- tcg_out_insn(s, 3614, SSHR, is_q, a0, a1, (16 << vece) - a2);
221
+ if (is_scalar) {
222
+ tcg_out_insn(s, 3609, SSHR, a0, a1, (16 << vece) - a2);
223
+ } else {
224
+ tcg_out_insn(s, 3614, SSHR, is_q, a0, a1, (16 << vece) - a2);
225
+ }
226
break;
227
case INDEX_op_aa64_sli_vec:
228
- tcg_out_insn(s, 3614, SLI, is_q, a0, a2, args[3] + (8 << vece));
229
+ if (is_scalar) {
230
+ tcg_out_insn(s, 3609, SLI, a0, a2, args[3] + (8 << vece));
231
+ } else {
232
+ tcg_out_insn(s, 3614, SLI, is_q, a0, a2, args[3] + (8 << vece));
233
+ }
234
break;
235
case INDEX_op_shlv_vec:
236
- tcg_out_insn(s, 3616, USHL, is_q, vece, a0, a1, a2);
237
+ if (is_scalar) {
238
+ tcg_out_insn(s, 3611, USHL, vece, a0, a1, a2);
239
+ } else {
240
+ tcg_out_insn(s, 3616, USHL, is_q, vece, a0, a1, a2);
241
+ }
242
break;
243
case INDEX_op_aa64_sshl_vec:
244
- tcg_out_insn(s, 3616, SSHL, is_q, vece, a0, a1, a2);
245
+ if (is_scalar) {
246
+ tcg_out_insn(s, 3611, SSHL, vece, a0, a1, a2);
247
+ } else {
248
+ tcg_out_insn(s, 3616, SSHL, is_q, vece, a0, a1, a2);
249
+ }
250
break;
251
case INDEX_op_cmp_vec:
252
{
253
@@ -XXX,XX +XXX,XX @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
254
255
if (cond == TCG_COND_NE) {
256
if (const_args[2]) {
257
- tcg_out_insn(s, 3616, CMTST, is_q, vece, a0, a1, a1);
258
+ if (is_scalar) {
259
+ tcg_out_insn(s, 3611, CMTST, vece, a0, a1, a1);
260
+ } else {
261
+ tcg_out_insn(s, 3616, CMTST, is_q, vece, a0, a1, a1);
262
+ }
263
} else {
264
- tcg_out_insn(s, 3616, CMEQ, is_q, vece, a0, a1, a2);
265
+ if (is_scalar) {
266
+ tcg_out_insn(s, 3611, CMEQ, vece, a0, a1, a2);
267
+ } else {
268
+ tcg_out_insn(s, 3616, CMEQ, is_q, vece, a0, a1, a2);
269
+ }
270
tcg_out_insn(s, 3617, NOT, is_q, 0, a0, a0);
271
}
272
} else {
273
if (const_args[2]) {
274
- insn = cmp0_insn[cond];
275
- if (insn) {
276
- tcg_out_insn_3617(s, insn, is_q, vece, a0, a1);
277
- break;
278
+ if (is_scalar) {
279
+ insn = cmp0_scalar_insn[cond];
280
+ if (insn) {
281
+ tcg_out_insn_3612(s, insn, vece, a0, a1);
282
+ break;
283
+ }
284
+ } else {
285
+ insn = cmp0_vec_insn[cond];
286
+ if (insn) {
287
+ tcg_out_insn_3617(s, insn, is_q, vece, a0, a1);
288
+ break;
289
+ }
290
}
291
tcg_out_dupi_vec(s, type, MO_8, TCG_VEC_TMP, 0);
292
a2 = TCG_VEC_TMP;
293
}
294
- insn = cmp_insn[cond];
295
- if (insn == 0) {
296
- TCGArg t;
297
- t = a1, a1 = a2, a2 = t;
298
- cond = tcg_swap_cond(cond);
299
- insn = cmp_insn[cond];
300
- tcg_debug_assert(insn != 0);
301
+ if (is_scalar) {
302
+ insn = cmp_scalar_insn[cond];
303
+ if (insn == 0) {
304
+ TCGArg t;
305
+ t = a1, a1 = a2, a2 = t;
306
+ cond = tcg_swap_cond(cond);
307
+ insn = cmp_scalar_insn[cond];
308
+ tcg_debug_assert(insn != 0);
309
+ }
310
+ tcg_out_insn_3611(s, insn, vece, a0, a1, a2);
311
+ } else {
312
+ insn = cmp_vec_insn[cond];
313
+ if (insn == 0) {
314
+ TCGArg t;
315
+ t = a1, a1 = a2, a2 = t;
316
+ cond = tcg_swap_cond(cond);
317
+ insn = cmp_vec_insn[cond];
318
+ tcg_debug_assert(insn != 0);
319
+ }
320
+ tcg_out_insn_3616(s, insn, is_q, vece, a0, a1, a2);
321
}
322
- tcg_out_insn_3616(s, insn, is_q, vece, a0, a1, a2);
323
}
324
}
325
break;
326
--
45
--
327
2.25.1
46
2.43.0
328
329
diff view generated by jsdifflib
New patch
[PULL 11/72] tcg/optimize: Use fold_masks_zs in fold_and
1
Avoid the use of the OptContext slots. Find TempOptInfo once.
2
Sink mask computation below fold_affected_mask early exit.
1
3
4
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
---
7
tcg/optimize.c | 30 ++++++++++++++++--------------
8
1 file changed, 16 insertions(+), 14 deletions(-)
9
10
diff --git a/tcg/optimize.c b/tcg/optimize.c
11
index XXXXXXX..XXXXXXX 100644
12
--- a/tcg/optimize.c
13
+++ b/tcg/optimize.c
14
@@ -XXX,XX +XXX,XX @@ static bool fold_add2(OptContext *ctx, TCGOp *op)
15
16
static bool fold_and(OptContext *ctx, TCGOp *op)
17
{
18
- uint64_t z1, z2;
19
+ uint64_t z1, z2, z_mask, s_mask;
20
+ TempOptInfo *t1, *t2;
21
22
if (fold_const2_commutative(ctx, op) ||
23
fold_xi_to_i(ctx, op, 0) ||
24
@@ -XXX,XX +XXX,XX @@ static bool fold_and(OptContext *ctx, TCGOp *op)
25
return true;
26
}
27
28
- z1 = arg_info(op->args[1])->z_mask;
29
- z2 = arg_info(op->args[2])->z_mask;
30
- ctx->z_mask = z1 & z2;
31
-
32
- /*
33
- * Sign repetitions are perforce all identical, whether they are 1 or 0.
34
- * Bitwise operations preserve the relative quantity of the repetitions.
35
- */
36
- ctx->s_mask = arg_info(op->args[1])->s_mask
37
- & arg_info(op->args[2])->s_mask;
38
+ t1 = arg_info(op->args[1]);
39
+ t2 = arg_info(op->args[2]);
40
+ z1 = t1->z_mask;
41
+ z2 = t2->z_mask;
42
43
/*
44
* Known-zeros does not imply known-ones. Therefore unless
45
* arg2 is constant, we can't infer affected bits from it.
46
*/
47
- if (arg_is_const(op->args[2]) &&
48
- fold_affected_mask(ctx, op, z1 & ~z2)) {
49
+ if (ti_is_const(t2) && fold_affected_mask(ctx, op, z1 & ~z2)) {
50
return true;
51
}
52
53
- return fold_masks(ctx, op);
54
+ z_mask = z1 & z2;
55
+
56
+ /*
57
+ * Sign repetitions are perforce all identical, whether they are 1 or 0.
58
+ * Bitwise operations preserve the relative quantity of the repetitions.
59
+ */
60
+ s_mask = t1->s_mask & t2->s_mask;
61
+
62
+ return fold_masks_zs(ctx, op, z_mask, s_mask);
63
}
64
65
static bool fold_andc(OptContext *ctx, TCGOp *op)
66
--
67
2.43.0
diff view generated by jsdifflib
New patch
[PULL 12/72] tcg/optimize: Use fold_masks_zs in fold_andc
1
Avoid the use of the OptContext slots. Find TempOptInfo once.
2
Avoid double inversion of the value of second const operand.
1
3
4
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
---
7
tcg/optimize.c | 21 +++++++++++----------
8
1 file changed, 11 insertions(+), 10 deletions(-)
9
10
diff --git a/tcg/optimize.c b/tcg/optimize.c
11
index XXXXXXX..XXXXXXX 100644
12
--- a/tcg/optimize.c
13
+++ b/tcg/optimize.c
14
@@ -XXX,XX +XXX,XX @@ static bool fold_and(OptContext *ctx, TCGOp *op)
15
16
static bool fold_andc(OptContext *ctx, TCGOp *op)
17
{
18
- uint64_t z1;
19
+ uint64_t z_mask, s_mask;
20
+ TempOptInfo *t1, *t2;
21
22
if (fold_const2(ctx, op) ||
23
fold_xx_to_i(ctx, op, 0) ||
24
@@ -XXX,XX +XXX,XX @@ static bool fold_andc(OptContext *ctx, TCGOp *op)
25
return true;
26
}
27
28
- z1 = arg_info(op->args[1])->z_mask;
29
+ t1 = arg_info(op->args[1]);
30
+ t2 = arg_info(op->args[2]);
31
+ z_mask = t1->z_mask;
32
33
/*
34
* Known-zeros does not imply known-ones. Therefore unless
35
* arg2 is constant, we can't infer anything from it.
36
*/
37
- if (arg_is_const(op->args[2])) {
38
- uint64_t z2 = ~arg_info(op->args[2])->z_mask;
39
- if (fold_affected_mask(ctx, op, z1 & ~z2)) {
40
+ if (ti_is_const(t2)) {
41
+ uint64_t v2 = ti_const_val(t2);
42
+ if (fold_affected_mask(ctx, op, z_mask & v2)) {
43
return true;
44
}
45
- z1 &= z2;
46
+ z_mask &= ~v2;
47
}
48
- ctx->z_mask = z1;
49
50
- ctx->s_mask = arg_info(op->args[1])->s_mask
51
- & arg_info(op->args[2])->s_mask;
52
- return fold_masks(ctx, op);
53
+ s_mask = t1->s_mask & t2->s_mask;
54
+ return fold_masks_zs(ctx, op, z_mask, s_mask);
55
}
56
57
static bool fold_brcond(OptContext *ctx, TCGOp *op)
58
--
59
2.43.0
diff view generated by jsdifflib
New patch
[PULL 13/72] tcg/optimize: Use fold_masks_zs in fold_bswap
1
Avoid the use of the OptContext slots. Find TempOptInfo once.
2
Always set s_mask along the BSWAP_OS path, since the result is
3
being explicitly sign-extended.
1
4
5
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
---
8
tcg/optimize.c | 21 ++++++++++-----------
9
1 file changed, 10 insertions(+), 11 deletions(-)
10
11
diff --git a/tcg/optimize.c b/tcg/optimize.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/tcg/optimize.c
14
+++ b/tcg/optimize.c
15
@@ -XXX,XX +XXX,XX @@ static bool fold_brcond2(OptContext *ctx, TCGOp *op)
16
static bool fold_bswap(OptContext *ctx, TCGOp *op)
17
{
18
uint64_t z_mask, s_mask, sign;
19
+ TempOptInfo *t1 = arg_info(op->args[1]);
20
21
- if (arg_is_const(op->args[1])) {
22
- uint64_t t = arg_info(op->args[1])->val;
23
-
24
- t = do_constant_folding(op->opc, ctx->type, t, op->args[2]);
25
- return tcg_opt_gen_movi(ctx, op, op->args[0], t);
26
+ if (ti_is_const(t1)) {
27
+ return tcg_opt_gen_movi(ctx, op, op->args[0],
28
+ do_constant_folding(op->opc, ctx->type,
29
+ ti_const_val(t1),
30
+ op->args[2]));
31
}
32
33
- z_mask = arg_info(op->args[1])->z_mask;
34
-
35
+ z_mask = t1->z_mask;
36
switch (op->opc) {
37
case INDEX_op_bswap16_i32:
38
case INDEX_op_bswap16_i64:
39
@@ -XXX,XX +XXX,XX @@ static bool fold_bswap(OptContext *ctx, TCGOp *op)
40
/* If the sign bit may be 1, force all the bits above to 1. */
41
if (z_mask & sign) {
42
z_mask |= sign;
43
- s_mask = sign << 1;
44
}
45
+ /* The value and therefore s_mask is explicitly sign-extended. */
46
+ s_mask = sign;
47
break;
48
default:
49
/* The high bits are undefined: force all bits above the sign to 1. */
50
z_mask |= sign << 1;
51
break;
52
}
53
- ctx->z_mask = z_mask;
54
- ctx->s_mask = s_mask;
55
56
- return fold_masks(ctx, op);
57
+ return fold_masks_zs(ctx, op, z_mask, s_mask);
58
}
59
60
static bool fold_call(OptContext *ctx, TCGOp *op)
61
--
62
2.43.0
diff view generated by jsdifflib
New patch
[PULL 14/72] tcg/optimize: Use fold_masks_zs in fold_count_zeros
1
Avoid the use of the OptContext slots. Find TempOptInfo once.
2
Compute s_mask from the union of the maximum count and the
3
op2 fallback for op1 being zero.
1
4
5
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
---
8
tcg/optimize.c | 15 ++++++++++-----
9
1 file changed, 10 insertions(+), 5 deletions(-)
10
11
diff --git a/tcg/optimize.c b/tcg/optimize.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/tcg/optimize.c
14
+++ b/tcg/optimize.c
15
@@ -XXX,XX +XXX,XX @@ static bool fold_call(OptContext *ctx, TCGOp *op)
16
17
static bool fold_count_zeros(OptContext *ctx, TCGOp *op)
18
{
19
- uint64_t z_mask;
20
+ uint64_t z_mask, s_mask;
21
+ TempOptInfo *t1 = arg_info(op->args[1]);
22
+ TempOptInfo *t2 = arg_info(op->args[2]);
23
24
- if (arg_is_const(op->args[1])) {
25
- uint64_t t = arg_info(op->args[1])->val;
26
+ if (ti_is_const(t1)) {
27
+ uint64_t t = ti_const_val(t1);
28
29
if (t != 0) {
30
t = do_constant_folding(op->opc, ctx->type, t, 0);
31
@@ -XXX,XX +XXX,XX @@ static bool fold_count_zeros(OptContext *ctx, TCGOp *op)
32
default:
33
g_assert_not_reached();
34
}
35
- ctx->z_mask = arg_info(op->args[2])->z_mask | z_mask;
36
- return false;
37
+ s_mask = ~z_mask;
38
+ z_mask |= t2->z_mask;
39
+ s_mask &= t2->s_mask;
40
+
41
+ return fold_masks_zs(ctx, op, z_mask, s_mask);
42
}
43
44
static bool fold_ctpop(OptContext *ctx, TCGOp *op)
45
--
46
2.43.0
diff view generated by jsdifflib
New patch
[PULL 15/72] tcg/optimize: Use fold_masks_z in fold_ctpop
1
Add fold_masks_z as a trivial wrapper around fold_masks_zs.
2
Avoid the use of the OptContext slots.
1
3
4
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
---
7
tcg/optimize.c | 13 ++++++++++---
8
1 file changed, 10 insertions(+), 3 deletions(-)
9
10
diff --git a/tcg/optimize.c b/tcg/optimize.c
11
index XXXXXXX..XXXXXXX 100644
12
--- a/tcg/optimize.c
13
+++ b/tcg/optimize.c
14
@@ -XXX,XX +XXX,XX @@ static bool fold_masks_zs(OptContext *ctx, TCGOp *op,
15
return true;
16
}
17
18
+static bool fold_masks_z(OptContext *ctx, TCGOp *op, uint64_t z_mask)
19
+{
20
+ return fold_masks_zs(ctx, op, z_mask, 0);
21
+}
22
+
23
static bool fold_masks(OptContext *ctx, TCGOp *op)
24
{
25
return fold_masks_zs(ctx, op, ctx->z_mask, ctx->s_mask);
26
@@ -XXX,XX +XXX,XX @@ static bool fold_count_zeros(OptContext *ctx, TCGOp *op)
27
28
static bool fold_ctpop(OptContext *ctx, TCGOp *op)
29
{
30
+ uint64_t z_mask;
31
+
32
if (fold_const1(ctx, op)) {
33
return true;
34
}
35
36
switch (ctx->type) {
37
case TCG_TYPE_I32:
38
- ctx->z_mask = 32 | 31;
39
+ z_mask = 32 | 31;
40
break;
41
case TCG_TYPE_I64:
42
- ctx->z_mask = 64 | 63;
43
+ z_mask = 64 | 63;
44
break;
45
default:
46
g_assert_not_reached();
47
}
48
- return false;
49
+ return fold_masks_z(ctx, op, z_mask);
50
}
51
52
static bool fold_deposit(OptContext *ctx, TCGOp *op)
53
--
54
2.43.0
diff view generated by jsdifflib
New patch
[PULL 16/72] tcg/optimize: Use fold_and and fold_masks_z in fold_deposit
1
Avoid the use of the OptContext slots. Find TempOptInfo once.
2
When we fold to and, use fold_and.
1
3
4
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
---
7
tcg/optimize.c | 35 +++++++++++++++++------------------
8
1 file changed, 17 insertions(+), 18 deletions(-)
9
10
diff --git a/tcg/optimize.c b/tcg/optimize.c
11
index XXXXXXX..XXXXXXX 100644
12
--- a/tcg/optimize.c
13
+++ b/tcg/optimize.c
14
@@ -XXX,XX +XXX,XX @@ static bool fold_ctpop(OptContext *ctx, TCGOp *op)
15
16
static bool fold_deposit(OptContext *ctx, TCGOp *op)
17
{
18
+ TempOptInfo *t1 = arg_info(op->args[1]);
19
+ TempOptInfo *t2 = arg_info(op->args[2]);
20
+ int ofs = op->args[3];
21
+ int len = op->args[4];
22
TCGOpcode and_opc;
23
+ uint64_t z_mask;
24
25
- if (arg_is_const(op->args[1]) && arg_is_const(op->args[2])) {
26
- uint64_t t1 = arg_info(op->args[1])->val;
27
- uint64_t t2 = arg_info(op->args[2])->val;
28
-
29
- t1 = deposit64(t1, op->args[3], op->args[4], t2);
30
- return tcg_opt_gen_movi(ctx, op, op->args[0], t1);
31
+ if (ti_is_const(t1) && ti_is_const(t2)) {
32
+ return tcg_opt_gen_movi(ctx, op, op->args[0],
33
+ deposit64(ti_const_val(t1), ofs, len,
34
+ ti_const_val(t2)));
35
}
36
37
switch (ctx->type) {
38
@@ -XXX,XX +XXX,XX @@ static bool fold_deposit(OptContext *ctx, TCGOp *op)
39
}
40
41
/* Inserting a value into zero at offset 0. */
42
- if (arg_is_const_val(op->args[1], 0) && op->args[3] == 0) {
43
- uint64_t mask = MAKE_64BIT_MASK(0, op->args[4]);
44
+ if (ti_is_const_val(t1, 0) && ofs == 0) {
45
+ uint64_t mask = MAKE_64BIT_MASK(0, len);
46
47
op->opc = and_opc;
48
op->args[1] = op->args[2];
49
op->args[2] = arg_new_constant(ctx, mask);
50
- ctx->z_mask = mask & arg_info(op->args[1])->z_mask;
51
- return false;
52
+ return fold_and(ctx, op);
53
}
54
55
/* Inserting zero into a value. */
56
- if (arg_is_const_val(op->args[2], 0)) {
57
- uint64_t mask = deposit64(-1, op->args[3], op->args[4], 0);
58
+ if (ti_is_const_val(t2, 0)) {
59
+ uint64_t mask = deposit64(-1, ofs, len, 0);
60
61
op->opc = and_opc;
62
op->args[2] = arg_new_constant(ctx, mask);
63
- ctx->z_mask = mask & arg_info(op->args[1])->z_mask;
64
- return false;
65
+ return fold_and(ctx, op);
66
}
67
68
- ctx->z_mask = deposit64(arg_info(op->args[1])->z_mask,
69
- op->args[3], op->args[4],
70
- arg_info(op->args[2])->z_mask);
71
- return false;
72
+ z_mask = deposit64(t1->z_mask, ofs, len, t2->z_mask);
73
+ return fold_masks_z(ctx, op, z_mask);
74
}
75
76
static bool fold_divide(OptContext *ctx, TCGOp *op)
77
--
78
2.43.0
diff view generated by jsdifflib
New patch
[PULL 17/72] tcg/optimize: Compute sign mask in fold_deposit
1
The input which overlaps the sign bit of the output can
2
have its input s_mask propagated to the output s_mask.
1
3
4
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
---
7
tcg/optimize.c | 14 ++++++++++++--
8
1 file changed, 12 insertions(+), 2 deletions(-)
9
10
diff --git a/tcg/optimize.c b/tcg/optimize.c
11
index XXXXXXX..XXXXXXX 100644
12
--- a/tcg/optimize.c
13
+++ b/tcg/optimize.c
14
@@ -XXX,XX +XXX,XX @@ static bool fold_deposit(OptContext *ctx, TCGOp *op)
15
TempOptInfo *t2 = arg_info(op->args[2]);
16
int ofs = op->args[3];
17
int len = op->args[4];
18
+ int width;
19
TCGOpcode and_opc;
20
- uint64_t z_mask;
21
+ uint64_t z_mask, s_mask;
22
23
if (ti_is_const(t1) && ti_is_const(t2)) {
24
return tcg_opt_gen_movi(ctx, op, op->args[0],
25
@@ -XXX,XX +XXX,XX @@ static bool fold_deposit(OptContext *ctx, TCGOp *op)
26
switch (ctx->type) {
27
case TCG_TYPE_I32:
28
and_opc = INDEX_op_and_i32;
29
+ width = 32;
30
break;
31
case TCG_TYPE_I64:
32
and_opc = INDEX_op_and_i64;
33
+ width = 64;
34
break;
35
default:
36
g_assert_not_reached();
37
@@ -XXX,XX +XXX,XX @@ static bool fold_deposit(OptContext *ctx, TCGOp *op)
38
return fold_and(ctx, op);
39
}
40
41
+ /* The s_mask from the top portion of the deposit is still valid. */
42
+ if (ofs + len == width) {
43
+ s_mask = t2->s_mask << ofs;
44
+ } else {
45
+ s_mask = t1->s_mask & ~MAKE_64BIT_MASK(0, ofs + len);
46
+ }
47
+
48
z_mask = deposit64(t1->z_mask, ofs, len, t2->z_mask);
49
- return fold_masks_z(ctx, op, z_mask);
50
+ return fold_masks_zs(ctx, op, z_mask, s_mask);
51
}
52
53
static bool fold_divide(OptContext *ctx, TCGOp *op)
54
--
55
2.43.0
diff view generated by jsdifflib
New patch
[PULL 18/72] tcg/optimize: Use finish_folding in fold_divide
1
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
2
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
3
---
4
tcg/optimize.c | 2 +-
5
1 file changed, 1 insertion(+), 1 deletion(-)
1
6
7
diff --git a/tcg/optimize.c b/tcg/optimize.c
8
index XXXXXXX..XXXXXXX 100644
9
--- a/tcg/optimize.c
10
+++ b/tcg/optimize.c
11
@@ -XXX,XX +XXX,XX @@ static bool fold_divide(OptContext *ctx, TCGOp *op)
12
fold_xi_to_x(ctx, op, 1)) {
13
return true;
14
}
15
- return false;
16
+ return finish_folding(ctx, op);
17
}
18
19
static bool fold_dup(OptContext *ctx, TCGOp *op)
20
--
21
2.43.0
diff view generated by jsdifflib
New patch
[PULL 19/72] tcg/optimize: Use finish_folding in fold_dup, fold_dup2
1
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
2
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
3
---
4
tcg/optimize.c | 4 ++--
5
1 file changed, 2 insertions(+), 2 deletions(-)
1
6
7
diff --git a/tcg/optimize.c b/tcg/optimize.c
8
index XXXXXXX..XXXXXXX 100644
9
--- a/tcg/optimize.c
10
+++ b/tcg/optimize.c
11
@@ -XXX,XX +XXX,XX @@ static bool fold_dup(OptContext *ctx, TCGOp *op)
12
t = dup_const(TCGOP_VECE(op), t);
13
return tcg_opt_gen_movi(ctx, op, op->args[0], t);
14
}
15
- return false;
16
+ return finish_folding(ctx, op);
17
}
18
19
static bool fold_dup2(OptContext *ctx, TCGOp *op)
20
@@ -XXX,XX +XXX,XX @@ static bool fold_dup2(OptContext *ctx, TCGOp *op)
21
op->opc = INDEX_op_dup_vec;
22
TCGOP_VECE(op) = MO_32;
23
}
24
- return false;
25
+ return finish_folding(ctx, op);
26
}
27
28
static bool fold_eqv(OptContext *ctx, TCGOp *op)
29
--
30
2.43.0
diff view generated by jsdifflib
[PATCH 27/27] accel/tcg: Precompute curr_cflags into cpu->tcg_cflags
[PULL 20/72] tcg/optimize: Use fold_masks_s in fold_eqv
1
The primary motivation is to remove a dozen insns along
1
Add fold_masks_s as a trivial wrapper around fold_masks_zs.
2
the fast-path in tb_lookup. As a byproduct, this allows
2
Avoid the use of the OptContext slots.
3
us to completely remove parallel_cpus.
4
3
4
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
---
6
---
7
accel/tcg/tcg-accel-ops.h | 1 +
7
tcg/optimize.c | 13 ++++++++++---
8
include/exec/exec-all.h | 7 +------
8
1 file changed, 10 insertions(+), 3 deletions(-)
9
include/hw/core/cpu.h | 2 ++
10
accel/tcg/cpu-exec.c | 3 ---
11
accel/tcg/tcg-accel-ops-mttcg.c | 3 +--
12
accel/tcg/tcg-accel-ops-rr.c | 2 +-
13
accel/tcg/tcg-accel-ops.c | 8 ++++++++
14
accel/tcg/translate-all.c | 4 ----
15
linux-user/main.c | 1 +
16
linux-user/sh4/signal.c | 8 +++++---
17
linux-user/syscall.c | 18 ++++++++++--------
18
11 files changed, 30 insertions(+), 27 deletions(-)
19
9
20
diff --git a/accel/tcg/tcg-accel-ops.h b/accel/tcg/tcg-accel-ops.h
10
diff --git a/tcg/optimize.c b/tcg/optimize.c
21
index XXXXXXX..XXXXXXX 100644
11
index XXXXXXX..XXXXXXX 100644
22
--- a/accel/tcg/tcg-accel-ops.h
12
--- a/tcg/optimize.c
23
+++ b/accel/tcg/tcg-accel-ops.h
13
+++ b/tcg/optimize.c
24
@@ -XXX,XX +XXX,XX @@
14
@@ -XXX,XX +XXX,XX @@ static bool fold_masks_z(OptContext *ctx, TCGOp *op, uint64_t z_mask)
25
void tcg_cpus_destroy(CPUState *cpu);
15
return fold_masks_zs(ctx, op, z_mask, 0);
26
int tcg_cpus_exec(CPUState *cpu);
27
void tcg_handle_interrupt(CPUState *cpu, int mask);
28
+void tcg_cpu_init_cflags(CPUState *cpu, bool parallel);
29
30
#endif /* TCG_CPUS_H */
31
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
32
index XXXXXXX..XXXXXXX 100644
33
--- a/include/exec/exec-all.h
34
+++ b/include/exec/exec-all.h
35
@@ -XXX,XX +XXX,XX @@ struct TranslationBlock {
36
uintptr_t jmp_dest[2];
37
};
38
39
-extern bool parallel_cpus;
40
-
41
/* Hide the qatomic_read to make code a little easier on the eyes */
42
static inline uint32_t tb_cflags(const TranslationBlock *tb)
43
{
44
@@ -XXX,XX +XXX,XX @@ static inline uint32_t tb_cflags(const TranslationBlock *tb)
45
/* current cflags for hashing/comparison */
46
static inline uint32_t curr_cflags(CPUState *cpu)
47
{
48
- uint32_t cflags = deposit32(0, CF_CLUSTER_SHIFT, 8, cpu->cluster_index);
49
- cflags |= parallel_cpus ? CF_PARALLEL : 0;
50
- cflags |= icount_enabled() ? CF_USE_ICOUNT : 0;
51
- return cflags;
52
+ return cpu->tcg_cflags;
53
}
16
}
54
17
55
/* TranslationBlock invalidate API */
18
+static bool fold_masks_s(OptContext *ctx, TCGOp *op, uint64_t s_mask)
56
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
57
index XXXXXXX..XXXXXXX 100644
58
--- a/include/hw/core/cpu.h
59
+++ b/include/hw/core/cpu.h
60
@@ -XXX,XX +XXX,XX @@ struct qemu_work_item;
61
* to a cluster this will be UNASSIGNED_CLUSTER_INDEX; otherwise it will
62
* be the same as the cluster-id property of the CPU object's TYPE_CPU_CLUSTER
63
* QOM parent.
64
+ * @tcg_cflags: Pre-computed cflags for this cpu.
65
* @nr_cores: Number of cores within this CPU package.
66
* @nr_threads: Number of threads within this CPU.
67
* @running: #true if CPU is currently running (lockless).
68
@@ -XXX,XX +XXX,XX @@ struct CPUState {
69
/* TODO Move common fields from CPUArchState here. */
70
int cpu_index;
71
int cluster_index;
72
+ uint32_t tcg_cflags;
73
uint32_t halted;
74
uint32_t can_do_io;
75
int32_t exception_index;
76
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
77
index XXXXXXX..XXXXXXX 100644
78
--- a/accel/tcg/cpu-exec.c
79
+++ b/accel/tcg/cpu-exec.c
80
@@ -XXX,XX +XXX,XX @@ void cpu_exec_step_atomic(CPUState *cpu)
81
mmap_unlock();
82
}
83
84
- /* Since we got here, we know that parallel_cpus must be true. */
85
- parallel_cpus = false;
86
cpu_exec_enter(cpu);
87
/* execute the generated code */
88
trace_exec_tb(tb, pc);
89
@@ -XXX,XX +XXX,XX @@ void cpu_exec_step_atomic(CPUState *cpu)
90
* the execution.
91
*/
92
g_assert(cpu_in_exclusive_context(cpu));
93
- parallel_cpus = true;
94
cpu->running = false;
95
end_exclusive();
96
}
97
diff --git a/accel/tcg/tcg-accel-ops-mttcg.c b/accel/tcg/tcg-accel-ops-mttcg.c
98
index XXXXXXX..XXXXXXX 100644
99
--- a/accel/tcg/tcg-accel-ops-mttcg.c
100
+++ b/accel/tcg/tcg-accel-ops-mttcg.c
101
@@ -XXX,XX +XXX,XX @@ void mttcg_start_vcpu_thread(CPUState *cpu)
102
char thread_name[VCPU_THREAD_NAME_SIZE];
103
104
g_assert(tcg_enabled());
105
-
106
- parallel_cpus = (current_machine->smp.max_cpus > 1);
107
+ tcg_cpu_init_cflags(cpu, current_machine->smp.max_cpus > 1);
108
109
cpu->thread = g_malloc0(sizeof(QemuThread));
110
cpu->halt_cond = g_malloc0(sizeof(QemuCond));
111
diff --git a/accel/tcg/tcg-accel-ops-rr.c b/accel/tcg/tcg-accel-ops-rr.c
112
index XXXXXXX..XXXXXXX 100644
113
--- a/accel/tcg/tcg-accel-ops-rr.c
114
+++ b/accel/tcg/tcg-accel-ops-rr.c
115
@@ -XXX,XX +XXX,XX @@ void rr_start_vcpu_thread(CPUState *cpu)
116
static QemuThread *single_tcg_cpu_thread;
117
118
g_assert(tcg_enabled());
119
- parallel_cpus = false;
120
+ tcg_cpu_init_cflags(cpu, false);
121
122
if (!single_tcg_cpu_thread) {
123
cpu->thread = g_malloc0(sizeof(QemuThread));
124
diff --git a/accel/tcg/tcg-accel-ops.c b/accel/tcg/tcg-accel-ops.c
125
index XXXXXXX..XXXXXXX 100644
126
--- a/accel/tcg/tcg-accel-ops.c
127
+++ b/accel/tcg/tcg-accel-ops.c
128
@@ -XXX,XX +XXX,XX @@
129
130
/* common functionality among all TCG variants */
131
132
+void tcg_cpu_init_cflags(CPUState *cpu, bool parallel)
133
+{
19
+{
134
+ uint32_t cflags = cpu->cluster_index << CF_CLUSTER_SHIFT;
20
+ return fold_masks_zs(ctx, op, -1, s_mask);
135
+ cflags |= parallel ? CF_PARALLEL : 0;
136
+ cflags |= icount_enabled() ? CF_USE_ICOUNT : 0;
137
+ cpu->tcg_cflags = cflags;
138
+}
21
+}
139
+
22
+
140
void tcg_cpus_destroy(CPUState *cpu)
23
static bool fold_masks(OptContext *ctx, TCGOp *op)
141
{
24
{
142
cpu_thread_signal_destroyed(cpu);
25
return fold_masks_zs(ctx, op, ctx->z_mask, ctx->s_mask);
143
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
26
@@ -XXX,XX +XXX,XX @@ static bool fold_dup2(OptContext *ctx, TCGOp *op)
144
index XXXXXXX..XXXXXXX 100644
27
145
--- a/accel/tcg/translate-all.c
28
static bool fold_eqv(OptContext *ctx, TCGOp *op)
146
+++ b/accel/tcg/translate-all.c
147
@@ -XXX,XX +XXX,XX @@ static void *l1_map[V_L1_MAX_SIZE];
148
TCGContext tcg_init_ctx;
149
__thread TCGContext *tcg_ctx;
150
TBContext tb_ctx;
151
-bool parallel_cpus;
152
153
static void page_table_config_init(void)
154
{
29
{
155
@@ -XXX,XX +XXX,XX @@ TranslationBlock *tb_gen_code(CPUState *cpu,
30
+ uint64_t s_mask;
156
cflags = (cflags & ~CF_COUNT_MASK) | 1;
31
+
32
if (fold_const2_commutative(ctx, op) ||
33
fold_xi_to_x(ctx, op, -1) ||
34
fold_xi_to_not(ctx, op, 0)) {
35
return true;
157
}
36
}
158
37
159
- cflags &= ~CF_CLUSTER_MASK;
38
- ctx->s_mask = arg_info(op->args[1])->s_mask
160
- cflags |= cpu->cluster_index << CF_CLUSTER_SHIFT;
39
- & arg_info(op->args[2])->s_mask;
161
-
40
- return false;
162
max_insns = cflags & CF_COUNT_MASK;
41
+ s_mask = arg_info(op->args[1])->s_mask
163
if (max_insns == 0) {
42
+ & arg_info(op->args[2])->s_mask;
164
max_insns = CF_COUNT_MASK;
43
+ return fold_masks_s(ctx, op, s_mask);
165
diff --git a/linux-user/main.c b/linux-user/main.c
166
index XXXXXXX..XXXXXXX 100644
167
--- a/linux-user/main.c
168
+++ b/linux-user/main.c
169
@@ -XXX,XX +XXX,XX @@ CPUArchState *cpu_copy(CPUArchState *env)
170
/* Reset non arch specific state */
171
cpu_reset(new_cpu);
172
173
+ new_cpu->tcg_cflags = cpu->tcg_cflags;
174
memcpy(new_env, env, sizeof(CPUArchState));
175
176
/* Clone all break/watchpoints.
177
diff --git a/linux-user/sh4/signal.c b/linux-user/sh4/signal.c
178
index XXXXXXX..XXXXXXX 100644
179
--- a/linux-user/sh4/signal.c
180
+++ b/linux-user/sh4/signal.c
181
@@ -XXX,XX +XXX,XX @@ static abi_ulong get_sigframe(struct target_sigaction *ka,
182
return (sp - frame_size) & -8ul;
183
}
44
}
184
45
185
-/* Notice when we're in the middle of a gUSA region and reset.
46
static bool fold_extract(OptContext *ctx, TCGOp *op)
186
- Note that this will only occur for !parallel_cpus, as we will
187
- translate such sequences differently in a parallel context. */
188
+/*
189
+ * Notice when we're in the middle of a gUSA region and reset.
190
+ * Note that this will only occur when #CF_PARALLEL is unset, as we
191
+ * will translate such sequences differently in a parallel context.
192
+ */
193
static void unwind_gusa(CPUSH4State *regs)
194
{
195
/* If the stack pointer is sufficiently negative, and we haven't
196
diff --git a/linux-user/syscall.c b/linux-user/syscall.c
197
index XXXXXXX..XXXXXXX 100644
198
--- a/linux-user/syscall.c
199
+++ b/linux-user/syscall.c
200
@@ -XXX,XX +XXX,XX @@ static int do_fork(CPUArchState *env, unsigned int flags, abi_ulong newsp,
201
/* Grab a mutex so that thread setup appears atomic. */
202
pthread_mutex_lock(&clone_lock);
203
204
+ /*
205
+ * If this is our first additional thread, we need to ensure we
206
+ * generate code for parallel execution and flush old translations.
207
+ * Do this now so that the copy gets CF_PARALLEL too.
208
+ */
209
+ if (!(cpu->tcg_cflags & CF_PARALLEL)) {
210
+ cpu->tcg_cflags |= CF_PARALLEL;
211
+ tb_flush(cpu);
212
+ }
213
+
214
/* we create a new CPU instance. */
215
new_env = cpu_copy(env);
216
/* Init regs that differ from the parent. */
217
@@ -XXX,XX +XXX,XX @@ static int do_fork(CPUArchState *env, unsigned int flags, abi_ulong newsp,
218
sigprocmask(SIG_BLOCK, &sigmask, &info.sigmask);
219
cpu->random_seed = qemu_guest_random_seed_thread_part1();
220
221
- /* If this is our first additional thread, we need to ensure we
222
- * generate code for parallel execution and flush old translations.
223
- */
224
- if (!parallel_cpus) {
225
- parallel_cpus = true;
226
- tb_flush(cpu);
227
- }
228
-
229
ret = pthread_create(&info.thread, &attr, clone_func, &info);
230
/* TODO: Free new CPU state if thread creation failed. */
231
232
--
47
--
233
2.25.1
48
2.43.0
234
235
diff view generated by jsdifflib
New patch
[PULL 21/72] tcg/optimize: Use fold_masks_z in fold_extract
1
Avoid the use of the OptContext slots. Find TempOptInfo once.
1
2
3
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
---
6
tcg/optimize.c | 15 ++++++---------
7
1 file changed, 6 insertions(+), 9 deletions(-)
8
9
diff --git a/tcg/optimize.c b/tcg/optimize.c
10
index XXXXXXX..XXXXXXX 100644
11
--- a/tcg/optimize.c
12
+++ b/tcg/optimize.c
13
@@ -XXX,XX +XXX,XX @@ static bool fold_eqv(OptContext *ctx, TCGOp *op)
14
static bool fold_extract(OptContext *ctx, TCGOp *op)
15
{
16
uint64_t z_mask_old, z_mask;
17
+ TempOptInfo *t1 = arg_info(op->args[1]);
18
int pos = op->args[2];
19
int len = op->args[3];
20
21
- if (arg_is_const(op->args[1])) {
22
- uint64_t t;
23
-
24
- t = arg_info(op->args[1])->val;
25
- t = extract64(t, pos, len);
26
- return tcg_opt_gen_movi(ctx, op, op->args[0], t);
27
+ if (ti_is_const(t1)) {
28
+ return tcg_opt_gen_movi(ctx, op, op->args[0],
29
+ extract64(ti_const_val(t1), pos, len));
30
}
31
32
- z_mask_old = arg_info(op->args[1])->z_mask;
33
+ z_mask_old = t1->z_mask;
34
z_mask = extract64(z_mask_old, pos, len);
35
if (pos == 0 && fold_affected_mask(ctx, op, z_mask_old ^ z_mask)) {
36
return true;
37
}
38
- ctx->z_mask = z_mask;
39
40
- return fold_masks(ctx, op);
41
+ return fold_masks_z(ctx, op, z_mask);
42
}
43
44
static bool fold_extract2(OptContext *ctx, TCGOp *op)
45
--
46
2.43.0
diff view generated by jsdifflib
New patch
[PULL 22/72] tcg/optimize: Use finish_folding in fold_extract2
1
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
2
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
3
---
4
tcg/optimize.c | 2 +-
5
1 file changed, 1 insertion(+), 1 deletion(-)
1
6
7
diff --git a/tcg/optimize.c b/tcg/optimize.c
8
index XXXXXXX..XXXXXXX 100644
9
--- a/tcg/optimize.c
10
+++ b/tcg/optimize.c
11
@@ -XXX,XX +XXX,XX @@ static bool fold_extract2(OptContext *ctx, TCGOp *op)
12
}
13
return tcg_opt_gen_movi(ctx, op, op->args[0], v1 | v2);
14
}
15
- return false;
16
+ return finish_folding(ctx, op);
17
}
18
19
static bool fold_exts(OptContext *ctx, TCGOp *op)
20
--
21
2.43.0
diff view generated by jsdifflib
New patch
[PULL 23/72] tcg/optimize: Use fold_masks_zs in fold_exts
1
Avoid the use of the OptContext slots. Find TempOptInfo once.
2
Explicitly sign-extend z_mask instead of doing that manually.
1
3
4
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
---
7
tcg/optimize.c | 29 ++++++++++++-----------------
8
1 file changed, 12 insertions(+), 17 deletions(-)
9
10
diff --git a/tcg/optimize.c b/tcg/optimize.c
11
index XXXXXXX..XXXXXXX 100644
12
--- a/tcg/optimize.c
13
+++ b/tcg/optimize.c
14
@@ -XXX,XX +XXX,XX @@ static bool fold_extract2(OptContext *ctx, TCGOp *op)
15
16
static bool fold_exts(OptContext *ctx, TCGOp *op)
17
{
18
- uint64_t s_mask_old, s_mask, z_mask, sign;
19
+ uint64_t s_mask_old, s_mask, z_mask;
20
bool type_change = false;
21
+ TempOptInfo *t1;
22
23
if (fold_const1(ctx, op)) {
24
return true;
25
}
26
27
- z_mask = arg_info(op->args[1])->z_mask;
28
- s_mask = arg_info(op->args[1])->s_mask;
29
+ t1 = arg_info(op->args[1]);
30
+ z_mask = t1->z_mask;
31
+ s_mask = t1->s_mask;
32
s_mask_old = s_mask;
33
34
switch (op->opc) {
35
CASE_OP_32_64(ext8s):
36
- sign = INT8_MIN;
37
- z_mask = (uint8_t)z_mask;
38
+ s_mask |= INT8_MIN;
39
+ z_mask = (int8_t)z_mask;
40
break;
41
CASE_OP_32_64(ext16s):
42
- sign = INT16_MIN;
43
- z_mask = (uint16_t)z_mask;
44
+ s_mask |= INT16_MIN;
45
+ z_mask = (int16_t)z_mask;
46
break;
47
case INDEX_op_ext_i32_i64:
48
type_change = true;
49
QEMU_FALLTHROUGH;
50
case INDEX_op_ext32s_i64:
51
- sign = INT32_MIN;
52
- z_mask = (uint32_t)z_mask;
53
+ s_mask |= INT32_MIN;
54
+ z_mask = (int32_t)z_mask;
55
break;
56
default:
57
g_assert_not_reached();
58
}
59
60
- if (z_mask & sign) {
61
- z_mask |= sign;
62
- }
63
- s_mask |= sign << 1;
64
-
65
- ctx->z_mask = z_mask;
66
- ctx->s_mask = s_mask;
67
if (0 && !type_change && fold_affected_mask(ctx, op, s_mask & ~s_mask_old)) {
68
return true;
69
}
70
71
- return fold_masks(ctx, op);
72
+ return fold_masks_zs(ctx, op, z_mask, s_mask);
73
}
74
75
static bool fold_extu(OptContext *ctx, TCGOp *op)
76
--
77
2.43.0
diff view generated by jsdifflib
New patch
[PULL 24/72] tcg/optimize: Use fold_masks_z in fold_extu
1
Avoid the use of the OptContext slots.
1
2
3
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
---
6
tcg/optimize.c | 4 ++--
7
1 file changed, 2 insertions(+), 2 deletions(-)
8
9
diff --git a/tcg/optimize.c b/tcg/optimize.c
10
index XXXXXXX..XXXXXXX 100644
11
--- a/tcg/optimize.c
12
+++ b/tcg/optimize.c
13
@@ -XXX,XX +XXX,XX @@ static bool fold_extu(OptContext *ctx, TCGOp *op)
14
g_assert_not_reached();
15
}
16
17
- ctx->z_mask = z_mask;
18
if (!type_change && fold_affected_mask(ctx, op, z_mask_old ^ z_mask)) {
19
return true;
20
}
21
- return fold_masks(ctx, op);
22
+
23
+ return fold_masks_z(ctx, op, z_mask);
24
}
25
26
static bool fold_mb(OptContext *ctx, TCGOp *op)
27
--
28
2.43.0
diff view generated by jsdifflib
New patch
[PULL 25/72] tcg/optimize: Use fold_masks_zs in fold_movcond
1
Avoid the use of the OptContext slots. Find TempOptInfo once.
1
2
3
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
---
6
tcg/optimize.c | 19 +++++++++++--------
7
1 file changed, 11 insertions(+), 8 deletions(-)
8
9
diff --git a/tcg/optimize.c b/tcg/optimize.c
10
index XXXXXXX..XXXXXXX 100644
11
--- a/tcg/optimize.c
12
+++ b/tcg/optimize.c
13
@@ -XXX,XX +XXX,XX @@ static bool fold_mov(OptContext *ctx, TCGOp *op)
14
15
static bool fold_movcond(OptContext *ctx, TCGOp *op)
16
{
17
+ uint64_t z_mask, s_mask;
18
+ TempOptInfo *tt, *ft;
19
int i;
20
21
/* If true and false values are the same, eliminate the cmp. */
22
@@ -XXX,XX +XXX,XX @@ static bool fold_movcond(OptContext *ctx, TCGOp *op)
23
return tcg_opt_gen_mov(ctx, op, op->args[0], op->args[4 - i]);
24
}
25
26
- ctx->z_mask = arg_info(op->args[3])->z_mask
27
- | arg_info(op->args[4])->z_mask;
28
- ctx->s_mask = arg_info(op->args[3])->s_mask
29
- & arg_info(op->args[4])->s_mask;
30
+ tt = arg_info(op->args[3]);
31
+ ft = arg_info(op->args[4]);
32
+ z_mask = tt->z_mask | ft->z_mask;
33
+ s_mask = tt->s_mask & ft->s_mask;
34
35
- if (arg_is_const(op->args[3]) && arg_is_const(op->args[4])) {
36
- uint64_t tv = arg_info(op->args[3])->val;
37
- uint64_t fv = arg_info(op->args[4])->val;
38
+ if (ti_is_const(tt) && ti_is_const(ft)) {
39
+ uint64_t tv = ti_const_val(tt);
40
+ uint64_t fv = ti_const_val(ft);
41
TCGOpcode opc, negopc = 0;
42
TCGCond cond = op->args[5];
43
44
@@ -XXX,XX +XXX,XX @@ static bool fold_movcond(OptContext *ctx, TCGOp *op)
45
}
46
}
47
}
48
- return false;
49
+
50
+ return fold_masks_zs(ctx, op, z_mask, s_mask);
51
}
52
53
static bool fold_mul(OptContext *ctx, TCGOp *op)
54
--
55
2.43.0
diff view generated by jsdifflib
New patch
[PULL 26/72] tcg/optimize: Use finish_folding in fold_mul*
1
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
2
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
3
---
4
tcg/optimize.c | 6 +++---
5
1 file changed, 3 insertions(+), 3 deletions(-)
1
6
7
diff --git a/tcg/optimize.c b/tcg/optimize.c
8
index XXXXXXX..XXXXXXX 100644
9
--- a/tcg/optimize.c
10
+++ b/tcg/optimize.c
11
@@ -XXX,XX +XXX,XX @@ static bool fold_mul(OptContext *ctx, TCGOp *op)
12
fold_xi_to_x(ctx, op, 1)) {
13
return true;
14
}
15
- return false;
16
+ return finish_folding(ctx, op);
17
}
18
19
static bool fold_mul_highpart(OptContext *ctx, TCGOp *op)
20
@@ -XXX,XX +XXX,XX @@ static bool fold_mul_highpart(OptContext *ctx, TCGOp *op)
21
fold_xi_to_i(ctx, op, 0)) {
22
return true;
23
}
24
- return false;
25
+ return finish_folding(ctx, op);
26
}
27
28
static bool fold_multiply2(OptContext *ctx, TCGOp *op)
29
@@ -XXX,XX +XXX,XX @@ static bool fold_multiply2(OptContext *ctx, TCGOp *op)
30
tcg_opt_gen_movi(ctx, op2, rh, h);
31
return true;
32
}
33
- return false;
34
+ return finish_folding(ctx, op);
35
}
36
37
static bool fold_nand(OptContext *ctx, TCGOp *op)
38
--
39
2.43.0
diff view generated by jsdifflib
New patch
[PULL 27/72] tcg/optimize: Use fold_masks_s in fold_nand
1
Avoid the use of the OptContext slots.
1
2
3
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
---
6
tcg/optimize.c | 8 +++++---
7
1 file changed, 5 insertions(+), 3 deletions(-)
8
9
diff --git a/tcg/optimize.c b/tcg/optimize.c
10
index XXXXXXX..XXXXXXX 100644
11
--- a/tcg/optimize.c
12
+++ b/tcg/optimize.c
13
@@ -XXX,XX +XXX,XX @@ static bool fold_multiply2(OptContext *ctx, TCGOp *op)
14
15
static bool fold_nand(OptContext *ctx, TCGOp *op)
16
{
17
+ uint64_t s_mask;
18
+
19
if (fold_const2_commutative(ctx, op) ||
20
fold_xi_to_not(ctx, op, -1)) {
21
return true;
22
}
23
24
- ctx->s_mask = arg_info(op->args[1])->s_mask
25
- & arg_info(op->args[2])->s_mask;
26
- return false;
27
+ s_mask = arg_info(op->args[1])->s_mask
28
+ & arg_info(op->args[2])->s_mask;
29
+ return fold_masks_s(ctx, op, s_mask);
30
}
31
32
static bool fold_neg_no_const(OptContext *ctx, TCGOp *op)
33
--
34
2.43.0
diff view generated by jsdifflib
New patch
[PULL 28/72] tcg/optimize: Use fold_masks_z in fold_neg_no_const
1
Avoid the use of the OptContext slots.
1
2
3
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
---
6
tcg/optimize.c | 9 ++-------
7
1 file changed, 2 insertions(+), 7 deletions(-)
8
9
diff --git a/tcg/optimize.c b/tcg/optimize.c
10
index XXXXXXX..XXXXXXX 100644
11
--- a/tcg/optimize.c
12
+++ b/tcg/optimize.c
13
@@ -XXX,XX +XXX,XX @@ static bool fold_neg_no_const(OptContext *ctx, TCGOp *op)
14
{
15
/* Set to 1 all bits to the left of the rightmost. */
16
uint64_t z_mask = arg_info(op->args[1])->z_mask;
17
- ctx->z_mask = -(z_mask & -z_mask);
18
+ z_mask = -(z_mask & -z_mask);
19
20
- /*
21
- * Because of fold_sub_to_neg, we want to always return true,
22
- * via finish_folding.
23
- */
24
- finish_folding(ctx, op);
25
- return true;
26
+ return fold_masks_z(ctx, op, z_mask);
27
}
28
29
static bool fold_neg(OptContext *ctx, TCGOp *op)
30
--
31
2.43.0
diff view generated by jsdifflib
New patch
[PULL 29/72] tcg/optimize: Use fold_masks_s in fold_nor
1
Avoid the use of the OptContext slots.
1
2
3
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
---
6
tcg/optimize.c | 8 +++++---
7
1 file changed, 5 insertions(+), 3 deletions(-)
8
9
diff --git a/tcg/optimize.c b/tcg/optimize.c
10
index XXXXXXX..XXXXXXX 100644
11
--- a/tcg/optimize.c
12
+++ b/tcg/optimize.c
13
@@ -XXX,XX +XXX,XX @@ static bool fold_neg(OptContext *ctx, TCGOp *op)
14
15
static bool fold_nor(OptContext *ctx, TCGOp *op)
16
{
17
+ uint64_t s_mask;
18
+
19
if (fold_const2_commutative(ctx, op) ||
20
fold_xi_to_not(ctx, op, 0)) {
21
return true;
22
}
23
24
- ctx->s_mask = arg_info(op->args[1])->s_mask
25
- & arg_info(op->args[2])->s_mask;
26
- return false;
27
+ s_mask = arg_info(op->args[1])->s_mask
28
+ & arg_info(op->args[2])->s_mask;
29
+ return fold_masks_s(ctx, op, s_mask);
30
}
31
32
static bool fold_not(OptContext *ctx, TCGOp *op)
33
--
34
2.43.0
diff view generated by jsdifflib
New patch
[PULL 30/72] tcg/optimize: Use fold_masks_s in fold_not
1
Avoid the use of the OptContext slots.
1
2
3
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
---
6
tcg/optimize.c | 7 +------
7
1 file changed, 1 insertion(+), 6 deletions(-)
8
9
diff --git a/tcg/optimize.c b/tcg/optimize.c
10
index XXXXXXX..XXXXXXX 100644
11
--- a/tcg/optimize.c
12
+++ b/tcg/optimize.c
13
@@ -XXX,XX +XXX,XX @@ static bool fold_not(OptContext *ctx, TCGOp *op)
14
if (fold_const1(ctx, op)) {
15
return true;
16
}
17
-
18
- ctx->s_mask = arg_info(op->args[1])->s_mask;
19
-
20
- /* Because of fold_to_not, we want to always return true, via finish. */
21
- finish_folding(ctx, op);
22
- return true;
23
+ return fold_masks_s(ctx, op, arg_info(op->args[1])->s_mask);
24
}
25
26
static bool fold_or(OptContext *ctx, TCGOp *op)
27
--
28
2.43.0
diff view generated by jsdifflib
New patch
[PULL 31/72] tcg/optimize: Use fold_masks_zs in fold_or
1
Avoid the use of the OptContext slots. Find TempOptInfo once.
1
2
3
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
---
6
tcg/optimize.c | 13 ++++++++-----
7
1 file changed, 8 insertions(+), 5 deletions(-)
8
9
diff --git a/tcg/optimize.c b/tcg/optimize.c
10
index XXXXXXX..XXXXXXX 100644
11
--- a/tcg/optimize.c
12
+++ b/tcg/optimize.c
13
@@ -XXX,XX +XXX,XX @@ static bool fold_not(OptContext *ctx, TCGOp *op)
14
15
static bool fold_or(OptContext *ctx, TCGOp *op)
16
{
17
+ uint64_t z_mask, s_mask;
18
+ TempOptInfo *t1, *t2;
19
+
20
if (fold_const2_commutative(ctx, op) ||
21
fold_xi_to_x(ctx, op, 0) ||
22
fold_xx_to_x(ctx, op)) {
23
return true;
24
}
25
26
- ctx->z_mask = arg_info(op->args[1])->z_mask
27
- | arg_info(op->args[2])->z_mask;
28
- ctx->s_mask = arg_info(op->args[1])->s_mask
29
- & arg_info(op->args[2])->s_mask;
30
- return fold_masks(ctx, op);
31
+ t1 = arg_info(op->args[1]);
32
+ t2 = arg_info(op->args[2]);
33
+ z_mask = t1->z_mask | t2->z_mask;
34
+ s_mask = t1->s_mask & t2->s_mask;
35
+ return fold_masks_zs(ctx, op, z_mask, s_mask);
36
}
37
38
static bool fold_orc(OptContext *ctx, TCGOp *op)
39
--
40
2.43.0
diff view generated by jsdifflib
[PATCH 26/27] include/exec: lightly re-arrange TranslationBlock
[PULL 32/72] tcg/optimize: Use fold_masks_zs in fold_orc
1
From: Alex Bennée <alex.bennee@linaro.org>
1
Avoid the use of the OptContext slots.
2
2
3
Lets make sure all the flags we compare when looking up blocks are
3
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
4
together in the same place.
5
6
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
7
Message-Id: <20210224165811.11567-5-alex.bennee@linaro.org>
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
---
5
---
10
include/exec/exec-all.h | 8 +++++---
6
tcg/optimize.c | 8 +++++---
11
1 file changed, 5 insertions(+), 3 deletions(-)
7
1 file changed, 5 insertions(+), 3 deletions(-)
12
8
13
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
9
diff --git a/tcg/optimize.c b/tcg/optimize.c
14
index XXXXXXX..XXXXXXX 100644
10
index XXXXXXX..XXXXXXX 100644
15
--- a/include/exec/exec-all.h
11
--- a/tcg/optimize.c
16
+++ b/include/exec/exec-all.h
12
+++ b/tcg/optimize.c
17
@@ -XXX,XX +XXX,XX @@ struct TranslationBlock {
13
@@ -XXX,XX +XXX,XX @@ static bool fold_or(OptContext *ctx, TCGOp *op)
18
target_ulong pc; /* simulated PC corresponding to this block (EIP + CS base) */
14
19
target_ulong cs_base; /* CS base for this block */
15
static bool fold_orc(OptContext *ctx, TCGOp *op)
20
uint32_t flags; /* flags defining in which context the code was generated */
16
{
21
- uint16_t size; /* size of target code for this block (1 <=
17
+ uint64_t s_mask;
22
- size <= TARGET_PAGE_SIZE) */
23
- uint16_t icount;
24
uint32_t cflags; /* compile flags */
25
#define CF_COUNT_MASK 0x00007fff
26
#define CF_LAST_IO 0x00008000 /* Last insn may be an IO access. */
27
@@ -XXX,XX +XXX,XX @@ struct TranslationBlock {
28
/* Per-vCPU dynamic tracing state used to generate this TB */
29
uint32_t trace_vcpu_dstate;
30
31
+ /* Above fields used for comparing */
32
+ uint16_t size; /* size of target code for this block (1 <=
33
+ size <= TARGET_PAGE_SIZE) */
34
+ uint16_t icount;
35
+
18
+
36
struct tb_tc tc;
19
if (fold_const2(ctx, op) ||
37
20
fold_xx_to_i(ctx, op, -1) ||
38
/* first and second physical page containing code. The lower bit
21
fold_xi_to_x(ctx, op, -1) ||
22
@@ -XXX,XX +XXX,XX @@ static bool fold_orc(OptContext *ctx, TCGOp *op)
23
return true;
24
}
25
26
- ctx->s_mask = arg_info(op->args[1])->s_mask
27
- & arg_info(op->args[2])->s_mask;
28
- return false;
29
+ s_mask = arg_info(op->args[1])->s_mask
30
+ & arg_info(op->args[2])->s_mask;
31
+ return fold_masks_s(ctx, op, s_mask);
32
}
33
34
static bool fold_qemu_ld(OptContext *ctx, TCGOp *op)
39
--
35
--
40
2.25.1
36
2.43.0
41
42
diff view generated by jsdifflib
New patch
[PULL 33/72] tcg/optimize: Use fold_masks_zs in fold_qemu_ld
1
Avoid the use of the OptContext slots.
1
2
3
Be careful not to call fold_masks_zs when the memory operation
4
is wide enough to require multiple outputs, so split into two
5
functions: fold_qemu_ld_1reg and fold_qemu_ld_2reg.
6
7
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
---
10
tcg/optimize.c | 26 +++++++++++++++++++++-----
11
1 file changed, 21 insertions(+), 5 deletions(-)
12
13
diff --git a/tcg/optimize.c b/tcg/optimize.c
14
index XXXXXXX..XXXXXXX 100644
15
--- a/tcg/optimize.c
16
+++ b/tcg/optimize.c
17
@@ -XXX,XX +XXX,XX @@ static bool fold_orc(OptContext *ctx, TCGOp *op)
18
return fold_masks_s(ctx, op, s_mask);
19
}
20
21
-static bool fold_qemu_ld(OptContext *ctx, TCGOp *op)
22
+static bool fold_qemu_ld_1reg(OptContext *ctx, TCGOp *op)
23
{
24
const TCGOpDef *def = &tcg_op_defs[op->opc];
25
MemOpIdx oi = op->args[def->nb_oargs + def->nb_iargs];
26
MemOp mop = get_memop(oi);
27
int width = 8 * memop_size(mop);
28
+ uint64_t z_mask = -1, s_mask = 0;
29
30
if (width < 64) {
31
if (mop & MO_SIGN) {
32
- ctx->s_mask = MAKE_64BIT_MASK(width, 64 - width);
33
+ s_mask = MAKE_64BIT_MASK(width - 1, 64 - (width - 1));
34
} else {
35
- ctx->z_mask = MAKE_64BIT_MASK(0, width);
36
+ z_mask = MAKE_64BIT_MASK(0, width);
37
}
38
}
39
40
/* Opcodes that touch guest memory stop the mb optimization. */
41
ctx->prev_mb = NULL;
42
- return false;
43
+
44
+ return fold_masks_zs(ctx, op, z_mask, s_mask);
45
+}
46
+
47
+static bool fold_qemu_ld_2reg(OptContext *ctx, TCGOp *op)
48
+{
49
+ /* Opcodes that touch guest memory stop the mb optimization. */
50
+ ctx->prev_mb = NULL;
51
+ return finish_folding(ctx, op);
52
}
53
54
static bool fold_qemu_st(OptContext *ctx, TCGOp *op)
55
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
56
break;
57
case INDEX_op_qemu_ld_a32_i32:
58
case INDEX_op_qemu_ld_a64_i32:
59
+ done = fold_qemu_ld_1reg(&ctx, op);
60
+ break;
61
case INDEX_op_qemu_ld_a32_i64:
62
case INDEX_op_qemu_ld_a64_i64:
63
+ if (TCG_TARGET_REG_BITS == 64) {
64
+ done = fold_qemu_ld_1reg(&ctx, op);
65
+ break;
66
+ }
67
+ QEMU_FALLTHROUGH;
68
case INDEX_op_qemu_ld_a32_i128:
69
case INDEX_op_qemu_ld_a64_i128:
70
- done = fold_qemu_ld(&ctx, op);
71
+ done = fold_qemu_ld_2reg(&ctx, op);
72
break;
73
case INDEX_op_qemu_st8_a32_i32:
74
case INDEX_op_qemu_st8_a64_i32:
75
--
76
2.43.0
diff view generated by jsdifflib
New patch
[PULL 34/72] tcg/optimize: Return true from fold_qemu_st, fold_tcg_st
1
Stores have no output operands, and so need no further work.
1
2
3
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
---
6
tcg/optimize.c | 11 +++++------
7
1 file changed, 5 insertions(+), 6 deletions(-)
8
9
diff --git a/tcg/optimize.c b/tcg/optimize.c
10
index XXXXXXX..XXXXXXX 100644
11
--- a/tcg/optimize.c
12
+++ b/tcg/optimize.c
13
@@ -XXX,XX +XXX,XX @@ static bool fold_qemu_st(OptContext *ctx, TCGOp *op)
14
{
15
/* Opcodes that touch guest memory stop the mb optimization. */
16
ctx->prev_mb = NULL;
17
- return false;
18
+ return true;
19
}
20
21
static bool fold_remainder(OptContext *ctx, TCGOp *op)
22
@@ -XXX,XX +XXX,XX @@ static bool fold_tcg_st(OptContext *ctx, TCGOp *op)
23
24
if (op->args[1] != tcgv_ptr_arg(tcg_env)) {
25
remove_mem_copy_all(ctx);
26
- return false;
27
+ return true;
28
}
29
30
switch (op->opc) {
31
@@ -XXX,XX +XXX,XX @@ static bool fold_tcg_st(OptContext *ctx, TCGOp *op)
32
g_assert_not_reached();
33
}
34
remove_mem_copy_in(ctx, ofs, ofs + lm1);
35
- return false;
36
+ return true;
37
}
38
39
static bool fold_tcg_st_memcopy(OptContext *ctx, TCGOp *op)
40
@@ -XXX,XX +XXX,XX @@ static bool fold_tcg_st_memcopy(OptContext *ctx, TCGOp *op)
41
TCGType type;
42
43
if (op->args[1] != tcgv_ptr_arg(tcg_env)) {
44
- fold_tcg_st(ctx, op);
45
- return false;
46
+ return fold_tcg_st(ctx, op);
47
}
48
49
src = arg_temp(op->args[0]);
50
@@ -XXX,XX +XXX,XX @@ static bool fold_tcg_st_memcopy(OptContext *ctx, TCGOp *op)
51
last = ofs + tcg_type_size(type) - 1;
52
remove_mem_copy_in(ctx, ofs, last);
53
record_mem_copy(ctx, type, src, ofs, last);
54
- return false;
55
+ return true;
56
}
57
58
static bool fold_xor(OptContext *ctx, TCGOp *op)
59
--
60
2.43.0
diff view generated by jsdifflib
New patch
[PULL 35/72] tcg/optimize: Use finish_folding in fold_remainder
1
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
2
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
3
---
4
tcg/optimize.c | 2 +-
5
1 file changed, 1 insertion(+), 1 deletion(-)
1
6
7
diff --git a/tcg/optimize.c b/tcg/optimize.c
8
index XXXXXXX..XXXXXXX 100644
9
--- a/tcg/optimize.c
10
+++ b/tcg/optimize.c
11
@@ -XXX,XX +XXX,XX @@ static bool fold_remainder(OptContext *ctx, TCGOp *op)
12
fold_xx_to_i(ctx, op, 0)) {
13
return true;
14
}
15
- return false;
16
+ return finish_folding(ctx, op);
17
}
18
19
static bool fold_setcond_zmask(OptContext *ctx, TCGOp *op, bool neg)
20
--
21
2.43.0
diff view generated by jsdifflib
[PATCH 24/27] accel/tcg: move CF_CLUSTER calculation to curr_cflags
[PULL 36/72] tcg/optimize: Distinguish simplification in fold_setcond_zmask
1
From: Alex Bennée <alex.bennee@linaro.org>
1
Change return from bool to int; distinguish between
2
complete folding, simplification, and no change.
2
3
3
There is nothing special about this compile flag that doesn't mean we
4
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
4
can't just compute it with curr_cflags() which we should be using when
5
building a new set.
6
7
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
8
Message-Id: <20210224165811.11567-3-alex.bennee@linaro.org>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
---
6
---
11
include/exec/exec-all.h | 8 +++++---
7
tcg/optimize.c | 22 ++++++++++++++--------
12
include/exec/tb-lookup.h | 3 ---
8
1 file changed, 14 insertions(+), 8 deletions(-)
13
accel/tcg/cpu-exec.c | 9 ++++-----
14
accel/tcg/tcg-runtime.c | 2 +-
15
accel/tcg/translate-all.c | 6 +++---
16
softmmu/physmem.c | 2 +-
17
6 files changed, 14 insertions(+), 16 deletions(-)
18
9
19
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
10
diff --git a/tcg/optimize.c b/tcg/optimize.c
20
index XXXXXXX..XXXXXXX 100644
11
index XXXXXXX..XXXXXXX 100644
21
--- a/include/exec/exec-all.h
12
--- a/tcg/optimize.c
22
+++ b/include/exec/exec-all.h
13
+++ b/tcg/optimize.c
23
@@ -XXX,XX +XXX,XX @@ static inline uint32_t tb_cflags(const TranslationBlock *tb)
14
@@ -XXX,XX +XXX,XX @@ static bool fold_remainder(OptContext *ctx, TCGOp *op)
15
return finish_folding(ctx, op);
24
}
16
}
25
17
26
/* current cflags for hashing/comparison */
18
-static bool fold_setcond_zmask(OptContext *ctx, TCGOp *op, bool neg)
27
-static inline uint32_t curr_cflags(void)
19
+/* Return 1 if finished, -1 if simplified, 0 if unchanged. */
28
+static inline uint32_t curr_cflags(CPUState *cpu)
20
+static int fold_setcond_zmask(OptContext *ctx, TCGOp *op, bool neg)
29
{
21
{
30
- return (parallel_cpus ? CF_PARALLEL : 0)
22
uint64_t a_zmask, b_val;
31
- | (icount_enabled() ? CF_USE_ICOUNT : 0);
23
TCGCond cond;
32
+ uint32_t cflags = deposit32(0, CF_CLUSTER_SHIFT, 8, cpu->cluster_index);
24
@@ -XXX,XX +XXX,XX @@ static bool fold_setcond_zmask(OptContext *ctx, TCGOp *op, bool neg)
33
+ cflags |= parallel_cpus ? CF_PARALLEL : 0;
25
op->opc = xor_opc;
34
+ cflags |= icount_enabled() ? CF_USE_ICOUNT : 0;
26
op->args[2] = arg_new_constant(ctx, 1);
35
+ return cflags;
27
}
28
- return false;
29
+ return -1;
30
}
31
}
32
-
33
- return false;
34
+ return 0;
36
}
35
}
37
36
38
/* TranslationBlock invalidate API */
37
static void fold_setcond_tst_pow2(OptContext *ctx, TCGOp *op, bool neg)
39
diff --git a/include/exec/tb-lookup.h b/include/exec/tb-lookup.h
38
@@ -XXX,XX +XXX,XX @@ static bool fold_setcond(OptContext *ctx, TCGOp *op)
40
index XXXXXXX..XXXXXXX 100644
39
return tcg_opt_gen_movi(ctx, op, op->args[0], i);
41
--- a/include/exec/tb-lookup.h
42
+++ b/include/exec/tb-lookup.h
43
@@ -XXX,XX +XXX,XX @@ static inline TranslationBlock * tb_lookup(CPUState *cpu,
44
hash = tb_jmp_cache_hash_func(pc);
45
tb = qatomic_rcu_read(&cpu->tb_jmp_cache[hash]);
46
47
- cf_mask &= ~CF_CLUSTER_MASK;
48
- cf_mask |= cpu->cluster_index << CF_CLUSTER_SHIFT;
49
-
50
if (likely(tb &&
51
tb->pc == pc &&
52
tb->cs_base == cs_base &&
53
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
54
index XXXXXXX..XXXXXXX 100644
55
--- a/accel/tcg/cpu-exec.c
56
+++ b/accel/tcg/cpu-exec.c
57
@@ -XXX,XX +XXX,XX @@ void cpu_exec_step_atomic(CPUState *cpu)
58
TranslationBlock *tb;
59
target_ulong cs_base, pc;
60
uint32_t flags;
61
- uint32_t cflags = 1;
62
- uint32_t cf_mask = cflags & CF_HASH_MASK;
63
+ uint32_t cflags = (curr_cflags(cpu) & ~CF_PARALLEL) | 1;
64
int tb_exit;
65
66
if (sigsetjmp(cpu->jmp_env, 0) == 0) {
67
@@ -XXX,XX +XXX,XX @@ void cpu_exec_step_atomic(CPUState *cpu)
68
cpu->running = true;
69
70
cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags);
71
- tb = tb_lookup(cpu, pc, cs_base, flags, cf_mask);
72
+ tb = tb_lookup(cpu, pc, cs_base, flags, cflags);
73
74
if (tb == NULL) {
75
mmap_lock();
76
@@ -XXX,XX +XXX,XX @@ static inline bool cpu_handle_exception(CPUState *cpu, int *ret)
77
if (replay_has_exception()
78
&& cpu_neg(cpu)->icount_decr.u16.low + cpu->icount_extra == 0) {
79
/* Execute just one insn to trigger exception pending in the log */
80
- cpu->cflags_next_tb = (curr_cflags() & ~CF_USE_ICOUNT) | 1;
81
+ cpu->cflags_next_tb = (curr_cflags(cpu) & ~CF_USE_ICOUNT) | 1;
82
}
83
#endif
84
return false;
85
@@ -XXX,XX +XXX,XX @@ int cpu_exec(CPUState *cpu)
86
have CF_INVALID set, -1 is a convenient invalid value that
87
does not require tcg headers for cpu_common_reset. */
88
if (cflags == -1) {
89
- cflags = curr_cflags();
90
+ cflags = curr_cflags(cpu);
91
} else {
92
cpu->cflags_next_tb = -1;
93
}
94
diff --git a/accel/tcg/tcg-runtime.c b/accel/tcg/tcg-runtime.c
95
index XXXXXXX..XXXXXXX 100644
96
--- a/accel/tcg/tcg-runtime.c
97
+++ b/accel/tcg/tcg-runtime.c
98
@@ -XXX,XX +XXX,XX @@ const void *HELPER(lookup_tb_ptr)(CPUArchState *env)
99
100
cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags);
101
102
- tb = tb_lookup(cpu, pc, cs_base, flags, curr_cflags());
103
+ tb = tb_lookup(cpu, pc, cs_base, flags, curr_cflags(cpu));
104
if (tb == NULL) {
105
return tcg_code_gen_epilogue;
106
}
40
}
107
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
41
108
index XXXXXXX..XXXXXXX 100644
42
- if (fold_setcond_zmask(ctx, op, false)) {
109
--- a/accel/tcg/translate-all.c
43
+ i = fold_setcond_zmask(ctx, op, false);
110
+++ b/accel/tcg/translate-all.c
44
+ if (i > 0) {
111
@@ -XXX,XX +XXX,XX @@ tb_invalidate_phys_page_range__locked(struct page_collection *pages,
112
if (current_tb_modified) {
113
page_collection_unlock(pages);
114
/* Force execution of one insn next time. */
115
- cpu->cflags_next_tb = 1 | curr_cflags();
116
+ cpu->cflags_next_tb = 1 | curr_cflags(cpu);
117
mmap_unlock();
118
cpu_loop_exit_noexc(cpu);
119
}
120
@@ -XXX,XX +XXX,XX @@ static bool tb_invalidate_phys_page(tb_page_addr_t addr, uintptr_t pc)
121
#ifdef TARGET_HAS_PRECISE_SMC
122
if (current_tb_modified) {
123
/* Force execution of one insn next time. */
124
- cpu->cflags_next_tb = 1 | curr_cflags();
125
+ cpu->cflags_next_tb = 1 | curr_cflags(cpu);
126
return true;
45
return true;
127
}
46
}
128
#endif
47
- fold_setcond_tst_pow2(ctx, op, false);
129
@@ -XXX,XX +XXX,XX @@ void cpu_io_recompile(CPUState *cpu, uintptr_t retaddr)
48
+ if (i == 0) {
130
* operations only (which execute after completion) so we don't
49
+ fold_setcond_tst_pow2(ctx, op, false);
131
* double instrument the instruction.
50
+ }
132
*/
51
133
- cpu->cflags_next_tb = curr_cflags() | CF_MEMI_ONLY | CF_LAST_IO | n;
52
ctx->z_mask = 1;
134
+ cpu->cflags_next_tb = curr_cflags(cpu) | CF_MEMI_ONLY | CF_LAST_IO | n;
53
return false;
135
54
@@ -XXX,XX +XXX,XX @@ static bool fold_negsetcond(OptContext *ctx, TCGOp *op)
136
qemu_log_mask_and_addr(CPU_LOG_EXEC, tb->pc,
55
return tcg_opt_gen_movi(ctx, op, op->args[0], -i);
137
"cpu_io_recompile: rewound execution of TB to "
56
}
138
diff --git a/softmmu/physmem.c b/softmmu/physmem.c
57
139
index XXXXXXX..XXXXXXX 100644
58
- if (fold_setcond_zmask(ctx, op, true)) {
140
--- a/softmmu/physmem.c
59
+ i = fold_setcond_zmask(ctx, op, true);
141
+++ b/softmmu/physmem.c
60
+ if (i > 0) {
142
@@ -XXX,XX +XXX,XX @@ void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr len,
61
return true;
143
cpu_loop_exit_restore(cpu, ra);
62
}
144
} else {
63
- fold_setcond_tst_pow2(ctx, op, true);
145
/* Force execution of one insn next time. */
64
+ if (i == 0) {
146
- cpu->cflags_next_tb = 1 | curr_cflags();
65
+ fold_setcond_tst_pow2(ctx, op, true);
147
+ cpu->cflags_next_tb = 1 | curr_cflags(cpu);
66
+ }
148
mmap_unlock();
67
149
if (ra) {
68
/* Value is {0,-1} so all bits are repetitions of the sign. */
150
cpu_restore_state(cpu, ra, true);
69
ctx->s_mask = -1;
151
--
70
--
152
2.25.1
71
2.43.0
153
154
diff view generated by jsdifflib
New patch
[PULL 37/72] tcg/optimize: Use fold_masks_z in fold_setcond
1
Avoid the use of the OptContext slots.
1
2
3
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
---
6
tcg/optimize.c | 3 +--
7
1 file changed, 1 insertion(+), 2 deletions(-)
8
9
diff --git a/tcg/optimize.c b/tcg/optimize.c
10
index XXXXXXX..XXXXXXX 100644
11
--- a/tcg/optimize.c
12
+++ b/tcg/optimize.c
13
@@ -XXX,XX +XXX,XX @@ static bool fold_setcond(OptContext *ctx, TCGOp *op)
14
fold_setcond_tst_pow2(ctx, op, false);
15
}
16
17
- ctx->z_mask = 1;
18
- return false;
19
+ return fold_masks_z(ctx, op, 1);
20
}
21
22
static bool fold_negsetcond(OptContext *ctx, TCGOp *op)
23
--
24
2.43.0
diff view generated by jsdifflib
New patch
[PULL 38/72] tcg/optimize: Use fold_masks_s in fold_negsetcond
1
Avoid the use of the OptContext slots.
1
2
3
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
---
6
tcg/optimize.c | 3 +--
7
1 file changed, 1 insertion(+), 2 deletions(-)
8
9
diff --git a/tcg/optimize.c b/tcg/optimize.c
10
index XXXXXXX..XXXXXXX 100644
11
--- a/tcg/optimize.c
12
+++ b/tcg/optimize.c
13
@@ -XXX,XX +XXX,XX @@ static bool fold_negsetcond(OptContext *ctx, TCGOp *op)
14
}
15
16
/* Value is {0,-1} so all bits are repetitions of the sign. */
17
- ctx->s_mask = -1;
18
- return false;
19
+ return fold_masks_s(ctx, op, -1);
20
}
21
22
static bool fold_setcond2(OptContext *ctx, TCGOp *op)
23
--
24
2.43.0
diff view generated by jsdifflib
New patch
[PULL 39/72] tcg/optimize: Use fold_masks_z in fold_setcond2
1
Avoid the use of the OptContext slots.
1
2
3
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
---
6
tcg/optimize.c | 3 +--
7
1 file changed, 1 insertion(+), 2 deletions(-)
8
9
diff --git a/tcg/optimize.c b/tcg/optimize.c
10
index XXXXXXX..XXXXXXX 100644
11
--- a/tcg/optimize.c
12
+++ b/tcg/optimize.c
13
@@ -XXX,XX +XXX,XX @@ static bool fold_setcond2(OptContext *ctx, TCGOp *op)
14
return fold_setcond(ctx, op);
15
}
16
17
- ctx->z_mask = 1;
18
- return false;
19
+ return fold_masks_z(ctx, op, 1);
20
21
do_setcond_const:
22
return tcg_opt_gen_movi(ctx, op, op->args[0], i);
23
--
24
2.43.0
diff view generated by jsdifflib
New patch
[PULL 40/72] tcg/optimize: Use finish_folding in fold_cmp_vec
1
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
2
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
3
---
4
tcg/optimize.c | 2 +-
5
1 file changed, 1 insertion(+), 1 deletion(-)
1
6
7
diff --git a/tcg/optimize.c b/tcg/optimize.c
8
index XXXXXXX..XXXXXXX 100644
9
--- a/tcg/optimize.c
10
+++ b/tcg/optimize.c
11
@@ -XXX,XX +XXX,XX @@ static bool fold_cmp_vec(OptContext *ctx, TCGOp *op)
12
if (swap_commutative(NO_DEST, &op->args[1], &op->args[2])) {
13
op->args[3] = tcg_swap_cond(op->args[3]);
14
}
15
- return false;
16
+ return finish_folding(ctx, op);
17
}
18
19
static bool fold_cmpsel_vec(OptContext *ctx, TCGOp *op)
20
--
21
2.43.0
diff view generated by jsdifflib
New patch
[PULL 41/72] tcg/optimize: Use finish_folding in fold_cmpsel_vec
1
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
2
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
3
---
4
tcg/optimize.c | 2 +-
5
1 file changed, 1 insertion(+), 1 deletion(-)
1
6
7
diff --git a/tcg/optimize.c b/tcg/optimize.c
8
index XXXXXXX..XXXXXXX 100644
9
--- a/tcg/optimize.c
10
+++ b/tcg/optimize.c
11
@@ -XXX,XX +XXX,XX @@ static bool fold_cmpsel_vec(OptContext *ctx, TCGOp *op)
12
if (swap_commutative(op->args[0], &op->args[4], &op->args[3])) {
13
op->args[5] = tcg_invert_cond(op->args[5]);
14
}
15
- return false;
16
+ return finish_folding(ctx, op);
17
}
18
19
static bool fold_sextract(OptContext *ctx, TCGOp *op)
20
--
21
2.43.0
diff view generated by jsdifflib
New patch
[PULL 42/72] tcg/optimize: Use fold_masks_zs in fold_sextract
1
Avoid the use of the OptContext slots. Find TempOptInfo once.
1
2
3
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
---
6
tcg/optimize.c | 24 +++++++++---------------
7
1 file changed, 9 insertions(+), 15 deletions(-)
8
9
diff --git a/tcg/optimize.c b/tcg/optimize.c
10
index XXXXXXX..XXXXXXX 100644
11
--- a/tcg/optimize.c
12
+++ b/tcg/optimize.c
13
@@ -XXX,XX +XXX,XX @@ static bool fold_cmpsel_vec(OptContext *ctx, TCGOp *op)
14
static bool fold_sextract(OptContext *ctx, TCGOp *op)
15
{
16
uint64_t z_mask, s_mask, s_mask_old;
17
+ TempOptInfo *t1 = arg_info(op->args[1]);
18
int pos = op->args[2];
19
int len = op->args[3];
20
21
- if (arg_is_const(op->args[1])) {
22
- uint64_t t;
23
-
24
- t = arg_info(op->args[1])->val;
25
- t = sextract64(t, pos, len);
26
- return tcg_opt_gen_movi(ctx, op, op->args[0], t);
27
+ if (ti_is_const(t1)) {
28
+ return tcg_opt_gen_movi(ctx, op, op->args[0],
29
+ sextract64(ti_const_val(t1), pos, len));
30
}
31
32
- z_mask = arg_info(op->args[1])->z_mask;
33
- z_mask = sextract64(z_mask, pos, len);
34
- ctx->z_mask = z_mask;
35
-
36
- s_mask_old = arg_info(op->args[1])->s_mask;
37
- s_mask = sextract64(s_mask_old, pos, len);
38
- s_mask |= MAKE_64BIT_MASK(len, 64 - len);
39
- ctx->s_mask = s_mask;
40
+ s_mask_old = t1->s_mask;
41
+ s_mask = s_mask_old >> pos;
42
+ s_mask |= -1ull << (len - 1);
43
44
if (0 && pos == 0 && fold_affected_mask(ctx, op, s_mask & ~s_mask_old)) {
45
return true;
46
}
47
48
- return fold_masks(ctx, op);
49
+ z_mask = sextract64(t1->z_mask, pos, len);
50
+ return fold_masks_zs(ctx, op, z_mask, s_mask);
51
}
52
53
static bool fold_shift(OptContext *ctx, TCGOp *op)
54
--
55
2.43.0
diff view generated by jsdifflib
New patch
[PULL 43/72] tcg/optimize: Use fold_masks_zs, fold_masks_s in fold_shift
1
Avoid the use of the OptContext slots. Find TempOptInfo once.
1
2
3
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
---
6
tcg/optimize.c | 27 ++++++++++++++-------------
7
1 file changed, 14 insertions(+), 13 deletions(-)
8
9
diff --git a/tcg/optimize.c b/tcg/optimize.c
10
index XXXXXXX..XXXXXXX 100644
11
--- a/tcg/optimize.c
12
+++ b/tcg/optimize.c
13
@@ -XXX,XX +XXX,XX @@ static bool fold_sextract(OptContext *ctx, TCGOp *op)
14
static bool fold_shift(OptContext *ctx, TCGOp *op)
15
{
16
uint64_t s_mask, z_mask, sign;
17
+ TempOptInfo *t1, *t2;
18
19
if (fold_const2(ctx, op) ||
20
fold_ix_to_i(ctx, op, 0) ||
21
@@ -XXX,XX +XXX,XX @@ static bool fold_shift(OptContext *ctx, TCGOp *op)
22
return true;
23
}
24
25
- s_mask = arg_info(op->args[1])->s_mask;
26
- z_mask = arg_info(op->args[1])->z_mask;
27
+ t1 = arg_info(op->args[1]);
28
+ t2 = arg_info(op->args[2]);
29
+ s_mask = t1->s_mask;
30
+ z_mask = t1->z_mask;
31
32
- if (arg_is_const(op->args[2])) {
33
- int sh = arg_info(op->args[2])->val;
34
-
35
- ctx->z_mask = do_constant_folding(op->opc, ctx->type, z_mask, sh);
36
+ if (ti_is_const(t2)) {
37
+ int sh = ti_const_val(t2);
38
39
+ z_mask = do_constant_folding(op->opc, ctx->type, z_mask, sh);
40
s_mask = do_constant_folding(op->opc, ctx->type, s_mask, sh);
41
42
- return fold_masks(ctx, op);
43
+ return fold_masks_zs(ctx, op, z_mask, s_mask);
44
}
45
46
switch (op->opc) {
47
@@ -XXX,XX +XXX,XX @@ static bool fold_shift(OptContext *ctx, TCGOp *op)
48
* Arithmetic right shift will not reduce the number of
49
* input sign repetitions.
50
*/
51
- ctx->s_mask = s_mask;
52
- break;
53
+ return fold_masks_s(ctx, op, s_mask);
54
CASE_OP_32_64(shr):
55
/*
56
* If the sign bit is known zero, then logical right shift
57
- * will not reduced the number of input sign repetitions.
58
+ * will not reduce the number of input sign repetitions.
59
*/
60
- sign = (s_mask & -s_mask) >> 1;
61
+ sign = -s_mask;
62
if (sign && !(z_mask & sign)) {
63
- ctx->s_mask = s_mask;
64
+ return fold_masks_s(ctx, op, s_mask);
65
}
66
break;
67
default:
68
break;
69
}
70
71
- return false;
72
+ return finish_folding(ctx, op);
73
}
74
75
static bool fold_sub_to_neg(OptContext *ctx, TCGOp *op)
76
--
77
2.43.0
diff view generated by jsdifflib
[PATCH 08/27] tcg/tci: Merge identical cases in generation (exchange opcodes)
[PULL 44/72] tcg/optimize: Simplify sign bit test in fold_shift
1
Use CASE_32_64 and CASE_64 to reduce ifdefs and merge
1
Merge the two conditions, sign != 0 && !(z_mask & sign),
2
cases that are identical between 32-bit and 64-bit hosts.
2
by testing ~z_mask & sign. If sign == 0, the logical and
3
will produce false.
3
4
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
5
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
6
Message-Id: <20210217202036.1724901-5-richard.henderson@linaro.org>
7
[PMD: Split patch as 2/5]
8
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
Message-Id: <20210218232840.1760806-3-f4bug@amsat.org>
10
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
11
---
7
---
12
tcg/tci/tcg-target.c.inc | 35 ++++++++++++++---------------------
8
tcg/optimize.c | 5 ++---
13
1 file changed, 14 insertions(+), 21 deletions(-)
9
1 file changed, 2 insertions(+), 3 deletions(-)
14
10
15
diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
11
diff --git a/tcg/optimize.c b/tcg/optimize.c
16
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
17
--- a/tcg/tci/tcg-target.c.inc
13
--- a/tcg/optimize.c
18
+++ b/tcg/tci/tcg-target.c.inc
14
+++ b/tcg/optimize.c
19
@@ -XXX,XX +XXX,XX @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
15
@@ -XXX,XX +XXX,XX @@ static bool fold_sextract(OptContext *ctx, TCGOp *op)
20
tcg_out8(s, args[2]); /* condition */
16
21
tci_out_label(s, arg_label(args[3]));
17
static bool fold_shift(OptContext *ctx, TCGOp *op)
22
break;
18
{
23
- case INDEX_op_bswap16_i64: /* Optional (TCG_TARGET_HAS_bswap16_i64). */
19
- uint64_t s_mask, z_mask, sign;
24
- case INDEX_op_bswap32_i64: /* Optional (TCG_TARGET_HAS_bswap32_i64). */
20
+ uint64_t s_mask, z_mask;
25
- case INDEX_op_bswap64_i64: /* Optional (TCG_TARGET_HAS_bswap64_i64). */
21
TempOptInfo *t1, *t2;
26
- case INDEX_op_not_i64: /* Optional (TCG_TARGET_HAS_not_i64). */
22
27
- case INDEX_op_neg_i64: /* Optional (TCG_TARGET_HAS_neg_i64). */
23
if (fold_const2(ctx, op) ||
28
- case INDEX_op_ext8s_i64: /* Optional (TCG_TARGET_HAS_ext8s_i64). */
24
@@ -XXX,XX +XXX,XX @@ static bool fold_shift(OptContext *ctx, TCGOp *op)
29
- case INDEX_op_ext8u_i64: /* Optional (TCG_TARGET_HAS_ext8u_i64). */
25
* If the sign bit is known zero, then logical right shift
30
- case INDEX_op_ext16s_i64: /* Optional (TCG_TARGET_HAS_ext16s_i64). */
26
* will not reduce the number of input sign repetitions.
31
- case INDEX_op_ext16u_i64: /* Optional (TCG_TARGET_HAS_ext16u_i64). */
27
*/
32
- case INDEX_op_ext32s_i64: /* Optional (TCG_TARGET_HAS_ext32s_i64). */
28
- sign = -s_mask;
33
- case INDEX_op_ext32u_i64: /* Optional (TCG_TARGET_HAS_ext32u_i64). */
29
- if (sign && !(z_mask & sign)) {
34
- case INDEX_op_ext_i32_i64:
30
+ if (~z_mask & -s_mask) {
35
- case INDEX_op_extu_i32_i64:
31
return fold_masks_s(ctx, op, s_mask);
36
#endif /* TCG_TARGET_REG_BITS == 64 */
32
}
37
- case INDEX_op_neg_i32: /* Optional (TCG_TARGET_HAS_neg_i32). */
38
- case INDEX_op_not_i32: /* Optional (TCG_TARGET_HAS_not_i32). */
39
- case INDEX_op_ext8s_i32: /* Optional (TCG_TARGET_HAS_ext8s_i32). */
40
- case INDEX_op_ext16s_i32: /* Optional (TCG_TARGET_HAS_ext16s_i32). */
41
- case INDEX_op_ext8u_i32: /* Optional (TCG_TARGET_HAS_ext8u_i32). */
42
- case INDEX_op_ext16u_i32: /* Optional (TCG_TARGET_HAS_ext16u_i32). */
43
- case INDEX_op_bswap16_i32: /* Optional (TCG_TARGET_HAS_bswap16_i32). */
44
- case INDEX_op_bswap32_i32: /* Optional (TCG_TARGET_HAS_bswap32_i32). */
45
+
46
+ CASE_32_64(neg) /* Optional (TCG_TARGET_HAS_neg_*). */
47
+ CASE_32_64(not) /* Optional (TCG_TARGET_HAS_not_*). */
48
+ CASE_32_64(ext8s) /* Optional (TCG_TARGET_HAS_ext8s_*). */
49
+ CASE_32_64(ext8u) /* Optional (TCG_TARGET_HAS_ext8u_*). */
50
+ CASE_32_64(ext16s) /* Optional (TCG_TARGET_HAS_ext16s_*). */
51
+ CASE_32_64(ext16u) /* Optional (TCG_TARGET_HAS_ext16u_*). */
52
+ CASE_64(ext32s) /* Optional (TCG_TARGET_HAS_ext32s_i64). */
53
+ CASE_64(ext32u) /* Optional (TCG_TARGET_HAS_ext32u_i64). */
54
+ CASE_64(ext_i32)
55
+ CASE_64(extu_i32)
56
+ CASE_32_64(bswap16) /* Optional (TCG_TARGET_HAS_bswap16_*). */
57
+ CASE_32_64(bswap32) /* Optional (TCG_TARGET_HAS_bswap32_*). */
58
+ CASE_64(bswap64) /* Optional (TCG_TARGET_HAS_bswap64_i64). */
59
tcg_out_r(s, args[0]);
60
tcg_out_r(s, args[1]);
61
break;
33
break;
62
--
34
--
63
2.25.1
35
2.43.0
64
65
diff view generated by jsdifflib
[PATCH 15/27] tcg/tci: Remove tci_read_r16s
[PULL 45/72] tcg/optimize: Use finish_folding in fold_sub, fold_sub_vec
1
Use explicit casts for ext16s opcodes.
1
Duplicate fold_sub_vec into fold_sub instead of calling it,
2
now that fold_sub_vec always returns true.
2
3
3
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
4
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
---
6
---
6
tcg/tci.c | 26 ++++----------------------
7
tcg/optimize.c | 9 ++++++---
7
1 file changed, 4 insertions(+), 22 deletions(-)
8
1 file changed, 6 insertions(+), 3 deletions(-)
8
9
9
diff --git a/tcg/tci.c b/tcg/tci.c
10
diff --git a/tcg/optimize.c b/tcg/optimize.c
10
index XXXXXXX..XXXXXXX 100644
11
index XXXXXXX..XXXXXXX 100644
11
--- a/tcg/tci.c
12
--- a/tcg/optimize.c
12
+++ b/tcg/tci.c
13
+++ b/tcg/optimize.c
13
@@ -XXX,XX +XXX,XX @@ static tcg_target_ulong tci_read_reg(const tcg_target_ulong *regs, TCGReg index)
14
@@ -XXX,XX +XXX,XX @@ static bool fold_sub_vec(OptContext *ctx, TCGOp *op)
14
return regs[index];
15
fold_sub_to_neg(ctx, op)) {
16
return true;
17
}
18
- return false;
19
+ return finish_folding(ctx, op);
15
}
20
}
16
21
17
-#if TCG_TARGET_HAS_ext16s_i32 || TCG_TARGET_HAS_ext16s_i64
22
static bool fold_sub(OptContext *ctx, TCGOp *op)
18
-static int16_t tci_read_reg16s(const tcg_target_ulong *regs, TCGReg index)
19
-{
20
- return (int16_t)tci_read_reg(regs, index);
21
-}
22
-#endif
23
-
24
#if TCG_TARGET_REG_BITS == 64
25
static int32_t tci_read_reg32s(const tcg_target_ulong *regs, TCGReg index)
26
{
23
{
27
@@ -XXX,XX +XXX,XX @@ tci_read_r(const tcg_target_ulong *regs, const uint8_t **tb_ptr)
24
- if (fold_const2(ctx, op) || fold_sub_vec(ctx, op)) {
28
return value;
25
+ if (fold_const2(ctx, op) ||
26
+ fold_xx_to_i(ctx, op, 0) ||
27
+ fold_xi_to_x(ctx, op, 0) ||
28
+ fold_sub_to_neg(ctx, op)) {
29
return true;
30
}
31
32
@@ -XXX,XX +XXX,XX @@ static bool fold_sub(OptContext *ctx, TCGOp *op)
33
? INDEX_op_add_i32 : INDEX_op_add_i64);
34
op->args[2] = arg_new_constant(ctx, -val);
35
}
36
- return false;
37
+ return finish_folding(ctx, op);
29
}
38
}
30
39
31
-#if TCG_TARGET_HAS_ext16s_i32 || TCG_TARGET_HAS_ext16s_i64
40
static bool fold_sub2(OptContext *ctx, TCGOp *op)
32
-/* Read indexed register (16 bit signed) from bytecode. */
33
-static int16_t tci_read_r16s(const tcg_target_ulong *regs,
34
- const uint8_t **tb_ptr)
35
-{
36
- int16_t value = tci_read_reg16s(regs, **tb_ptr);
37
- *tb_ptr += 1;
38
- return value;
39
-}
40
-#endif
41
-
42
/* Read indexed register (32 bit) from bytecode. */
43
static uint32_t tci_read_r32(const tcg_target_ulong *regs,
44
const uint8_t **tb_ptr)
45
@@ -XXX,XX +XXX,XX @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
46
#if TCG_TARGET_HAS_ext16s_i32
47
case INDEX_op_ext16s_i32:
48
t0 = *tb_ptr++;
49
- t1 = tci_read_r16s(regs, &tb_ptr);
50
- tci_write_reg(regs, t0, t1);
51
+ t1 = tci_read_r(regs, &tb_ptr);
52
+ tci_write_reg(regs, t0, (int16_t)t1);
53
break;
54
#endif
55
#if TCG_TARGET_HAS_ext8u_i32
56
@@ -XXX,XX +XXX,XX @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
57
#if TCG_TARGET_HAS_ext16s_i64
58
case INDEX_op_ext16s_i64:
59
t0 = *tb_ptr++;
60
- t1 = tci_read_r16s(regs, &tb_ptr);
61
- tci_write_reg(regs, t0, t1);
62
+ t1 = tci_read_r(regs, &tb_ptr);
63
+ tci_write_reg(regs, t0, (int16_t)t1);
64
break;
65
#endif
66
#if TCG_TARGET_HAS_ext16u_i64
67
--
41
--
68
2.25.1
42
2.43.0
69
70
diff view generated by jsdifflib
[PATCH 01/27] tcg/aarch64: Fix constant subtraction in tcg_out_addsub2
[PULL 46/72] tcg/optimize: Use fold_masks_zs in fold_tcg_ld
1
An hppa guest executing
1
Avoid the use of the OptContext slots.
2
2
3
0x000000000000e05c: ldil L%10000,r4
3
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
4
0x000000000000e060: ldo 0(r4),r4
5
0x000000000000e064: sub r3,r4,sp
6
7
produces
8
9
---- 000000000000e064 000000000000e068
10
sub2_i32 tmp0,tmp4,r3,$0x1,$0x10000,$0x0
11
12
after folding and constant propagation. Then we hit
13
14
tcg-target.c.inc:640: tcg_out_insn_3401: Assertion `aimm <= 0xfff' failed.
15
16
because aimm is in fact -16, but unsigned.
17
18
The ((bl < 0) ^ sub) condition which negates bl is incorrect and will
19
always lead to this abort. If the constant is positive, sub will make
20
it negative; if the constant is negative, sub will keep it negative.
21
22
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
23
---
5
---
24
tcg/aarch64/tcg-target.c.inc | 16 +++++++++-------
6
tcg/optimize.c | 16 +++++++++-------
25
1 file changed, 9 insertions(+), 7 deletions(-)
7
1 file changed, 9 insertions(+), 7 deletions(-)
26
8
27
diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc
9
diff --git a/tcg/optimize.c b/tcg/optimize.c
28
index XXXXXXX..XXXXXXX 100644
10
index XXXXXXX..XXXXXXX 100644
29
--- a/tcg/aarch64/tcg-target.c.inc
11
--- a/tcg/optimize.c
30
+++ b/tcg/aarch64/tcg-target.c.inc
12
+++ b/tcg/optimize.c
31
@@ -XXX,XX +XXX,XX @@ static void tcg_out_addsubi(TCGContext *s, int ext, TCGReg rd,
13
@@ -XXX,XX +XXX,XX @@ static bool fold_sub2(OptContext *ctx, TCGOp *op)
14
15
static bool fold_tcg_ld(OptContext *ctx, TCGOp *op)
16
{
17
+ uint64_t z_mask = -1, s_mask = 0;
18
+
19
/* We can't do any folding with a load, but we can record bits. */
20
switch (op->opc) {
21
CASE_OP_32_64(ld8s):
22
- ctx->s_mask = MAKE_64BIT_MASK(8, 56);
23
+ s_mask = INT8_MIN;
24
break;
25
CASE_OP_32_64(ld8u):
26
- ctx->z_mask = MAKE_64BIT_MASK(0, 8);
27
+ z_mask = MAKE_64BIT_MASK(0, 8);
28
break;
29
CASE_OP_32_64(ld16s):
30
- ctx->s_mask = MAKE_64BIT_MASK(16, 48);
31
+ s_mask = INT16_MIN;
32
break;
33
CASE_OP_32_64(ld16u):
34
- ctx->z_mask = MAKE_64BIT_MASK(0, 16);
35
+ z_mask = MAKE_64BIT_MASK(0, 16);
36
break;
37
case INDEX_op_ld32s_i64:
38
- ctx->s_mask = MAKE_64BIT_MASK(32, 32);
39
+ s_mask = INT32_MIN;
40
break;
41
case INDEX_op_ld32u_i64:
42
- ctx->z_mask = MAKE_64BIT_MASK(0, 32);
43
+ z_mask = MAKE_64BIT_MASK(0, 32);
44
break;
45
default:
46
g_assert_not_reached();
32
}
47
}
48
- return false;
49
+ return fold_masks_zs(ctx, op, z_mask, s_mask);
33
}
50
}
34
51
35
-static inline void tcg_out_addsub2(TCGContext *s, TCGType ext, TCGReg rl,
52
static bool fold_tcg_ld_memcopy(OptContext *ctx, TCGOp *op)
36
- TCGReg rh, TCGReg al, TCGReg ah,
37
- tcg_target_long bl, tcg_target_long bh,
38
- bool const_bl, bool const_bh, bool sub)
39
+static void tcg_out_addsub2(TCGContext *s, TCGType ext, TCGReg rl,
40
+ TCGReg rh, TCGReg al, TCGReg ah,
41
+ tcg_target_long bl, tcg_target_long bh,
42
+ bool const_bl, bool const_bh, bool sub)
43
{
44
TCGReg orig_rl = rl;
45
AArch64Insn insn;
46
@@ -XXX,XX +XXX,XX @@ static inline void tcg_out_addsub2(TCGContext *s, TCGType ext, TCGReg rl,
47
}
48
49
if (const_bl) {
50
- insn = I3401_ADDSI;
51
- if ((bl < 0) ^ sub) {
52
- insn = I3401_SUBSI;
53
+ if (bl < 0) {
54
bl = -bl;
55
+ insn = sub ? I3401_ADDSI : I3401_SUBSI;
56
+ } else {
57
+ insn = sub ? I3401_SUBSI : I3401_ADDSI;
58
}
59
+
60
if (unlikely(al == TCG_REG_XZR)) {
61
/* ??? We want to allow al to be zero for the benefit of
62
negation via subtraction. However, that leaves open the
63
--
53
--
64
2.25.1
54
2.43.0
65
66
diff view generated by jsdifflib
New patch
[PULL 47/72] tcg/optimize: Use finish_folding in fold_tcg_ld_memcopy
1
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
2
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
3
---
4
tcg/optimize.c | 2 +-
5
1 file changed, 1 insertion(+), 1 deletion(-)
1
6
7
diff --git a/tcg/optimize.c b/tcg/optimize.c
8
index XXXXXXX..XXXXXXX 100644
9
--- a/tcg/optimize.c
10
+++ b/tcg/optimize.c
11
@@ -XXX,XX +XXX,XX @@ static bool fold_tcg_ld_memcopy(OptContext *ctx, TCGOp *op)
12
TCGType type;
13
14
if (op->args[1] != tcgv_ptr_arg(tcg_env)) {
15
- return false;
16
+ return finish_folding(ctx, op);
17
}
18
19
type = ctx->type;
20
--
21
2.43.0
diff view generated by jsdifflib
[PATCH 16/27] tcg/tci: Remove tci_read_r32
[PULL 48/72] tcg/optimize: Use fold_masks_zs in fold_xor
1
Use explicit casts for ext32u opcodes, and allow truncation
1
Avoid the use of the OptContext slots. Find TempOptInfo once.
2
to happen for other users.
2
Remove fold_masks as the function becomes unused.
3
3
4
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
4
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
---
6
---
7
tcg/tci.c | 122 ++++++++++++++++++++++++------------------------------
7
tcg/optimize.c | 18 ++++++++----------
8
1 file changed, 54 insertions(+), 68 deletions(-)
8
1 file changed, 8 insertions(+), 10 deletions(-)
9
9
10
diff --git a/tcg/tci.c b/tcg/tci.c
10
diff --git a/tcg/optimize.c b/tcg/optimize.c
11
index XXXXXXX..XXXXXXX 100644
11
index XXXXXXX..XXXXXXX 100644
12
--- a/tcg/tci.c
12
--- a/tcg/optimize.c
13
+++ b/tcg/tci.c
13
+++ b/tcg/optimize.c
14
@@ -XXX,XX +XXX,XX @@ static int32_t tci_read_reg32s(const tcg_target_ulong *regs, TCGReg index)
14
@@ -XXX,XX +XXX,XX @@ static bool fold_masks_s(OptContext *ctx, TCGOp *op, uint64_t s_mask)
15
return fold_masks_zs(ctx, op, -1, s_mask);
15
}
16
}
16
#endif
17
17
18
-static bool fold_masks(OptContext *ctx, TCGOp *op)
18
-static uint32_t tci_read_reg32(const tcg_target_ulong *regs, TCGReg index)
19
-{
19
-{
20
- return (uint32_t)tci_read_reg(regs, index);
20
- return fold_masks_zs(ctx, op, ctx->z_mask, ctx->s_mask);
21
-}
21
-}
22
-
22
-
23
#if TCG_TARGET_REG_BITS == 64
23
/*
24
static uint64_t tci_read_reg64(const tcg_target_ulong *regs, TCGReg index)
24
* An "affected" mask bit is 0 if and only if the result is identical
25
* to the first input. Thus if the entire mask is 0, the operation
26
@@ -XXX,XX +XXX,XX @@ static bool fold_tcg_st_memcopy(OptContext *ctx, TCGOp *op)
27
28
static bool fold_xor(OptContext *ctx, TCGOp *op)
25
{
29
{
26
@@ -XXX,XX +XXX,XX @@ tci_read_r(const tcg_target_ulong *regs, const uint8_t **tb_ptr)
30
+ uint64_t z_mask, s_mask;
27
return value;
31
+ TempOptInfo *t1, *t2;
32
+
33
if (fold_const2_commutative(ctx, op) ||
34
fold_xx_to_i(ctx, op, 0) ||
35
fold_xi_to_x(ctx, op, 0) ||
36
@@ -XXX,XX +XXX,XX @@ static bool fold_xor(OptContext *ctx, TCGOp *op)
37
return true;
38
}
39
40
- ctx->z_mask = arg_info(op->args[1])->z_mask
41
- | arg_info(op->args[2])->z_mask;
42
- ctx->s_mask = arg_info(op->args[1])->s_mask
43
- & arg_info(op->args[2])->s_mask;
44
- return fold_masks(ctx, op);
45
+ t1 = arg_info(op->args[1]);
46
+ t2 = arg_info(op->args[2]);
47
+ z_mask = t1->z_mask | t2->z_mask;
48
+ s_mask = t1->s_mask & t2->s_mask;
49
+ return fold_masks_zs(ctx, op, z_mask, s_mask);
28
}
50
}
29
51
30
-/* Read indexed register (32 bit) from bytecode. */
52
static bool fold_bitsel_vec(OptContext *ctx, TCGOp *op)
31
-static uint32_t tci_read_r32(const tcg_target_ulong *regs,
32
- const uint8_t **tb_ptr)
33
-{
34
- uint32_t value = tci_read_reg32(regs, **tb_ptr);
35
- *tb_ptr += 1;
36
- return value;
37
-}
38
-
39
#if TCG_TARGET_REG_BITS == 32
40
/* Read two indexed registers (2 * 32 bit) from bytecode. */
41
static uint64_t tci_read_r64(const tcg_target_ulong *regs,
42
const uint8_t **tb_ptr)
43
{
44
- uint32_t low = tci_read_r32(regs, tb_ptr);
45
- return tci_uint64(tci_read_r32(regs, tb_ptr), low);
46
+ uint32_t low = tci_read_r(regs, tb_ptr);
47
+ return tci_uint64(tci_read_r(regs, tb_ptr), low);
48
}
49
#elif TCG_TARGET_REG_BITS == 64
50
/* Read indexed register (32 bit signed) from bytecode. */
51
@@ -XXX,XX +XXX,XX @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
52
continue;
53
case INDEX_op_setcond_i32:
54
t0 = *tb_ptr++;
55
- t1 = tci_read_r32(regs, &tb_ptr);
56
- t2 = tci_read_r32(regs, &tb_ptr);
57
+ t1 = tci_read_r(regs, &tb_ptr);
58
+ t2 = tci_read_r(regs, &tb_ptr);
59
condition = *tb_ptr++;
60
tci_write_reg(regs, t0, tci_compare32(t1, t2, condition));
61
break;
62
@@ -XXX,XX +XXX,XX @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
63
#endif
64
case INDEX_op_mov_i32:
65
t0 = *tb_ptr++;
66
- t1 = tci_read_r32(regs, &tb_ptr);
67
+ t1 = tci_read_r(regs, &tb_ptr);
68
tci_write_reg(regs, t0, t1);
69
break;
70
case INDEX_op_tci_movi_i32:
71
@@ -XXX,XX +XXX,XX @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
72
break;
73
case INDEX_op_st_i32:
74
CASE_64(st32)
75
- t0 = tci_read_r32(regs, &tb_ptr);
76
+ t0 = tci_read_r(regs, &tb_ptr);
77
t1 = tci_read_r(regs, &tb_ptr);
78
t2 = tci_read_s32(&tb_ptr);
79
*(uint32_t *)(t1 + t2) = t0;
80
@@ -XXX,XX +XXX,XX @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
81
82
case INDEX_op_add_i32:
83
t0 = *tb_ptr++;
84
- t1 = tci_read_r32(regs, &tb_ptr);
85
- t2 = tci_read_r32(regs, &tb_ptr);
86
+ t1 = tci_read_r(regs, &tb_ptr);
87
+ t2 = tci_read_r(regs, &tb_ptr);
88
tci_write_reg(regs, t0, t1 + t2);
89
break;
90
case INDEX_op_sub_i32:
91
t0 = *tb_ptr++;
92
- t1 = tci_read_r32(regs, &tb_ptr);
93
- t2 = tci_read_r32(regs, &tb_ptr);
94
+ t1 = tci_read_r(regs, &tb_ptr);
95
+ t2 = tci_read_r(regs, &tb_ptr);
96
tci_write_reg(regs, t0, t1 - t2);
97
break;
98
case INDEX_op_mul_i32:
99
t0 = *tb_ptr++;
100
- t1 = tci_read_r32(regs, &tb_ptr);
101
- t2 = tci_read_r32(regs, &tb_ptr);
102
+ t1 = tci_read_r(regs, &tb_ptr);
103
+ t2 = tci_read_r(regs, &tb_ptr);
104
tci_write_reg(regs, t0, t1 * t2);
105
break;
106
case INDEX_op_div_i32:
107
t0 = *tb_ptr++;
108
- t1 = tci_read_r32(regs, &tb_ptr);
109
- t2 = tci_read_r32(regs, &tb_ptr);
110
+ t1 = tci_read_r(regs, &tb_ptr);
111
+ t2 = tci_read_r(regs, &tb_ptr);
112
tci_write_reg(regs, t0, (int32_t)t1 / (int32_t)t2);
113
break;
114
case INDEX_op_divu_i32:
115
t0 = *tb_ptr++;
116
- t1 = tci_read_r32(regs, &tb_ptr);
117
- t2 = tci_read_r32(regs, &tb_ptr);
118
- tci_write_reg(regs, t0, t1 / t2);
119
+ t1 = tci_read_r(regs, &tb_ptr);
120
+ t2 = tci_read_r(regs, &tb_ptr);
121
+ tci_write_reg(regs, t0, (uint32_t)t1 / (uint32_t)t2);
122
break;
123
case INDEX_op_rem_i32:
124
t0 = *tb_ptr++;
125
- t1 = tci_read_r32(regs, &tb_ptr);
126
- t2 = tci_read_r32(regs, &tb_ptr);
127
+ t1 = tci_read_r(regs, &tb_ptr);
128
+ t2 = tci_read_r(regs, &tb_ptr);
129
tci_write_reg(regs, t0, (int32_t)t1 % (int32_t)t2);
130
break;
131
case INDEX_op_remu_i32:
132
t0 = *tb_ptr++;
133
- t1 = tci_read_r32(regs, &tb_ptr);
134
- t2 = tci_read_r32(regs, &tb_ptr);
135
- tci_write_reg(regs, t0, t1 % t2);
136
+ t1 = tci_read_r(regs, &tb_ptr);
137
+ t2 = tci_read_r(regs, &tb_ptr);
138
+ tci_write_reg(regs, t0, (uint32_t)t1 % (uint32_t)t2);
139
break;
140
case INDEX_op_and_i32:
141
t0 = *tb_ptr++;
142
- t1 = tci_read_r32(regs, &tb_ptr);
143
- t2 = tci_read_r32(regs, &tb_ptr);
144
+ t1 = tci_read_r(regs, &tb_ptr);
145
+ t2 = tci_read_r(regs, &tb_ptr);
146
tci_write_reg(regs, t0, t1 & t2);
147
break;
148
case INDEX_op_or_i32:
149
t0 = *tb_ptr++;
150
- t1 = tci_read_r32(regs, &tb_ptr);
151
- t2 = tci_read_r32(regs, &tb_ptr);
152
+ t1 = tci_read_r(regs, &tb_ptr);
153
+ t2 = tci_read_r(regs, &tb_ptr);
154
tci_write_reg(regs, t0, t1 | t2);
155
break;
156
case INDEX_op_xor_i32:
157
t0 = *tb_ptr++;
158
- t1 = tci_read_r32(regs, &tb_ptr);
159
- t2 = tci_read_r32(regs, &tb_ptr);
160
+ t1 = tci_read_r(regs, &tb_ptr);
161
+ t2 = tci_read_r(regs, &tb_ptr);
162
tci_write_reg(regs, t0, t1 ^ t2);
163
break;
164
165
@@ -XXX,XX +XXX,XX @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
166
167
case INDEX_op_shl_i32:
168
t0 = *tb_ptr++;
169
- t1 = tci_read_r32(regs, &tb_ptr);
170
- t2 = tci_read_r32(regs, &tb_ptr);
171
- tci_write_reg(regs, t0, t1 << (t2 & 31));
172
+ t1 = tci_read_r(regs, &tb_ptr);
173
+ t2 = tci_read_r(regs, &tb_ptr);
174
+ tci_write_reg(regs, t0, (uint32_t)t1 << (t2 & 31));
175
break;
176
case INDEX_op_shr_i32:
177
t0 = *tb_ptr++;
178
- t1 = tci_read_r32(regs, &tb_ptr);
179
- t2 = tci_read_r32(regs, &tb_ptr);
180
- tci_write_reg(regs, t0, t1 >> (t2 & 31));
181
+ t1 = tci_read_r(regs, &tb_ptr);
182
+ t2 = tci_read_r(regs, &tb_ptr);
183
+ tci_write_reg(regs, t0, (uint32_t)t1 >> (t2 & 31));
184
break;
185
case INDEX_op_sar_i32:
186
t0 = *tb_ptr++;
187
- t1 = tci_read_r32(regs, &tb_ptr);
188
- t2 = tci_read_r32(regs, &tb_ptr);
189
- tci_write_reg(regs, t0, ((int32_t)t1 >> (t2 & 31)));
190
+ t1 = tci_read_r(regs, &tb_ptr);
191
+ t2 = tci_read_r(regs, &tb_ptr);
192
+ tci_write_reg(regs, t0, (int32_t)t1 >> (t2 & 31));
193
break;
194
#if TCG_TARGET_HAS_rot_i32
195
case INDEX_op_rotl_i32:
196
t0 = *tb_ptr++;
197
- t1 = tci_read_r32(regs, &tb_ptr);
198
- t2 = tci_read_r32(regs, &tb_ptr);
199
+ t1 = tci_read_r(regs, &tb_ptr);
200
+ t2 = tci_read_r(regs, &tb_ptr);
201
tci_write_reg(regs, t0, rol32(t1, t2 & 31));
202
break;
203
case INDEX_op_rotr_i32:
204
t0 = *tb_ptr++;
205
- t1 = tci_read_r32(regs, &tb_ptr);
206
- t2 = tci_read_r32(regs, &tb_ptr);
207
+ t1 = tci_read_r(regs, &tb_ptr);
208
+ t2 = tci_read_r(regs, &tb_ptr);
209
tci_write_reg(regs, t0, ror32(t1, t2 & 31));
210
break;
211
#endif
212
#if TCG_TARGET_HAS_deposit_i32
213
case INDEX_op_deposit_i32:
214
t0 = *tb_ptr++;
215
- t1 = tci_read_r32(regs, &tb_ptr);
216
- t2 = tci_read_r32(regs, &tb_ptr);
217
+ t1 = tci_read_r(regs, &tb_ptr);
218
+ t2 = tci_read_r(regs, &tb_ptr);
219
tmp16 = *tb_ptr++;
220
tmp8 = *tb_ptr++;
221
tmp32 = (((1 << tmp8) - 1) << tmp16);
222
@@ -XXX,XX +XXX,XX @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
223
break;
224
#endif
225
case INDEX_op_brcond_i32:
226
- t0 = tci_read_r32(regs, &tb_ptr);
227
- t1 = tci_read_r32(regs, &tb_ptr);
228
+ t0 = tci_read_r(regs, &tb_ptr);
229
+ t1 = tci_read_r(regs, &tb_ptr);
230
condition = *tb_ptr++;
231
label = tci_read_label(&tb_ptr);
232
if (tci_compare32(t0, t1, condition)) {
233
@@ -XXX,XX +XXX,XX @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
234
case INDEX_op_mulu2_i32:
235
t0 = *tb_ptr++;
236
t1 = *tb_ptr++;
237
- t2 = tci_read_r32(regs, &tb_ptr);
238
- tmp64 = tci_read_r32(regs, &tb_ptr);
239
- tci_write_reg64(regs, t1, t0, t2 * tmp64);
240
+ t2 = tci_read_r(regs, &tb_ptr);
241
+ tmp64 = (uint32_t)tci_read_r(regs, &tb_ptr);
242
+ tci_write_reg64(regs, t1, t0, (uint32_t)t2 * tmp64);
243
break;
244
#endif /* TCG_TARGET_REG_BITS == 32 */
245
#if TCG_TARGET_HAS_ext8s_i32
246
@@ -XXX,XX +XXX,XX @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
247
#if TCG_TARGET_HAS_bswap32_i32
248
case INDEX_op_bswap32_i32:
249
t0 = *tb_ptr++;
250
- t1 = tci_read_r32(regs, &tb_ptr);
251
+ t1 = tci_read_r(regs, &tb_ptr);
252
tci_write_reg(regs, t0, bswap32(t1));
253
break;
254
#endif
255
#if TCG_TARGET_HAS_not_i32
256
case INDEX_op_not_i32:
257
t0 = *tb_ptr++;
258
- t1 = tci_read_r32(regs, &tb_ptr);
259
+ t1 = tci_read_r(regs, &tb_ptr);
260
tci_write_reg(regs, t0, ~t1);
261
break;
262
#endif
263
#if TCG_TARGET_HAS_neg_i32
264
case INDEX_op_neg_i32:
265
t0 = *tb_ptr++;
266
- t1 = tci_read_r32(regs, &tb_ptr);
267
+ t1 = tci_read_r(regs, &tb_ptr);
268
tci_write_reg(regs, t0, -t1);
269
break;
270
#endif
271
@@ -XXX,XX +XXX,XX @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
272
#endif
273
case INDEX_op_extu_i32_i64:
274
t0 = *tb_ptr++;
275
- t1 = tci_read_r32(regs, &tb_ptr);
276
- tci_write_reg(regs, t0, t1);
277
+ t1 = tci_read_r(regs, &tb_ptr);
278
+ tci_write_reg(regs, t0, (uint32_t)t1);
279
break;
280
#if TCG_TARGET_HAS_bswap16_i64
281
case INDEX_op_bswap16_i64:
282
@@ -XXX,XX +XXX,XX @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
283
#if TCG_TARGET_HAS_bswap32_i64
284
case INDEX_op_bswap32_i64:
285
t0 = *tb_ptr++;
286
- t1 = tci_read_r32(regs, &tb_ptr);
287
+ t1 = tci_read_r(regs, &tb_ptr);
288
tci_write_reg(regs, t0, bswap32(t1));
289
break;
290
#endif
291
--
53
--
292
2.25.1
54
2.43.0
293
294
diff view generated by jsdifflib
[PATCH 18/27] tcg/tci: Reduce use of tci_read_r64
[PULL 49/72] tcg/optimize: Use finish_folding in fold_bitsel_vec
1
In all cases restricted to 64-bit hosts, tcg_read_r is
1
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
2
identical. We retain the 64-bit symbol for the single
3
case of INDEX_op_qemu_st_i64.
4
5
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
---
3
---
8
tcg/tci.c | 93 +++++++++++++++++++++++++------------------------------
4
tcg/optimize.c | 2 +-
9
1 file changed, 42 insertions(+), 51 deletions(-)
5
1 file changed, 1 insertion(+), 1 deletion(-)
10
6
11
diff --git a/tcg/tci.c b/tcg/tci.c
7
diff --git a/tcg/optimize.c b/tcg/optimize.c
12
index XXXXXXX..XXXXXXX 100644
8
index XXXXXXX..XXXXXXX 100644
13
--- a/tcg/tci.c
9
--- a/tcg/optimize.c
14
+++ b/tcg/tci.c
10
+++ b/tcg/optimize.c
15
@@ -XXX,XX +XXX,XX @@ static tcg_target_ulong tci_read_reg(const tcg_target_ulong *regs, TCGReg index)
11
@@ -XXX,XX +XXX,XX @@ static bool fold_bitsel_vec(OptContext *ctx, TCGOp *op)
16
return regs[index];
12
return fold_orc(ctx, op);
13
}
14
}
15
- return false;
16
+ return finish_folding(ctx, op);
17
}
17
}
18
18
19
-#if TCG_TARGET_REG_BITS == 64
19
/* Propagate constants and copies, fold constant expressions. */
20
-static uint64_t tci_read_reg64(const tcg_target_ulong *regs, TCGReg index)
21
-{
22
- return tci_read_reg(regs, index);
23
-}
24
-#endif
25
-
26
static void
27
tci_write_reg(tcg_target_ulong *regs, TCGReg index, tcg_target_ulong value)
28
{
29
@@ -XXX,XX +XXX,XX @@ static uint64_t tci_read_r64(const tcg_target_ulong *regs,
30
static uint64_t tci_read_r64(const tcg_target_ulong *regs,
31
const uint8_t **tb_ptr)
32
{
33
- uint64_t value = tci_read_reg64(regs, **tb_ptr);
34
- *tb_ptr += 1;
35
- return value;
36
+ return tci_read_r(regs, tb_ptr);
37
}
38
#endif
39
40
@@ -XXX,XX +XXX,XX @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
41
#elif TCG_TARGET_REG_BITS == 64
42
case INDEX_op_setcond_i64:
43
t0 = *tb_ptr++;
44
- t1 = tci_read_r64(regs, &tb_ptr);
45
- t2 = tci_read_r64(regs, &tb_ptr);
46
+ t1 = tci_read_r(regs, &tb_ptr);
47
+ t2 = tci_read_r(regs, &tb_ptr);
48
condition = *tb_ptr++;
49
tci_write_reg(regs, t0, tci_compare64(t1, t2, condition));
50
break;
51
@@ -XXX,XX +XXX,XX @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
52
#if TCG_TARGET_REG_BITS == 64
53
case INDEX_op_mov_i64:
54
t0 = *tb_ptr++;
55
- t1 = tci_read_r64(regs, &tb_ptr);
56
+ t1 = tci_read_r(regs, &tb_ptr);
57
tci_write_reg(regs, t0, t1);
58
break;
59
case INDEX_op_tci_movi_i64:
60
@@ -XXX,XX +XXX,XX @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
61
tci_write_reg(regs, t0, *(uint64_t *)(t1 + t2));
62
break;
63
case INDEX_op_st_i64:
64
- t0 = tci_read_r64(regs, &tb_ptr);
65
+ t0 = tci_read_r(regs, &tb_ptr);
66
t1 = tci_read_r(regs, &tb_ptr);
67
t2 = tci_read_s32(&tb_ptr);
68
*(uint64_t *)(t1 + t2) = t0;
69
@@ -XXX,XX +XXX,XX @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
70
71
case INDEX_op_add_i64:
72
t0 = *tb_ptr++;
73
- t1 = tci_read_r64(regs, &tb_ptr);
74
- t2 = tci_read_r64(regs, &tb_ptr);
75
+ t1 = tci_read_r(regs, &tb_ptr);
76
+ t2 = tci_read_r(regs, &tb_ptr);
77
tci_write_reg(regs, t0, t1 + t2);
78
break;
79
case INDEX_op_sub_i64:
80
t0 = *tb_ptr++;
81
- t1 = tci_read_r64(regs, &tb_ptr);
82
- t2 = tci_read_r64(regs, &tb_ptr);
83
+ t1 = tci_read_r(regs, &tb_ptr);
84
+ t2 = tci_read_r(regs, &tb_ptr);
85
tci_write_reg(regs, t0, t1 - t2);
86
break;
87
case INDEX_op_mul_i64:
88
t0 = *tb_ptr++;
89
- t1 = tci_read_r64(regs, &tb_ptr);
90
- t2 = tci_read_r64(regs, &tb_ptr);
91
+ t1 = tci_read_r(regs, &tb_ptr);
92
+ t2 = tci_read_r(regs, &tb_ptr);
93
tci_write_reg(regs, t0, t1 * t2);
94
break;
95
case INDEX_op_div_i64:
96
t0 = *tb_ptr++;
97
- t1 = tci_read_r64(regs, &tb_ptr);
98
- t2 = tci_read_r64(regs, &tb_ptr);
99
+ t1 = tci_read_r(regs, &tb_ptr);
100
+ t2 = tci_read_r(regs, &tb_ptr);
101
tci_write_reg(regs, t0, (int64_t)t1 / (int64_t)t2);
102
break;
103
case INDEX_op_divu_i64:
104
t0 = *tb_ptr++;
105
- t1 = tci_read_r64(regs, &tb_ptr);
106
- t2 = tci_read_r64(regs, &tb_ptr);
107
+ t1 = tci_read_r(regs, &tb_ptr);
108
+ t2 = tci_read_r(regs, &tb_ptr);
109
tci_write_reg(regs, t0, (uint64_t)t1 / (uint64_t)t2);
110
break;
111
case INDEX_op_rem_i64:
112
t0 = *tb_ptr++;
113
- t1 = tci_read_r64(regs, &tb_ptr);
114
- t2 = tci_read_r64(regs, &tb_ptr);
115
+ t1 = tci_read_r(regs, &tb_ptr);
116
+ t2 = tci_read_r(regs, &tb_ptr);
117
tci_write_reg(regs, t0, (int64_t)t1 % (int64_t)t2);
118
break;
119
case INDEX_op_remu_i64:
120
t0 = *tb_ptr++;
121
- t1 = tci_read_r64(regs, &tb_ptr);
122
- t2 = tci_read_r64(regs, &tb_ptr);
123
+ t1 = tci_read_r(regs, &tb_ptr);
124
+ t2 = tci_read_r(regs, &tb_ptr);
125
tci_write_reg(regs, t0, (uint64_t)t1 % (uint64_t)t2);
126
break;
127
case INDEX_op_and_i64:
128
t0 = *tb_ptr++;
129
- t1 = tci_read_r64(regs, &tb_ptr);
130
- t2 = tci_read_r64(regs, &tb_ptr);
131
+ t1 = tci_read_r(regs, &tb_ptr);
132
+ t2 = tci_read_r(regs, &tb_ptr);
133
tci_write_reg(regs, t0, t1 & t2);
134
break;
135
case INDEX_op_or_i64:
136
t0 = *tb_ptr++;
137
- t1 = tci_read_r64(regs, &tb_ptr);
138
- t2 = tci_read_r64(regs, &tb_ptr);
139
+ t1 = tci_read_r(regs, &tb_ptr);
140
+ t2 = tci_read_r(regs, &tb_ptr);
141
tci_write_reg(regs, t0, t1 | t2);
142
break;
143
case INDEX_op_xor_i64:
144
t0 = *tb_ptr++;
145
- t1 = tci_read_r64(regs, &tb_ptr);
146
- t2 = tci_read_r64(regs, &tb_ptr);
147
+ t1 = tci_read_r(regs, &tb_ptr);
148
+ t2 = tci_read_r(regs, &tb_ptr);
149
tci_write_reg(regs, t0, t1 ^ t2);
150
break;
151
152
@@ -XXX,XX +XXX,XX @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
153
154
case INDEX_op_shl_i64:
155
t0 = *tb_ptr++;
156
- t1 = tci_read_r64(regs, &tb_ptr);
157
- t2 = tci_read_r64(regs, &tb_ptr);
158
+ t1 = tci_read_r(regs, &tb_ptr);
159
+ t2 = tci_read_r(regs, &tb_ptr);
160
tci_write_reg(regs, t0, t1 << (t2 & 63));
161
break;
162
case INDEX_op_shr_i64:
163
t0 = *tb_ptr++;
164
- t1 = tci_read_r64(regs, &tb_ptr);
165
- t2 = tci_read_r64(regs, &tb_ptr);
166
+ t1 = tci_read_r(regs, &tb_ptr);
167
+ t2 = tci_read_r(regs, &tb_ptr);
168
tci_write_reg(regs, t0, t1 >> (t2 & 63));
169
break;
170
case INDEX_op_sar_i64:
171
t0 = *tb_ptr++;
172
- t1 = tci_read_r64(regs, &tb_ptr);
173
- t2 = tci_read_r64(regs, &tb_ptr);
174
+ t1 = tci_read_r(regs, &tb_ptr);
175
+ t2 = tci_read_r(regs, &tb_ptr);
176
tci_write_reg(regs, t0, ((int64_t)t1 >> (t2 & 63)));
177
break;
178
#if TCG_TARGET_HAS_rot_i64
179
case INDEX_op_rotl_i64:
180
t0 = *tb_ptr++;
181
- t1 = tci_read_r64(regs, &tb_ptr);
182
- t2 = tci_read_r64(regs, &tb_ptr);
183
+ t1 = tci_read_r(regs, &tb_ptr);
184
+ t2 = tci_read_r(regs, &tb_ptr);
185
tci_write_reg(regs, t0, rol64(t1, t2 & 63));
186
break;
187
case INDEX_op_rotr_i64:
188
t0 = *tb_ptr++;
189
- t1 = tci_read_r64(regs, &tb_ptr);
190
- t2 = tci_read_r64(regs, &tb_ptr);
191
+ t1 = tci_read_r(regs, &tb_ptr);
192
+ t2 = tci_read_r(regs, &tb_ptr);
193
tci_write_reg(regs, t0, ror64(t1, t2 & 63));
194
break;
195
#endif
196
#if TCG_TARGET_HAS_deposit_i64
197
case INDEX_op_deposit_i64:
198
t0 = *tb_ptr++;
199
- t1 = tci_read_r64(regs, &tb_ptr);
200
- t2 = tci_read_r64(regs, &tb_ptr);
201
+ t1 = tci_read_r(regs, &tb_ptr);
202
+ t2 = tci_read_r(regs, &tb_ptr);
203
tmp16 = *tb_ptr++;
204
tmp8 = *tb_ptr++;
205
tmp64 = (((1ULL << tmp8) - 1) << tmp16);
206
@@ -XXX,XX +XXX,XX @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
207
break;
208
#endif
209
case INDEX_op_brcond_i64:
210
- t0 = tci_read_r64(regs, &tb_ptr);
211
- t1 = tci_read_r64(regs, &tb_ptr);
212
+ t0 = tci_read_r(regs, &tb_ptr);
213
+ t1 = tci_read_r(regs, &tb_ptr);
214
condition = *tb_ptr++;
215
label = tci_read_label(&tb_ptr);
216
if (tci_compare64(t0, t1, condition)) {
217
@@ -XXX,XX +XXX,XX @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
218
#if TCG_TARGET_HAS_bswap64_i64
219
case INDEX_op_bswap64_i64:
220
t0 = *tb_ptr++;
221
- t1 = tci_read_r64(regs, &tb_ptr);
222
+ t1 = tci_read_r(regs, &tb_ptr);
223
tci_write_reg(regs, t0, bswap64(t1));
224
break;
225
#endif
226
#if TCG_TARGET_HAS_not_i64
227
case INDEX_op_not_i64:
228
t0 = *tb_ptr++;
229
- t1 = tci_read_r64(regs, &tb_ptr);
230
+ t1 = tci_read_r(regs, &tb_ptr);
231
tci_write_reg(regs, t0, ~t1);
232
break;
233
#endif
234
#if TCG_TARGET_HAS_neg_i64
235
case INDEX_op_neg_i64:
236
t0 = *tb_ptr++;
237
- t1 = tci_read_r64(regs, &tb_ptr);
238
+ t1 = tci_read_r(regs, &tb_ptr);
239
tci_write_reg(regs, t0, -t1);
240
break;
241
#endif
242
--
20
--
243
2.25.1
21
2.43.0
244
245
diff view generated by jsdifflib
New patch
[PULL 50/72] tcg/optimize: Use finish_folding as default in tcg_optimize
1
All non-default cases now finish folding within each function.
2
Do the same with the default case and assert it is done after.
1
3
4
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
---
7
tcg/optimize.c | 6 ++----
8
1 file changed, 2 insertions(+), 4 deletions(-)
9
10
diff --git a/tcg/optimize.c b/tcg/optimize.c
11
index XXXXXXX..XXXXXXX 100644
12
--- a/tcg/optimize.c
13
+++ b/tcg/optimize.c
14
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
15
done = true;
16
break;
17
default:
18
+ done = finish_folding(&ctx, op);
19
break;
20
}
21
-
22
- if (!done) {
23
- finish_folding(&ctx, op);
24
- }
25
+ tcg_debug_assert(done);
26
}
27
}
28
--
29
2.43.0
diff view generated by jsdifflib
New patch
[PULL 51/72] tcg/optimize: Remove z_mask, s_mask from OptContext
1
All mask setting is now done with parameters via fold_masks_*.
1
2
3
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
---
6
tcg/optimize.c | 13 -------------
7
1 file changed, 13 deletions(-)
8
9
diff --git a/tcg/optimize.c b/tcg/optimize.c
10
index XXXXXXX..XXXXXXX 100644
11
--- a/tcg/optimize.c
12
+++ b/tcg/optimize.c
13
@@ -XXX,XX +XXX,XX @@ typedef struct OptContext {
14
QSIMPLEQ_HEAD(, MemCopyInfo) mem_free;
15
16
/* In flight values from optimization. */
17
- uint64_t z_mask; /* mask bit is 0 iff value bit is 0 */
18
- uint64_t s_mask; /* mask bit is 1 if value bit matches msb */
19
TCGType type;
20
} OptContext;
21
22
@@ -XXX,XX +XXX,XX @@ static bool finish_folding(OptContext *ctx, TCGOp *op)
23
for (i = 0; i < nb_oargs; i++) {
24
TCGTemp *ts = arg_temp(op->args[i]);
25
reset_ts(ctx, ts);
26
- /*
27
- * Save the corresponding known-zero/sign bits mask for the
28
- * first output argument (only one supported so far).
29
- */
30
- if (i == 0) {
31
- ts_info(ts)->z_mask = ctx->z_mask;
32
- }
33
}
34
return true;
35
}
36
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
37
ctx.type = TCG_TYPE_I32;
38
}
39
40
- /* Assume all bits affected, no bits known zero, no sign reps. */
41
- ctx.z_mask = -1;
42
- ctx.s_mask = 0;
43
-
44
/*
45
* Process each opcode.
46
* Sorted alphabetically by opcode as much as possible.
47
--
48
2.43.0
diff view generated by jsdifflib
[PATCH 19/27] tcg/tci: Merge basic arithmetic operations
[PULL 52/72] tcg/optimize: Re-enable sign-mask optimizations
1
This includes add, sub, mul, and, or, xor.
1
All instances of s_mask have been converted to the new
2
representation. We can now re-enable usage.
2
3
3
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
4
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
---
6
---
6
tcg/tci.c | 83 +++++++++++++++++--------------------------------------
7
tcg/optimize.c | 4 ++--
7
1 file changed, 25 insertions(+), 58 deletions(-)
8
1 file changed, 2 insertions(+), 2 deletions(-)
8
9
9
diff --git a/tcg/tci.c b/tcg/tci.c
10
diff --git a/tcg/optimize.c b/tcg/optimize.c
10
index XXXXXXX..XXXXXXX 100644
11
index XXXXXXX..XXXXXXX 100644
11
--- a/tcg/tci.c
12
--- a/tcg/optimize.c
12
+++ b/tcg/tci.c
13
+++ b/tcg/optimize.c
13
@@ -XXX,XX +XXX,XX @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
14
@@ -XXX,XX +XXX,XX @@ static bool fold_exts(OptContext *ctx, TCGOp *op)
14
*(uint32_t *)(t1 + t2) = t0;
15
g_assert_not_reached();
15
break;
16
}
16
17
17
- /* Arithmetic operations (32 bit). */
18
- if (0 && !type_change && fold_affected_mask(ctx, op, s_mask & ~s_mask_old)) {
18
+ /* Arithmetic operations (mixed 32/64 bit). */
19
+ if (!type_change && fold_affected_mask(ctx, op, s_mask & ~s_mask_old)) {
19
20
return true;
20
- case INDEX_op_add_i32:
21
}
21
+ CASE_32_64(add)
22
22
t0 = *tb_ptr++;
23
@@ -XXX,XX +XXX,XX @@ static bool fold_sextract(OptContext *ctx, TCGOp *op)
23
t1 = tci_read_r(regs, &tb_ptr);
24
s_mask = s_mask_old >> pos;
24
t2 = tci_read_r(regs, &tb_ptr);
25
s_mask |= -1ull << (len - 1);
25
tci_write_reg(regs, t0, t1 + t2);
26
26
break;
27
- if (0 && pos == 0 && fold_affected_mask(ctx, op, s_mask & ~s_mask_old)) {
27
- case INDEX_op_sub_i32:
28
+ if (pos == 0 && fold_affected_mask(ctx, op, s_mask & ~s_mask_old)) {
28
+ CASE_32_64(sub)
29
return true;
29
t0 = *tb_ptr++;
30
}
30
t1 = tci_read_r(regs, &tb_ptr);
31
t2 = tci_read_r(regs, &tb_ptr);
32
tci_write_reg(regs, t0, t1 - t2);
33
break;
34
- case INDEX_op_mul_i32:
35
+ CASE_32_64(mul)
36
t0 = *tb_ptr++;
37
t1 = tci_read_r(regs, &tb_ptr);
38
t2 = tci_read_r(regs, &tb_ptr);
39
tci_write_reg(regs, t0, t1 * t2);
40
break;
41
+ CASE_32_64(and)
42
+ t0 = *tb_ptr++;
43
+ t1 = tci_read_r(regs, &tb_ptr);
44
+ t2 = tci_read_r(regs, &tb_ptr);
45
+ tci_write_reg(regs, t0, t1 & t2);
46
+ break;
47
+ CASE_32_64(or)
48
+ t0 = *tb_ptr++;
49
+ t1 = tci_read_r(regs, &tb_ptr);
50
+ t2 = tci_read_r(regs, &tb_ptr);
51
+ tci_write_reg(regs, t0, t1 | t2);
52
+ break;
53
+ CASE_32_64(xor)
54
+ t0 = *tb_ptr++;
55
+ t1 = tci_read_r(regs, &tb_ptr);
56
+ t2 = tci_read_r(regs, &tb_ptr);
57
+ tci_write_reg(regs, t0, t1 ^ t2);
58
+ break;
59
+
60
+ /* Arithmetic operations (32 bit). */
61
+
62
case INDEX_op_div_i32:
63
t0 = *tb_ptr++;
64
t1 = tci_read_r(regs, &tb_ptr);
65
@@ -XXX,XX +XXX,XX @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
66
t2 = tci_read_r(regs, &tb_ptr);
67
tci_write_reg(regs, t0, (uint32_t)t1 % (uint32_t)t2);
68
break;
69
- case INDEX_op_and_i32:
70
- t0 = *tb_ptr++;
71
- t1 = tci_read_r(regs, &tb_ptr);
72
- t2 = tci_read_r(regs, &tb_ptr);
73
- tci_write_reg(regs, t0, t1 & t2);
74
- break;
75
- case INDEX_op_or_i32:
76
- t0 = *tb_ptr++;
77
- t1 = tci_read_r(regs, &tb_ptr);
78
- t2 = tci_read_r(regs, &tb_ptr);
79
- tci_write_reg(regs, t0, t1 | t2);
80
- break;
81
- case INDEX_op_xor_i32:
82
- t0 = *tb_ptr++;
83
- t1 = tci_read_r(regs, &tb_ptr);
84
- t2 = tci_read_r(regs, &tb_ptr);
85
- tci_write_reg(regs, t0, t1 ^ t2);
86
- break;
87
88
/* Shift/rotate operations (32 bit). */
89
90
@@ -XXX,XX +XXX,XX @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
91
92
/* Arithmetic operations (64 bit). */
93
94
- case INDEX_op_add_i64:
95
- t0 = *tb_ptr++;
96
- t1 = tci_read_r(regs, &tb_ptr);
97
- t2 = tci_read_r(regs, &tb_ptr);
98
- tci_write_reg(regs, t0, t1 + t2);
99
- break;
100
- case INDEX_op_sub_i64:
101
- t0 = *tb_ptr++;
102
- t1 = tci_read_r(regs, &tb_ptr);
103
- t2 = tci_read_r(regs, &tb_ptr);
104
- tci_write_reg(regs, t0, t1 - t2);
105
- break;
106
- case INDEX_op_mul_i64:
107
- t0 = *tb_ptr++;
108
- t1 = tci_read_r(regs, &tb_ptr);
109
- t2 = tci_read_r(regs, &tb_ptr);
110
- tci_write_reg(regs, t0, t1 * t2);
111
- break;
112
case INDEX_op_div_i64:
113
t0 = *tb_ptr++;
114
t1 = tci_read_r(regs, &tb_ptr);
115
@@ -XXX,XX +XXX,XX @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
116
t2 = tci_read_r(regs, &tb_ptr);
117
tci_write_reg(regs, t0, (uint64_t)t1 % (uint64_t)t2);
118
break;
119
- case INDEX_op_and_i64:
120
- t0 = *tb_ptr++;
121
- t1 = tci_read_r(regs, &tb_ptr);
122
- t2 = tci_read_r(regs, &tb_ptr);
123
- tci_write_reg(regs, t0, t1 & t2);
124
- break;
125
- case INDEX_op_or_i64:
126
- t0 = *tb_ptr++;
127
- t1 = tci_read_r(regs, &tb_ptr);
128
- t2 = tci_read_r(regs, &tb_ptr);
129
- tci_write_reg(regs, t0, t1 | t2);
130
- break;
131
- case INDEX_op_xor_i64:
132
- t0 = *tb_ptr++;
133
- t1 = tci_read_r(regs, &tb_ptr);
134
- t2 = tci_read_r(regs, &tb_ptr);
135
- tci_write_reg(regs, t0, t1 ^ t2);
136
- break;
137
138
/* Shift/rotate operations (64 bit). */
139
31
140
--
32
--
141
2.25.1
33
2.43.0
142
143
diff view generated by jsdifflib
[PATCH 05/27] tcg: Split out tcg_raise_tb_overflow
[PULL 53/72] tcg/optimize: Move fold_bitsel_vec into alphabetic sort
1
Allow other places in tcg to restart with a smaller tb.
1
The big comment just above says functions should be sorted.
2
Add forward declarations as needed.
2
3
3
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
4
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
---
6
---
6
tcg/tcg.c | 9 +++++++--
7
tcg/optimize.c | 114 +++++++++++++++++++++++++------------------------
7
1 file changed, 7 insertions(+), 2 deletions(-)
8
1 file changed, 59 insertions(+), 55 deletions(-)
8
9
9
diff --git a/tcg/tcg.c b/tcg/tcg.c
10
diff --git a/tcg/optimize.c b/tcg/optimize.c
10
index XXXXXXX..XXXXXXX 100644
11
index XXXXXXX..XXXXXXX 100644
11
--- a/tcg/tcg.c
12
--- a/tcg/optimize.c
12
+++ b/tcg/tcg.c
13
+++ b/tcg/optimize.c
13
@@ -XXX,XX +XXX,XX @@ static void set_jmp_reset_offset(TCGContext *s, int which)
14
@@ -XXX,XX +XXX,XX @@ static bool fold_xx_to_x(OptContext *ctx, TCGOp *op)
14
s->tb_jmp_reset_offset[which] = tcg_current_code_size(s);
15
* 3) those that produce information about the result value.
16
*/
17
18
+static bool fold_or(OptContext *ctx, TCGOp *op);
19
+static bool fold_orc(OptContext *ctx, TCGOp *op);
20
+static bool fold_xor(OptContext *ctx, TCGOp *op);
21
+
22
static bool fold_add(OptContext *ctx, TCGOp *op)
23
{
24
if (fold_const2_commutative(ctx, op) ||
25
@@ -XXX,XX +XXX,XX @@ static bool fold_andc(OptContext *ctx, TCGOp *op)
26
return fold_masks_zs(ctx, op, z_mask, s_mask);
15
}
27
}
16
28
17
+/* Signal overflow, starting over with fewer guest insns. */
29
+static bool fold_bitsel_vec(OptContext *ctx, TCGOp *op)
18
+static void QEMU_NORETURN tcg_raise_tb_overflow(TCGContext *s)
19
+{
30
+{
20
+ siglongjmp(s->jmp_trans, -2);
31
+ /* If true and false values are the same, eliminate the cmp. */
32
+ if (args_are_copies(op->args[2], op->args[3])) {
33
+ return tcg_opt_gen_mov(ctx, op, op->args[0], op->args[2]);
34
+ }
35
+
36
+ if (arg_is_const(op->args[2]) && arg_is_const(op->args[3])) {
37
+ uint64_t tv = arg_info(op->args[2])->val;
38
+ uint64_t fv = arg_info(op->args[3])->val;
39
+
40
+ if (tv == -1 && fv == 0) {
41
+ return tcg_opt_gen_mov(ctx, op, op->args[0], op->args[1]);
42
+ }
43
+ if (tv == 0 && fv == -1) {
44
+ if (TCG_TARGET_HAS_not_vec) {
45
+ op->opc = INDEX_op_not_vec;
46
+ return fold_not(ctx, op);
47
+ } else {
48
+ op->opc = INDEX_op_xor_vec;
49
+ op->args[2] = arg_new_constant(ctx, -1);
50
+ return fold_xor(ctx, op);
51
+ }
52
+ }
53
+ }
54
+ if (arg_is_const(op->args[2])) {
55
+ uint64_t tv = arg_info(op->args[2])->val;
56
+ if (tv == -1) {
57
+ op->opc = INDEX_op_or_vec;
58
+ op->args[2] = op->args[3];
59
+ return fold_or(ctx, op);
60
+ }
61
+ if (tv == 0 && TCG_TARGET_HAS_andc_vec) {
62
+ op->opc = INDEX_op_andc_vec;
63
+ op->args[2] = op->args[1];
64
+ op->args[1] = op->args[3];
65
+ return fold_andc(ctx, op);
66
+ }
67
+ }
68
+ if (arg_is_const(op->args[3])) {
69
+ uint64_t fv = arg_info(op->args[3])->val;
70
+ if (fv == 0) {
71
+ op->opc = INDEX_op_and_vec;
72
+ return fold_and(ctx, op);
73
+ }
74
+ if (fv == -1 && TCG_TARGET_HAS_orc_vec) {
75
+ op->opc = INDEX_op_orc_vec;
76
+ op->args[2] = op->args[1];
77
+ op->args[1] = op->args[3];
78
+ return fold_orc(ctx, op);
79
+ }
80
+ }
81
+ return finish_folding(ctx, op);
21
+}
82
+}
22
+
83
+
23
#define C_PFX1(P, A) P##A
84
static bool fold_brcond(OptContext *ctx, TCGOp *op)
24
#define C_PFX2(P, A, B) P##A##_##B
85
{
25
#define C_PFX3(P, A, B, C) P##A##_##B##_##C
86
int i = do_constant_folding_cond1(ctx, op, NO_DEST, &op->args[0],
26
@@ -XXX,XX +XXX,XX @@ static TCGTemp *tcg_temp_alloc(TCGContext *s)
87
@@ -XXX,XX +XXX,XX @@ static bool fold_xor(OptContext *ctx, TCGOp *op)
27
int n = s->nb_temps++;
88
return fold_masks_zs(ctx, op, z_mask, s_mask);
28
29
if (n >= TCG_MAX_TEMPS) {
30
- /* Signal overflow, starting over with fewer guest insns. */
31
- siglongjmp(s->jmp_trans, -2);
32
+ tcg_raise_tb_overflow(s);
33
}
34
return memset(&s->temps[n], 0, sizeof(TCGTemp));
35
}
89
}
90
91
-static bool fold_bitsel_vec(OptContext *ctx, TCGOp *op)
92
-{
93
- /* If true and false values are the same, eliminate the cmp. */
94
- if (args_are_copies(op->args[2], op->args[3])) {
95
- return tcg_opt_gen_mov(ctx, op, op->args[0], op->args[2]);
96
- }
97
-
98
- if (arg_is_const(op->args[2]) && arg_is_const(op->args[3])) {
99
- uint64_t tv = arg_info(op->args[2])->val;
100
- uint64_t fv = arg_info(op->args[3])->val;
101
-
102
- if (tv == -1 && fv == 0) {
103
- return tcg_opt_gen_mov(ctx, op, op->args[0], op->args[1]);
104
- }
105
- if (tv == 0 && fv == -1) {
106
- if (TCG_TARGET_HAS_not_vec) {
107
- op->opc = INDEX_op_not_vec;
108
- return fold_not(ctx, op);
109
- } else {
110
- op->opc = INDEX_op_xor_vec;
111
- op->args[2] = arg_new_constant(ctx, -1);
112
- return fold_xor(ctx, op);
113
- }
114
- }
115
- }
116
- if (arg_is_const(op->args[2])) {
117
- uint64_t tv = arg_info(op->args[2])->val;
118
- if (tv == -1) {
119
- op->opc = INDEX_op_or_vec;
120
- op->args[2] = op->args[3];
121
- return fold_or(ctx, op);
122
- }
123
- if (tv == 0 && TCG_TARGET_HAS_andc_vec) {
124
- op->opc = INDEX_op_andc_vec;
125
- op->args[2] = op->args[1];
126
- op->args[1] = op->args[3];
127
- return fold_andc(ctx, op);
128
- }
129
- }
130
- if (arg_is_const(op->args[3])) {
131
- uint64_t fv = arg_info(op->args[3])->val;
132
- if (fv == 0) {
133
- op->opc = INDEX_op_and_vec;
134
- return fold_and(ctx, op);
135
- }
136
- if (fv == -1 && TCG_TARGET_HAS_orc_vec) {
137
- op->opc = INDEX_op_orc_vec;
138
- op->args[2] = op->args[1];
139
- op->args[1] = op->args[3];
140
- return fold_orc(ctx, op);
141
- }
142
- }
143
- return finish_folding(ctx, op);
144
-}
145
-
146
/* Propagate constants and copies, fold constant expressions. */
147
void tcg_optimize(TCGContext *s)
148
{
36
--
149
--
37
2.25.1
150
2.43.0
38
39
diff view generated by jsdifflib
[PATCH 14/27] tcg/tci: Remove tci_read_r16
[PULL 54/72] tcg/optimize: Move fold_cmp_vec, fold_cmpsel_vec into alphabetic sort
1
Use explicit casts for ext16u opcodes, and allow truncation
1
The big comment just above says functions should be sorted.
2
to happen with the store for st16 opcodes, and with the call
3
for bswap16 opcodes.
4
2
5
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
3
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
---
5
---
8
tcg/tci.c | 28 +++++++---------------------
6
tcg/optimize.c | 60 +++++++++++++++++++++++++-------------------------
9
1 file changed, 7 insertions(+), 21 deletions(-)
7
1 file changed, 30 insertions(+), 30 deletions(-)
10
8
11
diff --git a/tcg/tci.c b/tcg/tci.c
9
diff --git a/tcg/optimize.c b/tcg/optimize.c
12
index XXXXXXX..XXXXXXX 100644
10
index XXXXXXX..XXXXXXX 100644
13
--- a/tcg/tci.c
11
--- a/tcg/optimize.c
14
+++ b/tcg/tci.c
12
+++ b/tcg/optimize.c
15
@@ -XXX,XX +XXX,XX @@ static int32_t tci_read_reg32s(const tcg_target_ulong *regs, TCGReg index)
13
@@ -XXX,XX +XXX,XX @@ static bool fold_call(OptContext *ctx, TCGOp *op)
14
return true;
16
}
15
}
17
#endif
16
18
17
+static bool fold_cmp_vec(OptContext *ctx, TCGOp *op)
19
-static uint16_t tci_read_reg16(const tcg_target_ulong *regs, TCGReg index)
18
+{
19
+ /* Canonicalize the comparison to put immediate second. */
20
+ if (swap_commutative(NO_DEST, &op->args[1], &op->args[2])) {
21
+ op->args[3] = tcg_swap_cond(op->args[3]);
22
+ }
23
+ return finish_folding(ctx, op);
24
+}
25
+
26
+static bool fold_cmpsel_vec(OptContext *ctx, TCGOp *op)
27
+{
28
+ /* If true and false values are the same, eliminate the cmp. */
29
+ if (args_are_copies(op->args[3], op->args[4])) {
30
+ return tcg_opt_gen_mov(ctx, op, op->args[0], op->args[3]);
31
+ }
32
+
33
+ /* Canonicalize the comparison to put immediate second. */
34
+ if (swap_commutative(NO_DEST, &op->args[1], &op->args[2])) {
35
+ op->args[5] = tcg_swap_cond(op->args[5]);
36
+ }
37
+ /*
38
+ * Canonicalize the "false" input reg to match the destination,
39
+ * so that the tcg backend can implement "move if true".
40
+ */
41
+ if (swap_commutative(op->args[0], &op->args[4], &op->args[3])) {
42
+ op->args[5] = tcg_invert_cond(op->args[5]);
43
+ }
44
+ return finish_folding(ctx, op);
45
+}
46
+
47
static bool fold_count_zeros(OptContext *ctx, TCGOp *op)
48
{
49
uint64_t z_mask, s_mask;
50
@@ -XXX,XX +XXX,XX @@ static bool fold_setcond2(OptContext *ctx, TCGOp *op)
51
return tcg_opt_gen_movi(ctx, op, op->args[0], i);
52
}
53
54
-static bool fold_cmp_vec(OptContext *ctx, TCGOp *op)
20
-{
55
-{
21
- return (uint16_t)tci_read_reg(regs, index);
56
- /* Canonicalize the comparison to put immediate second. */
57
- if (swap_commutative(NO_DEST, &op->args[1], &op->args[2])) {
58
- op->args[3] = tcg_swap_cond(op->args[3]);
59
- }
60
- return finish_folding(ctx, op);
22
-}
61
-}
23
-
62
-
24
static uint32_t tci_read_reg32(const tcg_target_ulong *regs, TCGReg index)
63
-static bool fold_cmpsel_vec(OptContext *ctx, TCGOp *op)
25
{
26
return (uint32_t)tci_read_reg(regs, index);
27
@@ -XXX,XX +XXX,XX @@ tci_read_r(const tcg_target_ulong *regs, const uint8_t **tb_ptr)
28
return value;
29
}
30
31
-/* Read indexed register (16 bit) from bytecode. */
32
-static uint16_t tci_read_r16(const tcg_target_ulong *regs,
33
- const uint8_t **tb_ptr)
34
-{
64
-{
35
- uint16_t value = tci_read_reg16(regs, **tb_ptr);
65
- /* If true and false values are the same, eliminate the cmp. */
36
- *tb_ptr += 1;
66
- if (args_are_copies(op->args[3], op->args[4])) {
37
- return value;
67
- return tcg_opt_gen_mov(ctx, op, op->args[0], op->args[3]);
68
- }
69
-
70
- /* Canonicalize the comparison to put immediate second. */
71
- if (swap_commutative(NO_DEST, &op->args[1], &op->args[2])) {
72
- op->args[5] = tcg_swap_cond(op->args[5]);
73
- }
74
- /*
75
- * Canonicalize the "false" input reg to match the destination,
76
- * so that the tcg backend can implement "move if true".
77
- */
78
- if (swap_commutative(op->args[0], &op->args[4], &op->args[3])) {
79
- op->args[5] = tcg_invert_cond(op->args[5]);
80
- }
81
- return finish_folding(ctx, op);
38
-}
82
-}
39
-
83
-
40
#if TCG_TARGET_HAS_ext16s_i32 || TCG_TARGET_HAS_ext16s_i64
84
static bool fold_sextract(OptContext *ctx, TCGOp *op)
41
/* Read indexed register (16 bit signed) from bytecode. */
85
{
42
static int16_t tci_read_r16s(const tcg_target_ulong *regs,
86
uint64_t z_mask, s_mask, s_mask_old;
43
@@ -XXX,XX +XXX,XX @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
44
*(uint8_t *)(t1 + t2) = t0;
45
break;
46
CASE_32_64(st16)
47
- t0 = tci_read_r16(regs, &tb_ptr);
48
+ t0 = tci_read_r(regs, &tb_ptr);
49
t1 = tci_read_r(regs, &tb_ptr);
50
t2 = tci_read_s32(&tb_ptr);
51
*(uint16_t *)(t1 + t2) = t0;
52
@@ -XXX,XX +XXX,XX @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
53
#if TCG_TARGET_HAS_ext16u_i32
54
case INDEX_op_ext16u_i32:
55
t0 = *tb_ptr++;
56
- t1 = tci_read_r16(regs, &tb_ptr);
57
- tci_write_reg(regs, t0, t1);
58
+ t1 = tci_read_r(regs, &tb_ptr);
59
+ tci_write_reg(regs, t0, (uint16_t)t1);
60
break;
61
#endif
62
#if TCG_TARGET_HAS_bswap16_i32
63
case INDEX_op_bswap16_i32:
64
t0 = *tb_ptr++;
65
- t1 = tci_read_r16(regs, &tb_ptr);
66
+ t1 = tci_read_r(regs, &tb_ptr);
67
tci_write_reg(regs, t0, bswap16(t1));
68
break;
69
#endif
70
@@ -XXX,XX +XXX,XX @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
71
#if TCG_TARGET_HAS_ext16u_i64
72
case INDEX_op_ext16u_i64:
73
t0 = *tb_ptr++;
74
- t1 = tci_read_r16(regs, &tb_ptr);
75
- tci_write_reg(regs, t0, t1);
76
+ t1 = tci_read_r(regs, &tb_ptr);
77
+ tci_write_reg(regs, t0, (uint16_t)t1);
78
break;
79
#endif
80
#if TCG_TARGET_HAS_ext32s_i64
81
@@ -XXX,XX +XXX,XX @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
82
#if TCG_TARGET_HAS_bswap16_i64
83
case INDEX_op_bswap16_i64:
84
t0 = *tb_ptr++;
85
- t1 = tci_read_r16(regs, &tb_ptr);
86
+ t1 = tci_read_r(regs, &tb_ptr);
87
tci_write_reg(regs, t0, bswap16(t1));
88
break;
89
#endif
90
--
87
--
91
2.25.1
88
2.43.0
92
93
diff view generated by jsdifflib
New patch
[PULL 55/72] softfloat: Add float{16,32,64}_muladd_scalbn
1
1
We currently have a flag, float_muladd_halve_result, to scale
2
the result by 2**-1. Extend this to handle arbitrary scaling.
3
4
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
---
7
include/fpu/softfloat.h | 6 ++++
8
fpu/softfloat.c | 58 ++++++++++++++++++++++-----------------
9
fpu/softfloat-parts.c.inc | 7 +++--
10
3 files changed, 44 insertions(+), 27 deletions(-)
11
12
diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h
13
index XXXXXXX..XXXXXXX 100644
14
--- a/include/fpu/softfloat.h
15
+++ b/include/fpu/softfloat.h
16
@@ -XXX,XX +XXX,XX @@ float16 float16_add(float16, float16, float_status *status);
17
float16 float16_sub(float16, float16, float_status *status);
18
float16 float16_mul(float16, float16, float_status *status);
19
float16 float16_muladd(float16, float16, float16, int, float_status *status);
20
+float16 float16_muladd_scalbn(float16, float16, float16,
21
+ int, int, float_status *status);
22
float16 float16_div(float16, float16, float_status *status);
23
float16 float16_scalbn(float16, int, float_status *status);
24
float16 float16_min(float16, float16, float_status *status);
25
@@ -XXX,XX +XXX,XX @@ float32 float32_mul(float32, float32, float_status *status);
26
float32 float32_div(float32, float32, float_status *status);
27
float32 float32_rem(float32, float32, float_status *status);
28
float32 float32_muladd(float32, float32, float32, int, float_status *status);
29
+float32 float32_muladd_scalbn(float32, float32, float32,
30
+ int, int, float_status *status);
31
float32 float32_sqrt(float32, float_status *status);
32
float32 float32_exp2(float32, float_status *status);
33
float32 float32_log2(float32, float_status *status);
34
@@ -XXX,XX +XXX,XX @@ float64 float64_mul(float64, float64, float_status *status);
35
float64 float64_div(float64, float64, float_status *status);
36
float64 float64_rem(float64, float64, float_status *status);
37
float64 float64_muladd(float64, float64, float64, int, float_status *status);
38
+float64 float64_muladd_scalbn(float64, float64, float64,
39
+ int, int, float_status *status);
40
float64 float64_sqrt(float64, float_status *status);
41
float64 float64_log2(float64, float_status *status);
42
FloatRelation float64_compare(float64, float64, float_status *status);
43
diff --git a/fpu/softfloat.c b/fpu/softfloat.c
44
index XXXXXXX..XXXXXXX 100644
45
--- a/fpu/softfloat.c
46
+++ b/fpu/softfloat.c
47
@@ -XXX,XX +XXX,XX @@ static FloatParts128 *parts128_mul(FloatParts128 *a, FloatParts128 *b,
48
#define parts_mul(A, B, S) \
49
PARTS_GENERIC_64_128(mul, A)(A, B, S)
50
51
-static FloatParts64 *parts64_muladd(FloatParts64 *a, FloatParts64 *b,
52
- FloatParts64 *c, int flags,
53
- float_status *s);
54
-static FloatParts128 *parts128_muladd(FloatParts128 *a, FloatParts128 *b,
55
- FloatParts128 *c, int flags,
56
- float_status *s);
57
+static FloatParts64 *parts64_muladd_scalbn(FloatParts64 *a, FloatParts64 *b,
58
+ FloatParts64 *c, int scale,
59
+ int flags, float_status *s);
60
+static FloatParts128 *parts128_muladd_scalbn(FloatParts128 *a, FloatParts128 *b,
61
+ FloatParts128 *c, int scale,
62
+ int flags, float_status *s);
63
64
-#define parts_muladd(A, B, C, Z, S) \
65
- PARTS_GENERIC_64_128(muladd, A)(A, B, C, Z, S)
66
+#define parts_muladd_scalbn(A, B, C, Z, Y, S) \
67
+ PARTS_GENERIC_64_128(muladd_scalbn, A)(A, B, C, Z, Y, S)
68
69
static FloatParts64 *parts64_div(FloatParts64 *a, FloatParts64 *b,
70
float_status *s);
71
@@ -XXX,XX +XXX,XX @@ floatx80_mul(floatx80 a, floatx80 b, float_status *status)
72
* Fused multiply-add
73
*/
74
75
-float16 QEMU_FLATTEN float16_muladd(float16 a, float16 b, float16 c,
76
- int flags, float_status *status)
77
+float16 QEMU_FLATTEN
78
+float16_muladd_scalbn(float16 a, float16 b, float16 c,
79
+ int scale, int flags, float_status *status)
80
{
81
FloatParts64 pa, pb, pc, *pr;
82
83
float16_unpack_canonical(&pa, a, status);
84
float16_unpack_canonical(&pb, b, status);
85
float16_unpack_canonical(&pc, c, status);
86
- pr = parts_muladd(&pa, &pb, &pc, flags, status);
87
+ pr = parts_muladd_scalbn(&pa, &pb, &pc, scale, flags, status);
88
89
return float16_round_pack_canonical(pr, status);
90
}
91
92
-static float32 QEMU_SOFTFLOAT_ATTR
93
-soft_f32_muladd(float32 a, float32 b, float32 c, int flags,
94
- float_status *status)
95
+float16 float16_muladd(float16 a, float16 b, float16 c,
96
+ int flags, float_status *status)
97
+{
98
+ return float16_muladd_scalbn(a, b, c, 0, flags, status);
99
+}
100
+
101
+float32 QEMU_SOFTFLOAT_ATTR
102
+float32_muladd_scalbn(float32 a, float32 b, float32 c,
103
+ int scale, int flags, float_status *status)
104
{
105
FloatParts64 pa, pb, pc, *pr;
106
107
float32_unpack_canonical(&pa, a, status);
108
float32_unpack_canonical(&pb, b, status);
109
float32_unpack_canonical(&pc, c, status);
110
- pr = parts_muladd(&pa, &pb, &pc, flags, status);
111
+ pr = parts_muladd_scalbn(&pa, &pb, &pc, scale, flags, status);
112
113
return float32_round_pack_canonical(pr, status);
114
}
115
116
-static float64 QEMU_SOFTFLOAT_ATTR
117
-soft_f64_muladd(float64 a, float64 b, float64 c, int flags,
118
- float_status *status)
119
+float64 QEMU_SOFTFLOAT_ATTR
120
+float64_muladd_scalbn(float64 a, float64 b, float64 c,
121
+ int scale, int flags, float_status *status)
122
{
123
FloatParts64 pa, pb, pc, *pr;
124
125
float64_unpack_canonical(&pa, a, status);
126
float64_unpack_canonical(&pb, b, status);
127
float64_unpack_canonical(&pc, c, status);
128
- pr = parts_muladd(&pa, &pb, &pc, flags, status);
129
+ pr = parts_muladd_scalbn(&pa, &pb, &pc, scale, flags, status);
130
131
return float64_round_pack_canonical(pr, status);
132
}
133
@@ -XXX,XX +XXX,XX @@ float32_muladd(float32 xa, float32 xb, float32 xc, int flags, float_status *s)
134
return ur.s;
135
136
soft:
137
- return soft_f32_muladd(ua.s, ub.s, uc.s, flags, s);
138
+ return float32_muladd_scalbn(ua.s, ub.s, uc.s, 0, flags, s);
139
}
140
141
float64 QEMU_FLATTEN
142
@@ -XXX,XX +XXX,XX @@ float64_muladd(float64 xa, float64 xb, float64 xc, int flags, float_status *s)
143
return ur.s;
144
145
soft:
146
- return soft_f64_muladd(ua.s, ub.s, uc.s, flags, s);
147
+ return float64_muladd_scalbn(ua.s, ub.s, uc.s, 0, flags, s);
148
}
149
150
float64 float64r32_muladd(float64 a, float64 b, float64 c,
151
@@ -XXX,XX +XXX,XX @@ float64 float64r32_muladd(float64 a, float64 b, float64 c,
152
float64_unpack_canonical(&pa, a, status);
153
float64_unpack_canonical(&pb, b, status);
154
float64_unpack_canonical(&pc, c, status);
155
- pr = parts_muladd(&pa, &pb, &pc, flags, status);
156
+ pr = parts_muladd_scalbn(&pa, &pb, &pc, 0, flags, status);
157
158
return float64r32_round_pack_canonical(pr, status);
159
}
160
@@ -XXX,XX +XXX,XX @@ bfloat16 QEMU_FLATTEN bfloat16_muladd(bfloat16 a, bfloat16 b, bfloat16 c,
161
bfloat16_unpack_canonical(&pa, a, status);
162
bfloat16_unpack_canonical(&pb, b, status);
163
bfloat16_unpack_canonical(&pc, c, status);
164
- pr = parts_muladd(&pa, &pb, &pc, flags, status);
165
+ pr = parts_muladd_scalbn(&pa, &pb, &pc, 0, flags, status);
166
167
return bfloat16_round_pack_canonical(pr, status);
168
}
169
@@ -XXX,XX +XXX,XX @@ float128 QEMU_FLATTEN float128_muladd(float128 a, float128 b, float128 c,
170
float128_unpack_canonical(&pa, a, status);
171
float128_unpack_canonical(&pb, b, status);
172
float128_unpack_canonical(&pc, c, status);
173
- pr = parts_muladd(&pa, &pb, &pc, flags, status);
174
+ pr = parts_muladd_scalbn(&pa, &pb, &pc, 0, flags, status);
175
176
return float128_round_pack_canonical(pr, status);
177
}
178
@@ -XXX,XX +XXX,XX @@ float32 float32_exp2(float32 a, float_status *status)
179
180
float64_unpack_canonical(&rp, float64_one, status);
181
for (i = 0 ; i < 15 ; i++) {
182
+
183
float64_unpack_canonical(&tp, float32_exp2_coefficients[i], status);
184
- rp = *parts_muladd(&tp, &xnp, &rp, 0, status);
185
+ rp = *parts_muladd_scalbn(&tp, &xnp, &rp, 0, 0, status);
186
xnp = *parts_mul(&xnp, &xp, status);
187
}
188
189
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
190
index XXXXXXX..XXXXXXX 100644
191
--- a/fpu/softfloat-parts.c.inc
192
+++ b/fpu/softfloat-parts.c.inc
193
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(mul)(FloatPartsN *a, FloatPartsN *b,
194
* Requires A and C extracted into a double-sized structure to provide the
195
* extra space for the widening multiply.
196
*/
197
-static FloatPartsN *partsN(muladd)(FloatPartsN *a, FloatPartsN *b,
198
- FloatPartsN *c, int flags, float_status *s)
199
+static FloatPartsN *partsN(muladd_scalbn)(FloatPartsN *a, FloatPartsN *b,
200
+ FloatPartsN *c, int scale,
201
+ int flags, float_status *s)
202
{
203
int ab_mask, abc_mask;
204
FloatPartsW p_widen, c_widen;
205
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(muladd)(FloatPartsN *a, FloatPartsN *b,
206
a->exp = p_widen.exp;
207
208
return_normal:
209
+ /* TODO: Replace all use of float_muladd_halve_result with scale. */
210
if (flags & float_muladd_halve_result) {
211
a->exp -= 1;
212
}
213
+ a->exp += scale;
214
finish_sign:
215
if (flags & float_muladd_negate_result) {
216
a->sign ^= 1;
217
--
218
2.43.0
219
220
diff view generated by jsdifflib
[PATCH 13/27] tcg/tci: Remove tci_read_r8s
[PULL 56/72] target/arm: Use float*_muladd_scalbn
1
Use explicit casts for ext8s opcodes.
1
Use the scalbn interface instead of float_muladd_halve_result.
2
2
3
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
3
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
---
5
---
6
tcg/tci.c | 25 ++++---------------------
6
target/arm/tcg/helper-a64.c | 6 +++---
7
1 file changed, 4 insertions(+), 21 deletions(-)
7
1 file changed, 3 insertions(+), 3 deletions(-)
8
8
9
diff --git a/tcg/tci.c b/tcg/tci.c
9
diff --git a/target/arm/tcg/helper-a64.c b/target/arm/tcg/helper-a64.c
10
index XXXXXXX..XXXXXXX 100644
10
index XXXXXXX..XXXXXXX 100644
11
--- a/tcg/tci.c
11
--- a/target/arm/tcg/helper-a64.c
12
+++ b/tcg/tci.c
12
+++ b/target/arm/tcg/helper-a64.c
13
@@ -XXX,XX +XXX,XX @@ static tcg_target_ulong tci_read_reg(const tcg_target_ulong *regs, TCGReg index)
13
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(rsqrtsf_f16)(uint32_t a, uint32_t b, float_status *fpst)
14
return regs[index];
14
(float16_is_infinity(b) && float16_is_zero(a))) {
15
return float16_one_point_five;
16
}
17
- return float16_muladd(a, b, float16_three, float_muladd_halve_result, fpst);
18
+ return float16_muladd_scalbn(a, b, float16_three, -1, 0, fpst);
15
}
19
}
16
20
17
-#if TCG_TARGET_HAS_ext8s_i32 || TCG_TARGET_HAS_ext8s_i64
21
float32 HELPER(rsqrtsf_f32)(float32 a, float32 b, float_status *fpst)
18
-static int8_t tci_read_reg8s(const tcg_target_ulong *regs, TCGReg index)
22
@@ -XXX,XX +XXX,XX @@ float32 HELPER(rsqrtsf_f32)(float32 a, float32 b, float_status *fpst)
19
-{
23
(float32_is_infinity(b) && float32_is_zero(a))) {
20
- return (int8_t)tci_read_reg(regs, index);
24
return float32_one_point_five;
21
-}
25
}
22
-#endif
26
- return float32_muladd(a, b, float32_three, float_muladd_halve_result, fpst);
23
-
27
+ return float32_muladd_scalbn(a, b, float32_three, -1, 0, fpst);
24
#if TCG_TARGET_HAS_ext16s_i32 || TCG_TARGET_HAS_ext16s_i64
25
static int16_t tci_read_reg16s(const tcg_target_ulong *regs, TCGReg index)
26
{
27
@@ -XXX,XX +XXX,XX @@ tci_read_r(const tcg_target_ulong *regs, const uint8_t **tb_ptr)
28
return value;
29
}
28
}
30
29
31
-#if TCG_TARGET_HAS_ext8s_i32 || TCG_TARGET_HAS_ext8s_i64
30
float64 HELPER(rsqrtsf_f64)(float64 a, float64 b, float_status *fpst)
32
-/* Read indexed register (8 bit signed) from bytecode. */
31
@@ -XXX,XX +XXX,XX @@ float64 HELPER(rsqrtsf_f64)(float64 a, float64 b, float_status *fpst)
33
-static int8_t tci_read_r8s(const tcg_target_ulong *regs, const uint8_t **tb_ptr)
32
(float64_is_infinity(b) && float64_is_zero(a))) {
34
-{
33
return float64_one_point_five;
35
- int8_t value = tci_read_reg8s(regs, **tb_ptr);
34
}
36
- *tb_ptr += 1;
35
- return float64_muladd(a, b, float64_three, float_muladd_halve_result, fpst);
37
- return value;
36
+ return float64_muladd_scalbn(a, b, float64_three, -1, 0, fpst);
38
-}
37
}
39
-#endif
38
40
-
39
/* Floating-point reciprocal exponent - see FPRecpX in ARM ARM */
41
/* Read indexed register (16 bit) from bytecode. */
42
static uint16_t tci_read_r16(const tcg_target_ulong *regs,
43
const uint8_t **tb_ptr)
44
@@ -XXX,XX +XXX,XX @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
45
#if TCG_TARGET_HAS_ext8s_i32
46
case INDEX_op_ext8s_i32:
47
t0 = *tb_ptr++;
48
- t1 = tci_read_r8s(regs, &tb_ptr);
49
- tci_write_reg(regs, t0, t1);
50
+ t1 = tci_read_r(regs, &tb_ptr);
51
+ tci_write_reg(regs, t0, (int8_t)t1);
52
break;
53
#endif
54
#if TCG_TARGET_HAS_ext16s_i32
55
@@ -XXX,XX +XXX,XX @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
56
#if TCG_TARGET_HAS_ext8s_i64
57
case INDEX_op_ext8s_i64:
58
t0 = *tb_ptr++;
59
- t1 = tci_read_r8s(regs, &tb_ptr);
60
- tci_write_reg(regs, t0, t1);
61
+ t1 = tci_read_r(regs, &tb_ptr);
62
+ tci_write_reg(regs, t0, (int8_t)t1);
63
break;
64
#endif
65
#if TCG_TARGET_HAS_ext16s_i64
66
--
40
--
67
2.25.1
41
2.43.0
68
42
69
43
diff view generated by jsdifflib
New patch
[PULL 57/72] target/sparc: Use float*_muladd_scalbn
1
1
Use the scalbn interface instead of float_muladd_halve_result.
2
3
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
---
6
target/sparc/helper.h | 4 +-
7
target/sparc/fop_helper.c | 8 ++--
8
target/sparc/translate.c | 80 +++++++++++++++++++++++----------------
9
3 files changed, 54 insertions(+), 38 deletions(-)
10
11
diff --git a/target/sparc/helper.h b/target/sparc/helper.h
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/sparc/helper.h
14
+++ b/target/sparc/helper.h
15
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(faddd, TCG_CALL_NO_WG, f64, env, f64, f64)
16
DEF_HELPER_FLAGS_3(fsubd, TCG_CALL_NO_WG, f64, env, f64, f64)
17
DEF_HELPER_FLAGS_3(fmuld, TCG_CALL_NO_WG, f64, env, f64, f64)
18
DEF_HELPER_FLAGS_3(fdivd, TCG_CALL_NO_WG, f64, env, f64, f64)
19
-DEF_HELPER_FLAGS_5(fmaddd, TCG_CALL_NO_WG, f64, env, f64, f64, f64, i32)
20
+DEF_HELPER_FLAGS_6(fmaddd, TCG_CALL_NO_WG, f64, env, f64, f64, f64, s32, i32)
21
DEF_HELPER_FLAGS_3(fnaddd, TCG_CALL_NO_WG, f64, env, f64, f64)
22
DEF_HELPER_FLAGS_3(fnmuld, TCG_CALL_NO_WG, f64, env, f64, f64)
23
24
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(fadds, TCG_CALL_NO_WG, f32, env, f32, f32)
25
DEF_HELPER_FLAGS_3(fsubs, TCG_CALL_NO_WG, f32, env, f32, f32)
26
DEF_HELPER_FLAGS_3(fmuls, TCG_CALL_NO_WG, f32, env, f32, f32)
27
DEF_HELPER_FLAGS_3(fdivs, TCG_CALL_NO_WG, f32, env, f32, f32)
28
-DEF_HELPER_FLAGS_5(fmadds, TCG_CALL_NO_WG, f32, env, f32, f32, f32, i32)
29
+DEF_HELPER_FLAGS_6(fmadds, TCG_CALL_NO_WG, f32, env, f32, f32, f32, s32, i32)
30
DEF_HELPER_FLAGS_3(fnadds, TCG_CALL_NO_WG, f32, env, f32, f32)
31
DEF_HELPER_FLAGS_3(fnmuls, TCG_CALL_NO_WG, f32, env, f32, f32)
32
33
diff --git a/target/sparc/fop_helper.c b/target/sparc/fop_helper.c
34
index XXXXXXX..XXXXXXX 100644
35
--- a/target/sparc/fop_helper.c
36
+++ b/target/sparc/fop_helper.c
37
@@ -XXX,XX +XXX,XX @@ Int128 helper_fsqrtq(CPUSPARCState *env, Int128 src)
38
}
39
40
float32 helper_fmadds(CPUSPARCState *env, float32 s1,
41
- float32 s2, float32 s3, uint32_t op)
42
+ float32 s2, float32 s3, int32_t sc, uint32_t op)
43
{
44
- float32 ret = float32_muladd(s1, s2, s3, op, &env->fp_status);
45
+ float32 ret = float32_muladd_scalbn(s1, s2, s3, sc, op, &env->fp_status);
46
check_ieee_exceptions(env, GETPC());
47
return ret;
48
}
49
50
float64 helper_fmaddd(CPUSPARCState *env, float64 s1,
51
- float64 s2, float64 s3, uint32_t op)
52
+ float64 s2, float64 s3, int32_t sc, uint32_t op)
53
{
54
- float64 ret = float64_muladd(s1, s2, s3, op, &env->fp_status);
55
+ float64 ret = float64_muladd_scalbn(s1, s2, s3, sc, op, &env->fp_status);
56
check_ieee_exceptions(env, GETPC());
57
return ret;
58
}
59
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
60
index XXXXXXX..XXXXXXX 100644
61
--- a/target/sparc/translate.c
62
+++ b/target/sparc/translate.c
63
@@ -XXX,XX +XXX,XX @@ static void gen_op_fabsq(TCGv_i128 dst, TCGv_i128 src)
64
65
static void gen_op_fmadds(TCGv_i32 d, TCGv_i32 s1, TCGv_i32 s2, TCGv_i32 s3)
66
{
67
- gen_helper_fmadds(d, tcg_env, s1, s2, s3, tcg_constant_i32(0));
68
+ TCGv_i32 z = tcg_constant_i32(0);
69
+ gen_helper_fmadds(d, tcg_env, s1, s2, s3, z, z);
70
}
71
72
static void gen_op_fmaddd(TCGv_i64 d, TCGv_i64 s1, TCGv_i64 s2, TCGv_i64 s3)
73
{
74
- gen_helper_fmaddd(d, tcg_env, s1, s2, s3, tcg_constant_i32(0));
75
+ TCGv_i32 z = tcg_constant_i32(0);
76
+ gen_helper_fmaddd(d, tcg_env, s1, s2, s3, z, z);
77
}
78
79
static void gen_op_fmsubs(TCGv_i32 d, TCGv_i32 s1, TCGv_i32 s2, TCGv_i32 s3)
80
{
81
- int op = float_muladd_negate_c;
82
- gen_helper_fmadds(d, tcg_env, s1, s2, s3, tcg_constant_i32(op));
83
+ TCGv_i32 z = tcg_constant_i32(0);
84
+ TCGv_i32 op = tcg_constant_i32(float_muladd_negate_c);
85
+ gen_helper_fmadds(d, tcg_env, s1, s2, s3, z, op);
86
}
87
88
static void gen_op_fmsubd(TCGv_i64 d, TCGv_i64 s1, TCGv_i64 s2, TCGv_i64 s3)
89
{
90
- int op = float_muladd_negate_c;
91
- gen_helper_fmaddd(d, tcg_env, s1, s2, s3, tcg_constant_i32(op));
92
+ TCGv_i32 z = tcg_constant_i32(0);
93
+ TCGv_i32 op = tcg_constant_i32(float_muladd_negate_c);
94
+ gen_helper_fmaddd(d, tcg_env, s1, s2, s3, z, op);
95
}
96
97
static void gen_op_fnmsubs(TCGv_i32 d, TCGv_i32 s1, TCGv_i32 s2, TCGv_i32 s3)
98
{
99
- int op = float_muladd_negate_c | float_muladd_negate_result;
100
- gen_helper_fmadds(d, tcg_env, s1, s2, s3, tcg_constant_i32(op));
101
+ TCGv_i32 z = tcg_constant_i32(0);
102
+ TCGv_i32 op = tcg_constant_i32(float_muladd_negate_c |
103
+ float_muladd_negate_result);
104
+ gen_helper_fmadds(d, tcg_env, s1, s2, s3, z, op);
105
}
106
107
static void gen_op_fnmsubd(TCGv_i64 d, TCGv_i64 s1, TCGv_i64 s2, TCGv_i64 s3)
108
{
109
- int op = float_muladd_negate_c | float_muladd_negate_result;
110
- gen_helper_fmaddd(d, tcg_env, s1, s2, s3, tcg_constant_i32(op));
111
+ TCGv_i32 z = tcg_constant_i32(0);
112
+ TCGv_i32 op = tcg_constant_i32(float_muladd_negate_c |
113
+ float_muladd_negate_result);
114
+ gen_helper_fmaddd(d, tcg_env, s1, s2, s3, z, op);
115
}
116
117
static void gen_op_fnmadds(TCGv_i32 d, TCGv_i32 s1, TCGv_i32 s2, TCGv_i32 s3)
118
{
119
- int op = float_muladd_negate_result;
120
- gen_helper_fmadds(d, tcg_env, s1, s2, s3, tcg_constant_i32(op));
121
+ TCGv_i32 z = tcg_constant_i32(0);
122
+ TCGv_i32 op = tcg_constant_i32(float_muladd_negate_result);
123
+ gen_helper_fmadds(d, tcg_env, s1, s2, s3, z, op);
124
}
125
126
static void gen_op_fnmaddd(TCGv_i64 d, TCGv_i64 s1, TCGv_i64 s2, TCGv_i64 s3)
127
{
128
- int op = float_muladd_negate_result;
129
- gen_helper_fmaddd(d, tcg_env, s1, s2, s3, tcg_constant_i32(op));
130
+ TCGv_i32 z = tcg_constant_i32(0);
131
+ TCGv_i32 op = tcg_constant_i32(float_muladd_negate_result);
132
+ gen_helper_fmaddd(d, tcg_env, s1, s2, s3, z, op);
133
}
134
135
/* Use muladd to compute (1 * src1) + src2 / 2 with one rounding. */
136
static void gen_op_fhadds(TCGv_i32 d, TCGv_i32 s1, TCGv_i32 s2)
137
{
138
- TCGv_i32 one = tcg_constant_i32(float32_one);
139
- int op = float_muladd_halve_result;
140
- gen_helper_fmadds(d, tcg_env, one, s1, s2, tcg_constant_i32(op));
141
+ TCGv_i32 fone = tcg_constant_i32(float32_one);
142
+ TCGv_i32 mone = tcg_constant_i32(-1);
143
+ TCGv_i32 op = tcg_constant_i32(0);
144
+ gen_helper_fmadds(d, tcg_env, fone, s1, s2, mone, op);
145
}
146
147
static void gen_op_fhaddd(TCGv_i64 d, TCGv_i64 s1, TCGv_i64 s2)
148
{
149
- TCGv_i64 one = tcg_constant_i64(float64_one);
150
- int op = float_muladd_halve_result;
151
- gen_helper_fmaddd(d, tcg_env, one, s1, s2, tcg_constant_i32(op));
152
+ TCGv_i64 fone = tcg_constant_i64(float64_one);
153
+ TCGv_i32 mone = tcg_constant_i32(-1);
154
+ TCGv_i32 op = tcg_constant_i32(0);
155
+ gen_helper_fmaddd(d, tcg_env, fone, s1, s2, mone, op);
156
}
157
158
/* Use muladd to compute (1 * src1) - src2 / 2 with one rounding. */
159
static void gen_op_fhsubs(TCGv_i32 d, TCGv_i32 s1, TCGv_i32 s2)
160
{
161
- TCGv_i32 one = tcg_constant_i32(float32_one);
162
- int op = float_muladd_negate_c | float_muladd_halve_result;
163
- gen_helper_fmadds(d, tcg_env, one, s1, s2, tcg_constant_i32(op));
164
+ TCGv_i32 fone = tcg_constant_i32(float32_one);
165
+ TCGv_i32 mone = tcg_constant_i32(-1);
166
+ TCGv_i32 op = tcg_constant_i32(float_muladd_negate_c);
167
+ gen_helper_fmadds(d, tcg_env, fone, s1, s2, mone, op);
168
}
169
170
static void gen_op_fhsubd(TCGv_i64 d, TCGv_i64 s1, TCGv_i64 s2)
171
{
172
- TCGv_i64 one = tcg_constant_i64(float64_one);
173
- int op = float_muladd_negate_c | float_muladd_halve_result;
174
- gen_helper_fmaddd(d, tcg_env, one, s1, s2, tcg_constant_i32(op));
175
+ TCGv_i64 fone = tcg_constant_i64(float64_one);
176
+ TCGv_i32 mone = tcg_constant_i32(-1);
177
+ TCGv_i32 op = tcg_constant_i32(float_muladd_negate_c);
178
+ gen_helper_fmaddd(d, tcg_env, fone, s1, s2, mone, op);
179
}
180
181
/* Use muladd to compute -((1 * src1) + src2 / 2) with one rounding. */
182
static void gen_op_fnhadds(TCGv_i32 d, TCGv_i32 s1, TCGv_i32 s2)
183
{
184
- TCGv_i32 one = tcg_constant_i32(float32_one);
185
- int op = float_muladd_negate_result | float_muladd_halve_result;
186
- gen_helper_fmadds(d, tcg_env, one, s1, s2, tcg_constant_i32(op));
187
+ TCGv_i32 fone = tcg_constant_i32(float32_one);
188
+ TCGv_i32 mone = tcg_constant_i32(-1);
189
+ TCGv_i32 op = tcg_constant_i32(float_muladd_negate_result);
190
+ gen_helper_fmadds(d, tcg_env, fone, s1, s2, mone, op);
191
}
192
193
static void gen_op_fnhaddd(TCGv_i64 d, TCGv_i64 s1, TCGv_i64 s2)
194
{
195
- TCGv_i64 one = tcg_constant_i64(float64_one);
196
- int op = float_muladd_negate_result | float_muladd_halve_result;
197
- gen_helper_fmaddd(d, tcg_env, one, s1, s2, tcg_constant_i32(op));
198
+ TCGv_i64 fone = tcg_constant_i64(float64_one);
199
+ TCGv_i32 mone = tcg_constant_i32(-1);
200
+ TCGv_i32 op = tcg_constant_i32(float_muladd_negate_result);
201
+ gen_helper_fmaddd(d, tcg_env, fone, s1, s2, mone, op);
202
}
203
204
static void gen_op_fpexception_im(DisasContext *dc, int ftt)
205
--
206
2.43.0
207
208
diff view generated by jsdifflib
[PATCH 22/27] tcg/tci: Merge mov, not and neg operations
[PULL 58/72] softfloat: Remove float_muladd_halve_result
1
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
All uses have been convered to float*_muladd_scalbn.
2
3
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
3
---
5
---
4
tcg/tci.c | 29 +++++------------------------
6
include/fpu/softfloat.h | 3 ---
5
1 file changed, 5 insertions(+), 24 deletions(-)
7
fpu/softfloat.c | 6 ------
8
fpu/softfloat-parts.c.inc | 4 ----
9
3 files changed, 13 deletions(-)
6
10
7
diff --git a/tcg/tci.c b/tcg/tci.c
11
diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h
8
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
9
--- a/tcg/tci.c
13
--- a/include/fpu/softfloat.h
10
+++ b/tcg/tci.c
14
+++ b/include/fpu/softfloat.h
11
@@ -XXX,XX +XXX,XX @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
15
@@ -XXX,XX +XXX,XX @@ bfloat16 bfloat16_squash_input_denormal(bfloat16 a, float_status *status);
12
tci_write_reg(regs, t0, tci_compare64(t1, t2, condition));
16
| Using these differs from negating an input or output before calling
13
break;
17
| the muladd function in that this means that a NaN doesn't have its
14
#endif
18
| sign bit inverted before it is propagated.
15
- case INDEX_op_mov_i32:
19
-| We also support halving the result before rounding, as a special
16
+ CASE_32_64(mov)
20
-| case to support the ARM fused-sqrt-step instruction FRSQRTS.
17
t0 = *tb_ptr++;
21
*----------------------------------------------------------------------------*/
18
t1 = tci_read_r(regs, &tb_ptr);
22
enum {
19
tci_write_reg(regs, t0, t1);
23
float_muladd_negate_c = 1,
20
@@ -XXX,XX +XXX,XX @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
24
float_muladd_negate_product = 2,
21
tci_write_reg(regs, t0, bswap32(t1));
25
float_muladd_negate_result = 4,
22
break;
26
- float_muladd_halve_result = 8,
23
#endif
27
};
24
-#if TCG_TARGET_HAS_not_i32
28
25
- case INDEX_op_not_i32:
29
/*----------------------------------------------------------------------------
26
+#if TCG_TARGET_HAS_not_i32 || TCG_TARGET_HAS_not_i64
30
diff --git a/fpu/softfloat.c b/fpu/softfloat.c
27
+ CASE_32_64(not)
31
index XXXXXXX..XXXXXXX 100644
28
t0 = *tb_ptr++;
32
--- a/fpu/softfloat.c
29
t1 = tci_read_r(regs, &tb_ptr);
33
+++ b/fpu/softfloat.c
30
tci_write_reg(regs, t0, ~t1);
34
@@ -XXX,XX +XXX,XX @@ float32_muladd(float32 xa, float32 xb, float32 xc, int flags, float_status *s)
31
break;
35
if (unlikely(!can_use_fpu(s))) {
32
#endif
36
goto soft;
33
-#if TCG_TARGET_HAS_neg_i32
37
}
34
- case INDEX_op_neg_i32:
38
- if (unlikely(flags & float_muladd_halve_result)) {
35
+#if TCG_TARGET_HAS_neg_i32 || TCG_TARGET_HAS_neg_i64
39
- goto soft;
36
+ CASE_32_64(neg)
40
- }
37
t0 = *tb_ptr++;
41
38
t1 = tci_read_r(regs, &tb_ptr);
42
float32_input_flush3(&ua.s, &ub.s, &uc.s, s);
39
tci_write_reg(regs, t0, -t1);
43
if (unlikely(!f32_is_zon3(ua, ub, uc))) {
40
break;
44
@@ -XXX,XX +XXX,XX @@ float64_muladd(float64 xa, float64 xb, float64 xc, int flags, float_status *s)
41
#endif
45
if (unlikely(!can_use_fpu(s))) {
42
#if TCG_TARGET_REG_BITS == 64
46
goto soft;
43
- case INDEX_op_mov_i64:
47
}
44
- t0 = *tb_ptr++;
48
- if (unlikely(flags & float_muladd_halve_result)) {
45
- t1 = tci_read_r(regs, &tb_ptr);
49
- goto soft;
46
- tci_write_reg(regs, t0, t1);
50
- }
47
- break;
51
48
case INDEX_op_tci_movi_i64:
52
float64_input_flush3(&ua.s, &ub.s, &uc.s, s);
49
t0 = *tb_ptr++;
53
if (unlikely(!f64_is_zon3(ua, ub, uc))) {
50
t1 = tci_read_i64(&tb_ptr);
54
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
51
@@ -XXX,XX +XXX,XX @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
55
index XXXXXXX..XXXXXXX 100644
52
tci_write_reg(regs, t0, bswap64(t1));
56
--- a/fpu/softfloat-parts.c.inc
53
break;
57
+++ b/fpu/softfloat-parts.c.inc
54
#endif
58
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(muladd_scalbn)(FloatPartsN *a, FloatPartsN *b,
55
-#if TCG_TARGET_HAS_not_i64
59
a->exp = p_widen.exp;
56
- case INDEX_op_not_i64:
60
57
- t0 = *tb_ptr++;
61
return_normal:
58
- t1 = tci_read_r(regs, &tb_ptr);
62
- /* TODO: Replace all use of float_muladd_halve_result with scale. */
59
- tci_write_reg(regs, t0, ~t1);
63
- if (flags & float_muladd_halve_result) {
60
- break;
64
- a->exp -= 1;
61
-#endif
65
- }
62
-#if TCG_TARGET_HAS_neg_i64
66
a->exp += scale;
63
- case INDEX_op_neg_i64:
67
finish_sign:
64
- t0 = *tb_ptr++;
68
if (flags & float_muladd_negate_result) {
65
- t1 = tci_read_r(regs, &tb_ptr);
66
- tci_write_reg(regs, t0, -t1);
67
- break;
68
-#endif
69
#endif /* TCG_TARGET_REG_BITS == 64 */
70
71
/* QEMU specific operations. */
72
--
69
--
73
2.25.1
70
2.43.0
74
71
75
72
diff view generated by jsdifflib
New patch
[PULL 59/72] softfloat: Add float_round_nearest_even_max
1
This rounding mode is used by Hexagon.
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
---
5
include/fpu/softfloat-types.h | 2 ++
6
fpu/softfloat-parts.c.inc | 3 +++
7
2 files changed, 5 insertions(+)
8
9
diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h
10
index XXXXXXX..XXXXXXX 100644
11
--- a/include/fpu/softfloat-types.h
12
+++ b/include/fpu/softfloat-types.h
13
@@ -XXX,XX +XXX,XX @@ typedef enum __attribute__((__packed__)) {
14
float_round_to_odd = 5,
15
/* Not an IEEE rounding mode: round to closest odd, overflow to inf */
16
float_round_to_odd_inf = 6,
17
+ /* Not an IEEE rounding mode: round to nearest even, overflow to max */
18
+ float_round_nearest_even_max = 7,
19
} FloatRoundMode;
20
21
/*
22
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
23
index XXXXXXX..XXXXXXX 100644
24
--- a/fpu/softfloat-parts.c.inc
25
+++ b/fpu/softfloat-parts.c.inc
26
@@ -XXX,XX +XXX,XX @@ static void partsN(uncanon_normal)(FloatPartsN *p, float_status *s,
27
int exp, flags = 0;
28
29
switch (s->float_rounding_mode) {
30
+ case float_round_nearest_even_max:
31
+ overflow_norm = true;
32
+ /* fall through */
33
case float_round_nearest_even:
34
if (N > 64 && frac_lsb == 0) {
35
inc = ((p->frac_hi & 1) || (p->frac_lo & round_mask) != frac_lsbm1
36
--
37
2.43.0
diff view generated by jsdifflib
New patch
[PULL 60/72] softfloat: Add float_muladd_suppress_add_product_zero
1
Certain Hexagon instructions suppress changes to the result
2
when the product of fma() is a true zero.
1
3
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
---
6
include/fpu/softfloat.h | 5 +++++
7
fpu/softfloat.c | 3 +++
8
fpu/softfloat-parts.c.inc | 4 +++-
9
3 files changed, 11 insertions(+), 1 deletion(-)
10
11
diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h
12
index XXXXXXX..XXXXXXX 100644
13
--- a/include/fpu/softfloat.h
14
+++ b/include/fpu/softfloat.h
15
@@ -XXX,XX +XXX,XX @@ bfloat16 bfloat16_squash_input_denormal(bfloat16 a, float_status *status);
16
| Using these differs from negating an input or output before calling
17
| the muladd function in that this means that a NaN doesn't have its
18
| sign bit inverted before it is propagated.
19
+|
20
+| With float_muladd_suppress_add_product_zero, if A or B is zero
21
+| such that the product is a true zero, then return C without addition.
22
+| This preserves the sign of C when C is +/- 0. Used for Hexagon.
23
*----------------------------------------------------------------------------*/
24
enum {
25
float_muladd_negate_c = 1,
26
float_muladd_negate_product = 2,
27
float_muladd_negate_result = 4,
28
+ float_muladd_suppress_add_product_zero = 8,
29
};
30
31
/*----------------------------------------------------------------------------
32
diff --git a/fpu/softfloat.c b/fpu/softfloat.c
33
index XXXXXXX..XXXXXXX 100644
34
--- a/fpu/softfloat.c
35
+++ b/fpu/softfloat.c
36
@@ -XXX,XX +XXX,XX @@ float32_muladd(float32 xa, float32 xb, float32 xc, int flags, float_status *s)
37
if (unlikely(!can_use_fpu(s))) {
38
goto soft;
39
}
40
+ if (unlikely(flags & float_muladd_suppress_add_product_zero)) {
41
+ goto soft;
42
+ }
43
44
float32_input_flush3(&ua.s, &ub.s, &uc.s, s);
45
if (unlikely(!f32_is_zon3(ua, ub, uc))) {
46
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
47
index XXXXXXX..XXXXXXX 100644
48
--- a/fpu/softfloat-parts.c.inc
49
+++ b/fpu/softfloat-parts.c.inc
50
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(muladd_scalbn)(FloatPartsN *a, FloatPartsN *b,
51
goto return_normal;
52
}
53
if (c->cls == float_class_zero) {
54
- if (a->sign != c->sign) {
55
+ if (flags & float_muladd_suppress_add_product_zero) {
56
+ a->sign = c->sign;
57
+ } else if (a->sign != c->sign) {
58
goto return_sub_zero;
59
}
60
goto return_zero;
61
--
62
2.43.0
diff view generated by jsdifflib
[PATCH 17/27] tcg/tci: Remove tci_read_r32s
[PULL 61/72] target/hexagon: Use float32_mul in helper_sfmpy
1
Use explicit casts for ext32s opcodes.
1
There are no special cases for this instruction.
2
Remove internal_mpyf as unused.
2
3
3
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
4
Reviewed-by: Brian Cain <brian.cain@oss.qualcomm.com>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
---
6
---
6
tcg/tci.c | 20 ++------------------
7
target/hexagon/fma_emu.h | 1 -
7
1 file changed, 2 insertions(+), 18 deletions(-)
8
target/hexagon/fma_emu.c | 8 --------
9
target/hexagon/op_helper.c | 2 +-
10
3 files changed, 1 insertion(+), 10 deletions(-)
8
11
9
diff --git a/tcg/tci.c b/tcg/tci.c
12
diff --git a/target/hexagon/fma_emu.h b/target/hexagon/fma_emu.h
10
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
11
--- a/tcg/tci.c
14
--- a/target/hexagon/fma_emu.h
12
+++ b/tcg/tci.c
15
+++ b/target/hexagon/fma_emu.h
13
@@ -XXX,XX +XXX,XX @@ static tcg_target_ulong tci_read_reg(const tcg_target_ulong *regs, TCGReg index)
16
@@ -XXX,XX +XXX,XX @@ int32_t float32_getexp(float32 f32);
14
return regs[index];
17
float32 infinite_float32(uint8_t sign);
18
float32 internal_fmafx(float32 a, float32 b, float32 c,
19
int scale, float_status *fp_status);
20
-float32 internal_mpyf(float32 a, float32 b, float_status *fp_status);
21
float64 internal_mpyhh(float64 a, float64 b,
22
unsigned long long int accumulated,
23
float_status *fp_status);
24
diff --git a/target/hexagon/fma_emu.c b/target/hexagon/fma_emu.c
25
index XXXXXXX..XXXXXXX 100644
26
--- a/target/hexagon/fma_emu.c
27
+++ b/target/hexagon/fma_emu.c
28
@@ -XXX,XX +XXX,XX @@ float32 internal_fmafx(float32 a, float32 b, float32 c, int scale,
29
return accum_round_float32(result, fp_status);
15
}
30
}
16
31
17
-#if TCG_TARGET_REG_BITS == 64
32
-float32 internal_mpyf(float32 a, float32 b, float_status *fp_status)
18
-static int32_t tci_read_reg32s(const tcg_target_ulong *regs, TCGReg index)
19
-{
33
-{
20
- return (int32_t)tci_read_reg(regs, index);
34
- if (float32_is_zero(a) || float32_is_zero(b)) {
21
-}
35
- return float32_mul(a, b, fp_status);
22
-#endif
36
- }
23
-
37
- return internal_fmafx(a, b, float32_zero, 0, fp_status);
24
#if TCG_TARGET_REG_BITS == 64
25
static uint64_t tci_read_reg64(const tcg_target_ulong *regs, TCGReg index)
26
{
27
@@ -XXX,XX +XXX,XX @@ static uint64_t tci_read_r64(const tcg_target_ulong *regs,
28
return tci_uint64(tci_read_r(regs, tb_ptr), low);
29
}
30
#elif TCG_TARGET_REG_BITS == 64
31
-/* Read indexed register (32 bit signed) from bytecode. */
32
-static int32_t tci_read_r32s(const tcg_target_ulong *regs,
33
- const uint8_t **tb_ptr)
34
-{
35
- int32_t value = tci_read_reg32s(regs, **tb_ptr);
36
- *tb_ptr += 1;
37
- return value;
38
-}
38
-}
39
-
39
-
40
/* Read indexed register (64 bit) from bytecode. */
40
float64 internal_mpyhh(float64 a, float64 b,
41
static uint64_t tci_read_r64(const tcg_target_ulong *regs,
41
unsigned long long int accumulated,
42
const uint8_t **tb_ptr)
42
float_status *fp_status)
43
@@ -XXX,XX +XXX,XX @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
43
diff --git a/target/hexagon/op_helper.c b/target/hexagon/op_helper.c
44
#endif
44
index XXXXXXX..XXXXXXX 100644
45
case INDEX_op_ext_i32_i64:
45
--- a/target/hexagon/op_helper.c
46
t0 = *tb_ptr++;
46
+++ b/target/hexagon/op_helper.c
47
- t1 = tci_read_r32s(regs, &tb_ptr);
47
@@ -XXX,XX +XXX,XX @@ float32 HELPER(sfmpy)(CPUHexagonState *env, float32 RsV, float32 RtV)
48
- tci_write_reg(regs, t0, t1);
48
{
49
+ t1 = tci_read_r(regs, &tb_ptr);
49
float32 RdV;
50
+ tci_write_reg(regs, t0, (int32_t)t1);
50
arch_fpop_start(env);
51
break;
51
- RdV = internal_mpyf(RsV, RtV, &env->fp_status);
52
#if TCG_TARGET_HAS_ext32u_i64
52
+ RdV = float32_mul(RsV, RtV, &env->fp_status);
53
case INDEX_op_ext32u_i64:
53
arch_fpop_end(env);
54
return RdV;
55
}
54
--
56
--
55
2.25.1
57
2.43.0
56
57
diff view generated by jsdifflib
[PATCH 21/27] tcg/tci: Merge bswap operations
[PULL 62/72] target/hexagon: Use float32_muladd for helper_sffma
1
This includes bswap16 and bswap32.
1
There are no special cases for this instruction.
2
2
3
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
3
Reviewed-by: Brian Cain <brian.cain@oss.qualcomm.com>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
---
5
---
6
tcg/tci.c | 22 ++++------------------
6
target/hexagon/op_helper.c | 2 +-
7
1 file changed, 4 insertions(+), 18 deletions(-)
7
1 file changed, 1 insertion(+), 1 deletion(-)
8
8
9
diff --git a/tcg/tci.c b/tcg/tci.c
9
diff --git a/target/hexagon/op_helper.c b/target/hexagon/op_helper.c
10
index XXXXXXX..XXXXXXX 100644
10
index XXXXXXX..XXXXXXX 100644
11
--- a/tcg/tci.c
11
--- a/target/hexagon/op_helper.c
12
+++ b/tcg/tci.c
12
+++ b/target/hexagon/op_helper.c
13
@@ -XXX,XX +XXX,XX @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
13
@@ -XXX,XX +XXX,XX @@ float32 HELPER(sffma)(CPUHexagonState *env, float32 RxV,
14
tci_write_reg(regs, t0, (uint16_t)t1);
14
float32 RsV, float32 RtV)
15
break;
15
{
16
#endif
16
arch_fpop_start(env);
17
-#if TCG_TARGET_HAS_bswap16_i32
17
- RxV = internal_fmafx(RsV, RtV, RxV, 0, &env->fp_status);
18
- case INDEX_op_bswap16_i32:
18
+ RxV = float32_muladd(RsV, RtV, RxV, 0, &env->fp_status);
19
+#if TCG_TARGET_HAS_bswap16_i32 || TCG_TARGET_HAS_bswap16_i64
19
arch_fpop_end(env);
20
+ CASE_32_64(bswap16)
20
return RxV;
21
t0 = *tb_ptr++;
21
}
22
t1 = tci_read_r(regs, &tb_ptr);
23
tci_write_reg(regs, t0, bswap16(t1));
24
break;
25
#endif
26
-#if TCG_TARGET_HAS_bswap32_i32
27
- case INDEX_op_bswap32_i32:
28
+#if TCG_TARGET_HAS_bswap32_i32 || TCG_TARGET_HAS_bswap32_i64
29
+ CASE_32_64(bswap32)
30
t0 = *tb_ptr++;
31
t1 = tci_read_r(regs, &tb_ptr);
32
tci_write_reg(regs, t0, bswap32(t1));
33
@@ -XXX,XX +XXX,XX @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
34
t1 = tci_read_r(regs, &tb_ptr);
35
tci_write_reg(regs, t0, (uint32_t)t1);
36
break;
37
-#if TCG_TARGET_HAS_bswap16_i64
38
- case INDEX_op_bswap16_i64:
39
- t0 = *tb_ptr++;
40
- t1 = tci_read_r(regs, &tb_ptr);
41
- tci_write_reg(regs, t0, bswap16(t1));
42
- break;
43
-#endif
44
-#if TCG_TARGET_HAS_bswap32_i64
45
- case INDEX_op_bswap32_i64:
46
- t0 = *tb_ptr++;
47
- t1 = tci_read_r(regs, &tb_ptr);
48
- tci_write_reg(regs, t0, bswap32(t1));
49
- break;
50
-#endif
51
#if TCG_TARGET_HAS_bswap64_i64
52
case INDEX_op_bswap64_i64:
53
t0 = *tb_ptr++;
54
--
22
--
55
2.25.1
23
2.43.0
56
57
diff view generated by jsdifflib
[PATCH 20/27] tcg/tci: Merge extension operations
[PULL 63/72] target/hexagon: Use float32_muladd for helper_sffms
1
This includes ext8s, ext8u, ext16s, ext16u.
1
There are no special cases for this instruction. Since hexagon
2
always uses default-nan mode, explicitly negating the first
3
input is unnecessary. Use float_muladd_negate_product instead.
2
4
3
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
5
Reviewed-by: Brian Cain <brian.cain@oss.qualcomm.com>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
---
7
---
6
tcg/tci.c | 44 ++++++++------------------------------------
8
target/hexagon/op_helper.c | 5 ++---
7
1 file changed, 8 insertions(+), 36 deletions(-)
9
1 file changed, 2 insertions(+), 3 deletions(-)
8
10
9
diff --git a/tcg/tci.c b/tcg/tci.c
11
diff --git a/target/hexagon/op_helper.c b/target/hexagon/op_helper.c
10
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
11
--- a/tcg/tci.c
13
--- a/target/hexagon/op_helper.c
12
+++ b/tcg/tci.c
14
+++ b/target/hexagon/op_helper.c
13
@@ -XXX,XX +XXX,XX @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
15
@@ -XXX,XX +XXX,XX @@ float32 HELPER(sffma_sc)(CPUHexagonState *env, float32 RxV,
14
tci_write_reg64(regs, t1, t0, (uint32_t)t2 * tmp64);
16
float32 HELPER(sffms)(CPUHexagonState *env, float32 RxV,
15
break;
17
float32 RsV, float32 RtV)
16
#endif /* TCG_TARGET_REG_BITS == 32 */
18
{
17
-#if TCG_TARGET_HAS_ext8s_i32
19
- float32 neg_RsV;
18
- case INDEX_op_ext8s_i32:
20
arch_fpop_start(env);
19
+#if TCG_TARGET_HAS_ext8s_i32 || TCG_TARGET_HAS_ext8s_i64
21
- neg_RsV = float32_set_sign(RsV, float32_is_neg(RsV) ? 0 : 1);
20
+ CASE_32_64(ext8s)
22
- RxV = internal_fmafx(neg_RsV, RtV, RxV, 0, &env->fp_status);
21
t0 = *tb_ptr++;
23
+ RxV = float32_muladd(RsV, RtV, RxV, float_muladd_negate_product,
22
t1 = tci_read_r(regs, &tb_ptr);
24
+ &env->fp_status);
23
tci_write_reg(regs, t0, (int8_t)t1);
25
arch_fpop_end(env);
24
break;
26
return RxV;
25
#endif
27
}
26
-#if TCG_TARGET_HAS_ext16s_i32
27
- case INDEX_op_ext16s_i32:
28
+#if TCG_TARGET_HAS_ext16s_i32 || TCG_TARGET_HAS_ext16s_i64
29
+ CASE_32_64(ext16s)
30
t0 = *tb_ptr++;
31
t1 = tci_read_r(regs, &tb_ptr);
32
tci_write_reg(regs, t0, (int16_t)t1);
33
break;
34
#endif
35
-#if TCG_TARGET_HAS_ext8u_i32
36
- case INDEX_op_ext8u_i32:
37
+#if TCG_TARGET_HAS_ext8u_i32 || TCG_TARGET_HAS_ext8u_i64
38
+ CASE_32_64(ext8u)
39
t0 = *tb_ptr++;
40
t1 = tci_read_r(regs, &tb_ptr);
41
tci_write_reg(regs, t0, (uint8_t)t1);
42
break;
43
#endif
44
-#if TCG_TARGET_HAS_ext16u_i32
45
- case INDEX_op_ext16u_i32:
46
+#if TCG_TARGET_HAS_ext16u_i32 || TCG_TARGET_HAS_ext16u_i64
47
+ CASE_32_64(ext16u)
48
t0 = *tb_ptr++;
49
t1 = tci_read_r(regs, &tb_ptr);
50
tci_write_reg(regs, t0, (uint16_t)t1);
51
@@ -XXX,XX +XXX,XX @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
52
continue;
53
}
54
break;
55
-#if TCG_TARGET_HAS_ext8u_i64
56
- case INDEX_op_ext8u_i64:
57
- t0 = *tb_ptr++;
58
- t1 = tci_read_r(regs, &tb_ptr);
59
- tci_write_reg(regs, t0, (uint8_t)t1);
60
- break;
61
-#endif
62
-#if TCG_TARGET_HAS_ext8s_i64
63
- case INDEX_op_ext8s_i64:
64
- t0 = *tb_ptr++;
65
- t1 = tci_read_r(regs, &tb_ptr);
66
- tci_write_reg(regs, t0, (int8_t)t1);
67
- break;
68
-#endif
69
-#if TCG_TARGET_HAS_ext16s_i64
70
- case INDEX_op_ext16s_i64:
71
- t0 = *tb_ptr++;
72
- t1 = tci_read_r(regs, &tb_ptr);
73
- tci_write_reg(regs, t0, (int16_t)t1);
74
- break;
75
-#endif
76
-#if TCG_TARGET_HAS_ext16u_i64
77
- case INDEX_op_ext16u_i64:
78
- t0 = *tb_ptr++;
79
- t1 = tci_read_r(regs, &tb_ptr);
80
- tci_write_reg(regs, t0, (uint16_t)t1);
81
- break;
82
-#endif
83
#if TCG_TARGET_HAS_ext32s_i64
84
case INDEX_op_ext32s_i64:
85
#endif
86
--
28
--
87
2.25.1
29
2.43.0
88
89
diff view generated by jsdifflib
[PATCH 11/27] tcg/tci: Merge identical cases in generation (load/store opcodes)
[PULL 64/72] target/hexagon: Use float32_muladd_scalbn for helper_sffma_sc
1
Use CASE_32_64 and CASE_64 to reduce ifdefs and merge
1
This instruction has a special case that 0 * x + c returns c
2
cases that are identical between 32-bit and 64-bit hosts.
2
without the normal sign folding that comes with 0 + -0.
3
Use the new float_muladd_suppress_add_product_zero to
4
describe this.
3
5
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Reviewed-by: Brian Cain <brian.cain@oss.qualcomm.com>
5
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
6
Message-Id: <20210217202036.1724901-5-richard.henderson@linaro.org>
7
[PMD: Split patch as 5/5]
8
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
Message-Id: <20210218232840.1760806-6-f4bug@amsat.org>
10
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
11
---
8
---
12
tcg/tci/tcg-target.c.inc | 49 ++++++++++++----------------------------
9
target/hexagon/op_helper.c | 11 +++--------
13
1 file changed, 14 insertions(+), 35 deletions(-)
10
1 file changed, 3 insertions(+), 8 deletions(-)
14
11
15
diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
12
diff --git a/target/hexagon/op_helper.c b/target/hexagon/op_helper.c
16
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
17
--- a/tcg/tci/tcg-target.c.inc
14
--- a/target/hexagon/op_helper.c
18
+++ b/tcg/tci/tcg-target.c.inc
15
+++ b/target/hexagon/op_helper.c
19
@@ -XXX,XX +XXX,XX @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
16
@@ -XXX,XX +XXX,XX @@ static float32 check_nan(float32 dst, float32 x, float_status *fp_status)
20
tcg_out8(s, args[5]); /* condition */
17
float32 HELPER(sffma_sc)(CPUHexagonState *env, float32 RxV,
21
break;
18
float32 RsV, float32 RtV, float32 PuV)
22
#endif
19
{
23
- case INDEX_op_ld8u_i32:
20
- size4s_t tmp;
24
- case INDEX_op_ld8s_i32:
21
arch_fpop_start(env);
25
- case INDEX_op_ld16u_i32:
22
- RxV = check_nan(RxV, RxV, &env->fp_status);
26
- case INDEX_op_ld16s_i32:
23
- RxV = check_nan(RxV, RsV, &env->fp_status);
27
+
24
- RxV = check_nan(RxV, RtV, &env->fp_status);
28
+ CASE_32_64(ld8u)
25
- tmp = internal_fmafx(RsV, RtV, RxV, fSXTN(8, 64, PuV), &env->fp_status);
29
+ CASE_32_64(ld8s)
26
- if (!(float32_is_zero(RxV) && is_zero_prod(RsV, RtV))) {
30
+ CASE_32_64(ld16u)
27
- RxV = tmp;
31
+ CASE_32_64(ld16s)
28
- }
32
case INDEX_op_ld_i32:
29
+ RxV = float32_muladd_scalbn(RsV, RtV, RxV, fSXTN(8, 64, PuV),
33
- case INDEX_op_st8_i32:
30
+ float_muladd_suppress_add_product_zero,
34
- case INDEX_op_st16_i32:
31
+ &env->fp_status);
35
+ CASE_64(ld32u)
32
arch_fpop_end(env);
36
+ CASE_64(ld32s)
33
return RxV;
37
+ CASE_64(ld)
34
}
38
+ CASE_32_64(st8)
39
+ CASE_32_64(st16)
40
case INDEX_op_st_i32:
41
- case INDEX_op_ld8u_i64:
42
- case INDEX_op_ld8s_i64:
43
- case INDEX_op_ld16u_i64:
44
- case INDEX_op_ld16s_i64:
45
- case INDEX_op_ld32u_i64:
46
- case INDEX_op_ld32s_i64:
47
- case INDEX_op_ld_i64:
48
- case INDEX_op_st8_i64:
49
- case INDEX_op_st16_i64:
50
- case INDEX_op_st32_i64:
51
- case INDEX_op_st_i64:
52
+ CASE_64(st32)
53
+ CASE_64(st)
54
stack_bounds_check(args[1], args[2]);
55
tcg_out_r(s, args[0]);
56
tcg_out_r(s, args[1]);
57
@@ -XXX,XX +XXX,XX @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
58
#endif
59
60
case INDEX_op_qemu_ld_i32:
61
- tcg_out_r(s, *args++);
62
- tcg_out_r(s, *args++);
63
- if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) {
64
- tcg_out_r(s, *args++);
65
- }
66
- tcg_out_i(s, *args++);
67
- break;
68
- case INDEX_op_qemu_ld_i64:
69
- tcg_out_r(s, *args++);
70
- if (TCG_TARGET_REG_BITS == 32) {
71
- tcg_out_r(s, *args++);
72
- }
73
- tcg_out_r(s, *args++);
74
- if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) {
75
- tcg_out_r(s, *args++);
76
- }
77
- tcg_out_i(s, *args++);
78
- break;
79
case INDEX_op_qemu_st_i32:
80
tcg_out_r(s, *args++);
81
tcg_out_r(s, *args++);
82
@@ -XXX,XX +XXX,XX @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
83
}
84
tcg_out_i(s, *args++);
85
break;
86
+
87
+ case INDEX_op_qemu_ld_i64:
88
case INDEX_op_qemu_st_i64:
89
tcg_out_r(s, *args++);
90
if (TCG_TARGET_REG_BITS == 32) {
91
--
35
--
92
2.25.1
36
2.43.0
93
94
diff view generated by jsdifflib
[PATCH 06/27] tcg: Manage splitwx in tc_ptr_to_region_tree by hand
[PULL 65/72] target/hexagon: Use float32_muladd for helper_sffm[as]_lib
1
The use in tcg_tb_lookup is given a random pc that comes from the pc
1
There are multiple special cases for this instruction.
2
of a signal handler. Do not assert that the pointer is already within
2
(1) The saturate to normal maximum instead of overflow to infinity is
3
the code gen buffer at all, much less the writable mirror of it.
3
handled by the new float_round_nearest_even_max rounding mode.
4
(2) The 0 * n + c special case is handled by the new
5
float_muladd_suppress_add_product_zero flag.
6
(3) The Inf - Inf -> 0 special case can be detected after the fact
7
by examining float_flag_invalid_isi.
4
8
5
Fixes: db0c51a3803
9
Reviewed-by: Brian Cain <brian.cain@oss.qualcomm.com>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
---
11
---
8
tcg/tcg.c | 20 ++++++++++++++++++--
12
target/hexagon/op_helper.c | 105 +++++++++----------------------------
9
1 file changed, 18 insertions(+), 2 deletions(-)
13
1 file changed, 26 insertions(+), 79 deletions(-)
10
14
11
diff --git a/tcg/tcg.c b/tcg/tcg.c
15
diff --git a/target/hexagon/op_helper.c b/target/hexagon/op_helper.c
12
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
13
--- a/tcg/tcg.c
17
--- a/target/hexagon/op_helper.c
14
+++ b/tcg/tcg.c
18
+++ b/target/hexagon/op_helper.c
15
@@ -XXX,XX +XXX,XX @@ static void tcg_region_trees_init(void)
19
@@ -XXX,XX +XXX,XX @@ float32 HELPER(sffma)(CPUHexagonState *env, float32 RxV,
16
}
20
return RxV;
17
}
21
}
18
22
19
-static struct tcg_region_tree *tc_ptr_to_region_tree(const void *cp)
23
-static bool is_zero_prod(float32 a, float32 b)
20
+static struct tcg_region_tree *tc_ptr_to_region_tree(const void *p)
24
-{
25
- return ((float32_is_zero(a) && is_finite(b)) ||
26
- (float32_is_zero(b) && is_finite(a)));
27
-}
28
-
29
-static float32 check_nan(float32 dst, float32 x, float_status *fp_status)
30
-{
31
- float32 ret = dst;
32
- if (float32_is_any_nan(x)) {
33
- if (extract32(x, 22, 1) == 0) {
34
- float_raise(float_flag_invalid, fp_status);
35
- }
36
- ret = make_float32(0xffffffff); /* nan */
37
- }
38
- return ret;
39
-}
40
-
41
float32 HELPER(sffma_sc)(CPUHexagonState *env, float32 RxV,
42
float32 RsV, float32 RtV, float32 PuV)
21
{
43
{
22
- void *p = tcg_splitwx_to_rw(cp);
44
@@ -XXX,XX +XXX,XX @@ float32 HELPER(sffms)(CPUHexagonState *env, float32 RxV,
23
size_t region_idx;
45
return RxV;
24
46
}
25
+ /*
47
26
+ * Like tcg_splitwx_to_rw, with no assert. The pc may come from
48
-static bool is_inf_prod(int32_t a, int32_t b)
27
+ * a signal handler over which the caller has no control.
49
+static float32 do_sffma_lib(CPUHexagonState *env, float32 RxV,
28
+ */
50
+ float32 RsV, float32 RtV, int negate)
29
+ if (!in_code_gen_buffer(p)) {
51
{
30
+ p -= tcg_splitwx_diff;
52
- return (float32_is_infinity(a) && float32_is_infinity(b)) ||
31
+ if (!in_code_gen_buffer(p)) {
53
- (float32_is_infinity(a) && is_finite(b) && !float32_is_zero(b)) ||
32
+ return NULL;
54
- (float32_is_infinity(b) && is_finite(a) && !float32_is_zero(a));
55
+ int flags;
56
+
57
+ arch_fpop_start(env);
58
+
59
+ set_float_rounding_mode(float_round_nearest_even_max, &env->fp_status);
60
+ RxV = float32_muladd(RsV, RtV, RxV,
61
+ negate | float_muladd_suppress_add_product_zero,
62
+ &env->fp_status);
63
+
64
+ flags = get_float_exception_flags(&env->fp_status);
65
+ if (flags) {
66
+ /* Flags are suppressed by this instruction. */
67
+ set_float_exception_flags(0, &env->fp_status);
68
+
69
+ /* Return 0 for Inf - Inf. */
70
+ if (flags & float_flag_invalid_isi) {
71
+ RxV = 0;
33
+ }
72
+ }
34
+ }
73
+ }
35
+
74
+
36
if (p < region.start_aligned) {
75
+ arch_fpop_end(env);
37
region_idx = 0;
76
+ return RxV;
38
} else {
77
}
39
@@ -XXX,XX +XXX,XX @@ void tcg_tb_insert(TranslationBlock *tb)
78
79
float32 HELPER(sffma_lib)(CPUHexagonState *env, float32 RxV,
80
float32 RsV, float32 RtV)
40
{
81
{
41
struct tcg_region_tree *rt = tc_ptr_to_region_tree(tb->tc.ptr);
82
- bool infinp;
42
83
- bool infminusinf;
43
+ g_assert(rt != NULL);
84
- float32 tmp;
44
qemu_mutex_lock(&rt->lock);
85
-
45
g_tree_insert(rt->tree, &tb->tc, tb);
86
- arch_fpop_start(env);
46
qemu_mutex_unlock(&rt->lock);
87
- set_float_rounding_mode(float_round_nearest_even, &env->fp_status);
47
@@ -XXX,XX +XXX,XX @@ void tcg_tb_remove(TranslationBlock *tb)
88
- infminusinf = float32_is_infinity(RxV) &&
89
- is_inf_prod(RsV, RtV) &&
90
- (fGETBIT(31, RsV ^ RxV ^ RtV) != 0);
91
- infinp = float32_is_infinity(RxV) ||
92
- float32_is_infinity(RtV) ||
93
- float32_is_infinity(RsV);
94
- RxV = check_nan(RxV, RxV, &env->fp_status);
95
- RxV = check_nan(RxV, RsV, &env->fp_status);
96
- RxV = check_nan(RxV, RtV, &env->fp_status);
97
- tmp = internal_fmafx(RsV, RtV, RxV, 0, &env->fp_status);
98
- if (!(float32_is_zero(RxV) && is_zero_prod(RsV, RtV))) {
99
- RxV = tmp;
100
- }
101
- set_float_exception_flags(0, &env->fp_status);
102
- if (float32_is_infinity(RxV) && !infinp) {
103
- RxV = RxV - 1;
104
- }
105
- if (infminusinf) {
106
- RxV = 0;
107
- }
108
- arch_fpop_end(env);
109
- return RxV;
110
+ return do_sffma_lib(env, RxV, RsV, RtV, 0);
111
}
112
113
float32 HELPER(sffms_lib)(CPUHexagonState *env, float32 RxV,
114
float32 RsV, float32 RtV)
48
{
115
{
49
struct tcg_region_tree *rt = tc_ptr_to_region_tree(tb->tc.ptr);
116
- bool infinp;
50
117
- bool infminusinf;
51
+ g_assert(rt != NULL);
118
- float32 tmp;
52
qemu_mutex_lock(&rt->lock);
119
-
53
g_tree_remove(rt->tree, &tb->tc);
120
- arch_fpop_start(env);
54
qemu_mutex_unlock(&rt->lock);
121
- set_float_rounding_mode(float_round_nearest_even, &env->fp_status);
55
@@ -XXX,XX +XXX,XX @@ TranslationBlock *tcg_tb_lookup(uintptr_t tc_ptr)
122
- infminusinf = float32_is_infinity(RxV) &&
56
TranslationBlock *tb;
123
- is_inf_prod(RsV, RtV) &&
57
struct tb_tc s = { .ptr = (void *)tc_ptr };
124
- (fGETBIT(31, RsV ^ RxV ^ RtV) == 0);
58
125
- infinp = float32_is_infinity(RxV) ||
59
+ if (rt == NULL) {
126
- float32_is_infinity(RtV) ||
60
+ return NULL;
127
- float32_is_infinity(RsV);
61
+ }
128
- RxV = check_nan(RxV, RxV, &env->fp_status);
62
+
129
- RxV = check_nan(RxV, RsV, &env->fp_status);
63
qemu_mutex_lock(&rt->lock);
130
- RxV = check_nan(RxV, RtV, &env->fp_status);
64
tb = g_tree_lookup(rt->tree, &s);
131
- float32 minus_RsV = float32_sub(float32_zero, RsV, &env->fp_status);
65
qemu_mutex_unlock(&rt->lock);
132
- tmp = internal_fmafx(minus_RsV, RtV, RxV, 0, &env->fp_status);
133
- if (!(float32_is_zero(RxV) && is_zero_prod(RsV, RtV))) {
134
- RxV = tmp;
135
- }
136
- set_float_exception_flags(0, &env->fp_status);
137
- if (float32_is_infinity(RxV) && !infinp) {
138
- RxV = RxV - 1;
139
- }
140
- if (infminusinf) {
141
- RxV = 0;
142
- }
143
- arch_fpop_end(env);
144
- return RxV;
145
+ return do_sffma_lib(env, RxV, RsV, RtV, float_muladd_negate_product);
146
}
147
148
float64 HELPER(dfmpyfix)(CPUHexagonState *env, float64 RssV, float64 RttV)
66
--
149
--
67
2.25.1
150
2.43.0
68
69
diff view generated by jsdifflib
[PATCH 10/27] tcg/tci: Merge identical cases in generation (conditional opcodes)
[PULL 66/72] target/hexagon: Remove internal_fmafx
1
Use CASE_32_64 and CASE_64 to reduce ifdefs and merge
1
The function is now unused.
2
cases that are identical between 32-bit and 64-bit hosts.
3
2
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
3
Reviewed-by: Brian Cain <brian.cain@oss.qualcomm.com>
5
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
6
Message-Id: <20210217202036.1724901-5-richard.henderson@linaro.org>
7
[PMD: Split patch as 4/5]
8
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
Message-Id: <20210218232840.1760806-5-f4bug@amsat.org>
10
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
11
---
5
---
12
tcg/tci/tcg-target.c.inc | 23 ++++++-----------------
6
target/hexagon/fma_emu.h | 2 -
13
1 file changed, 6 insertions(+), 17 deletions(-)
7
target/hexagon/fma_emu.c | 171 ---------------------------------------
8
2 files changed, 173 deletions(-)
14
9
15
diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
10
diff --git a/target/hexagon/fma_emu.h b/target/hexagon/fma_emu.h
16
index XXXXXXX..XXXXXXX 100644
11
index XXXXXXX..XXXXXXX 100644
17
--- a/tcg/tci/tcg-target.c.inc
12
--- a/target/hexagon/fma_emu.h
18
+++ b/tcg/tci/tcg-target.c.inc
13
+++ b/target/hexagon/fma_emu.h
19
@@ -XXX,XX +XXX,XX @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
14
@@ -XXX,XX +XXX,XX @@ static inline uint32_t float32_getexp_raw(float32 f32)
20
}
15
}
21
set_jmp_reset_offset(s, args[0]);
16
int32_t float32_getexp(float32 f32);
22
break;
17
float32 infinite_float32(uint8_t sign);
23
+
18
-float32 internal_fmafx(float32 a, float32 b, float32 c,
24
case INDEX_op_br:
19
- int scale, float_status *fp_status);
25
tci_out_label(s, arg_label(args[0]));
20
float64 internal_mpyhh(float64 a, float64 b,
26
break;
21
unsigned long long int accumulated,
27
- case INDEX_op_setcond_i32:
22
float_status *fp_status);
28
+
23
diff --git a/target/hexagon/fma_emu.c b/target/hexagon/fma_emu.c
29
+ CASE_32_64(setcond)
24
index XXXXXXX..XXXXXXX 100644
30
tcg_out_r(s, args[0]);
25
--- a/target/hexagon/fma_emu.c
31
tcg_out_r(s, args[1]);
26
+++ b/target/hexagon/fma_emu.c
32
tcg_out_r(s, args[2]);
27
@@ -XXX,XX +XXX,XX @@ int32_t float64_getexp(float64 f64)
33
tcg_out8(s, args[3]); /* condition */
28
return -1;
34
break;
29
}
35
+
30
36
#if TCG_TARGET_REG_BITS == 32
31
-static uint64_t float32_getmant(float32 f32)
37
case INDEX_op_setcond2_i32:
32
-{
38
/* setcond2_i32 cond, t0, t1_low, t1_high, t2_low, t2_high */
33
- Float a = { .i = f32 };
39
@@ -XXX,XX +XXX,XX @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
34
- if (float32_is_normal(f32)) {
40
tcg_out_r(s, args[4]);
35
- return a.mant | 1ULL << 23;
41
tcg_out8(s, args[5]); /* condition */
36
- }
42
break;
37
- if (float32_is_zero(f32)) {
43
-#elif TCG_TARGET_REG_BITS == 64
38
- return 0;
44
- case INDEX_op_setcond_i64:
39
- }
45
- tcg_out_r(s, args[0]);
40
- if (float32_is_denormal(f32)) {
46
- tcg_out_r(s, args[1]);
41
- return a.mant;
47
- tcg_out_r(s, args[2]);
42
- }
48
- tcg_out8(s, args[3]); /* condition */
43
- return ~0ULL;
49
- break;
44
-}
50
#endif
45
-
51
case INDEX_op_ld8u_i32:
46
int32_t float32_getexp(float32 f32)
52
case INDEX_op_ld8s_i32:
47
{
53
@@ -XXX,XX +XXX,XX @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
48
Float a = { .i = f32 };
54
tcg_out8(s, args[4]);
49
@@ -XXX,XX +XXX,XX @@ float32 infinite_float32(uint8_t sign)
55
break;
50
}
56
51
57
-#if TCG_TARGET_REG_BITS == 64
52
/* Return a maximum finite value with the requested sign */
58
- case INDEX_op_brcond_i64:
53
-static float32 maxfinite_float32(uint8_t sign)
59
+ CASE_32_64(brcond)
54
-{
60
tcg_out_r(s, args[0]);
55
- if (sign) {
61
tcg_out_r(s, args[1]);
56
- return make_float32(SF_MINUS_MAXF);
62
tcg_out8(s, args[2]); /* condition */
57
- } else {
63
tci_out_label(s, arg_label(args[3]));
58
- return make_float32(SF_MAXF);
64
break;
59
- }
65
-#endif /* TCG_TARGET_REG_BITS == 64 */
60
-}
66
61
-
67
CASE_32_64(neg) /* Optional (TCG_TARGET_HAS_neg_*). */
62
-/* Return a zero value with requested sign */
68
CASE_32_64(not) /* Optional (TCG_TARGET_HAS_not_*). */
63
-static float32 zero_float32(uint8_t sign)
69
@@ -XXX,XX +XXX,XX @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
64
-{
70
tcg_out_r(s, args[3]);
65
- if (sign) {
71
break;
66
- return make_float32(0x80000000);
72
#endif
67
- } else {
73
- case INDEX_op_brcond_i32:
68
- return float32_zero;
74
- tcg_out_r(s, args[0]);
69
- }
75
- tcg_out_r(s, args[1]);
70
-}
76
- tcg_out8(s, args[2]); /* condition */
71
-
77
- tci_out_label(s, arg_label(args[3]));
72
#define GEN_XF_ROUND(SUFFIX, MANTBITS, INF_EXP, INTERNAL_TYPE) \
78
- break;
73
static SUFFIX accum_round_##SUFFIX(Accum a, float_status * fp_status) \
79
+
74
{ \
80
case INDEX_op_qemu_ld_i32:
75
@@ -XXX,XX +XXX,XX @@ static SUFFIX accum_round_##SUFFIX(Accum a, float_status * fp_status) \
81
tcg_out_r(s, *args++);
76
}
82
tcg_out_r(s, *args++);
77
78
GEN_XF_ROUND(float64, DF_MANTBITS, DF_INF_EXP, Double)
79
-GEN_XF_ROUND(float32, SF_MANTBITS, SF_INF_EXP, Float)
80
-
81
-static bool is_inf_prod(float64 a, float64 b)
82
-{
83
- return ((float64_is_infinity(a) && float64_is_infinity(b)) ||
84
- (float64_is_infinity(a) && is_finite(b) && (!float64_is_zero(b))) ||
85
- (float64_is_infinity(b) && is_finite(a) && (!float64_is_zero(a))));
86
-}
87
-
88
-static float64 special_fma(float64 a, float64 b, float64 c,
89
- float_status *fp_status)
90
-{
91
- float64 ret = make_float64(0);
92
-
93
- /*
94
- * If A multiplied by B is an exact infinity and C is also an infinity
95
- * but with the opposite sign, FMA returns NaN and raises invalid.
96
- */
97
- uint8_t a_sign = float64_is_neg(a);
98
- uint8_t b_sign = float64_is_neg(b);
99
- uint8_t c_sign = float64_is_neg(c);
100
- if (is_inf_prod(a, b) && float64_is_infinity(c)) {
101
- if ((a_sign ^ b_sign) != c_sign) {
102
- ret = make_float64(DF_NAN);
103
- float_raise(float_flag_invalid, fp_status);
104
- return ret;
105
- }
106
- }
107
- if ((float64_is_infinity(a) && float64_is_zero(b)) ||
108
- (float64_is_zero(a) && float64_is_infinity(b))) {
109
- ret = make_float64(DF_NAN);
110
- float_raise(float_flag_invalid, fp_status);
111
- return ret;
112
- }
113
- /*
114
- * If none of the above checks are true and C is a NaN,
115
- * a NaN shall be returned
116
- * If A or B are NaN, a NAN shall be returned.
117
- */
118
- if (float64_is_any_nan(a) ||
119
- float64_is_any_nan(b) ||
120
- float64_is_any_nan(c)) {
121
- if (float64_is_any_nan(a) && (fGETBIT(51, a) == 0)) {
122
- float_raise(float_flag_invalid, fp_status);
123
- }
124
- if (float64_is_any_nan(b) && (fGETBIT(51, b) == 0)) {
125
- float_raise(float_flag_invalid, fp_status);
126
- }
127
- if (float64_is_any_nan(c) && (fGETBIT(51, c) == 0)) {
128
- float_raise(float_flag_invalid, fp_status);
129
- }
130
- ret = make_float64(DF_NAN);
131
- return ret;
132
- }
133
- /*
134
- * We have checked for adding opposite-signed infinities.
135
- * Other infinities return infinity with the correct sign
136
- */
137
- if (float64_is_infinity(c)) {
138
- ret = infinite_float64(c_sign);
139
- return ret;
140
- }
141
- if (float64_is_infinity(a) || float64_is_infinity(b)) {
142
- ret = infinite_float64(a_sign ^ b_sign);
143
- return ret;
144
- }
145
- g_assert_not_reached();
146
-}
147
-
148
-static float32 special_fmaf(float32 a, float32 b, float32 c,
149
- float_status *fp_status)
150
-{
151
- float64 aa, bb, cc;
152
- aa = float32_to_float64(a, fp_status);
153
- bb = float32_to_float64(b, fp_status);
154
- cc = float32_to_float64(c, fp_status);
155
- return float64_to_float32(special_fma(aa, bb, cc, fp_status), fp_status);
156
-}
157
-
158
-float32 internal_fmafx(float32 a, float32 b, float32 c, int scale,
159
- float_status *fp_status)
160
-{
161
- Accum prod;
162
- Accum acc;
163
- Accum result;
164
- accum_init(&prod);
165
- accum_init(&acc);
166
- accum_init(&result);
167
-
168
- uint8_t a_sign = float32_is_neg(a);
169
- uint8_t b_sign = float32_is_neg(b);
170
- uint8_t c_sign = float32_is_neg(c);
171
- if (float32_is_infinity(a) ||
172
- float32_is_infinity(b) ||
173
- float32_is_infinity(c)) {
174
- return special_fmaf(a, b, c, fp_status);
175
- }
176
- if (float32_is_any_nan(a) ||
177
- float32_is_any_nan(b) ||
178
- float32_is_any_nan(c)) {
179
- return special_fmaf(a, b, c, fp_status);
180
- }
181
- if ((scale == 0) && (float32_is_zero(a) || float32_is_zero(b))) {
182
- float32 tmp = float32_mul(a, b, fp_status);
183
- tmp = float32_add(tmp, c, fp_status);
184
- return tmp;
185
- }
186
-
187
- /* (a * 2**b) * (c * 2**d) == a*c * 2**(b+d) */
188
- prod.mant = int128_mul_6464(float32_getmant(a), float32_getmant(b));
189
-
190
- /*
191
- * Note: extracting the mantissa into an int is multiplying by
192
- * 2**23, so adjust here
193
- */
194
- prod.exp = float32_getexp(a) + float32_getexp(b) - SF_BIAS - 23;
195
- prod.sign = a_sign ^ b_sign;
196
- if (float32_is_zero(a) || float32_is_zero(b)) {
197
- prod.exp = -2 * WAY_BIG_EXP;
198
- }
199
- if ((scale > 0) && float32_is_denormal(c)) {
200
- acc.mant = int128_mul_6464(0, 0);
201
- acc.exp = -WAY_BIG_EXP;
202
- acc.sign = c_sign;
203
- acc.sticky = 1;
204
- result = accum_add(prod, acc);
205
- } else if (!float32_is_zero(c)) {
206
- acc.mant = int128_mul_6464(float32_getmant(c), 1);
207
- acc.exp = float32_getexp(c);
208
- acc.sign = c_sign;
209
- result = accum_add(prod, acc);
210
- } else {
211
- result = prod;
212
- }
213
- result.exp += scale;
214
- return accum_round_float32(result, fp_status);
215
-}
216
217
float64 internal_mpyhh(float64 a, float64 b,
218
unsigned long long int accumulated,
83
--
219
--
84
2.25.1
220
2.43.0
85
86
diff view generated by jsdifflib
[PATCH 07/27] tcg/tci: Merge identical cases in generation (arithmetic opcodes)
[PULL 67/72] target/hexagon: Expand GEN_XF_ROUND
1
Use CASE_32_64 and CASE_64 to reduce ifdefs and merge
1
This massive macro is now only used once.
2
cases that are identical between 32-bit and 64-bit hosts.
2
Expand it for use only by float64.
3
3
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Brian Cain <brian.cain@oss.qualcomm.com>
5
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
6
Message-Id: <20210217202036.1724901-5-richard.henderson@linaro.org>
7
[PMD: Split patch as 1/5]
8
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
Message-Id: <20210218232840.1760806-2-f4bug@amsat.org>
10
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
11
---
6
---
12
tcg/tci/tcg-target.c.inc | 85 +++++++++++++++++-----------------------
7
target/hexagon/fma_emu.c | 255 +++++++++++++++++++--------------------
13
1 file changed, 37 insertions(+), 48 deletions(-)
8
1 file changed, 127 insertions(+), 128 deletions(-)
14
9
15
diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
10
diff --git a/target/hexagon/fma_emu.c b/target/hexagon/fma_emu.c
16
index XXXXXXX..XXXXXXX 100644
11
index XXXXXXX..XXXXXXX 100644
17
--- a/tcg/tci/tcg-target.c.inc
12
--- a/target/hexagon/fma_emu.c
18
+++ b/tcg/tci/tcg-target.c.inc
13
+++ b/target/hexagon/fma_emu.c
19
@@ -XXX,XX +XXX,XX @@ static inline void tcg_out_call(TCGContext *s, const tcg_insn_unit *arg)
14
@@ -XXX,XX +XXX,XX @@ float32 infinite_float32(uint8_t sign)
20
old_code_ptr[1] = s->code_ptr - old_code_ptr;
21
}
15
}
22
16
23
+#if TCG_TARGET_REG_BITS == 64
17
/* Return a maximum finite value with the requested sign */
24
+# define CASE_32_64(x) \
18
-#define GEN_XF_ROUND(SUFFIX, MANTBITS, INF_EXP, INTERNAL_TYPE) \
25
+ case glue(glue(INDEX_op_, x), _i64): \
19
-static SUFFIX accum_round_##SUFFIX(Accum a, float_status * fp_status) \
26
+ case glue(glue(INDEX_op_, x), _i32):
20
-{ \
27
+# define CASE_64(x) \
21
- if ((int128_gethi(a.mant) == 0) && (int128_getlo(a.mant) == 0) \
28
+ case glue(glue(INDEX_op_, x), _i64):
22
- && ((a.guard | a.round | a.sticky) == 0)) { \
29
+#else
23
- /* result zero */ \
30
+# define CASE_32_64(x) \
24
- switch (fp_status->float_rounding_mode) { \
31
+ case glue(glue(INDEX_op_, x), _i32):
25
- case float_round_down: \
32
+# define CASE_64(x)
26
- return zero_##SUFFIX(1); \
33
+#endif
27
- default: \
34
+
28
- return zero_##SUFFIX(0); \
35
static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
29
- } \
36
const int *const_args)
30
- } \
37
{
31
- /* Normalize right */ \
38
@@ -XXX,XX +XXX,XX @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
32
- /* We want MANTBITS bits of mantissa plus the leading one. */ \
39
case INDEX_op_exit_tb:
33
- /* That means that we want MANTBITS+1 bits, or 0x000000000000FF_FFFF */ \
40
tcg_out64(s, args[0]);
34
- /* So we need to normalize right while the high word is non-zero and \
41
break;
35
- * while the low word is nonzero when masked with 0xffe0_0000_0000_0000 */ \
42
+
36
- while ((int128_gethi(a.mant) != 0) || \
43
case INDEX_op_goto_tb:
37
- ((int128_getlo(a.mant) >> (MANTBITS + 1)) != 0)) { \
44
if (s->tb_jmp_insn_offset) {
38
- a = accum_norm_right(a, 1); \
45
/* Direct jump method. */
39
- } \
46
@@ -XXX,XX +XXX,XX @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
40
- /* \
47
tcg_debug_assert(args[2] == (int32_t)args[2]);
41
- * OK, now normalize left \
48
tcg_out32(s, args[2]);
42
- * We want to normalize left until we have a leading one in bit 24 \
49
break;
43
- * Theoretically, we only need to shift a maximum of one to the left if we \
50
- case INDEX_op_add_i32:
44
- * shifted out lots of bits from B, or if we had no shift / 1 shift sticky \
51
- case INDEX_op_sub_i32:
45
- * should be 0 \
52
- case INDEX_op_mul_i32:
46
- */ \
53
- case INDEX_op_and_i32:
47
- while ((int128_getlo(a.mant) & (1ULL << MANTBITS)) == 0) { \
54
- case INDEX_op_andc_i32: /* Optional (TCG_TARGET_HAS_andc_i32). */
48
- a = accum_norm_left(a); \
55
- case INDEX_op_eqv_i32: /* Optional (TCG_TARGET_HAS_eqv_i32). */
49
- } \
56
- case INDEX_op_nand_i32: /* Optional (TCG_TARGET_HAS_nand_i32). */
50
- /* \
57
- case INDEX_op_nor_i32: /* Optional (TCG_TARGET_HAS_nor_i32). */
51
- * OK, now we might need to denormalize because of potential underflow. \
58
- case INDEX_op_or_i32:
52
- * We need to do this before rounding, and rounding might make us normal \
59
- case INDEX_op_orc_i32: /* Optional (TCG_TARGET_HAS_orc_i32). */
53
- * again \
60
- case INDEX_op_xor_i32:
54
- */ \
61
- case INDEX_op_shl_i32:
55
- while (a.exp <= 0) { \
62
- case INDEX_op_shr_i32:
56
- a = accum_norm_right(a, 1 - a.exp); \
63
- case INDEX_op_sar_i32:
57
- /* \
64
- case INDEX_op_rotl_i32: /* Optional (TCG_TARGET_HAS_rot_i32). */
58
- * Do we have underflow? \
65
- case INDEX_op_rotr_i32: /* Optional (TCG_TARGET_HAS_rot_i32). */
59
- * That's when we get an inexact answer because we ran out of bits \
66
+
60
- * in a denormal. \
67
+ CASE_32_64(add)
61
- */ \
68
+ CASE_32_64(sub)
62
- if (a.guard || a.round || a.sticky) { \
69
+ CASE_32_64(mul)
63
- float_raise(float_flag_underflow, fp_status); \
70
+ CASE_32_64(and)
64
- } \
71
+ CASE_32_64(or)
65
- } \
72
+ CASE_32_64(xor)
66
- /* OK, we're relatively canonical... now we need to round */ \
73
+ CASE_32_64(andc) /* Optional (TCG_TARGET_HAS_andc_*). */
67
- if (a.guard || a.round || a.sticky) { \
74
+ CASE_32_64(orc) /* Optional (TCG_TARGET_HAS_orc_*). */
68
- float_raise(float_flag_inexact, fp_status); \
75
+ CASE_32_64(eqv) /* Optional (TCG_TARGET_HAS_eqv_*). */
69
- switch (fp_status->float_rounding_mode) { \
76
+ CASE_32_64(nand) /* Optional (TCG_TARGET_HAS_nand_*). */
70
- case float_round_to_zero: \
77
+ CASE_32_64(nor) /* Optional (TCG_TARGET_HAS_nor_*). */
71
- /* Chop and we're done */ \
78
+ CASE_32_64(shl)
72
- break; \
79
+ CASE_32_64(shr)
73
- case float_round_up: \
80
+ CASE_32_64(sar)
74
- if (a.sign == 0) { \
81
+ CASE_32_64(rotl) /* Optional (TCG_TARGET_HAS_rot_*). */
75
- a.mant = int128_add(a.mant, int128_one()); \
82
+ CASE_32_64(rotr) /* Optional (TCG_TARGET_HAS_rot_*). */
76
- } \
83
+ CASE_32_64(div) /* Optional (TCG_TARGET_HAS_div_*). */
77
- break; \
84
+ CASE_32_64(divu) /* Optional (TCG_TARGET_HAS_div_*). */
78
- case float_round_down: \
85
+ CASE_32_64(rem) /* Optional (TCG_TARGET_HAS_div_*). */
79
- if (a.sign != 0) { \
86
+ CASE_32_64(remu) /* Optional (TCG_TARGET_HAS_div_*). */
80
- a.mant = int128_add(a.mant, int128_one()); \
87
tcg_out_r(s, args[0]);
81
- } \
88
tcg_out_r(s, args[1]);
82
- break; \
89
tcg_out_r(s, args[2]);
83
- default: \
90
@@ -XXX,XX +XXX,XX @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
84
- if (a.round || a.sticky) { \
91
break;
85
- /* round up if guard is 1, down if guard is zero */ \
92
86
- a.mant = int128_add(a.mant, int128_make64(a.guard)); \
93
#if TCG_TARGET_REG_BITS == 64
87
- } else if (a.guard) { \
94
- case INDEX_op_add_i64:
88
- /* exactly .5, round up if odd */ \
95
- case INDEX_op_sub_i64:
89
- a.mant = int128_add(a.mant, int128_and(a.mant, int128_one())); \
96
- case INDEX_op_mul_i64:
90
- } \
97
- case INDEX_op_and_i64:
91
- break; \
98
- case INDEX_op_andc_i64: /* Optional (TCG_TARGET_HAS_andc_i64). */
92
- } \
99
- case INDEX_op_eqv_i64: /* Optional (TCG_TARGET_HAS_eqv_i64). */
93
- } \
100
- case INDEX_op_nand_i64: /* Optional (TCG_TARGET_HAS_nand_i64). */
94
- /* \
101
- case INDEX_op_nor_i64: /* Optional (TCG_TARGET_HAS_nor_i64). */
95
- * OK, now we might have carried all the way up. \
102
- case INDEX_op_or_i64:
96
- * So we might need to shr once \
103
- case INDEX_op_orc_i64: /* Optional (TCG_TARGET_HAS_orc_i64). */
97
- * at least we know that the lsb should be zero if we rounded and \
104
- case INDEX_op_xor_i64:
98
- * got a carry out... \
105
- case INDEX_op_shl_i64:
99
- */ \
106
- case INDEX_op_shr_i64:
100
- if ((int128_getlo(a.mant) >> (MANTBITS + 1)) != 0) { \
107
- case INDEX_op_sar_i64:
101
- a = accum_norm_right(a, 1); \
108
- case INDEX_op_rotl_i64: /* Optional (TCG_TARGET_HAS_rot_i64). */
102
- } \
109
- case INDEX_op_rotr_i64: /* Optional (TCG_TARGET_HAS_rot_i64). */
103
- /* Overflow? */ \
110
- case INDEX_op_div_i64: /* Optional (TCG_TARGET_HAS_div_i64). */
104
- if (a.exp >= INF_EXP) { \
111
- case INDEX_op_divu_i64: /* Optional (TCG_TARGET_HAS_div_i64). */
105
- /* Yep, inf result */ \
112
- case INDEX_op_rem_i64: /* Optional (TCG_TARGET_HAS_div_i64). */
106
- float_raise(float_flag_overflow, fp_status); \
113
- case INDEX_op_remu_i64: /* Optional (TCG_TARGET_HAS_div_i64). */
107
- float_raise(float_flag_inexact, fp_status); \
114
- tcg_out_r(s, args[0]);
108
- switch (fp_status->float_rounding_mode) { \
115
- tcg_out_r(s, args[1]);
109
- case float_round_to_zero: \
116
- tcg_out_r(s, args[2]);
110
- return maxfinite_##SUFFIX(a.sign); \
117
- break;
111
- case float_round_up: \
118
case INDEX_op_deposit_i64: /* Optional (TCG_TARGET_HAS_deposit_i64). */
112
- if (a.sign == 0) { \
119
tcg_out_r(s, args[0]);
113
- return infinite_##SUFFIX(a.sign); \
120
tcg_out_r(s, args[1]);
114
- } else { \
121
@@ -XXX,XX +XXX,XX @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
115
- return maxfinite_##SUFFIX(a.sign); \
122
tcg_out_r(s, args[0]);
116
- } \
123
tcg_out_r(s, args[1]);
117
- case float_round_down: \
124
break;
118
- if (a.sign != 0) { \
125
- case INDEX_op_div_i32: /* Optional (TCG_TARGET_HAS_div_i32). */
119
- return infinite_##SUFFIX(a.sign); \
126
- case INDEX_op_divu_i32: /* Optional (TCG_TARGET_HAS_div_i32). */
120
- } else { \
127
- case INDEX_op_rem_i32: /* Optional (TCG_TARGET_HAS_div_i32). */
121
- return maxfinite_##SUFFIX(a.sign); \
128
- case INDEX_op_remu_i32: /* Optional (TCG_TARGET_HAS_div_i32). */
122
- } \
129
- tcg_out_r(s, args[0]);
123
- default: \
130
- tcg_out_r(s, args[1]);
124
- return infinite_##SUFFIX(a.sign); \
131
- tcg_out_r(s, args[2]);
125
- } \
132
- break;
126
- } \
133
+
127
- /* Underflow? */ \
134
#if TCG_TARGET_REG_BITS == 32
128
- if (int128_getlo(a.mant) & (1ULL << MANTBITS)) { \
135
case INDEX_op_add2_i32:
129
- /* Leading one means: No, we're normal. So, we should be done... */ \
136
case INDEX_op_sub2_i32:
130
- INTERNAL_TYPE ret; \
137
@@ -XXX,XX +XXX,XX @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
131
- ret.i = 0; \
138
}
132
- ret.sign = a.sign; \
139
tcg_out_i(s, *args++);
133
- ret.exp = a.exp; \
140
break;
134
- ret.mant = int128_getlo(a.mant); \
141
+
135
- return ret.i; \
142
case INDEX_op_mb:
136
- } \
143
break;
137
- assert(a.exp == 1); \
144
+
138
- INTERNAL_TYPE ret; \
145
case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
139
- ret.i = 0; \
146
case INDEX_op_mov_i64:
140
- ret.sign = a.sign; \
147
case INDEX_op_call: /* Always emitted via tcg_out_call. */
141
- ret.exp = 0; \
142
- ret.mant = int128_getlo(a.mant); \
143
- return ret.i; \
144
+static float64 accum_round_float64(Accum a, float_status *fp_status)
145
+{
146
+ if ((int128_gethi(a.mant) == 0) && (int128_getlo(a.mant) == 0)
147
+ && ((a.guard | a.round | a.sticky) == 0)) {
148
+ /* result zero */
149
+ switch (fp_status->float_rounding_mode) {
150
+ case float_round_down:
151
+ return zero_float64(1);
152
+ default:
153
+ return zero_float64(0);
154
+ }
155
+ }
156
+ /*
157
+ * Normalize right
158
+ * We want DF_MANTBITS bits of mantissa plus the leading one.
159
+ * That means that we want DF_MANTBITS+1 bits, or 0x000000000000FF_FFFF
160
+ * So we need to normalize right while the high word is non-zero and
161
+ * while the low word is nonzero when masked with 0xffe0_0000_0000_0000
162
+ */
163
+ while ((int128_gethi(a.mant) != 0) ||
164
+ ((int128_getlo(a.mant) >> (DF_MANTBITS + 1)) != 0)) {
165
+ a = accum_norm_right(a, 1);
166
+ }
167
+ /*
168
+ * OK, now normalize left
169
+ * We want to normalize left until we have a leading one in bit 24
170
+ * Theoretically, we only need to shift a maximum of one to the left if we
171
+ * shifted out lots of bits from B, or if we had no shift / 1 shift sticky
172
+ * should be 0
173
+ */
174
+ while ((int128_getlo(a.mant) & (1ULL << DF_MANTBITS)) == 0) {
175
+ a = accum_norm_left(a);
176
+ }
177
+ /*
178
+ * OK, now we might need to denormalize because of potential underflow.
179
+ * We need to do this before rounding, and rounding might make us normal
180
+ * again
181
+ */
182
+ while (a.exp <= 0) {
183
+ a = accum_norm_right(a, 1 - a.exp);
184
+ /*
185
+ * Do we have underflow?
186
+ * That's when we get an inexact answer because we ran out of bits
187
+ * in a denormal.
188
+ */
189
+ if (a.guard || a.round || a.sticky) {
190
+ float_raise(float_flag_underflow, fp_status);
191
+ }
192
+ }
193
+ /* OK, we're relatively canonical... now we need to round */
194
+ if (a.guard || a.round || a.sticky) {
195
+ float_raise(float_flag_inexact, fp_status);
196
+ switch (fp_status->float_rounding_mode) {
197
+ case float_round_to_zero:
198
+ /* Chop and we're done */
199
+ break;
200
+ case float_round_up:
201
+ if (a.sign == 0) {
202
+ a.mant = int128_add(a.mant, int128_one());
203
+ }
204
+ break;
205
+ case float_round_down:
206
+ if (a.sign != 0) {
207
+ a.mant = int128_add(a.mant, int128_one());
208
+ }
209
+ break;
210
+ default:
211
+ if (a.round || a.sticky) {
212
+ /* round up if guard is 1, down if guard is zero */
213
+ a.mant = int128_add(a.mant, int128_make64(a.guard));
214
+ } else if (a.guard) {
215
+ /* exactly .5, round up if odd */
216
+ a.mant = int128_add(a.mant, int128_and(a.mant, int128_one()));
217
+ }
218
+ break;
219
+ }
220
+ }
221
+ /*
222
+ * OK, now we might have carried all the way up.
223
+ * So we might need to shr once
224
+ * at least we know that the lsb should be zero if we rounded and
225
+ * got a carry out...
226
+ */
227
+ if ((int128_getlo(a.mant) >> (DF_MANTBITS + 1)) != 0) {
228
+ a = accum_norm_right(a, 1);
229
+ }
230
+ /* Overflow? */
231
+ if (a.exp >= DF_INF_EXP) {
232
+ /* Yep, inf result */
233
+ float_raise(float_flag_overflow, fp_status);
234
+ float_raise(float_flag_inexact, fp_status);
235
+ switch (fp_status->float_rounding_mode) {
236
+ case float_round_to_zero:
237
+ return maxfinite_float64(a.sign);
238
+ case float_round_up:
239
+ if (a.sign == 0) {
240
+ return infinite_float64(a.sign);
241
+ } else {
242
+ return maxfinite_float64(a.sign);
243
+ }
244
+ case float_round_down:
245
+ if (a.sign != 0) {
246
+ return infinite_float64(a.sign);
247
+ } else {
248
+ return maxfinite_float64(a.sign);
249
+ }
250
+ default:
251
+ return infinite_float64(a.sign);
252
+ }
253
+ }
254
+ /* Underflow? */
255
+ if (int128_getlo(a.mant) & (1ULL << DF_MANTBITS)) {
256
+ /* Leading one means: No, we're normal. So, we should be done... */
257
+ Double ret;
258
+ ret.i = 0;
259
+ ret.sign = a.sign;
260
+ ret.exp = a.exp;
261
+ ret.mant = int128_getlo(a.mant);
262
+ return ret.i;
263
+ }
264
+ assert(a.exp == 1);
265
+ Double ret;
266
+ ret.i = 0;
267
+ ret.sign = a.sign;
268
+ ret.exp = 0;
269
+ ret.mant = int128_getlo(a.mant);
270
+ return ret.i;
271
}
272
273
-GEN_XF_ROUND(float64, DF_MANTBITS, DF_INF_EXP, Double)
274
-
275
float64 internal_mpyhh(float64 a, float64 b,
276
unsigned long long int accumulated,
277
float_status *fp_status)
148
--
278
--
149
2.25.1
279
2.43.0
150
151
diff view generated by jsdifflib
[PATCH 09/27] tcg/tci: Merge identical cases in generation (deposit opcode)
[PULL 68/72] target/hexagon: Remove Float
1
Use CASE_32_64 and CASE_64 to reduce ifdefs and merge
1
This structure, with bitfields, is incorrect for big-endian.
2
cases that are identical between 32-bit and 64-bit hosts.
2
Use the existing float32_getexp_raw which uses extract32.
3
3
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Brian Cain <brian.cain@oss.qualcomm.com>
5
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
6
Message-Id: <20210217202036.1724901-5-richard.henderson@linaro.org>
7
[PMD: Split patch as 3/5]
8
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
Message-Id: <20210218232840.1760806-4-f4bug@amsat.org>
10
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
11
---
6
---
12
tcg/tci/tcg-target.c.inc | 12 ++----------
7
target/hexagon/fma_emu.c | 16 +++-------------
13
1 file changed, 2 insertions(+), 10 deletions(-)
8
1 file changed, 3 insertions(+), 13 deletions(-)
14
9
15
diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
10
diff --git a/target/hexagon/fma_emu.c b/target/hexagon/fma_emu.c
16
index XXXXXXX..XXXXXXX 100644
11
index XXXXXXX..XXXXXXX 100644
17
--- a/tcg/tci/tcg-target.c.inc
12
--- a/target/hexagon/fma_emu.c
18
+++ b/tcg/tci/tcg-target.c.inc
13
+++ b/target/hexagon/fma_emu.c
19
@@ -XXX,XX +XXX,XX @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
14
@@ -XXX,XX +XXX,XX @@ typedef union {
20
tcg_out_r(s, args[1]);
15
};
21
tcg_out_r(s, args[2]);
16
} Double;
22
break;
17
23
- case INDEX_op_deposit_i32: /* Optional (TCG_TARGET_HAS_deposit_i32). */
18
-typedef union {
24
+
19
- float f;
25
+ CASE_32_64(deposit) /* Optional (TCG_TARGET_HAS_deposit_*). */
20
- uint32_t i;
26
tcg_out_r(s, args[0]);
21
- struct {
27
tcg_out_r(s, args[1]);
22
- uint32_t mant:23;
28
tcg_out_r(s, args[2]);
23
- uint32_t exp:8;
29
@@ -XXX,XX +XXX,XX @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
24
- uint32_t sign:1;
30
break;
25
- };
31
26
-} Float;
32
#if TCG_TARGET_REG_BITS == 64
27
-
33
- case INDEX_op_deposit_i64: /* Optional (TCG_TARGET_HAS_deposit_i64). */
28
static uint64_t float64_getmant(float64 f64)
34
- tcg_out_r(s, args[0]);
29
{
35
- tcg_out_r(s, args[1]);
30
Double a = { .i = f64 };
36
- tcg_out_r(s, args[2]);
31
@@ -XXX,XX +XXX,XX @@ int32_t float64_getexp(float64 f64)
37
- tcg_debug_assert(args[3] <= UINT8_MAX);
32
38
- tcg_out8(s, args[3]);
33
int32_t float32_getexp(float32 f32)
39
- tcg_debug_assert(args[4] <= UINT8_MAX);
34
{
40
- tcg_out8(s, args[4]);
35
- Float a = { .i = f32 };
41
- break;
36
+ int exp = float32_getexp_raw(f32);
42
case INDEX_op_brcond_i64:
37
if (float32_is_normal(f32)) {
43
tcg_out_r(s, args[0]);
38
- return a.exp;
44
tcg_out_r(s, args[1]);
39
+ return exp;
40
}
41
if (float32_is_denormal(f32)) {
42
- return a.exp + 1;
43
+ return exp + 1;
44
}
45
return -1;
46
}
45
--
47
--
46
2.25.1
48
2.43.0
47
48
diff view generated by jsdifflib
[PATCH 04/27] tcg/tci: Use exec/cpu_ldst.h interfaces
[PULL 69/72] target/hexagon: Remove Double
1
Use the provided cpu_ldst.h interfaces. This fixes the build vs
1
This structure, with bitfields, is incorrect for big-endian.
2
the unconverted uses of g2h(), adds missed memory trace events,
2
Use extract64 and deposit64 instead.
3
and correctly recognizes when a SIGSEGV belongs to the guest via
4
set_helper_retaddr().
5
3
6
Fixes: 3e8f1628e864
4
Reviewed-by: Brian Cain <brian.cain@oss.qualcomm.com>
7
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
---
6
---
10
tcg/tci.c | 73 +++++++++++++++++++++----------------------------------
7
target/hexagon/fma_emu.c | 46 ++++++++++++++--------------------------
11
1 file changed, 28 insertions(+), 45 deletions(-)
8
1 file changed, 16 insertions(+), 30 deletions(-)
12
9
13
diff --git a/tcg/tci.c b/tcg/tci.c
10
diff --git a/target/hexagon/fma_emu.c b/target/hexagon/fma_emu.c
14
index XXXXXXX..XXXXXXX 100644
11
index XXXXXXX..XXXXXXX 100644
15
--- a/tcg/tci.c
12
--- a/target/hexagon/fma_emu.c
16
+++ b/tcg/tci.c
13
+++ b/target/hexagon/fma_emu.c
17
@@ -XXX,XX +XXX,XX @@ static bool tci_compare64(uint64_t u0, uint64_t u1, TCGCond condition)
14
@@ -XXX,XX +XXX,XX @@
18
return result;
15
16
#define WAY_BIG_EXP 4096
17
18
-typedef union {
19
- double f;
20
- uint64_t i;
21
- struct {
22
- uint64_t mant:52;
23
- uint64_t exp:11;
24
- uint64_t sign:1;
25
- };
26
-} Double;
27
-
28
static uint64_t float64_getmant(float64 f64)
29
{
30
- Double a = { .i = f64 };
31
+ uint64_t mant = extract64(f64, 0, 52);
32
if (float64_is_normal(f64)) {
33
- return a.mant | 1ULL << 52;
34
+ return mant | 1ULL << 52;
35
}
36
if (float64_is_zero(f64)) {
37
return 0;
38
}
39
if (float64_is_denormal(f64)) {
40
- return a.mant;
41
+ return mant;
42
}
43
return ~0ULL;
19
}
44
}
20
45
21
-#ifdef CONFIG_SOFTMMU
46
int32_t float64_getexp(float64 f64)
22
-# define qemu_ld_ub \
47
{
23
- helper_ret_ldub_mmu(env, taddr, oi, (uintptr_t)tb_ptr)
48
- Double a = { .i = f64 };
24
-# define qemu_ld_leuw \
49
+ int exp = extract64(f64, 52, 11);
25
- helper_le_lduw_mmu(env, taddr, oi, (uintptr_t)tb_ptr)
50
if (float64_is_normal(f64)) {
26
-# define qemu_ld_leul \
51
- return a.exp;
27
- helper_le_ldul_mmu(env, taddr, oi, (uintptr_t)tb_ptr)
52
+ return exp;
28
-# define qemu_ld_leq \
53
}
29
- helper_le_ldq_mmu(env, taddr, oi, (uintptr_t)tb_ptr)
54
if (float64_is_denormal(f64)) {
30
-# define qemu_ld_beuw \
55
- return a.exp + 1;
31
- helper_be_lduw_mmu(env, taddr, oi, (uintptr_t)tb_ptr)
56
+ return exp + 1;
32
-# define qemu_ld_beul \
57
}
33
- helper_be_ldul_mmu(env, taddr, oi, (uintptr_t)tb_ptr)
58
return -1;
34
-# define qemu_ld_beq \
59
}
35
- helper_be_ldq_mmu(env, taddr, oi, (uintptr_t)tb_ptr)
60
@@ -XXX,XX +XXX,XX @@ float32 infinite_float32(uint8_t sign)
36
-# define qemu_st_b(X) \
61
/* Return a maximum finite value with the requested sign */
37
- helper_ret_stb_mmu(env, taddr, X, oi, (uintptr_t)tb_ptr)
62
static float64 accum_round_float64(Accum a, float_status *fp_status)
38
-# define qemu_st_lew(X) \
63
{
39
- helper_le_stw_mmu(env, taddr, X, oi, (uintptr_t)tb_ptr)
64
+ uint64_t ret;
40
-# define qemu_st_lel(X) \
65
+
41
- helper_le_stl_mmu(env, taddr, X, oi, (uintptr_t)tb_ptr)
66
if ((int128_gethi(a.mant) == 0) && (int128_getlo(a.mant) == 0)
42
-# define qemu_st_leq(X) \
67
&& ((a.guard | a.round | a.sticky) == 0)) {
43
- helper_le_stq_mmu(env, taddr, X, oi, (uintptr_t)tb_ptr)
68
/* result zero */
44
-# define qemu_st_bew(X) \
69
@@ -XXX,XX +XXX,XX @@ static float64 accum_round_float64(Accum a, float_status *fp_status)
45
- helper_be_stw_mmu(env, taddr, X, oi, (uintptr_t)tb_ptr)
70
}
46
-# define qemu_st_bel(X) \
71
}
47
- helper_be_stl_mmu(env, taddr, X, oi, (uintptr_t)tb_ptr)
72
/* Underflow? */
48
-# define qemu_st_beq(X) \
73
- if (int128_getlo(a.mant) & (1ULL << DF_MANTBITS)) {
49
- helper_be_stq_mmu(env, taddr, X, oi, (uintptr_t)tb_ptr)
74
+ ret = int128_getlo(a.mant);
50
-#else
75
+ if (ret & (1ULL << DF_MANTBITS)) {
51
-# define qemu_ld_ub ldub_p(g2h(taddr))
76
/* Leading one means: No, we're normal. So, we should be done... */
52
-# define qemu_ld_leuw lduw_le_p(g2h(taddr))
77
- Double ret;
53
-# define qemu_ld_leul (uint32_t)ldl_le_p(g2h(taddr))
78
- ret.i = 0;
54
-# define qemu_ld_leq ldq_le_p(g2h(taddr))
79
- ret.sign = a.sign;
55
-# define qemu_ld_beuw lduw_be_p(g2h(taddr))
80
- ret.exp = a.exp;
56
-# define qemu_ld_beul (uint32_t)ldl_be_p(g2h(taddr))
81
- ret.mant = int128_getlo(a.mant);
57
-# define qemu_ld_beq ldq_be_p(g2h(taddr))
82
- return ret.i;
58
-# define qemu_st_b(X) stb_p(g2h(taddr), X)
83
+ ret = deposit64(ret, 52, 11, a.exp);
59
-# define qemu_st_lew(X) stw_le_p(g2h(taddr), X)
84
+ } else {
60
-# define qemu_st_lel(X) stl_le_p(g2h(taddr), X)
85
+ assert(a.exp == 1);
61
-# define qemu_st_leq(X) stq_le_p(g2h(taddr), X)
86
+ ret = deposit64(ret, 52, 11, 0);
62
-# define qemu_st_bew(X) stw_be_p(g2h(taddr), X)
87
}
63
-# define qemu_st_bel(X) stl_be_p(g2h(taddr), X)
88
- assert(a.exp == 1);
64
-# define qemu_st_beq(X) stq_be_p(g2h(taddr), X)
89
- Double ret;
65
-#endif
90
- ret.i = 0;
66
+#define qemu_ld_ub \
91
- ret.sign = a.sign;
67
+ cpu_ldub_mmuidx_ra(env, taddr, get_mmuidx(oi), (uintptr_t)tb_ptr)
92
- ret.exp = 0;
68
+#define qemu_ld_leuw \
93
- ret.mant = int128_getlo(a.mant);
69
+ cpu_lduw_le_mmuidx_ra(env, taddr, get_mmuidx(oi), (uintptr_t)tb_ptr)
94
- return ret.i;
70
+#define qemu_ld_leul \
95
+ ret = deposit64(ret, 63, 1, a.sign);
71
+ cpu_ldl_le_mmuidx_ra(env, taddr, get_mmuidx(oi), (uintptr_t)tb_ptr)
96
+ return ret;
72
+#define qemu_ld_leq \
97
}
73
+ cpu_ldq_le_mmuidx_ra(env, taddr, get_mmuidx(oi), (uintptr_t)tb_ptr)
98
74
+#define qemu_ld_beuw \
99
float64 internal_mpyhh(float64 a, float64 b,
75
+ cpu_lduw_be_mmuidx_ra(env, taddr, get_mmuidx(oi), (uintptr_t)tb_ptr)
76
+#define qemu_ld_beul \
77
+ cpu_ldl_be_mmuidx_ra(env, taddr, get_mmuidx(oi), (uintptr_t)tb_ptr)
78
+#define qemu_ld_beq \
79
+ cpu_ldq_be_mmuidx_ra(env, taddr, get_mmuidx(oi), (uintptr_t)tb_ptr)
80
+#define qemu_st_b(X) \
81
+ cpu_stb_mmuidx_ra(env, taddr, X, get_mmuidx(oi), (uintptr_t)tb_ptr)
82
+#define qemu_st_lew(X) \
83
+ cpu_stw_le_mmuidx_ra(env, taddr, X, get_mmuidx(oi), (uintptr_t)tb_ptr)
84
+#define qemu_st_lel(X) \
85
+ cpu_stl_le_mmuidx_ra(env, taddr, X, get_mmuidx(oi), (uintptr_t)tb_ptr)
86
+#define qemu_st_leq(X) \
87
+ cpu_stq_le_mmuidx_ra(env, taddr, X, get_mmuidx(oi), (uintptr_t)tb_ptr)
88
+#define qemu_st_bew(X) \
89
+ cpu_stw_be_mmuidx_ra(env, taddr, X, get_mmuidx(oi), (uintptr_t)tb_ptr)
90
+#define qemu_st_bel(X) \
91
+ cpu_stl_be_mmuidx_ra(env, taddr, X, get_mmuidx(oi), (uintptr_t)tb_ptr)
92
+#define qemu_st_beq(X) \
93
+ cpu_stq_be_mmuidx_ra(env, taddr, X, get_mmuidx(oi), (uintptr_t)tb_ptr)
94
95
#if TCG_TARGET_REG_BITS == 64
96
# define CASE_32_64(x) \
97
--
100
--
98
2.25.1
101
2.43.0
99
100
diff view generated by jsdifflib
[PATCH 12/27] tcg/tci: Remove tci_read_r8
[PULL 70/72] target/hexagon: Use mulu64 for int128_mul_6464
1
Use explicit casts for ext8u opcodes, and allow truncation
1
No need to open-code 64x64->128-bit multiplication.
2
to happen with the store for st8 opcodes.
3
2
4
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
3
Reviewed-by: Brian Cain <brian.cain@oss.qualcomm.com>
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
---
5
---
7
tcg/tci.c | 23 +++++------------------
6
target/hexagon/fma_emu.c | 32 +++-----------------------------
8
1 file changed, 5 insertions(+), 18 deletions(-)
7
1 file changed, 3 insertions(+), 29 deletions(-)
9
8
10
diff --git a/tcg/tci.c b/tcg/tci.c
9
diff --git a/target/hexagon/fma_emu.c b/target/hexagon/fma_emu.c
11
index XXXXXXX..XXXXXXX 100644
10
index XXXXXXX..XXXXXXX 100644
12
--- a/tcg/tci.c
11
--- a/target/hexagon/fma_emu.c
13
+++ b/tcg/tci.c
12
+++ b/target/hexagon/fma_emu.c
14
@@ -XXX,XX +XXX,XX @@ static int32_t tci_read_reg32s(const tcg_target_ulong *regs, TCGReg index)
13
@@ -XXX,XX +XXX,XX @@ int32_t float32_getexp(float32 f32)
14
return -1;
15
}
15
}
16
#endif
16
17
17
-static uint32_t int128_getw0(Int128 x)
18
-static uint8_t tci_read_reg8(const tcg_target_ulong *regs, TCGReg index)
19
-{
18
-{
20
- return (uint8_t)tci_read_reg(regs, index);
19
- return int128_getlo(x);
21
-}
20
-}
22
-
21
-
23
static uint16_t tci_read_reg16(const tcg_target_ulong *regs, TCGReg index)
22
-static uint32_t int128_getw1(Int128 x)
24
{
25
return (uint16_t)tci_read_reg(regs, index);
26
@@ -XXX,XX +XXX,XX @@ tci_read_r(const tcg_target_ulong *regs, const uint8_t **tb_ptr)
27
return value;
28
}
29
30
-/* Read indexed register (8 bit) from bytecode. */
31
-static uint8_t tci_read_r8(const tcg_target_ulong *regs, const uint8_t **tb_ptr)
32
-{
23
-{
33
- uint8_t value = tci_read_reg8(regs, **tb_ptr);
24
- return int128_getlo(x) >> 32;
34
- *tb_ptr += 1;
35
- return value;
36
-}
25
-}
37
-
26
-
38
#if TCG_TARGET_HAS_ext8s_i32 || TCG_TARGET_HAS_ext8s_i64
27
static Int128 int128_mul_6464(uint64_t ai, uint64_t bi)
39
/* Read indexed register (8 bit signed) from bytecode. */
28
{
40
static int8_t tci_read_r8s(const tcg_target_ulong *regs, const uint8_t **tb_ptr)
29
- Int128 a, b;
41
@@ -XXX,XX +XXX,XX @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
30
- uint64_t pp0, pp1a, pp1b, pp1s, pp2;
42
tci_write_reg(regs, t0, *(uint32_t *)(t1 + t2));
31
+ uint64_t l, h;
43
break;
32
44
CASE_32_64(st8)
33
- a = int128_make64(ai);
45
- t0 = tci_read_r8(regs, &tb_ptr);
34
- b = int128_make64(bi);
46
+ t0 = tci_read_r(regs, &tb_ptr);
35
- pp0 = (uint64_t)int128_getw0(a) * (uint64_t)int128_getw0(b);
47
t1 = tci_read_r(regs, &tb_ptr);
36
- pp1a = (uint64_t)int128_getw1(a) * (uint64_t)int128_getw0(b);
48
t2 = tci_read_s32(&tb_ptr);
37
- pp1b = (uint64_t)int128_getw1(b) * (uint64_t)int128_getw0(a);
49
*(uint8_t *)(t1 + t2) = t0;
38
- pp2 = (uint64_t)int128_getw1(a) * (uint64_t)int128_getw1(b);
50
@@ -XXX,XX +XXX,XX @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
39
-
51
#if TCG_TARGET_HAS_ext8u_i32
40
- pp1s = pp1a + pp1b;
52
case INDEX_op_ext8u_i32:
41
- if ((pp1s < pp1a) || (pp1s < pp1b)) {
53
t0 = *tb_ptr++;
42
- pp2 += (1ULL << 32);
54
- t1 = tci_read_r8(regs, &tb_ptr);
43
- }
55
- tci_write_reg(regs, t0, t1);
44
- uint64_t ret_low = pp0 + (pp1s << 32);
56
+ t1 = tci_read_r(regs, &tb_ptr);
45
- if ((ret_low < pp0) || (ret_low < (pp1s << 32))) {
57
+ tci_write_reg(regs, t0, (uint8_t)t1);
46
- pp2 += 1;
58
break;
47
- }
59
#endif
48
-
60
#if TCG_TARGET_HAS_ext16u_i32
49
- return int128_make128(ret_low, pp2 + (pp1s >> 32));
61
@@ -XXX,XX +XXX,XX @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
50
+ mulu64(&l, &h, ai, bi);
62
#if TCG_TARGET_HAS_ext8u_i64
51
+ return int128_make128(l, h);
63
case INDEX_op_ext8u_i64:
52
}
64
t0 = *tb_ptr++;
53
65
- t1 = tci_read_r8(regs, &tb_ptr);
54
static Int128 int128_sub_borrow(Int128 a, Int128 b, int borrow)
66
- tci_write_reg(regs, t0, t1);
67
+ t1 = tci_read_r(regs, &tb_ptr);
68
+ tci_write_reg(regs, t0, (uint8_t)t1);
69
break;
70
#endif
71
#if TCG_TARGET_HAS_ext8s_i64
72
--
55
--
73
2.25.1
56
2.43.0
74
75
diff view generated by jsdifflib
[PATCH 02/27] tcg/aarch64: Fix I3617_CMLE0
[PULL 71/72] target/hexagon: Simplify internal_mpyhh setup
1
Fix a typo in the encodeing of the cmle (zero) instruction.
1
Initialize x with accumulated via direct assignment,
2
rather than multiplying by 1.
2
3
3
Fixes: 14e4c1e2355 ("tcg/aarch64: Add vector operations")
4
Reviewed-by: Brian Cain <brian.cain@oss.qualcomm.com>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
---
6
---
6
tcg/aarch64/tcg-target.c.inc | 2 +-
7
target/hexagon/fma_emu.c | 2 +-
7
1 file changed, 1 insertion(+), 1 deletion(-)
8
1 file changed, 1 insertion(+), 1 deletion(-)
8
9
9
diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc
10
diff --git a/target/hexagon/fma_emu.c b/target/hexagon/fma_emu.c
10
index XXXXXXX..XXXXXXX 100644
11
index XXXXXXX..XXXXXXX 100644
11
--- a/tcg/aarch64/tcg-target.c.inc
12
--- a/target/hexagon/fma_emu.c
12
+++ b/tcg/aarch64/tcg-target.c.inc
13
+++ b/target/hexagon/fma_emu.c
13
@@ -XXX,XX +XXX,XX @@ typedef enum {
14
@@ -XXX,XX +XXX,XX @@ float64 internal_mpyhh(float64 a, float64 b,
14
I3617_CMEQ0 = 0x0e209800,
15
float64_is_infinity(b)) {
15
I3617_CMLT0 = 0x0e20a800,
16
return float64_mul(a, b, fp_status);
16
I3617_CMGE0 = 0x2e208800,
17
}
17
- I3617_CMLE0 = 0x2e20a800,
18
- x.mant = int128_mul_6464(accumulated, 1);
18
+ I3617_CMLE0 = 0x2e209800,
19
+ x.mant = int128_make64(accumulated);
19
I3617_NOT = 0x2e205800,
20
x.sticky = sticky;
20
I3617_ABS = 0x0e20b800,
21
prod = fGETUWORD(1, float64_getmant(a)) * fGETUWORD(1, float64_getmant(b));
21
I3617_NEG = 0x2e20b800,
22
x.mant = int128_add(x.mant, int128_mul_6464(prod, 0x100000000ULL));
22
--
23
--
23
2.25.1
24
2.43.0
24
25
diff view generated by jsdifflib
[PATCH 25/27] accel/tcg: drop the use of CF_HASH_MASK and rename params
[PULL 72/72] accel/tcg: Move gen_intermediate_code to TCGCPUOps.translate_core
1
From: Alex Bennée <alex.bennee@linaro.org>
1
Convert all targets simultaneously, as the gen_intermediate_code
2
function disappears from the target. While there are possible
3
workarounds, they're larger than simply performing the conversion.
2
4
3
We don't really deal in cf_mask most of the time. The one time it's
5
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
4
relevant is when we want to remove an invalidated TB from the QHT
5
lookup. Everywhere else we should be looking up things without
6
CF_INVALID set.
7
8
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
9
Message-Id: <20210224165811.11567-4-alex.bennee@linaro.org>
10
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
11
---
7
---
12
include/exec/exec-all.h | 4 +---
8
include/exec/translator.h | 14 --------------
13
include/exec/tb-lookup.h | 9 ++++++---
9
include/hw/core/tcg-cpu-ops.h | 13 +++++++++++++
14
accel/tcg/cpu-exec.c | 16 ++++++++--------
10
target/alpha/cpu.h | 2 ++
15
accel/tcg/tcg-runtime.c | 2 +-
11
target/arm/internals.h | 2 ++
16
accel/tcg/translate-all.c | 8 +++++---
12
target/avr/cpu.h | 2 ++
17
5 files changed, 21 insertions(+), 18 deletions(-)
13
target/hexagon/cpu.h | 2 ++
14
target/hppa/cpu.h | 2 ++
15
target/i386/tcg/helper-tcg.h | 2 ++
16
target/loongarch/internals.h | 2 ++
17
target/m68k/cpu.h | 2 ++
18
target/microblaze/cpu.h | 2 ++
19
target/mips/tcg/tcg-internal.h | 2 ++
20
target/openrisc/cpu.h | 2 ++
21
target/ppc/cpu.h | 2 ++
22
target/riscv/cpu.h | 3 +++
23
target/rx/cpu.h | 2 ++
24
target/s390x/s390x-internal.h | 2 ++
25
target/sh4/cpu.h | 2 ++
26
target/sparc/cpu.h | 2 ++
27
target/tricore/cpu.h | 2 ++
28
target/xtensa/cpu.h | 2 ++
29
accel/tcg/cpu-exec.c | 8 +++++---
30
accel/tcg/translate-all.c | 8 +++++---
31
target/alpha/cpu.c | 1 +
32
target/alpha/translate.c | 4 ++--
33
target/arm/cpu.c | 1 +
34
target/arm/tcg/cpu-v7m.c | 1 +
35
target/arm/tcg/translate.c | 5 ++---
36
target/avr/cpu.c | 1 +
37
target/avr/translate.c | 6 +++---
38
target/hexagon/cpu.c | 1 +
39
target/hexagon/translate.c | 4 ++--
40
target/hppa/cpu.c | 1 +
41
target/hppa/translate.c | 4 ++--
42
target/i386/tcg/tcg-cpu.c | 1 +
43
target/i386/tcg/translate.c | 5 ++---
44
target/loongarch/cpu.c | 1 +
45
target/loongarch/tcg/translate.c | 4 ++--
46
target/m68k/cpu.c | 1 +
47
target/m68k/translate.c | 4 ++--
48
target/microblaze/cpu.c | 1 +
49
target/microblaze/translate.c | 4 ++--
50
target/mips/cpu.c | 1 +
51
target/mips/tcg/translate.c | 4 ++--
52
target/openrisc/cpu.c | 1 +
53
target/openrisc/translate.c | 4 ++--
54
target/ppc/cpu_init.c | 1 +
55
target/ppc/translate.c | 4 ++--
56
target/riscv/tcg/tcg-cpu.c | 1 +
57
target/riscv/translate.c | 4 ++--
58
target/rx/cpu.c | 1 +
59
target/rx/translate.c | 4 ++--
60
target/s390x/cpu.c | 1 +
61
target/s390x/tcg/translate.c | 4 ++--
62
target/sh4/cpu.c | 1 +
63
target/sh4/translate.c | 4 ++--
64
target/sparc/cpu.c | 1 +
65
target/sparc/translate.c | 4 ++--
66
target/tricore/cpu.c | 1 +
67
target/tricore/translate.c | 5 ++---
68
target/xtensa/cpu.c | 1 +
69
target/xtensa/translate.c | 4 ++--
70
62 files changed, 121 insertions(+), 62 deletions(-)
18
71
19
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
72
diff --git a/include/exec/translator.h b/include/exec/translator.h
20
index XXXXXXX..XXXXXXX 100644
73
index XXXXXXX..XXXXXXX 100644
21
--- a/include/exec/exec-all.h
74
--- a/include/exec/translator.h
22
+++ b/include/exec/exec-all.h
75
+++ b/include/exec/translator.h
23
@@ -XXX,XX +XXX,XX @@ struct TranslationBlock {
24
#define CF_PARALLEL 0x00080000 /* Generate code for a parallel context */
25
#define CF_CLUSTER_MASK 0xff000000 /* Top 8 bits are cluster ID */
26
#define CF_CLUSTER_SHIFT 24
27
-/* cflags' mask for hashing/comparison, basically ignore CF_INVALID */
28
-#define CF_HASH_MASK (~CF_INVALID)
29
30
/* Per-vCPU dynamic tracing state used to generate this TB */
31
uint32_t trace_vcpu_dstate;
32
@@ -XXX,XX +XXX,XX @@ void tb_flush(CPUState *cpu);
33
void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr);
34
TranslationBlock *tb_htable_lookup(CPUState *cpu, target_ulong pc,
35
target_ulong cs_base, uint32_t flags,
36
- uint32_t cf_mask);
37
+ uint32_t cflags);
38
void tb_set_jmp_target(TranslationBlock *tb, int n, uintptr_t addr);
39
40
/* GETPC is the true target of the return instruction that we'll execute. */
41
diff --git a/include/exec/tb-lookup.h b/include/exec/tb-lookup.h
42
index XXXXXXX..XXXXXXX 100644
43
--- a/include/exec/tb-lookup.h
44
+++ b/include/exec/tb-lookup.h
45
@@ -XXX,XX +XXX,XX @@
76
@@ -XXX,XX +XXX,XX @@
46
/* Might cause an exception, so have a longjmp destination ready */
77
#include "qemu/bswap.h"
47
static inline TranslationBlock * tb_lookup(CPUState *cpu,
78
#include "exec/vaddr.h"
48
target_ulong pc, target_ulong cs_base,
79
49
- uint32_t flags, uint32_t cf_mask)
80
-/**
50
+ uint32_t flags, uint32_t cflags)
81
- * gen_intermediate_code
51
{
82
- * @cpu: cpu context
52
TranslationBlock *tb;
83
- * @tb: translation block
53
uint32_t hash;
84
- * @max_insns: max number of instructions to translate
54
85
- * @pc: guest virtual program counter address
55
+ /* we should never be trying to look up an INVALID tb */
86
- * @host_pc: host physical program counter address
56
+ tcg_debug_assert(!(cflags & CF_INVALID));
87
- *
88
- * This function must be provided by the target, which should create
89
- * the target-specific DisasContext, and then invoke translator_loop.
90
- */
91
-void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int *max_insns,
92
- vaddr pc, void *host_pc);
93
-
94
/**
95
* DisasJumpType:
96
* @DISAS_NEXT: Next instruction in program order.
97
diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h
98
index XXXXXXX..XXXXXXX 100644
99
--- a/include/hw/core/tcg-cpu-ops.h
100
+++ b/include/hw/core/tcg-cpu-ops.h
101
@@ -XXX,XX +XXX,XX @@ struct TCGCPUOps {
102
* Called when the first CPU is realized.
103
*/
104
void (*initialize)(void);
105
+ /**
106
+ * @translate_code: Translate guest instructions to TCGOps
107
+ * @cpu: cpu context
108
+ * @tb: translation block
109
+ * @max_insns: max number of instructions to translate
110
+ * @pc: guest virtual program counter address
111
+ * @host_pc: host physical program counter address
112
+ *
113
+ * This function must be provided by the target, which should create
114
+ * the target-specific DisasContext, and then invoke translator_loop.
115
+ */
116
+ void (*translate_code)(CPUState *cpu, TranslationBlock *tb,
117
+ int *max_insns, vaddr pc, void *host_pc);
118
/**
119
* @synchronize_from_tb: Synchronize state from a TCG #TranslationBlock
120
*
121
diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h
122
index XXXXXXX..XXXXXXX 100644
123
--- a/target/alpha/cpu.h
124
+++ b/target/alpha/cpu.h
125
@@ -XXX,XX +XXX,XX @@ enum {
126
};
127
128
void alpha_translate_init(void);
129
+void alpha_translate_code(CPUState *cs, TranslationBlock *tb,
130
+ int *max_insns, vaddr pc, void *host_pc);
131
132
#define CPU_RESOLVING_TYPE TYPE_ALPHA_CPU
133
134
diff --git a/target/arm/internals.h b/target/arm/internals.h
135
index XXXXXXX..XXXXXXX 100644
136
--- a/target/arm/internals.h
137
+++ b/target/arm/internals.h
138
@@ -XXX,XX +XXX,XX @@ void init_cpreg_list(ARMCPU *cpu);
139
140
void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu);
141
void arm_translate_init(void);
142
+void arm_translate_code(CPUState *cs, TranslationBlock *tb,
143
+ int *max_insns, vaddr pc, void *host_pc);
144
145
void arm_cpu_register_gdb_commands(ARMCPU *cpu);
146
void aarch64_cpu_register_gdb_commands(ARMCPU *cpu, GString *,
147
diff --git a/target/avr/cpu.h b/target/avr/cpu.h
148
index XXXXXXX..XXXXXXX 100644
149
--- a/target/avr/cpu.h
150
+++ b/target/avr/cpu.h
151
@@ -XXX,XX +XXX,XX @@ static inline void set_avr_feature(CPUAVRState *env, int feature)
152
}
153
154
void avr_cpu_tcg_init(void);
155
+void avr_cpu_translate_code(CPUState *cs, TranslationBlock *tb,
156
+ int *max_insns, vaddr pc, void *host_pc);
157
158
int cpu_avr_exec(CPUState *cpu);
159
160
diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h
161
index XXXXXXX..XXXXXXX 100644
162
--- a/target/hexagon/cpu.h
163
+++ b/target/hexagon/cpu.h
164
@@ -XXX,XX +XXX,XX @@ static inline void cpu_get_tb_cpu_state(CPUHexagonState *env, vaddr *pc,
165
typedef HexagonCPU ArchCPU;
166
167
void hexagon_translate_init(void);
168
+void hexagon_translate_code(CPUState *cs, TranslationBlock *tb,
169
+ int *max_insns, vaddr pc, void *host_pc);
170
171
#include "exec/cpu-all.h"
172
173
diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h
174
index XXXXXXX..XXXXXXX 100644
175
--- a/target/hppa/cpu.h
176
+++ b/target/hppa/cpu.h
177
@@ -XXX,XX +XXX,XX @@ static inline int HPPA_BTLB_ENTRIES(CPUHPPAState *env)
178
}
179
180
void hppa_translate_init(void);
181
+void hppa_translate_code(CPUState *cs, TranslationBlock *tb,
182
+ int *max_insns, vaddr pc, void *host_pc);
183
184
#define CPU_RESOLVING_TYPE TYPE_HPPA_CPU
185
186
diff --git a/target/i386/tcg/helper-tcg.h b/target/i386/tcg/helper-tcg.h
187
index XXXXXXX..XXXXXXX 100644
188
--- a/target/i386/tcg/helper-tcg.h
189
+++ b/target/i386/tcg/helper-tcg.h
190
@@ -XXX,XX +XXX,XX @@ static inline target_long lshift(target_long x, int n)
191
192
/* translate.c */
193
void tcg_x86_init(void);
194
+void x86_translate_code(CPUState *cs, TranslationBlock *tb,
195
+ int *max_insns, vaddr pc, void *host_pc);
196
197
/* excp_helper.c */
198
G_NORETURN void raise_exception(CPUX86State *env, int exception_index);
199
diff --git a/target/loongarch/internals.h b/target/loongarch/internals.h
200
index XXXXXXX..XXXXXXX 100644
201
--- a/target/loongarch/internals.h
202
+++ b/target/loongarch/internals.h
203
@@ -XXX,XX +XXX,XX @@
204
#define TARGET_VIRT_MASK MAKE_64BIT_MASK(0, TARGET_VIRT_ADDR_SPACE_BITS)
205
206
void loongarch_translate_init(void);
207
+void loongarch_translate_code(CPUState *cs, TranslationBlock *tb,
208
+ int *max_insns, vaddr pc, void *host_pc);
209
210
void G_NORETURN do_raise_exception(CPULoongArchState *env,
211
uint32_t exception,
212
diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h
213
index XXXXXXX..XXXXXXX 100644
214
--- a/target/m68k/cpu.h
215
+++ b/target/m68k/cpu.h
216
@@ -XXX,XX +XXX,XX @@ int m68k_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
217
int m68k_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
218
219
void m68k_tcg_init(void);
220
+void m68k_translate_code(CPUState *cs, TranslationBlock *tb,
221
+ int *max_insns, vaddr pc, void *host_pc);
222
void m68k_cpu_init_gdb(M68kCPU *cpu);
223
uint32_t cpu_m68k_get_ccr(CPUM68KState *env);
224
void cpu_m68k_set_ccr(CPUM68KState *env, uint32_t);
225
diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
226
index XXXXXXX..XXXXXXX 100644
227
--- a/target/microblaze/cpu.h
228
+++ b/target/microblaze/cpu.h
229
@@ -XXX,XX +XXX,XX @@ static inline void mb_cpu_write_msr(CPUMBState *env, uint32_t val)
230
}
231
232
void mb_tcg_init(void);
233
+void mb_translate_code(CPUState *cs, TranslationBlock *tb,
234
+ int *max_insns, vaddr pc, void *host_pc);
235
236
#define CPU_RESOLVING_TYPE TYPE_MICROBLAZE_CPU
237
238
diff --git a/target/mips/tcg/tcg-internal.h b/target/mips/tcg/tcg-internal.h
239
index XXXXXXX..XXXXXXX 100644
240
--- a/target/mips/tcg/tcg-internal.h
241
+++ b/target/mips/tcg/tcg-internal.h
242
@@ -XXX,XX +XXX,XX @@
243
#include "cpu.h"
244
245
void mips_tcg_init(void);
246
+void mips_translate_code(CPUState *cs, TranslationBlock *tb,
247
+ int *max_insns, vaddr pc, void *host_pc);
248
249
void mips_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb);
250
G_NORETURN void mips_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
251
diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h
252
index XXXXXXX..XXXXXXX 100644
253
--- a/target/openrisc/cpu.h
254
+++ b/target/openrisc/cpu.h
255
@@ -XXX,XX +XXX,XX @@ void openrisc_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
256
int openrisc_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
257
int openrisc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
258
void openrisc_translate_init(void);
259
+void openrisc_translate_code(CPUState *cs, TranslationBlock *tb,
260
+ int *max_insns, vaddr pc, void *host_pc);
261
int print_insn_or1k(bfd_vma addr, disassemble_info *info);
262
263
#ifndef CONFIG_USER_ONLY
264
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
265
index XXXXXXX..XXXXXXX 100644
266
--- a/target/ppc/cpu.h
267
+++ b/target/ppc/cpu.h
268
@@ -XXX,XX +XXX,XX @@ extern const VMStateDescription vmstate_ppc_cpu;
269
270
/*****************************************************************************/
271
void ppc_translate_init(void);
272
+void ppc_translate_code(CPUState *cs, TranslationBlock *tb,
273
+ int *max_insns, vaddr pc, void *host_pc);
274
275
#if !defined(CONFIG_USER_ONLY)
276
void ppc_store_sdr1(CPUPPCState *env, target_ulong value);
277
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
278
index XXXXXXX..XXXXXXX 100644
279
--- a/target/riscv/cpu.h
280
+++ b/target/riscv/cpu.h
281
@@ -XXX,XX +XXX,XX @@ RISCVException smstateen_acc_ok(CPURISCVState *env, int index, uint64_t bit);
282
void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv, bool virt_en);
283
284
void riscv_translate_init(void);
285
+void riscv_translate_code(CPUState *cs, TranslationBlock *tb,
286
+ int *max_insns, vaddr pc, void *host_pc);
57
+
287
+
58
hash = tb_jmp_cache_hash_func(pc);
288
G_NORETURN void riscv_raise_exception(CPURISCVState *env,
59
tb = qatomic_rcu_read(&cpu->tb_jmp_cache[hash]);
289
uint32_t exception, uintptr_t pc);
60
290
61
@@ -XXX,XX +XXX,XX @@ static inline TranslationBlock * tb_lookup(CPUState *cpu,
291
diff --git a/target/rx/cpu.h b/target/rx/cpu.h
62
tb->cs_base == cs_base &&
292
index XXXXXXX..XXXXXXX 100644
63
tb->flags == flags &&
293
--- a/target/rx/cpu.h
64
tb->trace_vcpu_dstate == *cpu->trace_dstate &&
294
+++ b/target/rx/cpu.h
65
- (tb_cflags(tb) & (CF_HASH_MASK | CF_INVALID)) == cf_mask)) {
295
@@ -XXX,XX +XXX,XX @@ int rx_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
66
+ tb_cflags(tb) == cflags)) {
296
int rx_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
67
return tb;
297
68
}
298
void rx_translate_init(void);
69
- tb = tb_htable_lookup(cpu, pc, cs_base, flags, cf_mask);
299
+void rx_translate_code(CPUState *cs, TranslationBlock *tb,
70
+ tb = tb_htable_lookup(cpu, pc, cs_base, flags, cflags);
300
+ int *max_insns, vaddr pc, void *host_pc);
71
if (tb == NULL) {
301
void rx_cpu_unpack_psw(CPURXState *env, uint32_t psw, int rte);
72
return NULL;
302
73
}
303
#include "exec/cpu-all.h"
304
diff --git a/target/s390x/s390x-internal.h b/target/s390x/s390x-internal.h
305
index XXXXXXX..XXXXXXX 100644
306
--- a/target/s390x/s390x-internal.h
307
+++ b/target/s390x/s390x-internal.h
308
@@ -XXX,XX +XXX,XX @@ void handle_diag_308(CPUS390XState *env, uint64_t r1, uint64_t r3,
309
310
/* translate.c */
311
void s390x_translate_init(void);
312
+void s390x_translate_code(CPUState *cs, TranslationBlock *tb,
313
+ int *max_insns, vaddr pc, void *host_pc);
314
void s390x_restore_state_to_opc(CPUState *cs,
315
const TranslationBlock *tb,
316
const uint64_t *data);
317
diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h
318
index XXXXXXX..XXXXXXX 100644
319
--- a/target/sh4/cpu.h
320
+++ b/target/sh4/cpu.h
321
@@ -XXX,XX +XXX,XX @@ G_NORETURN void superh_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
322
uintptr_t retaddr);
323
324
void sh4_translate_init(void);
325
+void sh4_translate_code(CPUState *cs, TranslationBlock *tb,
326
+ int *max_insns, vaddr pc, void *host_pc);
327
328
#if !defined(CONFIG_USER_ONLY)
329
hwaddr superh_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
330
diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h
331
index XXXXXXX..XXXXXXX 100644
332
--- a/target/sparc/cpu.h
333
+++ b/target/sparc/cpu.h
334
@@ -XXX,XX +XXX,XX @@ int sparc_cpu_memory_rw_debug(CPUState *cpu, vaddr addr,
335
336
/* translate.c */
337
void sparc_tcg_init(void);
338
+void sparc_translate_code(CPUState *cs, TranslationBlock *tb,
339
+ int *max_insns, vaddr pc, void *host_pc);
340
341
/* fop_helper.c */
342
target_ulong cpu_get_fsr(CPUSPARCState *);
343
diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h
344
index XXXXXXX..XXXXXXX 100644
345
--- a/target/tricore/cpu.h
346
+++ b/target/tricore/cpu.h
347
@@ -XXX,XX +XXX,XX @@ FIELD(TB_FLAGS, PRIV, 0, 2)
348
349
void cpu_state_reset(CPUTriCoreState *s);
350
void tricore_tcg_init(void);
351
+void tricore_translate_code(CPUState *cs, TranslationBlock *tb,
352
+ int *max_insns, vaddr pc, void *host_pc);
353
354
static inline void cpu_get_tb_cpu_state(CPUTriCoreState *env, vaddr *pc,
355
uint64_t *cs_base, uint32_t *flags)
356
diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h
357
index XXXXXXX..XXXXXXX 100644
358
--- a/target/xtensa/cpu.h
359
+++ b/target/xtensa/cpu.h
360
@@ -XXX,XX +XXX,XX @@ G_NORETURN void xtensa_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
361
362
void xtensa_collect_sr_names(const XtensaConfig *config);
363
void xtensa_translate_init(void);
364
+void xtensa_translate_code(CPUState *cs, TranslationBlock *tb,
365
+ int *max_insns, vaddr pc, void *host_pc);
366
void **xtensa_get_regfile_by_name(const char *name, int entries, int bits);
367
void xtensa_breakpoint_handler(CPUState *cs);
368
void xtensa_register_core(XtensaConfigList *node);
74
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
369
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
75
index XXXXXXX..XXXXXXX 100644
370
index XXXXXXX..XXXXXXX 100644
76
--- a/accel/tcg/cpu-exec.c
371
--- a/accel/tcg/cpu-exec.c
77
+++ b/accel/tcg/cpu-exec.c
372
+++ b/accel/tcg/cpu-exec.c
78
@@ -XXX,XX +XXX,XX @@ struct tb_desc {
373
@@ -XXX,XX +XXX,XX @@ bool tcg_exec_realizefn(CPUState *cpu, Error **errp)
79
CPUArchState *env;
374
80
tb_page_addr_t phys_page1;
375
if (!tcg_target_initialized) {
81
uint32_t flags;
376
/* Check mandatory TCGCPUOps handlers */
82
- uint32_t cf_mask;
377
+ const TCGCPUOps *tcg_ops = cpu->cc->tcg_ops;
83
+ uint32_t cflags;
378
#ifndef CONFIG_USER_ONLY
84
uint32_t trace_vcpu_dstate;
379
- assert(cpu->cc->tcg_ops->cpu_exec_halt);
85
};
380
- assert(cpu->cc->tcg_ops->cpu_exec_interrupt);
86
381
+ assert(tcg_ops->cpu_exec_halt);
87
@@ -XXX,XX +XXX,XX @@ static bool tb_lookup_cmp(const void *p, const void *d)
382
+ assert(tcg_ops->cpu_exec_interrupt);
88
tb->cs_base == desc->cs_base &&
383
#endif /* !CONFIG_USER_ONLY */
89
tb->flags == desc->flags &&
384
- cpu->cc->tcg_ops->initialize();
90
tb->trace_vcpu_dstate == desc->trace_vcpu_dstate &&
385
+ assert(tcg_ops->translate_code);
91
- (tb_cflags(tb) & (CF_HASH_MASK | CF_INVALID)) == desc->cf_mask) {
386
+ tcg_ops->initialize();
92
+ tb_cflags(tb) == desc->cflags) {
387
tcg_target_initialized = true;
93
/* check next page if needed */
94
if (tb->page_addr[1] == -1) {
95
return true;
96
@@ -XXX,XX +XXX,XX @@ static bool tb_lookup_cmp(const void *p, const void *d)
97
98
TranslationBlock *tb_htable_lookup(CPUState *cpu, target_ulong pc,
99
target_ulong cs_base, uint32_t flags,
100
- uint32_t cf_mask)
101
+ uint32_t cflags)
102
{
103
tb_page_addr_t phys_pc;
104
struct tb_desc desc;
105
@@ -XXX,XX +XXX,XX @@ TranslationBlock *tb_htable_lookup(CPUState *cpu, target_ulong pc,
106
desc.env = (CPUArchState *)cpu->env_ptr;
107
desc.cs_base = cs_base;
108
desc.flags = flags;
109
- desc.cf_mask = cf_mask;
110
+ desc.cflags = cflags;
111
desc.trace_vcpu_dstate = *cpu->trace_dstate;
112
desc.pc = pc;
113
phys_pc = get_page_addr_code(desc.env, pc);
114
@@ -XXX,XX +XXX,XX @@ TranslationBlock *tb_htable_lookup(CPUState *cpu, target_ulong pc,
115
return NULL;
116
}
388
}
117
desc.phys_page1 = phys_pc & TARGET_PAGE_MASK;
118
- h = tb_hash_func(phys_pc, pc, flags, cf_mask, *cpu->trace_dstate);
119
+ h = tb_hash_func(phys_pc, pc, flags, cflags, *cpu->trace_dstate);
120
return qht_lookup_custom(&tb_ctx.htable, &desc, h, tb_lookup_cmp);
121
}
122
123
@@ -XXX,XX +XXX,XX @@ static inline void tb_add_jump(TranslationBlock *tb, int n,
124
125
static inline TranslationBlock *tb_find(CPUState *cpu,
126
TranslationBlock *last_tb,
127
- int tb_exit, uint32_t cf_mask)
128
+ int tb_exit, uint32_t cflags)
129
{
130
CPUArchState *env = (CPUArchState *)cpu->env_ptr;
131
TranslationBlock *tb;
132
@@ -XXX,XX +XXX,XX @@ static inline TranslationBlock *tb_find(CPUState *cpu,
133
134
cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags);
135
136
- tb = tb_lookup(cpu, pc, cs_base, flags, cf_mask);
137
+ tb = tb_lookup(cpu, pc, cs_base, flags, cflags);
138
if (tb == NULL) {
139
mmap_lock();
140
- tb = tb_gen_code(cpu, pc, cs_base, flags, cf_mask);
141
+ tb = tb_gen_code(cpu, pc, cs_base, flags, cflags);
142
mmap_unlock();
143
/* We add the TB in the virtual pc hash table for the fast lookup */
144
qatomic_set(&cpu->tb_jmp_cache[tb_jmp_cache_hash_func(pc)], tb);
145
diff --git a/accel/tcg/tcg-runtime.c b/accel/tcg/tcg-runtime.c
146
index XXXXXXX..XXXXXXX 100644
147
--- a/accel/tcg/tcg-runtime.c
148
+++ b/accel/tcg/tcg-runtime.c
149
@@ -XXX,XX +XXX,XX @@
150
#include "exec/helper-proto.h"
151
#include "exec/cpu_ldst.h"
152
#include "exec/exec-all.h"
153
-#include "exec/tb-lookup.h"
154
#include "disas/disas.h"
155
#include "exec/log.h"
156
#include "tcg/tcg.h"
157
+#include "exec/tb-lookup.h"
158
159
/* 32-bit helpers */
160
389
161
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
390
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
162
index XXXXXXX..XXXXXXX 100644
391
index XXXXXXX..XXXXXXX 100644
163
--- a/accel/tcg/translate-all.c
392
--- a/accel/tcg/translate-all.c
164
+++ b/accel/tcg/translate-all.c
393
+++ b/accel/tcg/translate-all.c
165
@@ -XXX,XX +XXX,XX @@ static bool tb_cmp(const void *ap, const void *bp)
394
@@ -XXX,XX +XXX,XX @@ static int setjmp_gen_code(CPUArchState *env, TranslationBlock *tb,
166
return a->pc == b->pc &&
395
167
a->cs_base == b->cs_base &&
396
tcg_func_start(tcg_ctx);
168
a->flags == b->flags &&
397
169
- (tb_cflags(a) & CF_HASH_MASK) == (tb_cflags(b) & CF_HASH_MASK) &&
398
- tcg_ctx->cpu = env_cpu(env);
170
+ (tb_cflags(a) & ~CF_INVALID) == (tb_cflags(b) & ~CF_INVALID) &&
399
- gen_intermediate_code(env_cpu(env), tb, max_insns, pc, host_pc);
171
a->trace_vcpu_dstate == b->trace_vcpu_dstate &&
400
+ CPUState *cs = env_cpu(env);
172
a->page_addr[0] == b->page_addr[0] &&
401
+ tcg_ctx->cpu = cs;
173
a->page_addr[1] == b->page_addr[1];
402
+ cs->cc->tcg_ops->translate_code(cs, tb, max_insns, pc, host_pc);
174
@@ -XXX,XX +XXX,XX @@ static void do_tb_phys_invalidate(TranslationBlock *tb, bool rm_from_page_list)
403
+
175
PageDesc *p;
404
assert(tb->size != 0);
176
uint32_t h;
405
tcg_ctx->cpu = NULL;
177
tb_page_addr_t phys_pc;
406
*max_insns = tb->icount;
178
+ uint32_t orig_cflags = tb_cflags(tb);
407
@@ -XXX,XX +XXX,XX @@ TranslationBlock *tb_gen_code(CPUState *cpu,
179
408
/*
180
assert_memory_lock();
409
* Overflow of code_gen_buffer, or the current slice of it.
181
410
*
182
@@ -XXX,XX +XXX,XX @@ static void do_tb_phys_invalidate(TranslationBlock *tb, bool rm_from_page_list)
411
- * TODO: We don't need to re-do gen_intermediate_code, nor
183
412
+ * TODO: We don't need to re-do tcg_ops->translate_code, nor
184
/* remove the TB from the hash list */
413
* should we re-do the tcg optimization currently hidden
185
phys_pc = tb->page_addr[0] + (tb->pc & ~TARGET_PAGE_MASK);
414
* inside tcg_gen_code. All that should be required is to
186
- h = tb_hash_func(phys_pc, tb->pc, tb->flags, tb_cflags(tb) & CF_HASH_MASK,
415
* flush the TBs, allocate a new TB, re-initialize it per
187
+ h = tb_hash_func(phys_pc, tb->pc, tb->flags, orig_cflags,
416
diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c
188
tb->trace_vcpu_dstate);
417
index XXXXXXX..XXXXXXX 100644
189
if (!qht_remove(&tb_ctx.htable, tb, h)) {
418
--- a/target/alpha/cpu.c
190
return;
419
+++ b/target/alpha/cpu.c
191
@@ -XXX,XX +XXX,XX @@ tb_link_page(TranslationBlock *tb, tb_page_addr_t phys_pc,
420
@@ -XXX,XX +XXX,XX @@ static const struct SysemuCPUOps alpha_sysemu_ops = {
192
uint32_t h;
421
193
422
static const TCGCPUOps alpha_tcg_ops = {
194
assert_memory_lock();
423
.initialize = alpha_translate_init,
195
+ tcg_debug_assert(!(tb->cflags & CF_INVALID));
424
+ .translate_code = alpha_translate_code,
196
425
.synchronize_from_tb = alpha_cpu_synchronize_from_tb,
197
/*
426
.restore_state_to_opc = alpha_restore_state_to_opc,
198
* Add the TB to the page list, acquiring first the pages's locks.
427
199
@@ -XXX,XX +XXX,XX @@ tb_link_page(TranslationBlock *tb, tb_page_addr_t phys_pc,
428
diff --git a/target/alpha/translate.c b/target/alpha/translate.c
200
}
429
index XXXXXXX..XXXXXXX 100644
201
430
--- a/target/alpha/translate.c
202
/* add in the hash table */
431
+++ b/target/alpha/translate.c
203
- h = tb_hash_func(phys_pc, tb->pc, tb->flags, tb->cflags & CF_HASH_MASK,
432
@@ -XXX,XX +XXX,XX @@ static const TranslatorOps alpha_tr_ops = {
204
+ h = tb_hash_func(phys_pc, tb->pc, tb->flags, tb->cflags,
433
.tb_stop = alpha_tr_tb_stop,
205
tb->trace_vcpu_dstate);
434
};
206
qht_insert(&tb_ctx.htable, tb, h, &existing_tb);
435
207
436
-void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int *max_insns,
437
- vaddr pc, void *host_pc)
438
+void alpha_translate_code(CPUState *cpu, TranslationBlock *tb,
439
+ int *max_insns, vaddr pc, void *host_pc)
440
{
441
DisasContext dc;
442
translator_loop(cpu, tb, max_insns, pc, host_pc, &alpha_tr_ops, &dc.base);
443
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
444
index XXXXXXX..XXXXXXX 100644
445
--- a/target/arm/cpu.c
446
+++ b/target/arm/cpu.c
447
@@ -XXX,XX +XXX,XX @@ static const struct SysemuCPUOps arm_sysemu_ops = {
448
#ifdef CONFIG_TCG
449
static const TCGCPUOps arm_tcg_ops = {
450
.initialize = arm_translate_init,
451
+ .translate_code = arm_translate_code,
452
.synchronize_from_tb = arm_cpu_synchronize_from_tb,
453
.debug_excp_handler = arm_debug_excp_handler,
454
.restore_state_to_opc = arm_restore_state_to_opc,
455
diff --git a/target/arm/tcg/cpu-v7m.c b/target/arm/tcg/cpu-v7m.c
456
index XXXXXXX..XXXXXXX 100644
457
--- a/target/arm/tcg/cpu-v7m.c
458
+++ b/target/arm/tcg/cpu-v7m.c
459
@@ -XXX,XX +XXX,XX @@ static void cortex_m55_initfn(Object *obj)
460
461
static const TCGCPUOps arm_v7m_tcg_ops = {
462
.initialize = arm_translate_init,
463
+ .translate_code = arm_translate_code,
464
.synchronize_from_tb = arm_cpu_synchronize_from_tb,
465
.debug_excp_handler = arm_debug_excp_handler,
466
.restore_state_to_opc = arm_restore_state_to_opc,
467
diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c
468
index XXXXXXX..XXXXXXX 100644
469
--- a/target/arm/tcg/translate.c
470
+++ b/target/arm/tcg/translate.c
471
@@ -XXX,XX +XXX,XX @@ static const TranslatorOps thumb_translator_ops = {
472
.tb_stop = arm_tr_tb_stop,
473
};
474
475
-/* generate intermediate code for basic block 'tb'. */
476
-void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int *max_insns,
477
- vaddr pc, void *host_pc)
478
+void arm_translate_code(CPUState *cpu, TranslationBlock *tb,
479
+ int *max_insns, vaddr pc, void *host_pc)
480
{
481
DisasContext dc = { };
482
const TranslatorOps *ops = &arm_translator_ops;
483
diff --git a/target/avr/cpu.c b/target/avr/cpu.c
484
index XXXXXXX..XXXXXXX 100644
485
--- a/target/avr/cpu.c
486
+++ b/target/avr/cpu.c
487
@@ -XXX,XX +XXX,XX @@ static const struct SysemuCPUOps avr_sysemu_ops = {
488
489
static const TCGCPUOps avr_tcg_ops = {
490
.initialize = avr_cpu_tcg_init,
491
+ .translate_code = avr_cpu_translate_code,
492
.synchronize_from_tb = avr_cpu_synchronize_from_tb,
493
.restore_state_to_opc = avr_restore_state_to_opc,
494
.cpu_exec_interrupt = avr_cpu_exec_interrupt,
495
diff --git a/target/avr/translate.c b/target/avr/translate.c
496
index XXXXXXX..XXXXXXX 100644
497
--- a/target/avr/translate.c
498
+++ b/target/avr/translate.c
499
@@ -XXX,XX +XXX,XX @@ static bool trans_WDR(DisasContext *ctx, arg_WDR *a)
500
*
501
* - translate()
502
* - canonicalize_skip()
503
- * - gen_intermediate_code()
504
+ * - translate_code()
505
* - restore_state_to_opc()
506
*
507
*/
508
@@ -XXX,XX +XXX,XX @@ static const TranslatorOps avr_tr_ops = {
509
.tb_stop = avr_tr_tb_stop,
510
};
511
512
-void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns,
513
- vaddr pc, void *host_pc)
514
+void avr_cpu_translate_code(CPUState *cs, TranslationBlock *tb,
515
+ int *max_insns, vaddr pc, void *host_pc)
516
{
517
DisasContext dc = { };
518
translator_loop(cs, tb, max_insns, pc, host_pc, &avr_tr_ops, &dc.base);
519
diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c
520
index XXXXXXX..XXXXXXX 100644
521
--- a/target/hexagon/cpu.c
522
+++ b/target/hexagon/cpu.c
523
@@ -XXX,XX +XXX,XX @@ static void hexagon_cpu_init(Object *obj)
524
525
static const TCGCPUOps hexagon_tcg_ops = {
526
.initialize = hexagon_translate_init,
527
+ .translate_code = hexagon_translate_code,
528
.synchronize_from_tb = hexagon_cpu_synchronize_from_tb,
529
.restore_state_to_opc = hexagon_restore_state_to_opc,
530
};
531
diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c
532
index XXXXXXX..XXXXXXX 100644
533
--- a/target/hexagon/translate.c
534
+++ b/target/hexagon/translate.c
535
@@ -XXX,XX +XXX,XX @@ static const TranslatorOps hexagon_tr_ops = {
536
.tb_stop = hexagon_tr_tb_stop,
537
};
538
539
-void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns,
540
- vaddr pc, void *host_pc)
541
+void hexagon_translate_code(CPUState *cs, TranslationBlock *tb,
542
+ int *max_insns, vaddr pc, void *host_pc)
543
{
544
DisasContext ctx;
545
546
diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c
547
index XXXXXXX..XXXXXXX 100644
548
--- a/target/hppa/cpu.c
549
+++ b/target/hppa/cpu.c
550
@@ -XXX,XX +XXX,XX @@ static const struct SysemuCPUOps hppa_sysemu_ops = {
551
552
static const TCGCPUOps hppa_tcg_ops = {
553
.initialize = hppa_translate_init,
554
+ .translate_code = hppa_translate_code,
555
.synchronize_from_tb = hppa_cpu_synchronize_from_tb,
556
.restore_state_to_opc = hppa_restore_state_to_opc,
557
558
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
559
index XXXXXXX..XXXXXXX 100644
560
--- a/target/hppa/translate.c
561
+++ b/target/hppa/translate.c
562
@@ -XXX,XX +XXX,XX @@ static const TranslatorOps hppa_tr_ops = {
563
#endif
564
};
565
566
-void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns,
567
- vaddr pc, void *host_pc)
568
+void hppa_translate_code(CPUState *cs, TranslationBlock *tb,
569
+ int *max_insns, vaddr pc, void *host_pc)
570
{
571
DisasContext ctx = { };
572
translator_loop(cs, tb, max_insns, pc, host_pc, &hppa_tr_ops, &ctx.base);
573
diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c
574
index XXXXXXX..XXXXXXX 100644
575
--- a/target/i386/tcg/tcg-cpu.c
576
+++ b/target/i386/tcg/tcg-cpu.c
577
@@ -XXX,XX +XXX,XX @@ static bool x86_debug_check_breakpoint(CPUState *cs)
578
579
static const TCGCPUOps x86_tcg_ops = {
580
.initialize = tcg_x86_init,
581
+ .translate_code = x86_translate_code,
582
.synchronize_from_tb = x86_cpu_synchronize_from_tb,
583
.restore_state_to_opc = x86_restore_state_to_opc,
584
.cpu_exec_enter = x86_cpu_exec_enter,
585
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
586
index XXXXXXX..XXXXXXX 100644
587
--- a/target/i386/tcg/translate.c
588
+++ b/target/i386/tcg/translate.c
589
@@ -XXX,XX +XXX,XX @@ static const TranslatorOps i386_tr_ops = {
590
.tb_stop = i386_tr_tb_stop,
591
};
592
593
-/* generate intermediate code for basic block 'tb'. */
594
-void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int *max_insns,
595
- vaddr pc, void *host_pc)
596
+void x86_translate_code(CPUState *cpu, TranslationBlock *tb,
597
+ int *max_insns, vaddr pc, void *host_pc)
598
{
599
DisasContext dc;
600
601
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
602
index XXXXXXX..XXXXXXX 100644
603
--- a/target/loongarch/cpu.c
604
+++ b/target/loongarch/cpu.c
605
@@ -XXX,XX +XXX,XX @@ static void loongarch_cpu_dump_state(CPUState *cs, FILE *f, int flags)
606
607
static const TCGCPUOps loongarch_tcg_ops = {
608
.initialize = loongarch_translate_init,
609
+ .translate_code = loongarch_translate_code,
610
.synchronize_from_tb = loongarch_cpu_synchronize_from_tb,
611
.restore_state_to_opc = loongarch_restore_state_to_opc,
612
613
diff --git a/target/loongarch/tcg/translate.c b/target/loongarch/tcg/translate.c
614
index XXXXXXX..XXXXXXX 100644
615
--- a/target/loongarch/tcg/translate.c
616
+++ b/target/loongarch/tcg/translate.c
617
@@ -XXX,XX +XXX,XX @@ static const TranslatorOps loongarch_tr_ops = {
618
.tb_stop = loongarch_tr_tb_stop,
619
};
620
621
-void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns,
622
- vaddr pc, void *host_pc)
623
+void loongarch_translate_code(CPUState *cs, TranslationBlock *tb,
624
+ int *max_insns, vaddr pc, void *host_pc)
625
{
626
DisasContext ctx;
627
628
diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c
629
index XXXXXXX..XXXXXXX 100644
630
--- a/target/m68k/cpu.c
631
+++ b/target/m68k/cpu.c
632
@@ -XXX,XX +XXX,XX @@ static const struct SysemuCPUOps m68k_sysemu_ops = {
633
634
static const TCGCPUOps m68k_tcg_ops = {
635
.initialize = m68k_tcg_init,
636
+ .translate_code = m68k_translate_code,
637
.restore_state_to_opc = m68k_restore_state_to_opc,
638
639
#ifndef CONFIG_USER_ONLY
640
diff --git a/target/m68k/translate.c b/target/m68k/translate.c
641
index XXXXXXX..XXXXXXX 100644
642
--- a/target/m68k/translate.c
643
+++ b/target/m68k/translate.c
644
@@ -XXX,XX +XXX,XX @@ static const TranslatorOps m68k_tr_ops = {
645
.tb_stop = m68k_tr_tb_stop,
646
};
647
648
-void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int *max_insns,
649
- vaddr pc, void *host_pc)
650
+void m68k_translate_code(CPUState *cpu, TranslationBlock *tb,
651
+ int *max_insns, vaddr pc, void *host_pc)
652
{
653
DisasContext dc;
654
translator_loop(cpu, tb, max_insns, pc, host_pc, &m68k_tr_ops, &dc.base);
655
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
656
index XXXXXXX..XXXXXXX 100644
657
--- a/target/microblaze/cpu.c
658
+++ b/target/microblaze/cpu.c
659
@@ -XXX,XX +XXX,XX @@ static const struct SysemuCPUOps mb_sysemu_ops = {
660
661
static const TCGCPUOps mb_tcg_ops = {
662
.initialize = mb_tcg_init,
663
+ .translate_code = mb_translate_code,
664
.synchronize_from_tb = mb_cpu_synchronize_from_tb,
665
.restore_state_to_opc = mb_restore_state_to_opc,
666
667
diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
668
index XXXXXXX..XXXXXXX 100644
669
--- a/target/microblaze/translate.c
670
+++ b/target/microblaze/translate.c
671
@@ -XXX,XX +XXX,XX @@ static const TranslatorOps mb_tr_ops = {
672
.tb_stop = mb_tr_tb_stop,
673
};
674
675
-void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int *max_insns,
676
- vaddr pc, void *host_pc)
677
+void mb_translate_code(CPUState *cpu, TranslationBlock *tb,
678
+ int *max_insns, vaddr pc, void *host_pc)
679
{
680
DisasContext dc;
681
translator_loop(cpu, tb, max_insns, pc, host_pc, &mb_tr_ops, &dc.base);
682
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
683
index XXXXXXX..XXXXXXX 100644
684
--- a/target/mips/cpu.c
685
+++ b/target/mips/cpu.c
686
@@ -XXX,XX +XXX,XX @@ static const Property mips_cpu_properties[] = {
687
#include "hw/core/tcg-cpu-ops.h"
688
static const TCGCPUOps mips_tcg_ops = {
689
.initialize = mips_tcg_init,
690
+ .translate_code = mips_translate_code,
691
.synchronize_from_tb = mips_cpu_synchronize_from_tb,
692
.restore_state_to_opc = mips_restore_state_to_opc,
693
694
diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
695
index XXXXXXX..XXXXXXX 100644
696
--- a/target/mips/tcg/translate.c
697
+++ b/target/mips/tcg/translate.c
698
@@ -XXX,XX +XXX,XX @@ static const TranslatorOps mips_tr_ops = {
699
.tb_stop = mips_tr_tb_stop,
700
};
701
702
-void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns,
703
- vaddr pc, void *host_pc)
704
+void mips_translate_code(CPUState *cs, TranslationBlock *tb,
705
+ int *max_insns, vaddr pc, void *host_pc)
706
{
707
DisasContext ctx;
708
709
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
710
index XXXXXXX..XXXXXXX 100644
711
--- a/target/openrisc/cpu.c
712
+++ b/target/openrisc/cpu.c
713
@@ -XXX,XX +XXX,XX @@ static const struct SysemuCPUOps openrisc_sysemu_ops = {
714
715
static const TCGCPUOps openrisc_tcg_ops = {
716
.initialize = openrisc_translate_init,
717
+ .translate_code = openrisc_translate_code,
718
.synchronize_from_tb = openrisc_cpu_synchronize_from_tb,
719
.restore_state_to_opc = openrisc_restore_state_to_opc,
720
721
diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c
722
index XXXXXXX..XXXXXXX 100644
723
--- a/target/openrisc/translate.c
724
+++ b/target/openrisc/translate.c
725
@@ -XXX,XX +XXX,XX @@ static const TranslatorOps openrisc_tr_ops = {
726
.tb_stop = openrisc_tr_tb_stop,
727
};
728
729
-void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns,
730
- vaddr pc, void *host_pc)
731
+void openrisc_translate_code(CPUState *cs, TranslationBlock *tb,
732
+ int *max_insns, vaddr pc, void *host_pc)
733
{
734
DisasContext ctx;
735
736
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
737
index XXXXXXX..XXXXXXX 100644
738
--- a/target/ppc/cpu_init.c
739
+++ b/target/ppc/cpu_init.c
740
@@ -XXX,XX +XXX,XX @@ static const struct SysemuCPUOps ppc_sysemu_ops = {
741
742
static const TCGCPUOps ppc_tcg_ops = {
743
.initialize = ppc_translate_init,
744
+ .translate_code = ppc_translate_code,
745
.restore_state_to_opc = ppc_restore_state_to_opc,
746
747
#ifdef CONFIG_USER_ONLY
748
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
749
index XXXXXXX..XXXXXXX 100644
750
--- a/target/ppc/translate.c
751
+++ b/target/ppc/translate.c
752
@@ -XXX,XX +XXX,XX @@ static const TranslatorOps ppc_tr_ops = {
753
.tb_stop = ppc_tr_tb_stop,
754
};
755
756
-void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns,
757
- vaddr pc, void *host_pc)
758
+void ppc_translate_code(CPUState *cs, TranslationBlock *tb,
759
+ int *max_insns, vaddr pc, void *host_pc)
760
{
761
DisasContext ctx;
762
763
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
764
index XXXXXXX..XXXXXXX 100644
765
--- a/target/riscv/tcg/tcg-cpu.c
766
+++ b/target/riscv/tcg/tcg-cpu.c
767
@@ -XXX,XX +XXX,XX @@ static void riscv_restore_state_to_opc(CPUState *cs,
768
769
static const TCGCPUOps riscv_tcg_ops = {
770
.initialize = riscv_translate_init,
771
+ .translate_code = riscv_translate_code,
772
.synchronize_from_tb = riscv_cpu_synchronize_from_tb,
773
.restore_state_to_opc = riscv_restore_state_to_opc,
774
775
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
776
index XXXXXXX..XXXXXXX 100644
777
--- a/target/riscv/translate.c
778
+++ b/target/riscv/translate.c
779
@@ -XXX,XX +XXX,XX @@ static const TranslatorOps riscv_tr_ops = {
780
.tb_stop = riscv_tr_tb_stop,
781
};
782
783
-void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns,
784
- vaddr pc, void *host_pc)
785
+void riscv_translate_code(CPUState *cs, TranslationBlock *tb,
786
+ int *max_insns, vaddr pc, void *host_pc)
787
{
788
DisasContext ctx;
789
790
diff --git a/target/rx/cpu.c b/target/rx/cpu.c
791
index XXXXXXX..XXXXXXX 100644
792
--- a/target/rx/cpu.c
793
+++ b/target/rx/cpu.c
794
@@ -XXX,XX +XXX,XX @@ static const struct SysemuCPUOps rx_sysemu_ops = {
795
796
static const TCGCPUOps rx_tcg_ops = {
797
.initialize = rx_translate_init,
798
+ .translate_code = rx_translate_code,
799
.synchronize_from_tb = rx_cpu_synchronize_from_tb,
800
.restore_state_to_opc = rx_restore_state_to_opc,
801
.tlb_fill = rx_cpu_tlb_fill,
802
diff --git a/target/rx/translate.c b/target/rx/translate.c
803
index XXXXXXX..XXXXXXX 100644
804
--- a/target/rx/translate.c
805
+++ b/target/rx/translate.c
806
@@ -XXX,XX +XXX,XX @@ static const TranslatorOps rx_tr_ops = {
807
.tb_stop = rx_tr_tb_stop,
808
};
809
810
-void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns,
811
- vaddr pc, void *host_pc)
812
+void rx_translate_code(CPUState *cs, TranslationBlock *tb,
813
+ int *max_insns, vaddr pc, void *host_pc)
814
{
815
DisasContext dc;
816
817
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
818
index XXXXXXX..XXXXXXX 100644
819
--- a/target/s390x/cpu.c
820
+++ b/target/s390x/cpu.c
821
@@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPUS390XState *env, vaddr *pc,
822
823
static const TCGCPUOps s390_tcg_ops = {
824
.initialize = s390x_translate_init,
825
+ .translate_code = s390x_translate_code,
826
.restore_state_to_opc = s390x_restore_state_to_opc,
827
828
#ifdef CONFIG_USER_ONLY
829
diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c
830
index XXXXXXX..XXXXXXX 100644
831
--- a/target/s390x/tcg/translate.c
832
+++ b/target/s390x/tcg/translate.c
833
@@ -XXX,XX +XXX,XX @@ static const TranslatorOps s390x_tr_ops = {
834
.disas_log = s390x_tr_disas_log,
835
};
836
837
-void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns,
838
- vaddr pc, void *host_pc)
839
+void s390x_translate_code(CPUState *cs, TranslationBlock *tb,
840
+ int *max_insns, vaddr pc, void *host_pc)
841
{
842
DisasContext dc;
843
844
diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c
845
index XXXXXXX..XXXXXXX 100644
846
--- a/target/sh4/cpu.c
847
+++ b/target/sh4/cpu.c
848
@@ -XXX,XX +XXX,XX @@ static const struct SysemuCPUOps sh4_sysemu_ops = {
849
850
static const TCGCPUOps superh_tcg_ops = {
851
.initialize = sh4_translate_init,
852
+ .translate_code = sh4_translate_code,
853
.synchronize_from_tb = superh_cpu_synchronize_from_tb,
854
.restore_state_to_opc = superh_restore_state_to_opc,
855
856
diff --git a/target/sh4/translate.c b/target/sh4/translate.c
857
index XXXXXXX..XXXXXXX 100644
858
--- a/target/sh4/translate.c
859
+++ b/target/sh4/translate.c
860
@@ -XXX,XX +XXX,XX @@ static const TranslatorOps sh4_tr_ops = {
861
.tb_stop = sh4_tr_tb_stop,
862
};
863
864
-void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns,
865
- vaddr pc, void *host_pc)
866
+void sh4_translate_code(CPUState *cs, TranslationBlock *tb,
867
+ int *max_insns, vaddr pc, void *host_pc)
868
{
869
DisasContext ctx;
870
871
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
872
index XXXXXXX..XXXXXXX 100644
873
--- a/target/sparc/cpu.c
874
+++ b/target/sparc/cpu.c
875
@@ -XXX,XX +XXX,XX @@ static const struct SysemuCPUOps sparc_sysemu_ops = {
876
877
static const TCGCPUOps sparc_tcg_ops = {
878
.initialize = sparc_tcg_init,
879
+ .translate_code = sparc_translate_code,
880
.synchronize_from_tb = sparc_cpu_synchronize_from_tb,
881
.restore_state_to_opc = sparc_restore_state_to_opc,
882
883
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
884
index XXXXXXX..XXXXXXX 100644
885
--- a/target/sparc/translate.c
886
+++ b/target/sparc/translate.c
887
@@ -XXX,XX +XXX,XX @@ static const TranslatorOps sparc_tr_ops = {
888
.tb_stop = sparc_tr_tb_stop,
889
};
890
891
-void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns,
892
- vaddr pc, void *host_pc)
893
+void sparc_translate_code(CPUState *cs, TranslationBlock *tb,
894
+ int *max_insns, vaddr pc, void *host_pc)
895
{
896
DisasContext dc = {};
897
898
diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c
899
index XXXXXXX..XXXXXXX 100644
900
--- a/target/tricore/cpu.c
901
+++ b/target/tricore/cpu.c
902
@@ -XXX,XX +XXX,XX @@ static const struct SysemuCPUOps tricore_sysemu_ops = {
903
904
static const TCGCPUOps tricore_tcg_ops = {
905
.initialize = tricore_tcg_init,
906
+ .translate_code = tricore_translate_code,
907
.synchronize_from_tb = tricore_cpu_synchronize_from_tb,
908
.restore_state_to_opc = tricore_restore_state_to_opc,
909
.tlb_fill = tricore_cpu_tlb_fill,
910
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
911
index XXXXXXX..XXXXXXX 100644
912
--- a/target/tricore/translate.c
913
+++ b/target/tricore/translate.c
914
@@ -XXX,XX +XXX,XX @@ static const TranslatorOps tricore_tr_ops = {
915
.tb_stop = tricore_tr_tb_stop,
916
};
917
918
-
919
-void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns,
920
- vaddr pc, void *host_pc)
921
+void tricore_translate_code(CPUState *cs, TranslationBlock *tb,
922
+ int *max_insns, vaddr pc, void *host_pc)
923
{
924
DisasContext ctx;
925
translator_loop(cs, tb, max_insns, pc, host_pc,
926
diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
927
index XXXXXXX..XXXXXXX 100644
928
--- a/target/xtensa/cpu.c
929
+++ b/target/xtensa/cpu.c
930
@@ -XXX,XX +XXX,XX @@ static const struct SysemuCPUOps xtensa_sysemu_ops = {
931
932
static const TCGCPUOps xtensa_tcg_ops = {
933
.initialize = xtensa_translate_init,
934
+ .translate_code = xtensa_translate_code,
935
.debug_excp_handler = xtensa_breakpoint_handler,
936
.restore_state_to_opc = xtensa_restore_state_to_opc,
937
938
diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c
939
index XXXXXXX..XXXXXXX 100644
940
--- a/target/xtensa/translate.c
941
+++ b/target/xtensa/translate.c
942
@@ -XXX,XX +XXX,XX @@ static const TranslatorOps xtensa_translator_ops = {
943
.tb_stop = xtensa_tr_tb_stop,
944
};
945
946
-void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int *max_insns,
947
- vaddr pc, void *host_pc)
948
+void xtensa_translate_code(CPUState *cpu, TranslationBlock *tb,
949
+ int *max_insns, vaddr pc, void *host_pc)
950
{
951
DisasContext dc = {};
952
translator_loop(cpu, tb, max_insns, pc, host_pc,
208
--
953
--
209
2.25.1
954
2.43.0
210
955
211
956
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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