[PATCH 00/27] tcg patch queue
[PULL 00/56] tcg patch queue
1
Pulling together some cleanups, fixes, and prepatory tci stuff.
1
The following changes since commit c52d69e7dbaaed0ffdef8125e79218672c30161d:
2
Most of this has been reviewed, but not all.
3
2
4
Those lacking review:
3
Merge remote-tracking branch 'remotes/cschoenebeck/tags/pull-9p-20211027' into staging (2021-10-27 11:45:18 -0700)
5
4
6
01-tcg-aarch64-Fix-constant-subtraction-in-tcg_out_adds.patch
5
are available in the Git repository at:
7
02-tcg-aarch64-Fix-I3617_CMLE0.patch
8
03-tcg-aarch64-Fix-generation-of-scalar-vector-operatio.patch
9
04-tcg-tci-Use-exec-cpu_ldst.h-interfaces.patch
10
06-tcg-Manage-splitwx-in-tc_ptr_to_region_tree-by-hand.patch
11
23-accel-tcg-rename-tb_lookup__cpu_state-and-hoist-stat.patch
12
24-accel-tcg-move-CF_CLUSTER-calculation-to-curr_cflags.patch
13
25-accel-tcg-drop-the-use-of-CF_HASH_MASK-and-rename-pa.patch
14
26-include-exec-lightly-re-arrange-TranslationBlock.patch
15
27-accel-tcg-Precompute-curr_cflags-into-cpu-tcg_cflags.patch
16
6
17
Alex, the last patch is a re-write and extension of one that
7
https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20211027
18
you did review.
19
8
9
for you to fetch changes up to 820c025f0dcacf2f3c12735b1f162893fbfa7bc6:
20
10
21
r~
11
tcg/optimize: Propagate sign info for shifting (2021-10-27 17:11:23 -0700)
22
12
13
----------------------------------------------------------------
14
Improvements to qemu/int128
15
Fixes for 128/64 division.
16
Cleanup tcg/optimize.c
17
Optimize redundant sign extensions
23
18
24
Alex Bennée (4):
19
----------------------------------------------------------------
25
accel/tcg: rename tb_lookup__cpu_state and hoist state extraction
20
Frédéric Pétrot (1):
26
accel/tcg: move CF_CLUSTER calculation to curr_cflags
21
qemu/int128: Add int128_{not,xor}
27
accel/tcg: drop the use of CF_HASH_MASK and rename params
28
include/exec: lightly re-arrange TranslationBlock
29
22
30
Richard Henderson (23):
23
Luis Pires (4):
31
tcg/aarch64: Fix constant subtraction in tcg_out_addsub2
24
host-utils: move checks out of divu128/divs128
32
tcg/aarch64: Fix I3617_CMLE0
25
host-utils: move udiv_qrnnd() to host-utils
33
tcg/aarch64: Fix generation of "scalar" vector operations
26
host-utils: add 128-bit quotient support to divu128/divs128
34
tcg/tci: Use exec/cpu_ldst.h interfaces
27
host-utils: add unit tests for divu128/divs128
35
tcg: Split out tcg_raise_tb_overflow
36
tcg: Manage splitwx in tc_ptr_to_region_tree by hand
37
tcg/tci: Merge identical cases in generation (arithmetic opcodes)
38
tcg/tci: Merge identical cases in generation (exchange opcodes)
39
tcg/tci: Merge identical cases in generation (deposit opcode)
40
tcg/tci: Merge identical cases in generation (conditional opcodes)
41
tcg/tci: Merge identical cases in generation (load/store opcodes)
42
tcg/tci: Remove tci_read_r8
43
tcg/tci: Remove tci_read_r8s
44
tcg/tci: Remove tci_read_r16
45
tcg/tci: Remove tci_read_r16s
46
tcg/tci: Remove tci_read_r32
47
tcg/tci: Remove tci_read_r32s
48
tcg/tci: Reduce use of tci_read_r64
49
tcg/tci: Merge basic arithmetic operations
50
tcg/tci: Merge extension operations
51
tcg/tci: Merge bswap operations
52
tcg/tci: Merge mov, not and neg operations
53
accel/tcg: Precompute curr_cflags into cpu->tcg_cflags
54
28
55
accel/tcg/tcg-accel-ops.h | 1 +
29
Richard Henderson (51):
56
include/exec/exec-all.h | 19 +-
30
tcg/optimize: Rename "mask" to "z_mask"
57
include/exec/tb-lookup.h | 26 +-
31
tcg/optimize: Split out OptContext
58
include/hw/core/cpu.h | 2 +
32
tcg/optimize: Remove do_default label
59
accel/tcg/cpu-exec.c | 34 ++-
33
tcg/optimize: Change tcg_opt_gen_{mov,movi} interface
60
accel/tcg/tcg-accel-ops-mttcg.c | 3 +-
34
tcg/optimize: Move prev_mb into OptContext
61
accel/tcg/tcg-accel-ops-rr.c | 2 +-
35
tcg/optimize: Split out init_arguments
62
accel/tcg/tcg-accel-ops.c | 8 +
36
tcg/optimize: Split out copy_propagate
63
accel/tcg/tcg-runtime.c | 6 +-
37
tcg/optimize: Split out fold_call
64
accel/tcg/translate-all.c | 18 +-
38
tcg/optimize: Drop nb_oargs, nb_iargs locals
65
linux-user/main.c | 1 +
39
tcg/optimize: Change fail return for do_constant_folding_cond*
66
linux-user/sh4/signal.c | 8 +-
40
tcg/optimize: Return true from tcg_opt_gen_{mov,movi}
67
linux-user/syscall.c | 18 +-
41
tcg/optimize: Split out finish_folding
68
softmmu/physmem.c | 2 +-
42
tcg/optimize: Use a boolean to avoid a mass of continues
69
tcg/tcg.c | 29 +-
43
tcg/optimize: Split out fold_mb, fold_qemu_{ld,st}
70
tcg/tci.c | 526 ++++++++++----------------------
44
tcg/optimize: Split out fold_const{1,2}
71
tcg/aarch64/tcg-target.c.inc | 229 +++++++++++---
45
tcg/optimize: Split out fold_setcond2
72
tcg/tci/tcg-target.c.inc | 204 +++++--------
46
tcg/optimize: Split out fold_brcond2
73
18 files changed, 526 insertions(+), 610 deletions(-)
47
tcg/optimize: Split out fold_brcond
48
tcg/optimize: Split out fold_setcond
49
tcg/optimize: Split out fold_mulu2_i32
50
tcg/optimize: Split out fold_addsub2_i32
51
tcg/optimize: Split out fold_movcond
52
tcg/optimize: Split out fold_extract2
53
tcg/optimize: Split out fold_extract, fold_sextract
54
tcg/optimize: Split out fold_deposit
55
tcg/optimize: Split out fold_count_zeros
56
tcg/optimize: Split out fold_bswap
57
tcg/optimize: Split out fold_dup, fold_dup2
58
tcg/optimize: Split out fold_mov
59
tcg/optimize: Split out fold_xx_to_i
60
tcg/optimize: Split out fold_xx_to_x
61
tcg/optimize: Split out fold_xi_to_i
62
tcg/optimize: Add type to OptContext
63
tcg/optimize: Split out fold_to_not
64
tcg/optimize: Split out fold_sub_to_neg
65
tcg/optimize: Split out fold_xi_to_x
66
tcg/optimize: Split out fold_ix_to_i
67
tcg/optimize: Split out fold_masks
68
tcg/optimize: Expand fold_mulu2_i32 to all 4-arg multiplies
69
tcg/optimize: Expand fold_addsub2_i32 to 64-bit ops
70
tcg/optimize: Sink commutative operand swapping into fold functions
71
tcg/optimize: Stop forcing z_mask to "garbage" for 32-bit values
72
tcg/optimize: Use fold_xx_to_i for orc
73
tcg/optimize: Use fold_xi_to_x for mul
74
tcg/optimize: Use fold_xi_to_x for div
75
tcg/optimize: Use fold_xx_to_i for rem
76
tcg/optimize: Optimize sign extensions
77
tcg/optimize: Propagate sign info for logical operations
78
tcg/optimize: Propagate sign info for setcond
79
tcg/optimize: Propagate sign info for bit counting
80
tcg/optimize: Propagate sign info for shifting
74
81
75
--
82
include/fpu/softfloat-macros.h | 82 --
76
2.25.1
83
include/hw/clock.h | 5 +-
84
include/qemu/host-utils.h | 121 +-
85
include/qemu/int128.h | 20 +
86
target/ppc/int_helper.c | 23 +-
87
tcg/optimize.c | 2644 ++++++++++++++++++++++++----------------
88
tests/unit/test-div128.c | 197 +++
89
util/host-utils.c | 147 ++-
90
tests/unit/meson.build | 1 +
91
9 files changed, 2053 insertions(+), 1187 deletions(-)
92
create mode 100644 tests/unit/test-div128.c
77
93
78
diff view generated by jsdifflib
[PATCH 03/27] tcg/aarch64: Fix generation of "scalar" vector operations
[PULL 01/56] qemu/int128: Add int128_{not,xor}
1
For some vector operations, "1D" is not a valid type, and there
1
From: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
2
are separate instructions for the 64-bit scalar operation.
3
2
4
Tested-by: Stefan Weil <sw@weilnetz.de>
3
Addition of not and xor on 128-bit integers.
5
Buglink: https://bugs.launchpad.net/qemu/+bug/1916112
4
6
Fixes: 14e4c1e2355 ("tcg/aarch64: Add vector operations")
5
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
6
Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org>
7
Message-Id: <20211025122818.168890-3-frederic.petrot@univ-grenoble-alpes.fr>
8
[rth: Split out logical operations.]
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
---
11
---
9
tcg/aarch64/tcg-target.c.inc | 211 ++++++++++++++++++++++++++++++-----
12
include/qemu/int128.h | 20 ++++++++++++++++++++
10
1 file changed, 181 insertions(+), 30 deletions(-)
13
1 file changed, 20 insertions(+)
11
14
12
diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc
15
diff --git a/include/qemu/int128.h b/include/qemu/int128.h
13
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
14
--- a/tcg/aarch64/tcg-target.c.inc
17
--- a/include/qemu/int128.h
15
+++ b/tcg/aarch64/tcg-target.c.inc
18
+++ b/include/qemu/int128.h
16
@@ -XXX,XX +XXX,XX @@ typedef enum {
19
@@ -XXX,XX +XXX,XX @@ static inline Int128 int128_exts64(int64_t a)
17
I3606_BIC = 0x2f001400,
20
return a;
18
I3606_ORR = 0x0f001400,
19
20
+ /* AdvSIMD scalar shift by immediate */
21
+ I3609_SSHR = 0x5f000400,
22
+ I3609_SSRA = 0x5f001400,
23
+ I3609_SHL = 0x5f005400,
24
+ I3609_USHR = 0x7f000400,
25
+ I3609_USRA = 0x7f001400,
26
+ I3609_SLI = 0x7f005400,
27
+
28
+ /* AdvSIMD scalar three same */
29
+ I3611_SQADD = 0x5e200c00,
30
+ I3611_SQSUB = 0x5e202c00,
31
+ I3611_CMGT = 0x5e203400,
32
+ I3611_CMGE = 0x5e203c00,
33
+ I3611_SSHL = 0x5e204400,
34
+ I3611_ADD = 0x5e208400,
35
+ I3611_CMTST = 0x5e208c00,
36
+ I3611_UQADD = 0x7e200c00,
37
+ I3611_UQSUB = 0x7e202c00,
38
+ I3611_CMHI = 0x7e203400,
39
+ I3611_CMHS = 0x7e203c00,
40
+ I3611_USHL = 0x7e204400,
41
+ I3611_SUB = 0x7e208400,
42
+ I3611_CMEQ = 0x7e208c00,
43
+
44
+ /* AdvSIMD scalar two-reg misc */
45
+ I3612_CMGT0 = 0x5e208800,
46
+ I3612_CMEQ0 = 0x5e209800,
47
+ I3612_CMLT0 = 0x5e20a800,
48
+ I3612_ABS = 0x5e20b800,
49
+ I3612_CMGE0 = 0x7e208800,
50
+ I3612_CMLE0 = 0x7e209800,
51
+ I3612_NEG = 0x7e20b800,
52
+
53
/* AdvSIMD shift by immediate */
54
I3614_SSHR = 0x0f000400,
55
I3614_SSRA = 0x0f001400,
56
@@ -XXX,XX +XXX,XX @@ static void tcg_out_insn_3606(TCGContext *s, AArch64Insn insn, bool q,
57
| (imm8 & 0xe0) << (16 - 5) | (imm8 & 0x1f) << 5);
58
}
21
}
59
22
60
+static void tcg_out_insn_3609(TCGContext *s, AArch64Insn insn,
23
+static inline Int128 int128_not(Int128 a)
61
+ TCGReg rd, TCGReg rn, unsigned immhb)
62
+{
24
+{
63
+ tcg_out32(s, insn | immhb << 16 | (rn & 0x1f) << 5 | (rd & 0x1f));
25
+ return ~a;
64
+}
26
+}
65
+
27
+
66
+static void tcg_out_insn_3611(TCGContext *s, AArch64Insn insn,
28
static inline Int128 int128_and(Int128 a, Int128 b)
67
+ unsigned size, TCGReg rd, TCGReg rn, TCGReg rm)
29
{
30
return a & b;
31
@@ -XXX,XX +XXX,XX @@ static inline Int128 int128_or(Int128 a, Int128 b)
32
return a | b;
33
}
34
35
+static inline Int128 int128_xor(Int128 a, Int128 b)
68
+{
36
+{
69
+ tcg_out32(s, insn | (size << 22) | (rm & 0x1f) << 16
37
+ return a ^ b;
70
+ | (rn & 0x1f) << 5 | (rd & 0x1f));
71
+}
38
+}
72
+
39
+
73
+static void tcg_out_insn_3612(TCGContext *s, AArch64Insn insn,
40
static inline Int128 int128_rshift(Int128 a, int n)
74
+ unsigned size, TCGReg rd, TCGReg rn)
41
{
42
return a >> n;
43
@@ -XXX,XX +XXX,XX @@ static inline Int128 int128_exts64(int64_t a)
44
return int128_make128(a, (a < 0) ? -1 : 0);
45
}
46
47
+static inline Int128 int128_not(Int128 a)
75
+{
48
+{
76
+ tcg_out32(s, insn | (size << 22) | (rn & 0x1f) << 5 | (rd & 0x1f));
49
+ return int128_make128(~a.lo, ~a.hi);
77
+}
50
+}
78
+
51
+
79
static void tcg_out_insn_3614(TCGContext *s, AArch64Insn insn, bool q,
52
static inline Int128 int128_and(Int128 a, Int128 b)
80
TCGReg rd, TCGReg rn, unsigned immhb)
81
{
53
{
82
@@ -XXX,XX +XXX,XX @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
54
return int128_make128(a.lo & b.lo, a.hi & b.hi);
83
unsigned vecl, unsigned vece,
55
@@ -XXX,XX +XXX,XX @@ static inline Int128 int128_or(Int128 a, Int128 b)
84
const TCGArg *args, const int *const_args)
56
return int128_make128(a.lo | b.lo, a.hi | b.hi);
57
}
58
59
+static inline Int128 int128_xor(Int128 a, Int128 b)
60
+{
61
+ return int128_make128(a.lo ^ b.lo, a.hi ^ b.hi);
62
+}
63
+
64
static inline Int128 int128_rshift(Int128 a, int n)
85
{
65
{
86
- static const AArch64Insn cmp_insn[16] = {
66
int64_t h;
87
+ static const AArch64Insn cmp_vec_insn[16] = {
88
[TCG_COND_EQ] = I3616_CMEQ,
89
[TCG_COND_GT] = I3616_CMGT,
90
[TCG_COND_GE] = I3616_CMGE,
91
[TCG_COND_GTU] = I3616_CMHI,
92
[TCG_COND_GEU] = I3616_CMHS,
93
};
94
- static const AArch64Insn cmp0_insn[16] = {
95
+ static const AArch64Insn cmp_scalar_insn[16] = {
96
+ [TCG_COND_EQ] = I3611_CMEQ,
97
+ [TCG_COND_GT] = I3611_CMGT,
98
+ [TCG_COND_GE] = I3611_CMGE,
99
+ [TCG_COND_GTU] = I3611_CMHI,
100
+ [TCG_COND_GEU] = I3611_CMHS,
101
+ };
102
+ static const AArch64Insn cmp0_vec_insn[16] = {
103
[TCG_COND_EQ] = I3617_CMEQ0,
104
[TCG_COND_GT] = I3617_CMGT0,
105
[TCG_COND_GE] = I3617_CMGE0,
106
[TCG_COND_LT] = I3617_CMLT0,
107
[TCG_COND_LE] = I3617_CMLE0,
108
};
109
+ static const AArch64Insn cmp0_scalar_insn[16] = {
110
+ [TCG_COND_EQ] = I3612_CMEQ0,
111
+ [TCG_COND_GT] = I3612_CMGT0,
112
+ [TCG_COND_GE] = I3612_CMGE0,
113
+ [TCG_COND_LT] = I3612_CMLT0,
114
+ [TCG_COND_LE] = I3612_CMLE0,
115
+ };
116
117
TCGType type = vecl + TCG_TYPE_V64;
118
unsigned is_q = vecl;
119
+ bool is_scalar = !is_q && vece == MO_64;
120
TCGArg a0, a1, a2, a3;
121
int cmode, imm8;
122
123
@@ -XXX,XX +XXX,XX @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
124
tcg_out_dupm_vec(s, type, vece, a0, a1, a2);
125
break;
126
case INDEX_op_add_vec:
127
- tcg_out_insn(s, 3616, ADD, is_q, vece, a0, a1, a2);
128
+ if (is_scalar) {
129
+ tcg_out_insn(s, 3611, ADD, vece, a0, a1, a2);
130
+ } else {
131
+ tcg_out_insn(s, 3616, ADD, is_q, vece, a0, a1, a2);
132
+ }
133
break;
134
case INDEX_op_sub_vec:
135
- tcg_out_insn(s, 3616, SUB, is_q, vece, a0, a1, a2);
136
+ if (is_scalar) {
137
+ tcg_out_insn(s, 3611, SUB, vece, a0, a1, a2);
138
+ } else {
139
+ tcg_out_insn(s, 3616, SUB, is_q, vece, a0, a1, a2);
140
+ }
141
break;
142
case INDEX_op_mul_vec:
143
tcg_out_insn(s, 3616, MUL, is_q, vece, a0, a1, a2);
144
break;
145
case INDEX_op_neg_vec:
146
- tcg_out_insn(s, 3617, NEG, is_q, vece, a0, a1);
147
+ if (is_scalar) {
148
+ tcg_out_insn(s, 3612, NEG, vece, a0, a1);
149
+ } else {
150
+ tcg_out_insn(s, 3617, NEG, is_q, vece, a0, a1);
151
+ }
152
break;
153
case INDEX_op_abs_vec:
154
- tcg_out_insn(s, 3617, ABS, is_q, vece, a0, a1);
155
+ if (is_scalar) {
156
+ tcg_out_insn(s, 3612, ABS, vece, a0, a1);
157
+ } else {
158
+ tcg_out_insn(s, 3617, ABS, is_q, vece, a0, a1);
159
+ }
160
break;
161
case INDEX_op_and_vec:
162
if (const_args[2]) {
163
@@ -XXX,XX +XXX,XX @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
164
tcg_out_insn(s, 3616, EOR, is_q, 0, a0, a1, a2);
165
break;
166
case INDEX_op_ssadd_vec:
167
- tcg_out_insn(s, 3616, SQADD, is_q, vece, a0, a1, a2);
168
+ if (is_scalar) {
169
+ tcg_out_insn(s, 3611, SQADD, vece, a0, a1, a2);
170
+ } else {
171
+ tcg_out_insn(s, 3616, SQADD, is_q, vece, a0, a1, a2);
172
+ }
173
break;
174
case INDEX_op_sssub_vec:
175
- tcg_out_insn(s, 3616, SQSUB, is_q, vece, a0, a1, a2);
176
+ if (is_scalar) {
177
+ tcg_out_insn(s, 3611, SQSUB, vece, a0, a1, a2);
178
+ } else {
179
+ tcg_out_insn(s, 3616, SQSUB, is_q, vece, a0, a1, a2);
180
+ }
181
break;
182
case INDEX_op_usadd_vec:
183
- tcg_out_insn(s, 3616, UQADD, is_q, vece, a0, a1, a2);
184
+ if (is_scalar) {
185
+ tcg_out_insn(s, 3611, UQADD, vece, a0, a1, a2);
186
+ } else {
187
+ tcg_out_insn(s, 3616, UQADD, is_q, vece, a0, a1, a2);
188
+ }
189
break;
190
case INDEX_op_ussub_vec:
191
- tcg_out_insn(s, 3616, UQSUB, is_q, vece, a0, a1, a2);
192
+ if (is_scalar) {
193
+ tcg_out_insn(s, 3611, UQSUB, vece, a0, a1, a2);
194
+ } else {
195
+ tcg_out_insn(s, 3616, UQSUB, is_q, vece, a0, a1, a2);
196
+ }
197
break;
198
case INDEX_op_smax_vec:
199
tcg_out_insn(s, 3616, SMAX, is_q, vece, a0, a1, a2);
200
@@ -XXX,XX +XXX,XX @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
201
tcg_out_insn(s, 3617, NOT, is_q, 0, a0, a1);
202
break;
203
case INDEX_op_shli_vec:
204
- tcg_out_insn(s, 3614, SHL, is_q, a0, a1, a2 + (8 << vece));
205
+ if (is_scalar) {
206
+ tcg_out_insn(s, 3609, SHL, a0, a1, a2 + (8 << vece));
207
+ } else {
208
+ tcg_out_insn(s, 3614, SHL, is_q, a0, a1, a2 + (8 << vece));
209
+ }
210
break;
211
case INDEX_op_shri_vec:
212
- tcg_out_insn(s, 3614, USHR, is_q, a0, a1, (16 << vece) - a2);
213
+ if (is_scalar) {
214
+ tcg_out_insn(s, 3609, USHR, a0, a1, (16 << vece) - a2);
215
+ } else {
216
+ tcg_out_insn(s, 3614, USHR, is_q, a0, a1, (16 << vece) - a2);
217
+ }
218
break;
219
case INDEX_op_sari_vec:
220
- tcg_out_insn(s, 3614, SSHR, is_q, a0, a1, (16 << vece) - a2);
221
+ if (is_scalar) {
222
+ tcg_out_insn(s, 3609, SSHR, a0, a1, (16 << vece) - a2);
223
+ } else {
224
+ tcg_out_insn(s, 3614, SSHR, is_q, a0, a1, (16 << vece) - a2);
225
+ }
226
break;
227
case INDEX_op_aa64_sli_vec:
228
- tcg_out_insn(s, 3614, SLI, is_q, a0, a2, args[3] + (8 << vece));
229
+ if (is_scalar) {
230
+ tcg_out_insn(s, 3609, SLI, a0, a2, args[3] + (8 << vece));
231
+ } else {
232
+ tcg_out_insn(s, 3614, SLI, is_q, a0, a2, args[3] + (8 << vece));
233
+ }
234
break;
235
case INDEX_op_shlv_vec:
236
- tcg_out_insn(s, 3616, USHL, is_q, vece, a0, a1, a2);
237
+ if (is_scalar) {
238
+ tcg_out_insn(s, 3611, USHL, vece, a0, a1, a2);
239
+ } else {
240
+ tcg_out_insn(s, 3616, USHL, is_q, vece, a0, a1, a2);
241
+ }
242
break;
243
case INDEX_op_aa64_sshl_vec:
244
- tcg_out_insn(s, 3616, SSHL, is_q, vece, a0, a1, a2);
245
+ if (is_scalar) {
246
+ tcg_out_insn(s, 3611, SSHL, vece, a0, a1, a2);
247
+ } else {
248
+ tcg_out_insn(s, 3616, SSHL, is_q, vece, a0, a1, a2);
249
+ }
250
break;
251
case INDEX_op_cmp_vec:
252
{
253
@@ -XXX,XX +XXX,XX @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
254
255
if (cond == TCG_COND_NE) {
256
if (const_args[2]) {
257
- tcg_out_insn(s, 3616, CMTST, is_q, vece, a0, a1, a1);
258
+ if (is_scalar) {
259
+ tcg_out_insn(s, 3611, CMTST, vece, a0, a1, a1);
260
+ } else {
261
+ tcg_out_insn(s, 3616, CMTST, is_q, vece, a0, a1, a1);
262
+ }
263
} else {
264
- tcg_out_insn(s, 3616, CMEQ, is_q, vece, a0, a1, a2);
265
+ if (is_scalar) {
266
+ tcg_out_insn(s, 3611, CMEQ, vece, a0, a1, a2);
267
+ } else {
268
+ tcg_out_insn(s, 3616, CMEQ, is_q, vece, a0, a1, a2);
269
+ }
270
tcg_out_insn(s, 3617, NOT, is_q, 0, a0, a0);
271
}
272
} else {
273
if (const_args[2]) {
274
- insn = cmp0_insn[cond];
275
- if (insn) {
276
- tcg_out_insn_3617(s, insn, is_q, vece, a0, a1);
277
- break;
278
+ if (is_scalar) {
279
+ insn = cmp0_scalar_insn[cond];
280
+ if (insn) {
281
+ tcg_out_insn_3612(s, insn, vece, a0, a1);
282
+ break;
283
+ }
284
+ } else {
285
+ insn = cmp0_vec_insn[cond];
286
+ if (insn) {
287
+ tcg_out_insn_3617(s, insn, is_q, vece, a0, a1);
288
+ break;
289
+ }
290
}
291
tcg_out_dupi_vec(s, type, MO_8, TCG_VEC_TMP, 0);
292
a2 = TCG_VEC_TMP;
293
}
294
- insn = cmp_insn[cond];
295
- if (insn == 0) {
296
- TCGArg t;
297
- t = a1, a1 = a2, a2 = t;
298
- cond = tcg_swap_cond(cond);
299
- insn = cmp_insn[cond];
300
- tcg_debug_assert(insn != 0);
301
+ if (is_scalar) {
302
+ insn = cmp_scalar_insn[cond];
303
+ if (insn == 0) {
304
+ TCGArg t;
305
+ t = a1, a1 = a2, a2 = t;
306
+ cond = tcg_swap_cond(cond);
307
+ insn = cmp_scalar_insn[cond];
308
+ tcg_debug_assert(insn != 0);
309
+ }
310
+ tcg_out_insn_3611(s, insn, vece, a0, a1, a2);
311
+ } else {
312
+ insn = cmp_vec_insn[cond];
313
+ if (insn == 0) {
314
+ TCGArg t;
315
+ t = a1, a1 = a2, a2 = t;
316
+ cond = tcg_swap_cond(cond);
317
+ insn = cmp_vec_insn[cond];
318
+ tcg_debug_assert(insn != 0);
319
+ }
320
+ tcg_out_insn_3616(s, insn, is_q, vece, a0, a1, a2);
321
}
322
- tcg_out_insn_3616(s, insn, is_q, vece, a0, a1, a2);
323
}
324
}
325
break;
326
--
67
--
327
2.25.1
68
2.25.1
328
69
329
70
diff view generated by jsdifflib
New patch
[PULL 02/56] host-utils: move checks out of divu128/divs128
1
1
From: Luis Pires <luis.pires@eldorado.org.br>
2
3
In preparation for changing the divu128/divs128 implementations
4
to allow for quotients larger than 64 bits, move the div-by-zero
5
and overflow checks to the callers.
6
7
Signed-off-by: Luis Pires <luis.pires@eldorado.org.br>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-Id: <20211025191154.350831-2-luis.pires@eldorado.org.br>
10
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
11
---
12
include/hw/clock.h | 5 +++--
13
include/qemu/host-utils.h | 34 ++++++++++++---------------------
14
target/ppc/int_helper.c | 14 +++++++++-----
15
util/host-utils.c | 40 ++++++++++++++++++---------------------
16
4 files changed, 42 insertions(+), 51 deletions(-)
17
18
diff --git a/include/hw/clock.h b/include/hw/clock.h
19
index XXXXXXX..XXXXXXX 100644
20
--- a/include/hw/clock.h
21
+++ b/include/hw/clock.h
22
@@ -XXX,XX +XXX,XX @@ static inline uint64_t clock_ns_to_ticks(const Clock *clk, uint64_t ns)
23
return 0;
24
}
25
/*
26
- * Ignore divu128() return value as we've caught div-by-zero and don't
27
- * need different behaviour for overflow.
28
+ * BUG: when CONFIG_INT128 is not defined, the current implementation of
29
+ * divu128 does not return a valid truncated quotient, so the result will
30
+ * be wrong.
31
*/
32
divu128(&lo, &hi, clk->period);
33
return lo;
34
diff --git a/include/qemu/host-utils.h b/include/qemu/host-utils.h
35
index XXXXXXX..XXXXXXX 100644
36
--- a/include/qemu/host-utils.h
37
+++ b/include/qemu/host-utils.h
38
@@ -XXX,XX +XXX,XX @@ static inline uint64_t muldiv64(uint64_t a, uint32_t b, uint32_t c)
39
return (__int128_t)a * b / c;
40
}
41
42
-static inline int divu128(uint64_t *plow, uint64_t *phigh, uint64_t divisor)
43
+static inline void divu128(uint64_t *plow, uint64_t *phigh, uint64_t divisor)
44
{
45
- if (divisor == 0) {
46
- return 1;
47
- } else {
48
- __uint128_t dividend = ((__uint128_t)*phigh << 64) | *plow;
49
- __uint128_t result = dividend / divisor;
50
- *plow = result;
51
- *phigh = dividend % divisor;
52
- return result > UINT64_MAX;
53
- }
54
+ __uint128_t dividend = ((__uint128_t)*phigh << 64) | *plow;
55
+ __uint128_t result = dividend / divisor;
56
+ *plow = result;
57
+ *phigh = dividend % divisor;
58
}
59
60
-static inline int divs128(int64_t *plow, int64_t *phigh, int64_t divisor)
61
+static inline void divs128(int64_t *plow, int64_t *phigh, int64_t divisor)
62
{
63
- if (divisor == 0) {
64
- return 1;
65
- } else {
66
- __int128_t dividend = ((__int128_t)*phigh << 64) | (uint64_t)*plow;
67
- __int128_t result = dividend / divisor;
68
- *plow = result;
69
- *phigh = dividend % divisor;
70
- return result != *plow;
71
- }
72
+ __int128_t dividend = ((__int128_t)*phigh << 64) | (uint64_t)*plow;
73
+ __int128_t result = dividend / divisor;
74
+ *plow = result;
75
+ *phigh = dividend % divisor;
76
}
77
#else
78
void muls64(uint64_t *plow, uint64_t *phigh, int64_t a, int64_t b);
79
void mulu64(uint64_t *plow, uint64_t *phigh, uint64_t a, uint64_t b);
80
-int divu128(uint64_t *plow, uint64_t *phigh, uint64_t divisor);
81
-int divs128(int64_t *plow, int64_t *phigh, int64_t divisor);
82
+void divu128(uint64_t *plow, uint64_t *phigh, uint64_t divisor);
83
+void divs128(int64_t *plow, int64_t *phigh, int64_t divisor);
84
85
static inline uint64_t muldiv64(uint64_t a, uint32_t b, uint32_t c)
86
{
87
diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c
88
index XXXXXXX..XXXXXXX 100644
89
--- a/target/ppc/int_helper.c
90
+++ b/target/ppc/int_helper.c
91
@@ -XXX,XX +XXX,XX @@ uint64_t helper_divdeu(CPUPPCState *env, uint64_t ra, uint64_t rb, uint32_t oe)
92
uint64_t rt = 0;
93
int overflow = 0;
94
95
- overflow = divu128(&rt, &ra, rb);
96
-
97
- if (unlikely(overflow)) {
98
+ if (unlikely(rb == 0 || ra >= rb)) {
99
+ overflow = 1;
100
rt = 0; /* Undefined */
101
+ } else {
102
+ divu128(&rt, &ra, rb);
103
}
104
105
if (oe) {
106
@@ -XXX,XX +XXX,XX @@ uint64_t helper_divde(CPUPPCState *env, uint64_t rau, uint64_t rbu, uint32_t oe)
107
int64_t rt = 0;
108
int64_t ra = (int64_t)rau;
109
int64_t rb = (int64_t)rbu;
110
- int overflow = divs128(&rt, &ra, rb);
111
+ int overflow = 0;
112
113
- if (unlikely(overflow)) {
114
+ if (unlikely(rb == 0 || uabs64(ra) >= uabs64(rb))) {
115
+ overflow = 1;
116
rt = 0; /* Undefined */
117
+ } else {
118
+ divs128(&rt, &ra, rb);
119
}
120
121
if (oe) {
122
diff --git a/util/host-utils.c b/util/host-utils.c
123
index XXXXXXX..XXXXXXX 100644
124
--- a/util/host-utils.c
125
+++ b/util/host-utils.c
126
@@ -XXX,XX +XXX,XX @@ void muls64 (uint64_t *plow, uint64_t *phigh, int64_t a, int64_t b)
127
*phigh = rh;
128
}
129
130
-/* Unsigned 128x64 division. Returns 1 if overflow (divide by zero or */
131
-/* quotient exceeds 64 bits). Otherwise returns quotient via plow and */
132
-/* remainder via phigh. */
133
-int divu128(uint64_t *plow, uint64_t *phigh, uint64_t divisor)
134
+/*
135
+ * Unsigned 128-by-64 division. Returns quotient via plow and
136
+ * remainder via phigh.
137
+ * The result must fit in 64 bits (plow) - otherwise, the result
138
+ * is undefined.
139
+ * This function will cause a division by zero if passed a zero divisor.
140
+ */
141
+void divu128(uint64_t *plow, uint64_t *phigh, uint64_t divisor)
142
{
143
uint64_t dhi = *phigh;
144
uint64_t dlo = *plow;
145
unsigned i;
146
uint64_t carry = 0;
147
148
- if (divisor == 0) {
149
- return 1;
150
- } else if (dhi == 0) {
151
+ if (divisor == 0 || dhi == 0) {
152
*plow = dlo / divisor;
153
*phigh = dlo % divisor;
154
- return 0;
155
- } else if (dhi >= divisor) {
156
- return 1;
157
} else {
158
159
for (i = 0; i < 64; i++) {
160
@@ -XXX,XX +XXX,XX @@ int divu128(uint64_t *plow, uint64_t *phigh, uint64_t divisor)
161
162
*plow = dlo;
163
*phigh = dhi;
164
- return 0;
165
}
166
}
167
168
-int divs128(int64_t *plow, int64_t *phigh, int64_t divisor)
169
+/*
170
+ * Signed 128-by-64 division. Returns quotient via plow and
171
+ * remainder via phigh.
172
+ * The result must fit in 64 bits (plow) - otherwise, the result
173
+ * is undefined.
174
+ * This function will cause a division by zero if passed a zero divisor.
175
+ */
176
+void divs128(int64_t *plow, int64_t *phigh, int64_t divisor)
177
{
178
int sgn_dvdnd = *phigh < 0;
179
int sgn_divsr = divisor < 0;
180
- int overflow = 0;
181
182
if (sgn_dvdnd) {
183
*plow = ~(*plow);
184
@@ -XXX,XX +XXX,XX @@ int divs128(int64_t *plow, int64_t *phigh, int64_t divisor)
185
divisor = 0 - divisor;
186
}
187
188
- overflow = divu128((uint64_t *)plow, (uint64_t *)phigh, (uint64_t)divisor);
189
+ divu128((uint64_t *)plow, (uint64_t *)phigh, (uint64_t)divisor);
190
191
if (sgn_dvdnd ^ sgn_divsr) {
192
*plow = 0 - *plow;
193
}
194
-
195
- if (!overflow) {
196
- if ((*plow < 0) ^ (sgn_dvdnd ^ sgn_divsr)) {
197
- overflow = 1;
198
- }
199
- }
200
-
201
- return overflow;
202
}
203
#endif
204
205
--
206
2.25.1
207
208
diff view generated by jsdifflib
New patch
[PULL 03/56] host-utils: move udiv_qrnnd() to host-utils
1
1
From: Luis Pires <luis.pires@eldorado.org.br>
2
3
Move udiv_qrnnd() from include/fpu/softfloat-macros.h to host-utils,
4
so it can be reused by divu128().
5
6
Signed-off-by: Luis Pires <luis.pires@eldorado.org.br>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-Id: <20211025191154.350831-3-luis.pires@eldorado.org.br>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
---
11
include/fpu/softfloat-macros.h | 82 ----------------------------------
12
include/qemu/host-utils.h | 81 +++++++++++++++++++++++++++++++++
13
2 files changed, 81 insertions(+), 82 deletions(-)
14
15
diff --git a/include/fpu/softfloat-macros.h b/include/fpu/softfloat-macros.h
16
index XXXXXXX..XXXXXXX 100644
17
--- a/include/fpu/softfloat-macros.h
18
+++ b/include/fpu/softfloat-macros.h
19
@@ -XXX,XX +XXX,XX @@
20
* so some portions are provided under:
21
* the SoftFloat-2a license
22
* the BSD license
23
- * GPL-v2-or-later
24
*
25
* Any future contributions to this file after December 1st 2014 will be
26
* taken to be licensed under the Softfloat-2a license unless specifically
27
@@ -XXX,XX +XXX,XX @@ this code that are retained.
28
* THE POSSIBILITY OF SUCH DAMAGE.
29
*/
30
31
-/* Portions of this work are licensed under the terms of the GNU GPL,
32
- * version 2 or later. See the COPYING file in the top-level directory.
33
- */
34
-
35
#ifndef FPU_SOFTFLOAT_MACROS_H
36
#define FPU_SOFTFLOAT_MACROS_H
37
38
@@ -XXX,XX +XXX,XX @@ static inline uint64_t estimateDiv128To64(uint64_t a0, uint64_t a1, uint64_t b)
39
40
}
41
42
-/* From the GNU Multi Precision Library - longlong.h __udiv_qrnnd
43
- * (https://gmplib.org/repo/gmp/file/tip/longlong.h)
44
- *
45
- * Licensed under the GPLv2/LGPLv3
46
- */
47
-static inline uint64_t udiv_qrnnd(uint64_t *r, uint64_t n1,
48
- uint64_t n0, uint64_t d)
49
-{
50
-#if defined(__x86_64__)
51
- uint64_t q;
52
- asm("divq %4" : "=a"(q), "=d"(*r) : "0"(n0), "1"(n1), "rm"(d));
53
- return q;
54
-#elif defined(__s390x__) && !defined(__clang__)
55
- /* Need to use a TImode type to get an even register pair for DLGR. */
56
- unsigned __int128 n = (unsigned __int128)n1 << 64 | n0;
57
- asm("dlgr %0, %1" : "+r"(n) : "r"(d));
58
- *r = n >> 64;
59
- return n;
60
-#elif defined(_ARCH_PPC64) && defined(_ARCH_PWR7)
61
- /* From Power ISA 2.06, programming note for divdeu. */
62
- uint64_t q1, q2, Q, r1, r2, R;
63
- asm("divdeu %0,%2,%4; divdu %1,%3,%4"
64
- : "=&r"(q1), "=r"(q2)
65
- : "r"(n1), "r"(n0), "r"(d));
66
- r1 = -(q1 * d); /* low part of (n1<<64) - (q1 * d) */
67
- r2 = n0 - (q2 * d);
68
- Q = q1 + q2;
69
- R = r1 + r2;
70
- if (R >= d || R < r2) { /* overflow implies R > d */
71
- Q += 1;
72
- R -= d;
73
- }
74
- *r = R;
75
- return Q;
76
-#else
77
- uint64_t d0, d1, q0, q1, r1, r0, m;
78
-
79
- d0 = (uint32_t)d;
80
- d1 = d >> 32;
81
-
82
- r1 = n1 % d1;
83
- q1 = n1 / d1;
84
- m = q1 * d0;
85
- r1 = (r1 << 32) | (n0 >> 32);
86
- if (r1 < m) {
87
- q1 -= 1;
88
- r1 += d;
89
- if (r1 >= d) {
90
- if (r1 < m) {
91
- q1 -= 1;
92
- r1 += d;
93
- }
94
- }
95
- }
96
- r1 -= m;
97
-
98
- r0 = r1 % d1;
99
- q0 = r1 / d1;
100
- m = q0 * d0;
101
- r0 = (r0 << 32) | (uint32_t)n0;
102
- if (r0 < m) {
103
- q0 -= 1;
104
- r0 += d;
105
- if (r0 >= d) {
106
- if (r0 < m) {
107
- q0 -= 1;
108
- r0 += d;
109
- }
110
- }
111
- }
112
- r0 -= m;
113
-
114
- *r = r0;
115
- return (q1 << 32) | q0;
116
-#endif
117
-}
118
-
119
/*----------------------------------------------------------------------------
120
| Returns an approximation to the square root of the 32-bit significand given
121
| by `a'. Considered as an integer, `a' must be at least 2^31. If bit 0 of
122
diff --git a/include/qemu/host-utils.h b/include/qemu/host-utils.h
123
index XXXXXXX..XXXXXXX 100644
124
--- a/include/qemu/host-utils.h
125
+++ b/include/qemu/host-utils.h
126
@@ -XXX,XX +XXX,XX @@
127
* THE SOFTWARE.
128
*/
129
130
+/* Portions of this work are licensed under the terms of the GNU GPL,
131
+ * version 2 or later. See the COPYING file in the top-level directory.
132
+ */
133
+
134
#ifndef HOST_UTILS_H
135
#define HOST_UTILS_H
136
137
@@ -XXX,XX +XXX,XX @@ void urshift(uint64_t *plow, uint64_t *phigh, int32_t shift);
138
*/
139
void ulshift(uint64_t *plow, uint64_t *phigh, int32_t shift, bool *overflow);
140
141
+/* From the GNU Multi Precision Library - longlong.h __udiv_qrnnd
142
+ * (https://gmplib.org/repo/gmp/file/tip/longlong.h)
143
+ *
144
+ * Licensed under the GPLv2/LGPLv3
145
+ */
146
+static inline uint64_t udiv_qrnnd(uint64_t *r, uint64_t n1,
147
+ uint64_t n0, uint64_t d)
148
+{
149
+#if defined(__x86_64__)
150
+ uint64_t q;
151
+ asm("divq %4" : "=a"(q), "=d"(*r) : "0"(n0), "1"(n1), "rm"(d));
152
+ return q;
153
+#elif defined(__s390x__) && !defined(__clang__)
154
+ /* Need to use a TImode type to get an even register pair for DLGR. */
155
+ unsigned __int128 n = (unsigned __int128)n1 << 64 | n0;
156
+ asm("dlgr %0, %1" : "+r"(n) : "r"(d));
157
+ *r = n >> 64;
158
+ return n;
159
+#elif defined(_ARCH_PPC64) && defined(_ARCH_PWR7)
160
+ /* From Power ISA 2.06, programming note for divdeu. */
161
+ uint64_t q1, q2, Q, r1, r2, R;
162
+ asm("divdeu %0,%2,%4; divdu %1,%3,%4"
163
+ : "=&r"(q1), "=r"(q2)
164
+ : "r"(n1), "r"(n0), "r"(d));
165
+ r1 = -(q1 * d); /* low part of (n1<<64) - (q1 * d) */
166
+ r2 = n0 - (q2 * d);
167
+ Q = q1 + q2;
168
+ R = r1 + r2;
169
+ if (R >= d || R < r2) { /* overflow implies R > d */
170
+ Q += 1;
171
+ R -= d;
172
+ }
173
+ *r = R;
174
+ return Q;
175
+#else
176
+ uint64_t d0, d1, q0, q1, r1, r0, m;
177
+
178
+ d0 = (uint32_t)d;
179
+ d1 = d >> 32;
180
+
181
+ r1 = n1 % d1;
182
+ q1 = n1 / d1;
183
+ m = q1 * d0;
184
+ r1 = (r1 << 32) | (n0 >> 32);
185
+ if (r1 < m) {
186
+ q1 -= 1;
187
+ r1 += d;
188
+ if (r1 >= d) {
189
+ if (r1 < m) {
190
+ q1 -= 1;
191
+ r1 += d;
192
+ }
193
+ }
194
+ }
195
+ r1 -= m;
196
+
197
+ r0 = r1 % d1;
198
+ q0 = r1 / d1;
199
+ m = q0 * d0;
200
+ r0 = (r0 << 32) | (uint32_t)n0;
201
+ if (r0 < m) {
202
+ q0 -= 1;
203
+ r0 += d;
204
+ if (r0 >= d) {
205
+ if (r0 < m) {
206
+ q0 -= 1;
207
+ r0 += d;
208
+ }
209
+ }
210
+ }
211
+ r0 -= m;
212
+
213
+ *r = r0;
214
+ return (q1 << 32) | q0;
215
+#endif
216
+}
217
+
218
#endif
219
--
220
2.25.1
221
222
diff view generated by jsdifflib
New patch
[PULL 04/56] host-utils: add 128-bit quotient support to divu128/divs128
1
1
From: Luis Pires <luis.pires@eldorado.org.br>
2
3
These will be used to implement new decimal floating point
4
instructions from Power ISA 3.1.
5
6
The remainder is now returned directly by divu128/divs128,
7
freeing up phigh to receive the high 64 bits of the quotient.
8
9
Signed-off-by: Luis Pires <luis.pires@eldorado.org.br>
10
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
11
Message-Id: <20211025191154.350831-4-luis.pires@eldorado.org.br>
12
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
13
---
14
include/hw/clock.h | 6 +-
15
include/qemu/host-utils.h | 20 ++++--
16
target/ppc/int_helper.c | 9 +--
17
util/host-utils.c | 133 +++++++++++++++++++++++++-------------
18
4 files changed, 108 insertions(+), 60 deletions(-)
19
20
diff --git a/include/hw/clock.h b/include/hw/clock.h
21
index XXXXXXX..XXXXXXX 100644
22
--- a/include/hw/clock.h
23
+++ b/include/hw/clock.h
24
@@ -XXX,XX +XXX,XX @@ static inline uint64_t clock_ns_to_ticks(const Clock *clk, uint64_t ns)
25
if (clk->period == 0) {
26
return 0;
27
}
28
- /*
29
- * BUG: when CONFIG_INT128 is not defined, the current implementation of
30
- * divu128 does not return a valid truncated quotient, so the result will
31
- * be wrong.
32
- */
33
+
34
divu128(&lo, &hi, clk->period);
35
return lo;
36
}
37
diff --git a/include/qemu/host-utils.h b/include/qemu/host-utils.h
38
index XXXXXXX..XXXXXXX 100644
39
--- a/include/qemu/host-utils.h
40
+++ b/include/qemu/host-utils.h
41
@@ -XXX,XX +XXX,XX @@ static inline uint64_t muldiv64(uint64_t a, uint32_t b, uint32_t c)
42
return (__int128_t)a * b / c;
43
}
44
45
-static inline void divu128(uint64_t *plow, uint64_t *phigh, uint64_t divisor)
46
+static inline uint64_t divu128(uint64_t *plow, uint64_t *phigh,
47
+ uint64_t divisor)
48
{
49
__uint128_t dividend = ((__uint128_t)*phigh << 64) | *plow;
50
__uint128_t result = dividend / divisor;
51
+
52
*plow = result;
53
- *phigh = dividend % divisor;
54
+ *phigh = result >> 64;
55
+ return dividend % divisor;
56
}
57
58
-static inline void divs128(int64_t *plow, int64_t *phigh, int64_t divisor)
59
+static inline int64_t divs128(uint64_t *plow, int64_t *phigh,
60
+ int64_t divisor)
61
{
62
- __int128_t dividend = ((__int128_t)*phigh << 64) | (uint64_t)*plow;
63
+ __int128_t dividend = ((__int128_t)*phigh << 64) | *plow;
64
__int128_t result = dividend / divisor;
65
+
66
*plow = result;
67
- *phigh = dividend % divisor;
68
+ *phigh = result >> 64;
69
+ return dividend % divisor;
70
}
71
#else
72
void muls64(uint64_t *plow, uint64_t *phigh, int64_t a, int64_t b);
73
void mulu64(uint64_t *plow, uint64_t *phigh, uint64_t a, uint64_t b);
74
-void divu128(uint64_t *plow, uint64_t *phigh, uint64_t divisor);
75
-void divs128(int64_t *plow, int64_t *phigh, int64_t divisor);
76
+uint64_t divu128(uint64_t *plow, uint64_t *phigh, uint64_t divisor);
77
+int64_t divs128(uint64_t *plow, int64_t *phigh, int64_t divisor);
78
79
static inline uint64_t muldiv64(uint64_t a, uint32_t b, uint32_t c)
80
{
81
diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c
82
index XXXXXXX..XXXXXXX 100644
83
--- a/target/ppc/int_helper.c
84
+++ b/target/ppc/int_helper.c
85
@@ -XXX,XX +XXX,XX @@ uint64_t helper_divdeu(CPUPPCState *env, uint64_t ra, uint64_t rb, uint32_t oe)
86
87
uint64_t helper_divde(CPUPPCState *env, uint64_t rau, uint64_t rbu, uint32_t oe)
88
{
89
- int64_t rt = 0;
90
+ uint64_t rt = 0;
91
int64_t ra = (int64_t)rau;
92
int64_t rb = (int64_t)rbu;
93
int overflow = 0;
94
@@ -XXX,XX +XXX,XX @@ uint32_t helper_bcdcfsq(ppc_avr_t *r, ppc_avr_t *b, uint32_t ps)
95
int cr;
96
uint64_t lo_value;
97
uint64_t hi_value;
98
+ uint64_t rem;
99
ppc_avr_t ret = { .u64 = { 0, 0 } };
100
101
if (b->VsrSD(0) < 0) {
102
@@ -XXX,XX +XXX,XX @@ uint32_t helper_bcdcfsq(ppc_avr_t *r, ppc_avr_t *b, uint32_t ps)
103
* In that case, we leave r unchanged.
104
*/
105
} else {
106
- divu128(&lo_value, &hi_value, 1000000000000000ULL);
107
+ rem = divu128(&lo_value, &hi_value, 1000000000000000ULL);
108
109
- for (i = 1; i < 16; hi_value /= 10, i++) {
110
- bcd_put_digit(&ret, hi_value % 10, i);
111
+ for (i = 1; i < 16; rem /= 10, i++) {
112
+ bcd_put_digit(&ret, rem % 10, i);
113
}
114
115
for (; i < 32; lo_value /= 10, i++) {
116
diff --git a/util/host-utils.c b/util/host-utils.c
117
index XXXXXXX..XXXXXXX 100644
118
--- a/util/host-utils.c
119
+++ b/util/host-utils.c
120
@@ -XXX,XX +XXX,XX @@ void muls64 (uint64_t *plow, uint64_t *phigh, int64_t a, int64_t b)
121
}
122
123
/*
124
- * Unsigned 128-by-64 division. Returns quotient via plow and
125
- * remainder via phigh.
126
- * The result must fit in 64 bits (plow) - otherwise, the result
127
- * is undefined.
128
- * This function will cause a division by zero if passed a zero divisor.
129
+ * Unsigned 128-by-64 division.
130
+ * Returns the remainder.
131
+ * Returns quotient via plow and phigh.
132
+ * Also returns the remainder via the function return value.
133
*/
134
-void divu128(uint64_t *plow, uint64_t *phigh, uint64_t divisor)
135
+uint64_t divu128(uint64_t *plow, uint64_t *phigh, uint64_t divisor)
136
{
137
uint64_t dhi = *phigh;
138
uint64_t dlo = *plow;
139
- unsigned i;
140
- uint64_t carry = 0;
141
+ uint64_t rem, dhighest;
142
+ int sh;
143
144
if (divisor == 0 || dhi == 0) {
145
*plow = dlo / divisor;
146
- *phigh = dlo % divisor;
147
+ *phigh = 0;
148
+ return dlo % divisor;
149
} else {
150
+ sh = clz64(divisor);
151
152
- for (i = 0; i < 64; i++) {
153
- carry = dhi >> 63;
154
- dhi = (dhi << 1) | (dlo >> 63);
155
- if (carry || (dhi >= divisor)) {
156
- dhi -= divisor;
157
- carry = 1;
158
- } else {
159
- carry = 0;
160
+ if (dhi < divisor) {
161
+ if (sh != 0) {
162
+ /* normalize the divisor, shifting the dividend accordingly */
163
+ divisor <<= sh;
164
+ dhi = (dhi << sh) | (dlo >> (64 - sh));
165
+ dlo <<= sh;
166
}
167
- dlo = (dlo << 1) | carry;
168
+
169
+ *phigh = 0;
170
+ *plow = udiv_qrnnd(&rem, dhi, dlo, divisor);
171
+ } else {
172
+ if (sh != 0) {
173
+ /* normalize the divisor, shifting the dividend accordingly */
174
+ divisor <<= sh;
175
+ dhighest = dhi >> (64 - sh);
176
+ dhi = (dhi << sh) | (dlo >> (64 - sh));
177
+ dlo <<= sh;
178
+
179
+ *phigh = udiv_qrnnd(&dhi, dhighest, dhi, divisor);
180
+ } else {
181
+ /**
182
+ * dhi >= divisor
183
+ * Since the MSB of divisor is set (sh == 0),
184
+ * (dhi - divisor) < divisor
185
+ *
186
+ * Thus, the high part of the quotient is 1, and we can
187
+ * calculate the low part with a single call to udiv_qrnnd
188
+ * after subtracting divisor from dhi
189
+ */
190
+ dhi -= divisor;
191
+ *phigh = 1;
192
+ }
193
+
194
+ *plow = udiv_qrnnd(&rem, dhi, dlo, divisor);
195
}
196
197
- *plow = dlo;
198
- *phigh = dhi;
199
+ /*
200
+ * since the dividend/divisor might have been normalized,
201
+ * the remainder might also have to be shifted back
202
+ */
203
+ return rem >> sh;
204
}
205
}
206
207
/*
208
- * Signed 128-by-64 division. Returns quotient via plow and
209
- * remainder via phigh.
210
- * The result must fit in 64 bits (plow) - otherwise, the result
211
- * is undefined.
212
- * This function will cause a division by zero if passed a zero divisor.
213
+ * Signed 128-by-64 division.
214
+ * Returns quotient via plow and phigh.
215
+ * Also returns the remainder via the function return value.
216
*/
217
-void divs128(int64_t *plow, int64_t *phigh, int64_t divisor)
218
+int64_t divs128(uint64_t *plow, int64_t *phigh, int64_t divisor)
219
{
220
- int sgn_dvdnd = *phigh < 0;
221
- int sgn_divsr = divisor < 0;
222
+ bool neg_quotient = false, neg_remainder = false;
223
+ uint64_t unsig_hi = *phigh, unsig_lo = *plow;
224
+ uint64_t rem;
225
226
- if (sgn_dvdnd) {
227
- *plow = ~(*plow);
228
- *phigh = ~(*phigh);
229
- if (*plow == (int64_t)-1) {
230
+ if (*phigh < 0) {
231
+ neg_quotient = !neg_quotient;
232
+ neg_remainder = !neg_remainder;
233
+
234
+ if (unsig_lo == 0) {
235
+ unsig_hi = -unsig_hi;
236
+ } else {
237
+ unsig_hi = ~unsig_hi;
238
+ unsig_lo = -unsig_lo;
239
+ }
240
+ }
241
+
242
+ if (divisor < 0) {
243
+ neg_quotient = !neg_quotient;
244
+
245
+ divisor = -divisor;
246
+ }
247
+
248
+ rem = divu128(&unsig_lo, &unsig_hi, (uint64_t)divisor);
249
+
250
+ if (neg_quotient) {
251
+ if (unsig_lo == 0) {
252
+ *phigh = -unsig_hi;
253
*plow = 0;
254
- (*phigh)++;
255
- } else {
256
- (*plow)++;
257
- }
258
+ } else {
259
+ *phigh = ~unsig_hi;
260
+ *plow = -unsig_lo;
261
+ }
262
+ } else {
263
+ *phigh = unsig_hi;
264
+ *plow = unsig_lo;
265
}
266
267
- if (sgn_divsr) {
268
- divisor = 0 - divisor;
269
- }
270
-
271
- divu128((uint64_t *)plow, (uint64_t *)phigh, (uint64_t)divisor);
272
-
273
- if (sgn_dvdnd ^ sgn_divsr) {
274
- *plow = 0 - *plow;
275
+ if (neg_remainder) {
276
+ return -rem;
277
+ } else {
278
+ return rem;
279
}
280
}
281
#endif
282
--
283
2.25.1
284
285
diff view generated by jsdifflib
New patch
[PULL 05/56] host-utils: add unit tests for divu128/divs128
1
1
From: Luis Pires <luis.pires@eldorado.org.br>
2
3
Signed-off-by: Luis Pires <luis.pires@eldorado.org.br>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-Id: <20211025191154.350831-5-luis.pires@eldorado.org.br>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
---
8
tests/unit/test-div128.c | 197 +++++++++++++++++++++++++++++++++++++++
9
tests/unit/meson.build | 1 +
10
2 files changed, 198 insertions(+)
11
create mode 100644 tests/unit/test-div128.c
12
13
diff --git a/tests/unit/test-div128.c b/tests/unit/test-div128.c
14
new file mode 100644
15
index XXXXXXX..XXXXXXX
16
--- /dev/null
17
+++ b/tests/unit/test-div128.c
18
@@ -XXX,XX +XXX,XX @@
19
+/*
20
+ * Test 128-bit division functions
21
+ *
22
+ * Copyright (c) 2021 Instituto de Pesquisas Eldorado (eldorado.org.br)
23
+ *
24
+ * This library is free software; you can redistribute it and/or
25
+ * modify it under the terms of the GNU Lesser General Public
26
+ * License as published by the Free Software Foundation; either
27
+ * version 2.1 of the License, or (at your option) any later version.
28
+ *
29
+ * This library is distributed in the hope that it will be useful,
30
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
31
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
32
+ * Lesser General Public License for more details.
33
+ *
34
+ * You should have received a copy of the GNU Lesser General Public
35
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
36
+ */
37
+
38
+#include "qemu/osdep.h"
39
+#include "qemu/host-utils.h"
40
+
41
+typedef struct {
42
+ uint64_t high;
43
+ uint64_t low;
44
+ uint64_t rhigh;
45
+ uint64_t rlow;
46
+ uint64_t divisor;
47
+ uint64_t remainder;
48
+} test_data_unsigned;
49
+
50
+typedef struct {
51
+ int64_t high;
52
+ uint64_t low;
53
+ int64_t rhigh;
54
+ uint64_t rlow;
55
+ int64_t divisor;
56
+ int64_t remainder;
57
+} test_data_signed;
58
+
59
+static const test_data_unsigned test_table_unsigned[] = {
60
+ /* Dividend fits in 64 bits */
61
+ { 0x0000000000000000ULL, 0x0000000000000000ULL,
62
+ 0x0000000000000000ULL, 0x0000000000000000ULL,
63
+ 0x0000000000000001ULL, 0x0000000000000000ULL},
64
+ { 0x0000000000000000ULL, 0x0000000000000001ULL,
65
+ 0x0000000000000000ULL, 0x0000000000000001ULL,
66
+ 0x0000000000000001ULL, 0x0000000000000000ULL},
67
+ { 0x0000000000000000ULL, 0x0000000000000003ULL,
68
+ 0x0000000000000000ULL, 0x0000000000000001ULL,
69
+ 0x0000000000000002ULL, 0x0000000000000001ULL},
70
+ { 0x0000000000000000ULL, 0x8000000000000000ULL,
71
+ 0x0000000000000000ULL, 0x8000000000000000ULL,
72
+ 0x0000000000000001ULL, 0x0000000000000000ULL},
73
+ { 0x0000000000000000ULL, 0xa000000000000000ULL,
74
+ 0x0000000000000000ULL, 0x0000000000000002ULL,
75
+ 0x4000000000000000ULL, 0x2000000000000000ULL},
76
+ { 0x0000000000000000ULL, 0x8000000000000000ULL,
77
+ 0x0000000000000000ULL, 0x0000000000000001ULL,
78
+ 0x8000000000000000ULL, 0x0000000000000000ULL},
79
+
80
+ /* Dividend > 64 bits, with MSB 0 */
81
+ { 0x123456789abcdefeULL, 0xefedcba987654321ULL,
82
+ 0x123456789abcdefeULL, 0xefedcba987654321ULL,
83
+ 0x0000000000000001ULL, 0x0000000000000000ULL},
84
+ { 0x123456789abcdefeULL, 0xefedcba987654321ULL,
85
+ 0x0000000000000001ULL, 0x000000000000000dULL,
86
+ 0x123456789abcdefeULL, 0x03456789abcdf03bULL},
87
+ { 0x123456789abcdefeULL, 0xefedcba987654321ULL,
88
+ 0x0123456789abcdefULL, 0xeefedcba98765432ULL,
89
+ 0x0000000000000010ULL, 0x0000000000000001ULL},
90
+
91
+ /* Dividend > 64 bits, with MSB 1 */
92
+ { 0xfeeddccbbaa99887ULL, 0x766554433221100fULL,
93
+ 0xfeeddccbbaa99887ULL, 0x766554433221100fULL,
94
+ 0x0000000000000001ULL, 0x0000000000000000ULL},
95
+ { 0xfeeddccbbaa99887ULL, 0x766554433221100fULL,
96
+ 0x0000000000000001ULL, 0x0000000000000000ULL,
97
+ 0xfeeddccbbaa99887ULL, 0x766554433221100fULL},
98
+ { 0xfeeddccbbaa99887ULL, 0x766554433221100fULL,
99
+ 0x0feeddccbbaa9988ULL, 0x7766554433221100ULL,
100
+ 0x0000000000000010ULL, 0x000000000000000fULL},
101
+ { 0xfeeddccbbaa99887ULL, 0x766554433221100fULL,
102
+ 0x000000000000000eULL, 0x00f0f0f0f0f0f35aULL,
103
+ 0x123456789abcdefeULL, 0x0f8922bc55ef90c3ULL},
104
+
105
+ /**
106
+ * Divisor == 64 bits, with MSB 1
107
+ * and high 64 bits of dividend >= divisor
108
+ * (for testing normalization)
109
+ */
110
+ { 0xfeeddccbbaa99887ULL, 0x766554433221100fULL,
111
+ 0x0000000000000001ULL, 0x0000000000000000ULL,
112
+ 0xfeeddccbbaa99887ULL, 0x766554433221100fULL},
113
+ { 0xfeeddccbbaa99887ULL, 0x766554433221100fULL,
114
+ 0x0000000000000001ULL, 0xfddbb9977553310aULL,
115
+ 0x8000000000000001ULL, 0x78899aabbccddf05ULL},
116
+
117
+ /* Dividend > 64 bits, divisor almost as big */
118
+ { 0x0000000000000001ULL, 0x23456789abcdef01ULL,
119
+ 0x0000000000000000ULL, 0x000000000000000fULL,
120
+ 0x123456789abcdefeULL, 0x123456789abcde1fULL},
121
+};
122
+
123
+static const test_data_signed test_table_signed[] = {
124
+ /* Positive dividend, positive/negative divisors */
125
+ { 0x0000000000000000LL, 0x0000000000bc614eULL,
126
+ 0x0000000000000000LL, 0x0000000000bc614eULL,
127
+ 0x0000000000000001LL, 0x0000000000000000LL},
128
+ { 0x0000000000000000LL, 0x0000000000bc614eULL,
129
+ 0xffffffffffffffffLL, 0xffffffffff439eb2ULL,
130
+ 0xffffffffffffffffLL, 0x0000000000000000LL},
131
+ { 0x0000000000000000LL, 0x0000000000bc614eULL,
132
+ 0x0000000000000000LL, 0x00000000005e30a7ULL,
133
+ 0x0000000000000002LL, 0x0000000000000000LL},
134
+ { 0x0000000000000000LL, 0x0000000000bc614eULL,
135
+ 0xffffffffffffffffLL, 0xffffffffffa1cf59ULL,
136
+ 0xfffffffffffffffeLL, 0x0000000000000000LL},
137
+ { 0x0000000000000000LL, 0x0000000000bc614eULL,
138
+ 0x0000000000000000LL, 0x0000000000178c29ULL,
139
+ 0x0000000000000008LL, 0x0000000000000006LL},
140
+ { 0x0000000000000000LL, 0x0000000000bc614eULL,
141
+ 0xffffffffffffffffLL, 0xffffffffffe873d7ULL,
142
+ 0xfffffffffffffff8LL, 0x0000000000000006LL},
143
+ { 0x0000000000000000LL, 0x0000000000bc614eULL,
144
+ 0x0000000000000000LL, 0x000000000000550dULL,
145
+ 0x0000000000000237LL, 0x0000000000000183LL},
146
+ { 0x0000000000000000LL, 0x0000000000bc614eULL,
147
+ 0xffffffffffffffffLL, 0xffffffffffffaaf3ULL,
148
+ 0xfffffffffffffdc9LL, 0x0000000000000183LL},
149
+
150
+ /* Negative dividend, positive/negative divisors */
151
+ { 0xffffffffffffffffLL, 0xffffffffff439eb2ULL,
152
+ 0xffffffffffffffffLL, 0xffffffffff439eb2ULL,
153
+ 0x0000000000000001LL, 0x0000000000000000LL},
154
+ { 0xffffffffffffffffLL, 0xffffffffff439eb2ULL,
155
+ 0x0000000000000000LL, 0x0000000000bc614eULL,
156
+ 0xffffffffffffffffLL, 0x0000000000000000LL},
157
+ { 0xffffffffffffffffLL, 0xffffffffff439eb2ULL,
158
+ 0xffffffffffffffffLL, 0xffffffffffa1cf59ULL,
159
+ 0x0000000000000002LL, 0x0000000000000000LL},
160
+ { 0xffffffffffffffffLL, 0xffffffffff439eb2ULL,
161
+ 0x0000000000000000LL, 0x00000000005e30a7ULL,
162
+ 0xfffffffffffffffeLL, 0x0000000000000000LL},
163
+ { 0xffffffffffffffffLL, 0xffffffffff439eb2ULL,
164
+ 0xffffffffffffffffLL, 0xffffffffffe873d7ULL,
165
+ 0x0000000000000008LL, 0xfffffffffffffffaLL},
166
+ { 0xffffffffffffffffLL, 0xffffffffff439eb2ULL,
167
+ 0x0000000000000000LL, 0x0000000000178c29ULL,
168
+ 0xfffffffffffffff8LL, 0xfffffffffffffffaLL},
169
+ { 0xffffffffffffffffLL, 0xffffffffff439eb2ULL,
170
+ 0xffffffffffffffffLL, 0xffffffffffffaaf3ULL,
171
+ 0x0000000000000237LL, 0xfffffffffffffe7dLL},
172
+ { 0xffffffffffffffffLL, 0xffffffffff439eb2ULL,
173
+ 0x0000000000000000LL, 0x000000000000550dULL,
174
+ 0xfffffffffffffdc9LL, 0xfffffffffffffe7dLL},
175
+};
176
+
177
+static void test_divu128(void)
178
+{
179
+ int i;
180
+ uint64_t rem;
181
+ test_data_unsigned tmp;
182
+
183
+ for (i = 0; i < ARRAY_SIZE(test_table_unsigned); ++i) {
184
+ tmp = test_table_unsigned[i];
185
+
186
+ rem = divu128(&tmp.low, &tmp.high, tmp.divisor);
187
+ g_assert_cmpuint(tmp.low, ==, tmp.rlow);
188
+ g_assert_cmpuint(tmp.high, ==, tmp.rhigh);
189
+ g_assert_cmpuint(rem, ==, tmp.remainder);
190
+ }
191
+}
192
+
193
+static void test_divs128(void)
194
+{
195
+ int i;
196
+ int64_t rem;
197
+ test_data_signed tmp;
198
+
199
+ for (i = 0; i < ARRAY_SIZE(test_table_signed); ++i) {
200
+ tmp = test_table_signed[i];
201
+
202
+ rem = divs128(&tmp.low, &tmp.high, tmp.divisor);
203
+ g_assert_cmpuint(tmp.low, ==, tmp.rlow);
204
+ g_assert_cmpuint(tmp.high, ==, tmp.rhigh);
205
+ g_assert_cmpuint(rem, ==, tmp.remainder);
206
+ }
207
+}
208
+
209
+int main(int argc, char **argv)
210
+{
211
+ g_test_init(&argc, &argv, NULL);
212
+ g_test_add_func("/host-utils/test_divu128", test_divu128);
213
+ g_test_add_func("/host-utils/test_divs128", test_divs128);
214
+ return g_test_run();
215
+}
216
diff --git a/tests/unit/meson.build b/tests/unit/meson.build
217
index XXXXXXX..XXXXXXX 100644
218
--- a/tests/unit/meson.build
219
+++ b/tests/unit/meson.build
220
@@ -XXX,XX +XXX,XX @@ tests = {
221
# all code tested by test-x86-cpuid is inside topology.h
222
'test-x86-cpuid': [],
223
'test-cutils': [],
224
+ 'test-div128': [],
225
'test-shift128': [],
226
'test-mul64': [],
227
# all code tested by test-int128 is inside int128.h
228
--
229
2.25.1
230
231
diff view generated by jsdifflib
[PATCH 18/27] tcg/tci: Reduce use of tci_read_r64
[PULL 06/56] tcg/optimize: Rename "mask" to "z_mask"
1
In all cases restricted to 64-bit hosts, tcg_read_r is
1
Prepare for tracking different masks by renaming this one.
2
identical. We retain the 64-bit symbol for the single
3
case of INDEX_op_qemu_st_i64.
4
2
3
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
4
Reviewed-by: Luis Pires <luis.pires@eldorado.org.br>
5
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
5
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
---
7
---
8
tcg/tci.c | 93 +++++++++++++++++++++++++------------------------------
8
tcg/optimize.c | 142 +++++++++++++++++++++++++------------------------
9
1 file changed, 42 insertions(+), 51 deletions(-)
9
1 file changed, 72 insertions(+), 70 deletions(-)
10
10
11
diff --git a/tcg/tci.c b/tcg/tci.c
11
diff --git a/tcg/optimize.c b/tcg/optimize.c
12
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
13
--- a/tcg/tci.c
13
--- a/tcg/optimize.c
14
+++ b/tcg/tci.c
14
+++ b/tcg/optimize.c
15
@@ -XXX,XX +XXX,XX @@ static tcg_target_ulong tci_read_reg(const tcg_target_ulong *regs, TCGReg index)
15
@@ -XXX,XX +XXX,XX @@ typedef struct TempOptInfo {
16
return regs[index];
16
TCGTemp *prev_copy;
17
TCGTemp *next_copy;
18
uint64_t val;
19
- uint64_t mask;
20
+ uint64_t z_mask; /* mask bit is 0 if and only if value bit is 0 */
21
} TempOptInfo;
22
23
static inline TempOptInfo *ts_info(TCGTemp *ts)
24
@@ -XXX,XX +XXX,XX @@ static void reset_ts(TCGTemp *ts)
25
ti->next_copy = ts;
26
ti->prev_copy = ts;
27
ti->is_const = false;
28
- ti->mask = -1;
29
+ ti->z_mask = -1;
17
}
30
}
18
31
19
-#if TCG_TARGET_REG_BITS == 64
32
static void reset_temp(TCGArg arg)
20
-static uint64_t tci_read_reg64(const tcg_target_ulong *regs, TCGReg index)
33
@@ -XXX,XX +XXX,XX @@ static void init_ts_info(TCGTempSet *temps_used, TCGTemp *ts)
21
-{
34
if (ts->kind == TEMP_CONST) {
22
- return tci_read_reg(regs, index);
35
ti->is_const = true;
23
-}
36
ti->val = ts->val;
24
-#endif
37
- ti->mask = ts->val;
25
-
38
+ ti->z_mask = ts->val;
26
static void
39
if (TCG_TARGET_REG_BITS > 32 && ts->type == TCG_TYPE_I32) {
27
tci_write_reg(tcg_target_ulong *regs, TCGReg index, tcg_target_ulong value)
40
/* High bits of a 32-bit quantity are garbage. */
28
{
41
- ti->mask |= ~0xffffffffull;
29
@@ -XXX,XX +XXX,XX @@ static uint64_t tci_read_r64(const tcg_target_ulong *regs,
42
+ ti->z_mask |= ~0xffffffffull;
30
static uint64_t tci_read_r64(const tcg_target_ulong *regs,
43
}
31
const uint8_t **tb_ptr)
44
} else {
32
{
45
ti->is_const = false;
33
- uint64_t value = tci_read_reg64(regs, **tb_ptr);
46
- ti->mask = -1;
34
- *tb_ptr += 1;
47
+ ti->z_mask = -1;
35
- return value;
48
}
36
+ return tci_read_r(regs, tb_ptr);
37
}
49
}
38
#endif
50
39
51
@@ -XXX,XX +XXX,XX @@ static void tcg_opt_gen_mov(TCGContext *s, TCGOp *op, TCGArg dst, TCGArg src)
40
@@ -XXX,XX +XXX,XX @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
52
const TCGOpDef *def;
41
#elif TCG_TARGET_REG_BITS == 64
53
TempOptInfo *di;
42
case INDEX_op_setcond_i64:
54
TempOptInfo *si;
43
t0 = *tb_ptr++;
55
- uint64_t mask;
44
- t1 = tci_read_r64(regs, &tb_ptr);
56
+ uint64_t z_mask;
45
- t2 = tci_read_r64(regs, &tb_ptr);
57
TCGOpcode new_op;
46
+ t1 = tci_read_r(regs, &tb_ptr);
58
47
+ t2 = tci_read_r(regs, &tb_ptr);
59
if (ts_are_copies(dst_ts, src_ts)) {
48
condition = *tb_ptr++;
60
@@ -XXX,XX +XXX,XX @@ static void tcg_opt_gen_mov(TCGContext *s, TCGOp *op, TCGArg dst, TCGArg src)
49
tci_write_reg(regs, t0, tci_compare64(t1, t2, condition));
61
op->args[0] = dst;
50
break;
62
op->args[1] = src;
51
@@ -XXX,XX +XXX,XX @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
63
52
#if TCG_TARGET_REG_BITS == 64
64
- mask = si->mask;
53
case INDEX_op_mov_i64:
65
+ z_mask = si->z_mask;
54
t0 = *tb_ptr++;
66
if (TCG_TARGET_REG_BITS > 32 && new_op == INDEX_op_mov_i32) {
55
- t1 = tci_read_r64(regs, &tb_ptr);
67
/* High bits of the destination are now garbage. */
56
+ t1 = tci_read_r(regs, &tb_ptr);
68
- mask |= ~0xffffffffull;
57
tci_write_reg(regs, t0, t1);
69
+ z_mask |= ~0xffffffffull;
58
break;
70
}
59
case INDEX_op_tci_movi_i64:
71
- di->mask = mask;
60
@@ -XXX,XX +XXX,XX @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
72
+ di->z_mask = z_mask;
61
tci_write_reg(regs, t0, *(uint64_t *)(t1 + t2));
73
62
break;
74
if (src_ts->type == dst_ts->type) {
63
case INDEX_op_st_i64:
75
TempOptInfo *ni = ts_info(si->next_copy);
64
- t0 = tci_read_r64(regs, &tb_ptr);
76
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
65
+ t0 = tci_read_r(regs, &tb_ptr);
77
}
66
t1 = tci_read_r(regs, &tb_ptr);
78
67
t2 = tci_read_s32(&tb_ptr);
79
QTAILQ_FOREACH_SAFE(op, &s->ops, link, op_next) {
68
*(uint64_t *)(t1 + t2) = t0;
80
- uint64_t mask, partmask, affected, tmp;
69
@@ -XXX,XX +XXX,XX @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
81
+ uint64_t z_mask, partmask, affected, tmp;
70
82
int nb_oargs, nb_iargs;
71
case INDEX_op_add_i64:
83
TCGOpcode opc = op->opc;
72
t0 = *tb_ptr++;
84
const TCGOpDef *def = &tcg_op_defs[opc];
73
- t1 = tci_read_r64(regs, &tb_ptr);
85
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
74
- t2 = tci_read_r64(regs, &tb_ptr);
86
75
+ t1 = tci_read_r(regs, &tb_ptr);
87
/* Simplify using known-zero bits. Currently only ops with a single
76
+ t2 = tci_read_r(regs, &tb_ptr);
88
output argument is supported. */
77
tci_write_reg(regs, t0, t1 + t2);
89
- mask = -1;
78
break;
90
+ z_mask = -1;
79
case INDEX_op_sub_i64:
91
affected = -1;
80
t0 = *tb_ptr++;
92
switch (opc) {
81
- t1 = tci_read_r64(regs, &tb_ptr);
93
CASE_OP_32_64(ext8s):
82
- t2 = tci_read_r64(regs, &tb_ptr);
94
- if ((arg_info(op->args[1])->mask & 0x80) != 0) {
83
+ t1 = tci_read_r(regs, &tb_ptr);
95
+ if ((arg_info(op->args[1])->z_mask & 0x80) != 0) {
84
+ t2 = tci_read_r(regs, &tb_ptr);
96
break;
85
tci_write_reg(regs, t0, t1 - t2);
97
}
86
break;
98
QEMU_FALLTHROUGH;
87
case INDEX_op_mul_i64:
99
CASE_OP_32_64(ext8u):
88
t0 = *tb_ptr++;
100
- mask = 0xff;
89
- t1 = tci_read_r64(regs, &tb_ptr);
101
+ z_mask = 0xff;
90
- t2 = tci_read_r64(regs, &tb_ptr);
102
goto and_const;
91
+ t1 = tci_read_r(regs, &tb_ptr);
103
CASE_OP_32_64(ext16s):
92
+ t2 = tci_read_r(regs, &tb_ptr);
104
- if ((arg_info(op->args[1])->mask & 0x8000) != 0) {
93
tci_write_reg(regs, t0, t1 * t2);
105
+ if ((arg_info(op->args[1])->z_mask & 0x8000) != 0) {
94
break;
106
break;
95
case INDEX_op_div_i64:
107
}
96
t0 = *tb_ptr++;
108
QEMU_FALLTHROUGH;
97
- t1 = tci_read_r64(regs, &tb_ptr);
109
CASE_OP_32_64(ext16u):
98
- t2 = tci_read_r64(regs, &tb_ptr);
110
- mask = 0xffff;
99
+ t1 = tci_read_r(regs, &tb_ptr);
111
+ z_mask = 0xffff;
100
+ t2 = tci_read_r(regs, &tb_ptr);
112
goto and_const;
101
tci_write_reg(regs, t0, (int64_t)t1 / (int64_t)t2);
113
case INDEX_op_ext32s_i64:
102
break;
114
- if ((arg_info(op->args[1])->mask & 0x80000000) != 0) {
103
case INDEX_op_divu_i64:
115
+ if ((arg_info(op->args[1])->z_mask & 0x80000000) != 0) {
104
t0 = *tb_ptr++;
116
break;
105
- t1 = tci_read_r64(regs, &tb_ptr);
117
}
106
- t2 = tci_read_r64(regs, &tb_ptr);
118
QEMU_FALLTHROUGH;
107
+ t1 = tci_read_r(regs, &tb_ptr);
119
case INDEX_op_ext32u_i64:
108
+ t2 = tci_read_r(regs, &tb_ptr);
120
- mask = 0xffffffffU;
109
tci_write_reg(regs, t0, (uint64_t)t1 / (uint64_t)t2);
121
+ z_mask = 0xffffffffU;
110
break;
122
goto and_const;
111
case INDEX_op_rem_i64:
123
112
t0 = *tb_ptr++;
124
CASE_OP_32_64(and):
113
- t1 = tci_read_r64(regs, &tb_ptr);
125
- mask = arg_info(op->args[2])->mask;
114
- t2 = tci_read_r64(regs, &tb_ptr);
126
+ z_mask = arg_info(op->args[2])->z_mask;
115
+ t1 = tci_read_r(regs, &tb_ptr);
127
if (arg_is_const(op->args[2])) {
116
+ t2 = tci_read_r(regs, &tb_ptr);
128
and_const:
117
tci_write_reg(regs, t0, (int64_t)t1 % (int64_t)t2);
129
- affected = arg_info(op->args[1])->mask & ~mask;
118
break;
130
+ affected = arg_info(op->args[1])->z_mask & ~z_mask;
119
case INDEX_op_remu_i64:
131
}
120
t0 = *tb_ptr++;
132
- mask = arg_info(op->args[1])->mask & mask;
121
- t1 = tci_read_r64(regs, &tb_ptr);
133
+ z_mask = arg_info(op->args[1])->z_mask & z_mask;
122
- t2 = tci_read_r64(regs, &tb_ptr);
134
break;
123
+ t1 = tci_read_r(regs, &tb_ptr);
135
124
+ t2 = tci_read_r(regs, &tb_ptr);
136
case INDEX_op_ext_i32_i64:
125
tci_write_reg(regs, t0, (uint64_t)t1 % (uint64_t)t2);
137
- if ((arg_info(op->args[1])->mask & 0x80000000) != 0) {
126
break;
138
+ if ((arg_info(op->args[1])->z_mask & 0x80000000) != 0) {
127
case INDEX_op_and_i64:
139
break;
128
t0 = *tb_ptr++;
140
}
129
- t1 = tci_read_r64(regs, &tb_ptr);
141
QEMU_FALLTHROUGH;
130
- t2 = tci_read_r64(regs, &tb_ptr);
142
case INDEX_op_extu_i32_i64:
131
+ t1 = tci_read_r(regs, &tb_ptr);
143
/* We do not compute affected as it is a size changing op. */
132
+ t2 = tci_read_r(regs, &tb_ptr);
144
- mask = (uint32_t)arg_info(op->args[1])->mask;
133
tci_write_reg(regs, t0, t1 & t2);
145
+ z_mask = (uint32_t)arg_info(op->args[1])->z_mask;
134
break;
146
break;
135
case INDEX_op_or_i64:
147
136
t0 = *tb_ptr++;
148
CASE_OP_32_64(andc):
137
- t1 = tci_read_r64(regs, &tb_ptr);
149
/* Known-zeros does not imply known-ones. Therefore unless
138
- t2 = tci_read_r64(regs, &tb_ptr);
150
op->args[2] is constant, we can't infer anything from it. */
139
+ t1 = tci_read_r(regs, &tb_ptr);
151
if (arg_is_const(op->args[2])) {
140
+ t2 = tci_read_r(regs, &tb_ptr);
152
- mask = ~arg_info(op->args[2])->mask;
141
tci_write_reg(regs, t0, t1 | t2);
153
+ z_mask = ~arg_info(op->args[2])->z_mask;
142
break;
154
goto and_const;
143
case INDEX_op_xor_i64:
155
}
144
t0 = *tb_ptr++;
156
/* But we certainly know nothing outside args[1] may be set. */
145
- t1 = tci_read_r64(regs, &tb_ptr);
157
- mask = arg_info(op->args[1])->mask;
146
- t2 = tci_read_r64(regs, &tb_ptr);
158
+ z_mask = arg_info(op->args[1])->z_mask;
147
+ t1 = tci_read_r(regs, &tb_ptr);
159
break;
148
+ t2 = tci_read_r(regs, &tb_ptr);
160
149
tci_write_reg(regs, t0, t1 ^ t2);
161
case INDEX_op_sar_i32:
150
break;
162
if (arg_is_const(op->args[2])) {
151
163
tmp = arg_info(op->args[2])->val & 31;
152
@@ -XXX,XX +XXX,XX @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
164
- mask = (int32_t)arg_info(op->args[1])->mask >> tmp;
153
165
+ z_mask = (int32_t)arg_info(op->args[1])->z_mask >> tmp;
154
case INDEX_op_shl_i64:
166
}
155
t0 = *tb_ptr++;
167
break;
156
- t1 = tci_read_r64(regs, &tb_ptr);
168
case INDEX_op_sar_i64:
157
- t2 = tci_read_r64(regs, &tb_ptr);
169
if (arg_is_const(op->args[2])) {
158
+ t1 = tci_read_r(regs, &tb_ptr);
170
tmp = arg_info(op->args[2])->val & 63;
159
+ t2 = tci_read_r(regs, &tb_ptr);
171
- mask = (int64_t)arg_info(op->args[1])->mask >> tmp;
160
tci_write_reg(regs, t0, t1 << (t2 & 63));
172
+ z_mask = (int64_t)arg_info(op->args[1])->z_mask >> tmp;
173
}
174
break;
175
176
case INDEX_op_shr_i32:
177
if (arg_is_const(op->args[2])) {
178
tmp = arg_info(op->args[2])->val & 31;
179
- mask = (uint32_t)arg_info(op->args[1])->mask >> tmp;
180
+ z_mask = (uint32_t)arg_info(op->args[1])->z_mask >> tmp;
181
}
161
break;
182
break;
162
case INDEX_op_shr_i64:
183
case INDEX_op_shr_i64:
163
t0 = *tb_ptr++;
184
if (arg_is_const(op->args[2])) {
164
- t1 = tci_read_r64(regs, &tb_ptr);
185
tmp = arg_info(op->args[2])->val & 63;
165
- t2 = tci_read_r64(regs, &tb_ptr);
186
- mask = (uint64_t)arg_info(op->args[1])->mask >> tmp;
166
+ t1 = tci_read_r(regs, &tb_ptr);
187
+ z_mask = (uint64_t)arg_info(op->args[1])->z_mask >> tmp;
167
+ t2 = tci_read_r(regs, &tb_ptr);
188
}
168
tci_write_reg(regs, t0, t1 >> (t2 & 63));
189
break;
169
break;
190
170
case INDEX_op_sar_i64:
191
case INDEX_op_extrl_i64_i32:
171
t0 = *tb_ptr++;
192
- mask = (uint32_t)arg_info(op->args[1])->mask;
172
- t1 = tci_read_r64(regs, &tb_ptr);
193
+ z_mask = (uint32_t)arg_info(op->args[1])->z_mask;
173
- t2 = tci_read_r64(regs, &tb_ptr);
194
break;
174
+ t1 = tci_read_r(regs, &tb_ptr);
195
case INDEX_op_extrh_i64_i32:
175
+ t2 = tci_read_r(regs, &tb_ptr);
196
- mask = (uint64_t)arg_info(op->args[1])->mask >> 32;
176
tci_write_reg(regs, t0, ((int64_t)t1 >> (t2 & 63)));
197
+ z_mask = (uint64_t)arg_info(op->args[1])->z_mask >> 32;
177
break;
198
break;
178
#if TCG_TARGET_HAS_rot_i64
199
179
case INDEX_op_rotl_i64:
200
CASE_OP_32_64(shl):
180
t0 = *tb_ptr++;
201
if (arg_is_const(op->args[2])) {
181
- t1 = tci_read_r64(regs, &tb_ptr);
202
tmp = arg_info(op->args[2])->val & (TCG_TARGET_REG_BITS - 1);
182
- t2 = tci_read_r64(regs, &tb_ptr);
203
- mask = arg_info(op->args[1])->mask << tmp;
183
+ t1 = tci_read_r(regs, &tb_ptr);
204
+ z_mask = arg_info(op->args[1])->z_mask << tmp;
184
+ t2 = tci_read_r(regs, &tb_ptr);
205
}
185
tci_write_reg(regs, t0, rol64(t1, t2 & 63));
206
break;
186
break;
207
187
case INDEX_op_rotr_i64:
208
CASE_OP_32_64(neg):
188
t0 = *tb_ptr++;
209
/* Set to 1 all bits to the left of the rightmost. */
189
- t1 = tci_read_r64(regs, &tb_ptr);
210
- mask = -(arg_info(op->args[1])->mask
190
- t2 = tci_read_r64(regs, &tb_ptr);
211
- & -arg_info(op->args[1])->mask);
191
+ t1 = tci_read_r(regs, &tb_ptr);
212
+ z_mask = -(arg_info(op->args[1])->z_mask
192
+ t2 = tci_read_r(regs, &tb_ptr);
213
+ & -arg_info(op->args[1])->z_mask);
193
tci_write_reg(regs, t0, ror64(t1, t2 & 63));
214
break;
194
break;
215
195
#endif
216
CASE_OP_32_64(deposit):
196
#if TCG_TARGET_HAS_deposit_i64
217
- mask = deposit64(arg_info(op->args[1])->mask,
197
case INDEX_op_deposit_i64:
218
- op->args[3], op->args[4],
198
t0 = *tb_ptr++;
219
- arg_info(op->args[2])->mask);
199
- t1 = tci_read_r64(regs, &tb_ptr);
220
+ z_mask = deposit64(arg_info(op->args[1])->z_mask,
200
- t2 = tci_read_r64(regs, &tb_ptr);
221
+ op->args[3], op->args[4],
201
+ t1 = tci_read_r(regs, &tb_ptr);
222
+ arg_info(op->args[2])->z_mask);
202
+ t2 = tci_read_r(regs, &tb_ptr);
223
break;
203
tmp16 = *tb_ptr++;
224
204
tmp8 = *tb_ptr++;
225
CASE_OP_32_64(extract):
205
tmp64 = (((1ULL << tmp8) - 1) << tmp16);
226
- mask = extract64(arg_info(op->args[1])->mask,
206
@@ -XXX,XX +XXX,XX @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
227
- op->args[2], op->args[3]);
207
break;
228
+ z_mask = extract64(arg_info(op->args[1])->z_mask,
208
#endif
229
+ op->args[2], op->args[3]);
209
case INDEX_op_brcond_i64:
230
if (op->args[2] == 0) {
210
- t0 = tci_read_r64(regs, &tb_ptr);
231
- affected = arg_info(op->args[1])->mask & ~mask;
211
- t1 = tci_read_r64(regs, &tb_ptr);
232
+ affected = arg_info(op->args[1])->z_mask & ~z_mask;
212
+ t0 = tci_read_r(regs, &tb_ptr);
233
}
213
+ t1 = tci_read_r(regs, &tb_ptr);
234
break;
214
condition = *tb_ptr++;
235
CASE_OP_32_64(sextract):
215
label = tci_read_label(&tb_ptr);
236
- mask = sextract64(arg_info(op->args[1])->mask,
216
if (tci_compare64(t0, t1, condition)) {
237
- op->args[2], op->args[3]);
217
@@ -XXX,XX +XXX,XX @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
238
- if (op->args[2] == 0 && (tcg_target_long)mask >= 0) {
218
#if TCG_TARGET_HAS_bswap64_i64
239
- affected = arg_info(op->args[1])->mask & ~mask;
219
case INDEX_op_bswap64_i64:
240
+ z_mask = sextract64(arg_info(op->args[1])->z_mask,
220
t0 = *tb_ptr++;
241
+ op->args[2], op->args[3]);
221
- t1 = tci_read_r64(regs, &tb_ptr);
242
+ if (op->args[2] == 0 && (tcg_target_long)z_mask >= 0) {
222
+ t1 = tci_read_r(regs, &tb_ptr);
243
+ affected = arg_info(op->args[1])->z_mask & ~z_mask;
223
tci_write_reg(regs, t0, bswap64(t1));
244
}
224
break;
245
break;
225
#endif
246
226
#if TCG_TARGET_HAS_not_i64
247
CASE_OP_32_64(or):
227
case INDEX_op_not_i64:
248
CASE_OP_32_64(xor):
228
t0 = *tb_ptr++;
249
- mask = arg_info(op->args[1])->mask | arg_info(op->args[2])->mask;
229
- t1 = tci_read_r64(regs, &tb_ptr);
250
+ z_mask = arg_info(op->args[1])->z_mask
230
+ t1 = tci_read_r(regs, &tb_ptr);
251
+ | arg_info(op->args[2])->z_mask;
231
tci_write_reg(regs, t0, ~t1);
252
break;
232
break;
253
233
#endif
254
case INDEX_op_clz_i32:
234
#if TCG_TARGET_HAS_neg_i64
255
case INDEX_op_ctz_i32:
235
case INDEX_op_neg_i64:
256
- mask = arg_info(op->args[2])->mask | 31;
236
t0 = *tb_ptr++;
257
+ z_mask = arg_info(op->args[2])->z_mask | 31;
237
- t1 = tci_read_r64(regs, &tb_ptr);
258
break;
238
+ t1 = tci_read_r(regs, &tb_ptr);
259
239
tci_write_reg(regs, t0, -t1);
260
case INDEX_op_clz_i64:
240
break;
261
case INDEX_op_ctz_i64:
241
#endif
262
- mask = arg_info(op->args[2])->mask | 63;
263
+ z_mask = arg_info(op->args[2])->z_mask | 63;
264
break;
265
266
case INDEX_op_ctpop_i32:
267
- mask = 32 | 31;
268
+ z_mask = 32 | 31;
269
break;
270
case INDEX_op_ctpop_i64:
271
- mask = 64 | 63;
272
+ z_mask = 64 | 63;
273
break;
274
275
CASE_OP_32_64(setcond):
276
case INDEX_op_setcond2_i32:
277
- mask = 1;
278
+ z_mask = 1;
279
break;
280
281
CASE_OP_32_64(movcond):
282
- mask = arg_info(op->args[3])->mask | arg_info(op->args[4])->mask;
283
+ z_mask = arg_info(op->args[3])->z_mask
284
+ | arg_info(op->args[4])->z_mask;
285
break;
286
287
CASE_OP_32_64(ld8u):
288
- mask = 0xff;
289
+ z_mask = 0xff;
290
break;
291
CASE_OP_32_64(ld16u):
292
- mask = 0xffff;
293
+ z_mask = 0xffff;
294
break;
295
case INDEX_op_ld32u_i64:
296
- mask = 0xffffffffu;
297
+ z_mask = 0xffffffffu;
298
break;
299
300
CASE_OP_32_64(qemu_ld):
301
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
302
MemOpIdx oi = op->args[nb_oargs + nb_iargs];
303
MemOp mop = get_memop(oi);
304
if (!(mop & MO_SIGN)) {
305
- mask = (2ULL << ((8 << (mop & MO_SIZE)) - 1)) - 1;
306
+ z_mask = (2ULL << ((8 << (mop & MO_SIZE)) - 1)) - 1;
307
}
308
}
309
break;
310
311
CASE_OP_32_64(bswap16):
312
- mask = arg_info(op->args[1])->mask;
313
- if (mask <= 0xffff) {
314
+ z_mask = arg_info(op->args[1])->z_mask;
315
+ if (z_mask <= 0xffff) {
316
op->args[2] |= TCG_BSWAP_IZ;
317
}
318
- mask = bswap16(mask);
319
+ z_mask = bswap16(z_mask);
320
switch (op->args[2] & (TCG_BSWAP_OZ | TCG_BSWAP_OS)) {
321
case TCG_BSWAP_OZ:
322
break;
323
case TCG_BSWAP_OS:
324
- mask = (int16_t)mask;
325
+ z_mask = (int16_t)z_mask;
326
break;
327
default: /* undefined high bits */
328
- mask |= MAKE_64BIT_MASK(16, 48);
329
+ z_mask |= MAKE_64BIT_MASK(16, 48);
330
break;
331
}
332
break;
333
334
case INDEX_op_bswap32_i64:
335
- mask = arg_info(op->args[1])->mask;
336
- if (mask <= 0xffffffffu) {
337
+ z_mask = arg_info(op->args[1])->z_mask;
338
+ if (z_mask <= 0xffffffffu) {
339
op->args[2] |= TCG_BSWAP_IZ;
340
}
341
- mask = bswap32(mask);
342
+ z_mask = bswap32(z_mask);
343
switch (op->args[2] & (TCG_BSWAP_OZ | TCG_BSWAP_OS)) {
344
case TCG_BSWAP_OZ:
345
break;
346
case TCG_BSWAP_OS:
347
- mask = (int32_t)mask;
348
+ z_mask = (int32_t)z_mask;
349
break;
350
default: /* undefined high bits */
351
- mask |= MAKE_64BIT_MASK(32, 32);
352
+ z_mask |= MAKE_64BIT_MASK(32, 32);
353
break;
354
}
355
break;
356
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
357
/* 32-bit ops generate 32-bit results. For the result is zero test
358
below, we can ignore high bits, but for further optimizations we
359
need to record that the high bits contain garbage. */
360
- partmask = mask;
361
+ partmask = z_mask;
362
if (!(def->flags & TCG_OPF_64BIT)) {
363
- mask |= ~(tcg_target_ulong)0xffffffffu;
364
+ z_mask |= ~(tcg_target_ulong)0xffffffffu;
365
partmask &= 0xffffffffu;
366
affected &= 0xffffffffu;
367
}
368
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
369
vs the high word of the input. */
370
do_setcond_high:
371
reset_temp(op->args[0]);
372
- arg_info(op->args[0])->mask = 1;
373
+ arg_info(op->args[0])->z_mask = 1;
374
op->opc = INDEX_op_setcond_i32;
375
op->args[1] = op->args[2];
376
op->args[2] = op->args[4];
377
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
378
}
379
do_setcond_low:
380
reset_temp(op->args[0]);
381
- arg_info(op->args[0])->mask = 1;
382
+ arg_info(op->args[0])->z_mask = 1;
383
op->opc = INDEX_op_setcond_i32;
384
op->args[2] = op->args[3];
385
op->args[3] = op->args[5];
386
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
387
/* Default case: we know nothing about operation (or were unable
388
to compute the operation result) so no propagation is done.
389
We trash everything if the operation is the end of a basic
390
- block, otherwise we only trash the output args. "mask" is
391
+ block, otherwise we only trash the output args. "z_mask" is
392
the non-zero bits mask for the first output arg. */
393
if (def->flags & TCG_OPF_BB_END) {
394
memset(&temps_used, 0, sizeof(temps_used));
395
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
396
/* Save the corresponding known-zero bits mask for the
397
first output argument (only one supported so far). */
398
if (i == 0) {
399
- arg_info(op->args[i])->mask = mask;
400
+ arg_info(op->args[i])->z_mask = z_mask;
401
}
402
}
403
}
242
--
404
--
243
2.25.1
405
2.25.1
244
406
245
407
diff view generated by jsdifflib
New patch
[PULL 07/56] tcg/optimize: Split out OptContext
1
Provide what will become a larger context for splitting
2
the very large tcg_optimize function.
1
3
4
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
5
Reviewed-by: Luis Pires <luis.pires@eldorado.org.br>
6
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
---
9
tcg/optimize.c | 77 ++++++++++++++++++++++++++------------------------
10
1 file changed, 40 insertions(+), 37 deletions(-)
11
12
diff --git a/tcg/optimize.c b/tcg/optimize.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/tcg/optimize.c
15
+++ b/tcg/optimize.c
16
@@ -XXX,XX +XXX,XX @@ typedef struct TempOptInfo {
17
uint64_t z_mask; /* mask bit is 0 if and only if value bit is 0 */
18
} TempOptInfo;
19
20
+typedef struct OptContext {
21
+ TCGTempSet temps_used;
22
+} OptContext;
23
+
24
static inline TempOptInfo *ts_info(TCGTemp *ts)
25
{
26
return ts->state_ptr;
27
@@ -XXX,XX +XXX,XX @@ static void reset_temp(TCGArg arg)
28
}
29
30
/* Initialize and activate a temporary. */
31
-static void init_ts_info(TCGTempSet *temps_used, TCGTemp *ts)
32
+static void init_ts_info(OptContext *ctx, TCGTemp *ts)
33
{
34
size_t idx = temp_idx(ts);
35
TempOptInfo *ti;
36
37
- if (test_bit(idx, temps_used->l)) {
38
+ if (test_bit(idx, ctx->temps_used.l)) {
39
return;
40
}
41
- set_bit(idx, temps_used->l);
42
+ set_bit(idx, ctx->temps_used.l);
43
44
ti = ts->state_ptr;
45
if (ti == NULL) {
46
@@ -XXX,XX +XXX,XX @@ static void init_ts_info(TCGTempSet *temps_used, TCGTemp *ts)
47
}
48
}
49
50
-static void init_arg_info(TCGTempSet *temps_used, TCGArg arg)
51
+static void init_arg_info(OptContext *ctx, TCGArg arg)
52
{
53
- init_ts_info(temps_used, arg_temp(arg));
54
+ init_ts_info(ctx, arg_temp(arg));
55
}
56
57
static TCGTemp *find_better_copy(TCGContext *s, TCGTemp *ts)
58
@@ -XXX,XX +XXX,XX @@ static void tcg_opt_gen_mov(TCGContext *s, TCGOp *op, TCGArg dst, TCGArg src)
59
}
60
}
61
62
-static void tcg_opt_gen_movi(TCGContext *s, TCGTempSet *temps_used,
63
+static void tcg_opt_gen_movi(TCGContext *s, OptContext *ctx,
64
TCGOp *op, TCGArg dst, uint64_t val)
65
{
66
const TCGOpDef *def = &tcg_op_defs[op->opc];
67
@@ -XXX,XX +XXX,XX @@ static void tcg_opt_gen_movi(TCGContext *s, TCGTempSet *temps_used,
68
69
/* Convert movi to mov with constant temp. */
70
tv = tcg_constant_internal(type, val);
71
- init_ts_info(temps_used, tv);
72
+ init_ts_info(ctx, tv);
73
tcg_opt_gen_mov(s, op, dst, temp_arg(tv));
74
}
75
76
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
77
{
78
int nb_temps, nb_globals, i;
79
TCGOp *op, *op_next, *prev_mb = NULL;
80
- TCGTempSet temps_used;
81
+ OptContext ctx = {};
82
83
/* Array VALS has an element for each temp.
84
If this temp holds a constant then its value is kept in VALS' element.
85
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
86
nb_temps = s->nb_temps;
87
nb_globals = s->nb_globals;
88
89
- memset(&temps_used, 0, sizeof(temps_used));
90
for (i = 0; i < nb_temps; ++i) {
91
s->temps[i].state_ptr = NULL;
92
}
93
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
94
for (i = 0; i < nb_oargs + nb_iargs; i++) {
95
TCGTemp *ts = arg_temp(op->args[i]);
96
if (ts) {
97
- init_ts_info(&temps_used, ts);
98
+ init_ts_info(&ctx, ts);
99
}
100
}
101
} else {
102
nb_oargs = def->nb_oargs;
103
nb_iargs = def->nb_iargs;
104
for (i = 0; i < nb_oargs + nb_iargs; i++) {
105
- init_arg_info(&temps_used, op->args[i]);
106
+ init_arg_info(&ctx, op->args[i]);
107
}
108
}
109
110
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
111
CASE_OP_32_64(rotr):
112
if (arg_is_const(op->args[1])
113
&& arg_info(op->args[1])->val == 0) {
114
- tcg_opt_gen_movi(s, &temps_used, op, op->args[0], 0);
115
+ tcg_opt_gen_movi(s, &ctx, op, op->args[0], 0);
116
continue;
117
}
118
break;
119
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
120
121
if (partmask == 0) {
122
tcg_debug_assert(nb_oargs == 1);
123
- tcg_opt_gen_movi(s, &temps_used, op, op->args[0], 0);
124
+ tcg_opt_gen_movi(s, &ctx, op, op->args[0], 0);
125
continue;
126
}
127
if (affected == 0) {
128
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
129
CASE_OP_32_64(mulsh):
130
if (arg_is_const(op->args[2])
131
&& arg_info(op->args[2])->val == 0) {
132
- tcg_opt_gen_movi(s, &temps_used, op, op->args[0], 0);
133
+ tcg_opt_gen_movi(s, &ctx, op, op->args[0], 0);
134
continue;
135
}
136
break;
137
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
138
CASE_OP_32_64_VEC(sub):
139
CASE_OP_32_64_VEC(xor):
140
if (args_are_copies(op->args[1], op->args[2])) {
141
- tcg_opt_gen_movi(s, &temps_used, op, op->args[0], 0);
142
+ tcg_opt_gen_movi(s, &ctx, op, op->args[0], 0);
143
continue;
144
}
145
break;
146
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
147
if (arg_is_const(op->args[1])) {
148
tmp = arg_info(op->args[1])->val;
149
tmp = dup_const(TCGOP_VECE(op), tmp);
150
- tcg_opt_gen_movi(s, &temps_used, op, op->args[0], tmp);
151
+ tcg_opt_gen_movi(s, &ctx, op, op->args[0], tmp);
152
break;
153
}
154
goto do_default;
155
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
156
case INDEX_op_dup2_vec:
157
assert(TCG_TARGET_REG_BITS == 32);
158
if (arg_is_const(op->args[1]) && arg_is_const(op->args[2])) {
159
- tcg_opt_gen_movi(s, &temps_used, op, op->args[0],
160
+ tcg_opt_gen_movi(s, &ctx, op, op->args[0],
161
deposit64(arg_info(op->args[1])->val, 32, 32,
162
arg_info(op->args[2])->val));
163
break;
164
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
165
case INDEX_op_extrh_i64_i32:
166
if (arg_is_const(op->args[1])) {
167
tmp = do_constant_folding(opc, arg_info(op->args[1])->val, 0);
168
- tcg_opt_gen_movi(s, &temps_used, op, op->args[0], tmp);
169
+ tcg_opt_gen_movi(s, &ctx, op, op->args[0], tmp);
170
break;
171
}
172
goto do_default;
173
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
174
if (arg_is_const(op->args[1])) {
175
tmp = do_constant_folding(opc, arg_info(op->args[1])->val,
176
op->args[2]);
177
- tcg_opt_gen_movi(s, &temps_used, op, op->args[0], tmp);
178
+ tcg_opt_gen_movi(s, &ctx, op, op->args[0], tmp);
179
break;
180
}
181
goto do_default;
182
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
183
if (arg_is_const(op->args[1]) && arg_is_const(op->args[2])) {
184
tmp = do_constant_folding(opc, arg_info(op->args[1])->val,
185
arg_info(op->args[2])->val);
186
- tcg_opt_gen_movi(s, &temps_used, op, op->args[0], tmp);
187
+ tcg_opt_gen_movi(s, &ctx, op, op->args[0], tmp);
188
break;
189
}
190
goto do_default;
191
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
192
TCGArg v = arg_info(op->args[1])->val;
193
if (v != 0) {
194
tmp = do_constant_folding(opc, v, 0);
195
- tcg_opt_gen_movi(s, &temps_used, op, op->args[0], tmp);
196
+ tcg_opt_gen_movi(s, &ctx, op, op->args[0], tmp);
197
} else {
198
tcg_opt_gen_mov(s, op, op->args[0], op->args[2]);
199
}
200
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
201
tmp = deposit64(arg_info(op->args[1])->val,
202
op->args[3], op->args[4],
203
arg_info(op->args[2])->val);
204
- tcg_opt_gen_movi(s, &temps_used, op, op->args[0], tmp);
205
+ tcg_opt_gen_movi(s, &ctx, op, op->args[0], tmp);
206
break;
207
}
208
goto do_default;
209
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
210
if (arg_is_const(op->args[1])) {
211
tmp = extract64(arg_info(op->args[1])->val,
212
op->args[2], op->args[3]);
213
- tcg_opt_gen_movi(s, &temps_used, op, op->args[0], tmp);
214
+ tcg_opt_gen_movi(s, &ctx, op, op->args[0], tmp);
215
break;
216
}
217
goto do_default;
218
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
219
if (arg_is_const(op->args[1])) {
220
tmp = sextract64(arg_info(op->args[1])->val,
221
op->args[2], op->args[3]);
222
- tcg_opt_gen_movi(s, &temps_used, op, op->args[0], tmp);
223
+ tcg_opt_gen_movi(s, &ctx, op, op->args[0], tmp);
224
break;
225
}
226
goto do_default;
227
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
228
tmp = (int32_t)(((uint32_t)v1 >> shr) |
229
((uint32_t)v2 << (32 - shr)));
230
}
231
- tcg_opt_gen_movi(s, &temps_used, op, op->args[0], tmp);
232
+ tcg_opt_gen_movi(s, &ctx, op, op->args[0], tmp);
233
break;
234
}
235
goto do_default;
236
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
237
tmp = do_constant_folding_cond(opc, op->args[1],
238
op->args[2], op->args[3]);
239
if (tmp != 2) {
240
- tcg_opt_gen_movi(s, &temps_used, op, op->args[0], tmp);
241
+ tcg_opt_gen_movi(s, &ctx, op, op->args[0], tmp);
242
break;
243
}
244
goto do_default;
245
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
246
op->args[1], op->args[2]);
247
if (tmp != 2) {
248
if (tmp) {
249
- memset(&temps_used, 0, sizeof(temps_used));
250
+ memset(&ctx.temps_used, 0, sizeof(ctx.temps_used));
251
op->opc = INDEX_op_br;
252
op->args[0] = op->args[3];
253
} else {
254
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
255
256
rl = op->args[0];
257
rh = op->args[1];
258
- tcg_opt_gen_movi(s, &temps_used, op, rl, (int32_t)a);
259
- tcg_opt_gen_movi(s, &temps_used, op2, rh, (int32_t)(a >> 32));
260
+ tcg_opt_gen_movi(s, &ctx, op, rl, (int32_t)a);
261
+ tcg_opt_gen_movi(s, &ctx, op2, rh, (int32_t)(a >> 32));
262
break;
263
}
264
goto do_default;
265
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
266
267
rl = op->args[0];
268
rh = op->args[1];
269
- tcg_opt_gen_movi(s, &temps_used, op, rl, (int32_t)r);
270
- tcg_opt_gen_movi(s, &temps_used, op2, rh, (int32_t)(r >> 32));
271
+ tcg_opt_gen_movi(s, &ctx, op, rl, (int32_t)r);
272
+ tcg_opt_gen_movi(s, &ctx, op2, rh, (int32_t)(r >> 32));
273
break;
274
}
275
goto do_default;
276
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
277
if (tmp != 2) {
278
if (tmp) {
279
do_brcond_true:
280
- memset(&temps_used, 0, sizeof(temps_used));
281
+ memset(&ctx.temps_used, 0, sizeof(ctx.temps_used));
282
op->opc = INDEX_op_br;
283
op->args[0] = op->args[5];
284
} else {
285
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
286
/* Simplify LT/GE comparisons vs zero to a single compare
287
vs the high word of the input. */
288
do_brcond_high:
289
- memset(&temps_used, 0, sizeof(temps_used));
290
+ memset(&ctx.temps_used, 0, sizeof(ctx.temps_used));
291
op->opc = INDEX_op_brcond_i32;
292
op->args[0] = op->args[1];
293
op->args[1] = op->args[3];
294
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
295
goto do_default;
296
}
297
do_brcond_low:
298
- memset(&temps_used, 0, sizeof(temps_used));
299
+ memset(&ctx.temps_used, 0, sizeof(ctx.temps_used));
300
op->opc = INDEX_op_brcond_i32;
301
op->args[1] = op->args[2];
302
op->args[2] = op->args[4];
303
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
304
op->args[5]);
305
if (tmp != 2) {
306
do_setcond_const:
307
- tcg_opt_gen_movi(s, &temps_used, op, op->args[0], tmp);
308
+ tcg_opt_gen_movi(s, &ctx, op, op->args[0], tmp);
309
} else if ((op->args[5] == TCG_COND_LT
310
|| op->args[5] == TCG_COND_GE)
311
&& arg_is_const(op->args[3])
312
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
313
if (!(tcg_call_flags(op)
314
& (TCG_CALL_NO_READ_GLOBALS | TCG_CALL_NO_WRITE_GLOBALS))) {
315
for (i = 0; i < nb_globals; i++) {
316
- if (test_bit(i, temps_used.l)) {
317
+ if (test_bit(i, ctx.temps_used.l)) {
318
reset_ts(&s->temps[i]);
319
}
320
}
321
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
322
block, otherwise we only trash the output args. "z_mask" is
323
the non-zero bits mask for the first output arg. */
324
if (def->flags & TCG_OPF_BB_END) {
325
- memset(&temps_used, 0, sizeof(temps_used));
326
+ memset(&ctx.temps_used, 0, sizeof(ctx.temps_used));
327
} else {
328
do_reset_output:
329
for (i = 0; i < nb_oargs; i++) {
330
--
331
2.25.1
332
333
diff view generated by jsdifflib
New patch
[PULL 08/56] tcg/optimize: Remove do_default label
1
Break the final cleanup clause out of the main switch
2
statement. When fully folding an opcode to mov/movi,
3
use "continue" to process the next opcode, else break
4
to fall into the final cleanup.
1
5
6
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
7
Reviewed-by: Luis Pires <luis.pires@eldorado.org.br>
8
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
---
11
tcg/optimize.c | 190 ++++++++++++++++++++++++-------------------------
12
1 file changed, 94 insertions(+), 96 deletions(-)
13
14
diff --git a/tcg/optimize.c b/tcg/optimize.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/tcg/optimize.c
17
+++ b/tcg/optimize.c
18
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
19
switch (opc) {
20
CASE_OP_32_64_VEC(mov):
21
tcg_opt_gen_mov(s, op, op->args[0], op->args[1]);
22
- break;
23
+ continue;
24
25
case INDEX_op_dup_vec:
26
if (arg_is_const(op->args[1])) {
27
tmp = arg_info(op->args[1])->val;
28
tmp = dup_const(TCGOP_VECE(op), tmp);
29
tcg_opt_gen_movi(s, &ctx, op, op->args[0], tmp);
30
- break;
31
+ continue;
32
}
33
- goto do_default;
34
+ break;
35
36
case INDEX_op_dup2_vec:
37
assert(TCG_TARGET_REG_BITS == 32);
38
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
39
tcg_opt_gen_movi(s, &ctx, op, op->args[0],
40
deposit64(arg_info(op->args[1])->val, 32, 32,
41
arg_info(op->args[2])->val));
42
- break;
43
+ continue;
44
} else if (args_are_copies(op->args[1], op->args[2])) {
45
op->opc = INDEX_op_dup_vec;
46
TCGOP_VECE(op) = MO_32;
47
nb_iargs = 1;
48
}
49
- goto do_default;
50
+ break;
51
52
CASE_OP_32_64(not):
53
CASE_OP_32_64(neg):
54
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
55
if (arg_is_const(op->args[1])) {
56
tmp = do_constant_folding(opc, arg_info(op->args[1])->val, 0);
57
tcg_opt_gen_movi(s, &ctx, op, op->args[0], tmp);
58
- break;
59
+ continue;
60
}
61
- goto do_default;
62
+ break;
63
64
CASE_OP_32_64(bswap16):
65
CASE_OP_32_64(bswap32):
66
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
67
tmp = do_constant_folding(opc, arg_info(op->args[1])->val,
68
op->args[2]);
69
tcg_opt_gen_movi(s, &ctx, op, op->args[0], tmp);
70
- break;
71
+ continue;
72
}
73
- goto do_default;
74
+ break;
75
76
CASE_OP_32_64(add):
77
CASE_OP_32_64(sub):
78
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
79
tmp = do_constant_folding(opc, arg_info(op->args[1])->val,
80
arg_info(op->args[2])->val);
81
tcg_opt_gen_movi(s, &ctx, op, op->args[0], tmp);
82
- break;
83
+ continue;
84
}
85
- goto do_default;
86
+ break;
87
88
CASE_OP_32_64(clz):
89
CASE_OP_32_64(ctz):
90
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
91
} else {
92
tcg_opt_gen_mov(s, op, op->args[0], op->args[2]);
93
}
94
- break;
95
+ continue;
96
}
97
- goto do_default;
98
+ break;
99
100
CASE_OP_32_64(deposit):
101
if (arg_is_const(op->args[1]) && arg_is_const(op->args[2])) {
102
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
103
op->args[3], op->args[4],
104
arg_info(op->args[2])->val);
105
tcg_opt_gen_movi(s, &ctx, op, op->args[0], tmp);
106
- break;
107
+ continue;
108
}
109
- goto do_default;
110
+ break;
111
112
CASE_OP_32_64(extract):
113
if (arg_is_const(op->args[1])) {
114
tmp = extract64(arg_info(op->args[1])->val,
115
op->args[2], op->args[3]);
116
tcg_opt_gen_movi(s, &ctx, op, op->args[0], tmp);
117
- break;
118
+ continue;
119
}
120
- goto do_default;
121
+ break;
122
123
CASE_OP_32_64(sextract):
124
if (arg_is_const(op->args[1])) {
125
tmp = sextract64(arg_info(op->args[1])->val,
126
op->args[2], op->args[3]);
127
tcg_opt_gen_movi(s, &ctx, op, op->args[0], tmp);
128
- break;
129
+ continue;
130
}
131
- goto do_default;
132
+ break;
133
134
CASE_OP_32_64(extract2):
135
if (arg_is_const(op->args[1]) && arg_is_const(op->args[2])) {
136
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
137
((uint32_t)v2 << (32 - shr)));
138
}
139
tcg_opt_gen_movi(s, &ctx, op, op->args[0], tmp);
140
- break;
141
+ continue;
142
}
143
- goto do_default;
144
+ break;
145
146
CASE_OP_32_64(setcond):
147
tmp = do_constant_folding_cond(opc, op->args[1],
148
op->args[2], op->args[3]);
149
if (tmp != 2) {
150
tcg_opt_gen_movi(s, &ctx, op, op->args[0], tmp);
151
- break;
152
+ continue;
153
}
154
- goto do_default;
155
+ break;
156
157
CASE_OP_32_64(brcond):
158
tmp = do_constant_folding_cond(opc, op->args[0],
159
op->args[1], op->args[2]);
160
- if (tmp != 2) {
161
- if (tmp) {
162
- memset(&ctx.temps_used, 0, sizeof(ctx.temps_used));
163
- op->opc = INDEX_op_br;
164
- op->args[0] = op->args[3];
165
- } else {
166
- tcg_op_remove(s, op);
167
- }
168
+ switch (tmp) {
169
+ case 0:
170
+ tcg_op_remove(s, op);
171
+ continue;
172
+ case 1:
173
+ memset(&ctx.temps_used, 0, sizeof(ctx.temps_used));
174
+ op->opc = opc = INDEX_op_br;
175
+ op->args[0] = op->args[3];
176
break;
177
}
178
- goto do_default;
179
+ break;
180
181
CASE_OP_32_64(movcond):
182
tmp = do_constant_folding_cond(opc, op->args[1],
183
op->args[2], op->args[5]);
184
if (tmp != 2) {
185
tcg_opt_gen_mov(s, op, op->args[0], op->args[4-tmp]);
186
- break;
187
+ continue;
188
}
189
if (arg_is_const(op->args[3]) && arg_is_const(op->args[4])) {
190
uint64_t tv = arg_info(op->args[3])->val;
191
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
192
if (fv == 1 && tv == 0) {
193
cond = tcg_invert_cond(cond);
194
} else if (!(tv == 1 && fv == 0)) {
195
- goto do_default;
196
+ break;
197
}
198
op->args[3] = cond;
199
op->opc = opc = (opc == INDEX_op_movcond_i32
200
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
201
: INDEX_op_setcond_i64);
202
nb_iargs = 2;
203
}
204
- goto do_default;
205
+ break;
206
207
case INDEX_op_add2_i32:
208
case INDEX_op_sub2_i32:
209
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
210
rh = op->args[1];
211
tcg_opt_gen_movi(s, &ctx, op, rl, (int32_t)a);
212
tcg_opt_gen_movi(s, &ctx, op2, rh, (int32_t)(a >> 32));
213
- break;
214
+ continue;
215
}
216
- goto do_default;
217
+ break;
218
219
case INDEX_op_mulu2_i32:
220
if (arg_is_const(op->args[2]) && arg_is_const(op->args[3])) {
221
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
222
rh = op->args[1];
223
tcg_opt_gen_movi(s, &ctx, op, rl, (int32_t)r);
224
tcg_opt_gen_movi(s, &ctx, op2, rh, (int32_t)(r >> 32));
225
- break;
226
+ continue;
227
}
228
- goto do_default;
229
+ break;
230
231
case INDEX_op_brcond2_i32:
232
tmp = do_constant_folding_cond2(&op->args[0], &op->args[2],
233
op->args[4]);
234
- if (tmp != 2) {
235
- if (tmp) {
236
- do_brcond_true:
237
- memset(&ctx.temps_used, 0, sizeof(ctx.temps_used));
238
- op->opc = INDEX_op_br;
239
- op->args[0] = op->args[5];
240
- } else {
241
+ if (tmp == 0) {
242
do_brcond_false:
243
- tcg_op_remove(s, op);
244
- }
245
- } else if ((op->args[4] == TCG_COND_LT
246
- || op->args[4] == TCG_COND_GE)
247
- && arg_is_const(op->args[2])
248
- && arg_info(op->args[2])->val == 0
249
- && arg_is_const(op->args[3])
250
- && arg_info(op->args[3])->val == 0) {
251
+ tcg_op_remove(s, op);
252
+ continue;
253
+ }
254
+ if (tmp == 1) {
255
+ do_brcond_true:
256
+ op->opc = opc = INDEX_op_br;
257
+ op->args[0] = op->args[5];
258
+ break;
259
+ }
260
+ if ((op->args[4] == TCG_COND_LT || op->args[4] == TCG_COND_GE)
261
+ && arg_is_const(op->args[2])
262
+ && arg_info(op->args[2])->val == 0
263
+ && arg_is_const(op->args[3])
264
+ && arg_info(op->args[3])->val == 0) {
265
/* Simplify LT/GE comparisons vs zero to a single compare
266
vs the high word of the input. */
267
do_brcond_high:
268
- memset(&ctx.temps_used, 0, sizeof(ctx.temps_used));
269
- op->opc = INDEX_op_brcond_i32;
270
+ op->opc = opc = INDEX_op_brcond_i32;
271
op->args[0] = op->args[1];
272
op->args[1] = op->args[3];
273
op->args[2] = op->args[4];
274
op->args[3] = op->args[5];
275
- } else if (op->args[4] == TCG_COND_EQ) {
276
+ break;
277
+ }
278
+ if (op->args[4] == TCG_COND_EQ) {
279
/* Simplify EQ comparisons where one of the pairs
280
can be simplified. */
281
tmp = do_constant_folding_cond(INDEX_op_brcond_i32,
282
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
283
if (tmp == 0) {
284
goto do_brcond_false;
285
} else if (tmp != 1) {
286
- goto do_default;
287
+ break;
288
}
289
do_brcond_low:
290
memset(&ctx.temps_used, 0, sizeof(ctx.temps_used));
291
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
292
op->args[1] = op->args[2];
293
op->args[2] = op->args[4];
294
op->args[3] = op->args[5];
295
- } else if (op->args[4] == TCG_COND_NE) {
296
+ break;
297
+ }
298
+ if (op->args[4] == TCG_COND_NE) {
299
/* Simplify NE comparisons where one of the pairs
300
can be simplified. */
301
tmp = do_constant_folding_cond(INDEX_op_brcond_i32,
302
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
303
} else if (tmp == 1) {
304
goto do_brcond_true;
305
}
306
- goto do_default;
307
- } else {
308
- goto do_default;
309
}
310
break;
311
312
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
313
if (tmp != 2) {
314
do_setcond_const:
315
tcg_opt_gen_movi(s, &ctx, op, op->args[0], tmp);
316
- } else if ((op->args[5] == TCG_COND_LT
317
- || op->args[5] == TCG_COND_GE)
318
- && arg_is_const(op->args[3])
319
- && arg_info(op->args[3])->val == 0
320
- && arg_is_const(op->args[4])
321
- && arg_info(op->args[4])->val == 0) {
322
+ continue;
323
+ }
324
+ if ((op->args[5] == TCG_COND_LT || op->args[5] == TCG_COND_GE)
325
+ && arg_is_const(op->args[3])
326
+ && arg_info(op->args[3])->val == 0
327
+ && arg_is_const(op->args[4])
328
+ && arg_info(op->args[4])->val == 0) {
329
/* Simplify LT/GE comparisons vs zero to a single compare
330
vs the high word of the input. */
331
do_setcond_high:
332
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
333
op->args[1] = op->args[2];
334
op->args[2] = op->args[4];
335
op->args[3] = op->args[5];
336
- } else if (op->args[5] == TCG_COND_EQ) {
337
+ break;
338
+ }
339
+ if (op->args[5] == TCG_COND_EQ) {
340
/* Simplify EQ comparisons where one of the pairs
341
can be simplified. */
342
tmp = do_constant_folding_cond(INDEX_op_setcond_i32,
343
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
344
if (tmp == 0) {
345
goto do_setcond_high;
346
} else if (tmp != 1) {
347
- goto do_default;
348
+ break;
349
}
350
do_setcond_low:
351
reset_temp(op->args[0]);
352
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
353
op->opc = INDEX_op_setcond_i32;
354
op->args[2] = op->args[3];
355
op->args[3] = op->args[5];
356
- } else if (op->args[5] == TCG_COND_NE) {
357
+ break;
358
+ }
359
+ if (op->args[5] == TCG_COND_NE) {
360
/* Simplify NE comparisons where one of the pairs
361
can be simplified. */
362
tmp = do_constant_folding_cond(INDEX_op_setcond_i32,
363
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
364
} else if (tmp == 1) {
365
goto do_setcond_const;
366
}
367
- goto do_default;
368
- } else {
369
- goto do_default;
370
}
371
break;
372
373
- case INDEX_op_call:
374
- if (!(tcg_call_flags(op)
375
+ default:
376
+ break;
377
+ }
378
+
379
+ /* Some of the folding above can change opc. */
380
+ opc = op->opc;
381
+ def = &tcg_op_defs[opc];
382
+ if (def->flags & TCG_OPF_BB_END) {
383
+ memset(&ctx.temps_used, 0, sizeof(ctx.temps_used));
384
+ } else {
385
+ if (opc == INDEX_op_call &&
386
+ !(tcg_call_flags(op)
387
& (TCG_CALL_NO_READ_GLOBALS | TCG_CALL_NO_WRITE_GLOBALS))) {
388
for (i = 0; i < nb_globals; i++) {
389
if (test_bit(i, ctx.temps_used.l)) {
390
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
391
}
392
}
393
}
394
- goto do_reset_output;
395
396
- default:
397
- do_default:
398
- /* Default case: we know nothing about operation (or were unable
399
- to compute the operation result) so no propagation is done.
400
- We trash everything if the operation is the end of a basic
401
- block, otherwise we only trash the output args. "z_mask" is
402
- the non-zero bits mask for the first output arg. */
403
- if (def->flags & TCG_OPF_BB_END) {
404
- memset(&ctx.temps_used, 0, sizeof(ctx.temps_used));
405
- } else {
406
- do_reset_output:
407
- for (i = 0; i < nb_oargs; i++) {
408
- reset_temp(op->args[i]);
409
- /* Save the corresponding known-zero bits mask for the
410
- first output argument (only one supported so far). */
411
- if (i == 0) {
412
- arg_info(op->args[i])->z_mask = z_mask;
413
- }
414
+ for (i = 0; i < nb_oargs; i++) {
415
+ reset_temp(op->args[i]);
416
+ /* Save the corresponding known-zero bits mask for the
417
+ first output argument (only one supported so far). */
418
+ if (i == 0) {
419
+ arg_info(op->args[i])->z_mask = z_mask;
420
}
421
}
422
- break;
423
}
424
425
/* Eliminate duplicate and redundant fence instructions. */
426
--
427
2.25.1
428
429
diff view generated by jsdifflib
New patch
[PULL 09/56] tcg/optimize: Change tcg_opt_gen_{mov,movi} interface
1
1
Adjust the interface to take the OptContext parameter instead
2
of TCGContext or both.
3
4
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
5
Reviewed-by: Luis Pires <luis.pires@eldorado.org.br>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
---
8
tcg/optimize.c | 67 +++++++++++++++++++++++++-------------------------
9
1 file changed, 34 insertions(+), 33 deletions(-)
10
11
diff --git a/tcg/optimize.c b/tcg/optimize.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/tcg/optimize.c
14
+++ b/tcg/optimize.c
15
@@ -XXX,XX +XXX,XX @@ typedef struct TempOptInfo {
16
} TempOptInfo;
17
18
typedef struct OptContext {
19
+ TCGContext *tcg;
20
TCGTempSet temps_used;
21
} OptContext;
22
23
@@ -XXX,XX +XXX,XX @@ static bool args_are_copies(TCGArg arg1, TCGArg arg2)
24
return ts_are_copies(arg_temp(arg1), arg_temp(arg2));
25
}
26
27
-static void tcg_opt_gen_mov(TCGContext *s, TCGOp *op, TCGArg dst, TCGArg src)
28
+static void tcg_opt_gen_mov(OptContext *ctx, TCGOp *op, TCGArg dst, TCGArg src)
29
{
30
TCGTemp *dst_ts = arg_temp(dst);
31
TCGTemp *src_ts = arg_temp(src);
32
@@ -XXX,XX +XXX,XX @@ static void tcg_opt_gen_mov(TCGContext *s, TCGOp *op, TCGArg dst, TCGArg src)
33
TCGOpcode new_op;
34
35
if (ts_are_copies(dst_ts, src_ts)) {
36
- tcg_op_remove(s, op);
37
+ tcg_op_remove(ctx->tcg, op);
38
return;
39
}
40
41
@@ -XXX,XX +XXX,XX @@ static void tcg_opt_gen_mov(TCGContext *s, TCGOp *op, TCGArg dst, TCGArg src)
42
}
43
}
44
45
-static void tcg_opt_gen_movi(TCGContext *s, OptContext *ctx,
46
- TCGOp *op, TCGArg dst, uint64_t val)
47
+static void tcg_opt_gen_movi(OptContext *ctx, TCGOp *op,
48
+ TCGArg dst, uint64_t val)
49
{
50
const TCGOpDef *def = &tcg_op_defs[op->opc];
51
TCGType type;
52
@@ -XXX,XX +XXX,XX @@ static void tcg_opt_gen_movi(TCGContext *s, OptContext *ctx,
53
/* Convert movi to mov with constant temp. */
54
tv = tcg_constant_internal(type, val);
55
init_ts_info(ctx, tv);
56
- tcg_opt_gen_mov(s, op, dst, temp_arg(tv));
57
+ tcg_opt_gen_mov(ctx, op, dst, temp_arg(tv));
58
}
59
60
static uint64_t do_constant_folding_2(TCGOpcode op, uint64_t x, uint64_t y)
61
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
62
{
63
int nb_temps, nb_globals, i;
64
TCGOp *op, *op_next, *prev_mb = NULL;
65
- OptContext ctx = {};
66
+ OptContext ctx = { .tcg = s };
67
68
/* Array VALS has an element for each temp.
69
If this temp holds a constant then its value is kept in VALS' element.
70
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
71
CASE_OP_32_64(rotr):
72
if (arg_is_const(op->args[1])
73
&& arg_info(op->args[1])->val == 0) {
74
- tcg_opt_gen_movi(s, &ctx, op, op->args[0], 0);
75
+ tcg_opt_gen_movi(&ctx, op, op->args[0], 0);
76
continue;
77
}
78
break;
79
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
80
if (!arg_is_const(op->args[1])
81
&& arg_is_const(op->args[2])
82
&& arg_info(op->args[2])->val == 0) {
83
- tcg_opt_gen_mov(s, op, op->args[0], op->args[1]);
84
+ tcg_opt_gen_mov(&ctx, op, op->args[0], op->args[1]);
85
continue;
86
}
87
break;
88
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
89
if (!arg_is_const(op->args[1])
90
&& arg_is_const(op->args[2])
91
&& arg_info(op->args[2])->val == -1) {
92
- tcg_opt_gen_mov(s, op, op->args[0], op->args[1]);
93
+ tcg_opt_gen_mov(&ctx, op, op->args[0], op->args[1]);
94
continue;
95
}
96
break;
97
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
98
99
if (partmask == 0) {
100
tcg_debug_assert(nb_oargs == 1);
101
- tcg_opt_gen_movi(s, &ctx, op, op->args[0], 0);
102
+ tcg_opt_gen_movi(&ctx, op, op->args[0], 0);
103
continue;
104
}
105
if (affected == 0) {
106
tcg_debug_assert(nb_oargs == 1);
107
- tcg_opt_gen_mov(s, op, op->args[0], op->args[1]);
108
+ tcg_opt_gen_mov(&ctx, op, op->args[0], op->args[1]);
109
continue;
110
}
111
112
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
113
CASE_OP_32_64(mulsh):
114
if (arg_is_const(op->args[2])
115
&& arg_info(op->args[2])->val == 0) {
116
- tcg_opt_gen_movi(s, &ctx, op, op->args[0], 0);
117
+ tcg_opt_gen_movi(&ctx, op, op->args[0], 0);
118
continue;
119
}
120
break;
121
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
122
CASE_OP_32_64_VEC(or):
123
CASE_OP_32_64_VEC(and):
124
if (args_are_copies(op->args[1], op->args[2])) {
125
- tcg_opt_gen_mov(s, op, op->args[0], op->args[1]);
126
+ tcg_opt_gen_mov(&ctx, op, op->args[0], op->args[1]);
127
continue;
128
}
129
break;
130
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
131
CASE_OP_32_64_VEC(sub):
132
CASE_OP_32_64_VEC(xor):
133
if (args_are_copies(op->args[1], op->args[2])) {
134
- tcg_opt_gen_movi(s, &ctx, op, op->args[0], 0);
135
+ tcg_opt_gen_movi(&ctx, op, op->args[0], 0);
136
continue;
137
}
138
break;
139
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
140
allocator where needed and possible. Also detect copies. */
141
switch (opc) {
142
CASE_OP_32_64_VEC(mov):
143
- tcg_opt_gen_mov(s, op, op->args[0], op->args[1]);
144
+ tcg_opt_gen_mov(&ctx, op, op->args[0], op->args[1]);
145
continue;
146
147
case INDEX_op_dup_vec:
148
if (arg_is_const(op->args[1])) {
149
tmp = arg_info(op->args[1])->val;
150
tmp = dup_const(TCGOP_VECE(op), tmp);
151
- tcg_opt_gen_movi(s, &ctx, op, op->args[0], tmp);
152
+ tcg_opt_gen_movi(&ctx, op, op->args[0], tmp);
153
continue;
154
}
155
break;
156
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
157
case INDEX_op_dup2_vec:
158
assert(TCG_TARGET_REG_BITS == 32);
159
if (arg_is_const(op->args[1]) && arg_is_const(op->args[2])) {
160
- tcg_opt_gen_movi(s, &ctx, op, op->args[0],
161
+ tcg_opt_gen_movi(&ctx, op, op->args[0],
162
deposit64(arg_info(op->args[1])->val, 32, 32,
163
arg_info(op->args[2])->val));
164
continue;
165
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
166
case INDEX_op_extrh_i64_i32:
167
if (arg_is_const(op->args[1])) {
168
tmp = do_constant_folding(opc, arg_info(op->args[1])->val, 0);
169
- tcg_opt_gen_movi(s, &ctx, op, op->args[0], tmp);
170
+ tcg_opt_gen_movi(&ctx, op, op->args[0], tmp);
171
continue;
172
}
173
break;
174
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
175
if (arg_is_const(op->args[1])) {
176
tmp = do_constant_folding(opc, arg_info(op->args[1])->val,
177
op->args[2]);
178
- tcg_opt_gen_movi(s, &ctx, op, op->args[0], tmp);
179
+ tcg_opt_gen_movi(&ctx, op, op->args[0], tmp);
180
continue;
181
}
182
break;
183
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
184
if (arg_is_const(op->args[1]) && arg_is_const(op->args[2])) {
185
tmp = do_constant_folding(opc, arg_info(op->args[1])->val,
186
arg_info(op->args[2])->val);
187
- tcg_opt_gen_movi(s, &ctx, op, op->args[0], tmp);
188
+ tcg_opt_gen_movi(&ctx, op, op->args[0], tmp);
189
continue;
190
}
191
break;
192
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
193
TCGArg v = arg_info(op->args[1])->val;
194
if (v != 0) {
195
tmp = do_constant_folding(opc, v, 0);
196
- tcg_opt_gen_movi(s, &ctx, op, op->args[0], tmp);
197
+ tcg_opt_gen_movi(&ctx, op, op->args[0], tmp);
198
} else {
199
- tcg_opt_gen_mov(s, op, op->args[0], op->args[2]);
200
+ tcg_opt_gen_mov(&ctx, op, op->args[0], op->args[2]);
201
}
202
continue;
203
}
204
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
205
tmp = deposit64(arg_info(op->args[1])->val,
206
op->args[3], op->args[4],
207
arg_info(op->args[2])->val);
208
- tcg_opt_gen_movi(s, &ctx, op, op->args[0], tmp);
209
+ tcg_opt_gen_movi(&ctx, op, op->args[0], tmp);
210
continue;
211
}
212
break;
213
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
214
if (arg_is_const(op->args[1])) {
215
tmp = extract64(arg_info(op->args[1])->val,
216
op->args[2], op->args[3]);
217
- tcg_opt_gen_movi(s, &ctx, op, op->args[0], tmp);
218
+ tcg_opt_gen_movi(&ctx, op, op->args[0], tmp);
219
continue;
220
}
221
break;
222
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
223
if (arg_is_const(op->args[1])) {
224
tmp = sextract64(arg_info(op->args[1])->val,
225
op->args[2], op->args[3]);
226
- tcg_opt_gen_movi(s, &ctx, op, op->args[0], tmp);
227
+ tcg_opt_gen_movi(&ctx, op, op->args[0], tmp);
228
continue;
229
}
230
break;
231
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
232
tmp = (int32_t)(((uint32_t)v1 >> shr) |
233
((uint32_t)v2 << (32 - shr)));
234
}
235
- tcg_opt_gen_movi(s, &ctx, op, op->args[0], tmp);
236
+ tcg_opt_gen_movi(&ctx, op, op->args[0], tmp);
237
continue;
238
}
239
break;
240
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
241
tmp = do_constant_folding_cond(opc, op->args[1],
242
op->args[2], op->args[3]);
243
if (tmp != 2) {
244
- tcg_opt_gen_movi(s, &ctx, op, op->args[0], tmp);
245
+ tcg_opt_gen_movi(&ctx, op, op->args[0], tmp);
246
continue;
247
}
248
break;
249
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
250
tmp = do_constant_folding_cond(opc, op->args[1],
251
op->args[2], op->args[5]);
252
if (tmp != 2) {
253
- tcg_opt_gen_mov(s, op, op->args[0], op->args[4-tmp]);
254
+ tcg_opt_gen_mov(&ctx, op, op->args[0], op->args[4-tmp]);
255
continue;
256
}
257
if (arg_is_const(op->args[3]) && arg_is_const(op->args[4])) {
258
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
259
260
rl = op->args[0];
261
rh = op->args[1];
262
- tcg_opt_gen_movi(s, &ctx, op, rl, (int32_t)a);
263
- tcg_opt_gen_movi(s, &ctx, op2, rh, (int32_t)(a >> 32));
264
+ tcg_opt_gen_movi(&ctx, op, rl, (int32_t)a);
265
+ tcg_opt_gen_movi(&ctx, op2, rh, (int32_t)(a >> 32));
266
continue;
267
}
268
break;
269
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
270
271
rl = op->args[0];
272
rh = op->args[1];
273
- tcg_opt_gen_movi(s, &ctx, op, rl, (int32_t)r);
274
- tcg_opt_gen_movi(s, &ctx, op2, rh, (int32_t)(r >> 32));
275
+ tcg_opt_gen_movi(&ctx, op, rl, (int32_t)r);
276
+ tcg_opt_gen_movi(&ctx, op2, rh, (int32_t)(r >> 32));
277
continue;
278
}
279
break;
280
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
281
op->args[5]);
282
if (tmp != 2) {
283
do_setcond_const:
284
- tcg_opt_gen_movi(s, &ctx, op, op->args[0], tmp);
285
+ tcg_opt_gen_movi(&ctx, op, op->args[0], tmp);
286
continue;
287
}
288
if ((op->args[5] == TCG_COND_LT || op->args[5] == TCG_COND_GE)
289
--
290
2.25.1
291
292
diff view generated by jsdifflib
New patch
[PULL 10/56] tcg/optimize: Move prev_mb into OptContext
1
This will expose the variable to subroutines that
2
will be broken out of tcg_optimize.
1
3
4
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
5
Reviewed-by: Luis Pires <luis.pires@eldorado.org.br>
6
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
---
9
tcg/optimize.c | 11 ++++++-----
10
1 file changed, 6 insertions(+), 5 deletions(-)
11
12
diff --git a/tcg/optimize.c b/tcg/optimize.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/tcg/optimize.c
15
+++ b/tcg/optimize.c
16
@@ -XXX,XX +XXX,XX @@ typedef struct TempOptInfo {
17
18
typedef struct OptContext {
19
TCGContext *tcg;
20
+ TCGOp *prev_mb;
21
TCGTempSet temps_used;
22
} OptContext;
23
24
@@ -XXX,XX +XXX,XX @@ static bool swap_commutative2(TCGArg *p1, TCGArg *p2)
25
void tcg_optimize(TCGContext *s)
26
{
27
int nb_temps, nb_globals, i;
28
- TCGOp *op, *op_next, *prev_mb = NULL;
29
+ TCGOp *op, *op_next;
30
OptContext ctx = { .tcg = s };
31
32
/* Array VALS has an element for each temp.
33
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
34
}
35
36
/* Eliminate duplicate and redundant fence instructions. */
37
- if (prev_mb) {
38
+ if (ctx.prev_mb) {
39
switch (opc) {
40
case INDEX_op_mb:
41
/* Merge two barriers of the same type into one,
42
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
43
* barrier. This is stricter than specified but for
44
* the purposes of TCG is better than not optimizing.
45
*/
46
- prev_mb->args[0] |= op->args[0];
47
+ ctx.prev_mb->args[0] |= op->args[0];
48
tcg_op_remove(s, op);
49
break;
50
51
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
52
case INDEX_op_qemu_st_i64:
53
case INDEX_op_call:
54
/* Opcodes that touch guest memory stop the optimization. */
55
- prev_mb = NULL;
56
+ ctx.prev_mb = NULL;
57
break;
58
}
59
} else if (opc == INDEX_op_mb) {
60
- prev_mb = op;
61
+ ctx.prev_mb = op;
62
}
63
}
64
}
65
--
66
2.25.1
67
68
diff view generated by jsdifflib
[PATCH 16/27] tcg/tci: Remove tci_read_r32
[PULL 11/56] tcg/optimize: Split out init_arguments
1
Use explicit casts for ext32u opcodes, and allow truncation
1
There was no real reason for calls to have separate code here.
2
to happen for other users.
2
Unify init for calls vs non-calls using the call path, which
3
handles TCG_CALL_DUMMY_ARG.
3
4
5
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
6
Reviewed-by: Luis Pires <luis.pires@eldorado.org.br>
4
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
7
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
---
9
---
7
tcg/tci.c | 122 ++++++++++++++++++++++++------------------------------
10
tcg/optimize.c | 25 +++++++++++--------------
8
1 file changed, 54 insertions(+), 68 deletions(-)
11
1 file changed, 11 insertions(+), 14 deletions(-)
9
12
10
diff --git a/tcg/tci.c b/tcg/tci.c
13
diff --git a/tcg/optimize.c b/tcg/optimize.c
11
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
12
--- a/tcg/tci.c
15
--- a/tcg/optimize.c
13
+++ b/tcg/tci.c
16
+++ b/tcg/optimize.c
14
@@ -XXX,XX +XXX,XX @@ static int32_t tci_read_reg32s(const tcg_target_ulong *regs, TCGReg index)
17
@@ -XXX,XX +XXX,XX @@ static void init_ts_info(OptContext *ctx, TCGTemp *ts)
18
}
15
}
19
}
16
#endif
20
17
21
-static void init_arg_info(OptContext *ctx, TCGArg arg)
18
-static uint32_t tci_read_reg32(const tcg_target_ulong *regs, TCGReg index)
19
-{
22
-{
20
- return (uint32_t)tci_read_reg(regs, index);
23
- init_ts_info(ctx, arg_temp(arg));
21
-}
24
-}
22
-
25
-
23
#if TCG_TARGET_REG_BITS == 64
26
static TCGTemp *find_better_copy(TCGContext *s, TCGTemp *ts)
24
static uint64_t tci_read_reg64(const tcg_target_ulong *regs, TCGReg index)
25
{
27
{
26
@@ -XXX,XX +XXX,XX @@ tci_read_r(const tcg_target_ulong *regs, const uint8_t **tb_ptr)
28
TCGTemp *i, *g, *l;
27
return value;
29
@@ -XXX,XX +XXX,XX @@ static bool swap_commutative2(TCGArg *p1, TCGArg *p2)
30
return false;
28
}
31
}
29
32
30
-/* Read indexed register (32 bit) from bytecode. */
33
+static void init_arguments(OptContext *ctx, TCGOp *op, int nb_args)
31
-static uint32_t tci_read_r32(const tcg_target_ulong *regs,
34
+{
32
- const uint8_t **tb_ptr)
35
+ for (int i = 0; i < nb_args; i++) {
33
-{
36
+ TCGTemp *ts = arg_temp(op->args[i]);
34
- uint32_t value = tci_read_reg32(regs, **tb_ptr);
37
+ if (ts) {
35
- *tb_ptr += 1;
38
+ init_ts_info(ctx, ts);
36
- return value;
39
+ }
37
-}
40
+ }
38
-
41
+}
39
#if TCG_TARGET_REG_BITS == 32
42
+
40
/* Read two indexed registers (2 * 32 bit) from bytecode. */
43
/* Propagate constants and copies, fold constant expressions. */
41
static uint64_t tci_read_r64(const tcg_target_ulong *regs,
44
void tcg_optimize(TCGContext *s)
42
const uint8_t **tb_ptr)
43
{
45
{
44
- uint32_t low = tci_read_r32(regs, tb_ptr);
46
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
45
- return tci_uint64(tci_read_r32(regs, tb_ptr), low);
47
if (opc == INDEX_op_call) {
46
+ uint32_t low = tci_read_r(regs, tb_ptr);
48
nb_oargs = TCGOP_CALLO(op);
47
+ return tci_uint64(tci_read_r(regs, tb_ptr), low);
49
nb_iargs = TCGOP_CALLI(op);
48
}
50
- for (i = 0; i < nb_oargs + nb_iargs; i++) {
49
#elif TCG_TARGET_REG_BITS == 64
51
- TCGTemp *ts = arg_temp(op->args[i]);
50
/* Read indexed register (32 bit signed) from bytecode. */
52
- if (ts) {
51
@@ -XXX,XX +XXX,XX @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
53
- init_ts_info(&ctx, ts);
52
continue;
54
- }
53
case INDEX_op_setcond_i32:
55
- }
54
t0 = *tb_ptr++;
56
} else {
55
- t1 = tci_read_r32(regs, &tb_ptr);
57
nb_oargs = def->nb_oargs;
56
- t2 = tci_read_r32(regs, &tb_ptr);
58
nb_iargs = def->nb_iargs;
57
+ t1 = tci_read_r(regs, &tb_ptr);
59
- for (i = 0; i < nb_oargs + nb_iargs; i++) {
58
+ t2 = tci_read_r(regs, &tb_ptr);
60
- init_arg_info(&ctx, op->args[i]);
59
condition = *tb_ptr++;
61
- }
60
tci_write_reg(regs, t0, tci_compare32(t1, t2, condition));
62
}
61
break;
63
+ init_arguments(&ctx, op, nb_oargs + nb_iargs);
62
@@ -XXX,XX +XXX,XX @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
64
63
#endif
65
/* Do copy propagation */
64
case INDEX_op_mov_i32:
66
for (i = nb_oargs; i < nb_oargs + nb_iargs; i++) {
65
t0 = *tb_ptr++;
66
- t1 = tci_read_r32(regs, &tb_ptr);
67
+ t1 = tci_read_r(regs, &tb_ptr);
68
tci_write_reg(regs, t0, t1);
69
break;
70
case INDEX_op_tci_movi_i32:
71
@@ -XXX,XX +XXX,XX @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
72
break;
73
case INDEX_op_st_i32:
74
CASE_64(st32)
75
- t0 = tci_read_r32(regs, &tb_ptr);
76
+ t0 = tci_read_r(regs, &tb_ptr);
77
t1 = tci_read_r(regs, &tb_ptr);
78
t2 = tci_read_s32(&tb_ptr);
79
*(uint32_t *)(t1 + t2) = t0;
80
@@ -XXX,XX +XXX,XX @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
81
82
case INDEX_op_add_i32:
83
t0 = *tb_ptr++;
84
- t1 = tci_read_r32(regs, &tb_ptr);
85
- t2 = tci_read_r32(regs, &tb_ptr);
86
+ t1 = tci_read_r(regs, &tb_ptr);
87
+ t2 = tci_read_r(regs, &tb_ptr);
88
tci_write_reg(regs, t0, t1 + t2);
89
break;
90
case INDEX_op_sub_i32:
91
t0 = *tb_ptr++;
92
- t1 = tci_read_r32(regs, &tb_ptr);
93
- t2 = tci_read_r32(regs, &tb_ptr);
94
+ t1 = tci_read_r(regs, &tb_ptr);
95
+ t2 = tci_read_r(regs, &tb_ptr);
96
tci_write_reg(regs, t0, t1 - t2);
97
break;
98
case INDEX_op_mul_i32:
99
t0 = *tb_ptr++;
100
- t1 = tci_read_r32(regs, &tb_ptr);
101
- t2 = tci_read_r32(regs, &tb_ptr);
102
+ t1 = tci_read_r(regs, &tb_ptr);
103
+ t2 = tci_read_r(regs, &tb_ptr);
104
tci_write_reg(regs, t0, t1 * t2);
105
break;
106
case INDEX_op_div_i32:
107
t0 = *tb_ptr++;
108
- t1 = tci_read_r32(regs, &tb_ptr);
109
- t2 = tci_read_r32(regs, &tb_ptr);
110
+ t1 = tci_read_r(regs, &tb_ptr);
111
+ t2 = tci_read_r(regs, &tb_ptr);
112
tci_write_reg(regs, t0, (int32_t)t1 / (int32_t)t2);
113
break;
114
case INDEX_op_divu_i32:
115
t0 = *tb_ptr++;
116
- t1 = tci_read_r32(regs, &tb_ptr);
117
- t2 = tci_read_r32(regs, &tb_ptr);
118
- tci_write_reg(regs, t0, t1 / t2);
119
+ t1 = tci_read_r(regs, &tb_ptr);
120
+ t2 = tci_read_r(regs, &tb_ptr);
121
+ tci_write_reg(regs, t0, (uint32_t)t1 / (uint32_t)t2);
122
break;
123
case INDEX_op_rem_i32:
124
t0 = *tb_ptr++;
125
- t1 = tci_read_r32(regs, &tb_ptr);
126
- t2 = tci_read_r32(regs, &tb_ptr);
127
+ t1 = tci_read_r(regs, &tb_ptr);
128
+ t2 = tci_read_r(regs, &tb_ptr);
129
tci_write_reg(regs, t0, (int32_t)t1 % (int32_t)t2);
130
break;
131
case INDEX_op_remu_i32:
132
t0 = *tb_ptr++;
133
- t1 = tci_read_r32(regs, &tb_ptr);
134
- t2 = tci_read_r32(regs, &tb_ptr);
135
- tci_write_reg(regs, t0, t1 % t2);
136
+ t1 = tci_read_r(regs, &tb_ptr);
137
+ t2 = tci_read_r(regs, &tb_ptr);
138
+ tci_write_reg(regs, t0, (uint32_t)t1 % (uint32_t)t2);
139
break;
140
case INDEX_op_and_i32:
141
t0 = *tb_ptr++;
142
- t1 = tci_read_r32(regs, &tb_ptr);
143
- t2 = tci_read_r32(regs, &tb_ptr);
144
+ t1 = tci_read_r(regs, &tb_ptr);
145
+ t2 = tci_read_r(regs, &tb_ptr);
146
tci_write_reg(regs, t0, t1 & t2);
147
break;
148
case INDEX_op_or_i32:
149
t0 = *tb_ptr++;
150
- t1 = tci_read_r32(regs, &tb_ptr);
151
- t2 = tci_read_r32(regs, &tb_ptr);
152
+ t1 = tci_read_r(regs, &tb_ptr);
153
+ t2 = tci_read_r(regs, &tb_ptr);
154
tci_write_reg(regs, t0, t1 | t2);
155
break;
156
case INDEX_op_xor_i32:
157
t0 = *tb_ptr++;
158
- t1 = tci_read_r32(regs, &tb_ptr);
159
- t2 = tci_read_r32(regs, &tb_ptr);
160
+ t1 = tci_read_r(regs, &tb_ptr);
161
+ t2 = tci_read_r(regs, &tb_ptr);
162
tci_write_reg(regs, t0, t1 ^ t2);
163
break;
164
165
@@ -XXX,XX +XXX,XX @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
166
167
case INDEX_op_shl_i32:
168
t0 = *tb_ptr++;
169
- t1 = tci_read_r32(regs, &tb_ptr);
170
- t2 = tci_read_r32(regs, &tb_ptr);
171
- tci_write_reg(regs, t0, t1 << (t2 & 31));
172
+ t1 = tci_read_r(regs, &tb_ptr);
173
+ t2 = tci_read_r(regs, &tb_ptr);
174
+ tci_write_reg(regs, t0, (uint32_t)t1 << (t2 & 31));
175
break;
176
case INDEX_op_shr_i32:
177
t0 = *tb_ptr++;
178
- t1 = tci_read_r32(regs, &tb_ptr);
179
- t2 = tci_read_r32(regs, &tb_ptr);
180
- tci_write_reg(regs, t0, t1 >> (t2 & 31));
181
+ t1 = tci_read_r(regs, &tb_ptr);
182
+ t2 = tci_read_r(regs, &tb_ptr);
183
+ tci_write_reg(regs, t0, (uint32_t)t1 >> (t2 & 31));
184
break;
185
case INDEX_op_sar_i32:
186
t0 = *tb_ptr++;
187
- t1 = tci_read_r32(regs, &tb_ptr);
188
- t2 = tci_read_r32(regs, &tb_ptr);
189
- tci_write_reg(regs, t0, ((int32_t)t1 >> (t2 & 31)));
190
+ t1 = tci_read_r(regs, &tb_ptr);
191
+ t2 = tci_read_r(regs, &tb_ptr);
192
+ tci_write_reg(regs, t0, (int32_t)t1 >> (t2 & 31));
193
break;
194
#if TCG_TARGET_HAS_rot_i32
195
case INDEX_op_rotl_i32:
196
t0 = *tb_ptr++;
197
- t1 = tci_read_r32(regs, &tb_ptr);
198
- t2 = tci_read_r32(regs, &tb_ptr);
199
+ t1 = tci_read_r(regs, &tb_ptr);
200
+ t2 = tci_read_r(regs, &tb_ptr);
201
tci_write_reg(regs, t0, rol32(t1, t2 & 31));
202
break;
203
case INDEX_op_rotr_i32:
204
t0 = *tb_ptr++;
205
- t1 = tci_read_r32(regs, &tb_ptr);
206
- t2 = tci_read_r32(regs, &tb_ptr);
207
+ t1 = tci_read_r(regs, &tb_ptr);
208
+ t2 = tci_read_r(regs, &tb_ptr);
209
tci_write_reg(regs, t0, ror32(t1, t2 & 31));
210
break;
211
#endif
212
#if TCG_TARGET_HAS_deposit_i32
213
case INDEX_op_deposit_i32:
214
t0 = *tb_ptr++;
215
- t1 = tci_read_r32(regs, &tb_ptr);
216
- t2 = tci_read_r32(regs, &tb_ptr);
217
+ t1 = tci_read_r(regs, &tb_ptr);
218
+ t2 = tci_read_r(regs, &tb_ptr);
219
tmp16 = *tb_ptr++;
220
tmp8 = *tb_ptr++;
221
tmp32 = (((1 << tmp8) - 1) << tmp16);
222
@@ -XXX,XX +XXX,XX @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
223
break;
224
#endif
225
case INDEX_op_brcond_i32:
226
- t0 = tci_read_r32(regs, &tb_ptr);
227
- t1 = tci_read_r32(regs, &tb_ptr);
228
+ t0 = tci_read_r(regs, &tb_ptr);
229
+ t1 = tci_read_r(regs, &tb_ptr);
230
condition = *tb_ptr++;
231
label = tci_read_label(&tb_ptr);
232
if (tci_compare32(t0, t1, condition)) {
233
@@ -XXX,XX +XXX,XX @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
234
case INDEX_op_mulu2_i32:
235
t0 = *tb_ptr++;
236
t1 = *tb_ptr++;
237
- t2 = tci_read_r32(regs, &tb_ptr);
238
- tmp64 = tci_read_r32(regs, &tb_ptr);
239
- tci_write_reg64(regs, t1, t0, t2 * tmp64);
240
+ t2 = tci_read_r(regs, &tb_ptr);
241
+ tmp64 = (uint32_t)tci_read_r(regs, &tb_ptr);
242
+ tci_write_reg64(regs, t1, t0, (uint32_t)t2 * tmp64);
243
break;
244
#endif /* TCG_TARGET_REG_BITS == 32 */
245
#if TCG_TARGET_HAS_ext8s_i32
246
@@ -XXX,XX +XXX,XX @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
247
#if TCG_TARGET_HAS_bswap32_i32
248
case INDEX_op_bswap32_i32:
249
t0 = *tb_ptr++;
250
- t1 = tci_read_r32(regs, &tb_ptr);
251
+ t1 = tci_read_r(regs, &tb_ptr);
252
tci_write_reg(regs, t0, bswap32(t1));
253
break;
254
#endif
255
#if TCG_TARGET_HAS_not_i32
256
case INDEX_op_not_i32:
257
t0 = *tb_ptr++;
258
- t1 = tci_read_r32(regs, &tb_ptr);
259
+ t1 = tci_read_r(regs, &tb_ptr);
260
tci_write_reg(regs, t0, ~t1);
261
break;
262
#endif
263
#if TCG_TARGET_HAS_neg_i32
264
case INDEX_op_neg_i32:
265
t0 = *tb_ptr++;
266
- t1 = tci_read_r32(regs, &tb_ptr);
267
+ t1 = tci_read_r(regs, &tb_ptr);
268
tci_write_reg(regs, t0, -t1);
269
break;
270
#endif
271
@@ -XXX,XX +XXX,XX @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
272
#endif
273
case INDEX_op_extu_i32_i64:
274
t0 = *tb_ptr++;
275
- t1 = tci_read_r32(regs, &tb_ptr);
276
- tci_write_reg(regs, t0, t1);
277
+ t1 = tci_read_r(regs, &tb_ptr);
278
+ tci_write_reg(regs, t0, (uint32_t)t1);
279
break;
280
#if TCG_TARGET_HAS_bswap16_i64
281
case INDEX_op_bswap16_i64:
282
@@ -XXX,XX +XXX,XX @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
283
#if TCG_TARGET_HAS_bswap32_i64
284
case INDEX_op_bswap32_i64:
285
t0 = *tb_ptr++;
286
- t1 = tci_read_r32(regs, &tb_ptr);
287
+ t1 = tci_read_r(regs, &tb_ptr);
288
tci_write_reg(regs, t0, bswap32(t1));
289
break;
290
#endif
291
--
67
--
292
2.25.1
68
2.25.1
293
69
294
70
diff view generated by jsdifflib
New patch
[PULL 12/56] tcg/optimize: Split out copy_propagate
1
Continue splitting tcg_optimize.
1
2
3
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
4
Reviewed-by: Luis Pires <luis.pires@eldorado.org.br>
5
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
---
8
tcg/optimize.c | 22 ++++++++++++++--------
9
1 file changed, 14 insertions(+), 8 deletions(-)
10
11
diff --git a/tcg/optimize.c b/tcg/optimize.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/tcg/optimize.c
14
+++ b/tcg/optimize.c
15
@@ -XXX,XX +XXX,XX @@ static void init_arguments(OptContext *ctx, TCGOp *op, int nb_args)
16
}
17
}
18
19
+static void copy_propagate(OptContext *ctx, TCGOp *op,
20
+ int nb_oargs, int nb_iargs)
21
+{
22
+ TCGContext *s = ctx->tcg;
23
+
24
+ for (int i = nb_oargs; i < nb_oargs + nb_iargs; i++) {
25
+ TCGTemp *ts = arg_temp(op->args[i]);
26
+ if (ts && ts_is_copy(ts)) {
27
+ op->args[i] = temp_arg(find_better_copy(s, ts));
28
+ }
29
+ }
30
+}
31
+
32
/* Propagate constants and copies, fold constant expressions. */
33
void tcg_optimize(TCGContext *s)
34
{
35
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
36
nb_iargs = def->nb_iargs;
37
}
38
init_arguments(&ctx, op, nb_oargs + nb_iargs);
39
-
40
- /* Do copy propagation */
41
- for (i = nb_oargs; i < nb_oargs + nb_iargs; i++) {
42
- TCGTemp *ts = arg_temp(op->args[i]);
43
- if (ts && ts_is_copy(ts)) {
44
- op->args[i] = temp_arg(find_better_copy(s, ts));
45
- }
46
- }
47
+ copy_propagate(&ctx, op, nb_oargs, nb_iargs);
48
49
/* For commutative operations make constant second argument */
50
switch (opc) {
51
--
52
2.25.1
53
54
diff view generated by jsdifflib
[PATCH 06/27] tcg: Manage splitwx in tc_ptr_to_region_tree by hand
[PULL 13/56] tcg/optimize: Split out fold_call
1
The use in tcg_tb_lookup is given a random pc that comes from the pc
1
Calls are special in that they have a variable number
2
of a signal handler. Do not assert that the pointer is already within
2
of arguments, and need to be able to clobber globals.
3
the code gen buffer at all, much less the writable mirror of it.
4
3
5
Fixes: db0c51a3803
4
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
5
Reviewed-by: Luis Pires <luis.pires@eldorado.org.br>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
---
7
---
8
tcg/tcg.c | 20 ++++++++++++++++++--
8
tcg/optimize.c | 63 ++++++++++++++++++++++++++++++++------------------
9
1 file changed, 18 insertions(+), 2 deletions(-)
9
1 file changed, 41 insertions(+), 22 deletions(-)
10
10
11
diff --git a/tcg/tcg.c b/tcg/tcg.c
11
diff --git a/tcg/optimize.c b/tcg/optimize.c
12
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
13
--- a/tcg/tcg.c
13
--- a/tcg/optimize.c
14
+++ b/tcg/tcg.c
14
+++ b/tcg/optimize.c
15
@@ -XXX,XX +XXX,XX @@ static void tcg_region_trees_init(void)
15
@@ -XXX,XX +XXX,XX @@ static void copy_propagate(OptContext *ctx, TCGOp *op,
16
}
16
}
17
}
17
}
18
18
19
-static struct tcg_region_tree *tc_ptr_to_region_tree(const void *cp)
19
+static bool fold_call(OptContext *ctx, TCGOp *op)
20
+static struct tcg_region_tree *tc_ptr_to_region_tree(const void *p)
20
+{
21
{
21
+ TCGContext *s = ctx->tcg;
22
- void *p = tcg_splitwx_to_rw(cp);
22
+ int nb_oargs = TCGOP_CALLO(op);
23
size_t region_idx;
23
+ int nb_iargs = TCGOP_CALLI(op);
24
24
+ int flags, i;
25
+ /*
25
+
26
+ * Like tcg_splitwx_to_rw, with no assert. The pc may come from
26
+ init_arguments(ctx, op, nb_oargs + nb_iargs);
27
+ * a signal handler over which the caller has no control.
27
+ copy_propagate(ctx, op, nb_oargs, nb_iargs);
28
+ */
28
+
29
+ if (!in_code_gen_buffer(p)) {
29
+ /* If the function reads or writes globals, reset temp data. */
30
+ p -= tcg_splitwx_diff;
30
+ flags = tcg_call_flags(op);
31
+ if (!in_code_gen_buffer(p)) {
31
+ if (!(flags & (TCG_CALL_NO_READ_GLOBALS | TCG_CALL_NO_WRITE_GLOBALS))) {
32
+ return NULL;
32
+ int nb_globals = s->nb_globals;
33
+
34
+ for (i = 0; i < nb_globals; i++) {
35
+ if (test_bit(i, ctx->temps_used.l)) {
36
+ reset_ts(&ctx->tcg->temps[i]);
37
+ }
33
+ }
38
+ }
34
+ }
39
+ }
35
+
40
+
36
if (p < region.start_aligned) {
41
+ /* Reset temp data for outputs. */
37
region_idx = 0;
42
+ for (i = 0; i < nb_oargs; i++) {
38
} else {
43
+ reset_temp(op->args[i]);
39
@@ -XXX,XX +XXX,XX @@ void tcg_tb_insert(TranslationBlock *tb)
40
{
41
struct tcg_region_tree *rt = tc_ptr_to_region_tree(tb->tc.ptr);
42
43
+ g_assert(rt != NULL);
44
qemu_mutex_lock(&rt->lock);
45
g_tree_insert(rt->tree, &tb->tc, tb);
46
qemu_mutex_unlock(&rt->lock);
47
@@ -XXX,XX +XXX,XX @@ void tcg_tb_remove(TranslationBlock *tb)
48
{
49
struct tcg_region_tree *rt = tc_ptr_to_region_tree(tb->tc.ptr);
50
51
+ g_assert(rt != NULL);
52
qemu_mutex_lock(&rt->lock);
53
g_tree_remove(rt->tree, &tb->tc);
54
qemu_mutex_unlock(&rt->lock);
55
@@ -XXX,XX +XXX,XX @@ TranslationBlock *tcg_tb_lookup(uintptr_t tc_ptr)
56
TranslationBlock *tb;
57
struct tb_tc s = { .ptr = (void *)tc_ptr };
58
59
+ if (rt == NULL) {
60
+ return NULL;
61
+ }
44
+ }
62
+
45
+
63
qemu_mutex_lock(&rt->lock);
46
+ /* Stop optimizing MB across calls. */
64
tb = g_tree_lookup(rt->tree, &s);
47
+ ctx->prev_mb = NULL;
65
qemu_mutex_unlock(&rt->lock);
48
+ return true;
49
+}
50
+
51
/* Propagate constants and copies, fold constant expressions. */
52
void tcg_optimize(TCGContext *s)
53
{
54
- int nb_temps, nb_globals, i;
55
+ int nb_temps, i;
56
TCGOp *op, *op_next;
57
OptContext ctx = { .tcg = s };
58
59
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
60
available through the doubly linked circular list. */
61
62
nb_temps = s->nb_temps;
63
- nb_globals = s->nb_globals;
64
-
65
for (i = 0; i < nb_temps; ++i) {
66
s->temps[i].state_ptr = NULL;
67
}
68
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
69
uint64_t z_mask, partmask, affected, tmp;
70
int nb_oargs, nb_iargs;
71
TCGOpcode opc = op->opc;
72
- const TCGOpDef *def = &tcg_op_defs[opc];
73
+ const TCGOpDef *def;
74
75
- /* Count the arguments, and initialize the temps that are
76
- going to be used */
77
+ /* Calls are special. */
78
if (opc == INDEX_op_call) {
79
- nb_oargs = TCGOP_CALLO(op);
80
- nb_iargs = TCGOP_CALLI(op);
81
- } else {
82
- nb_oargs = def->nb_oargs;
83
- nb_iargs = def->nb_iargs;
84
+ fold_call(&ctx, op);
85
+ continue;
86
}
87
+
88
+ def = &tcg_op_defs[opc];
89
+ nb_oargs = def->nb_oargs;
90
+ nb_iargs = def->nb_iargs;
91
init_arguments(&ctx, op, nb_oargs + nb_iargs);
92
copy_propagate(&ctx, op, nb_oargs, nb_iargs);
93
94
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
95
if (def->flags & TCG_OPF_BB_END) {
96
memset(&ctx.temps_used, 0, sizeof(ctx.temps_used));
97
} else {
98
- if (opc == INDEX_op_call &&
99
- !(tcg_call_flags(op)
100
- & (TCG_CALL_NO_READ_GLOBALS | TCG_CALL_NO_WRITE_GLOBALS))) {
101
- for (i = 0; i < nb_globals; i++) {
102
- if (test_bit(i, ctx.temps_used.l)) {
103
- reset_ts(&s->temps[i]);
104
- }
105
- }
106
- }
107
-
108
for (i = 0; i < nb_oargs; i++) {
109
reset_temp(op->args[i]);
110
/* Save the corresponding known-zero bits mask for the
111
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
112
case INDEX_op_qemu_st_i32:
113
case INDEX_op_qemu_st8_i32:
114
case INDEX_op_qemu_st_i64:
115
- case INDEX_op_call:
116
/* Opcodes that touch guest memory stop the optimization. */
117
ctx.prev_mb = NULL;
118
break;
66
--
119
--
67
2.25.1
120
2.25.1
68
121
69
122
diff view generated by jsdifflib
New patch
[PULL 14/56] tcg/optimize: Drop nb_oargs, nb_iargs locals
1
Rather than try to keep these up-to-date across folding,
2
re-read nb_oargs at the end, after re-reading the opcode.
1
3
4
A couple of asserts need dropping, but that will take care
5
of itself as we split the function further.
6
7
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
8
Reviewed-by: Luis Pires <luis.pires@eldorado.org.br>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
---
11
tcg/optimize.c | 14 ++++----------
12
1 file changed, 4 insertions(+), 10 deletions(-)
13
14
diff --git a/tcg/optimize.c b/tcg/optimize.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/tcg/optimize.c
17
+++ b/tcg/optimize.c
18
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
19
20
QTAILQ_FOREACH_SAFE(op, &s->ops, link, op_next) {
21
uint64_t z_mask, partmask, affected, tmp;
22
- int nb_oargs, nb_iargs;
23
TCGOpcode opc = op->opc;
24
const TCGOpDef *def;
25
26
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
27
}
28
29
def = &tcg_op_defs[opc];
30
- nb_oargs = def->nb_oargs;
31
- nb_iargs = def->nb_iargs;
32
- init_arguments(&ctx, op, nb_oargs + nb_iargs);
33
- copy_propagate(&ctx, op, nb_oargs, nb_iargs);
34
+ init_arguments(&ctx, op, def->nb_oargs + def->nb_iargs);
35
+ copy_propagate(&ctx, op, def->nb_oargs, def->nb_iargs);
36
37
/* For commutative operations make constant second argument */
38
switch (opc) {
39
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
40
41
CASE_OP_32_64(qemu_ld):
42
{
43
- MemOpIdx oi = op->args[nb_oargs + nb_iargs];
44
+ MemOpIdx oi = op->args[def->nb_oargs + def->nb_iargs];
45
MemOp mop = get_memop(oi);
46
if (!(mop & MO_SIGN)) {
47
z_mask = (2ULL << ((8 << (mop & MO_SIZE)) - 1)) - 1;
48
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
49
}
50
51
if (partmask == 0) {
52
- tcg_debug_assert(nb_oargs == 1);
53
tcg_opt_gen_movi(&ctx, op, op->args[0], 0);
54
continue;
55
}
56
if (affected == 0) {
57
- tcg_debug_assert(nb_oargs == 1);
58
tcg_opt_gen_mov(&ctx, op, op->args[0], op->args[1]);
59
continue;
60
}
61
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
62
} else if (args_are_copies(op->args[1], op->args[2])) {
63
op->opc = INDEX_op_dup_vec;
64
TCGOP_VECE(op) = MO_32;
65
- nb_iargs = 1;
66
}
67
break;
68
69
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
70
op->opc = opc = (opc == INDEX_op_movcond_i32
71
? INDEX_op_setcond_i32
72
: INDEX_op_setcond_i64);
73
- nb_iargs = 2;
74
}
75
break;
76
77
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
78
if (def->flags & TCG_OPF_BB_END) {
79
memset(&ctx.temps_used, 0, sizeof(ctx.temps_used));
80
} else {
81
+ int nb_oargs = def->nb_oargs;
82
for (i = 0; i < nb_oargs; i++) {
83
reset_temp(op->args[i]);
84
/* Save the corresponding known-zero bits mask for the
85
--
86
2.25.1
87
88
diff view generated by jsdifflib
[PATCH 14/27] tcg/tci: Remove tci_read_r16
[PULL 15/56] tcg/optimize: Change fail return for do_constant_folding_cond*
1
Use explicit casts for ext16u opcodes, and allow truncation
1
Return -1 instead of 2 for failure, so that we can
2
to happen with the store for st16 opcodes, and with the call
2
use comparisons against 0 for all cases.
3
for bswap16 opcodes.
3
4
4
Reviewed-by: Luis Pires <luis.pires@eldorado.org.br>
5
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
5
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
---
7
---
8
tcg/tci.c | 28 +++++++---------------------
8
tcg/optimize.c | 145 +++++++++++++++++++++++++------------------------
9
1 file changed, 7 insertions(+), 21 deletions(-)
9
1 file changed, 74 insertions(+), 71 deletions(-)
10
10
11
diff --git a/tcg/tci.c b/tcg/tci.c
11
diff --git a/tcg/optimize.c b/tcg/optimize.c
12
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
13
--- a/tcg/tci.c
13
--- a/tcg/optimize.c
14
+++ b/tcg/tci.c
14
+++ b/tcg/optimize.c
15
@@ -XXX,XX +XXX,XX @@ static int32_t tci_read_reg32s(const tcg_target_ulong *regs, TCGReg index)
15
@@ -XXX,XX +XXX,XX @@ static bool do_constant_folding_cond_eq(TCGCond c)
16
}
16
}
17
}
17
#endif
18
18
19
-/* Return 2 if the condition can't be simplified, and the result
19
-static uint16_t tci_read_reg16(const tcg_target_ulong *regs, TCGReg index)
20
- of the condition (0 or 1) if it can */
20
-{
21
-static TCGArg do_constant_folding_cond(TCGOpcode op, TCGArg x,
21
- return (uint16_t)tci_read_reg(regs, index);
22
- TCGArg y, TCGCond c)
22
-}
23
+/*
23
-
24
+ * Return -1 if the condition can't be simplified,
24
static uint32_t tci_read_reg32(const tcg_target_ulong *regs, TCGReg index)
25
+ * and the result of the condition (0 or 1) if it can.
26
+ */
27
+static int do_constant_folding_cond(TCGOpcode op, TCGArg x,
28
+ TCGArg y, TCGCond c)
25
{
29
{
26
return (uint32_t)tci_read_reg(regs, index);
30
uint64_t xv = arg_info(x)->val;
27
@@ -XXX,XX +XXX,XX @@ tci_read_r(const tcg_target_ulong *regs, const uint8_t **tb_ptr)
31
uint64_t yv = arg_info(y)->val;
28
return value;
32
@@ -XXX,XX +XXX,XX @@ static TCGArg do_constant_folding_cond(TCGOpcode op, TCGArg x,
33
case TCG_COND_GEU:
34
return 1;
35
default:
36
- return 2;
37
+ return -1;
38
}
39
}
40
- return 2;
41
+ return -1;
29
}
42
}
30
43
31
-/* Read indexed register (16 bit) from bytecode. */
44
-/* Return 2 if the condition can't be simplified, and the result
32
-static uint16_t tci_read_r16(const tcg_target_ulong *regs,
45
- of the condition (0 or 1) if it can */
33
- const uint8_t **tb_ptr)
46
-static TCGArg do_constant_folding_cond2(TCGArg *p1, TCGArg *p2, TCGCond c)
34
-{
47
+/*
35
- uint16_t value = tci_read_reg16(regs, **tb_ptr);
48
+ * Return -1 if the condition can't be simplified,
36
- *tb_ptr += 1;
49
+ * and the result of the condition (0 or 1) if it can.
37
- return value;
50
+ */
38
-}
51
+static int do_constant_folding_cond2(TCGArg *p1, TCGArg *p2, TCGCond c)
39
-
52
{
40
#if TCG_TARGET_HAS_ext16s_i32 || TCG_TARGET_HAS_ext16s_i64
53
TCGArg al = p1[0], ah = p1[1];
41
/* Read indexed register (16 bit signed) from bytecode. */
54
TCGArg bl = p2[0], bh = p2[1];
42
static int16_t tci_read_r16s(const tcg_target_ulong *regs,
55
@@ -XXX,XX +XXX,XX @@ static TCGArg do_constant_folding_cond2(TCGArg *p1, TCGArg *p2, TCGCond c)
43
@@ -XXX,XX +XXX,XX @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
56
if (args_are_copies(al, bl) && args_are_copies(ah, bh)) {
44
*(uint8_t *)(t1 + t2) = t0;
57
return do_constant_folding_cond_eq(c);
45
break;
58
}
46
CASE_32_64(st16)
59
- return 2;
47
- t0 = tci_read_r16(regs, &tb_ptr);
60
+ return -1;
48
+ t0 = tci_read_r(regs, &tb_ptr);
61
}
49
t1 = tci_read_r(regs, &tb_ptr);
62
50
t2 = tci_read_s32(&tb_ptr);
63
static bool swap_commutative(TCGArg dest, TCGArg *p1, TCGArg *p2)
51
*(uint16_t *)(t1 + t2) = t0;
64
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
52
@@ -XXX,XX +XXX,XX @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
65
break;
53
#if TCG_TARGET_HAS_ext16u_i32
66
54
case INDEX_op_ext16u_i32:
67
CASE_OP_32_64(setcond):
55
t0 = *tb_ptr++;
68
- tmp = do_constant_folding_cond(opc, op->args[1],
56
- t1 = tci_read_r16(regs, &tb_ptr);
69
- op->args[2], op->args[3]);
57
- tci_write_reg(regs, t0, t1);
70
- if (tmp != 2) {
58
+ t1 = tci_read_r(regs, &tb_ptr);
71
- tcg_opt_gen_movi(&ctx, op, op->args[0], tmp);
59
+ tci_write_reg(regs, t0, (uint16_t)t1);
72
+ i = do_constant_folding_cond(opc, op->args[1],
60
break;
73
+ op->args[2], op->args[3]);
61
#endif
74
+ if (i >= 0) {
62
#if TCG_TARGET_HAS_bswap16_i32
75
+ tcg_opt_gen_movi(&ctx, op, op->args[0], i);
63
case INDEX_op_bswap16_i32:
76
continue;
64
t0 = *tb_ptr++;
77
}
65
- t1 = tci_read_r16(regs, &tb_ptr);
78
break;
66
+ t1 = tci_read_r(regs, &tb_ptr);
79
67
tci_write_reg(regs, t0, bswap16(t1));
80
CASE_OP_32_64(brcond):
68
break;
81
- tmp = do_constant_folding_cond(opc, op->args[0],
69
#endif
82
- op->args[1], op->args[2]);
70
@@ -XXX,XX +XXX,XX @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
83
- switch (tmp) {
71
#if TCG_TARGET_HAS_ext16u_i64
84
- case 0:
72
case INDEX_op_ext16u_i64:
85
+ i = do_constant_folding_cond(opc, op->args[0],
73
t0 = *tb_ptr++;
86
+ op->args[1], op->args[2]);
74
- t1 = tci_read_r16(regs, &tb_ptr);
87
+ if (i == 0) {
75
- tci_write_reg(regs, t0, t1);
88
tcg_op_remove(s, op);
76
+ t1 = tci_read_r(regs, &tb_ptr);
89
continue;
77
+ tci_write_reg(regs, t0, (uint16_t)t1);
90
- case 1:
78
break;
91
+ } else if (i > 0) {
79
#endif
92
memset(&ctx.temps_used, 0, sizeof(ctx.temps_used));
80
#if TCG_TARGET_HAS_ext32s_i64
93
op->opc = opc = INDEX_op_br;
81
@@ -XXX,XX +XXX,XX @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
94
op->args[0] = op->args[3];
82
#if TCG_TARGET_HAS_bswap16_i64
95
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
83
case INDEX_op_bswap16_i64:
96
break;
84
t0 = *tb_ptr++;
97
85
- t1 = tci_read_r16(regs, &tb_ptr);
98
CASE_OP_32_64(movcond):
86
+ t1 = tci_read_r(regs, &tb_ptr);
99
- tmp = do_constant_folding_cond(opc, op->args[1],
87
tci_write_reg(regs, t0, bswap16(t1));
100
- op->args[2], op->args[5]);
88
break;
101
- if (tmp != 2) {
89
#endif
102
- tcg_opt_gen_mov(&ctx, op, op->args[0], op->args[4-tmp]);
103
+ i = do_constant_folding_cond(opc, op->args[1],
104
+ op->args[2], op->args[5]);
105
+ if (i >= 0) {
106
+ tcg_opt_gen_mov(&ctx, op, op->args[0], op->args[4 - i]);
107
continue;
108
}
109
if (arg_is_const(op->args[3]) && arg_is_const(op->args[4])) {
110
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
111
break;
112
113
case INDEX_op_brcond2_i32:
114
- tmp = do_constant_folding_cond2(&op->args[0], &op->args[2],
115
- op->args[4]);
116
- if (tmp == 0) {
117
+ i = do_constant_folding_cond2(&op->args[0], &op->args[2],
118
+ op->args[4]);
119
+ if (i == 0) {
120
do_brcond_false:
121
tcg_op_remove(s, op);
122
continue;
123
}
124
- if (tmp == 1) {
125
+ if (i > 0) {
126
do_brcond_true:
127
op->opc = opc = INDEX_op_br;
128
op->args[0] = op->args[5];
129
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
130
if (op->args[4] == TCG_COND_EQ) {
131
/* Simplify EQ comparisons where one of the pairs
132
can be simplified. */
133
- tmp = do_constant_folding_cond(INDEX_op_brcond_i32,
134
- op->args[0], op->args[2],
135
- TCG_COND_EQ);
136
- if (tmp == 0) {
137
+ i = do_constant_folding_cond(INDEX_op_brcond_i32,
138
+ op->args[0], op->args[2],
139
+ TCG_COND_EQ);
140
+ if (i == 0) {
141
goto do_brcond_false;
142
- } else if (tmp == 1) {
143
+ } else if (i > 0) {
144
goto do_brcond_high;
145
}
146
- tmp = do_constant_folding_cond(INDEX_op_brcond_i32,
147
- op->args[1], op->args[3],
148
- TCG_COND_EQ);
149
- if (tmp == 0) {
150
+ i = do_constant_folding_cond(INDEX_op_brcond_i32,
151
+ op->args[1], op->args[3],
152
+ TCG_COND_EQ);
153
+ if (i == 0) {
154
goto do_brcond_false;
155
- } else if (tmp != 1) {
156
+ } else if (i < 0) {
157
break;
158
}
159
do_brcond_low:
160
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
161
if (op->args[4] == TCG_COND_NE) {
162
/* Simplify NE comparisons where one of the pairs
163
can be simplified. */
164
- tmp = do_constant_folding_cond(INDEX_op_brcond_i32,
165
- op->args[0], op->args[2],
166
- TCG_COND_NE);
167
- if (tmp == 0) {
168
+ i = do_constant_folding_cond(INDEX_op_brcond_i32,
169
+ op->args[0], op->args[2],
170
+ TCG_COND_NE);
171
+ if (i == 0) {
172
goto do_brcond_high;
173
- } else if (tmp == 1) {
174
+ } else if (i > 0) {
175
goto do_brcond_true;
176
}
177
- tmp = do_constant_folding_cond(INDEX_op_brcond_i32,
178
- op->args[1], op->args[3],
179
- TCG_COND_NE);
180
- if (tmp == 0) {
181
+ i = do_constant_folding_cond(INDEX_op_brcond_i32,
182
+ op->args[1], op->args[3],
183
+ TCG_COND_NE);
184
+ if (i == 0) {
185
goto do_brcond_low;
186
- } else if (tmp == 1) {
187
+ } else if (i > 0) {
188
goto do_brcond_true;
189
}
190
}
191
break;
192
193
case INDEX_op_setcond2_i32:
194
- tmp = do_constant_folding_cond2(&op->args[1], &op->args[3],
195
- op->args[5]);
196
- if (tmp != 2) {
197
+ i = do_constant_folding_cond2(&op->args[1], &op->args[3],
198
+ op->args[5]);
199
+ if (i >= 0) {
200
do_setcond_const:
201
- tcg_opt_gen_movi(&ctx, op, op->args[0], tmp);
202
+ tcg_opt_gen_movi(&ctx, op, op->args[0], i);
203
continue;
204
}
205
if ((op->args[5] == TCG_COND_LT || op->args[5] == TCG_COND_GE)
206
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
207
if (op->args[5] == TCG_COND_EQ) {
208
/* Simplify EQ comparisons where one of the pairs
209
can be simplified. */
210
- tmp = do_constant_folding_cond(INDEX_op_setcond_i32,
211
- op->args[1], op->args[3],
212
- TCG_COND_EQ);
213
- if (tmp == 0) {
214
+ i = do_constant_folding_cond(INDEX_op_setcond_i32,
215
+ op->args[1], op->args[3],
216
+ TCG_COND_EQ);
217
+ if (i == 0) {
218
goto do_setcond_const;
219
- } else if (tmp == 1) {
220
+ } else if (i > 0) {
221
goto do_setcond_high;
222
}
223
- tmp = do_constant_folding_cond(INDEX_op_setcond_i32,
224
- op->args[2], op->args[4],
225
- TCG_COND_EQ);
226
- if (tmp == 0) {
227
+ i = do_constant_folding_cond(INDEX_op_setcond_i32,
228
+ op->args[2], op->args[4],
229
+ TCG_COND_EQ);
230
+ if (i == 0) {
231
goto do_setcond_high;
232
- } else if (tmp != 1) {
233
+ } else if (i < 0) {
234
break;
235
}
236
do_setcond_low:
237
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
238
if (op->args[5] == TCG_COND_NE) {
239
/* Simplify NE comparisons where one of the pairs
240
can be simplified. */
241
- tmp = do_constant_folding_cond(INDEX_op_setcond_i32,
242
- op->args[1], op->args[3],
243
- TCG_COND_NE);
244
- if (tmp == 0) {
245
+ i = do_constant_folding_cond(INDEX_op_setcond_i32,
246
+ op->args[1], op->args[3],
247
+ TCG_COND_NE);
248
+ if (i == 0) {
249
goto do_setcond_high;
250
- } else if (tmp == 1) {
251
+ } else if (i > 0) {
252
goto do_setcond_const;
253
}
254
- tmp = do_constant_folding_cond(INDEX_op_setcond_i32,
255
- op->args[2], op->args[4],
256
- TCG_COND_NE);
257
- if (tmp == 0) {
258
+ i = do_constant_folding_cond(INDEX_op_setcond_i32,
259
+ op->args[2], op->args[4],
260
+ TCG_COND_NE);
261
+ if (i == 0) {
262
goto do_setcond_low;
263
- } else if (tmp == 1) {
264
+ } else if (i > 0) {
265
goto do_setcond_const;
266
}
267
}
90
--
268
--
91
2.25.1
269
2.25.1
92
270
93
271
diff view generated by jsdifflib
[PATCH 15/27] tcg/tci: Remove tci_read_r16s
[PULL 16/56] tcg/optimize: Return true from tcg_opt_gen_{mov,movi}
1
Use explicit casts for ext16s opcodes.
1
This will allow callers to tail call to these functions
2
and return true indicating processing complete.
2
3
4
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
5
Reviewed-by: Luis Pires <luis.pires@eldorado.org.br>
3
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
6
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
---
8
---
6
tcg/tci.c | 26 ++++----------------------
9
tcg/optimize.c | 9 +++++----
7
1 file changed, 4 insertions(+), 22 deletions(-)
10
1 file changed, 5 insertions(+), 4 deletions(-)
8
11
9
diff --git a/tcg/tci.c b/tcg/tci.c
12
diff --git a/tcg/optimize.c b/tcg/optimize.c
10
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
11
--- a/tcg/tci.c
14
--- a/tcg/optimize.c
12
+++ b/tcg/tci.c
15
+++ b/tcg/optimize.c
13
@@ -XXX,XX +XXX,XX @@ static tcg_target_ulong tci_read_reg(const tcg_target_ulong *regs, TCGReg index)
16
@@ -XXX,XX +XXX,XX @@ static bool args_are_copies(TCGArg arg1, TCGArg arg2)
14
return regs[index];
17
return ts_are_copies(arg_temp(arg1), arg_temp(arg2));
15
}
18
}
16
19
17
-#if TCG_TARGET_HAS_ext16s_i32 || TCG_TARGET_HAS_ext16s_i64
20
-static void tcg_opt_gen_mov(OptContext *ctx, TCGOp *op, TCGArg dst, TCGArg src)
18
-static int16_t tci_read_reg16s(const tcg_target_ulong *regs, TCGReg index)
21
+static bool tcg_opt_gen_mov(OptContext *ctx, TCGOp *op, TCGArg dst, TCGArg src)
19
-{
20
- return (int16_t)tci_read_reg(regs, index);
21
-}
22
-#endif
23
-
24
#if TCG_TARGET_REG_BITS == 64
25
static int32_t tci_read_reg32s(const tcg_target_ulong *regs, TCGReg index)
26
{
22
{
27
@@ -XXX,XX +XXX,XX @@ tci_read_r(const tcg_target_ulong *regs, const uint8_t **tb_ptr)
23
TCGTemp *dst_ts = arg_temp(dst);
28
return value;
24
TCGTemp *src_ts = arg_temp(src);
25
@@ -XXX,XX +XXX,XX @@ static void tcg_opt_gen_mov(OptContext *ctx, TCGOp *op, TCGArg dst, TCGArg src)
26
27
if (ts_are_copies(dst_ts, src_ts)) {
28
tcg_op_remove(ctx->tcg, op);
29
- return;
30
+ return true;
31
}
32
33
reset_ts(dst_ts);
34
@@ -XXX,XX +XXX,XX @@ static void tcg_opt_gen_mov(OptContext *ctx, TCGOp *op, TCGArg dst, TCGArg src)
35
di->is_const = si->is_const;
36
di->val = si->val;
37
}
38
+ return true;
29
}
39
}
30
40
31
-#if TCG_TARGET_HAS_ext16s_i32 || TCG_TARGET_HAS_ext16s_i64
41
-static void tcg_opt_gen_movi(OptContext *ctx, TCGOp *op,
32
-/* Read indexed register (16 bit signed) from bytecode. */
42
+static bool tcg_opt_gen_movi(OptContext *ctx, TCGOp *op,
33
-static int16_t tci_read_r16s(const tcg_target_ulong *regs,
43
TCGArg dst, uint64_t val)
34
- const uint8_t **tb_ptr)
44
{
35
-{
45
const TCGOpDef *def = &tcg_op_defs[op->opc];
36
- int16_t value = tci_read_reg16s(regs, **tb_ptr);
46
@@ -XXX,XX +XXX,XX @@ static void tcg_opt_gen_movi(OptContext *ctx, TCGOp *op,
37
- *tb_ptr += 1;
47
/* Convert movi to mov with constant temp. */
38
- return value;
48
tv = tcg_constant_internal(type, val);
39
-}
49
init_ts_info(ctx, tv);
40
-#endif
50
- tcg_opt_gen_mov(ctx, op, dst, temp_arg(tv));
41
-
51
+ return tcg_opt_gen_mov(ctx, op, dst, temp_arg(tv));
42
/* Read indexed register (32 bit) from bytecode. */
52
}
43
static uint32_t tci_read_r32(const tcg_target_ulong *regs,
53
44
const uint8_t **tb_ptr)
54
static uint64_t do_constant_folding_2(TCGOpcode op, uint64_t x, uint64_t y)
45
@@ -XXX,XX +XXX,XX @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
46
#if TCG_TARGET_HAS_ext16s_i32
47
case INDEX_op_ext16s_i32:
48
t0 = *tb_ptr++;
49
- t1 = tci_read_r16s(regs, &tb_ptr);
50
- tci_write_reg(regs, t0, t1);
51
+ t1 = tci_read_r(regs, &tb_ptr);
52
+ tci_write_reg(regs, t0, (int16_t)t1);
53
break;
54
#endif
55
#if TCG_TARGET_HAS_ext8u_i32
56
@@ -XXX,XX +XXX,XX @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
57
#if TCG_TARGET_HAS_ext16s_i64
58
case INDEX_op_ext16s_i64:
59
t0 = *tb_ptr++;
60
- t1 = tci_read_r16s(regs, &tb_ptr);
61
- tci_write_reg(regs, t0, t1);
62
+ t1 = tci_read_r(regs, &tb_ptr);
63
+ tci_write_reg(regs, t0, (int16_t)t1);
64
break;
65
#endif
66
#if TCG_TARGET_HAS_ext16u_i64
67
--
55
--
68
2.25.1
56
2.25.1
69
57
70
58
diff view generated by jsdifflib
New patch
[PULL 17/56] tcg/optimize: Split out finish_folding
1
Copy z_mask into OptContext, for writeback to the
2
first output within the new function.
1
3
4
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
5
Reviewed-by: Luis Pires <luis.pires@eldorado.org.br>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
---
8
tcg/optimize.c | 49 +++++++++++++++++++++++++++++++++----------------
9
1 file changed, 33 insertions(+), 16 deletions(-)
10
11
diff --git a/tcg/optimize.c b/tcg/optimize.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/tcg/optimize.c
14
+++ b/tcg/optimize.c
15
@@ -XXX,XX +XXX,XX @@ typedef struct OptContext {
16
TCGContext *tcg;
17
TCGOp *prev_mb;
18
TCGTempSet temps_used;
19
+
20
+ /* In flight values from optimization. */
21
+ uint64_t z_mask;
22
} OptContext;
23
24
static inline TempOptInfo *ts_info(TCGTemp *ts)
25
@@ -XXX,XX +XXX,XX @@ static void copy_propagate(OptContext *ctx, TCGOp *op,
26
}
27
}
28
29
+static void finish_folding(OptContext *ctx, TCGOp *op)
30
+{
31
+ const TCGOpDef *def = &tcg_op_defs[op->opc];
32
+ int i, nb_oargs;
33
+
34
+ /*
35
+ * For an opcode that ends a BB, reset all temp data.
36
+ * We do no cross-BB optimization.
37
+ */
38
+ if (def->flags & TCG_OPF_BB_END) {
39
+ memset(&ctx->temps_used, 0, sizeof(ctx->temps_used));
40
+ ctx->prev_mb = NULL;
41
+ return;
42
+ }
43
+
44
+ nb_oargs = def->nb_oargs;
45
+ for (i = 0; i < nb_oargs; i++) {
46
+ reset_temp(op->args[i]);
47
+ /*
48
+ * Save the corresponding known-zero bits mask for the
49
+ * first output argument (only one supported so far).
50
+ */
51
+ if (i == 0) {
52
+ arg_info(op->args[i])->z_mask = ctx->z_mask;
53
+ }
54
+ }
55
+}
56
+
57
static bool fold_call(OptContext *ctx, TCGOp *op)
58
{
59
TCGContext *s = ctx->tcg;
60
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
61
partmask &= 0xffffffffu;
62
affected &= 0xffffffffu;
63
}
64
+ ctx.z_mask = z_mask;
65
66
if (partmask == 0) {
67
tcg_opt_gen_movi(&ctx, op, op->args[0], 0);
68
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
69
break;
70
}
71
72
- /* Some of the folding above can change opc. */
73
- opc = op->opc;
74
- def = &tcg_op_defs[opc];
75
- if (def->flags & TCG_OPF_BB_END) {
76
- memset(&ctx.temps_used, 0, sizeof(ctx.temps_used));
77
- } else {
78
- int nb_oargs = def->nb_oargs;
79
- for (i = 0; i < nb_oargs; i++) {
80
- reset_temp(op->args[i]);
81
- /* Save the corresponding known-zero bits mask for the
82
- first output argument (only one supported so far). */
83
- if (i == 0) {
84
- arg_info(op->args[i])->z_mask = z_mask;
85
- }
86
- }
87
- }
88
+ finish_folding(&ctx, op);
89
90
/* Eliminate duplicate and redundant fence instructions. */
91
if (ctx.prev_mb) {
92
--
93
2.25.1
94
95
diff view generated by jsdifflib
New patch
[PULL 18/56] tcg/optimize: Use a boolean to avoid a mass of continues
1
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
2
Reviewed-by: Luis Pires <luis.pires@eldorado.org.br>
3
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
---
6
tcg/optimize.c | 9 ++++++---
7
1 file changed, 6 insertions(+), 3 deletions(-)
1
8
9
diff --git a/tcg/optimize.c b/tcg/optimize.c
10
index XXXXXXX..XXXXXXX 100644
11
--- a/tcg/optimize.c
12
+++ b/tcg/optimize.c
13
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
14
uint64_t z_mask, partmask, affected, tmp;
15
TCGOpcode opc = op->opc;
16
const TCGOpDef *def;
17
+ bool done = false;
18
19
/* Calls are special. */
20
if (opc == INDEX_op_call) {
21
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
22
allocator where needed and possible. Also detect copies. */
23
switch (opc) {
24
CASE_OP_32_64_VEC(mov):
25
- tcg_opt_gen_mov(&ctx, op, op->args[0], op->args[1]);
26
- continue;
27
+ done = tcg_opt_gen_mov(&ctx, op, op->args[0], op->args[1]);
28
+ break;
29
30
case INDEX_op_dup_vec:
31
if (arg_is_const(op->args[1])) {
32
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
33
break;
34
}
35
36
- finish_folding(&ctx, op);
37
+ if (!done) {
38
+ finish_folding(&ctx, op);
39
+ }
40
41
/* Eliminate duplicate and redundant fence instructions. */
42
if (ctx.prev_mb) {
43
--
44
2.25.1
45
46
diff view generated by jsdifflib
[PATCH 19/27] tcg/tci: Merge basic arithmetic operations
[PULL 19/56] tcg/optimize: Split out fold_mb, fold_qemu_{ld,st}
1
This includes add, sub, mul, and, or, xor.
1
This puts the separate mb optimization into the same framework
2
as the others. While fold_qemu_{ld,st} are currently identical,
3
that won't last as more code gets moved.
2
4
5
Reviewed-by: Luis Pires <luis.pires@eldorado.org.br>
3
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
6
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
---
8
---
6
tcg/tci.c | 83 +++++++++++++++++--------------------------------------
9
tcg/optimize.c | 89 +++++++++++++++++++++++++++++---------------------
7
1 file changed, 25 insertions(+), 58 deletions(-)
10
1 file changed, 51 insertions(+), 38 deletions(-)
8
11
9
diff --git a/tcg/tci.c b/tcg/tci.c
12
diff --git a/tcg/optimize.c b/tcg/optimize.c
10
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
11
--- a/tcg/tci.c
14
--- a/tcg/optimize.c
12
+++ b/tcg/tci.c
15
+++ b/tcg/optimize.c
13
@@ -XXX,XX +XXX,XX @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
16
@@ -XXX,XX +XXX,XX @@ static bool fold_call(OptContext *ctx, TCGOp *op)
14
*(uint32_t *)(t1 + t2) = t0;
17
return true;
18
}
19
20
+static bool fold_mb(OptContext *ctx, TCGOp *op)
21
+{
22
+ /* Eliminate duplicate and redundant fence instructions. */
23
+ if (ctx->prev_mb) {
24
+ /*
25
+ * Merge two barriers of the same type into one,
26
+ * or a weaker barrier into a stronger one,
27
+ * or two weaker barriers into a stronger one.
28
+ * mb X; mb Y => mb X|Y
29
+ * mb; strl => mb; st
30
+ * ldaq; mb => ld; mb
31
+ * ldaq; strl => ld; mb; st
32
+ * Other combinations are also merged into a strong
33
+ * barrier. This is stricter than specified but for
34
+ * the purposes of TCG is better than not optimizing.
35
+ */
36
+ ctx->prev_mb->args[0] |= op->args[0];
37
+ tcg_op_remove(ctx->tcg, op);
38
+ } else {
39
+ ctx->prev_mb = op;
40
+ }
41
+ return true;
42
+}
43
+
44
+static bool fold_qemu_ld(OptContext *ctx, TCGOp *op)
45
+{
46
+ /* Opcodes that touch guest memory stop the mb optimization. */
47
+ ctx->prev_mb = NULL;
48
+ return false;
49
+}
50
+
51
+static bool fold_qemu_st(OptContext *ctx, TCGOp *op)
52
+{
53
+ /* Opcodes that touch guest memory stop the mb optimization. */
54
+ ctx->prev_mb = NULL;
55
+ return false;
56
+}
57
+
58
/* Propagate constants and copies, fold constant expressions. */
59
void tcg_optimize(TCGContext *s)
60
{
61
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
62
}
15
break;
63
break;
16
64
17
- /* Arithmetic operations (32 bit). */
65
+ case INDEX_op_mb:
18
+ /* Arithmetic operations (mixed 32/64 bit). */
66
+ done = fold_mb(&ctx, op);
19
20
- case INDEX_op_add_i32:
21
+ CASE_32_64(add)
22
t0 = *tb_ptr++;
23
t1 = tci_read_r(regs, &tb_ptr);
24
t2 = tci_read_r(regs, &tb_ptr);
25
tci_write_reg(regs, t0, t1 + t2);
26
break;
27
- case INDEX_op_sub_i32:
28
+ CASE_32_64(sub)
29
t0 = *tb_ptr++;
30
t1 = tci_read_r(regs, &tb_ptr);
31
t2 = tci_read_r(regs, &tb_ptr);
32
tci_write_reg(regs, t0, t1 - t2);
33
break;
34
- case INDEX_op_mul_i32:
35
+ CASE_32_64(mul)
36
t0 = *tb_ptr++;
37
t1 = tci_read_r(regs, &tb_ptr);
38
t2 = tci_read_r(regs, &tb_ptr);
39
tci_write_reg(regs, t0, t1 * t2);
40
break;
41
+ CASE_32_64(and)
42
+ t0 = *tb_ptr++;
43
+ t1 = tci_read_r(regs, &tb_ptr);
44
+ t2 = tci_read_r(regs, &tb_ptr);
45
+ tci_write_reg(regs, t0, t1 & t2);
46
+ break;
67
+ break;
47
+ CASE_32_64(or)
68
+ case INDEX_op_qemu_ld_i32:
48
+ t0 = *tb_ptr++;
69
+ case INDEX_op_qemu_ld_i64:
49
+ t1 = tci_read_r(regs, &tb_ptr);
70
+ done = fold_qemu_ld(&ctx, op);
50
+ t2 = tci_read_r(regs, &tb_ptr);
51
+ tci_write_reg(regs, t0, t1 | t2);
52
+ break;
71
+ break;
53
+ CASE_32_64(xor)
72
+ case INDEX_op_qemu_st_i32:
54
+ t0 = *tb_ptr++;
73
+ case INDEX_op_qemu_st8_i32:
55
+ t1 = tci_read_r(regs, &tb_ptr);
74
+ case INDEX_op_qemu_st_i64:
56
+ t2 = tci_read_r(regs, &tb_ptr);
75
+ done = fold_qemu_st(&ctx, op);
57
+ tci_write_reg(regs, t0, t1 ^ t2);
58
+ break;
76
+ break;
59
+
77
+
60
+ /* Arithmetic operations (32 bit). */
78
default:
61
+
62
case INDEX_op_div_i32:
63
t0 = *tb_ptr++;
64
t1 = tci_read_r(regs, &tb_ptr);
65
@@ -XXX,XX +XXX,XX @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
66
t2 = tci_read_r(regs, &tb_ptr);
67
tci_write_reg(regs, t0, (uint32_t)t1 % (uint32_t)t2);
68
break;
79
break;
69
- case INDEX_op_and_i32:
80
}
70
- t0 = *tb_ptr++;
81
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
71
- t1 = tci_read_r(regs, &tb_ptr);
82
if (!done) {
72
- t2 = tci_read_r(regs, &tb_ptr);
83
finish_folding(&ctx, op);
73
- tci_write_reg(regs, t0, t1 & t2);
84
}
74
- break;
85
-
75
- case INDEX_op_or_i32:
86
- /* Eliminate duplicate and redundant fence instructions. */
76
- t0 = *tb_ptr++;
87
- if (ctx.prev_mb) {
77
- t1 = tci_read_r(regs, &tb_ptr);
88
- switch (opc) {
78
- t2 = tci_read_r(regs, &tb_ptr);
89
- case INDEX_op_mb:
79
- tci_write_reg(regs, t0, t1 | t2);
90
- /* Merge two barriers of the same type into one,
80
- break;
91
- * or a weaker barrier into a stronger one,
81
- case INDEX_op_xor_i32:
92
- * or two weaker barriers into a stronger one.
82
- t0 = *tb_ptr++;
93
- * mb X; mb Y => mb X|Y
83
- t1 = tci_read_r(regs, &tb_ptr);
94
- * mb; strl => mb; st
84
- t2 = tci_read_r(regs, &tb_ptr);
95
- * ldaq; mb => ld; mb
85
- tci_write_reg(regs, t0, t1 ^ t2);
96
- * ldaq; strl => ld; mb; st
86
- break;
97
- * Other combinations are also merged into a strong
87
98
- * barrier. This is stricter than specified but for
88
/* Shift/rotate operations (32 bit). */
99
- * the purposes of TCG is better than not optimizing.
89
100
- */
90
@@ -XXX,XX +XXX,XX @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
101
- ctx.prev_mb->args[0] |= op->args[0];
91
102
- tcg_op_remove(s, op);
92
/* Arithmetic operations (64 bit). */
103
- break;
93
104
-
94
- case INDEX_op_add_i64:
105
- default:
95
- t0 = *tb_ptr++;
106
- /* Opcodes that end the block stop the optimization. */
96
- t1 = tci_read_r(regs, &tb_ptr);
107
- if ((def->flags & TCG_OPF_BB_END) == 0) {
97
- t2 = tci_read_r(regs, &tb_ptr);
108
- break;
98
- tci_write_reg(regs, t0, t1 + t2);
109
- }
99
- break;
110
- /* fallthru */
100
- case INDEX_op_sub_i64:
111
- case INDEX_op_qemu_ld_i32:
101
- t0 = *tb_ptr++;
112
- case INDEX_op_qemu_ld_i64:
102
- t1 = tci_read_r(regs, &tb_ptr);
113
- case INDEX_op_qemu_st_i32:
103
- t2 = tci_read_r(regs, &tb_ptr);
114
- case INDEX_op_qemu_st8_i32:
104
- tci_write_reg(regs, t0, t1 - t2);
115
- case INDEX_op_qemu_st_i64:
105
- break;
116
- /* Opcodes that touch guest memory stop the optimization. */
106
- case INDEX_op_mul_i64:
117
- ctx.prev_mb = NULL;
107
- t0 = *tb_ptr++;
118
- break;
108
- t1 = tci_read_r(regs, &tb_ptr);
119
- }
109
- t2 = tci_read_r(regs, &tb_ptr);
120
- } else if (opc == INDEX_op_mb) {
110
- tci_write_reg(regs, t0, t1 * t2);
121
- ctx.prev_mb = op;
111
- break;
122
- }
112
case INDEX_op_div_i64:
123
}
113
t0 = *tb_ptr++;
124
}
114
t1 = tci_read_r(regs, &tb_ptr);
115
@@ -XXX,XX +XXX,XX @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
116
t2 = tci_read_r(regs, &tb_ptr);
117
tci_write_reg(regs, t0, (uint64_t)t1 % (uint64_t)t2);
118
break;
119
- case INDEX_op_and_i64:
120
- t0 = *tb_ptr++;
121
- t1 = tci_read_r(regs, &tb_ptr);
122
- t2 = tci_read_r(regs, &tb_ptr);
123
- tci_write_reg(regs, t0, t1 & t2);
124
- break;
125
- case INDEX_op_or_i64:
126
- t0 = *tb_ptr++;
127
- t1 = tci_read_r(regs, &tb_ptr);
128
- t2 = tci_read_r(regs, &tb_ptr);
129
- tci_write_reg(regs, t0, t1 | t2);
130
- break;
131
- case INDEX_op_xor_i64:
132
- t0 = *tb_ptr++;
133
- t1 = tci_read_r(regs, &tb_ptr);
134
- t2 = tci_read_r(regs, &tb_ptr);
135
- tci_write_reg(regs, t0, t1 ^ t2);
136
- break;
137
138
/* Shift/rotate operations (64 bit). */
139
140
--
125
--
141
2.25.1
126
2.25.1
142
127
143
128
diff view generated by jsdifflib
[PATCH 25/27] accel/tcg: drop the use of CF_HASH_MASK and rename params
[PULL 20/56] tcg/optimize: Split out fold_const{1,2}
1
From: Alex Bennée <alex.bennee@linaro.org>
1
Split out a whole bunch of placeholder functions, which are
2
2
currently identical. That won't last as more code gets moved.
3
We don't really deal in cf_mask most of the time. The one time it's
3
4
relevant is when we want to remove an invalidated TB from the QHT
4
Use CASE_32_64_VEC for some logical operators that previously
5
lookup. Everywhere else we should be looking up things without
5
missed the addition of vectors.
6
CF_INVALID set.
6
7
7
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
8
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
8
Reviewed-by: Luis Pires <luis.pires@eldorado.org.br>
9
Message-Id: <20210224165811.11567-4-alex.bennee@linaro.org>
10
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
11
---
10
---
12
include/exec/exec-all.h | 4 +---
11
tcg/optimize.c | 271 +++++++++++++++++++++++++++++++++++++++----------
13
include/exec/tb-lookup.h | 9 ++++++---
12
1 file changed, 219 insertions(+), 52 deletions(-)
14
accel/tcg/cpu-exec.c | 16 ++++++++--------
13
15
accel/tcg/tcg-runtime.c | 2 +-
14
diff --git a/tcg/optimize.c b/tcg/optimize.c
16
accel/tcg/translate-all.c | 8 +++++---
17
5 files changed, 21 insertions(+), 18 deletions(-)
18
19
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
20
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
21
--- a/include/exec/exec-all.h
16
--- a/tcg/optimize.c
22
+++ b/include/exec/exec-all.h
17
+++ b/tcg/optimize.c
23
@@ -XXX,XX +XXX,XX @@ struct TranslationBlock {
18
@@ -XXX,XX +XXX,XX @@ static void finish_folding(OptContext *ctx, TCGOp *op)
24
#define CF_PARALLEL 0x00080000 /* Generate code for a parallel context */
19
}
25
#define CF_CLUSTER_MASK 0xff000000 /* Top 8 bits are cluster ID */
20
}
26
#define CF_CLUSTER_SHIFT 24
21
27
-/* cflags' mask for hashing/comparison, basically ignore CF_INVALID */
22
+/*
28
-#define CF_HASH_MASK (~CF_INVALID)
23
+ * The fold_* functions return true when processing is complete,
29
24
+ * usually by folding the operation to a constant or to a copy,
30
/* Per-vCPU dynamic tracing state used to generate this TB */
25
+ * and calling tcg_opt_gen_{mov,movi}. They may do other things,
31
uint32_t trace_vcpu_dstate;
26
+ * like collect information about the value produced, for use in
32
@@ -XXX,XX +XXX,XX @@ void tb_flush(CPUState *cpu);
27
+ * optimizing a subsequent operation.
33
void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr);
28
+ *
34
TranslationBlock *tb_htable_lookup(CPUState *cpu, target_ulong pc,
29
+ * These first fold_* functions are all helpers, used by other
35
target_ulong cs_base, uint32_t flags,
30
+ * folders for more specific operations.
36
- uint32_t cf_mask);
31
+ */
37
+ uint32_t cflags);
32
+
38
void tb_set_jmp_target(TranslationBlock *tb, int n, uintptr_t addr);
33
+static bool fold_const1(OptContext *ctx, TCGOp *op)
39
34
+{
40
/* GETPC is the true target of the return instruction that we'll execute. */
35
+ if (arg_is_const(op->args[1])) {
41
diff --git a/include/exec/tb-lookup.h b/include/exec/tb-lookup.h
36
+ uint64_t t;
42
index XXXXXXX..XXXXXXX 100644
37
+
43
--- a/include/exec/tb-lookup.h
38
+ t = arg_info(op->args[1])->val;
44
+++ b/include/exec/tb-lookup.h
39
+ t = do_constant_folding(op->opc, t, 0);
45
@@ -XXX,XX +XXX,XX @@
40
+ return tcg_opt_gen_movi(ctx, op, op->args[0], t);
46
/* Might cause an exception, so have a longjmp destination ready */
41
+ }
47
static inline TranslationBlock * tb_lookup(CPUState *cpu,
42
+ return false;
48
target_ulong pc, target_ulong cs_base,
43
+}
49
- uint32_t flags, uint32_t cf_mask)
44
+
50
+ uint32_t flags, uint32_t cflags)
45
+static bool fold_const2(OptContext *ctx, TCGOp *op)
46
+{
47
+ if (arg_is_const(op->args[1]) && arg_is_const(op->args[2])) {
48
+ uint64_t t1 = arg_info(op->args[1])->val;
49
+ uint64_t t2 = arg_info(op->args[2])->val;
50
+
51
+ t1 = do_constant_folding(op->opc, t1, t2);
52
+ return tcg_opt_gen_movi(ctx, op, op->args[0], t1);
53
+ }
54
+ return false;
55
+}
56
+
57
+/*
58
+ * These outermost fold_<op> functions are sorted alphabetically.
59
+ */
60
+
61
+static bool fold_add(OptContext *ctx, TCGOp *op)
62
+{
63
+ return fold_const2(ctx, op);
64
+}
65
+
66
+static bool fold_and(OptContext *ctx, TCGOp *op)
67
+{
68
+ return fold_const2(ctx, op);
69
+}
70
+
71
+static bool fold_andc(OptContext *ctx, TCGOp *op)
72
+{
73
+ return fold_const2(ctx, op);
74
+}
75
+
76
static bool fold_call(OptContext *ctx, TCGOp *op)
51
{
77
{
52
TranslationBlock *tb;
78
TCGContext *s = ctx->tcg;
53
uint32_t hash;
79
@@ -XXX,XX +XXX,XX @@ static bool fold_call(OptContext *ctx, TCGOp *op)
54
80
return true;
55
+ /* we should never be trying to look up an INVALID tb */
81
}
56
+ tcg_debug_assert(!(cflags & CF_INVALID));
82
57
+
83
+static bool fold_ctpop(OptContext *ctx, TCGOp *op)
58
hash = tb_jmp_cache_hash_func(pc);
84
+{
59
tb = qatomic_rcu_read(&cpu->tb_jmp_cache[hash]);
85
+ return fold_const1(ctx, op);
60
86
+}
61
@@ -XXX,XX +XXX,XX @@ static inline TranslationBlock * tb_lookup(CPUState *cpu,
87
+
62
tb->cs_base == cs_base &&
88
+static bool fold_divide(OptContext *ctx, TCGOp *op)
63
tb->flags == flags &&
89
+{
64
tb->trace_vcpu_dstate == *cpu->trace_dstate &&
90
+ return fold_const2(ctx, op);
65
- (tb_cflags(tb) & (CF_HASH_MASK | CF_INVALID)) == cf_mask)) {
91
+}
66
+ tb_cflags(tb) == cflags)) {
92
+
67
return tb;
93
+static bool fold_eqv(OptContext *ctx, TCGOp *op)
68
}
94
+{
69
- tb = tb_htable_lookup(cpu, pc, cs_base, flags, cf_mask);
95
+ return fold_const2(ctx, op);
70
+ tb = tb_htable_lookup(cpu, pc, cs_base, flags, cflags);
96
+}
71
if (tb == NULL) {
97
+
72
return NULL;
98
+static bool fold_exts(OptContext *ctx, TCGOp *op)
73
}
99
+{
74
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
100
+ return fold_const1(ctx, op);
75
index XXXXXXX..XXXXXXX 100644
101
+}
76
--- a/accel/tcg/cpu-exec.c
102
+
77
+++ b/accel/tcg/cpu-exec.c
103
+static bool fold_extu(OptContext *ctx, TCGOp *op)
78
@@ -XXX,XX +XXX,XX @@ struct tb_desc {
104
+{
79
CPUArchState *env;
105
+ return fold_const1(ctx, op);
80
tb_page_addr_t phys_page1;
106
+}
81
uint32_t flags;
107
+
82
- uint32_t cf_mask;
108
static bool fold_mb(OptContext *ctx, TCGOp *op)
83
+ uint32_t cflags;
84
uint32_t trace_vcpu_dstate;
85
};
86
87
@@ -XXX,XX +XXX,XX @@ static bool tb_lookup_cmp(const void *p, const void *d)
88
tb->cs_base == desc->cs_base &&
89
tb->flags == desc->flags &&
90
tb->trace_vcpu_dstate == desc->trace_vcpu_dstate &&
91
- (tb_cflags(tb) & (CF_HASH_MASK | CF_INVALID)) == desc->cf_mask) {
92
+ tb_cflags(tb) == desc->cflags) {
93
/* check next page if needed */
94
if (tb->page_addr[1] == -1) {
95
return true;
96
@@ -XXX,XX +XXX,XX @@ static bool tb_lookup_cmp(const void *p, const void *d)
97
98
TranslationBlock *tb_htable_lookup(CPUState *cpu, target_ulong pc,
99
target_ulong cs_base, uint32_t flags,
100
- uint32_t cf_mask)
101
+ uint32_t cflags)
102
{
109
{
103
tb_page_addr_t phys_pc;
110
/* Eliminate duplicate and redundant fence instructions. */
104
struct tb_desc desc;
111
@@ -XXX,XX +XXX,XX @@ static bool fold_mb(OptContext *ctx, TCGOp *op)
105
@@ -XXX,XX +XXX,XX @@ TranslationBlock *tb_htable_lookup(CPUState *cpu, target_ulong pc,
112
return true;
106
desc.env = (CPUArchState *)cpu->env_ptr;
107
desc.cs_base = cs_base;
108
desc.flags = flags;
109
- desc.cf_mask = cf_mask;
110
+ desc.cflags = cflags;
111
desc.trace_vcpu_dstate = *cpu->trace_dstate;
112
desc.pc = pc;
113
phys_pc = get_page_addr_code(desc.env, pc);
114
@@ -XXX,XX +XXX,XX @@ TranslationBlock *tb_htable_lookup(CPUState *cpu, target_ulong pc,
115
return NULL;
116
}
117
desc.phys_page1 = phys_pc & TARGET_PAGE_MASK;
118
- h = tb_hash_func(phys_pc, pc, flags, cf_mask, *cpu->trace_dstate);
119
+ h = tb_hash_func(phys_pc, pc, flags, cflags, *cpu->trace_dstate);
120
return qht_lookup_custom(&tb_ctx.htable, &desc, h, tb_lookup_cmp);
121
}
113
}
122
114
123
@@ -XXX,XX +XXX,XX @@ static inline void tb_add_jump(TranslationBlock *tb, int n,
115
+static bool fold_mul(OptContext *ctx, TCGOp *op)
124
116
+{
125
static inline TranslationBlock *tb_find(CPUState *cpu,
117
+ return fold_const2(ctx, op);
126
TranslationBlock *last_tb,
118
+}
127
- int tb_exit, uint32_t cf_mask)
119
+
128
+ int tb_exit, uint32_t cflags)
120
+static bool fold_mul_highpart(OptContext *ctx, TCGOp *op)
121
+{
122
+ return fold_const2(ctx, op);
123
+}
124
+
125
+static bool fold_nand(OptContext *ctx, TCGOp *op)
126
+{
127
+ return fold_const2(ctx, op);
128
+}
129
+
130
+static bool fold_neg(OptContext *ctx, TCGOp *op)
131
+{
132
+ return fold_const1(ctx, op);
133
+}
134
+
135
+static bool fold_nor(OptContext *ctx, TCGOp *op)
136
+{
137
+ return fold_const2(ctx, op);
138
+}
139
+
140
+static bool fold_not(OptContext *ctx, TCGOp *op)
141
+{
142
+ return fold_const1(ctx, op);
143
+}
144
+
145
+static bool fold_or(OptContext *ctx, TCGOp *op)
146
+{
147
+ return fold_const2(ctx, op);
148
+}
149
+
150
+static bool fold_orc(OptContext *ctx, TCGOp *op)
151
+{
152
+ return fold_const2(ctx, op);
153
+}
154
+
155
static bool fold_qemu_ld(OptContext *ctx, TCGOp *op)
129
{
156
{
130
CPUArchState *env = (CPUArchState *)cpu->env_ptr;
157
/* Opcodes that touch guest memory stop the mb optimization. */
131
TranslationBlock *tb;
158
@@ -XXX,XX +XXX,XX @@ static bool fold_qemu_st(OptContext *ctx, TCGOp *op)
132
@@ -XXX,XX +XXX,XX @@ static inline TranslationBlock *tb_find(CPUState *cpu,
159
return false;
133
160
}
134
cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags);
161
135
162
+static bool fold_remainder(OptContext *ctx, TCGOp *op)
136
- tb = tb_lookup(cpu, pc, cs_base, flags, cf_mask);
163
+{
137
+ tb = tb_lookup(cpu, pc, cs_base, flags, cflags);
164
+ return fold_const2(ctx, op);
138
if (tb == NULL) {
165
+}
139
mmap_lock();
166
+
140
- tb = tb_gen_code(cpu, pc, cs_base, flags, cf_mask);
167
+static bool fold_shift(OptContext *ctx, TCGOp *op)
141
+ tb = tb_gen_code(cpu, pc, cs_base, flags, cflags);
168
+{
142
mmap_unlock();
169
+ return fold_const2(ctx, op);
143
/* We add the TB in the virtual pc hash table for the fast lookup */
170
+}
144
qatomic_set(&cpu->tb_jmp_cache[tb_jmp_cache_hash_func(pc)], tb);
171
+
145
diff --git a/accel/tcg/tcg-runtime.c b/accel/tcg/tcg-runtime.c
172
+static bool fold_sub(OptContext *ctx, TCGOp *op)
146
index XXXXXXX..XXXXXXX 100644
173
+{
147
--- a/accel/tcg/tcg-runtime.c
174
+ return fold_const2(ctx, op);
148
+++ b/accel/tcg/tcg-runtime.c
175
+}
149
@@ -XXX,XX +XXX,XX @@
176
+
150
#include "exec/helper-proto.h"
177
+static bool fold_xor(OptContext *ctx, TCGOp *op)
151
#include "exec/cpu_ldst.h"
178
+{
152
#include "exec/exec-all.h"
179
+ return fold_const2(ctx, op);
153
-#include "exec/tb-lookup.h"
180
+}
154
#include "disas/disas.h"
181
+
155
#include "exec/log.h"
182
/* Propagate constants and copies, fold constant expressions. */
156
#include "tcg/tcg.h"
183
void tcg_optimize(TCGContext *s)
157
+#include "exec/tb-lookup.h"
184
{
158
185
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
159
/* 32-bit helpers */
186
}
160
187
break;
161
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
188
162
index XXXXXXX..XXXXXXX 100644
189
- CASE_OP_32_64(not):
163
--- a/accel/tcg/translate-all.c
190
- CASE_OP_32_64(neg):
164
+++ b/accel/tcg/translate-all.c
191
- CASE_OP_32_64(ext8s):
165
@@ -XXX,XX +XXX,XX @@ static bool tb_cmp(const void *ap, const void *bp)
192
- CASE_OP_32_64(ext8u):
166
return a->pc == b->pc &&
193
- CASE_OP_32_64(ext16s):
167
a->cs_base == b->cs_base &&
194
- CASE_OP_32_64(ext16u):
168
a->flags == b->flags &&
195
- CASE_OP_32_64(ctpop):
169
- (tb_cflags(a) & CF_HASH_MASK) == (tb_cflags(b) & CF_HASH_MASK) &&
196
- case INDEX_op_ext32s_i64:
170
+ (tb_cflags(a) & ~CF_INVALID) == (tb_cflags(b) & ~CF_INVALID) &&
197
- case INDEX_op_ext32u_i64:
171
a->trace_vcpu_dstate == b->trace_vcpu_dstate &&
198
- case INDEX_op_ext_i32_i64:
172
a->page_addr[0] == b->page_addr[0] &&
199
- case INDEX_op_extu_i32_i64:
173
a->page_addr[1] == b->page_addr[1];
200
- case INDEX_op_extrl_i64_i32:
174
@@ -XXX,XX +XXX,XX @@ static void do_tb_phys_invalidate(TranslationBlock *tb, bool rm_from_page_list)
201
- case INDEX_op_extrh_i64_i32:
175
PageDesc *p;
202
- if (arg_is_const(op->args[1])) {
176
uint32_t h;
203
- tmp = do_constant_folding(opc, arg_info(op->args[1])->val, 0);
177
tb_page_addr_t phys_pc;
204
- tcg_opt_gen_movi(&ctx, op, op->args[0], tmp);
178
+ uint32_t orig_cflags = tb_cflags(tb);
205
- continue;
179
206
- }
180
assert_memory_lock();
207
- break;
181
208
-
182
@@ -XXX,XX +XXX,XX @@ static void do_tb_phys_invalidate(TranslationBlock *tb, bool rm_from_page_list)
209
CASE_OP_32_64(bswap16):
183
210
CASE_OP_32_64(bswap32):
184
/* remove the TB from the hash list */
211
case INDEX_op_bswap64_i64:
185
phys_pc = tb->page_addr[0] + (tb->pc & ~TARGET_PAGE_MASK);
212
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
186
- h = tb_hash_func(phys_pc, tb->pc, tb->flags, tb_cflags(tb) & CF_HASH_MASK,
213
}
187
+ h = tb_hash_func(phys_pc, tb->pc, tb->flags, orig_cflags,
214
break;
188
tb->trace_vcpu_dstate);
215
189
if (!qht_remove(&tb_ctx.htable, tb, h)) {
216
- CASE_OP_32_64(add):
190
return;
217
- CASE_OP_32_64(sub):
191
@@ -XXX,XX +XXX,XX @@ tb_link_page(TranslationBlock *tb, tb_page_addr_t phys_pc,
218
- CASE_OP_32_64(mul):
192
uint32_t h;
219
- CASE_OP_32_64(or):
193
220
- CASE_OP_32_64(and):
194
assert_memory_lock();
221
- CASE_OP_32_64(xor):
195
+ tcg_debug_assert(!(tb->cflags & CF_INVALID));
222
- CASE_OP_32_64(shl):
196
223
- CASE_OP_32_64(shr):
197
/*
224
- CASE_OP_32_64(sar):
198
* Add the TB to the page list, acquiring first the pages's locks.
225
- CASE_OP_32_64(rotl):
199
@@ -XXX,XX +XXX,XX @@ tb_link_page(TranslationBlock *tb, tb_page_addr_t phys_pc,
226
- CASE_OP_32_64(rotr):
200
}
227
- CASE_OP_32_64(andc):
201
228
- CASE_OP_32_64(orc):
202
/* add in the hash table */
229
- CASE_OP_32_64(eqv):
203
- h = tb_hash_func(phys_pc, tb->pc, tb->flags, tb->cflags & CF_HASH_MASK,
230
- CASE_OP_32_64(nand):
204
+ h = tb_hash_func(phys_pc, tb->pc, tb->flags, tb->cflags,
231
- CASE_OP_32_64(nor):
205
tb->trace_vcpu_dstate);
232
- CASE_OP_32_64(muluh):
206
qht_insert(&tb_ctx.htable, tb, h, &existing_tb);
233
- CASE_OP_32_64(mulsh):
234
- CASE_OP_32_64(div):
235
- CASE_OP_32_64(divu):
236
- CASE_OP_32_64(rem):
237
- CASE_OP_32_64(remu):
238
- if (arg_is_const(op->args[1]) && arg_is_const(op->args[2])) {
239
- tmp = do_constant_folding(opc, arg_info(op->args[1])->val,
240
- arg_info(op->args[2])->val);
241
- tcg_opt_gen_movi(&ctx, op, op->args[0], tmp);
242
- continue;
243
- }
244
- break;
245
-
246
CASE_OP_32_64(clz):
247
CASE_OP_32_64(ctz):
248
if (arg_is_const(op->args[1])) {
249
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
250
}
251
break;
252
253
+ default:
254
+ break;
255
+
256
+ /* ---------------------------------------------------------- */
257
+ /* Sorted alphabetically by opcode as much as possible. */
258
+
259
+ CASE_OP_32_64_VEC(add):
260
+ done = fold_add(&ctx, op);
261
+ break;
262
+ CASE_OP_32_64_VEC(and):
263
+ done = fold_and(&ctx, op);
264
+ break;
265
+ CASE_OP_32_64_VEC(andc):
266
+ done = fold_andc(&ctx, op);
267
+ break;
268
+ CASE_OP_32_64(ctpop):
269
+ done = fold_ctpop(&ctx, op);
270
+ break;
271
+ CASE_OP_32_64(div):
272
+ CASE_OP_32_64(divu):
273
+ done = fold_divide(&ctx, op);
274
+ break;
275
+ CASE_OP_32_64(eqv):
276
+ done = fold_eqv(&ctx, op);
277
+ break;
278
+ CASE_OP_32_64(ext8s):
279
+ CASE_OP_32_64(ext16s):
280
+ case INDEX_op_ext32s_i64:
281
+ case INDEX_op_ext_i32_i64:
282
+ done = fold_exts(&ctx, op);
283
+ break;
284
+ CASE_OP_32_64(ext8u):
285
+ CASE_OP_32_64(ext16u):
286
+ case INDEX_op_ext32u_i64:
287
+ case INDEX_op_extu_i32_i64:
288
+ case INDEX_op_extrl_i64_i32:
289
+ case INDEX_op_extrh_i64_i32:
290
+ done = fold_extu(&ctx, op);
291
+ break;
292
case INDEX_op_mb:
293
done = fold_mb(&ctx, op);
294
break;
295
+ CASE_OP_32_64(mul):
296
+ done = fold_mul(&ctx, op);
297
+ break;
298
+ CASE_OP_32_64(mulsh):
299
+ CASE_OP_32_64(muluh):
300
+ done = fold_mul_highpart(&ctx, op);
301
+ break;
302
+ CASE_OP_32_64(nand):
303
+ done = fold_nand(&ctx, op);
304
+ break;
305
+ CASE_OP_32_64(neg):
306
+ done = fold_neg(&ctx, op);
307
+ break;
308
+ CASE_OP_32_64(nor):
309
+ done = fold_nor(&ctx, op);
310
+ break;
311
+ CASE_OP_32_64_VEC(not):
312
+ done = fold_not(&ctx, op);
313
+ break;
314
+ CASE_OP_32_64_VEC(or):
315
+ done = fold_or(&ctx, op);
316
+ break;
317
+ CASE_OP_32_64_VEC(orc):
318
+ done = fold_orc(&ctx, op);
319
+ break;
320
case INDEX_op_qemu_ld_i32:
321
case INDEX_op_qemu_ld_i64:
322
done = fold_qemu_ld(&ctx, op);
323
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
324
case INDEX_op_qemu_st_i64:
325
done = fold_qemu_st(&ctx, op);
326
break;
327
-
328
- default:
329
+ CASE_OP_32_64(rem):
330
+ CASE_OP_32_64(remu):
331
+ done = fold_remainder(&ctx, op);
332
+ break;
333
+ CASE_OP_32_64(rotl):
334
+ CASE_OP_32_64(rotr):
335
+ CASE_OP_32_64(sar):
336
+ CASE_OP_32_64(shl):
337
+ CASE_OP_32_64(shr):
338
+ done = fold_shift(&ctx, op);
339
+ break;
340
+ CASE_OP_32_64_VEC(sub):
341
+ done = fold_sub(&ctx, op);
342
+ break;
343
+ CASE_OP_32_64_VEC(xor):
344
+ done = fold_xor(&ctx, op);
345
break;
346
}
207
347
208
--
348
--
209
2.25.1
349
2.25.1
210
350
211
351
diff view generated by jsdifflib
New patch
[PULL 21/56] tcg/optimize: Split out fold_setcond2
1
Reduce some code duplication by folding the NE and EQ cases.
1
2
3
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
4
Reviewed-by: Luis Pires <luis.pires@eldorado.org.br>
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
---
7
tcg/optimize.c | 145 ++++++++++++++++++++++++-------------------------
8
1 file changed, 72 insertions(+), 73 deletions(-)
9
10
diff --git a/tcg/optimize.c b/tcg/optimize.c
11
index XXXXXXX..XXXXXXX 100644
12
--- a/tcg/optimize.c
13
+++ b/tcg/optimize.c
14
@@ -XXX,XX +XXX,XX @@ static bool fold_remainder(OptContext *ctx, TCGOp *op)
15
return fold_const2(ctx, op);
16
}
17
18
+static bool fold_setcond2(OptContext *ctx, TCGOp *op)
19
+{
20
+ TCGCond cond = op->args[5];
21
+ int i = do_constant_folding_cond2(&op->args[1], &op->args[3], cond);
22
+ int inv = 0;
23
+
24
+ if (i >= 0) {
25
+ goto do_setcond_const;
26
+ }
27
+
28
+ switch (cond) {
29
+ case TCG_COND_LT:
30
+ case TCG_COND_GE:
31
+ /*
32
+ * Simplify LT/GE comparisons vs zero to a single compare
33
+ * vs the high word of the input.
34
+ */
35
+ if (arg_is_const(op->args[3]) && arg_info(op->args[3])->val == 0 &&
36
+ arg_is_const(op->args[4]) && arg_info(op->args[4])->val == 0) {
37
+ goto do_setcond_high;
38
+ }
39
+ break;
40
+
41
+ case TCG_COND_NE:
42
+ inv = 1;
43
+ QEMU_FALLTHROUGH;
44
+ case TCG_COND_EQ:
45
+ /*
46
+ * Simplify EQ/NE comparisons where one of the pairs
47
+ * can be simplified.
48
+ */
49
+ i = do_constant_folding_cond(INDEX_op_setcond_i32, op->args[1],
50
+ op->args[3], cond);
51
+ switch (i ^ inv) {
52
+ case 0:
53
+ goto do_setcond_const;
54
+ case 1:
55
+ goto do_setcond_high;
56
+ }
57
+
58
+ i = do_constant_folding_cond(INDEX_op_setcond_i32, op->args[2],
59
+ op->args[4], cond);
60
+ switch (i ^ inv) {
61
+ case 0:
62
+ goto do_setcond_const;
63
+ case 1:
64
+ op->args[2] = op->args[3];
65
+ op->args[3] = cond;
66
+ op->opc = INDEX_op_setcond_i32;
67
+ break;
68
+ }
69
+ break;
70
+
71
+ default:
72
+ break;
73
+
74
+ do_setcond_high:
75
+ op->args[1] = op->args[2];
76
+ op->args[2] = op->args[4];
77
+ op->args[3] = cond;
78
+ op->opc = INDEX_op_setcond_i32;
79
+ break;
80
+ }
81
+ return false;
82
+
83
+ do_setcond_const:
84
+ return tcg_opt_gen_movi(ctx, op, op->args[0], i);
85
+}
86
+
87
static bool fold_shift(OptContext *ctx, TCGOp *op)
88
{
89
return fold_const2(ctx, op);
90
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
91
}
92
break;
93
94
- case INDEX_op_setcond2_i32:
95
- i = do_constant_folding_cond2(&op->args[1], &op->args[3],
96
- op->args[5]);
97
- if (i >= 0) {
98
- do_setcond_const:
99
- tcg_opt_gen_movi(&ctx, op, op->args[0], i);
100
- continue;
101
- }
102
- if ((op->args[5] == TCG_COND_LT || op->args[5] == TCG_COND_GE)
103
- && arg_is_const(op->args[3])
104
- && arg_info(op->args[3])->val == 0
105
- && arg_is_const(op->args[4])
106
- && arg_info(op->args[4])->val == 0) {
107
- /* Simplify LT/GE comparisons vs zero to a single compare
108
- vs the high word of the input. */
109
- do_setcond_high:
110
- reset_temp(op->args[0]);
111
- arg_info(op->args[0])->z_mask = 1;
112
- op->opc = INDEX_op_setcond_i32;
113
- op->args[1] = op->args[2];
114
- op->args[2] = op->args[4];
115
- op->args[3] = op->args[5];
116
- break;
117
- }
118
- if (op->args[5] == TCG_COND_EQ) {
119
- /* Simplify EQ comparisons where one of the pairs
120
- can be simplified. */
121
- i = do_constant_folding_cond(INDEX_op_setcond_i32,
122
- op->args[1], op->args[3],
123
- TCG_COND_EQ);
124
- if (i == 0) {
125
- goto do_setcond_const;
126
- } else if (i > 0) {
127
- goto do_setcond_high;
128
- }
129
- i = do_constant_folding_cond(INDEX_op_setcond_i32,
130
- op->args[2], op->args[4],
131
- TCG_COND_EQ);
132
- if (i == 0) {
133
- goto do_setcond_high;
134
- } else if (i < 0) {
135
- break;
136
- }
137
- do_setcond_low:
138
- reset_temp(op->args[0]);
139
- arg_info(op->args[0])->z_mask = 1;
140
- op->opc = INDEX_op_setcond_i32;
141
- op->args[2] = op->args[3];
142
- op->args[3] = op->args[5];
143
- break;
144
- }
145
- if (op->args[5] == TCG_COND_NE) {
146
- /* Simplify NE comparisons where one of the pairs
147
- can be simplified. */
148
- i = do_constant_folding_cond(INDEX_op_setcond_i32,
149
- op->args[1], op->args[3],
150
- TCG_COND_NE);
151
- if (i == 0) {
152
- goto do_setcond_high;
153
- } else if (i > 0) {
154
- goto do_setcond_const;
155
- }
156
- i = do_constant_folding_cond(INDEX_op_setcond_i32,
157
- op->args[2], op->args[4],
158
- TCG_COND_NE);
159
- if (i == 0) {
160
- goto do_setcond_low;
161
- } else if (i > 0) {
162
- goto do_setcond_const;
163
- }
164
- }
165
- break;
166
-
167
default:
168
break;
169
170
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
171
CASE_OP_32_64(shr):
172
done = fold_shift(&ctx, op);
173
break;
174
+ case INDEX_op_setcond2_i32:
175
+ done = fold_setcond2(&ctx, op);
176
+ break;
177
CASE_OP_32_64_VEC(sub):
178
done = fold_sub(&ctx, op);
179
break;
180
--
181
2.25.1
182
183
diff view generated by jsdifflib
New patch
[PULL 22/56] tcg/optimize: Split out fold_brcond2
1
Reduce some code duplication by folding the NE and EQ cases.
1
2
3
Reviewed-by: Luis Pires <luis.pires@eldorado.org.br>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
---
6
tcg/optimize.c | 159 +++++++++++++++++++++++++------------------------
7
1 file changed, 81 insertions(+), 78 deletions(-)
8
9
diff --git a/tcg/optimize.c b/tcg/optimize.c
10
index XXXXXXX..XXXXXXX 100644
11
--- a/tcg/optimize.c
12
+++ b/tcg/optimize.c
13
@@ -XXX,XX +XXX,XX @@ static bool fold_andc(OptContext *ctx, TCGOp *op)
14
return fold_const2(ctx, op);
15
}
16
17
+static bool fold_brcond2(OptContext *ctx, TCGOp *op)
18
+{
19
+ TCGCond cond = op->args[4];
20
+ int i = do_constant_folding_cond2(&op->args[0], &op->args[2], cond);
21
+ TCGArg label = op->args[5];
22
+ int inv = 0;
23
+
24
+ if (i >= 0) {
25
+ goto do_brcond_const;
26
+ }
27
+
28
+ switch (cond) {
29
+ case TCG_COND_LT:
30
+ case TCG_COND_GE:
31
+ /*
32
+ * Simplify LT/GE comparisons vs zero to a single compare
33
+ * vs the high word of the input.
34
+ */
35
+ if (arg_is_const(op->args[2]) && arg_info(op->args[2])->val == 0 &&
36
+ arg_is_const(op->args[3]) && arg_info(op->args[3])->val == 0) {
37
+ goto do_brcond_high;
38
+ }
39
+ break;
40
+
41
+ case TCG_COND_NE:
42
+ inv = 1;
43
+ QEMU_FALLTHROUGH;
44
+ case TCG_COND_EQ:
45
+ /*
46
+ * Simplify EQ/NE comparisons where one of the pairs
47
+ * can be simplified.
48
+ */
49
+ i = do_constant_folding_cond(INDEX_op_brcond_i32, op->args[0],
50
+ op->args[2], cond);
51
+ switch (i ^ inv) {
52
+ case 0:
53
+ goto do_brcond_const;
54
+ case 1:
55
+ goto do_brcond_high;
56
+ }
57
+
58
+ i = do_constant_folding_cond(INDEX_op_brcond_i32, op->args[1],
59
+ op->args[3], cond);
60
+ switch (i ^ inv) {
61
+ case 0:
62
+ goto do_brcond_const;
63
+ case 1:
64
+ op->opc = INDEX_op_brcond_i32;
65
+ op->args[1] = op->args[2];
66
+ op->args[2] = cond;
67
+ op->args[3] = label;
68
+ break;
69
+ }
70
+ break;
71
+
72
+ default:
73
+ break;
74
+
75
+ do_brcond_high:
76
+ op->opc = INDEX_op_brcond_i32;
77
+ op->args[0] = op->args[1];
78
+ op->args[1] = op->args[3];
79
+ op->args[2] = cond;
80
+ op->args[3] = label;
81
+ break;
82
+
83
+ do_brcond_const:
84
+ if (i == 0) {
85
+ tcg_op_remove(ctx->tcg, op);
86
+ return true;
87
+ }
88
+ op->opc = INDEX_op_br;
89
+ op->args[0] = label;
90
+ break;
91
+ }
92
+ return false;
93
+}
94
+
95
static bool fold_call(OptContext *ctx, TCGOp *op)
96
{
97
TCGContext *s = ctx->tcg;
98
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
99
}
100
break;
101
102
- case INDEX_op_brcond2_i32:
103
- i = do_constant_folding_cond2(&op->args[0], &op->args[2],
104
- op->args[4]);
105
- if (i == 0) {
106
- do_brcond_false:
107
- tcg_op_remove(s, op);
108
- continue;
109
- }
110
- if (i > 0) {
111
- do_brcond_true:
112
- op->opc = opc = INDEX_op_br;
113
- op->args[0] = op->args[5];
114
- break;
115
- }
116
- if ((op->args[4] == TCG_COND_LT || op->args[4] == TCG_COND_GE)
117
- && arg_is_const(op->args[2])
118
- && arg_info(op->args[2])->val == 0
119
- && arg_is_const(op->args[3])
120
- && arg_info(op->args[3])->val == 0) {
121
- /* Simplify LT/GE comparisons vs zero to a single compare
122
- vs the high word of the input. */
123
- do_brcond_high:
124
- op->opc = opc = INDEX_op_brcond_i32;
125
- op->args[0] = op->args[1];
126
- op->args[1] = op->args[3];
127
- op->args[2] = op->args[4];
128
- op->args[3] = op->args[5];
129
- break;
130
- }
131
- if (op->args[4] == TCG_COND_EQ) {
132
- /* Simplify EQ comparisons where one of the pairs
133
- can be simplified. */
134
- i = do_constant_folding_cond(INDEX_op_brcond_i32,
135
- op->args[0], op->args[2],
136
- TCG_COND_EQ);
137
- if (i == 0) {
138
- goto do_brcond_false;
139
- } else if (i > 0) {
140
- goto do_brcond_high;
141
- }
142
- i = do_constant_folding_cond(INDEX_op_brcond_i32,
143
- op->args[1], op->args[3],
144
- TCG_COND_EQ);
145
- if (i == 0) {
146
- goto do_brcond_false;
147
- } else if (i < 0) {
148
- break;
149
- }
150
- do_brcond_low:
151
- memset(&ctx.temps_used, 0, sizeof(ctx.temps_used));
152
- op->opc = INDEX_op_brcond_i32;
153
- op->args[1] = op->args[2];
154
- op->args[2] = op->args[4];
155
- op->args[3] = op->args[5];
156
- break;
157
- }
158
- if (op->args[4] == TCG_COND_NE) {
159
- /* Simplify NE comparisons where one of the pairs
160
- can be simplified. */
161
- i = do_constant_folding_cond(INDEX_op_brcond_i32,
162
- op->args[0], op->args[2],
163
- TCG_COND_NE);
164
- if (i == 0) {
165
- goto do_brcond_high;
166
- } else if (i > 0) {
167
- goto do_brcond_true;
168
- }
169
- i = do_constant_folding_cond(INDEX_op_brcond_i32,
170
- op->args[1], op->args[3],
171
- TCG_COND_NE);
172
- if (i == 0) {
173
- goto do_brcond_low;
174
- } else if (i > 0) {
175
- goto do_brcond_true;
176
- }
177
- }
178
- break;
179
-
180
default:
181
break;
182
183
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
184
CASE_OP_32_64_VEC(andc):
185
done = fold_andc(&ctx, op);
186
break;
187
+ case INDEX_op_brcond2_i32:
188
+ done = fold_brcond2(&ctx, op);
189
+ break;
190
CASE_OP_32_64(ctpop):
191
done = fold_ctpop(&ctx, op);
192
break;
193
--
194
2.25.1
195
196
diff view generated by jsdifflib
New patch
[PULL 23/56] tcg/optimize: Split out fold_brcond
1
Reviewed-by: Luis Pires <luis.pires@eldorado.org.br>
2
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
---
5
tcg/optimize.c | 33 +++++++++++++++++++--------------
6
1 file changed, 19 insertions(+), 14 deletions(-)
1
7
8
diff --git a/tcg/optimize.c b/tcg/optimize.c
9
index XXXXXXX..XXXXXXX 100644
10
--- a/tcg/optimize.c
11
+++ b/tcg/optimize.c
12
@@ -XXX,XX +XXX,XX @@ static bool fold_andc(OptContext *ctx, TCGOp *op)
13
return fold_const2(ctx, op);
14
}
15
16
+static bool fold_brcond(OptContext *ctx, TCGOp *op)
17
+{
18
+ TCGCond cond = op->args[2];
19
+ int i = do_constant_folding_cond(op->opc, op->args[0], op->args[1], cond);
20
+
21
+ if (i == 0) {
22
+ tcg_op_remove(ctx->tcg, op);
23
+ return true;
24
+ }
25
+ if (i > 0) {
26
+ op->opc = INDEX_op_br;
27
+ op->args[0] = op->args[3];
28
+ }
29
+ return false;
30
+}
31
+
32
static bool fold_brcond2(OptContext *ctx, TCGOp *op)
33
{
34
TCGCond cond = op->args[4];
35
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
36
}
37
break;
38
39
- CASE_OP_32_64(brcond):
40
- i = do_constant_folding_cond(opc, op->args[0],
41
- op->args[1], op->args[2]);
42
- if (i == 0) {
43
- tcg_op_remove(s, op);
44
- continue;
45
- } else if (i > 0) {
46
- memset(&ctx.temps_used, 0, sizeof(ctx.temps_used));
47
- op->opc = opc = INDEX_op_br;
48
- op->args[0] = op->args[3];
49
- break;
50
- }
51
- break;
52
-
53
CASE_OP_32_64(movcond):
54
i = do_constant_folding_cond(opc, op->args[1],
55
op->args[2], op->args[5]);
56
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
57
CASE_OP_32_64_VEC(andc):
58
done = fold_andc(&ctx, op);
59
break;
60
+ CASE_OP_32_64(brcond):
61
+ done = fold_brcond(&ctx, op);
62
+ break;
63
case INDEX_op_brcond2_i32:
64
done = fold_brcond2(&ctx, op);
65
break;
66
--
67
2.25.1
68
69
diff view generated by jsdifflib
New patch
[PULL 24/56] tcg/optimize: Split out fold_setcond
1
Reviewed-by: Luis Pires <luis.pires@eldorado.org.br>
2
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
---
5
tcg/optimize.c | 23 ++++++++++++++---------
6
1 file changed, 14 insertions(+), 9 deletions(-)
1
7
8
diff --git a/tcg/optimize.c b/tcg/optimize.c
9
index XXXXXXX..XXXXXXX 100644
10
--- a/tcg/optimize.c
11
+++ b/tcg/optimize.c
12
@@ -XXX,XX +XXX,XX @@ static bool fold_remainder(OptContext *ctx, TCGOp *op)
13
return fold_const2(ctx, op);
14
}
15
16
+static bool fold_setcond(OptContext *ctx, TCGOp *op)
17
+{
18
+ TCGCond cond = op->args[3];
19
+ int i = do_constant_folding_cond(op->opc, op->args[1], op->args[2], cond);
20
+
21
+ if (i >= 0) {
22
+ return tcg_opt_gen_movi(ctx, op, op->args[0], i);
23
+ }
24
+ return false;
25
+}
26
+
27
static bool fold_setcond2(OptContext *ctx, TCGOp *op)
28
{
29
TCGCond cond = op->args[5];
30
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
31
}
32
break;
33
34
- CASE_OP_32_64(setcond):
35
- i = do_constant_folding_cond(opc, op->args[1],
36
- op->args[2], op->args[3]);
37
- if (i >= 0) {
38
- tcg_opt_gen_movi(&ctx, op, op->args[0], i);
39
- continue;
40
- }
41
- break;
42
-
43
CASE_OP_32_64(movcond):
44
i = do_constant_folding_cond(opc, op->args[1],
45
op->args[2], op->args[5]);
46
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
47
CASE_OP_32_64(shr):
48
done = fold_shift(&ctx, op);
49
break;
50
+ CASE_OP_32_64(setcond):
51
+ done = fold_setcond(&ctx, op);
52
+ break;
53
case INDEX_op_setcond2_i32:
54
done = fold_setcond2(&ctx, op);
55
break;
56
--
57
2.25.1
58
59
diff view generated by jsdifflib
New patch
[PULL 25/56] tcg/optimize: Split out fold_mulu2_i32
1
Reviewed-by: Luis Pires <luis.pires@eldorado.org.br>
2
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
---
5
tcg/optimize.c | 37 +++++++++++++++++++++----------------
6
1 file changed, 21 insertions(+), 16 deletions(-)
1
7
8
diff --git a/tcg/optimize.c b/tcg/optimize.c
9
index XXXXXXX..XXXXXXX 100644
10
--- a/tcg/optimize.c
11
+++ b/tcg/optimize.c
12
@@ -XXX,XX +XXX,XX @@ static bool fold_mul_highpart(OptContext *ctx, TCGOp *op)
13
return fold_const2(ctx, op);
14
}
15
16
+static bool fold_mulu2_i32(OptContext *ctx, TCGOp *op)
17
+{
18
+ if (arg_is_const(op->args[2]) && arg_is_const(op->args[3])) {
19
+ uint32_t a = arg_info(op->args[2])->val;
20
+ uint32_t b = arg_info(op->args[3])->val;
21
+ uint64_t r = (uint64_t)a * b;
22
+ TCGArg rl, rh;
23
+ TCGOp *op2 = tcg_op_insert_before(ctx->tcg, op, INDEX_op_mov_i32);
24
+
25
+ rl = op->args[0];
26
+ rh = op->args[1];
27
+ tcg_opt_gen_movi(ctx, op, rl, (int32_t)r);
28
+ tcg_opt_gen_movi(ctx, op2, rh, (int32_t)(r >> 32));
29
+ return true;
30
+ }
31
+ return false;
32
+}
33
+
34
static bool fold_nand(OptContext *ctx, TCGOp *op)
35
{
36
return fold_const2(ctx, op);
37
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
38
}
39
break;
40
41
- case INDEX_op_mulu2_i32:
42
- if (arg_is_const(op->args[2]) && arg_is_const(op->args[3])) {
43
- uint32_t a = arg_info(op->args[2])->val;
44
- uint32_t b = arg_info(op->args[3])->val;
45
- uint64_t r = (uint64_t)a * b;
46
- TCGArg rl, rh;
47
- TCGOp *op2 = tcg_op_insert_before(s, op, INDEX_op_mov_i32);
48
-
49
- rl = op->args[0];
50
- rh = op->args[1];
51
- tcg_opt_gen_movi(&ctx, op, rl, (int32_t)r);
52
- tcg_opt_gen_movi(&ctx, op2, rh, (int32_t)(r >> 32));
53
- continue;
54
- }
55
- break;
56
-
57
default:
58
break;
59
60
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
61
CASE_OP_32_64(muluh):
62
done = fold_mul_highpart(&ctx, op);
63
break;
64
+ case INDEX_op_mulu2_i32:
65
+ done = fold_mulu2_i32(&ctx, op);
66
+ break;
67
CASE_OP_32_64(nand):
68
done = fold_nand(&ctx, op);
69
break;
70
--
71
2.25.1
72
73
diff view generated by jsdifflib
New patch
[PULL 26/56] tcg/optimize: Split out fold_addsub2_i32
1
Add two additional helpers, fold_add2_i32 and fold_sub2_i32
2
which will not be simple wrappers forever.
1
3
4
Reviewed-by: Luis Pires <luis.pires@eldorado.org.br>
5
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
---
8
tcg/optimize.c | 70 +++++++++++++++++++++++++++++++-------------------
9
1 file changed, 44 insertions(+), 26 deletions(-)
10
11
diff --git a/tcg/optimize.c b/tcg/optimize.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/tcg/optimize.c
14
+++ b/tcg/optimize.c
15
@@ -XXX,XX +XXX,XX @@ static bool fold_add(OptContext *ctx, TCGOp *op)
16
return fold_const2(ctx, op);
17
}
18
19
+static bool fold_addsub2_i32(OptContext *ctx, TCGOp *op, bool add)
20
+{
21
+ if (arg_is_const(op->args[2]) && arg_is_const(op->args[3]) &&
22
+ arg_is_const(op->args[4]) && arg_is_const(op->args[5])) {
23
+ uint32_t al = arg_info(op->args[2])->val;
24
+ uint32_t ah = arg_info(op->args[3])->val;
25
+ uint32_t bl = arg_info(op->args[4])->val;
26
+ uint32_t bh = arg_info(op->args[5])->val;
27
+ uint64_t a = ((uint64_t)ah << 32) | al;
28
+ uint64_t b = ((uint64_t)bh << 32) | bl;
29
+ TCGArg rl, rh;
30
+ TCGOp *op2 = tcg_op_insert_before(ctx->tcg, op, INDEX_op_mov_i32);
31
+
32
+ if (add) {
33
+ a += b;
34
+ } else {
35
+ a -= b;
36
+ }
37
+
38
+ rl = op->args[0];
39
+ rh = op->args[1];
40
+ tcg_opt_gen_movi(ctx, op, rl, (int32_t)a);
41
+ tcg_opt_gen_movi(ctx, op2, rh, (int32_t)(a >> 32));
42
+ return true;
43
+ }
44
+ return false;
45
+}
46
+
47
+static bool fold_add2_i32(OptContext *ctx, TCGOp *op)
48
+{
49
+ return fold_addsub2_i32(ctx, op, true);
50
+}
51
+
52
static bool fold_and(OptContext *ctx, TCGOp *op)
53
{
54
return fold_const2(ctx, op);
55
@@ -XXX,XX +XXX,XX @@ static bool fold_sub(OptContext *ctx, TCGOp *op)
56
return fold_const2(ctx, op);
57
}
58
59
+static bool fold_sub2_i32(OptContext *ctx, TCGOp *op)
60
+{
61
+ return fold_addsub2_i32(ctx, op, false);
62
+}
63
+
64
static bool fold_xor(OptContext *ctx, TCGOp *op)
65
{
66
return fold_const2(ctx, op);
67
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
68
}
69
break;
70
71
- case INDEX_op_add2_i32:
72
- case INDEX_op_sub2_i32:
73
- if (arg_is_const(op->args[2]) && arg_is_const(op->args[3])
74
- && arg_is_const(op->args[4]) && arg_is_const(op->args[5])) {
75
- uint32_t al = arg_info(op->args[2])->val;
76
- uint32_t ah = arg_info(op->args[3])->val;
77
- uint32_t bl = arg_info(op->args[4])->val;
78
- uint32_t bh = arg_info(op->args[5])->val;
79
- uint64_t a = ((uint64_t)ah << 32) | al;
80
- uint64_t b = ((uint64_t)bh << 32) | bl;
81
- TCGArg rl, rh;
82
- TCGOp *op2 = tcg_op_insert_before(s, op, INDEX_op_mov_i32);
83
-
84
- if (opc == INDEX_op_add2_i32) {
85
- a += b;
86
- } else {
87
- a -= b;
88
- }
89
-
90
- rl = op->args[0];
91
- rh = op->args[1];
92
- tcg_opt_gen_movi(&ctx, op, rl, (int32_t)a);
93
- tcg_opt_gen_movi(&ctx, op2, rh, (int32_t)(a >> 32));
94
- continue;
95
- }
96
- break;
97
98
default:
99
break;
100
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
101
CASE_OP_32_64_VEC(add):
102
done = fold_add(&ctx, op);
103
break;
104
+ case INDEX_op_add2_i32:
105
+ done = fold_add2_i32(&ctx, op);
106
+ break;
107
CASE_OP_32_64_VEC(and):
108
done = fold_and(&ctx, op);
109
break;
110
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
111
CASE_OP_32_64_VEC(sub):
112
done = fold_sub(&ctx, op);
113
break;
114
+ case INDEX_op_sub2_i32:
115
+ done = fold_sub2_i32(&ctx, op);
116
+ break;
117
CASE_OP_32_64_VEC(xor):
118
done = fold_xor(&ctx, op);
119
break;
120
--
121
2.25.1
122
123
diff view generated by jsdifflib
New patch
[PULL 27/56] tcg/optimize: Split out fold_movcond
1
Reviewed-by: Luis Pires <luis.pires@eldorado.org.br>
2
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
---
5
tcg/optimize.c | 56 ++++++++++++++++++++++++++++----------------------
6
1 file changed, 31 insertions(+), 25 deletions(-)
1
7
8
diff --git a/tcg/optimize.c b/tcg/optimize.c
9
index XXXXXXX..XXXXXXX 100644
10
--- a/tcg/optimize.c
11
+++ b/tcg/optimize.c
12
@@ -XXX,XX +XXX,XX @@ static bool fold_mb(OptContext *ctx, TCGOp *op)
13
return true;
14
}
15
16
+static bool fold_movcond(OptContext *ctx, TCGOp *op)
17
+{
18
+ TCGOpcode opc = op->opc;
19
+ TCGCond cond = op->args[5];
20
+ int i = do_constant_folding_cond(opc, op->args[1], op->args[2], cond);
21
+
22
+ if (i >= 0) {
23
+ return tcg_opt_gen_mov(ctx, op, op->args[0], op->args[4 - i]);
24
+ }
25
+
26
+ if (arg_is_const(op->args[3]) && arg_is_const(op->args[4])) {
27
+ uint64_t tv = arg_info(op->args[3])->val;
28
+ uint64_t fv = arg_info(op->args[4])->val;
29
+
30
+ opc = (opc == INDEX_op_movcond_i32
31
+ ? INDEX_op_setcond_i32 : INDEX_op_setcond_i64);
32
+
33
+ if (tv == 1 && fv == 0) {
34
+ op->opc = opc;
35
+ op->args[3] = cond;
36
+ } else if (fv == 1 && tv == 0) {
37
+ op->opc = opc;
38
+ op->args[3] = tcg_invert_cond(cond);
39
+ }
40
+ }
41
+ return false;
42
+}
43
+
44
static bool fold_mul(OptContext *ctx, TCGOp *op)
45
{
46
return fold_const2(ctx, op);
47
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
48
}
49
break;
50
51
- CASE_OP_32_64(movcond):
52
- i = do_constant_folding_cond(opc, op->args[1],
53
- op->args[2], op->args[5]);
54
- if (i >= 0) {
55
- tcg_opt_gen_mov(&ctx, op, op->args[0], op->args[4 - i]);
56
- continue;
57
- }
58
- if (arg_is_const(op->args[3]) && arg_is_const(op->args[4])) {
59
- uint64_t tv = arg_info(op->args[3])->val;
60
- uint64_t fv = arg_info(op->args[4])->val;
61
- TCGCond cond = op->args[5];
62
-
63
- if (fv == 1 && tv == 0) {
64
- cond = tcg_invert_cond(cond);
65
- } else if (!(tv == 1 && fv == 0)) {
66
- break;
67
- }
68
- op->args[3] = cond;
69
- op->opc = opc = (opc == INDEX_op_movcond_i32
70
- ? INDEX_op_setcond_i32
71
- : INDEX_op_setcond_i64);
72
- }
73
- break;
74
-
75
-
76
default:
77
break;
78
79
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
80
case INDEX_op_mb:
81
done = fold_mb(&ctx, op);
82
break;
83
+ CASE_OP_32_64(movcond):
84
+ done = fold_movcond(&ctx, op);
85
+ break;
86
CASE_OP_32_64(mul):
87
done = fold_mul(&ctx, op);
88
break;
89
--
90
2.25.1
91
92
diff view generated by jsdifflib
New patch
[PULL 28/56] tcg/optimize: Split out fold_extract2
1
Reviewed-by: Luis Pires <luis.pires@eldorado.org.br>
2
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
---
5
tcg/optimize.c | 39 ++++++++++++++++++++++-----------------
6
1 file changed, 22 insertions(+), 17 deletions(-)
1
7
8
diff --git a/tcg/optimize.c b/tcg/optimize.c
9
index XXXXXXX..XXXXXXX 100644
10
--- a/tcg/optimize.c
11
+++ b/tcg/optimize.c
12
@@ -XXX,XX +XXX,XX @@ static bool fold_eqv(OptContext *ctx, TCGOp *op)
13
return fold_const2(ctx, op);
14
}
15
16
+static bool fold_extract2(OptContext *ctx, TCGOp *op)
17
+{
18
+ if (arg_is_const(op->args[1]) && arg_is_const(op->args[2])) {
19
+ uint64_t v1 = arg_info(op->args[1])->val;
20
+ uint64_t v2 = arg_info(op->args[2])->val;
21
+ int shr = op->args[3];
22
+
23
+ if (op->opc == INDEX_op_extract2_i64) {
24
+ v1 >>= shr;
25
+ v2 <<= 64 - shr;
26
+ } else {
27
+ v1 = (uint32_t)v1 >> shr;
28
+ v2 = (int32_t)v2 << (32 - shr);
29
+ }
30
+ return tcg_opt_gen_movi(ctx, op, op->args[0], v1 | v2);
31
+ }
32
+ return false;
33
+}
34
+
35
static bool fold_exts(OptContext *ctx, TCGOp *op)
36
{
37
return fold_const1(ctx, op);
38
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
39
}
40
break;
41
42
- CASE_OP_32_64(extract2):
43
- if (arg_is_const(op->args[1]) && arg_is_const(op->args[2])) {
44
- uint64_t v1 = arg_info(op->args[1])->val;
45
- uint64_t v2 = arg_info(op->args[2])->val;
46
- int shr = op->args[3];
47
-
48
- if (opc == INDEX_op_extract2_i64) {
49
- tmp = (v1 >> shr) | (v2 << (64 - shr));
50
- } else {
51
- tmp = (int32_t)(((uint32_t)v1 >> shr) |
52
- ((uint32_t)v2 << (32 - shr)));
53
- }
54
- tcg_opt_gen_movi(&ctx, op, op->args[0], tmp);
55
- continue;
56
- }
57
- break;
58
-
59
default:
60
break;
61
62
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
63
CASE_OP_32_64(eqv):
64
done = fold_eqv(&ctx, op);
65
break;
66
+ CASE_OP_32_64(extract2):
67
+ done = fold_extract2(&ctx, op);
68
+ break;
69
CASE_OP_32_64(ext8s):
70
CASE_OP_32_64(ext16s):
71
case INDEX_op_ext32s_i64:
72
--
73
2.25.1
74
75
diff view generated by jsdifflib
New patch
[PULL 29/56] tcg/optimize: Split out fold_extract, fold_sextract
1
Reviewed-by: Luis Pires <luis.pires@eldorado.org.br>
2
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
---
5
tcg/optimize.c | 48 ++++++++++++++++++++++++++++++------------------
6
1 file changed, 30 insertions(+), 18 deletions(-)
1
7
8
diff --git a/tcg/optimize.c b/tcg/optimize.c
9
index XXXXXXX..XXXXXXX 100644
10
--- a/tcg/optimize.c
11
+++ b/tcg/optimize.c
12
@@ -XXX,XX +XXX,XX @@ static bool fold_eqv(OptContext *ctx, TCGOp *op)
13
return fold_const2(ctx, op);
14
}
15
16
+static bool fold_extract(OptContext *ctx, TCGOp *op)
17
+{
18
+ if (arg_is_const(op->args[1])) {
19
+ uint64_t t;
20
+
21
+ t = arg_info(op->args[1])->val;
22
+ t = extract64(t, op->args[2], op->args[3]);
23
+ return tcg_opt_gen_movi(ctx, op, op->args[0], t);
24
+ }
25
+ return false;
26
+}
27
+
28
static bool fold_extract2(OptContext *ctx, TCGOp *op)
29
{
30
if (arg_is_const(op->args[1]) && arg_is_const(op->args[2])) {
31
@@ -XXX,XX +XXX,XX @@ static bool fold_setcond2(OptContext *ctx, TCGOp *op)
32
return tcg_opt_gen_movi(ctx, op, op->args[0], i);
33
}
34
35
+static bool fold_sextract(OptContext *ctx, TCGOp *op)
36
+{
37
+ if (arg_is_const(op->args[1])) {
38
+ uint64_t t;
39
+
40
+ t = arg_info(op->args[1])->val;
41
+ t = sextract64(t, op->args[2], op->args[3]);
42
+ return tcg_opt_gen_movi(ctx, op, op->args[0], t);
43
+ }
44
+ return false;
45
+}
46
+
47
static bool fold_shift(OptContext *ctx, TCGOp *op)
48
{
49
return fold_const2(ctx, op);
50
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
51
}
52
break;
53
54
- CASE_OP_32_64(extract):
55
- if (arg_is_const(op->args[1])) {
56
- tmp = extract64(arg_info(op->args[1])->val,
57
- op->args[2], op->args[3]);
58
- tcg_opt_gen_movi(&ctx, op, op->args[0], tmp);
59
- continue;
60
- }
61
- break;
62
-
63
- CASE_OP_32_64(sextract):
64
- if (arg_is_const(op->args[1])) {
65
- tmp = sextract64(arg_info(op->args[1])->val,
66
- op->args[2], op->args[3]);
67
- tcg_opt_gen_movi(&ctx, op, op->args[0], tmp);
68
- continue;
69
- }
70
- break;
71
-
72
default:
73
break;
74
75
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
76
CASE_OP_32_64(eqv):
77
done = fold_eqv(&ctx, op);
78
break;
79
+ CASE_OP_32_64(extract):
80
+ done = fold_extract(&ctx, op);
81
+ break;
82
CASE_OP_32_64(extract2):
83
done = fold_extract2(&ctx, op);
84
break;
85
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
86
case INDEX_op_setcond2_i32:
87
done = fold_setcond2(&ctx, op);
88
break;
89
+ CASE_OP_32_64(sextract):
90
+ done = fold_sextract(&ctx, op);
91
+ break;
92
CASE_OP_32_64_VEC(sub):
93
done = fold_sub(&ctx, op);
94
break;
95
--
96
2.25.1
97
98
diff view generated by jsdifflib
New patch
[PULL 30/56] tcg/optimize: Split out fold_deposit
1
Reviewed-by: Luis Pires <luis.pires@eldorado.org.br>
2
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
---
5
tcg/optimize.c | 25 +++++++++++++++----------
6
1 file changed, 15 insertions(+), 10 deletions(-)
1
7
8
diff --git a/tcg/optimize.c b/tcg/optimize.c
9
index XXXXXXX..XXXXXXX 100644
10
--- a/tcg/optimize.c
11
+++ b/tcg/optimize.c
12
@@ -XXX,XX +XXX,XX @@ static bool fold_ctpop(OptContext *ctx, TCGOp *op)
13
return fold_const1(ctx, op);
14
}
15
16
+static bool fold_deposit(OptContext *ctx, TCGOp *op)
17
+{
18
+ if (arg_is_const(op->args[1]) && arg_is_const(op->args[2])) {
19
+ uint64_t t1 = arg_info(op->args[1])->val;
20
+ uint64_t t2 = arg_info(op->args[2])->val;
21
+
22
+ t1 = deposit64(t1, op->args[3], op->args[4], t2);
23
+ return tcg_opt_gen_movi(ctx, op, op->args[0], t1);
24
+ }
25
+ return false;
26
+}
27
+
28
static bool fold_divide(OptContext *ctx, TCGOp *op)
29
{
30
return fold_const2(ctx, op);
31
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
32
}
33
break;
34
35
- CASE_OP_32_64(deposit):
36
- if (arg_is_const(op->args[1]) && arg_is_const(op->args[2])) {
37
- tmp = deposit64(arg_info(op->args[1])->val,
38
- op->args[3], op->args[4],
39
- arg_info(op->args[2])->val);
40
- tcg_opt_gen_movi(&ctx, op, op->args[0], tmp);
41
- continue;
42
- }
43
- break;
44
-
45
default:
46
break;
47
48
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
49
CASE_OP_32_64(ctpop):
50
done = fold_ctpop(&ctx, op);
51
break;
52
+ CASE_OP_32_64(deposit):
53
+ done = fold_deposit(&ctx, op);
54
+ break;
55
CASE_OP_32_64(div):
56
CASE_OP_32_64(divu):
57
done = fold_divide(&ctx, op);
58
--
59
2.25.1
60
61
diff view generated by jsdifflib
New patch
[PULL 31/56] tcg/optimize: Split out fold_count_zeros
1
Reviewed-by: Luis Pires <luis.pires@eldorado.org.br>
2
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
---
5
tcg/optimize.c | 32 ++++++++++++++++++--------------
6
1 file changed, 18 insertions(+), 14 deletions(-)
1
7
8
diff --git a/tcg/optimize.c b/tcg/optimize.c
9
index XXXXXXX..XXXXXXX 100644
10
--- a/tcg/optimize.c
11
+++ b/tcg/optimize.c
12
@@ -XXX,XX +XXX,XX @@ static bool fold_call(OptContext *ctx, TCGOp *op)
13
return true;
14
}
15
16
+static bool fold_count_zeros(OptContext *ctx, TCGOp *op)
17
+{
18
+ if (arg_is_const(op->args[1])) {
19
+ uint64_t t = arg_info(op->args[1])->val;
20
+
21
+ if (t != 0) {
22
+ t = do_constant_folding(op->opc, t, 0);
23
+ return tcg_opt_gen_movi(ctx, op, op->args[0], t);
24
+ }
25
+ return tcg_opt_gen_mov(ctx, op, op->args[0], op->args[2]);
26
+ }
27
+ return false;
28
+}
29
+
30
static bool fold_ctpop(OptContext *ctx, TCGOp *op)
31
{
32
return fold_const1(ctx, op);
33
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
34
}
35
break;
36
37
- CASE_OP_32_64(clz):
38
- CASE_OP_32_64(ctz):
39
- if (arg_is_const(op->args[1])) {
40
- TCGArg v = arg_info(op->args[1])->val;
41
- if (v != 0) {
42
- tmp = do_constant_folding(opc, v, 0);
43
- tcg_opt_gen_movi(&ctx, op, op->args[0], tmp);
44
- } else {
45
- tcg_opt_gen_mov(&ctx, op, op->args[0], op->args[2]);
46
- }
47
- continue;
48
- }
49
- break;
50
-
51
default:
52
break;
53
54
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
55
case INDEX_op_brcond2_i32:
56
done = fold_brcond2(&ctx, op);
57
break;
58
+ CASE_OP_32_64(clz):
59
+ CASE_OP_32_64(ctz):
60
+ done = fold_count_zeros(&ctx, op);
61
+ break;
62
CASE_OP_32_64(ctpop):
63
done = fold_ctpop(&ctx, op);
64
break;
65
--
66
2.25.1
67
68
diff view generated by jsdifflib
New patch
[PULL 32/56] tcg/optimize: Split out fold_bswap
1
Reviewed-by: Luis Pires <luis.pires@eldorado.org.br>
2
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
---
5
tcg/optimize.c | 27 ++++++++++++++++-----------
6
1 file changed, 16 insertions(+), 11 deletions(-)
1
7
8
diff --git a/tcg/optimize.c b/tcg/optimize.c
9
index XXXXXXX..XXXXXXX 100644
10
--- a/tcg/optimize.c
11
+++ b/tcg/optimize.c
12
@@ -XXX,XX +XXX,XX @@ static bool fold_brcond2(OptContext *ctx, TCGOp *op)
13
return false;
14
}
15
16
+static bool fold_bswap(OptContext *ctx, TCGOp *op)
17
+{
18
+ if (arg_is_const(op->args[1])) {
19
+ uint64_t t = arg_info(op->args[1])->val;
20
+
21
+ t = do_constant_folding(op->opc, t, op->args[2]);
22
+ return tcg_opt_gen_movi(ctx, op, op->args[0], t);
23
+ }
24
+ return false;
25
+}
26
+
27
static bool fold_call(OptContext *ctx, TCGOp *op)
28
{
29
TCGContext *s = ctx->tcg;
30
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
31
}
32
break;
33
34
- CASE_OP_32_64(bswap16):
35
- CASE_OP_32_64(bswap32):
36
- case INDEX_op_bswap64_i64:
37
- if (arg_is_const(op->args[1])) {
38
- tmp = do_constant_folding(opc, arg_info(op->args[1])->val,
39
- op->args[2]);
40
- tcg_opt_gen_movi(&ctx, op, op->args[0], tmp);
41
- continue;
42
- }
43
- break;
44
-
45
default:
46
break;
47
48
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
49
case INDEX_op_brcond2_i32:
50
done = fold_brcond2(&ctx, op);
51
break;
52
+ CASE_OP_32_64(bswap16):
53
+ CASE_OP_32_64(bswap32):
54
+ case INDEX_op_bswap64_i64:
55
+ done = fold_bswap(&ctx, op);
56
+ break;
57
CASE_OP_32_64(clz):
58
CASE_OP_32_64(ctz):
59
done = fold_count_zeros(&ctx, op);
60
--
61
2.25.1
62
63
diff view generated by jsdifflib
New patch
[PULL 33/56] tcg/optimize: Split out fold_dup, fold_dup2
1
Reviewed-by: Luis Pires <luis.pires@eldorado.org.br>
2
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
---
5
tcg/optimize.c | 53 +++++++++++++++++++++++++++++---------------------
6
1 file changed, 31 insertions(+), 22 deletions(-)
1
7
8
diff --git a/tcg/optimize.c b/tcg/optimize.c
9
index XXXXXXX..XXXXXXX 100644
10
--- a/tcg/optimize.c
11
+++ b/tcg/optimize.c
12
@@ -XXX,XX +XXX,XX @@ static bool fold_divide(OptContext *ctx, TCGOp *op)
13
return fold_const2(ctx, op);
14
}
15
16
+static bool fold_dup(OptContext *ctx, TCGOp *op)
17
+{
18
+ if (arg_is_const(op->args[1])) {
19
+ uint64_t t = arg_info(op->args[1])->val;
20
+ t = dup_const(TCGOP_VECE(op), t);
21
+ return tcg_opt_gen_movi(ctx, op, op->args[0], t);
22
+ }
23
+ return false;
24
+}
25
+
26
+static bool fold_dup2(OptContext *ctx, TCGOp *op)
27
+{
28
+ if (arg_is_const(op->args[1]) && arg_is_const(op->args[2])) {
29
+ uint64_t t = deposit64(arg_info(op->args[1])->val, 32, 32,
30
+ arg_info(op->args[2])->val);
31
+ return tcg_opt_gen_movi(ctx, op, op->args[0], t);
32
+ }
33
+
34
+ if (args_are_copies(op->args[1], op->args[2])) {
35
+ op->opc = INDEX_op_dup_vec;
36
+ TCGOP_VECE(op) = MO_32;
37
+ }
38
+ return false;
39
+}
40
+
41
static bool fold_eqv(OptContext *ctx, TCGOp *op)
42
{
43
return fold_const2(ctx, op);
44
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
45
done = tcg_opt_gen_mov(&ctx, op, op->args[0], op->args[1]);
46
break;
47
48
- case INDEX_op_dup_vec:
49
- if (arg_is_const(op->args[1])) {
50
- tmp = arg_info(op->args[1])->val;
51
- tmp = dup_const(TCGOP_VECE(op), tmp);
52
- tcg_opt_gen_movi(&ctx, op, op->args[0], tmp);
53
- continue;
54
- }
55
- break;
56
-
57
- case INDEX_op_dup2_vec:
58
- assert(TCG_TARGET_REG_BITS == 32);
59
- if (arg_is_const(op->args[1]) && arg_is_const(op->args[2])) {
60
- tcg_opt_gen_movi(&ctx, op, op->args[0],
61
- deposit64(arg_info(op->args[1])->val, 32, 32,
62
- arg_info(op->args[2])->val));
63
- continue;
64
- } else if (args_are_copies(op->args[1], op->args[2])) {
65
- op->opc = INDEX_op_dup_vec;
66
- TCGOP_VECE(op) = MO_32;
67
- }
68
- break;
69
-
70
default:
71
break;
72
73
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
74
CASE_OP_32_64(divu):
75
done = fold_divide(&ctx, op);
76
break;
77
+ case INDEX_op_dup_vec:
78
+ done = fold_dup(&ctx, op);
79
+ break;
80
+ case INDEX_op_dup2_vec:
81
+ done = fold_dup2(&ctx, op);
82
+ break;
83
CASE_OP_32_64(eqv):
84
done = fold_eqv(&ctx, op);
85
break;
86
--
87
2.25.1
88
89
diff view generated by jsdifflib
New patch
[PULL 34/56] tcg/optimize: Split out fold_mov
1
This is the final entry in the main switch that was in a
2
different form. After this, we have the option to convert
3
the switch into a function dispatch table.
1
4
5
Reviewed-by: Luis Pires <luis.pires@eldorado.org.br>
6
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
---
9
tcg/optimize.c | 27 ++++++++++++++-------------
10
1 file changed, 14 insertions(+), 13 deletions(-)
11
12
diff --git a/tcg/optimize.c b/tcg/optimize.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/tcg/optimize.c
15
+++ b/tcg/optimize.c
16
@@ -XXX,XX +XXX,XX @@ static bool fold_mb(OptContext *ctx, TCGOp *op)
17
return true;
18
}
19
20
+static bool fold_mov(OptContext *ctx, TCGOp *op)
21
+{
22
+ return tcg_opt_gen_mov(ctx, op, op->args[0], op->args[1]);
23
+}
24
+
25
static bool fold_movcond(OptContext *ctx, TCGOp *op)
26
{
27
TCGOpcode opc = op->opc;
28
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
29
break;
30
}
31
32
- /* Propagate constants through copy operations and do constant
33
- folding. Constants will be substituted to arguments by register
34
- allocator where needed and possible. Also detect copies. */
35
+ /*
36
+ * Process each opcode.
37
+ * Sorted alphabetically by opcode as much as possible.
38
+ */
39
switch (opc) {
40
- CASE_OP_32_64_VEC(mov):
41
- done = tcg_opt_gen_mov(&ctx, op, op->args[0], op->args[1]);
42
- break;
43
-
44
- default:
45
- break;
46
-
47
- /* ---------------------------------------------------------- */
48
- /* Sorted alphabetically by opcode as much as possible. */
49
-
50
CASE_OP_32_64_VEC(add):
51
done = fold_add(&ctx, op);
52
break;
53
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
54
case INDEX_op_mb:
55
done = fold_mb(&ctx, op);
56
break;
57
+ CASE_OP_32_64_VEC(mov):
58
+ done = fold_mov(&ctx, op);
59
+ break;
60
CASE_OP_32_64(movcond):
61
done = fold_movcond(&ctx, op);
62
break;
63
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
64
CASE_OP_32_64_VEC(xor):
65
done = fold_xor(&ctx, op);
66
break;
67
+ default:
68
+ break;
69
}
70
71
if (!done) {
72
--
73
2.25.1
74
75
diff view generated by jsdifflib
New patch
[PULL 35/56] tcg/optimize: Split out fold_xx_to_i
1
Pull the "op r, a, a => movi r, 0" optimization into a function,
2
and use it in the outer opcode fold functions.
1
3
4
Reviewed-by: Luis Pires <luis.pires@eldorado.org.br>
5
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
---
8
tcg/optimize.c | 41 ++++++++++++++++++++++++-----------------
9
1 file changed, 24 insertions(+), 17 deletions(-)
10
11
diff --git a/tcg/optimize.c b/tcg/optimize.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/tcg/optimize.c
14
+++ b/tcg/optimize.c
15
@@ -XXX,XX +XXX,XX @@ static bool fold_const2(OptContext *ctx, TCGOp *op)
16
return false;
17
}
18
19
+/* If the binary operation has both arguments equal, fold to @i. */
20
+static bool fold_xx_to_i(OptContext *ctx, TCGOp *op, uint64_t i)
21
+{
22
+ if (args_are_copies(op->args[1], op->args[2])) {
23
+ return tcg_opt_gen_movi(ctx, op, op->args[0], i);
24
+ }
25
+ return false;
26
+}
27
+
28
/*
29
* These outermost fold_<op> functions are sorted alphabetically.
30
*/
31
@@ -XXX,XX +XXX,XX @@ static bool fold_and(OptContext *ctx, TCGOp *op)
32
33
static bool fold_andc(OptContext *ctx, TCGOp *op)
34
{
35
- return fold_const2(ctx, op);
36
+ if (fold_const2(ctx, op) ||
37
+ fold_xx_to_i(ctx, op, 0)) {
38
+ return true;
39
+ }
40
+ return false;
41
}
42
43
static bool fold_brcond(OptContext *ctx, TCGOp *op)
44
@@ -XXX,XX +XXX,XX @@ static bool fold_shift(OptContext *ctx, TCGOp *op)
45
46
static bool fold_sub(OptContext *ctx, TCGOp *op)
47
{
48
- return fold_const2(ctx, op);
49
+ if (fold_const2(ctx, op) ||
50
+ fold_xx_to_i(ctx, op, 0)) {
51
+ return true;
52
+ }
53
+ return false;
54
}
55
56
static bool fold_sub2_i32(OptContext *ctx, TCGOp *op)
57
@@ -XXX,XX +XXX,XX @@ static bool fold_sub2_i32(OptContext *ctx, TCGOp *op)
58
59
static bool fold_xor(OptContext *ctx, TCGOp *op)
60
{
61
- return fold_const2(ctx, op);
62
+ if (fold_const2(ctx, op) ||
63
+ fold_xx_to_i(ctx, op, 0)) {
64
+ return true;
65
+ }
66
+ return false;
67
}
68
69
/* Propagate constants and copies, fold constant expressions. */
70
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
71
break;
72
}
73
74
- /* Simplify expression for "op r, a, a => movi r, 0" cases */
75
- switch (opc) {
76
- CASE_OP_32_64_VEC(andc):
77
- CASE_OP_32_64_VEC(sub):
78
- CASE_OP_32_64_VEC(xor):
79
- if (args_are_copies(op->args[1], op->args[2])) {
80
- tcg_opt_gen_movi(&ctx, op, op->args[0], 0);
81
- continue;
82
- }
83
- break;
84
- default:
85
- break;
86
- }
87
-
88
/*
89
* Process each opcode.
90
* Sorted alphabetically by opcode as much as possible.
91
--
92
2.25.1
93
94
diff view generated by jsdifflib
New patch
[PULL 36/56] tcg/optimize: Split out fold_xx_to_x
1
Pull the "op r, a, a => mov r, a" optimization into a function,
2
and use it in the outer opcode fold functions.
1
3
4
Reviewed-by: Luis Pires <luis.pires@eldorado.org.br>
5
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
---
8
tcg/optimize.c | 39 ++++++++++++++++++++++++---------------
9
1 file changed, 24 insertions(+), 15 deletions(-)
10
11
diff --git a/tcg/optimize.c b/tcg/optimize.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/tcg/optimize.c
14
+++ b/tcg/optimize.c
15
@@ -XXX,XX +XXX,XX @@ static bool fold_xx_to_i(OptContext *ctx, TCGOp *op, uint64_t i)
16
return false;
17
}
18
19
+/* If the binary operation has both arguments equal, fold to identity. */
20
+static bool fold_xx_to_x(OptContext *ctx, TCGOp *op)
21
+{
22
+ if (args_are_copies(op->args[1], op->args[2])) {
23
+ return tcg_opt_gen_mov(ctx, op, op->args[0], op->args[1]);
24
+ }
25
+ return false;
26
+}
27
+
28
/*
29
* These outermost fold_<op> functions are sorted alphabetically.
30
+ *
31
+ * The ordering of the transformations should be:
32
+ * 1) those that produce a constant
33
+ * 2) those that produce a copy
34
+ * 3) those that produce information about the result value.
35
*/
36
37
static bool fold_add(OptContext *ctx, TCGOp *op)
38
@@ -XXX,XX +XXX,XX @@ static bool fold_add2_i32(OptContext *ctx, TCGOp *op)
39
40
static bool fold_and(OptContext *ctx, TCGOp *op)
41
{
42
- return fold_const2(ctx, op);
43
+ if (fold_const2(ctx, op) ||
44
+ fold_xx_to_x(ctx, op)) {
45
+ return true;
46
+ }
47
+ return false;
48
}
49
50
static bool fold_andc(OptContext *ctx, TCGOp *op)
51
@@ -XXX,XX +XXX,XX @@ static bool fold_not(OptContext *ctx, TCGOp *op)
52
53
static bool fold_or(OptContext *ctx, TCGOp *op)
54
{
55
- return fold_const2(ctx, op);
56
+ if (fold_const2(ctx, op) ||
57
+ fold_xx_to_x(ctx, op)) {
58
+ return true;
59
+ }
60
+ return false;
61
}
62
63
static bool fold_orc(OptContext *ctx, TCGOp *op)
64
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
65
break;
66
}
67
68
- /* Simplify expression for "op r, a, a => mov r, a" cases */
69
- switch (opc) {
70
- CASE_OP_32_64_VEC(or):
71
- CASE_OP_32_64_VEC(and):
72
- if (args_are_copies(op->args[1], op->args[2])) {
73
- tcg_opt_gen_mov(&ctx, op, op->args[0], op->args[1]);
74
- continue;
75
- }
76
- break;
77
- default:
78
- break;
79
- }
80
-
81
/*
82
* Process each opcode.
83
* Sorted alphabetically by opcode as much as possible.
84
--
85
2.25.1
86
87
diff view generated by jsdifflib
New patch
[PULL 37/56] tcg/optimize: Split out fold_xi_to_i
1
Pull the "op r, a, 0 => movi r, 0" optimization into a function,
2
and use it in the outer opcode fold functions.
1
3
4
Reviewed-by: Luis Pires <luis.pires@eldorado.org.br>
5
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
---
8
tcg/optimize.c | 38 ++++++++++++++++++++------------------
9
1 file changed, 20 insertions(+), 18 deletions(-)
10
11
diff --git a/tcg/optimize.c b/tcg/optimize.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/tcg/optimize.c
14
+++ b/tcg/optimize.c
15
@@ -XXX,XX +XXX,XX @@ static bool fold_const2(OptContext *ctx, TCGOp *op)
16
return false;
17
}
18
19
+/* If the binary operation has second argument @i, fold to @i. */
20
+static bool fold_xi_to_i(OptContext *ctx, TCGOp *op, uint64_t i)
21
+{
22
+ if (arg_is_const(op->args[2]) && arg_info(op->args[2])->val == i) {
23
+ return tcg_opt_gen_movi(ctx, op, op->args[0], i);
24
+ }
25
+ return false;
26
+}
27
+
28
/* If the binary operation has both arguments equal, fold to @i. */
29
static bool fold_xx_to_i(OptContext *ctx, TCGOp *op, uint64_t i)
30
{
31
@@ -XXX,XX +XXX,XX @@ static bool fold_add2_i32(OptContext *ctx, TCGOp *op)
32
static bool fold_and(OptContext *ctx, TCGOp *op)
33
{
34
if (fold_const2(ctx, op) ||
35
+ fold_xi_to_i(ctx, op, 0) ||
36
fold_xx_to_x(ctx, op)) {
37
return true;
38
}
39
@@ -XXX,XX +XXX,XX @@ static bool fold_movcond(OptContext *ctx, TCGOp *op)
40
41
static bool fold_mul(OptContext *ctx, TCGOp *op)
42
{
43
- return fold_const2(ctx, op);
44
+ if (fold_const2(ctx, op) ||
45
+ fold_xi_to_i(ctx, op, 0)) {
46
+ return true;
47
+ }
48
+ return false;
49
}
50
51
static bool fold_mul_highpart(OptContext *ctx, TCGOp *op)
52
{
53
- return fold_const2(ctx, op);
54
+ if (fold_const2(ctx, op) ||
55
+ fold_xi_to_i(ctx, op, 0)) {
56
+ return true;
57
+ }
58
+ return false;
59
}
60
61
static bool fold_mulu2_i32(OptContext *ctx, TCGOp *op)
62
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
63
continue;
64
}
65
66
- /* Simplify expression for "op r, a, 0 => movi r, 0" cases */
67
- switch (opc) {
68
- CASE_OP_32_64_VEC(and):
69
- CASE_OP_32_64_VEC(mul):
70
- CASE_OP_32_64(muluh):
71
- CASE_OP_32_64(mulsh):
72
- if (arg_is_const(op->args[2])
73
- && arg_info(op->args[2])->val == 0) {
74
- tcg_opt_gen_movi(&ctx, op, op->args[0], 0);
75
- continue;
76
- }
77
- break;
78
- default:
79
- break;
80
- }
81
-
82
/*
83
* Process each opcode.
84
* Sorted alphabetically by opcode as much as possible.
85
--
86
2.25.1
87
88
diff view generated by jsdifflib
[PATCH 26/27] include/exec: lightly re-arrange TranslationBlock
[PULL 38/56] tcg/optimize: Add type to OptContext
1
From: Alex Bennée <alex.bennee@linaro.org>
1
Compute the type of the operation early.
2
2
3
Lets make sure all the flags we compare when looking up blocks are
3
There are at least 4 places that used a def->flags ladder
4
together in the same place.
4
to determine the type of the operation being optimized.
5
5
6
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
6
There were two places that assumed !TCG_OPF_64BIT means
7
Message-Id: <20210224165811.11567-5-alex.bennee@linaro.org>
7
TCG_TYPE_I32, and so could potentially compute incorrect
8
results for vector operations.
9
10
Reviewed-by: Luis Pires <luis.pires@eldorado.org.br>
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
11
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
---
12
---
10
include/exec/exec-all.h | 8 +++++---
13
tcg/optimize.c | 149 +++++++++++++++++++++++++++++--------------------
11
1 file changed, 5 insertions(+), 3 deletions(-)
14
1 file changed, 89 insertions(+), 60 deletions(-)
12
15
13
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
16
diff --git a/tcg/optimize.c b/tcg/optimize.c
14
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
15
--- a/include/exec/exec-all.h
18
--- a/tcg/optimize.c
16
+++ b/include/exec/exec-all.h
19
+++ b/tcg/optimize.c
17
@@ -XXX,XX +XXX,XX @@ struct TranslationBlock {
20
@@ -XXX,XX +XXX,XX @@ typedef struct OptContext {
18
target_ulong pc; /* simulated PC corresponding to this block (EIP + CS base) */
21
19
target_ulong cs_base; /* CS base for this block */
22
/* In flight values from optimization. */
20
uint32_t flags; /* flags defining in which context the code was generated */
23
uint64_t z_mask;
21
- uint16_t size; /* size of target code for this block (1 <=
24
+ TCGType type;
22
- size <= TARGET_PAGE_SIZE) */
25
} OptContext;
23
- uint16_t icount;
26
24
uint32_t cflags; /* compile flags */
27
static inline TempOptInfo *ts_info(TCGTemp *ts)
25
#define CF_COUNT_MASK 0x00007fff
28
@@ -XXX,XX +XXX,XX @@ static bool tcg_opt_gen_mov(OptContext *ctx, TCGOp *op, TCGArg dst, TCGArg src)
26
#define CF_LAST_IO 0x00008000 /* Last insn may be an IO access. */
29
{
27
@@ -XXX,XX +XXX,XX @@ struct TranslationBlock {
30
TCGTemp *dst_ts = arg_temp(dst);
28
/* Per-vCPU dynamic tracing state used to generate this TB */
31
TCGTemp *src_ts = arg_temp(src);
29
uint32_t trace_vcpu_dstate;
32
- const TCGOpDef *def;
30
33
TempOptInfo *di;
31
+ /* Above fields used for comparing */
34
TempOptInfo *si;
32
+ uint16_t size; /* size of target code for this block (1 <=
35
uint64_t z_mask;
33
+ size <= TARGET_PAGE_SIZE) */
36
@@ -XXX,XX +XXX,XX @@ static bool tcg_opt_gen_mov(OptContext *ctx, TCGOp *op, TCGArg dst, TCGArg src)
34
+ uint16_t icount;
37
reset_ts(dst_ts);
38
di = ts_info(dst_ts);
39
si = ts_info(src_ts);
40
- def = &tcg_op_defs[op->opc];
41
- if (def->flags & TCG_OPF_VECTOR) {
42
- new_op = INDEX_op_mov_vec;
43
- } else if (def->flags & TCG_OPF_64BIT) {
44
- new_op = INDEX_op_mov_i64;
45
- } else {
35
+
46
+
36
struct tb_tc tc;
47
+ switch (ctx->type) {
37
48
+ case TCG_TYPE_I32:
38
/* first and second physical page containing code. The lower bit
49
new_op = INDEX_op_mov_i32;
50
+ break;
51
+ case TCG_TYPE_I64:
52
+ new_op = INDEX_op_mov_i64;
53
+ break;
54
+ case TCG_TYPE_V64:
55
+ case TCG_TYPE_V128:
56
+ case TCG_TYPE_V256:
57
+ /* TCGOP_VECL and TCGOP_VECE remain unchanged. */
58
+ new_op = INDEX_op_mov_vec;
59
+ break;
60
+ default:
61
+ g_assert_not_reached();
62
}
63
op->opc = new_op;
64
- /* TCGOP_VECL and TCGOP_VECE remain unchanged. */
65
op->args[0] = dst;
66
op->args[1] = src;
67
68
@@ -XXX,XX +XXX,XX @@ static bool tcg_opt_gen_mov(OptContext *ctx, TCGOp *op, TCGArg dst, TCGArg src)
69
static bool tcg_opt_gen_movi(OptContext *ctx, TCGOp *op,
70
TCGArg dst, uint64_t val)
71
{
72
- const TCGOpDef *def = &tcg_op_defs[op->opc];
73
- TCGType type;
74
- TCGTemp *tv;
75
-
76
- if (def->flags & TCG_OPF_VECTOR) {
77
- type = TCGOP_VECL(op) + TCG_TYPE_V64;
78
- } else if (def->flags & TCG_OPF_64BIT) {
79
- type = TCG_TYPE_I64;
80
- } else {
81
- type = TCG_TYPE_I32;
82
- }
83
-
84
/* Convert movi to mov with constant temp. */
85
- tv = tcg_constant_internal(type, val);
86
+ TCGTemp *tv = tcg_constant_internal(ctx->type, val);
87
+
88
init_ts_info(ctx, tv);
89
return tcg_opt_gen_mov(ctx, op, dst, temp_arg(tv));
90
}
91
@@ -XXX,XX +XXX,XX @@ static uint64_t do_constant_folding_2(TCGOpcode op, uint64_t x, uint64_t y)
92
}
93
}
94
95
-static uint64_t do_constant_folding(TCGOpcode op, uint64_t x, uint64_t y)
96
+static uint64_t do_constant_folding(TCGOpcode op, TCGType type,
97
+ uint64_t x, uint64_t y)
98
{
99
- const TCGOpDef *def = &tcg_op_defs[op];
100
uint64_t res = do_constant_folding_2(op, x, y);
101
- if (!(def->flags & TCG_OPF_64BIT)) {
102
+ if (type == TCG_TYPE_I32) {
103
res = (int32_t)res;
104
}
105
return res;
106
@@ -XXX,XX +XXX,XX @@ static bool do_constant_folding_cond_eq(TCGCond c)
107
* Return -1 if the condition can't be simplified,
108
* and the result of the condition (0 or 1) if it can.
109
*/
110
-static int do_constant_folding_cond(TCGOpcode op, TCGArg x,
111
+static int do_constant_folding_cond(TCGType type, TCGArg x,
112
TCGArg y, TCGCond c)
113
{
114
uint64_t xv = arg_info(x)->val;
115
uint64_t yv = arg_info(y)->val;
116
117
if (arg_is_const(x) && arg_is_const(y)) {
118
- const TCGOpDef *def = &tcg_op_defs[op];
119
- tcg_debug_assert(!(def->flags & TCG_OPF_VECTOR));
120
- if (def->flags & TCG_OPF_64BIT) {
121
- return do_constant_folding_cond_64(xv, yv, c);
122
- } else {
123
+ switch (type) {
124
+ case TCG_TYPE_I32:
125
return do_constant_folding_cond_32(xv, yv, c);
126
+ case TCG_TYPE_I64:
127
+ return do_constant_folding_cond_64(xv, yv, c);
128
+ default:
129
+ /* Only scalar comparisons are optimizable */
130
+ return -1;
131
}
132
} else if (args_are_copies(x, y)) {
133
return do_constant_folding_cond_eq(c);
134
@@ -XXX,XX +XXX,XX @@ static bool fold_const1(OptContext *ctx, TCGOp *op)
135
uint64_t t;
136
137
t = arg_info(op->args[1])->val;
138
- t = do_constant_folding(op->opc, t, 0);
139
+ t = do_constant_folding(op->opc, ctx->type, t, 0);
140
return tcg_opt_gen_movi(ctx, op, op->args[0], t);
141
}
142
return false;
143
@@ -XXX,XX +XXX,XX @@ static bool fold_const2(OptContext *ctx, TCGOp *op)
144
uint64_t t1 = arg_info(op->args[1])->val;
145
uint64_t t2 = arg_info(op->args[2])->val;
146
147
- t1 = do_constant_folding(op->opc, t1, t2);
148
+ t1 = do_constant_folding(op->opc, ctx->type, t1, t2);
149
return tcg_opt_gen_movi(ctx, op, op->args[0], t1);
150
}
151
return false;
152
@@ -XXX,XX +XXX,XX @@ static bool fold_andc(OptContext *ctx, TCGOp *op)
153
static bool fold_brcond(OptContext *ctx, TCGOp *op)
154
{
155
TCGCond cond = op->args[2];
156
- int i = do_constant_folding_cond(op->opc, op->args[0], op->args[1], cond);
157
+ int i = do_constant_folding_cond(ctx->type, op->args[0], op->args[1], cond);
158
159
if (i == 0) {
160
tcg_op_remove(ctx->tcg, op);
161
@@ -XXX,XX +XXX,XX @@ static bool fold_brcond2(OptContext *ctx, TCGOp *op)
162
* Simplify EQ/NE comparisons where one of the pairs
163
* can be simplified.
164
*/
165
- i = do_constant_folding_cond(INDEX_op_brcond_i32, op->args[0],
166
+ i = do_constant_folding_cond(TCG_TYPE_I32, op->args[0],
167
op->args[2], cond);
168
switch (i ^ inv) {
169
case 0:
170
@@ -XXX,XX +XXX,XX @@ static bool fold_brcond2(OptContext *ctx, TCGOp *op)
171
goto do_brcond_high;
172
}
173
174
- i = do_constant_folding_cond(INDEX_op_brcond_i32, op->args[1],
175
+ i = do_constant_folding_cond(TCG_TYPE_I32, op->args[1],
176
op->args[3], cond);
177
switch (i ^ inv) {
178
case 0:
179
@@ -XXX,XX +XXX,XX @@ static bool fold_bswap(OptContext *ctx, TCGOp *op)
180
if (arg_is_const(op->args[1])) {
181
uint64_t t = arg_info(op->args[1])->val;
182
183
- t = do_constant_folding(op->opc, t, op->args[2]);
184
+ t = do_constant_folding(op->opc, ctx->type, t, op->args[2]);
185
return tcg_opt_gen_movi(ctx, op, op->args[0], t);
186
}
187
return false;
188
@@ -XXX,XX +XXX,XX @@ static bool fold_count_zeros(OptContext *ctx, TCGOp *op)
189
uint64_t t = arg_info(op->args[1])->val;
190
191
if (t != 0) {
192
- t = do_constant_folding(op->opc, t, 0);
193
+ t = do_constant_folding(op->opc, ctx->type, t, 0);
194
return tcg_opt_gen_movi(ctx, op, op->args[0], t);
195
}
196
return tcg_opt_gen_mov(ctx, op, op->args[0], op->args[2]);
197
@@ -XXX,XX +XXX,XX @@ static bool fold_mov(OptContext *ctx, TCGOp *op)
198
199
static bool fold_movcond(OptContext *ctx, TCGOp *op)
200
{
201
- TCGOpcode opc = op->opc;
202
TCGCond cond = op->args[5];
203
- int i = do_constant_folding_cond(opc, op->args[1], op->args[2], cond);
204
+ int i = do_constant_folding_cond(ctx->type, op->args[1], op->args[2], cond);
205
206
if (i >= 0) {
207
return tcg_opt_gen_mov(ctx, op, op->args[0], op->args[4 - i]);
208
@@ -XXX,XX +XXX,XX @@ static bool fold_movcond(OptContext *ctx, TCGOp *op)
209
if (arg_is_const(op->args[3]) && arg_is_const(op->args[4])) {
210
uint64_t tv = arg_info(op->args[3])->val;
211
uint64_t fv = arg_info(op->args[4])->val;
212
+ TCGOpcode opc;
213
214
- opc = (opc == INDEX_op_movcond_i32
215
- ? INDEX_op_setcond_i32 : INDEX_op_setcond_i64);
216
+ switch (ctx->type) {
217
+ case TCG_TYPE_I32:
218
+ opc = INDEX_op_setcond_i32;
219
+ break;
220
+ case TCG_TYPE_I64:
221
+ opc = INDEX_op_setcond_i64;
222
+ break;
223
+ default:
224
+ g_assert_not_reached();
225
+ }
226
227
if (tv == 1 && fv == 0) {
228
op->opc = opc;
229
@@ -XXX,XX +XXX,XX @@ static bool fold_remainder(OptContext *ctx, TCGOp *op)
230
static bool fold_setcond(OptContext *ctx, TCGOp *op)
231
{
232
TCGCond cond = op->args[3];
233
- int i = do_constant_folding_cond(op->opc, op->args[1], op->args[2], cond);
234
+ int i = do_constant_folding_cond(ctx->type, op->args[1], op->args[2], cond);
235
236
if (i >= 0) {
237
return tcg_opt_gen_movi(ctx, op, op->args[0], i);
238
@@ -XXX,XX +XXX,XX @@ static bool fold_setcond2(OptContext *ctx, TCGOp *op)
239
* Simplify EQ/NE comparisons where one of the pairs
240
* can be simplified.
241
*/
242
- i = do_constant_folding_cond(INDEX_op_setcond_i32, op->args[1],
243
+ i = do_constant_folding_cond(TCG_TYPE_I32, op->args[1],
244
op->args[3], cond);
245
switch (i ^ inv) {
246
case 0:
247
@@ -XXX,XX +XXX,XX @@ static bool fold_setcond2(OptContext *ctx, TCGOp *op)
248
goto do_setcond_high;
249
}
250
251
- i = do_constant_folding_cond(INDEX_op_setcond_i32, op->args[2],
252
+ i = do_constant_folding_cond(TCG_TYPE_I32, op->args[2],
253
op->args[4], cond);
254
switch (i ^ inv) {
255
case 0:
256
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
257
init_arguments(&ctx, op, def->nb_oargs + def->nb_iargs);
258
copy_propagate(&ctx, op, def->nb_oargs, def->nb_iargs);
259
260
+ /* Pre-compute the type of the operation. */
261
+ if (def->flags & TCG_OPF_VECTOR) {
262
+ ctx.type = TCG_TYPE_V64 + TCGOP_VECL(op);
263
+ } else if (def->flags & TCG_OPF_64BIT) {
264
+ ctx.type = TCG_TYPE_I64;
265
+ } else {
266
+ ctx.type = TCG_TYPE_I32;
267
+ }
268
+
269
/* For commutative operations make constant second argument */
270
switch (opc) {
271
CASE_OP_32_64_VEC(add):
272
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
273
/* Proceed with possible constant folding. */
274
break;
275
}
276
- if (opc == INDEX_op_sub_i32) {
277
+ switch (ctx.type) {
278
+ case TCG_TYPE_I32:
279
neg_op = INDEX_op_neg_i32;
280
have_neg = TCG_TARGET_HAS_neg_i32;
281
- } else if (opc == INDEX_op_sub_i64) {
282
+ break;
283
+ case TCG_TYPE_I64:
284
neg_op = INDEX_op_neg_i64;
285
have_neg = TCG_TARGET_HAS_neg_i64;
286
- } else if (TCG_TARGET_HAS_neg_vec) {
287
- TCGType type = TCGOP_VECL(op) + TCG_TYPE_V64;
288
- unsigned vece = TCGOP_VECE(op);
289
- neg_op = INDEX_op_neg_vec;
290
- have_neg = tcg_can_emit_vec_op(neg_op, type, vece) > 0;
291
- } else {
292
break;
293
+ case TCG_TYPE_V64:
294
+ case TCG_TYPE_V128:
295
+ case TCG_TYPE_V256:
296
+ neg_op = INDEX_op_neg_vec;
297
+ have_neg = tcg_can_emit_vec_op(neg_op, ctx.type,
298
+ TCGOP_VECE(op)) > 0;
299
+ break;
300
+ default:
301
+ g_assert_not_reached();
302
}
303
if (!have_neg) {
304
break;
305
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
306
TCGOpcode not_op;
307
bool have_not;
308
309
- if (def->flags & TCG_OPF_VECTOR) {
310
- not_op = INDEX_op_not_vec;
311
- have_not = TCG_TARGET_HAS_not_vec;
312
- } else if (def->flags & TCG_OPF_64BIT) {
313
- not_op = INDEX_op_not_i64;
314
- have_not = TCG_TARGET_HAS_not_i64;
315
- } else {
316
+ switch (ctx.type) {
317
+ case TCG_TYPE_I32:
318
not_op = INDEX_op_not_i32;
319
have_not = TCG_TARGET_HAS_not_i32;
320
+ break;
321
+ case TCG_TYPE_I64:
322
+ not_op = INDEX_op_not_i64;
323
+ have_not = TCG_TARGET_HAS_not_i64;
324
+ break;
325
+ case TCG_TYPE_V64:
326
+ case TCG_TYPE_V128:
327
+ case TCG_TYPE_V256:
328
+ not_op = INDEX_op_not_vec;
329
+ have_not = TCG_TARGET_HAS_not_vec;
330
+ break;
331
+ default:
332
+ g_assert_not_reached();
333
}
334
if (!have_not) {
335
break;
336
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
337
below, we can ignore high bits, but for further optimizations we
338
need to record that the high bits contain garbage. */
339
partmask = z_mask;
340
- if (!(def->flags & TCG_OPF_64BIT)) {
341
+ if (ctx.type == TCG_TYPE_I32) {
342
z_mask |= ~(tcg_target_ulong)0xffffffffu;
343
partmask &= 0xffffffffu;
344
affected &= 0xffffffffu;
39
--
345
--
40
2.25.1
346
2.25.1
41
347
42
348
diff view generated by jsdifflib
[PATCH 23/27] accel/tcg: rename tb_lookup__cpu_state and hoist state extraction
[PULL 39/56] tcg/optimize: Split out fold_to_not
1
From: Alex Bennée <alex.bennee@linaro.org>
1
Split out the conditional conversion from a more complex logical
2
2
operation to a simple NOT. Create a couple more helpers to make
3
Having a function return either and valid TB and some system state
3
this easy for the outer-most logical operations.
4
seems excessive. It will make the subsequent re-factoring easier if we
4
5
lookup the current state where we are.
5
Reviewed-by: Luis Pires <luis.pires@eldorado.org.br>
6
7
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
8
Message-Id: <20210224165811.11567-2-alex.bennee@linaro.org>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
---
7
---
11
include/exec/tb-lookup.h | 18 ++++++++----------
8
tcg/optimize.c | 158 +++++++++++++++++++++++++++----------------------
12
accel/tcg/cpu-exec.c | 10 ++++++++--
9
1 file changed, 86 insertions(+), 72 deletions(-)
13
accel/tcg/tcg-runtime.c | 4 +++-
10
14
3 files changed, 19 insertions(+), 13 deletions(-)
11
diff --git a/tcg/optimize.c b/tcg/optimize.c
15
16
diff --git a/include/exec/tb-lookup.h b/include/exec/tb-lookup.h
17
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
18
--- a/include/exec/tb-lookup.h
13
--- a/tcg/optimize.c
19
+++ b/include/exec/tb-lookup.h
14
+++ b/tcg/optimize.c
20
@@ -XXX,XX +XXX,XX @@
15
@@ -XXX,XX +XXX,XX @@ static bool fold_const2(OptContext *ctx, TCGOp *op)
21
#include "exec/tb-hash.h"
16
return false;
22
17
}
23
/* Might cause an exception, so have a longjmp destination ready */
18
24
-static inline TranslationBlock *
19
+/*
25
-tb_lookup__cpu_state(CPUState *cpu, target_ulong *pc, target_ulong *cs_base,
20
+ * Convert @op to NOT, if NOT is supported by the host.
26
- uint32_t *flags, uint32_t cf_mask)
21
+ * Return true f the conversion is successful, which will still
27
+static inline TranslationBlock * tb_lookup(CPUState *cpu,
22
+ * indicate that the processing is complete.
28
+ target_ulong pc, target_ulong cs_base,
23
+ */
29
+ uint32_t flags, uint32_t cf_mask)
24
+static bool fold_not(OptContext *ctx, TCGOp *op);
30
{
25
+static bool fold_to_not(OptContext *ctx, TCGOp *op, int idx)
31
- CPUArchState *env = (CPUArchState *)cpu->env_ptr;
26
+{
32
TranslationBlock *tb;
27
+ TCGOpcode not_op;
33
uint32_t hash;
28
+ bool have_not;
34
29
+
35
- cpu_get_tb_cpu_state(env, pc, cs_base, flags);
30
+ switch (ctx->type) {
36
- hash = tb_jmp_cache_hash_func(*pc);
31
+ case TCG_TYPE_I32:
37
+ hash = tb_jmp_cache_hash_func(pc);
32
+ not_op = INDEX_op_not_i32;
38
tb = qatomic_rcu_read(&cpu->tb_jmp_cache[hash]);
33
+ have_not = TCG_TARGET_HAS_not_i32;
39
34
+ break;
40
cf_mask &= ~CF_CLUSTER_MASK;
35
+ case TCG_TYPE_I64:
41
cf_mask |= cpu->cluster_index << CF_CLUSTER_SHIFT;
36
+ not_op = INDEX_op_not_i64;
42
37
+ have_not = TCG_TARGET_HAS_not_i64;
43
if (likely(tb &&
38
+ break;
44
- tb->pc == *pc &&
39
+ case TCG_TYPE_V64:
45
- tb->cs_base == *cs_base &&
40
+ case TCG_TYPE_V128:
46
- tb->flags == *flags &&
41
+ case TCG_TYPE_V256:
47
+ tb->pc == pc &&
42
+ not_op = INDEX_op_not_vec;
48
+ tb->cs_base == cs_base &&
43
+ have_not = TCG_TARGET_HAS_not_vec;
49
+ tb->flags == flags &&
44
+ break;
50
tb->trace_vcpu_dstate == *cpu->trace_dstate &&
45
+ default:
51
(tb_cflags(tb) & (CF_HASH_MASK | CF_INVALID)) == cf_mask)) {
46
+ g_assert_not_reached();
52
return tb;
47
+ }
48
+ if (have_not) {
49
+ op->opc = not_op;
50
+ op->args[1] = op->args[idx];
51
+ return fold_not(ctx, op);
52
+ }
53
+ return false;
54
+}
55
+
56
+/* If the binary operation has first argument @i, fold to NOT. */
57
+static bool fold_ix_to_not(OptContext *ctx, TCGOp *op, uint64_t i)
58
+{
59
+ if (arg_is_const(op->args[1]) && arg_info(op->args[1])->val == i) {
60
+ return fold_to_not(ctx, op, 2);
61
+ }
62
+ return false;
63
+}
64
+
65
/* If the binary operation has second argument @i, fold to @i. */
66
static bool fold_xi_to_i(OptContext *ctx, TCGOp *op, uint64_t i)
67
{
68
@@ -XXX,XX +XXX,XX @@ static bool fold_xi_to_i(OptContext *ctx, TCGOp *op, uint64_t i)
69
return false;
70
}
71
72
+/* If the binary operation has second argument @i, fold to NOT. */
73
+static bool fold_xi_to_not(OptContext *ctx, TCGOp *op, uint64_t i)
74
+{
75
+ if (arg_is_const(op->args[2]) && arg_info(op->args[2])->val == i) {
76
+ return fold_to_not(ctx, op, 1);
77
+ }
78
+ return false;
79
+}
80
+
81
/* If the binary operation has both arguments equal, fold to @i. */
82
static bool fold_xx_to_i(OptContext *ctx, TCGOp *op, uint64_t i)
83
{
84
@@ -XXX,XX +XXX,XX @@ static bool fold_and(OptContext *ctx, TCGOp *op)
85
static bool fold_andc(OptContext *ctx, TCGOp *op)
86
{
87
if (fold_const2(ctx, op) ||
88
- fold_xx_to_i(ctx, op, 0)) {
89
+ fold_xx_to_i(ctx, op, 0) ||
90
+ fold_ix_to_not(ctx, op, -1)) {
91
return true;
53
}
92
}
54
- tb = tb_htable_lookup(cpu, *pc, *cs_base, *flags, cf_mask);
93
return false;
55
+ tb = tb_htable_lookup(cpu, pc, cs_base, flags, cf_mask);
94
@@ -XXX,XX +XXX,XX @@ static bool fold_dup2(OptContext *ctx, TCGOp *op)
56
if (tb == NULL) {
95
57
return NULL;
96
static bool fold_eqv(OptContext *ctx, TCGOp *op)
97
{
98
- return fold_const2(ctx, op);
99
+ if (fold_const2(ctx, op) ||
100
+ fold_xi_to_not(ctx, op, 0)) {
101
+ return true;
102
+ }
103
+ return false;
104
}
105
106
static bool fold_extract(OptContext *ctx, TCGOp *op)
107
@@ -XXX,XX +XXX,XX @@ static bool fold_mulu2_i32(OptContext *ctx, TCGOp *op)
108
109
static bool fold_nand(OptContext *ctx, TCGOp *op)
110
{
111
- return fold_const2(ctx, op);
112
+ if (fold_const2(ctx, op) ||
113
+ fold_xi_to_not(ctx, op, -1)) {
114
+ return true;
115
+ }
116
+ return false;
117
}
118
119
static bool fold_neg(OptContext *ctx, TCGOp *op)
120
@@ -XXX,XX +XXX,XX @@ static bool fold_neg(OptContext *ctx, TCGOp *op)
121
122
static bool fold_nor(OptContext *ctx, TCGOp *op)
123
{
124
- return fold_const2(ctx, op);
125
+ if (fold_const2(ctx, op) ||
126
+ fold_xi_to_not(ctx, op, 0)) {
127
+ return true;
128
+ }
129
+ return false;
130
}
131
132
static bool fold_not(OptContext *ctx, TCGOp *op)
133
{
134
- return fold_const1(ctx, op);
135
+ if (fold_const1(ctx, op)) {
136
+ return true;
137
+ }
138
+
139
+ /* Because of fold_to_not, we want to always return true, via finish. */
140
+ finish_folding(ctx, op);
141
+ return true;
142
}
143
144
static bool fold_or(OptContext *ctx, TCGOp *op)
145
@@ -XXX,XX +XXX,XX @@ static bool fold_or(OptContext *ctx, TCGOp *op)
146
147
static bool fold_orc(OptContext *ctx, TCGOp *op)
148
{
149
- return fold_const2(ctx, op);
150
+ if (fold_const2(ctx, op) ||
151
+ fold_ix_to_not(ctx, op, 0)) {
152
+ return true;
153
+ }
154
+ return false;
155
}
156
157
static bool fold_qemu_ld(OptContext *ctx, TCGOp *op)
158
@@ -XXX,XX +XXX,XX @@ static bool fold_sub2_i32(OptContext *ctx, TCGOp *op)
159
static bool fold_xor(OptContext *ctx, TCGOp *op)
160
{
161
if (fold_const2(ctx, op) ||
162
- fold_xx_to_i(ctx, op, 0)) {
163
+ fold_xx_to_i(ctx, op, 0) ||
164
+ fold_xi_to_not(ctx, op, -1)) {
165
return true;
58
}
166
}
59
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
167
return false;
60
index XXXXXXX..XXXXXXX 100644
168
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
61
--- a/accel/tcg/cpu-exec.c
169
}
62
+++ b/accel/tcg/cpu-exec.c
170
}
63
@@ -XXX,XX +XXX,XX @@ static void cpu_exec_exit(CPUState *cpu)
171
break;
64
172
- CASE_OP_32_64_VEC(xor):
65
void cpu_exec_step_atomic(CPUState *cpu)
173
- CASE_OP_32_64(nand):
66
{
174
- if (!arg_is_const(op->args[1])
67
+ CPUArchState *env = (CPUArchState *)cpu->env_ptr;
175
- && arg_is_const(op->args[2])
68
TranslationBlock *tb;
176
- && arg_info(op->args[2])->val == -1) {
69
target_ulong cs_base, pc;
177
- i = 1;
70
uint32_t flags;
178
- goto try_not;
71
@@ -XXX,XX +XXX,XX @@ void cpu_exec_step_atomic(CPUState *cpu)
179
- }
72
g_assert(!cpu->running);
180
- break;
73
cpu->running = true;
181
- CASE_OP_32_64(nor):
74
182
- if (!arg_is_const(op->args[1])
75
- tb = tb_lookup__cpu_state(cpu, &pc, &cs_base, &flags, cf_mask);
183
- && arg_is_const(op->args[2])
76
+ cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags);
184
- && arg_info(op->args[2])->val == 0) {
77
+ tb = tb_lookup(cpu, pc, cs_base, flags, cf_mask);
185
- i = 1;
78
+
186
- goto try_not;
79
if (tb == NULL) {
187
- }
80
mmap_lock();
188
- break;
81
tb = tb_gen_code(cpu, pc, cs_base, flags, cflags);
189
- CASE_OP_32_64_VEC(andc):
82
@@ -XXX,XX +XXX,XX @@ static inline TranslationBlock *tb_find(CPUState *cpu,
190
- if (!arg_is_const(op->args[2])
83
TranslationBlock *last_tb,
191
- && arg_is_const(op->args[1])
84
int tb_exit, uint32_t cf_mask)
192
- && arg_info(op->args[1])->val == -1) {
85
{
193
- i = 2;
86
+ CPUArchState *env = (CPUArchState *)cpu->env_ptr;
194
- goto try_not;
87
TranslationBlock *tb;
195
- }
88
target_ulong cs_base, pc;
196
- break;
89
uint32_t flags;
197
- CASE_OP_32_64_VEC(orc):
90
198
- CASE_OP_32_64(eqv):
91
- tb = tb_lookup__cpu_state(cpu, &pc, &cs_base, &flags, cf_mask);
199
- if (!arg_is_const(op->args[2])
92
+ cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags);
200
- && arg_is_const(op->args[1])
93
+
201
- && arg_info(op->args[1])->val == 0) {
94
+ tb = tb_lookup(cpu, pc, cs_base, flags, cf_mask);
202
- i = 2;
95
if (tb == NULL) {
203
- goto try_not;
96
mmap_lock();
204
- }
97
tb = tb_gen_code(cpu, pc, cs_base, flags, cf_mask);
205
- break;
98
diff --git a/accel/tcg/tcg-runtime.c b/accel/tcg/tcg-runtime.c
206
- try_not:
99
index XXXXXXX..XXXXXXX 100644
207
- {
100
--- a/accel/tcg/tcg-runtime.c
208
- TCGOpcode not_op;
101
+++ b/accel/tcg/tcg-runtime.c
209
- bool have_not;
102
@@ -XXX,XX +XXX,XX @@ const void *HELPER(lookup_tb_ptr)(CPUArchState *env)
210
-
103
target_ulong cs_base, pc;
211
- switch (ctx.type) {
104
uint32_t flags;
212
- case TCG_TYPE_I32:
105
213
- not_op = INDEX_op_not_i32;
106
- tb = tb_lookup__cpu_state(cpu, &pc, &cs_base, &flags, curr_cflags());
214
- have_not = TCG_TARGET_HAS_not_i32;
107
+ cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags);
215
- break;
108
+
216
- case TCG_TYPE_I64:
109
+ tb = tb_lookup(cpu, pc, cs_base, flags, curr_cflags());
217
- not_op = INDEX_op_not_i64;
110
if (tb == NULL) {
218
- have_not = TCG_TARGET_HAS_not_i64;
111
return tcg_code_gen_epilogue;
219
- break;
112
}
220
- case TCG_TYPE_V64:
221
- case TCG_TYPE_V128:
222
- case TCG_TYPE_V256:
223
- not_op = INDEX_op_not_vec;
224
- have_not = TCG_TARGET_HAS_not_vec;
225
- break;
226
- default:
227
- g_assert_not_reached();
228
- }
229
- if (!have_not) {
230
- break;
231
- }
232
- op->opc = not_op;
233
- reset_temp(op->args[0]);
234
- op->args[1] = op->args[i];
235
- continue;
236
- }
237
default:
238
break;
239
}
113
--
240
--
114
2.25.1
241
2.25.1
115
242
116
243
diff view generated by jsdifflib
[PATCH 20/27] tcg/tci: Merge extension operations
[PULL 40/56] tcg/optimize: Split out fold_sub_to_neg
1
This includes ext8s, ext8u, ext16s, ext16u.
1
Even though there is only one user, place this more complex
2
conversion into its own helper.
2
3
3
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
4
Reviewed-by: Luis Pires <luis.pires@eldorado.org.br>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
---
6
---
6
tcg/tci.c | 44 ++++++++------------------------------------
7
tcg/optimize.c | 89 ++++++++++++++++++++++++++------------------------
7
1 file changed, 8 insertions(+), 36 deletions(-)
8
1 file changed, 47 insertions(+), 42 deletions(-)
8
9
9
diff --git a/tcg/tci.c b/tcg/tci.c
10
diff --git a/tcg/optimize.c b/tcg/optimize.c
10
index XXXXXXX..XXXXXXX 100644
11
index XXXXXXX..XXXXXXX 100644
11
--- a/tcg/tci.c
12
--- a/tcg/optimize.c
12
+++ b/tcg/tci.c
13
+++ b/tcg/optimize.c
13
@@ -XXX,XX +XXX,XX @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
14
@@ -XXX,XX +XXX,XX @@ static bool fold_nand(OptContext *ctx, TCGOp *op)
14
tci_write_reg64(regs, t1, t0, (uint32_t)t2 * tmp64);
15
15
break;
16
static bool fold_neg(OptContext *ctx, TCGOp *op)
16
#endif /* TCG_TARGET_REG_BITS == 32 */
17
{
17
-#if TCG_TARGET_HAS_ext8s_i32
18
- return fold_const1(ctx, op);
18
- case INDEX_op_ext8s_i32:
19
+ if (fold_const1(ctx, op)) {
19
+#if TCG_TARGET_HAS_ext8s_i32 || TCG_TARGET_HAS_ext8s_i64
20
+ return true;
20
+ CASE_32_64(ext8s)
21
+ }
21
t0 = *tb_ptr++;
22
+ /*
22
t1 = tci_read_r(regs, &tb_ptr);
23
+ * Because of fold_sub_to_neg, we want to always return true,
23
tci_write_reg(regs, t0, (int8_t)t1);
24
+ * via finish_folding.
24
break;
25
+ */
25
#endif
26
+ finish_folding(ctx, op);
26
-#if TCG_TARGET_HAS_ext16s_i32
27
+ return true;
27
- case INDEX_op_ext16s_i32:
28
}
28
+#if TCG_TARGET_HAS_ext16s_i32 || TCG_TARGET_HAS_ext16s_i64
29
29
+ CASE_32_64(ext16s)
30
static bool fold_nor(OptContext *ctx, TCGOp *op)
30
t0 = *tb_ptr++;
31
@@ -XXX,XX +XXX,XX @@ static bool fold_shift(OptContext *ctx, TCGOp *op)
31
t1 = tci_read_r(regs, &tb_ptr);
32
return fold_const2(ctx, op);
32
tci_write_reg(regs, t0, (int16_t)t1);
33
}
33
break;
34
34
#endif
35
+static bool fold_sub_to_neg(OptContext *ctx, TCGOp *op)
35
-#if TCG_TARGET_HAS_ext8u_i32
36
+{
36
- case INDEX_op_ext8u_i32:
37
+ TCGOpcode neg_op;
37
+#if TCG_TARGET_HAS_ext8u_i32 || TCG_TARGET_HAS_ext8u_i64
38
+ bool have_neg;
38
+ CASE_32_64(ext8u)
39
+
39
t0 = *tb_ptr++;
40
+ if (!arg_is_const(op->args[1]) || arg_info(op->args[1])->val != 0) {
40
t1 = tci_read_r(regs, &tb_ptr);
41
+ return false;
41
tci_write_reg(regs, t0, (uint8_t)t1);
42
+ }
42
break;
43
+
43
#endif
44
+ switch (ctx->type) {
44
-#if TCG_TARGET_HAS_ext16u_i32
45
+ case TCG_TYPE_I32:
45
- case INDEX_op_ext16u_i32:
46
+ neg_op = INDEX_op_neg_i32;
46
+#if TCG_TARGET_HAS_ext16u_i32 || TCG_TARGET_HAS_ext16u_i64
47
+ have_neg = TCG_TARGET_HAS_neg_i32;
47
+ CASE_32_64(ext16u)
48
+ break;
48
t0 = *tb_ptr++;
49
+ case TCG_TYPE_I64:
49
t1 = tci_read_r(regs, &tb_ptr);
50
+ neg_op = INDEX_op_neg_i64;
50
tci_write_reg(regs, t0, (uint16_t)t1);
51
+ have_neg = TCG_TARGET_HAS_neg_i64;
51
@@ -XXX,XX +XXX,XX @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
52
+ break;
53
+ case TCG_TYPE_V64:
54
+ case TCG_TYPE_V128:
55
+ case TCG_TYPE_V256:
56
+ neg_op = INDEX_op_neg_vec;
57
+ have_neg = (TCG_TARGET_HAS_neg_vec &&
58
+ tcg_can_emit_vec_op(neg_op, ctx->type, TCGOP_VECE(op)) > 0);
59
+ break;
60
+ default:
61
+ g_assert_not_reached();
62
+ }
63
+ if (have_neg) {
64
+ op->opc = neg_op;
65
+ op->args[1] = op->args[2];
66
+ return fold_neg(ctx, op);
67
+ }
68
+ return false;
69
+}
70
+
71
static bool fold_sub(OptContext *ctx, TCGOp *op)
72
{
73
if (fold_const2(ctx, op) ||
74
- fold_xx_to_i(ctx, op, 0)) {
75
+ fold_xx_to_i(ctx, op, 0) ||
76
+ fold_sub_to_neg(ctx, op)) {
77
return true;
78
}
79
return false;
80
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
52
continue;
81
continue;
53
}
82
}
54
break;
83
break;
55
-#if TCG_TARGET_HAS_ext8u_i64
84
- CASE_OP_32_64_VEC(sub):
56
- case INDEX_op_ext8u_i64:
85
- {
57
- t0 = *tb_ptr++;
86
- TCGOpcode neg_op;
58
- t1 = tci_read_r(regs, &tb_ptr);
87
- bool have_neg;
59
- tci_write_reg(regs, t0, (uint8_t)t1);
88
-
89
- if (arg_is_const(op->args[2])) {
90
- /* Proceed with possible constant folding. */
91
- break;
92
- }
93
- switch (ctx.type) {
94
- case TCG_TYPE_I32:
95
- neg_op = INDEX_op_neg_i32;
96
- have_neg = TCG_TARGET_HAS_neg_i32;
97
- break;
98
- case TCG_TYPE_I64:
99
- neg_op = INDEX_op_neg_i64;
100
- have_neg = TCG_TARGET_HAS_neg_i64;
101
- break;
102
- case TCG_TYPE_V64:
103
- case TCG_TYPE_V128:
104
- case TCG_TYPE_V256:
105
- neg_op = INDEX_op_neg_vec;
106
- have_neg = tcg_can_emit_vec_op(neg_op, ctx.type,
107
- TCGOP_VECE(op)) > 0;
108
- break;
109
- default:
110
- g_assert_not_reached();
111
- }
112
- if (!have_neg) {
113
- break;
114
- }
115
- if (arg_is_const(op->args[1])
116
- && arg_info(op->args[1])->val == 0) {
117
- op->opc = neg_op;
118
- reset_temp(op->args[0]);
119
- op->args[1] = op->args[2];
120
- continue;
121
- }
122
- }
60
- break;
123
- break;
61
-#endif
124
default:
62
-#if TCG_TARGET_HAS_ext8s_i64
125
break;
63
- case INDEX_op_ext8s_i64:
126
}
64
- t0 = *tb_ptr++;
65
- t1 = tci_read_r(regs, &tb_ptr);
66
- tci_write_reg(regs, t0, (int8_t)t1);
67
- break;
68
-#endif
69
-#if TCG_TARGET_HAS_ext16s_i64
70
- case INDEX_op_ext16s_i64:
71
- t0 = *tb_ptr++;
72
- t1 = tci_read_r(regs, &tb_ptr);
73
- tci_write_reg(regs, t0, (int16_t)t1);
74
- break;
75
-#endif
76
-#if TCG_TARGET_HAS_ext16u_i64
77
- case INDEX_op_ext16u_i64:
78
- t0 = *tb_ptr++;
79
- t1 = tci_read_r(regs, &tb_ptr);
80
- tci_write_reg(regs, t0, (uint16_t)t1);
81
- break;
82
-#endif
83
#if TCG_TARGET_HAS_ext32s_i64
84
case INDEX_op_ext32s_i64:
85
#endif
86
--
127
--
87
2.25.1
128
2.25.1
88
129
89
130
diff view generated by jsdifflib
[PATCH 24/27] accel/tcg: move CF_CLUSTER calculation to curr_cflags
[PULL 41/56] tcg/optimize: Split out fold_xi_to_x
1
From: Alex Bennée <alex.bennee@linaro.org>
1
Pull the "op r, a, i => mov r, a" optimization into a function,
2
and use them in the outer-most logical operations.
2
3
3
There is nothing special about this compile flag that doesn't mean we
4
Reviewed-by: Luis Pires <luis.pires@eldorado.org.br>
4
can't just compute it with curr_cflags() which we should be using when
5
building a new set.
6
7
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
8
Message-Id: <20210224165811.11567-3-alex.bennee@linaro.org>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
---
6
---
11
include/exec/exec-all.h | 8 +++++---
7
tcg/optimize.c | 61 +++++++++++++++++++++-----------------------------
12
include/exec/tb-lookup.h | 3 ---
8
1 file changed, 26 insertions(+), 35 deletions(-)
13
accel/tcg/cpu-exec.c | 9 ++++-----
14
accel/tcg/tcg-runtime.c | 2 +-
15
accel/tcg/translate-all.c | 6 +++---
16
softmmu/physmem.c | 2 +-
17
6 files changed, 14 insertions(+), 16 deletions(-)
18
9
19
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
10
diff --git a/tcg/optimize.c b/tcg/optimize.c
20
index XXXXXXX..XXXXXXX 100644
11
index XXXXXXX..XXXXXXX 100644
21
--- a/include/exec/exec-all.h
12
--- a/tcg/optimize.c
22
+++ b/include/exec/exec-all.h
13
+++ b/tcg/optimize.c
23
@@ -XXX,XX +XXX,XX @@ static inline uint32_t tb_cflags(const TranslationBlock *tb)
14
@@ -XXX,XX +XXX,XX @@ static bool fold_xi_to_i(OptContext *ctx, TCGOp *op, uint64_t i)
15
return false;
24
}
16
}
25
17
26
/* current cflags for hashing/comparison */
18
+/* If the binary operation has second argument @i, fold to identity. */
27
-static inline uint32_t curr_cflags(void)
19
+static bool fold_xi_to_x(OptContext *ctx, TCGOp *op, uint64_t i)
28
+static inline uint32_t curr_cflags(CPUState *cpu)
20
+{
21
+ if (arg_is_const(op->args[2]) && arg_info(op->args[2])->val == i) {
22
+ return tcg_opt_gen_mov(ctx, op, op->args[0], op->args[1]);
23
+ }
24
+ return false;
25
+}
26
+
27
/* If the binary operation has second argument @i, fold to NOT. */
28
static bool fold_xi_to_not(OptContext *ctx, TCGOp *op, uint64_t i)
29
{
29
{
30
- return (parallel_cpus ? CF_PARALLEL : 0)
30
@@ -XXX,XX +XXX,XX @@ static bool fold_xx_to_x(OptContext *ctx, TCGOp *op)
31
- | (icount_enabled() ? CF_USE_ICOUNT : 0);
31
32
+ uint32_t cflags = deposit32(0, CF_CLUSTER_SHIFT, 8, cpu->cluster_index);
32
static bool fold_add(OptContext *ctx, TCGOp *op)
33
+ cflags |= parallel_cpus ? CF_PARALLEL : 0;
33
{
34
+ cflags |= icount_enabled() ? CF_USE_ICOUNT : 0;
34
- return fold_const2(ctx, op);
35
+ return cflags;
35
+ if (fold_const2(ctx, op) ||
36
+ fold_xi_to_x(ctx, op, 0)) {
37
+ return true;
38
+ }
39
+ return false;
36
}
40
}
37
41
38
/* TranslationBlock invalidate API */
42
static bool fold_addsub2_i32(OptContext *ctx, TCGOp *op, bool add)
39
diff --git a/include/exec/tb-lookup.h b/include/exec/tb-lookup.h
43
@@ -XXX,XX +XXX,XX @@ static bool fold_and(OptContext *ctx, TCGOp *op)
40
index XXXXXXX..XXXXXXX 100644
44
{
41
--- a/include/exec/tb-lookup.h
45
if (fold_const2(ctx, op) ||
42
+++ b/include/exec/tb-lookup.h
46
fold_xi_to_i(ctx, op, 0) ||
43
@@ -XXX,XX +XXX,XX @@ static inline TranslationBlock * tb_lookup(CPUState *cpu,
47
+ fold_xi_to_x(ctx, op, -1) ||
44
hash = tb_jmp_cache_hash_func(pc);
48
fold_xx_to_x(ctx, op)) {
45
tb = qatomic_rcu_read(&cpu->tb_jmp_cache[hash]);
46
47
- cf_mask &= ~CF_CLUSTER_MASK;
48
- cf_mask |= cpu->cluster_index << CF_CLUSTER_SHIFT;
49
-
50
if (likely(tb &&
51
tb->pc == pc &&
52
tb->cs_base == cs_base &&
53
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
54
index XXXXXXX..XXXXXXX 100644
55
--- a/accel/tcg/cpu-exec.c
56
+++ b/accel/tcg/cpu-exec.c
57
@@ -XXX,XX +XXX,XX @@ void cpu_exec_step_atomic(CPUState *cpu)
58
TranslationBlock *tb;
59
target_ulong cs_base, pc;
60
uint32_t flags;
61
- uint32_t cflags = 1;
62
- uint32_t cf_mask = cflags & CF_HASH_MASK;
63
+ uint32_t cflags = (curr_cflags(cpu) & ~CF_PARALLEL) | 1;
64
int tb_exit;
65
66
if (sigsetjmp(cpu->jmp_env, 0) == 0) {
67
@@ -XXX,XX +XXX,XX @@ void cpu_exec_step_atomic(CPUState *cpu)
68
cpu->running = true;
69
70
cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags);
71
- tb = tb_lookup(cpu, pc, cs_base, flags, cf_mask);
72
+ tb = tb_lookup(cpu, pc, cs_base, flags, cflags);
73
74
if (tb == NULL) {
75
mmap_lock();
76
@@ -XXX,XX +XXX,XX @@ static inline bool cpu_handle_exception(CPUState *cpu, int *ret)
77
if (replay_has_exception()
78
&& cpu_neg(cpu)->icount_decr.u16.low + cpu->icount_extra == 0) {
79
/* Execute just one insn to trigger exception pending in the log */
80
- cpu->cflags_next_tb = (curr_cflags() & ~CF_USE_ICOUNT) | 1;
81
+ cpu->cflags_next_tb = (curr_cflags(cpu) & ~CF_USE_ICOUNT) | 1;
82
}
83
#endif
84
return false;
85
@@ -XXX,XX +XXX,XX @@ int cpu_exec(CPUState *cpu)
86
have CF_INVALID set, -1 is a convenient invalid value that
87
does not require tcg headers for cpu_common_reset. */
88
if (cflags == -1) {
89
- cflags = curr_cflags();
90
+ cflags = curr_cflags(cpu);
91
} else {
92
cpu->cflags_next_tb = -1;
93
}
94
diff --git a/accel/tcg/tcg-runtime.c b/accel/tcg/tcg-runtime.c
95
index XXXXXXX..XXXXXXX 100644
96
--- a/accel/tcg/tcg-runtime.c
97
+++ b/accel/tcg/tcg-runtime.c
98
@@ -XXX,XX +XXX,XX @@ const void *HELPER(lookup_tb_ptr)(CPUArchState *env)
99
100
cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags);
101
102
- tb = tb_lookup(cpu, pc, cs_base, flags, curr_cflags());
103
+ tb = tb_lookup(cpu, pc, cs_base, flags, curr_cflags(cpu));
104
if (tb == NULL) {
105
return tcg_code_gen_epilogue;
106
}
107
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
108
index XXXXXXX..XXXXXXX 100644
109
--- a/accel/tcg/translate-all.c
110
+++ b/accel/tcg/translate-all.c
111
@@ -XXX,XX +XXX,XX @@ tb_invalidate_phys_page_range__locked(struct page_collection *pages,
112
if (current_tb_modified) {
113
page_collection_unlock(pages);
114
/* Force execution of one insn next time. */
115
- cpu->cflags_next_tb = 1 | curr_cflags();
116
+ cpu->cflags_next_tb = 1 | curr_cflags(cpu);
117
mmap_unlock();
118
cpu_loop_exit_noexc(cpu);
119
}
120
@@ -XXX,XX +XXX,XX @@ static bool tb_invalidate_phys_page(tb_page_addr_t addr, uintptr_t pc)
121
#ifdef TARGET_HAS_PRECISE_SMC
122
if (current_tb_modified) {
123
/* Force execution of one insn next time. */
124
- cpu->cflags_next_tb = 1 | curr_cflags();
125
+ cpu->cflags_next_tb = 1 | curr_cflags(cpu);
126
return true;
49
return true;
127
}
50
}
128
#endif
51
@@ -XXX,XX +XXX,XX @@ static bool fold_andc(OptContext *ctx, TCGOp *op)
129
@@ -XXX,XX +XXX,XX @@ void cpu_io_recompile(CPUState *cpu, uintptr_t retaddr)
52
{
130
* operations only (which execute after completion) so we don't
53
if (fold_const2(ctx, op) ||
131
* double instrument the instruction.
54
fold_xx_to_i(ctx, op, 0) ||
132
*/
55
+ fold_xi_to_x(ctx, op, 0) ||
133
- cpu->cflags_next_tb = curr_cflags() | CF_MEMI_ONLY | CF_LAST_IO | n;
56
fold_ix_to_not(ctx, op, -1)) {
134
+ cpu->cflags_next_tb = curr_cflags(cpu) | CF_MEMI_ONLY | CF_LAST_IO | n;
57
return true;
135
58
}
136
qemu_log_mask_and_addr(CPU_LOG_EXEC, tb->pc,
59
@@ -XXX,XX +XXX,XX @@ static bool fold_dup2(OptContext *ctx, TCGOp *op)
137
"cpu_io_recompile: rewound execution of TB to "
60
static bool fold_eqv(OptContext *ctx, TCGOp *op)
138
diff --git a/softmmu/physmem.c b/softmmu/physmem.c
61
{
139
index XXXXXXX..XXXXXXX 100644
62
if (fold_const2(ctx, op) ||
140
--- a/softmmu/physmem.c
63
+ fold_xi_to_x(ctx, op, -1) ||
141
+++ b/softmmu/physmem.c
64
fold_xi_to_not(ctx, op, 0)) {
142
@@ -XXX,XX +XXX,XX @@ void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr len,
65
return true;
143
cpu_loop_exit_restore(cpu, ra);
66
}
144
} else {
67
@@ -XXX,XX +XXX,XX @@ static bool fold_not(OptContext *ctx, TCGOp *op)
145
/* Force execution of one insn next time. */
68
static bool fold_or(OptContext *ctx, TCGOp *op)
146
- cpu->cflags_next_tb = 1 | curr_cflags();
69
{
147
+ cpu->cflags_next_tb = 1 | curr_cflags(cpu);
70
if (fold_const2(ctx, op) ||
148
mmap_unlock();
71
+ fold_xi_to_x(ctx, op, 0) ||
149
if (ra) {
72
fold_xx_to_x(ctx, op)) {
150
cpu_restore_state(cpu, ra, true);
73
return true;
74
}
75
@@ -XXX,XX +XXX,XX @@ static bool fold_or(OptContext *ctx, TCGOp *op)
76
static bool fold_orc(OptContext *ctx, TCGOp *op)
77
{
78
if (fold_const2(ctx, op) ||
79
+ fold_xi_to_x(ctx, op, -1) ||
80
fold_ix_to_not(ctx, op, 0)) {
81
return true;
82
}
83
@@ -XXX,XX +XXX,XX @@ static bool fold_sextract(OptContext *ctx, TCGOp *op)
84
85
static bool fold_shift(OptContext *ctx, TCGOp *op)
86
{
87
- return fold_const2(ctx, op);
88
+ if (fold_const2(ctx, op) ||
89
+ fold_xi_to_x(ctx, op, 0)) {
90
+ return true;
91
+ }
92
+ return false;
93
}
94
95
static bool fold_sub_to_neg(OptContext *ctx, TCGOp *op)
96
@@ -XXX,XX +XXX,XX @@ static bool fold_sub(OptContext *ctx, TCGOp *op)
97
{
98
if (fold_const2(ctx, op) ||
99
fold_xx_to_i(ctx, op, 0) ||
100
+ fold_xi_to_x(ctx, op, 0) ||
101
fold_sub_to_neg(ctx, op)) {
102
return true;
103
}
104
@@ -XXX,XX +XXX,XX @@ static bool fold_xor(OptContext *ctx, TCGOp *op)
105
{
106
if (fold_const2(ctx, op) ||
107
fold_xx_to_i(ctx, op, 0) ||
108
+ fold_xi_to_x(ctx, op, 0) ||
109
fold_xi_to_not(ctx, op, -1)) {
110
return true;
111
}
112
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
113
break;
114
}
115
116
- /* Simplify expression for "op r, a, const => mov r, a" cases */
117
- switch (opc) {
118
- CASE_OP_32_64_VEC(add):
119
- CASE_OP_32_64_VEC(sub):
120
- CASE_OP_32_64_VEC(or):
121
- CASE_OP_32_64_VEC(xor):
122
- CASE_OP_32_64_VEC(andc):
123
- CASE_OP_32_64(shl):
124
- CASE_OP_32_64(shr):
125
- CASE_OP_32_64(sar):
126
- CASE_OP_32_64(rotl):
127
- CASE_OP_32_64(rotr):
128
- if (!arg_is_const(op->args[1])
129
- && arg_is_const(op->args[2])
130
- && arg_info(op->args[2])->val == 0) {
131
- tcg_opt_gen_mov(&ctx, op, op->args[0], op->args[1]);
132
- continue;
133
- }
134
- break;
135
- CASE_OP_32_64_VEC(and):
136
- CASE_OP_32_64_VEC(orc):
137
- CASE_OP_32_64(eqv):
138
- if (!arg_is_const(op->args[1])
139
- && arg_is_const(op->args[2])
140
- && arg_info(op->args[2])->val == -1) {
141
- tcg_opt_gen_mov(&ctx, op, op->args[0], op->args[1]);
142
- continue;
143
- }
144
- break;
145
- default:
146
- break;
147
- }
148
-
149
/* Simplify using known-zero bits. Currently only ops with a single
150
output argument is supported. */
151
z_mask = -1;
151
--
152
--
152
2.25.1
153
2.25.1
153
154
154
155
diff view generated by jsdifflib
[PATCH 05/27] tcg: Split out tcg_raise_tb_overflow
[PULL 42/56] tcg/optimize: Split out fold_ix_to_i
1
Allow other places in tcg to restart with a smaller tb.
1
Pull the "op r, 0, b => movi r, 0" optimization into a function,
2
and use it in fold_shift.
2
3
4
Reviewed-by: Luis Pires <luis.pires@eldorado.org.br>
3
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
5
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
---
7
---
6
tcg/tcg.c | 9 +++++++--
8
tcg/optimize.c | 28 ++++++++++------------------
7
1 file changed, 7 insertions(+), 2 deletions(-)
9
1 file changed, 10 insertions(+), 18 deletions(-)
8
10
9
diff --git a/tcg/tcg.c b/tcg/tcg.c
11
diff --git a/tcg/optimize.c b/tcg/optimize.c
10
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
11
--- a/tcg/tcg.c
13
--- a/tcg/optimize.c
12
+++ b/tcg/tcg.c
14
+++ b/tcg/optimize.c
13
@@ -XXX,XX +XXX,XX @@ static void set_jmp_reset_offset(TCGContext *s, int which)
15
@@ -XXX,XX +XXX,XX @@ static bool fold_to_not(OptContext *ctx, TCGOp *op, int idx)
14
s->tb_jmp_reset_offset[which] = tcg_current_code_size(s);
16
return false;
15
}
17
}
16
18
17
+/* Signal overflow, starting over with fewer guest insns. */
19
+/* If the binary operation has first argument @i, fold to @i. */
18
+static void QEMU_NORETURN tcg_raise_tb_overflow(TCGContext *s)
20
+static bool fold_ix_to_i(OptContext *ctx, TCGOp *op, uint64_t i)
19
+{
21
+{
20
+ siglongjmp(s->jmp_trans, -2);
22
+ if (arg_is_const(op->args[1]) && arg_info(op->args[1])->val == i) {
23
+ return tcg_opt_gen_movi(ctx, op, op->args[0], i);
24
+ }
25
+ return false;
21
+}
26
+}
22
+
27
+
23
#define C_PFX1(P, A) P##A
28
/* If the binary operation has first argument @i, fold to NOT. */
24
#define C_PFX2(P, A, B) P##A##_##B
29
static bool fold_ix_to_not(OptContext *ctx, TCGOp *op, uint64_t i)
25
#define C_PFX3(P, A, B, C) P##A##_##B##_##C
30
{
26
@@ -XXX,XX +XXX,XX @@ static TCGTemp *tcg_temp_alloc(TCGContext *s)
31
@@ -XXX,XX +XXX,XX @@ static bool fold_sextract(OptContext *ctx, TCGOp *op)
27
int n = s->nb_temps++;
32
static bool fold_shift(OptContext *ctx, TCGOp *op)
28
33
{
29
if (n >= TCG_MAX_TEMPS) {
34
if (fold_const2(ctx, op) ||
30
- /* Signal overflow, starting over with fewer guest insns. */
35
+ fold_ix_to_i(ctx, op, 0) ||
31
- siglongjmp(s->jmp_trans, -2);
36
fold_xi_to_x(ctx, op, 0)) {
32
+ tcg_raise_tb_overflow(s);
37
return true;
33
}
38
}
34
return memset(&s->temps[n], 0, sizeof(TCGTemp));
39
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
35
}
40
break;
41
}
42
43
- /* Simplify expressions for "shift/rot r, 0, a => movi r, 0",
44
- and "sub r, 0, a => neg r, a" case. */
45
- switch (opc) {
46
- CASE_OP_32_64(shl):
47
- CASE_OP_32_64(shr):
48
- CASE_OP_32_64(sar):
49
- CASE_OP_32_64(rotl):
50
- CASE_OP_32_64(rotr):
51
- if (arg_is_const(op->args[1])
52
- && arg_info(op->args[1])->val == 0) {
53
- tcg_opt_gen_movi(&ctx, op, op->args[0], 0);
54
- continue;
55
- }
56
- break;
57
- default:
58
- break;
59
- }
60
-
61
/* Simplify using known-zero bits. Currently only ops with a single
62
output argument is supported. */
63
z_mask = -1;
36
--
64
--
37
2.25.1
65
2.25.1
38
66
39
67
diff view generated by jsdifflib
[PATCH 08/27] tcg/tci: Merge identical cases in generation (exchange opcodes)
[PULL 43/56] tcg/optimize: Split out fold_masks
1
Use CASE_32_64 and CASE_64 to reduce ifdefs and merge
1
Move all of the known-zero optimizations into the per-opcode
2
cases that are identical between 32-bit and 64-bit hosts.
2
functions. Use fold_masks when there is a possibility of the
3
result being determined, and simply set ctx->z_mask otherwise.
3
4
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
5
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
6
Reviewed-by: Luis Pires <luis.pires@eldorado.org.br>
6
Message-Id: <20210217202036.1724901-5-richard.henderson@linaro.org>
7
[PMD: Split patch as 2/5]
8
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
Message-Id: <20210218232840.1760806-3-f4bug@amsat.org>
10
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
11
---
8
---
12
tcg/tci/tcg-target.c.inc | 35 ++++++++++++++---------------------
9
tcg/optimize.c | 545 ++++++++++++++++++++++++++-----------------------
13
1 file changed, 14 insertions(+), 21 deletions(-)
10
1 file changed, 294 insertions(+), 251 deletions(-)
14
11
15
diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
12
diff --git a/tcg/optimize.c b/tcg/optimize.c
16
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
17
--- a/tcg/tci/tcg-target.c.inc
14
--- a/tcg/optimize.c
18
+++ b/tcg/tci/tcg-target.c.inc
15
+++ b/tcg/optimize.c
19
@@ -XXX,XX +XXX,XX @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
16
@@ -XXX,XX +XXX,XX @@ typedef struct OptContext {
20
tcg_out8(s, args[2]); /* condition */
17
TCGTempSet temps_used;
21
tci_out_label(s, arg_label(args[3]));
18
19
/* In flight values from optimization. */
20
- uint64_t z_mask;
21
+ uint64_t a_mask; /* mask bit is 0 iff value identical to first input */
22
+ uint64_t z_mask; /* mask bit is 0 iff value bit is 0 */
23
TCGType type;
24
} OptContext;
25
26
@@ -XXX,XX +XXX,XX @@ static bool fold_const2(OptContext *ctx, TCGOp *op)
27
return false;
28
}
29
30
+static bool fold_masks(OptContext *ctx, TCGOp *op)
31
+{
32
+ uint64_t a_mask = ctx->a_mask;
33
+ uint64_t z_mask = ctx->z_mask;
34
+
35
+ /*
36
+ * 32-bit ops generate 32-bit results. For the result is zero test
37
+ * below, we can ignore high bits, but for further optimizations we
38
+ * need to record that the high bits contain garbage.
39
+ */
40
+ if (ctx->type == TCG_TYPE_I32) {
41
+ ctx->z_mask |= MAKE_64BIT_MASK(32, 32);
42
+ a_mask &= MAKE_64BIT_MASK(0, 32);
43
+ z_mask &= MAKE_64BIT_MASK(0, 32);
44
+ }
45
+
46
+ if (z_mask == 0) {
47
+ return tcg_opt_gen_movi(ctx, op, op->args[0], 0);
48
+ }
49
+ if (a_mask == 0) {
50
+ return tcg_opt_gen_mov(ctx, op, op->args[0], op->args[1]);
51
+ }
52
+ return false;
53
+}
54
+
55
/*
56
* Convert @op to NOT, if NOT is supported by the host.
57
* Return true f the conversion is successful, which will still
58
@@ -XXX,XX +XXX,XX @@ static bool fold_add2_i32(OptContext *ctx, TCGOp *op)
59
60
static bool fold_and(OptContext *ctx, TCGOp *op)
61
{
62
+ uint64_t z1, z2;
63
+
64
if (fold_const2(ctx, op) ||
65
fold_xi_to_i(ctx, op, 0) ||
66
fold_xi_to_x(ctx, op, -1) ||
67
fold_xx_to_x(ctx, op)) {
68
return true;
69
}
70
- return false;
71
+
72
+ z1 = arg_info(op->args[1])->z_mask;
73
+ z2 = arg_info(op->args[2])->z_mask;
74
+ ctx->z_mask = z1 & z2;
75
+
76
+ /*
77
+ * Known-zeros does not imply known-ones. Therefore unless
78
+ * arg2 is constant, we can't infer affected bits from it.
79
+ */
80
+ if (arg_is_const(op->args[2])) {
81
+ ctx->a_mask = z1 & ~z2;
82
+ }
83
+
84
+ return fold_masks(ctx, op);
85
}
86
87
static bool fold_andc(OptContext *ctx, TCGOp *op)
88
{
89
+ uint64_t z1;
90
+
91
if (fold_const2(ctx, op) ||
92
fold_xx_to_i(ctx, op, 0) ||
93
fold_xi_to_x(ctx, op, 0) ||
94
fold_ix_to_not(ctx, op, -1)) {
95
return true;
96
}
97
- return false;
98
+
99
+ z1 = arg_info(op->args[1])->z_mask;
100
+
101
+ /*
102
+ * Known-zeros does not imply known-ones. Therefore unless
103
+ * arg2 is constant, we can't infer anything from it.
104
+ */
105
+ if (arg_is_const(op->args[2])) {
106
+ uint64_t z2 = ~arg_info(op->args[2])->z_mask;
107
+ ctx->a_mask = z1 & ~z2;
108
+ z1 &= z2;
109
+ }
110
+ ctx->z_mask = z1;
111
+
112
+ return fold_masks(ctx, op);
113
}
114
115
static bool fold_brcond(OptContext *ctx, TCGOp *op)
116
@@ -XXX,XX +XXX,XX @@ static bool fold_brcond2(OptContext *ctx, TCGOp *op)
117
118
static bool fold_bswap(OptContext *ctx, TCGOp *op)
119
{
120
+ uint64_t z_mask, sign;
121
+
122
if (arg_is_const(op->args[1])) {
123
uint64_t t = arg_info(op->args[1])->val;
124
125
t = do_constant_folding(op->opc, ctx->type, t, op->args[2]);
126
return tcg_opt_gen_movi(ctx, op, op->args[0], t);
127
}
128
- return false;
129
+
130
+ z_mask = arg_info(op->args[1])->z_mask;
131
+ switch (op->opc) {
132
+ case INDEX_op_bswap16_i32:
133
+ case INDEX_op_bswap16_i64:
134
+ z_mask = bswap16(z_mask);
135
+ sign = INT16_MIN;
136
+ break;
137
+ case INDEX_op_bswap32_i32:
138
+ case INDEX_op_bswap32_i64:
139
+ z_mask = bswap32(z_mask);
140
+ sign = INT32_MIN;
141
+ break;
142
+ case INDEX_op_bswap64_i64:
143
+ z_mask = bswap64(z_mask);
144
+ sign = INT64_MIN;
145
+ break;
146
+ default:
147
+ g_assert_not_reached();
148
+ }
149
+
150
+ switch (op->args[2] & (TCG_BSWAP_OZ | TCG_BSWAP_OS)) {
151
+ case TCG_BSWAP_OZ:
152
+ break;
153
+ case TCG_BSWAP_OS:
154
+ /* If the sign bit may be 1, force all the bits above to 1. */
155
+ if (z_mask & sign) {
156
+ z_mask |= sign;
157
+ }
158
+ break;
159
+ default:
160
+ /* The high bits are undefined: force all bits above the sign to 1. */
161
+ z_mask |= sign << 1;
162
+ break;
163
+ }
164
+ ctx->z_mask = z_mask;
165
+
166
+ return fold_masks(ctx, op);
167
}
168
169
static bool fold_call(OptContext *ctx, TCGOp *op)
170
@@ -XXX,XX +XXX,XX @@ static bool fold_call(OptContext *ctx, TCGOp *op)
171
172
static bool fold_count_zeros(OptContext *ctx, TCGOp *op)
173
{
174
+ uint64_t z_mask;
175
+
176
if (arg_is_const(op->args[1])) {
177
uint64_t t = arg_info(op->args[1])->val;
178
179
@@ -XXX,XX +XXX,XX @@ static bool fold_count_zeros(OptContext *ctx, TCGOp *op)
180
}
181
return tcg_opt_gen_mov(ctx, op, op->args[0], op->args[2]);
182
}
183
+
184
+ switch (ctx->type) {
185
+ case TCG_TYPE_I32:
186
+ z_mask = 31;
187
+ break;
188
+ case TCG_TYPE_I64:
189
+ z_mask = 63;
190
+ break;
191
+ default:
192
+ g_assert_not_reached();
193
+ }
194
+ ctx->z_mask = arg_info(op->args[2])->z_mask | z_mask;
195
+
196
return false;
197
}
198
199
static bool fold_ctpop(OptContext *ctx, TCGOp *op)
200
{
201
- return fold_const1(ctx, op);
202
+ if (fold_const1(ctx, op)) {
203
+ return true;
204
+ }
205
+
206
+ switch (ctx->type) {
207
+ case TCG_TYPE_I32:
208
+ ctx->z_mask = 32 | 31;
209
+ break;
210
+ case TCG_TYPE_I64:
211
+ ctx->z_mask = 64 | 63;
212
+ break;
213
+ default:
214
+ g_assert_not_reached();
215
+ }
216
+ return false;
217
}
218
219
static bool fold_deposit(OptContext *ctx, TCGOp *op)
220
@@ -XXX,XX +XXX,XX @@ static bool fold_deposit(OptContext *ctx, TCGOp *op)
221
t1 = deposit64(t1, op->args[3], op->args[4], t2);
222
return tcg_opt_gen_movi(ctx, op, op->args[0], t1);
223
}
224
+
225
+ ctx->z_mask = deposit64(arg_info(op->args[1])->z_mask,
226
+ op->args[3], op->args[4],
227
+ arg_info(op->args[2])->z_mask);
228
return false;
229
}
230
231
@@ -XXX,XX +XXX,XX @@ static bool fold_eqv(OptContext *ctx, TCGOp *op)
232
233
static bool fold_extract(OptContext *ctx, TCGOp *op)
234
{
235
+ uint64_t z_mask_old, z_mask;
236
+
237
if (arg_is_const(op->args[1])) {
238
uint64_t t;
239
240
@@ -XXX,XX +XXX,XX @@ static bool fold_extract(OptContext *ctx, TCGOp *op)
241
t = extract64(t, op->args[2], op->args[3]);
242
return tcg_opt_gen_movi(ctx, op, op->args[0], t);
243
}
244
- return false;
245
+
246
+ z_mask_old = arg_info(op->args[1])->z_mask;
247
+ z_mask = extract64(z_mask_old, op->args[2], op->args[3]);
248
+ if (op->args[2] == 0) {
249
+ ctx->a_mask = z_mask_old ^ z_mask;
250
+ }
251
+ ctx->z_mask = z_mask;
252
+
253
+ return fold_masks(ctx, op);
254
}
255
256
static bool fold_extract2(OptContext *ctx, TCGOp *op)
257
@@ -XXX,XX +XXX,XX @@ static bool fold_extract2(OptContext *ctx, TCGOp *op)
258
259
static bool fold_exts(OptContext *ctx, TCGOp *op)
260
{
261
- return fold_const1(ctx, op);
262
+ uint64_t z_mask_old, z_mask, sign;
263
+ bool type_change = false;
264
+
265
+ if (fold_const1(ctx, op)) {
266
+ return true;
267
+ }
268
+
269
+ z_mask_old = z_mask = arg_info(op->args[1])->z_mask;
270
+
271
+ switch (op->opc) {
272
+ CASE_OP_32_64(ext8s):
273
+ sign = INT8_MIN;
274
+ z_mask = (uint8_t)z_mask;
275
+ break;
276
+ CASE_OP_32_64(ext16s):
277
+ sign = INT16_MIN;
278
+ z_mask = (uint16_t)z_mask;
279
+ break;
280
+ case INDEX_op_ext_i32_i64:
281
+ type_change = true;
282
+ QEMU_FALLTHROUGH;
283
+ case INDEX_op_ext32s_i64:
284
+ sign = INT32_MIN;
285
+ z_mask = (uint32_t)z_mask;
286
+ break;
287
+ default:
288
+ g_assert_not_reached();
289
+ }
290
+
291
+ if (z_mask & sign) {
292
+ z_mask |= sign;
293
+ } else if (!type_change) {
294
+ ctx->a_mask = z_mask_old ^ z_mask;
295
+ }
296
+ ctx->z_mask = z_mask;
297
+
298
+ return fold_masks(ctx, op);
299
}
300
301
static bool fold_extu(OptContext *ctx, TCGOp *op)
302
{
303
- return fold_const1(ctx, op);
304
+ uint64_t z_mask_old, z_mask;
305
+ bool type_change = false;
306
+
307
+ if (fold_const1(ctx, op)) {
308
+ return true;
309
+ }
310
+
311
+ z_mask_old = z_mask = arg_info(op->args[1])->z_mask;
312
+
313
+ switch (op->opc) {
314
+ CASE_OP_32_64(ext8u):
315
+ z_mask = (uint8_t)z_mask;
316
+ break;
317
+ CASE_OP_32_64(ext16u):
318
+ z_mask = (uint16_t)z_mask;
319
+ break;
320
+ case INDEX_op_extrl_i64_i32:
321
+ case INDEX_op_extu_i32_i64:
322
+ type_change = true;
323
+ QEMU_FALLTHROUGH;
324
+ case INDEX_op_ext32u_i64:
325
+ z_mask = (uint32_t)z_mask;
326
+ break;
327
+ case INDEX_op_extrh_i64_i32:
328
+ type_change = true;
329
+ z_mask >>= 32;
330
+ break;
331
+ default:
332
+ g_assert_not_reached();
333
+ }
334
+
335
+ ctx->z_mask = z_mask;
336
+ if (!type_change) {
337
+ ctx->a_mask = z_mask_old ^ z_mask;
338
+ }
339
+ return fold_masks(ctx, op);
340
}
341
342
static bool fold_mb(OptContext *ctx, TCGOp *op)
343
@@ -XXX,XX +XXX,XX @@ static bool fold_movcond(OptContext *ctx, TCGOp *op)
344
return tcg_opt_gen_mov(ctx, op, op->args[0], op->args[4 - i]);
345
}
346
347
+ ctx->z_mask = arg_info(op->args[3])->z_mask
348
+ | arg_info(op->args[4])->z_mask;
349
+
350
if (arg_is_const(op->args[3]) && arg_is_const(op->args[4])) {
351
uint64_t tv = arg_info(op->args[3])->val;
352
uint64_t fv = arg_info(op->args[4])->val;
353
@@ -XXX,XX +XXX,XX @@ static bool fold_nand(OptContext *ctx, TCGOp *op)
354
355
static bool fold_neg(OptContext *ctx, TCGOp *op)
356
{
357
+ uint64_t z_mask;
358
+
359
if (fold_const1(ctx, op)) {
360
return true;
361
}
362
+
363
+ /* Set to 1 all bits to the left of the rightmost. */
364
+ z_mask = arg_info(op->args[1])->z_mask;
365
+ ctx->z_mask = -(z_mask & -z_mask);
366
+
367
/*
368
* Because of fold_sub_to_neg, we want to always return true,
369
* via finish_folding.
370
@@ -XXX,XX +XXX,XX @@ static bool fold_or(OptContext *ctx, TCGOp *op)
371
fold_xx_to_x(ctx, op)) {
372
return true;
373
}
374
- return false;
375
+
376
+ ctx->z_mask = arg_info(op->args[1])->z_mask
377
+ | arg_info(op->args[2])->z_mask;
378
+ return fold_masks(ctx, op);
379
}
380
381
static bool fold_orc(OptContext *ctx, TCGOp *op)
382
@@ -XXX,XX +XXX,XX @@ static bool fold_orc(OptContext *ctx, TCGOp *op)
383
384
static bool fold_qemu_ld(OptContext *ctx, TCGOp *op)
385
{
386
+ const TCGOpDef *def = &tcg_op_defs[op->opc];
387
+ MemOpIdx oi = op->args[def->nb_oargs + def->nb_iargs];
388
+ MemOp mop = get_memop(oi);
389
+ int width = 8 * memop_size(mop);
390
+
391
+ if (!(mop & MO_SIGN) && width < 64) {
392
+ ctx->z_mask = MAKE_64BIT_MASK(0, width);
393
+ }
394
+
395
/* Opcodes that touch guest memory stop the mb optimization. */
396
ctx->prev_mb = NULL;
397
return false;
398
@@ -XXX,XX +XXX,XX @@ static bool fold_setcond(OptContext *ctx, TCGOp *op)
399
if (i >= 0) {
400
return tcg_opt_gen_movi(ctx, op, op->args[0], i);
401
}
402
+
403
+ ctx->z_mask = 1;
404
return false;
405
}
406
407
@@ -XXX,XX +XXX,XX @@ static bool fold_setcond2(OptContext *ctx, TCGOp *op)
408
op->opc = INDEX_op_setcond_i32;
22
break;
409
break;
23
- case INDEX_op_bswap16_i64: /* Optional (TCG_TARGET_HAS_bswap16_i64). */
410
}
24
- case INDEX_op_bswap32_i64: /* Optional (TCG_TARGET_HAS_bswap32_i64). */
411
+
25
- case INDEX_op_bswap64_i64: /* Optional (TCG_TARGET_HAS_bswap64_i64). */
412
+ ctx->z_mask = 1;
26
- case INDEX_op_not_i64: /* Optional (TCG_TARGET_HAS_not_i64). */
413
return false;
27
- case INDEX_op_neg_i64: /* Optional (TCG_TARGET_HAS_neg_i64). */
414
28
- case INDEX_op_ext8s_i64: /* Optional (TCG_TARGET_HAS_ext8s_i64). */
415
do_setcond_const:
29
- case INDEX_op_ext8u_i64: /* Optional (TCG_TARGET_HAS_ext8u_i64). */
416
@@ -XXX,XX +XXX,XX @@ static bool fold_setcond2(OptContext *ctx, TCGOp *op)
30
- case INDEX_op_ext16s_i64: /* Optional (TCG_TARGET_HAS_ext16s_i64). */
417
31
- case INDEX_op_ext16u_i64: /* Optional (TCG_TARGET_HAS_ext16u_i64). */
418
static bool fold_sextract(OptContext *ctx, TCGOp *op)
32
- case INDEX_op_ext32s_i64: /* Optional (TCG_TARGET_HAS_ext32s_i64). */
419
{
33
- case INDEX_op_ext32u_i64: /* Optional (TCG_TARGET_HAS_ext32u_i64). */
420
+ int64_t z_mask_old, z_mask;
34
- case INDEX_op_ext_i32_i64:
421
+
35
- case INDEX_op_extu_i32_i64:
422
if (arg_is_const(op->args[1])) {
36
#endif /* TCG_TARGET_REG_BITS == 64 */
423
uint64_t t;
37
- case INDEX_op_neg_i32: /* Optional (TCG_TARGET_HAS_neg_i32). */
424
38
- case INDEX_op_not_i32: /* Optional (TCG_TARGET_HAS_not_i32). */
425
@@ -XXX,XX +XXX,XX @@ static bool fold_sextract(OptContext *ctx, TCGOp *op)
39
- case INDEX_op_ext8s_i32: /* Optional (TCG_TARGET_HAS_ext8s_i32). */
426
t = sextract64(t, op->args[2], op->args[3]);
40
- case INDEX_op_ext16s_i32: /* Optional (TCG_TARGET_HAS_ext16s_i32). */
427
return tcg_opt_gen_movi(ctx, op, op->args[0], t);
41
- case INDEX_op_ext8u_i32: /* Optional (TCG_TARGET_HAS_ext8u_i32). */
428
}
42
- case INDEX_op_ext16u_i32: /* Optional (TCG_TARGET_HAS_ext16u_i32). */
429
- return false;
43
- case INDEX_op_bswap16_i32: /* Optional (TCG_TARGET_HAS_bswap16_i32). */
430
+
44
- case INDEX_op_bswap32_i32: /* Optional (TCG_TARGET_HAS_bswap32_i32). */
431
+ z_mask_old = arg_info(op->args[1])->z_mask;
45
+
432
+ z_mask = sextract64(z_mask_old, op->args[2], op->args[3]);
46
+ CASE_32_64(neg) /* Optional (TCG_TARGET_HAS_neg_*). */
433
+ if (op->args[2] == 0 && z_mask >= 0) {
47
+ CASE_32_64(not) /* Optional (TCG_TARGET_HAS_not_*). */
434
+ ctx->a_mask = z_mask_old ^ z_mask;
48
+ CASE_32_64(ext8s) /* Optional (TCG_TARGET_HAS_ext8s_*). */
435
+ }
49
+ CASE_32_64(ext8u) /* Optional (TCG_TARGET_HAS_ext8u_*). */
436
+ ctx->z_mask = z_mask;
50
+ CASE_32_64(ext16s) /* Optional (TCG_TARGET_HAS_ext16s_*). */
437
+
51
+ CASE_32_64(ext16u) /* Optional (TCG_TARGET_HAS_ext16u_*). */
438
+ return fold_masks(ctx, op);
52
+ CASE_64(ext32s) /* Optional (TCG_TARGET_HAS_ext32s_i64). */
439
}
53
+ CASE_64(ext32u) /* Optional (TCG_TARGET_HAS_ext32u_i64). */
440
54
+ CASE_64(ext_i32)
441
static bool fold_shift(OptContext *ctx, TCGOp *op)
55
+ CASE_64(extu_i32)
442
@@ -XXX,XX +XXX,XX @@ static bool fold_shift(OptContext *ctx, TCGOp *op)
56
+ CASE_32_64(bswap16) /* Optional (TCG_TARGET_HAS_bswap16_*). */
443
fold_xi_to_x(ctx, op, 0)) {
57
+ CASE_32_64(bswap32) /* Optional (TCG_TARGET_HAS_bswap32_*). */
444
return true;
58
+ CASE_64(bswap64) /* Optional (TCG_TARGET_HAS_bswap64_i64). */
445
}
59
tcg_out_r(s, args[0]);
446
+
60
tcg_out_r(s, args[1]);
447
+ if (arg_is_const(op->args[2])) {
61
break;
448
+ ctx->z_mask = do_constant_folding(op->opc, ctx->type,
449
+ arg_info(op->args[1])->z_mask,
450
+ arg_info(op->args[2])->val);
451
+ return fold_masks(ctx, op);
452
+ }
453
return false;
454
}
455
456
@@ -XXX,XX +XXX,XX @@ static bool fold_sub2_i32(OptContext *ctx, TCGOp *op)
457
return fold_addsub2_i32(ctx, op, false);
458
}
459
460
+static bool fold_tcg_ld(OptContext *ctx, TCGOp *op)
461
+{
462
+ /* We can't do any folding with a load, but we can record bits. */
463
+ switch (op->opc) {
464
+ CASE_OP_32_64(ld8u):
465
+ ctx->z_mask = MAKE_64BIT_MASK(0, 8);
466
+ break;
467
+ CASE_OP_32_64(ld16u):
468
+ ctx->z_mask = MAKE_64BIT_MASK(0, 16);
469
+ break;
470
+ case INDEX_op_ld32u_i64:
471
+ ctx->z_mask = MAKE_64BIT_MASK(0, 32);
472
+ break;
473
+ default:
474
+ g_assert_not_reached();
475
+ }
476
+ return false;
477
+}
478
+
479
static bool fold_xor(OptContext *ctx, TCGOp *op)
480
{
481
if (fold_const2(ctx, op) ||
482
@@ -XXX,XX +XXX,XX @@ static bool fold_xor(OptContext *ctx, TCGOp *op)
483
fold_xi_to_not(ctx, op, -1)) {
484
return true;
485
}
486
- return false;
487
+
488
+ ctx->z_mask = arg_info(op->args[1])->z_mask
489
+ | arg_info(op->args[2])->z_mask;
490
+ return fold_masks(ctx, op);
491
}
492
493
/* Propagate constants and copies, fold constant expressions. */
494
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
495
}
496
497
QTAILQ_FOREACH_SAFE(op, &s->ops, link, op_next) {
498
- uint64_t z_mask, partmask, affected, tmp;
499
TCGOpcode opc = op->opc;
500
const TCGOpDef *def;
501
bool done = false;
502
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
503
break;
504
}
505
506
- /* Simplify using known-zero bits. Currently only ops with a single
507
- output argument is supported. */
508
- z_mask = -1;
509
- affected = -1;
510
- switch (opc) {
511
- CASE_OP_32_64(ext8s):
512
- if ((arg_info(op->args[1])->z_mask & 0x80) != 0) {
513
- break;
514
- }
515
- QEMU_FALLTHROUGH;
516
- CASE_OP_32_64(ext8u):
517
- z_mask = 0xff;
518
- goto and_const;
519
- CASE_OP_32_64(ext16s):
520
- if ((arg_info(op->args[1])->z_mask & 0x8000) != 0) {
521
- break;
522
- }
523
- QEMU_FALLTHROUGH;
524
- CASE_OP_32_64(ext16u):
525
- z_mask = 0xffff;
526
- goto and_const;
527
- case INDEX_op_ext32s_i64:
528
- if ((arg_info(op->args[1])->z_mask & 0x80000000) != 0) {
529
- break;
530
- }
531
- QEMU_FALLTHROUGH;
532
- case INDEX_op_ext32u_i64:
533
- z_mask = 0xffffffffU;
534
- goto and_const;
535
-
536
- CASE_OP_32_64(and):
537
- z_mask = arg_info(op->args[2])->z_mask;
538
- if (arg_is_const(op->args[2])) {
539
- and_const:
540
- affected = arg_info(op->args[1])->z_mask & ~z_mask;
541
- }
542
- z_mask = arg_info(op->args[1])->z_mask & z_mask;
543
- break;
544
-
545
- case INDEX_op_ext_i32_i64:
546
- if ((arg_info(op->args[1])->z_mask & 0x80000000) != 0) {
547
- break;
548
- }
549
- QEMU_FALLTHROUGH;
550
- case INDEX_op_extu_i32_i64:
551
- /* We do not compute affected as it is a size changing op. */
552
- z_mask = (uint32_t)arg_info(op->args[1])->z_mask;
553
- break;
554
-
555
- CASE_OP_32_64(andc):
556
- /* Known-zeros does not imply known-ones. Therefore unless
557
- op->args[2] is constant, we can't infer anything from it. */
558
- if (arg_is_const(op->args[2])) {
559
- z_mask = ~arg_info(op->args[2])->z_mask;
560
- goto and_const;
561
- }
562
- /* But we certainly know nothing outside args[1] may be set. */
563
- z_mask = arg_info(op->args[1])->z_mask;
564
- break;
565
-
566
- case INDEX_op_sar_i32:
567
- if (arg_is_const(op->args[2])) {
568
- tmp = arg_info(op->args[2])->val & 31;
569
- z_mask = (int32_t)arg_info(op->args[1])->z_mask >> tmp;
570
- }
571
- break;
572
- case INDEX_op_sar_i64:
573
- if (arg_is_const(op->args[2])) {
574
- tmp = arg_info(op->args[2])->val & 63;
575
- z_mask = (int64_t)arg_info(op->args[1])->z_mask >> tmp;
576
- }
577
- break;
578
-
579
- case INDEX_op_shr_i32:
580
- if (arg_is_const(op->args[2])) {
581
- tmp = arg_info(op->args[2])->val & 31;
582
- z_mask = (uint32_t)arg_info(op->args[1])->z_mask >> tmp;
583
- }
584
- break;
585
- case INDEX_op_shr_i64:
586
- if (arg_is_const(op->args[2])) {
587
- tmp = arg_info(op->args[2])->val & 63;
588
- z_mask = (uint64_t)arg_info(op->args[1])->z_mask >> tmp;
589
- }
590
- break;
591
-
592
- case INDEX_op_extrl_i64_i32:
593
- z_mask = (uint32_t)arg_info(op->args[1])->z_mask;
594
- break;
595
- case INDEX_op_extrh_i64_i32:
596
- z_mask = (uint64_t)arg_info(op->args[1])->z_mask >> 32;
597
- break;
598
-
599
- CASE_OP_32_64(shl):
600
- if (arg_is_const(op->args[2])) {
601
- tmp = arg_info(op->args[2])->val & (TCG_TARGET_REG_BITS - 1);
602
- z_mask = arg_info(op->args[1])->z_mask << tmp;
603
- }
604
- break;
605
-
606
- CASE_OP_32_64(neg):
607
- /* Set to 1 all bits to the left of the rightmost. */
608
- z_mask = -(arg_info(op->args[1])->z_mask
609
- & -arg_info(op->args[1])->z_mask);
610
- break;
611
-
612
- CASE_OP_32_64(deposit):
613
- z_mask = deposit64(arg_info(op->args[1])->z_mask,
614
- op->args[3], op->args[4],
615
- arg_info(op->args[2])->z_mask);
616
- break;
617
-
618
- CASE_OP_32_64(extract):
619
- z_mask = extract64(arg_info(op->args[1])->z_mask,
620
- op->args[2], op->args[3]);
621
- if (op->args[2] == 0) {
622
- affected = arg_info(op->args[1])->z_mask & ~z_mask;
623
- }
624
- break;
625
- CASE_OP_32_64(sextract):
626
- z_mask = sextract64(arg_info(op->args[1])->z_mask,
627
- op->args[2], op->args[3]);
628
- if (op->args[2] == 0 && (tcg_target_long)z_mask >= 0) {
629
- affected = arg_info(op->args[1])->z_mask & ~z_mask;
630
- }
631
- break;
632
-
633
- CASE_OP_32_64(or):
634
- CASE_OP_32_64(xor):
635
- z_mask = arg_info(op->args[1])->z_mask
636
- | arg_info(op->args[2])->z_mask;
637
- break;
638
-
639
- case INDEX_op_clz_i32:
640
- case INDEX_op_ctz_i32:
641
- z_mask = arg_info(op->args[2])->z_mask | 31;
642
- break;
643
-
644
- case INDEX_op_clz_i64:
645
- case INDEX_op_ctz_i64:
646
- z_mask = arg_info(op->args[2])->z_mask | 63;
647
- break;
648
-
649
- case INDEX_op_ctpop_i32:
650
- z_mask = 32 | 31;
651
- break;
652
- case INDEX_op_ctpop_i64:
653
- z_mask = 64 | 63;
654
- break;
655
-
656
- CASE_OP_32_64(setcond):
657
- case INDEX_op_setcond2_i32:
658
- z_mask = 1;
659
- break;
660
-
661
- CASE_OP_32_64(movcond):
662
- z_mask = arg_info(op->args[3])->z_mask
663
- | arg_info(op->args[4])->z_mask;
664
- break;
665
-
666
- CASE_OP_32_64(ld8u):
667
- z_mask = 0xff;
668
- break;
669
- CASE_OP_32_64(ld16u):
670
- z_mask = 0xffff;
671
- break;
672
- case INDEX_op_ld32u_i64:
673
- z_mask = 0xffffffffu;
674
- break;
675
-
676
- CASE_OP_32_64(qemu_ld):
677
- {
678
- MemOpIdx oi = op->args[def->nb_oargs + def->nb_iargs];
679
- MemOp mop = get_memop(oi);
680
- if (!(mop & MO_SIGN)) {
681
- z_mask = (2ULL << ((8 << (mop & MO_SIZE)) - 1)) - 1;
682
- }
683
- }
684
- break;
685
-
686
- CASE_OP_32_64(bswap16):
687
- z_mask = arg_info(op->args[1])->z_mask;
688
- if (z_mask <= 0xffff) {
689
- op->args[2] |= TCG_BSWAP_IZ;
690
- }
691
- z_mask = bswap16(z_mask);
692
- switch (op->args[2] & (TCG_BSWAP_OZ | TCG_BSWAP_OS)) {
693
- case TCG_BSWAP_OZ:
694
- break;
695
- case TCG_BSWAP_OS:
696
- z_mask = (int16_t)z_mask;
697
- break;
698
- default: /* undefined high bits */
699
- z_mask |= MAKE_64BIT_MASK(16, 48);
700
- break;
701
- }
702
- break;
703
-
704
- case INDEX_op_bswap32_i64:
705
- z_mask = arg_info(op->args[1])->z_mask;
706
- if (z_mask <= 0xffffffffu) {
707
- op->args[2] |= TCG_BSWAP_IZ;
708
- }
709
- z_mask = bswap32(z_mask);
710
- switch (op->args[2] & (TCG_BSWAP_OZ | TCG_BSWAP_OS)) {
711
- case TCG_BSWAP_OZ:
712
- break;
713
- case TCG_BSWAP_OS:
714
- z_mask = (int32_t)z_mask;
715
- break;
716
- default: /* undefined high bits */
717
- z_mask |= MAKE_64BIT_MASK(32, 32);
718
- break;
719
- }
720
- break;
721
-
722
- default:
723
- break;
724
- }
725
-
726
- /* 32-bit ops generate 32-bit results. For the result is zero test
727
- below, we can ignore high bits, but for further optimizations we
728
- need to record that the high bits contain garbage. */
729
- partmask = z_mask;
730
- if (ctx.type == TCG_TYPE_I32) {
731
- z_mask |= ~(tcg_target_ulong)0xffffffffu;
732
- partmask &= 0xffffffffu;
733
- affected &= 0xffffffffu;
734
- }
735
- ctx.z_mask = z_mask;
736
-
737
- if (partmask == 0) {
738
- tcg_opt_gen_movi(&ctx, op, op->args[0], 0);
739
- continue;
740
- }
741
- if (affected == 0) {
742
- tcg_opt_gen_mov(&ctx, op, op->args[0], op->args[1]);
743
- continue;
744
- }
745
+ /* Assume all bits affected, and no bits known zero. */
746
+ ctx.a_mask = -1;
747
+ ctx.z_mask = -1;
748
749
/*
750
* Process each opcode.
751
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
752
case INDEX_op_extrh_i64_i32:
753
done = fold_extu(&ctx, op);
754
break;
755
+ CASE_OP_32_64(ld8u):
756
+ CASE_OP_32_64(ld16u):
757
+ case INDEX_op_ld32u_i64:
758
+ done = fold_tcg_ld(&ctx, op);
759
+ break;
760
case INDEX_op_mb:
761
done = fold_mb(&ctx, op);
762
break;
62
--
763
--
63
2.25.1
764
2.25.1
64
765
65
766
diff view generated by jsdifflib
[PATCH 22/27] tcg/tci: Merge mov, not and neg operations
[PULL 44/56] tcg/optimize: Expand fold_mulu2_i32 to all 4-arg multiplies
1
Rename to fold_multiply2, and handle muls2_i32, mulu2_i64,
2
and muls2_i64.
3
4
Reviewed-by: Luis Pires <luis.pires@eldorado.org.br>
1
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
5
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
3
---
7
---
4
tcg/tci.c | 29 +++++------------------------
8
tcg/optimize.c | 44 +++++++++++++++++++++++++++++++++++---------
5
1 file changed, 5 insertions(+), 24 deletions(-)
9
1 file changed, 35 insertions(+), 9 deletions(-)
6
10
7
diff --git a/tcg/tci.c b/tcg/tci.c
11
diff --git a/tcg/optimize.c b/tcg/optimize.c
8
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
9
--- a/tcg/tci.c
13
--- a/tcg/optimize.c
10
+++ b/tcg/tci.c
14
+++ b/tcg/optimize.c
11
@@ -XXX,XX +XXX,XX @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
15
@@ -XXX,XX +XXX,XX @@ static bool fold_mul_highpart(OptContext *ctx, TCGOp *op)
12
tci_write_reg(regs, t0, tci_compare64(t1, t2, condition));
16
return false;
17
}
18
19
-static bool fold_mulu2_i32(OptContext *ctx, TCGOp *op)
20
+static bool fold_multiply2(OptContext *ctx, TCGOp *op)
21
{
22
if (arg_is_const(op->args[2]) && arg_is_const(op->args[3])) {
23
- uint32_t a = arg_info(op->args[2])->val;
24
- uint32_t b = arg_info(op->args[3])->val;
25
- uint64_t r = (uint64_t)a * b;
26
+ uint64_t a = arg_info(op->args[2])->val;
27
+ uint64_t b = arg_info(op->args[3])->val;
28
+ uint64_t h, l;
29
TCGArg rl, rh;
30
- TCGOp *op2 = tcg_op_insert_before(ctx->tcg, op, INDEX_op_mov_i32);
31
+ TCGOp *op2;
32
+
33
+ switch (op->opc) {
34
+ case INDEX_op_mulu2_i32:
35
+ l = (uint64_t)(uint32_t)a * (uint32_t)b;
36
+ h = (int32_t)(l >> 32);
37
+ l = (int32_t)l;
38
+ break;
39
+ case INDEX_op_muls2_i32:
40
+ l = (int64_t)(int32_t)a * (int32_t)b;
41
+ h = l >> 32;
42
+ l = (int32_t)l;
43
+ break;
44
+ case INDEX_op_mulu2_i64:
45
+ mulu64(&l, &h, a, b);
46
+ break;
47
+ case INDEX_op_muls2_i64:
48
+ muls64(&l, &h, a, b);
49
+ break;
50
+ default:
51
+ g_assert_not_reached();
52
+ }
53
54
rl = op->args[0];
55
rh = op->args[1];
56
- tcg_opt_gen_movi(ctx, op, rl, (int32_t)r);
57
- tcg_opt_gen_movi(ctx, op2, rh, (int32_t)(r >> 32));
58
+
59
+ /* The proper opcode is supplied by tcg_opt_gen_mov. */
60
+ op2 = tcg_op_insert_before(ctx->tcg, op, 0);
61
+
62
+ tcg_opt_gen_movi(ctx, op, rl, l);
63
+ tcg_opt_gen_movi(ctx, op2, rh, h);
64
return true;
65
}
66
return false;
67
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
68
CASE_OP_32_64(muluh):
69
done = fold_mul_highpart(&ctx, op);
13
break;
70
break;
14
#endif
71
- case INDEX_op_mulu2_i32:
15
- case INDEX_op_mov_i32:
72
- done = fold_mulu2_i32(&ctx, op);
16
+ CASE_32_64(mov)
73
+ CASE_OP_32_64(muls2):
17
t0 = *tb_ptr++;
74
+ CASE_OP_32_64(mulu2):
18
t1 = tci_read_r(regs, &tb_ptr);
75
+ done = fold_multiply2(&ctx, op);
19
tci_write_reg(regs, t0, t1);
20
@@ -XXX,XX +XXX,XX @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
21
tci_write_reg(regs, t0, bswap32(t1));
22
break;
76
break;
23
#endif
77
CASE_OP_32_64(nand):
24
-#if TCG_TARGET_HAS_not_i32
78
done = fold_nand(&ctx, op);
25
- case INDEX_op_not_i32:
26
+#if TCG_TARGET_HAS_not_i32 || TCG_TARGET_HAS_not_i64
27
+ CASE_32_64(not)
28
t0 = *tb_ptr++;
29
t1 = tci_read_r(regs, &tb_ptr);
30
tci_write_reg(regs, t0, ~t1);
31
break;
32
#endif
33
-#if TCG_TARGET_HAS_neg_i32
34
- case INDEX_op_neg_i32:
35
+#if TCG_TARGET_HAS_neg_i32 || TCG_TARGET_HAS_neg_i64
36
+ CASE_32_64(neg)
37
t0 = *tb_ptr++;
38
t1 = tci_read_r(regs, &tb_ptr);
39
tci_write_reg(regs, t0, -t1);
40
break;
41
#endif
42
#if TCG_TARGET_REG_BITS == 64
43
- case INDEX_op_mov_i64:
44
- t0 = *tb_ptr++;
45
- t1 = tci_read_r(regs, &tb_ptr);
46
- tci_write_reg(regs, t0, t1);
47
- break;
48
case INDEX_op_tci_movi_i64:
49
t0 = *tb_ptr++;
50
t1 = tci_read_i64(&tb_ptr);
51
@@ -XXX,XX +XXX,XX @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
52
tci_write_reg(regs, t0, bswap64(t1));
53
break;
54
#endif
55
-#if TCG_TARGET_HAS_not_i64
56
- case INDEX_op_not_i64:
57
- t0 = *tb_ptr++;
58
- t1 = tci_read_r(regs, &tb_ptr);
59
- tci_write_reg(regs, t0, ~t1);
60
- break;
61
-#endif
62
-#if TCG_TARGET_HAS_neg_i64
63
- case INDEX_op_neg_i64:
64
- t0 = *tb_ptr++;
65
- t1 = tci_read_r(regs, &tb_ptr);
66
- tci_write_reg(regs, t0, -t1);
67
- break;
68
-#endif
69
#endif /* TCG_TARGET_REG_BITS == 64 */
70
71
/* QEMU specific operations. */
72
--
79
--
73
2.25.1
80
2.25.1
74
81
75
82
diff view generated by jsdifflib
[PATCH 13/27] tcg/tci: Remove tci_read_r8s
[PULL 45/56] tcg/optimize: Expand fold_addsub2_i32 to 64-bit ops
1
Use explicit casts for ext8s opcodes.
1
Rename to fold_addsub2.
2
Use Int128 to implement the wider operation.
2
3
4
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
5
Reviewed-by: Luis Pires <luis.pires@eldorado.org.br>
3
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
6
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
---
8
---
6
tcg/tci.c | 25 ++++---------------------
9
tcg/optimize.c | 65 ++++++++++++++++++++++++++++++++++----------------
7
1 file changed, 4 insertions(+), 21 deletions(-)
10
1 file changed, 44 insertions(+), 21 deletions(-)
8
11
9
diff --git a/tcg/tci.c b/tcg/tci.c
12
diff --git a/tcg/optimize.c b/tcg/optimize.c
10
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
11
--- a/tcg/tci.c
14
--- a/tcg/optimize.c
12
+++ b/tcg/tci.c
15
+++ b/tcg/optimize.c
13
@@ -XXX,XX +XXX,XX @@ static tcg_target_ulong tci_read_reg(const tcg_target_ulong *regs, TCGReg index)
16
@@ -XXX,XX +XXX,XX @@
14
return regs[index];
17
*/
18
19
#include "qemu/osdep.h"
20
+#include "qemu/int128.h"
21
#include "tcg/tcg-op.h"
22
#include "tcg-internal.h"
23
24
@@ -XXX,XX +XXX,XX @@ static bool fold_add(OptContext *ctx, TCGOp *op)
25
return false;
15
}
26
}
16
27
17
-#if TCG_TARGET_HAS_ext8s_i32 || TCG_TARGET_HAS_ext8s_i64
28
-static bool fold_addsub2_i32(OptContext *ctx, TCGOp *op, bool add)
18
-static int8_t tci_read_reg8s(const tcg_target_ulong *regs, TCGReg index)
29
+static bool fold_addsub2(OptContext *ctx, TCGOp *op, bool add)
19
-{
20
- return (int8_t)tci_read_reg(regs, index);
21
-}
22
-#endif
23
-
24
#if TCG_TARGET_HAS_ext16s_i32 || TCG_TARGET_HAS_ext16s_i64
25
static int16_t tci_read_reg16s(const tcg_target_ulong *regs, TCGReg index)
26
{
30
{
27
@@ -XXX,XX +XXX,XX @@ tci_read_r(const tcg_target_ulong *regs, const uint8_t **tb_ptr)
31
if (arg_is_const(op->args[2]) && arg_is_const(op->args[3]) &&
28
return value;
32
arg_is_const(op->args[4]) && arg_is_const(op->args[5])) {
33
- uint32_t al = arg_info(op->args[2])->val;
34
- uint32_t ah = arg_info(op->args[3])->val;
35
- uint32_t bl = arg_info(op->args[4])->val;
36
- uint32_t bh = arg_info(op->args[5])->val;
37
- uint64_t a = ((uint64_t)ah << 32) | al;
38
- uint64_t b = ((uint64_t)bh << 32) | bl;
39
+ uint64_t al = arg_info(op->args[2])->val;
40
+ uint64_t ah = arg_info(op->args[3])->val;
41
+ uint64_t bl = arg_info(op->args[4])->val;
42
+ uint64_t bh = arg_info(op->args[5])->val;
43
TCGArg rl, rh;
44
- TCGOp *op2 = tcg_op_insert_before(ctx->tcg, op, INDEX_op_mov_i32);
45
+ TCGOp *op2;
46
47
- if (add) {
48
- a += b;
49
+ if (ctx->type == TCG_TYPE_I32) {
50
+ uint64_t a = deposit64(al, 32, 32, ah);
51
+ uint64_t b = deposit64(bl, 32, 32, bh);
52
+
53
+ if (add) {
54
+ a += b;
55
+ } else {
56
+ a -= b;
57
+ }
58
+
59
+ al = sextract64(a, 0, 32);
60
+ ah = sextract64(a, 32, 32);
61
} else {
62
- a -= b;
63
+ Int128 a = int128_make128(al, ah);
64
+ Int128 b = int128_make128(bl, bh);
65
+
66
+ if (add) {
67
+ a = int128_add(a, b);
68
+ } else {
69
+ a = int128_sub(a, b);
70
+ }
71
+
72
+ al = int128_getlo(a);
73
+ ah = int128_gethi(a);
74
}
75
76
rl = op->args[0];
77
rh = op->args[1];
78
- tcg_opt_gen_movi(ctx, op, rl, (int32_t)a);
79
- tcg_opt_gen_movi(ctx, op2, rh, (int32_t)(a >> 32));
80
+
81
+ /* The proper opcode is supplied by tcg_opt_gen_mov. */
82
+ op2 = tcg_op_insert_before(ctx->tcg, op, 0);
83
+
84
+ tcg_opt_gen_movi(ctx, op, rl, al);
85
+ tcg_opt_gen_movi(ctx, op2, rh, ah);
86
return true;
87
}
88
return false;
29
}
89
}
30
90
31
-#if TCG_TARGET_HAS_ext8s_i32 || TCG_TARGET_HAS_ext8s_i64
91
-static bool fold_add2_i32(OptContext *ctx, TCGOp *op)
32
-/* Read indexed register (8 bit signed) from bytecode. */
92
+static bool fold_add2(OptContext *ctx, TCGOp *op)
33
-static int8_t tci_read_r8s(const tcg_target_ulong *regs, const uint8_t **tb_ptr)
93
{
34
-{
94
- return fold_addsub2_i32(ctx, op, true);
35
- int8_t value = tci_read_reg8s(regs, **tb_ptr);
95
+ return fold_addsub2(ctx, op, true);
36
- *tb_ptr += 1;
96
}
37
- return value;
97
38
-}
98
static bool fold_and(OptContext *ctx, TCGOp *op)
39
-#endif
99
@@ -XXX,XX +XXX,XX @@ static bool fold_sub(OptContext *ctx, TCGOp *op)
40
-
100
return false;
41
/* Read indexed register (16 bit) from bytecode. */
101
}
42
static uint16_t tci_read_r16(const tcg_target_ulong *regs,
102
43
const uint8_t **tb_ptr)
103
-static bool fold_sub2_i32(OptContext *ctx, TCGOp *op)
44
@@ -XXX,XX +XXX,XX @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
104
+static bool fold_sub2(OptContext *ctx, TCGOp *op)
45
#if TCG_TARGET_HAS_ext8s_i32
105
{
46
case INDEX_op_ext8s_i32:
106
- return fold_addsub2_i32(ctx, op, false);
47
t0 = *tb_ptr++;
107
+ return fold_addsub2(ctx, op, false);
48
- t1 = tci_read_r8s(regs, &tb_ptr);
108
}
49
- tci_write_reg(regs, t0, t1);
109
50
+ t1 = tci_read_r(regs, &tb_ptr);
110
static bool fold_tcg_ld(OptContext *ctx, TCGOp *op)
51
+ tci_write_reg(regs, t0, (int8_t)t1);
111
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
112
CASE_OP_32_64_VEC(add):
113
done = fold_add(&ctx, op);
52
break;
114
break;
53
#endif
115
- case INDEX_op_add2_i32:
54
#if TCG_TARGET_HAS_ext16s_i32
116
- done = fold_add2_i32(&ctx, op);
55
@@ -XXX,XX +XXX,XX @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
117
+ CASE_OP_32_64(add2):
56
#if TCG_TARGET_HAS_ext8s_i64
118
+ done = fold_add2(&ctx, op);
57
case INDEX_op_ext8s_i64:
58
t0 = *tb_ptr++;
59
- t1 = tci_read_r8s(regs, &tb_ptr);
60
- tci_write_reg(regs, t0, t1);
61
+ t1 = tci_read_r(regs, &tb_ptr);
62
+ tci_write_reg(regs, t0, (int8_t)t1);
63
break;
119
break;
64
#endif
120
CASE_OP_32_64_VEC(and):
65
#if TCG_TARGET_HAS_ext16s_i64
121
done = fold_and(&ctx, op);
122
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
123
CASE_OP_32_64_VEC(sub):
124
done = fold_sub(&ctx, op);
125
break;
126
- case INDEX_op_sub2_i32:
127
- done = fold_sub2_i32(&ctx, op);
128
+ CASE_OP_32_64(sub2):
129
+ done = fold_sub2(&ctx, op);
130
break;
131
CASE_OP_32_64_VEC(xor):
132
done = fold_xor(&ctx, op);
66
--
133
--
67
2.25.1
134
2.25.1
68
135
69
136
diff view generated by jsdifflib
[PATCH 10/27] tcg/tci: Merge identical cases in generation (conditional opcodes)
[PULL 46/56] tcg/optimize: Sink commutative operand swapping into fold functions
1
Use CASE_32_64 and CASE_64 to reduce ifdefs and merge
1
Most of these are handled by creating a fold_const2_commutative
2
cases that are identical between 32-bit and 64-bit hosts.
2
to handle all of the binary operators. The rest were already
3
3
handled on a case-by-case basis in the switch, and have their
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
own fold function in which to place the call.
5
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
5
6
Message-Id: <20210217202036.1724901-5-richard.henderson@linaro.org>
6
We now have only one major switch on TCGOpcode.
7
[PMD: Split patch as 4/5]
7
8
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Introduce NO_DEST and a block comment for swap_commutative in
9
Message-Id: <20210218232840.1760806-5-f4bug@amsat.org>
9
order to make the handling of brcond and movcond opcodes cleaner.
10
11
Reviewed-by: Luis Pires <luis.pires@eldorado.org.br>
10
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
11
---
13
---
12
tcg/tci/tcg-target.c.inc | 23 ++++++-----------------
14
tcg/optimize.c | 142 ++++++++++++++++++++++++-------------------------
13
1 file changed, 6 insertions(+), 17 deletions(-)
15
1 file changed, 70 insertions(+), 72 deletions(-)
14
16
15
diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
17
diff --git a/tcg/optimize.c b/tcg/optimize.c
16
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
17
--- a/tcg/tci/tcg-target.c.inc
19
--- a/tcg/optimize.c
18
+++ b/tcg/tci/tcg-target.c.inc
20
+++ b/tcg/optimize.c
19
@@ -XXX,XX +XXX,XX @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
21
@@ -XXX,XX +XXX,XX @@ static int do_constant_folding_cond2(TCGArg *p1, TCGArg *p2, TCGCond c)
22
return -1;
23
}
24
25
+/**
26
+ * swap_commutative:
27
+ * @dest: TCGArg of the destination argument, or NO_DEST.
28
+ * @p1: first paired argument
29
+ * @p2: second paired argument
30
+ *
31
+ * If *@p1 is a constant and *@p2 is not, swap.
32
+ * If *@p2 matches @dest, swap.
33
+ * Return true if a swap was performed.
34
+ */
35
+
36
+#define NO_DEST temp_arg(NULL)
37
+
38
static bool swap_commutative(TCGArg dest, TCGArg *p1, TCGArg *p2)
39
{
40
TCGArg a1 = *p1, a2 = *p2;
41
@@ -XXX,XX +XXX,XX @@ static bool fold_const2(OptContext *ctx, TCGOp *op)
42
return false;
43
}
44
45
+static bool fold_const2_commutative(OptContext *ctx, TCGOp *op)
46
+{
47
+ swap_commutative(op->args[0], &op->args[1], &op->args[2]);
48
+ return fold_const2(ctx, op);
49
+}
50
+
51
static bool fold_masks(OptContext *ctx, TCGOp *op)
52
{
53
uint64_t a_mask = ctx->a_mask;
54
@@ -XXX,XX +XXX,XX @@ static bool fold_xx_to_x(OptContext *ctx, TCGOp *op)
55
56
static bool fold_add(OptContext *ctx, TCGOp *op)
57
{
58
- if (fold_const2(ctx, op) ||
59
+ if (fold_const2_commutative(ctx, op) ||
60
fold_xi_to_x(ctx, op, 0)) {
61
return true;
62
}
63
@@ -XXX,XX +XXX,XX @@ static bool fold_addsub2(OptContext *ctx, TCGOp *op, bool add)
64
65
static bool fold_add2(OptContext *ctx, TCGOp *op)
66
{
67
+ /* Note that the high and low parts may be independently swapped. */
68
+ swap_commutative(op->args[0], &op->args[2], &op->args[4]);
69
+ swap_commutative(op->args[1], &op->args[3], &op->args[5]);
70
+
71
return fold_addsub2(ctx, op, true);
72
}
73
74
@@ -XXX,XX +XXX,XX @@ static bool fold_and(OptContext *ctx, TCGOp *op)
75
{
76
uint64_t z1, z2;
77
78
- if (fold_const2(ctx, op) ||
79
+ if (fold_const2_commutative(ctx, op) ||
80
fold_xi_to_i(ctx, op, 0) ||
81
fold_xi_to_x(ctx, op, -1) ||
82
fold_xx_to_x(ctx, op)) {
83
@@ -XXX,XX +XXX,XX @@ static bool fold_andc(OptContext *ctx, TCGOp *op)
84
static bool fold_brcond(OptContext *ctx, TCGOp *op)
85
{
86
TCGCond cond = op->args[2];
87
- int i = do_constant_folding_cond(ctx->type, op->args[0], op->args[1], cond);
88
+ int i;
89
90
+ if (swap_commutative(NO_DEST, &op->args[0], &op->args[1])) {
91
+ op->args[2] = cond = tcg_swap_cond(cond);
92
+ }
93
+
94
+ i = do_constant_folding_cond(ctx->type, op->args[0], op->args[1], cond);
95
if (i == 0) {
96
tcg_op_remove(ctx->tcg, op);
97
return true;
98
@@ -XXX,XX +XXX,XX @@ static bool fold_brcond(OptContext *ctx, TCGOp *op)
99
static bool fold_brcond2(OptContext *ctx, TCGOp *op)
100
{
101
TCGCond cond = op->args[4];
102
- int i = do_constant_folding_cond2(&op->args[0], &op->args[2], cond);
103
TCGArg label = op->args[5];
104
- int inv = 0;
105
+ int i, inv = 0;
106
107
+ if (swap_commutative2(&op->args[0], &op->args[2])) {
108
+ op->args[4] = cond = tcg_swap_cond(cond);
109
+ }
110
+
111
+ i = do_constant_folding_cond2(&op->args[0], &op->args[2], cond);
112
if (i >= 0) {
113
goto do_brcond_const;
114
}
115
@@ -XXX,XX +XXX,XX @@ static bool fold_dup2(OptContext *ctx, TCGOp *op)
116
117
static bool fold_eqv(OptContext *ctx, TCGOp *op)
118
{
119
- if (fold_const2(ctx, op) ||
120
+ if (fold_const2_commutative(ctx, op) ||
121
fold_xi_to_x(ctx, op, -1) ||
122
fold_xi_to_not(ctx, op, 0)) {
123
return true;
124
@@ -XXX,XX +XXX,XX @@ static bool fold_mov(OptContext *ctx, TCGOp *op)
125
static bool fold_movcond(OptContext *ctx, TCGOp *op)
126
{
127
TCGCond cond = op->args[5];
128
- int i = do_constant_folding_cond(ctx->type, op->args[1], op->args[2], cond);
129
+ int i;
130
131
+ if (swap_commutative(NO_DEST, &op->args[1], &op->args[2])) {
132
+ op->args[5] = cond = tcg_swap_cond(cond);
133
+ }
134
+ /*
135
+ * Canonicalize the "false" input reg to match the destination reg so
136
+ * that the tcg backend can implement a "move if true" operation.
137
+ */
138
+ if (swap_commutative(op->args[0], &op->args[4], &op->args[3])) {
139
+ op->args[5] = cond = tcg_invert_cond(cond);
140
+ }
141
+
142
+ i = do_constant_folding_cond(ctx->type, op->args[1], op->args[2], cond);
143
if (i >= 0) {
144
return tcg_opt_gen_mov(ctx, op, op->args[0], op->args[4 - i]);
145
}
146
@@ -XXX,XX +XXX,XX @@ static bool fold_mul(OptContext *ctx, TCGOp *op)
147
148
static bool fold_mul_highpart(OptContext *ctx, TCGOp *op)
149
{
150
- if (fold_const2(ctx, op) ||
151
+ if (fold_const2_commutative(ctx, op) ||
152
fold_xi_to_i(ctx, op, 0)) {
153
return true;
154
}
155
@@ -XXX,XX +XXX,XX @@ static bool fold_mul_highpart(OptContext *ctx, TCGOp *op)
156
157
static bool fold_multiply2(OptContext *ctx, TCGOp *op)
158
{
159
+ swap_commutative(op->args[0], &op->args[2], &op->args[3]);
160
+
161
if (arg_is_const(op->args[2]) && arg_is_const(op->args[3])) {
162
uint64_t a = arg_info(op->args[2])->val;
163
uint64_t b = arg_info(op->args[3])->val;
164
@@ -XXX,XX +XXX,XX @@ static bool fold_multiply2(OptContext *ctx, TCGOp *op)
165
166
static bool fold_nand(OptContext *ctx, TCGOp *op)
167
{
168
- if (fold_const2(ctx, op) ||
169
+ if (fold_const2_commutative(ctx, op) ||
170
fold_xi_to_not(ctx, op, -1)) {
171
return true;
172
}
173
@@ -XXX,XX +XXX,XX @@ static bool fold_neg(OptContext *ctx, TCGOp *op)
174
175
static bool fold_nor(OptContext *ctx, TCGOp *op)
176
{
177
- if (fold_const2(ctx, op) ||
178
+ if (fold_const2_commutative(ctx, op) ||
179
fold_xi_to_not(ctx, op, 0)) {
180
return true;
181
}
182
@@ -XXX,XX +XXX,XX @@ static bool fold_not(OptContext *ctx, TCGOp *op)
183
184
static bool fold_or(OptContext *ctx, TCGOp *op)
185
{
186
- if (fold_const2(ctx, op) ||
187
+ if (fold_const2_commutative(ctx, op) ||
188
fold_xi_to_x(ctx, op, 0) ||
189
fold_xx_to_x(ctx, op)) {
190
return true;
191
@@ -XXX,XX +XXX,XX @@ static bool fold_remainder(OptContext *ctx, TCGOp *op)
192
static bool fold_setcond(OptContext *ctx, TCGOp *op)
193
{
194
TCGCond cond = op->args[3];
195
- int i = do_constant_folding_cond(ctx->type, op->args[1], op->args[2], cond);
196
+ int i;
197
198
+ if (swap_commutative(op->args[0], &op->args[1], &op->args[2])) {
199
+ op->args[3] = cond = tcg_swap_cond(cond);
200
+ }
201
+
202
+ i = do_constant_folding_cond(ctx->type, op->args[1], op->args[2], cond);
203
if (i >= 0) {
204
return tcg_opt_gen_movi(ctx, op, op->args[0], i);
205
}
206
@@ -XXX,XX +XXX,XX @@ static bool fold_setcond(OptContext *ctx, TCGOp *op)
207
static bool fold_setcond2(OptContext *ctx, TCGOp *op)
208
{
209
TCGCond cond = op->args[5];
210
- int i = do_constant_folding_cond2(&op->args[1], &op->args[3], cond);
211
- int inv = 0;
212
+ int i, inv = 0;
213
214
+ if (swap_commutative2(&op->args[1], &op->args[3])) {
215
+ op->args[5] = cond = tcg_swap_cond(cond);
216
+ }
217
+
218
+ i = do_constant_folding_cond2(&op->args[1], &op->args[3], cond);
219
if (i >= 0) {
220
goto do_setcond_const;
221
}
222
@@ -XXX,XX +XXX,XX @@ static bool fold_tcg_ld(OptContext *ctx, TCGOp *op)
223
224
static bool fold_xor(OptContext *ctx, TCGOp *op)
225
{
226
- if (fold_const2(ctx, op) ||
227
+ if (fold_const2_commutative(ctx, op) ||
228
fold_xx_to_i(ctx, op, 0) ||
229
fold_xi_to_x(ctx, op, 0) ||
230
fold_xi_to_not(ctx, op, -1)) {
231
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
232
ctx.type = TCG_TYPE_I32;
20
}
233
}
21
set_jmp_reset_offset(s, args[0]);
234
22
break;
235
- /* For commutative operations make constant second argument */
23
+
236
- switch (opc) {
24
case INDEX_op_br:
237
- CASE_OP_32_64_VEC(add):
25
tci_out_label(s, arg_label(args[0]));
238
- CASE_OP_32_64_VEC(mul):
26
break;
239
- CASE_OP_32_64_VEC(and):
27
- case INDEX_op_setcond_i32:
240
- CASE_OP_32_64_VEC(or):
28
+
241
- CASE_OP_32_64_VEC(xor):
29
+ CASE_32_64(setcond)
242
- CASE_OP_32_64(eqv):
30
tcg_out_r(s, args[0]);
243
- CASE_OP_32_64(nand):
31
tcg_out_r(s, args[1]);
244
- CASE_OP_32_64(nor):
32
tcg_out_r(s, args[2]);
245
- CASE_OP_32_64(muluh):
33
tcg_out8(s, args[3]); /* condition */
246
- CASE_OP_32_64(mulsh):
34
break;
247
- swap_commutative(op->args[0], &op->args[1], &op->args[2]);
35
+
248
- break;
36
#if TCG_TARGET_REG_BITS == 32
249
- CASE_OP_32_64(brcond):
37
case INDEX_op_setcond2_i32:
250
- if (swap_commutative(-1, &op->args[0], &op->args[1])) {
38
/* setcond2_i32 cond, t0, t1_low, t1_high, t2_low, t2_high */
251
- op->args[2] = tcg_swap_cond(op->args[2]);
39
@@ -XXX,XX +XXX,XX @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
252
- }
40
tcg_out_r(s, args[4]);
253
- break;
41
tcg_out8(s, args[5]); /* condition */
254
- CASE_OP_32_64(setcond):
42
break;
255
- if (swap_commutative(op->args[0], &op->args[1], &op->args[2])) {
43
-#elif TCG_TARGET_REG_BITS == 64
256
- op->args[3] = tcg_swap_cond(op->args[3]);
44
- case INDEX_op_setcond_i64:
257
- }
45
- tcg_out_r(s, args[0]);
258
- break;
46
- tcg_out_r(s, args[1]);
259
- CASE_OP_32_64(movcond):
47
- tcg_out_r(s, args[2]);
260
- if (swap_commutative(-1, &op->args[1], &op->args[2])) {
48
- tcg_out8(s, args[3]); /* condition */
261
- op->args[5] = tcg_swap_cond(op->args[5]);
49
- break;
262
- }
50
#endif
263
- /* For movcond, we canonicalize the "false" input reg to match
51
case INDEX_op_ld8u_i32:
264
- the destination reg so that the tcg backend can implement
52
case INDEX_op_ld8s_i32:
265
- a "move if true" operation. */
53
@@ -XXX,XX +XXX,XX @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
266
- if (swap_commutative(op->args[0], &op->args[4], &op->args[3])) {
54
tcg_out8(s, args[4]);
267
- op->args[5] = tcg_invert_cond(op->args[5]);
55
break;
268
- }
56
269
- break;
57
-#if TCG_TARGET_REG_BITS == 64
270
- CASE_OP_32_64(add2):
58
- case INDEX_op_brcond_i64:
271
- swap_commutative(op->args[0], &op->args[2], &op->args[4]);
59
+ CASE_32_64(brcond)
272
- swap_commutative(op->args[1], &op->args[3], &op->args[5]);
60
tcg_out_r(s, args[0]);
273
- break;
61
tcg_out_r(s, args[1]);
274
- CASE_OP_32_64(mulu2):
62
tcg_out8(s, args[2]); /* condition */
275
- CASE_OP_32_64(muls2):
63
tci_out_label(s, arg_label(args[3]));
276
- swap_commutative(op->args[0], &op->args[2], &op->args[3]);
64
break;
277
- break;
65
-#endif /* TCG_TARGET_REG_BITS == 64 */
278
- case INDEX_op_brcond2_i32:
66
279
- if (swap_commutative2(&op->args[0], &op->args[2])) {
67
CASE_32_64(neg) /* Optional (TCG_TARGET_HAS_neg_*). */
280
- op->args[4] = tcg_swap_cond(op->args[4]);
68
CASE_32_64(not) /* Optional (TCG_TARGET_HAS_not_*). */
281
- }
69
@@ -XXX,XX +XXX,XX @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
282
- break;
70
tcg_out_r(s, args[3]);
283
- case INDEX_op_setcond2_i32:
71
break;
284
- if (swap_commutative2(&op->args[1], &op->args[3])) {
72
#endif
285
- op->args[5] = tcg_swap_cond(op->args[5]);
73
- case INDEX_op_brcond_i32:
286
- }
74
- tcg_out_r(s, args[0]);
287
- break;
75
- tcg_out_r(s, args[1]);
288
- default:
76
- tcg_out8(s, args[2]); /* condition */
289
- break;
77
- tci_out_label(s, arg_label(args[3]));
290
- }
78
- break;
291
-
79
+
292
/* Assume all bits affected, and no bits known zero. */
80
case INDEX_op_qemu_ld_i32:
293
ctx.a_mask = -1;
81
tcg_out_r(s, *args++);
294
ctx.z_mask = -1;
82
tcg_out_r(s, *args++);
83
--
295
--
84
2.25.1
296
2.25.1
85
297
86
298
diff view generated by jsdifflib
[PATCH 11/27] tcg/tci: Merge identical cases in generation (load/store opcodes)
[PULL 47/56] tcg/optimize: Stop forcing z_mask to "garbage" for 32-bit values
1
Use CASE_32_64 and CASE_64 to reduce ifdefs and merge
1
This "garbage" setting pre-dates the addition of the type
2
cases that are identical between 32-bit and 64-bit hosts.
2
changing opcodes INDEX_op_ext_i32_i64, INDEX_op_extu_i32_i64,
3
and INDEX_op_extr{l,h}_i64_i32.
3
4
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
So now we have a definitive points at which to adjust z_mask
5
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
6
to eliminate such bits from the 32-bit operands.
6
Message-Id: <20210217202036.1724901-5-richard.henderson@linaro.org>
7
7
[PMD: Split patch as 5/5]
8
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
8
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
Reviewed-by: Luis Pires <luis.pires@eldorado.org.br>
9
Message-Id: <20210218232840.1760806-6-f4bug@amsat.org>
10
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
11
---
11
---
12
tcg/tci/tcg-target.c.inc | 49 ++++++++++++----------------------------
12
tcg/optimize.c | 35 ++++++++++++++++-------------------
13
1 file changed, 14 insertions(+), 35 deletions(-)
13
1 file changed, 16 insertions(+), 19 deletions(-)
14
14
15
diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
15
diff --git a/tcg/optimize.c b/tcg/optimize.c
16
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
17
--- a/tcg/tci/tcg-target.c.inc
17
--- a/tcg/optimize.c
18
+++ b/tcg/tci/tcg-target.c.inc
18
+++ b/tcg/optimize.c
19
@@ -XXX,XX +XXX,XX @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
19
@@ -XXX,XX +XXX,XX @@ static void init_ts_info(OptContext *ctx, TCGTemp *ts)
20
tcg_out8(s, args[5]); /* condition */
20
ti->is_const = true;
21
break;
21
ti->val = ts->val;
22
#endif
22
ti->z_mask = ts->val;
23
- case INDEX_op_ld8u_i32:
23
- if (TCG_TARGET_REG_BITS > 32 && ts->type == TCG_TYPE_I32) {
24
- case INDEX_op_ld8s_i32:
24
- /* High bits of a 32-bit quantity are garbage. */
25
- case INDEX_op_ld16u_i32:
25
- ti->z_mask |= ~0xffffffffull;
26
- case INDEX_op_ld16s_i32:
26
- }
27
} else {
28
ti->is_const = false;
29
ti->z_mask = -1;
30
@@ -XXX,XX +XXX,XX @@ static bool tcg_opt_gen_mov(OptContext *ctx, TCGOp *op, TCGArg dst, TCGArg src)
31
TCGTemp *src_ts = arg_temp(src);
32
TempOptInfo *di;
33
TempOptInfo *si;
34
- uint64_t z_mask;
35
TCGOpcode new_op;
36
37
if (ts_are_copies(dst_ts, src_ts)) {
38
@@ -XXX,XX +XXX,XX @@ static bool tcg_opt_gen_mov(OptContext *ctx, TCGOp *op, TCGArg dst, TCGArg src)
39
op->args[0] = dst;
40
op->args[1] = src;
41
42
- z_mask = si->z_mask;
43
- if (TCG_TARGET_REG_BITS > 32 && new_op == INDEX_op_mov_i32) {
44
- /* High bits of the destination are now garbage. */
45
- z_mask |= ~0xffffffffull;
46
- }
47
- di->z_mask = z_mask;
48
+ di->z_mask = si->z_mask;
49
50
if (src_ts->type == dst_ts->type) {
51
TempOptInfo *ni = ts_info(si->next_copy);
52
@@ -XXX,XX +XXX,XX @@ static bool tcg_opt_gen_mov(OptContext *ctx, TCGOp *op, TCGArg dst, TCGArg src)
53
static bool tcg_opt_gen_movi(OptContext *ctx, TCGOp *op,
54
TCGArg dst, uint64_t val)
55
{
56
- /* Convert movi to mov with constant temp. */
57
- TCGTemp *tv = tcg_constant_internal(ctx->type, val);
58
+ TCGTemp *tv;
59
60
+ if (ctx->type == TCG_TYPE_I32) {
61
+ val = (int32_t)val;
62
+ }
27
+
63
+
28
+ CASE_32_64(ld8u)
64
+ /* Convert movi to mov with constant temp. */
29
+ CASE_32_64(ld8s)
65
+ tv = tcg_constant_internal(ctx->type, val);
30
+ CASE_32_64(ld16u)
66
init_ts_info(ctx, tv);
31
+ CASE_32_64(ld16s)
67
return tcg_opt_gen_mov(ctx, op, dst, temp_arg(tv));
32
case INDEX_op_ld_i32:
68
}
33
- case INDEX_op_st8_i32:
69
@@ -XXX,XX +XXX,XX @@ static bool fold_masks(OptContext *ctx, TCGOp *op)
34
- case INDEX_op_st16_i32:
70
uint64_t z_mask = ctx->z_mask;
35
+ CASE_64(ld32u)
71
36
+ CASE_64(ld32s)
72
/*
37
+ CASE_64(ld)
73
- * 32-bit ops generate 32-bit results. For the result is zero test
38
+ CASE_32_64(st8)
74
- * below, we can ignore high bits, but for further optimizations we
39
+ CASE_32_64(st16)
75
- * need to record that the high bits contain garbage.
40
case INDEX_op_st_i32:
76
+ * 32-bit ops generate 32-bit results, which for the purpose of
41
- case INDEX_op_ld8u_i64:
77
+ * simplifying tcg are sign-extended. Certainly that's how we
42
- case INDEX_op_ld8s_i64:
78
+ * represent our constants elsewhere. Note that the bits will
43
- case INDEX_op_ld16u_i64:
79
+ * be reset properly for a 64-bit value when encountering the
44
- case INDEX_op_ld16s_i64:
80
+ * type changing opcodes.
45
- case INDEX_op_ld32u_i64:
81
*/
46
- case INDEX_op_ld32s_i64:
82
if (ctx->type == TCG_TYPE_I32) {
47
- case INDEX_op_ld_i64:
83
- ctx->z_mask |= MAKE_64BIT_MASK(32, 32);
48
- case INDEX_op_st8_i64:
84
- a_mask &= MAKE_64BIT_MASK(0, 32);
49
- case INDEX_op_st16_i64:
85
- z_mask &= MAKE_64BIT_MASK(0, 32);
50
- case INDEX_op_st32_i64:
86
+ a_mask = (int32_t)a_mask;
51
- case INDEX_op_st_i64:
87
+ z_mask = (int32_t)z_mask;
52
+ CASE_64(st32)
88
+ ctx->z_mask = z_mask;
53
+ CASE_64(st)
89
}
54
stack_bounds_check(args[1], args[2]);
90
55
tcg_out_r(s, args[0]);
91
if (z_mask == 0) {
56
tcg_out_r(s, args[1]);
57
@@ -XXX,XX +XXX,XX @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
58
#endif
59
60
case INDEX_op_qemu_ld_i32:
61
- tcg_out_r(s, *args++);
62
- tcg_out_r(s, *args++);
63
- if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) {
64
- tcg_out_r(s, *args++);
65
- }
66
- tcg_out_i(s, *args++);
67
- break;
68
- case INDEX_op_qemu_ld_i64:
69
- tcg_out_r(s, *args++);
70
- if (TCG_TARGET_REG_BITS == 32) {
71
- tcg_out_r(s, *args++);
72
- }
73
- tcg_out_r(s, *args++);
74
- if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) {
75
- tcg_out_r(s, *args++);
76
- }
77
- tcg_out_i(s, *args++);
78
- break;
79
case INDEX_op_qemu_st_i32:
80
tcg_out_r(s, *args++);
81
tcg_out_r(s, *args++);
82
@@ -XXX,XX +XXX,XX @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
83
}
84
tcg_out_i(s, *args++);
85
break;
86
+
87
+ case INDEX_op_qemu_ld_i64:
88
case INDEX_op_qemu_st_i64:
89
tcg_out_r(s, *args++);
90
if (TCG_TARGET_REG_BITS == 32) {
91
--
92
--
92
2.25.1
93
2.25.1
93
94
94
95
diff view generated by jsdifflib
[PATCH 21/27] tcg/tci: Merge bswap operations
[PULL 48/56] tcg/optimize: Use fold_xx_to_i for orc
1
This includes bswap16 and bswap32.
1
Recognize the constant function for or-complement.
2
2
3
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
4
Reviewed-by: Luis Pires <luis.pires@eldorado.org.br>
3
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
5
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
---
7
---
6
tcg/tci.c | 22 ++++------------------
8
tcg/optimize.c | 1 +
7
1 file changed, 4 insertions(+), 18 deletions(-)
9
1 file changed, 1 insertion(+)
8
10
9
diff --git a/tcg/tci.c b/tcg/tci.c
11
diff --git a/tcg/optimize.c b/tcg/optimize.c
10
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
11
--- a/tcg/tci.c
13
--- a/tcg/optimize.c
12
+++ b/tcg/tci.c
14
+++ b/tcg/optimize.c
13
@@ -XXX,XX +XXX,XX @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
15
@@ -XXX,XX +XXX,XX @@ static bool fold_or(OptContext *ctx, TCGOp *op)
14
tci_write_reg(regs, t0, (uint16_t)t1);
16
static bool fold_orc(OptContext *ctx, TCGOp *op)
15
break;
17
{
16
#endif
18
if (fold_const2(ctx, op) ||
17
-#if TCG_TARGET_HAS_bswap16_i32
19
+ fold_xx_to_i(ctx, op, -1) ||
18
- case INDEX_op_bswap16_i32:
20
fold_xi_to_x(ctx, op, -1) ||
19
+#if TCG_TARGET_HAS_bswap16_i32 || TCG_TARGET_HAS_bswap16_i64
21
fold_ix_to_not(ctx, op, 0)) {
20
+ CASE_32_64(bswap16)
22
return true;
21
t0 = *tb_ptr++;
22
t1 = tci_read_r(regs, &tb_ptr);
23
tci_write_reg(regs, t0, bswap16(t1));
24
break;
25
#endif
26
-#if TCG_TARGET_HAS_bswap32_i32
27
- case INDEX_op_bswap32_i32:
28
+#if TCG_TARGET_HAS_bswap32_i32 || TCG_TARGET_HAS_bswap32_i64
29
+ CASE_32_64(bswap32)
30
t0 = *tb_ptr++;
31
t1 = tci_read_r(regs, &tb_ptr);
32
tci_write_reg(regs, t0, bswap32(t1));
33
@@ -XXX,XX +XXX,XX @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
34
t1 = tci_read_r(regs, &tb_ptr);
35
tci_write_reg(regs, t0, (uint32_t)t1);
36
break;
37
-#if TCG_TARGET_HAS_bswap16_i64
38
- case INDEX_op_bswap16_i64:
39
- t0 = *tb_ptr++;
40
- t1 = tci_read_r(regs, &tb_ptr);
41
- tci_write_reg(regs, t0, bswap16(t1));
42
- break;
43
-#endif
44
-#if TCG_TARGET_HAS_bswap32_i64
45
- case INDEX_op_bswap32_i64:
46
- t0 = *tb_ptr++;
47
- t1 = tci_read_r(regs, &tb_ptr);
48
- tci_write_reg(regs, t0, bswap32(t1));
49
- break;
50
-#endif
51
#if TCG_TARGET_HAS_bswap64_i64
52
case INDEX_op_bswap64_i64:
53
t0 = *tb_ptr++;
54
--
23
--
55
2.25.1
24
2.25.1
56
25
57
26
diff view generated by jsdifflib
[PATCH 09/27] tcg/tci: Merge identical cases in generation (deposit opcode)
[PULL 49/56] tcg/optimize: Use fold_xi_to_x for mul
1
Use CASE_32_64 and CASE_64 to reduce ifdefs and merge
1
Recognize the identity function for low-part multiply.
2
cases that are identical between 32-bit and 64-bit hosts.
3
2
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
3
Suggested-by: Luis Pires <luis.pires@eldorado.org.br>
4
Reviewed-by: Luis Pires <luis.pires@eldorado.org.br>
5
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
5
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
6
Message-Id: <20210217202036.1724901-5-richard.henderson@linaro.org>
7
[PMD: Split patch as 3/5]
8
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
Message-Id: <20210218232840.1760806-4-f4bug@amsat.org>
10
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
11
---
7
---
12
tcg/tci/tcg-target.c.inc | 12 ++----------
8
tcg/optimize.c | 3 ++-
13
1 file changed, 2 insertions(+), 10 deletions(-)
9
1 file changed, 2 insertions(+), 1 deletion(-)
14
10
15
diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
11
diff --git a/tcg/optimize.c b/tcg/optimize.c
16
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
17
--- a/tcg/tci/tcg-target.c.inc
13
--- a/tcg/optimize.c
18
+++ b/tcg/tci/tcg-target.c.inc
14
+++ b/tcg/optimize.c
19
@@ -XXX,XX +XXX,XX @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
15
@@ -XXX,XX +XXX,XX @@ static bool fold_movcond(OptContext *ctx, TCGOp *op)
20
tcg_out_r(s, args[1]);
16
static bool fold_mul(OptContext *ctx, TCGOp *op)
21
tcg_out_r(s, args[2]);
17
{
22
break;
18
if (fold_const2(ctx, op) ||
23
- case INDEX_op_deposit_i32: /* Optional (TCG_TARGET_HAS_deposit_i32). */
19
- fold_xi_to_i(ctx, op, 0)) {
24
+
20
+ fold_xi_to_i(ctx, op, 0) ||
25
+ CASE_32_64(deposit) /* Optional (TCG_TARGET_HAS_deposit_*). */
21
+ fold_xi_to_x(ctx, op, 1)) {
26
tcg_out_r(s, args[0]);
22
return true;
27
tcg_out_r(s, args[1]);
23
}
28
tcg_out_r(s, args[2]);
24
return false;
29
@@ -XXX,XX +XXX,XX @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
30
break;
31
32
#if TCG_TARGET_REG_BITS == 64
33
- case INDEX_op_deposit_i64: /* Optional (TCG_TARGET_HAS_deposit_i64). */
34
- tcg_out_r(s, args[0]);
35
- tcg_out_r(s, args[1]);
36
- tcg_out_r(s, args[2]);
37
- tcg_debug_assert(args[3] <= UINT8_MAX);
38
- tcg_out8(s, args[3]);
39
- tcg_debug_assert(args[4] <= UINT8_MAX);
40
- tcg_out8(s, args[4]);
41
- break;
42
case INDEX_op_brcond_i64:
43
tcg_out_r(s, args[0]);
44
tcg_out_r(s, args[1]);
45
--
25
--
46
2.25.1
26
2.25.1
47
27
48
28
diff view generated by jsdifflib
[PATCH 04/27] tcg/tci: Use exec/cpu_ldst.h interfaces
[PULL 50/56] tcg/optimize: Use fold_xi_to_x for div
1
Use the provided cpu_ldst.h interfaces. This fixes the build vs
1
Recognize the identity function for division.
2
the unconverted uses of g2h(), adds missed memory trace events,
3
and correctly recognizes when a SIGSEGV belongs to the guest via
4
set_helper_retaddr().
5
2
6
Fixes: 3e8f1628e864
3
Suggested-by: Luis Pires <luis.pires@eldorado.org.br>
7
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
4
Reviewed-by: Luis Pires <luis.pires@eldorado.org.br>
5
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
---
7
---
10
tcg/tci.c | 73 +++++++++++++++++++++----------------------------------
8
tcg/optimize.c | 6 +++++-
11
1 file changed, 28 insertions(+), 45 deletions(-)
9
1 file changed, 5 insertions(+), 1 deletion(-)
12
10
13
diff --git a/tcg/tci.c b/tcg/tci.c
11
diff --git a/tcg/optimize.c b/tcg/optimize.c
14
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
15
--- a/tcg/tci.c
13
--- a/tcg/optimize.c
16
+++ b/tcg/tci.c
14
+++ b/tcg/optimize.c
17
@@ -XXX,XX +XXX,XX @@ static bool tci_compare64(uint64_t u0, uint64_t u1, TCGCond condition)
15
@@ -XXX,XX +XXX,XX @@ static bool fold_deposit(OptContext *ctx, TCGOp *op)
18
return result;
16
17
static bool fold_divide(OptContext *ctx, TCGOp *op)
18
{
19
- return fold_const2(ctx, op);
20
+ if (fold_const2(ctx, op) ||
21
+ fold_xi_to_x(ctx, op, 1)) {
22
+ return true;
23
+ }
24
+ return false;
19
}
25
}
20
26
21
-#ifdef CONFIG_SOFTMMU
27
static bool fold_dup(OptContext *ctx, TCGOp *op)
22
-# define qemu_ld_ub \
23
- helper_ret_ldub_mmu(env, taddr, oi, (uintptr_t)tb_ptr)
24
-# define qemu_ld_leuw \
25
- helper_le_lduw_mmu(env, taddr, oi, (uintptr_t)tb_ptr)
26
-# define qemu_ld_leul \
27
- helper_le_ldul_mmu(env, taddr, oi, (uintptr_t)tb_ptr)
28
-# define qemu_ld_leq \
29
- helper_le_ldq_mmu(env, taddr, oi, (uintptr_t)tb_ptr)
30
-# define qemu_ld_beuw \
31
- helper_be_lduw_mmu(env, taddr, oi, (uintptr_t)tb_ptr)
32
-# define qemu_ld_beul \
33
- helper_be_ldul_mmu(env, taddr, oi, (uintptr_t)tb_ptr)
34
-# define qemu_ld_beq \
35
- helper_be_ldq_mmu(env, taddr, oi, (uintptr_t)tb_ptr)
36
-# define qemu_st_b(X) \
37
- helper_ret_stb_mmu(env, taddr, X, oi, (uintptr_t)tb_ptr)
38
-# define qemu_st_lew(X) \
39
- helper_le_stw_mmu(env, taddr, X, oi, (uintptr_t)tb_ptr)
40
-# define qemu_st_lel(X) \
41
- helper_le_stl_mmu(env, taddr, X, oi, (uintptr_t)tb_ptr)
42
-# define qemu_st_leq(X) \
43
- helper_le_stq_mmu(env, taddr, X, oi, (uintptr_t)tb_ptr)
44
-# define qemu_st_bew(X) \
45
- helper_be_stw_mmu(env, taddr, X, oi, (uintptr_t)tb_ptr)
46
-# define qemu_st_bel(X) \
47
- helper_be_stl_mmu(env, taddr, X, oi, (uintptr_t)tb_ptr)
48
-# define qemu_st_beq(X) \
49
- helper_be_stq_mmu(env, taddr, X, oi, (uintptr_t)tb_ptr)
50
-#else
51
-# define qemu_ld_ub ldub_p(g2h(taddr))
52
-# define qemu_ld_leuw lduw_le_p(g2h(taddr))
53
-# define qemu_ld_leul (uint32_t)ldl_le_p(g2h(taddr))
54
-# define qemu_ld_leq ldq_le_p(g2h(taddr))
55
-# define qemu_ld_beuw lduw_be_p(g2h(taddr))
56
-# define qemu_ld_beul (uint32_t)ldl_be_p(g2h(taddr))
57
-# define qemu_ld_beq ldq_be_p(g2h(taddr))
58
-# define qemu_st_b(X) stb_p(g2h(taddr), X)
59
-# define qemu_st_lew(X) stw_le_p(g2h(taddr), X)
60
-# define qemu_st_lel(X) stl_le_p(g2h(taddr), X)
61
-# define qemu_st_leq(X) stq_le_p(g2h(taddr), X)
62
-# define qemu_st_bew(X) stw_be_p(g2h(taddr), X)
63
-# define qemu_st_bel(X) stl_be_p(g2h(taddr), X)
64
-# define qemu_st_beq(X) stq_be_p(g2h(taddr), X)
65
-#endif
66
+#define qemu_ld_ub \
67
+ cpu_ldub_mmuidx_ra(env, taddr, get_mmuidx(oi), (uintptr_t)tb_ptr)
68
+#define qemu_ld_leuw \
69
+ cpu_lduw_le_mmuidx_ra(env, taddr, get_mmuidx(oi), (uintptr_t)tb_ptr)
70
+#define qemu_ld_leul \
71
+ cpu_ldl_le_mmuidx_ra(env, taddr, get_mmuidx(oi), (uintptr_t)tb_ptr)
72
+#define qemu_ld_leq \
73
+ cpu_ldq_le_mmuidx_ra(env, taddr, get_mmuidx(oi), (uintptr_t)tb_ptr)
74
+#define qemu_ld_beuw \
75
+ cpu_lduw_be_mmuidx_ra(env, taddr, get_mmuidx(oi), (uintptr_t)tb_ptr)
76
+#define qemu_ld_beul \
77
+ cpu_ldl_be_mmuidx_ra(env, taddr, get_mmuidx(oi), (uintptr_t)tb_ptr)
78
+#define qemu_ld_beq \
79
+ cpu_ldq_be_mmuidx_ra(env, taddr, get_mmuidx(oi), (uintptr_t)tb_ptr)
80
+#define qemu_st_b(X) \
81
+ cpu_stb_mmuidx_ra(env, taddr, X, get_mmuidx(oi), (uintptr_t)tb_ptr)
82
+#define qemu_st_lew(X) \
83
+ cpu_stw_le_mmuidx_ra(env, taddr, X, get_mmuidx(oi), (uintptr_t)tb_ptr)
84
+#define qemu_st_lel(X) \
85
+ cpu_stl_le_mmuidx_ra(env, taddr, X, get_mmuidx(oi), (uintptr_t)tb_ptr)
86
+#define qemu_st_leq(X) \
87
+ cpu_stq_le_mmuidx_ra(env, taddr, X, get_mmuidx(oi), (uintptr_t)tb_ptr)
88
+#define qemu_st_bew(X) \
89
+ cpu_stw_be_mmuidx_ra(env, taddr, X, get_mmuidx(oi), (uintptr_t)tb_ptr)
90
+#define qemu_st_bel(X) \
91
+ cpu_stl_be_mmuidx_ra(env, taddr, X, get_mmuidx(oi), (uintptr_t)tb_ptr)
92
+#define qemu_st_beq(X) \
93
+ cpu_stq_be_mmuidx_ra(env, taddr, X, get_mmuidx(oi), (uintptr_t)tb_ptr)
94
95
#if TCG_TARGET_REG_BITS == 64
96
# define CASE_32_64(x) \
97
--
28
--
98
2.25.1
29
2.25.1
99
30
100
31
diff view generated by jsdifflib
[PATCH 17/27] tcg/tci: Remove tci_read_r32s
[PULL 51/56] tcg/optimize: Use fold_xx_to_i for rem
1
Use explicit casts for ext32s opcodes.
1
Recognize the constant function for remainder.
2
2
3
Suggested-by: Luis Pires <luis.pires@eldorado.org.br>
3
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
4
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
---
6
---
6
tcg/tci.c | 20 ++------------------
7
tcg/optimize.c | 6 +++++-
7
1 file changed, 2 insertions(+), 18 deletions(-)
8
1 file changed, 5 insertions(+), 1 deletion(-)
8
9
9
diff --git a/tcg/tci.c b/tcg/tci.c
10
diff --git a/tcg/optimize.c b/tcg/optimize.c
10
index XXXXXXX..XXXXXXX 100644
11
index XXXXXXX..XXXXXXX 100644
11
--- a/tcg/tci.c
12
--- a/tcg/optimize.c
12
+++ b/tcg/tci.c
13
+++ b/tcg/optimize.c
13
@@ -XXX,XX +XXX,XX @@ static tcg_target_ulong tci_read_reg(const tcg_target_ulong *regs, TCGReg index)
14
@@ -XXX,XX +XXX,XX @@ static bool fold_qemu_st(OptContext *ctx, TCGOp *op)
14
return regs[index];
15
16
static bool fold_remainder(OptContext *ctx, TCGOp *op)
17
{
18
- return fold_const2(ctx, op);
19
+ if (fold_const2(ctx, op) ||
20
+ fold_xx_to_i(ctx, op, 0)) {
21
+ return true;
22
+ }
23
+ return false;
15
}
24
}
16
25
17
-#if TCG_TARGET_REG_BITS == 64
26
static bool fold_setcond(OptContext *ctx, TCGOp *op)
18
-static int32_t tci_read_reg32s(const tcg_target_ulong *regs, TCGReg index)
19
-{
20
- return (int32_t)tci_read_reg(regs, index);
21
-}
22
-#endif
23
-
24
#if TCG_TARGET_REG_BITS == 64
25
static uint64_t tci_read_reg64(const tcg_target_ulong *regs, TCGReg index)
26
{
27
@@ -XXX,XX +XXX,XX @@ static uint64_t tci_read_r64(const tcg_target_ulong *regs,
28
return tci_uint64(tci_read_r(regs, tb_ptr), low);
29
}
30
#elif TCG_TARGET_REG_BITS == 64
31
-/* Read indexed register (32 bit signed) from bytecode. */
32
-static int32_t tci_read_r32s(const tcg_target_ulong *regs,
33
- const uint8_t **tb_ptr)
34
-{
35
- int32_t value = tci_read_reg32s(regs, **tb_ptr);
36
- *tb_ptr += 1;
37
- return value;
38
-}
39
-
40
/* Read indexed register (64 bit) from bytecode. */
41
static uint64_t tci_read_r64(const tcg_target_ulong *regs,
42
const uint8_t **tb_ptr)
43
@@ -XXX,XX +XXX,XX @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
44
#endif
45
case INDEX_op_ext_i32_i64:
46
t0 = *tb_ptr++;
47
- t1 = tci_read_r32s(regs, &tb_ptr);
48
- tci_write_reg(regs, t0, t1);
49
+ t1 = tci_read_r(regs, &tb_ptr);
50
+ tci_write_reg(regs, t0, (int32_t)t1);
51
break;
52
#if TCG_TARGET_HAS_ext32u_i64
53
case INDEX_op_ext32u_i64:
54
--
27
--
55
2.25.1
28
2.25.1
56
29
57
30
diff view generated by jsdifflib
[PATCH 02/27] tcg/aarch64: Fix I3617_CMLE0
[PULL 52/56] tcg/optimize: Optimize sign extensions
1
Fix a typo in the encodeing of the cmle (zero) instruction.
1
Certain targets, like riscv, produce signed 32-bit results.
2
2
This can lead to lots of redundant extensions as values are
3
Fixes: 14e4c1e2355 ("tcg/aarch64: Add vector operations")
3
manipulated.
4
5
Begin by tracking only the obvious sign-extensions, and
6
converting them to simple copies when possible.
7
8
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
9
Reviewed-by: Luis Pires <luis.pires@eldorado.org.br>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
---
11
---
6
tcg/aarch64/tcg-target.c.inc | 2 +-
12
tcg/optimize.c | 123 ++++++++++++++++++++++++++++++++++++++++---------
7
1 file changed, 1 insertion(+), 1 deletion(-)
13
1 file changed, 102 insertions(+), 21 deletions(-)
8
14
9
diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc
15
diff --git a/tcg/optimize.c b/tcg/optimize.c
10
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
11
--- a/tcg/aarch64/tcg-target.c.inc
17
--- a/tcg/optimize.c
12
+++ b/tcg/aarch64/tcg-target.c.inc
18
+++ b/tcg/optimize.c
13
@@ -XXX,XX +XXX,XX @@ typedef enum {
19
@@ -XXX,XX +XXX,XX @@ typedef struct TempOptInfo {
14
I3617_CMEQ0 = 0x0e209800,
20
TCGTemp *next_copy;
15
I3617_CMLT0 = 0x0e20a800,
21
uint64_t val;
16
I3617_CMGE0 = 0x2e208800,
22
uint64_t z_mask; /* mask bit is 0 if and only if value bit is 0 */
17
- I3617_CMLE0 = 0x2e20a800,
23
+ uint64_t s_mask; /* a left-aligned mask of clrsb(value) bits. */
18
+ I3617_CMLE0 = 0x2e209800,
24
} TempOptInfo;
19
I3617_NOT = 0x2e205800,
25
20
I3617_ABS = 0x0e20b800,
26
typedef struct OptContext {
21
I3617_NEG = 0x2e20b800,
27
@@ -XXX,XX +XXX,XX @@ typedef struct OptContext {
28
/* In flight values from optimization. */
29
uint64_t a_mask; /* mask bit is 0 iff value identical to first input */
30
uint64_t z_mask; /* mask bit is 0 iff value bit is 0 */
31
+ uint64_t s_mask; /* mask of clrsb(value) bits */
32
TCGType type;
33
} OptContext;
34
35
+/* Calculate the smask for a specific value. */
36
+static uint64_t smask_from_value(uint64_t value)
37
+{
38
+ int rep = clrsb64(value);
39
+ return ~(~0ull >> rep);
40
+}
41
+
42
+/*
43
+ * Calculate the smask for a given set of known-zeros.
44
+ * If there are lots of zeros on the left, we can consider the remainder
45
+ * an unsigned field, and thus the corresponding signed field is one bit
46
+ * larger.
47
+ */
48
+static uint64_t smask_from_zmask(uint64_t zmask)
49
+{
50
+ /*
51
+ * Only the 0 bits are significant for zmask, thus the msb itself
52
+ * must be zero, else we have no sign information.
53
+ */
54
+ int rep = clz64(zmask);
55
+ if (rep == 0) {
56
+ return 0;
57
+ }
58
+ rep -= 1;
59
+ return ~(~0ull >> rep);
60
+}
61
+
62
static inline TempOptInfo *ts_info(TCGTemp *ts)
63
{
64
return ts->state_ptr;
65
@@ -XXX,XX +XXX,XX @@ static void reset_ts(TCGTemp *ts)
66
ti->prev_copy = ts;
67
ti->is_const = false;
68
ti->z_mask = -1;
69
+ ti->s_mask = 0;
70
}
71
72
static void reset_temp(TCGArg arg)
73
@@ -XXX,XX +XXX,XX @@ static void init_ts_info(OptContext *ctx, TCGTemp *ts)
74
ti->is_const = true;
75
ti->val = ts->val;
76
ti->z_mask = ts->val;
77
+ ti->s_mask = smask_from_value(ts->val);
78
} else {
79
ti->is_const = false;
80
ti->z_mask = -1;
81
+ ti->s_mask = 0;
82
}
83
}
84
85
@@ -XXX,XX +XXX,XX @@ static bool tcg_opt_gen_mov(OptContext *ctx, TCGOp *op, TCGArg dst, TCGArg src)
86
op->args[1] = src;
87
88
di->z_mask = si->z_mask;
89
+ di->s_mask = si->s_mask;
90
91
if (src_ts->type == dst_ts->type) {
92
TempOptInfo *ni = ts_info(si->next_copy);
93
@@ -XXX,XX +XXX,XX @@ static void finish_folding(OptContext *ctx, TCGOp *op)
94
95
nb_oargs = def->nb_oargs;
96
for (i = 0; i < nb_oargs; i++) {
97
- reset_temp(op->args[i]);
98
+ TCGTemp *ts = arg_temp(op->args[i]);
99
+ reset_ts(ts);
100
/*
101
- * Save the corresponding known-zero bits mask for the
102
+ * Save the corresponding known-zero/sign bits mask for the
103
* first output argument (only one supported so far).
104
*/
105
if (i == 0) {
106
- arg_info(op->args[i])->z_mask = ctx->z_mask;
107
+ ts_info(ts)->z_mask = ctx->z_mask;
108
+ ts_info(ts)->s_mask = ctx->s_mask;
109
}
110
}
111
}
112
@@ -XXX,XX +XXX,XX @@ static bool fold_masks(OptContext *ctx, TCGOp *op)
113
{
114
uint64_t a_mask = ctx->a_mask;
115
uint64_t z_mask = ctx->z_mask;
116
+ uint64_t s_mask = ctx->s_mask;
117
118
/*
119
* 32-bit ops generate 32-bit results, which for the purpose of
120
@@ -XXX,XX +XXX,XX @@ static bool fold_masks(OptContext *ctx, TCGOp *op)
121
if (ctx->type == TCG_TYPE_I32) {
122
a_mask = (int32_t)a_mask;
123
z_mask = (int32_t)z_mask;
124
+ s_mask |= MAKE_64BIT_MASK(32, 32);
125
ctx->z_mask = z_mask;
126
+ ctx->s_mask = s_mask;
127
}
128
129
if (z_mask == 0) {
130
@@ -XXX,XX +XXX,XX @@ static bool fold_brcond2(OptContext *ctx, TCGOp *op)
131
132
static bool fold_bswap(OptContext *ctx, TCGOp *op)
133
{
134
- uint64_t z_mask, sign;
135
+ uint64_t z_mask, s_mask, sign;
136
137
if (arg_is_const(op->args[1])) {
138
uint64_t t = arg_info(op->args[1])->val;
139
@@ -XXX,XX +XXX,XX @@ static bool fold_bswap(OptContext *ctx, TCGOp *op)
140
}
141
142
z_mask = arg_info(op->args[1])->z_mask;
143
+
144
switch (op->opc) {
145
case INDEX_op_bswap16_i32:
146
case INDEX_op_bswap16_i64:
147
@@ -XXX,XX +XXX,XX @@ static bool fold_bswap(OptContext *ctx, TCGOp *op)
148
default:
149
g_assert_not_reached();
150
}
151
+ s_mask = smask_from_zmask(z_mask);
152
153
switch (op->args[2] & (TCG_BSWAP_OZ | TCG_BSWAP_OS)) {
154
case TCG_BSWAP_OZ:
155
@@ -XXX,XX +XXX,XX @@ static bool fold_bswap(OptContext *ctx, TCGOp *op)
156
/* If the sign bit may be 1, force all the bits above to 1. */
157
if (z_mask & sign) {
158
z_mask |= sign;
159
+ s_mask = sign << 1;
160
}
161
break;
162
default:
163
/* The high bits are undefined: force all bits above the sign to 1. */
164
z_mask |= sign << 1;
165
+ s_mask = 0;
166
break;
167
}
168
ctx->z_mask = z_mask;
169
+ ctx->s_mask = s_mask;
170
171
return fold_masks(ctx, op);
172
}
173
@@ -XXX,XX +XXX,XX @@ static bool fold_eqv(OptContext *ctx, TCGOp *op)
174
static bool fold_extract(OptContext *ctx, TCGOp *op)
175
{
176
uint64_t z_mask_old, z_mask;
177
+ int pos = op->args[2];
178
+ int len = op->args[3];
179
180
if (arg_is_const(op->args[1])) {
181
uint64_t t;
182
183
t = arg_info(op->args[1])->val;
184
- t = extract64(t, op->args[2], op->args[3]);
185
+ t = extract64(t, pos, len);
186
return tcg_opt_gen_movi(ctx, op, op->args[0], t);
187
}
188
189
z_mask_old = arg_info(op->args[1])->z_mask;
190
- z_mask = extract64(z_mask_old, op->args[2], op->args[3]);
191
- if (op->args[2] == 0) {
192
+ z_mask = extract64(z_mask_old, pos, len);
193
+ if (pos == 0) {
194
ctx->a_mask = z_mask_old ^ z_mask;
195
}
196
ctx->z_mask = z_mask;
197
+ ctx->s_mask = smask_from_zmask(z_mask);
198
199
return fold_masks(ctx, op);
200
}
201
@@ -XXX,XX +XXX,XX @@ static bool fold_extract2(OptContext *ctx, TCGOp *op)
202
203
static bool fold_exts(OptContext *ctx, TCGOp *op)
204
{
205
- uint64_t z_mask_old, z_mask, sign;
206
+ uint64_t s_mask_old, s_mask, z_mask, sign;
207
bool type_change = false;
208
209
if (fold_const1(ctx, op)) {
210
return true;
211
}
212
213
- z_mask_old = z_mask = arg_info(op->args[1])->z_mask;
214
+ z_mask = arg_info(op->args[1])->z_mask;
215
+ s_mask = arg_info(op->args[1])->s_mask;
216
+ s_mask_old = s_mask;
217
218
switch (op->opc) {
219
CASE_OP_32_64(ext8s):
220
@@ -XXX,XX +XXX,XX @@ static bool fold_exts(OptContext *ctx, TCGOp *op)
221
222
if (z_mask & sign) {
223
z_mask |= sign;
224
- } else if (!type_change) {
225
- ctx->a_mask = z_mask_old ^ z_mask;
226
}
227
+ s_mask |= sign << 1;
228
+
229
ctx->z_mask = z_mask;
230
+ ctx->s_mask = s_mask;
231
+ if (!type_change) {
232
+ ctx->a_mask = s_mask & ~s_mask_old;
233
+ }
234
235
return fold_masks(ctx, op);
236
}
237
@@ -XXX,XX +XXX,XX @@ static bool fold_extu(OptContext *ctx, TCGOp *op)
238
}
239
240
ctx->z_mask = z_mask;
241
+ ctx->s_mask = smask_from_zmask(z_mask);
242
if (!type_change) {
243
ctx->a_mask = z_mask_old ^ z_mask;
244
}
245
@@ -XXX,XX +XXX,XX @@ static bool fold_qemu_ld(OptContext *ctx, TCGOp *op)
246
MemOp mop = get_memop(oi);
247
int width = 8 * memop_size(mop);
248
249
- if (!(mop & MO_SIGN) && width < 64) {
250
- ctx->z_mask = MAKE_64BIT_MASK(0, width);
251
+ if (width < 64) {
252
+ ctx->s_mask = MAKE_64BIT_MASK(width, 64 - width);
253
+ if (!(mop & MO_SIGN)) {
254
+ ctx->z_mask = MAKE_64BIT_MASK(0, width);
255
+ ctx->s_mask <<= 1;
256
+ }
257
}
258
259
/* Opcodes that touch guest memory stop the mb optimization. */
260
@@ -XXX,XX +XXX,XX @@ static bool fold_setcond2(OptContext *ctx, TCGOp *op)
261
262
static bool fold_sextract(OptContext *ctx, TCGOp *op)
263
{
264
- int64_t z_mask_old, z_mask;
265
+ uint64_t z_mask, s_mask, s_mask_old;
266
+ int pos = op->args[2];
267
+ int len = op->args[3];
268
269
if (arg_is_const(op->args[1])) {
270
uint64_t t;
271
272
t = arg_info(op->args[1])->val;
273
- t = sextract64(t, op->args[2], op->args[3]);
274
+ t = sextract64(t, pos, len);
275
return tcg_opt_gen_movi(ctx, op, op->args[0], t);
276
}
277
278
- z_mask_old = arg_info(op->args[1])->z_mask;
279
- z_mask = sextract64(z_mask_old, op->args[2], op->args[3]);
280
- if (op->args[2] == 0 && z_mask >= 0) {
281
- ctx->a_mask = z_mask_old ^ z_mask;
282
- }
283
+ z_mask = arg_info(op->args[1])->z_mask;
284
+ z_mask = sextract64(z_mask, pos, len);
285
ctx->z_mask = z_mask;
286
287
+ s_mask_old = arg_info(op->args[1])->s_mask;
288
+ s_mask = sextract64(s_mask_old, pos, len);
289
+ s_mask |= MAKE_64BIT_MASK(len, 64 - len);
290
+ ctx->s_mask = s_mask;
291
+
292
+ if (pos == 0) {
293
+ ctx->a_mask = s_mask & ~s_mask_old;
294
+ }
295
+
296
return fold_masks(ctx, op);
297
}
298
299
@@ -XXX,XX +XXX,XX @@ static bool fold_tcg_ld(OptContext *ctx, TCGOp *op)
300
{
301
/* We can't do any folding with a load, but we can record bits. */
302
switch (op->opc) {
303
+ CASE_OP_32_64(ld8s):
304
+ ctx->s_mask = MAKE_64BIT_MASK(8, 56);
305
+ break;
306
CASE_OP_32_64(ld8u):
307
ctx->z_mask = MAKE_64BIT_MASK(0, 8);
308
+ ctx->s_mask = MAKE_64BIT_MASK(9, 55);
309
+ break;
310
+ CASE_OP_32_64(ld16s):
311
+ ctx->s_mask = MAKE_64BIT_MASK(16, 48);
312
break;
313
CASE_OP_32_64(ld16u):
314
ctx->z_mask = MAKE_64BIT_MASK(0, 16);
315
+ ctx->s_mask = MAKE_64BIT_MASK(17, 47);
316
+ break;
317
+ case INDEX_op_ld32s_i64:
318
+ ctx->s_mask = MAKE_64BIT_MASK(32, 32);
319
break;
320
case INDEX_op_ld32u_i64:
321
ctx->z_mask = MAKE_64BIT_MASK(0, 32);
322
+ ctx->s_mask = MAKE_64BIT_MASK(33, 31);
323
break;
324
default:
325
g_assert_not_reached();
326
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
327
ctx.type = TCG_TYPE_I32;
328
}
329
330
- /* Assume all bits affected, and no bits known zero. */
331
+ /* Assume all bits affected, no bits known zero, no sign reps. */
332
ctx.a_mask = -1;
333
ctx.z_mask = -1;
334
+ ctx.s_mask = 0;
335
336
/*
337
* Process each opcode.
338
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
339
case INDEX_op_extrh_i64_i32:
340
done = fold_extu(&ctx, op);
341
break;
342
+ CASE_OP_32_64(ld8s):
343
CASE_OP_32_64(ld8u):
344
+ CASE_OP_32_64(ld16s):
345
CASE_OP_32_64(ld16u):
346
+ case INDEX_op_ld32s_i64:
347
case INDEX_op_ld32u_i64:
348
done = fold_tcg_ld(&ctx, op);
349
break;
22
--
350
--
23
2.25.1
351
2.25.1
24
352
25
353
diff view generated by jsdifflib
[PATCH 12/27] tcg/tci: Remove tci_read_r8
[PULL 53/56] tcg/optimize: Propagate sign info for logical operations
1
Use explicit casts for ext8u opcodes, and allow truncation
1
Sign repetitions are perforce all identical, whether they are 1 or 0.
2
to happen with the store for st8 opcodes.
2
Bitwise operations preserve the relative quantity of the repetitions.
3
3
4
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
5
Reviewed-by: Luis Pires <luis.pires@eldorado.org.br>
4
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
6
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
---
8
---
7
tcg/tci.c | 23 +++++------------------
9
tcg/optimize.c | 29 +++++++++++++++++++++++++++++
8
1 file changed, 5 insertions(+), 18 deletions(-)
10
1 file changed, 29 insertions(+)
9
11
10
diff --git a/tcg/tci.c b/tcg/tci.c
12
diff --git a/tcg/optimize.c b/tcg/optimize.c
11
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
12
--- a/tcg/tci.c
14
--- a/tcg/optimize.c
13
+++ b/tcg/tci.c
15
+++ b/tcg/optimize.c
14
@@ -XXX,XX +XXX,XX @@ static int32_t tci_read_reg32s(const tcg_target_ulong *regs, TCGReg index)
16
@@ -XXX,XX +XXX,XX @@ static bool fold_and(OptContext *ctx, TCGOp *op)
17
z2 = arg_info(op->args[2])->z_mask;
18
ctx->z_mask = z1 & z2;
19
20
+ /*
21
+ * Sign repetitions are perforce all identical, whether they are 1 or 0.
22
+ * Bitwise operations preserve the relative quantity of the repetitions.
23
+ */
24
+ ctx->s_mask = arg_info(op->args[1])->s_mask
25
+ & arg_info(op->args[2])->s_mask;
26
+
27
/*
28
* Known-zeros does not imply known-ones. Therefore unless
29
* arg2 is constant, we can't infer affected bits from it.
30
@@ -XXX,XX +XXX,XX @@ static bool fold_andc(OptContext *ctx, TCGOp *op)
31
}
32
ctx->z_mask = z1;
33
34
+ ctx->s_mask = arg_info(op->args[1])->s_mask
35
+ & arg_info(op->args[2])->s_mask;
36
return fold_masks(ctx, op);
15
}
37
}
16
#endif
38
17
39
@@ -XXX,XX +XXX,XX @@ static bool fold_eqv(OptContext *ctx, TCGOp *op)
18
-static uint8_t tci_read_reg8(const tcg_target_ulong *regs, TCGReg index)
40
fold_xi_to_not(ctx, op, 0)) {
19
-{
41
return true;
20
- return (uint8_t)tci_read_reg(regs, index);
42
}
21
-}
43
+
22
-
44
+ ctx->s_mask = arg_info(op->args[1])->s_mask
23
static uint16_t tci_read_reg16(const tcg_target_ulong *regs, TCGReg index)
45
+ & arg_info(op->args[2])->s_mask;
24
{
46
return false;
25
return (uint16_t)tci_read_reg(regs, index);
26
@@ -XXX,XX +XXX,XX @@ tci_read_r(const tcg_target_ulong *regs, const uint8_t **tb_ptr)
27
return value;
28
}
47
}
29
48
30
-/* Read indexed register (8 bit) from bytecode. */
49
@@ -XXX,XX +XXX,XX @@ static bool fold_movcond(OptContext *ctx, TCGOp *op)
31
-static uint8_t tci_read_r8(const tcg_target_ulong *regs, const uint8_t **tb_ptr)
50
32
-{
51
ctx->z_mask = arg_info(op->args[3])->z_mask
33
- uint8_t value = tci_read_reg8(regs, **tb_ptr);
52
| arg_info(op->args[4])->z_mask;
34
- *tb_ptr += 1;
53
+ ctx->s_mask = arg_info(op->args[3])->s_mask
35
- return value;
54
+ & arg_info(op->args[4])->s_mask;
36
-}
55
37
-
56
if (arg_is_const(op->args[3]) && arg_is_const(op->args[4])) {
38
#if TCG_TARGET_HAS_ext8s_i32 || TCG_TARGET_HAS_ext8s_i64
57
uint64_t tv = arg_info(op->args[3])->val;
39
/* Read indexed register (8 bit signed) from bytecode. */
58
@@ -XXX,XX +XXX,XX @@ static bool fold_nand(OptContext *ctx, TCGOp *op)
40
static int8_t tci_read_r8s(const tcg_target_ulong *regs, const uint8_t **tb_ptr)
59
fold_xi_to_not(ctx, op, -1)) {
41
@@ -XXX,XX +XXX,XX @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
60
return true;
42
tci_write_reg(regs, t0, *(uint32_t *)(t1 + t2));
61
}
43
break;
62
+
44
CASE_32_64(st8)
63
+ ctx->s_mask = arg_info(op->args[1])->s_mask
45
- t0 = tci_read_r8(regs, &tb_ptr);
64
+ & arg_info(op->args[2])->s_mask;
46
+ t0 = tci_read_r(regs, &tb_ptr);
65
return false;
47
t1 = tci_read_r(regs, &tb_ptr);
66
}
48
t2 = tci_read_s32(&tb_ptr);
67
49
*(uint8_t *)(t1 + t2) = t0;
68
@@ -XXX,XX +XXX,XX @@ static bool fold_nor(OptContext *ctx, TCGOp *op)
50
@@ -XXX,XX +XXX,XX @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
69
fold_xi_to_not(ctx, op, 0)) {
51
#if TCG_TARGET_HAS_ext8u_i32
70
return true;
52
case INDEX_op_ext8u_i32:
71
}
53
t0 = *tb_ptr++;
72
+
54
- t1 = tci_read_r8(regs, &tb_ptr);
73
+ ctx->s_mask = arg_info(op->args[1])->s_mask
55
- tci_write_reg(regs, t0, t1);
74
+ & arg_info(op->args[2])->s_mask;
56
+ t1 = tci_read_r(regs, &tb_ptr);
75
return false;
57
+ tci_write_reg(regs, t0, (uint8_t)t1);
76
}
58
break;
77
59
#endif
78
@@ -XXX,XX +XXX,XX @@ static bool fold_not(OptContext *ctx, TCGOp *op)
60
#if TCG_TARGET_HAS_ext16u_i32
79
return true;
61
@@ -XXX,XX +XXX,XX @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
80
}
62
#if TCG_TARGET_HAS_ext8u_i64
81
63
case INDEX_op_ext8u_i64:
82
+ ctx->s_mask = arg_info(op->args[1])->s_mask;
64
t0 = *tb_ptr++;
83
+
65
- t1 = tci_read_r8(regs, &tb_ptr);
84
/* Because of fold_to_not, we want to always return true, via finish. */
66
- tci_write_reg(regs, t0, t1);
85
finish_folding(ctx, op);
67
+ t1 = tci_read_r(regs, &tb_ptr);
86
return true;
68
+ tci_write_reg(regs, t0, (uint8_t)t1);
87
@@ -XXX,XX +XXX,XX @@ static bool fold_or(OptContext *ctx, TCGOp *op)
69
break;
88
70
#endif
89
ctx->z_mask = arg_info(op->args[1])->z_mask
71
#if TCG_TARGET_HAS_ext8s_i64
90
| arg_info(op->args[2])->z_mask;
91
+ ctx->s_mask = arg_info(op->args[1])->s_mask
92
+ & arg_info(op->args[2])->s_mask;
93
return fold_masks(ctx, op);
94
}
95
96
@@ -XXX,XX +XXX,XX @@ static bool fold_orc(OptContext *ctx, TCGOp *op)
97
fold_ix_to_not(ctx, op, 0)) {
98
return true;
99
}
100
+
101
+ ctx->s_mask = arg_info(op->args[1])->s_mask
102
+ & arg_info(op->args[2])->s_mask;
103
return false;
104
}
105
106
@@ -XXX,XX +XXX,XX @@ static bool fold_xor(OptContext *ctx, TCGOp *op)
107
108
ctx->z_mask = arg_info(op->args[1])->z_mask
109
| arg_info(op->args[2])->z_mask;
110
+ ctx->s_mask = arg_info(op->args[1])->s_mask
111
+ & arg_info(op->args[2])->s_mask;
112
return fold_masks(ctx, op);
113
}
114
72
--
115
--
73
2.25.1
116
2.25.1
74
117
75
118
diff view generated by jsdifflib
[PATCH 01/27] tcg/aarch64: Fix constant subtraction in tcg_out_addsub2
[PULL 54/56] tcg/optimize: Propagate sign info for setcond
1
An hppa guest executing
1
The result is either 0 or 1, which means that we have
2
a 2 bit signed result, and thus 62 bits of sign.
3
For clarity, use the smask_from_zmask function.
2
4
3
0x000000000000e05c: ldil L%10000,r4
5
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
4
0x000000000000e060: ldo 0(r4),r4
6
Reviewed-by: Luis Pires <luis.pires@eldorado.org.br>
5
0x000000000000e064: sub r3,r4,sp
6
7
produces
8
9
---- 000000000000e064 000000000000e068
10
sub2_i32 tmp0,tmp4,r3,$0x1,$0x10000,$0x0
11
12
after folding and constant propagation. Then we hit
13
14
tcg-target.c.inc:640: tcg_out_insn_3401: Assertion `aimm <= 0xfff' failed.
15
16
because aimm is in fact -16, but unsigned.
17
18
The ((bl < 0) ^ sub) condition which negates bl is incorrect and will
19
always lead to this abort. If the constant is positive, sub will make
20
it negative; if the constant is negative, sub will keep it negative.
21
22
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
23
---
8
---
24
tcg/aarch64/tcg-target.c.inc | 16 +++++++++-------
9
tcg/optimize.c | 2 ++
25
1 file changed, 9 insertions(+), 7 deletions(-)
10
1 file changed, 2 insertions(+)
26
11
27
diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc
12
diff --git a/tcg/optimize.c b/tcg/optimize.c
28
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
29
--- a/tcg/aarch64/tcg-target.c.inc
14
--- a/tcg/optimize.c
30
+++ b/tcg/aarch64/tcg-target.c.inc
15
+++ b/tcg/optimize.c
31
@@ -XXX,XX +XXX,XX @@ static void tcg_out_addsubi(TCGContext *s, int ext, TCGReg rd,
16
@@ -XXX,XX +XXX,XX @@ static bool fold_setcond(OptContext *ctx, TCGOp *op)
32
}
17
}
18
19
ctx->z_mask = 1;
20
+ ctx->s_mask = smask_from_zmask(1);
21
return false;
33
}
22
}
34
23
35
-static inline void tcg_out_addsub2(TCGContext *s, TCGType ext, TCGReg rl,
24
@@ -XXX,XX +XXX,XX @@ static bool fold_setcond2(OptContext *ctx, TCGOp *op)
36
- TCGReg rh, TCGReg al, TCGReg ah,
37
- tcg_target_long bl, tcg_target_long bh,
38
- bool const_bl, bool const_bh, bool sub)
39
+static void tcg_out_addsub2(TCGContext *s, TCGType ext, TCGReg rl,
40
+ TCGReg rh, TCGReg al, TCGReg ah,
41
+ tcg_target_long bl, tcg_target_long bh,
42
+ bool const_bl, bool const_bh, bool sub)
43
{
44
TCGReg orig_rl = rl;
45
AArch64Insn insn;
46
@@ -XXX,XX +XXX,XX @@ static inline void tcg_out_addsub2(TCGContext *s, TCGType ext, TCGReg rl,
47
}
25
}
48
26
49
if (const_bl) {
27
ctx->z_mask = 1;
50
- insn = I3401_ADDSI;
28
+ ctx->s_mask = smask_from_zmask(1);
51
- if ((bl < 0) ^ sub) {
29
return false;
52
- insn = I3401_SUBSI;
30
53
+ if (bl < 0) {
31
do_setcond_const:
54
bl = -bl;
55
+ insn = sub ? I3401_ADDSI : I3401_SUBSI;
56
+ } else {
57
+ insn = sub ? I3401_SUBSI : I3401_ADDSI;
58
}
59
+
60
if (unlikely(al == TCG_REG_XZR)) {
61
/* ??? We want to allow al to be zero for the benefit of
62
negation via subtraction. However, that leaves open the
63
--
32
--
64
2.25.1
33
2.25.1
65
34
66
35
diff view generated by jsdifflib
[PATCH 07/27] tcg/tci: Merge identical cases in generation (arithmetic opcodes)
[PULL 55/56] tcg/optimize: Propagate sign info for bit counting
1
Use CASE_32_64 and CASE_64 to reduce ifdefs and merge
1
The results are generally 6 bit unsigned values, though
2
cases that are identical between 32-bit and 64-bit hosts.
2
the count leading and trailing bits may produce any value
3
for a zero input.
3
4
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
5
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
6
Reviewed-by: Luis Pires <luis.pires@eldorado.org.br>
6
Message-Id: <20210217202036.1724901-5-richard.henderson@linaro.org>
7
[PMD: Split patch as 1/5]
8
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
Message-Id: <20210218232840.1760806-2-f4bug@amsat.org>
10
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
11
---
8
---
12
tcg/tci/tcg-target.c.inc | 85 +++++++++++++++++-----------------------
9
tcg/optimize.c | 3 ++-
13
1 file changed, 37 insertions(+), 48 deletions(-)
10
1 file changed, 2 insertions(+), 1 deletion(-)
14
11
15
diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
12
diff --git a/tcg/optimize.c b/tcg/optimize.c
16
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
17
--- a/tcg/tci/tcg-target.c.inc
14
--- a/tcg/optimize.c
18
+++ b/tcg/tci/tcg-target.c.inc
15
+++ b/tcg/optimize.c
19
@@ -XXX,XX +XXX,XX @@ static inline void tcg_out_call(TCGContext *s, const tcg_insn_unit *arg)
16
@@ -XXX,XX +XXX,XX @@ static bool fold_count_zeros(OptContext *ctx, TCGOp *op)
20
old_code_ptr[1] = s->code_ptr - old_code_ptr;
17
g_assert_not_reached();
18
}
19
ctx->z_mask = arg_info(op->args[2])->z_mask | z_mask;
20
-
21
+ ctx->s_mask = smask_from_zmask(ctx->z_mask);
22
return false;
21
}
23
}
22
24
23
+#if TCG_TARGET_REG_BITS == 64
25
@@ -XXX,XX +XXX,XX @@ static bool fold_ctpop(OptContext *ctx, TCGOp *op)
24
+# define CASE_32_64(x) \
26
default:
25
+ case glue(glue(INDEX_op_, x), _i64): \
27
g_assert_not_reached();
26
+ case glue(glue(INDEX_op_, x), _i32):
28
}
27
+# define CASE_64(x) \
29
+ ctx->s_mask = smask_from_zmask(ctx->z_mask);
28
+ case glue(glue(INDEX_op_, x), _i64):
30
return false;
29
+#else
31
}
30
+# define CASE_32_64(x) \
32
31
+ case glue(glue(INDEX_op_, x), _i32):
32
+# define CASE_64(x)
33
+#endif
34
+
35
static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
36
const int *const_args)
37
{
38
@@ -XXX,XX +XXX,XX @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
39
case INDEX_op_exit_tb:
40
tcg_out64(s, args[0]);
41
break;
42
+
43
case INDEX_op_goto_tb:
44
if (s->tb_jmp_insn_offset) {
45
/* Direct jump method. */
46
@@ -XXX,XX +XXX,XX @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
47
tcg_debug_assert(args[2] == (int32_t)args[2]);
48
tcg_out32(s, args[2]);
49
break;
50
- case INDEX_op_add_i32:
51
- case INDEX_op_sub_i32:
52
- case INDEX_op_mul_i32:
53
- case INDEX_op_and_i32:
54
- case INDEX_op_andc_i32: /* Optional (TCG_TARGET_HAS_andc_i32). */
55
- case INDEX_op_eqv_i32: /* Optional (TCG_TARGET_HAS_eqv_i32). */
56
- case INDEX_op_nand_i32: /* Optional (TCG_TARGET_HAS_nand_i32). */
57
- case INDEX_op_nor_i32: /* Optional (TCG_TARGET_HAS_nor_i32). */
58
- case INDEX_op_or_i32:
59
- case INDEX_op_orc_i32: /* Optional (TCG_TARGET_HAS_orc_i32). */
60
- case INDEX_op_xor_i32:
61
- case INDEX_op_shl_i32:
62
- case INDEX_op_shr_i32:
63
- case INDEX_op_sar_i32:
64
- case INDEX_op_rotl_i32: /* Optional (TCG_TARGET_HAS_rot_i32). */
65
- case INDEX_op_rotr_i32: /* Optional (TCG_TARGET_HAS_rot_i32). */
66
+
67
+ CASE_32_64(add)
68
+ CASE_32_64(sub)
69
+ CASE_32_64(mul)
70
+ CASE_32_64(and)
71
+ CASE_32_64(or)
72
+ CASE_32_64(xor)
73
+ CASE_32_64(andc) /* Optional (TCG_TARGET_HAS_andc_*). */
74
+ CASE_32_64(orc) /* Optional (TCG_TARGET_HAS_orc_*). */
75
+ CASE_32_64(eqv) /* Optional (TCG_TARGET_HAS_eqv_*). */
76
+ CASE_32_64(nand) /* Optional (TCG_TARGET_HAS_nand_*). */
77
+ CASE_32_64(nor) /* Optional (TCG_TARGET_HAS_nor_*). */
78
+ CASE_32_64(shl)
79
+ CASE_32_64(shr)
80
+ CASE_32_64(sar)
81
+ CASE_32_64(rotl) /* Optional (TCG_TARGET_HAS_rot_*). */
82
+ CASE_32_64(rotr) /* Optional (TCG_TARGET_HAS_rot_*). */
83
+ CASE_32_64(div) /* Optional (TCG_TARGET_HAS_div_*). */
84
+ CASE_32_64(divu) /* Optional (TCG_TARGET_HAS_div_*). */
85
+ CASE_32_64(rem) /* Optional (TCG_TARGET_HAS_div_*). */
86
+ CASE_32_64(remu) /* Optional (TCG_TARGET_HAS_div_*). */
87
tcg_out_r(s, args[0]);
88
tcg_out_r(s, args[1]);
89
tcg_out_r(s, args[2]);
90
@@ -XXX,XX +XXX,XX @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
91
break;
92
93
#if TCG_TARGET_REG_BITS == 64
94
- case INDEX_op_add_i64:
95
- case INDEX_op_sub_i64:
96
- case INDEX_op_mul_i64:
97
- case INDEX_op_and_i64:
98
- case INDEX_op_andc_i64: /* Optional (TCG_TARGET_HAS_andc_i64). */
99
- case INDEX_op_eqv_i64: /* Optional (TCG_TARGET_HAS_eqv_i64). */
100
- case INDEX_op_nand_i64: /* Optional (TCG_TARGET_HAS_nand_i64). */
101
- case INDEX_op_nor_i64: /* Optional (TCG_TARGET_HAS_nor_i64). */
102
- case INDEX_op_or_i64:
103
- case INDEX_op_orc_i64: /* Optional (TCG_TARGET_HAS_orc_i64). */
104
- case INDEX_op_xor_i64:
105
- case INDEX_op_shl_i64:
106
- case INDEX_op_shr_i64:
107
- case INDEX_op_sar_i64:
108
- case INDEX_op_rotl_i64: /* Optional (TCG_TARGET_HAS_rot_i64). */
109
- case INDEX_op_rotr_i64: /* Optional (TCG_TARGET_HAS_rot_i64). */
110
- case INDEX_op_div_i64: /* Optional (TCG_TARGET_HAS_div_i64). */
111
- case INDEX_op_divu_i64: /* Optional (TCG_TARGET_HAS_div_i64). */
112
- case INDEX_op_rem_i64: /* Optional (TCG_TARGET_HAS_div_i64). */
113
- case INDEX_op_remu_i64: /* Optional (TCG_TARGET_HAS_div_i64). */
114
- tcg_out_r(s, args[0]);
115
- tcg_out_r(s, args[1]);
116
- tcg_out_r(s, args[2]);
117
- break;
118
case INDEX_op_deposit_i64: /* Optional (TCG_TARGET_HAS_deposit_i64). */
119
tcg_out_r(s, args[0]);
120
tcg_out_r(s, args[1]);
121
@@ -XXX,XX +XXX,XX @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
122
tcg_out_r(s, args[0]);
123
tcg_out_r(s, args[1]);
124
break;
125
- case INDEX_op_div_i32: /* Optional (TCG_TARGET_HAS_div_i32). */
126
- case INDEX_op_divu_i32: /* Optional (TCG_TARGET_HAS_div_i32). */
127
- case INDEX_op_rem_i32: /* Optional (TCG_TARGET_HAS_div_i32). */
128
- case INDEX_op_remu_i32: /* Optional (TCG_TARGET_HAS_div_i32). */
129
- tcg_out_r(s, args[0]);
130
- tcg_out_r(s, args[1]);
131
- tcg_out_r(s, args[2]);
132
- break;
133
+
134
#if TCG_TARGET_REG_BITS == 32
135
case INDEX_op_add2_i32:
136
case INDEX_op_sub2_i32:
137
@@ -XXX,XX +XXX,XX @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
138
}
139
tcg_out_i(s, *args++);
140
break;
141
+
142
case INDEX_op_mb:
143
break;
144
+
145
case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
146
case INDEX_op_mov_i64:
147
case INDEX_op_call: /* Always emitted via tcg_out_call. */
148
--
33
--
149
2.25.1
34
2.25.1
150
35
151
36
diff view generated by jsdifflib
[PATCH 27/27] accel/tcg: Precompute curr_cflags into cpu->tcg_cflags
[PULL 56/56] tcg/optimize: Propagate sign info for shifting
1
The primary motivation is to remove a dozen insns along
1
For constant shifts, we can simply shift the s_mask.
2
the fast-path in tb_lookup. As a byproduct, this allows
3
us to completely remove parallel_cpus.
4
2
3
For variable shifts, we know that sar does not reduce
4
the s_mask, which helps for sequences like
5
6
ext32s_i64 t, in
7
sar_i64 t, t, v
8
ext32s_i64 out, t
9
10
allowing the final extend to be eliminated.
11
12
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
13
Reviewed-by: Luis Pires <luis.pires@eldorado.org.br>
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
14
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
---
15
---
7
accel/tcg/tcg-accel-ops.h | 1 +
16
tcg/optimize.c | 50 +++++++++++++++++++++++++++++++++++++++++++++++---
8
include/exec/exec-all.h | 7 +------
17
1 file changed, 47 insertions(+), 3 deletions(-)
9
include/hw/core/cpu.h | 2 ++
10
accel/tcg/cpu-exec.c | 3 ---
11
accel/tcg/tcg-accel-ops-mttcg.c | 3 +--
12
accel/tcg/tcg-accel-ops-rr.c | 2 +-
13
accel/tcg/tcg-accel-ops.c | 8 ++++++++
14
accel/tcg/translate-all.c | 4 ----
15
linux-user/main.c | 1 +
16
linux-user/sh4/signal.c | 8 +++++---
17
linux-user/syscall.c | 18 ++++++++++--------
18
11 files changed, 30 insertions(+), 27 deletions(-)
19
18
20
diff --git a/accel/tcg/tcg-accel-ops.h b/accel/tcg/tcg-accel-ops.h
19
diff --git a/tcg/optimize.c b/tcg/optimize.c
21
index XXXXXXX..XXXXXXX 100644
20
index XXXXXXX..XXXXXXX 100644
22
--- a/accel/tcg/tcg-accel-ops.h
21
--- a/tcg/optimize.c
23
+++ b/accel/tcg/tcg-accel-ops.h
22
+++ b/tcg/optimize.c
24
@@ -XXX,XX +XXX,XX @@
23
@@ -XXX,XX +XXX,XX @@ static uint64_t smask_from_zmask(uint64_t zmask)
25
void tcg_cpus_destroy(CPUState *cpu);
24
return ~(~0ull >> rep);
26
int tcg_cpus_exec(CPUState *cpu);
27
void tcg_handle_interrupt(CPUState *cpu, int mask);
28
+void tcg_cpu_init_cflags(CPUState *cpu, bool parallel);
29
30
#endif /* TCG_CPUS_H */
31
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
32
index XXXXXXX..XXXXXXX 100644
33
--- a/include/exec/exec-all.h
34
+++ b/include/exec/exec-all.h
35
@@ -XXX,XX +XXX,XX @@ struct TranslationBlock {
36
uintptr_t jmp_dest[2];
37
};
38
39
-extern bool parallel_cpus;
40
-
41
/* Hide the qatomic_read to make code a little easier on the eyes */
42
static inline uint32_t tb_cflags(const TranslationBlock *tb)
43
{
44
@@ -XXX,XX +XXX,XX @@ static inline uint32_t tb_cflags(const TranslationBlock *tb)
45
/* current cflags for hashing/comparison */
46
static inline uint32_t curr_cflags(CPUState *cpu)
47
{
48
- uint32_t cflags = deposit32(0, CF_CLUSTER_SHIFT, 8, cpu->cluster_index);
49
- cflags |= parallel_cpus ? CF_PARALLEL : 0;
50
- cflags |= icount_enabled() ? CF_USE_ICOUNT : 0;
51
- return cflags;
52
+ return cpu->tcg_cflags;
53
}
25
}
54
26
55
/* TranslationBlock invalidate API */
27
+/*
56
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
28
+ * Recreate a properly left-aligned smask after manipulation.
57
index XXXXXXX..XXXXXXX 100644
29
+ * Some bit-shuffling, particularly shifts and rotates, may
58
--- a/include/hw/core/cpu.h
30
+ * retain sign bits on the left, but may scatter disconnected
59
+++ b/include/hw/core/cpu.h
31
+ * sign bits on the right. Retain only what remains to the left.
60
@@ -XXX,XX +XXX,XX @@ struct qemu_work_item;
32
+ */
61
* to a cluster this will be UNASSIGNED_CLUSTER_INDEX; otherwise it will
33
+static uint64_t smask_from_smask(int64_t smask)
62
* be the same as the cluster-id property of the CPU object's TYPE_CPU_CLUSTER
63
* QOM parent.
64
+ * @tcg_cflags: Pre-computed cflags for this cpu.
65
* @nr_cores: Number of cores within this CPU package.
66
* @nr_threads: Number of threads within this CPU.
67
* @running: #true if CPU is currently running (lockless).
68
@@ -XXX,XX +XXX,XX @@ struct CPUState {
69
/* TODO Move common fields from CPUArchState here. */
70
int cpu_index;
71
int cluster_index;
72
+ uint32_t tcg_cflags;
73
uint32_t halted;
74
uint32_t can_do_io;
75
int32_t exception_index;
76
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
77
index XXXXXXX..XXXXXXX 100644
78
--- a/accel/tcg/cpu-exec.c
79
+++ b/accel/tcg/cpu-exec.c
80
@@ -XXX,XX +XXX,XX @@ void cpu_exec_step_atomic(CPUState *cpu)
81
mmap_unlock();
82
}
83
84
- /* Since we got here, we know that parallel_cpus must be true. */
85
- parallel_cpus = false;
86
cpu_exec_enter(cpu);
87
/* execute the generated code */
88
trace_exec_tb(tb, pc);
89
@@ -XXX,XX +XXX,XX @@ void cpu_exec_step_atomic(CPUState *cpu)
90
* the execution.
91
*/
92
g_assert(cpu_in_exclusive_context(cpu));
93
- parallel_cpus = true;
94
cpu->running = false;
95
end_exclusive();
96
}
97
diff --git a/accel/tcg/tcg-accel-ops-mttcg.c b/accel/tcg/tcg-accel-ops-mttcg.c
98
index XXXXXXX..XXXXXXX 100644
99
--- a/accel/tcg/tcg-accel-ops-mttcg.c
100
+++ b/accel/tcg/tcg-accel-ops-mttcg.c
101
@@ -XXX,XX +XXX,XX @@ void mttcg_start_vcpu_thread(CPUState *cpu)
102
char thread_name[VCPU_THREAD_NAME_SIZE];
103
104
g_assert(tcg_enabled());
105
-
106
- parallel_cpus = (current_machine->smp.max_cpus > 1);
107
+ tcg_cpu_init_cflags(cpu, current_machine->smp.max_cpus > 1);
108
109
cpu->thread = g_malloc0(sizeof(QemuThread));
110
cpu->halt_cond = g_malloc0(sizeof(QemuCond));
111
diff --git a/accel/tcg/tcg-accel-ops-rr.c b/accel/tcg/tcg-accel-ops-rr.c
112
index XXXXXXX..XXXXXXX 100644
113
--- a/accel/tcg/tcg-accel-ops-rr.c
114
+++ b/accel/tcg/tcg-accel-ops-rr.c
115
@@ -XXX,XX +XXX,XX @@ void rr_start_vcpu_thread(CPUState *cpu)
116
static QemuThread *single_tcg_cpu_thread;
117
118
g_assert(tcg_enabled());
119
- parallel_cpus = false;
120
+ tcg_cpu_init_cflags(cpu, false);
121
122
if (!single_tcg_cpu_thread) {
123
cpu->thread = g_malloc0(sizeof(QemuThread));
124
diff --git a/accel/tcg/tcg-accel-ops.c b/accel/tcg/tcg-accel-ops.c
125
index XXXXXXX..XXXXXXX 100644
126
--- a/accel/tcg/tcg-accel-ops.c
127
+++ b/accel/tcg/tcg-accel-ops.c
128
@@ -XXX,XX +XXX,XX @@
129
130
/* common functionality among all TCG variants */
131
132
+void tcg_cpu_init_cflags(CPUState *cpu, bool parallel)
133
+{
34
+{
134
+ uint32_t cflags = cpu->cluster_index << CF_CLUSTER_SHIFT;
35
+ /* Only the 1 bits are significant for smask */
135
+ cflags |= parallel ? CF_PARALLEL : 0;
36
+ return smask_from_zmask(~smask);
136
+ cflags |= icount_enabled() ? CF_USE_ICOUNT : 0;
137
+ cpu->tcg_cflags = cflags;
138
+}
37
+}
139
+
38
+
140
void tcg_cpus_destroy(CPUState *cpu)
39
static inline TempOptInfo *ts_info(TCGTemp *ts)
141
{
40
{
142
cpu_thread_signal_destroyed(cpu);
41
return ts->state_ptr;
143
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
42
@@ -XXX,XX +XXX,XX @@ static bool fold_sextract(OptContext *ctx, TCGOp *op)
144
index XXXXXXX..XXXXXXX 100644
43
145
--- a/accel/tcg/translate-all.c
44
static bool fold_shift(OptContext *ctx, TCGOp *op)
146
+++ b/accel/tcg/translate-all.c
147
@@ -XXX,XX +XXX,XX @@ static void *l1_map[V_L1_MAX_SIZE];
148
TCGContext tcg_init_ctx;
149
__thread TCGContext *tcg_ctx;
150
TBContext tb_ctx;
151
-bool parallel_cpus;
152
153
static void page_table_config_init(void)
154
{
45
{
155
@@ -XXX,XX +XXX,XX @@ TranslationBlock *tb_gen_code(CPUState *cpu,
46
+ uint64_t s_mask, z_mask, sign;
156
cflags = (cflags & ~CF_COUNT_MASK) | 1;
47
+
48
if (fold_const2(ctx, op) ||
49
fold_ix_to_i(ctx, op, 0) ||
50
fold_xi_to_x(ctx, op, 0)) {
51
return true;
157
}
52
}
158
53
159
- cflags &= ~CF_CLUSTER_MASK;
54
+ s_mask = arg_info(op->args[1])->s_mask;
160
- cflags |= cpu->cluster_index << CF_CLUSTER_SHIFT;
55
+ z_mask = arg_info(op->args[1])->z_mask;
161
-
56
+
162
max_insns = cflags & CF_COUNT_MASK;
57
if (arg_is_const(op->args[2])) {
163
if (max_insns == 0) {
58
- ctx->z_mask = do_constant_folding(op->opc, ctx->type,
164
max_insns = CF_COUNT_MASK;
59
- arg_info(op->args[1])->z_mask,
165
diff --git a/linux-user/main.c b/linux-user/main.c
60
- arg_info(op->args[2])->val);
166
index XXXXXXX..XXXXXXX 100644
61
+ int sh = arg_info(op->args[2])->val;
167
--- a/linux-user/main.c
62
+
168
+++ b/linux-user/main.c
63
+ ctx->z_mask = do_constant_folding(op->opc, ctx->type, z_mask, sh);
169
@@ -XXX,XX +XXX,XX @@ CPUArchState *cpu_copy(CPUArchState *env)
64
+
170
/* Reset non arch specific state */
65
+ s_mask = do_constant_folding(op->opc, ctx->type, s_mask, sh);
171
cpu_reset(new_cpu);
66
+ ctx->s_mask = smask_from_smask(s_mask);
172
67
+
173
+ new_cpu->tcg_cflags = cpu->tcg_cflags;
68
return fold_masks(ctx, op);
174
memcpy(new_env, env, sizeof(CPUArchState));
69
}
175
70
+
176
/* Clone all break/watchpoints.
71
+ switch (op->opc) {
177
diff --git a/linux-user/sh4/signal.c b/linux-user/sh4/signal.c
72
+ CASE_OP_32_64(sar):
178
index XXXXXXX..XXXXXXX 100644
73
+ /*
179
--- a/linux-user/sh4/signal.c
74
+ * Arithmetic right shift will not reduce the number of
180
+++ b/linux-user/sh4/signal.c
75
+ * input sign repetitions.
181
@@ -XXX,XX +XXX,XX @@ static abi_ulong get_sigframe(struct target_sigaction *ka,
76
+ */
182
return (sp - frame_size) & -8ul;
77
+ ctx->s_mask = s_mask;
78
+ break;
79
+ CASE_OP_32_64(shr):
80
+ /*
81
+ * If the sign bit is known zero, then logical right shift
82
+ * will not reduced the number of input sign repetitions.
83
+ */
84
+ sign = (s_mask & -s_mask) >> 1;
85
+ if (!(z_mask & sign)) {
86
+ ctx->s_mask = s_mask;
87
+ }
88
+ break;
89
+ default:
90
+ break;
91
+ }
92
+
93
return false;
183
}
94
}
184
185
-/* Notice when we're in the middle of a gUSA region and reset.
186
- Note that this will only occur for !parallel_cpus, as we will
187
- translate such sequences differently in a parallel context. */
188
+/*
189
+ * Notice when we're in the middle of a gUSA region and reset.
190
+ * Note that this will only occur when #CF_PARALLEL is unset, as we
191
+ * will translate such sequences differently in a parallel context.
192
+ */
193
static void unwind_gusa(CPUSH4State *regs)
194
{
195
/* If the stack pointer is sufficiently negative, and we haven't
196
diff --git a/linux-user/syscall.c b/linux-user/syscall.c
197
index XXXXXXX..XXXXXXX 100644
198
--- a/linux-user/syscall.c
199
+++ b/linux-user/syscall.c
200
@@ -XXX,XX +XXX,XX @@ static int do_fork(CPUArchState *env, unsigned int flags, abi_ulong newsp,
201
/* Grab a mutex so that thread setup appears atomic. */
202
pthread_mutex_lock(&clone_lock);
203
204
+ /*
205
+ * If this is our first additional thread, we need to ensure we
206
+ * generate code for parallel execution and flush old translations.
207
+ * Do this now so that the copy gets CF_PARALLEL too.
208
+ */
209
+ if (!(cpu->tcg_cflags & CF_PARALLEL)) {
210
+ cpu->tcg_cflags |= CF_PARALLEL;
211
+ tb_flush(cpu);
212
+ }
213
+
214
/* we create a new CPU instance. */
215
new_env = cpu_copy(env);
216
/* Init regs that differ from the parent. */
217
@@ -XXX,XX +XXX,XX @@ static int do_fork(CPUArchState *env, unsigned int flags, abi_ulong newsp,
218
sigprocmask(SIG_BLOCK, &sigmask, &info.sigmask);
219
cpu->random_seed = qemu_guest_random_seed_thread_part1();
220
221
- /* If this is our first additional thread, we need to ensure we
222
- * generate code for parallel execution and flush old translations.
223
- */
224
- if (!parallel_cpus) {
225
- parallel_cpus = true;
226
- tb_flush(cpu);
227
- }
228
-
229
ret = pthread_create(&info.thread, &attr, clone_func, &info);
230
/* TODO: Free new CPU state if thread creation failed. */
231
95
232
--
96
--
233
2.25.1
97
2.25.1
234
98
235
99
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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