[PATCH v7 10/75] target/riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr registers

From: Frank Chang <frank.chang@sifive.com>

If VS field is off, accessing vector csr registers should raise an
illegal-instruction exception.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/csr.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 92cf2eedd40..a6a535f7e33 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -48,6 +48,11 @@ static int fs(CPURISCVState *env, int csrno)
 static int vs(CPURISCVState *env, int csrno)
 {
     if (env->misa & RVV) {
+#if !defined(CONFIG_USER_ONLY)
+        if (!env->debugger && !riscv_cpu_vector_enabled(env)) {
+            return -RISCV_EXCP_ILLEGAL_INST;
+        }
+#endif
         return 0;
     }
     return -RISCV_EXCP_ILLEGAL_INST;
-- 
2.17.1

• [PATCH v7 01/75] target/riscv: drop vector 0.7.1 and add 1.0 support
• [PATCH v7 02/75] target/riscv: Use FIELD_EX32() to extract wd field
• [PATCH v7 03/75] target/riscv: rvv-1.0: add mstatus VS field
• [PATCH v7 04/75] target/riscv: rvv-1.0: add sstatus VS field
• [PATCH v7 05/75] target/riscv: rvv-1.0: introduce writable misa.v field
• [PATCH v7 06/75] target/riscv: rvv-1.0: add translation-time vector context status
• [PATCH v7 07/75] target/riscv: rvv-1.0: remove rvv related codes from fcsr registers
• [PATCH v7 08/75] target/riscv: rvv-1.0: add vcsr register
• [PATCH v7 09/75] target/riscv: rvv-1.0: add vlenb register
• [PATCH v7 10/75] target/riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr registers
• [PATCH v7 11/75] target/riscv: rvv-1.0: remove MLEN calculations
• [PATCH v7 12/75] target/riscv: rvv-1.0: add fractional LMUL
• [PATCH v7 13/75] target/riscv: rvv-1.0: add VMA and VTA
• [PATCH v7 14/75] target/riscv: rvv-1.0: update check functions
• [PATCH v7 15/75] target/riscv: introduce more imm value modes in translator functions
• [PATCH v7 16/75] target/riscv: rvv:1.0: add translation-time nan-box helper function
• [PATCH v7 17/75] target/riscv: rvv-1.0: configure instructions
• [PATCH v7 18/75] target/riscv: rvv-1.0: stride load and store instructions
• [PATCH v7 19/75] target/riscv: rvv-1.0: index load and store instructions
• [PATCH v7 20/75] target/riscv: rvv-1.0: fix address index overflow bug of indexed load/store insns
• [PATCH v7 21/75] target/riscv: rvv-1.0: fault-only-first unit stride load
• [PATCH v7 22/75] target/riscv: rvv-1.0: amo operations
• [PATCH v7 23/75] target/riscv: rvv-1.0: load/store whole register instructions
• [PATCH v7 24/75] target/riscv: rvv-1.0: update vext_max_elems() for load/store insns
• [PATCH v7 25/75] target/riscv: rvv-1.0: take fractional LMUL into vector max elements calculation
• [PATCH v7 26/75] target/riscv: rvv-1.0: floating-point square-root instruction
• [PATCH v7 27/75] target/riscv: rvv-1.0: floating-point classify instructions
• [PATCH v7 28/75] target/riscv: rvv-1.0: mask population count instruction
• [PATCH v7 29/75] target/riscv: rvv-1.0: find-first-set mask bit instruction
• [PATCH v7 30/75] target/riscv: rvv-1.0: set-X-first mask bit instructions
• [PATCH v7 31/75] target/riscv: rvv-1.0: iota instruction
• [PATCH v7 32/75] target/riscv: rvv-1.0: element index instruction
• [PATCH v7 33/75] target/riscv: rvv-1.0: allow load element with sign-extended
• [PATCH v7 34/75] target/riscv: rvv-1.0: register gather instructions
• [PATCH v7 35/75] target/riscv: rvv-1.0: integer scalar move instructions
• [PATCH v7 36/75] target/riscv: rvv-1.0: floating-point move instruction
• [PATCH v7 37/75] target/riscv: rvv-1.0: floating-point scalar move instructions
• [PATCH v7 38/75] target/riscv: rvv-1.0: whole register move instructions
• [PATCH v7 39/75] target/riscv: rvv-1.0: integer extension instructions
• [PATCH v7 40/75] target/riscv: rvv-1.0: single-width averaging add and subtract instructions
• [PATCH v7 41/75] target/riscv: rvv-1.0: single-width bit shift instructions
• [PATCH v7 42/75] target/riscv: rvv-1.0: integer add-with-carry/subtract-with-borrow
• [PATCH v7 43/75] target/riscv: rvv-1.0: narrowing integer right shift instructions
• [PATCH v7 44/75] target/riscv: rvv-1.0: widening integer multiply-add instructions
• [PATCH v7 45/75] target/riscv: rvv-1.0: single-width saturating add and subtract instructions
• [PATCH v7 46/75] target/riscv: rvv-1.0: integer comparison instructions
• [PATCH v7 47/75] target/riscv: rvv-1.0: floating-point compare instructions
• [PATCH v7 48/75] target/riscv: rvv-1.0: mask-register logical instructions
• [PATCH v7 49/75] target/riscv: rvv-1.0: slide instructions
• [PATCH v7 50/75] target/riscv: rvv-1.0: floating-point slide instructions
• [PATCH v7 51/75] target/riscv: rvv-1.0: narrowing fixed-point clip instructions
• [PATCH v7 52/75] target/riscv: rvv-1.0: single-width floating-point reduction
• [PATCH v7 53/75] target/riscv: rvv-1.0: widening floating-point reduction instructions
• [PATCH v7 54/75] target/riscv: rvv-1.0: single-width scaling shift instructions
• [PATCH v7 55/75] target/riscv: rvv-1.0: remove widening saturating scaled multiply-add
• [PATCH v7 56/75] target/riscv: rvv-1.0: remove vmford.vv and vmford.vf
• [PATCH v7 57/75] target/riscv: rvv-1.0: remove integer extract instruction
• [PATCH v7 58/75] target/riscv: rvv-1.0: floating-point min/max instructions
• [PATCH v7 59/75] target/riscv: introduce floating-point rounding mode enum
• [PATCH v7 60/75] target/riscv: rvv-1.0: floating-point/integer type-convert instructions
• [PATCH v7 61/75] target/riscv: rvv-1.0: widening floating-point/integer type-convert
• [PATCH v7 62/75] target/riscv: add "set round to odd" rounding mode helper function
• [PATCH v7 63/75] target/riscv: rvv-1.0: narrowing floating-point/integer type-convert
• [PATCH v7 64/75] target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits
• [PATCH v7 65/75] target/riscv: rvv-1.0: implement vstart CSR
• [PATCH v7 66/75] target/riscv: rvv-1.0: trigger illegal instruction exception if frm is not valid
• [PATCH v7 67/75] target/riscv: rvv-1.0: set mstatus.SD bit when writing vector CSRs
• [PATCH v7 68/75] target/riscv: gdb: support vector registers for rv64 & rv32
• [PATCH v7 69/75] target/riscv: rvv-1.0: floating-point reciprocal square-root estimate instruction
• [PATCH v7 70/75] target/riscv: rvv-1.0: floating-point reciprocal estimate instruction
• [PATCH v7 71/75] target/riscv: set mstatus.SD bit when writing fp CSRs
• [PATCH v7 72/75] target/riscv: rvv-1.0: rename r2_zimm to r2_zimm11
• [PATCH v7 73/75] target/riscv: rvv-1.0: add vsetivli instruction
• [PATCH v7 74/75] target/riscv: rvv-1.0: add evl parameter to vext_ldst_us()
• [PATCH v7 75/75] target/riscv: rvv-1.0: add vector unit-stride mask load/store insns