V2: Patch 35: do not re-find the python executable to use.

r~


The following changes since commit 91416a4254015e1e3f602f2b241b9ddb7879c10b:

  Merge remote-tracking branch 'remotes/stsquad/tags/pull-plugin-updates-180221-1' into staging (2021-02-18 13:27:03 +0000)

are available in the Git repository at:

  https://gitlab.com/rth7680/qemu.git tags/pull-hex-20210218

for you to fetch changes up to 3e7a84eeccc3b3a9b43c6dfb52bd98ea5acebf0a:

  Hexagon build infrastructure (2021-02-18 08:25:06 -0800)

----------------------------------------------------------------
Initial commit for the Qualcomm Hexagon processor.

----------------------------------------------------------------
Richard Henderson (1):
      qemu/int128: Add int128_or

Taylor Simpson (34):
      Hexagon Update MAINTAINERS file
      Hexagon (target/hexagon) README
      Hexagon (include/elf.h) ELF machine definition
      Hexagon (target/hexagon) scalar core definition
      Hexagon (disas) disassembler
      Hexagon (target/hexagon) register names
      Hexagon (target/hexagon) scalar core helpers
      Hexagon (target/hexagon) GDB Stub
      Hexagon (target/hexagon) architecture types
      Hexagon (target/hexagon) instruction and packet types
      Hexagon (target/hexagon) register fields
      Hexagon (target/hexagon) instruction attributes
      Hexagon (target/hexagon) instruction/packet decode
      Hexagon (target/hexagon) instruction printing
      Hexagon (target/hexagon/arch.[ch]) utility functions
      Hexagon (target/hexagon/conv_emu.[ch]) utility functions
      Hexagon (target/hexagon/fma_emu.[ch]) utility functions
      Hexagon (target/hexagon/imported) arch import
      Hexagon (target/hexagon) generator phase 1 - C preprocessor for semantics
      Hexagon (target/hexagon) generator phase 2 - generate header files
      Hexagon (target/hexagon) generator phase 3 - C preprocessor for decode tree
      Hexagon (target/hexagon) generater phase 4 - decode tree
      Hexagon (target/hexagon) opcode data structures
      Hexagon (target/hexagon) macros
      Hexagon (target/hexagon) instruction classes
      Hexagon (target/hexagon) TCG generation
      Hexagon (target/hexagon) TCG for instructions with multiple definitions
      Hexagon (target/hexagon) TCG for floating point instructions
      Hexagon (target/hexagon) translation
      Hexagon (linux-user/hexagon) Linux user emulation
      Hexagon (tests/tcg/hexagon) TCG tests - multiarch
      Hexagon (tests/tcg/hexagon) TCG tests - atomics/load/store/misc
      Hexagon (tests/tcg/hexagon) TCG tests - floating point
      Hexagon build infrastructure

 default-configs/targets/hexagon-linux-user.mak |    1 +
 meson.build                                    |    1 +
 include/disas/dis-asm.h                        |    1 +
 include/elf.h                                  |    1 +
 include/qemu/int128.h                          |   10 +
 linux-user/hexagon/sockbits.h                  |   18 +
 linux-user/hexagon/syscall_nr.h                |  322 ++++
 linux-user/hexagon/target_cpu.h                |   44 +
 linux-user/hexagon/target_elf.h                |   40 +
 linux-user/hexagon/target_fcntl.h              |   18 +
 linux-user/hexagon/target_signal.h             |   34 +
 linux-user/hexagon/target_structs.h            |   54 +
 linux-user/hexagon/target_syscall.h            |   36 +
 linux-user/hexagon/termbits.h                  |   18 +
 linux-user/qemu.h                              |    2 +
 linux-user/syscall_defs.h                      |   33 +
 target/hexagon/arch.h                          |   34 +
 target/hexagon/attribs.h                       |   35 +
 target/hexagon/conv_emu.h                      |   31 +
 target/hexagon/cpu-param.h                     |   29 +
 target/hexagon/cpu.h                           |  159 ++
 target/hexagon/cpu_bits.h                      |   58 +
 target/hexagon/decode.h                        |   32 +
 target/hexagon/fma_emu.h                       |   36 +
 target/hexagon/gen_tcg.h                       |  319 ++++
 target/hexagon/genptr.h                        |   25 +
 target/hexagon/helper.h                        |   88 +
 target/hexagon/hex_arch_types.h                |   38 +
 target/hexagon/hex_regs.h                      |   83 +
 target/hexagon/iclass.h                        |   50 +
 target/hexagon/insn.h                          |   74 +
 target/hexagon/internal.h                      |   37 +
 target/hexagon/macros.h                        |  592 +++++++
 target/hexagon/opcodes.h                       |   58 +
 target/hexagon/printinsn.h                     |   27 +
 target/hexagon/reg_fields.h                    |   36 +
 target/hexagon/translate.h                     |   93 ++
 target/hexagon/attribs_def.h.inc               |   97 ++
 target/hexagon/reg_fields_def.h.inc            |   41 +
 disas/hexagon.c                                |   65 +
 linux-user/elfload.c                           |   16 +
 linux-user/hexagon/cpu_loop.c                  |  100 ++
 linux-user/hexagon/signal.c                    |  276 ++++
 target/hexagon/arch.c                          |  300 ++++
 target/hexagon/conv_emu.c                      |  177 ++
 target/hexagon/cpu.c                           |  318 ++++
 target/hexagon/decode.c                        |  957 +++++++++++
 target/hexagon/fma_emu.c                       |  702 ++++++++
 target/hexagon/gdbstub.c                       |   47 +
 target/hexagon/gen_dectree_import.c            |  188 +++
 target/hexagon/gen_semantics.c                 |   88 +
 target/hexagon/genptr.c                        |  331 ++++
 target/hexagon/iclass.c                        |   73 +
 target/hexagon/op_helper.c                     | 1064 ++++++++++++
 target/hexagon/opcodes.c                       |  142 ++
 target/hexagon/printinsn.c                     |  146 ++
 target/hexagon/reg_fields.c                    |   27 +
 target/hexagon/translate.c                     |  748 +++++++++
 tests/tcg/hexagon/atomics.c                    |  139 ++
 tests/tcg/hexagon/dual_stores.c                |   60 +
 tests/tcg/hexagon/fpstuff.c                    |  370 +++++
 tests/tcg/hexagon/mem_noshuf.c                 |  328 ++++
 tests/tcg/hexagon/misc.c                       |  380 +++++
 tests/tcg/hexagon/preg_alias.c                 |  169 ++
 MAINTAINERS                                    |    9 +
 disas/meson.build                              |    1 +
 scripts/gensyscalls.sh                         |    1 +
 scripts/qemu-binfmt-conf.sh                    |    6 +-
 target/hexagon/README                          |  235 +++
 target/hexagon/dectree.py                      |  351 ++++
 target/hexagon/gen_helper_funcs.py             |  220 +++
 target/hexagon/gen_helper_protos.py            |  150 ++
 target/hexagon/gen_op_attribs.py               |   39 +
 target/hexagon/gen_op_regs.py                  |  110 ++
 target/hexagon/gen_opcodes_def.py              |   36 +
 target/hexagon/gen_printinsn.py                |  173 ++
 target/hexagon/gen_shortcode.py                |   60 +
 target/hexagon/gen_tcg_func_table.py           |   58 +
 target/hexagon/gen_tcg_funcs.py                |  485 ++++++
 target/hexagon/hex_common.py                   |  234 +++
 target/hexagon/imported/allidefs.def           |   30 +
 target/hexagon/imported/alu.idef               | 1258 ++++++++++++++
 target/hexagon/imported/branch.idef            |  326 ++++
 target/hexagon/imported/compare.idef           |  619 +++++++
 target/hexagon/imported/encode.def             |  124 ++
 target/hexagon/imported/encode_pp.def          | 2110 ++++++++++++++++++++++++
 target/hexagon/imported/encode_subinsn.def     |  149 ++
 target/hexagon/imported/float.idef             |  312 ++++
 target/hexagon/imported/iclass.def             |   51 +
 target/hexagon/imported/ldst.idef              |  286 ++++
 target/hexagon/imported/macros.def             | 1531 +++++++++++++++++
 target/hexagon/imported/mpy.idef               | 1208 ++++++++++++++
 target/hexagon/imported/shift.idef             | 1066 ++++++++++++
 target/hexagon/imported/subinsns.idef          |  149 ++
 target/hexagon/imported/system.idef            |   68 +
 target/hexagon/meson.build                     |  191 +++
 target/meson.build                             |    1 +
 tests/tcg/configure.sh                         |    4 +-
 tests/tcg/hexagon/Makefile.target              |   46 +
 tests/tcg/hexagon/first.S                      |   56 +
 tests/tcg/hexagon/float_convs.ref              |  748 +++++++++
 tests/tcg/hexagon/float_madds.ref              |  768 +++++++++
 102 files changed, 23183 insertions(+), 2 deletions(-)
 create mode 100644 default-configs/targets/hexagon-linux-user.mak
 create mode 100644 linux-user/hexagon/sockbits.h
 create mode 100644 linux-user/hexagon/syscall_nr.h
 create mode 100644 linux-user/hexagon/target_cpu.h
 create mode 100644 linux-user/hexagon/target_elf.h
 create mode 100644 linux-user/hexagon/target_fcntl.h
 create mode 100644 linux-user/hexagon/target_signal.h
 create mode 100644 linux-user/hexagon/target_structs.h
 create mode 100644 linux-user/hexagon/target_syscall.h
 create mode 100644 linux-user/hexagon/termbits.h
 create mode 100644 target/hexagon/arch.h
 create mode 100644 target/hexagon/attribs.h
 create mode 100644 target/hexagon/conv_emu.h
 create mode 100644 target/hexagon/cpu-param.h
 create mode 100644 target/hexagon/cpu.h
 create mode 100644 target/hexagon/cpu_bits.h
 create mode 100644 target/hexagon/decode.h
 create mode 100644 target/hexagon/fma_emu.h
 create mode 100644 target/hexagon/gen_tcg.h
 create mode 100644 target/hexagon/genptr.h
 create mode 100644 target/hexagon/helper.h
 create mode 100644 target/hexagon/hex_arch_types.h
 create mode 100644 target/hexagon/hex_regs.h
 create mode 100644 target/hexagon/iclass.h
 create mode 100644 target/hexagon/insn.h
 create mode 100644 target/hexagon/internal.h
 create mode 100644 target/hexagon/macros.h
 create mode 100644 target/hexagon/opcodes.h
 create mode 100644 target/hexagon/printinsn.h
 create mode 100644 target/hexagon/reg_fields.h
 create mode 100644 target/hexagon/translate.h
 create mode 100644 target/hexagon/attribs_def.h.inc
 create mode 100644 target/hexagon/reg_fields_def.h.inc
 create mode 100644 disas/hexagon.c
 create mode 100644 linux-user/hexagon/cpu_loop.c
 create mode 100644 linux-user/hexagon/signal.c
 create mode 100644 target/hexagon/arch.c
 create mode 100644 target/hexagon/conv_emu.c
 create mode 100644 target/hexagon/cpu.c
 create mode 100644 target/hexagon/decode.c
 create mode 100644 target/hexagon/fma_emu.c
 create mode 100644 target/hexagon/gdbstub.c
 create mode 100644 target/hexagon/gen_dectree_import.c
 create mode 100644 target/hexagon/gen_semantics.c
 create mode 100644 target/hexagon/genptr.c
 create mode 100644 target/hexagon/iclass.c
 create mode 100644 target/hexagon/op_helper.c
 create mode 100644 target/hexagon/opcodes.c
 create mode 100644 target/hexagon/printinsn.c
 create mode 100644 target/hexagon/reg_fields.c
 create mode 100644 target/hexagon/translate.c
 create mode 100644 tests/tcg/hexagon/atomics.c
 create mode 100644 tests/tcg/hexagon/dual_stores.c
 create mode 100644 tests/tcg/hexagon/fpstuff.c
 create mode 100644 tests/tcg/hexagon/mem_noshuf.c
 create mode 100644 tests/tcg/hexagon/misc.c
 create mode 100644 tests/tcg/hexagon/preg_alias.c
 create mode 100644 target/hexagon/README
 create mode 100755 target/hexagon/dectree.py
 create mode 100755 target/hexagon/gen_helper_funcs.py
 create mode 100755 target/hexagon/gen_helper_protos.py
 create mode 100755 target/hexagon/gen_op_attribs.py
 create mode 100755 target/hexagon/gen_op_regs.py
 create mode 100755 target/hexagon/gen_opcodes_def.py
 create mode 100755 target/hexagon/gen_printinsn.py
 create mode 100755 target/hexagon/gen_shortcode.py
 create mode 100755 target/hexagon/gen_tcg_func_table.py
 create mode 100755 target/hexagon/gen_tcg_funcs.py
 create mode 100755 target/hexagon/hex_common.py
 create mode 100644 target/hexagon/imported/allidefs.def
 create mode 100644 target/hexagon/imported/alu.idef
 create mode 100644 target/hexagon/imported/branch.idef
 create mode 100644 target/hexagon/imported/compare.idef
 create mode 100644 target/hexagon/imported/encode.def
 create mode 100644 target/hexagon/imported/encode_pp.def
 create mode 100644 target/hexagon/imported/encode_subinsn.def
 create mode 100644 target/hexagon/imported/float.idef
 create mode 100644 target/hexagon/imported/iclass.def
 create mode 100644 target/hexagon/imported/ldst.idef
 create mode 100755 target/hexagon/imported/macros.def
 create mode 100644 target/hexagon/imported/mpy.idef
 create mode 100644 target/hexagon/imported/shift.idef
 create mode 100644 target/hexagon/imported/subinsns.idef
 create mode 100644 target/hexagon/imported/system.idef
 create mode 100644 target/hexagon/meson.build
 create mode 100644 tests/tcg/hexagon/Makefile.target
 create mode 100644 tests/tcg/hexagon/first.S
 create mode 100644 tests/tcg/hexagon/float_convs.ref
 create mode 100644 tests/tcg/hexagon/float_madds.ref

On Thu, 18 Feb 2021 at 16:29, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> V2: Patch 35: do not re-find the python executable to use.
>
> r~
>
>
> The following changes since commit 91416a4254015e1e3f602f2b241b9ddb7879c10b:
>
>   Merge remote-tracking branch 'remotes/stsquad/tags/pull-plugin-updates-180221-1' into staging (2021-02-18 13:27:03 +0000)
>
> are available in the Git repository at:
>
>   https://gitlab.com/rth7680/qemu.git tags/pull-hex-20210218
>
> for you to fetch changes up to 3e7a84eeccc3b3a9b43c6dfb52bd98ea5acebf0a:
>
>   Hexagon build infrastructure (2021-02-18 08:25:06 -0800)
>
> ----------------------------------------------------------------
> Initial commit for the Qualcomm Hexagon processor.
>
> ----------------------------------------------------------------


Applied, thanks.

Please update the changelog at https://wiki.qemu.org/ChangeLog/6.0
for any user-visible changes.

-- PMM

On Thu, 18 Feb 2021 at 16:29, Richard Henderson
<richard.henderson@linaro.org> wrote:
> ----------------------------------------------------------------
> Initial commit for the Qualcomm Hexagon processor.
>
> ----------------------------------------------------------------

Hi; Coverity Scan reports a pile of new issues in the Hexagon
code; could one of you go through them and confirm whether they
are either false positives or else provide fixes for them, please?

thanks
-- PMM

I requested access to scan.coverity.com.  Once it is granted, I'll take a look.

Thanks,
Taylor


> -----Original Message-----
> From: Peter Maydell <peter.maydell@linaro.org>
> Sent: Friday, February 19, 2021 4:52 AM
> To: Richard Henderson <richard.henderson@linaro.org>
> Cc: QEMU Developers <qemu-devel@nongnu.org>; Taylor Simpson
> <tsimpson@quicinc.com>
> Subject: Re: [PULL v2 00/35] hexagon initial commit
>
> -------------------------------------------------------------------------
> CAUTION: This email originated from outside of the organization.
> -------------------------------------------------------------------------
>
> On Thu, 18 Feb 2021 at 16:29, Richard Henderson
> <richard.henderson@linaro.org> wrote:
> > ----------------------------------------------------------------
> > Initial commit for the Qualcomm Hexagon processor.
> >
> > ----------------------------------------------------------------
>
> Hi; Coverity Scan reports a pile of new issues in the Hexagon
> code; could one of you go through them and confirm whether they
> are either false positives or else provide fixes for them, please?
>
> thanks
> -- PMM

On 2/19/21 8:30 AM, Taylor Simpson wrote:
> I requested access to scan.coverity.com.  Once it is granted, I'll take a look.

I took a quick look.  Quite a lot of the errors are related to

> #define fASHIFTL(SRC, SHAMT, REGSTYPE) \
>     (((SHAMT) >= 64) ? 0 : (fCAST##REGSTYPE##s(SRC) << (SHAMT)))

and

> #define fLSHIFTR(SRC, SHAMT, REGSTYPE) \
>     (((SHAMT) >= 64) ? 0 : (fCAST##REGSTYPE##u(SRC) >> (SHAMT)))

Coverity does not look beyond the leading comparison to inform the bounds, and
these macros are used with a 32-bit type.  It then warns that the shift could
be out of bounds.

It appears that none of the uses of fASHIFTL can actually overflow the shift count:

  * S2_asl_i has a 5-bit immediate shift count.
  * S2_addasl_rrri has a 3-bit immediate shift count.
  * S2_valign has a 3-bit scaled immediate shift count
    (on a 64-bit type).

So it looks like you could simply drop the tests entirely.
If you really want to keep it, then you should make use of REGSTYPE and bound
based on that.


r~