Introduce the PROT3W opcode (Parallel Rotate 3 Words).
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/tx79.decode | 1 +
target/mips/tx79_translate.c | 28 ++++++++++++++++++++++++++++
2 files changed, 29 insertions(+)
diff --git a/target/mips/tx79.decode b/target/mips/tx79.decode
index 0ea9fc95568..79001359242 100644
--- a/target/mips/tx79.decode
+++ b/target/mips/tx79.decode
@@ -56,6 +56,7 @@ PAND 011100 ..... ..... ..... 10010 001001 @rs_rt_rd
PXOR 011100 ..... ..... ..... 10011 001001 @rs_rt_rd
PEXEH 011100 00000 ..... ..... 11010 001001 @rt_rd
PEXEW 011100 00000 ..... ..... 11110 001001 @rt_rd
+PROT3W 011100 00000 ..... ..... 11111 001001 @rt_rd
# MMI3
diff --git a/target/mips/tx79_translate.c b/target/mips/tx79_translate.c
index 59451a043a4..c25f61d382c 100644
--- a/target/mips/tx79_translate.c
+++ b/target/mips/tx79_translate.c
@@ -753,3 +753,31 @@ static bool trans_PEXEW(DisasContext *ctx, arg_rtype *a)
return true;
}
+
+/* Parallel Rotate 3 Words Left */
+static bool trans_PROT3W(DisasContext *ctx, arg_rtype *a)
+{
+ TCGv_i64 ax;
+
+ if (a->rd == 0) {
+ /* nop */
+ return true;
+ }
+ if (a->rt == 0) {
+ tcg_gen_movi_i64(cpu_gpr[a->rd], 0);
+ tcg_gen_movi_i64(cpu_gpr_hi[a->rd], 0);
+ return true;
+ }
+
+ ax = tcg_temp_new_i64();
+
+ tcg_gen_mov_i64(ax, cpu_gpr_hi[a->rt]);
+ tcg_gen_deposit_i64(cpu_gpr_hi[a->rd], ax, cpu_gpr[a->rt], 0, 32);
+
+ tcg_gen_deposit_i64(cpu_gpr[a->rd], cpu_gpr[a->rt], ax, 0, 32);
+ tcg_gen_rotri_i64(cpu_gpr[a->rd], cpu_gpr[a->rd], 32);
+
+ tcg_temp_free(ax);
+
+ return true;
+}
--
2.26.2