| 1 | Massively slimmed down v2: MemTag broke bsd-user, and the npcm7xx | 1 | v1->v2: fix format string nit in ITS patches (%lu used when PRIu64 needed) |
|---|---|---|---|
| 2 | ethernet device failed 'make check' on big-endian hosts. | ||
| 3 | 2 | ||
| 4 | -- PMM | 3 | The following changes since commit eae587e8e3694b1aceab23239493fb4c7e1a80f5: |
| 5 | 4 | ||
| 6 | The following changes since commit 83339e21d05c824ebc9131d644f25c23d0e41ecf: | 5 | Merge remote-tracking branch 'remotes/armbru/tags/pull-qapi-2021-09-13' into staging (2021-09-13 11:00:30 +0100) |
| 7 | |||
| 8 | Merge remote-tracking branch 'remotes/stefanha-gitlab/tags/block-pull-request' into staging (2021-02-10 15:42:20 +0000) | ||
| 9 | 6 | ||
| 10 | are available in the Git repository at: | 7 | are available in the Git repository at: |
| 11 | 8 | ||
| 12 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210211-1 | 9 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210913-1 |
| 13 | 10 | ||
| 14 | for you to fetch changes up to d3c1183ffeb71ca3a783eae3d7e1c51e71e8a621: | 11 | for you to fetch changes up to 925e3b205bb17af52ac06c7bdd9d84b27345a4e9: |
| 15 | 12 | ||
| 16 | target/arm: Correctly initialize MDCR_EL2.HPMN (2021-02-11 19:48:09 +0000) | 13 | hw/arm/mps2.c: Mark internal-only I2C buses as 'full' (2021-09-13 19:36:50 +0100) |
| 17 | 14 | ||
| 18 | ---------------------------------------------------------------- | 15 | ---------------------------------------------------------------- |
| 19 | target-arm queue: | 16 | target-arm queue: |
| 20 | * Correctly initialize MDCR_EL2.HPMN | 17 | * mark MPS2/MPS3 board-internal i2c buses as 'full' so that command |
| 21 | * versal: Use nr_apu_cpus in favor of hard coding 2 | 18 | line user-created devices are not plugged into them |
| 22 | * accel/tcg: Add URL of clang bug to comment about our workaround | 19 | * Take an exception if PSTATE.IL is set |
| 23 | * Add support for FEAT_DIT, Data Independent Timing | 20 | * Support an emulated ITS in the virt board |
| 24 | * Remove GPIO from unimplemented NPCM7XX | 21 | * Add support for kudo-bmc board |
| 25 | * Fix SCR RES1 handling | 22 | * Probe for KVM_CAP_ARM_VM_IPA_SIZE when creating scratch VM |
| 26 | * Don't migrate CPUARMState.features | 23 | * cadence_uart: Fix clock handling issues that prevented |
| 24 | u-boot from running | ||
| 27 | 25 | ||
| 28 | ---------------------------------------------------------------- | 26 | ---------------------------------------------------------------- |
| 29 | Aaron Lindsay (1): | 27 | Bin Meng (6): |
| 30 | target/arm: Don't migrate CPUARMState.features | 28 | hw/misc: zynq_slcr: Correctly compute output clocks in the reset exit phase |
| 29 | hw/char: cadence_uart: Disable transmit when input clock is disabled | ||
| 30 | hw/char: cadence_uart: Move clock/reset check to uart_can_receive() | ||
| 31 | hw/char: cadence_uart: Convert to memop_with_attrs() ops | ||
| 32 | hw/char: cadence_uart: Ignore access when unclocked or in reset for uart_{read, write}() | ||
| 33 | hw/char: cadence_uart: Log a guest error when device is unclocked or in reset | ||
| 31 | 34 | ||
| 32 | Daniel Müller (1): | 35 | Chris Rauer (1): |
| 33 | target/arm: Correctly initialize MDCR_EL2.HPMN | 36 | hw/arm: Add support for kudo-bmc board. |
| 34 | 37 | ||
| 35 | Edgar E. Iglesias (1): | 38 | Marc Zyngier (1): |
| 36 | hw/arm: versal: Use nr_apu_cpus in favor of hard coding 2 | 39 | hw/arm/virt: KVM: Probe for KVM_CAP_ARM_VM_IPA_SIZE when creating scratch VM |
| 37 | 40 | ||
| 38 | Hao Wu (1): | 41 | Peter Maydell (5): |
| 39 | hw/arm: Remove GPIO from unimplemented NPCM7XX | 42 | target/arm: Take an exception if PSTATE.IL is set |
| 43 | qdev: Support marking individual buses as 'full' | ||
| 44 | hw/arm/mps2-tz.c: Add extra data parameter to MakeDevFn | ||
| 45 | hw/arm/mps2-tz.c: Mark internal-only I2C buses as 'full' | ||
| 46 | hw/arm/mps2.c: Mark internal-only I2C buses as 'full' | ||
| 40 | 47 | ||
| 41 | Mike Nawrocki (1): | 48 | Richard Henderson (1): |
| 42 | target/arm: Fix SCR RES1 handling | 49 | target/arm: Merge disas_a64_insn into aarch64_tr_translate_insn |
| 43 | 50 | ||
| 44 | Peter Maydell (2): | 51 | Shashi Mallela (9): |
| 45 | arm: Update infocenter.arm.com URLs | 52 | hw/intc: GICv3 ITS initial framework |
| 46 | accel/tcg: Add URL of clang bug to comment about our workaround | 53 | hw/intc: GICv3 ITS register definitions added |
| 54 | hw/intc: GICv3 ITS command queue framework | ||
| 55 | hw/intc: GICv3 ITS Command processing | ||
| 56 | hw/intc: GICv3 ITS Feature enablement | ||
| 57 | hw/intc: GICv3 redistributor ITS processing | ||
| 58 | tests/data/acpi/virt: Add IORT files for ITS | ||
| 59 | hw/arm/virt: add ITS support in virt GIC | ||
| 60 | tests/data/acpi/virt: Update IORT files for ITS | ||
| 47 | 61 | ||
| 48 | Rebecca Cran (4): | 62 | docs/system/arm/nuvoton.rst | 1 + |
| 49 | target/arm: Add support for FEAT_DIT, Data Independent Timing | 63 | hw/intc/gicv3_internal.h | 188 ++++- |
| 50 | target/arm: Support AA32 DIT by moving PSTATE_SS from cpsr into env->pstate | 64 | include/hw/arm/virt.h | 2 + |
| 51 | target/arm: Set ID_AA64PFR0.DIT and ID_PFR0.DIT to 1 for "max" AA64 CPU | 65 | include/hw/intc/arm_gicv3_common.h | 13 + |
| 52 | target/arm: Set ID_PFR0.DIT to 1 for "max" 32-bit CPU | 66 | include/hw/intc/arm_gicv3_its_common.h | 32 +- |
| 67 | include/hw/qdev-core.h | 24 + | ||
| 68 | target/arm/cpu.h | 1 + | ||
| 69 | target/arm/kvm_arm.h | 4 +- | ||
| 70 | target/arm/syndrome.h | 5 + | ||
| 71 | target/arm/translate.h | 2 + | ||
| 72 | hw/arm/mps2-tz.c | 92 ++- | ||
| 73 | hw/arm/mps2.c | 12 +- | ||
| 74 | hw/arm/npcm7xx_boards.c | 34 + | ||
| 75 | hw/arm/virt.c | 29 +- | ||
| 76 | hw/char/cadence_uart.c | 61 +- | ||
| 77 | hw/intc/arm_gicv3.c | 14 + | ||
| 78 | hw/intc/arm_gicv3_common.c | 13 + | ||
| 79 | hw/intc/arm_gicv3_cpuif.c | 7 +- | ||
| 80 | hw/intc/arm_gicv3_dist.c | 5 +- | ||
| 81 | hw/intc/arm_gicv3_its.c | 1322 ++++++++++++++++++++++++++++++++ | ||
| 82 | hw/intc/arm_gicv3_its_common.c | 7 +- | ||
| 83 | hw/intc/arm_gicv3_its_kvm.c | 2 +- | ||
| 84 | hw/intc/arm_gicv3_redist.c | 153 +++- | ||
| 85 | hw/misc/zynq_slcr.c | 31 +- | ||
| 86 | softmmu/qdev-monitor.c | 7 +- | ||
| 87 | target/arm/helper-a64.c | 1 + | ||
| 88 | target/arm/helper.c | 8 + | ||
| 89 | target/arm/kvm.c | 7 +- | ||
| 90 | target/arm/translate-a64.c | 255 +++--- | ||
| 91 | target/arm/translate.c | 21 + | ||
| 92 | hw/intc/meson.build | 1 + | ||
| 93 | tests/data/acpi/virt/IORT | Bin 0 -> 124 bytes | ||
| 94 | tests/data/acpi/virt/IORT.memhp | Bin 0 -> 124 bytes | ||
| 95 | tests/data/acpi/virt/IORT.numamem | Bin 0 -> 124 bytes | ||
| 96 | tests/data/acpi/virt/IORT.pxb | Bin 0 -> 124 bytes | ||
| 97 | 35 files changed, 2144 insertions(+), 210 deletions(-) | ||
| 98 | create mode 100644 hw/intc/arm_gicv3_its.c | ||
| 99 | create mode 100644 tests/data/acpi/virt/IORT | ||
| 100 | create mode 100644 tests/data/acpi/virt/IORT.memhp | ||
| 101 | create mode 100644 tests/data/acpi/virt/IORT.numamem | ||
| 102 | create mode 100644 tests/data/acpi/virt/IORT.pxb | ||
| 53 | 103 | ||
| 54 | include/hw/dma/pl080.h | 7 ++-- | ||
| 55 | include/hw/misc/arm_integrator_debug.h | 2 +- | ||
| 56 | include/hw/ssi/pl022.h | 5 ++- | ||
| 57 | target/arm/cpu.h | 17 ++++++++ | ||
| 58 | target/arm/internals.h | 6 +++ | ||
| 59 | accel/tcg/cpu-exec.c | 25 +++++++++--- | ||
| 60 | hw/arm/aspeed_ast2600.c | 2 +- | ||
| 61 | hw/arm/musca.c | 4 +- | ||
| 62 | hw/arm/npcm7xx.c | 8 ---- | ||
| 63 | hw/arm/xlnx-versal.c | 4 +- | ||
| 64 | hw/misc/arm_integrator_debug.c | 2 +- | ||
| 65 | hw/timer/arm_timer.c | 7 ++-- | ||
| 66 | target/arm/cpu.c | 4 ++ | ||
| 67 | target/arm/cpu64.c | 5 +++ | ||
| 68 | target/arm/helper-a64.c | 27 +++++++++++-- | ||
| 69 | target/arm/helper.c | 71 +++++++++++++++++++++++++++------- | ||
| 70 | target/arm/machine.c | 2 +- | ||
| 71 | target/arm/op_helper.c | 9 +---- | ||
| 72 | target/arm/translate-a64.c | 12 ++++++ | ||
| 73 | 19 files changed, 164 insertions(+), 55 deletions(-) | ||
| 74 | diff view generated by jsdifflib |