[PULL v2 00/11] target-arm queue
[PULL v2 00/54] target-arm queue
1
Massively slimmed down v2: MemTag broke bsd-user, and the npcm7xx
1
v1->v2: fix format-string errors on 32-bit hosts in xilinx csu dma model.
2
ethernet device failed 'make check' on big-endian hosts.
3
2
4
-- PMM
3
-- PMM
5
4
6
The following changes since commit 83339e21d05c824ebc9131d644f25c23d0e41ecf:
5
The following changes since commit 0436c55edf6b357ff56e2a5bf688df8636f83456:
7
6
8
Merge remote-tracking branch 'remotes/stefanha-gitlab/tags/block-pull-request' into staging (2021-02-10 15:42:20 +0000)
7
Merge remote-tracking branch 'remotes/bonzini-gitlab/tags/for-upstream' into staging (2021-03-08 13:51:41 +0000)
9
8
10
are available in the Git repository at:
9
are available in the Git repository at:
11
10
12
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210211-1
11
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210310
13
12
14
for you to fetch changes up to d3c1183ffeb71ca3a783eae3d7e1c51e71e8a621:
13
for you to fetch changes up to 81b3ddaf8772ec6f88d372e52f9b433cfa46bc46:
15
14
16
target/arm: Correctly initialize MDCR_EL2.HPMN (2021-02-11 19:48:09 +0000)
15
hw/timer/renesas_tmr: Fix use of uninitialized data in read_tcnt() (2021-03-10 13:54:51 +0000)
17
16
18
----------------------------------------------------------------
17
----------------------------------------------------------------
19
target-arm queue:
18
target-arm queue:
20
* Correctly initialize MDCR_EL2.HPMN
19
* Add new mps3-an547 board
21
* versal: Use nr_apu_cpus in favor of hard coding 2
20
* target/arm: Restrict v7A TCG cpus to TCG accel
22
* accel/tcg: Add URL of clang bug to comment about our workaround
21
* Implement a Xilinx CSU DMA model
23
* Add support for FEAT_DIT, Data Independent Timing
22
* hw/timer/renesas_tmr: Fix use of uninitialized data in read_tcnt()
24
* Remove GPIO from unimplemented NPCM7XX
25
* Fix SCR RES1 handling
26
* Don't migrate CPUARMState.features
27
23
28
----------------------------------------------------------------
24
----------------------------------------------------------------
29
Aaron Lindsay (1):
25
Peter Maydell (48):
30
target/arm: Don't migrate CPUARMState.features
26
clock: Add ClockEvent parameter to callbacks
27
clock: Add ClockPreUpdate callback event type
28
clock: Add clock_ns_to_ticks() function
29
hw/timer/npcm7xx_timer: Use new clock_ns_to_ticks()
30
hw/arm/armsse: Introduce SSE subsystem version property
31
hw/misc/iotkit-sysctl: Remove is_sse200 flag
32
hw/misc/iotkit-secctl.c: Implement SSE-300 PID register values
33
hw/misc/iotkit-sysinfo.c: Implement SSE-300 PID register values
34
hw/arm/armsse.c: Use correct SYS_CONFIG0 register value for SSE-300
35
hw/misc/iotkit-sysinfo.c: Implement SYS_CONFIG1 and IIDR
36
hw/timer/sse-counter: Model the SSE Subsystem System Counter
37
hw/timer/sse-timer: Model the SSE Subsystem System Timer
38
hw/misc/iotkit-sysctl: Add SSE-300 cases which match SSE-200 behaviour
39
hw/misc/iotkit-sysctl: Handle CPU_WAIT, NMI_ENABLE for SSE-300
40
hw/misc/iotkit-sysctl: Handle INITSVTOR* for SSE-300
41
hw/misc/iotkit-sysctl: Implement dummy version of SSE-300 PWRCTRL register
42
hw/misc/iotkit-sysctl: Handle SSE-300 changes to PDCM_PD_*_SENSE registers
43
hw/misc/iotkit-sysctl: Implement SSE-200 and SSE-300 PID register values
44
hw/arm/Kconfig: Move ARMSSE_CPUID and ARMSSE_MHU stanzas to hw/misc
45
hw/misc/sse-cpu-pwrctrl: Implement SSE-300 CPU<N>_PWRCTRL register block
46
hw/arm/armsse: Use an array for apb_ppc fields in the state structure
47
hw/arm/armsse: Add a define for number of IRQs used by the SSE itself
48
hw/arm/armsse: Add framework for data-driven device placement
49
hw/arm/armsse: Move dual-timer device into data-driven framework
50
hw/arm/armsse: Move watchdogs into data-driven framework
51
hw/arm/armsse: Move s32ktimer into data-driven framework
52
hw/arm/armsse: Move sysinfo register block into data-driven framework
53
hw/arm/armsse: Move sysctl register block into data-driven framework
54
hw/arm/armsse: Move PPUs into data-driven framework
55
hw/arm/armsse: Add missing SSE-200 SYS_PPU
56
hw/arm/armsse: Indirect irq_is_common[] through ARMSSEInfo
57
hw/arm/armsse: Add support for SSE variants with a system counter
58
hw/arm/armsse: Add support for TYPE_SSE_TIMER in ARMSSEDeviceInfo
59
hw/arm/armsse: Support variants with ARMSSE_CPU_PWRCTRL block
60
hw/arm/armsse: Add SSE-300 support
61
hw/arm/mps2-tz: Make UART overflow IRQ board-specific
62
hw/misc/mps2-fpgaio: Fold counters subsection into main vmstate
63
hw/misc/mps2-fpgaio: Support AN547 DBGCTRL register
64
hw/misc/mps2-scc: Implement changes for AN547
65
hw/arm/mps2-tz: Support running APB peripherals on different clock
66
hw/arm/mps2-tz: Make initsvtor0 setting board-specific
67
hw/arm/mps2-tz: Add new mps3-an547 board
68
docs/system/arm/mps2.rst: Document the new mps3-an547 board
69
tests/qtest/sse-timer-test: Add simple test of the SSE counter
70
tests/qtest/sse-timer-test: Test the system timer
71
tests/qtest/sse-timer-test: Test counter scaling changes
72
hw/timer/renesas_tmr: Prefix constants for CSS values with CSS_
73
hw/timer/renesas_tmr: Fix use of uninitialized data in read_tcnt()
31
74
32
Daniel Müller (1):
75
Philippe Mathieu-Daudé (1):
33
target/arm: Correctly initialize MDCR_EL2.HPMN
76
target/arm: Restrict v7A TCG cpus to TCG accel
34
77
35
Edgar E. Iglesias (1):
78
Xuzhou Cheng (5):
36
hw/arm: versal: Use nr_apu_cpus in favor of hard coding 2
79
hw/dma: Implement a Xilinx CSU DMA model
80
hw/arm: xlnx-zynqmp: Clean up coding convention issues
81
hw/arm: xlnx-zynqmp: Connect a Xilinx CSU DMA module for QSPI
82
hw/ssi: xilinx_spips: Clean up coding convention issues
83
hw/ssi: xilinx_spips: Remove DMA related dead codes from zynqmp_spips
37
84
38
Hao Wu (1):
85
docs/devel/clocks.rst | 71 ++-
39
hw/arm: Remove GPIO from unimplemented NPCM7XX
86
docs/system/arm/mps2.rst | 6 +-
87
include/hw/arm/armsse-version.h | 42 ++
88
include/hw/arm/armsse.h | 40 +-
89
include/hw/arm/xlnx-zynqmp.h | 5 +-
90
include/hw/clock.h | 63 ++-
91
include/hw/dma/xlnx_csu_dma.h | 52 ++
92
include/hw/misc/armsse-cpu-pwrctrl.h | 40 ++
93
include/hw/misc/iotkit-secctl.h | 2 +
94
include/hw/misc/iotkit-sysctl.h | 13 +-
95
include/hw/misc/iotkit-sysinfo.h | 2 +
96
include/hw/misc/mps2-fpgaio.h | 2 +
97
include/hw/qdev-clock.h | 17 +-
98
include/hw/ssi/xilinx_spips.h | 2 +-
99
include/hw/timer/sse-counter.h | 105 ++++
100
include/hw/timer/sse-timer.h | 53 ++
101
hw/adc/npcm7xx_adc.c | 2 +-
102
hw/arm/armsse.c | 1008 +++++++++++++++++++++++++---------
103
hw/arm/mps2-tz.c | 168 +++++-
104
hw/arm/xlnx-zynqmp.c | 21 +-
105
hw/char/cadence_uart.c | 4 +-
106
hw/char/ibex_uart.c | 4 +-
107
hw/char/pl011.c | 5 +-
108
hw/core/clock.c | 24 +-
109
hw/core/qdev-clock.c | 8 +-
110
hw/dma/xlnx_csu_dma.c | 745 +++++++++++++++++++++++++
111
hw/mips/cps.c | 2 +-
112
hw/misc/armsse-cpu-pwrctrl.c | 149 +++++
113
hw/misc/bcm2835_cprman.c | 23 +-
114
hw/misc/iotkit-secctl.c | 50 +-
115
hw/misc/iotkit-sysctl.c | 522 +++++++++++++++---
116
hw/misc/iotkit-sysinfo.c | 51 +-
117
hw/misc/mps2-fpgaio.c | 52 +-
118
hw/misc/mps2-scc.c | 15 +-
119
hw/misc/npcm7xx_clk.c | 26 +-
120
hw/misc/npcm7xx_pwm.c | 2 +-
121
hw/misc/zynq_slcr.c | 5 +-
122
hw/ssi/xilinx_spips.c | 33 +-
123
hw/timer/cmsdk-apb-dualtimer.c | 5 +-
124
hw/timer/cmsdk-apb-timer.c | 4 +-
125
hw/timer/npcm7xx_timer.c | 6 +-
126
hw/timer/renesas_tmr.c | 33 +-
127
hw/timer/sse-counter.c | 474 ++++++++++++++++
128
hw/timer/sse-timer.c | 470 ++++++++++++++++
129
hw/watchdog/cmsdk-apb-watchdog.c | 5 +-
130
target/arm/cpu.c | 335 -----------
131
target/arm/cpu_tcg.c | 318 +++++++++++
132
target/mips/cpu.c | 2 +-
133
tests/qtest/sse-timer-test.c | 240 ++++++++
134
MAINTAINERS | 7 +
135
hw/arm/Kconfig | 10 +-
136
hw/dma/Kconfig | 4 +
137
hw/dma/meson.build | 1 +
138
hw/misc/Kconfig | 9 +
139
hw/misc/meson.build | 1 +
140
hw/misc/trace-events | 4 +
141
hw/timer/Kconfig | 6 +
142
hw/timer/meson.build | 2 +
143
hw/timer/trace-events | 12 +
144
tests/qtest/meson.build | 1 +
145
60 files changed, 4537 insertions(+), 846 deletions(-)
146
create mode 100644 include/hw/arm/armsse-version.h
147
create mode 100644 include/hw/dma/xlnx_csu_dma.h
148
create mode 100644 include/hw/misc/armsse-cpu-pwrctrl.h
149
create mode 100644 include/hw/timer/sse-counter.h
150
create mode 100644 include/hw/timer/sse-timer.h
151
create mode 100644 hw/dma/xlnx_csu_dma.c
152
create mode 100644 hw/misc/armsse-cpu-pwrctrl.c
153
create mode 100644 hw/timer/sse-counter.c
154
create mode 100644 hw/timer/sse-timer.c
155
create mode 100644 tests/qtest/sse-timer-test.c
40
156
41
Mike Nawrocki (1):
42
target/arm: Fix SCR RES1 handling
43
44
Peter Maydell (2):
45
arm: Update infocenter.arm.com URLs
46
accel/tcg: Add URL of clang bug to comment about our workaround
47
48
Rebecca Cran (4):
49
target/arm: Add support for FEAT_DIT, Data Independent Timing
50
target/arm: Support AA32 DIT by moving PSTATE_SS from cpsr into env->pstate
51
target/arm: Set ID_AA64PFR0.DIT and ID_PFR0.DIT to 1 for "max" AA64 CPU
52
target/arm: Set ID_PFR0.DIT to 1 for "max" 32-bit CPU
53
54
include/hw/dma/pl080.h | 7 ++--
55
include/hw/misc/arm_integrator_debug.h | 2 +-
56
include/hw/ssi/pl022.h | 5 ++-
57
target/arm/cpu.h | 17 ++++++++
58
target/arm/internals.h | 6 +++
59
accel/tcg/cpu-exec.c | 25 +++++++++---
60
hw/arm/aspeed_ast2600.c | 2 +-
61
hw/arm/musca.c | 4 +-
62
hw/arm/npcm7xx.c | 8 ----
63
hw/arm/xlnx-versal.c | 4 +-
64
hw/misc/arm_integrator_debug.c | 2 +-
65
hw/timer/arm_timer.c | 7 ++--
66
target/arm/cpu.c | 4 ++
67
target/arm/cpu64.c | 5 +++
68
target/arm/helper-a64.c | 27 +++++++++++--
69
target/arm/helper.c | 71 +++++++++++++++++++++++++++-------
70
target/arm/machine.c | 2 +-
71
target/arm/op_helper.c | 9 +----
72
target/arm/translate-a64.c | 12 ++++++
73
19 files changed, 164 insertions(+), 55 deletions(-)
74
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

© 2016 - 2025 Red Hat, Inc.