[PULL v2 00/21] target-arm queue
[PULL v2 00/57] target-arm queue
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no changes to v1, except adding the CVE identifier to one of the commit
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Squashed in a trivial fix for 32-bit hosts:
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messages.
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--- a/target/arm/mve_helper.c
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+++ b/target/arm/mve_helper.c
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@@ -XXX,XX +XXX,XX @@ DO_LDAV(vmlsldavxsw, 4, int32_t, true, +=, -=)
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acc = EVENACC(acc, TO128(n[H##ESIZE(e + 1 * XCHG)] * \
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m[H##ESIZE(e)])); \
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} \
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- acc = int128_add(acc, 1 << 7); \
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+ acc = int128_add(acc, int128_make64(1 << 7)); \
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} \
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} \
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mve_advance_vpt(env); \
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-- PMM
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-- PMM
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The following changes since commit cf7ca7d5b9faca13f1f8e3ea92cfb2f741eb0c0e:
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The following changes since commit 53f306f316549d20c76886903181413d20842423:
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Merge remote-tracking branch 'remotes/stefanha-gitlab/tags/tracing-pull-request' into staging (2021-02-01 16:28:00 +0000)
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Merge remote-tracking branch 'remotes/ehabkost-gl/tags/x86-next-pull-request' into staging (2021-06-21 11:26:04 +0100)
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are available in the Git repository at:
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are available in the Git repository at:
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210203
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210624
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for you to fetch changes up to fd8f71b95da86f530aae3d02a14b0ccd9e024772:
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for you to fetch changes up to 90a76c6316cfe6416fc33814a838fb3928f746ee:
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hw/arm: Display CPU type in machine description (2021-02-03 10:15:51 +0000)
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docs/system: arm: Add nRF boards description (2021-06-24 14:58:48 +0100)
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----------------------------------------------------------------
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----------------------------------------------------------------
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target-arm queue:
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target-arm queue:
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* hw/intc/arm_gic: Allow to use QTest without crashing
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* Don't require 'virt' board to be compiled in for ACPI GHES code
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* hw/char/exynos4210_uart: Fix buffer size reporting with FIFO disabled
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* docs: Document which architecture extensions we emulate
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* hw/char/exynos4210_uart: Fix missing call to report ready for input
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* Fix bugs in M-profile FPCXT_NS accesses
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* hw/arm/smmuv3: Fix addr_mask for range-based invalidation
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* First slice of MVE patches
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* hw/ssi/imx_spi: Fix various minor bugs
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* Implement MTE3
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* hw/intc/arm_gic: Fix interrupt ID in GICD_SGIR register
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* docs/system: arm: Add nRF boards description
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* hw/arm: Add missing Kconfig dependencies
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* hw/arm: Display CPU type in machine description
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----------------------------------------------------------------
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----------------------------------------------------------------
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Bin Meng (5):
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Alexandre Iooss (1):
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hw/ssi: imx_spi: Use a macro for number of chip selects supported
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docs/system: arm: Add nRF boards description
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hw/ssi: imx_spi: Remove imx_spi_update_irq() in imx_spi_reset()
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hw/ssi: imx_spi: Round up the burst length to be multiple of 8
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hw/ssi: imx_spi: Correct the burst length > 32 bit transfer logic
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hw/ssi: imx_spi: Correct tx and rx fifo endianness
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Iris Johnson (2):
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Peter Collingbourne (1):
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hw/char/exynos4210_uart: Fix buffer size reporting with FIFO disabled
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target/arm: Implement MTE3
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hw/char/exynos4210_uart: Fix missing call to report ready for input
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Philippe Mathieu-Daudé (12):
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Peter Maydell (55):
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hw/intc/arm_gic: Allow to use QTest without crashing
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hw/acpi: Provide stub version of acpi_ghes_record_errors()
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hw/ssi: imx_spi: Remove pointless variable initialization
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hw/acpi: Provide function acpi_ghes_present()
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hw/ssi: imx_spi: Rework imx_spi_reset() to keep CONREG register value
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target/arm: Use acpi_ghes_present() to see if we report ACPI memory errors
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hw/ssi: imx_spi: Rework imx_spi_read() to handle block disabled
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docs/system/arm: Document which architecture extensions we emulate
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hw/ssi: imx_spi: Rework imx_spi_write() to handle block disabled
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target/arm/translate-vfp.c: Whitespace fixes
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hw/intc/arm_gic: Fix interrupt ID in GICD_SGIR register
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target/arm: Handle FPU being disabled in FPCXT_NS accesses
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hw/arm/stm32f405_soc: Add missing dependency on OR_IRQ
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target/arm: Don't NOCP fault for FPCXT_NS accesses
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hw/arm/exynos4210: Add missing dependency on OR_IRQ
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target/arm: Handle writeback in VLDR/VSTR sysreg with no memory access
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hw/arm/xlnx-versal: Versal SoC requires ZDMA
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target/arm: Factor FP context update code out into helper function
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hw/arm/xlnx-versal: Versal SoC requires ZynqMP peripherals
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target/arm: Split vfp_access_check() into A and M versions
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hw/net/can: ZynqMP CAN device requires PTIMER
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target/arm: Handle FPU check for FPCXT_NS insns via vfp_access_check_m()
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hw/arm: Display CPU type in machine description
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target/arm: Implement MVE VLDR/VSTR (non-widening forms)
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target/arm: Implement widening/narrowing MVE VLDR/VSTR insns
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target/arm: Implement MVE VCLZ
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target/arm: Implement MVE VCLS
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target/arm: Implement MVE VREV16, VREV32, VREV64
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target/arm: Implement MVE VMVN (register)
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target/arm: Implement MVE VABS
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target/arm: Implement MVE VNEG
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tcg: Make gen_dup_i32/i64() public as tcg_gen_dup_i32/i64
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target/arm: Implement MVE VDUP
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target/arm: Implement MVE VAND, VBIC, VORR, VORN, VEOR
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target/arm: Implement MVE VADD, VSUB, VMUL
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target/arm: Implement MVE VMULH
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target/arm: Implement MVE VRMULH
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target/arm: Implement MVE VMAX, VMIN
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target/arm: Implement MVE VABD
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target/arm: Implement MVE VHADD, VHSUB
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target/arm: Implement MVE VMULL
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target/arm: Implement MVE VMLALDAV
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target/arm: Implement MVE VMLSLDAV
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target/arm: Implement MVE VRMLALDAVH, VRMLSLDAVH
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target/arm: Implement MVE VADD (scalar)
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target/arm: Implement MVE VSUB, VMUL (scalar)
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target/arm: Implement MVE VHADD, VHSUB (scalar)
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target/arm: Implement MVE VBRSR
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target/arm: Implement MVE VPST
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target/arm: Implement MVE VQADD and VQSUB
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target/arm: Implement MVE VQDMULH and VQRDMULH (scalar)
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target/arm: Implement MVE VQDMULL scalar
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target/arm: Implement MVE VQDMULH, VQRDMULH (vector)
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target/arm: Implement MVE VQADD, VQSUB (vector)
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target/arm: Implement MVE VQSHL (vector)
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target/arm: Implement MVE VQRSHL
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target/arm: Implement MVE VSHL insn
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target/arm: Implement MVE VRSHL
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target/arm: Implement MVE VQDMLADH and VQRDMLADH
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target/arm: Implement MVE VQDMLSDH and VQRDMLSDH
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target/arm: Implement MVE VQDMULL (vector)
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target/arm: Implement MVE VRHADD
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target/arm: Implement MVE VADC, VSBC
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target/arm: Implement MVE VCADD
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target/arm: Implement MVE VHCADD
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target/arm: Implement MVE VADDV
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target/arm: Make VMOV scalar <-> gpreg beatwise for MVE
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Xuzhou Cheng (1):
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docs/system/arm/emulation.rst | 103 ++++
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hw/ssi: imx_spi: Disable chip selects when controller is disabled
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docs/system/arm/nrf.rst | 51 ++
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docs/system/target-arm.rst | 7 +
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include/hw/acpi/ghes.h | 9 +
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include/tcg/tcg-op.h | 8 +
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include/tcg/tcg.h | 1 -
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target/arm/helper-mve.h | 357 +++++++++++++
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target/arm/helper.h | 2 +
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target/arm/internals.h | 11 +
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target/arm/translate-a32.h | 3 +
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target/arm/translate.h | 10 +
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target/arm/m-nocp.decode | 24 +
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target/arm/mve.decode | 240 +++++++++
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target/arm/vfp.decode | 14 -
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hw/acpi/ghes-stub.c | 22 +
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hw/acpi/ghes.c | 17 +
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target/arm/cpu64.c | 2 +-
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target/arm/kvm64.c | 6 +-
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target/arm/mte_helper.c | 82 +--
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target/arm/mve_helper.c | 1160 +++++++++++++++++++++++++++++++++++++++++
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target/arm/translate-m-nocp.c | 550 +++++++++++++++++++
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target/arm/translate-mve.c | 759 +++++++++++++++++++++++++++
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target/arm/translate-vfp.c | 741 +++++++-------------------
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tcg/tcg-op-gvec.c | 20 +-
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MAINTAINERS | 1 +
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hw/acpi/meson.build | 6 +-
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target/arm/meson.build | 1 +
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27 files changed, 3578 insertions(+), 629 deletions(-)
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create mode 100644 docs/system/arm/emulation.rst
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create mode 100644 docs/system/arm/nrf.rst
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create mode 100644 target/arm/helper-mve.h
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create mode 100644 hw/acpi/ghes-stub.c
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create mode 100644 target/arm/mve_helper.c
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135
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Zenghui Yu (1):
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hw/arm/smmuv3: Fix addr_mask for range-based invalidation
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include/hw/ssi/imx_spi.h | 5 +-
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hw/arm/digic_boards.c | 2 +-
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hw/arm/microbit.c | 2 +-
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hw/arm/netduino2.c | 2 +-
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hw/arm/netduinoplus2.c | 2 +-
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hw/arm/orangepi.c | 2 +-
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hw/arm/smmuv3.c | 4 +-
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hw/arm/stellaris.c | 4 +-
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hw/char/exynos4210_uart.c | 7 ++-
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hw/intc/arm_gic.c | 5 +-
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hw/ssi/imx_spi.c | 153 +++++++++++++++++++++++++++++-----------------
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hw/Kconfig | 1 +
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hw/arm/Kconfig | 5 ++
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hw/dma/Kconfig | 3 +
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hw/dma/meson.build | 2 +-
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15 files changed, 130 insertions(+), 69 deletions(-)
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diff view generated by jsdifflib

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