[PULL 00/24] tcg patch queue
[PULL v2.5 00/27] tcg patch queue
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The following changes since commit 77f3804ab7ed94b471a14acb260e5aeacf26193f:
1
v2: Fix target/loongarch printf formats for vaddr
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Include two more reviewed patches.
2
3
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Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into staging (2021-02-02 16:47:51 +0000)
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This time with actual pull urls. :-/
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r~
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The following changes since commit db7aa99ef894e88fc5eedf02ca2579b8c344b2ec:
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Merge tag 'hw-misc-20250216' of https://github.com/philmd/qemu into staging (2025-02-16 20:48:06 -0500)
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are available in the Git repository at:
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are available in the Git repository at:
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https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20210202
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https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20250215-2
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for you to fetch changes up to 0c823e596877a30fd6c17a1ae9f98218a53055ea:
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for you to fetch changes up to a39bdd0f4ba96fcbb6b5bcb6e89591d2b24f52eb:
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tcg: Remove TCG_TARGET_CON_SET_H (2021-02-02 12:12:43 -1000)
19
tcg: Remove TCG_TARGET_HAS_{br,set}cond2 from riscv and loongarch64 (2025-02-17 09:52:07 -0800)
12
20
13
----------------------------------------------------------------
21
----------------------------------------------------------------
14
TCG backend constraints cleanup
22
tcg: Remove last traces of TCG_TARGET_NEED_POOL_LABELS
23
tcg: Cleanups after disallowing 64-on-32
24
tcg: Introduce constraint for zero register
25
tcg: Remove TCG_TARGET_HAS_{br,set}cond2 from riscv and loongarch64
26
tcg/i386: Use tcg_{high,unsigned}_cond in tcg_out_brcond2
27
linux-user: Move TARGET_SA_RESTORER out of generic/signal.h
28
linux-user: Fix alignment when unmapping excess reservation
29
target/sparc: Fix register selection for all F*TOx and FxTO* instructions
30
target/sparc: Fix gdbstub incorrectly handling registers f32-f62
31
target/sparc: fake UltraSPARC T1 PCR and PIC registers
15
32
16
----------------------------------------------------------------
33
----------------------------------------------------------------
17
Richard Henderson (24):
34
Andreas Schwab (1):
18
tcg/tci: Drop L and S constraints
35
linux-user: Move TARGET_SA_RESTORER out of generic/signal.h
19
tcg/tci: Remove TCG_TARGET_HAS_* ifdefs
20
tcg/i386: Move constraint type check to tcg_target_const_match
21
tcg/i386: Tidy register constraint definitions
22
tcg/i386: Split out target constraints to tcg-target-con-str.h
23
tcg/arm: Split out target constraints to tcg-target-con-str.h
24
tcg/aarch64: Split out target constraints to tcg-target-con-str.h
25
tcg/ppc: Split out target constraints to tcg-target-con-str.h
26
tcg/tci: Split out target constraints to tcg-target-con-str.h
27
tcg/mips: Split out target constraints to tcg-target-con-str.h
28
tcg/riscv: Split out target constraints to tcg-target-con-str.h
29
tcg/s390: Split out target constraints to tcg-target-con-str.h
30
tcg/sparc: Split out target constraints to tcg-target-con-str.h
31
tcg: Remove TCG_TARGET_CON_STR_H
32
tcg/i386: Split out constraint sets to tcg-target-con-set.h
33
tcg/aarch64: Split out constraint sets to tcg-target-con-set.h
34
tcg/arm: Split out constraint sets to tcg-target-con-set.h
35
tcg/mips: Split out constraint sets to tcg-target-con-set.h
36
tcg/ppc: Split out constraint sets to tcg-target-con-set.h
37
tcg/riscv: Split out constraint sets to tcg-target-con-set.h
38
tcg/s390: Split out constraint sets to tcg-target-con-set.h
39
tcg/sparc: Split out constraint sets to tcg-target-con-set.h
40
tcg/tci: Split out constraint sets to tcg-target-con-set.h
41
tcg: Remove TCG_TARGET_CON_SET_H
42
36
43
tcg/aarch64/tcg-target-con-set.h | 36 ++++
37
Artyom Tarasenko (1):
44
tcg/aarch64/tcg-target-con-str.h | 24 +++
38
target/sparc: fake UltraSPARC T1 PCR and PIC registers
45
tcg/arm/tcg-target-con-set.h | 35 ++++
46
tcg/arm/tcg-target-con-str.h | 22 +++
47
tcg/i386/tcg-target-con-set.h | 55 ++++++
48
tcg/i386/tcg-target-con-str.h | 33 ++++
49
tcg/mips/tcg-target-con-set.h | 36 ++++
50
tcg/mips/tcg-target-con-str.h | 24 +++
51
tcg/ppc/tcg-target-con-set.h | 42 +++++
52
tcg/ppc/tcg-target-con-str.h | 30 ++++
53
tcg/riscv/tcg-target-con-set.h | 30 ++++
54
tcg/riscv/tcg-target-con-str.h | 21 +++
55
tcg/s390/tcg-target-con-set.h | 29 ++++
56
tcg/s390/tcg-target-con-str.h | 28 +++
57
tcg/sparc/tcg-target-con-set.h | 32 ++++
58
tcg/sparc/tcg-target-con-str.h | 23 +++
59
tcg/sparc/tcg-target.h | 4 -
60
tcg/tci/tcg-target-con-set.h | 25 +++
61
tcg/tci/tcg-target-con-str.h | 11 ++
62
tcg/tcg.c | 136 +++++++++++++--
63
tcg/aarch64/tcg-target.c.inc | 137 ++++-----------
64
tcg/arm/tcg-target.c.inc | 168 ++++++------------
65
tcg/i386/tcg-target.c.inc | 317 +++++++++++-----------------------
66
tcg/mips/tcg-target.c.inc | 173 ++++++-------------
67
tcg/ppc/tcg-target.c.inc | 209 ++++++++---------------
68
tcg/riscv/tcg-target.c.inc | 135 ++++-----------
69
tcg/s390/tcg-target.c.inc | 174 +++++++------------
70
tcg/sparc/tcg-target.c.inc | 156 ++++++-----------
71
tcg/tci/tcg-target.c.inc | 359 ++++++++++++++-------------------------
72
29 files changed, 1244 insertions(+), 1260 deletions(-)
73
create mode 100644 tcg/aarch64/tcg-target-con-set.h
74
create mode 100644 tcg/aarch64/tcg-target-con-str.h
75
create mode 100644 tcg/arm/tcg-target-con-set.h
76
create mode 100644 tcg/arm/tcg-target-con-str.h
77
create mode 100644 tcg/i386/tcg-target-con-set.h
78
create mode 100644 tcg/i386/tcg-target-con-str.h
79
create mode 100644 tcg/mips/tcg-target-con-set.h
80
create mode 100644 tcg/mips/tcg-target-con-str.h
81
create mode 100644 tcg/ppc/tcg-target-con-set.h
82
create mode 100644 tcg/ppc/tcg-target-con-str.h
83
create mode 100644 tcg/riscv/tcg-target-con-set.h
84
create mode 100644 tcg/riscv/tcg-target-con-str.h
85
create mode 100644 tcg/s390/tcg-target-con-set.h
86
create mode 100644 tcg/s390/tcg-target-con-str.h
87
create mode 100644 tcg/sparc/tcg-target-con-set.h
88
create mode 100644 tcg/sparc/tcg-target-con-str.h
89
create mode 100644 tcg/tci/tcg-target-con-set.h
90
create mode 100644 tcg/tci/tcg-target-con-str.h
91
39
40
Fabiano Rosas (1):
41
elfload: Fix alignment when unmapping excess reservation
42
43
Mikael Szreder (2):
44
target/sparc: Fix register selection for all F*TOx and FxTO* instructions
45
target/sparc: Fix gdbstub incorrectly handling registers f32-f62
46
47
Richard Henderson (22):
48
tcg: Remove last traces of TCG_TARGET_NEED_POOL_LABELS
49
tcg: Remove TCG_OVERSIZED_GUEST
50
tcg: Drop support for two address registers in gen_ldst
51
tcg: Merge INDEX_op_qemu_*_{a32,a64}_*
52
tcg/arm: Drop addrhi from prepare_host_addr
53
tcg/i386: Drop addrhi from prepare_host_addr
54
tcg/mips: Drop addrhi from prepare_host_addr
55
tcg/ppc: Drop addrhi from prepare_host_addr
56
tcg: Replace addr{lo,hi}_reg with addr_reg in TCGLabelQemuLdst
57
plugins: Fix qemu_plugin_read_memory_vaddr parameters
58
accel/tcg: Fix tlb_set_page_with_attrs, tlb_set_page
59
target/loongarch: Use VADDR_PRIx for logging pc_next
60
include/exec: Change vaddr to uintptr_t
61
include/exec: Use uintptr_t in CPUTLBEntry
62
tcg: Introduce the 'z' constraint for a hardware zero register
63
tcg/aarch64: Use 'z' constraint
64
tcg/loongarch64: Use 'z' constraint
65
tcg/mips: Use 'z' constraint
66
tcg/riscv: Use 'z' constraint
67
tcg/sparc64: Use 'z' constraint
68
tcg/i386: Use tcg_{high,unsigned}_cond in tcg_out_brcond2
69
tcg: Remove TCG_TARGET_HAS_{br,set}cond2 from riscv and loongarch64
70
71
include/exec/tlb-common.h | 10 +-
72
include/exec/vaddr.h | 16 +-
73
include/qemu/atomic.h | 18 +-
74
include/tcg/oversized-guest.h | 23 ---
75
include/tcg/tcg-opc.h | 28 +--
76
include/tcg/tcg.h | 3 +-
77
linux-user/aarch64/target_signal.h | 2 +
78
linux-user/arm/target_signal.h | 2 +
79
linux-user/generic/signal.h | 1 -
80
linux-user/i386/target_signal.h | 2 +
81
linux-user/m68k/target_signal.h | 1 +
82
linux-user/microblaze/target_signal.h | 2 +
83
linux-user/ppc/target_signal.h | 2 +
84
linux-user/s390x/target_signal.h | 2 +
85
linux-user/sh4/target_signal.h | 2 +
86
linux-user/x86_64/target_signal.h | 2 +
87
linux-user/xtensa/target_signal.h | 2 +
88
tcg/aarch64/tcg-target-con-set.h | 12 +-
89
tcg/aarch64/tcg-target.h | 2 +
90
tcg/loongarch64/tcg-target-con-set.h | 15 +-
91
tcg/loongarch64/tcg-target-con-str.h | 1 -
92
tcg/loongarch64/tcg-target-has.h | 2 -
93
tcg/loongarch64/tcg-target.h | 2 +
94
tcg/mips/tcg-target-con-set.h | 26 +--
95
tcg/mips/tcg-target-con-str.h | 1 -
96
tcg/mips/tcg-target.h | 2 +
97
tcg/riscv/tcg-target-con-set.h | 10 +-
98
tcg/riscv/tcg-target-con-str.h | 1 -
99
tcg/riscv/tcg-target-has.h | 2 -
100
tcg/riscv/tcg-target.h | 2 +
101
tcg/sparc64/tcg-target-con-set.h | 12 +-
102
tcg/sparc64/tcg-target-con-str.h | 1 -
103
tcg/sparc64/tcg-target.h | 3 +-
104
tcg/tci/tcg-target.h | 1 -
105
accel/tcg/cputlb.c | 32 +---
106
accel/tcg/tcg-all.c | 9 +-
107
linux-user/elfload.c | 4 +-
108
plugins/api.c | 2 +-
109
target/arm/ptw.c | 34 ----
110
target/loongarch/tcg/translate.c | 2 +-
111
target/riscv/cpu_helper.c | 13 +-
112
target/sparc/gdbstub.c | 18 +-
113
target/sparc/translate.c | 19 +++
114
tcg/optimize.c | 21 +--
115
tcg/tcg-op-ldst.c | 103 +++--------
116
tcg/tcg.c | 97 +++++------
117
tcg/tci.c | 119 +++----------
118
docs/devel/multi-thread-tcg.rst | 1 -
119
docs/devel/tcg-ops.rst | 4 +-
120
target/loongarch/tcg/insn_trans/trans_atomic.c.inc | 2 +-
121
target/sparc/insns.decode | 19 ++-
122
tcg/aarch64/tcg-target.c.inc | 86 ++++------
123
tcg/arm/tcg-target.c.inc | 114 ++++---------
124
tcg/i386/tcg-target.c.inc | 190 +++++----------------
125
tcg/loongarch64/tcg-target.c.inc | 72 +++-----
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tcg/mips/tcg-target.c.inc | 169 ++++++------------
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tcg/ppc/tcg-target.c.inc | 164 +++++-------------
128
tcg/riscv/tcg-target.c.inc | 56 +++---
129
tcg/s390x/tcg-target.c.inc | 40 ++---
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tcg/sparc64/tcg-target.c.inc | 45 ++---
131
tcg/tci/tcg-target.c.inc | 60 ++-----
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61 files changed, 548 insertions(+), 1160 deletions(-)
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delete mode 100644 include/tcg/oversized-guest.h
diff view generated by jsdifflib
[PULL 01/24] tcg/tci: Drop L and S constraints
Deleted patch
1
These are identical to the 'r' constraint.
2
1
3
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
---
6
tcg/tci/tcg-target.c.inc | 10 ++++------
7
1 file changed, 4 insertions(+), 6 deletions(-)
8
9
diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
10
index XXXXXXX..XXXXXXX 100644
11
--- a/tcg/tci/tcg-target.c.inc
12
+++ b/tcg/tci/tcg-target.c.inc
13
@@ -XXX,XX +XXX,XX @@
14
# define R64 "r"
15
#endif
16
#if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
17
-# define L "L", "L"
18
-# define S "S", "S"
19
+# define L "r", "r"
20
+# define S "r", "r"
21
#else
22
-# define L "L"
23
-# define S "S"
24
+# define L "r"
25
+# define S "r"
26
#endif
27
28
/* TODO: documentation. */
29
@@ -XXX,XX +XXX,XX @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
30
{
31
switch (*ct_str++) {
32
case 'r':
33
- case 'L': /* qemu_ld constraint */
34
- case 'S': /* qemu_st constraint */
35
ct->regs = BIT(TCG_TARGET_NB_REGS) - 1;
36
break;
37
default:
38
--
39
2.25.1
40
41
diff view generated by jsdifflib
[PULL 02/24] tcg/tci: Remove TCG_TARGET_HAS_* ifdefs
Deleted patch
1
The opcodes always exist, regardless of whether or not they
2
are enabled. Remove the unnecessary ifdefs.
3
1
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
---
6
tcg/tci/tcg-target.c.inc | 82 ----------------------------------------
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1 file changed, 82 deletions(-)
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9
diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
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index XXXXXXX..XXXXXXX 100644
11
--- a/tcg/tci/tcg-target.c.inc
12
+++ b/tcg/tci/tcg-target.c.inc
13
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef tcg_target_op_defs[] = {
14
{ INDEX_op_add_i32, { R, RI, RI } },
15
{ INDEX_op_sub_i32, { R, RI, RI } },
16
{ INDEX_op_mul_i32, { R, RI, RI } },
17
-#if TCG_TARGET_HAS_div_i32
18
{ INDEX_op_div_i32, { R, R, R } },
19
{ INDEX_op_divu_i32, { R, R, R } },
20
{ INDEX_op_rem_i32, { R, R, R } },
21
{ INDEX_op_remu_i32, { R, R, R } },
22
-#elif TCG_TARGET_HAS_div2_i32
23
- { INDEX_op_div2_i32, { R, R, "0", "1", R } },
24
- { INDEX_op_divu2_i32, { R, R, "0", "1", R } },
25
-#endif
26
/* TODO: Does R, RI, RI result in faster code than R, R, RI?
27
If both operands are constants, we can optimize. */
28
{ INDEX_op_and_i32, { R, RI, RI } },
29
-#if TCG_TARGET_HAS_andc_i32
30
{ INDEX_op_andc_i32, { R, RI, RI } },
31
-#endif
32
-#if TCG_TARGET_HAS_eqv_i32
33
{ INDEX_op_eqv_i32, { R, RI, RI } },
34
-#endif
35
-#if TCG_TARGET_HAS_nand_i32
36
{ INDEX_op_nand_i32, { R, RI, RI } },
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-#endif
38
-#if TCG_TARGET_HAS_nor_i32
39
{ INDEX_op_nor_i32, { R, RI, RI } },
40
-#endif
41
{ INDEX_op_or_i32, { R, RI, RI } },
42
-#if TCG_TARGET_HAS_orc_i32
43
{ INDEX_op_orc_i32, { R, RI, RI } },
44
-#endif
45
{ INDEX_op_xor_i32, { R, RI, RI } },
46
{ INDEX_op_shl_i32, { R, RI, RI } },
47
{ INDEX_op_shr_i32, { R, RI, RI } },
48
{ INDEX_op_sar_i32, { R, RI, RI } },
49
-#if TCG_TARGET_HAS_rot_i32
50
{ INDEX_op_rotl_i32, { R, RI, RI } },
51
{ INDEX_op_rotr_i32, { R, RI, RI } },
52
-#endif
53
-#if TCG_TARGET_HAS_deposit_i32
54
{ INDEX_op_deposit_i32, { R, "0", R } },
55
-#endif
56
57
{ INDEX_op_brcond_i32, { R, RI } },
58
59
{ INDEX_op_setcond_i32, { R, R, RI } },
60
-#if TCG_TARGET_REG_BITS == 64
61
{ INDEX_op_setcond_i64, { R, R, RI } },
62
-#endif /* TCG_TARGET_REG_BITS == 64 */
63
64
-#if TCG_TARGET_REG_BITS == 32
65
/* TODO: Support R, R, R, R, RI, RI? Will it be faster? */
66
{ INDEX_op_add2_i32, { R, R, R, R, R, R } },
67
{ INDEX_op_sub2_i32, { R, R, R, R, R, R } },
68
{ INDEX_op_brcond2_i32, { R, R, RI, RI } },
69
{ INDEX_op_mulu2_i32, { R, R, R, R } },
70
{ INDEX_op_setcond2_i32, { R, R, R, RI, RI } },
71
-#endif
72
73
-#if TCG_TARGET_HAS_not_i32
74
{ INDEX_op_not_i32, { R, R } },
75
-#endif
76
-#if TCG_TARGET_HAS_neg_i32
77
{ INDEX_op_neg_i32, { R, R } },
78
-#endif
79
80
-#if TCG_TARGET_REG_BITS == 64
81
{ INDEX_op_ld8u_i64, { R, R } },
82
{ INDEX_op_ld8s_i64, { R, R } },
83
{ INDEX_op_ld16u_i64, { R, R } },
84
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef tcg_target_op_defs[] = {
85
{ INDEX_op_add_i64, { R, RI, RI } },
86
{ INDEX_op_sub_i64, { R, RI, RI } },
87
{ INDEX_op_mul_i64, { R, RI, RI } },
88
-#if TCG_TARGET_HAS_div_i64
89
{ INDEX_op_div_i64, { R, R, R } },
90
{ INDEX_op_divu_i64, { R, R, R } },
91
{ INDEX_op_rem_i64, { R, R, R } },
92
{ INDEX_op_remu_i64, { R, R, R } },
93
-#elif TCG_TARGET_HAS_div2_i64
94
- { INDEX_op_div2_i64, { R, R, "0", "1", R } },
95
- { INDEX_op_divu2_i64, { R, R, "0", "1", R } },
96
-#endif
97
{ INDEX_op_and_i64, { R, RI, RI } },
98
-#if TCG_TARGET_HAS_andc_i64
99
{ INDEX_op_andc_i64, { R, RI, RI } },
100
-#endif
101
-#if TCG_TARGET_HAS_eqv_i64
102
{ INDEX_op_eqv_i64, { R, RI, RI } },
103
-#endif
104
-#if TCG_TARGET_HAS_nand_i64
105
{ INDEX_op_nand_i64, { R, RI, RI } },
106
-#endif
107
-#if TCG_TARGET_HAS_nor_i64
108
{ INDEX_op_nor_i64, { R, RI, RI } },
109
-#endif
110
{ INDEX_op_or_i64, { R, RI, RI } },
111
-#if TCG_TARGET_HAS_orc_i64
112
{ INDEX_op_orc_i64, { R, RI, RI } },
113
-#endif
114
{ INDEX_op_xor_i64, { R, RI, RI } },
115
{ INDEX_op_shl_i64, { R, RI, RI } },
116
{ INDEX_op_shr_i64, { R, RI, RI } },
117
{ INDEX_op_sar_i64, { R, RI, RI } },
118
-#if TCG_TARGET_HAS_rot_i64
119
{ INDEX_op_rotl_i64, { R, RI, RI } },
120
{ INDEX_op_rotr_i64, { R, RI, RI } },
121
-#endif
122
-#if TCG_TARGET_HAS_deposit_i64
123
{ INDEX_op_deposit_i64, { R, "0", R } },
124
-#endif
125
{ INDEX_op_brcond_i64, { R, RI } },
126
127
-#if TCG_TARGET_HAS_ext8s_i64
128
{ INDEX_op_ext8s_i64, { R, R } },
129
-#endif
130
-#if TCG_TARGET_HAS_ext16s_i64
131
{ INDEX_op_ext16s_i64, { R, R } },
132
-#endif
133
-#if TCG_TARGET_HAS_ext32s_i64
134
{ INDEX_op_ext32s_i64, { R, R } },
135
-#endif
136
-#if TCG_TARGET_HAS_ext8u_i64
137
{ INDEX_op_ext8u_i64, { R, R } },
138
-#endif
139
-#if TCG_TARGET_HAS_ext16u_i64
140
{ INDEX_op_ext16u_i64, { R, R } },
141
-#endif
142
-#if TCG_TARGET_HAS_ext32u_i64
143
{ INDEX_op_ext32u_i64, { R, R } },
144
-#endif
145
{ INDEX_op_ext_i32_i64, { R, R } },
146
{ INDEX_op_extu_i32_i64, { R, R } },
147
-#if TCG_TARGET_HAS_bswap16_i64
148
{ INDEX_op_bswap16_i64, { R, R } },
149
-#endif
150
-#if TCG_TARGET_HAS_bswap32_i64
151
{ INDEX_op_bswap32_i64, { R, R } },
152
-#endif
153
-#if TCG_TARGET_HAS_bswap64_i64
154
{ INDEX_op_bswap64_i64, { R, R } },
155
-#endif
156
-#if TCG_TARGET_HAS_not_i64
157
{ INDEX_op_not_i64, { R, R } },
158
-#endif
159
-#if TCG_TARGET_HAS_neg_i64
160
{ INDEX_op_neg_i64, { R, R } },
161
-#endif
162
-#endif /* TCG_TARGET_REG_BITS == 64 */
163
164
{ INDEX_op_qemu_ld_i32, { R, L } },
165
{ INDEX_op_qemu_ld_i64, { R64, L } },
166
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef tcg_target_op_defs[] = {
167
{ INDEX_op_qemu_st_i32, { R, S } },
168
{ INDEX_op_qemu_st_i64, { R64, S } },
169
170
-#if TCG_TARGET_HAS_ext8s_i32
171
{ INDEX_op_ext8s_i32, { R, R } },
172
-#endif
173
-#if TCG_TARGET_HAS_ext16s_i32
174
{ INDEX_op_ext16s_i32, { R, R } },
175
-#endif
176
-#if TCG_TARGET_HAS_ext8u_i32
177
{ INDEX_op_ext8u_i32, { R, R } },
178
-#endif
179
-#if TCG_TARGET_HAS_ext16u_i32
180
{ INDEX_op_ext16u_i32, { R, R } },
181
-#endif
182
183
-#if TCG_TARGET_HAS_bswap16_i32
184
{ INDEX_op_bswap16_i32, { R, R } },
185
-#endif
186
-#if TCG_TARGET_HAS_bswap32_i32
187
{ INDEX_op_bswap32_i32, { R, R } },
188
-#endif
189
190
{ INDEX_op_mb, { } },
191
{ -1 },
192
--
193
2.25.1
194
195
diff view generated by jsdifflib
[PULL 03/24] tcg/i386: Move constraint type check to tcg_target_const_match
Deleted patch
1
Rather than check the type when filling in the constraint,
2
check it when matching the constant. This removes the only
3
use of the type argument to target_parse_constraint.
4
1
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
---
8
tcg/i386/tcg-target.c.inc | 28 +++++++++++++++++-----------
9
1 file changed, 17 insertions(+), 11 deletions(-)
10
11
diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
12
index XXXXXXX..XXXXXXX 100644
13
--- a/tcg/i386/tcg-target.c.inc
14
+++ b/tcg/i386/tcg-target.c.inc
15
@@ -XXX,XX +XXX,XX @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
16
break;
17
18
case 'e':
19
- ct->ct |= (type == TCG_TYPE_I32 ? TCG_CT_CONST : TCG_CT_CONST_S32);
20
+ ct->ct |= TCG_CT_CONST_S32;
21
break;
22
case 'Z':
23
- ct->ct |= (type == TCG_TYPE_I32 ? TCG_CT_CONST : TCG_CT_CONST_U32);
24
+ ct->ct |= TCG_CT_CONST_U32;
25
break;
26
case 'I':
27
- ct->ct |= (type == TCG_TYPE_I32 ? TCG_CT_CONST : TCG_CT_CONST_I32);
28
+ ct->ct |= TCG_CT_CONST_I32;
29
break;
30
31
default:
32
@@ -XXX,XX +XXX,XX @@ static inline int tcg_target_const_match(tcg_target_long val, TCGType type,
33
if (ct & TCG_CT_CONST) {
34
return 1;
35
}
36
- if ((ct & TCG_CT_CONST_S32) && val == (int32_t)val) {
37
- return 1;
38
- }
39
- if ((ct & TCG_CT_CONST_U32) && val == (uint32_t)val) {
40
- return 1;
41
- }
42
- if ((ct & TCG_CT_CONST_I32) && ~val == (int32_t)~val) {
43
- return 1;
44
+ if (type == TCG_TYPE_I32) {
45
+ if (ct & (TCG_CT_CONST_S32 | TCG_CT_CONST_U32 | TCG_CT_CONST_I32)) {
46
+ return 1;
47
+ }
48
+ } else {
49
+ if ((ct & TCG_CT_CONST_S32) && val == (int32_t)val) {
50
+ return 1;
51
+ }
52
+ if ((ct & TCG_CT_CONST_U32) && val == (uint32_t)val) {
53
+ return 1;
54
+ }
55
+ if ((ct & TCG_CT_CONST_I32) && ~val == (int32_t)~val) {
56
+ return 1;
57
+ }
58
}
59
if ((ct & TCG_CT_CONST_WSZ) && val == (type == TCG_TYPE_I32 ? 32 : 64)) {
60
return 1;
61
--
62
2.25.1
63
64
diff view generated by jsdifflib
[PULL 04/24] tcg/i386: Tidy register constraint definitions
Deleted patch
1
Create symbolic constants for all low-byte-addressable
2
and second-byte-addressable registers. Create a symbol
3
for the registers that need reserving for softmmu.
4
1
5
There is no functional change for 's', as this letter is
6
only used for i386. The BYTEL name is correct for the
7
action we wish from the constraint.
8
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
11
---
12
tcg/i386/tcg-target.c.inc | 40 +++++++++++++++++++--------------------
13
1 file changed, 20 insertions(+), 20 deletions(-)
14
15
diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
16
index XXXXXXX..XXXXXXX 100644
17
--- a/tcg/i386/tcg-target.c.inc
18
+++ b/tcg/i386/tcg-target.c.inc
19
@@ -XXX,XX +XXX,XX @@ static const int tcg_target_call_oarg_regs[] = {
20
# define TCG_REG_L1 TCG_REG_EDX
21
#endif
22
23
+#define ALL_BYTEH_REGS 0x0000000fu
24
+#if TCG_TARGET_REG_BITS == 64
25
+# define ALL_GENERAL_REGS 0x0000ffffu
26
+# define ALL_VECTOR_REGS 0xffff0000u
27
+# define ALL_BYTEL_REGS ALL_GENERAL_REGS
28
+#else
29
+# define ALL_GENERAL_REGS 0x000000ffu
30
+# define ALL_VECTOR_REGS 0x00ff0000u
31
+# define ALL_BYTEL_REGS ALL_BYTEH_REGS
32
+#endif
33
+#ifdef CONFIG_SOFTMMU
34
+# define SOFTMMU_RESERVE_REGS ((1 << TCG_REG_L0) | (1 << TCG_REG_L1))
35
+#else
36
+# define SOFTMMU_RESERVE_REGS 0
37
+#endif
38
+
39
/* The host compiler should supply <cpuid.h> to enable runtime features
40
detection, as we're not going to go so far as our own inline assembly.
41
If not available, default values will be assumed. */
42
@@ -XXX,XX +XXX,XX @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
43
return true;
44
}
45
46
-#if TCG_TARGET_REG_BITS == 64
47
-#define ALL_GENERAL_REGS 0x0000ffffu
48
-#define ALL_VECTOR_REGS 0xffff0000u
49
-#else
50
-#define ALL_GENERAL_REGS 0x000000ffu
51
-#define ALL_VECTOR_REGS 0x00ff0000u
52
-#endif
53
-
54
/* parse target specific constraints */
55
static const char *target_parse_constraint(TCGArgConstraint *ct,
56
const char *ct_str, TCGType type)
57
@@ -XXX,XX +XXX,XX @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
58
break;
59
case 'q':
60
/* A register that can be used as a byte operand. */
61
- ct->regs = TCG_TARGET_REG_BITS == 64 ? 0xffff : 0xf;
62
+ ct->regs |= ALL_BYTEL_REGS;
63
break;
64
case 'Q':
65
/* A register with an addressable second byte (e.g. %ah). */
66
- ct->regs = 0xf;
67
+ ct->regs |= ALL_BYTEH_REGS;
68
break;
69
case 'r':
70
/* A general register. */
71
@@ -XXX,XX +XXX,XX @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
72
73
case 'L':
74
/* qemu_ld/st data+address constraint */
75
- ct->regs = TCG_TARGET_REG_BITS == 64 ? 0xffff : 0xff;
76
-#ifdef CONFIG_SOFTMMU
77
- tcg_regset_reset_reg(ct->regs, TCG_REG_L0);
78
- tcg_regset_reset_reg(ct->regs, TCG_REG_L1);
79
-#endif
80
+ ct->regs |= ALL_GENERAL_REGS & ~SOFTMMU_RESERVE_REGS;
81
break;
82
case 's':
83
/* qemu_st8_i32 data constraint */
84
- ct->regs = 0xf;
85
-#ifdef CONFIG_SOFTMMU
86
- tcg_regset_reset_reg(ct->regs, TCG_REG_L0);
87
- tcg_regset_reset_reg(ct->regs, TCG_REG_L1);
88
-#endif
89
+ ct->regs |= ALL_BYTEL_REGS & ~SOFTMMU_RESERVE_REGS;
90
break;
91
92
case 'e':
93
--
94
2.25.1
95
96
diff view generated by jsdifflib
[PULL 05/24] tcg/i386: Split out target constraints to tcg-target-con-str.h
Deleted patch
1
This eliminates the target-specific function target_parse_constraint
2
and folds it into the single caller, process_op_defs. Since this is
3
done directly into the switch statement, duplicates are compilation
4
errors rather than silently ignored at runtime.
5
1
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
---
9
tcg/i386/tcg-target-con-str.h | 33 +++++++++++++++++
10
tcg/i386/tcg-target.h | 1 +
11
tcg/tcg.c | 33 ++++++++++++++---
12
tcg/i386/tcg-target.c.inc | 69 -----------------------------------
13
4 files changed, 62 insertions(+), 74 deletions(-)
14
create mode 100644 tcg/i386/tcg-target-con-str.h
15
16
diff --git a/tcg/i386/tcg-target-con-str.h b/tcg/i386/tcg-target-con-str.h
17
new file mode 100644
18
index XXXXXXX..XXXXXXX
19
--- /dev/null
20
+++ b/tcg/i386/tcg-target-con-str.h
21
@@ -XXX,XX +XXX,XX @@
22
+/* SPDX-License-Identifier: MIT */
23
+/*
24
+ * Define i386 target-specific operand constraints.
25
+ * Copyright (c) 2021 Linaro
26
+ *
27
+ */
28
+
29
+/*
30
+ * Define constraint letters for register sets:
31
+ * REGS(letter, register_mask)
32
+ */
33
+REGS('a', 1u << TCG_REG_EAX)
34
+REGS('b', 1u << TCG_REG_EBX)
35
+REGS('c', 1u << TCG_REG_ECX)
36
+REGS('d', 1u << TCG_REG_EDX)
37
+REGS('S', 1u << TCG_REG_ESI)
38
+REGS('D', 1u << TCG_REG_EDI)
39
+
40
+REGS('r', ALL_GENERAL_REGS)
41
+REGS('x', ALL_VECTOR_REGS)
42
+REGS('q', ALL_BYTEL_REGS) /* regs that can be used as a byte operand */
43
+REGS('Q', ALL_BYTEH_REGS) /* regs with a second byte (e.g. %ah) */
44
+REGS('L', ALL_GENERAL_REGS & ~SOFTMMU_RESERVE_REGS) /* qemu_ld/st */
45
+REGS('s', ALL_BYTEL_REGS & ~SOFTMMU_RESERVE_REGS) /* qemu_st8_i32 data */
46
+
47
+/*
48
+ * Define constraint letters for constants:
49
+ * CONST(letter, TCG_CT_CONST_* bit set)
50
+ */
51
+CONST('e', TCG_CT_CONST_S32)
52
+CONST('I', TCG_CT_CONST_I32)
53
+CONST('W', TCG_CT_CONST_WSZ)
54
+CONST('Z', TCG_CT_CONST_U32)
55
diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h
56
index XXXXXXX..XXXXXXX 100644
57
--- a/tcg/i386/tcg-target.h
58
+++ b/tcg/i386/tcg-target.h
59
@@ -XXX,XX +XXX,XX @@ static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_rx,
60
#define TCG_TARGET_NEED_LDST_LABELS
61
#endif
62
#define TCG_TARGET_NEED_POOL_LABELS
63
+#define TCG_TARGET_CON_STR_H
64
65
#endif
66
diff --git a/tcg/tcg.c b/tcg/tcg.c
67
index XXXXXXX..XXXXXXX 100644
68
--- a/tcg/tcg.c
69
+++ b/tcg/tcg.c
70
@@ -XXX,XX +XXX,XX @@ static void tcg_register_jit_int(const void *buf, size_t size,
71
__attribute__((unused));
72
73
/* Forward declarations for functions declared and used in tcg-target.c.inc. */
74
+#ifndef TCG_TARGET_CON_STR_H
75
static const char *target_parse_constraint(TCGArgConstraint *ct,
76
const char *ct_str, TCGType type);
77
+#endif
78
static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg1,
79
intptr_t arg2);
80
static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg);
81
@@ -XXX,XX +XXX,XX @@ static void process_op_defs(TCGContext *s)
82
for (op = 0; op < NB_OPS; op++) {
83
TCGOpDef *def = &tcg_op_defs[op];
84
const TCGTargetOpDef *tdefs;
85
- TCGType type;
86
int i, nb_args;
87
88
if (def->flags & TCG_OPF_NOT_PRESENT) {
89
@@ -XXX,XX +XXX,XX @@ static void process_op_defs(TCGContext *s)
90
/* Missing TCGTargetOpDef entry. */
91
tcg_debug_assert(tdefs != NULL);
92
93
- type = (def->flags & TCG_OPF_64BIT ? TCG_TYPE_I64 : TCG_TYPE_I32);
94
for (i = 0; i < nb_args; i++) {
95
const char *ct_str = tdefs->args_ct_str[i];
96
/* Incomplete TCGTargetOpDef entry. */
97
@@ -XXX,XX +XXX,XX @@ static void process_op_defs(TCGContext *s)
98
def->args_ct[i].ct |= TCG_CT_CONST;
99
ct_str++;
100
break;
101
+
102
+#ifdef TCG_TARGET_CON_STR_H
103
+ /* Include all of the target-specific constraints. */
104
+
105
+#undef CONST
106
+#define CONST(CASE, MASK) \
107
+ case CASE: def->args_ct[i].ct |= MASK; ct_str++; break;
108
+#define REGS(CASE, MASK) \
109
+ case CASE: def->args_ct[i].regs |= MASK; ct_str++; break;
110
+
111
+#include "tcg-target-con-str.h"
112
+
113
+#undef REGS
114
+#undef CONST
115
default:
116
- ct_str = target_parse_constraint(&def->args_ct[i],
117
- ct_str, type);
118
/* Typo in TCGTargetOpDef constraint. */
119
- tcg_debug_assert(ct_str != NULL);
120
+ g_assert_not_reached();
121
+#else
122
+ default:
123
+ {
124
+ TCGType type = (def->flags & TCG_OPF_64BIT
125
+ ? TCG_TYPE_I64 : TCG_TYPE_I32);
126
+ ct_str = target_parse_constraint(&def->args_ct[i],
127
+ ct_str, type);
128
+ /* Typo in TCGTargetOpDef constraint. */
129
+ tcg_debug_assert(ct_str != NULL);
130
+ }
131
+#endif
132
}
133
}
134
}
135
diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
136
index XXXXXXX..XXXXXXX 100644
137
--- a/tcg/i386/tcg-target.c.inc
138
+++ b/tcg/i386/tcg-target.c.inc
139
@@ -XXX,XX +XXX,XX @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
140
return true;
141
}
142
143
-/* parse target specific constraints */
144
-static const char *target_parse_constraint(TCGArgConstraint *ct,
145
- const char *ct_str, TCGType type)
146
-{
147
- switch(*ct_str++) {
148
- case 'a':
149
- tcg_regset_set_reg(ct->regs, TCG_REG_EAX);
150
- break;
151
- case 'b':
152
- tcg_regset_set_reg(ct->regs, TCG_REG_EBX);
153
- break;
154
- case 'c':
155
- tcg_regset_set_reg(ct->regs, TCG_REG_ECX);
156
- break;
157
- case 'd':
158
- tcg_regset_set_reg(ct->regs, TCG_REG_EDX);
159
- break;
160
- case 'S':
161
- tcg_regset_set_reg(ct->regs, TCG_REG_ESI);
162
- break;
163
- case 'D':
164
- tcg_regset_set_reg(ct->regs, TCG_REG_EDI);
165
- break;
166
- case 'q':
167
- /* A register that can be used as a byte operand. */
168
- ct->regs |= ALL_BYTEL_REGS;
169
- break;
170
- case 'Q':
171
- /* A register with an addressable second byte (e.g. %ah). */
172
- ct->regs |= ALL_BYTEH_REGS;
173
- break;
174
- case 'r':
175
- /* A general register. */
176
- ct->regs |= ALL_GENERAL_REGS;
177
- break;
178
- case 'W':
179
- /* With TZCNT/LZCNT, we can have operand-size as an input. */
180
- ct->ct |= TCG_CT_CONST_WSZ;
181
- break;
182
- case 'x':
183
- /* A vector register. */
184
- ct->regs |= ALL_VECTOR_REGS;
185
- break;
186
-
187
- case 'L':
188
- /* qemu_ld/st data+address constraint */
189
- ct->regs |= ALL_GENERAL_REGS & ~SOFTMMU_RESERVE_REGS;
190
- break;
191
- case 's':
192
- /* qemu_st8_i32 data constraint */
193
- ct->regs |= ALL_BYTEL_REGS & ~SOFTMMU_RESERVE_REGS;
194
- break;
195
-
196
- case 'e':
197
- ct->ct |= TCG_CT_CONST_S32;
198
- break;
199
- case 'Z':
200
- ct->ct |= TCG_CT_CONST_U32;
201
- break;
202
- case 'I':
203
- ct->ct |= TCG_CT_CONST_I32;
204
- break;
205
-
206
- default:
207
- return NULL;
208
- }
209
- return ct_str;
210
-}
211
-
212
/* test if a constant matches the constraint */
213
static inline int tcg_target_const_match(tcg_target_long val, TCGType type,
214
const TCGArgConstraint *arg_ct)
215
--
216
2.25.1
217
218
diff view generated by jsdifflib
[PULL 06/24] tcg/arm: Split out target constraints to tcg-target-con-str.h
Deleted patch
1
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
2
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
3
---
4
tcg/arm/tcg-target-con-str.h | 22 +++++++++++
5
tcg/arm/tcg-target.h | 1 +
6
tcg/arm/tcg-target.c.inc | 74 +++++++++---------------------------
7
3 files changed, 41 insertions(+), 56 deletions(-)
8
create mode 100644 tcg/arm/tcg-target-con-str.h
9
1
10
diff --git a/tcg/arm/tcg-target-con-str.h b/tcg/arm/tcg-target-con-str.h
11
new file mode 100644
12
index XXXXXXX..XXXXXXX
13
--- /dev/null
14
+++ b/tcg/arm/tcg-target-con-str.h
15
@@ -XXX,XX +XXX,XX @@
16
+/* SPDX-License-Identifier: MIT */
17
+/*
18
+ * Define Arm target-specific operand constraints.
19
+ * Copyright (c) 2021 Linaro
20
+ */
21
+
22
+/*
23
+ * Define constraint letters for register sets:
24
+ * REGS(letter, register_mask)
25
+ */
26
+REGS('r', ALL_GENERAL_REGS)
27
+REGS('l', ALL_QLOAD_REGS)
28
+REGS('s', ALL_QSTORE_REGS)
29
+
30
+/*
31
+ * Define constraint letters for constants:
32
+ * CONST(letter, TCG_CT_CONST_* bit set)
33
+ */
34
+CONST('I', TCG_CT_CONST_ARM)
35
+CONST('K', TCG_CT_CONST_INV)
36
+CONST('N', TCG_CT_CONST_NEG)
37
+CONST('Z', TCG_CT_CONST_ZERO)
38
diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
39
index XXXXXXX..XXXXXXX 100644
40
--- a/tcg/arm/tcg-target.h
41
+++ b/tcg/arm/tcg-target.h
42
@@ -XXX,XX +XXX,XX @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t);
43
#define TCG_TARGET_NEED_LDST_LABELS
44
#endif
45
#define TCG_TARGET_NEED_POOL_LABELS
46
+#define TCG_TARGET_CON_STR_H
47
48
#endif
49
diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
50
index XXXXXXX..XXXXXXX 100644
51
--- a/tcg/arm/tcg-target.c.inc
52
+++ b/tcg/arm/tcg-target.c.inc
53
@@ -XXX,XX +XXX,XX @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
54
#define TCG_CT_CONST_NEG 0x400
55
#define TCG_CT_CONST_ZERO 0x800
56
57
-/* parse target specific constraints */
58
-static const char *target_parse_constraint(TCGArgConstraint *ct,
59
- const char *ct_str, TCGType type)
60
-{
61
- switch (*ct_str++) {
62
- case 'I':
63
- ct->ct |= TCG_CT_CONST_ARM;
64
- break;
65
- case 'K':
66
- ct->ct |= TCG_CT_CONST_INV;
67
- break;
68
- case 'N': /* The gcc constraint letter is L, already used here. */
69
- ct->ct |= TCG_CT_CONST_NEG;
70
- break;
71
- case 'Z':
72
- ct->ct |= TCG_CT_CONST_ZERO;
73
- break;
74
+#define ALL_GENERAL_REGS 0xffffu
75
76
- case 'r':
77
- ct->regs = 0xffff;
78
- break;
79
-
80
- /* qemu_ld address */
81
- case 'l':
82
- ct->regs = 0xffff;
83
+/*
84
+ * r0-r2 will be overwritten when reading the tlb entry (softmmu only)
85
+ * and r0-r1 doing the byte swapping, so don't use these.
86
+ * r3 is removed for softmmu to avoid clashes with helper arguments.
87
+ */
88
#ifdef CONFIG_SOFTMMU
89
- /* r0-r2,lr will be overwritten when reading the tlb entry,
90
- so don't use these. */
91
- tcg_regset_reset_reg(ct->regs, TCG_REG_R0);
92
- tcg_regset_reset_reg(ct->regs, TCG_REG_R1);
93
- tcg_regset_reset_reg(ct->regs, TCG_REG_R2);
94
- tcg_regset_reset_reg(ct->regs, TCG_REG_R3);
95
- tcg_regset_reset_reg(ct->regs, TCG_REG_R14);
96
+#define ALL_QLOAD_REGS \
97
+ (ALL_GENERAL_REGS & ~((1 << TCG_REG_R0) | (1 << TCG_REG_R1) | \
98
+ (1 << TCG_REG_R2) | (1 << TCG_REG_R3) | \
99
+ (1 << TCG_REG_R14)))
100
+#define ALL_QSTORE_REGS \
101
+ (ALL_GENERAL_REGS & ~((1 << TCG_REG_R0) | (1 << TCG_REG_R1) | \
102
+ (1 << TCG_REG_R2) | (1 << TCG_REG_R14) | \
103
+ ((TARGET_LONG_BITS == 64) << TCG_REG_R3)))
104
+#else
105
+#define ALL_QLOAD_REGS ALL_GENERAL_REGS
106
+#define ALL_QSTORE_REGS \
107
+ (ALL_GENERAL_REGS & ~((1 << TCG_REG_R0) | (1 << TCG_REG_R1)))
108
#endif
109
- break;
110
-
111
- /* qemu_st address & data */
112
- case 's':
113
- ct->regs = 0xffff;
114
- /* r0-r2 will be overwritten when reading the tlb entry (softmmu only)
115
- and r0-r1 doing the byte swapping, so don't use these. */
116
- tcg_regset_reset_reg(ct->regs, TCG_REG_R0);
117
- tcg_regset_reset_reg(ct->regs, TCG_REG_R1);
118
-#if defined(CONFIG_SOFTMMU)
119
- /* Avoid clashes with registers being used for helper args */
120
- tcg_regset_reset_reg(ct->regs, TCG_REG_R2);
121
-#if TARGET_LONG_BITS == 64
122
- /* Avoid clashes with registers being used for helper args */
123
- tcg_regset_reset_reg(ct->regs, TCG_REG_R3);
124
-#endif
125
- tcg_regset_reset_reg(ct->regs, TCG_REG_R14);
126
-#endif
127
- break;
128
-
129
- default:
130
- return NULL;
131
- }
132
- return ct_str;
133
-}
134
135
static inline uint32_t rotl(uint32_t val, int n)
136
{
137
--
138
2.25.1
139
140
diff view generated by jsdifflib
[PULL 07/24] tcg/aarch64: Split out target constraints to tcg-target-con-str.h
Deleted patch
1
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
2
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
3
---
4
tcg/aarch64/tcg-target-con-str.h | 24 +++++++++++++++
5
tcg/aarch64/tcg-target.h | 1 +
6
tcg/aarch64/tcg-target.c.inc | 51 +++++---------------------------
7
3 files changed, 33 insertions(+), 43 deletions(-)
8
create mode 100644 tcg/aarch64/tcg-target-con-str.h
9
1
10
diff --git a/tcg/aarch64/tcg-target-con-str.h b/tcg/aarch64/tcg-target-con-str.h
11
new file mode 100644
12
index XXXXXXX..XXXXXXX
13
--- /dev/null
14
+++ b/tcg/aarch64/tcg-target-con-str.h
15
@@ -XXX,XX +XXX,XX @@
16
+/* SPDX-License-Identifier: GPL-2.0-or-later */
17
+/*
18
+ * Define AArch64 target-specific operand constraints.
19
+ * Copyright (c) 2021 Linaro
20
+ */
21
+
22
+/*
23
+ * Define constraint letters for register sets:
24
+ * REGS(letter, register_mask)
25
+ */
26
+REGS('r', ALL_GENERAL_REGS)
27
+REGS('l', ALL_QLDST_REGS)
28
+REGS('w', ALL_VECTOR_REGS)
29
+
30
+/*
31
+ * Define constraint letters for constants:
32
+ * CONST(letter, TCG_CT_CONST_* bit set)
33
+ */
34
+CONST('A', TCG_CT_CONST_AIMM)
35
+CONST('L', TCG_CT_CONST_LIMM)
36
+CONST('M', TCG_CT_CONST_MONE)
37
+CONST('O', TCG_CT_CONST_ORRI)
38
+CONST('N', TCG_CT_CONST_ANDI)
39
+CONST('Z', TCG_CT_CONST_ZERO)
40
diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h
41
index XXXXXXX..XXXXXXX 100644
42
--- a/tcg/aarch64/tcg-target.h
43
+++ b/tcg/aarch64/tcg-target.h
44
@@ -XXX,XX +XXX,XX @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t);
45
#define TCG_TARGET_NEED_LDST_LABELS
46
#endif
47
#define TCG_TARGET_NEED_POOL_LABELS
48
+#define TCG_TARGET_CON_STR_H
49
50
#endif /* AARCH64_TCG_TARGET_H */
51
diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc
52
index XXXXXXX..XXXXXXX 100644
53
--- a/tcg/aarch64/tcg-target.c.inc
54
+++ b/tcg/aarch64/tcg-target.c.inc
55
@@ -XXX,XX +XXX,XX @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
56
#define TCG_CT_CONST_ORRI 0x1000
57
#define TCG_CT_CONST_ANDI 0x2000
58
59
-/* parse target specific constraints */
60
-static const char *target_parse_constraint(TCGArgConstraint *ct,
61
- const char *ct_str, TCGType type)
62
-{
63
- switch (*ct_str++) {
64
- case 'r': /* general registers */
65
- ct->regs |= 0xffffffffu;
66
- break;
67
- case 'w': /* advsimd registers */
68
- ct->regs |= 0xffffffff00000000ull;
69
- break;
70
- case 'l': /* qemu_ld / qemu_st address, data_reg */
71
- ct->regs = 0xffffffffu;
72
+#define ALL_GENERAL_REGS 0xffffffffu
73
+#define ALL_VECTOR_REGS 0xffffffff00000000ull
74
+
75
#ifdef CONFIG_SOFTMMU
76
- /* x0 and x1 will be overwritten when reading the tlb entry,
77
- and x2, and x3 for helper args, better to avoid using them. */
78
- tcg_regset_reset_reg(ct->regs, TCG_REG_X0);
79
- tcg_regset_reset_reg(ct->regs, TCG_REG_X1);
80
- tcg_regset_reset_reg(ct->regs, TCG_REG_X2);
81
- tcg_regset_reset_reg(ct->regs, TCG_REG_X3);
82
+#define ALL_QLDST_REGS \
83
+ (ALL_GENERAL_REGS & ~((1 << TCG_REG_X0) | (1 << TCG_REG_X1) | \
84
+ (1 << TCG_REG_X2) | (1 << TCG_REG_X3)))
85
+#else
86
+#define ALL_QLDST_REGS ALL_GENERAL_REGS
87
#endif
88
- break;
89
- case 'A': /* Valid for arithmetic immediate (positive or negative). */
90
- ct->ct |= TCG_CT_CONST_AIMM;
91
- break;
92
- case 'L': /* Valid for logical immediate. */
93
- ct->ct |= TCG_CT_CONST_LIMM;
94
- break;
95
- case 'M': /* minus one */
96
- ct->ct |= TCG_CT_CONST_MONE;
97
- break;
98
- case 'O': /* vector orr/bic immediate */
99
- ct->ct |= TCG_CT_CONST_ORRI;
100
- break;
101
- case 'N': /* vector orr/bic immediate, inverted */
102
- ct->ct |= TCG_CT_CONST_ANDI;
103
- break;
104
- case 'Z': /* zero */
105
- ct->ct |= TCG_CT_CONST_ZERO;
106
- break;
107
- default:
108
- return NULL;
109
- }
110
- return ct_str;
111
-}
112
113
/* Match a constant valid for addition (12-bit, optionally shifted). */
114
static inline bool is_aimm(uint64_t val)
115
--
116
2.25.1
117
118
diff view generated by jsdifflib
[PULL 08/24] tcg/ppc: Split out target constraints to tcg-target-con-str.h
Deleted patch
1
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
2
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
3
---
4
tcg/ppc/tcg-target-con-str.h | 30 +++++++++++++++
5
tcg/ppc/tcg-target.h | 1 +
6
tcg/ppc/tcg-target.c.inc | 73 ++++++++----------------------------
7
3 files changed, 46 insertions(+), 58 deletions(-)
8
create mode 100644 tcg/ppc/tcg-target-con-str.h
9
1
10
diff --git a/tcg/ppc/tcg-target-con-str.h b/tcg/ppc/tcg-target-con-str.h
11
new file mode 100644
12
index XXXXXXX..XXXXXXX
13
--- /dev/null
14
+++ b/tcg/ppc/tcg-target-con-str.h
15
@@ -XXX,XX +XXX,XX @@
16
+/* SPDX-License-Identifier: MIT */
17
+/*
18
+ * Define PowerPC target-specific operand constraints.
19
+ * Copyright (c) 2021 Linaro
20
+ */
21
+
22
+/*
23
+ * Define constraint letters for register sets:
24
+ * REGS(letter, register_mask)
25
+ */
26
+REGS('r', ALL_GENERAL_REGS)
27
+REGS('v', ALL_VECTOR_REGS)
28
+REGS('A', 1u << TCG_REG_R3)
29
+REGS('B', 1u << TCG_REG_R4)
30
+REGS('C', 1u << TCG_REG_R5)
31
+REGS('D', 1u << TCG_REG_R6)
32
+REGS('L', ALL_QLOAD_REGS)
33
+REGS('S', ALL_QSTORE_REGS)
34
+
35
+/*
36
+ * Define constraint letters for constants:
37
+ * CONST(letter, TCG_CT_CONST_* bit set)
38
+ */
39
+CONST('I', TCG_CT_CONST_S16)
40
+CONST('J', TCG_CT_CONST_U16)
41
+CONST('M', TCG_CT_CONST_MONE)
42
+CONST('T', TCG_CT_CONST_S32)
43
+CONST('U', TCG_CT_CONST_U32)
44
+CONST('W', TCG_CT_CONST_WSZ)
45
+CONST('Z', TCG_CT_CONST_ZERO)
46
diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h
47
index XXXXXXX..XXXXXXX 100644
48
--- a/tcg/ppc/tcg-target.h
49
+++ b/tcg/ppc/tcg-target.h
50
@@ -XXX,XX +XXX,XX @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t);
51
#define TCG_TARGET_NEED_LDST_LABELS
52
#endif
53
#define TCG_TARGET_NEED_POOL_LABELS
54
+#define TCG_TARGET_CON_STR_H
55
56
#endif
57
diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc
58
index XXXXXXX..XXXXXXX 100644
59
--- a/tcg/ppc/tcg-target.c.inc
60
+++ b/tcg/ppc/tcg-target.c.inc
61
@@ -XXX,XX +XXX,XX @@
62
#define TCG_CT_CONST_MONE 0x2000
63
#define TCG_CT_CONST_WSZ 0x4000
64
65
+#define ALL_GENERAL_REGS 0xffffffffu
66
+#define ALL_VECTOR_REGS 0xffffffff00000000ull
67
+
68
+#ifdef CONFIG_SOFTMMU
69
+#define ALL_QLOAD_REGS \
70
+ (ALL_GENERAL_REGS & \
71
+ ~((1 << TCG_REG_R3) | (1 << TCG_REG_R4) | (1 << TCG_REG_R5)))
72
+#define ALL_QSTORE_REGS \
73
+ (ALL_GENERAL_REGS & ~((1 << TCG_REG_R3) | (1 << TCG_REG_R4) | \
74
+ (1 << TCG_REG_R5) | (1 << TCG_REG_R6)))
75
+#else
76
+#define ALL_QLOAD_REGS (ALL_GENERAL_REGS & ~(1 << TCG_REG_R3))
77
+#define ALL_QSTORE_REGS ALL_QLOAD_REGS
78
+#endif
79
+
80
TCGPowerISA have_isa;
81
static bool have_isel;
82
bool have_altivec;
83
@@ -XXX,XX +XXX,XX @@ static bool reloc_pc14(tcg_insn_unit *src_rw, const tcg_insn_unit *target)
84
return false;
85
}
86
87
-/* parse target specific constraints */
88
-static const char *target_parse_constraint(TCGArgConstraint *ct,
89
- const char *ct_str, TCGType type)
90
-{
91
- switch (*ct_str++) {
92
- case 'A': case 'B': case 'C': case 'D':
93
- tcg_regset_set_reg(ct->regs, 3 + ct_str[0] - 'A');
94
- break;
95
- case 'r':
96
- ct->regs = 0xffffffff;
97
- break;
98
- case 'v':
99
- ct->regs = 0xffffffff00000000ull;
100
- break;
101
- case 'L': /* qemu_ld constraint */
102
- ct->regs = 0xffffffff;
103
- tcg_regset_reset_reg(ct->regs, TCG_REG_R3);
104
-#ifdef CONFIG_SOFTMMU
105
- tcg_regset_reset_reg(ct->regs, TCG_REG_R4);
106
- tcg_regset_reset_reg(ct->regs, TCG_REG_R5);
107
-#endif
108
- break;
109
- case 'S': /* qemu_st constraint */
110
- ct->regs = 0xffffffff;
111
- tcg_regset_reset_reg(ct->regs, TCG_REG_R3);
112
-#ifdef CONFIG_SOFTMMU
113
- tcg_regset_reset_reg(ct->regs, TCG_REG_R4);
114
- tcg_regset_reset_reg(ct->regs, TCG_REG_R5);
115
- tcg_regset_reset_reg(ct->regs, TCG_REG_R6);
116
-#endif
117
- break;
118
- case 'I':
119
- ct->ct |= TCG_CT_CONST_S16;
120
- break;
121
- case 'J':
122
- ct->ct |= TCG_CT_CONST_U16;
123
- break;
124
- case 'M':
125
- ct->ct |= TCG_CT_CONST_MONE;
126
- break;
127
- case 'T':
128
- ct->ct |= TCG_CT_CONST_S32;
129
- break;
130
- case 'U':
131
- ct->ct |= TCG_CT_CONST_U32;
132
- break;
133
- case 'W':
134
- ct->ct |= TCG_CT_CONST_WSZ;
135
- break;
136
- case 'Z':
137
- ct->ct |= TCG_CT_CONST_ZERO;
138
- break;
139
- default:
140
- return NULL;
141
- }
142
- return ct_str;
143
-}
144
-
145
/* test if a constant matches the constraint */
146
static int tcg_target_const_match(tcg_target_long val, TCGType type,
147
const TCGArgConstraint *arg_ct)
148
--
149
2.25.1
150
151
diff view generated by jsdifflib
[PULL 09/24] tcg/tci: Split out target constraints to tcg-target-con-str.h
Deleted patch
1
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
2
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
---
5
tcg/tci/tcg-target-con-str.h | 11 +++++++++++
6
tcg/tci/tcg-target.h | 2 ++
7
tcg/tci/tcg-target.c.inc | 14 --------------
8
3 files changed, 13 insertions(+), 14 deletions(-)
9
create mode 100644 tcg/tci/tcg-target-con-str.h
10
1
11
diff --git a/tcg/tci/tcg-target-con-str.h b/tcg/tci/tcg-target-con-str.h
12
new file mode 100644
13
index XXXXXXX..XXXXXXX
14
--- /dev/null
15
+++ b/tcg/tci/tcg-target-con-str.h
16
@@ -XXX,XX +XXX,XX @@
17
+/* SPDX-License-Identifier: MIT */
18
+/*
19
+ * Define TCI target-specific operand constraints.
20
+ * Copyright (c) 2021 Linaro
21
+ */
22
+
23
+/*
24
+ * Define constraint letters for register sets:
25
+ * REGS(letter, register_mask)
26
+ */
27
+REGS('r', MAKE_64BIT_MASK(0, TCG_TARGET_NB_REGS))
28
diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h
29
index XXXXXXX..XXXXXXX 100644
30
--- a/tcg/tci/tcg-target.h
31
+++ b/tcg/tci/tcg-target.h
32
@@ -XXX,XX +XXX,XX @@ static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_rx,
33
/* no need to flush icache explicitly */
34
}
35
36
+#define TCG_TARGET_CON_STR_H
37
+
38
#endif /* TCG_TARGET_H */
39
diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
40
index XXXXXXX..XXXXXXX 100644
41
--- a/tcg/tci/tcg-target.c.inc
42
+++ b/tcg/tci/tcg-target.c.inc
43
@@ -XXX,XX +XXX,XX @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
44
return true;
45
}
46
47
-/* Parse target specific constraints. */
48
-static const char *target_parse_constraint(TCGArgConstraint *ct,
49
- const char *ct_str, TCGType type)
50
-{
51
- switch (*ct_str++) {
52
- case 'r':
53
- ct->regs = BIT(TCG_TARGET_NB_REGS) - 1;
54
- break;
55
- default:
56
- return NULL;
57
- }
58
- return ct_str;
59
-}
60
-
61
#if defined(CONFIG_DEBUG_TCG_INTERPRETER)
62
/* Show current bytecode. Used by tcg interpreter. */
63
void tci_disas(uint8_t opc)
64
--
65
2.25.1
66
67
diff view generated by jsdifflib
[PULL 10/24] tcg/mips: Split out target constraints to tcg-target-con-str.h
Deleted patch
1
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
2
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
---
5
tcg/mips/tcg-target-con-str.h | 24 +++++++++++
6
tcg/mips/tcg-target.h | 1 +
7
tcg/mips/tcg-target.c.inc | 77 ++++++++++-------------------------
8
3 files changed, 46 insertions(+), 56 deletions(-)
9
create mode 100644 tcg/mips/tcg-target-con-str.h
10
1
11
diff --git a/tcg/mips/tcg-target-con-str.h b/tcg/mips/tcg-target-con-str.h
12
new file mode 100644
13
index XXXXXXX..XXXXXXX
14
--- /dev/null
15
+++ b/tcg/mips/tcg-target-con-str.h
16
@@ -XXX,XX +XXX,XX @@
17
+/* SPDX-License-Identifier: MIT */
18
+/*
19
+ * Define MIPS target-specific operand constraints.
20
+ * Copyright (c) 2021 Linaro
21
+ */
22
+
23
+/*
24
+ * Define constraint letters for register sets:
25
+ * REGS(letter, register_mask)
26
+ */
27
+REGS('r', ALL_GENERAL_REGS)
28
+REGS('L', ALL_QLOAD_REGS)
29
+REGS('S', ALL_QSTORE_REGS)
30
+
31
+/*
32
+ * Define constraint letters for constants:
33
+ * CONST(letter, TCG_CT_CONST_* bit set)
34
+ */
35
+CONST('I', TCG_CT_CONST_U16)
36
+CONST('J', TCG_CT_CONST_S16)
37
+CONST('K', TCG_CT_CONST_P2M1)
38
+CONST('N', TCG_CT_CONST_N16)
39
+CONST('W', TCG_CT_CONST_WSZ)
40
+CONST('Z', TCG_CT_CONST_ZERO)
41
diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h
42
index XXXXXXX..XXXXXXX 100644
43
--- a/tcg/mips/tcg-target.h
44
+++ b/tcg/mips/tcg-target.h
45
@@ -XXX,XX +XXX,XX @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t);
46
#ifdef CONFIG_SOFTMMU
47
#define TCG_TARGET_NEED_LDST_LABELS
48
#endif
49
+#define TCG_TARGET_CON_STR_H
50
51
#endif
52
diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc
53
index XXXXXXX..XXXXXXX 100644
54
--- a/tcg/mips/tcg-target.c.inc
55
+++ b/tcg/mips/tcg-target.c.inc
56
@@ -XXX,XX +XXX,XX @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
57
#define TCG_CT_CONST_N16 0x1000 /* "Negatable" 16-bit: -32767 - 32767 */
58
#define TCG_CT_CONST_WSZ 0x2000 /* word size */
59
60
+#define ALL_GENERAL_REGS 0xffffffffu
61
+#define NOA0_REGS (ALL_GENERAL_REGS & ~(1 << TCG_REG_A0))
62
+
63
+#ifdef CONFIG_SOFTMMU
64
+#define ALL_QLOAD_REGS \
65
+ (NOA0_REGS & ~((TCG_TARGET_REG_BITS < TARGET_LONG_BITS) << TCG_REG_A2))
66
+#define ALL_QSTORE_REGS \
67
+ (NOA0_REGS & ~(TCG_TARGET_REG_BITS < TARGET_LONG_BITS \
68
+ ? (1 << TCG_REG_A2) | (1 << TCG_REG_A3) \
69
+ : (1 << TCG_REG_A1)))
70
+#else
71
+#define ALL_QLOAD_REGS NOA0_REGS
72
+#define ALL_QSTORE_REGS NOA0_REGS
73
+#endif
74
+
75
+
76
static inline bool is_p2m1(tcg_target_long val)
77
{
78
return val && ((val + 1) & val) == 0;
79
}
80
81
-/* parse target specific constraints */
82
-static const char *target_parse_constraint(TCGArgConstraint *ct,
83
- const char *ct_str, TCGType type)
84
-{
85
- switch(*ct_str++) {
86
- case 'r':
87
- ct->regs = 0xffffffff;
88
- break;
89
- case 'L': /* qemu_ld input arg constraint */
90
- ct->regs = 0xffffffff;
91
- tcg_regset_reset_reg(ct->regs, TCG_REG_A0);
92
-#if defined(CONFIG_SOFTMMU)
93
- if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
94
- tcg_regset_reset_reg(ct->regs, TCG_REG_A2);
95
- }
96
-#endif
97
- break;
98
- case 'S': /* qemu_st constraint */
99
- ct->regs = 0xffffffff;
100
- tcg_regset_reset_reg(ct->regs, TCG_REG_A0);
101
-#if defined(CONFIG_SOFTMMU)
102
- if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
103
- tcg_regset_reset_reg(ct->regs, TCG_REG_A2);
104
- tcg_regset_reset_reg(ct->regs, TCG_REG_A3);
105
- } else {
106
- tcg_regset_reset_reg(ct->regs, TCG_REG_A1);
107
- }
108
-#endif
109
- break;
110
- case 'I':
111
- ct->ct |= TCG_CT_CONST_U16;
112
- break;
113
- case 'J':
114
- ct->ct |= TCG_CT_CONST_S16;
115
- break;
116
- case 'K':
117
- ct->ct |= TCG_CT_CONST_P2M1;
118
- break;
119
- case 'N':
120
- ct->ct |= TCG_CT_CONST_N16;
121
- break;
122
- case 'W':
123
- ct->ct |= TCG_CT_CONST_WSZ;
124
- break;
125
- case 'Z':
126
- /* We are cheating a bit here, using the fact that the register
127
- ZERO is also the register number 0. Hence there is no need
128
- to check for const_args in each instruction. */
129
- ct->ct |= TCG_CT_CONST_ZERO;
130
- break;
131
- default:
132
- return NULL;
133
- }
134
- return ct_str;
135
-}
136
-
137
/* test if a constant matches the constraint */
138
static inline int tcg_target_const_match(tcg_target_long val, TCGType type,
139
const TCGArgConstraint *arg_ct)
140
@@ -XXX,XX +XXX,XX @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
141
TCGArg a0, a1, a2;
142
int c2;
143
144
+ /*
145
+ * Note that many operands use the constraint set "rZ".
146
+ * We make use of the fact that 0 is the ZERO register,
147
+ * and hence such cases need not check for const_args.
148
+ */
149
a0 = args[0];
150
a1 = args[1];
151
a2 = args[2];
152
--
153
2.25.1
154
155
diff view generated by jsdifflib
[PULL 11/24] tcg/riscv: Split out target constraints to tcg-target-con-str.h
Deleted patch
1
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
2
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
3
---
4
tcg/riscv/tcg-target-con-str.h | 21 ++++++++++++++
5
tcg/riscv/tcg-target.h | 1 +
6
tcg/riscv/tcg-target.c.inc | 52 +++++++++-------------------------
7
3 files changed, 35 insertions(+), 39 deletions(-)
8
create mode 100644 tcg/riscv/tcg-target-con-str.h
9
1
10
diff --git a/tcg/riscv/tcg-target-con-str.h b/tcg/riscv/tcg-target-con-str.h
11
new file mode 100644
12
index XXXXXXX..XXXXXXX
13
--- /dev/null
14
+++ b/tcg/riscv/tcg-target-con-str.h
15
@@ -XXX,XX +XXX,XX @@
16
+/* SPDX-License-Identifier: MIT */
17
+/*
18
+ * Define RISC-V target-specific operand constraints.
19
+ * Copyright (c) 2021 Linaro
20
+ */
21
+
22
+/*
23
+ * Define constraint letters for register sets:
24
+ * REGS(letter, register_mask)
25
+ */
26
+REGS('r', ALL_GENERAL_REGS)
27
+REGS('L', ALL_GENERAL_REGS & ~SOFTMMU_RESERVE_REGS)
28
+
29
+/*
30
+ * Define constraint letters for constants:
31
+ * CONST(letter, TCG_CT_CONST_* bit set)
32
+ */
33
+CONST('I', TCG_CT_CONST_S12)
34
+CONST('N', TCG_CT_CONST_N12)
35
+CONST('M', TCG_CT_CONST_M12)
36
+CONST('Z', TCG_CT_CONST_ZERO)
37
diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h
38
index XXXXXXX..XXXXXXX 100644
39
--- a/tcg/riscv/tcg-target.h
40
+++ b/tcg/riscv/tcg-target.h
41
@@ -XXX,XX +XXX,XX @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t);
42
#define TCG_TARGET_NEED_POOL_LABELS
43
44
#define TCG_TARGET_HAS_MEMORY_BSWAP 0
45
+#define TCG_TARGET_CON_STR_H
46
47
#endif
48
diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
49
index XXXXXXX..XXXXXXX 100644
50
--- a/tcg/riscv/tcg-target.c.inc
51
+++ b/tcg/riscv/tcg-target.c.inc
52
@@ -XXX,XX +XXX,XX @@ static const int tcg_target_call_oarg_regs[] = {
53
#define TCG_CT_CONST_N12 0x400
54
#define TCG_CT_CONST_M12 0x800
55
56
+#define ALL_GENERAL_REGS MAKE_64BIT_MASK(0, 32)
57
+/*
58
+ * For softmmu, we need to avoid conflicts with the first 5
59
+ * argument registers to call the helper. Some of these are
60
+ * also used for the tlb lookup.
61
+ */
62
+#ifdef CONFIG_SOFTMMU
63
+#define SOFTMMU_RESERVE_REGS MAKE_64BIT_MASK(TCG_REG_A0, 5)
64
+#else
65
+#define SOFTMMU_RESERVE_REGS 0
66
+#endif
67
+
68
+
69
static inline tcg_target_long sextreg(tcg_target_long val, int pos, int len)
70
{
71
if (TCG_TARGET_REG_BITS == 32) {
72
@@ -XXX,XX +XXX,XX @@ static inline tcg_target_long sextreg(tcg_target_long val, int pos, int len)
73
}
74
}
75
76
-/* parse target specific constraints */
77
-static const char *target_parse_constraint(TCGArgConstraint *ct,
78
- const char *ct_str, TCGType type)
79
-{
80
- switch (*ct_str++) {
81
- case 'r':
82
- ct->regs = 0xffffffff;
83
- break;
84
- case 'L':
85
- /* qemu_ld/qemu_st constraint */
86
- ct->regs = 0xffffffff;
87
- /* qemu_ld/qemu_st uses TCG_REG_TMP0 */
88
-#if defined(CONFIG_SOFTMMU)
89
- tcg_regset_reset_reg(ct->regs, tcg_target_call_iarg_regs[0]);
90
- tcg_regset_reset_reg(ct->regs, tcg_target_call_iarg_regs[1]);
91
- tcg_regset_reset_reg(ct->regs, tcg_target_call_iarg_regs[2]);
92
- tcg_regset_reset_reg(ct->regs, tcg_target_call_iarg_regs[3]);
93
- tcg_regset_reset_reg(ct->regs, tcg_target_call_iarg_regs[4]);
94
-#endif
95
- break;
96
- case 'I':
97
- ct->ct |= TCG_CT_CONST_S12;
98
- break;
99
- case 'N':
100
- ct->ct |= TCG_CT_CONST_N12;
101
- break;
102
- case 'M':
103
- ct->ct |= TCG_CT_CONST_M12;
104
- break;
105
- case 'Z':
106
- /* we can use a zero immediate as a zero register argument. */
107
- ct->ct |= TCG_CT_CONST_ZERO;
108
- break;
109
- default:
110
- return NULL;
111
- }
112
- return ct_str;
113
-}
114
-
115
/* test if a constant matches the constraint */
116
static int tcg_target_const_match(tcg_target_long val, TCGType type,
117
const TCGArgConstraint *arg_ct)
118
--
119
2.25.1
120
121
diff view generated by jsdifflib
[PULL 12/24] tcg/s390: Split out target constraints to tcg-target-con-str.h
Deleted patch
1
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
2
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
3
---
4
tcg/s390/tcg-target-con-str.h | 28 ++++++++++++++++++
5
tcg/s390/tcg-target.h | 1 +
6
tcg/s390/tcg-target.c.inc | 53 +++++++++--------------------------
7
3 files changed, 42 insertions(+), 40 deletions(-)
8
create mode 100644 tcg/s390/tcg-target-con-str.h
9
1
10
diff --git a/tcg/s390/tcg-target-con-str.h b/tcg/s390/tcg-target-con-str.h
11
new file mode 100644
12
index XXXXXXX..XXXXXXX
13
--- /dev/null
14
+++ b/tcg/s390/tcg-target-con-str.h
15
@@ -XXX,XX +XXX,XX @@
16
+/* SPDX-License-Identifier: MIT */
17
+/*
18
+ * Define S390 target-specific operand constraints.
19
+ * Copyright (c) 2021 Linaro
20
+ */
21
+
22
+/*
23
+ * Define constraint letters for register sets:
24
+ * REGS(letter, register_mask)
25
+ */
26
+REGS('r', ALL_GENERAL_REGS)
27
+REGS('L', ALL_GENERAL_REGS & ~SOFTMMU_RESERVE_REGS)
28
+/*
29
+ * A (single) even/odd pair for division.
30
+ * TODO: Add something to the register allocator to allow
31
+ * this kind of regno+1 pairing to be done more generally.
32
+ */
33
+REGS('a', 1u << TCG_REG_R2)
34
+REGS('b', 1u << TCG_REG_R3)
35
+
36
+/*
37
+ * Define constraint letters for constants:
38
+ * CONST(letter, TCG_CT_CONST_* bit set)
39
+ */
40
+CONST('A', TCG_CT_CONST_S33)
41
+CONST('I', TCG_CT_CONST_S16)
42
+CONST('J', TCG_CT_CONST_S32)
43
+CONST('Z', TCG_CT_CONST_ZERO)
44
diff --git a/tcg/s390/tcg-target.h b/tcg/s390/tcg-target.h
45
index XXXXXXX..XXXXXXX 100644
46
--- a/tcg/s390/tcg-target.h
47
+++ b/tcg/s390/tcg-target.h
48
@@ -XXX,XX +XXX,XX @@ static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_rx,
49
#define TCG_TARGET_NEED_LDST_LABELS
50
#endif
51
#define TCG_TARGET_NEED_POOL_LABELS
52
+#define TCG_TARGET_CON_STR_H
53
54
#endif
55
diff --git a/tcg/s390/tcg-target.c.inc b/tcg/s390/tcg-target.c.inc
56
index XXXXXXX..XXXXXXX 100644
57
--- a/tcg/s390/tcg-target.c.inc
58
+++ b/tcg/s390/tcg-target.c.inc
59
@@ -XXX,XX +XXX,XX @@
60
#define TCG_CT_CONST_S33 0x400
61
#define TCG_CT_CONST_ZERO 0x800
62
63
+#define ALL_GENERAL_REGS MAKE_64BIT_MASK(0, 16)
64
+/*
65
+ * For softmmu, we need to avoid conflicts with the first 3
66
+ * argument registers to perform the tlb lookup, and to call
67
+ * the helper function.
68
+ */
69
+#ifdef CONFIG_SOFTMMU
70
+#define SOFTMMU_RESERVE_REGS MAKE_64BIT_MASK(TCG_REG_R2, 3)
71
+#else
72
+#define SOFTMMU_RESERVE_REGS 0
73
+#endif
74
+
75
+
76
/* Several places within the instruction set 0 means "no register"
77
rather than TCG_REG_R0. */
78
#define TCG_REG_NONE 0
79
@@ -XXX,XX +XXX,XX @@ static bool patch_reloc(tcg_insn_unit *src_rw, int type,
80
return false;
81
}
82
83
-/* parse target specific constraints */
84
-static const char *target_parse_constraint(TCGArgConstraint *ct,
85
- const char *ct_str, TCGType type)
86
-{
87
- switch (*ct_str++) {
88
- case 'r': /* all registers */
89
- ct->regs = 0xffff;
90
- break;
91
- case 'L': /* qemu_ld/st constraint */
92
- ct->regs = 0xffff;
93
- tcg_regset_reset_reg(ct->regs, TCG_REG_R2);
94
- tcg_regset_reset_reg(ct->regs, TCG_REG_R3);
95
- tcg_regset_reset_reg(ct->regs, TCG_REG_R4);
96
- break;
97
- case 'a': /* force R2 for division */
98
- ct->regs = 0;
99
- tcg_regset_set_reg(ct->regs, TCG_REG_R2);
100
- break;
101
- case 'b': /* force R3 for division */
102
- ct->regs = 0;
103
- tcg_regset_set_reg(ct->regs, TCG_REG_R3);
104
- break;
105
- case 'A':
106
- ct->ct |= TCG_CT_CONST_S33;
107
- break;
108
- case 'I':
109
- ct->ct |= TCG_CT_CONST_S16;
110
- break;
111
- case 'J':
112
- ct->ct |= TCG_CT_CONST_S32;
113
- break;
114
- case 'Z':
115
- ct->ct |= TCG_CT_CONST_ZERO;
116
- break;
117
- default:
118
- return NULL;
119
- }
120
- return ct_str;
121
-}
122
-
123
/* Test if a constant matches the constraint. */
124
static int tcg_target_const_match(tcg_target_long val, TCGType type,
125
const TCGArgConstraint *arg_ct)
126
--
127
2.25.1
128
129
diff view generated by jsdifflib
[PULL 13/24] tcg/sparc: Split out target constraints to tcg-target-con-str.h
Deleted patch
1
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
---
5
tcg/sparc/tcg-target-con-str.h | 23 ++++++++++
6
tcg/sparc/tcg-target.h | 5 +--
7
tcg/sparc/tcg-target.c.inc | 81 +++++++++++++---------------------
8
3 files changed, 55 insertions(+), 54 deletions(-)
9
create mode 100644 tcg/sparc/tcg-target-con-str.h
10
1
11
diff --git a/tcg/sparc/tcg-target-con-str.h b/tcg/sparc/tcg-target-con-str.h
12
new file mode 100644
13
index XXXXXXX..XXXXXXX
14
--- /dev/null
15
+++ b/tcg/sparc/tcg-target-con-str.h
16
@@ -XXX,XX +XXX,XX @@
17
+/* SPDX-License-Identifier: MIT */
18
+/*
19
+ * Define Sparc target-specific operand constraints.
20
+ * Copyright (c) 2021 Linaro
21
+ */
22
+
23
+/*
24
+ * Define constraint letters for register sets:
25
+ * REGS(letter, register_mask)
26
+ */
27
+REGS('r', ALL_GENERAL_REGS)
28
+REGS('R', ALL_GENERAL_REGS64)
29
+REGS('s', ALL_QLDST_REGS)
30
+REGS('S', ALL_QLDST_REGS64)
31
+REGS('A', TARGET_LONG_BITS == 64 ? ALL_QLDST_REGS64 : ALL_QLDST_REGS)
32
+
33
+/*
34
+ * Define constraint letters for constants:
35
+ * CONST(letter, TCG_CT_CONST_* bit set)
36
+ */
37
+CONST('I', TCG_CT_CONST_S11)
38
+CONST('J', TCG_CT_CONST_S13)
39
+CONST('Z', TCG_CT_CONST_ZERO)
40
diff --git a/tcg/sparc/tcg-target.h b/tcg/sparc/tcg-target.h
41
index XXXXXXX..XXXXXXX 100644
42
--- a/tcg/sparc/tcg-target.h
43
+++ b/tcg/sparc/tcg-target.h
44
@@ -XXX,XX +XXX,XX @@ typedef enum {
45
TCG_REG_I7,
46
} TCGReg;
47
48
-#define TCG_CT_CONST_S11 0x100
49
-#define TCG_CT_CONST_S13 0x200
50
-#define TCG_CT_CONST_ZERO 0x400
51
-
52
/* used for function call generation */
53
#define TCG_REG_CALL_STACK TCG_REG_O6
54
55
@@ -XXX,XX +XXX,XX @@ extern bool use_vis3_instructions;
56
void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t);
57
58
#define TCG_TARGET_NEED_POOL_LABELS
59
+#define TCG_TARGET_CON_STR_H
60
61
#endif
62
diff --git a/tcg/sparc/tcg-target.c.inc b/tcg/sparc/tcg-target.c.inc
63
index XXXXXXX..XXXXXXX 100644
64
--- a/tcg/sparc/tcg-target.c.inc
65
+++ b/tcg/sparc/tcg-target.c.inc
66
@@ -XXX,XX +XXX,XX @@ static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
67
# define SPARC64 0
68
#endif
69
70
-/* Note that sparcv8plus can only hold 64 bit quantities in %g and %o
71
- registers. These are saved manually by the kernel in full 64-bit
72
- slots. The %i and %l registers are saved by the register window
73
- mechanism, which only allocates space for 32 bits. Given that this
74
- window spill/fill can happen on any signal, we must consider the
75
- high bits of the %i and %l registers garbage at all times. */
76
-#if SPARC64
77
-# define ALL_64 0xffffffffu
78
+#define TCG_CT_CONST_S11 0x100
79
+#define TCG_CT_CONST_S13 0x200
80
+#define TCG_CT_CONST_ZERO 0x400
81
+
82
+/*
83
+ * For softmmu, we need to avoid conflicts with the first 3
84
+ * argument registers to perform the tlb lookup, and to call
85
+ * the helper function.
86
+ */
87
+#ifdef CONFIG_SOFTMMU
88
+#define SOFTMMU_RESERVE_REGS MAKE_64BIT_MASK(TCG_REG_O0, 3)
89
#else
90
-# define ALL_64 0xffffu
91
+#define SOFTMMU_RESERVE_REGS 0
92
#endif
93
94
+/*
95
+ * Note that sparcv8plus can only hold 64 bit quantities in %g and %o
96
+ * registers. These are saved manually by the kernel in full 64-bit
97
+ * slots. The %i and %l registers are saved by the register window
98
+ * mechanism, which only allocates space for 32 bits. Given that this
99
+ * window spill/fill can happen on any signal, we must consider the
100
+ * high bits of the %i and %l registers garbage at all times.
101
+ */
102
+#define ALL_GENERAL_REGS MAKE_64BIT_MASK(0, 32)
103
+#if SPARC64
104
+# define ALL_GENERAL_REGS64 ALL_GENERAL_REGS
105
+#else
106
+# define ALL_GENERAL_REGS64 MAKE_64BIT_MASK(0, 16)
107
+#endif
108
+#define ALL_QLDST_REGS (ALL_GENERAL_REGS & ~SOFTMMU_RESERVE_REGS)
109
+#define ALL_QLDST_REGS64 (ALL_GENERAL_REGS64 & ~SOFTMMU_RESERVE_REGS)
110
+
111
/* Define some temporary registers. T2 is used for constant generation. */
112
#define TCG_REG_T1 TCG_REG_G1
113
#define TCG_REG_T2 TCG_REG_O7
114
@@ -XXX,XX +XXX,XX @@ static bool patch_reloc(tcg_insn_unit *src_rw, int type,
115
return true;
116
}
117
118
-/* parse target specific constraints */
119
-static const char *target_parse_constraint(TCGArgConstraint *ct,
120
- const char *ct_str, TCGType type)
121
-{
122
- switch (*ct_str++) {
123
- case 'r':
124
- ct->regs = 0xffffffff;
125
- break;
126
- case 'R':
127
- ct->regs = ALL_64;
128
- break;
129
- case 'A': /* qemu_ld/st address constraint */
130
- ct->regs = TARGET_LONG_BITS == 64 ? ALL_64 : 0xffffffff;
131
- reserve_helpers:
132
- tcg_regset_reset_reg(ct->regs, TCG_REG_O0);
133
- tcg_regset_reset_reg(ct->regs, TCG_REG_O1);
134
- tcg_regset_reset_reg(ct->regs, TCG_REG_O2);
135
- break;
136
- case 's': /* qemu_st data 32-bit constraint */
137
- ct->regs = 0xffffffff;
138
- goto reserve_helpers;
139
- case 'S': /* qemu_st data 64-bit constraint */
140
- ct->regs = ALL_64;
141
- goto reserve_helpers;
142
- case 'I':
143
- ct->ct |= TCG_CT_CONST_S11;
144
- break;
145
- case 'J':
146
- ct->ct |= TCG_CT_CONST_S13;
147
- break;
148
- case 'Z':
149
- ct->ct |= TCG_CT_CONST_ZERO;
150
- break;
151
- default:
152
- return NULL;
153
- }
154
- return ct_str;
155
-}
156
-
157
/* test if a constant matches the constraint */
158
static inline int tcg_target_const_match(tcg_target_long val, TCGType type,
159
const TCGArgConstraint *arg_ct)
160
@@ -XXX,XX +XXX,XX @@ static void tcg_target_init(TCGContext *s)
161
}
162
#endif
163
164
- tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffff;
165
- tcg_target_available_regs[TCG_TYPE_I64] = ALL_64;
166
+ tcg_target_available_regs[TCG_TYPE_I32] = ALL_GENERAL_REGS;
167
+ tcg_target_available_regs[TCG_TYPE_I64] = ALL_GENERAL_REGS64;
168
169
tcg_target_call_clobber_regs = 0;
170
tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_G1);
171
--
172
2.25.1
173
174
diff view generated by jsdifflib
[PULL 14/24] tcg: Remove TCG_TARGET_CON_STR_H
Deleted patch
1
All backends have now been converted to tcg-target-con-str.h,
2
so we can remove the fallback code.
3
1
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
---
8
tcg/aarch64/tcg-target.h | 1 -
9
tcg/arm/tcg-target.h | 1 -
10
tcg/i386/tcg-target.h | 1 -
11
tcg/mips/tcg-target.h | 1 -
12
tcg/ppc/tcg-target.h | 1 -
13
tcg/riscv/tcg-target.h | 1 -
14
tcg/s390/tcg-target.h | 1 -
15
tcg/sparc/tcg-target.h | 1 -
16
tcg/tci/tcg-target.h | 2 --
17
tcg/tcg.c | 16 ----------------
18
10 files changed, 26 deletions(-)
19
20
diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h
21
index XXXXXXX..XXXXXXX 100644
22
--- a/tcg/aarch64/tcg-target.h
23
+++ b/tcg/aarch64/tcg-target.h
24
@@ -XXX,XX +XXX,XX @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t);
25
#define TCG_TARGET_NEED_LDST_LABELS
26
#endif
27
#define TCG_TARGET_NEED_POOL_LABELS
28
-#define TCG_TARGET_CON_STR_H
29
30
#endif /* AARCH64_TCG_TARGET_H */
31
diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
32
index XXXXXXX..XXXXXXX 100644
33
--- a/tcg/arm/tcg-target.h
34
+++ b/tcg/arm/tcg-target.h
35
@@ -XXX,XX +XXX,XX @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t);
36
#define TCG_TARGET_NEED_LDST_LABELS
37
#endif
38
#define TCG_TARGET_NEED_POOL_LABELS
39
-#define TCG_TARGET_CON_STR_H
40
41
#endif
42
diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h
43
index XXXXXXX..XXXXXXX 100644
44
--- a/tcg/i386/tcg-target.h
45
+++ b/tcg/i386/tcg-target.h
46
@@ -XXX,XX +XXX,XX @@ static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_rx,
47
#define TCG_TARGET_NEED_LDST_LABELS
48
#endif
49
#define TCG_TARGET_NEED_POOL_LABELS
50
-#define TCG_TARGET_CON_STR_H
51
52
#endif
53
diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h
54
index XXXXXXX..XXXXXXX 100644
55
--- a/tcg/mips/tcg-target.h
56
+++ b/tcg/mips/tcg-target.h
57
@@ -XXX,XX +XXX,XX @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t);
58
#ifdef CONFIG_SOFTMMU
59
#define TCG_TARGET_NEED_LDST_LABELS
60
#endif
61
-#define TCG_TARGET_CON_STR_H
62
63
#endif
64
diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h
65
index XXXXXXX..XXXXXXX 100644
66
--- a/tcg/ppc/tcg-target.h
67
+++ b/tcg/ppc/tcg-target.h
68
@@ -XXX,XX +XXX,XX @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t);
69
#define TCG_TARGET_NEED_LDST_LABELS
70
#endif
71
#define TCG_TARGET_NEED_POOL_LABELS
72
-#define TCG_TARGET_CON_STR_H
73
74
#endif
75
diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h
76
index XXXXXXX..XXXXXXX 100644
77
--- a/tcg/riscv/tcg-target.h
78
+++ b/tcg/riscv/tcg-target.h
79
@@ -XXX,XX +XXX,XX @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t);
80
#define TCG_TARGET_NEED_POOL_LABELS
81
82
#define TCG_TARGET_HAS_MEMORY_BSWAP 0
83
-#define TCG_TARGET_CON_STR_H
84
85
#endif
86
diff --git a/tcg/s390/tcg-target.h b/tcg/s390/tcg-target.h
87
index XXXXXXX..XXXXXXX 100644
88
--- a/tcg/s390/tcg-target.h
89
+++ b/tcg/s390/tcg-target.h
90
@@ -XXX,XX +XXX,XX @@ static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_rx,
91
#define TCG_TARGET_NEED_LDST_LABELS
92
#endif
93
#define TCG_TARGET_NEED_POOL_LABELS
94
-#define TCG_TARGET_CON_STR_H
95
96
#endif
97
diff --git a/tcg/sparc/tcg-target.h b/tcg/sparc/tcg-target.h
98
index XXXXXXX..XXXXXXX 100644
99
--- a/tcg/sparc/tcg-target.h
100
+++ b/tcg/sparc/tcg-target.h
101
@@ -XXX,XX +XXX,XX @@ extern bool use_vis3_instructions;
102
void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t);
103
104
#define TCG_TARGET_NEED_POOL_LABELS
105
-#define TCG_TARGET_CON_STR_H
106
107
#endif
108
diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h
109
index XXXXXXX..XXXXXXX 100644
110
--- a/tcg/tci/tcg-target.h
111
+++ b/tcg/tci/tcg-target.h
112
@@ -XXX,XX +XXX,XX @@ static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_rx,
113
/* no need to flush icache explicitly */
114
}
115
116
-#define TCG_TARGET_CON_STR_H
117
-
118
#endif /* TCG_TARGET_H */
119
diff --git a/tcg/tcg.c b/tcg/tcg.c
120
index XXXXXXX..XXXXXXX 100644
121
--- a/tcg/tcg.c
122
+++ b/tcg/tcg.c
123
@@ -XXX,XX +XXX,XX @@ static void tcg_register_jit_int(const void *buf, size_t size,
124
__attribute__((unused));
125
126
/* Forward declarations for functions declared and used in tcg-target.c.inc. */
127
-#ifndef TCG_TARGET_CON_STR_H
128
-static const char *target_parse_constraint(TCGArgConstraint *ct,
129
- const char *ct_str, TCGType type);
130
-#endif
131
static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg1,
132
intptr_t arg2);
133
static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg);
134
@@ -XXX,XX +XXX,XX @@ static void process_op_defs(TCGContext *s)
135
ct_str++;
136
break;
137
138
-#ifdef TCG_TARGET_CON_STR_H
139
/* Include all of the target-specific constraints. */
140
141
#undef CONST
142
@@ -XXX,XX +XXX,XX @@ static void process_op_defs(TCGContext *s)
143
default:
144
/* Typo in TCGTargetOpDef constraint. */
145
g_assert_not_reached();
146
-#else
147
- default:
148
- {
149
- TCGType type = (def->flags & TCG_OPF_64BIT
150
- ? TCG_TYPE_I64 : TCG_TYPE_I32);
151
- ct_str = target_parse_constraint(&def->args_ct[i],
152
- ct_str, type);
153
- /* Typo in TCGTargetOpDef constraint. */
154
- tcg_debug_assert(ct_str != NULL);
155
- }
156
-#endif
157
}
158
}
159
}
160
--
161
2.25.1
162
163
diff view generated by jsdifflib
[PULL 15/24] tcg/i386: Split out constraint sets to tcg-target-con-set.h
Deleted patch
1
This exports the constraint sets from tcg_target_op_def to
2
a place we will be able to manipulate more in future.
3
1
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
---
7
tcg/i386/tcg-target-con-set.h | 55 ++++++++++
8
tcg/i386/tcg-target.h | 1 +
9
tcg/tcg.c | 119 +++++++++++++++++++++
10
tcg/i386/tcg-target.c.inc | 194 ++++++++++++----------------------
11
4 files changed, 242 insertions(+), 127 deletions(-)
12
create mode 100644 tcg/i386/tcg-target-con-set.h
13
14
diff --git a/tcg/i386/tcg-target-con-set.h b/tcg/i386/tcg-target-con-set.h
15
new file mode 100644
16
index XXXXXXX..XXXXXXX
17
--- /dev/null
18
+++ b/tcg/i386/tcg-target-con-set.h
19
@@ -XXX,XX +XXX,XX @@
20
+/* SPDX-License-Identifier: MIT */
21
+/*
22
+ * Define i386 target-specific constraint sets.
23
+ * Copyright (c) 2021 Linaro
24
+ */
25
+
26
+/*
27
+ * C_On_Im(...) defines a constraint set with <n> outputs and <m> inputs.
28
+ * Each operand should be a sequence of constraint letters as defined by
29
+ * tcg-target-con-str.h; the constraint combination is inclusive or.
30
+ *
31
+ * C_N1_Im(...) defines a constraint set with 1 output and <m> inputs,
32
+ * except that the output must use a new register.
33
+ */
34
+C_O0_I1(r)
35
+C_O0_I2(L, L)
36
+C_O0_I2(qi, r)
37
+C_O0_I2(re, r)
38
+C_O0_I2(ri, r)
39
+C_O0_I2(r, re)
40
+C_O0_I2(s, L)
41
+C_O0_I2(x, r)
42
+C_O0_I3(L, L, L)
43
+C_O0_I3(s, L, L)
44
+C_O0_I4(L, L, L, L)
45
+C_O0_I4(r, r, ri, ri)
46
+C_O1_I1(r, 0)
47
+C_O1_I1(r, L)
48
+C_O1_I1(r, q)
49
+C_O1_I1(r, r)
50
+C_O1_I1(x, r)
51
+C_O1_I1(x, x)
52
+C_O1_I2(Q, 0, Q)
53
+C_O1_I2(q, r, re)
54
+C_O1_I2(r, 0, ci)
55
+C_O1_I2(r, 0, r)
56
+C_O1_I2(r, 0, re)
57
+C_O1_I2(r, 0, reZ)
58
+C_O1_I2(r, 0, ri)
59
+C_O1_I2(r, 0, rI)
60
+C_O1_I2(r, L, L)
61
+C_O1_I2(r, r, re)
62
+C_O1_I2(r, r, ri)
63
+C_O1_I2(r, r, rI)
64
+C_O1_I2(x, x, x)
65
+C_N1_I2(r, r, r)
66
+C_N1_I2(r, r, rW)
67
+C_O1_I3(x, x, x, x)
68
+C_O1_I4(r, r, re, r, 0)
69
+C_O1_I4(r, r, r, ri, ri)
70
+C_O2_I1(r, r, L)
71
+C_O2_I2(a, d, a, r)
72
+C_O2_I2(r, r, L, L)
73
+C_O2_I3(a, d, 0, 1, r)
74
+C_O2_I4(r, r, 0, 1, re, re)
75
diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h
76
index XXXXXXX..XXXXXXX 100644
77
--- a/tcg/i386/tcg-target.h
78
+++ b/tcg/i386/tcg-target.h
79
@@ -XXX,XX +XXX,XX @@ static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_rx,
80
#define TCG_TARGET_NEED_LDST_LABELS
81
#endif
82
#define TCG_TARGET_NEED_POOL_LABELS
83
+#define TCG_TARGET_CON_SET_H
84
85
#endif
86
diff --git a/tcg/tcg.c b/tcg/tcg.c
87
index XXXXXXX..XXXXXXX 100644
88
--- a/tcg/tcg.c
89
+++ b/tcg/tcg.c
90
@@ -XXX,XX +XXX,XX @@
91
/* Forward declarations for functions declared in tcg-target.c.inc and
92
used here. */
93
static void tcg_target_init(TCGContext *s);
94
+#ifndef TCG_TARGET_CON_SET_H
95
static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode);
96
+#endif
97
static void tcg_target_qemu_prologue(TCGContext *s);
98
static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
99
intptr_t value, intptr_t addend);
100
@@ -XXX,XX +XXX,XX @@ static void set_jmp_reset_offset(TCGContext *s, int which)
101
s->tb_jmp_reset_offset[which] = tcg_current_code_size(s);
102
}
103
104
+#ifdef TCG_TARGET_CON_SET_H
105
+#define C_PFX1(P, A) P##A
106
+#define C_PFX2(P, A, B) P##A##_##B
107
+#define C_PFX3(P, A, B, C) P##A##_##B##_##C
108
+#define C_PFX4(P, A, B, C, D) P##A##_##B##_##C##_##D
109
+#define C_PFX5(P, A, B, C, D, E) P##A##_##B##_##C##_##D##_##E
110
+#define C_PFX6(P, A, B, C, D, E, F) P##A##_##B##_##C##_##D##_##E##_##F
111
+
112
+/* Define an enumeration for the various combinations. */
113
+
114
+#define C_O0_I1(I1) C_PFX1(c_o0_i1_, I1),
115
+#define C_O0_I2(I1, I2) C_PFX2(c_o0_i2_, I1, I2),
116
+#define C_O0_I3(I1, I2, I3) C_PFX3(c_o0_i3_, I1, I2, I3),
117
+#define C_O0_I4(I1, I2, I3, I4) C_PFX4(c_o0_i4_, I1, I2, I3, I4),
118
+
119
+#define C_O1_I1(O1, I1) C_PFX2(c_o1_i1_, O1, I1),
120
+#define C_O1_I2(O1, I1, I2) C_PFX3(c_o1_i2_, O1, I1, I2),
121
+#define C_O1_I3(O1, I1, I2, I3) C_PFX4(c_o1_i3_, O1, I1, I2, I3),
122
+#define C_O1_I4(O1, I1, I2, I3, I4) C_PFX5(c_o1_i4_, O1, I1, I2, I3, I4),
123
+
124
+#define C_N1_I2(O1, I1, I2) C_PFX3(c_n1_i2_, O1, I1, I2),
125
+
126
+#define C_O2_I1(O1, O2, I1) C_PFX3(c_o2_i1_, O1, O2, I1),
127
+#define C_O2_I2(O1, O2, I1, I2) C_PFX4(c_o2_i2_, O1, O2, I1, I2),
128
+#define C_O2_I3(O1, O2, I1, I2, I3) C_PFX5(c_o2_i3_, O1, O2, I1, I2, I3),
129
+#define C_O2_I4(O1, O2, I1, I2, I3, I4) C_PFX6(c_o2_i4_, O1, O2, I1, I2, I3, I4),
130
+
131
+typedef enum {
132
+#include "tcg-target-con-set.h"
133
+} TCGConstraintSetIndex;
134
+
135
+static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode);
136
+
137
+#undef C_O0_I1
138
+#undef C_O0_I2
139
+#undef C_O0_I3
140
+#undef C_O0_I4
141
+#undef C_O1_I1
142
+#undef C_O1_I2
143
+#undef C_O1_I3
144
+#undef C_O1_I4
145
+#undef C_N1_I2
146
+#undef C_O2_I1
147
+#undef C_O2_I2
148
+#undef C_O2_I3
149
+#undef C_O2_I4
150
+
151
+/* Put all of the constraint sets into an array, indexed by the enum. */
152
+
153
+#define C_O0_I1(I1) { .args_ct_str = { #I1 } },
154
+#define C_O0_I2(I1, I2) { .args_ct_str = { #I1, #I2 } },
155
+#define C_O0_I3(I1, I2, I3) { .args_ct_str = { #I1, #I2, #I3 } },
156
+#define C_O0_I4(I1, I2, I3, I4) { .args_ct_str = { #I1, #I2, #I3, #I4 } },
157
+
158
+#define C_O1_I1(O1, I1) { .args_ct_str = { #O1, #I1 } },
159
+#define C_O1_I2(O1, I1, I2) { .args_ct_str = { #O1, #I1, #I2 } },
160
+#define C_O1_I3(O1, I1, I2, I3) { .args_ct_str = { #O1, #I1, #I2, #I3 } },
161
+#define C_O1_I4(O1, I1, I2, I3, I4) { .args_ct_str = { #O1, #I1, #I2, #I3, #I4 } },
162
+
163
+#define C_N1_I2(O1, I1, I2) { .args_ct_str = { "&" #O1, #I1, #I2 } },
164
+
165
+#define C_O2_I1(O1, O2, I1) { .args_ct_str = { #O1, #O2, #I1 } },
166
+#define C_O2_I2(O1, O2, I1, I2) { .args_ct_str = { #O1, #O2, #I1, #I2 } },
167
+#define C_O2_I3(O1, O2, I1, I2, I3) { .args_ct_str = { #O1, #O2, #I1, #I2, #I3 } },
168
+#define C_O2_I4(O1, O2, I1, I2, I3, I4) { .args_ct_str = { #O1, #O2, #I1, #I2, #I3, #I4 } },
169
+
170
+static const TCGTargetOpDef constraint_sets[] = {
171
+#include "tcg-target-con-set.h"
172
+};
173
+
174
+
175
+#undef C_O0_I1
176
+#undef C_O0_I2
177
+#undef C_O0_I3
178
+#undef C_O0_I4
179
+#undef C_O1_I1
180
+#undef C_O1_I2
181
+#undef C_O1_I3
182
+#undef C_O1_I4
183
+#undef C_N1_I2
184
+#undef C_O2_I1
185
+#undef C_O2_I2
186
+#undef C_O2_I3
187
+#undef C_O2_I4
188
+
189
+/* Expand the enumerator to be returned from tcg_target_op_def(). */
190
+
191
+#define C_O0_I1(I1) C_PFX1(c_o0_i1_, I1)
192
+#define C_O0_I2(I1, I2) C_PFX2(c_o0_i2_, I1, I2)
193
+#define C_O0_I3(I1, I2, I3) C_PFX3(c_o0_i3_, I1, I2, I3)
194
+#define C_O0_I4(I1, I2, I3, I4) C_PFX4(c_o0_i4_, I1, I2, I3, I4)
195
+
196
+#define C_O1_I1(O1, I1) C_PFX2(c_o1_i1_, O1, I1)
197
+#define C_O1_I2(O1, I1, I2) C_PFX3(c_o1_i2_, O1, I1, I2)
198
+#define C_O1_I3(O1, I1, I2, I3) C_PFX4(c_o1_i3_, O1, I1, I2, I3)
199
+#define C_O1_I4(O1, I1, I2, I3, I4) C_PFX5(c_o1_i4_, O1, I1, I2, I3, I4)
200
+
201
+#define C_N1_I2(O1, I1, I2) C_PFX3(c_n1_i2_, O1, I1, I2)
202
+
203
+#define C_O2_I1(O1, O2, I1) C_PFX3(c_o2_i1_, O1, O2, I1)
204
+#define C_O2_I2(O1, O2, I1, I2) C_PFX4(c_o2_i2_, O1, O2, I1, I2)
205
+#define C_O2_I3(O1, O2, I1, I2, I3) C_PFX5(c_o2_i3_, O1, O2, I1, I2, I3)
206
+#define C_O2_I4(O1, O2, I1, I2, I3, I4) C_PFX6(c_o2_i4_, O1, O2, I1, I2, I3, I4)
207
+
208
+#endif /* TCG_TARGET_CON_SET_H */
209
+
210
#include "tcg-target.c.inc"
211
212
/* compare a pointer @ptr and a tb_tc @s */
213
@@ -XXX,XX +XXX,XX @@ static void process_op_defs(TCGContext *s)
214
continue;
215
}
216
217
+#ifdef TCG_TARGET_CON_SET_H
218
+ /*
219
+ * Macro magic should make it impossible, but double-check that
220
+ * the array index is in range. Since the signness of an enum
221
+ * is implementation defined, force the result to unsigned.
222
+ */
223
+ unsigned con_set = tcg_target_op_def(op);
224
+ tcg_debug_assert(con_set < ARRAY_SIZE(constraint_sets));
225
+ tdefs = &constraint_sets[con_set];
226
+#else
227
tdefs = tcg_target_op_def(op);
228
/* Missing TCGTargetOpDef entry. */
229
tcg_debug_assert(tdefs != NULL);
230
+#endif
231
232
for (i = 0; i < nb_args; i++) {
233
const char *ct_str = tdefs->args_ct_str[i];
234
diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
235
index XXXXXXX..XXXXXXX 100644
236
--- a/tcg/i386/tcg-target.c.inc
237
+++ b/tcg/i386/tcg-target.c.inc
238
@@ -XXX,XX +XXX,XX @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
239
}
240
}
241
242
-static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
243
+static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
244
{
245
- static const TCGTargetOpDef r = { .args_ct_str = { "r" } };
246
- static const TCGTargetOpDef ri_r = { .args_ct_str = { "ri", "r" } };
247
- static const TCGTargetOpDef re_r = { .args_ct_str = { "re", "r" } };
248
- static const TCGTargetOpDef qi_r = { .args_ct_str = { "qi", "r" } };
249
- static const TCGTargetOpDef r_r = { .args_ct_str = { "r", "r" } };
250
- static const TCGTargetOpDef r_q = { .args_ct_str = { "r", "q" } };
251
- static const TCGTargetOpDef r_re = { .args_ct_str = { "r", "re" } };
252
- static const TCGTargetOpDef r_0 = { .args_ct_str = { "r", "0" } };
253
- static const TCGTargetOpDef r_r_ri = { .args_ct_str = { "r", "r", "ri" } };
254
- static const TCGTargetOpDef r_r_re = { .args_ct_str = { "r", "r", "re" } };
255
- static const TCGTargetOpDef r_0_r = { .args_ct_str = { "r", "0", "r" } };
256
- static const TCGTargetOpDef r_0_re = { .args_ct_str = { "r", "0", "re" } };
257
- static const TCGTargetOpDef r_0_ci = { .args_ct_str = { "r", "0", "ci" } };
258
- static const TCGTargetOpDef r_L = { .args_ct_str = { "r", "L" } };
259
- static const TCGTargetOpDef L_L = { .args_ct_str = { "L", "L" } };
260
- static const TCGTargetOpDef s_L = { .args_ct_str = { "s", "L" } };
261
- static const TCGTargetOpDef r_L_L = { .args_ct_str = { "r", "L", "L" } };
262
- static const TCGTargetOpDef r_r_L = { .args_ct_str = { "r", "r", "L" } };
263
- static const TCGTargetOpDef L_L_L = { .args_ct_str = { "L", "L", "L" } };
264
- static const TCGTargetOpDef s_L_L = { .args_ct_str = { "s", "L", "L" } };
265
- static const TCGTargetOpDef r_r_L_L
266
- = { .args_ct_str = { "r", "r", "L", "L" } };
267
- static const TCGTargetOpDef L_L_L_L
268
- = { .args_ct_str = { "L", "L", "L", "L" } };
269
- static const TCGTargetOpDef x_x = { .args_ct_str = { "x", "x" } };
270
- static const TCGTargetOpDef x_x_x = { .args_ct_str = { "x", "x", "x" } };
271
- static const TCGTargetOpDef x_x_x_x
272
- = { .args_ct_str = { "x", "x", "x", "x" } };
273
- static const TCGTargetOpDef x_r = { .args_ct_str = { "x", "r" } };
274
-
275
switch (op) {
276
case INDEX_op_goto_ptr:
277
- return &r;
278
+ return C_O0_I1(r);
279
280
case INDEX_op_ld8u_i32:
281
case INDEX_op_ld8u_i64:
282
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
283
case INDEX_op_ld32u_i64:
284
case INDEX_op_ld32s_i64:
285
case INDEX_op_ld_i64:
286
- return &r_r;
287
+ return C_O1_I1(r, r);
288
289
case INDEX_op_st8_i32:
290
case INDEX_op_st8_i64:
291
- return &qi_r;
292
+ return C_O0_I2(qi, r);
293
+
294
case INDEX_op_st16_i32:
295
case INDEX_op_st16_i64:
296
case INDEX_op_st_i32:
297
case INDEX_op_st32_i64:
298
- return &ri_r;
299
+ return C_O0_I2(ri, r);
300
+
301
case INDEX_op_st_i64:
302
- return &re_r;
303
+ return C_O0_I2(re, r);
304
305
case INDEX_op_add_i32:
306
case INDEX_op_add_i64:
307
- return &r_r_re;
308
+ return C_O1_I2(r, r, re);
309
+
310
case INDEX_op_sub_i32:
311
case INDEX_op_sub_i64:
312
case INDEX_op_mul_i32:
313
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
314
case INDEX_op_or_i64:
315
case INDEX_op_xor_i32:
316
case INDEX_op_xor_i64:
317
- return &r_0_re;
318
+ return C_O1_I2(r, 0, re);
319
320
case INDEX_op_and_i32:
321
case INDEX_op_and_i64:
322
- {
323
- static const TCGTargetOpDef and
324
- = { .args_ct_str = { "r", "0", "reZ" } };
325
- return &and;
326
- }
327
- break;
328
+ return C_O1_I2(r, 0, reZ);
329
+
330
case INDEX_op_andc_i32:
331
case INDEX_op_andc_i64:
332
- {
333
- static const TCGTargetOpDef andc
334
- = { .args_ct_str = { "r", "r", "rI" } };
335
- return &andc;
336
- }
337
- break;
338
+ return C_O1_I2(r, r, rI);
339
340
case INDEX_op_shl_i32:
341
case INDEX_op_shl_i64:
342
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
343
case INDEX_op_shr_i64:
344
case INDEX_op_sar_i32:
345
case INDEX_op_sar_i64:
346
- return have_bmi2 ? &r_r_ri : &r_0_ci;
347
+ return have_bmi2 ? C_O1_I2(r, r, ri) : C_O1_I2(r, 0, ci);
348
+
349
case INDEX_op_rotl_i32:
350
case INDEX_op_rotl_i64:
351
case INDEX_op_rotr_i32:
352
case INDEX_op_rotr_i64:
353
- return &r_0_ci;
354
+ return C_O1_I2(r, 0, ci);
355
356
case INDEX_op_brcond_i32:
357
case INDEX_op_brcond_i64:
358
- return &r_re;
359
+ return C_O0_I2(r, re);
360
361
case INDEX_op_bswap16_i32:
362
case INDEX_op_bswap16_i64:
363
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
364
case INDEX_op_not_i32:
365
case INDEX_op_not_i64:
366
case INDEX_op_extrh_i64_i32:
367
- return &r_0;
368
+ return C_O1_I1(r, 0);
369
370
case INDEX_op_ext8s_i32:
371
case INDEX_op_ext8s_i64:
372
case INDEX_op_ext8u_i32:
373
case INDEX_op_ext8u_i64:
374
- return &r_q;
375
+ return C_O1_I1(r, q);
376
+
377
case INDEX_op_ext16s_i32:
378
case INDEX_op_ext16s_i64:
379
case INDEX_op_ext16u_i32:
380
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
381
case INDEX_op_sextract_i32:
382
case INDEX_op_ctpop_i32:
383
case INDEX_op_ctpop_i64:
384
- return &r_r;
385
+ return C_O1_I1(r, r);
386
+
387
case INDEX_op_extract2_i32:
388
case INDEX_op_extract2_i64:
389
- return &r_0_r;
390
+ return C_O1_I2(r, 0, r);
391
392
case INDEX_op_deposit_i32:
393
case INDEX_op_deposit_i64:
394
- {
395
- static const TCGTargetOpDef dep
396
- = { .args_ct_str = { "Q", "0", "Q" } };
397
- return &dep;
398
- }
399
+ return C_O1_I2(Q, 0, Q);
400
+
401
case INDEX_op_setcond_i32:
402
case INDEX_op_setcond_i64:
403
- {
404
- static const TCGTargetOpDef setc
405
- = { .args_ct_str = { "q", "r", "re" } };
406
- return &setc;
407
- }
408
+ return C_O1_I2(q, r, re);
409
+
410
case INDEX_op_movcond_i32:
411
case INDEX_op_movcond_i64:
412
- {
413
- static const TCGTargetOpDef movc
414
- = { .args_ct_str = { "r", "r", "re", "r", "0" } };
415
- return &movc;
416
- }
417
+ return C_O1_I4(r, r, re, r, 0);
418
+
419
case INDEX_op_div2_i32:
420
case INDEX_op_div2_i64:
421
case INDEX_op_divu2_i32:
422
case INDEX_op_divu2_i64:
423
- {
424
- static const TCGTargetOpDef div2
425
- = { .args_ct_str = { "a", "d", "0", "1", "r" } };
426
- return &div2;
427
- }
428
+ return C_O2_I3(a, d, 0, 1, r);
429
+
430
case INDEX_op_mulu2_i32:
431
case INDEX_op_mulu2_i64:
432
case INDEX_op_muls2_i32:
433
case INDEX_op_muls2_i64:
434
- {
435
- static const TCGTargetOpDef mul2
436
- = { .args_ct_str = { "a", "d", "a", "r" } };
437
- return &mul2;
438
- }
439
+ return C_O2_I2(a, d, a, r);
440
+
441
case INDEX_op_add2_i32:
442
case INDEX_op_add2_i64:
443
case INDEX_op_sub2_i32:
444
case INDEX_op_sub2_i64:
445
- {
446
- static const TCGTargetOpDef arith2
447
- = { .args_ct_str = { "r", "r", "0", "1", "re", "re" } };
448
- return &arith2;
449
- }
450
+ return C_O2_I4(r, r, 0, 1, re, re);
451
+
452
case INDEX_op_ctz_i32:
453
case INDEX_op_ctz_i64:
454
- {
455
- static const TCGTargetOpDef ctz[2] = {
456
- { .args_ct_str = { "&r", "r", "r" } },
457
- { .args_ct_str = { "&r", "r", "rW" } },
458
- };
459
- return &ctz[have_bmi1];
460
- }
461
+ return have_bmi1 ? C_N1_I2(r, r, rW) : C_N1_I2(r, r, r);
462
+
463
case INDEX_op_clz_i32:
464
case INDEX_op_clz_i64:
465
- {
466
- static const TCGTargetOpDef clz[2] = {
467
- { .args_ct_str = { "&r", "r", "r" } },
468
- { .args_ct_str = { "&r", "r", "rW" } },
469
- };
470
- return &clz[have_lzcnt];
471
- }
472
+ return have_lzcnt ? C_N1_I2(r, r, rW) : C_N1_I2(r, r, r);
473
474
case INDEX_op_qemu_ld_i32:
475
- return TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &r_L : &r_L_L;
476
+ return (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS
477
+ ? C_O1_I1(r, L) : C_O1_I2(r, L, L));
478
+
479
case INDEX_op_qemu_st_i32:
480
- return TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &L_L : &L_L_L;
481
+ return (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS
482
+ ? C_O0_I2(L, L) : C_O0_I3(L, L, L));
483
case INDEX_op_qemu_st8_i32:
484
- return TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &s_L : &s_L_L;
485
+ return (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS
486
+ ? C_O0_I2(s, L) : C_O0_I3(s, L, L));
487
+
488
case INDEX_op_qemu_ld_i64:
489
- return (TCG_TARGET_REG_BITS == 64 ? &r_L
490
- : TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &r_r_L
491
- : &r_r_L_L);
492
+ return (TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, L)
493
+ : TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? C_O2_I1(r, r, L)
494
+ : C_O2_I2(r, r, L, L));
495
+
496
case INDEX_op_qemu_st_i64:
497
- return (TCG_TARGET_REG_BITS == 64 ? &L_L
498
- : TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &L_L_L
499
- : &L_L_L_L);
500
+ return (TCG_TARGET_REG_BITS == 64 ? C_O0_I2(L, L)
501
+ : TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? C_O0_I3(L, L, L)
502
+ : C_O0_I4(L, L, L, L));
503
504
case INDEX_op_brcond2_i32:
505
- {
506
- static const TCGTargetOpDef b2
507
- = { .args_ct_str = { "r", "r", "ri", "ri" } };
508
- return &b2;
509
- }
510
+ return C_O0_I4(r, r, ri, ri);
511
+
512
case INDEX_op_setcond2_i32:
513
- {
514
- static const TCGTargetOpDef s2
515
- = { .args_ct_str = { "r", "r", "r", "ri", "ri" } };
516
- return &s2;
517
- }
518
+ return C_O1_I4(r, r, r, ri, ri);
519
520
case INDEX_op_ld_vec:
521
- case INDEX_op_st_vec:
522
case INDEX_op_dupm_vec:
523
- return &x_r;
524
+ return C_O1_I1(x, r);
525
+
526
+ case INDEX_op_st_vec:
527
+ return C_O0_I2(x, r);
528
529
case INDEX_op_add_vec:
530
case INDEX_op_sub_vec:
531
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
532
#if TCG_TARGET_REG_BITS == 32
533
case INDEX_op_dup2_vec:
534
#endif
535
- return &x_x_x;
536
+ return C_O1_I2(x, x, x);
537
+
538
case INDEX_op_abs_vec:
539
case INDEX_op_dup_vec:
540
case INDEX_op_shli_vec:
541
case INDEX_op_shri_vec:
542
case INDEX_op_sari_vec:
543
case INDEX_op_x86_psrldq_vec:
544
- return &x_x;
545
+ return C_O1_I1(x, x);
546
+
547
case INDEX_op_x86_vpblendvb_vec:
548
- return &x_x_x_x;
549
+ return C_O1_I3(x, x, x, x);
550
551
default:
552
- break;
553
+ g_assert_not_reached();
554
}
555
- return NULL;
556
}
557
558
int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
559
--
560
2.25.1
561
562
diff view generated by jsdifflib
[PULL 16/24] tcg/aarch64: Split out constraint sets to tcg-target-con-set.h
Deleted patch
1
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
2
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
3
---
4
tcg/aarch64/tcg-target-con-set.h | 36 +++++++++++++
5
tcg/aarch64/tcg-target.h | 1 +
6
tcg/aarch64/tcg-target.c.inc | 86 +++++++++++---------------------
7
3 files changed, 65 insertions(+), 58 deletions(-)
8
create mode 100644 tcg/aarch64/tcg-target-con-set.h
9
1
10
diff --git a/tcg/aarch64/tcg-target-con-set.h b/tcg/aarch64/tcg-target-con-set.h
11
new file mode 100644
12
index XXXXXXX..XXXXXXX
13
--- /dev/null
14
+++ b/tcg/aarch64/tcg-target-con-set.h
15
@@ -XXX,XX +XXX,XX @@
16
+/* SPDX-License-Identifier: GPL-2.0-or-later */
17
+/*
18
+ * Define AArch64 target-specific constraint sets.
19
+ * Copyright (c) 2021 Linaro
20
+ */
21
+
22
+/*
23
+ * C_On_Im(...) defines a constraint set with <n> outputs and <m> inputs.
24
+ * Each operand should be a sequence of constraint letters as defined by
25
+ * tcg-target-con-str.h; the constraint combination is inclusive or.
26
+ */
27
+C_O0_I1(r)
28
+C_O0_I2(lZ, l)
29
+C_O0_I2(r, rA)
30
+C_O0_I2(rZ, r)
31
+C_O0_I2(w, r)
32
+C_O1_I1(r, l)
33
+C_O1_I1(r, r)
34
+C_O1_I1(w, r)
35
+C_O1_I1(w, w)
36
+C_O1_I1(w, wr)
37
+C_O1_I2(r, 0, rZ)
38
+C_O1_I2(r, r, r)
39
+C_O1_I2(r, r, rA)
40
+C_O1_I2(r, r, rAL)
41
+C_O1_I2(r, r, ri)
42
+C_O1_I2(r, r, rL)
43
+C_O1_I2(r, rZ, rZ)
44
+C_O1_I2(w, 0, w)
45
+C_O1_I2(w, w, w)
46
+C_O1_I2(w, w, wN)
47
+C_O1_I2(w, w, wO)
48
+C_O1_I2(w, w, wZ)
49
+C_O1_I3(w, w, w, w)
50
+C_O1_I4(r, r, rA, rZ, rZ)
51
+C_O2_I4(r, r, rZ, rZ, rA, rMZ)
52
diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h
53
index XXXXXXX..XXXXXXX 100644
54
--- a/tcg/aarch64/tcg-target.h
55
+++ b/tcg/aarch64/tcg-target.h
56
@@ -XXX,XX +XXX,XX @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t);
57
#define TCG_TARGET_NEED_LDST_LABELS
58
#endif
59
#define TCG_TARGET_NEED_POOL_LABELS
60
+#define TCG_TARGET_CON_SET_H
61
62
#endif /* AARCH64_TCG_TARGET_H */
63
diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc
64
index XXXXXXX..XXXXXXX 100644
65
--- a/tcg/aarch64/tcg-target.c.inc
66
+++ b/tcg/aarch64/tcg-target.c.inc
67
@@ -XXX,XX +XXX,XX @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece,
68
va_end(va);
69
}
70
71
-static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
72
+static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
73
{
74
- static const TCGTargetOpDef r = { .args_ct_str = { "r" } };
75
- static const TCGTargetOpDef r_r = { .args_ct_str = { "r", "r" } };
76
- static const TCGTargetOpDef w_w = { .args_ct_str = { "w", "w" } };
77
- static const TCGTargetOpDef w_r = { .args_ct_str = { "w", "r" } };
78
- static const TCGTargetOpDef w_wr = { .args_ct_str = { "w", "wr" } };
79
- static const TCGTargetOpDef r_l = { .args_ct_str = { "r", "l" } };
80
- static const TCGTargetOpDef r_rA = { .args_ct_str = { "r", "rA" } };
81
- static const TCGTargetOpDef rZ_r = { .args_ct_str = { "rZ", "r" } };
82
- static const TCGTargetOpDef lZ_l = { .args_ct_str = { "lZ", "l" } };
83
- static const TCGTargetOpDef r_r_r = { .args_ct_str = { "r", "r", "r" } };
84
- static const TCGTargetOpDef w_w_w = { .args_ct_str = { "w", "w", "w" } };
85
- static const TCGTargetOpDef w_0_w = { .args_ct_str = { "w", "0", "w" } };
86
- static const TCGTargetOpDef w_w_wO = { .args_ct_str = { "w", "w", "wO" } };
87
- static const TCGTargetOpDef w_w_wN = { .args_ct_str = { "w", "w", "wN" } };
88
- static const TCGTargetOpDef w_w_wZ = { .args_ct_str = { "w", "w", "wZ" } };
89
- static const TCGTargetOpDef r_r_ri = { .args_ct_str = { "r", "r", "ri" } };
90
- static const TCGTargetOpDef r_r_rA = { .args_ct_str = { "r", "r", "rA" } };
91
- static const TCGTargetOpDef r_r_rL = { .args_ct_str = { "r", "r", "rL" } };
92
- static const TCGTargetOpDef r_r_rAL
93
- = { .args_ct_str = { "r", "r", "rAL" } };
94
- static const TCGTargetOpDef dep
95
- = { .args_ct_str = { "r", "0", "rZ" } };
96
- static const TCGTargetOpDef ext2
97
- = { .args_ct_str = { "r", "rZ", "rZ" } };
98
- static const TCGTargetOpDef movc
99
- = { .args_ct_str = { "r", "r", "rA", "rZ", "rZ" } };
100
- static const TCGTargetOpDef add2
101
- = { .args_ct_str = { "r", "r", "rZ", "rZ", "rA", "rMZ" } };
102
- static const TCGTargetOpDef w_w_w_w
103
- = { .args_ct_str = { "w", "w", "w", "w" } };
104
-
105
switch (op) {
106
case INDEX_op_goto_ptr:
107
- return &r;
108
+ return C_O0_I1(r);
109
110
case INDEX_op_ld8u_i32:
111
case INDEX_op_ld8s_i32:
112
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
113
case INDEX_op_extract_i64:
114
case INDEX_op_sextract_i32:
115
case INDEX_op_sextract_i64:
116
- return &r_r;
117
+ return C_O1_I1(r, r);
118
119
case INDEX_op_st8_i32:
120
case INDEX_op_st16_i32:
121
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
122
case INDEX_op_st16_i64:
123
case INDEX_op_st32_i64:
124
case INDEX_op_st_i64:
125
- return &rZ_r;
126
+ return C_O0_I2(rZ, r);
127
128
case INDEX_op_add_i32:
129
case INDEX_op_add_i64:
130
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
131
case INDEX_op_sub_i64:
132
case INDEX_op_setcond_i32:
133
case INDEX_op_setcond_i64:
134
- return &r_r_rA;
135
+ return C_O1_I2(r, r, rA);
136
137
case INDEX_op_mul_i32:
138
case INDEX_op_mul_i64:
139
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
140
case INDEX_op_remu_i64:
141
case INDEX_op_muluh_i64:
142
case INDEX_op_mulsh_i64:
143
- return &r_r_r;
144
+ return C_O1_I2(r, r, r);
145
146
case INDEX_op_and_i32:
147
case INDEX_op_and_i64:
148
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
149
case INDEX_op_orc_i64:
150
case INDEX_op_eqv_i32:
151
case INDEX_op_eqv_i64:
152
- return &r_r_rL;
153
+ return C_O1_I2(r, r, rL);
154
155
case INDEX_op_shl_i32:
156
case INDEX_op_shr_i32:
157
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
158
case INDEX_op_sar_i64:
159
case INDEX_op_rotl_i64:
160
case INDEX_op_rotr_i64:
161
- return &r_r_ri;
162
+ return C_O1_I2(r, r, ri);
163
164
case INDEX_op_clz_i32:
165
case INDEX_op_ctz_i32:
166
case INDEX_op_clz_i64:
167
case INDEX_op_ctz_i64:
168
- return &r_r_rAL;
169
+ return C_O1_I2(r, r, rAL);
170
171
case INDEX_op_brcond_i32:
172
case INDEX_op_brcond_i64:
173
- return &r_rA;
174
+ return C_O0_I2(r, rA);
175
176
case INDEX_op_movcond_i32:
177
case INDEX_op_movcond_i64:
178
- return &movc;
179
+ return C_O1_I4(r, r, rA, rZ, rZ);
180
181
case INDEX_op_qemu_ld_i32:
182
case INDEX_op_qemu_ld_i64:
183
- return &r_l;
184
+ return C_O1_I1(r, l);
185
case INDEX_op_qemu_st_i32:
186
case INDEX_op_qemu_st_i64:
187
- return &lZ_l;
188
+ return C_O0_I2(lZ, l);
189
190
case INDEX_op_deposit_i32:
191
case INDEX_op_deposit_i64:
192
- return &dep;
193
+ return C_O1_I2(r, 0, rZ);
194
195
case INDEX_op_extract2_i32:
196
case INDEX_op_extract2_i64:
197
- return &ext2;
198
+ return C_O1_I2(r, rZ, rZ);
199
200
case INDEX_op_add2_i32:
201
case INDEX_op_add2_i64:
202
case INDEX_op_sub2_i32:
203
case INDEX_op_sub2_i64:
204
- return &add2;
205
+ return C_O2_I4(r, r, rZ, rZ, rA, rMZ);
206
207
case INDEX_op_add_vec:
208
case INDEX_op_sub_vec:
209
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
210
case INDEX_op_shrv_vec:
211
case INDEX_op_sarv_vec:
212
case INDEX_op_aa64_sshl_vec:
213
- return &w_w_w;
214
+ return C_O1_I2(w, w, w);
215
case INDEX_op_not_vec:
216
case INDEX_op_neg_vec:
217
case INDEX_op_abs_vec:
218
case INDEX_op_shli_vec:
219
case INDEX_op_shri_vec:
220
case INDEX_op_sari_vec:
221
- return &w_w;
222
+ return C_O1_I1(w, w);
223
case INDEX_op_ld_vec:
224
- case INDEX_op_st_vec:
225
case INDEX_op_dupm_vec:
226
- return &w_r;
227
+ return C_O1_I1(w, r);
228
+ case INDEX_op_st_vec:
229
+ return C_O0_I2(w, r);
230
case INDEX_op_dup_vec:
231
- return &w_wr;
232
+ return C_O1_I1(w, wr);
233
case INDEX_op_or_vec:
234
case INDEX_op_andc_vec:
235
- return &w_w_wO;
236
+ return C_O1_I2(w, w, wO);
237
case INDEX_op_and_vec:
238
case INDEX_op_orc_vec:
239
- return &w_w_wN;
240
+ return C_O1_I2(w, w, wN);
241
case INDEX_op_cmp_vec:
242
- return &w_w_wZ;
243
+ return C_O1_I2(w, w, wZ);
244
case INDEX_op_bitsel_vec:
245
- return &w_w_w_w;
246
+ return C_O1_I3(w, w, w, w);
247
case INDEX_op_aa64_sli_vec:
248
- return &w_0_w;
249
+ return C_O1_I2(w, 0, w);
250
251
default:
252
- return NULL;
253
+ g_assert_not_reached();
254
}
255
}
256
257
--
258
2.25.1
259
260
diff view generated by jsdifflib
[PULL 17/24] tcg/arm: Split out constraint sets to tcg-target-con-set.h
Deleted patch
1
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
2
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
3
---
4
tcg/arm/tcg-target-con-set.h | 35 ++++++++++++++
5
tcg/arm/tcg-target.h | 1 +
6
tcg/arm/tcg-target.c.inc | 94 ++++++++++++------------------------
7
3 files changed, 68 insertions(+), 62 deletions(-)
8
create mode 100644 tcg/arm/tcg-target-con-set.h
9
1
10
diff --git a/tcg/arm/tcg-target-con-set.h b/tcg/arm/tcg-target-con-set.h
11
new file mode 100644
12
index XXXXXXX..XXXXXXX
13
--- /dev/null
14
+++ b/tcg/arm/tcg-target-con-set.h
15
@@ -XXX,XX +XXX,XX @@
16
+/* SPDX-License-Identifier: MIT */
17
+/*
18
+ * Define Arm target-specific constraint sets.
19
+ * Copyright (c) 2021 Linaro
20
+ */
21
+
22
+/*
23
+ * C_On_Im(...) defines a constraint set with <n> outputs and <m> inputs.
24
+ * Each operand should be a sequence of constraint letters as defined by
25
+ * tcg-target-con-str.h; the constraint combination is inclusive or.
26
+ */
27
+C_O0_I1(r)
28
+C_O0_I2(r, r)
29
+C_O0_I2(r, rIN)
30
+C_O0_I2(s, s)
31
+C_O0_I3(s, s, s)
32
+C_O0_I4(r, r, rI, rI)
33
+C_O0_I4(s, s, s, s)
34
+C_O1_I1(r, l)
35
+C_O1_I1(r, r)
36
+C_O1_I2(r, 0, rZ)
37
+C_O1_I2(r, l, l)
38
+C_O1_I2(r, r, r)
39
+C_O1_I2(r, r, rI)
40
+C_O1_I2(r, r, rIK)
41
+C_O1_I2(r, r, rIN)
42
+C_O1_I2(r, r, ri)
43
+C_O1_I2(r, rZ, rZ)
44
+C_O1_I4(r, r, r, rI, rI)
45
+C_O1_I4(r, r, rIN, rIK, 0)
46
+C_O2_I1(r, r, l)
47
+C_O2_I2(r, r, l, l)
48
+C_O2_I2(r, r, r, r)
49
+C_O2_I4(r, r, r, r, rIN, rIK)
50
+C_O2_I4(r, r, rI, rI, rIN, rIK)
51
diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
52
index XXXXXXX..XXXXXXX 100644
53
--- a/tcg/arm/tcg-target.h
54
+++ b/tcg/arm/tcg-target.h
55
@@ -XXX,XX +XXX,XX @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t);
56
#define TCG_TARGET_NEED_LDST_LABELS
57
#endif
58
#define TCG_TARGET_NEED_POOL_LABELS
59
+#define TCG_TARGET_CON_SET_H
60
61
#endif
62
diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
63
index XXXXXXX..XXXXXXX 100644
64
--- a/tcg/arm/tcg-target.c.inc
65
+++ b/tcg/arm/tcg-target.c.inc
66
@@ -XXX,XX +XXX,XX @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
67
}
68
}
69
70
-static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
71
+static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
72
{
73
- static const TCGTargetOpDef r = { .args_ct_str = { "r" } };
74
- static const TCGTargetOpDef r_r = { .args_ct_str = { "r", "r" } };
75
- static const TCGTargetOpDef s_s = { .args_ct_str = { "s", "s" } };
76
- static const TCGTargetOpDef r_l = { .args_ct_str = { "r", "l" } };
77
- static const TCGTargetOpDef r_r_r = { .args_ct_str = { "r", "r", "r" } };
78
- static const TCGTargetOpDef r_r_l = { .args_ct_str = { "r", "r", "l" } };
79
- static const TCGTargetOpDef r_l_l = { .args_ct_str = { "r", "l", "l" } };
80
- static const TCGTargetOpDef s_s_s = { .args_ct_str = { "s", "s", "s" } };
81
- static const TCGTargetOpDef r_r_ri = { .args_ct_str = { "r", "r", "ri" } };
82
- static const TCGTargetOpDef r_r_rI = { .args_ct_str = { "r", "r", "rI" } };
83
- static const TCGTargetOpDef r_r_rIN
84
- = { .args_ct_str = { "r", "r", "rIN" } };
85
- static const TCGTargetOpDef r_r_rIK
86
- = { .args_ct_str = { "r", "r", "rIK" } };
87
- static const TCGTargetOpDef r_r_r_r
88
- = { .args_ct_str = { "r", "r", "r", "r" } };
89
- static const TCGTargetOpDef r_r_l_l
90
- = { .args_ct_str = { "r", "r", "l", "l" } };
91
- static const TCGTargetOpDef s_s_s_s
92
- = { .args_ct_str = { "s", "s", "s", "s" } };
93
- static const TCGTargetOpDef br
94
- = { .args_ct_str = { "r", "rIN" } };
95
- static const TCGTargetOpDef ext2
96
- = { .args_ct_str = { "r", "rZ", "rZ" } };
97
- static const TCGTargetOpDef dep
98
- = { .args_ct_str = { "r", "0", "rZ" } };
99
- static const TCGTargetOpDef movc
100
- = { .args_ct_str = { "r", "r", "rIN", "rIK", "0" } };
101
- static const TCGTargetOpDef add2
102
- = { .args_ct_str = { "r", "r", "r", "r", "rIN", "rIK" } };
103
- static const TCGTargetOpDef sub2
104
- = { .args_ct_str = { "r", "r", "rI", "rI", "rIN", "rIK" } };
105
- static const TCGTargetOpDef br2
106
- = { .args_ct_str = { "r", "r", "rI", "rI" } };
107
- static const TCGTargetOpDef setc2
108
- = { .args_ct_str = { "r", "r", "r", "rI", "rI" } };
109
-
110
switch (op) {
111
case INDEX_op_goto_ptr:
112
- return &r;
113
+ return C_O0_I1(r);
114
115
case INDEX_op_ld8u_i32:
116
case INDEX_op_ld8s_i32:
117
case INDEX_op_ld16u_i32:
118
case INDEX_op_ld16s_i32:
119
case INDEX_op_ld_i32:
120
- case INDEX_op_st8_i32:
121
- case INDEX_op_st16_i32:
122
- case INDEX_op_st_i32:
123
case INDEX_op_neg_i32:
124
case INDEX_op_not_i32:
125
case INDEX_op_bswap16_i32:
126
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
127
case INDEX_op_ext16u_i32:
128
case INDEX_op_extract_i32:
129
case INDEX_op_sextract_i32:
130
- return &r_r;
131
+ return C_O1_I1(r, r);
132
+
133
+ case INDEX_op_st8_i32:
134
+ case INDEX_op_st16_i32:
135
+ case INDEX_op_st_i32:
136
+ return C_O0_I2(r, r);
137
138
case INDEX_op_add_i32:
139
case INDEX_op_sub_i32:
140
case INDEX_op_setcond_i32:
141
- return &r_r_rIN;
142
+ return C_O1_I2(r, r, rIN);
143
+
144
case INDEX_op_and_i32:
145
case INDEX_op_andc_i32:
146
case INDEX_op_clz_i32:
147
case INDEX_op_ctz_i32:
148
- return &r_r_rIK;
149
+ return C_O1_I2(r, r, rIK);
150
+
151
case INDEX_op_mul_i32:
152
case INDEX_op_div_i32:
153
case INDEX_op_divu_i32:
154
- return &r_r_r;
155
+ return C_O1_I2(r, r, r);
156
+
157
case INDEX_op_mulu2_i32:
158
case INDEX_op_muls2_i32:
159
- return &r_r_r_r;
160
+ return C_O2_I2(r, r, r, r);
161
+
162
case INDEX_op_or_i32:
163
case INDEX_op_xor_i32:
164
- return &r_r_rI;
165
+ return C_O1_I2(r, r, rI);
166
+
167
case INDEX_op_shl_i32:
168
case INDEX_op_shr_i32:
169
case INDEX_op_sar_i32:
170
case INDEX_op_rotl_i32:
171
case INDEX_op_rotr_i32:
172
- return &r_r_ri;
173
+ return C_O1_I2(r, r, ri);
174
175
case INDEX_op_brcond_i32:
176
- return &br;
177
+ return C_O0_I2(r, rIN);
178
case INDEX_op_deposit_i32:
179
- return &dep;
180
+ return C_O1_I2(r, 0, rZ);
181
case INDEX_op_extract2_i32:
182
- return &ext2;
183
+ return C_O1_I2(r, rZ, rZ);
184
case INDEX_op_movcond_i32:
185
- return &movc;
186
+ return C_O1_I4(r, r, rIN, rIK, 0);
187
case INDEX_op_add2_i32:
188
- return &add2;
189
+ return C_O2_I4(r, r, r, r, rIN, rIK);
190
case INDEX_op_sub2_i32:
191
- return &sub2;
192
+ return C_O2_I4(r, r, rI, rI, rIN, rIK);
193
case INDEX_op_brcond2_i32:
194
- return &br2;
195
+ return C_O0_I4(r, r, rI, rI);
196
case INDEX_op_setcond2_i32:
197
- return &setc2;
198
+ return C_O1_I4(r, r, r, rI, rI);
199
200
case INDEX_op_qemu_ld_i32:
201
- return TARGET_LONG_BITS == 32 ? &r_l : &r_l_l;
202
+ return TARGET_LONG_BITS == 32 ? C_O1_I1(r, l) : C_O1_I2(r, l, l);
203
case INDEX_op_qemu_ld_i64:
204
- return TARGET_LONG_BITS == 32 ? &r_r_l : &r_r_l_l;
205
+ return TARGET_LONG_BITS == 32 ? C_O2_I1(r, r, l) : C_O2_I2(r, r, l, l);
206
case INDEX_op_qemu_st_i32:
207
- return TARGET_LONG_BITS == 32 ? &s_s : &s_s_s;
208
+ return TARGET_LONG_BITS == 32 ? C_O0_I2(s, s) : C_O0_I3(s, s, s);
209
case INDEX_op_qemu_st_i64:
210
- return TARGET_LONG_BITS == 32 ? &s_s_s : &s_s_s_s;
211
+ return TARGET_LONG_BITS == 32 ? C_O0_I3(s, s, s) : C_O0_I4(s, s, s, s);
212
213
default:
214
- return NULL;
215
+ g_assert_not_reached();
216
}
217
}
218
219
--
220
2.25.1
221
222
diff view generated by jsdifflib
[PULL 18/24] tcg/mips: Split out constraint sets to tcg-target-con-set.h
Deleted patch
1
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
2
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
3
---
4
tcg/mips/tcg-target-con-set.h | 36 +++++++++++++
5
tcg/mips/tcg-target.h | 1 +
6
tcg/mips/tcg-target.c.inc | 96 +++++++++++------------------------
7
3 files changed, 66 insertions(+), 67 deletions(-)
8
create mode 100644 tcg/mips/tcg-target-con-set.h
9
1
10
diff --git a/tcg/mips/tcg-target-con-set.h b/tcg/mips/tcg-target-con-set.h
11
new file mode 100644
12
index XXXXXXX..XXXXXXX
13
--- /dev/null
14
+++ b/tcg/mips/tcg-target-con-set.h
15
@@ -XXX,XX +XXX,XX @@
16
+/* SPDX-License-Identifier: MIT */
17
+/*
18
+ * Define MIPS target-specific constraint sets.
19
+ * Copyright (c) 2021 Linaro
20
+ */
21
+
22
+/*
23
+ * C_On_Im(...) defines a constraint set with <n> outputs and <m> inputs.
24
+ * Each operand should be a sequence of constraint letters as defined by
25
+ * tcg-target-con-str.h; the constraint combination is inclusive or.
26
+ */
27
+C_O0_I1(r)
28
+C_O0_I2(rZ, r)
29
+C_O0_I2(rZ, rZ)
30
+C_O0_I2(SZ, S)
31
+C_O0_I3(SZ, S, S)
32
+C_O0_I3(SZ, SZ, S)
33
+C_O0_I4(rZ, rZ, rZ, rZ)
34
+C_O0_I4(SZ, SZ, S, S)
35
+C_O1_I1(r, L)
36
+C_O1_I1(r, r)
37
+C_O1_I2(r, 0, rZ)
38
+C_O1_I2(r, L, L)
39
+C_O1_I2(r, r, ri)
40
+C_O1_I2(r, r, rI)
41
+C_O1_I2(r, r, rIK)
42
+C_O1_I2(r, r, rJ)
43
+C_O1_I2(r, r, rWZ)
44
+C_O1_I2(r, rZ, rN)
45
+C_O1_I2(r, rZ, rZ)
46
+C_O1_I4(r, rZ, rZ, rZ, 0)
47
+C_O1_I4(r, rZ, rZ, rZ, rZ)
48
+C_O2_I1(r, r, L)
49
+C_O2_I2(r, r, L, L)
50
+C_O2_I2(r, r, r, r)
51
+C_O2_I4(r, r, rZ, rZ, rN, rN)
52
diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h
53
index XXXXXXX..XXXXXXX 100644
54
--- a/tcg/mips/tcg-target.h
55
+++ b/tcg/mips/tcg-target.h
56
@@ -XXX,XX +XXX,XX @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t);
57
#ifdef CONFIG_SOFTMMU
58
#define TCG_TARGET_NEED_LDST_LABELS
59
#endif
60
+#define TCG_TARGET_CON_SET_H
61
62
#endif
63
diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc
64
index XXXXXXX..XXXXXXX 100644
65
--- a/tcg/mips/tcg-target.c.inc
66
+++ b/tcg/mips/tcg-target.c.inc
67
@@ -XXX,XX +XXX,XX @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
68
}
69
}
70
71
-static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
72
+static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
73
{
74
- static const TCGTargetOpDef r = { .args_ct_str = { "r" } };
75
- static const TCGTargetOpDef r_r = { .args_ct_str = { "r", "r" } };
76
- static const TCGTargetOpDef r_L = { .args_ct_str = { "r", "L" } };
77
- static const TCGTargetOpDef rZ_r = { .args_ct_str = { "rZ", "r" } };
78
- static const TCGTargetOpDef SZ_S = { .args_ct_str = { "SZ", "S" } };
79
- static const TCGTargetOpDef rZ_rZ = { .args_ct_str = { "rZ", "rZ" } };
80
- static const TCGTargetOpDef r_r_L = { .args_ct_str = { "r", "r", "L" } };
81
- static const TCGTargetOpDef r_L_L = { .args_ct_str = { "r", "L", "L" } };
82
- static const TCGTargetOpDef r_r_ri = { .args_ct_str = { "r", "r", "ri" } };
83
- static const TCGTargetOpDef r_r_rI = { .args_ct_str = { "r", "r", "rI" } };
84
- static const TCGTargetOpDef r_r_rJ = { .args_ct_str = { "r", "r", "rJ" } };
85
- static const TCGTargetOpDef SZ_S_S = { .args_ct_str = { "SZ", "S", "S" } };
86
- static const TCGTargetOpDef SZ_SZ_S
87
- = { .args_ct_str = { "SZ", "SZ", "S" } };
88
- static const TCGTargetOpDef SZ_SZ_S_S
89
- = { .args_ct_str = { "SZ", "SZ", "S", "S" } };
90
- static const TCGTargetOpDef r_rZ_rN
91
- = { .args_ct_str = { "r", "rZ", "rN" } };
92
- static const TCGTargetOpDef r_rZ_rZ
93
- = { .args_ct_str = { "r", "rZ", "rZ" } };
94
- static const TCGTargetOpDef r_r_rIK
95
- = { .args_ct_str = { "r", "r", "rIK" } };
96
- static const TCGTargetOpDef r_r_rWZ
97
- = { .args_ct_str = { "r", "r", "rWZ" } };
98
- static const TCGTargetOpDef r_r_r_r
99
- = { .args_ct_str = { "r", "r", "r", "r" } };
100
- static const TCGTargetOpDef r_r_L_L
101
- = { .args_ct_str = { "r", "r", "L", "L" } };
102
- static const TCGTargetOpDef dep
103
- = { .args_ct_str = { "r", "0", "rZ" } };
104
- static const TCGTargetOpDef movc
105
- = { .args_ct_str = { "r", "rZ", "rZ", "rZ", "0" } };
106
- static const TCGTargetOpDef movc_r6
107
- = { .args_ct_str = { "r", "rZ", "rZ", "rZ", "rZ" } };
108
- static const TCGTargetOpDef add2
109
- = { .args_ct_str = { "r", "r", "rZ", "rZ", "rN", "rN" } };
110
- static const TCGTargetOpDef br2
111
- = { .args_ct_str = { "rZ", "rZ", "rZ", "rZ" } };
112
- static const TCGTargetOpDef setc2
113
- = { .args_ct_str = { "r", "rZ", "rZ", "rZ", "rZ" } };
114
-
115
switch (op) {
116
case INDEX_op_goto_ptr:
117
- return &r;
118
+ return C_O0_I1(r);
119
120
case INDEX_op_ld8u_i32:
121
case INDEX_op_ld8s_i32:
122
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
123
case INDEX_op_extrl_i64_i32:
124
case INDEX_op_extrh_i64_i32:
125
case INDEX_op_extract_i64:
126
- return &r_r;
127
+ return C_O1_I1(r, r);
128
129
case INDEX_op_st8_i32:
130
case INDEX_op_st16_i32:
131
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
132
case INDEX_op_st16_i64:
133
case INDEX_op_st32_i64:
134
case INDEX_op_st_i64:
135
- return &rZ_r;
136
+ return C_O0_I2(rZ, r);
137
138
case INDEX_op_add_i32:
139
case INDEX_op_add_i64:
140
- return &r_r_rJ;
141
+ return C_O1_I2(r, r, rJ);
142
case INDEX_op_sub_i32:
143
case INDEX_op_sub_i64:
144
- return &r_rZ_rN;
145
+ return C_O1_I2(r, rZ, rN);
146
case INDEX_op_mul_i32:
147
case INDEX_op_mulsh_i32:
148
case INDEX_op_muluh_i32:
149
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
150
case INDEX_op_remu_i64:
151
case INDEX_op_nor_i64:
152
case INDEX_op_setcond_i64:
153
- return &r_rZ_rZ;
154
+ return C_O1_I2(r, rZ, rZ);
155
case INDEX_op_muls2_i32:
156
case INDEX_op_mulu2_i32:
157
case INDEX_op_muls2_i64:
158
case INDEX_op_mulu2_i64:
159
- return &r_r_r_r;
160
+ return C_O2_I2(r, r, r, r);
161
case INDEX_op_and_i32:
162
case INDEX_op_and_i64:
163
- return &r_r_rIK;
164
+ return C_O1_I2(r, r, rIK);
165
case INDEX_op_or_i32:
166
case INDEX_op_xor_i32:
167
case INDEX_op_or_i64:
168
case INDEX_op_xor_i64:
169
- return &r_r_rI;
170
+ return C_O1_I2(r, r, rI);
171
case INDEX_op_shl_i32:
172
case INDEX_op_shr_i32:
173
case INDEX_op_sar_i32:
174
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
175
case INDEX_op_sar_i64:
176
case INDEX_op_rotr_i64:
177
case INDEX_op_rotl_i64:
178
- return &r_r_ri;
179
+ return C_O1_I2(r, r, ri);
180
case INDEX_op_clz_i32:
181
case INDEX_op_clz_i64:
182
- return &r_r_rWZ;
183
+ return C_O1_I2(r, r, rWZ);
184
185
case INDEX_op_deposit_i32:
186
case INDEX_op_deposit_i64:
187
- return &dep;
188
+ return C_O1_I2(r, 0, rZ);
189
case INDEX_op_brcond_i32:
190
case INDEX_op_brcond_i64:
191
- return &rZ_rZ;
192
+ return C_O0_I2(rZ, rZ);
193
case INDEX_op_movcond_i32:
194
case INDEX_op_movcond_i64:
195
- return use_mips32r6_instructions ? &movc_r6 : &movc;
196
-
197
+ return (use_mips32r6_instructions
198
+ ? C_O1_I4(r, rZ, rZ, rZ, rZ)
199
+ : C_O1_I4(r, rZ, rZ, rZ, 0));
200
case INDEX_op_add2_i32:
201
case INDEX_op_sub2_i32:
202
- return &add2;
203
+ return C_O2_I4(r, r, rZ, rZ, rN, rN);
204
case INDEX_op_setcond2_i32:
205
- return &setc2;
206
+ return C_O1_I4(r, rZ, rZ, rZ, rZ);
207
case INDEX_op_brcond2_i32:
208
- return &br2;
209
+ return C_O0_I4(rZ, rZ, rZ, rZ);
210
211
case INDEX_op_qemu_ld_i32:
212
return (TCG_TARGET_REG_BITS == 64 || TARGET_LONG_BITS == 32
213
- ? &r_L : &r_L_L);
214
+ ? C_O1_I1(r, L) : C_O1_I2(r, L, L));
215
case INDEX_op_qemu_st_i32:
216
return (TCG_TARGET_REG_BITS == 64 || TARGET_LONG_BITS == 32
217
- ? &SZ_S : &SZ_S_S);
218
+ ? C_O0_I2(SZ, S) : C_O0_I3(SZ, S, S));
219
case INDEX_op_qemu_ld_i64:
220
- return (TCG_TARGET_REG_BITS == 64 ? &r_L
221
- : TARGET_LONG_BITS == 32 ? &r_r_L : &r_r_L_L);
222
+ return (TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, L)
223
+ : TARGET_LONG_BITS == 32 ? C_O2_I1(r, r, L)
224
+ : C_O2_I2(r, r, L, L));
225
case INDEX_op_qemu_st_i64:
226
- return (TCG_TARGET_REG_BITS == 64 ? &SZ_S
227
- : TARGET_LONG_BITS == 32 ? &SZ_SZ_S : &SZ_SZ_S_S);
228
+ return (TCG_TARGET_REG_BITS == 64 ? C_O0_I2(SZ, S)
229
+ : TARGET_LONG_BITS == 32 ? C_O0_I3(SZ, SZ, S)
230
+ : C_O0_I4(SZ, SZ, S, S));
231
232
default:
233
- return NULL;
234
+ g_assert_not_reached();
235
}
236
}
237
238
--
239
2.25.1
240
241
diff view generated by jsdifflib
[PULL 19/24] tcg/ppc: Split out constraint sets to tcg-target-con-set.h
Deleted patch
1
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
2
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
3
---
4
tcg/ppc/tcg-target-con-set.h | 42 +++++++++++
5
tcg/ppc/tcg-target.h | 1 +
6
tcg/ppc/tcg-target.c.inc | 136 +++++++++++++++--------------------
7
3 files changed, 99 insertions(+), 80 deletions(-)
8
create mode 100644 tcg/ppc/tcg-target-con-set.h
9
1
10
diff --git a/tcg/ppc/tcg-target-con-set.h b/tcg/ppc/tcg-target-con-set.h
11
new file mode 100644
12
index XXXXXXX..XXXXXXX
13
--- /dev/null
14
+++ b/tcg/ppc/tcg-target-con-set.h
15
@@ -XXX,XX +XXX,XX @@
16
+/* SPDX-License-Identifier: MIT */
17
+/*
18
+ * Define PowerPC target-specific constraint sets.
19
+ * Copyright (c) 2021 Linaro
20
+ */
21
+
22
+/*
23
+ * C_On_Im(...) defines a constraint set with <n> outputs and <m> inputs.
24
+ * Each operand should be a sequence of constraint letters as defined by
25
+ * tcg-target-con-str.h; the constraint combination is inclusive or.
26
+ */
27
+C_O0_I1(r)
28
+C_O0_I2(r, r)
29
+C_O0_I2(r, ri)
30
+C_O0_I2(S, S)
31
+C_O0_I2(v, r)
32
+C_O0_I3(S, S, S)
33
+C_O0_I4(r, r, ri, ri)
34
+C_O0_I4(S, S, S, S)
35
+C_O1_I1(r, L)
36
+C_O1_I1(r, r)
37
+C_O1_I1(v, r)
38
+C_O1_I1(v, v)
39
+C_O1_I1(v, vr)
40
+C_O1_I2(r, 0, rZ)
41
+C_O1_I2(r, L, L)
42
+C_O1_I2(r, rI, ri)
43
+C_O1_I2(r, rI, rT)
44
+C_O1_I2(r, r, r)
45
+C_O1_I2(r, r, ri)
46
+C_O1_I2(r, r, rI)
47
+C_O1_I2(r, r, rT)
48
+C_O1_I2(r, r, rU)
49
+C_O1_I2(r, r, rZW)
50
+C_O1_I2(v, v, v)
51
+C_O1_I3(v, v, v, v)
52
+C_O1_I4(r, r, ri, rZ, rZ)
53
+C_O1_I4(r, r, r, ri, ri)
54
+C_O2_I1(L, L, L)
55
+C_O2_I2(L, L, L, L)
56
+C_O2_I4(r, r, rI, rZM, r, r)
57
+C_O2_I4(r, r, r, r, rI, rZM)
58
diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h
59
index XXXXXXX..XXXXXXX 100644
60
--- a/tcg/ppc/tcg-target.h
61
+++ b/tcg/ppc/tcg-target.h
62
@@ -XXX,XX +XXX,XX @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t);
63
#define TCG_TARGET_NEED_LDST_LABELS
64
#endif
65
#define TCG_TARGET_NEED_POOL_LABELS
66
+#define TCG_TARGET_CON_SET_H
67
68
#endif
69
diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc
70
index XXXXXXX..XXXXXXX 100644
71
--- a/tcg/ppc/tcg-target.c.inc
72
+++ b/tcg/ppc/tcg-target.c.inc
73
@@ -XXX,XX +XXX,XX @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece,
74
va_end(va);
75
}
76
77
-static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
78
+static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
79
{
80
- static const TCGTargetOpDef r = { .args_ct_str = { "r" } };
81
- static const TCGTargetOpDef r_r = { .args_ct_str = { "r", "r" } };
82
- static const TCGTargetOpDef r_L = { .args_ct_str = { "r", "L" } };
83
- static const TCGTargetOpDef S_S = { .args_ct_str = { "S", "S" } };
84
- static const TCGTargetOpDef r_ri = { .args_ct_str = { "r", "ri" } };
85
- static const TCGTargetOpDef r_r_r = { .args_ct_str = { "r", "r", "r" } };
86
- static const TCGTargetOpDef r_L_L = { .args_ct_str = { "r", "L", "L" } };
87
- static const TCGTargetOpDef L_L_L = { .args_ct_str = { "L", "L", "L" } };
88
- static const TCGTargetOpDef S_S_S = { .args_ct_str = { "S", "S", "S" } };
89
- static const TCGTargetOpDef r_r_ri = { .args_ct_str = { "r", "r", "ri" } };
90
- static const TCGTargetOpDef r_r_rI = { .args_ct_str = { "r", "r", "rI" } };
91
- static const TCGTargetOpDef r_r_rT = { .args_ct_str = { "r", "r", "rT" } };
92
- static const TCGTargetOpDef r_r_rU = { .args_ct_str = { "r", "r", "rU" } };
93
- static const TCGTargetOpDef r_rI_ri
94
- = { .args_ct_str = { "r", "rI", "ri" } };
95
- static const TCGTargetOpDef r_rI_rT
96
- = { .args_ct_str = { "r", "rI", "rT" } };
97
- static const TCGTargetOpDef r_r_rZW
98
- = { .args_ct_str = { "r", "r", "rZW" } };
99
- static const TCGTargetOpDef L_L_L_L
100
- = { .args_ct_str = { "L", "L", "L", "L" } };
101
- static const TCGTargetOpDef S_S_S_S
102
- = { .args_ct_str = { "S", "S", "S", "S" } };
103
- static const TCGTargetOpDef movc
104
- = { .args_ct_str = { "r", "r", "ri", "rZ", "rZ" } };
105
- static const TCGTargetOpDef dep
106
- = { .args_ct_str = { "r", "0", "rZ" } };
107
- static const TCGTargetOpDef br2
108
- = { .args_ct_str = { "r", "r", "ri", "ri" } };
109
- static const TCGTargetOpDef setc2
110
- = { .args_ct_str = { "r", "r", "r", "ri", "ri" } };
111
- static const TCGTargetOpDef add2
112
- = { .args_ct_str = { "r", "r", "r", "r", "rI", "rZM" } };
113
- static const TCGTargetOpDef sub2
114
- = { .args_ct_str = { "r", "r", "rI", "rZM", "r", "r" } };
115
- static const TCGTargetOpDef v_r = { .args_ct_str = { "v", "r" } };
116
- static const TCGTargetOpDef v_vr = { .args_ct_str = { "v", "vr" } };
117
- static const TCGTargetOpDef v_v = { .args_ct_str = { "v", "v" } };
118
- static const TCGTargetOpDef v_v_v = { .args_ct_str = { "v", "v", "v" } };
119
- static const TCGTargetOpDef v_v_v_v
120
- = { .args_ct_str = { "v", "v", "v", "v" } };
121
-
122
switch (op) {
123
case INDEX_op_goto_ptr:
124
- return &r;
125
+ return C_O0_I1(r);
126
127
case INDEX_op_ld8u_i32:
128
case INDEX_op_ld8s_i32:
129
case INDEX_op_ld16u_i32:
130
case INDEX_op_ld16s_i32:
131
case INDEX_op_ld_i32:
132
- case INDEX_op_st8_i32:
133
- case INDEX_op_st16_i32:
134
- case INDEX_op_st_i32:
135
case INDEX_op_ctpop_i32:
136
case INDEX_op_neg_i32:
137
case INDEX_op_not_i32:
138
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
139
case INDEX_op_ld32u_i64:
140
case INDEX_op_ld32s_i64:
141
case INDEX_op_ld_i64:
142
- case INDEX_op_st8_i64:
143
- case INDEX_op_st16_i64:
144
- case INDEX_op_st32_i64:
145
- case INDEX_op_st_i64:
146
case INDEX_op_ctpop_i64:
147
case INDEX_op_neg_i64:
148
case INDEX_op_not_i64:
149
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
150
case INDEX_op_bswap32_i64:
151
case INDEX_op_bswap64_i64:
152
case INDEX_op_extract_i64:
153
- return &r_r;
154
+ return C_O1_I1(r, r);
155
+
156
+ case INDEX_op_st8_i32:
157
+ case INDEX_op_st16_i32:
158
+ case INDEX_op_st_i32:
159
+ case INDEX_op_st8_i64:
160
+ case INDEX_op_st16_i64:
161
+ case INDEX_op_st32_i64:
162
+ case INDEX_op_st_i64:
163
+ return C_O0_I2(r, r);
164
165
case INDEX_op_add_i32:
166
case INDEX_op_and_i32:
167
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
168
case INDEX_op_rotl_i64:
169
case INDEX_op_rotr_i64:
170
case INDEX_op_setcond_i64:
171
- return &r_r_ri;
172
+ return C_O1_I2(r, r, ri);
173
+
174
case INDEX_op_mul_i32:
175
case INDEX_op_mul_i64:
176
- return &r_r_rI;
177
+ return C_O1_I2(r, r, rI);
178
+
179
case INDEX_op_div_i32:
180
case INDEX_op_divu_i32:
181
case INDEX_op_nand_i32:
182
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
183
case INDEX_op_divu_i64:
184
case INDEX_op_mulsh_i64:
185
case INDEX_op_muluh_i64:
186
- return &r_r_r;
187
+ return C_O1_I2(r, r, r);
188
+
189
case INDEX_op_sub_i32:
190
- return &r_rI_ri;
191
+ return C_O1_I2(r, rI, ri);
192
case INDEX_op_add_i64:
193
- return &r_r_rT;
194
+ return C_O1_I2(r, r, rT);
195
case INDEX_op_or_i64:
196
case INDEX_op_xor_i64:
197
- return &r_r_rU;
198
+ return C_O1_I2(r, r, rU);
199
case INDEX_op_sub_i64:
200
- return &r_rI_rT;
201
+ return C_O1_I2(r, rI, rT);
202
case INDEX_op_clz_i32:
203
case INDEX_op_ctz_i32:
204
case INDEX_op_clz_i64:
205
case INDEX_op_ctz_i64:
206
- return &r_r_rZW;
207
+ return C_O1_I2(r, r, rZW);
208
209
case INDEX_op_brcond_i32:
210
case INDEX_op_brcond_i64:
211
- return &r_ri;
212
+ return C_O0_I2(r, ri);
213
214
case INDEX_op_movcond_i32:
215
case INDEX_op_movcond_i64:
216
- return &movc;
217
+ return C_O1_I4(r, r, ri, rZ, rZ);
218
case INDEX_op_deposit_i32:
219
case INDEX_op_deposit_i64:
220
- return &dep;
221
+ return C_O1_I2(r, 0, rZ);
222
case INDEX_op_brcond2_i32:
223
- return &br2;
224
+ return C_O0_I4(r, r, ri, ri);
225
case INDEX_op_setcond2_i32:
226
- return &setc2;
227
+ return C_O1_I4(r, r, r, ri, ri);
228
case INDEX_op_add2_i64:
229
case INDEX_op_add2_i32:
230
- return &add2;
231
+ return C_O2_I4(r, r, r, r, rI, rZM);
232
case INDEX_op_sub2_i64:
233
case INDEX_op_sub2_i32:
234
- return &sub2;
235
+ return C_O2_I4(r, r, rI, rZM, r, r);
236
237
case INDEX_op_qemu_ld_i32:
238
return (TCG_TARGET_REG_BITS == 64 || TARGET_LONG_BITS == 32
239
- ? &r_L : &r_L_L);
240
+ ? C_O1_I1(r, L)
241
+ : C_O1_I2(r, L, L));
242
+
243
case INDEX_op_qemu_st_i32:
244
return (TCG_TARGET_REG_BITS == 64 || TARGET_LONG_BITS == 32
245
- ? &S_S : &S_S_S);
246
+ ? C_O0_I2(S, S)
247
+ : C_O0_I3(S, S, S));
248
+
249
case INDEX_op_qemu_ld_i64:
250
- return (TCG_TARGET_REG_BITS == 64 ? &r_L
251
- : TARGET_LONG_BITS == 32 ? &L_L_L : &L_L_L_L);
252
+ return (TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, L)
253
+ : TARGET_LONG_BITS == 32 ? C_O2_I1(L, L, L)
254
+ : C_O2_I2(L, L, L, L));
255
+
256
case INDEX_op_qemu_st_i64:
257
- return (TCG_TARGET_REG_BITS == 64 ? &S_S
258
- : TARGET_LONG_BITS == 32 ? &S_S_S : &S_S_S_S);
259
+ return (TCG_TARGET_REG_BITS == 64 ? C_O0_I2(S, S)
260
+ : TARGET_LONG_BITS == 32 ? C_O0_I3(S, S, S)
261
+ : C_O0_I4(S, S, S, S));
262
263
case INDEX_op_add_vec:
264
case INDEX_op_sub_vec:
265
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
266
case INDEX_op_ppc_mulou_vec:
267
case INDEX_op_ppc_pkum_vec:
268
case INDEX_op_dup2_vec:
269
- return &v_v_v;
270
+ return C_O1_I2(v, v, v);
271
+
272
case INDEX_op_not_vec:
273
case INDEX_op_neg_vec:
274
- return &v_v;
275
+ return C_O1_I1(v, v);
276
+
277
case INDEX_op_dup_vec:
278
- return have_isa_3_00 ? &v_vr : &v_v;
279
+ return have_isa_3_00 ? C_O1_I1(v, vr) : C_O1_I1(v, v);
280
+
281
case INDEX_op_ld_vec:
282
- case INDEX_op_st_vec:
283
case INDEX_op_dupm_vec:
284
- return &v_r;
285
+ return C_O1_I1(v, r);
286
+
287
+ case INDEX_op_st_vec:
288
+ return C_O0_I2(v, r);
289
+
290
case INDEX_op_bitsel_vec:
291
case INDEX_op_ppc_msum_vec:
292
- return &v_v_v_v;
293
+ return C_O1_I3(v, v, v, v);
294
295
default:
296
- return NULL;
297
+ g_assert_not_reached();
298
}
299
}
300
301
--
302
2.25.1
303
304
diff view generated by jsdifflib
[PULL 20/24] tcg/riscv: Split out constraint sets to tcg-target-con-set.h
Deleted patch
1
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
2
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
---
5
tcg/riscv/tcg-target-con-set.h | 30 ++++++++++++
6
tcg/riscv/tcg-target.h | 1 +
7
tcg/riscv/tcg-target.c.inc | 83 ++++++++++------------------------
8
3 files changed, 54 insertions(+), 60 deletions(-)
9
create mode 100644 tcg/riscv/tcg-target-con-set.h
10
1
11
diff --git a/tcg/riscv/tcg-target-con-set.h b/tcg/riscv/tcg-target-con-set.h
12
new file mode 100644
13
index XXXXXXX..XXXXXXX
14
--- /dev/null
15
+++ b/tcg/riscv/tcg-target-con-set.h
16
@@ -XXX,XX +XXX,XX @@
17
+/* SPDX-License-Identifier: MIT */
18
+/*
19
+ * Define RISC-V target-specific constraint sets.
20
+ * Copyright (c) 2021 Linaro
21
+ */
22
+
23
+/*
24
+ * C_On_Im(...) defines a constraint set with <n> outputs and <m> inputs.
25
+ * Each operand should be a sequence of constraint letters as defined by
26
+ * tcg-target-con-str.h; the constraint combination is inclusive or.
27
+ */
28
+C_O0_I1(r)
29
+C_O0_I2(LZ, L)
30
+C_O0_I2(rZ, r)
31
+C_O0_I2(rZ, rZ)
32
+C_O0_I3(LZ, L, L)
33
+C_O0_I3(LZ, LZ, L)
34
+C_O0_I4(LZ, LZ, L, L)
35
+C_O0_I4(rZ, rZ, rZ, rZ)
36
+C_O1_I1(r, L)
37
+C_O1_I1(r, r)
38
+C_O1_I2(r, L, L)
39
+C_O1_I2(r, r, ri)
40
+C_O1_I2(r, r, rI)
41
+C_O1_I2(r, rZ, rN)
42
+C_O1_I2(r, rZ, rZ)
43
+C_O1_I4(r, rZ, rZ, rZ, rZ)
44
+C_O2_I1(r, r, L)
45
+C_O2_I2(r, r, L, L)
46
+C_O2_I4(r, r, rZ, rZ, rM, rM)
47
diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h
48
index XXXXXXX..XXXXXXX 100644
49
--- a/tcg/riscv/tcg-target.h
50
+++ b/tcg/riscv/tcg-target.h
51
@@ -XXX,XX +XXX,XX @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t);
52
#define TCG_TARGET_NEED_POOL_LABELS
53
54
#define TCG_TARGET_HAS_MEMORY_BSWAP 0
55
+#define TCG_TARGET_CON_SET_H
56
57
#endif
58
diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
59
index XXXXXXX..XXXXXXX 100644
60
--- a/tcg/riscv/tcg-target.c.inc
61
+++ b/tcg/riscv/tcg-target.c.inc
62
@@ -XXX,XX +XXX,XX @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
63
}
64
}
65
66
-static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
67
+static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
68
{
69
- static const TCGTargetOpDef r
70
- = { .args_ct_str = { "r" } };
71
- static const TCGTargetOpDef r_r
72
- = { .args_ct_str = { "r", "r" } };
73
- static const TCGTargetOpDef rZ_r
74
- = { .args_ct_str = { "rZ", "r" } };
75
- static const TCGTargetOpDef rZ_rZ
76
- = { .args_ct_str = { "rZ", "rZ" } };
77
- static const TCGTargetOpDef rZ_rZ_rZ_rZ
78
- = { .args_ct_str = { "rZ", "rZ", "rZ", "rZ" } };
79
- static const TCGTargetOpDef r_r_ri
80
- = { .args_ct_str = { "r", "r", "ri" } };
81
- static const TCGTargetOpDef r_r_rI
82
- = { .args_ct_str = { "r", "r", "rI" } };
83
- static const TCGTargetOpDef r_rZ_rN
84
- = { .args_ct_str = { "r", "rZ", "rN" } };
85
- static const TCGTargetOpDef r_rZ_rZ
86
- = { .args_ct_str = { "r", "rZ", "rZ" } };
87
- static const TCGTargetOpDef r_rZ_rZ_rZ_rZ
88
- = { .args_ct_str = { "r", "rZ", "rZ", "rZ", "rZ" } };
89
- static const TCGTargetOpDef r_L
90
- = { .args_ct_str = { "r", "L" } };
91
- static const TCGTargetOpDef r_r_L
92
- = { .args_ct_str = { "r", "r", "L" } };
93
- static const TCGTargetOpDef r_L_L
94
- = { .args_ct_str = { "r", "L", "L" } };
95
- static const TCGTargetOpDef r_r_L_L
96
- = { .args_ct_str = { "r", "r", "L", "L" } };
97
- static const TCGTargetOpDef LZ_L
98
- = { .args_ct_str = { "LZ", "L" } };
99
- static const TCGTargetOpDef LZ_L_L
100
- = { .args_ct_str = { "LZ", "L", "L" } };
101
- static const TCGTargetOpDef LZ_LZ_L
102
- = { .args_ct_str = { "LZ", "LZ", "L" } };
103
- static const TCGTargetOpDef LZ_LZ_L_L
104
- = { .args_ct_str = { "LZ", "LZ", "L", "L" } };
105
- static const TCGTargetOpDef r_r_rZ_rZ_rM_rM
106
- = { .args_ct_str = { "r", "r", "rZ", "rZ", "rM", "rM" } };
107
-
108
switch (op) {
109
case INDEX_op_goto_ptr:
110
- return &r;
111
+ return C_O0_I1(r);
112
113
case INDEX_op_ld8u_i32:
114
case INDEX_op_ld8s_i32:
115
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
116
case INDEX_op_extrl_i64_i32:
117
case INDEX_op_extrh_i64_i32:
118
case INDEX_op_ext_i32_i64:
119
- return &r_r;
120
+ return C_O1_I1(r, r);
121
122
case INDEX_op_st8_i32:
123
case INDEX_op_st16_i32:
124
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
125
case INDEX_op_st16_i64:
126
case INDEX_op_st32_i64:
127
case INDEX_op_st_i64:
128
- return &rZ_r;
129
+ return C_O0_I2(rZ, r);
130
131
case INDEX_op_add_i32:
132
case INDEX_op_and_i32:
133
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
134
case INDEX_op_and_i64:
135
case INDEX_op_or_i64:
136
case INDEX_op_xor_i64:
137
- return &r_r_rI;
138
+ return C_O1_I2(r, r, rI);
139
140
case INDEX_op_sub_i32:
141
case INDEX_op_sub_i64:
142
- return &r_rZ_rN;
143
+ return C_O1_I2(r, rZ, rN);
144
145
case INDEX_op_mul_i32:
146
case INDEX_op_mulsh_i32:
147
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
148
case INDEX_op_rem_i64:
149
case INDEX_op_remu_i64:
150
case INDEX_op_setcond_i64:
151
- return &r_rZ_rZ;
152
+ return C_O1_I2(r, rZ, rZ);
153
154
case INDEX_op_shl_i32:
155
case INDEX_op_shr_i32:
156
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
157
case INDEX_op_shl_i64:
158
case INDEX_op_shr_i64:
159
case INDEX_op_sar_i64:
160
- return &r_r_ri;
161
+ return C_O1_I2(r, r, ri);
162
163
case INDEX_op_brcond_i32:
164
case INDEX_op_brcond_i64:
165
- return &rZ_rZ;
166
+ return C_O0_I2(rZ, rZ);
167
168
case INDEX_op_add2_i32:
169
case INDEX_op_add2_i64:
170
case INDEX_op_sub2_i32:
171
case INDEX_op_sub2_i64:
172
- return &r_r_rZ_rZ_rM_rM;
173
+ return C_O2_I4(r, r, rZ, rZ, rM, rM);
174
175
case INDEX_op_brcond2_i32:
176
- return &rZ_rZ_rZ_rZ;
177
+ return C_O0_I4(rZ, rZ, rZ, rZ);
178
179
case INDEX_op_setcond2_i32:
180
- return &r_rZ_rZ_rZ_rZ;
181
+ return C_O1_I4(r, rZ, rZ, rZ, rZ);
182
183
case INDEX_op_qemu_ld_i32:
184
- return TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &r_L : &r_L_L;
185
+ return (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS
186
+ ? C_O1_I1(r, L) : C_O1_I2(r, L, L));
187
case INDEX_op_qemu_st_i32:
188
- return TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &LZ_L : &LZ_L_L;
189
+ return (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS
190
+ ? C_O0_I2(LZ, L) : C_O0_I3(LZ, L, L));
191
case INDEX_op_qemu_ld_i64:
192
- return TCG_TARGET_REG_BITS == 64 ? &r_L
193
- : TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &r_r_L
194
- : &r_r_L_L;
195
+ return (TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, L)
196
+ : TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? C_O2_I1(r, r, L)
197
+ : C_O2_I2(r, r, L, L));
198
case INDEX_op_qemu_st_i64:
199
- return TCG_TARGET_REG_BITS == 64 ? &LZ_L
200
- : TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &LZ_LZ_L
201
- : &LZ_LZ_L_L;
202
+ return (TCG_TARGET_REG_BITS == 64 ? C_O0_I2(LZ, L)
203
+ : TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? C_O0_I3(LZ, LZ, L)
204
+ : C_O0_I4(LZ, LZ, L, L));
205
206
default:
207
- return NULL;
208
+ g_assert_not_reached();
209
}
210
}
211
212
--
213
2.25.1
214
215
diff view generated by jsdifflib
[PULL 21/24] tcg/s390: Split out constraint sets to tcg-target-con-set.h
Deleted patch
1
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
2
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
3
---
4
tcg/s390/tcg-target-con-set.h | 29 ++++++++
5
tcg/s390/tcg-target.h | 1 +
6
tcg/s390/tcg-target.c.inc | 121 ++++++++++++++--------------------
7
3 files changed, 81 insertions(+), 70 deletions(-)
8
create mode 100644 tcg/s390/tcg-target-con-set.h
9
1
10
diff --git a/tcg/s390/tcg-target-con-set.h b/tcg/s390/tcg-target-con-set.h
11
new file mode 100644
12
index XXXXXXX..XXXXXXX
13
--- /dev/null
14
+++ b/tcg/s390/tcg-target-con-set.h
15
@@ -XXX,XX +XXX,XX @@
16
+/* SPDX-License-Identifier: MIT */
17
+/*
18
+ * Define S390 target-specific constraint sets.
19
+ * Copyright (c) 2021 Linaro
20
+ */
21
+
22
+/*
23
+ * C_On_Im(...) defines a constraint set with <n> outputs and <m> inputs.
24
+ * Each operand should be a sequence of constraint letters as defined by
25
+ * tcg-target-con-str.h; the constraint combination is inclusive or.
26
+ */
27
+C_O0_I1(r)
28
+C_O0_I2(L, L)
29
+C_O0_I2(r, r)
30
+C_O0_I2(r, ri)
31
+C_O1_I1(r, L)
32
+C_O1_I1(r, r)
33
+C_O1_I2(r, 0, ri)
34
+C_O1_I2(r, 0, rI)
35
+C_O1_I2(r, 0, rJ)
36
+C_O1_I2(r, r, ri)
37
+C_O1_I2(r, rZ, r)
38
+C_O1_I4(r, r, ri, r, 0)
39
+C_O1_I4(r, r, ri, rI, 0)
40
+C_O2_I2(b, a, 0, r)
41
+C_O2_I3(b, a, 0, 1, r)
42
+C_O2_I4(r, r, 0, 1, rA, r)
43
+C_O2_I4(r, r, 0, 1, ri, r)
44
+C_O2_I4(r, r, 0, 1, r, r)
45
diff --git a/tcg/s390/tcg-target.h b/tcg/s390/tcg-target.h
46
index XXXXXXX..XXXXXXX 100644
47
--- a/tcg/s390/tcg-target.h
48
+++ b/tcg/s390/tcg-target.h
49
@@ -XXX,XX +XXX,XX @@ static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_rx,
50
#define TCG_TARGET_NEED_LDST_LABELS
51
#endif
52
#define TCG_TARGET_NEED_POOL_LABELS
53
+#define TCG_TARGET_CON_SET_H
54
55
#endif
56
diff --git a/tcg/s390/tcg-target.c.inc b/tcg/s390/tcg-target.c.inc
57
index XXXXXXX..XXXXXXX 100644
58
--- a/tcg/s390/tcg-target.c.inc
59
+++ b/tcg/s390/tcg-target.c.inc
60
@@ -XXX,XX +XXX,XX @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
61
}
62
}
63
64
-static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
65
+static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
66
{
67
- static const TCGTargetOpDef r = { .args_ct_str = { "r" } };
68
- static const TCGTargetOpDef r_r = { .args_ct_str = { "r", "r" } };
69
- static const TCGTargetOpDef r_L = { .args_ct_str = { "r", "L" } };
70
- static const TCGTargetOpDef L_L = { .args_ct_str = { "L", "L" } };
71
- static const TCGTargetOpDef r_ri = { .args_ct_str = { "r", "ri" } };
72
- static const TCGTargetOpDef r_r_ri = { .args_ct_str = { "r", "r", "ri" } };
73
- static const TCGTargetOpDef r_0_ri = { .args_ct_str = { "r", "0", "ri" } };
74
- static const TCGTargetOpDef r_0_rI = { .args_ct_str = { "r", "0", "rI" } };
75
- static const TCGTargetOpDef r_0_rJ = { .args_ct_str = { "r", "0", "rJ" } };
76
- static const TCGTargetOpDef a2_r
77
- = { .args_ct_str = { "r", "r", "0", "1", "r", "r" } };
78
- static const TCGTargetOpDef a2_ri
79
- = { .args_ct_str = { "r", "r", "0", "1", "ri", "r" } };
80
- static const TCGTargetOpDef a2_rA
81
- = { .args_ct_str = { "r", "r", "0", "1", "rA", "r" } };
82
-
83
switch (op) {
84
case INDEX_op_goto_ptr:
85
- return &r;
86
+ return C_O0_I1(r);
87
88
case INDEX_op_ld8u_i32:
89
case INDEX_op_ld8u_i64:
90
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
91
case INDEX_op_ld32u_i64:
92
case INDEX_op_ld32s_i64:
93
case INDEX_op_ld_i64:
94
+ return C_O1_I1(r, r);
95
+
96
case INDEX_op_st8_i32:
97
case INDEX_op_st8_i64:
98
case INDEX_op_st16_i32:
99
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
100
case INDEX_op_st_i32:
101
case INDEX_op_st32_i64:
102
case INDEX_op_st_i64:
103
- return &r_r;
104
+ return C_O0_I2(r, r);
105
106
case INDEX_op_add_i32:
107
case INDEX_op_add_i64:
108
- return &r_r_ri;
109
+ case INDEX_op_shl_i64:
110
+ case INDEX_op_shr_i64:
111
+ case INDEX_op_sar_i64:
112
+ case INDEX_op_rotl_i32:
113
+ case INDEX_op_rotl_i64:
114
+ case INDEX_op_rotr_i32:
115
+ case INDEX_op_rotr_i64:
116
+ case INDEX_op_clz_i64:
117
+ case INDEX_op_setcond_i32:
118
+ case INDEX_op_setcond_i64:
119
+ return C_O1_I2(r, r, ri);
120
+
121
case INDEX_op_sub_i32:
122
case INDEX_op_sub_i64:
123
case INDEX_op_and_i32:
124
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
125
case INDEX_op_or_i64:
126
case INDEX_op_xor_i32:
127
case INDEX_op_xor_i64:
128
- return (s390_facilities & FACILITY_DISTINCT_OPS ? &r_r_ri : &r_0_ri);
129
+ return (s390_facilities & FACILITY_DISTINCT_OPS
130
+ ? C_O1_I2(r, r, ri)
131
+ : C_O1_I2(r, 0, ri));
132
133
case INDEX_op_mul_i32:
134
/* If we have the general-instruction-extensions, then we have
135
MULTIPLY SINGLE IMMEDIATE with a signed 32-bit, otherwise we
136
have only MULTIPLY HALFWORD IMMEDIATE, with a signed 16-bit. */
137
- return (s390_facilities & FACILITY_GEN_INST_EXT ? &r_0_ri : &r_0_rI);
138
+ return (s390_facilities & FACILITY_GEN_INST_EXT
139
+ ? C_O1_I2(r, 0, ri)
140
+ : C_O1_I2(r, 0, rI));
141
+
142
case INDEX_op_mul_i64:
143
- return (s390_facilities & FACILITY_GEN_INST_EXT ? &r_0_rJ : &r_0_rI);
144
+ return (s390_facilities & FACILITY_GEN_INST_EXT
145
+ ? C_O1_I2(r, 0, rJ)
146
+ : C_O1_I2(r, 0, rI));
147
148
case INDEX_op_shl_i32:
149
case INDEX_op_shr_i32:
150
case INDEX_op_sar_i32:
151
- return (s390_facilities & FACILITY_DISTINCT_OPS ? &r_r_ri : &r_0_ri);
152
-
153
- case INDEX_op_shl_i64:
154
- case INDEX_op_shr_i64:
155
- case INDEX_op_sar_i64:
156
- return &r_r_ri;
157
-
158
- case INDEX_op_rotl_i32:
159
- case INDEX_op_rotl_i64:
160
- case INDEX_op_rotr_i32:
161
- case INDEX_op_rotr_i64:
162
- return &r_r_ri;
163
+ return (s390_facilities & FACILITY_DISTINCT_OPS
164
+ ? C_O1_I2(r, r, ri)
165
+ : C_O1_I2(r, 0, ri));
166
167
case INDEX_op_brcond_i32:
168
case INDEX_op_brcond_i64:
169
- return &r_ri;
170
+ return C_O0_I2(r, ri);
171
172
case INDEX_op_bswap16_i32:
173
case INDEX_op_bswap16_i64:
174
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
175
case INDEX_op_extu_i32_i64:
176
case INDEX_op_extract_i32:
177
case INDEX_op_extract_i64:
178
- return &r_r;
179
-
180
- case INDEX_op_clz_i64:
181
- case INDEX_op_setcond_i32:
182
- case INDEX_op_setcond_i64:
183
- return &r_r_ri;
184
+ return C_O1_I1(r, r);
185
186
case INDEX_op_qemu_ld_i32:
187
case INDEX_op_qemu_ld_i64:
188
- return &r_L;
189
+ return C_O1_I1(r, L);
190
case INDEX_op_qemu_st_i64:
191
case INDEX_op_qemu_st_i32:
192
- return &L_L;
193
+ return C_O0_I2(L, L);
194
195
case INDEX_op_deposit_i32:
196
case INDEX_op_deposit_i64:
197
- {
198
- static const TCGTargetOpDef dep
199
- = { .args_ct_str = { "r", "rZ", "r" } };
200
- return &dep;
201
- }
202
+ return C_O1_I2(r, rZ, r);
203
+
204
case INDEX_op_movcond_i32:
205
case INDEX_op_movcond_i64:
206
- {
207
- static const TCGTargetOpDef movc
208
- = { .args_ct_str = { "r", "r", "ri", "r", "0" } };
209
- static const TCGTargetOpDef movc_l
210
- = { .args_ct_str = { "r", "r", "ri", "rI", "0" } };
211
- return (s390_facilities & FACILITY_LOAD_ON_COND2 ? &movc_l : &movc);
212
- }
213
+ return (s390_facilities & FACILITY_LOAD_ON_COND2
214
+ ? C_O1_I4(r, r, ri, rI, 0)
215
+ : C_O1_I4(r, r, ri, r, 0));
216
+
217
case INDEX_op_div2_i32:
218
case INDEX_op_div2_i64:
219
case INDEX_op_divu2_i32:
220
case INDEX_op_divu2_i64:
221
- {
222
- static const TCGTargetOpDef div2
223
- = { .args_ct_str = { "b", "a", "0", "1", "r" } };
224
- return &div2;
225
- }
226
+ return C_O2_I3(b, a, 0, 1, r);
227
+
228
case INDEX_op_mulu2_i64:
229
- {
230
- static const TCGTargetOpDef mul2
231
- = { .args_ct_str = { "b", "a", "0", "r" } };
232
- return &mul2;
233
- }
234
+ return C_O2_I2(b, a, 0, r);
235
236
case INDEX_op_add2_i32:
237
case INDEX_op_sub2_i32:
238
- return (s390_facilities & FACILITY_EXT_IMM ? &a2_ri : &a2_r);
239
+ return (s390_facilities & FACILITY_EXT_IMM
240
+ ? C_O2_I4(r, r, 0, 1, ri, r)
241
+ : C_O2_I4(r, r, 0, 1, r, r));
242
+
243
case INDEX_op_add2_i64:
244
case INDEX_op_sub2_i64:
245
- return (s390_facilities & FACILITY_EXT_IMM ? &a2_rA : &a2_r);
246
+ return (s390_facilities & FACILITY_EXT_IMM
247
+ ? C_O2_I4(r, r, 0, 1, rA, r)
248
+ : C_O2_I4(r, r, 0, 1, r, r));
249
250
default:
251
- break;
252
+ g_assert_not_reached();
253
}
254
- return NULL;
255
}
256
257
static void query_s390_facilities(void)
258
--
259
2.25.1
260
261
diff view generated by jsdifflib
[PULL 22/24] tcg/sparc: Split out constraint sets to tcg-target-con-set.h
Deleted patch
1
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
2
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
3
---
4
tcg/sparc/tcg-target-con-set.h | 32 +++++++++++++++
5
tcg/sparc/tcg-target.h | 1 +
6
tcg/sparc/tcg-target.c.inc | 75 +++++++++++-----------------------
7
3 files changed, 56 insertions(+), 52 deletions(-)
8
create mode 100644 tcg/sparc/tcg-target-con-set.h
9
1
10
diff --git a/tcg/sparc/tcg-target-con-set.h b/tcg/sparc/tcg-target-con-set.h
11
new file mode 100644
12
index XXXXXXX..XXXXXXX
13
--- /dev/null
14
+++ b/tcg/sparc/tcg-target-con-set.h
15
@@ -XXX,XX +XXX,XX @@
16
+/* SPDX-License-Identifier: MIT */
17
+/*
18
+ * Define Sparc target-specific constraint sets.
19
+ * Copyright (c) 2021 Linaro
20
+ */
21
+
22
+/*
23
+ * C_On_Im(...) defines a constraint set with <n> outputs and <m> inputs.
24
+ * Each operand should be a sequence of constraint letters as defined by
25
+ * tcg-target-con-str.h; the constraint combination is inclusive or.
26
+ */
27
+C_O0_I1(r)
28
+C_O0_I2(rZ, r)
29
+C_O0_I2(RZ, r)
30
+C_O0_I2(rZ, rJ)
31
+C_O0_I2(RZ, RJ)
32
+C_O0_I2(sZ, A)
33
+C_O0_I2(SZ, A)
34
+C_O1_I1(r, A)
35
+C_O1_I1(R, A)
36
+C_O1_I1(r, r)
37
+C_O1_I1(r, R)
38
+C_O1_I1(R, r)
39
+C_O1_I1(R, R)
40
+C_O1_I2(R, R, R)
41
+C_O1_I2(r, rZ, rJ)
42
+C_O1_I2(R, RZ, RJ)
43
+C_O1_I4(r, rZ, rJ, rI, 0)
44
+C_O1_I4(R, RZ, RJ, RI, 0)
45
+C_O2_I2(r, r, rZ, rJ)
46
+C_O2_I4(R, R, RZ, RZ, RJ, RI)
47
+C_O2_I4(r, r, rZ, rZ, rJ, rJ)
48
diff --git a/tcg/sparc/tcg-target.h b/tcg/sparc/tcg-target.h
49
index XXXXXXX..XXXXXXX 100644
50
--- a/tcg/sparc/tcg-target.h
51
+++ b/tcg/sparc/tcg-target.h
52
@@ -XXX,XX +XXX,XX @@ extern bool use_vis3_instructions;
53
void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t);
54
55
#define TCG_TARGET_NEED_POOL_LABELS
56
+#define TCG_TARGET_CON_SET_H
57
58
#endif
59
diff --git a/tcg/sparc/tcg-target.c.inc b/tcg/sparc/tcg-target.c.inc
60
index XXXXXXX..XXXXXXX 100644
61
--- a/tcg/sparc/tcg-target.c.inc
62
+++ b/tcg/sparc/tcg-target.c.inc
63
@@ -XXX,XX +XXX,XX @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
64
}
65
}
66
67
-static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
68
+static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
69
{
70
- static const TCGTargetOpDef r = { .args_ct_str = { "r" } };
71
- static const TCGTargetOpDef r_r = { .args_ct_str = { "r", "r" } };
72
- static const TCGTargetOpDef R_r = { .args_ct_str = { "R", "r" } };
73
- static const TCGTargetOpDef r_R = { .args_ct_str = { "r", "R" } };
74
- static const TCGTargetOpDef R_R = { .args_ct_str = { "R", "R" } };
75
- static const TCGTargetOpDef r_A = { .args_ct_str = { "r", "A" } };
76
- static const TCGTargetOpDef R_A = { .args_ct_str = { "R", "A" } };
77
- static const TCGTargetOpDef rZ_r = { .args_ct_str = { "rZ", "r" } };
78
- static const TCGTargetOpDef RZ_r = { .args_ct_str = { "RZ", "r" } };
79
- static const TCGTargetOpDef sZ_A = { .args_ct_str = { "sZ", "A" } };
80
- static const TCGTargetOpDef SZ_A = { .args_ct_str = { "SZ", "A" } };
81
- static const TCGTargetOpDef rZ_rJ = { .args_ct_str = { "rZ", "rJ" } };
82
- static const TCGTargetOpDef RZ_RJ = { .args_ct_str = { "RZ", "RJ" } };
83
- static const TCGTargetOpDef R_R_R = { .args_ct_str = { "R", "R", "R" } };
84
- static const TCGTargetOpDef r_rZ_rJ
85
- = { .args_ct_str = { "r", "rZ", "rJ" } };
86
- static const TCGTargetOpDef R_RZ_RJ
87
- = { .args_ct_str = { "R", "RZ", "RJ" } };
88
- static const TCGTargetOpDef r_r_rZ_rJ
89
- = { .args_ct_str = { "r", "r", "rZ", "rJ" } };
90
- static const TCGTargetOpDef movc_32
91
- = { .args_ct_str = { "r", "rZ", "rJ", "rI", "0" } };
92
- static const TCGTargetOpDef movc_64
93
- = { .args_ct_str = { "R", "RZ", "RJ", "RI", "0" } };
94
- static const TCGTargetOpDef add2_32
95
- = { .args_ct_str = { "r", "r", "rZ", "rZ", "rJ", "rJ" } };
96
- static const TCGTargetOpDef add2_64
97
- = { .args_ct_str = { "R", "R", "RZ", "RZ", "RJ", "RI" } };
98
-
99
switch (op) {
100
case INDEX_op_goto_ptr:
101
- return &r;
102
+ return C_O0_I1(r);
103
104
case INDEX_op_ld8u_i32:
105
case INDEX_op_ld8s_i32:
106
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
107
case INDEX_op_ld_i32:
108
case INDEX_op_neg_i32:
109
case INDEX_op_not_i32:
110
- return &r_r;
111
+ return C_O1_I1(r, r);
112
113
case INDEX_op_st8_i32:
114
case INDEX_op_st16_i32:
115
case INDEX_op_st_i32:
116
- return &rZ_r;
117
+ return C_O0_I2(rZ, r);
118
119
case INDEX_op_add_i32:
120
case INDEX_op_mul_i32:
121
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
122
case INDEX_op_shr_i32:
123
case INDEX_op_sar_i32:
124
case INDEX_op_setcond_i32:
125
- return &r_rZ_rJ;
126
+ return C_O1_I2(r, rZ, rJ);
127
128
case INDEX_op_brcond_i32:
129
- return &rZ_rJ;
130
+ return C_O0_I2(rZ, rJ);
131
case INDEX_op_movcond_i32:
132
- return &movc_32;
133
+ return C_O1_I4(r, rZ, rJ, rI, 0);
134
case INDEX_op_add2_i32:
135
case INDEX_op_sub2_i32:
136
- return &add2_32;
137
+ return C_O2_I4(r, r, rZ, rZ, rJ, rJ);
138
case INDEX_op_mulu2_i32:
139
case INDEX_op_muls2_i32:
140
- return &r_r_rZ_rJ;
141
+ return C_O2_I2(r, r, rZ, rJ);
142
143
case INDEX_op_ld8u_i64:
144
case INDEX_op_ld8s_i64:
145
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
146
case INDEX_op_ld_i64:
147
case INDEX_op_ext_i32_i64:
148
case INDEX_op_extu_i32_i64:
149
- return &R_r;
150
+ return C_O1_I1(R, r);
151
152
case INDEX_op_st8_i64:
153
case INDEX_op_st16_i64:
154
case INDEX_op_st32_i64:
155
case INDEX_op_st_i64:
156
- return &RZ_r;
157
+ return C_O0_I2(RZ, r);
158
159
case INDEX_op_add_i64:
160
case INDEX_op_mul_i64:
161
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
162
case INDEX_op_shr_i64:
163
case INDEX_op_sar_i64:
164
case INDEX_op_setcond_i64:
165
- return &R_RZ_RJ;
166
+ return C_O1_I2(R, RZ, RJ);
167
168
case INDEX_op_neg_i64:
169
case INDEX_op_not_i64:
170
case INDEX_op_ext32s_i64:
171
case INDEX_op_ext32u_i64:
172
- return &R_R;
173
+ return C_O1_I1(R, R);
174
175
case INDEX_op_extrl_i64_i32:
176
case INDEX_op_extrh_i64_i32:
177
- return &r_R;
178
+ return C_O1_I1(r, R);
179
180
case INDEX_op_brcond_i64:
181
- return &RZ_RJ;
182
+ return C_O0_I2(RZ, RJ);
183
case INDEX_op_movcond_i64:
184
- return &movc_64;
185
+ return C_O1_I4(R, RZ, RJ, RI, 0);
186
case INDEX_op_add2_i64:
187
case INDEX_op_sub2_i64:
188
- return &add2_64;
189
+ return C_O2_I4(R, R, RZ, RZ, RJ, RI);
190
case INDEX_op_muluh_i64:
191
- return &R_R_R;
192
+ return C_O1_I2(R, R, R);
193
194
case INDEX_op_qemu_ld_i32:
195
- return &r_A;
196
+ return C_O1_I1(r, A);
197
case INDEX_op_qemu_ld_i64:
198
- return &R_A;
199
+ return C_O1_I1(R, A);
200
case INDEX_op_qemu_st_i32:
201
- return &sZ_A;
202
+ return C_O0_I2(sZ, A);
203
case INDEX_op_qemu_st_i64:
204
- return &SZ_A;
205
+ return C_O0_I2(SZ, A);
206
207
default:
208
- return NULL;
209
+ g_assert_not_reached();
210
}
211
}
212
213
--
214
2.25.1
215
216
diff view generated by jsdifflib
[PULL 23/24] tcg/tci: Split out constraint sets to tcg-target-con-set.h
Deleted patch
1
This requires finishing the conversion to tcg_target_op_def.
2
1
3
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
---
6
tcg/tci/tcg-target-con-set.h | 25 ++++
7
tcg/tci/tcg-target.h | 2 +
8
tcg/tci/tcg-target.c.inc | 279 +++++++++++++++++------------------
9
3 files changed, 161 insertions(+), 145 deletions(-)
10
create mode 100644 tcg/tci/tcg-target-con-set.h
11
12
diff --git a/tcg/tci/tcg-target-con-set.h b/tcg/tci/tcg-target-con-set.h
13
new file mode 100644
14
index XXXXXXX..XXXXXXX
15
--- /dev/null
16
+++ b/tcg/tci/tcg-target-con-set.h
17
@@ -XXX,XX +XXX,XX @@
18
+/* SPDX-License-Identifier: MIT */
19
+/*
20
+ * TCI target-specific constraint sets.
21
+ * Copyright (c) 2021 Linaro
22
+ */
23
+
24
+/*
25
+ * C_On_Im(...) defines a constraint set with <n> outputs and <m> inputs.
26
+ * Each operand should be a sequence of constraint letters as defined by
27
+ * tcg-target-con-str.h; the constraint combination is inclusive or.
28
+ */
29
+C_O0_I2(r, r)
30
+C_O0_I2(r, ri)
31
+C_O0_I3(r, r, r)
32
+C_O0_I4(r, r, ri, ri)
33
+C_O0_I4(r, r, r, r)
34
+C_O1_I1(r, r)
35
+C_O1_I2(r, 0, r)
36
+C_O1_I2(r, ri, ri)
37
+C_O1_I2(r, r, r)
38
+C_O1_I2(r, r, ri)
39
+C_O1_I4(r, r, r, ri, ri)
40
+C_O2_I1(r, r, r)
41
+C_O2_I2(r, r, r, r)
42
+C_O2_I4(r, r, r, r, r, r)
43
diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h
44
index XXXXXXX..XXXXXXX 100644
45
--- a/tcg/tci/tcg-target.h
46
+++ b/tcg/tci/tcg-target.h
47
@@ -XXX,XX +XXX,XX @@ static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_rx,
48
/* no need to flush icache explicitly */
49
}
50
51
+#define TCG_TARGET_CON_SET_H
52
+
53
#endif /* TCG_TARGET_H */
54
diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
55
index XXXXXXX..XXXXXXX 100644
56
--- a/tcg/tci/tcg-target.c.inc
57
+++ b/tcg/tci/tcg-target.c.inc
58
@@ -XXX,XX +XXX,XX @@
59
/* Bitfield n...m (in 32 bit value). */
60
#define BITS(n, m) (((0xffffffffU << (31 - n)) >> (31 - n + m)) << m)
61
62
-/* Macros used in tcg_target_op_defs. */
63
-#define R "r"
64
-#define RI "ri"
65
-#if TCG_TARGET_REG_BITS == 32
66
-# define R64 "r", "r"
67
-#else
68
-# define R64 "r"
69
-#endif
70
-#if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
71
-# define L "r", "r"
72
-# define S "r", "r"
73
-#else
74
-# define L "r"
75
-# define S "r"
76
-#endif
77
-
78
-/* TODO: documentation. */
79
-static const TCGTargetOpDef tcg_target_op_defs[] = {
80
- { INDEX_op_exit_tb, { NULL } },
81
- { INDEX_op_goto_tb, { NULL } },
82
- { INDEX_op_br, { NULL } },
83
-
84
- { INDEX_op_ld8u_i32, { R, R } },
85
- { INDEX_op_ld8s_i32, { R, R } },
86
- { INDEX_op_ld16u_i32, { R, R } },
87
- { INDEX_op_ld16s_i32, { R, R } },
88
- { INDEX_op_ld_i32, { R, R } },
89
- { INDEX_op_st8_i32, { R, R } },
90
- { INDEX_op_st16_i32, { R, R } },
91
- { INDEX_op_st_i32, { R, R } },
92
-
93
- { INDEX_op_add_i32, { R, RI, RI } },
94
- { INDEX_op_sub_i32, { R, RI, RI } },
95
- { INDEX_op_mul_i32, { R, RI, RI } },
96
- { INDEX_op_div_i32, { R, R, R } },
97
- { INDEX_op_divu_i32, { R, R, R } },
98
- { INDEX_op_rem_i32, { R, R, R } },
99
- { INDEX_op_remu_i32, { R, R, R } },
100
- /* TODO: Does R, RI, RI result in faster code than R, R, RI?
101
- If both operands are constants, we can optimize. */
102
- { INDEX_op_and_i32, { R, RI, RI } },
103
- { INDEX_op_andc_i32, { R, RI, RI } },
104
- { INDEX_op_eqv_i32, { R, RI, RI } },
105
- { INDEX_op_nand_i32, { R, RI, RI } },
106
- { INDEX_op_nor_i32, { R, RI, RI } },
107
- { INDEX_op_or_i32, { R, RI, RI } },
108
- { INDEX_op_orc_i32, { R, RI, RI } },
109
- { INDEX_op_xor_i32, { R, RI, RI } },
110
- { INDEX_op_shl_i32, { R, RI, RI } },
111
- { INDEX_op_shr_i32, { R, RI, RI } },
112
- { INDEX_op_sar_i32, { R, RI, RI } },
113
- { INDEX_op_rotl_i32, { R, RI, RI } },
114
- { INDEX_op_rotr_i32, { R, RI, RI } },
115
- { INDEX_op_deposit_i32, { R, "0", R } },
116
-
117
- { INDEX_op_brcond_i32, { R, RI } },
118
-
119
- { INDEX_op_setcond_i32, { R, R, RI } },
120
- { INDEX_op_setcond_i64, { R, R, RI } },
121
-
122
- /* TODO: Support R, R, R, R, RI, RI? Will it be faster? */
123
- { INDEX_op_add2_i32, { R, R, R, R, R, R } },
124
- { INDEX_op_sub2_i32, { R, R, R, R, R, R } },
125
- { INDEX_op_brcond2_i32, { R, R, RI, RI } },
126
- { INDEX_op_mulu2_i32, { R, R, R, R } },
127
- { INDEX_op_setcond2_i32, { R, R, R, RI, RI } },
128
-
129
- { INDEX_op_not_i32, { R, R } },
130
- { INDEX_op_neg_i32, { R, R } },
131
-
132
- { INDEX_op_ld8u_i64, { R, R } },
133
- { INDEX_op_ld8s_i64, { R, R } },
134
- { INDEX_op_ld16u_i64, { R, R } },
135
- { INDEX_op_ld16s_i64, { R, R } },
136
- { INDEX_op_ld32u_i64, { R, R } },
137
- { INDEX_op_ld32s_i64, { R, R } },
138
- { INDEX_op_ld_i64, { R, R } },
139
-
140
- { INDEX_op_st8_i64, { R, R } },
141
- { INDEX_op_st16_i64, { R, R } },
142
- { INDEX_op_st32_i64, { R, R } },
143
- { INDEX_op_st_i64, { R, R } },
144
-
145
- { INDEX_op_add_i64, { R, RI, RI } },
146
- { INDEX_op_sub_i64, { R, RI, RI } },
147
- { INDEX_op_mul_i64, { R, RI, RI } },
148
- { INDEX_op_div_i64, { R, R, R } },
149
- { INDEX_op_divu_i64, { R, R, R } },
150
- { INDEX_op_rem_i64, { R, R, R } },
151
- { INDEX_op_remu_i64, { R, R, R } },
152
- { INDEX_op_and_i64, { R, RI, RI } },
153
- { INDEX_op_andc_i64, { R, RI, RI } },
154
- { INDEX_op_eqv_i64, { R, RI, RI } },
155
- { INDEX_op_nand_i64, { R, RI, RI } },
156
- { INDEX_op_nor_i64, { R, RI, RI } },
157
- { INDEX_op_or_i64, { R, RI, RI } },
158
- { INDEX_op_orc_i64, { R, RI, RI } },
159
- { INDEX_op_xor_i64, { R, RI, RI } },
160
- { INDEX_op_shl_i64, { R, RI, RI } },
161
- { INDEX_op_shr_i64, { R, RI, RI } },
162
- { INDEX_op_sar_i64, { R, RI, RI } },
163
- { INDEX_op_rotl_i64, { R, RI, RI } },
164
- { INDEX_op_rotr_i64, { R, RI, RI } },
165
- { INDEX_op_deposit_i64, { R, "0", R } },
166
- { INDEX_op_brcond_i64, { R, RI } },
167
-
168
- { INDEX_op_ext8s_i64, { R, R } },
169
- { INDEX_op_ext16s_i64, { R, R } },
170
- { INDEX_op_ext32s_i64, { R, R } },
171
- { INDEX_op_ext8u_i64, { R, R } },
172
- { INDEX_op_ext16u_i64, { R, R } },
173
- { INDEX_op_ext32u_i64, { R, R } },
174
- { INDEX_op_ext_i32_i64, { R, R } },
175
- { INDEX_op_extu_i32_i64, { R, R } },
176
- { INDEX_op_bswap16_i64, { R, R } },
177
- { INDEX_op_bswap32_i64, { R, R } },
178
- { INDEX_op_bswap64_i64, { R, R } },
179
- { INDEX_op_not_i64, { R, R } },
180
- { INDEX_op_neg_i64, { R, R } },
181
-
182
- { INDEX_op_qemu_ld_i32, { R, L } },
183
- { INDEX_op_qemu_ld_i64, { R64, L } },
184
-
185
- { INDEX_op_qemu_st_i32, { R, S } },
186
- { INDEX_op_qemu_st_i64, { R64, S } },
187
-
188
- { INDEX_op_ext8s_i32, { R, R } },
189
- { INDEX_op_ext16s_i32, { R, R } },
190
- { INDEX_op_ext8u_i32, { R, R } },
191
- { INDEX_op_ext16u_i32, { R, R } },
192
-
193
- { INDEX_op_bswap16_i32, { R, R } },
194
- { INDEX_op_bswap32_i32, { R, R } },
195
-
196
- { INDEX_op_mb, { } },
197
- { -1 },
198
-};
199
-
200
-static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
201
+static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
202
{
203
- int i, n = ARRAY_SIZE(tcg_target_op_defs);
204
+ switch (op) {
205
+ case INDEX_op_ld8u_i32:
206
+ case INDEX_op_ld8s_i32:
207
+ case INDEX_op_ld16u_i32:
208
+ case INDEX_op_ld16s_i32:
209
+ case INDEX_op_ld_i32:
210
+ case INDEX_op_ld8u_i64:
211
+ case INDEX_op_ld8s_i64:
212
+ case INDEX_op_ld16u_i64:
213
+ case INDEX_op_ld16s_i64:
214
+ case INDEX_op_ld32u_i64:
215
+ case INDEX_op_ld32s_i64:
216
+ case INDEX_op_ld_i64:
217
+ case INDEX_op_not_i32:
218
+ case INDEX_op_not_i64:
219
+ case INDEX_op_neg_i32:
220
+ case INDEX_op_neg_i64:
221
+ case INDEX_op_ext8s_i32:
222
+ case INDEX_op_ext8s_i64:
223
+ case INDEX_op_ext16s_i32:
224
+ case INDEX_op_ext16s_i64:
225
+ case INDEX_op_ext8u_i32:
226
+ case INDEX_op_ext8u_i64:
227
+ case INDEX_op_ext16u_i32:
228
+ case INDEX_op_ext16u_i64:
229
+ case INDEX_op_ext32s_i64:
230
+ case INDEX_op_ext32u_i64:
231
+ case INDEX_op_ext_i32_i64:
232
+ case INDEX_op_extu_i32_i64:
233
+ case INDEX_op_bswap16_i32:
234
+ case INDEX_op_bswap16_i64:
235
+ case INDEX_op_bswap32_i32:
236
+ case INDEX_op_bswap32_i64:
237
+ case INDEX_op_bswap64_i64:
238
+ return C_O1_I1(r, r);
239
240
- for (i = 0; i < n; ++i) {
241
- if (tcg_target_op_defs[i].op == op) {
242
- return &tcg_target_op_defs[i];
243
- }
244
+ case INDEX_op_st8_i32:
245
+ case INDEX_op_st16_i32:
246
+ case INDEX_op_st_i32:
247
+ case INDEX_op_st8_i64:
248
+ case INDEX_op_st16_i64:
249
+ case INDEX_op_st32_i64:
250
+ case INDEX_op_st_i64:
251
+ return C_O0_I2(r, r);
252
+
253
+ case INDEX_op_div_i32:
254
+ case INDEX_op_div_i64:
255
+ case INDEX_op_divu_i32:
256
+ case INDEX_op_divu_i64:
257
+ case INDEX_op_rem_i32:
258
+ case INDEX_op_rem_i64:
259
+ case INDEX_op_remu_i32:
260
+ case INDEX_op_remu_i64:
261
+ return C_O1_I2(r, r, r);
262
+
263
+ case INDEX_op_add_i32:
264
+ case INDEX_op_add_i64:
265
+ case INDEX_op_sub_i32:
266
+ case INDEX_op_sub_i64:
267
+ case INDEX_op_mul_i32:
268
+ case INDEX_op_mul_i64:
269
+ case INDEX_op_and_i32:
270
+ case INDEX_op_and_i64:
271
+ case INDEX_op_andc_i32:
272
+ case INDEX_op_andc_i64:
273
+ case INDEX_op_eqv_i32:
274
+ case INDEX_op_eqv_i64:
275
+ case INDEX_op_nand_i32:
276
+ case INDEX_op_nand_i64:
277
+ case INDEX_op_nor_i32:
278
+ case INDEX_op_nor_i64:
279
+ case INDEX_op_or_i32:
280
+ case INDEX_op_or_i64:
281
+ case INDEX_op_orc_i32:
282
+ case INDEX_op_orc_i64:
283
+ case INDEX_op_xor_i32:
284
+ case INDEX_op_xor_i64:
285
+ case INDEX_op_shl_i32:
286
+ case INDEX_op_shl_i64:
287
+ case INDEX_op_shr_i32:
288
+ case INDEX_op_shr_i64:
289
+ case INDEX_op_sar_i32:
290
+ case INDEX_op_sar_i64:
291
+ case INDEX_op_rotl_i32:
292
+ case INDEX_op_rotl_i64:
293
+ case INDEX_op_rotr_i32:
294
+ case INDEX_op_rotr_i64:
295
+ /* TODO: Does R, RI, RI result in faster code than R, R, RI? */
296
+ return C_O1_I2(r, ri, ri);
297
+
298
+ case INDEX_op_deposit_i32:
299
+ case INDEX_op_deposit_i64:
300
+ return C_O1_I2(r, 0, r);
301
+
302
+ case INDEX_op_brcond_i32:
303
+ case INDEX_op_brcond_i64:
304
+ return C_O0_I2(r, ri);
305
+
306
+ case INDEX_op_setcond_i32:
307
+ case INDEX_op_setcond_i64:
308
+ return C_O1_I2(r, r, ri);
309
+
310
+#if TCG_TARGET_REG_BITS == 32
311
+ /* TODO: Support R, R, R, R, RI, RI? Will it be faster? */
312
+ case INDEX_op_add2_i32:
313
+ case INDEX_op_sub2_i32:
314
+ return C_O2_I4(r, r, r, r, r, r);
315
+ case INDEX_op_brcond2_i32:
316
+ return C_O0_I4(r, r, ri, ri);
317
+ case INDEX_op_mulu2_i32:
318
+ return C_O2_I2(r, r, r, r);
319
+ case INDEX_op_setcond2_i32:
320
+ return C_O1_I4(r, r, r, ri, ri);
321
+#endif
322
+
323
+ case INDEX_op_qemu_ld_i32:
324
+ return (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS
325
+ ? C_O1_I1(r, r)
326
+ : C_O1_I2(r, r, r));
327
+ case INDEX_op_qemu_ld_i64:
328
+ return (TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, r)
329
+ : TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? C_O2_I1(r, r, r)
330
+ : C_O2_I2(r, r, r, r));
331
+ case INDEX_op_qemu_st_i32:
332
+ return (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS
333
+ ? C_O0_I2(r, r)
334
+ : C_O0_I3(r, r, r));
335
+ case INDEX_op_qemu_st_i64:
336
+ return (TCG_TARGET_REG_BITS == 64 ? C_O0_I2(r, r)
337
+ : TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? C_O0_I3(r, r, r)
338
+ : C_O0_I4(r, r, r, r));
339
+
340
+ default:
341
+ g_assert_not_reached();
342
}
343
- return NULL;
344
}
345
346
static const int tcg_target_reg_alloc_order[] = {
347
--
348
2.25.1
349
350
diff view generated by jsdifflib
[PULL 24/24] tcg: Remove TCG_TARGET_CON_SET_H
Deleted patch
1
All backends have now been converted to tcg-target-con-set.h,
2
so we can remove the fallback code.
3
1
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
---
8
tcg/aarch64/tcg-target.h | 1 -
9
tcg/arm/tcg-target.h | 1 -
10
tcg/i386/tcg-target.h | 1 -
11
tcg/mips/tcg-target.h | 1 -
12
tcg/ppc/tcg-target.h | 1 -
13
tcg/riscv/tcg-target.h | 1 -
14
tcg/s390/tcg-target.h | 1 -
15
tcg/sparc/tcg-target.h | 1 -
16
tcg/tci/tcg-target.h | 2 --
17
tcg/tcg.c | 12 ------------
18
10 files changed, 22 deletions(-)
19
20
diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h
21
index XXXXXXX..XXXXXXX 100644
22
--- a/tcg/aarch64/tcg-target.h
23
+++ b/tcg/aarch64/tcg-target.h
24
@@ -XXX,XX +XXX,XX @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t);
25
#define TCG_TARGET_NEED_LDST_LABELS
26
#endif
27
#define TCG_TARGET_NEED_POOL_LABELS
28
-#define TCG_TARGET_CON_SET_H
29
30
#endif /* AARCH64_TCG_TARGET_H */
31
diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
32
index XXXXXXX..XXXXXXX 100644
33
--- a/tcg/arm/tcg-target.h
34
+++ b/tcg/arm/tcg-target.h
35
@@ -XXX,XX +XXX,XX @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t);
36
#define TCG_TARGET_NEED_LDST_LABELS
37
#endif
38
#define TCG_TARGET_NEED_POOL_LABELS
39
-#define TCG_TARGET_CON_SET_H
40
41
#endif
42
diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h
43
index XXXXXXX..XXXXXXX 100644
44
--- a/tcg/i386/tcg-target.h
45
+++ b/tcg/i386/tcg-target.h
46
@@ -XXX,XX +XXX,XX @@ static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_rx,
47
#define TCG_TARGET_NEED_LDST_LABELS
48
#endif
49
#define TCG_TARGET_NEED_POOL_LABELS
50
-#define TCG_TARGET_CON_SET_H
51
52
#endif
53
diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h
54
index XXXXXXX..XXXXXXX 100644
55
--- a/tcg/mips/tcg-target.h
56
+++ b/tcg/mips/tcg-target.h
57
@@ -XXX,XX +XXX,XX @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t);
58
#ifdef CONFIG_SOFTMMU
59
#define TCG_TARGET_NEED_LDST_LABELS
60
#endif
61
-#define TCG_TARGET_CON_SET_H
62
63
#endif
64
diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h
65
index XXXXXXX..XXXXXXX 100644
66
--- a/tcg/ppc/tcg-target.h
67
+++ b/tcg/ppc/tcg-target.h
68
@@ -XXX,XX +XXX,XX @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t);
69
#define TCG_TARGET_NEED_LDST_LABELS
70
#endif
71
#define TCG_TARGET_NEED_POOL_LABELS
72
-#define TCG_TARGET_CON_SET_H
73
74
#endif
75
diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h
76
index XXXXXXX..XXXXXXX 100644
77
--- a/tcg/riscv/tcg-target.h
78
+++ b/tcg/riscv/tcg-target.h
79
@@ -XXX,XX +XXX,XX @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t);
80
#define TCG_TARGET_NEED_POOL_LABELS
81
82
#define TCG_TARGET_HAS_MEMORY_BSWAP 0
83
-#define TCG_TARGET_CON_SET_H
84
85
#endif
86
diff --git a/tcg/s390/tcg-target.h b/tcg/s390/tcg-target.h
87
index XXXXXXX..XXXXXXX 100644
88
--- a/tcg/s390/tcg-target.h
89
+++ b/tcg/s390/tcg-target.h
90
@@ -XXX,XX +XXX,XX @@ static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_rx,
91
#define TCG_TARGET_NEED_LDST_LABELS
92
#endif
93
#define TCG_TARGET_NEED_POOL_LABELS
94
-#define TCG_TARGET_CON_SET_H
95
96
#endif
97
diff --git a/tcg/sparc/tcg-target.h b/tcg/sparc/tcg-target.h
98
index XXXXXXX..XXXXXXX 100644
99
--- a/tcg/sparc/tcg-target.h
100
+++ b/tcg/sparc/tcg-target.h
101
@@ -XXX,XX +XXX,XX @@ extern bool use_vis3_instructions;
102
void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t);
103
104
#define TCG_TARGET_NEED_POOL_LABELS
105
-#define TCG_TARGET_CON_SET_H
106
107
#endif
108
diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h
109
index XXXXXXX..XXXXXXX 100644
110
--- a/tcg/tci/tcg-target.h
111
+++ b/tcg/tci/tcg-target.h
112
@@ -XXX,XX +XXX,XX @@ static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_rx,
113
/* no need to flush icache explicitly */
114
}
115
116
-#define TCG_TARGET_CON_SET_H
117
-
118
#endif /* TCG_TARGET_H */
119
diff --git a/tcg/tcg.c b/tcg/tcg.c
120
index XXXXXXX..XXXXXXX 100644
121
--- a/tcg/tcg.c
122
+++ b/tcg/tcg.c
123
@@ -XXX,XX +XXX,XX @@
124
/* Forward declarations for functions declared in tcg-target.c.inc and
125
used here. */
126
static void tcg_target_init(TCGContext *s);
127
-#ifndef TCG_TARGET_CON_SET_H
128
-static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode);
129
-#endif
130
static void tcg_target_qemu_prologue(TCGContext *s);
131
static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
132
intptr_t value, intptr_t addend);
133
@@ -XXX,XX +XXX,XX @@ static void set_jmp_reset_offset(TCGContext *s, int which)
134
s->tb_jmp_reset_offset[which] = tcg_current_code_size(s);
135
}
136
137
-#ifdef TCG_TARGET_CON_SET_H
138
#define C_PFX1(P, A) P##A
139
#define C_PFX2(P, A, B) P##A##_##B
140
#define C_PFX3(P, A, B, C) P##A##_##B##_##C
141
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef constraint_sets[] = {
142
#define C_O2_I3(O1, O2, I1, I2, I3) C_PFX5(c_o2_i3_, O1, O2, I1, I2, I3)
143
#define C_O2_I4(O1, O2, I1, I2, I3, I4) C_PFX6(c_o2_i4_, O1, O2, I1, I2, I3, I4)
144
145
-#endif /* TCG_TARGET_CON_SET_H */
146
-
147
#include "tcg-target.c.inc"
148
149
/* compare a pointer @ptr and a tb_tc @s */
150
@@ -XXX,XX +XXX,XX @@ static void process_op_defs(TCGContext *s)
151
continue;
152
}
153
154
-#ifdef TCG_TARGET_CON_SET_H
155
/*
156
* Macro magic should make it impossible, but double-check that
157
* the array index is in range. Since the signness of an enum
158
@@ -XXX,XX +XXX,XX @@ static void process_op_defs(TCGContext *s)
159
unsigned con_set = tcg_target_op_def(op);
160
tcg_debug_assert(con_set < ARRAY_SIZE(constraint_sets));
161
tdefs = &constraint_sets[con_set];
162
-#else
163
- tdefs = tcg_target_op_def(op);
164
- /* Missing TCGTargetOpDef entry. */
165
- tcg_debug_assert(tdefs != NULL);
166
-#endif
167
168
for (i = 0; i < nb_args; i++) {
169
const char *ct_str = tdefs->args_ct_str[i];
170
--
171
2.25.1
172
173
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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