[PULL 00/24] tcg patch queue
[PULL 00/24] tcg patch queue
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The following changes since commit 77f3804ab7ed94b471a14acb260e5aeacf26193f:
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With a couple of linux-user and target/sparc patches thrown in for good measure.
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3
Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into staging (2021-02-02 16:47:51 +0000)
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r~
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The following changes since commit 495de0fd82d8bb2d7035f82d9869cfeb48de2f9e:
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Merge tag 'pull-trivial-patches' of https://gitlab.com/mjt0k/qemu into staging (2025-02-14 08:19:05 -0500)
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9
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are available in the Git repository at:
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are available in the Git repository at:
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11
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https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20210202
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https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20250215
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13
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for you to fetch changes up to 0c823e596877a30fd6c17a1ae9f98218a53055ea:
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for you to fetch changes up to 2132751069134114814c7e1609e9cf644f077aad:
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tcg: Remove TCG_TARGET_CON_SET_H (2021-02-02 12:12:43 -1000)
16
target/sparc: fake UltraSPARC T1 PCR and PIC registers (2025-02-15 12:04:13 -0800)
12
17
13
----------------------------------------------------------------
18
----------------------------------------------------------------
14
TCG backend constraints cleanup
19
tcg: Remove last traces of TCG_TARGET_NEED_POOL_LABELS
20
tcg: Cleanups after disallowing 64-on-32
21
tcg: Introduce constraint for zero register
22
linux-user: Move TARGET_SA_RESTORER out of generic/signal.h
23
linux-user: Fix alignment when unmapping excess reservation
24
target/sparc: Fix register selection for all F*TOx and FxTO* instructions
25
target/sparc: Fix gdbstub incorrectly handling registers f32-f62
26
target/sparc: fake UltraSPARC T1 PCR and PIC registers
15
27
16
----------------------------------------------------------------
28
----------------------------------------------------------------
17
Richard Henderson (24):
29
Andreas Schwab (1):
18
tcg/tci: Drop L and S constraints
30
linux-user: Move TARGET_SA_RESTORER out of generic/signal.h
19
tcg/tci: Remove TCG_TARGET_HAS_* ifdefs
20
tcg/i386: Move constraint type check to tcg_target_const_match
21
tcg/i386: Tidy register constraint definitions
22
tcg/i386: Split out target constraints to tcg-target-con-str.h
23
tcg/arm: Split out target constraints to tcg-target-con-str.h
24
tcg/aarch64: Split out target constraints to tcg-target-con-str.h
25
tcg/ppc: Split out target constraints to tcg-target-con-str.h
26
tcg/tci: Split out target constraints to tcg-target-con-str.h
27
tcg/mips: Split out target constraints to tcg-target-con-str.h
28
tcg/riscv: Split out target constraints to tcg-target-con-str.h
29
tcg/s390: Split out target constraints to tcg-target-con-str.h
30
tcg/sparc: Split out target constraints to tcg-target-con-str.h
31
tcg: Remove TCG_TARGET_CON_STR_H
32
tcg/i386: Split out constraint sets to tcg-target-con-set.h
33
tcg/aarch64: Split out constraint sets to tcg-target-con-set.h
34
tcg/arm: Split out constraint sets to tcg-target-con-set.h
35
tcg/mips: Split out constraint sets to tcg-target-con-set.h
36
tcg/ppc: Split out constraint sets to tcg-target-con-set.h
37
tcg/riscv: Split out constraint sets to tcg-target-con-set.h
38
tcg/s390: Split out constraint sets to tcg-target-con-set.h
39
tcg/sparc: Split out constraint sets to tcg-target-con-set.h
40
tcg/tci: Split out constraint sets to tcg-target-con-set.h
41
tcg: Remove TCG_TARGET_CON_SET_H
42
31
43
tcg/aarch64/tcg-target-con-set.h | 36 ++++
32
Artyom Tarasenko (1):
44
tcg/aarch64/tcg-target-con-str.h | 24 +++
33
target/sparc: fake UltraSPARC T1 PCR and PIC registers
45
tcg/arm/tcg-target-con-set.h | 35 ++++
46
tcg/arm/tcg-target-con-str.h | 22 +++
47
tcg/i386/tcg-target-con-set.h | 55 ++++++
48
tcg/i386/tcg-target-con-str.h | 33 ++++
49
tcg/mips/tcg-target-con-set.h | 36 ++++
50
tcg/mips/tcg-target-con-str.h | 24 +++
51
tcg/ppc/tcg-target-con-set.h | 42 +++++
52
tcg/ppc/tcg-target-con-str.h | 30 ++++
53
tcg/riscv/tcg-target-con-set.h | 30 ++++
54
tcg/riscv/tcg-target-con-str.h | 21 +++
55
tcg/s390/tcg-target-con-set.h | 29 ++++
56
tcg/s390/tcg-target-con-str.h | 28 +++
57
tcg/sparc/tcg-target-con-set.h | 32 ++++
58
tcg/sparc/tcg-target-con-str.h | 23 +++
59
tcg/sparc/tcg-target.h | 4 -
60
tcg/tci/tcg-target-con-set.h | 25 +++
61
tcg/tci/tcg-target-con-str.h | 11 ++
62
tcg/tcg.c | 136 +++++++++++++--
63
tcg/aarch64/tcg-target.c.inc | 137 ++++-----------
64
tcg/arm/tcg-target.c.inc | 168 ++++++------------
65
tcg/i386/tcg-target.c.inc | 317 +++++++++++-----------------------
66
tcg/mips/tcg-target.c.inc | 173 ++++++-------------
67
tcg/ppc/tcg-target.c.inc | 209 ++++++++---------------
68
tcg/riscv/tcg-target.c.inc | 135 ++++-----------
69
tcg/s390/tcg-target.c.inc | 174 +++++++------------
70
tcg/sparc/tcg-target.c.inc | 156 ++++++-----------
71
tcg/tci/tcg-target.c.inc | 359 ++++++++++++++-------------------------
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29 files changed, 1244 insertions(+), 1260 deletions(-)
73
create mode 100644 tcg/aarch64/tcg-target-con-set.h
74
create mode 100644 tcg/aarch64/tcg-target-con-str.h
75
create mode 100644 tcg/arm/tcg-target-con-set.h
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create mode 100644 tcg/arm/tcg-target-con-str.h
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create mode 100644 tcg/i386/tcg-target-con-set.h
78
create mode 100644 tcg/i386/tcg-target-con-str.h
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create mode 100644 tcg/mips/tcg-target-con-set.h
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create mode 100644 tcg/mips/tcg-target-con-str.h
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create mode 100644 tcg/ppc/tcg-target-con-set.h
82
create mode 100644 tcg/ppc/tcg-target-con-str.h
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create mode 100644 tcg/riscv/tcg-target-con-set.h
84
create mode 100644 tcg/riscv/tcg-target-con-str.h
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create mode 100644 tcg/s390/tcg-target-con-set.h
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create mode 100644 tcg/s390/tcg-target-con-str.h
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create mode 100644 tcg/sparc/tcg-target-con-set.h
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create mode 100644 tcg/sparc/tcg-target-con-str.h
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create mode 100644 tcg/tci/tcg-target-con-set.h
90
create mode 100644 tcg/tci/tcg-target-con-str.h
91
34
35
Fabiano Rosas (1):
36
elfload: Fix alignment when unmapping excess reservation
37
38
Mikael Szreder (2):
39
target/sparc: Fix register selection for all F*TOx and FxTO* instructions
40
target/sparc: Fix gdbstub incorrectly handling registers f32-f62
41
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Richard Henderson (19):
43
tcg: Remove last traces of TCG_TARGET_NEED_POOL_LABELS
44
tcg: Remove TCG_OVERSIZED_GUEST
45
tcg: Drop support for two address registers in gen_ldst
46
tcg: Merge INDEX_op_qemu_*_{a32,a64}_*
47
tcg/arm: Drop addrhi from prepare_host_addr
48
tcg/i386: Drop addrhi from prepare_host_addr
49
tcg/mips: Drop addrhi from prepare_host_addr
50
tcg/ppc: Drop addrhi from prepare_host_addr
51
tcg: Replace addr{lo,hi}_reg with addr_reg in TCGLabelQemuLdst
52
plugins: Fix qemu_plugin_read_memory_vaddr parameters
53
accel/tcg: Fix tlb_set_page_with_attrs, tlb_set_page
54
include/exec: Change vaddr to uintptr_t
55
include/exec: Use uintptr_t in CPUTLBEntry
56
tcg: Introduce the 'z' constraint for a hardware zero register
57
tcg/aarch64: Use 'z' constraint
58
tcg/loongarch64: Use 'z' constraint
59
tcg/mips: Use 'z' constraint
60
tcg/riscv: Use 'z' constraint
61
tcg/sparc64: Use 'z' constraint
62
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include/exec/tlb-common.h | 10 +-
64
include/exec/vaddr.h | 16 ++--
65
include/qemu/atomic.h | 18 +---
66
include/tcg/oversized-guest.h | 23 -----
67
include/tcg/tcg-opc.h | 28 ++----
68
include/tcg/tcg.h | 3 +-
69
linux-user/aarch64/target_signal.h | 2 +
70
linux-user/arm/target_signal.h | 2 +
71
linux-user/generic/signal.h | 1 -
72
linux-user/i386/target_signal.h | 2 +
73
linux-user/m68k/target_signal.h | 1 +
74
linux-user/microblaze/target_signal.h | 2 +
75
linux-user/ppc/target_signal.h | 2 +
76
linux-user/s390x/target_signal.h | 2 +
77
linux-user/sh4/target_signal.h | 2 +
78
linux-user/x86_64/target_signal.h | 2 +
79
linux-user/xtensa/target_signal.h | 2 +
80
tcg/aarch64/tcg-target-con-set.h | 12 +--
81
tcg/aarch64/tcg-target.h | 2 +
82
tcg/loongarch64/tcg-target-con-set.h | 15 ++-
83
tcg/loongarch64/tcg-target-con-str.h | 1 -
84
tcg/loongarch64/tcg-target.h | 2 +
85
tcg/mips/tcg-target-con-set.h | 26 +++---
86
tcg/mips/tcg-target-con-str.h | 1 -
87
tcg/mips/tcg-target.h | 2 +
88
tcg/riscv/tcg-target-con-set.h | 10 +-
89
tcg/riscv/tcg-target-con-str.h | 1 -
90
tcg/riscv/tcg-target.h | 2 +
91
tcg/sparc64/tcg-target-con-set.h | 12 +--
92
tcg/sparc64/tcg-target-con-str.h | 1 -
93
tcg/sparc64/tcg-target.h | 3 +-
94
tcg/tci/tcg-target.h | 1 -
95
accel/tcg/cputlb.c | 32 ++-----
96
accel/tcg/tcg-all.c | 9 +-
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linux-user/elfload.c | 4 +-
98
plugins/api.c | 2 +-
99
target/arm/ptw.c | 34 -------
100
target/riscv/cpu_helper.c | 13 +--
101
target/sparc/gdbstub.c | 18 +++-
102
target/sparc/translate.c | 19 ++++
103
tcg/optimize.c | 21 ++---
104
tcg/tcg-op-ldst.c | 103 +++++----------------
105
tcg/tcg.c | 97 +++++++++----------
106
tcg/tci.c | 119 +++++-------------------
107
docs/devel/multi-thread-tcg.rst | 1 -
108
docs/devel/tcg-ops.rst | 4 +-
109
target/sparc/insns.decode | 19 ++--
110
tcg/aarch64/tcg-target.c.inc | 86 +++++++----------
111
tcg/arm/tcg-target.c.inc | 104 ++++++---------------
112
tcg/i386/tcg-target.c.inc | 125 +++++++------------------
113
tcg/loongarch64/tcg-target.c.inc | 72 ++++++---------
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tcg/mips/tcg-target.c.inc | 169 +++++++++++-----------------------
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tcg/ppc/tcg-target.c.inc | 164 ++++++++-------------------------
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tcg/riscv/tcg-target.c.inc | 56 +++++------
117
tcg/s390x/tcg-target.c.inc | 40 +++-----
118
tcg/sparc64/tcg-target.c.inc | 45 ++++-----
119
tcg/tci/tcg-target.c.inc | 60 +++---------
120
57 files changed, 536 insertions(+), 1089 deletions(-)
121
delete mode 100644 include/tcg/oversized-guest.h
diff view generated by jsdifflib
[PULL 24/24] tcg: Remove TCG_TARGET_CON_SET_H
[PULL 01/24] tcg: Remove last traces of TCG_TARGET_NEED_POOL_LABELS
1
All backends have now been converted to tcg-target-con-set.h,
1
These should have been removed with the rest. There are
2
so we can remove the fallback code.
2
a couple of hosts which can emit guest_base into the
3
constant pool: aarch64, mips64, ppc64, riscv64.
3
4
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Fixes: a417ef835058 ("tcg: Remove TCG_TARGET_NEED_LDST_LABELS and TCG_TARGET_NEED_POOL_LABELS")
5
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
---
7
---
8
tcg/aarch64/tcg-target.h | 1 -
8
tcg/tci/tcg-target.h | 1 -
9
tcg/arm/tcg-target.h | 1 -
9
tcg/tcg.c | 4 ----
10
tcg/i386/tcg-target.h | 1 -
10
2 files changed, 5 deletions(-)
11
tcg/mips/tcg-target.h | 1 -
12
tcg/ppc/tcg-target.h | 1 -
13
tcg/riscv/tcg-target.h | 1 -
14
tcg/s390/tcg-target.h | 1 -
15
tcg/sparc/tcg-target.h | 1 -
16
tcg/tci/tcg-target.h | 2 --
17
tcg/tcg.c | 12 ------------
18
10 files changed, 22 deletions(-)
19
11
20
diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h
21
index XXXXXXX..XXXXXXX 100644
22
--- a/tcg/aarch64/tcg-target.h
23
+++ b/tcg/aarch64/tcg-target.h
24
@@ -XXX,XX +XXX,XX @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t);
25
#define TCG_TARGET_NEED_LDST_LABELS
26
#endif
27
#define TCG_TARGET_NEED_POOL_LABELS
28
-#define TCG_TARGET_CON_SET_H
29
30
#endif /* AARCH64_TCG_TARGET_H */
31
diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
32
index XXXXXXX..XXXXXXX 100644
33
--- a/tcg/arm/tcg-target.h
34
+++ b/tcg/arm/tcg-target.h
35
@@ -XXX,XX +XXX,XX @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t);
36
#define TCG_TARGET_NEED_LDST_LABELS
37
#endif
38
#define TCG_TARGET_NEED_POOL_LABELS
39
-#define TCG_TARGET_CON_SET_H
40
41
#endif
42
diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h
43
index XXXXXXX..XXXXXXX 100644
44
--- a/tcg/i386/tcg-target.h
45
+++ b/tcg/i386/tcg-target.h
46
@@ -XXX,XX +XXX,XX @@ static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_rx,
47
#define TCG_TARGET_NEED_LDST_LABELS
48
#endif
49
#define TCG_TARGET_NEED_POOL_LABELS
50
-#define TCG_TARGET_CON_SET_H
51
52
#endif
53
diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h
54
index XXXXXXX..XXXXXXX 100644
55
--- a/tcg/mips/tcg-target.h
56
+++ b/tcg/mips/tcg-target.h
57
@@ -XXX,XX +XXX,XX @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t);
58
#ifdef CONFIG_SOFTMMU
59
#define TCG_TARGET_NEED_LDST_LABELS
60
#endif
61
-#define TCG_TARGET_CON_SET_H
62
63
#endif
64
diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h
65
index XXXXXXX..XXXXXXX 100644
66
--- a/tcg/ppc/tcg-target.h
67
+++ b/tcg/ppc/tcg-target.h
68
@@ -XXX,XX +XXX,XX @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t);
69
#define TCG_TARGET_NEED_LDST_LABELS
70
#endif
71
#define TCG_TARGET_NEED_POOL_LABELS
72
-#define TCG_TARGET_CON_SET_H
73
74
#endif
75
diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h
76
index XXXXXXX..XXXXXXX 100644
77
--- a/tcg/riscv/tcg-target.h
78
+++ b/tcg/riscv/tcg-target.h
79
@@ -XXX,XX +XXX,XX @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t);
80
#define TCG_TARGET_NEED_POOL_LABELS
81
82
#define TCG_TARGET_HAS_MEMORY_BSWAP 0
83
-#define TCG_TARGET_CON_SET_H
84
85
#endif
86
diff --git a/tcg/s390/tcg-target.h b/tcg/s390/tcg-target.h
87
index XXXXXXX..XXXXXXX 100644
88
--- a/tcg/s390/tcg-target.h
89
+++ b/tcg/s390/tcg-target.h
90
@@ -XXX,XX +XXX,XX @@ static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_rx,
91
#define TCG_TARGET_NEED_LDST_LABELS
92
#endif
93
#define TCG_TARGET_NEED_POOL_LABELS
94
-#define TCG_TARGET_CON_SET_H
95
96
#endif
97
diff --git a/tcg/sparc/tcg-target.h b/tcg/sparc/tcg-target.h
98
index XXXXXXX..XXXXXXX 100644
99
--- a/tcg/sparc/tcg-target.h
100
+++ b/tcg/sparc/tcg-target.h
101
@@ -XXX,XX +XXX,XX @@ extern bool use_vis3_instructions;
102
void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t);
103
104
#define TCG_TARGET_NEED_POOL_LABELS
105
-#define TCG_TARGET_CON_SET_H
106
107
#endif
108
diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h
12
diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h
109
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
110
--- a/tcg/tci/tcg-target.h
14
--- a/tcg/tci/tcg-target.h
111
+++ b/tcg/tci/tcg-target.h
15
+++ b/tcg/tci/tcg-target.h
112
@@ -XXX,XX +XXX,XX @@ static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_rx,
16
@@ -XXX,XX +XXX,XX @@ typedef enum {
113
/* no need to flush icache explicitly */
17
} TCGReg;
114
}
18
115
19
#define HAVE_TCG_QEMU_TB_EXEC
116
-#define TCG_TARGET_CON_SET_H
20
-#define TCG_TARGET_NEED_POOL_LABELS
117
-
21
118
#endif /* TCG_TARGET_H */
22
#endif /* TCG_TARGET_H */
119
diff --git a/tcg/tcg.c b/tcg/tcg.c
23
diff --git a/tcg/tcg.c b/tcg/tcg.c
120
index XXXXXXX..XXXXXXX 100644
24
index XXXXXXX..XXXXXXX 100644
121
--- a/tcg/tcg.c
25
--- a/tcg/tcg.c
122
+++ b/tcg/tcg.c
26
+++ b/tcg/tcg.c
123
@@ -XXX,XX +XXX,XX @@
27
@@ -XXX,XX +XXX,XX @@ void tcg_prologue_init(void)
124
/* Forward declarations for functions declared in tcg-target.c.inc and
28
tcg_qemu_tb_exec = (tcg_prologue_fn *)tcg_splitwx_to_rx(s->code_ptr);
125
used here. */
29
#endif
126
static void tcg_target_init(TCGContext *s);
30
127
-#ifndef TCG_TARGET_CON_SET_H
31
-#ifdef TCG_TARGET_NEED_POOL_LABELS
128
-static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode);
32
s->pool_labels = NULL;
129
-#endif
33
-#endif
130
static void tcg_target_qemu_prologue(TCGContext *s);
34
131
static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
35
qemu_thread_jit_write();
132
intptr_t value, intptr_t addend);
36
/* Generate the prologue. */
133
@@ -XXX,XX +XXX,XX @@ static void set_jmp_reset_offset(TCGContext *s, int which)
37
tcg_target_qemu_prologue(s);
134
s->tb_jmp_reset_offset[which] = tcg_current_code_size(s);
38
135
}
39
-#ifdef TCG_TARGET_NEED_POOL_LABELS
136
40
/* Allow the prologue to put e.g. guest_base into a pool entry. */
137
-#ifdef TCG_TARGET_CON_SET_H
41
{
138
#define C_PFX1(P, A) P##A
42
int result = tcg_out_pool_finalize(s);
139
#define C_PFX2(P, A, B) P##A##_##B
43
tcg_debug_assert(result == 0);
140
#define C_PFX3(P, A, B, C) P##A##_##B##_##C
44
}
141
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef constraint_sets[] = {
142
#define C_O2_I3(O1, O2, I1, I2, I3) C_PFX5(c_o2_i3_, O1, O2, I1, I2, I3)
143
#define C_O2_I4(O1, O2, I1, I2, I3, I4) C_PFX6(c_o2_i4_, O1, O2, I1, I2, I3, I4)
144
145
-#endif /* TCG_TARGET_CON_SET_H */
146
-
147
#include "tcg-target.c.inc"
148
149
/* compare a pointer @ptr and a tb_tc @s */
150
@@ -XXX,XX +XXX,XX @@ static void process_op_defs(TCGContext *s)
151
continue;
152
}
153
154
-#ifdef TCG_TARGET_CON_SET_H
155
/*
156
* Macro magic should make it impossible, but double-check that
157
* the array index is in range. Since the signness of an enum
158
@@ -XXX,XX +XXX,XX @@ static void process_op_defs(TCGContext *s)
159
unsigned con_set = tcg_target_op_def(op);
160
tcg_debug_assert(con_set < ARRAY_SIZE(constraint_sets));
161
tdefs = &constraint_sets[con_set];
162
-#else
163
- tdefs = tcg_target_op_def(op);
164
- /* Missing TCGTargetOpDef entry. */
165
- tcg_debug_assert(tdefs != NULL);
166
-#endif
45
-#endif
167
46
168
for (i = 0; i < nb_args; i++) {
47
prologue_size = tcg_current_code_size(s);
169
const char *ct_str = tdefs->args_ct_str[i];
48
perf_report_prologue(s->code_gen_ptr, prologue_size);
170
--
49
--
171
2.25.1
50
2.43.0
172
173
diff view generated by jsdifflib
[PULL 23/24] tcg/tci: Split out constraint sets to tcg-target-con-set.h
[PULL 02/24] tcg: Remove TCG_OVERSIZED_GUEST
1
This requires finishing the conversion to tcg_target_op_def.
1
This is now prohibited in configuration.
2
2
3
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
3
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
---
5
---
6
tcg/tci/tcg-target-con-set.h | 25 ++++
6
include/qemu/atomic.h | 18 +++--------------
7
tcg/tci/tcg-target.h | 2 +
7
include/tcg/oversized-guest.h | 23 ----------------------
8
tcg/tci/tcg-target.c.inc | 279 +++++++++++++++++------------------
8
accel/tcg/cputlb.c | 7 -------
9
3 files changed, 161 insertions(+), 145 deletions(-)
9
accel/tcg/tcg-all.c | 9 ++++-----
10
create mode 100644 tcg/tci/tcg-target-con-set.h
10
target/arm/ptw.c | 34 ---------------------------------
11
11
target/riscv/cpu_helper.c | 13 +------------
12
diff --git a/tcg/tci/tcg-target-con-set.h b/tcg/tci/tcg-target-con-set.h
12
docs/devel/multi-thread-tcg.rst | 1 -
13
new file mode 100644
13
7 files changed, 8 insertions(+), 97 deletions(-)
14
delete mode 100644 include/tcg/oversized-guest.h
15
16
diff --git a/include/qemu/atomic.h b/include/qemu/atomic.h
17
index XXXXXXX..XXXXXXX 100644
18
--- a/include/qemu/atomic.h
19
+++ b/include/qemu/atomic.h
20
@@ -XXX,XX +XXX,XX @@
21
*/
22
#define signal_barrier() __atomic_signal_fence(__ATOMIC_SEQ_CST)
23
24
-/* Sanity check that the size of an atomic operation isn't "overly large".
25
+/*
26
+ * Sanity check that the size of an atomic operation isn't "overly large".
27
* Despite the fact that e.g. i686 has 64-bit atomic operations, we do not
28
* want to use them because we ought not need them, and this lets us do a
29
* bit of sanity checking that other 32-bit hosts might build.
30
- *
31
- * That said, we have a problem on 64-bit ILP32 hosts in that in order to
32
- * sync with TCG_OVERSIZED_GUEST, this must match TCG_TARGET_REG_BITS.
33
- * We'd prefer not want to pull in everything else TCG related, so handle
34
- * those few cases by hand.
35
- *
36
- * Note that x32 is fully detected with __x86_64__ + _ILP32, and that for
37
- * Sparc we always force the use of sparcv9 in configure. MIPS n32 (ILP32) &
38
- * n64 (LP64) ABIs are both detected using __mips64.
39
*/
40
-#if defined(__x86_64__) || defined(__sparc__) || defined(__mips64)
41
-# define ATOMIC_REG_SIZE 8
42
-#else
43
-# define ATOMIC_REG_SIZE sizeof(void *)
44
-#endif
45
+#define ATOMIC_REG_SIZE sizeof(void *)
46
47
/* Weak atomic operations prevent the compiler moving other
48
* loads/stores past the atomic operation load/store. However there is
49
diff --git a/include/tcg/oversized-guest.h b/include/tcg/oversized-guest.h
50
deleted file mode 100644
14
index XXXXXXX..XXXXXXX
51
index XXXXXXX..XXXXXXX
15
--- /dev/null
52
--- a/include/tcg/oversized-guest.h
16
+++ b/tcg/tci/tcg-target-con-set.h
53
+++ /dev/null
17
@@ -XXX,XX +XXX,XX @@
54
@@ -XXX,XX +XXX,XX @@
18
+/* SPDX-License-Identifier: MIT */
55
-/* SPDX-License-Identifier: MIT */
19
+/*
56
-/*
20
+ * TCI target-specific constraint sets.
57
- * Define TCG_OVERSIZED_GUEST
21
+ * Copyright (c) 2021 Linaro
58
- * Copyright (c) 2008 Fabrice Bellard
22
+ */
59
- */
60
-
61
-#ifndef EXEC_TCG_OVERSIZED_GUEST_H
62
-#define EXEC_TCG_OVERSIZED_GUEST_H
63
-
64
-#include "tcg-target-reg-bits.h"
65
-#include "cpu-param.h"
66
-
67
-/*
68
- * Oversized TCG guests make things like MTTCG hard
69
- * as we can't use atomics for cputlb updates.
70
- */
71
-#if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
72
-#define TCG_OVERSIZED_GUEST 1
73
-#else
74
-#define TCG_OVERSIZED_GUEST 0
75
-#endif
76
-
77
-#endif
78
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
79
index XXXXXXX..XXXXXXX 100644
80
--- a/accel/tcg/cputlb.c
81
+++ b/accel/tcg/cputlb.c
82
@@ -XXX,XX +XXX,XX @@
83
#include "qemu/plugin-memory.h"
84
#endif
85
#include "tcg/tcg-ldst.h"
86
-#include "tcg/oversized-guest.h"
87
88
/* DEBUG defines, enable DEBUG_TLB_LOG to log to the CPU_LOG_MMU target */
89
/* #define DEBUG_TLB */
90
@@ -XXX,XX +XXX,XX @@ static inline uint64_t tlb_read_idx(const CPUTLBEntry *entry,
91
return qatomic_read(ptr);
92
#else
93
const uint64_t *ptr = &entry->addr_idx[access_type];
94
-# if TCG_OVERSIZED_GUEST
95
- return *ptr;
96
-# else
97
/* ofs might correspond to .addr_write, so use qatomic_read */
98
return qatomic_read(ptr);
99
-# endif
100
#endif
101
}
102
103
@@ -XXX,XX +XXX,XX @@ static void tlb_reset_dirty_range_locked(CPUTLBEntry *tlb_entry,
104
uint32_t *ptr_write = (uint32_t *)&tlb_entry->addr_write;
105
ptr_write += HOST_BIG_ENDIAN;
106
qatomic_set(ptr_write, *ptr_write | TLB_NOTDIRTY);
107
-#elif TCG_OVERSIZED_GUEST
108
- tlb_entry->addr_write |= TLB_NOTDIRTY;
109
#else
110
qatomic_set(&tlb_entry->addr_write,
111
tlb_entry->addr_write | TLB_NOTDIRTY);
112
diff --git a/accel/tcg/tcg-all.c b/accel/tcg/tcg-all.c
113
index XXXXXXX..XXXXXXX 100644
114
--- a/accel/tcg/tcg-all.c
115
+++ b/accel/tcg/tcg-all.c
116
@@ -XXX,XX +XXX,XX @@
117
#include "exec/replay-core.h"
118
#include "system/cpu-timers.h"
119
#include "tcg/startup.h"
120
-#include "tcg/oversized-guest.h"
121
#include "qapi/error.h"
122
#include "qemu/error-report.h"
123
#include "qemu/accel.h"
124
@@ -XXX,XX +XXX,XX @@
125
#include "hw/boards.h"
126
#endif
127
#include "internal-common.h"
128
+#include "cpu-param.h"
23
+
129
+
24
+/*
130
25
+ * C_On_Im(...) defines a constraint set with <n> outputs and <m> inputs.
131
struct TCGState {
26
+ * Each operand should be a sequence of constraint letters as defined by
132
AccelState parent_obj;
27
+ * tcg-target-con-str.h; the constraint combination is inclusive or.
133
@@ -XXX,XX +XXX,XX @@ DECLARE_INSTANCE_CHECKER(TCGState, TCG_STATE,
28
+ */
134
29
+C_O0_I2(r, r)
135
static bool default_mttcg_enabled(void)
30
+C_O0_I2(r, ri)
31
+C_O0_I3(r, r, r)
32
+C_O0_I4(r, r, ri, ri)
33
+C_O0_I4(r, r, r, r)
34
+C_O1_I1(r, r)
35
+C_O1_I2(r, 0, r)
36
+C_O1_I2(r, ri, ri)
37
+C_O1_I2(r, r, r)
38
+C_O1_I2(r, r, ri)
39
+C_O1_I4(r, r, r, ri, ri)
40
+C_O2_I1(r, r, r)
41
+C_O2_I2(r, r, r, r)
42
+C_O2_I4(r, r, r, r, r, r)
43
diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h
44
index XXXXXXX..XXXXXXX 100644
45
--- a/tcg/tci/tcg-target.h
46
+++ b/tcg/tci/tcg-target.h
47
@@ -XXX,XX +XXX,XX @@ static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_rx,
48
/* no need to flush icache explicitly */
49
}
50
51
+#define TCG_TARGET_CON_SET_H
52
+
53
#endif /* TCG_TARGET_H */
54
diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
55
index XXXXXXX..XXXXXXX 100644
56
--- a/tcg/tci/tcg-target.c.inc
57
+++ b/tcg/tci/tcg-target.c.inc
58
@@ -XXX,XX +XXX,XX @@
59
/* Bitfield n...m (in 32 bit value). */
60
#define BITS(n, m) (((0xffffffffU << (31 - n)) >> (31 - n + m)) << m)
61
62
-/* Macros used in tcg_target_op_defs. */
63
-#define R "r"
64
-#define RI "ri"
65
-#if TCG_TARGET_REG_BITS == 32
66
-# define R64 "r", "r"
67
-#else
68
-# define R64 "r"
69
-#endif
70
-#if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
71
-# define L "r", "r"
72
-# define S "r", "r"
73
-#else
74
-# define L "r"
75
-# define S "r"
76
-#endif
77
-
78
-/* TODO: documentation. */
79
-static const TCGTargetOpDef tcg_target_op_defs[] = {
80
- { INDEX_op_exit_tb, { NULL } },
81
- { INDEX_op_goto_tb, { NULL } },
82
- { INDEX_op_br, { NULL } },
83
-
84
- { INDEX_op_ld8u_i32, { R, R } },
85
- { INDEX_op_ld8s_i32, { R, R } },
86
- { INDEX_op_ld16u_i32, { R, R } },
87
- { INDEX_op_ld16s_i32, { R, R } },
88
- { INDEX_op_ld_i32, { R, R } },
89
- { INDEX_op_st8_i32, { R, R } },
90
- { INDEX_op_st16_i32, { R, R } },
91
- { INDEX_op_st_i32, { R, R } },
92
-
93
- { INDEX_op_add_i32, { R, RI, RI } },
94
- { INDEX_op_sub_i32, { R, RI, RI } },
95
- { INDEX_op_mul_i32, { R, RI, RI } },
96
- { INDEX_op_div_i32, { R, R, R } },
97
- { INDEX_op_divu_i32, { R, R, R } },
98
- { INDEX_op_rem_i32, { R, R, R } },
99
- { INDEX_op_remu_i32, { R, R, R } },
100
- /* TODO: Does R, RI, RI result in faster code than R, R, RI?
101
- If both operands are constants, we can optimize. */
102
- { INDEX_op_and_i32, { R, RI, RI } },
103
- { INDEX_op_andc_i32, { R, RI, RI } },
104
- { INDEX_op_eqv_i32, { R, RI, RI } },
105
- { INDEX_op_nand_i32, { R, RI, RI } },
106
- { INDEX_op_nor_i32, { R, RI, RI } },
107
- { INDEX_op_or_i32, { R, RI, RI } },
108
- { INDEX_op_orc_i32, { R, RI, RI } },
109
- { INDEX_op_xor_i32, { R, RI, RI } },
110
- { INDEX_op_shl_i32, { R, RI, RI } },
111
- { INDEX_op_shr_i32, { R, RI, RI } },
112
- { INDEX_op_sar_i32, { R, RI, RI } },
113
- { INDEX_op_rotl_i32, { R, RI, RI } },
114
- { INDEX_op_rotr_i32, { R, RI, RI } },
115
- { INDEX_op_deposit_i32, { R, "0", R } },
116
-
117
- { INDEX_op_brcond_i32, { R, RI } },
118
-
119
- { INDEX_op_setcond_i32, { R, R, RI } },
120
- { INDEX_op_setcond_i64, { R, R, RI } },
121
-
122
- /* TODO: Support R, R, R, R, RI, RI? Will it be faster? */
123
- { INDEX_op_add2_i32, { R, R, R, R, R, R } },
124
- { INDEX_op_sub2_i32, { R, R, R, R, R, R } },
125
- { INDEX_op_brcond2_i32, { R, R, RI, RI } },
126
- { INDEX_op_mulu2_i32, { R, R, R, R } },
127
- { INDEX_op_setcond2_i32, { R, R, R, RI, RI } },
128
-
129
- { INDEX_op_not_i32, { R, R } },
130
- { INDEX_op_neg_i32, { R, R } },
131
-
132
- { INDEX_op_ld8u_i64, { R, R } },
133
- { INDEX_op_ld8s_i64, { R, R } },
134
- { INDEX_op_ld16u_i64, { R, R } },
135
- { INDEX_op_ld16s_i64, { R, R } },
136
- { INDEX_op_ld32u_i64, { R, R } },
137
- { INDEX_op_ld32s_i64, { R, R } },
138
- { INDEX_op_ld_i64, { R, R } },
139
-
140
- { INDEX_op_st8_i64, { R, R } },
141
- { INDEX_op_st16_i64, { R, R } },
142
- { INDEX_op_st32_i64, { R, R } },
143
- { INDEX_op_st_i64, { R, R } },
144
-
145
- { INDEX_op_add_i64, { R, RI, RI } },
146
- { INDEX_op_sub_i64, { R, RI, RI } },
147
- { INDEX_op_mul_i64, { R, RI, RI } },
148
- { INDEX_op_div_i64, { R, R, R } },
149
- { INDEX_op_divu_i64, { R, R, R } },
150
- { INDEX_op_rem_i64, { R, R, R } },
151
- { INDEX_op_remu_i64, { R, R, R } },
152
- { INDEX_op_and_i64, { R, RI, RI } },
153
- { INDEX_op_andc_i64, { R, RI, RI } },
154
- { INDEX_op_eqv_i64, { R, RI, RI } },
155
- { INDEX_op_nand_i64, { R, RI, RI } },
156
- { INDEX_op_nor_i64, { R, RI, RI } },
157
- { INDEX_op_or_i64, { R, RI, RI } },
158
- { INDEX_op_orc_i64, { R, RI, RI } },
159
- { INDEX_op_xor_i64, { R, RI, RI } },
160
- { INDEX_op_shl_i64, { R, RI, RI } },
161
- { INDEX_op_shr_i64, { R, RI, RI } },
162
- { INDEX_op_sar_i64, { R, RI, RI } },
163
- { INDEX_op_rotl_i64, { R, RI, RI } },
164
- { INDEX_op_rotr_i64, { R, RI, RI } },
165
- { INDEX_op_deposit_i64, { R, "0", R } },
166
- { INDEX_op_brcond_i64, { R, RI } },
167
-
168
- { INDEX_op_ext8s_i64, { R, R } },
169
- { INDEX_op_ext16s_i64, { R, R } },
170
- { INDEX_op_ext32s_i64, { R, R } },
171
- { INDEX_op_ext8u_i64, { R, R } },
172
- { INDEX_op_ext16u_i64, { R, R } },
173
- { INDEX_op_ext32u_i64, { R, R } },
174
- { INDEX_op_ext_i32_i64, { R, R } },
175
- { INDEX_op_extu_i32_i64, { R, R } },
176
- { INDEX_op_bswap16_i64, { R, R } },
177
- { INDEX_op_bswap32_i64, { R, R } },
178
- { INDEX_op_bswap64_i64, { R, R } },
179
- { INDEX_op_not_i64, { R, R } },
180
- { INDEX_op_neg_i64, { R, R } },
181
-
182
- { INDEX_op_qemu_ld_i32, { R, L } },
183
- { INDEX_op_qemu_ld_i64, { R64, L } },
184
-
185
- { INDEX_op_qemu_st_i32, { R, S } },
186
- { INDEX_op_qemu_st_i64, { R64, S } },
187
-
188
- { INDEX_op_ext8s_i32, { R, R } },
189
- { INDEX_op_ext16s_i32, { R, R } },
190
- { INDEX_op_ext8u_i32, { R, R } },
191
- { INDEX_op_ext16u_i32, { R, R } },
192
-
193
- { INDEX_op_bswap16_i32, { R, R } },
194
- { INDEX_op_bswap32_i32, { R, R } },
195
-
196
- { INDEX_op_mb, { } },
197
- { -1 },
198
-};
199
-
200
-static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
201
+static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
202
{
136
{
203
- int i, n = ARRAY_SIZE(tcg_target_op_defs);
137
- if (icount_enabled() || TCG_OVERSIZED_GUEST) {
204
+ switch (op) {
138
+ if (icount_enabled()) {
205
+ case INDEX_op_ld8u_i32:
139
return false;
206
+ case INDEX_op_ld8s_i32:
140
}
207
+ case INDEX_op_ld16u_i32:
141
#ifdef TARGET_SUPPORTS_MTTCG
208
+ case INDEX_op_ld16s_i32:
142
@@ -XXX,XX +XXX,XX @@ static void tcg_set_thread(Object *obj, const char *value, Error **errp)
209
+ case INDEX_op_ld_i32:
143
TCGState *s = TCG_STATE(obj);
210
+ case INDEX_op_ld8u_i64:
144
211
+ case INDEX_op_ld8s_i64:
145
if (strcmp(value, "multi") == 0) {
212
+ case INDEX_op_ld16u_i64:
146
- if (TCG_OVERSIZED_GUEST) {
213
+ case INDEX_op_ld16s_i64:
147
- error_setg(errp, "No MTTCG when guest word size > hosts");
214
+ case INDEX_op_ld32u_i64:
148
- } else if (icount_enabled()) {
215
+ case INDEX_op_ld32s_i64:
149
+ if (icount_enabled()) {
216
+ case INDEX_op_ld_i64:
150
error_setg(errp, "No MTTCG when icount is enabled");
217
+ case INDEX_op_not_i32:
151
} else {
218
+ case INDEX_op_not_i64:
152
#ifndef TARGET_SUPPORTS_MTTCG
219
+ case INDEX_op_neg_i32:
153
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
220
+ case INDEX_op_neg_i64:
154
index XXXXXXX..XXXXXXX 100644
221
+ case INDEX_op_ext8s_i32:
155
--- a/target/arm/ptw.c
222
+ case INDEX_op_ext8s_i64:
156
+++ b/target/arm/ptw.c
223
+ case INDEX_op_ext16s_i32:
157
@@ -XXX,XX +XXX,XX @@
224
+ case INDEX_op_ext16s_i64:
158
#include "internals.h"
225
+ case INDEX_op_ext8u_i32:
159
#include "cpu-features.h"
226
+ case INDEX_op_ext8u_i64:
160
#include "idau.h"
227
+ case INDEX_op_ext16u_i32:
161
-#ifdef CONFIG_TCG
228
+ case INDEX_op_ext16u_i64:
162
-# include "tcg/oversized-guest.h"
229
+ case INDEX_op_ext32s_i64:
163
-#endif
230
+ case INDEX_op_ext32u_i64:
164
231
+ case INDEX_op_ext_i32_i64:
165
typedef struct S1Translate {
232
+ case INDEX_op_extu_i32_i64:
166
/*
233
+ case INDEX_op_bswap16_i32:
167
@@ -XXX,XX +XXX,XX @@ static uint64_t arm_casq_ptw(CPUARMState *env, uint64_t old_val,
234
+ case INDEX_op_bswap16_i64:
168
ptw->out_rw = true;
235
+ case INDEX_op_bswap32_i32:
169
}
236
+ case INDEX_op_bswap32_i64:
170
237
+ case INDEX_op_bswap64_i64:
171
-#ifdef CONFIG_ATOMIC64
238
+ return C_O1_I1(r, r);
172
if (ptw->out_be) {
239
173
old_val = cpu_to_be64(old_val);
240
- for (i = 0; i < n; ++i) {
174
new_val = cpu_to_be64(new_val);
241
- if (tcg_target_op_defs[i].op == op) {
175
@@ -XXX,XX +XXX,XX @@ static uint64_t arm_casq_ptw(CPUARMState *env, uint64_t old_val,
242
- return &tcg_target_op_defs[i];
176
cur_val = qatomic_cmpxchg__nocheck((uint64_t *)host, old_val, new_val);
177
cur_val = le64_to_cpu(cur_val);
178
}
179
-#else
180
- /*
181
- * We can't support the full 64-bit atomic cmpxchg on the host.
182
- * Because this is only used for FEAT_HAFDBS, which is only for AA64,
183
- * we know that TCG_OVERSIZED_GUEST is set, which means that we are
184
- * running in round-robin mode and could only race with dma i/o.
185
- */
186
-#if !TCG_OVERSIZED_GUEST
187
-# error "Unexpected configuration"
188
-#endif
189
- bool locked = bql_locked();
190
- if (!locked) {
191
- bql_lock();
192
- }
193
- if (ptw->out_be) {
194
- cur_val = ldq_be_p(host);
195
- if (cur_val == old_val) {
196
- stq_be_p(host, new_val);
243
- }
197
- }
244
+ case INDEX_op_st8_i32:
198
- } else {
245
+ case INDEX_op_st16_i32:
199
- cur_val = ldq_le_p(host);
246
+ case INDEX_op_st_i32:
200
- if (cur_val == old_val) {
247
+ case INDEX_op_st8_i64:
201
- stq_le_p(host, new_val);
248
+ case INDEX_op_st16_i64:
202
- }
249
+ case INDEX_op_st32_i64:
203
- }
250
+ case INDEX_op_st_i64:
204
- if (!locked) {
251
+ return C_O0_I2(r, r);
205
- bql_unlock();
252
+
206
- }
253
+ case INDEX_op_div_i32:
207
-#endif
254
+ case INDEX_op_div_i64:
208
-
255
+ case INDEX_op_divu_i32:
209
return cur_val;
256
+ case INDEX_op_divu_i64:
210
#else
257
+ case INDEX_op_rem_i32:
211
/* AArch32 does not have FEAT_HADFS; non-TCG guests only use debug-mode. */
258
+ case INDEX_op_rem_i64:
212
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
259
+ case INDEX_op_remu_i32:
213
index XXXXXXX..XXXXXXX 100644
260
+ case INDEX_op_remu_i64:
214
--- a/target/riscv/cpu_helper.c
261
+ return C_O1_I2(r, r, r);
215
+++ b/target/riscv/cpu_helper.c
262
+
216
@@ -XXX,XX +XXX,XX @@
263
+ case INDEX_op_add_i32:
217
#include "system/cpu-timers.h"
264
+ case INDEX_op_add_i64:
218
#include "cpu_bits.h"
265
+ case INDEX_op_sub_i32:
219
#include "debug.h"
266
+ case INDEX_op_sub_i64:
220
-#include "tcg/oversized-guest.h"
267
+ case INDEX_op_mul_i32:
221
#include "pmp.h"
268
+ case INDEX_op_mul_i64:
222
269
+ case INDEX_op_and_i32:
223
int riscv_env_mmu_index(CPURISCVState *env, bool ifetch)
270
+ case INDEX_op_and_i64:
224
@@ -XXX,XX +XXX,XX @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
271
+ case INDEX_op_andc_i32:
225
hwaddr pte_addr;
272
+ case INDEX_op_andc_i64:
226
int i;
273
+ case INDEX_op_eqv_i32:
227
274
+ case INDEX_op_eqv_i64:
228
-#if !TCG_OVERSIZED_GUEST
275
+ case INDEX_op_nand_i32:
229
-restart:
276
+ case INDEX_op_nand_i64:
230
-#endif
277
+ case INDEX_op_nor_i32:
231
+ restart:
278
+ case INDEX_op_nor_i64:
232
for (i = 0; i < levels; i++, ptshift -= ptidxbits) {
279
+ case INDEX_op_or_i32:
233
target_ulong idx;
280
+ case INDEX_op_or_i64:
234
if (i == 0) {
281
+ case INDEX_op_orc_i32:
235
@@ -XXX,XX +XXX,XX @@ restart:
282
+ case INDEX_op_orc_i64:
236
false, MEMTXATTRS_UNSPECIFIED);
283
+ case INDEX_op_xor_i32:
237
if (memory_region_is_ram(mr)) {
284
+ case INDEX_op_xor_i64:
238
target_ulong *pte_pa = qemu_map_ram_ptr(mr->ram_block, addr1);
285
+ case INDEX_op_shl_i32:
239
-#if TCG_OVERSIZED_GUEST
286
+ case INDEX_op_shl_i64:
240
- /*
287
+ case INDEX_op_shr_i32:
241
- * MTTCG is not enabled on oversized TCG guests so
288
+ case INDEX_op_shr_i64:
242
- * page table updates do not need to be atomic
289
+ case INDEX_op_sar_i32:
243
- */
290
+ case INDEX_op_sar_i64:
244
- *pte_pa = pte = updated_pte;
291
+ case INDEX_op_rotl_i32:
245
-#else
292
+ case INDEX_op_rotl_i64:
246
target_ulong old_pte;
293
+ case INDEX_op_rotr_i32:
247
if (riscv_cpu_sxl(env) == MXL_RV32) {
294
+ case INDEX_op_rotr_i64:
248
old_pte = qatomic_cmpxchg((uint32_t *)pte_pa, pte, updated_pte);
295
+ /* TODO: Does R, RI, RI result in faster code than R, R, RI? */
249
@@ -XXX,XX +XXX,XX @@ restart:
296
+ return C_O1_I2(r, ri, ri);
250
goto restart;
297
+
251
}
298
+ case INDEX_op_deposit_i32:
252
pte = updated_pte;
299
+ case INDEX_op_deposit_i64:
253
-#endif
300
+ return C_O1_I2(r, 0, r);
254
} else {
301
+
255
/*
302
+ case INDEX_op_brcond_i32:
256
* Misconfigured PTE in ROM (AD bits are not preset) or
303
+ case INDEX_op_brcond_i64:
257
diff --git a/docs/devel/multi-thread-tcg.rst b/docs/devel/multi-thread-tcg.rst
304
+ return C_O0_I2(r, ri);
258
index XXXXXXX..XXXXXXX 100644
305
+
259
--- a/docs/devel/multi-thread-tcg.rst
306
+ case INDEX_op_setcond_i32:
260
+++ b/docs/devel/multi-thread-tcg.rst
307
+ case INDEX_op_setcond_i64:
261
@@ -XXX,XX +XXX,XX @@ if:
308
+ return C_O1_I2(r, r, ri);
262
309
+
263
* forced by --accel tcg,thread=single
310
+#if TCG_TARGET_REG_BITS == 32
264
* enabling --icount mode
311
+ /* TODO: Support R, R, R, R, RI, RI? Will it be faster? */
265
-* 64 bit guests on 32 bit hosts (TCG_OVERSIZED_GUEST)
312
+ case INDEX_op_add2_i32:
266
313
+ case INDEX_op_sub2_i32:
267
In the general case of running translated code there should be no
314
+ return C_O2_I4(r, r, r, r, r, r);
268
inter-vCPU dependencies and all vCPUs should be able to run at full
315
+ case INDEX_op_brcond2_i32:
316
+ return C_O0_I4(r, r, ri, ri);
317
+ case INDEX_op_mulu2_i32:
318
+ return C_O2_I2(r, r, r, r);
319
+ case INDEX_op_setcond2_i32:
320
+ return C_O1_I4(r, r, r, ri, ri);
321
+#endif
322
+
323
+ case INDEX_op_qemu_ld_i32:
324
+ return (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS
325
+ ? C_O1_I1(r, r)
326
+ : C_O1_I2(r, r, r));
327
+ case INDEX_op_qemu_ld_i64:
328
+ return (TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, r)
329
+ : TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? C_O2_I1(r, r, r)
330
+ : C_O2_I2(r, r, r, r));
331
+ case INDEX_op_qemu_st_i32:
332
+ return (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS
333
+ ? C_O0_I2(r, r)
334
+ : C_O0_I3(r, r, r));
335
+ case INDEX_op_qemu_st_i64:
336
+ return (TCG_TARGET_REG_BITS == 64 ? C_O0_I2(r, r)
337
+ : TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? C_O0_I3(r, r, r)
338
+ : C_O0_I4(r, r, r, r));
339
+
340
+ default:
341
+ g_assert_not_reached();
342
}
343
- return NULL;
344
}
345
346
static const int tcg_target_reg_alloc_order[] = {
347
--
269
--
348
2.25.1
270
2.43.0
349
271
350
272
diff view generated by jsdifflib
[PULL 22/24] tcg/sparc: Split out constraint sets to tcg-target-con-set.h
[PULL 03/24] tcg: Drop support for two address registers in gen_ldst
1
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
1
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
3
---
3
---
4
tcg/sparc/tcg-target-con-set.h | 32 +++++++++++++++
4
tcg/tcg-op-ldst.c | 21 +++------------------
5
tcg/sparc/tcg-target.h | 1 +
5
tcg/tcg.c | 4 +---
6
tcg/sparc/tcg-target.c.inc | 75 +++++++++++-----------------------
6
2 files changed, 4 insertions(+), 21 deletions(-)
7
3 files changed, 56 insertions(+), 52 deletions(-)
8
create mode 100644 tcg/sparc/tcg-target-con-set.h
9
7
10
diff --git a/tcg/sparc/tcg-target-con-set.h b/tcg/sparc/tcg-target-con-set.h
8
diff --git a/tcg/tcg-op-ldst.c b/tcg/tcg-op-ldst.c
11
new file mode 100644
12
index XXXXXXX..XXXXXXX
13
--- /dev/null
14
+++ b/tcg/sparc/tcg-target-con-set.h
15
@@ -XXX,XX +XXX,XX @@
16
+/* SPDX-License-Identifier: MIT */
17
+/*
18
+ * Define Sparc target-specific constraint sets.
19
+ * Copyright (c) 2021 Linaro
20
+ */
21
+
22
+/*
23
+ * C_On_Im(...) defines a constraint set with <n> outputs and <m> inputs.
24
+ * Each operand should be a sequence of constraint letters as defined by
25
+ * tcg-target-con-str.h; the constraint combination is inclusive or.
26
+ */
27
+C_O0_I1(r)
28
+C_O0_I2(rZ, r)
29
+C_O0_I2(RZ, r)
30
+C_O0_I2(rZ, rJ)
31
+C_O0_I2(RZ, RJ)
32
+C_O0_I2(sZ, A)
33
+C_O0_I2(SZ, A)
34
+C_O1_I1(r, A)
35
+C_O1_I1(R, A)
36
+C_O1_I1(r, r)
37
+C_O1_I1(r, R)
38
+C_O1_I1(R, r)
39
+C_O1_I1(R, R)
40
+C_O1_I2(R, R, R)
41
+C_O1_I2(r, rZ, rJ)
42
+C_O1_I2(R, RZ, RJ)
43
+C_O1_I4(r, rZ, rJ, rI, 0)
44
+C_O1_I4(R, RZ, RJ, RI, 0)
45
+C_O2_I2(r, r, rZ, rJ)
46
+C_O2_I4(R, R, RZ, RZ, RJ, RI)
47
+C_O2_I4(r, r, rZ, rZ, rJ, rJ)
48
diff --git a/tcg/sparc/tcg-target.h b/tcg/sparc/tcg-target.h
49
index XXXXXXX..XXXXXXX 100644
9
index XXXXXXX..XXXXXXX 100644
50
--- a/tcg/sparc/tcg-target.h
10
--- a/tcg/tcg-op-ldst.c
51
+++ b/tcg/sparc/tcg-target.h
11
+++ b/tcg/tcg-op-ldst.c
52
@@ -XXX,XX +XXX,XX @@ extern bool use_vis3_instructions;
12
@@ -XXX,XX +XXX,XX @@ static MemOp tcg_canonicalize_memop(MemOp op, bool is64, bool st)
53
void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t);
13
static void gen_ldst(TCGOpcode opc, TCGType type, TCGTemp *vl, TCGTemp *vh,
54
14
TCGTemp *addr, MemOpIdx oi)
55
#define TCG_TARGET_NEED_POOL_LABELS
15
{
56
+#define TCG_TARGET_CON_SET_H
16
- if (TCG_TARGET_REG_BITS == 64 || tcg_ctx->addr_type == TCG_TYPE_I32) {
57
17
- if (vh) {
58
#endif
18
- tcg_gen_op4(opc, type, temp_arg(vl), temp_arg(vh),
59
diff --git a/tcg/sparc/tcg-target.c.inc b/tcg/sparc/tcg-target.c.inc
19
- temp_arg(addr), oi);
60
index XXXXXXX..XXXXXXX 100644
20
- } else {
61
--- a/tcg/sparc/tcg-target.c.inc
21
- tcg_gen_op3(opc, type, temp_arg(vl), temp_arg(addr), oi);
62
+++ b/tcg/sparc/tcg-target.c.inc
22
- }
63
@@ -XXX,XX +XXX,XX @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
23
+ if (vh) {
24
+ tcg_gen_op4(opc, type, temp_arg(vl), temp_arg(vh), temp_arg(addr), oi);
25
} else {
26
- /* See TCGV_LOW/HIGH. */
27
- TCGTemp *al = addr + HOST_BIG_ENDIAN;
28
- TCGTemp *ah = addr + !HOST_BIG_ENDIAN;
29
-
30
- if (vh) {
31
- tcg_gen_op5(opc, type, temp_arg(vl), temp_arg(vh),
32
- temp_arg(al), temp_arg(ah), oi);
33
- } else {
34
- tcg_gen_op4(opc, type, temp_arg(vl),
35
- temp_arg(al), temp_arg(ah), oi);
36
- }
37
+ tcg_gen_op3(opc, type, temp_arg(vl), temp_arg(addr), oi);
64
}
38
}
65
}
39
}
66
40
67
-static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
41
diff --git a/tcg/tcg.c b/tcg/tcg.c
68
+static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
42
index XXXXXXX..XXXXXXX 100644
69
{
43
--- a/tcg/tcg.c
70
- static const TCGTargetOpDef r = { .args_ct_str = { "r" } };
44
+++ b/tcg/tcg.c
71
- static const TCGTargetOpDef r_r = { .args_ct_str = { "r", "r" } };
45
@@ -XXX,XX +XXX,XX @@ void tcg_func_start(TCGContext *s)
72
- static const TCGTargetOpDef R_r = { .args_ct_str = { "R", "r" } };
46
s->emit_before_op = NULL;
73
- static const TCGTargetOpDef r_R = { .args_ct_str = { "r", "R" } };
47
QSIMPLEQ_INIT(&s->labels);
74
- static const TCGTargetOpDef R_R = { .args_ct_str = { "R", "R" } };
48
75
- static const TCGTargetOpDef r_A = { .args_ct_str = { "r", "A" } };
49
- tcg_debug_assert(s->addr_type == TCG_TYPE_I32 ||
76
- static const TCGTargetOpDef R_A = { .args_ct_str = { "R", "A" } };
50
- s->addr_type == TCG_TYPE_I64);
77
- static const TCGTargetOpDef rZ_r = { .args_ct_str = { "rZ", "r" } };
78
- static const TCGTargetOpDef RZ_r = { .args_ct_str = { "RZ", "r" } };
79
- static const TCGTargetOpDef sZ_A = { .args_ct_str = { "sZ", "A" } };
80
- static const TCGTargetOpDef SZ_A = { .args_ct_str = { "SZ", "A" } };
81
- static const TCGTargetOpDef rZ_rJ = { .args_ct_str = { "rZ", "rJ" } };
82
- static const TCGTargetOpDef RZ_RJ = { .args_ct_str = { "RZ", "RJ" } };
83
- static const TCGTargetOpDef R_R_R = { .args_ct_str = { "R", "R", "R" } };
84
- static const TCGTargetOpDef r_rZ_rJ
85
- = { .args_ct_str = { "r", "rZ", "rJ" } };
86
- static const TCGTargetOpDef R_RZ_RJ
87
- = { .args_ct_str = { "R", "RZ", "RJ" } };
88
- static const TCGTargetOpDef r_r_rZ_rJ
89
- = { .args_ct_str = { "r", "r", "rZ", "rJ" } };
90
- static const TCGTargetOpDef movc_32
91
- = { .args_ct_str = { "r", "rZ", "rJ", "rI", "0" } };
92
- static const TCGTargetOpDef movc_64
93
- = { .args_ct_str = { "R", "RZ", "RJ", "RI", "0" } };
94
- static const TCGTargetOpDef add2_32
95
- = { .args_ct_str = { "r", "r", "rZ", "rZ", "rJ", "rJ" } };
96
- static const TCGTargetOpDef add2_64
97
- = { .args_ct_str = { "R", "R", "RZ", "RZ", "RJ", "RI" } };
98
-
51
-
99
switch (op) {
52
+ tcg_debug_assert(s->addr_type <= TCG_TYPE_REG);
100
case INDEX_op_goto_ptr:
53
tcg_debug_assert(s->insn_start_words > 0);
101
- return &r;
102
+ return C_O0_I1(r);
103
104
case INDEX_op_ld8u_i32:
105
case INDEX_op_ld8s_i32:
106
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
107
case INDEX_op_ld_i32:
108
case INDEX_op_neg_i32:
109
case INDEX_op_not_i32:
110
- return &r_r;
111
+ return C_O1_I1(r, r);
112
113
case INDEX_op_st8_i32:
114
case INDEX_op_st16_i32:
115
case INDEX_op_st_i32:
116
- return &rZ_r;
117
+ return C_O0_I2(rZ, r);
118
119
case INDEX_op_add_i32:
120
case INDEX_op_mul_i32:
121
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
122
case INDEX_op_shr_i32:
123
case INDEX_op_sar_i32:
124
case INDEX_op_setcond_i32:
125
- return &r_rZ_rJ;
126
+ return C_O1_I2(r, rZ, rJ);
127
128
case INDEX_op_brcond_i32:
129
- return &rZ_rJ;
130
+ return C_O0_I2(rZ, rJ);
131
case INDEX_op_movcond_i32:
132
- return &movc_32;
133
+ return C_O1_I4(r, rZ, rJ, rI, 0);
134
case INDEX_op_add2_i32:
135
case INDEX_op_sub2_i32:
136
- return &add2_32;
137
+ return C_O2_I4(r, r, rZ, rZ, rJ, rJ);
138
case INDEX_op_mulu2_i32:
139
case INDEX_op_muls2_i32:
140
- return &r_r_rZ_rJ;
141
+ return C_O2_I2(r, r, rZ, rJ);
142
143
case INDEX_op_ld8u_i64:
144
case INDEX_op_ld8s_i64:
145
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
146
case INDEX_op_ld_i64:
147
case INDEX_op_ext_i32_i64:
148
case INDEX_op_extu_i32_i64:
149
- return &R_r;
150
+ return C_O1_I1(R, r);
151
152
case INDEX_op_st8_i64:
153
case INDEX_op_st16_i64:
154
case INDEX_op_st32_i64:
155
case INDEX_op_st_i64:
156
- return &RZ_r;
157
+ return C_O0_I2(RZ, r);
158
159
case INDEX_op_add_i64:
160
case INDEX_op_mul_i64:
161
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
162
case INDEX_op_shr_i64:
163
case INDEX_op_sar_i64:
164
case INDEX_op_setcond_i64:
165
- return &R_RZ_RJ;
166
+ return C_O1_I2(R, RZ, RJ);
167
168
case INDEX_op_neg_i64:
169
case INDEX_op_not_i64:
170
case INDEX_op_ext32s_i64:
171
case INDEX_op_ext32u_i64:
172
- return &R_R;
173
+ return C_O1_I1(R, R);
174
175
case INDEX_op_extrl_i64_i32:
176
case INDEX_op_extrh_i64_i32:
177
- return &r_R;
178
+ return C_O1_I1(r, R);
179
180
case INDEX_op_brcond_i64:
181
- return &RZ_RJ;
182
+ return C_O0_I2(RZ, RJ);
183
case INDEX_op_movcond_i64:
184
- return &movc_64;
185
+ return C_O1_I4(R, RZ, RJ, RI, 0);
186
case INDEX_op_add2_i64:
187
case INDEX_op_sub2_i64:
188
- return &add2_64;
189
+ return C_O2_I4(R, R, RZ, RZ, RJ, RI);
190
case INDEX_op_muluh_i64:
191
- return &R_R_R;
192
+ return C_O1_I2(R, R, R);
193
194
case INDEX_op_qemu_ld_i32:
195
- return &r_A;
196
+ return C_O1_I1(r, A);
197
case INDEX_op_qemu_ld_i64:
198
- return &R_A;
199
+ return C_O1_I1(R, A);
200
case INDEX_op_qemu_st_i32:
201
- return &sZ_A;
202
+ return C_O0_I2(sZ, A);
203
case INDEX_op_qemu_st_i64:
204
- return &SZ_A;
205
+ return C_O0_I2(SZ, A);
206
207
default:
208
- return NULL;
209
+ g_assert_not_reached();
210
}
211
}
54
}
212
55
213
--
56
--
214
2.25.1
57
2.43.0
215
58
216
59
diff view generated by jsdifflib
[PULL 09/24] tcg/tci: Split out target constraints to tcg-target-con-str.h
[PULL 04/24] tcg: Merge INDEX_op_qemu_*_{a32,a64}_*
1
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
1
Since 64-on-32 is now unsupported, guest addresses always
2
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
fit in one host register. Drop the replication of opcodes.
3
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
---
5
---
5
tcg/tci/tcg-target-con-str.h | 11 +++++++++++
6
include/tcg/tcg-opc.h | 28 ++------
6
tcg/tci/tcg-target.h | 2 ++
7
tcg/optimize.c | 21 ++----
7
tcg/tci/tcg-target.c.inc | 14 --------------
8
tcg/tcg-op-ldst.c | 82 +++++----------------
8
3 files changed, 13 insertions(+), 14 deletions(-)
9
tcg/tcg.c | 42 ++++-------
9
create mode 100644 tcg/tci/tcg-target-con-str.h
10
tcg/tci.c | 119 ++++++-------------------------
11
tcg/aarch64/tcg-target.c.inc | 36 ++++------
12
tcg/arm/tcg-target.c.inc | 40 +++--------
13
tcg/i386/tcg-target.c.inc | 69 ++++--------------
14
tcg/loongarch64/tcg-target.c.inc | 36 ++++------
15
tcg/mips/tcg-target.c.inc | 51 +++----------
16
tcg/ppc/tcg-target.c.inc | 68 ++++--------------
17
tcg/riscv/tcg-target.c.inc | 24 +++----
18
tcg/s390x/tcg-target.c.inc | 36 ++++------
19
tcg/sparc64/tcg-target.c.inc | 24 +++----
20
tcg/tci/tcg-target.c.inc | 60 ++++------------
21
15 files changed, 177 insertions(+), 559 deletions(-)
10
22
11
diff --git a/tcg/tci/tcg-target-con-str.h b/tcg/tci/tcg-target-con-str.h
23
diff --git a/include/tcg/tcg-opc.h b/include/tcg/tcg-opc.h
12
new file mode 100644
24
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX
25
--- a/include/tcg/tcg-opc.h
14
--- /dev/null
26
+++ b/include/tcg/tcg-opc.h
15
+++ b/tcg/tci/tcg-target-con-str.h
27
@@ -XXX,XX +XXX,XX @@ DEF(goto_ptr, 0, 1, 0, TCG_OPF_BB_EXIT | TCG_OPF_BB_END)
16
@@ -XXX,XX +XXX,XX @@
28
DEF(plugin_cb, 0, 0, 1, TCG_OPF_NOT_PRESENT)
17
+/* SPDX-License-Identifier: MIT */
29
DEF(plugin_mem_cb, 0, 1, 1, TCG_OPF_NOT_PRESENT)
18
+/*
30
19
+ * Define TCI target-specific operand constraints.
31
-/* Replicate ld/st ops for 32 and 64-bit guest addresses. */
20
+ * Copyright (c) 2021 Linaro
32
-DEF(qemu_ld_a32_i32, 1, 1, 1,
21
+ */
33
+DEF(qemu_ld_i32, 1, 1, 1,
22
+
34
TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
23
+/*
35
-DEF(qemu_st_a32_i32, 0, 1 + 1, 1,
24
+ * Define constraint letters for register sets:
36
+DEF(qemu_st_i32, 0, 1 + 1, 1,
25
+ * REGS(letter, register_mask)
37
TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
26
+ */
38
-DEF(qemu_ld_a32_i64, DATA64_ARGS, 1, 1,
27
+REGS('r', MAKE_64BIT_MASK(0, TCG_TARGET_NB_REGS))
39
+DEF(qemu_ld_i64, DATA64_ARGS, 1, 1,
28
diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h
40
TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
29
index XXXXXXX..XXXXXXX 100644
41
-DEF(qemu_st_a32_i64, 0, DATA64_ARGS + 1, 1,
30
--- a/tcg/tci/tcg-target.h
42
- TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
31
+++ b/tcg/tci/tcg-target.h
43
-
32
@@ -XXX,XX +XXX,XX @@ static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_rx,
44
-DEF(qemu_ld_a64_i32, 1, DATA64_ARGS, 1,
33
/* no need to flush icache explicitly */
45
- TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
46
-DEF(qemu_st_a64_i32, 0, 1 + DATA64_ARGS, 1,
47
- TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
48
-DEF(qemu_ld_a64_i64, DATA64_ARGS, DATA64_ARGS, 1,
49
- TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
50
-DEF(qemu_st_a64_i64, 0, DATA64_ARGS + DATA64_ARGS, 1,
51
+DEF(qemu_st_i64, 0, DATA64_ARGS + 1, 1,
52
TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
53
54
/* Only used by i386 to cope with stupid register constraints. */
55
-DEF(qemu_st8_a32_i32, 0, 1 + 1, 1,
56
- TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
57
-DEF(qemu_st8_a64_i32, 0, 1 + DATA64_ARGS, 1,
58
+DEF(qemu_st8_i32, 0, 1 + 1, 1,
59
TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
60
61
/* Only for 64-bit hosts at the moment. */
62
-DEF(qemu_ld_a32_i128, 2, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
63
-DEF(qemu_ld_a64_i128, 2, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
64
-DEF(qemu_st_a32_i128, 0, 3, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
65
-DEF(qemu_st_a64_i128, 0, 3, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
66
+DEF(qemu_ld_i128, 2, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
67
+DEF(qemu_st_i128, 0, 3, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
68
69
/* Host vector support. */
70
71
diff --git a/tcg/optimize.c b/tcg/optimize.c
72
index XXXXXXX..XXXXXXX 100644
73
--- a/tcg/optimize.c
74
+++ b/tcg/optimize.c
75
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
76
CASE_OP_32_64_VEC(orc):
77
done = fold_orc(&ctx, op);
78
break;
79
- case INDEX_op_qemu_ld_a32_i32:
80
- case INDEX_op_qemu_ld_a64_i32:
81
+ case INDEX_op_qemu_ld_i32:
82
done = fold_qemu_ld_1reg(&ctx, op);
83
break;
84
- case INDEX_op_qemu_ld_a32_i64:
85
- case INDEX_op_qemu_ld_a64_i64:
86
+ case INDEX_op_qemu_ld_i64:
87
if (TCG_TARGET_REG_BITS == 64) {
88
done = fold_qemu_ld_1reg(&ctx, op);
89
break;
90
}
91
QEMU_FALLTHROUGH;
92
- case INDEX_op_qemu_ld_a32_i128:
93
- case INDEX_op_qemu_ld_a64_i128:
94
+ case INDEX_op_qemu_ld_i128:
95
done = fold_qemu_ld_2reg(&ctx, op);
96
break;
97
- case INDEX_op_qemu_st8_a32_i32:
98
- case INDEX_op_qemu_st8_a64_i32:
99
- case INDEX_op_qemu_st_a32_i32:
100
- case INDEX_op_qemu_st_a64_i32:
101
- case INDEX_op_qemu_st_a32_i64:
102
- case INDEX_op_qemu_st_a64_i64:
103
- case INDEX_op_qemu_st_a32_i128:
104
- case INDEX_op_qemu_st_a64_i128:
105
+ case INDEX_op_qemu_st8_i32:
106
+ case INDEX_op_qemu_st_i32:
107
+ case INDEX_op_qemu_st_i64:
108
+ case INDEX_op_qemu_st_i128:
109
done = fold_qemu_st(&ctx, op);
110
break;
111
CASE_OP_32_64(rem):
112
diff --git a/tcg/tcg-op-ldst.c b/tcg/tcg-op-ldst.c
113
index XXXXXXX..XXXXXXX 100644
114
--- a/tcg/tcg-op-ldst.c
115
+++ b/tcg/tcg-op-ldst.c
116
@@ -XXX,XX +XXX,XX @@ static void tcg_gen_qemu_ld_i32_int(TCGv_i32 val, TCGTemp *addr,
117
MemOp orig_memop;
118
MemOpIdx orig_oi, oi;
119
TCGv_i64 copy_addr;
120
- TCGOpcode opc;
121
122
tcg_gen_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD);
123
orig_memop = memop = tcg_canonicalize_memop(memop, 0, 0);
124
@@ -XXX,XX +XXX,XX @@ static void tcg_gen_qemu_ld_i32_int(TCGv_i32 val, TCGTemp *addr,
125
}
126
127
copy_addr = plugin_maybe_preserve_addr(addr);
128
- if (tcg_ctx->addr_type == TCG_TYPE_I32) {
129
- opc = INDEX_op_qemu_ld_a32_i32;
130
- } else {
131
- opc = INDEX_op_qemu_ld_a64_i32;
132
- }
133
- gen_ldst(opc, TCG_TYPE_I32, tcgv_i32_temp(val), NULL, addr, oi);
134
+ gen_ldst(INDEX_op_qemu_ld_i32, TCG_TYPE_I32,
135
+ tcgv_i32_temp(val), NULL, addr, oi);
136
plugin_gen_mem_callbacks_i32(val, copy_addr, addr, orig_oi,
137
QEMU_PLUGIN_MEM_R);
138
139
@@ -XXX,XX +XXX,XX @@ static void tcg_gen_qemu_st_i32_int(TCGv_i32 val, TCGTemp *addr,
140
}
141
142
if (TCG_TARGET_HAS_qemu_st8_i32 && (memop & MO_SIZE) == MO_8) {
143
- if (tcg_ctx->addr_type == TCG_TYPE_I32) {
144
- opc = INDEX_op_qemu_st8_a32_i32;
145
- } else {
146
- opc = INDEX_op_qemu_st8_a64_i32;
147
- }
148
+ opc = INDEX_op_qemu_st8_i32;
149
} else {
150
- if (tcg_ctx->addr_type == TCG_TYPE_I32) {
151
- opc = INDEX_op_qemu_st_a32_i32;
152
- } else {
153
- opc = INDEX_op_qemu_st_a64_i32;
154
- }
155
+ opc = INDEX_op_qemu_st_i32;
156
}
157
gen_ldst(opc, TCG_TYPE_I32, tcgv_i32_temp(val), NULL, addr, oi);
158
plugin_gen_mem_callbacks_i32(val, NULL, addr, orig_oi, QEMU_PLUGIN_MEM_W);
159
@@ -XXX,XX +XXX,XX @@ static void tcg_gen_qemu_ld_i64_int(TCGv_i64 val, TCGTemp *addr,
160
MemOp orig_memop;
161
MemOpIdx orig_oi, oi;
162
TCGv_i64 copy_addr;
163
- TCGOpcode opc;
164
165
if (TCG_TARGET_REG_BITS == 32 && (memop & MO_SIZE) < MO_64) {
166
tcg_gen_qemu_ld_i32_int(TCGV_LOW(val), addr, idx, memop);
167
@@ -XXX,XX +XXX,XX @@ static void tcg_gen_qemu_ld_i64_int(TCGv_i64 val, TCGTemp *addr,
168
}
169
170
copy_addr = plugin_maybe_preserve_addr(addr);
171
- if (tcg_ctx->addr_type == TCG_TYPE_I32) {
172
- opc = INDEX_op_qemu_ld_a32_i64;
173
- } else {
174
- opc = INDEX_op_qemu_ld_a64_i64;
175
- }
176
- gen_ldst_i64(opc, val, addr, oi);
177
+ gen_ldst_i64(INDEX_op_qemu_ld_i64, val, addr, oi);
178
plugin_gen_mem_callbacks_i64(val, copy_addr, addr, orig_oi,
179
QEMU_PLUGIN_MEM_R);
180
181
@@ -XXX,XX +XXX,XX @@ static void tcg_gen_qemu_st_i64_int(TCGv_i64 val, TCGTemp *addr,
182
{
183
TCGv_i64 swap = NULL;
184
MemOpIdx orig_oi, oi;
185
- TCGOpcode opc;
186
187
if (TCG_TARGET_REG_BITS == 32 && (memop & MO_SIZE) < MO_64) {
188
tcg_gen_qemu_st_i32_int(TCGV_LOW(val), addr, idx, memop);
189
@@ -XXX,XX +XXX,XX @@ static void tcg_gen_qemu_st_i64_int(TCGv_i64 val, TCGTemp *addr,
190
oi = make_memop_idx(memop, idx);
191
}
192
193
- if (tcg_ctx->addr_type == TCG_TYPE_I32) {
194
- opc = INDEX_op_qemu_st_a32_i64;
195
- } else {
196
- opc = INDEX_op_qemu_st_a64_i64;
197
- }
198
- gen_ldst_i64(opc, val, addr, oi);
199
+ gen_ldst_i64(INDEX_op_qemu_st_i64, val, addr, oi);
200
plugin_gen_mem_callbacks_i64(val, NULL, addr, orig_oi, QEMU_PLUGIN_MEM_W);
201
202
if (swap) {
203
@@ -XXX,XX +XXX,XX @@ static void tcg_gen_qemu_ld_i128_int(TCGv_i128 val, TCGTemp *addr,
204
{
205
MemOpIdx orig_oi;
206
TCGv_i64 ext_addr = NULL;
207
- TCGOpcode opc;
208
209
check_max_alignment(memop_alignment_bits(memop));
210
tcg_gen_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD);
211
@@ -XXX,XX +XXX,XX @@ static void tcg_gen_qemu_ld_i128_int(TCGv_i128 val, TCGTemp *addr,
212
hi = TCGV128_HIGH(val);
213
}
214
215
- if (tcg_ctx->addr_type == TCG_TYPE_I32) {
216
- opc = INDEX_op_qemu_ld_a32_i128;
217
- } else {
218
- opc = INDEX_op_qemu_ld_a64_i128;
219
- }
220
- gen_ldst(opc, TCG_TYPE_I128, tcgv_i64_temp(lo),
221
+ gen_ldst(INDEX_op_qemu_ld_i128, TCG_TYPE_I128, tcgv_i64_temp(lo),
222
tcgv_i64_temp(hi), addr, oi);
223
224
if (need_bswap) {
225
@@ -XXX,XX +XXX,XX @@ static void tcg_gen_qemu_ld_i128_int(TCGv_i128 val, TCGTemp *addr,
226
canonicalize_memop_i128_as_i64(mop, memop);
227
need_bswap = (mop[0] ^ memop) & MO_BSWAP;
228
229
- if (tcg_ctx->addr_type == TCG_TYPE_I32) {
230
- opc = INDEX_op_qemu_ld_a32_i64;
231
- } else {
232
- opc = INDEX_op_qemu_ld_a64_i64;
233
- }
234
-
235
/*
236
* Since there are no global TCGv_i128, there is no visible state
237
* changed if the second load faults. Load directly into the two
238
@@ -XXX,XX +XXX,XX @@ static void tcg_gen_qemu_ld_i128_int(TCGv_i128 val, TCGTemp *addr,
239
y = TCGV128_LOW(val);
240
}
241
242
- gen_ldst_i64(opc, x, addr, make_memop_idx(mop[0], idx));
243
+ gen_ldst_i64(INDEX_op_qemu_ld_i64, x, addr,
244
+ make_memop_idx(mop[0], idx));
245
246
if (need_bswap) {
247
tcg_gen_bswap64_i64(x, x);
248
@@ -XXX,XX +XXX,XX @@ static void tcg_gen_qemu_ld_i128_int(TCGv_i128 val, TCGTemp *addr,
249
addr_p8 = tcgv_i64_temp(t);
250
}
251
252
- gen_ldst_i64(opc, y, addr_p8, make_memop_idx(mop[1], idx));
253
+ gen_ldst_i64(INDEX_op_qemu_ld_i64, y, addr_p8,
254
+ make_memop_idx(mop[1], idx));
255
tcg_temp_free_internal(addr_p8);
256
257
if (need_bswap) {
258
@@ -XXX,XX +XXX,XX @@ static void tcg_gen_qemu_st_i128_int(TCGv_i128 val, TCGTemp *addr,
259
{
260
MemOpIdx orig_oi;
261
TCGv_i64 ext_addr = NULL;
262
- TCGOpcode opc;
263
264
check_max_alignment(memop_alignment_bits(memop));
265
tcg_gen_req_mo(TCG_MO_ST_LD | TCG_MO_ST_ST);
266
@@ -XXX,XX +XXX,XX @@ static void tcg_gen_qemu_st_i128_int(TCGv_i128 val, TCGTemp *addr,
267
hi = TCGV128_HIGH(val);
268
}
269
270
- if (tcg_ctx->addr_type == TCG_TYPE_I32) {
271
- opc = INDEX_op_qemu_st_a32_i128;
272
- } else {
273
- opc = INDEX_op_qemu_st_a64_i128;
274
- }
275
- gen_ldst(opc, TCG_TYPE_I128, tcgv_i64_temp(lo),
276
- tcgv_i64_temp(hi), addr, oi);
277
+ gen_ldst(INDEX_op_qemu_st_i128, TCG_TYPE_I128,
278
+ tcgv_i64_temp(lo), tcgv_i64_temp(hi), addr, oi);
279
280
if (need_bswap) {
281
tcg_temp_free_i64(lo);
282
@@ -XXX,XX +XXX,XX @@ static void tcg_gen_qemu_st_i128_int(TCGv_i128 val, TCGTemp *addr,
283
284
canonicalize_memop_i128_as_i64(mop, memop);
285
286
- if (tcg_ctx->addr_type == TCG_TYPE_I32) {
287
- opc = INDEX_op_qemu_st_a32_i64;
288
- } else {
289
- opc = INDEX_op_qemu_st_a64_i64;
290
- }
291
-
292
if ((memop & MO_BSWAP) == MO_LE) {
293
x = TCGV128_LOW(val);
294
y = TCGV128_HIGH(val);
295
@@ -XXX,XX +XXX,XX @@ static void tcg_gen_qemu_st_i128_int(TCGv_i128 val, TCGTemp *addr,
296
x = b;
297
}
298
299
- gen_ldst_i64(opc, x, addr, make_memop_idx(mop[0], idx));
300
+ gen_ldst_i64(INDEX_op_qemu_st_i64, x, addr,
301
+ make_memop_idx(mop[0], idx));
302
303
if (tcg_ctx->addr_type == TCG_TYPE_I32) {
304
TCGv_i32 t = tcg_temp_ebb_new_i32();
305
@@ -XXX,XX +XXX,XX @@ static void tcg_gen_qemu_st_i128_int(TCGv_i128 val, TCGTemp *addr,
306
307
if (b) {
308
tcg_gen_bswap64_i64(b, y);
309
- gen_ldst_i64(opc, b, addr_p8, make_memop_idx(mop[1], idx));
310
+ gen_ldst_i64(INDEX_op_qemu_st_i64, b, addr_p8,
311
+ make_memop_idx(mop[1], idx));
312
tcg_temp_free_i64(b);
313
} else {
314
- gen_ldst_i64(opc, y, addr_p8, make_memop_idx(mop[1], idx));
315
+ gen_ldst_i64(INDEX_op_qemu_st_i64, y, addr_p8,
316
+ make_memop_idx(mop[1], idx));
317
}
318
tcg_temp_free_internal(addr_p8);
319
} else {
320
diff --git a/tcg/tcg.c b/tcg/tcg.c
321
index XXXXXXX..XXXXXXX 100644
322
--- a/tcg/tcg.c
323
+++ b/tcg/tcg.c
324
@@ -XXX,XX +XXX,XX @@ bool tcg_op_supported(TCGOpcode op, TCGType type, unsigned flags)
325
case INDEX_op_exit_tb:
326
case INDEX_op_goto_tb:
327
case INDEX_op_goto_ptr:
328
- case INDEX_op_qemu_ld_a32_i32:
329
- case INDEX_op_qemu_ld_a64_i32:
330
- case INDEX_op_qemu_st_a32_i32:
331
- case INDEX_op_qemu_st_a64_i32:
332
- case INDEX_op_qemu_ld_a32_i64:
333
- case INDEX_op_qemu_ld_a64_i64:
334
- case INDEX_op_qemu_st_a32_i64:
335
- case INDEX_op_qemu_st_a64_i64:
336
+ case INDEX_op_qemu_ld_i32:
337
+ case INDEX_op_qemu_st_i32:
338
+ case INDEX_op_qemu_ld_i64:
339
+ case INDEX_op_qemu_st_i64:
340
return true;
341
342
- case INDEX_op_qemu_st8_a32_i32:
343
- case INDEX_op_qemu_st8_a64_i32:
344
+ case INDEX_op_qemu_st8_i32:
345
return TCG_TARGET_HAS_qemu_st8_i32;
346
347
- case INDEX_op_qemu_ld_a32_i128:
348
- case INDEX_op_qemu_ld_a64_i128:
349
- case INDEX_op_qemu_st_a32_i128:
350
- case INDEX_op_qemu_st_a64_i128:
351
+ case INDEX_op_qemu_ld_i128:
352
+ case INDEX_op_qemu_st_i128:
353
return TCG_TARGET_HAS_qemu_ldst_i128;
354
355
case INDEX_op_mov_i32:
356
@@ -XXX,XX +XXX,XX @@ void tcg_dump_ops(TCGContext *s, FILE *f, bool have_prefs)
357
}
358
i = 1;
359
break;
360
- case INDEX_op_qemu_ld_a32_i32:
361
- case INDEX_op_qemu_ld_a64_i32:
362
- case INDEX_op_qemu_st_a32_i32:
363
- case INDEX_op_qemu_st_a64_i32:
364
- case INDEX_op_qemu_st8_a32_i32:
365
- case INDEX_op_qemu_st8_a64_i32:
366
- case INDEX_op_qemu_ld_a32_i64:
367
- case INDEX_op_qemu_ld_a64_i64:
368
- case INDEX_op_qemu_st_a32_i64:
369
- case INDEX_op_qemu_st_a64_i64:
370
- case INDEX_op_qemu_ld_a32_i128:
371
- case INDEX_op_qemu_ld_a64_i128:
372
- case INDEX_op_qemu_st_a32_i128:
373
- case INDEX_op_qemu_st_a64_i128:
374
+ case INDEX_op_qemu_ld_i32:
375
+ case INDEX_op_qemu_st_i32:
376
+ case INDEX_op_qemu_st8_i32:
377
+ case INDEX_op_qemu_ld_i64:
378
+ case INDEX_op_qemu_st_i64:
379
+ case INDEX_op_qemu_ld_i128:
380
+ case INDEX_op_qemu_st_i128:
381
{
382
const char *s_al, *s_op, *s_at;
383
MemOpIdx oi = op->args[k++];
384
diff --git a/tcg/tci.c b/tcg/tci.c
385
index XXXXXXX..XXXXXXX 100644
386
--- a/tcg/tci.c
387
+++ b/tcg/tci.c
388
@@ -XXX,XX +XXX,XX @@ static void tci_args_rrrbb(uint32_t insn, TCGReg *r0, TCGReg *r1,
389
*i4 = extract32(insn, 26, 6);
34
}
390
}
35
391
36
+#define TCG_TARGET_CON_STR_H
392
-static void tci_args_rrrrr(uint32_t insn, TCGReg *r0, TCGReg *r1,
37
+
393
- TCGReg *r2, TCGReg *r3, TCGReg *r4)
38
#endif /* TCG_TARGET_H */
394
-{
395
- *r0 = extract32(insn, 8, 4);
396
- *r1 = extract32(insn, 12, 4);
397
- *r2 = extract32(insn, 16, 4);
398
- *r3 = extract32(insn, 20, 4);
399
- *r4 = extract32(insn, 24, 4);
400
-}
401
-
402
static void tci_args_rrrr(uint32_t insn,
403
TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGReg *r3)
404
{
405
@@ -XXX,XX +XXX,XX @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
406
tb_ptr = ptr;
407
break;
408
409
- case INDEX_op_qemu_ld_a32_i32:
410
+ case INDEX_op_qemu_ld_i32:
411
tci_args_rrm(insn, &r0, &r1, &oi);
412
- taddr = (uint32_t)regs[r1];
413
- goto do_ld_i32;
414
- case INDEX_op_qemu_ld_a64_i32:
415
- if (TCG_TARGET_REG_BITS == 64) {
416
- tci_args_rrm(insn, &r0, &r1, &oi);
417
- taddr = regs[r1];
418
- } else {
419
- tci_args_rrrr(insn, &r0, &r1, &r2, &r3);
420
- taddr = tci_uint64(regs[r2], regs[r1]);
421
- oi = regs[r3];
422
- }
423
- do_ld_i32:
424
+ taddr = regs[r1];
425
regs[r0] = tci_qemu_ld(env, taddr, oi, tb_ptr);
426
break;
427
428
- case INDEX_op_qemu_ld_a32_i64:
429
- if (TCG_TARGET_REG_BITS == 64) {
430
- tci_args_rrm(insn, &r0, &r1, &oi);
431
- taddr = (uint32_t)regs[r1];
432
- } else {
433
- tci_args_rrrr(insn, &r0, &r1, &r2, &r3);
434
- taddr = (uint32_t)regs[r2];
435
- oi = regs[r3];
436
- }
437
- goto do_ld_i64;
438
- case INDEX_op_qemu_ld_a64_i64:
439
+ case INDEX_op_qemu_ld_i64:
440
if (TCG_TARGET_REG_BITS == 64) {
441
tci_args_rrm(insn, &r0, &r1, &oi);
442
taddr = regs[r1];
443
} else {
444
- tci_args_rrrrr(insn, &r0, &r1, &r2, &r3, &r4);
445
- taddr = tci_uint64(regs[r3], regs[r2]);
446
- oi = regs[r4];
447
+ tci_args_rrrr(insn, &r0, &r1, &r2, &r3);
448
+ taddr = regs[r2];
449
+ oi = regs[r3];
450
}
451
- do_ld_i64:
452
tmp64 = tci_qemu_ld(env, taddr, oi, tb_ptr);
453
if (TCG_TARGET_REG_BITS == 32) {
454
tci_write_reg64(regs, r1, r0, tmp64);
455
@@ -XXX,XX +XXX,XX @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
456
}
457
break;
458
459
- case INDEX_op_qemu_st_a32_i32:
460
+ case INDEX_op_qemu_st_i32:
461
tci_args_rrm(insn, &r0, &r1, &oi);
462
- taddr = (uint32_t)regs[r1];
463
- goto do_st_i32;
464
- case INDEX_op_qemu_st_a64_i32:
465
- if (TCG_TARGET_REG_BITS == 64) {
466
- tci_args_rrm(insn, &r0, &r1, &oi);
467
- taddr = regs[r1];
468
- } else {
469
- tci_args_rrrr(insn, &r0, &r1, &r2, &r3);
470
- taddr = tci_uint64(regs[r2], regs[r1]);
471
- oi = regs[r3];
472
- }
473
- do_st_i32:
474
+ taddr = regs[r1];
475
tci_qemu_st(env, taddr, regs[r0], oi, tb_ptr);
476
break;
477
478
- case INDEX_op_qemu_st_a32_i64:
479
- if (TCG_TARGET_REG_BITS == 64) {
480
- tci_args_rrm(insn, &r0, &r1, &oi);
481
- tmp64 = regs[r0];
482
- taddr = (uint32_t)regs[r1];
483
- } else {
484
- tci_args_rrrr(insn, &r0, &r1, &r2, &r3);
485
- tmp64 = tci_uint64(regs[r1], regs[r0]);
486
- taddr = (uint32_t)regs[r2];
487
- oi = regs[r3];
488
- }
489
- goto do_st_i64;
490
- case INDEX_op_qemu_st_a64_i64:
491
+ case INDEX_op_qemu_st_i64:
492
if (TCG_TARGET_REG_BITS == 64) {
493
tci_args_rrm(insn, &r0, &r1, &oi);
494
tmp64 = regs[r0];
495
taddr = regs[r1];
496
} else {
497
- tci_args_rrrrr(insn, &r0, &r1, &r2, &r3, &r4);
498
+ tci_args_rrrr(insn, &r0, &r1, &r2, &r3);
499
tmp64 = tci_uint64(regs[r1], regs[r0]);
500
- taddr = tci_uint64(regs[r3], regs[r2]);
501
- oi = regs[r4];
502
+ taddr = regs[r2];
503
+ oi = regs[r3];
504
}
505
- do_st_i64:
506
tci_qemu_st(env, taddr, tmp64, oi, tb_ptr);
507
break;
508
509
@@ -XXX,XX +XXX,XX @@ int print_insn_tci(bfd_vma addr, disassemble_info *info)
510
str_r(r3), str_r(r4), str_r(r5));
511
break;
512
513
- case INDEX_op_qemu_ld_a32_i32:
514
- case INDEX_op_qemu_st_a32_i32:
515
- len = 1 + 1;
516
- goto do_qemu_ldst;
517
- case INDEX_op_qemu_ld_a32_i64:
518
- case INDEX_op_qemu_st_a32_i64:
519
- case INDEX_op_qemu_ld_a64_i32:
520
- case INDEX_op_qemu_st_a64_i32:
521
- len = 1 + DIV_ROUND_UP(64, TCG_TARGET_REG_BITS);
522
- goto do_qemu_ldst;
523
- case INDEX_op_qemu_ld_a64_i64:
524
- case INDEX_op_qemu_st_a64_i64:
525
- len = 2 * DIV_ROUND_UP(64, TCG_TARGET_REG_BITS);
526
- goto do_qemu_ldst;
527
- do_qemu_ldst:
528
- switch (len) {
529
- case 2:
530
- tci_args_rrm(insn, &r0, &r1, &oi);
531
- info->fprintf_func(info->stream, "%-12s %s, %s, %x",
532
- op_name, str_r(r0), str_r(r1), oi);
533
- break;
534
- case 3:
535
+ case INDEX_op_qemu_ld_i64:
536
+ case INDEX_op_qemu_st_i64:
537
+ if (TCG_TARGET_REG_BITS == 32) {
538
tci_args_rrrr(insn, &r0, &r1, &r2, &r3);
539
info->fprintf_func(info->stream, "%-12s %s, %s, %s, %s",
540
op_name, str_r(r0), str_r(r1),
541
str_r(r2), str_r(r3));
542
break;
543
- case 4:
544
- tci_args_rrrrr(insn, &r0, &r1, &r2, &r3, &r4);
545
- info->fprintf_func(info->stream, "%-12s %s, %s, %s, %s, %s",
546
- op_name, str_r(r0), str_r(r1),
547
- str_r(r2), str_r(r3), str_r(r4));
548
- break;
549
- default:
550
- g_assert_not_reached();
551
}
552
+ /* fall through */
553
+ case INDEX_op_qemu_ld_i32:
554
+ case INDEX_op_qemu_st_i32:
555
+ tci_args_rrm(insn, &r0, &r1, &oi);
556
+ info->fprintf_func(info->stream, "%-12s %s, %s, %x",
557
+ op_name, str_r(r0), str_r(r1), oi);
558
break;
559
560
case 0:
561
diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc
562
index XXXXXXX..XXXXXXX 100644
563
--- a/tcg/aarch64/tcg-target.c.inc
564
+++ b/tcg/aarch64/tcg-target.c.inc
565
@@ -XXX,XX +XXX,XX @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType ext,
566
tcg_out_insn(s, 3506, CSEL, ext, a0, REG0(3), REG0(4), args[5]);
567
break;
568
569
- case INDEX_op_qemu_ld_a32_i32:
570
- case INDEX_op_qemu_ld_a64_i32:
571
- case INDEX_op_qemu_ld_a32_i64:
572
- case INDEX_op_qemu_ld_a64_i64:
573
+ case INDEX_op_qemu_ld_i32:
574
+ case INDEX_op_qemu_ld_i64:
575
tcg_out_qemu_ld(s, a0, a1, a2, ext);
576
break;
577
- case INDEX_op_qemu_st_a32_i32:
578
- case INDEX_op_qemu_st_a64_i32:
579
- case INDEX_op_qemu_st_a32_i64:
580
- case INDEX_op_qemu_st_a64_i64:
581
+ case INDEX_op_qemu_st_i32:
582
+ case INDEX_op_qemu_st_i64:
583
tcg_out_qemu_st(s, REG0(0), a1, a2, ext);
584
break;
585
- case INDEX_op_qemu_ld_a32_i128:
586
- case INDEX_op_qemu_ld_a64_i128:
587
+ case INDEX_op_qemu_ld_i128:
588
tcg_out_qemu_ldst_i128(s, a0, a1, a2, args[3], true);
589
break;
590
- case INDEX_op_qemu_st_a32_i128:
591
- case INDEX_op_qemu_st_a64_i128:
592
+ case INDEX_op_qemu_st_i128:
593
tcg_out_qemu_ldst_i128(s, REG0(0), REG0(1), a2, args[3], false);
594
break;
595
596
@@ -XXX,XX +XXX,XX @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
597
case INDEX_op_movcond_i64:
598
return C_O1_I4(r, r, rC, rZ, rZ);
599
600
- case INDEX_op_qemu_ld_a32_i32:
601
- case INDEX_op_qemu_ld_a64_i32:
602
- case INDEX_op_qemu_ld_a32_i64:
603
- case INDEX_op_qemu_ld_a64_i64:
604
+ case INDEX_op_qemu_ld_i32:
605
+ case INDEX_op_qemu_ld_i64:
606
return C_O1_I1(r, r);
607
- case INDEX_op_qemu_ld_a32_i128:
608
- case INDEX_op_qemu_ld_a64_i128:
609
+ case INDEX_op_qemu_ld_i128:
610
return C_O2_I1(r, r, r);
611
- case INDEX_op_qemu_st_a32_i32:
612
- case INDEX_op_qemu_st_a64_i32:
613
- case INDEX_op_qemu_st_a32_i64:
614
- case INDEX_op_qemu_st_a64_i64:
615
+ case INDEX_op_qemu_st_i32:
616
+ case INDEX_op_qemu_st_i64:
617
return C_O0_I2(rZ, r);
618
- case INDEX_op_qemu_st_a32_i128:
619
- case INDEX_op_qemu_st_a64_i128:
620
+ case INDEX_op_qemu_st_i128:
621
return C_O0_I3(rZ, rZ, r);
622
623
case INDEX_op_deposit_i32:
624
diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
625
index XXXXXXX..XXXXXXX 100644
626
--- a/tcg/arm/tcg-target.c.inc
627
+++ b/tcg/arm/tcg-target.c.inc
628
@@ -XXX,XX +XXX,XX @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
629
ARITH_MOV, args[0], 0, 0);
630
break;
631
632
- case INDEX_op_qemu_ld_a32_i32:
633
+ case INDEX_op_qemu_ld_i32:
634
tcg_out_qemu_ld(s, args[0], -1, args[1], -1, args[2], TCG_TYPE_I32);
635
break;
636
- case INDEX_op_qemu_ld_a64_i32:
637
- tcg_out_qemu_ld(s, args[0], -1, args[1], args[2],
638
- args[3], TCG_TYPE_I32);
639
- break;
640
- case INDEX_op_qemu_ld_a32_i64:
641
+ case INDEX_op_qemu_ld_i64:
642
tcg_out_qemu_ld(s, args[0], args[1], args[2], -1,
643
args[3], TCG_TYPE_I64);
644
break;
645
- case INDEX_op_qemu_ld_a64_i64:
646
- tcg_out_qemu_ld(s, args[0], args[1], args[2], args[3],
647
- args[4], TCG_TYPE_I64);
648
- break;
649
650
- case INDEX_op_qemu_st_a32_i32:
651
+ case INDEX_op_qemu_st_i32:
652
tcg_out_qemu_st(s, args[0], -1, args[1], -1, args[2], TCG_TYPE_I32);
653
break;
654
- case INDEX_op_qemu_st_a64_i32:
655
- tcg_out_qemu_st(s, args[0], -1, args[1], args[2],
656
- args[3], TCG_TYPE_I32);
657
- break;
658
- case INDEX_op_qemu_st_a32_i64:
659
+ case INDEX_op_qemu_st_i64:
660
tcg_out_qemu_st(s, args[0], args[1], args[2], -1,
661
args[3], TCG_TYPE_I64);
662
break;
663
- case INDEX_op_qemu_st_a64_i64:
664
- tcg_out_qemu_st(s, args[0], args[1], args[2], args[3],
665
- args[4], TCG_TYPE_I64);
666
- break;
667
668
case INDEX_op_bswap16_i32:
669
tcg_out_bswap16(s, COND_AL, args[0], args[1], args[2]);
670
@@ -XXX,XX +XXX,XX @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
671
case INDEX_op_setcond2_i32:
672
return C_O1_I4(r, r, r, rI, rI);
673
674
- case INDEX_op_qemu_ld_a32_i32:
675
+ case INDEX_op_qemu_ld_i32:
676
return C_O1_I1(r, q);
677
- case INDEX_op_qemu_ld_a64_i32:
678
- return C_O1_I2(r, q, q);
679
- case INDEX_op_qemu_ld_a32_i64:
680
+ case INDEX_op_qemu_ld_i64:
681
return C_O2_I1(e, p, q);
682
- case INDEX_op_qemu_ld_a64_i64:
683
- return C_O2_I2(e, p, q, q);
684
- case INDEX_op_qemu_st_a32_i32:
685
+ case INDEX_op_qemu_st_i32:
686
return C_O0_I2(q, q);
687
- case INDEX_op_qemu_st_a64_i32:
688
- return C_O0_I3(q, q, q);
689
- case INDEX_op_qemu_st_a32_i64:
690
+ case INDEX_op_qemu_st_i64:
691
return C_O0_I3(Q, p, q);
692
- case INDEX_op_qemu_st_a64_i64:
693
- return C_O0_I4(Q, p, q, q);
694
695
case INDEX_op_st_vec:
696
return C_O0_I2(w, r);
697
diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
698
index XXXXXXX..XXXXXXX 100644
699
--- a/tcg/i386/tcg-target.c.inc
700
+++ b/tcg/i386/tcg-target.c.inc
701
@@ -XXX,XX +XXX,XX @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
702
tcg_out_modrm(s, OPC_GRP3_Ev + rexw, EXT3_NOT, a0);
703
break;
704
705
- case INDEX_op_qemu_ld_a64_i32:
706
- if (TCG_TARGET_REG_BITS == 32) {
707
- tcg_out_qemu_ld(s, a0, -1, a1, a2, args[3], TCG_TYPE_I32);
708
- break;
709
- }
710
- /* fall through */
711
- case INDEX_op_qemu_ld_a32_i32:
712
+ case INDEX_op_qemu_ld_i32:
713
tcg_out_qemu_ld(s, a0, -1, a1, -1, a2, TCG_TYPE_I32);
714
break;
715
- case INDEX_op_qemu_ld_a32_i64:
716
+ case INDEX_op_qemu_ld_i64:
717
if (TCG_TARGET_REG_BITS == 64) {
718
tcg_out_qemu_ld(s, a0, -1, a1, -1, a2, TCG_TYPE_I64);
719
} else {
720
tcg_out_qemu_ld(s, a0, a1, a2, -1, args[3], TCG_TYPE_I64);
721
}
722
break;
723
- case INDEX_op_qemu_ld_a64_i64:
724
- if (TCG_TARGET_REG_BITS == 64) {
725
- tcg_out_qemu_ld(s, a0, -1, a1, -1, a2, TCG_TYPE_I64);
726
- } else {
727
- tcg_out_qemu_ld(s, a0, a1, a2, args[3], args[4], TCG_TYPE_I64);
728
- }
729
- break;
730
- case INDEX_op_qemu_ld_a32_i128:
731
- case INDEX_op_qemu_ld_a64_i128:
732
+ case INDEX_op_qemu_ld_i128:
733
tcg_debug_assert(TCG_TARGET_REG_BITS == 64);
734
tcg_out_qemu_ld(s, a0, a1, a2, -1, args[3], TCG_TYPE_I128);
735
break;
736
737
- case INDEX_op_qemu_st_a64_i32:
738
- case INDEX_op_qemu_st8_a64_i32:
739
- if (TCG_TARGET_REG_BITS == 32) {
740
- tcg_out_qemu_st(s, a0, -1, a1, a2, args[3], TCG_TYPE_I32);
741
- break;
742
- }
743
- /* fall through */
744
- case INDEX_op_qemu_st_a32_i32:
745
- case INDEX_op_qemu_st8_a32_i32:
746
+ case INDEX_op_qemu_st_i32:
747
+ case INDEX_op_qemu_st8_i32:
748
tcg_out_qemu_st(s, a0, -1, a1, -1, a2, TCG_TYPE_I32);
749
break;
750
- case INDEX_op_qemu_st_a32_i64:
751
+ case INDEX_op_qemu_st_i64:
752
if (TCG_TARGET_REG_BITS == 64) {
753
tcg_out_qemu_st(s, a0, -1, a1, -1, a2, TCG_TYPE_I64);
754
} else {
755
tcg_out_qemu_st(s, a0, a1, a2, -1, args[3], TCG_TYPE_I64);
756
}
757
break;
758
- case INDEX_op_qemu_st_a64_i64:
759
- if (TCG_TARGET_REG_BITS == 64) {
760
- tcg_out_qemu_st(s, a0, -1, a1, -1, a2, TCG_TYPE_I64);
761
- } else {
762
- tcg_out_qemu_st(s, a0, a1, a2, args[3], args[4], TCG_TYPE_I64);
763
- }
764
- break;
765
- case INDEX_op_qemu_st_a32_i128:
766
- case INDEX_op_qemu_st_a64_i128:
767
+ case INDEX_op_qemu_st_i128:
768
tcg_debug_assert(TCG_TARGET_REG_BITS == 64);
769
tcg_out_qemu_st(s, a0, a1, a2, -1, args[3], TCG_TYPE_I128);
770
break;
771
@@ -XXX,XX +XXX,XX @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
772
case INDEX_op_clz_i64:
773
return have_lzcnt ? C_N1_I2(r, r, rW) : C_N1_I2(r, r, r);
774
775
- case INDEX_op_qemu_ld_a32_i32:
776
+ case INDEX_op_qemu_ld_i32:
777
return C_O1_I1(r, L);
778
- case INDEX_op_qemu_ld_a64_i32:
779
- return TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, L) : C_O1_I2(r, L, L);
780
781
- case INDEX_op_qemu_st_a32_i32:
782
+ case INDEX_op_qemu_st_i32:
783
return C_O0_I2(L, L);
784
- case INDEX_op_qemu_st_a64_i32:
785
- return TCG_TARGET_REG_BITS == 64 ? C_O0_I2(L, L) : C_O0_I3(L, L, L);
786
- case INDEX_op_qemu_st8_a32_i32:
787
+ case INDEX_op_qemu_st8_i32:
788
return C_O0_I2(s, L);
789
- case INDEX_op_qemu_st8_a64_i32:
790
- return TCG_TARGET_REG_BITS == 64 ? C_O0_I2(s, L) : C_O0_I3(s, L, L);
791
792
- case INDEX_op_qemu_ld_a32_i64:
793
+ case INDEX_op_qemu_ld_i64:
794
return TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, L) : C_O2_I1(r, r, L);
795
- case INDEX_op_qemu_ld_a64_i64:
796
- return TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, L) : C_O2_I2(r, r, L, L);
797
798
- case INDEX_op_qemu_st_a32_i64:
799
+ case INDEX_op_qemu_st_i64:
800
return TCG_TARGET_REG_BITS == 64 ? C_O0_I2(L, L) : C_O0_I3(L, L, L);
801
- case INDEX_op_qemu_st_a64_i64:
802
- return TCG_TARGET_REG_BITS == 64 ? C_O0_I2(L, L) : C_O0_I4(L, L, L, L);
803
804
- case INDEX_op_qemu_ld_a32_i128:
805
- case INDEX_op_qemu_ld_a64_i128:
806
+ case INDEX_op_qemu_ld_i128:
807
tcg_debug_assert(TCG_TARGET_REG_BITS == 64);
808
return C_O2_I1(r, r, L);
809
- case INDEX_op_qemu_st_a32_i128:
810
- case INDEX_op_qemu_st_a64_i128:
811
+ case INDEX_op_qemu_st_i128:
812
tcg_debug_assert(TCG_TARGET_REG_BITS == 64);
813
return C_O0_I3(L, L, L);
814
815
diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc
816
index XXXXXXX..XXXXXXX 100644
817
--- a/tcg/loongarch64/tcg-target.c.inc
818
+++ b/tcg/loongarch64/tcg-target.c.inc
819
@@ -XXX,XX +XXX,XX @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
820
tcg_out_ldst(s, OPC_ST_D, a0, a1, a2);
821
break;
822
823
- case INDEX_op_qemu_ld_a32_i32:
824
- case INDEX_op_qemu_ld_a64_i32:
825
+ case INDEX_op_qemu_ld_i32:
826
tcg_out_qemu_ld(s, a0, a1, a2, TCG_TYPE_I32);
827
break;
828
- case INDEX_op_qemu_ld_a32_i64:
829
- case INDEX_op_qemu_ld_a64_i64:
830
+ case INDEX_op_qemu_ld_i64:
831
tcg_out_qemu_ld(s, a0, a1, a2, TCG_TYPE_I64);
832
break;
833
- case INDEX_op_qemu_ld_a32_i128:
834
- case INDEX_op_qemu_ld_a64_i128:
835
+ case INDEX_op_qemu_ld_i128:
836
tcg_out_qemu_ldst_i128(s, a0, a1, a2, a3, true);
837
break;
838
- case INDEX_op_qemu_st_a32_i32:
839
- case INDEX_op_qemu_st_a64_i32:
840
+ case INDEX_op_qemu_st_i32:
841
tcg_out_qemu_st(s, a0, a1, a2, TCG_TYPE_I32);
842
break;
843
- case INDEX_op_qemu_st_a32_i64:
844
- case INDEX_op_qemu_st_a64_i64:
845
+ case INDEX_op_qemu_st_i64:
846
tcg_out_qemu_st(s, a0, a1, a2, TCG_TYPE_I64);
847
break;
848
- case INDEX_op_qemu_st_a32_i128:
849
- case INDEX_op_qemu_st_a64_i128:
850
+ case INDEX_op_qemu_st_i128:
851
tcg_out_qemu_ldst_i128(s, a0, a1, a2, a3, false);
852
break;
853
854
@@ -XXX,XX +XXX,XX @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
855
case INDEX_op_st32_i64:
856
case INDEX_op_st_i32:
857
case INDEX_op_st_i64:
858
- case INDEX_op_qemu_st_a32_i32:
859
- case INDEX_op_qemu_st_a64_i32:
860
- case INDEX_op_qemu_st_a32_i64:
861
- case INDEX_op_qemu_st_a64_i64:
862
+ case INDEX_op_qemu_st_i32:
863
+ case INDEX_op_qemu_st_i64:
864
return C_O0_I2(rZ, r);
865
866
- case INDEX_op_qemu_ld_a32_i128:
867
- case INDEX_op_qemu_ld_a64_i128:
868
+ case INDEX_op_qemu_ld_i128:
869
return C_N2_I1(r, r, r);
870
871
- case INDEX_op_qemu_st_a32_i128:
872
- case INDEX_op_qemu_st_a64_i128:
873
+ case INDEX_op_qemu_st_i128:
874
return C_O0_I3(r, r, r);
875
876
case INDEX_op_brcond_i32:
877
@@ -XXX,XX +XXX,XX @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
878
case INDEX_op_ld32u_i64:
879
case INDEX_op_ld_i32:
880
case INDEX_op_ld_i64:
881
- case INDEX_op_qemu_ld_a32_i32:
882
- case INDEX_op_qemu_ld_a64_i32:
883
- case INDEX_op_qemu_ld_a32_i64:
884
- case INDEX_op_qemu_ld_a64_i64:
885
+ case INDEX_op_qemu_ld_i32:
886
+ case INDEX_op_qemu_ld_i64:
887
return C_O1_I1(r, r);
888
889
case INDEX_op_andc_i32:
890
diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc
891
index XXXXXXX..XXXXXXX 100644
892
--- a/tcg/mips/tcg-target.c.inc
893
+++ b/tcg/mips/tcg-target.c.inc
894
@@ -XXX,XX +XXX,XX @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
895
tcg_out_setcond2(s, args[5], a0, a1, a2, args[3], args[4]);
896
break;
897
898
- case INDEX_op_qemu_ld_a64_i32:
899
- if (TCG_TARGET_REG_BITS == 32) {
900
- tcg_out_qemu_ld(s, a0, 0, a1, a2, args[3], TCG_TYPE_I32);
901
- break;
902
- }
903
- /* fall through */
904
- case INDEX_op_qemu_ld_a32_i32:
905
+ case INDEX_op_qemu_ld_i32:
906
tcg_out_qemu_ld(s, a0, 0, a1, 0, a2, TCG_TYPE_I32);
907
break;
908
- case INDEX_op_qemu_ld_a32_i64:
909
+ case INDEX_op_qemu_ld_i64:
910
if (TCG_TARGET_REG_BITS == 64) {
911
tcg_out_qemu_ld(s, a0, 0, a1, 0, a2, TCG_TYPE_I64);
912
} else {
913
tcg_out_qemu_ld(s, a0, a1, a2, 0, args[3], TCG_TYPE_I64);
914
}
915
break;
916
- case INDEX_op_qemu_ld_a64_i64:
917
- if (TCG_TARGET_REG_BITS == 64) {
918
- tcg_out_qemu_ld(s, a0, 0, a1, 0, a2, TCG_TYPE_I64);
919
- } else {
920
- tcg_out_qemu_ld(s, a0, a1, a2, args[3], args[4], TCG_TYPE_I64);
921
- }
922
- break;
923
924
- case INDEX_op_qemu_st_a64_i32:
925
- if (TCG_TARGET_REG_BITS == 32) {
926
- tcg_out_qemu_st(s, a0, 0, a1, a2, args[3], TCG_TYPE_I32);
927
- break;
928
- }
929
- /* fall through */
930
- case INDEX_op_qemu_st_a32_i32:
931
+ case INDEX_op_qemu_st_i32:
932
tcg_out_qemu_st(s, a0, 0, a1, 0, a2, TCG_TYPE_I32);
933
break;
934
- case INDEX_op_qemu_st_a32_i64:
935
+ case INDEX_op_qemu_st_i64:
936
if (TCG_TARGET_REG_BITS == 64) {
937
tcg_out_qemu_st(s, a0, 0, a1, 0, a2, TCG_TYPE_I64);
938
} else {
939
tcg_out_qemu_st(s, a0, a1, a2, 0, args[3], TCG_TYPE_I64);
940
}
941
break;
942
- case INDEX_op_qemu_st_a64_i64:
943
- if (TCG_TARGET_REG_BITS == 64) {
944
- tcg_out_qemu_st(s, a0, 0, a1, 0, a2, TCG_TYPE_I64);
945
- } else {
946
- tcg_out_qemu_st(s, a0, a1, a2, args[3], args[4], TCG_TYPE_I64);
947
- }
948
- break;
949
950
case INDEX_op_add2_i32:
951
tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5],
952
@@ -XXX,XX +XXX,XX @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
953
case INDEX_op_brcond2_i32:
954
return C_O0_I4(rZ, rZ, rZ, rZ);
955
956
- case INDEX_op_qemu_ld_a32_i32:
957
+ case INDEX_op_qemu_ld_i32:
958
return C_O1_I1(r, r);
959
- case INDEX_op_qemu_ld_a64_i32:
960
- return TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, r) : C_O1_I2(r, r, r);
961
- case INDEX_op_qemu_st_a32_i32:
962
+ case INDEX_op_qemu_st_i32:
963
return C_O0_I2(rZ, r);
964
- case INDEX_op_qemu_st_a64_i32:
965
- return TCG_TARGET_REG_BITS == 64 ? C_O0_I2(rZ, r) : C_O0_I3(rZ, r, r);
966
- case INDEX_op_qemu_ld_a32_i64:
967
+ case INDEX_op_qemu_ld_i64:
968
return TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, r) : C_O2_I1(r, r, r);
969
- case INDEX_op_qemu_ld_a64_i64:
970
- return TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, r) : C_O2_I2(r, r, r, r);
971
- case INDEX_op_qemu_st_a32_i64:
972
+ case INDEX_op_qemu_st_i64:
973
return TCG_TARGET_REG_BITS == 64 ? C_O0_I2(rZ, r) : C_O0_I3(rZ, rZ, r);
974
- case INDEX_op_qemu_st_a64_i64:
975
- return (TCG_TARGET_REG_BITS == 64 ? C_O0_I2(rZ, r)
976
- : C_O0_I4(rZ, rZ, r, r));
977
978
default:
979
return C_NotImplemented;
980
diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc
981
index XXXXXXX..XXXXXXX 100644
982
--- a/tcg/ppc/tcg-target.c.inc
983
+++ b/tcg/ppc/tcg-target.c.inc
984
@@ -XXX,XX +XXX,XX @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
985
tcg_out32(s, MODUD | TAB(args[0], args[1], args[2]));
986
break;
987
988
- case INDEX_op_qemu_ld_a64_i32:
989
- if (TCG_TARGET_REG_BITS == 32) {
990
- tcg_out_qemu_ld(s, args[0], -1, args[1], args[2],
991
- args[3], TCG_TYPE_I32);
992
- break;
993
- }
994
- /* fall through */
995
- case INDEX_op_qemu_ld_a32_i32:
996
+ case INDEX_op_qemu_ld_i32:
997
tcg_out_qemu_ld(s, args[0], -1, args[1], -1, args[2], TCG_TYPE_I32);
998
break;
999
- case INDEX_op_qemu_ld_a32_i64:
1000
+ case INDEX_op_qemu_ld_i64:
1001
if (TCG_TARGET_REG_BITS == 64) {
1002
tcg_out_qemu_ld(s, args[0], -1, args[1], -1,
1003
args[2], TCG_TYPE_I64);
1004
@@ -XXX,XX +XXX,XX @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
1005
args[3], TCG_TYPE_I64);
1006
}
1007
break;
1008
- case INDEX_op_qemu_ld_a64_i64:
1009
- if (TCG_TARGET_REG_BITS == 64) {
1010
- tcg_out_qemu_ld(s, args[0], -1, args[1], -1,
1011
- args[2], TCG_TYPE_I64);
1012
- } else {
1013
- tcg_out_qemu_ld(s, args[0], args[1], args[2], args[3],
1014
- args[4], TCG_TYPE_I64);
1015
- }
1016
- break;
1017
- case INDEX_op_qemu_ld_a32_i128:
1018
- case INDEX_op_qemu_ld_a64_i128:
1019
+ case INDEX_op_qemu_ld_i128:
1020
tcg_debug_assert(TCG_TARGET_REG_BITS == 64);
1021
tcg_out_qemu_ldst_i128(s, args[0], args[1], args[2], args[3], true);
1022
break;
1023
1024
- case INDEX_op_qemu_st_a64_i32:
1025
- if (TCG_TARGET_REG_BITS == 32) {
1026
- tcg_out_qemu_st(s, args[0], -1, args[1], args[2],
1027
- args[3], TCG_TYPE_I32);
1028
- break;
1029
- }
1030
- /* fall through */
1031
- case INDEX_op_qemu_st_a32_i32:
1032
+ case INDEX_op_qemu_st_i32:
1033
tcg_out_qemu_st(s, args[0], -1, args[1], -1, args[2], TCG_TYPE_I32);
1034
break;
1035
- case INDEX_op_qemu_st_a32_i64:
1036
+ case INDEX_op_qemu_st_i64:
1037
if (TCG_TARGET_REG_BITS == 64) {
1038
tcg_out_qemu_st(s, args[0], -1, args[1], -1,
1039
args[2], TCG_TYPE_I64);
1040
@@ -XXX,XX +XXX,XX @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
1041
args[3], TCG_TYPE_I64);
1042
}
1043
break;
1044
- case INDEX_op_qemu_st_a64_i64:
1045
- if (TCG_TARGET_REG_BITS == 64) {
1046
- tcg_out_qemu_st(s, args[0], -1, args[1], -1,
1047
- args[2], TCG_TYPE_I64);
1048
- } else {
1049
- tcg_out_qemu_st(s, args[0], args[1], args[2], args[3],
1050
- args[4], TCG_TYPE_I64);
1051
- }
1052
- break;
1053
- case INDEX_op_qemu_st_a32_i128:
1054
- case INDEX_op_qemu_st_a64_i128:
1055
+ case INDEX_op_qemu_st_i128:
1056
tcg_debug_assert(TCG_TARGET_REG_BITS == 64);
1057
tcg_out_qemu_ldst_i128(s, args[0], args[1], args[2], args[3], false);
1058
break;
1059
@@ -XXX,XX +XXX,XX @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
1060
case INDEX_op_sub2_i32:
1061
return C_O2_I4(r, r, rI, rZM, r, r);
1062
1063
- case INDEX_op_qemu_ld_a32_i32:
1064
+ case INDEX_op_qemu_ld_i32:
1065
return C_O1_I1(r, r);
1066
- case INDEX_op_qemu_ld_a64_i32:
1067
- return TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, r) : C_O1_I2(r, r, r);
1068
- case INDEX_op_qemu_ld_a32_i64:
1069
+ case INDEX_op_qemu_ld_i64:
1070
return TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, r) : C_O2_I1(r, r, r);
1071
- case INDEX_op_qemu_ld_a64_i64:
1072
- return TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, r) : C_O2_I2(r, r, r, r);
1073
1074
- case INDEX_op_qemu_st_a32_i32:
1075
+ case INDEX_op_qemu_st_i32:
1076
return C_O0_I2(r, r);
1077
- case INDEX_op_qemu_st_a64_i32:
1078
+ case INDEX_op_qemu_st_i64:
1079
return TCG_TARGET_REG_BITS == 64 ? C_O0_I2(r, r) : C_O0_I3(r, r, r);
1080
- case INDEX_op_qemu_st_a32_i64:
1081
- return TCG_TARGET_REG_BITS == 64 ? C_O0_I2(r, r) : C_O0_I3(r, r, r);
1082
- case INDEX_op_qemu_st_a64_i64:
1083
- return TCG_TARGET_REG_BITS == 64 ? C_O0_I2(r, r) : C_O0_I4(r, r, r, r);
1084
1085
- case INDEX_op_qemu_ld_a32_i128:
1086
- case INDEX_op_qemu_ld_a64_i128:
1087
+ case INDEX_op_qemu_ld_i128:
1088
return C_N1O1_I1(o, m, r);
1089
- case INDEX_op_qemu_st_a32_i128:
1090
- case INDEX_op_qemu_st_a64_i128:
1091
+ case INDEX_op_qemu_st_i128:
1092
return C_O0_I3(o, m, r);
1093
1094
case INDEX_op_add_vec:
1095
diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
1096
index XXXXXXX..XXXXXXX 100644
1097
--- a/tcg/riscv/tcg-target.c.inc
1098
+++ b/tcg/riscv/tcg-target.c.inc
1099
@@ -XXX,XX +XXX,XX @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
1100
args[3], const_args[3], args[4], const_args[4]);
1101
break;
1102
1103
- case INDEX_op_qemu_ld_a32_i32:
1104
- case INDEX_op_qemu_ld_a64_i32:
1105
+ case INDEX_op_qemu_ld_i32:
1106
tcg_out_qemu_ld(s, a0, a1, a2, TCG_TYPE_I32);
1107
break;
1108
- case INDEX_op_qemu_ld_a32_i64:
1109
- case INDEX_op_qemu_ld_a64_i64:
1110
+ case INDEX_op_qemu_ld_i64:
1111
tcg_out_qemu_ld(s, a0, a1, a2, TCG_TYPE_I64);
1112
break;
1113
- case INDEX_op_qemu_st_a32_i32:
1114
- case INDEX_op_qemu_st_a64_i32:
1115
+ case INDEX_op_qemu_st_i32:
1116
tcg_out_qemu_st(s, a0, a1, a2, TCG_TYPE_I32);
1117
break;
1118
- case INDEX_op_qemu_st_a32_i64:
1119
- case INDEX_op_qemu_st_a64_i64:
1120
+ case INDEX_op_qemu_st_i64:
1121
tcg_out_qemu_st(s, a0, a1, a2, TCG_TYPE_I64);
1122
break;
1123
1124
@@ -XXX,XX +XXX,XX @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
1125
case INDEX_op_sub2_i64:
1126
return C_O2_I4(r, r, rZ, rZ, rM, rM);
1127
1128
- case INDEX_op_qemu_ld_a32_i32:
1129
- case INDEX_op_qemu_ld_a64_i32:
1130
- case INDEX_op_qemu_ld_a32_i64:
1131
- case INDEX_op_qemu_ld_a64_i64:
1132
+ case INDEX_op_qemu_ld_i32:
1133
+ case INDEX_op_qemu_ld_i64:
1134
return C_O1_I1(r, r);
1135
- case INDEX_op_qemu_st_a32_i32:
1136
- case INDEX_op_qemu_st_a64_i32:
1137
- case INDEX_op_qemu_st_a32_i64:
1138
- case INDEX_op_qemu_st_a64_i64:
1139
+ case INDEX_op_qemu_st_i32:
1140
+ case INDEX_op_qemu_st_i64:
1141
return C_O0_I2(rZ, r);
1142
1143
case INDEX_op_st_vec:
1144
diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc
1145
index XXXXXXX..XXXXXXX 100644
1146
--- a/tcg/s390x/tcg-target.c.inc
1147
+++ b/tcg/s390x/tcg-target.c.inc
1148
@@ -XXX,XX +XXX,XX @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
1149
args[2], const_args[2], args[3], const_args[3], args[4]);
1150
break;
1151
1152
- case INDEX_op_qemu_ld_a32_i32:
1153
- case INDEX_op_qemu_ld_a64_i32:
1154
+ case INDEX_op_qemu_ld_i32:
1155
tcg_out_qemu_ld(s, args[0], args[1], args[2], TCG_TYPE_I32);
1156
break;
1157
- case INDEX_op_qemu_ld_a32_i64:
1158
- case INDEX_op_qemu_ld_a64_i64:
1159
+ case INDEX_op_qemu_ld_i64:
1160
tcg_out_qemu_ld(s, args[0], args[1], args[2], TCG_TYPE_I64);
1161
break;
1162
- case INDEX_op_qemu_st_a32_i32:
1163
- case INDEX_op_qemu_st_a64_i32:
1164
+ case INDEX_op_qemu_st_i32:
1165
tcg_out_qemu_st(s, args[0], args[1], args[2], TCG_TYPE_I32);
1166
break;
1167
- case INDEX_op_qemu_st_a32_i64:
1168
- case INDEX_op_qemu_st_a64_i64:
1169
+ case INDEX_op_qemu_st_i64:
1170
tcg_out_qemu_st(s, args[0], args[1], args[2], TCG_TYPE_I64);
1171
break;
1172
- case INDEX_op_qemu_ld_a32_i128:
1173
- case INDEX_op_qemu_ld_a64_i128:
1174
+ case INDEX_op_qemu_ld_i128:
1175
tcg_out_qemu_ldst_i128(s, args[0], args[1], args[2], args[3], true);
1176
break;
1177
- case INDEX_op_qemu_st_a32_i128:
1178
- case INDEX_op_qemu_st_a64_i128:
1179
+ case INDEX_op_qemu_st_i128:
1180
tcg_out_qemu_ldst_i128(s, args[0], args[1], args[2], args[3], false);
1181
break;
1182
1183
@@ -XXX,XX +XXX,XX @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
1184
case INDEX_op_ctpop_i64:
1185
return C_O1_I1(r, r);
1186
1187
- case INDEX_op_qemu_ld_a32_i32:
1188
- case INDEX_op_qemu_ld_a64_i32:
1189
- case INDEX_op_qemu_ld_a32_i64:
1190
- case INDEX_op_qemu_ld_a64_i64:
1191
+ case INDEX_op_qemu_ld_i32:
1192
+ case INDEX_op_qemu_ld_i64:
1193
return C_O1_I1(r, r);
1194
- case INDEX_op_qemu_st_a32_i64:
1195
- case INDEX_op_qemu_st_a64_i64:
1196
- case INDEX_op_qemu_st_a32_i32:
1197
- case INDEX_op_qemu_st_a64_i32:
1198
+ case INDEX_op_qemu_st_i64:
1199
+ case INDEX_op_qemu_st_i32:
1200
return C_O0_I2(r, r);
1201
- case INDEX_op_qemu_ld_a32_i128:
1202
- case INDEX_op_qemu_ld_a64_i128:
1203
+ case INDEX_op_qemu_ld_i128:
1204
return C_O2_I1(o, m, r);
1205
- case INDEX_op_qemu_st_a32_i128:
1206
- case INDEX_op_qemu_st_a64_i128:
1207
+ case INDEX_op_qemu_st_i128:
1208
return C_O0_I3(o, m, r);
1209
1210
case INDEX_op_deposit_i32:
1211
diff --git a/tcg/sparc64/tcg-target.c.inc b/tcg/sparc64/tcg-target.c.inc
1212
index XXXXXXX..XXXXXXX 100644
1213
--- a/tcg/sparc64/tcg-target.c.inc
1214
+++ b/tcg/sparc64/tcg-target.c.inc
1215
@@ -XXX,XX +XXX,XX @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
1216
tcg_out_arithi(s, a1, a0, 32, SHIFT_SRLX);
1217
break;
1218
1219
- case INDEX_op_qemu_ld_a32_i32:
1220
- case INDEX_op_qemu_ld_a64_i32:
1221
+ case INDEX_op_qemu_ld_i32:
1222
tcg_out_qemu_ld(s, a0, a1, a2, TCG_TYPE_I32);
1223
break;
1224
- case INDEX_op_qemu_ld_a32_i64:
1225
- case INDEX_op_qemu_ld_a64_i64:
1226
+ case INDEX_op_qemu_ld_i64:
1227
tcg_out_qemu_ld(s, a0, a1, a2, TCG_TYPE_I64);
1228
break;
1229
- case INDEX_op_qemu_st_a32_i32:
1230
- case INDEX_op_qemu_st_a64_i32:
1231
+ case INDEX_op_qemu_st_i32:
1232
tcg_out_qemu_st(s, a0, a1, a2, TCG_TYPE_I32);
1233
break;
1234
- case INDEX_op_qemu_st_a32_i64:
1235
- case INDEX_op_qemu_st_a64_i64:
1236
+ case INDEX_op_qemu_st_i64:
1237
tcg_out_qemu_st(s, a0, a1, a2, TCG_TYPE_I64);
1238
break;
1239
1240
@@ -XXX,XX +XXX,XX @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
1241
case INDEX_op_extu_i32_i64:
1242
case INDEX_op_extract_i64:
1243
case INDEX_op_sextract_i64:
1244
- case INDEX_op_qemu_ld_a32_i32:
1245
- case INDEX_op_qemu_ld_a64_i32:
1246
- case INDEX_op_qemu_ld_a32_i64:
1247
- case INDEX_op_qemu_ld_a64_i64:
1248
+ case INDEX_op_qemu_ld_i32:
1249
+ case INDEX_op_qemu_ld_i64:
1250
return C_O1_I1(r, r);
1251
1252
case INDEX_op_st8_i32:
1253
@@ -XXX,XX +XXX,XX @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
1254
case INDEX_op_st_i32:
1255
case INDEX_op_st32_i64:
1256
case INDEX_op_st_i64:
1257
- case INDEX_op_qemu_st_a32_i32:
1258
- case INDEX_op_qemu_st_a64_i32:
1259
- case INDEX_op_qemu_st_a32_i64:
1260
- case INDEX_op_qemu_st_a64_i64:
1261
+ case INDEX_op_qemu_st_i32:
1262
+ case INDEX_op_qemu_st_i64:
1263
return C_O0_I2(rZ, r);
1264
1265
case INDEX_op_add_i32:
39
diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
1266
diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
40
index XXXXXXX..XXXXXXX 100644
1267
index XXXXXXX..XXXXXXX 100644
41
--- a/tcg/tci/tcg-target.c.inc
1268
--- a/tcg/tci/tcg-target.c.inc
42
+++ b/tcg/tci/tcg-target.c.inc
1269
+++ b/tcg/tci/tcg-target.c.inc
43
@@ -XXX,XX +XXX,XX @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
1270
@@ -XXX,XX +XXX,XX @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
44
return true;
1271
case INDEX_op_setcond2_i32:
1272
return C_O1_I4(r, r, r, r, r);
1273
1274
- case INDEX_op_qemu_ld_a32_i32:
1275
+ case INDEX_op_qemu_ld_i32:
1276
return C_O1_I1(r, r);
1277
- case INDEX_op_qemu_ld_a64_i32:
1278
- return TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, r) : C_O1_I2(r, r, r);
1279
- case INDEX_op_qemu_ld_a32_i64:
1280
+ case INDEX_op_qemu_ld_i64:
1281
return TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, r) : C_O2_I1(r, r, r);
1282
- case INDEX_op_qemu_ld_a64_i64:
1283
- return TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, r) : C_O2_I2(r, r, r, r);
1284
- case INDEX_op_qemu_st_a32_i32:
1285
+ case INDEX_op_qemu_st_i32:
1286
return C_O0_I2(r, r);
1287
- case INDEX_op_qemu_st_a64_i32:
1288
+ case INDEX_op_qemu_st_i64:
1289
return TCG_TARGET_REG_BITS == 64 ? C_O0_I2(r, r) : C_O0_I3(r, r, r);
1290
- case INDEX_op_qemu_st_a32_i64:
1291
- return TCG_TARGET_REG_BITS == 64 ? C_O0_I2(r, r) : C_O0_I3(r, r, r);
1292
- case INDEX_op_qemu_st_a64_i64:
1293
- return TCG_TARGET_REG_BITS == 64 ? C_O0_I2(r, r) : C_O0_I4(r, r, r, r);
1294
1295
default:
1296
return C_NotImplemented;
1297
@@ -XXX,XX +XXX,XX @@ static void tcg_out_op_rrrbb(TCGContext *s, TCGOpcode op, TCGReg r0,
1298
tcg_out32(s, insn);
45
}
1299
}
46
1300
47
-/* Parse target specific constraints. */
1301
-static void tcg_out_op_rrrrr(TCGContext *s, TCGOpcode op, TCGReg r0,
48
-static const char *target_parse_constraint(TCGArgConstraint *ct,
1302
- TCGReg r1, TCGReg r2, TCGReg r3, TCGReg r4)
49
- const char *ct_str, TCGType type)
50
-{
1303
-{
51
- switch (*ct_str++) {
1304
- tcg_insn_unit insn = 0;
52
- case 'r':
1305
-
53
- ct->regs = BIT(TCG_TARGET_NB_REGS) - 1;
1306
- insn = deposit32(insn, 0, 8, op);
54
- break;
1307
- insn = deposit32(insn, 8, 4, r0);
55
- default:
1308
- insn = deposit32(insn, 12, 4, r1);
56
- return NULL;
1309
- insn = deposit32(insn, 16, 4, r2);
57
- }
1310
- insn = deposit32(insn, 20, 4, r3);
58
- return ct_str;
1311
- insn = deposit32(insn, 24, 4, r4);
1312
- tcg_out32(s, insn);
59
-}
1313
-}
60
-
1314
-
61
#if defined(CONFIG_DEBUG_TCG_INTERPRETER)
1315
static void tcg_out_op_rrrr(TCGContext *s, TCGOpcode op,
62
/* Show current bytecode. Used by tcg interpreter. */
1316
TCGReg r0, TCGReg r1, TCGReg r2, TCGReg r3)
63
void tci_disas(uint8_t opc)
1317
{
1318
@@ -XXX,XX +XXX,XX @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
1319
tcg_out_op_rrrr(s, opc, args[0], args[1], args[2], args[3]);
1320
break;
1321
1322
- case INDEX_op_qemu_ld_a32_i32:
1323
- case INDEX_op_qemu_st_a32_i32:
1324
- tcg_out_op_rrm(s, opc, args[0], args[1], args[2]);
1325
- break;
1326
- case INDEX_op_qemu_ld_a64_i32:
1327
- case INDEX_op_qemu_st_a64_i32:
1328
- case INDEX_op_qemu_ld_a32_i64:
1329
- case INDEX_op_qemu_st_a32_i64:
1330
- if (TCG_TARGET_REG_BITS == 64) {
1331
- tcg_out_op_rrm(s, opc, args[0], args[1], args[2]);
1332
- } else {
1333
+ case INDEX_op_qemu_ld_i64:
1334
+ case INDEX_op_qemu_st_i64:
1335
+ if (TCG_TARGET_REG_BITS == 32) {
1336
tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_TMP, args[3]);
1337
tcg_out_op_rrrr(s, opc, args[0], args[1], args[2], TCG_REG_TMP);
1338
+ break;
1339
}
1340
- break;
1341
- case INDEX_op_qemu_ld_a64_i64:
1342
- case INDEX_op_qemu_st_a64_i64:
1343
- if (TCG_TARGET_REG_BITS == 64) {
1344
- tcg_out_op_rrm(s, opc, args[0], args[1], args[2]);
1345
+ /* fall through */
1346
+ case INDEX_op_qemu_ld_i32:
1347
+ case INDEX_op_qemu_st_i32:
1348
+ if (TCG_TARGET_REG_BITS == 64 && s->addr_type == TCG_TYPE_I32) {
1349
+ tcg_out_ext32u(s, TCG_REG_TMP, args[1]);
1350
+ tcg_out_op_rrm(s, opc, args[0], TCG_REG_TMP, args[2]);
1351
} else {
1352
- tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_TMP, args[4]);
1353
- tcg_out_op_rrrrr(s, opc, args[0], args[1],
1354
- args[2], args[3], TCG_REG_TMP);
1355
+ tcg_out_op_rrm(s, opc, args[0], args[1], args[2]);
1356
}
1357
break;
1358
64
--
1359
--
65
2.25.1
1360
2.43.0
66
67
diff view generated by jsdifflib
[PULL 17/24] tcg/arm: Split out constraint sets to tcg-target-con-set.h
[PULL 05/24] tcg/arm: Drop addrhi from prepare_host_addr
1
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
1
The guest address will now always be TCG_TYPE_I32.
2
2
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
3
---
4
---
4
tcg/arm/tcg-target-con-set.h | 35 ++++++++++++++
5
tcg/arm/tcg-target.c.inc | 63 ++++++++++++++--------------------------
5
tcg/arm/tcg-target.h | 1 +
6
1 file changed, 21 insertions(+), 42 deletions(-)
6
tcg/arm/tcg-target.c.inc | 94 ++++++++++++------------------------
7
3 files changed, 68 insertions(+), 62 deletions(-)
8
create mode 100644 tcg/arm/tcg-target-con-set.h
9
7
10
diff --git a/tcg/arm/tcg-target-con-set.h b/tcg/arm/tcg-target-con-set.h
11
new file mode 100644
12
index XXXXXXX..XXXXXXX
13
--- /dev/null
14
+++ b/tcg/arm/tcg-target-con-set.h
15
@@ -XXX,XX +XXX,XX @@
16
+/* SPDX-License-Identifier: MIT */
17
+/*
18
+ * Define Arm target-specific constraint sets.
19
+ * Copyright (c) 2021 Linaro
20
+ */
21
+
22
+/*
23
+ * C_On_Im(...) defines a constraint set with <n> outputs and <m> inputs.
24
+ * Each operand should be a sequence of constraint letters as defined by
25
+ * tcg-target-con-str.h; the constraint combination is inclusive or.
26
+ */
27
+C_O0_I1(r)
28
+C_O0_I2(r, r)
29
+C_O0_I2(r, rIN)
30
+C_O0_I2(s, s)
31
+C_O0_I3(s, s, s)
32
+C_O0_I4(r, r, rI, rI)
33
+C_O0_I4(s, s, s, s)
34
+C_O1_I1(r, l)
35
+C_O1_I1(r, r)
36
+C_O1_I2(r, 0, rZ)
37
+C_O1_I2(r, l, l)
38
+C_O1_I2(r, r, r)
39
+C_O1_I2(r, r, rI)
40
+C_O1_I2(r, r, rIK)
41
+C_O1_I2(r, r, rIN)
42
+C_O1_I2(r, r, ri)
43
+C_O1_I2(r, rZ, rZ)
44
+C_O1_I4(r, r, r, rI, rI)
45
+C_O1_I4(r, r, rIN, rIK, 0)
46
+C_O2_I1(r, r, l)
47
+C_O2_I2(r, r, l, l)
48
+C_O2_I2(r, r, r, r)
49
+C_O2_I4(r, r, r, r, rIN, rIK)
50
+C_O2_I4(r, r, rI, rI, rIN, rIK)
51
diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
52
index XXXXXXX..XXXXXXX 100644
53
--- a/tcg/arm/tcg-target.h
54
+++ b/tcg/arm/tcg-target.h
55
@@ -XXX,XX +XXX,XX @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t);
56
#define TCG_TARGET_NEED_LDST_LABELS
57
#endif
58
#define TCG_TARGET_NEED_POOL_LABELS
59
+#define TCG_TARGET_CON_SET_H
60
61
#endif
62
diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
8
diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
63
index XXXXXXX..XXXXXXX 100644
9
index XXXXXXX..XXXXXXX 100644
64
--- a/tcg/arm/tcg-target.c.inc
10
--- a/tcg/arm/tcg-target.c.inc
65
+++ b/tcg/arm/tcg-target.c.inc
11
+++ b/tcg/arm/tcg-target.c.inc
66
@@ -XXX,XX +XXX,XX @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
12
@@ -XXX,XX +XXX,XX @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
13
#define MIN_TLB_MASK_TABLE_OFS -256
14
15
static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
16
- TCGReg addrlo, TCGReg addrhi,
17
- MemOpIdx oi, bool is_ld)
18
+ TCGReg addr, MemOpIdx oi, bool is_ld)
19
{
20
TCGLabelQemuLdst *ldst = NULL;
21
MemOp opc = get_memop(oi);
22
@@ -XXX,XX +XXX,XX @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
23
if (tcg_use_softmmu) {
24
*h = (HostAddress){
25
.cond = COND_AL,
26
- .base = addrlo,
27
+ .base = addr,
28
.index = TCG_REG_R1,
29
.index_scratch = true,
30
};
31
} else {
32
*h = (HostAddress){
33
.cond = COND_AL,
34
- .base = addrlo,
35
+ .base = addr,
36
.index = guest_base ? TCG_REG_GUEST_BASE : -1,
37
.index_scratch = false,
38
};
39
@@ -XXX,XX +XXX,XX @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
40
ldst = new_ldst_label(s);
41
ldst->is_ld = is_ld;
42
ldst->oi = oi;
43
- ldst->addrlo_reg = addrlo;
44
- ldst->addrhi_reg = addrhi;
45
+ ldst->addrlo_reg = addr;
46
47
/* Load cpu->neg.tlb.f[mmu_idx].{mask,table} into {r0,r1}. */
48
QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, mask) != 0);
49
@@ -XXX,XX +XXX,XX @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
50
tcg_out_ldrd_8(s, COND_AL, TCG_REG_R0, TCG_AREG0, fast_off);
51
52
/* Extract the tlb index from the address into R0. */
53
- tcg_out_dat_reg(s, COND_AL, ARITH_AND, TCG_REG_R0, TCG_REG_R0, addrlo,
54
+ tcg_out_dat_reg(s, COND_AL, ARITH_AND, TCG_REG_R0, TCG_REG_R0, addr,
55
SHIFT_IMM_LSR(s->page_bits - CPU_TLB_ENTRY_BITS));
56
57
/*
58
* Add the tlb_table pointer, creating the CPUTLBEntry address in R1.
59
- * Load the tlb comparator into R2/R3 and the fast path addend into R1.
60
+ * Load the tlb comparator into R2 and the fast path addend into R1.
61
*/
62
QEMU_BUILD_BUG_ON(HOST_BIG_ENDIAN);
63
if (cmp_off == 0) {
64
- if (s->addr_type == TCG_TYPE_I32) {
65
- tcg_out_ld32_rwb(s, COND_AL, TCG_REG_R2,
66
- TCG_REG_R1, TCG_REG_R0);
67
- } else {
68
- tcg_out_ldrd_rwb(s, COND_AL, TCG_REG_R2,
69
- TCG_REG_R1, TCG_REG_R0);
70
- }
71
+ tcg_out_ld32_rwb(s, COND_AL, TCG_REG_R2, TCG_REG_R1, TCG_REG_R0);
72
} else {
73
tcg_out_dat_reg(s, COND_AL, ARITH_ADD,
74
TCG_REG_R1, TCG_REG_R1, TCG_REG_R0, 0);
75
- if (s->addr_type == TCG_TYPE_I32) {
76
- tcg_out_ld32_12(s, COND_AL, TCG_REG_R2, TCG_REG_R1, cmp_off);
77
- } else {
78
- tcg_out_ldrd_8(s, COND_AL, TCG_REG_R2, TCG_REG_R1, cmp_off);
79
- }
80
+ tcg_out_ld32_12(s, COND_AL, TCG_REG_R2, TCG_REG_R1, cmp_off);
81
}
82
83
/* Load the tlb addend. */
84
@@ -XXX,XX +XXX,XX @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
85
* This leaves the least significant alignment bits unchanged, and of
86
* course must be zero.
87
*/
88
- t_addr = addrlo;
89
+ t_addr = addr;
90
if (a_mask < s_mask) {
91
t_addr = TCG_REG_R0;
92
tcg_out_dat_imm(s, COND_AL, ARITH_ADD, t_addr,
93
- addrlo, s_mask - a_mask);
94
+ addr, s_mask - a_mask);
95
}
96
if (use_armv7_instructions && s->page_bits <= 16) {
97
tcg_out_movi32(s, COND_AL, TCG_REG_TMP, ~(s->page_mask | a_mask));
98
@@ -XXX,XX +XXX,XX @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
99
} else {
100
if (a_mask) {
101
tcg_debug_assert(a_mask <= 0xff);
102
- tcg_out_dat_imm(s, COND_AL, ARITH_TST, 0, addrlo, a_mask);
103
+ tcg_out_dat_imm(s, COND_AL, ARITH_TST, 0, addr, a_mask);
104
}
105
tcg_out_dat_reg(s, COND_AL, ARITH_MOV, TCG_REG_TMP, 0, t_addr,
106
SHIFT_IMM_LSR(s->page_bits));
107
@@ -XXX,XX +XXX,XX @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
108
0, TCG_REG_R2, TCG_REG_TMP,
109
SHIFT_IMM_LSL(s->page_bits));
110
}
111
-
112
- if (s->addr_type != TCG_TYPE_I32) {
113
- tcg_out_dat_reg(s, COND_EQ, ARITH_CMP, 0, TCG_REG_R3, addrhi, 0);
114
- }
115
} else if (a_mask) {
116
ldst = new_ldst_label(s);
117
ldst->is_ld = is_ld;
118
ldst->oi = oi;
119
- ldst->addrlo_reg = addrlo;
120
- ldst->addrhi_reg = addrhi;
121
+ ldst->addrlo_reg = addr;
122
123
/* We are expecting alignment to max out at 7 */
124
tcg_debug_assert(a_mask <= 0xff);
125
/* tst addr, #mask */
126
- tcg_out_dat_imm(s, COND_AL, ARITH_TST, 0, addrlo, a_mask);
127
+ tcg_out_dat_imm(s, COND_AL, ARITH_TST, 0, addr, a_mask);
67
}
128
}
129
130
return ldst;
131
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_ld_direct(TCGContext *s, MemOp opc, TCGReg datalo,
68
}
132
}
69
133
70
-static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
134
static void tcg_out_qemu_ld(TCGContext *s, TCGReg datalo, TCGReg datahi,
71
+static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
135
- TCGReg addrlo, TCGReg addrhi,
136
- MemOpIdx oi, TCGType data_type)
137
+ TCGReg addr, MemOpIdx oi, TCGType data_type)
72
{
138
{
73
- static const TCGTargetOpDef r = { .args_ct_str = { "r" } };
139
MemOp opc = get_memop(oi);
74
- static const TCGTargetOpDef r_r = { .args_ct_str = { "r", "r" } };
140
TCGLabelQemuLdst *ldst;
75
- static const TCGTargetOpDef s_s = { .args_ct_str = { "s", "s" } };
141
HostAddress h;
76
- static const TCGTargetOpDef r_l = { .args_ct_str = { "r", "l" } };
142
77
- static const TCGTargetOpDef r_r_r = { .args_ct_str = { "r", "r", "r" } };
143
- ldst = prepare_host_addr(s, &h, addrlo, addrhi, oi, true);
78
- static const TCGTargetOpDef r_r_l = { .args_ct_str = { "r", "r", "l" } };
144
+ ldst = prepare_host_addr(s, &h, addr, oi, true);
79
- static const TCGTargetOpDef r_l_l = { .args_ct_str = { "r", "l", "l" } };
145
if (ldst) {
80
- static const TCGTargetOpDef s_s_s = { .args_ct_str = { "s", "s", "s" } };
146
ldst->type = data_type;
81
- static const TCGTargetOpDef r_r_ri = { .args_ct_str = { "r", "r", "ri" } };
147
ldst->datalo_reg = datalo;
82
- static const TCGTargetOpDef r_r_rI = { .args_ct_str = { "r", "r", "rI" } };
148
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_st_direct(TCGContext *s, MemOp opc, TCGReg datalo,
83
- static const TCGTargetOpDef r_r_rIN
149
}
84
- = { .args_ct_str = { "r", "r", "rIN" } };
150
85
- static const TCGTargetOpDef r_r_rIK
151
static void tcg_out_qemu_st(TCGContext *s, TCGReg datalo, TCGReg datahi,
86
- = { .args_ct_str = { "r", "r", "rIK" } };
152
- TCGReg addrlo, TCGReg addrhi,
87
- static const TCGTargetOpDef r_r_r_r
153
- MemOpIdx oi, TCGType data_type)
88
- = { .args_ct_str = { "r", "r", "r", "r" } };
154
+ TCGReg addr, MemOpIdx oi, TCGType data_type)
89
- static const TCGTargetOpDef r_r_l_l
155
{
90
- = { .args_ct_str = { "r", "r", "l", "l" } };
156
MemOp opc = get_memop(oi);
91
- static const TCGTargetOpDef s_s_s_s
157
TCGLabelQemuLdst *ldst;
92
- = { .args_ct_str = { "s", "s", "s", "s" } };
158
HostAddress h;
93
- static const TCGTargetOpDef br
159
94
- = { .args_ct_str = { "r", "rIN" } };
160
- ldst = prepare_host_addr(s, &h, addrlo, addrhi, oi, false);
95
- static const TCGTargetOpDef ext2
161
+ ldst = prepare_host_addr(s, &h, addr, oi, false);
96
- = { .args_ct_str = { "r", "rZ", "rZ" } };
162
if (ldst) {
97
- static const TCGTargetOpDef dep
163
ldst->type = data_type;
98
- = { .args_ct_str = { "r", "0", "rZ" } };
164
ldst->datalo_reg = datalo;
99
- static const TCGTargetOpDef movc
165
@@ -XXX,XX +XXX,XX @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
100
- = { .args_ct_str = { "r", "r", "rIN", "rIK", "0" } };
166
break;
101
- static const TCGTargetOpDef add2
167
102
- = { .args_ct_str = { "r", "r", "r", "r", "rIN", "rIK" } };
168
case INDEX_op_qemu_ld_i32:
103
- static const TCGTargetOpDef sub2
169
- tcg_out_qemu_ld(s, args[0], -1, args[1], -1, args[2], TCG_TYPE_I32);
104
- = { .args_ct_str = { "r", "r", "rI", "rI", "rIN", "rIK" } };
170
+ tcg_out_qemu_ld(s, args[0], -1, args[1], args[2], TCG_TYPE_I32);
105
- static const TCGTargetOpDef br2
171
break;
106
- = { .args_ct_str = { "r", "r", "rI", "rI" } };
172
case INDEX_op_qemu_ld_i64:
107
- static const TCGTargetOpDef setc2
173
- tcg_out_qemu_ld(s, args[0], args[1], args[2], -1,
108
- = { .args_ct_str = { "r", "r", "r", "rI", "rI" } };
174
- args[3], TCG_TYPE_I64);
109
-
175
+ tcg_out_qemu_ld(s, args[0], args[1], args[2], args[3], TCG_TYPE_I64);
110
switch (op) {
176
break;
111
case INDEX_op_goto_ptr:
177
112
- return &r;
178
case INDEX_op_qemu_st_i32:
113
+ return C_O0_I1(r);
179
- tcg_out_qemu_st(s, args[0], -1, args[1], -1, args[2], TCG_TYPE_I32);
114
180
+ tcg_out_qemu_st(s, args[0], -1, args[1], args[2], TCG_TYPE_I32);
115
case INDEX_op_ld8u_i32:
181
break;
116
case INDEX_op_ld8s_i32:
182
case INDEX_op_qemu_st_i64:
117
case INDEX_op_ld16u_i32:
183
- tcg_out_qemu_st(s, args[0], args[1], args[2], -1,
118
case INDEX_op_ld16s_i32:
184
- args[3], TCG_TYPE_I64);
119
case INDEX_op_ld_i32:
185
+ tcg_out_qemu_st(s, args[0], args[1], args[2], args[3], TCG_TYPE_I64);
120
- case INDEX_op_st8_i32:
186
break;
121
- case INDEX_op_st16_i32:
187
122
- case INDEX_op_st_i32:
123
case INDEX_op_neg_i32:
124
case INDEX_op_not_i32:
125
case INDEX_op_bswap16_i32:
188
case INDEX_op_bswap16_i32:
126
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
127
case INDEX_op_ext16u_i32:
128
case INDEX_op_extract_i32:
129
case INDEX_op_sextract_i32:
130
- return &r_r;
131
+ return C_O1_I1(r, r);
132
+
133
+ case INDEX_op_st8_i32:
134
+ case INDEX_op_st16_i32:
135
+ case INDEX_op_st_i32:
136
+ return C_O0_I2(r, r);
137
138
case INDEX_op_add_i32:
139
case INDEX_op_sub_i32:
140
case INDEX_op_setcond_i32:
141
- return &r_r_rIN;
142
+ return C_O1_I2(r, r, rIN);
143
+
144
case INDEX_op_and_i32:
145
case INDEX_op_andc_i32:
146
case INDEX_op_clz_i32:
147
case INDEX_op_ctz_i32:
148
- return &r_r_rIK;
149
+ return C_O1_I2(r, r, rIK);
150
+
151
case INDEX_op_mul_i32:
152
case INDEX_op_div_i32:
153
case INDEX_op_divu_i32:
154
- return &r_r_r;
155
+ return C_O1_I2(r, r, r);
156
+
157
case INDEX_op_mulu2_i32:
158
case INDEX_op_muls2_i32:
159
- return &r_r_r_r;
160
+ return C_O2_I2(r, r, r, r);
161
+
162
case INDEX_op_or_i32:
163
case INDEX_op_xor_i32:
164
- return &r_r_rI;
165
+ return C_O1_I2(r, r, rI);
166
+
167
case INDEX_op_shl_i32:
168
case INDEX_op_shr_i32:
169
case INDEX_op_sar_i32:
170
case INDEX_op_rotl_i32:
171
case INDEX_op_rotr_i32:
172
- return &r_r_ri;
173
+ return C_O1_I2(r, r, ri);
174
175
case INDEX_op_brcond_i32:
176
- return &br;
177
+ return C_O0_I2(r, rIN);
178
case INDEX_op_deposit_i32:
179
- return &dep;
180
+ return C_O1_I2(r, 0, rZ);
181
case INDEX_op_extract2_i32:
182
- return &ext2;
183
+ return C_O1_I2(r, rZ, rZ);
184
case INDEX_op_movcond_i32:
185
- return &movc;
186
+ return C_O1_I4(r, r, rIN, rIK, 0);
187
case INDEX_op_add2_i32:
188
- return &add2;
189
+ return C_O2_I4(r, r, r, r, rIN, rIK);
190
case INDEX_op_sub2_i32:
191
- return &sub2;
192
+ return C_O2_I4(r, r, rI, rI, rIN, rIK);
193
case INDEX_op_brcond2_i32:
194
- return &br2;
195
+ return C_O0_I4(r, r, rI, rI);
196
case INDEX_op_setcond2_i32:
197
- return &setc2;
198
+ return C_O1_I4(r, r, r, rI, rI);
199
200
case INDEX_op_qemu_ld_i32:
201
- return TARGET_LONG_BITS == 32 ? &r_l : &r_l_l;
202
+ return TARGET_LONG_BITS == 32 ? C_O1_I1(r, l) : C_O1_I2(r, l, l);
203
case INDEX_op_qemu_ld_i64:
204
- return TARGET_LONG_BITS == 32 ? &r_r_l : &r_r_l_l;
205
+ return TARGET_LONG_BITS == 32 ? C_O2_I1(r, r, l) : C_O2_I2(r, r, l, l);
206
case INDEX_op_qemu_st_i32:
207
- return TARGET_LONG_BITS == 32 ? &s_s : &s_s_s;
208
+ return TARGET_LONG_BITS == 32 ? C_O0_I2(s, s) : C_O0_I3(s, s, s);
209
case INDEX_op_qemu_st_i64:
210
- return TARGET_LONG_BITS == 32 ? &s_s_s : &s_s_s_s;
211
+ return TARGET_LONG_BITS == 32 ? C_O0_I3(s, s, s) : C_O0_I4(s, s, s, s);
212
213
default:
214
- return NULL;
215
+ g_assert_not_reached();
216
}
217
}
218
219
--
189
--
220
2.25.1
190
2.43.0
221
222
diff view generated by jsdifflib
[PULL 03/24] tcg/i386: Move constraint type check to tcg_target_const_match
[PULL 06/24] tcg/i386: Drop addrhi from prepare_host_addr
1
Rather than check the type when filling in the constraint,
1
The guest address will now always fit in one register.
2
check it when matching the constant. This removes the only
3
use of the type argument to target_parse_constraint.
4
2
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
3
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
---
5
---
8
tcg/i386/tcg-target.c.inc | 28 +++++++++++++++++-----------
6
tcg/i386/tcg-target.c.inc | 56 ++++++++++++++-------------------------
9
1 file changed, 17 insertions(+), 11 deletions(-)
7
1 file changed, 20 insertions(+), 36 deletions(-)
10
8
11
diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
9
diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
12
index XXXXXXX..XXXXXXX 100644
10
index XXXXXXX..XXXXXXX 100644
13
--- a/tcg/i386/tcg-target.c.inc
11
--- a/tcg/i386/tcg-target.c.inc
14
+++ b/tcg/i386/tcg-target.c.inc
12
+++ b/tcg/i386/tcg-target.c.inc
15
@@ -XXX,XX +XXX,XX @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
13
@@ -XXX,XX +XXX,XX @@ static inline int setup_guest_base_seg(void)
14
* is required and fill in @h with the host address for the fast path.
15
*/
16
static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
17
- TCGReg addrlo, TCGReg addrhi,
18
- MemOpIdx oi, bool is_ld)
19
+ TCGReg addr, MemOpIdx oi, bool is_ld)
20
{
21
TCGLabelQemuLdst *ldst = NULL;
22
MemOp opc = get_memop(oi);
23
@@ -XXX,XX +XXX,XX @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
24
} else {
25
*h = x86_guest_base;
26
}
27
- h->base = addrlo;
28
+ h->base = addr;
29
h->aa = atom_and_align_for_opc(s, opc, MO_ATOM_IFALIGN, s_bits == MO_128);
30
a_mask = (1 << h->aa.align) - 1;
31
32
@@ -XXX,XX +XXX,XX @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
33
ldst = new_ldst_label(s);
34
ldst->is_ld = is_ld;
35
ldst->oi = oi;
36
- ldst->addrlo_reg = addrlo;
37
- ldst->addrhi_reg = addrhi;
38
+ ldst->addrlo_reg = addr;
39
40
if (TCG_TARGET_REG_BITS == 64) {
41
ttype = s->addr_type;
42
@@ -XXX,XX +XXX,XX @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
43
}
44
}
45
46
- tcg_out_mov(s, tlbtype, TCG_REG_L0, addrlo);
47
+ tcg_out_mov(s, tlbtype, TCG_REG_L0, addr);
48
tcg_out_shifti(s, SHIFT_SHR + tlbrexw, TCG_REG_L0,
49
s->page_bits - CPU_TLB_ENTRY_BITS);
50
51
@@ -XXX,XX +XXX,XX @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
52
* check that we don't cross pages for the complete access.
53
*/
54
if (a_mask >= s_mask) {
55
- tcg_out_mov(s, ttype, TCG_REG_L1, addrlo);
56
+ tcg_out_mov(s, ttype, TCG_REG_L1, addr);
57
} else {
58
tcg_out_modrm_offset(s, OPC_LEA + trexw, TCG_REG_L1,
59
- addrlo, s_mask - a_mask);
60
+ addr, s_mask - a_mask);
61
}
62
tlb_mask = s->page_mask | a_mask;
63
tgen_arithi(s, ARITH_AND + trexw, TCG_REG_L1, tlb_mask, 0);
64
@@ -XXX,XX +XXX,XX @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
65
ldst->label_ptr[0] = s->code_ptr;
66
s->code_ptr += 4;
67
68
- if (TCG_TARGET_REG_BITS == 32 && s->addr_type == TCG_TYPE_I64) {
69
- /* cmp 4(TCG_REG_L0), addrhi */
70
- tcg_out_modrm_offset(s, OPC_CMP_GvEv, addrhi,
71
- TCG_REG_L0, cmp_ofs + 4);
72
-
73
- /* jne slow_path */
74
- tcg_out_opc(s, OPC_JCC_long + JCC_JNE, 0, 0, 0);
75
- ldst->label_ptr[1] = s->code_ptr;
76
- s->code_ptr += 4;
77
- }
78
-
79
/* TLB Hit. */
80
tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_L0, TCG_REG_L0,
81
offsetof(CPUTLBEntry, addend));
82
@@ -XXX,XX +XXX,XX @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
83
ldst = new_ldst_label(s);
84
ldst->is_ld = is_ld;
85
ldst->oi = oi;
86
- ldst->addrlo_reg = addrlo;
87
- ldst->addrhi_reg = addrhi;
88
+ ldst->addrlo_reg = addr;
89
90
/* jne slow_path */
91
- jcc = tcg_out_cmp(s, TCG_COND_TSTNE, addrlo, a_mask, true, false);
92
+ jcc = tcg_out_cmp(s, TCG_COND_TSTNE, addr, a_mask, true, false);
93
tcg_out_opc(s, OPC_JCC_long + jcc, 0, 0, 0);
94
ldst->label_ptr[0] = s->code_ptr;
95
s->code_ptr += 4;
96
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg datalo, TCGReg datahi,
97
}
98
99
static void tcg_out_qemu_ld(TCGContext *s, TCGReg datalo, TCGReg datahi,
100
- TCGReg addrlo, TCGReg addrhi,
101
- MemOpIdx oi, TCGType data_type)
102
+ TCGReg addr, MemOpIdx oi, TCGType data_type)
103
{
104
TCGLabelQemuLdst *ldst;
105
HostAddress h;
106
107
- ldst = prepare_host_addr(s, &h, addrlo, addrhi, oi, true);
108
+ ldst = prepare_host_addr(s, &h, addr, oi, true);
109
tcg_out_qemu_ld_direct(s, datalo, datahi, h, data_type, get_memop(oi));
110
111
if (ldst) {
112
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg datalo, TCGReg datahi,
113
}
114
115
static void tcg_out_qemu_st(TCGContext *s, TCGReg datalo, TCGReg datahi,
116
- TCGReg addrlo, TCGReg addrhi,
117
- MemOpIdx oi, TCGType data_type)
118
+ TCGReg addr, MemOpIdx oi, TCGType data_type)
119
{
120
TCGLabelQemuLdst *ldst;
121
HostAddress h;
122
123
- ldst = prepare_host_addr(s, &h, addrlo, addrhi, oi, false);
124
+ ldst = prepare_host_addr(s, &h, addr, oi, false);
125
tcg_out_qemu_st_direct(s, datalo, datahi, h, get_memop(oi));
126
127
if (ldst) {
128
@@ -XXX,XX +XXX,XX @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
16
break;
129
break;
17
130
18
case 'e':
131
case INDEX_op_qemu_ld_i32:
19
- ct->ct |= (type == TCG_TYPE_I32 ? TCG_CT_CONST : TCG_CT_CONST_S32);
132
- tcg_out_qemu_ld(s, a0, -1, a1, -1, a2, TCG_TYPE_I32);
20
+ ct->ct |= TCG_CT_CONST_S32;
133
+ tcg_out_qemu_ld(s, a0, -1, a1, a2, TCG_TYPE_I32);
21
break;
134
break;
22
case 'Z':
135
case INDEX_op_qemu_ld_i64:
23
- ct->ct |= (type == TCG_TYPE_I32 ? TCG_CT_CONST : TCG_CT_CONST_U32);
136
if (TCG_TARGET_REG_BITS == 64) {
24
+ ct->ct |= TCG_CT_CONST_U32;
137
- tcg_out_qemu_ld(s, a0, -1, a1, -1, a2, TCG_TYPE_I64);
138
+ tcg_out_qemu_ld(s, a0, -1, a1, a2, TCG_TYPE_I64);
139
} else {
140
- tcg_out_qemu_ld(s, a0, a1, a2, -1, args[3], TCG_TYPE_I64);
141
+ tcg_out_qemu_ld(s, a0, a1, a2, args[3], TCG_TYPE_I64);
142
}
25
break;
143
break;
26
case 'I':
144
case INDEX_op_qemu_ld_i128:
27
- ct->ct |= (type == TCG_TYPE_I32 ? TCG_CT_CONST : TCG_CT_CONST_I32);
145
tcg_debug_assert(TCG_TARGET_REG_BITS == 64);
28
+ ct->ct |= TCG_CT_CONST_I32;
146
- tcg_out_qemu_ld(s, a0, a1, a2, -1, args[3], TCG_TYPE_I128);
147
+ tcg_out_qemu_ld(s, a0, a1, a2, args[3], TCG_TYPE_I128);
29
break;
148
break;
30
149
31
default:
150
case INDEX_op_qemu_st_i32:
32
@@ -XXX,XX +XXX,XX @@ static inline int tcg_target_const_match(tcg_target_long val, TCGType type,
151
case INDEX_op_qemu_st8_i32:
33
if (ct & TCG_CT_CONST) {
152
- tcg_out_qemu_st(s, a0, -1, a1, -1, a2, TCG_TYPE_I32);
34
return 1;
153
+ tcg_out_qemu_st(s, a0, -1, a1, a2, TCG_TYPE_I32);
35
}
154
break;
36
- if ((ct & TCG_CT_CONST_S32) && val == (int32_t)val) {
155
case INDEX_op_qemu_st_i64:
37
- return 1;
156
if (TCG_TARGET_REG_BITS == 64) {
38
- }
157
- tcg_out_qemu_st(s, a0, -1, a1, -1, a2, TCG_TYPE_I64);
39
- if ((ct & TCG_CT_CONST_U32) && val == (uint32_t)val) {
158
+ tcg_out_qemu_st(s, a0, -1, a1, a2, TCG_TYPE_I64);
40
- return 1;
159
} else {
41
- }
160
- tcg_out_qemu_st(s, a0, a1, a2, -1, args[3], TCG_TYPE_I64);
42
- if ((ct & TCG_CT_CONST_I32) && ~val == (int32_t)~val) {
161
+ tcg_out_qemu_st(s, a0, a1, a2, args[3], TCG_TYPE_I64);
43
- return 1;
162
}
44
+ if (type == TCG_TYPE_I32) {
163
break;
45
+ if (ct & (TCG_CT_CONST_S32 | TCG_CT_CONST_U32 | TCG_CT_CONST_I32)) {
164
case INDEX_op_qemu_st_i128:
46
+ return 1;
165
tcg_debug_assert(TCG_TARGET_REG_BITS == 64);
47
+ }
166
- tcg_out_qemu_st(s, a0, a1, a2, -1, args[3], TCG_TYPE_I128);
48
+ } else {
167
+ tcg_out_qemu_st(s, a0, a1, a2, args[3], TCG_TYPE_I128);
49
+ if ((ct & TCG_CT_CONST_S32) && val == (int32_t)val) {
168
break;
50
+ return 1;
169
51
+ }
170
OP_32_64(mulu2):
52
+ if ((ct & TCG_CT_CONST_U32) && val == (uint32_t)val) {
53
+ return 1;
54
+ }
55
+ if ((ct & TCG_CT_CONST_I32) && ~val == (int32_t)~val) {
56
+ return 1;
57
+ }
58
}
59
if ((ct & TCG_CT_CONST_WSZ) && val == (type == TCG_TYPE_I32 ? 32 : 64)) {
60
return 1;
61
--
171
--
62
2.25.1
172
2.43.0
63
173
64
174
diff view generated by jsdifflib
[PULL 10/24] tcg/mips: Split out target constraints to tcg-target-con-str.h
[PULL 07/24] tcg/mips: Drop addrhi from prepare_host_addr
1
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
1
The guest address will now always fit in one register.
2
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
3
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
---
5
---
5
tcg/mips/tcg-target-con-str.h | 24 +++++++++++
6
tcg/mips/tcg-target.c.inc | 62 ++++++++++++++-------------------------
6
tcg/mips/tcg-target.h | 1 +
7
1 file changed, 22 insertions(+), 40 deletions(-)
7
tcg/mips/tcg-target.c.inc | 77 ++++++++++-------------------------
8
3 files changed, 46 insertions(+), 56 deletions(-)
9
create mode 100644 tcg/mips/tcg-target-con-str.h
10
8
11
diff --git a/tcg/mips/tcg-target-con-str.h b/tcg/mips/tcg-target-con-str.h
12
new file mode 100644
13
index XXXXXXX..XXXXXXX
14
--- /dev/null
15
+++ b/tcg/mips/tcg-target-con-str.h
16
@@ -XXX,XX +XXX,XX @@
17
+/* SPDX-License-Identifier: MIT */
18
+/*
19
+ * Define MIPS target-specific operand constraints.
20
+ * Copyright (c) 2021 Linaro
21
+ */
22
+
23
+/*
24
+ * Define constraint letters for register sets:
25
+ * REGS(letter, register_mask)
26
+ */
27
+REGS('r', ALL_GENERAL_REGS)
28
+REGS('L', ALL_QLOAD_REGS)
29
+REGS('S', ALL_QSTORE_REGS)
30
+
31
+/*
32
+ * Define constraint letters for constants:
33
+ * CONST(letter, TCG_CT_CONST_* bit set)
34
+ */
35
+CONST('I', TCG_CT_CONST_U16)
36
+CONST('J', TCG_CT_CONST_S16)
37
+CONST('K', TCG_CT_CONST_P2M1)
38
+CONST('N', TCG_CT_CONST_N16)
39
+CONST('W', TCG_CT_CONST_WSZ)
40
+CONST('Z', TCG_CT_CONST_ZERO)
41
diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h
42
index XXXXXXX..XXXXXXX 100644
43
--- a/tcg/mips/tcg-target.h
44
+++ b/tcg/mips/tcg-target.h
45
@@ -XXX,XX +XXX,XX @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t);
46
#ifdef CONFIG_SOFTMMU
47
#define TCG_TARGET_NEED_LDST_LABELS
48
#endif
49
+#define TCG_TARGET_CON_STR_H
50
51
#endif
52
diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc
9
diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc
53
index XXXXXXX..XXXXXXX 100644
10
index XXXXXXX..XXXXXXX 100644
54
--- a/tcg/mips/tcg-target.c.inc
11
--- a/tcg/mips/tcg-target.c.inc
55
+++ b/tcg/mips/tcg-target.c.inc
12
+++ b/tcg/mips/tcg-target.c.inc
56
@@ -XXX,XX +XXX,XX @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
13
@@ -XXX,XX +XXX,XX @@ bool tcg_target_has_memory_bswap(MemOp memop)
57
#define TCG_CT_CONST_N16 0x1000 /* "Negatable" 16-bit: -32767 - 32767 */
14
* is required and fill in @h with the host address for the fast path.
58
#define TCG_CT_CONST_WSZ 0x2000 /* word size */
15
*/
59
16
static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
60
+#define ALL_GENERAL_REGS 0xffffffffu
17
- TCGReg addrlo, TCGReg addrhi,
61
+#define NOA0_REGS (ALL_GENERAL_REGS & ~(1 << TCG_REG_A0))
18
- MemOpIdx oi, bool is_ld)
62
+
19
+ TCGReg addr, MemOpIdx oi, bool is_ld)
63
+#ifdef CONFIG_SOFTMMU
64
+#define ALL_QLOAD_REGS \
65
+ (NOA0_REGS & ~((TCG_TARGET_REG_BITS < TARGET_LONG_BITS) << TCG_REG_A2))
66
+#define ALL_QSTORE_REGS \
67
+ (NOA0_REGS & ~(TCG_TARGET_REG_BITS < TARGET_LONG_BITS \
68
+ ? (1 << TCG_REG_A2) | (1 << TCG_REG_A3) \
69
+ : (1 << TCG_REG_A1)))
70
+#else
71
+#define ALL_QLOAD_REGS NOA0_REGS
72
+#define ALL_QSTORE_REGS NOA0_REGS
73
+#endif
74
+
75
+
76
static inline bool is_p2m1(tcg_target_long val)
77
{
20
{
78
return val && ((val + 1) & val) == 0;
21
TCGType addr_type = s->addr_type;
22
TCGLabelQemuLdst *ldst = NULL;
23
@@ -XXX,XX +XXX,XX @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
24
ldst = new_ldst_label(s);
25
ldst->is_ld = is_ld;
26
ldst->oi = oi;
27
- ldst->addrlo_reg = addrlo;
28
- ldst->addrhi_reg = addrhi;
29
+ ldst->addrlo_reg = addr;
30
31
/* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */
32
tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP0, TCG_AREG0, mask_off);
33
@@ -XXX,XX +XXX,XX @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
34
35
/* Extract the TLB index from the address into TMP3. */
36
if (TCG_TARGET_REG_BITS == 32 || addr_type == TCG_TYPE_I32) {
37
- tcg_out_opc_sa(s, OPC_SRL, TCG_TMP3, addrlo,
38
+ tcg_out_opc_sa(s, OPC_SRL, TCG_TMP3, addr,
39
s->page_bits - CPU_TLB_ENTRY_BITS);
40
} else {
41
- tcg_out_dsrl(s, TCG_TMP3, addrlo,
42
- s->page_bits - CPU_TLB_ENTRY_BITS);
43
+ tcg_out_dsrl(s, TCG_TMP3, addr, s->page_bits - CPU_TLB_ENTRY_BITS);
44
}
45
tcg_out_opc_reg(s, OPC_AND, TCG_TMP3, TCG_TMP3, TCG_TMP0);
46
47
@@ -XXX,XX +XXX,XX @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
48
tcg_out_opc_imm(s, (TCG_TARGET_REG_BITS == 32
49
|| addr_type == TCG_TYPE_I32
50
? OPC_ADDIU : OPC_DADDIU),
51
- TCG_TMP2, addrlo, s_mask - a_mask);
52
+ TCG_TMP2, addr, s_mask - a_mask);
53
tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, TCG_TMP2);
54
} else {
55
- tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, addrlo);
56
+ tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, addr);
57
}
58
59
/* Zero extend a 32-bit guest address for a 64-bit host. */
60
if (TCG_TARGET_REG_BITS == 64 && addr_type == TCG_TYPE_I32) {
61
- tcg_out_ext32u(s, TCG_TMP2, addrlo);
62
- addrlo = TCG_TMP2;
63
+ tcg_out_ext32u(s, TCG_TMP2, addr);
64
+ addr = TCG_TMP2;
65
}
66
67
ldst->label_ptr[0] = s->code_ptr;
68
tcg_out_opc_br(s, OPC_BNE, TCG_TMP1, TCG_TMP0);
69
70
- /* Load and test the high half tlb comparator. */
71
- if (TCG_TARGET_REG_BITS == 32 && addr_type != TCG_TYPE_I32) {
72
- /* delay slot */
73
- tcg_out_ldst(s, OPC_LW, TCG_TMP0, TCG_TMP3, cmp_off + HI_OFF);
74
-
75
- /* Load the tlb addend for the fast path. */
76
- tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP3, TCG_TMP3, add_off);
77
-
78
- ldst->label_ptr[1] = s->code_ptr;
79
- tcg_out_opc_br(s, OPC_BNE, addrhi, TCG_TMP0);
80
- }
81
-
82
/* delay slot */
83
base = TCG_TMP3;
84
- tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_TMP3, addrlo);
85
+ tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_TMP3, addr);
86
} else {
87
if (a_mask && (use_mips32r6_instructions || a_bits != s_bits)) {
88
ldst = new_ldst_label(s);
89
90
ldst->is_ld = is_ld;
91
ldst->oi = oi;
92
- ldst->addrlo_reg = addrlo;
93
- ldst->addrhi_reg = addrhi;
94
+ ldst->addrlo_reg = addr;
95
96
/* We are expecting a_bits to max out at 7, much lower than ANDI. */
97
tcg_debug_assert(a_bits < 16);
98
- tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP0, addrlo, a_mask);
99
+ tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP0, addr, a_mask);
100
101
ldst->label_ptr[0] = s->code_ptr;
102
if (use_mips32r6_instructions) {
103
@@ -XXX,XX +XXX,XX @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
104
}
105
}
106
107
- base = addrlo;
108
+ base = addr;
109
if (TCG_TARGET_REG_BITS == 64 && addr_type == TCG_TYPE_I32) {
110
tcg_out_ext32u(s, TCG_REG_A0, base);
111
base = TCG_REG_A0;
112
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_ld_unalign(TCGContext *s, TCGReg lo, TCGReg hi,
79
}
113
}
80
114
81
-/* parse target specific constraints */
115
static void tcg_out_qemu_ld(TCGContext *s, TCGReg datalo, TCGReg datahi,
82
-static const char *target_parse_constraint(TCGArgConstraint *ct,
116
- TCGReg addrlo, TCGReg addrhi,
83
- const char *ct_str, TCGType type)
117
- MemOpIdx oi, TCGType data_type)
84
-{
118
+ TCGReg addr, MemOpIdx oi, TCGType data_type)
85
- switch(*ct_str++) {
119
{
86
- case 'r':
120
MemOp opc = get_memop(oi);
87
- ct->regs = 0xffffffff;
121
TCGLabelQemuLdst *ldst;
88
- break;
122
HostAddress h;
89
- case 'L': /* qemu_ld input arg constraint */
123
90
- ct->regs = 0xffffffff;
124
- ldst = prepare_host_addr(s, &h, addrlo, addrhi, oi, true);
91
- tcg_regset_reset_reg(ct->regs, TCG_REG_A0);
125
+ ldst = prepare_host_addr(s, &h, addr, oi, true);
92
-#if defined(CONFIG_SOFTMMU)
126
93
- if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
127
if (use_mips32r6_instructions || h.aa.align >= (opc & MO_SIZE)) {
94
- tcg_regset_reset_reg(ct->regs, TCG_REG_A2);
128
tcg_out_qemu_ld_direct(s, datalo, datahi, h.base, opc, data_type);
95
- }
129
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_st_unalign(TCGContext *s, TCGReg lo, TCGReg hi,
96
-#endif
130
}
97
- break;
131
98
- case 'S': /* qemu_st constraint */
132
static void tcg_out_qemu_st(TCGContext *s, TCGReg datalo, TCGReg datahi,
99
- ct->regs = 0xffffffff;
133
- TCGReg addrlo, TCGReg addrhi,
100
- tcg_regset_reset_reg(ct->regs, TCG_REG_A0);
134
- MemOpIdx oi, TCGType data_type)
101
-#if defined(CONFIG_SOFTMMU)
135
+ TCGReg addr, MemOpIdx oi, TCGType data_type)
102
- if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
136
{
103
- tcg_regset_reset_reg(ct->regs, TCG_REG_A2);
137
MemOp opc = get_memop(oi);
104
- tcg_regset_reset_reg(ct->regs, TCG_REG_A3);
138
TCGLabelQemuLdst *ldst;
105
- } else {
139
HostAddress h;
106
- tcg_regset_reset_reg(ct->regs, TCG_REG_A1);
140
107
- }
141
- ldst = prepare_host_addr(s, &h, addrlo, addrhi, oi, false);
108
-#endif
142
+ ldst = prepare_host_addr(s, &h, addr, oi, false);
109
- break;
143
110
- case 'I':
144
if (use_mips32r6_instructions || h.aa.align >= (opc & MO_SIZE)) {
111
- ct->ct |= TCG_CT_CONST_U16;
145
tcg_out_qemu_st_direct(s, datalo, datahi, h.base, opc);
112
- break;
146
@@ -XXX,XX +XXX,XX @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
113
- case 'J':
147
break;
114
- ct->ct |= TCG_CT_CONST_S16;
148
115
- break;
149
case INDEX_op_qemu_ld_i32:
116
- case 'K':
150
- tcg_out_qemu_ld(s, a0, 0, a1, 0, a2, TCG_TYPE_I32);
117
- ct->ct |= TCG_CT_CONST_P2M1;
151
+ tcg_out_qemu_ld(s, a0, 0, a1, a2, TCG_TYPE_I32);
118
- break;
152
break;
119
- case 'N':
153
case INDEX_op_qemu_ld_i64:
120
- ct->ct |= TCG_CT_CONST_N16;
154
if (TCG_TARGET_REG_BITS == 64) {
121
- break;
155
- tcg_out_qemu_ld(s, a0, 0, a1, 0, a2, TCG_TYPE_I64);
122
- case 'W':
156
+ tcg_out_qemu_ld(s, a0, 0, a1, a2, TCG_TYPE_I64);
123
- ct->ct |= TCG_CT_CONST_WSZ;
157
} else {
124
- break;
158
- tcg_out_qemu_ld(s, a0, a1, a2, 0, args[3], TCG_TYPE_I64);
125
- case 'Z':
159
+ tcg_out_qemu_ld(s, a0, a1, a2, args[3], TCG_TYPE_I64);
126
- /* We are cheating a bit here, using the fact that the register
160
}
127
- ZERO is also the register number 0. Hence there is no need
161
break;
128
- to check for const_args in each instruction. */
162
129
- ct->ct |= TCG_CT_CONST_ZERO;
163
case INDEX_op_qemu_st_i32:
130
- break;
164
- tcg_out_qemu_st(s, a0, 0, a1, 0, a2, TCG_TYPE_I32);
131
- default:
165
+ tcg_out_qemu_st(s, a0, 0, a1, a2, TCG_TYPE_I32);
132
- return NULL;
166
break;
133
- }
167
case INDEX_op_qemu_st_i64:
134
- return ct_str;
168
if (TCG_TARGET_REG_BITS == 64) {
135
-}
169
- tcg_out_qemu_st(s, a0, 0, a1, 0, a2, TCG_TYPE_I64);
136
-
170
+ tcg_out_qemu_st(s, a0, 0, a1, a2, TCG_TYPE_I64);
137
/* test if a constant matches the constraint */
171
} else {
138
static inline int tcg_target_const_match(tcg_target_long val, TCGType type,
172
- tcg_out_qemu_st(s, a0, a1, a2, 0, args[3], TCG_TYPE_I64);
139
const TCGArgConstraint *arg_ct)
173
+ tcg_out_qemu_st(s, a0, a1, a2, args[3], TCG_TYPE_I64);
140
@@ -XXX,XX +XXX,XX @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
174
}
141
TCGArg a0, a1, a2;
175
break;
142
int c2;
176
143
144
+ /*
145
+ * Note that many operands use the constraint set "rZ".
146
+ * We make use of the fact that 0 is the ZERO register,
147
+ * and hence such cases need not check for const_args.
148
+ */
149
a0 = args[0];
150
a1 = args[1];
151
a2 = args[2];
152
--
177
--
153
2.25.1
178
2.43.0
154
179
155
180
diff view generated by jsdifflib
[PULL 19/24] tcg/ppc: Split out constraint sets to tcg-target-con-set.h
[PULL 08/24] tcg/ppc: Drop addrhi from prepare_host_addr
1
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
1
The guest address will now always fit in one register.
2
3
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
3
---
5
---
4
tcg/ppc/tcg-target-con-set.h | 42 +++++++++++
6
tcg/ppc/tcg-target.c.inc | 75 ++++++++++++----------------------------
5
tcg/ppc/tcg-target.h | 1 +
7
1 file changed, 23 insertions(+), 52 deletions(-)
6
tcg/ppc/tcg-target.c.inc | 136 +++++++++++++++--------------------
8
7
3 files changed, 99 insertions(+), 80 deletions(-)
8
create mode 100644 tcg/ppc/tcg-target-con-set.h
9
10
diff --git a/tcg/ppc/tcg-target-con-set.h b/tcg/ppc/tcg-target-con-set.h
11
new file mode 100644
12
index XXXXXXX..XXXXXXX
13
--- /dev/null
14
+++ b/tcg/ppc/tcg-target-con-set.h
15
@@ -XXX,XX +XXX,XX @@
16
+/* SPDX-License-Identifier: MIT */
17
+/*
18
+ * Define PowerPC target-specific constraint sets.
19
+ * Copyright (c) 2021 Linaro
20
+ */
21
+
22
+/*
23
+ * C_On_Im(...) defines a constraint set with <n> outputs and <m> inputs.
24
+ * Each operand should be a sequence of constraint letters as defined by
25
+ * tcg-target-con-str.h; the constraint combination is inclusive or.
26
+ */
27
+C_O0_I1(r)
28
+C_O0_I2(r, r)
29
+C_O0_I2(r, ri)
30
+C_O0_I2(S, S)
31
+C_O0_I2(v, r)
32
+C_O0_I3(S, S, S)
33
+C_O0_I4(r, r, ri, ri)
34
+C_O0_I4(S, S, S, S)
35
+C_O1_I1(r, L)
36
+C_O1_I1(r, r)
37
+C_O1_I1(v, r)
38
+C_O1_I1(v, v)
39
+C_O1_I1(v, vr)
40
+C_O1_I2(r, 0, rZ)
41
+C_O1_I2(r, L, L)
42
+C_O1_I2(r, rI, ri)
43
+C_O1_I2(r, rI, rT)
44
+C_O1_I2(r, r, r)
45
+C_O1_I2(r, r, ri)
46
+C_O1_I2(r, r, rI)
47
+C_O1_I2(r, r, rT)
48
+C_O1_I2(r, r, rU)
49
+C_O1_I2(r, r, rZW)
50
+C_O1_I2(v, v, v)
51
+C_O1_I3(v, v, v, v)
52
+C_O1_I4(r, r, ri, rZ, rZ)
53
+C_O1_I4(r, r, r, ri, ri)
54
+C_O2_I1(L, L, L)
55
+C_O2_I2(L, L, L, L)
56
+C_O2_I4(r, r, rI, rZM, r, r)
57
+C_O2_I4(r, r, r, r, rI, rZM)
58
diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h
59
index XXXXXXX..XXXXXXX 100644
60
--- a/tcg/ppc/tcg-target.h
61
+++ b/tcg/ppc/tcg-target.h
62
@@ -XXX,XX +XXX,XX @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t);
63
#define TCG_TARGET_NEED_LDST_LABELS
64
#endif
65
#define TCG_TARGET_NEED_POOL_LABELS
66
+#define TCG_TARGET_CON_SET_H
67
68
#endif
69
diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc
9
diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc
70
index XXXXXXX..XXXXXXX 100644
10
index XXXXXXX..XXXXXXX 100644
71
--- a/tcg/ppc/tcg-target.c.inc
11
--- a/tcg/ppc/tcg-target.c.inc
72
+++ b/tcg/ppc/tcg-target.c.inc
12
+++ b/tcg/ppc/tcg-target.c.inc
73
@@ -XXX,XX +XXX,XX @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece,
13
@@ -XXX,XX +XXX,XX @@ bool tcg_target_has_memory_bswap(MemOp memop)
74
va_end(va);
14
* is required and fill in @h with the host address for the fast path.
15
*/
16
static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
17
- TCGReg addrlo, TCGReg addrhi,
18
- MemOpIdx oi, bool is_ld)
19
+ TCGReg addr, MemOpIdx oi, bool is_ld)
20
{
21
TCGType addr_type = s->addr_type;
22
TCGLabelQemuLdst *ldst = NULL;
23
@@ -XXX,XX +XXX,XX @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
24
ldst = new_ldst_label(s);
25
ldst->is_ld = is_ld;
26
ldst->oi = oi;
27
- ldst->addrlo_reg = addrlo;
28
- ldst->addrhi_reg = addrhi;
29
+ ldst->addrlo_reg = addr;
30
31
/* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */
32
tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, TCG_AREG0, mask_off);
33
@@ -XXX,XX +XXX,XX @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
34
35
/* Extract the page index, shifted into place for tlb index. */
36
if (TCG_TARGET_REG_BITS == 32) {
37
- tcg_out_shri32(s, TCG_REG_R0, addrlo,
38
+ tcg_out_shri32(s, TCG_REG_R0, addr,
39
s->page_bits - CPU_TLB_ENTRY_BITS);
40
} else {
41
- tcg_out_shri64(s, TCG_REG_R0, addrlo,
42
+ tcg_out_shri64(s, TCG_REG_R0, addr,
43
s->page_bits - CPU_TLB_ENTRY_BITS);
44
}
45
tcg_out32(s, AND | SAB(TCG_REG_TMP1, TCG_REG_TMP1, TCG_REG_R0));
46
@@ -XXX,XX +XXX,XX @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
47
if (a_bits < s_bits) {
48
a_bits = s_bits;
49
}
50
- tcg_out_rlw(s, RLWINM, TCG_REG_R0, addrlo, 0,
51
+ tcg_out_rlw(s, RLWINM, TCG_REG_R0, addr, 0,
52
(32 - a_bits) & 31, 31 - s->page_bits);
53
} else {
54
- TCGReg t = addrlo;
55
+ TCGReg t = addr;
56
57
/*
58
* If the access is unaligned, we need to make sure we fail if we
59
@@ -XXX,XX +XXX,XX @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
60
}
61
}
62
63
- if (TCG_TARGET_REG_BITS == 32 && addr_type != TCG_TYPE_I32) {
64
- /* Low part comparison into cr7. */
65
- tcg_out_cmp(s, TCG_COND_EQ, TCG_REG_R0, TCG_REG_TMP2,
66
- 0, 7, TCG_TYPE_I32);
67
-
68
- /* Load the high part TLB comparator into TMP2. */
69
- tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_TMP2, TCG_REG_TMP1,
70
- cmp_off + 4 * !HOST_BIG_ENDIAN);
71
-
72
- /* Load addend, deferred for this case. */
73
- tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, TCG_REG_TMP1,
74
- offsetof(CPUTLBEntry, addend));
75
-
76
- /* High part comparison into cr6. */
77
- tcg_out_cmp(s, TCG_COND_EQ, addrhi, TCG_REG_TMP2,
78
- 0, 6, TCG_TYPE_I32);
79
-
80
- /* Combine comparisons into cr0. */
81
- tcg_out32(s, CRAND | BT(0, CR_EQ) | BA(6, CR_EQ) | BB(7, CR_EQ));
82
- } else {
83
- /* Full comparison into cr0. */
84
- tcg_out_cmp(s, TCG_COND_EQ, TCG_REG_R0, TCG_REG_TMP2,
85
- 0, 0, addr_type);
86
- }
87
+ /* Full comparison into cr0. */
88
+ tcg_out_cmp(s, TCG_COND_EQ, TCG_REG_R0, TCG_REG_TMP2, 0, 0, addr_type);
89
90
/* Load a pointer into the current opcode w/conditional branch-link. */
91
ldst->label_ptr[0] = s->code_ptr;
92
@@ -XXX,XX +XXX,XX @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
93
ldst = new_ldst_label(s);
94
ldst->is_ld = is_ld;
95
ldst->oi = oi;
96
- ldst->addrlo_reg = addrlo;
97
- ldst->addrhi_reg = addrhi;
98
+ ldst->addrlo_reg = addr;
99
100
/* We are expecting a_bits to max out at 7, much lower than ANDI. */
101
tcg_debug_assert(a_bits < 16);
102
- tcg_out32(s, ANDI | SAI(addrlo, TCG_REG_R0, (1 << a_bits) - 1));
103
+ tcg_out32(s, ANDI | SAI(addr, TCG_REG_R0, (1 << a_bits) - 1));
104
105
ldst->label_ptr[0] = s->code_ptr;
106
tcg_out32(s, BC | BI(0, CR_EQ) | BO_COND_FALSE | LK);
107
@@ -XXX,XX +XXX,XX @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
108
109
if (TCG_TARGET_REG_BITS == 64 && addr_type == TCG_TYPE_I32) {
110
/* Zero-extend the guest address for use in the host address. */
111
- tcg_out_ext32u(s, TCG_REG_TMP2, addrlo);
112
+ tcg_out_ext32u(s, TCG_REG_TMP2, addr);
113
h->index = TCG_REG_TMP2;
114
} else {
115
- h->index = addrlo;
116
+ h->index = addr;
117
}
118
119
return ldst;
75
}
120
}
76
121
77
-static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
122
static void tcg_out_qemu_ld(TCGContext *s, TCGReg datalo, TCGReg datahi,
78
+static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
123
- TCGReg addrlo, TCGReg addrhi,
124
- MemOpIdx oi, TCGType data_type)
125
+ TCGReg addr, MemOpIdx oi, TCGType data_type)
79
{
126
{
80
- static const TCGTargetOpDef r = { .args_ct_str = { "r" } };
127
MemOp opc = get_memop(oi);
81
- static const TCGTargetOpDef r_r = { .args_ct_str = { "r", "r" } };
128
TCGLabelQemuLdst *ldst;
82
- static const TCGTargetOpDef r_L = { .args_ct_str = { "r", "L" } };
129
HostAddress h;
83
- static const TCGTargetOpDef S_S = { .args_ct_str = { "S", "S" } };
130
84
- static const TCGTargetOpDef r_ri = { .args_ct_str = { "r", "ri" } };
131
- ldst = prepare_host_addr(s, &h, addrlo, addrhi, oi, true);
85
- static const TCGTargetOpDef r_r_r = { .args_ct_str = { "r", "r", "r" } };
132
+ ldst = prepare_host_addr(s, &h, addr, oi, true);
86
- static const TCGTargetOpDef r_L_L = { .args_ct_str = { "r", "L", "L" } };
133
87
- static const TCGTargetOpDef L_L_L = { .args_ct_str = { "L", "L", "L" } };
134
if (TCG_TARGET_REG_BITS == 32 && (opc & MO_SIZE) == MO_64) {
88
- static const TCGTargetOpDef S_S_S = { .args_ct_str = { "S", "S", "S" } };
135
if (opc & MO_BSWAP) {
89
- static const TCGTargetOpDef r_r_ri = { .args_ct_str = { "r", "r", "ri" } };
136
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg datalo, TCGReg datahi,
90
- static const TCGTargetOpDef r_r_rI = { .args_ct_str = { "r", "r", "rI" } };
137
}
91
- static const TCGTargetOpDef r_r_rT = { .args_ct_str = { "r", "r", "rT" } };
138
92
- static const TCGTargetOpDef r_r_rU = { .args_ct_str = { "r", "r", "rU" } };
139
static void tcg_out_qemu_st(TCGContext *s, TCGReg datalo, TCGReg datahi,
93
- static const TCGTargetOpDef r_rI_ri
140
- TCGReg addrlo, TCGReg addrhi,
94
- = { .args_ct_str = { "r", "rI", "ri" } };
141
- MemOpIdx oi, TCGType data_type)
95
- static const TCGTargetOpDef r_rI_rT
142
+ TCGReg addr, MemOpIdx oi, TCGType data_type)
96
- = { .args_ct_str = { "r", "rI", "rT" } };
143
{
97
- static const TCGTargetOpDef r_r_rZW
144
MemOp opc = get_memop(oi);
98
- = { .args_ct_str = { "r", "r", "rZW" } };
145
TCGLabelQemuLdst *ldst;
99
- static const TCGTargetOpDef L_L_L_L
146
HostAddress h;
100
- = { .args_ct_str = { "L", "L", "L", "L" } };
147
101
- static const TCGTargetOpDef S_S_S_S
148
- ldst = prepare_host_addr(s, &h, addrlo, addrhi, oi, false);
102
- = { .args_ct_str = { "S", "S", "S", "S" } };
149
+ ldst = prepare_host_addr(s, &h, addr, oi, false);
103
- static const TCGTargetOpDef movc
150
104
- = { .args_ct_str = { "r", "r", "ri", "rZ", "rZ" } };
151
if (TCG_TARGET_REG_BITS == 32 && (opc & MO_SIZE) == MO_64) {
105
- static const TCGTargetOpDef dep
152
if (opc & MO_BSWAP) {
106
- = { .args_ct_str = { "r", "0", "rZ" } };
153
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_ldst_i128(TCGContext *s, TCGReg datalo, TCGReg datahi,
107
- static const TCGTargetOpDef br2
154
uint32_t insn;
108
- = { .args_ct_str = { "r", "r", "ri", "ri" } };
155
TCGReg index;
109
- static const TCGTargetOpDef setc2
156
110
- = { .args_ct_str = { "r", "r", "r", "ri", "ri" } };
157
- ldst = prepare_host_addr(s, &h, addr_reg, -1, oi, is_ld);
111
- static const TCGTargetOpDef add2
158
+ ldst = prepare_host_addr(s, &h, addr_reg, oi, is_ld);
112
- = { .args_ct_str = { "r", "r", "r", "r", "rI", "rZM" } };
159
113
- static const TCGTargetOpDef sub2
160
/* Compose the final address, as LQ/STQ have no indexing. */
114
- = { .args_ct_str = { "r", "r", "rI", "rZM", "r", "r" } };
161
index = h.index;
115
- static const TCGTargetOpDef v_r = { .args_ct_str = { "v", "r" } };
162
@@ -XXX,XX +XXX,XX @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
116
- static const TCGTargetOpDef v_vr = { .args_ct_str = { "v", "vr" } };
163
break;
117
- static const TCGTargetOpDef v_v = { .args_ct_str = { "v", "v" } };
118
- static const TCGTargetOpDef v_v_v = { .args_ct_str = { "v", "v", "v" } };
119
- static const TCGTargetOpDef v_v_v_v
120
- = { .args_ct_str = { "v", "v", "v", "v" } };
121
-
122
switch (op) {
123
case INDEX_op_goto_ptr:
124
- return &r;
125
+ return C_O0_I1(r);
126
127
case INDEX_op_ld8u_i32:
128
case INDEX_op_ld8s_i32:
129
case INDEX_op_ld16u_i32:
130
case INDEX_op_ld16s_i32:
131
case INDEX_op_ld_i32:
132
- case INDEX_op_st8_i32:
133
- case INDEX_op_st16_i32:
134
- case INDEX_op_st_i32:
135
case INDEX_op_ctpop_i32:
136
case INDEX_op_neg_i32:
137
case INDEX_op_not_i32:
138
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
139
case INDEX_op_ld32u_i64:
140
case INDEX_op_ld32s_i64:
141
case INDEX_op_ld_i64:
142
- case INDEX_op_st8_i64:
143
- case INDEX_op_st16_i64:
144
- case INDEX_op_st32_i64:
145
- case INDEX_op_st_i64:
146
case INDEX_op_ctpop_i64:
147
case INDEX_op_neg_i64:
148
case INDEX_op_not_i64:
149
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
150
case INDEX_op_bswap32_i64:
151
case INDEX_op_bswap64_i64:
152
case INDEX_op_extract_i64:
153
- return &r_r;
154
+ return C_O1_I1(r, r);
155
+
156
+ case INDEX_op_st8_i32:
157
+ case INDEX_op_st16_i32:
158
+ case INDEX_op_st_i32:
159
+ case INDEX_op_st8_i64:
160
+ case INDEX_op_st16_i64:
161
+ case INDEX_op_st32_i64:
162
+ case INDEX_op_st_i64:
163
+ return C_O0_I2(r, r);
164
165
case INDEX_op_add_i32:
166
case INDEX_op_and_i32:
167
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
168
case INDEX_op_rotl_i64:
169
case INDEX_op_rotr_i64:
170
case INDEX_op_setcond_i64:
171
- return &r_r_ri;
172
+ return C_O1_I2(r, r, ri);
173
+
174
case INDEX_op_mul_i32:
175
case INDEX_op_mul_i64:
176
- return &r_r_rI;
177
+ return C_O1_I2(r, r, rI);
178
+
179
case INDEX_op_div_i32:
180
case INDEX_op_divu_i32:
181
case INDEX_op_nand_i32:
182
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
183
case INDEX_op_divu_i64:
184
case INDEX_op_mulsh_i64:
185
case INDEX_op_muluh_i64:
186
- return &r_r_r;
187
+ return C_O1_I2(r, r, r);
188
+
189
case INDEX_op_sub_i32:
190
- return &r_rI_ri;
191
+ return C_O1_I2(r, rI, ri);
192
case INDEX_op_add_i64:
193
- return &r_r_rT;
194
+ return C_O1_I2(r, r, rT);
195
case INDEX_op_or_i64:
196
case INDEX_op_xor_i64:
197
- return &r_r_rU;
198
+ return C_O1_I2(r, r, rU);
199
case INDEX_op_sub_i64:
200
- return &r_rI_rT;
201
+ return C_O1_I2(r, rI, rT);
202
case INDEX_op_clz_i32:
203
case INDEX_op_ctz_i32:
204
case INDEX_op_clz_i64:
205
case INDEX_op_ctz_i64:
206
- return &r_r_rZW;
207
+ return C_O1_I2(r, r, rZW);
208
209
case INDEX_op_brcond_i32:
210
case INDEX_op_brcond_i64:
211
- return &r_ri;
212
+ return C_O0_I2(r, ri);
213
214
case INDEX_op_movcond_i32:
215
case INDEX_op_movcond_i64:
216
- return &movc;
217
+ return C_O1_I4(r, r, ri, rZ, rZ);
218
case INDEX_op_deposit_i32:
219
case INDEX_op_deposit_i64:
220
- return &dep;
221
+ return C_O1_I2(r, 0, rZ);
222
case INDEX_op_brcond2_i32:
223
- return &br2;
224
+ return C_O0_I4(r, r, ri, ri);
225
case INDEX_op_setcond2_i32:
226
- return &setc2;
227
+ return C_O1_I4(r, r, r, ri, ri);
228
case INDEX_op_add2_i64:
229
case INDEX_op_add2_i32:
230
- return &add2;
231
+ return C_O2_I4(r, r, r, r, rI, rZM);
232
case INDEX_op_sub2_i64:
233
case INDEX_op_sub2_i32:
234
- return &sub2;
235
+ return C_O2_I4(r, r, rI, rZM, r, r);
236
164
237
case INDEX_op_qemu_ld_i32:
165
case INDEX_op_qemu_ld_i32:
238
return (TCG_TARGET_REG_BITS == 64 || TARGET_LONG_BITS == 32
166
- tcg_out_qemu_ld(s, args[0], -1, args[1], -1, args[2], TCG_TYPE_I32);
239
- ? &r_L : &r_L_L);
167
+ tcg_out_qemu_ld(s, args[0], -1, args[1], args[2], TCG_TYPE_I32);
240
+ ? C_O1_I1(r, L)
168
break;
241
+ : C_O1_I2(r, L, L));
169
case INDEX_op_qemu_ld_i64:
242
+
170
if (TCG_TARGET_REG_BITS == 64) {
171
- tcg_out_qemu_ld(s, args[0], -1, args[1], -1,
172
- args[2], TCG_TYPE_I64);
173
+ tcg_out_qemu_ld(s, args[0], -1, args[1], args[2], TCG_TYPE_I64);
174
} else {
175
- tcg_out_qemu_ld(s, args[0], args[1], args[2], -1,
176
+ tcg_out_qemu_ld(s, args[0], args[1], args[2],
177
args[3], TCG_TYPE_I64);
178
}
179
break;
180
@@ -XXX,XX +XXX,XX @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
181
break;
182
243
case INDEX_op_qemu_st_i32:
183
case INDEX_op_qemu_st_i32:
244
return (TCG_TARGET_REG_BITS == 64 || TARGET_LONG_BITS == 32
184
- tcg_out_qemu_st(s, args[0], -1, args[1], -1, args[2], TCG_TYPE_I32);
245
- ? &S_S : &S_S_S);
185
+ tcg_out_qemu_st(s, args[0], -1, args[1], args[2], TCG_TYPE_I32);
246
+ ? C_O0_I2(S, S)
186
break;
247
+ : C_O0_I3(S, S, S));
248
+
249
case INDEX_op_qemu_ld_i64:
250
- return (TCG_TARGET_REG_BITS == 64 ? &r_L
251
- : TARGET_LONG_BITS == 32 ? &L_L_L : &L_L_L_L);
252
+ return (TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, L)
253
+ : TARGET_LONG_BITS == 32 ? C_O2_I1(L, L, L)
254
+ : C_O2_I2(L, L, L, L));
255
+
256
case INDEX_op_qemu_st_i64:
187
case INDEX_op_qemu_st_i64:
257
- return (TCG_TARGET_REG_BITS == 64 ? &S_S
188
if (TCG_TARGET_REG_BITS == 64) {
258
- : TARGET_LONG_BITS == 32 ? &S_S_S : &S_S_S_S);
189
- tcg_out_qemu_st(s, args[0], -1, args[1], -1,
259
+ return (TCG_TARGET_REG_BITS == 64 ? C_O0_I2(S, S)
190
- args[2], TCG_TYPE_I64);
260
+ : TARGET_LONG_BITS == 32 ? C_O0_I3(S, S, S)
191
+ tcg_out_qemu_st(s, args[0], -1, args[1], args[2], TCG_TYPE_I64);
261
+ : C_O0_I4(S, S, S, S));
192
} else {
262
193
- tcg_out_qemu_st(s, args[0], args[1], args[2], -1,
263
case INDEX_op_add_vec:
194
+ tcg_out_qemu_st(s, args[0], args[1], args[2],
264
case INDEX_op_sub_vec:
195
args[3], TCG_TYPE_I64);
265
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
196
}
266
case INDEX_op_ppc_mulou_vec:
197
break;
267
case INDEX_op_ppc_pkum_vec:
268
case INDEX_op_dup2_vec:
269
- return &v_v_v;
270
+ return C_O1_I2(v, v, v);
271
+
272
case INDEX_op_not_vec:
273
case INDEX_op_neg_vec:
274
- return &v_v;
275
+ return C_O1_I1(v, v);
276
+
277
case INDEX_op_dup_vec:
278
- return have_isa_3_00 ? &v_vr : &v_v;
279
+ return have_isa_3_00 ? C_O1_I1(v, vr) : C_O1_I1(v, v);
280
+
281
case INDEX_op_ld_vec:
282
- case INDEX_op_st_vec:
283
case INDEX_op_dupm_vec:
284
- return &v_r;
285
+ return C_O1_I1(v, r);
286
+
287
+ case INDEX_op_st_vec:
288
+ return C_O0_I2(v, r);
289
+
290
case INDEX_op_bitsel_vec:
291
case INDEX_op_ppc_msum_vec:
292
- return &v_v_v_v;
293
+ return C_O1_I3(v, v, v, v);
294
295
default:
296
- return NULL;
297
+ g_assert_not_reached();
298
}
299
}
300
301
--
198
--
302
2.25.1
199
2.43.0
303
200
304
201
diff view generated by jsdifflib
[PULL 05/24] tcg/i386: Split out target constraints to tcg-target-con-str.h
[PULL 09/24] tcg: Replace addr{lo, hi}_reg with addr_reg in TCGLabelQemuLdst
1
This eliminates the target-specific function target_parse_constraint
1
There is now always only one guest address register.
2
and folds it into the single caller, process_op_defs. Since this is
2
3
done directly into the switch statement, duplicates are compilation
3
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
4
errors rather than silently ignored at runtime.
5
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
---
5
---
9
tcg/i386/tcg-target-con-str.h | 33 +++++++++++++++++
6
tcg/tcg.c | 18 +++++++++---------
10
tcg/i386/tcg-target.h | 1 +
7
tcg/aarch64/tcg-target.c.inc | 4 ++--
11
tcg/tcg.c | 33 ++++++++++++++---
8
tcg/arm/tcg-target.c.inc | 4 ++--
12
tcg/i386/tcg-target.c.inc | 69 -----------------------------------
9
tcg/i386/tcg-target.c.inc | 4 ++--
13
4 files changed, 62 insertions(+), 74 deletions(-)
10
tcg/loongarch64/tcg-target.c.inc | 4 ++--
14
create mode 100644 tcg/i386/tcg-target-con-str.h
11
tcg/mips/tcg-target.c.inc | 4 ++--
15
12
tcg/ppc/tcg-target.c.inc | 4 ++--
16
diff --git a/tcg/i386/tcg-target-con-str.h b/tcg/i386/tcg-target-con-str.h
13
tcg/riscv/tcg-target.c.inc | 4 ++--
17
new file mode 100644
14
tcg/s390x/tcg-target.c.inc | 4 ++--
18
index XXXXXXX..XXXXXXX
15
tcg/sparc64/tcg-target.c.inc | 4 ++--
19
--- /dev/null
16
10 files changed, 27 insertions(+), 27 deletions(-)
20
+++ b/tcg/i386/tcg-target-con-str.h
17
21
@@ -XXX,XX +XXX,XX @@
22
+/* SPDX-License-Identifier: MIT */
23
+/*
24
+ * Define i386 target-specific operand constraints.
25
+ * Copyright (c) 2021 Linaro
26
+ *
27
+ */
28
+
29
+/*
30
+ * Define constraint letters for register sets:
31
+ * REGS(letter, register_mask)
32
+ */
33
+REGS('a', 1u << TCG_REG_EAX)
34
+REGS('b', 1u << TCG_REG_EBX)
35
+REGS('c', 1u << TCG_REG_ECX)
36
+REGS('d', 1u << TCG_REG_EDX)
37
+REGS('S', 1u << TCG_REG_ESI)
38
+REGS('D', 1u << TCG_REG_EDI)
39
+
40
+REGS('r', ALL_GENERAL_REGS)
41
+REGS('x', ALL_VECTOR_REGS)
42
+REGS('q', ALL_BYTEL_REGS) /* regs that can be used as a byte operand */
43
+REGS('Q', ALL_BYTEH_REGS) /* regs with a second byte (e.g. %ah) */
44
+REGS('L', ALL_GENERAL_REGS & ~SOFTMMU_RESERVE_REGS) /* qemu_ld/st */
45
+REGS('s', ALL_BYTEL_REGS & ~SOFTMMU_RESERVE_REGS) /* qemu_st8_i32 data */
46
+
47
+/*
48
+ * Define constraint letters for constants:
49
+ * CONST(letter, TCG_CT_CONST_* bit set)
50
+ */
51
+CONST('e', TCG_CT_CONST_S32)
52
+CONST('I', TCG_CT_CONST_I32)
53
+CONST('W', TCG_CT_CONST_WSZ)
54
+CONST('Z', TCG_CT_CONST_U32)
55
diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h
56
index XXXXXXX..XXXXXXX 100644
57
--- a/tcg/i386/tcg-target.h
58
+++ b/tcg/i386/tcg-target.h
59
@@ -XXX,XX +XXX,XX @@ static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_rx,
60
#define TCG_TARGET_NEED_LDST_LABELS
61
#endif
62
#define TCG_TARGET_NEED_POOL_LABELS
63
+#define TCG_TARGET_CON_STR_H
64
65
#endif
66
diff --git a/tcg/tcg.c b/tcg/tcg.c
18
diff --git a/tcg/tcg.c b/tcg/tcg.c
67
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
68
--- a/tcg/tcg.c
20
--- a/tcg/tcg.c
69
+++ b/tcg/tcg.c
21
+++ b/tcg/tcg.c
70
@@ -XXX,XX +XXX,XX @@ static void tcg_register_jit_int(const void *buf, size_t size,
22
@@ -XXX,XX +XXX,XX @@ struct TCGLabelQemuLdst {
71
__attribute__((unused));
23
bool is_ld; /* qemu_ld: true, qemu_st: false */
72
24
MemOpIdx oi;
73
/* Forward declarations for functions declared and used in tcg-target.c.inc. */
25
TCGType type; /* result type of a load */
74
+#ifndef TCG_TARGET_CON_STR_H
26
- TCGReg addrlo_reg; /* reg index for low word of guest virtual addr */
75
static const char *target_parse_constraint(TCGArgConstraint *ct,
27
- TCGReg addrhi_reg; /* reg index for high word of guest virtual addr */
76
const char *ct_str, TCGType type);
28
+ TCGReg addr_reg; /* reg index for guest virtual addr */
77
+#endif
29
TCGReg datalo_reg; /* reg index for low word to be loaded or stored */
78
static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg1,
30
TCGReg datahi_reg; /* reg index for high word to be loaded or stored */
79
intptr_t arg2);
31
const tcg_insn_unit *raddr; /* addr of the next IR of qemu_ld/st IR */
80
static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg);
32
@@ -XXX,XX +XXX,XX @@ static void tcg_out_ld_helper_args(TCGContext *s, const TCGLabelQemuLdst *ldst,
81
@@ -XXX,XX +XXX,XX @@ static void process_op_defs(TCGContext *s)
33
*/
82
for (op = 0; op < NB_OPS; op++) {
34
tcg_out_helper_add_mov(mov, loc + HOST_BIG_ENDIAN,
83
TCGOpDef *def = &tcg_op_defs[op];
35
TCG_TYPE_I32, TCG_TYPE_I32,
84
const TCGTargetOpDef *tdefs;
36
- ldst->addrlo_reg, -1);
85
- TCGType type;
37
+ ldst->addr_reg, -1);
86
int i, nb_args;
38
tcg_out_helper_load_slots(s, 1, mov, parm);
87
39
88
if (def->flags & TCG_OPF_NOT_PRESENT) {
40
tcg_out_helper_load_imm(s, loc[!HOST_BIG_ENDIAN].arg_slot,
89
@@ -XXX,XX +XXX,XX @@ static void process_op_defs(TCGContext *s)
41
@@ -XXX,XX +XXX,XX @@ static void tcg_out_ld_helper_args(TCGContext *s, const TCGLabelQemuLdst *ldst,
90
/* Missing TCGTargetOpDef entry. */
42
next_arg += 2;
91
tcg_debug_assert(tdefs != NULL);
43
} else {
92
44
nmov = tcg_out_helper_add_mov(mov, loc, TCG_TYPE_I64, s->addr_type,
93
- type = (def->flags & TCG_OPF_64BIT ? TCG_TYPE_I64 : TCG_TYPE_I32);
45
- ldst->addrlo_reg, ldst->addrhi_reg);
94
for (i = 0; i < nb_args; i++) {
46
+ ldst->addr_reg, -1);
95
const char *ct_str = tdefs->args_ct_str[i];
47
tcg_out_helper_load_slots(s, nmov, mov, parm);
96
/* Incomplete TCGTargetOpDef entry. */
48
next_arg += nmov;
97
@@ -XXX,XX +XXX,XX @@ static void process_op_defs(TCGContext *s)
49
}
98
def->args_ct[i].ct |= TCG_CT_CONST;
50
@@ -XXX,XX +XXX,XX @@ static void tcg_out_st_helper_args(TCGContext *s, const TCGLabelQemuLdst *ldst,
99
ct_str++;
51
100
break;
52
/* Handle addr argument. */
101
+
53
loc = &info->in[next_arg];
102
+#ifdef TCG_TARGET_CON_STR_H
54
- if (TCG_TARGET_REG_BITS == 32 && s->addr_type == TCG_TYPE_I32) {
103
+ /* Include all of the target-specific constraints. */
55
+ tcg_debug_assert(s->addr_type <= TCG_TYPE_REG);
104
+
56
+ if (TCG_TARGET_REG_BITS == 32) {
105
+#undef CONST
57
/*
106
+#define CONST(CASE, MASK) \
58
- * 32-bit host with 32-bit guest: zero-extend the guest address
107
+ case CASE: def->args_ct[i].ct |= MASK; ct_str++; break;
59
+ * 32-bit host (and thus 32-bit guest): zero-extend the guest address
108
+#define REGS(CASE, MASK) \
60
* to 64-bits for the helper by storing the low part. Later,
109
+ case CASE: def->args_ct[i].regs |= MASK; ct_str++; break;
61
* after we have processed the register inputs, we will load a
110
+
62
* zero for the high part.
111
+#include "tcg-target-con-str.h"
63
*/
112
+
64
tcg_out_helper_add_mov(mov, loc + HOST_BIG_ENDIAN,
113
+#undef REGS
65
TCG_TYPE_I32, TCG_TYPE_I32,
114
+#undef CONST
66
- ldst->addrlo_reg, -1);
115
default:
67
+ ldst->addr_reg, -1);
116
- ct_str = target_parse_constraint(&def->args_ct[i],
68
next_arg += 2;
117
- ct_str, type);
69
nmov += 1;
118
/* Typo in TCGTargetOpDef constraint. */
70
} else {
119
- tcg_debug_assert(ct_str != NULL);
71
n = tcg_out_helper_add_mov(mov, loc, TCG_TYPE_I64, s->addr_type,
120
+ g_assert_not_reached();
72
- ldst->addrlo_reg, ldst->addrhi_reg);
121
+#else
73
+ ldst->addr_reg, -1);
122
+ default:
74
next_arg += n;
123
+ {
75
nmov += n;
124
+ TCGType type = (def->flags & TCG_OPF_64BIT
76
}
125
+ ? TCG_TYPE_I64 : TCG_TYPE_I32);
77
@@ -XXX,XX +XXX,XX @@ static void tcg_out_st_helper_args(TCGContext *s, const TCGLabelQemuLdst *ldst,
126
+ ct_str = target_parse_constraint(&def->args_ct[i],
78
g_assert_not_reached();
127
+ ct_str, type);
79
}
128
+ /* Typo in TCGTargetOpDef constraint. */
80
129
+ tcg_debug_assert(ct_str != NULL);
81
- if (TCG_TARGET_REG_BITS == 32 && s->addr_type == TCG_TYPE_I32) {
130
+ }
82
+ if (TCG_TARGET_REG_BITS == 32) {
131
+#endif
83
/* Zero extend the address by loading a zero for the high part. */
132
}
84
loc = &info->in[1 + !HOST_BIG_ENDIAN];
133
}
85
tcg_out_helper_load_imm(s, loc->arg_slot, TCG_TYPE_I32, 0, parm);
134
}
86
diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc
87
index XXXXXXX..XXXXXXX 100644
88
--- a/tcg/aarch64/tcg-target.c.inc
89
+++ b/tcg/aarch64/tcg-target.c.inc
90
@@ -XXX,XX +XXX,XX @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
91
ldst = new_ldst_label(s);
92
ldst->is_ld = is_ld;
93
ldst->oi = oi;
94
- ldst->addrlo_reg = addr_reg;
95
+ ldst->addr_reg = addr_reg;
96
97
mask_type = (s->page_bits + s->tlb_dyn_max_bits > 32
98
? TCG_TYPE_I64 : TCG_TYPE_I32);
99
@@ -XXX,XX +XXX,XX @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
100
101
ldst->is_ld = is_ld;
102
ldst->oi = oi;
103
- ldst->addrlo_reg = addr_reg;
104
+ ldst->addr_reg = addr_reg;
105
106
/* tst addr, #mask */
107
tcg_out_logicali(s, I3404_ANDSI, 0, TCG_REG_XZR, addr_reg, a_mask);
108
diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
109
index XXXXXXX..XXXXXXX 100644
110
--- a/tcg/arm/tcg-target.c.inc
111
+++ b/tcg/arm/tcg-target.c.inc
112
@@ -XXX,XX +XXX,XX @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
113
ldst = new_ldst_label(s);
114
ldst->is_ld = is_ld;
115
ldst->oi = oi;
116
- ldst->addrlo_reg = addr;
117
+ ldst->addr_reg = addr;
118
119
/* Load cpu->neg.tlb.f[mmu_idx].{mask,table} into {r0,r1}. */
120
QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, mask) != 0);
121
@@ -XXX,XX +XXX,XX @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
122
ldst = new_ldst_label(s);
123
ldst->is_ld = is_ld;
124
ldst->oi = oi;
125
- ldst->addrlo_reg = addr;
126
+ ldst->addr_reg = addr;
127
128
/* We are expecting alignment to max out at 7 */
129
tcg_debug_assert(a_mask <= 0xff);
135
diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
130
diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
136
index XXXXXXX..XXXXXXX 100644
131
index XXXXXXX..XXXXXXX 100644
137
--- a/tcg/i386/tcg-target.c.inc
132
--- a/tcg/i386/tcg-target.c.inc
138
+++ b/tcg/i386/tcg-target.c.inc
133
+++ b/tcg/i386/tcg-target.c.inc
139
@@ -XXX,XX +XXX,XX @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
134
@@ -XXX,XX +XXX,XX @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
140
return true;
135
ldst = new_ldst_label(s);
141
}
136
ldst->is_ld = is_ld;
142
137
ldst->oi = oi;
143
-/* parse target specific constraints */
138
- ldst->addrlo_reg = addr;
144
-static const char *target_parse_constraint(TCGArgConstraint *ct,
139
+ ldst->addr_reg = addr;
145
- const char *ct_str, TCGType type)
140
146
-{
141
if (TCG_TARGET_REG_BITS == 64) {
147
- switch(*ct_str++) {
142
ttype = s->addr_type;
148
- case 'a':
143
@@ -XXX,XX +XXX,XX @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
149
- tcg_regset_set_reg(ct->regs, TCG_REG_EAX);
144
ldst = new_ldst_label(s);
150
- break;
145
ldst->is_ld = is_ld;
151
- case 'b':
146
ldst->oi = oi;
152
- tcg_regset_set_reg(ct->regs, TCG_REG_EBX);
147
- ldst->addrlo_reg = addr;
153
- break;
148
+ ldst->addr_reg = addr;
154
- case 'c':
149
155
- tcg_regset_set_reg(ct->regs, TCG_REG_ECX);
150
/* jne slow_path */
156
- break;
151
jcc = tcg_out_cmp(s, TCG_COND_TSTNE, addr, a_mask, true, false);
157
- case 'd':
152
diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc
158
- tcg_regset_set_reg(ct->regs, TCG_REG_EDX);
153
index XXXXXXX..XXXXXXX 100644
159
- break;
154
--- a/tcg/loongarch64/tcg-target.c.inc
160
- case 'S':
155
+++ b/tcg/loongarch64/tcg-target.c.inc
161
- tcg_regset_set_reg(ct->regs, TCG_REG_ESI);
156
@@ -XXX,XX +XXX,XX @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
162
- break;
157
ldst = new_ldst_label(s);
163
- case 'D':
158
ldst->is_ld = is_ld;
164
- tcg_regset_set_reg(ct->regs, TCG_REG_EDI);
159
ldst->oi = oi;
165
- break;
160
- ldst->addrlo_reg = addr_reg;
166
- case 'q':
161
+ ldst->addr_reg = addr_reg;
167
- /* A register that can be used as a byte operand. */
162
168
- ct->regs |= ALL_BYTEL_REGS;
163
tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP0, TCG_AREG0, mask_ofs);
169
- break;
164
tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, TCG_AREG0, table_ofs);
170
- case 'Q':
165
@@ -XXX,XX +XXX,XX @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
171
- /* A register with an addressable second byte (e.g. %ah). */
166
172
- ct->regs |= ALL_BYTEH_REGS;
167
ldst->is_ld = is_ld;
173
- break;
168
ldst->oi = oi;
174
- case 'r':
169
- ldst->addrlo_reg = addr_reg;
175
- /* A general register. */
170
+ ldst->addr_reg = addr_reg;
176
- ct->regs |= ALL_GENERAL_REGS;
171
177
- break;
172
/*
178
- case 'W':
173
* Without micro-architecture details, we don't know which of
179
- /* With TZCNT/LZCNT, we can have operand-size as an input. */
174
diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc
180
- ct->ct |= TCG_CT_CONST_WSZ;
175
index XXXXXXX..XXXXXXX 100644
181
- break;
176
--- a/tcg/mips/tcg-target.c.inc
182
- case 'x':
177
+++ b/tcg/mips/tcg-target.c.inc
183
- /* A vector register. */
178
@@ -XXX,XX +XXX,XX @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
184
- ct->regs |= ALL_VECTOR_REGS;
179
ldst = new_ldst_label(s);
185
- break;
180
ldst->is_ld = is_ld;
186
-
181
ldst->oi = oi;
187
- case 'L':
182
- ldst->addrlo_reg = addr;
188
- /* qemu_ld/st data+address constraint */
183
+ ldst->addr_reg = addr;
189
- ct->regs |= ALL_GENERAL_REGS & ~SOFTMMU_RESERVE_REGS;
184
190
- break;
185
/* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */
191
- case 's':
186
tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP0, TCG_AREG0, mask_off);
192
- /* qemu_st8_i32 data constraint */
187
@@ -XXX,XX +XXX,XX @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
193
- ct->regs |= ALL_BYTEL_REGS & ~SOFTMMU_RESERVE_REGS;
188
194
- break;
189
ldst->is_ld = is_ld;
195
-
190
ldst->oi = oi;
196
- case 'e':
191
- ldst->addrlo_reg = addr;
197
- ct->ct |= TCG_CT_CONST_S32;
192
+ ldst->addr_reg = addr;
198
- break;
193
199
- case 'Z':
194
/* We are expecting a_bits to max out at 7, much lower than ANDI. */
200
- ct->ct |= TCG_CT_CONST_U32;
195
tcg_debug_assert(a_bits < 16);
201
- break;
196
diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc
202
- case 'I':
197
index XXXXXXX..XXXXXXX 100644
203
- ct->ct |= TCG_CT_CONST_I32;
198
--- a/tcg/ppc/tcg-target.c.inc
204
- break;
199
+++ b/tcg/ppc/tcg-target.c.inc
205
-
200
@@ -XXX,XX +XXX,XX @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
206
- default:
201
ldst = new_ldst_label(s);
207
- return NULL;
202
ldst->is_ld = is_ld;
208
- }
203
ldst->oi = oi;
209
- return ct_str;
204
- ldst->addrlo_reg = addr;
210
-}
205
+ ldst->addr_reg = addr;
211
-
206
212
/* test if a constant matches the constraint */
207
/* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */
213
static inline int tcg_target_const_match(tcg_target_long val, TCGType type,
208
tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, TCG_AREG0, mask_off);
214
const TCGArgConstraint *arg_ct)
209
@@ -XXX,XX +XXX,XX @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
210
ldst = new_ldst_label(s);
211
ldst->is_ld = is_ld;
212
ldst->oi = oi;
213
- ldst->addrlo_reg = addr;
214
+ ldst->addr_reg = addr;
215
216
/* We are expecting a_bits to max out at 7, much lower than ANDI. */
217
tcg_debug_assert(a_bits < 16);
218
diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
219
index XXXXXXX..XXXXXXX 100644
220
--- a/tcg/riscv/tcg-target.c.inc
221
+++ b/tcg/riscv/tcg-target.c.inc
222
@@ -XXX,XX +XXX,XX @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, TCGReg *pbase,
223
ldst = new_ldst_label(s);
224
ldst->is_ld = is_ld;
225
ldst->oi = oi;
226
- ldst->addrlo_reg = addr_reg;
227
+ ldst->addr_reg = addr_reg;
228
229
init_setting_vtype(s);
230
231
@@ -XXX,XX +XXX,XX @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, TCGReg *pbase,
232
ldst = new_ldst_label(s);
233
ldst->is_ld = is_ld;
234
ldst->oi = oi;
235
- ldst->addrlo_reg = addr_reg;
236
+ ldst->addr_reg = addr_reg;
237
238
init_setting_vtype(s);
239
240
diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc
241
index XXXXXXX..XXXXXXX 100644
242
--- a/tcg/s390x/tcg-target.c.inc
243
+++ b/tcg/s390x/tcg-target.c.inc
244
@@ -XXX,XX +XXX,XX @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
245
ldst = new_ldst_label(s);
246
ldst->is_ld = is_ld;
247
ldst->oi = oi;
248
- ldst->addrlo_reg = addr_reg;
249
+ ldst->addr_reg = addr_reg;
250
251
tcg_out_sh64(s, RSY_SRLG, TCG_TMP0, addr_reg, TCG_REG_NONE,
252
s->page_bits - CPU_TLB_ENTRY_BITS);
253
@@ -XXX,XX +XXX,XX @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
254
ldst = new_ldst_label(s);
255
ldst->is_ld = is_ld;
256
ldst->oi = oi;
257
- ldst->addrlo_reg = addr_reg;
258
+ ldst->addr_reg = addr_reg;
259
260
tcg_debug_assert(a_mask <= 0xffff);
261
tcg_out_insn(s, RI, TMLL, addr_reg, a_mask);
262
diff --git a/tcg/sparc64/tcg-target.c.inc b/tcg/sparc64/tcg-target.c.inc
263
index XXXXXXX..XXXXXXX 100644
264
--- a/tcg/sparc64/tcg-target.c.inc
265
+++ b/tcg/sparc64/tcg-target.c.inc
266
@@ -XXX,XX +XXX,XX @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
267
ldst = new_ldst_label(s);
268
ldst->is_ld = is_ld;
269
ldst->oi = oi;
270
- ldst->addrlo_reg = addr_reg;
271
+ ldst->addr_reg = addr_reg;
272
ldst->label_ptr[0] = s->code_ptr;
273
274
/* bne,pn %[xi]cc, label0 */
275
@@ -XXX,XX +XXX,XX @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
276
ldst = new_ldst_label(s);
277
ldst->is_ld = is_ld;
278
ldst->oi = oi;
279
- ldst->addrlo_reg = addr_reg;
280
+ ldst->addr_reg = addr_reg;
281
ldst->label_ptr[0] = s->code_ptr;
282
283
/* bne,pn %icc, label0 */
215
--
284
--
216
2.25.1
285
2.43.0
217
286
218
287
diff view generated by jsdifflib
[PULL 08/24] tcg/ppc: Split out target constraints to tcg-target-con-str.h
[PULL 10/24] plugins: Fix qemu_plugin_read_memory_vaddr parameters
1
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
1
The declaration uses uint64_t for addr.
2
3
Fixes: 595cd9ce2ec ("plugins: add plugin API to read guest memory")
4
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
3
---
6
---
4
tcg/ppc/tcg-target-con-str.h | 30 +++++++++++++++
7
plugins/api.c | 2 +-
5
tcg/ppc/tcg-target.h | 1 +
8
1 file changed, 1 insertion(+), 1 deletion(-)
6
tcg/ppc/tcg-target.c.inc | 73 ++++++++----------------------------
7
3 files changed, 46 insertions(+), 58 deletions(-)
8
create mode 100644 tcg/ppc/tcg-target-con-str.h
9
9
10
diff --git a/tcg/ppc/tcg-target-con-str.h b/tcg/ppc/tcg-target-con-str.h
10
diff --git a/plugins/api.c b/plugins/api.c
11
new file mode 100644
12
index XXXXXXX..XXXXXXX
13
--- /dev/null
14
+++ b/tcg/ppc/tcg-target-con-str.h
15
@@ -XXX,XX +XXX,XX @@
16
+/* SPDX-License-Identifier: MIT */
17
+/*
18
+ * Define PowerPC target-specific operand constraints.
19
+ * Copyright (c) 2021 Linaro
20
+ */
21
+
22
+/*
23
+ * Define constraint letters for register sets:
24
+ * REGS(letter, register_mask)
25
+ */
26
+REGS('r', ALL_GENERAL_REGS)
27
+REGS('v', ALL_VECTOR_REGS)
28
+REGS('A', 1u << TCG_REG_R3)
29
+REGS('B', 1u << TCG_REG_R4)
30
+REGS('C', 1u << TCG_REG_R5)
31
+REGS('D', 1u << TCG_REG_R6)
32
+REGS('L', ALL_QLOAD_REGS)
33
+REGS('S', ALL_QSTORE_REGS)
34
+
35
+/*
36
+ * Define constraint letters for constants:
37
+ * CONST(letter, TCG_CT_CONST_* bit set)
38
+ */
39
+CONST('I', TCG_CT_CONST_S16)
40
+CONST('J', TCG_CT_CONST_U16)
41
+CONST('M', TCG_CT_CONST_MONE)
42
+CONST('T', TCG_CT_CONST_S32)
43
+CONST('U', TCG_CT_CONST_U32)
44
+CONST('W', TCG_CT_CONST_WSZ)
45
+CONST('Z', TCG_CT_CONST_ZERO)
46
diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h
47
index XXXXXXX..XXXXXXX 100644
11
index XXXXXXX..XXXXXXX 100644
48
--- a/tcg/ppc/tcg-target.h
12
--- a/plugins/api.c
49
+++ b/tcg/ppc/tcg-target.h
13
+++ b/plugins/api.c
50
@@ -XXX,XX +XXX,XX @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t);
14
@@ -XXX,XX +XXX,XX @@ GArray *qemu_plugin_get_registers(void)
51
#define TCG_TARGET_NEED_LDST_LABELS
15
return create_register_handles(regs);
52
#endif
53
#define TCG_TARGET_NEED_POOL_LABELS
54
+#define TCG_TARGET_CON_STR_H
55
56
#endif
57
diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc
58
index XXXXXXX..XXXXXXX 100644
59
--- a/tcg/ppc/tcg-target.c.inc
60
+++ b/tcg/ppc/tcg-target.c.inc
61
@@ -XXX,XX +XXX,XX @@
62
#define TCG_CT_CONST_MONE 0x2000
63
#define TCG_CT_CONST_WSZ 0x4000
64
65
+#define ALL_GENERAL_REGS 0xffffffffu
66
+#define ALL_VECTOR_REGS 0xffffffff00000000ull
67
+
68
+#ifdef CONFIG_SOFTMMU
69
+#define ALL_QLOAD_REGS \
70
+ (ALL_GENERAL_REGS & \
71
+ ~((1 << TCG_REG_R3) | (1 << TCG_REG_R4) | (1 << TCG_REG_R5)))
72
+#define ALL_QSTORE_REGS \
73
+ (ALL_GENERAL_REGS & ~((1 << TCG_REG_R3) | (1 << TCG_REG_R4) | \
74
+ (1 << TCG_REG_R5) | (1 << TCG_REG_R6)))
75
+#else
76
+#define ALL_QLOAD_REGS (ALL_GENERAL_REGS & ~(1 << TCG_REG_R3))
77
+#define ALL_QSTORE_REGS ALL_QLOAD_REGS
78
+#endif
79
+
80
TCGPowerISA have_isa;
81
static bool have_isel;
82
bool have_altivec;
83
@@ -XXX,XX +XXX,XX @@ static bool reloc_pc14(tcg_insn_unit *src_rw, const tcg_insn_unit *target)
84
return false;
85
}
16
}
86
17
87
-/* parse target specific constraints */
18
-bool qemu_plugin_read_memory_vaddr(vaddr addr, GByteArray *data, size_t len)
88
-static const char *target_parse_constraint(TCGArgConstraint *ct,
19
+bool qemu_plugin_read_memory_vaddr(uint64_t addr, GByteArray *data, size_t len)
89
- const char *ct_str, TCGType type)
20
{
90
-{
21
g_assert(current_cpu);
91
- switch (*ct_str++) {
22
92
- case 'A': case 'B': case 'C': case 'D':
93
- tcg_regset_set_reg(ct->regs, 3 + ct_str[0] - 'A');
94
- break;
95
- case 'r':
96
- ct->regs = 0xffffffff;
97
- break;
98
- case 'v':
99
- ct->regs = 0xffffffff00000000ull;
100
- break;
101
- case 'L': /* qemu_ld constraint */
102
- ct->regs = 0xffffffff;
103
- tcg_regset_reset_reg(ct->regs, TCG_REG_R3);
104
-#ifdef CONFIG_SOFTMMU
105
- tcg_regset_reset_reg(ct->regs, TCG_REG_R4);
106
- tcg_regset_reset_reg(ct->regs, TCG_REG_R5);
107
-#endif
108
- break;
109
- case 'S': /* qemu_st constraint */
110
- ct->regs = 0xffffffff;
111
- tcg_regset_reset_reg(ct->regs, TCG_REG_R3);
112
-#ifdef CONFIG_SOFTMMU
113
- tcg_regset_reset_reg(ct->regs, TCG_REG_R4);
114
- tcg_regset_reset_reg(ct->regs, TCG_REG_R5);
115
- tcg_regset_reset_reg(ct->regs, TCG_REG_R6);
116
-#endif
117
- break;
118
- case 'I':
119
- ct->ct |= TCG_CT_CONST_S16;
120
- break;
121
- case 'J':
122
- ct->ct |= TCG_CT_CONST_U16;
123
- break;
124
- case 'M':
125
- ct->ct |= TCG_CT_CONST_MONE;
126
- break;
127
- case 'T':
128
- ct->ct |= TCG_CT_CONST_S32;
129
- break;
130
- case 'U':
131
- ct->ct |= TCG_CT_CONST_U32;
132
- break;
133
- case 'W':
134
- ct->ct |= TCG_CT_CONST_WSZ;
135
- break;
136
- case 'Z':
137
- ct->ct |= TCG_CT_CONST_ZERO;
138
- break;
139
- default:
140
- return NULL;
141
- }
142
- return ct_str;
143
-}
144
-
145
/* test if a constant matches the constraint */
146
static int tcg_target_const_match(tcg_target_long val, TCGType type,
147
const TCGArgConstraint *arg_ct)
148
--
23
--
149
2.25.1
24
2.43.0
150
25
151
26
diff view generated by jsdifflib
[PULL 02/24] tcg/tci: Remove TCG_TARGET_HAS_* ifdefs
[PULL 11/24] accel/tcg: Fix tlb_set_page_with_attrs, tlb_set_page
1
The opcodes always exist, regardless of whether or not they
1
The declarations use vaddr for size.
2
are enabled. Remove the unnecessary ifdefs.
3
2
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
---
4
---
6
tcg/tci/tcg-target.c.inc | 82 ----------------------------------------
5
accel/tcg/cputlb.c | 4 ++--
7
1 file changed, 82 deletions(-)
6
1 file changed, 2 insertions(+), 2 deletions(-)
8
7
9
diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
8
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
10
index XXXXXXX..XXXXXXX 100644
9
index XXXXXXX..XXXXXXX 100644
11
--- a/tcg/tci/tcg-target.c.inc
10
--- a/accel/tcg/cputlb.c
12
+++ b/tcg/tci/tcg-target.c.inc
11
+++ b/accel/tcg/cputlb.c
13
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef tcg_target_op_defs[] = {
12
@@ -XXX,XX +XXX,XX @@ void tlb_set_page_full(CPUState *cpu, int mmu_idx,
14
{ INDEX_op_add_i32, { R, RI, RI } },
13
15
{ INDEX_op_sub_i32, { R, RI, RI } },
14
void tlb_set_page_with_attrs(CPUState *cpu, vaddr addr,
16
{ INDEX_op_mul_i32, { R, RI, RI } },
15
hwaddr paddr, MemTxAttrs attrs, int prot,
17
-#if TCG_TARGET_HAS_div_i32
16
- int mmu_idx, uint64_t size)
18
{ INDEX_op_div_i32, { R, R, R } },
17
+ int mmu_idx, vaddr size)
19
{ INDEX_op_divu_i32, { R, R, R } },
18
{
20
{ INDEX_op_rem_i32, { R, R, R } },
19
CPUTLBEntryFull full = {
21
{ INDEX_op_remu_i32, { R, R, R } },
20
.phys_addr = paddr,
22
-#elif TCG_TARGET_HAS_div2_i32
21
@@ -XXX,XX +XXX,XX @@ void tlb_set_page_with_attrs(CPUState *cpu, vaddr addr,
23
- { INDEX_op_div2_i32, { R, R, "0", "1", R } },
22
24
- { INDEX_op_divu2_i32, { R, R, "0", "1", R } },
23
void tlb_set_page(CPUState *cpu, vaddr addr,
25
-#endif
24
hwaddr paddr, int prot,
26
/* TODO: Does R, RI, RI result in faster code than R, R, RI?
25
- int mmu_idx, uint64_t size)
27
If both operands are constants, we can optimize. */
26
+ int mmu_idx, vaddr size)
28
{ INDEX_op_and_i32, { R, RI, RI } },
27
{
29
-#if TCG_TARGET_HAS_andc_i32
28
tlb_set_page_with_attrs(cpu, addr, paddr, MEMTXATTRS_UNSPECIFIED,
30
{ INDEX_op_andc_i32, { R, RI, RI } },
29
prot, mmu_idx, size);
31
-#endif
32
-#if TCG_TARGET_HAS_eqv_i32
33
{ INDEX_op_eqv_i32, { R, RI, RI } },
34
-#endif
35
-#if TCG_TARGET_HAS_nand_i32
36
{ INDEX_op_nand_i32, { R, RI, RI } },
37
-#endif
38
-#if TCG_TARGET_HAS_nor_i32
39
{ INDEX_op_nor_i32, { R, RI, RI } },
40
-#endif
41
{ INDEX_op_or_i32, { R, RI, RI } },
42
-#if TCG_TARGET_HAS_orc_i32
43
{ INDEX_op_orc_i32, { R, RI, RI } },
44
-#endif
45
{ INDEX_op_xor_i32, { R, RI, RI } },
46
{ INDEX_op_shl_i32, { R, RI, RI } },
47
{ INDEX_op_shr_i32, { R, RI, RI } },
48
{ INDEX_op_sar_i32, { R, RI, RI } },
49
-#if TCG_TARGET_HAS_rot_i32
50
{ INDEX_op_rotl_i32, { R, RI, RI } },
51
{ INDEX_op_rotr_i32, { R, RI, RI } },
52
-#endif
53
-#if TCG_TARGET_HAS_deposit_i32
54
{ INDEX_op_deposit_i32, { R, "0", R } },
55
-#endif
56
57
{ INDEX_op_brcond_i32, { R, RI } },
58
59
{ INDEX_op_setcond_i32, { R, R, RI } },
60
-#if TCG_TARGET_REG_BITS == 64
61
{ INDEX_op_setcond_i64, { R, R, RI } },
62
-#endif /* TCG_TARGET_REG_BITS == 64 */
63
64
-#if TCG_TARGET_REG_BITS == 32
65
/* TODO: Support R, R, R, R, RI, RI? Will it be faster? */
66
{ INDEX_op_add2_i32, { R, R, R, R, R, R } },
67
{ INDEX_op_sub2_i32, { R, R, R, R, R, R } },
68
{ INDEX_op_brcond2_i32, { R, R, RI, RI } },
69
{ INDEX_op_mulu2_i32, { R, R, R, R } },
70
{ INDEX_op_setcond2_i32, { R, R, R, RI, RI } },
71
-#endif
72
73
-#if TCG_TARGET_HAS_not_i32
74
{ INDEX_op_not_i32, { R, R } },
75
-#endif
76
-#if TCG_TARGET_HAS_neg_i32
77
{ INDEX_op_neg_i32, { R, R } },
78
-#endif
79
80
-#if TCG_TARGET_REG_BITS == 64
81
{ INDEX_op_ld8u_i64, { R, R } },
82
{ INDEX_op_ld8s_i64, { R, R } },
83
{ INDEX_op_ld16u_i64, { R, R } },
84
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef tcg_target_op_defs[] = {
85
{ INDEX_op_add_i64, { R, RI, RI } },
86
{ INDEX_op_sub_i64, { R, RI, RI } },
87
{ INDEX_op_mul_i64, { R, RI, RI } },
88
-#if TCG_TARGET_HAS_div_i64
89
{ INDEX_op_div_i64, { R, R, R } },
90
{ INDEX_op_divu_i64, { R, R, R } },
91
{ INDEX_op_rem_i64, { R, R, R } },
92
{ INDEX_op_remu_i64, { R, R, R } },
93
-#elif TCG_TARGET_HAS_div2_i64
94
- { INDEX_op_div2_i64, { R, R, "0", "1", R } },
95
- { INDEX_op_divu2_i64, { R, R, "0", "1", R } },
96
-#endif
97
{ INDEX_op_and_i64, { R, RI, RI } },
98
-#if TCG_TARGET_HAS_andc_i64
99
{ INDEX_op_andc_i64, { R, RI, RI } },
100
-#endif
101
-#if TCG_TARGET_HAS_eqv_i64
102
{ INDEX_op_eqv_i64, { R, RI, RI } },
103
-#endif
104
-#if TCG_TARGET_HAS_nand_i64
105
{ INDEX_op_nand_i64, { R, RI, RI } },
106
-#endif
107
-#if TCG_TARGET_HAS_nor_i64
108
{ INDEX_op_nor_i64, { R, RI, RI } },
109
-#endif
110
{ INDEX_op_or_i64, { R, RI, RI } },
111
-#if TCG_TARGET_HAS_orc_i64
112
{ INDEX_op_orc_i64, { R, RI, RI } },
113
-#endif
114
{ INDEX_op_xor_i64, { R, RI, RI } },
115
{ INDEX_op_shl_i64, { R, RI, RI } },
116
{ INDEX_op_shr_i64, { R, RI, RI } },
117
{ INDEX_op_sar_i64, { R, RI, RI } },
118
-#if TCG_TARGET_HAS_rot_i64
119
{ INDEX_op_rotl_i64, { R, RI, RI } },
120
{ INDEX_op_rotr_i64, { R, RI, RI } },
121
-#endif
122
-#if TCG_TARGET_HAS_deposit_i64
123
{ INDEX_op_deposit_i64, { R, "0", R } },
124
-#endif
125
{ INDEX_op_brcond_i64, { R, RI } },
126
127
-#if TCG_TARGET_HAS_ext8s_i64
128
{ INDEX_op_ext8s_i64, { R, R } },
129
-#endif
130
-#if TCG_TARGET_HAS_ext16s_i64
131
{ INDEX_op_ext16s_i64, { R, R } },
132
-#endif
133
-#if TCG_TARGET_HAS_ext32s_i64
134
{ INDEX_op_ext32s_i64, { R, R } },
135
-#endif
136
-#if TCG_TARGET_HAS_ext8u_i64
137
{ INDEX_op_ext8u_i64, { R, R } },
138
-#endif
139
-#if TCG_TARGET_HAS_ext16u_i64
140
{ INDEX_op_ext16u_i64, { R, R } },
141
-#endif
142
-#if TCG_TARGET_HAS_ext32u_i64
143
{ INDEX_op_ext32u_i64, { R, R } },
144
-#endif
145
{ INDEX_op_ext_i32_i64, { R, R } },
146
{ INDEX_op_extu_i32_i64, { R, R } },
147
-#if TCG_TARGET_HAS_bswap16_i64
148
{ INDEX_op_bswap16_i64, { R, R } },
149
-#endif
150
-#if TCG_TARGET_HAS_bswap32_i64
151
{ INDEX_op_bswap32_i64, { R, R } },
152
-#endif
153
-#if TCG_TARGET_HAS_bswap64_i64
154
{ INDEX_op_bswap64_i64, { R, R } },
155
-#endif
156
-#if TCG_TARGET_HAS_not_i64
157
{ INDEX_op_not_i64, { R, R } },
158
-#endif
159
-#if TCG_TARGET_HAS_neg_i64
160
{ INDEX_op_neg_i64, { R, R } },
161
-#endif
162
-#endif /* TCG_TARGET_REG_BITS == 64 */
163
164
{ INDEX_op_qemu_ld_i32, { R, L } },
165
{ INDEX_op_qemu_ld_i64, { R64, L } },
166
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef tcg_target_op_defs[] = {
167
{ INDEX_op_qemu_st_i32, { R, S } },
168
{ INDEX_op_qemu_st_i64, { R64, S } },
169
170
-#if TCG_TARGET_HAS_ext8s_i32
171
{ INDEX_op_ext8s_i32, { R, R } },
172
-#endif
173
-#if TCG_TARGET_HAS_ext16s_i32
174
{ INDEX_op_ext16s_i32, { R, R } },
175
-#endif
176
-#if TCG_TARGET_HAS_ext8u_i32
177
{ INDEX_op_ext8u_i32, { R, R } },
178
-#endif
179
-#if TCG_TARGET_HAS_ext16u_i32
180
{ INDEX_op_ext16u_i32, { R, R } },
181
-#endif
182
183
-#if TCG_TARGET_HAS_bswap16_i32
184
{ INDEX_op_bswap16_i32, { R, R } },
185
-#endif
186
-#if TCG_TARGET_HAS_bswap32_i32
187
{ INDEX_op_bswap32_i32, { R, R } },
188
-#endif
189
190
{ INDEX_op_mb, { } },
191
{ -1 },
192
--
30
--
193
2.25.1
31
2.43.0
194
195
diff view generated by jsdifflib
[PULL 13/24] tcg/sparc: Split out target constraints to tcg-target-con-str.h
[PULL 12/24] include/exec: Change vaddr to uintptr_t
1
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
Since we no longer support 64-bit guests on 32-bit hosts,
2
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
2
we can use a 32-bit type on a 32-bit host.
3
4
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
---
6
---
5
tcg/sparc/tcg-target-con-str.h | 23 ++++++++++
7
include/exec/vaddr.h | 16 +++++++++-------
6
tcg/sparc/tcg-target.h | 5 +--
8
1 file changed, 9 insertions(+), 7 deletions(-)
7
tcg/sparc/tcg-target.c.inc | 81 +++++++++++++---------------------
8
3 files changed, 55 insertions(+), 54 deletions(-)
9
create mode 100644 tcg/sparc/tcg-target-con-str.h
10
9
11
diff --git a/tcg/sparc/tcg-target-con-str.h b/tcg/sparc/tcg-target-con-str.h
10
diff --git a/include/exec/vaddr.h b/include/exec/vaddr.h
12
new file mode 100644
11
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX
12
--- a/include/exec/vaddr.h
14
--- /dev/null
13
+++ b/include/exec/vaddr.h
15
+++ b/tcg/sparc/tcg-target-con-str.h
16
@@ -XXX,XX +XXX,XX @@
14
@@ -XXX,XX +XXX,XX @@
17
+/* SPDX-License-Identifier: MIT */
15
/**
18
+/*
16
* vaddr:
19
+ * Define Sparc target-specific operand constraints.
17
* Type wide enough to contain any #target_ulong virtual address.
20
+ * Copyright (c) 2021 Linaro
18
+ * We do not support 64-bit guest on 32-host and detect at configure time.
21
+ */
19
+ * Therefore, a host pointer width will always fit a guest pointer.
22
+
20
*/
23
+/*
21
-typedef uint64_t vaddr;
24
+ * Define constraint letters for register sets:
22
-#define VADDR_PRId PRId64
25
+ * REGS(letter, register_mask)
23
-#define VADDR_PRIu PRIu64
26
+ */
24
-#define VADDR_PRIo PRIo64
27
+REGS('r', ALL_GENERAL_REGS)
25
-#define VADDR_PRIx PRIx64
28
+REGS('R', ALL_GENERAL_REGS64)
26
-#define VADDR_PRIX PRIX64
29
+REGS('s', ALL_QLDST_REGS)
27
-#define VADDR_MAX UINT64_MAX
30
+REGS('S', ALL_QLDST_REGS64)
28
+typedef uintptr_t vaddr;
31
+REGS('A', TARGET_LONG_BITS == 64 ? ALL_QLDST_REGS64 : ALL_QLDST_REGS)
29
+#define VADDR_PRId PRIdPTR
32
+
30
+#define VADDR_PRIu PRIuPTR
33
+/*
31
+#define VADDR_PRIo PRIoPTR
34
+ * Define constraint letters for constants:
32
+#define VADDR_PRIx PRIxPTR
35
+ * CONST(letter, TCG_CT_CONST_* bit set)
33
+#define VADDR_PRIX PRIXPTR
36
+ */
34
+#define VADDR_MAX UINTPTR_MAX
37
+CONST('I', TCG_CT_CONST_S11)
38
+CONST('J', TCG_CT_CONST_S13)
39
+CONST('Z', TCG_CT_CONST_ZERO)
40
diff --git a/tcg/sparc/tcg-target.h b/tcg/sparc/tcg-target.h
41
index XXXXXXX..XXXXXXX 100644
42
--- a/tcg/sparc/tcg-target.h
43
+++ b/tcg/sparc/tcg-target.h
44
@@ -XXX,XX +XXX,XX @@ typedef enum {
45
TCG_REG_I7,
46
} TCGReg;
47
48
-#define TCG_CT_CONST_S11 0x100
49
-#define TCG_CT_CONST_S13 0x200
50
-#define TCG_CT_CONST_ZERO 0x400
51
-
52
/* used for function call generation */
53
#define TCG_REG_CALL_STACK TCG_REG_O6
54
55
@@ -XXX,XX +XXX,XX @@ extern bool use_vis3_instructions;
56
void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t);
57
58
#define TCG_TARGET_NEED_POOL_LABELS
59
+#define TCG_TARGET_CON_STR_H
60
35
61
#endif
36
#endif
62
diff --git a/tcg/sparc/tcg-target.c.inc b/tcg/sparc/tcg-target.c.inc
63
index XXXXXXX..XXXXXXX 100644
64
--- a/tcg/sparc/tcg-target.c.inc
65
+++ b/tcg/sparc/tcg-target.c.inc
66
@@ -XXX,XX +XXX,XX @@ static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
67
# define SPARC64 0
68
#endif
69
70
-/* Note that sparcv8plus can only hold 64 bit quantities in %g and %o
71
- registers. These are saved manually by the kernel in full 64-bit
72
- slots. The %i and %l registers are saved by the register window
73
- mechanism, which only allocates space for 32 bits. Given that this
74
- window spill/fill can happen on any signal, we must consider the
75
- high bits of the %i and %l registers garbage at all times. */
76
-#if SPARC64
77
-# define ALL_64 0xffffffffu
78
+#define TCG_CT_CONST_S11 0x100
79
+#define TCG_CT_CONST_S13 0x200
80
+#define TCG_CT_CONST_ZERO 0x400
81
+
82
+/*
83
+ * For softmmu, we need to avoid conflicts with the first 3
84
+ * argument registers to perform the tlb lookup, and to call
85
+ * the helper function.
86
+ */
87
+#ifdef CONFIG_SOFTMMU
88
+#define SOFTMMU_RESERVE_REGS MAKE_64BIT_MASK(TCG_REG_O0, 3)
89
#else
90
-# define ALL_64 0xffffu
91
+#define SOFTMMU_RESERVE_REGS 0
92
#endif
93
94
+/*
95
+ * Note that sparcv8plus can only hold 64 bit quantities in %g and %o
96
+ * registers. These are saved manually by the kernel in full 64-bit
97
+ * slots. The %i and %l registers are saved by the register window
98
+ * mechanism, which only allocates space for 32 bits. Given that this
99
+ * window spill/fill can happen on any signal, we must consider the
100
+ * high bits of the %i and %l registers garbage at all times.
101
+ */
102
+#define ALL_GENERAL_REGS MAKE_64BIT_MASK(0, 32)
103
+#if SPARC64
104
+# define ALL_GENERAL_REGS64 ALL_GENERAL_REGS
105
+#else
106
+# define ALL_GENERAL_REGS64 MAKE_64BIT_MASK(0, 16)
107
+#endif
108
+#define ALL_QLDST_REGS (ALL_GENERAL_REGS & ~SOFTMMU_RESERVE_REGS)
109
+#define ALL_QLDST_REGS64 (ALL_GENERAL_REGS64 & ~SOFTMMU_RESERVE_REGS)
110
+
111
/* Define some temporary registers. T2 is used for constant generation. */
112
#define TCG_REG_T1 TCG_REG_G1
113
#define TCG_REG_T2 TCG_REG_O7
114
@@ -XXX,XX +XXX,XX @@ static bool patch_reloc(tcg_insn_unit *src_rw, int type,
115
return true;
116
}
117
118
-/* parse target specific constraints */
119
-static const char *target_parse_constraint(TCGArgConstraint *ct,
120
- const char *ct_str, TCGType type)
121
-{
122
- switch (*ct_str++) {
123
- case 'r':
124
- ct->regs = 0xffffffff;
125
- break;
126
- case 'R':
127
- ct->regs = ALL_64;
128
- break;
129
- case 'A': /* qemu_ld/st address constraint */
130
- ct->regs = TARGET_LONG_BITS == 64 ? ALL_64 : 0xffffffff;
131
- reserve_helpers:
132
- tcg_regset_reset_reg(ct->regs, TCG_REG_O0);
133
- tcg_regset_reset_reg(ct->regs, TCG_REG_O1);
134
- tcg_regset_reset_reg(ct->regs, TCG_REG_O2);
135
- break;
136
- case 's': /* qemu_st data 32-bit constraint */
137
- ct->regs = 0xffffffff;
138
- goto reserve_helpers;
139
- case 'S': /* qemu_st data 64-bit constraint */
140
- ct->regs = ALL_64;
141
- goto reserve_helpers;
142
- case 'I':
143
- ct->ct |= TCG_CT_CONST_S11;
144
- break;
145
- case 'J':
146
- ct->ct |= TCG_CT_CONST_S13;
147
- break;
148
- case 'Z':
149
- ct->ct |= TCG_CT_CONST_ZERO;
150
- break;
151
- default:
152
- return NULL;
153
- }
154
- return ct_str;
155
-}
156
-
157
/* test if a constant matches the constraint */
158
static inline int tcg_target_const_match(tcg_target_long val, TCGType type,
159
const TCGArgConstraint *arg_ct)
160
@@ -XXX,XX +XXX,XX @@ static void tcg_target_init(TCGContext *s)
161
}
162
#endif
163
164
- tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffff;
165
- tcg_target_available_regs[TCG_TYPE_I64] = ALL_64;
166
+ tcg_target_available_regs[TCG_TYPE_I32] = ALL_GENERAL_REGS;
167
+ tcg_target_available_regs[TCG_TYPE_I64] = ALL_GENERAL_REGS64;
168
169
tcg_target_call_clobber_regs = 0;
170
tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_G1);
171
--
37
--
172
2.25.1
38
2.43.0
173
39
174
40
diff view generated by jsdifflib
[PULL 06/24] tcg/arm: Split out target constraints to tcg-target-con-str.h
[PULL 13/24] include/exec: Use uintptr_t in CPUTLBEntry
1
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
1
Since we no longer support 64-bit guests on 32-bit hosts,
2
we can use a 32-bit type on a 32-bit host. This shrinks
3
the size of the structure to 16 bytes on a 32-bit host.
4
5
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
3
---
7
---
4
tcg/arm/tcg-target-con-str.h | 22 +++++++++++
8
include/exec/tlb-common.h | 10 +++++-----
5
tcg/arm/tcg-target.h | 1 +
9
accel/tcg/cputlb.c | 21 ++++-----------------
6
tcg/arm/tcg-target.c.inc | 74 +++++++++---------------------------
10
tcg/arm/tcg-target.c.inc | 1 -
7
3 files changed, 41 insertions(+), 56 deletions(-)
11
tcg/mips/tcg-target.c.inc | 12 +++++-------
8
create mode 100644 tcg/arm/tcg-target-con-str.h
12
tcg/ppc/tcg-target.c.inc | 21 +++++----------------
13
5 files changed, 19 insertions(+), 46 deletions(-)
9
14
10
diff --git a/tcg/arm/tcg-target-con-str.h b/tcg/arm/tcg-target-con-str.h
15
diff --git a/include/exec/tlb-common.h b/include/exec/tlb-common.h
11
new file mode 100644
16
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX
17
--- a/include/exec/tlb-common.h
13
--- /dev/null
18
+++ b/include/exec/tlb-common.h
14
+++ b/tcg/arm/tcg-target-con-str.h
15
@@ -XXX,XX +XXX,XX @@
19
@@ -XXX,XX +XXX,XX @@
16
+/* SPDX-License-Identifier: MIT */
20
#ifndef EXEC_TLB_COMMON_H
17
+/*
21
#define EXEC_TLB_COMMON_H 1
18
+ * Define Arm target-specific operand constraints.
22
19
+ * Copyright (c) 2021 Linaro
23
-#define CPU_TLB_ENTRY_BITS 5
20
+ */
24
+#define CPU_TLB_ENTRY_BITS (HOST_LONG_BITS == 32 ? 4 : 5)
21
+
25
22
+/*
26
/* Minimalized TLB entry for use by TCG fast path. */
23
+ * Define constraint letters for register sets:
27
typedef union CPUTLBEntry {
24
+ * REGS(letter, register_mask)
28
struct {
25
+ */
29
- uint64_t addr_read;
26
+REGS('r', ALL_GENERAL_REGS)
30
- uint64_t addr_write;
27
+REGS('l', ALL_QLOAD_REGS)
31
- uint64_t addr_code;
28
+REGS('s', ALL_QSTORE_REGS)
32
+ uintptr_t addr_read;
29
+
33
+ uintptr_t addr_write;
30
+/*
34
+ uintptr_t addr_code;
31
+ * Define constraint letters for constants:
35
/*
32
+ * CONST(letter, TCG_CT_CONST_* bit set)
36
* Addend to virtual address to get host address. IO accesses
33
+ */
37
* use the corresponding iotlb value.
34
+CONST('I', TCG_CT_CONST_ARM)
38
@@ -XXX,XX +XXX,XX @@ typedef union CPUTLBEntry {
35
+CONST('K', TCG_CT_CONST_INV)
39
* Padding to get a power of two size, as well as index
36
+CONST('N', TCG_CT_CONST_NEG)
40
* access to addr_{read,write,code}.
37
+CONST('Z', TCG_CT_CONST_ZERO)
41
*/
38
diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
42
- uint64_t addr_idx[(1 << CPU_TLB_ENTRY_BITS) / sizeof(uint64_t)];
43
+ uintptr_t addr_idx[(1 << CPU_TLB_ENTRY_BITS) / sizeof(uintptr_t)];
44
} CPUTLBEntry;
45
46
QEMU_BUILD_BUG_ON(sizeof(CPUTLBEntry) != (1 << CPU_TLB_ENTRY_BITS));
47
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
39
index XXXXXXX..XXXXXXX 100644
48
index XXXXXXX..XXXXXXX 100644
40
--- a/tcg/arm/tcg-target.h
49
--- a/accel/tcg/cputlb.c
41
+++ b/tcg/arm/tcg-target.h
50
+++ b/accel/tcg/cputlb.c
42
@@ -XXX,XX +XXX,XX @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t);
51
@@ -XXX,XX +XXX,XX @@ static inline uint64_t tlb_read_idx(const CPUTLBEntry *entry,
43
#define TCG_TARGET_NEED_LDST_LABELS
52
{
44
#endif
53
/* Do not rearrange the CPUTLBEntry structure members. */
45
#define TCG_TARGET_NEED_POOL_LABELS
54
QEMU_BUILD_BUG_ON(offsetof(CPUTLBEntry, addr_read) !=
46
+#define TCG_TARGET_CON_STR_H
55
- MMU_DATA_LOAD * sizeof(uint64_t));
47
56
+ MMU_DATA_LOAD * sizeof(uintptr_t));
48
#endif
57
QEMU_BUILD_BUG_ON(offsetof(CPUTLBEntry, addr_write) !=
58
- MMU_DATA_STORE * sizeof(uint64_t));
59
+ MMU_DATA_STORE * sizeof(uintptr_t));
60
QEMU_BUILD_BUG_ON(offsetof(CPUTLBEntry, addr_code) !=
61
- MMU_INST_FETCH * sizeof(uint64_t));
62
+ MMU_INST_FETCH * sizeof(uintptr_t));
63
64
-#if TARGET_LONG_BITS == 32
65
- /* Use qatomic_read, in case of addr_write; only care about low bits. */
66
- const uint32_t *ptr = (uint32_t *)&entry->addr_idx[access_type];
67
- ptr += HOST_BIG_ENDIAN;
68
- return qatomic_read(ptr);
69
-#else
70
- const uint64_t *ptr = &entry->addr_idx[access_type];
71
+ const uintptr_t *ptr = &entry->addr_idx[access_type];
72
/* ofs might correspond to .addr_write, so use qatomic_read */
73
return qatomic_read(ptr);
74
-#endif
75
}
76
77
static inline uint64_t tlb_addr_write(const CPUTLBEntry *entry)
78
@@ -XXX,XX +XXX,XX @@ static void tlb_reset_dirty_range_locked(CPUTLBEntry *tlb_entry,
79
addr &= TARGET_PAGE_MASK;
80
addr += tlb_entry->addend;
81
if ((addr - start) < length) {
82
-#if TARGET_LONG_BITS == 32
83
- uint32_t *ptr_write = (uint32_t *)&tlb_entry->addr_write;
84
- ptr_write += HOST_BIG_ENDIAN;
85
- qatomic_set(ptr_write, *ptr_write | TLB_NOTDIRTY);
86
-#else
87
qatomic_set(&tlb_entry->addr_write,
88
tlb_entry->addr_write | TLB_NOTDIRTY);
89
-#endif
90
}
91
}
92
}
49
diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
93
diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
50
index XXXXXXX..XXXXXXX 100644
94
index XXXXXXX..XXXXXXX 100644
51
--- a/tcg/arm/tcg-target.c.inc
95
--- a/tcg/arm/tcg-target.c.inc
52
+++ b/tcg/arm/tcg-target.c.inc
96
+++ b/tcg/arm/tcg-target.c.inc
53
@@ -XXX,XX +XXX,XX @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
97
@@ -XXX,XX +XXX,XX @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
54
#define TCG_CT_CONST_NEG 0x400
98
* Add the tlb_table pointer, creating the CPUTLBEntry address in R1.
55
#define TCG_CT_CONST_ZERO 0x800
99
* Load the tlb comparator into R2 and the fast path addend into R1.
56
100
*/
57
-/* parse target specific constraints */
101
- QEMU_BUILD_BUG_ON(HOST_BIG_ENDIAN);
58
-static const char *target_parse_constraint(TCGArgConstraint *ct,
102
if (cmp_off == 0) {
59
- const char *ct_str, TCGType type)
103
tcg_out_ld32_rwb(s, COND_AL, TCG_REG_R2, TCG_REG_R1, TCG_REG_R0);
60
-{
104
} else {
61
- switch (*ct_str++) {
105
diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc
62
- case 'I':
106
index XXXXXXX..XXXXXXX 100644
63
- ct->ct |= TCG_CT_CONST_ARM;
107
--- a/tcg/mips/tcg-target.c.inc
64
- break;
108
+++ b/tcg/mips/tcg-target.c.inc
65
- case 'K':
109
@@ -XXX,XX +XXX,XX @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
66
- ct->ct |= TCG_CT_CONST_INV;
110
/* Add the tlb_table pointer, creating the CPUTLBEntry address. */
67
- break;
111
tcg_out_opc_reg(s, ALIAS_PADD, TCG_TMP3, TCG_TMP3, TCG_TMP1);
68
- case 'N': /* The gcc constraint letter is L, already used here. */
112
69
- ct->ct |= TCG_CT_CONST_NEG;
113
- if (TCG_TARGET_REG_BITS == 32 || addr_type == TCG_TYPE_I32) {
70
- break;
114
- /* Load the (low half) tlb comparator. */
71
- case 'Z':
115
+ /* Load the tlb comparator. */
72
- ct->ct |= TCG_CT_CONST_ZERO;
116
+ if (TCG_TARGET_REG_BITS == 64 && addr_type == TCG_TYPE_I32) {
73
- break;
117
tcg_out_ld(s, TCG_TYPE_I32, TCG_TMP0, TCG_TMP3,
74
+#define ALL_GENERAL_REGS 0xffffu
118
cmp_off + HOST_BIG_ENDIAN * 4);
75
119
} else {
76
- case 'r':
120
- tcg_out_ld(s, TCG_TYPE_I64, TCG_TMP0, TCG_TMP3, cmp_off);
77
- ct->regs = 0xffff;
121
+ tcg_out_ld(s, TCG_TYPE_REG, TCG_TMP0, TCG_TMP3, cmp_off);
78
- break;
122
}
79
-
123
80
- /* qemu_ld address */
124
- if (TCG_TARGET_REG_BITS == 64 || addr_type == TCG_TYPE_I32) {
81
- case 'l':
125
- /* Load the tlb addend for the fast path. */
82
- ct->regs = 0xffff;
126
- tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP3, TCG_TMP3, add_off);
83
+/*
127
- }
84
+ * r0-r2 will be overwritten when reading the tlb entry (softmmu only)
128
+ /* Load the tlb addend for the fast path. */
85
+ * and r0-r1 doing the byte swapping, so don't use these.
129
+ tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP3, TCG_TMP3, add_off);
86
+ * r3 is removed for softmmu to avoid clashes with helper arguments.
130
87
+ */
131
/*
88
#ifdef CONFIG_SOFTMMU
132
* Mask the page bits, keeping the alignment bits to compare against.
89
- /* r0-r2,lr will be overwritten when reading the tlb entry,
133
diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc
90
- so don't use these. */
134
index XXXXXXX..XXXXXXX 100644
91
- tcg_regset_reset_reg(ct->regs, TCG_REG_R0);
135
--- a/tcg/ppc/tcg-target.c.inc
92
- tcg_regset_reset_reg(ct->regs, TCG_REG_R1);
136
+++ b/tcg/ppc/tcg-target.c.inc
93
- tcg_regset_reset_reg(ct->regs, TCG_REG_R2);
137
@@ -XXX,XX +XXX,XX @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
94
- tcg_regset_reset_reg(ct->regs, TCG_REG_R3);
138
tcg_out32(s, AND | SAB(TCG_REG_TMP1, TCG_REG_TMP1, TCG_REG_R0));
95
- tcg_regset_reset_reg(ct->regs, TCG_REG_R14);
139
96
+#define ALL_QLOAD_REGS \
140
/*
97
+ (ALL_GENERAL_REGS & ~((1 << TCG_REG_R0) | (1 << TCG_REG_R1) | \
141
- * Load the (low part) TLB comparator into TMP2.
98
+ (1 << TCG_REG_R2) | (1 << TCG_REG_R3) | \
142
+ * Load the TLB comparator into TMP2.
99
+ (1 << TCG_REG_R14)))
143
* For 64-bit host, always load the entire 64-bit slot for simplicity.
100
+#define ALL_QSTORE_REGS \
144
* We will ignore the high bits with tcg_out_cmp(..., addr_type).
101
+ (ALL_GENERAL_REGS & ~((1 << TCG_REG_R0) | (1 << TCG_REG_R1) | \
145
*/
102
+ (1 << TCG_REG_R2) | (1 << TCG_REG_R14) | \
146
- if (TCG_TARGET_REG_BITS == 64) {
103
+ ((TARGET_LONG_BITS == 64) << TCG_REG_R3)))
147
- if (cmp_off == 0) {
104
+#else
148
- tcg_out32(s, LDUX | TAB(TCG_REG_TMP2,
105
+#define ALL_QLOAD_REGS ALL_GENERAL_REGS
149
- TCG_REG_TMP1, TCG_REG_TMP2));
106
+#define ALL_QSTORE_REGS \
150
- } else {
107
+ (ALL_GENERAL_REGS & ~((1 << TCG_REG_R0) | (1 << TCG_REG_R1)))
151
- tcg_out32(s, ADD | TAB(TCG_REG_TMP1,
108
#endif
152
- TCG_REG_TMP1, TCG_REG_TMP2));
109
- break;
153
- tcg_out_ld(s, TCG_TYPE_I64, TCG_REG_TMP2,
110
-
154
- TCG_REG_TMP1, cmp_off);
111
- /* qemu_st address & data */
155
- }
112
- case 's':
156
- } else if (cmp_off == 0 && !HOST_BIG_ENDIAN) {
113
- ct->regs = 0xffff;
157
- tcg_out32(s, LWZUX | TAB(TCG_REG_TMP2,
114
- /* r0-r2 will be overwritten when reading the tlb entry (softmmu only)
158
- TCG_REG_TMP1, TCG_REG_TMP2));
115
- and r0-r1 doing the byte swapping, so don't use these. */
159
+ if (cmp_off == 0) {
116
- tcg_regset_reset_reg(ct->regs, TCG_REG_R0);
160
+ tcg_out32(s, (TCG_TARGET_REG_BITS == 64 ? LDUX : LWZUX)
117
- tcg_regset_reset_reg(ct->regs, TCG_REG_R1);
161
+ | TAB(TCG_REG_TMP2, TCG_REG_TMP1, TCG_REG_TMP2));
118
-#if defined(CONFIG_SOFTMMU)
162
} else {
119
- /* Avoid clashes with registers being used for helper args */
163
tcg_out32(s, ADD | TAB(TCG_REG_TMP1, TCG_REG_TMP1, TCG_REG_TMP2));
120
- tcg_regset_reset_reg(ct->regs, TCG_REG_R2);
164
- tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_TMP2, TCG_REG_TMP1,
121
-#if TARGET_LONG_BITS == 64
165
- cmp_off + 4 * HOST_BIG_ENDIAN);
122
- /* Avoid clashes with registers being used for helper args */
166
+ tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP2, TCG_REG_TMP1, cmp_off);
123
- tcg_regset_reset_reg(ct->regs, TCG_REG_R3);
167
}
124
-#endif
168
125
- tcg_regset_reset_reg(ct->regs, TCG_REG_R14);
169
/*
126
-#endif
127
- break;
128
-
129
- default:
130
- return NULL;
131
- }
132
- return ct_str;
133
-}
134
135
static inline uint32_t rotl(uint32_t val, int n)
136
{
137
--
170
--
138
2.25.1
171
2.43.0
139
172
140
173
diff view generated by jsdifflib
[PULL 14/24] tcg: Remove TCG_TARGET_CON_STR_H
[PULL 14/24] tcg: Introduce the 'z' constraint for a hardware zero register
1
All backends have now been converted to tcg-target-con-str.h,
1
For loongarch, mips, riscv and sparc, a zero register is
2
so we can remove the fallback code.
2
available all the time. For aarch64, register index 31
3
depends on context: sometimes it is the stack pointer,
4
and sometimes it is the zero register.
3
5
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Introduce a new general-purpose constraint which maps 0
5
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
7
to TCG_REG_ZERO, if defined. This differs from existing
8
constant constraints in that const_arg[*] is recorded as
9
false, indicating that the value is in a register.
10
11
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
---
13
---
8
tcg/aarch64/tcg-target.h | 1 -
14
include/tcg/tcg.h | 3 ++-
9
tcg/arm/tcg-target.h | 1 -
15
tcg/aarch64/tcg-target.h | 2 ++
10
tcg/i386/tcg-target.h | 1 -
16
tcg/loongarch64/tcg-target.h | 2 ++
11
tcg/mips/tcg-target.h | 1 -
17
tcg/mips/tcg-target.h | 2 ++
12
tcg/ppc/tcg-target.h | 1 -
18
tcg/riscv/tcg-target.h | 2 ++
13
tcg/riscv/tcg-target.h | 1 -
19
tcg/sparc64/tcg-target.h | 3 ++-
14
tcg/s390/tcg-target.h | 1 -
20
tcg/tcg.c | 29 ++++++++++++++++++++++-------
15
tcg/sparc/tcg-target.h | 1 -
21
docs/devel/tcg-ops.rst | 4 +++-
16
tcg/tci/tcg-target.h | 2 --
22
8 files changed, 37 insertions(+), 10 deletions(-)
17
tcg/tcg.c | 16 ----------------
18
10 files changed, 26 deletions(-)
19
23
24
diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h
25
index XXXXXXX..XXXXXXX 100644
26
--- a/include/tcg/tcg.h
27
+++ b/include/tcg/tcg.h
28
@@ -XXX,XX +XXX,XX @@ void tb_target_set_jmp_target(const TranslationBlock *, int,
29
30
void tcg_set_frame(TCGContext *s, TCGReg reg, intptr_t start, intptr_t size);
31
32
-#define TCG_CT_CONST 1 /* any constant of register size */
33
+#define TCG_CT_CONST 1 /* any constant of register size */
34
+#define TCG_CT_REG_ZERO 2 /* zero, in TCG_REG_ZERO */
35
36
typedef struct TCGArgConstraint {
37
unsigned ct : 16;
20
diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h
38
diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h
21
index XXXXXXX..XXXXXXX 100644
39
index XXXXXXX..XXXXXXX 100644
22
--- a/tcg/aarch64/tcg-target.h
40
--- a/tcg/aarch64/tcg-target.h
23
+++ b/tcg/aarch64/tcg-target.h
41
+++ b/tcg/aarch64/tcg-target.h
24
@@ -XXX,XX +XXX,XX @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t);
42
@@ -XXX,XX +XXX,XX @@ typedef enum {
25
#define TCG_TARGET_NEED_LDST_LABELS
43
TCG_AREG0 = TCG_REG_X19,
26
#endif
44
} TCGReg;
27
#define TCG_TARGET_NEED_POOL_LABELS
45
28
-#define TCG_TARGET_CON_STR_H
46
+#define TCG_REG_ZERO TCG_REG_XZR
47
+
48
#define TCG_TARGET_NB_REGS 64
29
49
30
#endif /* AARCH64_TCG_TARGET_H */
50
#endif /* AARCH64_TCG_TARGET_H */
31
diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
51
diff --git a/tcg/loongarch64/tcg-target.h b/tcg/loongarch64/tcg-target.h
32
index XXXXXXX..XXXXXXX 100644
52
index XXXXXXX..XXXXXXX 100644
33
--- a/tcg/arm/tcg-target.h
53
--- a/tcg/loongarch64/tcg-target.h
34
+++ b/tcg/arm/tcg-target.h
54
+++ b/tcg/loongarch64/tcg-target.h
35
@@ -XXX,XX +XXX,XX @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t);
55
@@ -XXX,XX +XXX,XX @@ typedef enum {
36
#define TCG_TARGET_NEED_LDST_LABELS
56
TCG_VEC_TMP0 = TCG_REG_V23,
37
#endif
57
} TCGReg;
38
#define TCG_TARGET_NEED_POOL_LABELS
58
39
-#define TCG_TARGET_CON_STR_H
59
+#define TCG_REG_ZERO TCG_REG_ZERO
40
60
+
41
#endif
61
#endif /* LOONGARCH_TCG_TARGET_H */
42
diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h
43
index XXXXXXX..XXXXXXX 100644
44
--- a/tcg/i386/tcg-target.h
45
+++ b/tcg/i386/tcg-target.h
46
@@ -XXX,XX +XXX,XX @@ static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_rx,
47
#define TCG_TARGET_NEED_LDST_LABELS
48
#endif
49
#define TCG_TARGET_NEED_POOL_LABELS
50
-#define TCG_TARGET_CON_STR_H
51
52
#endif
53
diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h
62
diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h
54
index XXXXXXX..XXXXXXX 100644
63
index XXXXXXX..XXXXXXX 100644
55
--- a/tcg/mips/tcg-target.h
64
--- a/tcg/mips/tcg-target.h
56
+++ b/tcg/mips/tcg-target.h
65
+++ b/tcg/mips/tcg-target.h
57
@@ -XXX,XX +XXX,XX @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t);
66
@@ -XXX,XX +XXX,XX @@ typedef enum {
58
#ifdef CONFIG_SOFTMMU
67
TCG_AREG0 = TCG_REG_S8,
59
#define TCG_TARGET_NEED_LDST_LABELS
68
} TCGReg;
60
#endif
69
61
-#define TCG_TARGET_CON_STR_H
70
+#define TCG_REG_ZERO TCG_REG_ZERO
62
71
+
63
#endif
64
diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h
65
index XXXXXXX..XXXXXXX 100644
66
--- a/tcg/ppc/tcg-target.h
67
+++ b/tcg/ppc/tcg-target.h
68
@@ -XXX,XX +XXX,XX @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t);
69
#define TCG_TARGET_NEED_LDST_LABELS
70
#endif
71
#define TCG_TARGET_NEED_POOL_LABELS
72
-#define TCG_TARGET_CON_STR_H
73
74
#endif
72
#endif
75
diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h
73
diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h
76
index XXXXXXX..XXXXXXX 100644
74
index XXXXXXX..XXXXXXX 100644
77
--- a/tcg/riscv/tcg-target.h
75
--- a/tcg/riscv/tcg-target.h
78
+++ b/tcg/riscv/tcg-target.h
76
+++ b/tcg/riscv/tcg-target.h
79
@@ -XXX,XX +XXX,XX @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t);
77
@@ -XXX,XX +XXX,XX @@ typedef enum {
80
#define TCG_TARGET_NEED_POOL_LABELS
78
TCG_REG_TMP2 = TCG_REG_T4,
81
79
} TCGReg;
82
#define TCG_TARGET_HAS_MEMORY_BSWAP 0
80
83
-#define TCG_TARGET_CON_STR_H
81
+#define TCG_REG_ZERO TCG_REG_ZERO
84
82
+
85
#endif
83
#endif
86
diff --git a/tcg/s390/tcg-target.h b/tcg/s390/tcg-target.h
84
diff --git a/tcg/sparc64/tcg-target.h b/tcg/sparc64/tcg-target.h
87
index XXXXXXX..XXXXXXX 100644
85
index XXXXXXX..XXXXXXX 100644
88
--- a/tcg/s390/tcg-target.h
86
--- a/tcg/sparc64/tcg-target.h
89
+++ b/tcg/s390/tcg-target.h
87
+++ b/tcg/sparc64/tcg-target.h
90
@@ -XXX,XX +XXX,XX @@ static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_rx,
88
@@ -XXX,XX +XXX,XX @@ typedef enum {
91
#define TCG_TARGET_NEED_LDST_LABELS
89
TCG_REG_I7,
90
} TCGReg;
91
92
-#define TCG_AREG0 TCG_REG_I0
93
+#define TCG_AREG0 TCG_REG_I0
94
+#define TCG_REG_ZERO TCG_REG_G0
95
92
#endif
96
#endif
93
#define TCG_TARGET_NEED_POOL_LABELS
94
-#define TCG_TARGET_CON_STR_H
95
96
#endif
97
diff --git a/tcg/sparc/tcg-target.h b/tcg/sparc/tcg-target.h
98
index XXXXXXX..XXXXXXX 100644
99
--- a/tcg/sparc/tcg-target.h
100
+++ b/tcg/sparc/tcg-target.h
101
@@ -XXX,XX +XXX,XX @@ extern bool use_vis3_instructions;
102
void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t);
103
104
#define TCG_TARGET_NEED_POOL_LABELS
105
-#define TCG_TARGET_CON_STR_H
106
107
#endif
108
diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h
109
index XXXXXXX..XXXXXXX 100644
110
--- a/tcg/tci/tcg-target.h
111
+++ b/tcg/tci/tcg-target.h
112
@@ -XXX,XX +XXX,XX @@ static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_rx,
113
/* no need to flush icache explicitly */
114
}
115
116
-#define TCG_TARGET_CON_STR_H
117
-
118
#endif /* TCG_TARGET_H */
119
diff --git a/tcg/tcg.c b/tcg/tcg.c
97
diff --git a/tcg/tcg.c b/tcg/tcg.c
120
index XXXXXXX..XXXXXXX 100644
98
index XXXXXXX..XXXXXXX 100644
121
--- a/tcg/tcg.c
99
--- a/tcg/tcg.c
122
+++ b/tcg/tcg.c
100
+++ b/tcg/tcg.c
123
@@ -XXX,XX +XXX,XX @@ static void tcg_register_jit_int(const void *buf, size_t size,
101
@@ -XXX,XX +XXX,XX @@ static void process_constraint_sets(void)
124
__attribute__((unused));
102
case 'i':
125
103
args_ct[i].ct |= TCG_CT_CONST;
126
/* Forward declarations for functions declared and used in tcg-target.c.inc. */
127
-#ifndef TCG_TARGET_CON_STR_H
128
-static const char *target_parse_constraint(TCGArgConstraint *ct,
129
- const char *ct_str, TCGType type);
130
-#endif
131
static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg1,
132
intptr_t arg2);
133
static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg);
134
@@ -XXX,XX +XXX,XX @@ static void process_op_defs(TCGContext *s)
135
ct_str++;
136
break;
104
break;
137
105
+#ifdef TCG_REG_ZERO
138
-#ifdef TCG_TARGET_CON_STR_H
106
+ case 'z':
107
+ args_ct[i].ct |= TCG_CT_REG_ZERO;
108
+ break;
109
+#endif
110
139
/* Include all of the target-specific constraints. */
111
/* Include all of the target-specific constraints. */
140
112
141
#undef CONST
113
@@ -XXX,XX +XXX,XX @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
142
@@ -XXX,XX +XXX,XX @@ static void process_op_defs(TCGContext *s)
114
arg_ct = &args_ct[i];
143
default:
115
ts = arg_temp(arg);
144
/* Typo in TCGTargetOpDef constraint. */
116
145
g_assert_not_reached();
117
- if (ts->val_type == TEMP_VAL_CONST
146
-#else
118
- && tcg_target_const_match(ts->val, arg_ct->ct, ts->type,
147
- default:
119
- op_cond, TCGOP_VECE(op))) {
148
- {
120
- /* constant is OK for instruction */
149
- TCGType type = (def->flags & TCG_OPF_64BIT
121
- const_args[i] = 1;
150
- ? TCG_TYPE_I64 : TCG_TYPE_I32);
122
- new_args[i] = ts->val;
151
- ct_str = target_parse_constraint(&def->args_ct[i],
123
- continue;
152
- ct_str, type);
124
+ if (ts->val_type == TEMP_VAL_CONST) {
153
- /* Typo in TCGTargetOpDef constraint. */
125
+#ifdef TCG_REG_ZERO
154
- tcg_debug_assert(ct_str != NULL);
126
+ if (ts->val == 0 && (arg_ct->ct & TCG_CT_REG_ZERO)) {
155
- }
127
+ /* Hardware zero register: indicate register via non-const. */
156
-#endif
128
+ const_args[i] = 0;
157
}
129
+ new_args[i] = TCG_REG_ZERO;
158
}
130
+ continue;
131
+ }
132
+#endif
133
+
134
+ if (tcg_target_const_match(ts->val, arg_ct->ct, ts->type,
135
+ op_cond, TCGOP_VECE(op))) {
136
+ /* constant is OK for instruction */
137
+ const_args[i] = 1;
138
+ new_args[i] = ts->val;
139
+ continue;
140
+ }
159
}
141
}
142
143
reg = ts->reg;
144
diff --git a/docs/devel/tcg-ops.rst b/docs/devel/tcg-ops.rst
145
index XXXXXXX..XXXXXXX 100644
146
--- a/docs/devel/tcg-ops.rst
147
+++ b/docs/devel/tcg-ops.rst
148
@@ -XXX,XX +XXX,XX @@ operation uses a constant input constraint which does not allow all
149
constants, it must also accept registers in order to have a fallback.
150
The constraint '``i``' is defined generically to accept any constant.
151
The constraint '``r``' is not defined generically, but is consistently
152
-used by each backend to indicate all registers.
153
+used by each backend to indicate all registers. If ``TCG_REG_ZERO``
154
+is defined by the backend, the constraint '``z``' is defined generically
155
+to map constant 0 to the hardware zero register.
156
157
The movi_i32 and movi_i64 operations must accept any constants.
158
160
--
159
--
161
2.25.1
160
2.43.0
162
161
163
162
diff view generated by jsdifflib
[PULL 16/24] tcg/aarch64: Split out constraint sets to tcg-target-con-set.h
[PULL 15/24] tcg/aarch64: Use 'z' constraint
1
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
1
Note that 'Z' is still used for addsub2.
2
2
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
3
---
4
---
4
tcg/aarch64/tcg-target-con-set.h | 36 +++++++++++++
5
tcg/aarch64/tcg-target-con-set.h | 12 ++++-----
5
tcg/aarch64/tcg-target.h | 1 +
6
tcg/aarch64/tcg-target.c.inc | 46 ++++++++++++++------------------
6
tcg/aarch64/tcg-target.c.inc | 86 +++++++++++---------------------
7
2 files changed, 26 insertions(+), 32 deletions(-)
7
3 files changed, 65 insertions(+), 58 deletions(-)
8
create mode 100644 tcg/aarch64/tcg-target-con-set.h
9
8
10
diff --git a/tcg/aarch64/tcg-target-con-set.h b/tcg/aarch64/tcg-target-con-set.h
9
diff --git a/tcg/aarch64/tcg-target-con-set.h b/tcg/aarch64/tcg-target-con-set.h
11
new file mode 100644
10
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX
11
--- a/tcg/aarch64/tcg-target-con-set.h
13
--- /dev/null
14
+++ b/tcg/aarch64/tcg-target-con-set.h
12
+++ b/tcg/aarch64/tcg-target-con-set.h
15
@@ -XXX,XX +XXX,XX @@
13
@@ -XXX,XX +XXX,XX @@
16
+/* SPDX-License-Identifier: GPL-2.0-or-later */
14
*/
17
+/*
15
C_O0_I1(r)
18
+ * Define AArch64 target-specific constraint sets.
16
C_O0_I2(r, rC)
19
+ * Copyright (c) 2021 Linaro
17
-C_O0_I2(rZ, r)
20
+ */
18
+C_O0_I2(rz, r)
21
+
19
C_O0_I2(w, r)
22
+/*
20
-C_O0_I3(rZ, rZ, r)
23
+ * C_On_Im(...) defines a constraint set with <n> outputs and <m> inputs.
21
+C_O0_I3(rz, rz, r)
24
+ * Each operand should be a sequence of constraint letters as defined by
22
C_O1_I1(r, r)
25
+ * tcg-target-con-str.h; the constraint combination is inclusive or.
23
C_O1_I1(w, r)
26
+ */
24
C_O1_I1(w, w)
27
+C_O0_I1(r)
25
C_O1_I1(w, wr)
28
+C_O0_I2(lZ, l)
26
-C_O1_I2(r, 0, rZ)
29
+C_O0_I2(r, rA)
27
+C_O1_I2(r, 0, rz)
30
+C_O0_I2(rZ, r)
28
C_O1_I2(r, r, r)
31
+C_O0_I2(w, r)
29
C_O1_I2(r, r, rA)
32
+C_O1_I1(r, l)
30
C_O1_I2(r, r, rAL)
33
+C_O1_I1(r, r)
31
C_O1_I2(r, r, rC)
34
+C_O1_I1(w, r)
32
C_O1_I2(r, r, ri)
35
+C_O1_I1(w, w)
33
C_O1_I2(r, r, rL)
36
+C_O1_I1(w, wr)
34
-C_O1_I2(r, rZ, rZ)
37
+C_O1_I2(r, 0, rZ)
35
+C_O1_I2(r, rz, rz)
38
+C_O1_I2(r, r, r)
36
C_O1_I2(w, 0, w)
39
+C_O1_I2(r, r, rA)
37
C_O1_I2(w, w, w)
40
+C_O1_I2(r, r, rAL)
38
C_O1_I2(w, w, wN)
41
+C_O1_I2(r, r, ri)
39
C_O1_I2(w, w, wO)
42
+C_O1_I2(r, r, rL)
40
C_O1_I2(w, w, wZ)
43
+C_O1_I2(r, rZ, rZ)
41
C_O1_I3(w, w, w, w)
44
+C_O1_I2(w, 0, w)
42
-C_O1_I4(r, r, rC, rZ, rZ)
45
+C_O1_I2(w, w, w)
43
+C_O1_I4(r, r, rC, rz, rz)
46
+C_O1_I2(w, w, wN)
44
C_O2_I1(r, r, r)
47
+C_O1_I2(w, w, wO)
45
-C_O2_I4(r, r, rZ, rZ, rA, rMZ)
48
+C_O1_I2(w, w, wZ)
46
+C_O2_I4(r, r, rz, rz, rA, rMZ)
49
+C_O1_I3(w, w, w, w)
50
+C_O1_I4(r, r, rA, rZ, rZ)
51
+C_O2_I4(r, r, rZ, rZ, rA, rMZ)
52
diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h
53
index XXXXXXX..XXXXXXX 100644
54
--- a/tcg/aarch64/tcg-target.h
55
+++ b/tcg/aarch64/tcg-target.h
56
@@ -XXX,XX +XXX,XX @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t);
57
#define TCG_TARGET_NEED_LDST_LABELS
58
#endif
59
#define TCG_TARGET_NEED_POOL_LABELS
60
+#define TCG_TARGET_CON_SET_H
61
62
#endif /* AARCH64_TCG_TARGET_H */
63
diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc
47
diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc
64
index XXXXXXX..XXXXXXX 100644
48
index XXXXXXX..XXXXXXX 100644
65
--- a/tcg/aarch64/tcg-target.c.inc
49
--- a/tcg/aarch64/tcg-target.c.inc
66
+++ b/tcg/aarch64/tcg-target.c.inc
50
+++ b/tcg/aarch64/tcg-target.c.inc
67
@@ -XXX,XX +XXX,XX @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece,
51
@@ -XXX,XX +XXX,XX @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType ext,
68
va_end(va);
52
TCGArg a2 = args[2];
53
int c2 = const_args[2];
54
55
- /* Some operands are defined with "rZ" constraint, a register or
56
- the zero register. These need not actually test args[I] == 0. */
57
-#define REG0(I) (const_args[I] ? TCG_REG_XZR : (TCGReg)args[I])
58
-
59
switch (opc) {
60
case INDEX_op_goto_ptr:
61
tcg_out_insn(s, 3207, BR, a0);
62
@@ -XXX,XX +XXX,XX @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType ext,
63
64
case INDEX_op_st8_i32:
65
case INDEX_op_st8_i64:
66
- tcg_out_ldst(s, I3312_STRB, REG0(0), a1, a2, 0);
67
+ tcg_out_ldst(s, I3312_STRB, a0, a1, a2, 0);
68
break;
69
case INDEX_op_st16_i32:
70
case INDEX_op_st16_i64:
71
- tcg_out_ldst(s, I3312_STRH, REG0(0), a1, a2, 1);
72
+ tcg_out_ldst(s, I3312_STRH, a0, a1, a2, 1);
73
break;
74
case INDEX_op_st_i32:
75
case INDEX_op_st32_i64:
76
- tcg_out_ldst(s, I3312_STRW, REG0(0), a1, a2, 2);
77
+ tcg_out_ldst(s, I3312_STRW, a0, a1, a2, 2);
78
break;
79
case INDEX_op_st_i64:
80
- tcg_out_ldst(s, I3312_STRX, REG0(0), a1, a2, 3);
81
+ tcg_out_ldst(s, I3312_STRX, a0, a1, a2, 3);
82
break;
83
84
case INDEX_op_add_i32:
85
@@ -XXX,XX +XXX,XX @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType ext,
86
/* FALLTHRU */
87
case INDEX_op_movcond_i64:
88
tcg_out_cmp(s, ext, args[5], a1, a2, c2);
89
- tcg_out_insn(s, 3506, CSEL, ext, a0, REG0(3), REG0(4), args[5]);
90
+ tcg_out_insn(s, 3506, CSEL, ext, a0, args[3], args[4], args[5]);
91
break;
92
93
case INDEX_op_qemu_ld_i32:
94
@@ -XXX,XX +XXX,XX @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType ext,
95
break;
96
case INDEX_op_qemu_st_i32:
97
case INDEX_op_qemu_st_i64:
98
- tcg_out_qemu_st(s, REG0(0), a1, a2, ext);
99
+ tcg_out_qemu_st(s, a0, a1, a2, ext);
100
break;
101
case INDEX_op_qemu_ld_i128:
102
tcg_out_qemu_ldst_i128(s, a0, a1, a2, args[3], true);
103
break;
104
case INDEX_op_qemu_st_i128:
105
- tcg_out_qemu_ldst_i128(s, REG0(0), REG0(1), a2, args[3], false);
106
+ tcg_out_qemu_ldst_i128(s, a0, a1, a2, args[3], false);
107
break;
108
109
case INDEX_op_bswap64_i64:
110
@@ -XXX,XX +XXX,XX @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType ext,
111
112
case INDEX_op_deposit_i64:
113
case INDEX_op_deposit_i32:
114
- tcg_out_dep(s, ext, a0, REG0(2), args[3], args[4]);
115
+ tcg_out_dep(s, ext, a0, a2, args[3], args[4]);
116
break;
117
118
case INDEX_op_extract_i64:
119
@@ -XXX,XX +XXX,XX @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType ext,
120
121
case INDEX_op_extract2_i64:
122
case INDEX_op_extract2_i32:
123
- tcg_out_extr(s, ext, a0, REG0(2), REG0(1), args[3]);
124
+ tcg_out_extr(s, ext, a0, a2, a1, args[3]);
125
break;
126
127
case INDEX_op_add2_i32:
128
- tcg_out_addsub2(s, TCG_TYPE_I32, a0, a1, REG0(2), REG0(3),
129
+ tcg_out_addsub2(s, TCG_TYPE_I32, a0, a1, a2, args[3],
130
(int32_t)args[4], args[5], const_args[4],
131
const_args[5], false);
132
break;
133
case INDEX_op_add2_i64:
134
- tcg_out_addsub2(s, TCG_TYPE_I64, a0, a1, REG0(2), REG0(3), args[4],
135
+ tcg_out_addsub2(s, TCG_TYPE_I64, a0, a1, a2, args[3], args[4],
136
args[5], const_args[4], const_args[5], false);
137
break;
138
case INDEX_op_sub2_i32:
139
- tcg_out_addsub2(s, TCG_TYPE_I32, a0, a1, REG0(2), REG0(3),
140
+ tcg_out_addsub2(s, TCG_TYPE_I32, a0, a1, a2, args[3],
141
(int32_t)args[4], args[5], const_args[4],
142
const_args[5], true);
143
break;
144
case INDEX_op_sub2_i64:
145
- tcg_out_addsub2(s, TCG_TYPE_I64, a0, a1, REG0(2), REG0(3), args[4],
146
+ tcg_out_addsub2(s, TCG_TYPE_I64, a0, a1, a2, args[3], args[4],
147
args[5], const_args[4], const_args[5], true);
148
break;
149
150
@@ -XXX,XX +XXX,XX @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType ext,
151
default:
152
g_assert_not_reached();
153
}
154
-
155
-#undef REG0
69
}
156
}
70
157
71
-static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
158
static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
72
+static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
159
@@ -XXX,XX +XXX,XX @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
73
{
74
- static const TCGTargetOpDef r = { .args_ct_str = { "r" } };
75
- static const TCGTargetOpDef r_r = { .args_ct_str = { "r", "r" } };
76
- static const TCGTargetOpDef w_w = { .args_ct_str = { "w", "w" } };
77
- static const TCGTargetOpDef w_r = { .args_ct_str = { "w", "r" } };
78
- static const TCGTargetOpDef w_wr = { .args_ct_str = { "w", "wr" } };
79
- static const TCGTargetOpDef r_l = { .args_ct_str = { "r", "l" } };
80
- static const TCGTargetOpDef r_rA = { .args_ct_str = { "r", "rA" } };
81
- static const TCGTargetOpDef rZ_r = { .args_ct_str = { "rZ", "r" } };
82
- static const TCGTargetOpDef lZ_l = { .args_ct_str = { "lZ", "l" } };
83
- static const TCGTargetOpDef r_r_r = { .args_ct_str = { "r", "r", "r" } };
84
- static const TCGTargetOpDef w_w_w = { .args_ct_str = { "w", "w", "w" } };
85
- static const TCGTargetOpDef w_0_w = { .args_ct_str = { "w", "0", "w" } };
86
- static const TCGTargetOpDef w_w_wO = { .args_ct_str = { "w", "w", "wO" } };
87
- static const TCGTargetOpDef w_w_wN = { .args_ct_str = { "w", "w", "wN" } };
88
- static const TCGTargetOpDef w_w_wZ = { .args_ct_str = { "w", "w", "wZ" } };
89
- static const TCGTargetOpDef r_r_ri = { .args_ct_str = { "r", "r", "ri" } };
90
- static const TCGTargetOpDef r_r_rA = { .args_ct_str = { "r", "r", "rA" } };
91
- static const TCGTargetOpDef r_r_rL = { .args_ct_str = { "r", "r", "rL" } };
92
- static const TCGTargetOpDef r_r_rAL
93
- = { .args_ct_str = { "r", "r", "rAL" } };
94
- static const TCGTargetOpDef dep
95
- = { .args_ct_str = { "r", "0", "rZ" } };
96
- static const TCGTargetOpDef ext2
97
- = { .args_ct_str = { "r", "rZ", "rZ" } };
98
- static const TCGTargetOpDef movc
99
- = { .args_ct_str = { "r", "r", "rA", "rZ", "rZ" } };
100
- static const TCGTargetOpDef add2
101
- = { .args_ct_str = { "r", "r", "rZ", "rZ", "rA", "rMZ" } };
102
- static const TCGTargetOpDef w_w_w_w
103
- = { .args_ct_str = { "w", "w", "w", "w" } };
104
-
105
switch (op) {
106
case INDEX_op_goto_ptr:
107
- return &r;
108
+ return C_O0_I1(r);
109
110
case INDEX_op_ld8u_i32:
111
case INDEX_op_ld8s_i32:
112
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
113
case INDEX_op_extract_i64:
114
case INDEX_op_sextract_i32:
115
case INDEX_op_sextract_i64:
116
- return &r_r;
117
+ return C_O1_I1(r, r);
118
119
case INDEX_op_st8_i32:
120
case INDEX_op_st16_i32:
121
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
122
case INDEX_op_st16_i64:
160
case INDEX_op_st16_i64:
123
case INDEX_op_st32_i64:
161
case INDEX_op_st32_i64:
124
case INDEX_op_st_i64:
162
case INDEX_op_st_i64:
125
- return &rZ_r;
163
- return C_O0_I2(rZ, r);
126
+ return C_O0_I2(rZ, r);
164
+ return C_O0_I2(rz, r);
127
165
128
case INDEX_op_add_i32:
166
case INDEX_op_add_i32:
129
case INDEX_op_add_i64:
167
case INDEX_op_add_i64:
130
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
168
@@ -XXX,XX +XXX,XX @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
131
case INDEX_op_sub_i64:
132
case INDEX_op_setcond_i32:
133
case INDEX_op_setcond_i64:
134
- return &r_r_rA;
135
+ return C_O1_I2(r, r, rA);
136
137
case INDEX_op_mul_i32:
138
case INDEX_op_mul_i64:
139
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
140
case INDEX_op_remu_i64:
141
case INDEX_op_muluh_i64:
142
case INDEX_op_mulsh_i64:
143
- return &r_r_r;
144
+ return C_O1_I2(r, r, r);
145
146
case INDEX_op_and_i32:
147
case INDEX_op_and_i64:
148
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
149
case INDEX_op_orc_i64:
150
case INDEX_op_eqv_i32:
151
case INDEX_op_eqv_i64:
152
- return &r_r_rL;
153
+ return C_O1_I2(r, r, rL);
154
155
case INDEX_op_shl_i32:
156
case INDEX_op_shr_i32:
157
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
158
case INDEX_op_sar_i64:
159
case INDEX_op_rotl_i64:
160
case INDEX_op_rotr_i64:
161
- return &r_r_ri;
162
+ return C_O1_I2(r, r, ri);
163
164
case INDEX_op_clz_i32:
165
case INDEX_op_ctz_i32:
166
case INDEX_op_clz_i64:
167
case INDEX_op_ctz_i64:
168
- return &r_r_rAL;
169
+ return C_O1_I2(r, r, rAL);
170
171
case INDEX_op_brcond_i32:
172
case INDEX_op_brcond_i64:
173
- return &r_rA;
174
+ return C_O0_I2(r, rA);
175
169
176
case INDEX_op_movcond_i32:
170
case INDEX_op_movcond_i32:
177
case INDEX_op_movcond_i64:
171
case INDEX_op_movcond_i64:
178
- return &movc;
172
- return C_O1_I4(r, r, rC, rZ, rZ);
179
+ return C_O1_I4(r, r, rA, rZ, rZ);
173
+ return C_O1_I4(r, r, rC, rz, rz);
180
174
181
case INDEX_op_qemu_ld_i32:
175
case INDEX_op_qemu_ld_i32:
182
case INDEX_op_qemu_ld_i64:
176
case INDEX_op_qemu_ld_i64:
183
- return &r_l;
177
@@ -XXX,XX +XXX,XX @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
184
+ return C_O1_I1(r, l);
178
return C_O2_I1(r, r, r);
185
case INDEX_op_qemu_st_i32:
179
case INDEX_op_qemu_st_i32:
186
case INDEX_op_qemu_st_i64:
180
case INDEX_op_qemu_st_i64:
187
- return &lZ_l;
181
- return C_O0_I2(rZ, r);
188
+ return C_O0_I2(lZ, l);
182
+ return C_O0_I2(rz, r);
183
case INDEX_op_qemu_st_i128:
184
- return C_O0_I3(rZ, rZ, r);
185
+ return C_O0_I3(rz, rz, r);
189
186
190
case INDEX_op_deposit_i32:
187
case INDEX_op_deposit_i32:
191
case INDEX_op_deposit_i64:
188
case INDEX_op_deposit_i64:
192
- return &dep;
189
- return C_O1_I2(r, 0, rZ);
193
+ return C_O1_I2(r, 0, rZ);
190
+ return C_O1_I2(r, 0, rz);
194
191
195
case INDEX_op_extract2_i32:
192
case INDEX_op_extract2_i32:
196
case INDEX_op_extract2_i64:
193
case INDEX_op_extract2_i64:
197
- return &ext2;
194
- return C_O1_I2(r, rZ, rZ);
198
+ return C_O1_I2(r, rZ, rZ);
195
+ return C_O1_I2(r, rz, rz);
199
196
200
case INDEX_op_add2_i32:
197
case INDEX_op_add2_i32:
201
case INDEX_op_add2_i64:
198
case INDEX_op_add2_i64:
202
case INDEX_op_sub2_i32:
199
case INDEX_op_sub2_i32:
203
case INDEX_op_sub2_i64:
200
case INDEX_op_sub2_i64:
204
- return &add2;
201
- return C_O2_I4(r, r, rZ, rZ, rA, rMZ);
205
+ return C_O2_I4(r, r, rZ, rZ, rA, rMZ);
202
+ return C_O2_I4(r, r, rz, rz, rA, rMZ);
206
203
207
case INDEX_op_add_vec:
204
case INDEX_op_add_vec:
208
case INDEX_op_sub_vec:
205
case INDEX_op_sub_vec:
209
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
210
case INDEX_op_shrv_vec:
211
case INDEX_op_sarv_vec:
212
case INDEX_op_aa64_sshl_vec:
213
- return &w_w_w;
214
+ return C_O1_I2(w, w, w);
215
case INDEX_op_not_vec:
216
case INDEX_op_neg_vec:
217
case INDEX_op_abs_vec:
218
case INDEX_op_shli_vec:
219
case INDEX_op_shri_vec:
220
case INDEX_op_sari_vec:
221
- return &w_w;
222
+ return C_O1_I1(w, w);
223
case INDEX_op_ld_vec:
224
- case INDEX_op_st_vec:
225
case INDEX_op_dupm_vec:
226
- return &w_r;
227
+ return C_O1_I1(w, r);
228
+ case INDEX_op_st_vec:
229
+ return C_O0_I2(w, r);
230
case INDEX_op_dup_vec:
231
- return &w_wr;
232
+ return C_O1_I1(w, wr);
233
case INDEX_op_or_vec:
234
case INDEX_op_andc_vec:
235
- return &w_w_wO;
236
+ return C_O1_I2(w, w, wO);
237
case INDEX_op_and_vec:
238
case INDEX_op_orc_vec:
239
- return &w_w_wN;
240
+ return C_O1_I2(w, w, wN);
241
case INDEX_op_cmp_vec:
242
- return &w_w_wZ;
243
+ return C_O1_I2(w, w, wZ);
244
case INDEX_op_bitsel_vec:
245
- return &w_w_w_w;
246
+ return C_O1_I3(w, w, w, w);
247
case INDEX_op_aa64_sli_vec:
248
- return &w_0_w;
249
+ return C_O1_I2(w, 0, w);
250
251
default:
252
- return NULL;
253
+ g_assert_not_reached();
254
}
255
}
256
257
--
206
--
258
2.25.1
207
2.43.0
259
260
diff view generated by jsdifflib
[PULL 21/24] tcg/s390: Split out constraint sets to tcg-target-con-set.h
[PULL 16/24] tcg/loongarch64: Use 'z' constraint
1
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
1
Replace target-specific 'Z' with generic 'z'.
2
3
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
3
---
5
---
4
tcg/s390/tcg-target-con-set.h | 29 ++++++++
6
tcg/loongarch64/tcg-target-con-set.h | 15 ++++++-------
5
tcg/s390/tcg-target.h | 1 +
7
tcg/loongarch64/tcg-target-con-str.h | 1 -
6
tcg/s390/tcg-target.c.inc | 121 ++++++++++++++--------------------
8
tcg/loongarch64/tcg-target.c.inc | 32 ++++++++++++----------------
7
3 files changed, 81 insertions(+), 70 deletions(-)
9
3 files changed, 21 insertions(+), 27 deletions(-)
8
create mode 100644 tcg/s390/tcg-target-con-set.h
9
10
10
diff --git a/tcg/s390/tcg-target-con-set.h b/tcg/s390/tcg-target-con-set.h
11
diff --git a/tcg/loongarch64/tcg-target-con-set.h b/tcg/loongarch64/tcg-target-con-set.h
11
new file mode 100644
12
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX
13
--- a/tcg/loongarch64/tcg-target-con-set.h
13
--- /dev/null
14
+++ b/tcg/loongarch64/tcg-target-con-set.h
14
+++ b/tcg/s390/tcg-target-con-set.h
15
@@ -XXX,XX +XXX,XX @@
15
@@ -XXX,XX +XXX,XX @@
16
+/* SPDX-License-Identifier: MIT */
16
* tcg-target-con-str.h; the constraint combination is inclusive or.
17
+/*
17
*/
18
+ * Define S390 target-specific constraint sets.
18
C_O0_I1(r)
19
+ * Copyright (c) 2021 Linaro
19
-C_O0_I2(rZ, r)
20
+ */
20
-C_O0_I2(rZ, rZ)
21
+
21
+C_O0_I2(rz, r)
22
+/*
22
+C_O0_I2(rz, rz)
23
+ * C_On_Im(...) defines a constraint set with <n> outputs and <m> inputs.
23
C_O0_I2(w, r)
24
+ * Each operand should be a sequence of constraint letters as defined by
24
C_O0_I3(r, r, r)
25
+ * tcg-target-con-str.h; the constraint combination is inclusive or.
25
C_O1_I1(r, r)
26
+ */
26
@@ -XXX,XX +XXX,XX @@ C_O1_I2(r, r, rI)
27
+C_O0_I1(r)
27
C_O1_I2(r, r, rJ)
28
+C_O0_I2(L, L)
28
C_O1_I2(r, r, rU)
29
+C_O0_I2(r, r)
29
C_O1_I2(r, r, rW)
30
+C_O0_I2(r, ri)
30
-C_O1_I2(r, r, rZ)
31
+C_O1_I1(r, L)
31
-C_O1_I2(r, 0, rZ)
32
+C_O1_I1(r, r)
32
-C_O1_I2(r, rZ, ri)
33
+C_O1_I2(r, 0, ri)
33
-C_O1_I2(r, rZ, rJ)
34
+C_O1_I2(r, 0, rI)
34
-C_O1_I2(r, rZ, rZ)
35
+C_O1_I2(r, 0, rJ)
35
+C_O1_I2(r, 0, rz)
36
+C_O1_I2(r, r, ri)
36
+C_O1_I2(r, rz, ri)
37
+C_O1_I2(r, rZ, r)
37
+C_O1_I2(r, rz, rJ)
38
+C_O1_I4(r, r, ri, r, 0)
38
+C_O1_I2(r, rz, rz)
39
+C_O1_I4(r, r, ri, rI, 0)
39
C_O1_I2(w, w, w)
40
+C_O2_I2(b, a, 0, r)
40
C_O1_I2(w, w, wM)
41
+C_O2_I3(b, a, 0, 1, r)
41
C_O1_I2(w, w, wA)
42
+C_O2_I4(r, r, 0, 1, rA, r)
42
C_O1_I3(w, w, w, w)
43
+C_O2_I4(r, r, 0, 1, ri, r)
43
-C_O1_I4(r, rZ, rJ, rZ, rZ)
44
+C_O2_I4(r, r, 0, 1, r, r)
44
+C_O1_I4(r, rz, rJ, rz, rz)
45
diff --git a/tcg/s390/tcg-target.h b/tcg/s390/tcg-target.h
45
C_N2_I1(r, r, r)
46
diff --git a/tcg/loongarch64/tcg-target-con-str.h b/tcg/loongarch64/tcg-target-con-str.h
46
index XXXXXXX..XXXXXXX 100644
47
index XXXXXXX..XXXXXXX 100644
47
--- a/tcg/s390/tcg-target.h
48
--- a/tcg/loongarch64/tcg-target-con-str.h
48
+++ b/tcg/s390/tcg-target.h
49
+++ b/tcg/loongarch64/tcg-target-con-str.h
49
@@ -XXX,XX +XXX,XX @@ static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_rx,
50
@@ -XXX,XX +XXX,XX @@ REGS('w', ALL_VECTOR_REGS)
50
#define TCG_TARGET_NEED_LDST_LABELS
51
CONST('I', TCG_CT_CONST_S12)
51
#endif
52
CONST('J', TCG_CT_CONST_S32)
52
#define TCG_TARGET_NEED_POOL_LABELS
53
CONST('U', TCG_CT_CONST_U12)
53
+#define TCG_TARGET_CON_SET_H
54
-CONST('Z', TCG_CT_CONST_ZERO)
54
55
CONST('C', TCG_CT_CONST_C12)
55
#endif
56
CONST('W', TCG_CT_CONST_WSZ)
56
diff --git a/tcg/s390/tcg-target.c.inc b/tcg/s390/tcg-target.c.inc
57
CONST('M', TCG_CT_CONST_VCMP)
58
diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc
57
index XXXXXXX..XXXXXXX 100644
59
index XXXXXXX..XXXXXXX 100644
58
--- a/tcg/s390/tcg-target.c.inc
60
--- a/tcg/loongarch64/tcg-target.c.inc
59
+++ b/tcg/s390/tcg-target.c.inc
61
+++ b/tcg/loongarch64/tcg-target.c.inc
60
@@ -XXX,XX +XXX,XX @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
62
@@ -XXX,XX +XXX,XX @@ static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot)
63
64
#define TCG_GUEST_BASE_REG TCG_REG_S1
65
66
-#define TCG_CT_CONST_ZERO 0x100
67
-#define TCG_CT_CONST_S12 0x200
68
-#define TCG_CT_CONST_S32 0x400
69
-#define TCG_CT_CONST_U12 0x800
70
-#define TCG_CT_CONST_C12 0x1000
71
-#define TCG_CT_CONST_WSZ 0x2000
72
-#define TCG_CT_CONST_VCMP 0x4000
73
-#define TCG_CT_CONST_VADD 0x8000
74
+#define TCG_CT_CONST_S12 0x100
75
+#define TCG_CT_CONST_S32 0x200
76
+#define TCG_CT_CONST_U12 0x400
77
+#define TCG_CT_CONST_C12 0x800
78
+#define TCG_CT_CONST_WSZ 0x1000
79
+#define TCG_CT_CONST_VCMP 0x2000
80
+#define TCG_CT_CONST_VADD 0x4000
81
82
#define ALL_GENERAL_REGS MAKE_64BIT_MASK(0, 32)
83
#define ALL_VECTOR_REGS MAKE_64BIT_MASK(32, 32)
84
@@ -XXX,XX +XXX,XX @@ static bool tcg_target_const_match(int64_t val, int ct,
85
if (ct & TCG_CT_CONST) {
86
return true;
61
}
87
}
62
}
88
- if ((ct & TCG_CT_CONST_ZERO) && val == 0) {
63
89
- return true;
64
-static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
90
- }
65
+static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
91
if ((ct & TCG_CT_CONST_S12) && val == sextreg(val, 0, 12)) {
66
{
92
return true;
67
- static const TCGTargetOpDef r = { .args_ct_str = { "r" } };
93
}
68
- static const TCGTargetOpDef r_r = { .args_ct_str = { "r", "r" } };
94
@@ -XXX,XX +XXX,XX @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
69
- static const TCGTargetOpDef r_L = { .args_ct_str = { "r", "L" } };
70
- static const TCGTargetOpDef L_L = { .args_ct_str = { "L", "L" } };
71
- static const TCGTargetOpDef r_ri = { .args_ct_str = { "r", "ri" } };
72
- static const TCGTargetOpDef r_r_ri = { .args_ct_str = { "r", "r", "ri" } };
73
- static const TCGTargetOpDef r_0_ri = { .args_ct_str = { "r", "0", "ri" } };
74
- static const TCGTargetOpDef r_0_rI = { .args_ct_str = { "r", "0", "rI" } };
75
- static const TCGTargetOpDef r_0_rJ = { .args_ct_str = { "r", "0", "rJ" } };
76
- static const TCGTargetOpDef a2_r
77
- = { .args_ct_str = { "r", "r", "0", "1", "r", "r" } };
78
- static const TCGTargetOpDef a2_ri
79
- = { .args_ct_str = { "r", "r", "0", "1", "ri", "r" } };
80
- static const TCGTargetOpDef a2_rA
81
- = { .args_ct_str = { "r", "r", "0", "1", "rA", "r" } };
82
-
83
switch (op) {
84
case INDEX_op_goto_ptr:
85
- return &r;
86
+ return C_O0_I1(r);
87
88
case INDEX_op_ld8u_i32:
89
case INDEX_op_ld8u_i64:
90
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
91
case INDEX_op_ld32u_i64:
92
case INDEX_op_ld32s_i64:
93
case INDEX_op_ld_i64:
94
+ return C_O1_I1(r, r);
95
+
96
case INDEX_op_st8_i32:
97
case INDEX_op_st8_i64:
98
case INDEX_op_st16_i32:
99
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
100
case INDEX_op_st_i32:
101
case INDEX_op_st32_i64:
102
case INDEX_op_st_i64:
95
case INDEX_op_st_i64:
103
- return &r_r;
96
case INDEX_op_qemu_st_i32:
104
+ return C_O0_I2(r, r);
97
case INDEX_op_qemu_st_i64:
105
98
- return C_O0_I2(rZ, r);
106
case INDEX_op_add_i32:
99
+ return C_O0_I2(rz, r);
107
case INDEX_op_add_i64:
100
108
- return &r_r_ri;
101
case INDEX_op_qemu_ld_i128:
109
+ case INDEX_op_shl_i64:
102
return C_N2_I1(r, r, r);
110
+ case INDEX_op_shr_i64:
103
@@ -XXX,XX +XXX,XX @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
111
+ case INDEX_op_sar_i64:
112
+ case INDEX_op_rotl_i32:
113
+ case INDEX_op_rotl_i64:
114
+ case INDEX_op_rotr_i32:
115
+ case INDEX_op_rotr_i64:
116
+ case INDEX_op_clz_i64:
117
+ case INDEX_op_setcond_i32:
118
+ case INDEX_op_setcond_i64:
119
+ return C_O1_I2(r, r, ri);
120
+
121
case INDEX_op_sub_i32:
122
case INDEX_op_sub_i64:
123
case INDEX_op_and_i32:
124
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
125
case INDEX_op_or_i64:
126
case INDEX_op_xor_i32:
127
case INDEX_op_xor_i64:
128
- return (s390_facilities & FACILITY_DISTINCT_OPS ? &r_r_ri : &r_0_ri);
129
+ return (s390_facilities & FACILITY_DISTINCT_OPS
130
+ ? C_O1_I2(r, r, ri)
131
+ : C_O1_I2(r, 0, ri));
132
133
case INDEX_op_mul_i32:
134
/* If we have the general-instruction-extensions, then we have
135
MULTIPLY SINGLE IMMEDIATE with a signed 32-bit, otherwise we
136
have only MULTIPLY HALFWORD IMMEDIATE, with a signed 16-bit. */
137
- return (s390_facilities & FACILITY_GEN_INST_EXT ? &r_0_ri : &r_0_rI);
138
+ return (s390_facilities & FACILITY_GEN_INST_EXT
139
+ ? C_O1_I2(r, 0, ri)
140
+ : C_O1_I2(r, 0, rI));
141
+
142
case INDEX_op_mul_i64:
143
- return (s390_facilities & FACILITY_GEN_INST_EXT ? &r_0_rJ : &r_0_rI);
144
+ return (s390_facilities & FACILITY_GEN_INST_EXT
145
+ ? C_O1_I2(r, 0, rJ)
146
+ : C_O1_I2(r, 0, rI));
147
148
case INDEX_op_shl_i32:
149
case INDEX_op_shr_i32:
150
case INDEX_op_sar_i32:
151
- return (s390_facilities & FACILITY_DISTINCT_OPS ? &r_r_ri : &r_0_ri);
152
-
153
- case INDEX_op_shl_i64:
154
- case INDEX_op_shr_i64:
155
- case INDEX_op_sar_i64:
156
- return &r_r_ri;
157
-
158
- case INDEX_op_rotl_i32:
159
- case INDEX_op_rotl_i64:
160
- case INDEX_op_rotr_i32:
161
- case INDEX_op_rotr_i64:
162
- return &r_r_ri;
163
+ return (s390_facilities & FACILITY_DISTINCT_OPS
164
+ ? C_O1_I2(r, r, ri)
165
+ : C_O1_I2(r, 0, ri));
166
104
167
case INDEX_op_brcond_i32:
105
case INDEX_op_brcond_i32:
168
case INDEX_op_brcond_i64:
106
case INDEX_op_brcond_i64:
169
- return &r_ri;
107
- return C_O0_I2(rZ, rZ);
170
+ return C_O0_I2(r, ri);
108
+ return C_O0_I2(rz, rz);
171
109
172
case INDEX_op_bswap16_i32:
110
case INDEX_op_ext8s_i32:
173
case INDEX_op_bswap16_i64:
111
case INDEX_op_ext8s_i64:
174
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
112
@@ -XXX,XX +XXX,XX @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
175
case INDEX_op_extu_i32_i64:
176
case INDEX_op_extract_i32:
177
case INDEX_op_extract_i64:
178
- return &r_r;
179
-
180
- case INDEX_op_clz_i64:
181
- case INDEX_op_setcond_i32:
182
- case INDEX_op_setcond_i64:
183
- return &r_r_ri;
184
+ return C_O1_I1(r, r);
185
186
case INDEX_op_qemu_ld_i32:
187
case INDEX_op_qemu_ld_i64:
188
- return &r_L;
189
+ return C_O1_I1(r, L);
190
case INDEX_op_qemu_st_i64:
191
case INDEX_op_qemu_st_i32:
192
- return &L_L;
193
+ return C_O0_I2(L, L);
194
195
case INDEX_op_deposit_i32:
113
case INDEX_op_deposit_i32:
196
case INDEX_op_deposit_i64:
114
case INDEX_op_deposit_i64:
197
- {
115
/* Must deposit into the same register as input */
198
- static const TCGTargetOpDef dep
116
- return C_O1_I2(r, 0, rZ);
199
- = { .args_ct_str = { "r", "rZ", "r" } };
117
+ return C_O1_I2(r, 0, rz);
200
- return &dep;
118
201
- }
119
case INDEX_op_sub_i32:
202
+ return C_O1_I2(r, rZ, r);
120
case INDEX_op_setcond_i32:
203
+
121
- return C_O1_I2(r, rZ, ri);
122
+ return C_O1_I2(r, rz, ri);
123
case INDEX_op_sub_i64:
124
case INDEX_op_setcond_i64:
125
- return C_O1_I2(r, rZ, rJ);
126
+ return C_O1_I2(r, rz, rJ);
127
128
case INDEX_op_mul_i32:
129
case INDEX_op_mul_i64:
130
@@ -XXX,XX +XXX,XX @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
131
case INDEX_op_rem_i64:
132
case INDEX_op_remu_i32:
133
case INDEX_op_remu_i64:
134
- return C_O1_I2(r, rZ, rZ);
135
+ return C_O1_I2(r, rz, rz);
136
204
case INDEX_op_movcond_i32:
137
case INDEX_op_movcond_i32:
205
case INDEX_op_movcond_i64:
138
case INDEX_op_movcond_i64:
206
- {
139
- return C_O1_I4(r, rZ, rJ, rZ, rZ);
207
- static const TCGTargetOpDef movc
140
+ return C_O1_I4(r, rz, rJ, rz, rz);
208
- = { .args_ct_str = { "r", "r", "ri", "r", "0" } };
141
209
- static const TCGTargetOpDef movc_l
142
case INDEX_op_ld_vec:
210
- = { .args_ct_str = { "r", "r", "ri", "rI", "0" } };
143
case INDEX_op_dupm_vec:
211
- return (s390_facilities & FACILITY_LOAD_ON_COND2 ? &movc_l : &movc);
212
- }
213
+ return (s390_facilities & FACILITY_LOAD_ON_COND2
214
+ ? C_O1_I4(r, r, ri, rI, 0)
215
+ : C_O1_I4(r, r, ri, r, 0));
216
+
217
case INDEX_op_div2_i32:
218
case INDEX_op_div2_i64:
219
case INDEX_op_divu2_i32:
220
case INDEX_op_divu2_i64:
221
- {
222
- static const TCGTargetOpDef div2
223
- = { .args_ct_str = { "b", "a", "0", "1", "r" } };
224
- return &div2;
225
- }
226
+ return C_O2_I3(b, a, 0, 1, r);
227
+
228
case INDEX_op_mulu2_i64:
229
- {
230
- static const TCGTargetOpDef mul2
231
- = { .args_ct_str = { "b", "a", "0", "r" } };
232
- return &mul2;
233
- }
234
+ return C_O2_I2(b, a, 0, r);
235
236
case INDEX_op_add2_i32:
237
case INDEX_op_sub2_i32:
238
- return (s390_facilities & FACILITY_EXT_IMM ? &a2_ri : &a2_r);
239
+ return (s390_facilities & FACILITY_EXT_IMM
240
+ ? C_O2_I4(r, r, 0, 1, ri, r)
241
+ : C_O2_I4(r, r, 0, 1, r, r));
242
+
243
case INDEX_op_add2_i64:
244
case INDEX_op_sub2_i64:
245
- return (s390_facilities & FACILITY_EXT_IMM ? &a2_rA : &a2_r);
246
+ return (s390_facilities & FACILITY_EXT_IMM
247
+ ? C_O2_I4(r, r, 0, 1, rA, r)
248
+ : C_O2_I4(r, r, 0, 1, r, r));
249
250
default:
251
- break;
252
+ g_assert_not_reached();
253
}
254
- return NULL;
255
}
256
257
static void query_s390_facilities(void)
258
--
144
--
259
2.25.1
145
2.43.0
260
146
261
147
diff view generated by jsdifflib
[PULL 18/24] tcg/mips: Split out constraint sets to tcg-target-con-set.h
[PULL 17/24] tcg/mips: Use 'z' constraint
1
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
1
Replace target-specific 'Z' with generic 'z'.
2
3
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
3
---
5
---
4
tcg/mips/tcg-target-con-set.h | 36 +++++++++++++
6
tcg/mips/tcg-target-con-set.h | 26 ++++++++++-----------
5
tcg/mips/tcg-target.h | 1 +
7
tcg/mips/tcg-target-con-str.h | 1 -
6
tcg/mips/tcg-target.c.inc | 96 +++++++++++------------------------
8
tcg/mips/tcg-target.c.inc | 44 ++++++++++++++---------------------
7
3 files changed, 66 insertions(+), 67 deletions(-)
9
3 files changed, 31 insertions(+), 40 deletions(-)
8
create mode 100644 tcg/mips/tcg-target-con-set.h
9
10
10
diff --git a/tcg/mips/tcg-target-con-set.h b/tcg/mips/tcg-target-con-set.h
11
diff --git a/tcg/mips/tcg-target-con-set.h b/tcg/mips/tcg-target-con-set.h
11
new file mode 100644
12
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX
13
--- a/tcg/mips/tcg-target-con-set.h
13
--- /dev/null
14
+++ b/tcg/mips/tcg-target-con-set.h
14
+++ b/tcg/mips/tcg-target-con-set.h
15
@@ -XXX,XX +XXX,XX @@
15
@@ -XXX,XX +XXX,XX @@
16
+/* SPDX-License-Identifier: MIT */
16
* tcg-target-con-str.h; the constraint combination is inclusive or.
17
+/*
17
*/
18
+ * Define MIPS target-specific constraint sets.
18
C_O0_I1(r)
19
+ * Copyright (c) 2021 Linaro
19
-C_O0_I2(rZ, r)
20
+ */
20
-C_O0_I2(rZ, rZ)
21
+
21
-C_O0_I3(rZ, r, r)
22
+/*
22
-C_O0_I3(rZ, rZ, r)
23
+ * C_On_Im(...) defines a constraint set with <n> outputs and <m> inputs.
23
-C_O0_I4(rZ, rZ, rZ, rZ)
24
+ * Each operand should be a sequence of constraint letters as defined by
24
-C_O0_I4(rZ, rZ, r, r)
25
+ * tcg-target-con-str.h; the constraint combination is inclusive or.
25
+C_O0_I2(rz, r)
26
+ */
26
+C_O0_I2(rz, rz)
27
+C_O0_I1(r)
27
+C_O0_I3(rz, r, r)
28
+C_O0_I2(rZ, r)
28
+C_O0_I3(rz, rz, r)
29
+C_O0_I2(rZ, rZ)
29
+C_O0_I4(rz, rz, rz, rz)
30
+C_O0_I2(SZ, S)
30
+C_O0_I4(rz, rz, r, r)
31
+C_O0_I3(SZ, S, S)
31
C_O1_I1(r, r)
32
+C_O0_I3(SZ, SZ, S)
32
-C_O1_I2(r, 0, rZ)
33
+C_O0_I4(rZ, rZ, rZ, rZ)
33
+C_O1_I2(r, 0, rz)
34
+C_O0_I4(SZ, SZ, S, S)
34
C_O1_I2(r, r, r)
35
+C_O1_I1(r, L)
35
C_O1_I2(r, r, ri)
36
+C_O1_I1(r, r)
36
C_O1_I2(r, r, rI)
37
+C_O1_I2(r, 0, rZ)
37
C_O1_I2(r, r, rIK)
38
+C_O1_I2(r, L, L)
38
C_O1_I2(r, r, rJ)
39
+C_O1_I2(r, r, ri)
39
-C_O1_I2(r, r, rWZ)
40
+C_O1_I2(r, r, rI)
40
-C_O1_I2(r, rZ, rN)
41
+C_O1_I2(r, r, rIK)
41
-C_O1_I2(r, rZ, rZ)
42
+C_O1_I2(r, r, rJ)
42
-C_O1_I4(r, rZ, rZ, rZ, 0)
43
+C_O1_I2(r, r, rWZ)
43
-C_O1_I4(r, rZ, rZ, rZ, rZ)
44
+C_O1_I2(r, rZ, rN)
44
+C_O1_I2(r, r, rzW)
45
+C_O1_I2(r, rZ, rZ)
45
+C_O1_I2(r, rz, rN)
46
+C_O1_I4(r, rZ, rZ, rZ, 0)
46
+C_O1_I2(r, rz, rz)
47
+C_O1_I4(r, rZ, rZ, rZ, rZ)
47
+C_O1_I4(r, rz, rz, rz, 0)
48
+C_O2_I1(r, r, L)
48
+C_O1_I4(r, rz, rz, rz, rz)
49
+C_O2_I2(r, r, L, L)
49
C_O2_I1(r, r, r)
50
+C_O2_I2(r, r, r, r)
50
C_O2_I2(r, r, r, r)
51
+C_O2_I4(r, r, rZ, rZ, rN, rN)
51
-C_O2_I4(r, r, rZ, rZ, rN, rN)
52
diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h
52
+C_O2_I4(r, r, rz, rz, rN, rN)
53
diff --git a/tcg/mips/tcg-target-con-str.h b/tcg/mips/tcg-target-con-str.h
53
index XXXXXXX..XXXXXXX 100644
54
index XXXXXXX..XXXXXXX 100644
54
--- a/tcg/mips/tcg-target.h
55
--- a/tcg/mips/tcg-target-con-str.h
55
+++ b/tcg/mips/tcg-target.h
56
+++ b/tcg/mips/tcg-target-con-str.h
56
@@ -XXX,XX +XXX,XX @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t);
57
@@ -XXX,XX +XXX,XX @@ CONST('J', TCG_CT_CONST_S16)
57
#ifdef CONFIG_SOFTMMU
58
CONST('K', TCG_CT_CONST_P2M1)
58
#define TCG_TARGET_NEED_LDST_LABELS
59
CONST('N', TCG_CT_CONST_N16)
59
#endif
60
CONST('W', TCG_CT_CONST_WSZ)
60
+#define TCG_TARGET_CON_SET_H
61
-CONST('Z', TCG_CT_CONST_ZERO)
61
62
#endif
63
diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc
62
diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc
64
index XXXXXXX..XXXXXXX 100644
63
index XXXXXXX..XXXXXXX 100644
65
--- a/tcg/mips/tcg-target.c.inc
64
--- a/tcg/mips/tcg-target.c.inc
66
+++ b/tcg/mips/tcg-target.c.inc
65
+++ b/tcg/mips/tcg-target.c.inc
67
@@ -XXX,XX +XXX,XX @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
66
@@ -XXX,XX +XXX,XX @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
68
}
67
g_assert_not_reached();
69
}
68
}
70
69
71
-static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
70
-#define TCG_CT_CONST_ZERO 0x100
72
+static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
71
-#define TCG_CT_CONST_U16 0x200 /* Unsigned 16-bit: 0 - 0xffff. */
72
-#define TCG_CT_CONST_S16 0x400 /* Signed 16-bit: -32768 - 32767 */
73
-#define TCG_CT_CONST_P2M1 0x800 /* Power of 2 minus 1. */
74
-#define TCG_CT_CONST_N16 0x1000 /* "Negatable" 16-bit: -32767 - 32767 */
75
-#define TCG_CT_CONST_WSZ 0x2000 /* word size */
76
+#define TCG_CT_CONST_U16 0x100 /* Unsigned 16-bit: 0 - 0xffff. */
77
+#define TCG_CT_CONST_S16 0x200 /* Signed 16-bit: -32768 - 32767 */
78
+#define TCG_CT_CONST_P2M1 0x400 /* Power of 2 minus 1. */
79
+#define TCG_CT_CONST_N16 0x800 /* "Negatable" 16-bit: -32767 - 32767 */
80
+#define TCG_CT_CONST_WSZ 0x1000 /* word size */
81
82
#define ALL_GENERAL_REGS 0xffffffffu
83
84
@@ -XXX,XX +XXX,XX @@ static bool tcg_target_const_match(int64_t val, int ct,
73
{
85
{
74
- static const TCGTargetOpDef r = { .args_ct_str = { "r" } };
86
if (ct & TCG_CT_CONST) {
75
- static const TCGTargetOpDef r_r = { .args_ct_str = { "r", "r" } };
87
return 1;
76
- static const TCGTargetOpDef r_L = { .args_ct_str = { "r", "L" } };
88
- } else if ((ct & TCG_CT_CONST_ZERO) && val == 0) {
77
- static const TCGTargetOpDef rZ_r = { .args_ct_str = { "rZ", "r" } };
89
- return 1;
78
- static const TCGTargetOpDef SZ_S = { .args_ct_str = { "SZ", "S" } };
90
} else if ((ct & TCG_CT_CONST_U16) && val == (uint16_t)val) {
79
- static const TCGTargetOpDef rZ_rZ = { .args_ct_str = { "rZ", "rZ" } };
91
return 1;
80
- static const TCGTargetOpDef r_r_L = { .args_ct_str = { "r", "r", "L" } };
92
} else if ((ct & TCG_CT_CONST_S16) && val == (int16_t)val) {
81
- static const TCGTargetOpDef r_L_L = { .args_ct_str = { "r", "L", "L" } };
93
@@ -XXX,XX +XXX,XX @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
82
- static const TCGTargetOpDef r_r_ri = { .args_ct_str = { "r", "r", "ri" } };
94
TCGArg a0, a1, a2;
83
- static const TCGTargetOpDef r_r_rI = { .args_ct_str = { "r", "r", "rI" } };
95
int c2;
84
- static const TCGTargetOpDef r_r_rJ = { .args_ct_str = { "r", "r", "rJ" } };
96
85
- static const TCGTargetOpDef SZ_S_S = { .args_ct_str = { "SZ", "S", "S" } };
97
- /*
86
- static const TCGTargetOpDef SZ_SZ_S
98
- * Note that many operands use the constraint set "rZ".
87
- = { .args_ct_str = { "SZ", "SZ", "S" } };
99
- * We make use of the fact that 0 is the ZERO register,
88
- static const TCGTargetOpDef SZ_SZ_S_S
100
- * and hence such cases need not check for const_args.
89
- = { .args_ct_str = { "SZ", "SZ", "S", "S" } };
101
- */
90
- static const TCGTargetOpDef r_rZ_rN
102
a0 = args[0];
91
- = { .args_ct_str = { "r", "rZ", "rN" } };
103
a1 = args[1];
92
- static const TCGTargetOpDef r_rZ_rZ
104
a2 = args[2];
93
- = { .args_ct_str = { "r", "rZ", "rZ" } };
105
@@ -XXX,XX +XXX,XX @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
94
- static const TCGTargetOpDef r_r_rIK
95
- = { .args_ct_str = { "r", "r", "rIK" } };
96
- static const TCGTargetOpDef r_r_rWZ
97
- = { .args_ct_str = { "r", "r", "rWZ" } };
98
- static const TCGTargetOpDef r_r_r_r
99
- = { .args_ct_str = { "r", "r", "r", "r" } };
100
- static const TCGTargetOpDef r_r_L_L
101
- = { .args_ct_str = { "r", "r", "L", "L" } };
102
- static const TCGTargetOpDef dep
103
- = { .args_ct_str = { "r", "0", "rZ" } };
104
- static const TCGTargetOpDef movc
105
- = { .args_ct_str = { "r", "rZ", "rZ", "rZ", "0" } };
106
- static const TCGTargetOpDef movc_r6
107
- = { .args_ct_str = { "r", "rZ", "rZ", "rZ", "rZ" } };
108
- static const TCGTargetOpDef add2
109
- = { .args_ct_str = { "r", "r", "rZ", "rZ", "rN", "rN" } };
110
- static const TCGTargetOpDef br2
111
- = { .args_ct_str = { "rZ", "rZ", "rZ", "rZ" } };
112
- static const TCGTargetOpDef setc2
113
- = { .args_ct_str = { "r", "rZ", "rZ", "rZ", "rZ" } };
114
-
115
switch (op) {
116
case INDEX_op_goto_ptr:
117
- return &r;
118
+ return C_O0_I1(r);
119
120
case INDEX_op_ld8u_i32:
121
case INDEX_op_ld8s_i32:
122
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
123
case INDEX_op_extrl_i64_i32:
124
case INDEX_op_extrh_i64_i32:
125
case INDEX_op_extract_i64:
126
- return &r_r;
127
+ return C_O1_I1(r, r);
128
129
case INDEX_op_st8_i32:
130
case INDEX_op_st16_i32:
131
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
132
case INDEX_op_st16_i64:
106
case INDEX_op_st16_i64:
133
case INDEX_op_st32_i64:
107
case INDEX_op_st32_i64:
134
case INDEX_op_st_i64:
108
case INDEX_op_st_i64:
135
- return &rZ_r;
109
- return C_O0_I2(rZ, r);
136
+ return C_O0_I2(rZ, r);
110
+ return C_O0_I2(rz, r);
137
111
138
case INDEX_op_add_i32:
112
case INDEX_op_add_i32:
139
case INDEX_op_add_i64:
113
case INDEX_op_add_i64:
140
- return &r_r_rJ;
114
return C_O1_I2(r, r, rJ);
141
+ return C_O1_I2(r, r, rJ);
142
case INDEX_op_sub_i32:
115
case INDEX_op_sub_i32:
143
case INDEX_op_sub_i64:
116
case INDEX_op_sub_i64:
144
- return &r_rZ_rN;
117
- return C_O1_I2(r, rZ, rN);
145
+ return C_O1_I2(r, rZ, rN);
118
+ return C_O1_I2(r, rz, rN);
146
case INDEX_op_mul_i32:
119
case INDEX_op_mul_i32:
147
case INDEX_op_mulsh_i32:
120
case INDEX_op_mulsh_i32:
148
case INDEX_op_muluh_i32:
121
case INDEX_op_muluh_i32:
149
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
122
@@ -XXX,XX +XXX,XX @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
150
case INDEX_op_remu_i64:
123
case INDEX_op_remu_i64:
151
case INDEX_op_nor_i64:
124
case INDEX_op_nor_i64:
152
case INDEX_op_setcond_i64:
125
case INDEX_op_setcond_i64:
153
- return &r_rZ_rZ;
126
- return C_O1_I2(r, rZ, rZ);
154
+ return C_O1_I2(r, rZ, rZ);
127
+ return C_O1_I2(r, rz, rz);
155
case INDEX_op_muls2_i32:
128
case INDEX_op_muls2_i32:
156
case INDEX_op_mulu2_i32:
129
case INDEX_op_mulu2_i32:
157
case INDEX_op_muls2_i64:
130
case INDEX_op_muls2_i64:
158
case INDEX_op_mulu2_i64:
131
@@ -XXX,XX +XXX,XX @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
159
- return &r_r_r_r;
132
return C_O1_I2(r, r, ri);
160
+ return C_O2_I2(r, r, r, r);
161
case INDEX_op_and_i32:
162
case INDEX_op_and_i64:
163
- return &r_r_rIK;
164
+ return C_O1_I2(r, r, rIK);
165
case INDEX_op_or_i32:
166
case INDEX_op_xor_i32:
167
case INDEX_op_or_i64:
168
case INDEX_op_xor_i64:
169
- return &r_r_rI;
170
+ return C_O1_I2(r, r, rI);
171
case INDEX_op_shl_i32:
172
case INDEX_op_shr_i32:
173
case INDEX_op_sar_i32:
174
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
175
case INDEX_op_sar_i64:
176
case INDEX_op_rotr_i64:
177
case INDEX_op_rotl_i64:
178
- return &r_r_ri;
179
+ return C_O1_I2(r, r, ri);
180
case INDEX_op_clz_i32:
133
case INDEX_op_clz_i32:
181
case INDEX_op_clz_i64:
134
case INDEX_op_clz_i64:
182
- return &r_r_rWZ;
135
- return C_O1_I2(r, r, rWZ);
183
+ return C_O1_I2(r, r, rWZ);
136
+ return C_O1_I2(r, r, rzW);
184
137
185
case INDEX_op_deposit_i32:
138
case INDEX_op_deposit_i32:
186
case INDEX_op_deposit_i64:
139
case INDEX_op_deposit_i64:
187
- return &dep;
140
- return C_O1_I2(r, 0, rZ);
188
+ return C_O1_I2(r, 0, rZ);
141
+ return C_O1_I2(r, 0, rz);
189
case INDEX_op_brcond_i32:
142
case INDEX_op_brcond_i32:
190
case INDEX_op_brcond_i64:
143
case INDEX_op_brcond_i64:
191
- return &rZ_rZ;
144
- return C_O0_I2(rZ, rZ);
192
+ return C_O0_I2(rZ, rZ);
145
+ return C_O0_I2(rz, rz);
193
case INDEX_op_movcond_i32:
146
case INDEX_op_movcond_i32:
194
case INDEX_op_movcond_i64:
147
case INDEX_op_movcond_i64:
195
- return use_mips32r6_instructions ? &movc_r6 : &movc;
148
return (use_mips32r6_instructions
196
-
149
- ? C_O1_I4(r, rZ, rZ, rZ, rZ)
197
+ return (use_mips32r6_instructions
150
- : C_O1_I4(r, rZ, rZ, rZ, 0));
198
+ ? C_O1_I4(r, rZ, rZ, rZ, rZ)
151
+ ? C_O1_I4(r, rz, rz, rz, rz)
199
+ : C_O1_I4(r, rZ, rZ, rZ, 0));
152
+ : C_O1_I4(r, rz, rz, rz, 0));
200
case INDEX_op_add2_i32:
153
case INDEX_op_add2_i32:
201
case INDEX_op_sub2_i32:
154
case INDEX_op_sub2_i32:
202
- return &add2;
155
- return C_O2_I4(r, r, rZ, rZ, rN, rN);
203
+ return C_O2_I4(r, r, rZ, rZ, rN, rN);
156
+ return C_O2_I4(r, r, rz, rz, rN, rN);
204
case INDEX_op_setcond2_i32:
157
case INDEX_op_setcond2_i32:
205
- return &setc2;
158
- return C_O1_I4(r, rZ, rZ, rZ, rZ);
206
+ return C_O1_I4(r, rZ, rZ, rZ, rZ);
159
+ return C_O1_I4(r, rz, rz, rz, rz);
207
case INDEX_op_brcond2_i32:
160
case INDEX_op_brcond2_i32:
208
- return &br2;
161
- return C_O0_I4(rZ, rZ, rZ, rZ);
209
+ return C_O0_I4(rZ, rZ, rZ, rZ);
162
+ return C_O0_I4(rz, rz, rz, rz);
210
163
211
case INDEX_op_qemu_ld_i32:
164
case INDEX_op_qemu_ld_i32:
212
return (TCG_TARGET_REG_BITS == 64 || TARGET_LONG_BITS == 32
165
return C_O1_I1(r, r);
213
- ? &r_L : &r_L_L);
214
+ ? C_O1_I1(r, L) : C_O1_I2(r, L, L));
215
case INDEX_op_qemu_st_i32:
166
case INDEX_op_qemu_st_i32:
216
return (TCG_TARGET_REG_BITS == 64 || TARGET_LONG_BITS == 32
167
- return C_O0_I2(rZ, r);
217
- ? &SZ_S : &SZ_S_S);
168
+ return C_O0_I2(rz, r);
218
+ ? C_O0_I2(SZ, S) : C_O0_I3(SZ, S, S));
219
case INDEX_op_qemu_ld_i64:
169
case INDEX_op_qemu_ld_i64:
220
- return (TCG_TARGET_REG_BITS == 64 ? &r_L
170
return TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, r) : C_O2_I1(r, r, r);
221
- : TARGET_LONG_BITS == 32 ? &r_r_L : &r_r_L_L);
222
+ return (TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, L)
223
+ : TARGET_LONG_BITS == 32 ? C_O2_I1(r, r, L)
224
+ : C_O2_I2(r, r, L, L));
225
case INDEX_op_qemu_st_i64:
171
case INDEX_op_qemu_st_i64:
226
- return (TCG_TARGET_REG_BITS == 64 ? &SZ_S
172
- return TCG_TARGET_REG_BITS == 64 ? C_O0_I2(rZ, r) : C_O0_I3(rZ, rZ, r);
227
- : TARGET_LONG_BITS == 32 ? &SZ_SZ_S : &SZ_SZ_S_S);
173
+ return TCG_TARGET_REG_BITS == 64 ? C_O0_I2(rz, r) : C_O0_I3(rz, rz, r);
228
+ return (TCG_TARGET_REG_BITS == 64 ? C_O0_I2(SZ, S)
229
+ : TARGET_LONG_BITS == 32 ? C_O0_I3(SZ, SZ, S)
230
+ : C_O0_I4(SZ, SZ, S, S));
231
174
232
default:
175
default:
233
- return NULL;
176
return C_NotImplemented;
234
+ g_assert_not_reached();
235
}
236
}
237
238
--
177
--
239
2.25.1
178
2.43.0
240
179
241
180
diff view generated by jsdifflib
[PULL 20/24] tcg/riscv: Split out constraint sets to tcg-target-con-set.h
[PULL 18/24] tcg/riscv: Use 'z' constraint
1
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
1
Replace target-specific 'Z' with generic 'z'.
2
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
2
3
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
---
5
---
5
tcg/riscv/tcg-target-con-set.h | 30 ++++++++++++
6
tcg/riscv/tcg-target-con-set.h | 10 +++++-----
6
tcg/riscv/tcg-target.h | 1 +
7
tcg/riscv/tcg-target-con-str.h | 1 -
7
tcg/riscv/tcg-target.c.inc | 83 ++++++++++------------------------
8
tcg/riscv/tcg-target.c.inc | 28 ++++++++++++----------------
8
3 files changed, 54 insertions(+), 60 deletions(-)
9
3 files changed, 17 insertions(+), 22 deletions(-)
9
create mode 100644 tcg/riscv/tcg-target-con-set.h
10
10
11
diff --git a/tcg/riscv/tcg-target-con-set.h b/tcg/riscv/tcg-target-con-set.h
11
diff --git a/tcg/riscv/tcg-target-con-set.h b/tcg/riscv/tcg-target-con-set.h
12
new file mode 100644
12
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX
13
--- a/tcg/riscv/tcg-target-con-set.h
14
--- /dev/null
15
+++ b/tcg/riscv/tcg-target-con-set.h
14
+++ b/tcg/riscv/tcg-target-con-set.h
16
@@ -XXX,XX +XXX,XX @@
15
@@ -XXX,XX +XXX,XX @@
17
+/* SPDX-License-Identifier: MIT */
16
* tcg-target-con-str.h; the constraint combination is inclusive or.
18
+/*
17
*/
19
+ * Define RISC-V target-specific constraint sets.
18
C_O0_I1(r)
20
+ * Copyright (c) 2021 Linaro
19
-C_O0_I2(rZ, r)
21
+ */
20
-C_O0_I2(rZ, rZ)
22
+
21
+C_O0_I2(rz, r)
23
+/*
22
+C_O0_I2(rz, rz)
24
+ * C_On_Im(...) defines a constraint set with <n> outputs and <m> inputs.
23
C_O1_I1(r, r)
25
+ * Each operand should be a sequence of constraint letters as defined by
24
C_O1_I2(r, r, ri)
26
+ * tcg-target-con-str.h; the constraint combination is inclusive or.
25
C_O1_I2(r, r, rI)
27
+ */
26
C_O1_I2(r, r, rJ)
28
+C_O0_I1(r)
27
-C_O1_I2(r, rZ, rN)
29
+C_O0_I2(LZ, L)
28
-C_O1_I2(r, rZ, rZ)
30
+C_O0_I2(rZ, r)
29
+C_O1_I2(r, rz, rN)
31
+C_O0_I2(rZ, rZ)
30
+C_O1_I2(r, rz, rz)
32
+C_O0_I3(LZ, L, L)
31
C_N1_I2(r, r, rM)
33
+C_O0_I3(LZ, LZ, L)
32
C_O1_I4(r, r, rI, rM, rM)
34
+C_O0_I4(LZ, LZ, L, L)
33
-C_O2_I4(r, r, rZ, rZ, rM, rM)
35
+C_O0_I4(rZ, rZ, rZ, rZ)
34
+C_O2_I4(r, r, rz, rz, rM, rM)
36
+C_O1_I1(r, L)
35
C_O0_I2(v, r)
37
+C_O1_I1(r, r)
36
C_O1_I1(v, r)
38
+C_O1_I2(r, L, L)
37
C_O1_I1(v, v)
39
+C_O1_I2(r, r, ri)
38
diff --git a/tcg/riscv/tcg-target-con-str.h b/tcg/riscv/tcg-target-con-str.h
40
+C_O1_I2(r, r, rI)
41
+C_O1_I2(r, rZ, rN)
42
+C_O1_I2(r, rZ, rZ)
43
+C_O1_I4(r, rZ, rZ, rZ, rZ)
44
+C_O2_I1(r, r, L)
45
+C_O2_I2(r, r, L, L)
46
+C_O2_I4(r, r, rZ, rZ, rM, rM)
47
diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h
48
index XXXXXXX..XXXXXXX 100644
39
index XXXXXXX..XXXXXXX 100644
49
--- a/tcg/riscv/tcg-target.h
40
--- a/tcg/riscv/tcg-target-con-str.h
50
+++ b/tcg/riscv/tcg-target.h
41
+++ b/tcg/riscv/tcg-target-con-str.h
51
@@ -XXX,XX +XXX,XX @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t);
42
@@ -XXX,XX +XXX,XX @@ CONST('K', TCG_CT_CONST_S5)
52
#define TCG_TARGET_NEED_POOL_LABELS
43
CONST('L', TCG_CT_CONST_CMP_VI)
53
44
CONST('N', TCG_CT_CONST_N12)
54
#define TCG_TARGET_HAS_MEMORY_BSWAP 0
45
CONST('M', TCG_CT_CONST_M12)
55
+#define TCG_TARGET_CON_SET_H
46
-CONST('Z', TCG_CT_CONST_ZERO)
56
57
#endif
58
diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
47
diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
59
index XXXXXXX..XXXXXXX 100644
48
index XXXXXXX..XXXXXXX 100644
60
--- a/tcg/riscv/tcg-target.c.inc
49
--- a/tcg/riscv/tcg-target.c.inc
61
+++ b/tcg/riscv/tcg-target.c.inc
50
+++ b/tcg/riscv/tcg-target.c.inc
62
@@ -XXX,XX +XXX,XX @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
51
@@ -XXX,XX +XXX,XX @@ static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot)
52
return TCG_REG_A0 + slot;
53
}
54
55
-#define TCG_CT_CONST_ZERO 0x100
56
-#define TCG_CT_CONST_S12 0x200
57
-#define TCG_CT_CONST_N12 0x400
58
-#define TCG_CT_CONST_M12 0x800
59
-#define TCG_CT_CONST_J12 0x1000
60
-#define TCG_CT_CONST_S5 0x2000
61
-#define TCG_CT_CONST_CMP_VI 0x4000
62
+#define TCG_CT_CONST_S12 0x100
63
+#define TCG_CT_CONST_N12 0x200
64
+#define TCG_CT_CONST_M12 0x400
65
+#define TCG_CT_CONST_J12 0x800
66
+#define TCG_CT_CONST_S5 0x1000
67
+#define TCG_CT_CONST_CMP_VI 0x2000
68
69
#define ALL_GENERAL_REGS MAKE_64BIT_MASK(0, 32)
70
#define ALL_VECTOR_REGS MAKE_64BIT_MASK(32, 32)
71
@@ -XXX,XX +XXX,XX @@ static bool tcg_target_const_match(int64_t val, int ct,
72
if (ct & TCG_CT_CONST) {
73
return 1;
63
}
74
}
64
}
75
- if ((ct & TCG_CT_CONST_ZERO) && val == 0) {
65
76
- return 1;
66
-static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
77
- }
67
+static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
78
if (type >= TCG_TYPE_V64) {
68
{
79
/* Val is replicated by VECE; extract the highest element. */
69
- static const TCGTargetOpDef r
80
val >>= (-8 << vece) & 63;
70
- = { .args_ct_str = { "r" } };
81
@@ -XXX,XX +XXX,XX @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
71
- static const TCGTargetOpDef r_r
72
- = { .args_ct_str = { "r", "r" } };
73
- static const TCGTargetOpDef rZ_r
74
- = { .args_ct_str = { "rZ", "r" } };
75
- static const TCGTargetOpDef rZ_rZ
76
- = { .args_ct_str = { "rZ", "rZ" } };
77
- static const TCGTargetOpDef rZ_rZ_rZ_rZ
78
- = { .args_ct_str = { "rZ", "rZ", "rZ", "rZ" } };
79
- static const TCGTargetOpDef r_r_ri
80
- = { .args_ct_str = { "r", "r", "ri" } };
81
- static const TCGTargetOpDef r_r_rI
82
- = { .args_ct_str = { "r", "r", "rI" } };
83
- static const TCGTargetOpDef r_rZ_rN
84
- = { .args_ct_str = { "r", "rZ", "rN" } };
85
- static const TCGTargetOpDef r_rZ_rZ
86
- = { .args_ct_str = { "r", "rZ", "rZ" } };
87
- static const TCGTargetOpDef r_rZ_rZ_rZ_rZ
88
- = { .args_ct_str = { "r", "rZ", "rZ", "rZ", "rZ" } };
89
- static const TCGTargetOpDef r_L
90
- = { .args_ct_str = { "r", "L" } };
91
- static const TCGTargetOpDef r_r_L
92
- = { .args_ct_str = { "r", "r", "L" } };
93
- static const TCGTargetOpDef r_L_L
94
- = { .args_ct_str = { "r", "L", "L" } };
95
- static const TCGTargetOpDef r_r_L_L
96
- = { .args_ct_str = { "r", "r", "L", "L" } };
97
- static const TCGTargetOpDef LZ_L
98
- = { .args_ct_str = { "LZ", "L" } };
99
- static const TCGTargetOpDef LZ_L_L
100
- = { .args_ct_str = { "LZ", "L", "L" } };
101
- static const TCGTargetOpDef LZ_LZ_L
102
- = { .args_ct_str = { "LZ", "LZ", "L" } };
103
- static const TCGTargetOpDef LZ_LZ_L_L
104
- = { .args_ct_str = { "LZ", "LZ", "L", "L" } };
105
- static const TCGTargetOpDef r_r_rZ_rZ_rM_rM
106
- = { .args_ct_str = { "r", "r", "rZ", "rZ", "rM", "rM" } };
107
-
108
switch (op) {
109
case INDEX_op_goto_ptr:
110
- return &r;
111
+ return C_O0_I1(r);
112
113
case INDEX_op_ld8u_i32:
114
case INDEX_op_ld8s_i32:
115
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
116
case INDEX_op_extrl_i64_i32:
117
case INDEX_op_extrh_i64_i32:
118
case INDEX_op_ext_i32_i64:
119
- return &r_r;
120
+ return C_O1_I1(r, r);
121
122
case INDEX_op_st8_i32:
123
case INDEX_op_st16_i32:
124
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
125
case INDEX_op_st16_i64:
82
case INDEX_op_st16_i64:
126
case INDEX_op_st32_i64:
83
case INDEX_op_st32_i64:
127
case INDEX_op_st_i64:
84
case INDEX_op_st_i64:
128
- return &rZ_r;
85
- return C_O0_I2(rZ, r);
129
+ return C_O0_I2(rZ, r);
86
+ return C_O0_I2(rz, r);
130
87
131
case INDEX_op_add_i32:
88
case INDEX_op_add_i32:
132
case INDEX_op_and_i32:
89
case INDEX_op_and_i32:
133
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
90
@@ -XXX,XX +XXX,XX @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
134
case INDEX_op_and_i64:
135
case INDEX_op_or_i64:
136
case INDEX_op_xor_i64:
137
- return &r_r_rI;
138
+ return C_O1_I2(r, r, rI);
139
91
140
case INDEX_op_sub_i32:
92
case INDEX_op_sub_i32:
141
case INDEX_op_sub_i64:
93
case INDEX_op_sub_i64:
142
- return &r_rZ_rN;
94
- return C_O1_I2(r, rZ, rN);
143
+ return C_O1_I2(r, rZ, rN);
95
+ return C_O1_I2(r, rz, rN);
144
96
145
case INDEX_op_mul_i32:
97
case INDEX_op_mul_i32:
146
case INDEX_op_mulsh_i32:
98
case INDEX_op_mulsh_i32:
147
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
99
@@ -XXX,XX +XXX,XX @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
100
case INDEX_op_divu_i64:
148
case INDEX_op_rem_i64:
101
case INDEX_op_rem_i64:
149
case INDEX_op_remu_i64:
102
case INDEX_op_remu_i64:
150
case INDEX_op_setcond_i64:
103
- return C_O1_I2(r, rZ, rZ);
151
- return &r_rZ_rZ;
104
+ return C_O1_I2(r, rz, rz);
152
+ return C_O1_I2(r, rZ, rZ);
153
105
154
case INDEX_op_shl_i32:
106
case INDEX_op_shl_i32:
155
case INDEX_op_shr_i32:
107
case INDEX_op_shr_i32:
156
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
108
@@ -XXX,XX +XXX,XX @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
157
case INDEX_op_shl_i64:
158
case INDEX_op_shr_i64:
159
case INDEX_op_sar_i64:
160
- return &r_r_ri;
161
+ return C_O1_I2(r, r, ri);
162
109
163
case INDEX_op_brcond_i32:
110
case INDEX_op_brcond_i32:
164
case INDEX_op_brcond_i64:
111
case INDEX_op_brcond_i64:
165
- return &rZ_rZ;
112
- return C_O0_I2(rZ, rZ);
166
+ return C_O0_I2(rZ, rZ);
113
+ return C_O0_I2(rz, rz);
167
114
168
case INDEX_op_add2_i32:
115
case INDEX_op_movcond_i32:
116
case INDEX_op_movcond_i64:
117
@@ -XXX,XX +XXX,XX @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
169
case INDEX_op_add2_i64:
118
case INDEX_op_add2_i64:
170
case INDEX_op_sub2_i32:
119
case INDEX_op_sub2_i32:
171
case INDEX_op_sub2_i64:
120
case INDEX_op_sub2_i64:
172
- return &r_r_rZ_rZ_rM_rM;
121
- return C_O2_I4(r, r, rZ, rZ, rM, rM);
173
+ return C_O2_I4(r, r, rZ, rZ, rM, rM);
122
+ return C_O2_I4(r, r, rz, rz, rM, rM);
174
175
case INDEX_op_brcond2_i32:
176
- return &rZ_rZ_rZ_rZ;
177
+ return C_O0_I4(rZ, rZ, rZ, rZ);
178
179
case INDEX_op_setcond2_i32:
180
- return &r_rZ_rZ_rZ_rZ;
181
+ return C_O1_I4(r, rZ, rZ, rZ, rZ);
182
123
183
case INDEX_op_qemu_ld_i32:
124
case INDEX_op_qemu_ld_i32:
184
- return TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &r_L : &r_L_L;
125
case INDEX_op_qemu_ld_i64:
185
+ return (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS
126
return C_O1_I1(r, r);
186
+ ? C_O1_I1(r, L) : C_O1_I2(r, L, L));
187
case INDEX_op_qemu_st_i32:
127
case INDEX_op_qemu_st_i32:
188
- return TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &LZ_L : &LZ_L_L;
189
+ return (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS
190
+ ? C_O0_I2(LZ, L) : C_O0_I3(LZ, L, L));
191
case INDEX_op_qemu_ld_i64:
192
- return TCG_TARGET_REG_BITS == 64 ? &r_L
193
- : TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &r_r_L
194
- : &r_r_L_L;
195
+ return (TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, L)
196
+ : TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? C_O2_I1(r, r, L)
197
+ : C_O2_I2(r, r, L, L));
198
case INDEX_op_qemu_st_i64:
128
case INDEX_op_qemu_st_i64:
199
- return TCG_TARGET_REG_BITS == 64 ? &LZ_L
129
- return C_O0_I2(rZ, r);
200
- : TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &LZ_LZ_L
130
+ return C_O0_I2(rz, r);
201
- : &LZ_LZ_L_L;
131
202
+ return (TCG_TARGET_REG_BITS == 64 ? C_O0_I2(LZ, L)
132
case INDEX_op_st_vec:
203
+ : TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? C_O0_I3(LZ, LZ, L)
133
return C_O0_I2(v, r);
204
+ : C_O0_I4(LZ, LZ, L, L));
205
206
default:
207
- return NULL;
208
+ g_assert_not_reached();
209
}
210
}
211
212
--
134
--
213
2.25.1
135
2.43.0
214
136
215
137
diff view generated by jsdifflib
[PULL 15/24] tcg/i386: Split out constraint sets to tcg-target-con-set.h
[PULL 19/24] tcg/sparc64: Use 'z' constraint
1
This exports the constraint sets from tcg_target_op_def to
1
Replace target-specific 'Z' with generic 'z'.
2
a place we will be able to manipulate more in future.
3
2
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
3
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
---
5
---
7
tcg/i386/tcg-target-con-set.h | 55 ++++++++++
6
tcg/sparc64/tcg-target-con-set.h | 12 ++++++------
8
tcg/i386/tcg-target.h | 1 +
7
tcg/sparc64/tcg-target-con-str.h | 1 -
9
tcg/tcg.c | 119 +++++++++++++++++++++
8
tcg/sparc64/tcg-target.c.inc | 17 +++++++----------
10
tcg/i386/tcg-target.c.inc | 194 ++++++++++++----------------------
9
3 files changed, 13 insertions(+), 17 deletions(-)
11
4 files changed, 242 insertions(+), 127 deletions(-)
12
create mode 100644 tcg/i386/tcg-target-con-set.h
13
10
14
diff --git a/tcg/i386/tcg-target-con-set.h b/tcg/i386/tcg-target-con-set.h
11
diff --git a/tcg/sparc64/tcg-target-con-set.h b/tcg/sparc64/tcg-target-con-set.h
15
new file mode 100644
12
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX
13
--- a/tcg/sparc64/tcg-target-con-set.h
17
--- /dev/null
14
+++ b/tcg/sparc64/tcg-target-con-set.h
18
+++ b/tcg/i386/tcg-target-con-set.h
19
@@ -XXX,XX +XXX,XX @@
15
@@ -XXX,XX +XXX,XX @@
20
+/* SPDX-License-Identifier: MIT */
16
* tcg-target-con-str.h; the constraint combination is inclusive or.
21
+/*
17
*/
22
+ * Define i386 target-specific constraint sets.
18
C_O0_I1(r)
23
+ * Copyright (c) 2021 Linaro
19
-C_O0_I2(rZ, r)
24
+ */
20
-C_O0_I2(rZ, rJ)
25
+
21
+C_O0_I2(rz, r)
26
+/*
22
+C_O0_I2(rz, rJ)
27
+ * C_On_Im(...) defines a constraint set with <n> outputs and <m> inputs.
23
C_O1_I1(r, r)
28
+ * Each operand should be a sequence of constraint letters as defined by
24
C_O1_I2(r, r, r)
29
+ * tcg-target-con-str.h; the constraint combination is inclusive or.
25
-C_O1_I2(r, rZ, rJ)
30
+ *
26
-C_O1_I4(r, rZ, rJ, rI, 0)
31
+ * C_N1_Im(...) defines a constraint set with 1 output and <m> inputs,
27
-C_O2_I2(r, r, rZ, rJ)
32
+ * except that the output must use a new register.
28
-C_O2_I4(r, r, rZ, rZ, rJ, rJ)
33
+ */
29
+C_O1_I2(r, rz, rJ)
34
+C_O0_I1(r)
30
+C_O1_I4(r, rz, rJ, rI, 0)
35
+C_O0_I2(L, L)
31
+C_O2_I2(r, r, rz, rJ)
36
+C_O0_I2(qi, r)
32
+C_O2_I4(r, r, rz, rz, rJ, rJ)
37
+C_O0_I2(re, r)
33
diff --git a/tcg/sparc64/tcg-target-con-str.h b/tcg/sparc64/tcg-target-con-str.h
38
+C_O0_I2(ri, r)
39
+C_O0_I2(r, re)
40
+C_O0_I2(s, L)
41
+C_O0_I2(x, r)
42
+C_O0_I3(L, L, L)
43
+C_O0_I3(s, L, L)
44
+C_O0_I4(L, L, L, L)
45
+C_O0_I4(r, r, ri, ri)
46
+C_O1_I1(r, 0)
47
+C_O1_I1(r, L)
48
+C_O1_I1(r, q)
49
+C_O1_I1(r, r)
50
+C_O1_I1(x, r)
51
+C_O1_I1(x, x)
52
+C_O1_I2(Q, 0, Q)
53
+C_O1_I2(q, r, re)
54
+C_O1_I2(r, 0, ci)
55
+C_O1_I2(r, 0, r)
56
+C_O1_I2(r, 0, re)
57
+C_O1_I2(r, 0, reZ)
58
+C_O1_I2(r, 0, ri)
59
+C_O1_I2(r, 0, rI)
60
+C_O1_I2(r, L, L)
61
+C_O1_I2(r, r, re)
62
+C_O1_I2(r, r, ri)
63
+C_O1_I2(r, r, rI)
64
+C_O1_I2(x, x, x)
65
+C_N1_I2(r, r, r)
66
+C_N1_I2(r, r, rW)
67
+C_O1_I3(x, x, x, x)
68
+C_O1_I4(r, r, re, r, 0)
69
+C_O1_I4(r, r, r, ri, ri)
70
+C_O2_I1(r, r, L)
71
+C_O2_I2(a, d, a, r)
72
+C_O2_I2(r, r, L, L)
73
+C_O2_I3(a, d, 0, 1, r)
74
+C_O2_I4(r, r, 0, 1, re, re)
75
diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h
76
index XXXXXXX..XXXXXXX 100644
34
index XXXXXXX..XXXXXXX 100644
77
--- a/tcg/i386/tcg-target.h
35
--- a/tcg/sparc64/tcg-target-con-str.h
78
+++ b/tcg/i386/tcg-target.h
36
+++ b/tcg/sparc64/tcg-target-con-str.h
79
@@ -XXX,XX +XXX,XX @@ static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_rx,
37
@@ -XXX,XX +XXX,XX @@ REGS('r', ALL_GENERAL_REGS)
80
#define TCG_TARGET_NEED_LDST_LABELS
38
*/
81
#endif
39
CONST('I', TCG_CT_CONST_S11)
82
#define TCG_TARGET_NEED_POOL_LABELS
40
CONST('J', TCG_CT_CONST_S13)
83
+#define TCG_TARGET_CON_SET_H
41
-CONST('Z', TCG_CT_CONST_ZERO)
84
42
diff --git a/tcg/sparc64/tcg-target.c.inc b/tcg/sparc64/tcg-target.c.inc
85
#endif
86
diff --git a/tcg/tcg.c b/tcg/tcg.c
87
index XXXXXXX..XXXXXXX 100644
43
index XXXXXXX..XXXXXXX 100644
88
--- a/tcg/tcg.c
44
--- a/tcg/sparc64/tcg-target.c.inc
89
+++ b/tcg/tcg.c
45
+++ b/tcg/sparc64/tcg-target.c.inc
90
@@ -XXX,XX +XXX,XX @@
46
@@ -XXX,XX +XXX,XX @@ static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
91
/* Forward declarations for functions declared in tcg-target.c.inc and
47
92
used here. */
48
#define TCG_CT_CONST_S11 0x100
93
static void tcg_target_init(TCGContext *s);
49
#define TCG_CT_CONST_S13 0x200
94
+#ifndef TCG_TARGET_CON_SET_H
50
-#define TCG_CT_CONST_ZERO 0x400
95
static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode);
51
96
+#endif
52
#define ALL_GENERAL_REGS MAKE_64BIT_MASK(0, 32)
97
static void tcg_target_qemu_prologue(TCGContext *s);
53
98
static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
54
@@ -XXX,XX +XXX,XX @@ static bool tcg_target_const_match(int64_t val, int ct,
99
intptr_t value, intptr_t addend);
55
val = (int32_t)val;
100
@@ -XXX,XX +XXX,XX @@ static void set_jmp_reset_offset(TCGContext *s, int which)
101
s->tb_jmp_reset_offset[which] = tcg_current_code_size(s);
102
}
103
104
+#ifdef TCG_TARGET_CON_SET_H
105
+#define C_PFX1(P, A) P##A
106
+#define C_PFX2(P, A, B) P##A##_##B
107
+#define C_PFX3(P, A, B, C) P##A##_##B##_##C
108
+#define C_PFX4(P, A, B, C, D) P##A##_##B##_##C##_##D
109
+#define C_PFX5(P, A, B, C, D, E) P##A##_##B##_##C##_##D##_##E
110
+#define C_PFX6(P, A, B, C, D, E, F) P##A##_##B##_##C##_##D##_##E##_##F
111
+
112
+/* Define an enumeration for the various combinations. */
113
+
114
+#define C_O0_I1(I1) C_PFX1(c_o0_i1_, I1),
115
+#define C_O0_I2(I1, I2) C_PFX2(c_o0_i2_, I1, I2),
116
+#define C_O0_I3(I1, I2, I3) C_PFX3(c_o0_i3_, I1, I2, I3),
117
+#define C_O0_I4(I1, I2, I3, I4) C_PFX4(c_o0_i4_, I1, I2, I3, I4),
118
+
119
+#define C_O1_I1(O1, I1) C_PFX2(c_o1_i1_, O1, I1),
120
+#define C_O1_I2(O1, I1, I2) C_PFX3(c_o1_i2_, O1, I1, I2),
121
+#define C_O1_I3(O1, I1, I2, I3) C_PFX4(c_o1_i3_, O1, I1, I2, I3),
122
+#define C_O1_I4(O1, I1, I2, I3, I4) C_PFX5(c_o1_i4_, O1, I1, I2, I3, I4),
123
+
124
+#define C_N1_I2(O1, I1, I2) C_PFX3(c_n1_i2_, O1, I1, I2),
125
+
126
+#define C_O2_I1(O1, O2, I1) C_PFX3(c_o2_i1_, O1, O2, I1),
127
+#define C_O2_I2(O1, O2, I1, I2) C_PFX4(c_o2_i2_, O1, O2, I1, I2),
128
+#define C_O2_I3(O1, O2, I1, I2, I3) C_PFX5(c_o2_i3_, O1, O2, I1, I2, I3),
129
+#define C_O2_I4(O1, O2, I1, I2, I3, I4) C_PFX6(c_o2_i4_, O1, O2, I1, I2, I3, I4),
130
+
131
+typedef enum {
132
+#include "tcg-target-con-set.h"
133
+} TCGConstraintSetIndex;
134
+
135
+static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode);
136
+
137
+#undef C_O0_I1
138
+#undef C_O0_I2
139
+#undef C_O0_I3
140
+#undef C_O0_I4
141
+#undef C_O1_I1
142
+#undef C_O1_I2
143
+#undef C_O1_I3
144
+#undef C_O1_I4
145
+#undef C_N1_I2
146
+#undef C_O2_I1
147
+#undef C_O2_I2
148
+#undef C_O2_I3
149
+#undef C_O2_I4
150
+
151
+/* Put all of the constraint sets into an array, indexed by the enum. */
152
+
153
+#define C_O0_I1(I1) { .args_ct_str = { #I1 } },
154
+#define C_O0_I2(I1, I2) { .args_ct_str = { #I1, #I2 } },
155
+#define C_O0_I3(I1, I2, I3) { .args_ct_str = { #I1, #I2, #I3 } },
156
+#define C_O0_I4(I1, I2, I3, I4) { .args_ct_str = { #I1, #I2, #I3, #I4 } },
157
+
158
+#define C_O1_I1(O1, I1) { .args_ct_str = { #O1, #I1 } },
159
+#define C_O1_I2(O1, I1, I2) { .args_ct_str = { #O1, #I1, #I2 } },
160
+#define C_O1_I3(O1, I1, I2, I3) { .args_ct_str = { #O1, #I1, #I2, #I3 } },
161
+#define C_O1_I4(O1, I1, I2, I3, I4) { .args_ct_str = { #O1, #I1, #I2, #I3, #I4 } },
162
+
163
+#define C_N1_I2(O1, I1, I2) { .args_ct_str = { "&" #O1, #I1, #I2 } },
164
+
165
+#define C_O2_I1(O1, O2, I1) { .args_ct_str = { #O1, #O2, #I1 } },
166
+#define C_O2_I2(O1, O2, I1, I2) { .args_ct_str = { #O1, #O2, #I1, #I2 } },
167
+#define C_O2_I3(O1, O2, I1, I2, I3) { .args_ct_str = { #O1, #O2, #I1, #I2, #I3 } },
168
+#define C_O2_I4(O1, O2, I1, I2, I3, I4) { .args_ct_str = { #O1, #O2, #I1, #I2, #I3, #I4 } },
169
+
170
+static const TCGTargetOpDef constraint_sets[] = {
171
+#include "tcg-target-con-set.h"
172
+};
173
+
174
+
175
+#undef C_O0_I1
176
+#undef C_O0_I2
177
+#undef C_O0_I3
178
+#undef C_O0_I4
179
+#undef C_O1_I1
180
+#undef C_O1_I2
181
+#undef C_O1_I3
182
+#undef C_O1_I4
183
+#undef C_N1_I2
184
+#undef C_O2_I1
185
+#undef C_O2_I2
186
+#undef C_O2_I3
187
+#undef C_O2_I4
188
+
189
+/* Expand the enumerator to be returned from tcg_target_op_def(). */
190
+
191
+#define C_O0_I1(I1) C_PFX1(c_o0_i1_, I1)
192
+#define C_O0_I2(I1, I2) C_PFX2(c_o0_i2_, I1, I2)
193
+#define C_O0_I3(I1, I2, I3) C_PFX3(c_o0_i3_, I1, I2, I3)
194
+#define C_O0_I4(I1, I2, I3, I4) C_PFX4(c_o0_i4_, I1, I2, I3, I4)
195
+
196
+#define C_O1_I1(O1, I1) C_PFX2(c_o1_i1_, O1, I1)
197
+#define C_O1_I2(O1, I1, I2) C_PFX3(c_o1_i2_, O1, I1, I2)
198
+#define C_O1_I3(O1, I1, I2, I3) C_PFX4(c_o1_i3_, O1, I1, I2, I3)
199
+#define C_O1_I4(O1, I1, I2, I3, I4) C_PFX5(c_o1_i4_, O1, I1, I2, I3, I4)
200
+
201
+#define C_N1_I2(O1, I1, I2) C_PFX3(c_n1_i2_, O1, I1, I2)
202
+
203
+#define C_O2_I1(O1, O2, I1) C_PFX3(c_o2_i1_, O1, O2, I1)
204
+#define C_O2_I2(O1, O2, I1, I2) C_PFX4(c_o2_i2_, O1, O2, I1, I2)
205
+#define C_O2_I3(O1, O2, I1, I2, I3) C_PFX5(c_o2_i3_, O1, O2, I1, I2, I3)
206
+#define C_O2_I4(O1, O2, I1, I2, I3, I4) C_PFX6(c_o2_i4_, O1, O2, I1, I2, I3, I4)
207
+
208
+#endif /* TCG_TARGET_CON_SET_H */
209
+
210
#include "tcg-target.c.inc"
211
212
/* compare a pointer @ptr and a tb_tc @s */
213
@@ -XXX,XX +XXX,XX @@ static void process_op_defs(TCGContext *s)
214
continue;
215
}
216
217
+#ifdef TCG_TARGET_CON_SET_H
218
+ /*
219
+ * Macro magic should make it impossible, but double-check that
220
+ * the array index is in range. Since the signness of an enum
221
+ * is implementation defined, force the result to unsigned.
222
+ */
223
+ unsigned con_set = tcg_target_op_def(op);
224
+ tcg_debug_assert(con_set < ARRAY_SIZE(constraint_sets));
225
+ tdefs = &constraint_sets[con_set];
226
+#else
227
tdefs = tcg_target_op_def(op);
228
/* Missing TCGTargetOpDef entry. */
229
tcg_debug_assert(tdefs != NULL);
230
+#endif
231
232
for (i = 0; i < nb_args; i++) {
233
const char *ct_str = tdefs->args_ct_str[i];
234
diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
235
index XXXXXXX..XXXXXXX 100644
236
--- a/tcg/i386/tcg-target.c.inc
237
+++ b/tcg/i386/tcg-target.c.inc
238
@@ -XXX,XX +XXX,XX @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
239
}
56
}
240
}
57
241
58
- if ((ct & TCG_CT_CONST_ZERO) && val == 0) {
242
-static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
59
- return 1;
243
+static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
60
- } else if ((ct & TCG_CT_CONST_S11) && check_fit_tl(val, 11)) {
244
{
61
+ if ((ct & TCG_CT_CONST_S11) && check_fit_tl(val, 11)) {
245
- static const TCGTargetOpDef r = { .args_ct_str = { "r" } };
62
return 1;
246
- static const TCGTargetOpDef ri_r = { .args_ct_str = { "ri", "r" } };
63
} else if ((ct & TCG_CT_CONST_S13) && check_fit_tl(val, 13)) {
247
- static const TCGTargetOpDef re_r = { .args_ct_str = { "re", "r" } };
64
return 1;
248
- static const TCGTargetOpDef qi_r = { .args_ct_str = { "qi", "r" } };
65
@@ -XXX,XX +XXX,XX @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
249
- static const TCGTargetOpDef r_r = { .args_ct_str = { "r", "r" } };
250
- static const TCGTargetOpDef r_q = { .args_ct_str = { "r", "q" } };
251
- static const TCGTargetOpDef r_re = { .args_ct_str = { "r", "re" } };
252
- static const TCGTargetOpDef r_0 = { .args_ct_str = { "r", "0" } };
253
- static const TCGTargetOpDef r_r_ri = { .args_ct_str = { "r", "r", "ri" } };
254
- static const TCGTargetOpDef r_r_re = { .args_ct_str = { "r", "r", "re" } };
255
- static const TCGTargetOpDef r_0_r = { .args_ct_str = { "r", "0", "r" } };
256
- static const TCGTargetOpDef r_0_re = { .args_ct_str = { "r", "0", "re" } };
257
- static const TCGTargetOpDef r_0_ci = { .args_ct_str = { "r", "0", "ci" } };
258
- static const TCGTargetOpDef r_L = { .args_ct_str = { "r", "L" } };
259
- static const TCGTargetOpDef L_L = { .args_ct_str = { "L", "L" } };
260
- static const TCGTargetOpDef s_L = { .args_ct_str = { "s", "L" } };
261
- static const TCGTargetOpDef r_L_L = { .args_ct_str = { "r", "L", "L" } };
262
- static const TCGTargetOpDef r_r_L = { .args_ct_str = { "r", "r", "L" } };
263
- static const TCGTargetOpDef L_L_L = { .args_ct_str = { "L", "L", "L" } };
264
- static const TCGTargetOpDef s_L_L = { .args_ct_str = { "s", "L", "L" } };
265
- static const TCGTargetOpDef r_r_L_L
266
- = { .args_ct_str = { "r", "r", "L", "L" } };
267
- static const TCGTargetOpDef L_L_L_L
268
- = { .args_ct_str = { "L", "L", "L", "L" } };
269
- static const TCGTargetOpDef x_x = { .args_ct_str = { "x", "x" } };
270
- static const TCGTargetOpDef x_x_x = { .args_ct_str = { "x", "x", "x" } };
271
- static const TCGTargetOpDef x_x_x_x
272
- = { .args_ct_str = { "x", "x", "x", "x" } };
273
- static const TCGTargetOpDef x_r = { .args_ct_str = { "x", "r" } };
274
-
275
switch (op) {
276
case INDEX_op_goto_ptr:
277
- return &r;
278
+ return C_O0_I1(r);
279
280
case INDEX_op_ld8u_i32:
281
case INDEX_op_ld8u_i64:
282
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
283
case INDEX_op_ld32u_i64:
284
case INDEX_op_ld32s_i64:
285
case INDEX_op_ld_i64:
286
- return &r_r;
287
+ return C_O1_I1(r, r);
288
289
case INDEX_op_st8_i32:
290
case INDEX_op_st8_i64:
291
- return &qi_r;
292
+ return C_O0_I2(qi, r);
293
+
294
case INDEX_op_st16_i32:
295
case INDEX_op_st16_i64:
296
case INDEX_op_st_i32:
297
case INDEX_op_st32_i64:
298
- return &ri_r;
299
+ return C_O0_I2(ri, r);
300
+
301
case INDEX_op_st_i64:
66
case INDEX_op_st_i64:
302
- return &re_r;
67
case INDEX_op_qemu_st_i32:
303
+ return C_O0_I2(re, r);
68
case INDEX_op_qemu_st_i64:
69
- return C_O0_I2(rZ, r);
70
+ return C_O0_I2(rz, r);
304
71
305
case INDEX_op_add_i32:
72
case INDEX_op_add_i32:
306
case INDEX_op_add_i64:
73
case INDEX_op_add_i64:
307
- return &r_r_re;
74
@@ -XXX,XX +XXX,XX @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
308
+ return C_O1_I2(r, r, re);
75
case INDEX_op_setcond_i64:
309
+
76
case INDEX_op_negsetcond_i32:
310
case INDEX_op_sub_i32:
77
case INDEX_op_negsetcond_i64:
311
case INDEX_op_sub_i64:
78
- return C_O1_I2(r, rZ, rJ);
312
case INDEX_op_mul_i32:
79
+ return C_O1_I2(r, rz, rJ);
313
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
314
case INDEX_op_or_i64:
315
case INDEX_op_xor_i32:
316
case INDEX_op_xor_i64:
317
- return &r_0_re;
318
+ return C_O1_I2(r, 0, re);
319
320
case INDEX_op_and_i32:
321
case INDEX_op_and_i64:
322
- {
323
- static const TCGTargetOpDef and
324
- = { .args_ct_str = { "r", "0", "reZ" } };
325
- return &and;
326
- }
327
- break;
328
+ return C_O1_I2(r, 0, reZ);
329
+
330
case INDEX_op_andc_i32:
331
case INDEX_op_andc_i64:
332
- {
333
- static const TCGTargetOpDef andc
334
- = { .args_ct_str = { "r", "r", "rI" } };
335
- return &andc;
336
- }
337
- break;
338
+ return C_O1_I2(r, r, rI);
339
340
case INDEX_op_shl_i32:
341
case INDEX_op_shl_i64:
342
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
343
case INDEX_op_shr_i64:
344
case INDEX_op_sar_i32:
345
case INDEX_op_sar_i64:
346
- return have_bmi2 ? &r_r_ri : &r_0_ci;
347
+ return have_bmi2 ? C_O1_I2(r, r, ri) : C_O1_I2(r, 0, ci);
348
+
349
case INDEX_op_rotl_i32:
350
case INDEX_op_rotl_i64:
351
case INDEX_op_rotr_i32:
352
case INDEX_op_rotr_i64:
353
- return &r_0_ci;
354
+ return C_O1_I2(r, 0, ci);
355
80
356
case INDEX_op_brcond_i32:
81
case INDEX_op_brcond_i32:
357
case INDEX_op_brcond_i64:
82
case INDEX_op_brcond_i64:
358
- return &r_re;
83
- return C_O0_I2(rZ, rJ);
359
+ return C_O0_I2(r, re);
84
+ return C_O0_I2(rz, rJ);
360
361
case INDEX_op_bswap16_i32:
362
case INDEX_op_bswap16_i64:
363
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
364
case INDEX_op_not_i32:
365
case INDEX_op_not_i64:
366
case INDEX_op_extrh_i64_i32:
367
- return &r_0;
368
+ return C_O1_I1(r, 0);
369
370
case INDEX_op_ext8s_i32:
371
case INDEX_op_ext8s_i64:
372
case INDEX_op_ext8u_i32:
373
case INDEX_op_ext8u_i64:
374
- return &r_q;
375
+ return C_O1_I1(r, q);
376
+
377
case INDEX_op_ext16s_i32:
378
case INDEX_op_ext16s_i64:
379
case INDEX_op_ext16u_i32:
380
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
381
case INDEX_op_sextract_i32:
382
case INDEX_op_ctpop_i32:
383
case INDEX_op_ctpop_i64:
384
- return &r_r;
385
+ return C_O1_I1(r, r);
386
+
387
case INDEX_op_extract2_i32:
388
case INDEX_op_extract2_i64:
389
- return &r_0_r;
390
+ return C_O1_I2(r, 0, r);
391
392
case INDEX_op_deposit_i32:
393
case INDEX_op_deposit_i64:
394
- {
395
- static const TCGTargetOpDef dep
396
- = { .args_ct_str = { "Q", "0", "Q" } };
397
- return &dep;
398
- }
399
+ return C_O1_I2(Q, 0, Q);
400
+
401
case INDEX_op_setcond_i32:
402
case INDEX_op_setcond_i64:
403
- {
404
- static const TCGTargetOpDef setc
405
- = { .args_ct_str = { "q", "r", "re" } };
406
- return &setc;
407
- }
408
+ return C_O1_I2(q, r, re);
409
+
410
case INDEX_op_movcond_i32:
85
case INDEX_op_movcond_i32:
411
case INDEX_op_movcond_i64:
86
case INDEX_op_movcond_i64:
412
- {
87
- return C_O1_I4(r, rZ, rJ, rI, 0);
413
- static const TCGTargetOpDef movc
88
+ return C_O1_I4(r, rz, rJ, rI, 0);
414
- = { .args_ct_str = { "r", "r", "re", "r", "0" } };
415
- return &movc;
416
- }
417
+ return C_O1_I4(r, r, re, r, 0);
418
+
419
case INDEX_op_div2_i32:
420
case INDEX_op_div2_i64:
421
case INDEX_op_divu2_i32:
422
case INDEX_op_divu2_i64:
423
- {
424
- static const TCGTargetOpDef div2
425
- = { .args_ct_str = { "a", "d", "0", "1", "r" } };
426
- return &div2;
427
- }
428
+ return C_O2_I3(a, d, 0, 1, r);
429
+
430
case INDEX_op_mulu2_i32:
431
case INDEX_op_mulu2_i64:
432
case INDEX_op_muls2_i32:
433
case INDEX_op_muls2_i64:
434
- {
435
- static const TCGTargetOpDef mul2
436
- = { .args_ct_str = { "a", "d", "a", "r" } };
437
- return &mul2;
438
- }
439
+ return C_O2_I2(a, d, a, r);
440
+
441
case INDEX_op_add2_i32:
89
case INDEX_op_add2_i32:
442
case INDEX_op_add2_i64:
90
case INDEX_op_add2_i64:
443
case INDEX_op_sub2_i32:
91
case INDEX_op_sub2_i32:
444
case INDEX_op_sub2_i64:
92
case INDEX_op_sub2_i64:
445
- {
93
- return C_O2_I4(r, r, rZ, rZ, rJ, rJ);
446
- static const TCGTargetOpDef arith2
94
+ return C_O2_I4(r, r, rz, rz, rJ, rJ);
447
- = { .args_ct_str = { "r", "r", "0", "1", "re", "re" } };
95
case INDEX_op_mulu2_i32:
448
- return &arith2;
96
case INDEX_op_muls2_i32:
449
- }
97
- return C_O2_I2(r, r, rZ, rJ);
450
+ return C_O2_I4(r, r, 0, 1, re, re);
98
+ return C_O2_I2(r, r, rz, rJ);
451
+
99
case INDEX_op_muluh_i64:
452
case INDEX_op_ctz_i32:
100
return C_O1_I2(r, r, r);
453
case INDEX_op_ctz_i64:
101
454
- {
455
- static const TCGTargetOpDef ctz[2] = {
456
- { .args_ct_str = { "&r", "r", "r" } },
457
- { .args_ct_str = { "&r", "r", "rW" } },
458
- };
459
- return &ctz[have_bmi1];
460
- }
461
+ return have_bmi1 ? C_N1_I2(r, r, rW) : C_N1_I2(r, r, r);
462
+
463
case INDEX_op_clz_i32:
464
case INDEX_op_clz_i64:
465
- {
466
- static const TCGTargetOpDef clz[2] = {
467
- { .args_ct_str = { "&r", "r", "r" } },
468
- { .args_ct_str = { "&r", "r", "rW" } },
469
- };
470
- return &clz[have_lzcnt];
471
- }
472
+ return have_lzcnt ? C_N1_I2(r, r, rW) : C_N1_I2(r, r, r);
473
474
case INDEX_op_qemu_ld_i32:
475
- return TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &r_L : &r_L_L;
476
+ return (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS
477
+ ? C_O1_I1(r, L) : C_O1_I2(r, L, L));
478
+
479
case INDEX_op_qemu_st_i32:
480
- return TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &L_L : &L_L_L;
481
+ return (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS
482
+ ? C_O0_I2(L, L) : C_O0_I3(L, L, L));
483
case INDEX_op_qemu_st8_i32:
484
- return TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &s_L : &s_L_L;
485
+ return (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS
486
+ ? C_O0_I2(s, L) : C_O0_I3(s, L, L));
487
+
488
case INDEX_op_qemu_ld_i64:
489
- return (TCG_TARGET_REG_BITS == 64 ? &r_L
490
- : TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &r_r_L
491
- : &r_r_L_L);
492
+ return (TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, L)
493
+ : TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? C_O2_I1(r, r, L)
494
+ : C_O2_I2(r, r, L, L));
495
+
496
case INDEX_op_qemu_st_i64:
497
- return (TCG_TARGET_REG_BITS == 64 ? &L_L
498
- : TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &L_L_L
499
- : &L_L_L_L);
500
+ return (TCG_TARGET_REG_BITS == 64 ? C_O0_I2(L, L)
501
+ : TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? C_O0_I3(L, L, L)
502
+ : C_O0_I4(L, L, L, L));
503
504
case INDEX_op_brcond2_i32:
505
- {
506
- static const TCGTargetOpDef b2
507
- = { .args_ct_str = { "r", "r", "ri", "ri" } };
508
- return &b2;
509
- }
510
+ return C_O0_I4(r, r, ri, ri);
511
+
512
case INDEX_op_setcond2_i32:
513
- {
514
- static const TCGTargetOpDef s2
515
- = { .args_ct_str = { "r", "r", "r", "ri", "ri" } };
516
- return &s2;
517
- }
518
+ return C_O1_I4(r, r, r, ri, ri);
519
520
case INDEX_op_ld_vec:
521
- case INDEX_op_st_vec:
522
case INDEX_op_dupm_vec:
523
- return &x_r;
524
+ return C_O1_I1(x, r);
525
+
526
+ case INDEX_op_st_vec:
527
+ return C_O0_I2(x, r);
528
529
case INDEX_op_add_vec:
530
case INDEX_op_sub_vec:
531
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
532
#if TCG_TARGET_REG_BITS == 32
533
case INDEX_op_dup2_vec:
534
#endif
535
- return &x_x_x;
536
+ return C_O1_I2(x, x, x);
537
+
538
case INDEX_op_abs_vec:
539
case INDEX_op_dup_vec:
540
case INDEX_op_shli_vec:
541
case INDEX_op_shri_vec:
542
case INDEX_op_sari_vec:
543
case INDEX_op_x86_psrldq_vec:
544
- return &x_x;
545
+ return C_O1_I1(x, x);
546
+
547
case INDEX_op_x86_vpblendvb_vec:
548
- return &x_x_x_x;
549
+ return C_O1_I3(x, x, x, x);
550
551
default:
552
- break;
553
+ g_assert_not_reached();
554
}
555
- return NULL;
556
}
557
558
int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
559
--
102
--
560
2.25.1
103
2.43.0
561
104
562
105
diff view generated by jsdifflib
[PULL 04/24] tcg/i386: Tidy register constraint definitions
[PULL 20/24] elfload: Fix alignment when unmapping excess reservation
1
Create symbolic constants for all low-byte-addressable
1
From: Fabiano Rosas <farosas@suse.de>
2
and second-byte-addressable registers. Create a symbol
3
for the registers that need reserving for softmmu.
4
2
5
There is no functional change for 's', as this letter is
3
When complying with the alignment requested in the ELF and unmapping
6
only used for i386. The BYTEL name is correct for the
4
the excess reservation, having align_end not aligned to the guest page
7
action we wish from the constraint.
5
causes the unmap to be rejected by the alignment check at
6
target_munmap and later brk adjustments hit an EEXIST.
8
7
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Fix by aligning the start of region to be unmapped.
9
10
Fixes: c81d1fafa6 ("linux-user: Honor elf alignment when placing images")
11
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1913
12
Signed-off-by: Fabiano Rosas <farosas@suse.de>
13
[rth: Align load_end as well.]
10
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
14
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
15
Message-ID: <20250213143558.10504-1-farosas@suse.de>
11
---
16
---
12
tcg/i386/tcg-target.c.inc | 40 +++++++++++++++++++--------------------
17
linux-user/elfload.c | 4 ++--
13
1 file changed, 20 insertions(+), 20 deletions(-)
18
1 file changed, 2 insertions(+), 2 deletions(-)
14
19
15
diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
20
diff --git a/linux-user/elfload.c b/linux-user/elfload.c
16
index XXXXXXX..XXXXXXX 100644
21
index XXXXXXX..XXXXXXX 100644
17
--- a/tcg/i386/tcg-target.c.inc
22
--- a/linux-user/elfload.c
18
+++ b/tcg/i386/tcg-target.c.inc
23
+++ b/linux-user/elfload.c
19
@@ -XXX,XX +XXX,XX @@ static const int tcg_target_call_oarg_regs[] = {
24
@@ -XXX,XX +XXX,XX @@ static void load_elf_image(const char *image_name, const ImageSource *src,
20
# define TCG_REG_L1 TCG_REG_EDX
25
21
#endif
26
if (align_size != reserve_size) {
22
27
abi_ulong align_addr = ROUND_UP(load_addr, align);
23
+#define ALL_BYTEH_REGS 0x0000000fu
28
- abi_ulong align_end = align_addr + reserve_size;
24
+#if TCG_TARGET_REG_BITS == 64
29
- abi_ulong load_end = load_addr + align_size;
25
+# define ALL_GENERAL_REGS 0x0000ffffu
30
+ abi_ulong align_end = TARGET_PAGE_ALIGN(align_addr + reserve_size);
26
+# define ALL_VECTOR_REGS 0xffff0000u
31
+ abi_ulong load_end = TARGET_PAGE_ALIGN(load_addr + align_size);
27
+# define ALL_BYTEL_REGS ALL_GENERAL_REGS
32
28
+#else
33
if (align_addr != load_addr) {
29
+# define ALL_GENERAL_REGS 0x000000ffu
34
target_munmap(load_addr, align_addr - load_addr);
30
+# define ALL_VECTOR_REGS 0x00ff0000u
31
+# define ALL_BYTEL_REGS ALL_BYTEH_REGS
32
+#endif
33
+#ifdef CONFIG_SOFTMMU
34
+# define SOFTMMU_RESERVE_REGS ((1 << TCG_REG_L0) | (1 << TCG_REG_L1))
35
+#else
36
+# define SOFTMMU_RESERVE_REGS 0
37
+#endif
38
+
39
/* The host compiler should supply <cpuid.h> to enable runtime features
40
detection, as we're not going to go so far as our own inline assembly.
41
If not available, default values will be assumed. */
42
@@ -XXX,XX +XXX,XX @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
43
return true;
44
}
45
46
-#if TCG_TARGET_REG_BITS == 64
47
-#define ALL_GENERAL_REGS 0x0000ffffu
48
-#define ALL_VECTOR_REGS 0xffff0000u
49
-#else
50
-#define ALL_GENERAL_REGS 0x000000ffu
51
-#define ALL_VECTOR_REGS 0x00ff0000u
52
-#endif
53
-
54
/* parse target specific constraints */
55
static const char *target_parse_constraint(TCGArgConstraint *ct,
56
const char *ct_str, TCGType type)
57
@@ -XXX,XX +XXX,XX @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
58
break;
59
case 'q':
60
/* A register that can be used as a byte operand. */
61
- ct->regs = TCG_TARGET_REG_BITS == 64 ? 0xffff : 0xf;
62
+ ct->regs |= ALL_BYTEL_REGS;
63
break;
64
case 'Q':
65
/* A register with an addressable second byte (e.g. %ah). */
66
- ct->regs = 0xf;
67
+ ct->regs |= ALL_BYTEH_REGS;
68
break;
69
case 'r':
70
/* A general register. */
71
@@ -XXX,XX +XXX,XX @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
72
73
case 'L':
74
/* qemu_ld/st data+address constraint */
75
- ct->regs = TCG_TARGET_REG_BITS == 64 ? 0xffff : 0xff;
76
-#ifdef CONFIG_SOFTMMU
77
- tcg_regset_reset_reg(ct->regs, TCG_REG_L0);
78
- tcg_regset_reset_reg(ct->regs, TCG_REG_L1);
79
-#endif
80
+ ct->regs |= ALL_GENERAL_REGS & ~SOFTMMU_RESERVE_REGS;
81
break;
82
case 's':
83
/* qemu_st8_i32 data constraint */
84
- ct->regs = 0xf;
85
-#ifdef CONFIG_SOFTMMU
86
- tcg_regset_reset_reg(ct->regs, TCG_REG_L0);
87
- tcg_regset_reset_reg(ct->regs, TCG_REG_L1);
88
-#endif
89
+ ct->regs |= ALL_BYTEL_REGS & ~SOFTMMU_RESERVE_REGS;
90
break;
91
92
case 'e':
93
--
35
--
94
2.25.1
36
2.43.0
95
96
diff view generated by jsdifflib
[PULL 12/24] tcg/s390: Split out target constraints to tcg-target-con-str.h
[PULL 21/24] linux-user: Move TARGET_SA_RESTORER out of generic/signal.h
1
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
1
From: Andreas Schwab <schwab@suse.de>
2
3
SA_RESTORER and the associated sa_restorer field of struct sigaction are
4
an obsolete feature, not expected to be used by future architectures.
5
They are also absent on RISC-V, LoongArch, Hexagon and OpenRISC, but
6
defined due to their use of generic/signal.h. This leads to corrupted
7
data and out-of-bounds accesses.
8
9
Move the definition of TARGET_SA_RESTORER out of generic/signal.h into the
10
target_signal.h files that need it. Note that m68k has the sa_restorer
11
field, but does not use it and does not define SA_RESTORER.
12
13
Reported-by: Thomas Weißschuh <thomas@t-8ch.de>
14
Signed-off-by: Andreas Schwab <schwab@suse.de>
15
Reviewed-by: Thomas Weißschuh <thomas@t-8ch.de>
16
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
17
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
18
Message-ID: <mvmed060xc9.fsf@suse.de>
3
---
19
---
4
tcg/s390/tcg-target-con-str.h | 28 ++++++++++++++++++
20
linux-user/aarch64/target_signal.h | 2 ++
5
tcg/s390/tcg-target.h | 1 +
21
linux-user/arm/target_signal.h | 2 ++
6
tcg/s390/tcg-target.c.inc | 53 +++++++++--------------------------
22
linux-user/generic/signal.h | 1 -
7
3 files changed, 42 insertions(+), 40 deletions(-)
23
linux-user/i386/target_signal.h | 2 ++
8
create mode 100644 tcg/s390/tcg-target-con-str.h
24
linux-user/m68k/target_signal.h | 1 +
25
linux-user/microblaze/target_signal.h | 2 ++
26
linux-user/ppc/target_signal.h | 2 ++
27
linux-user/s390x/target_signal.h | 2 ++
28
linux-user/sh4/target_signal.h | 2 ++
29
linux-user/x86_64/target_signal.h | 2 ++
30
linux-user/xtensa/target_signal.h | 2 ++
31
11 files changed, 19 insertions(+), 1 deletion(-)
9
32
10
diff --git a/tcg/s390/tcg-target-con-str.h b/tcg/s390/tcg-target-con-str.h
33
diff --git a/linux-user/aarch64/target_signal.h b/linux-user/aarch64/target_signal.h
11
new file mode 100644
34
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX
35
--- a/linux-user/aarch64/target_signal.h
13
--- /dev/null
36
+++ b/linux-user/aarch64/target_signal.h
14
+++ b/tcg/s390/tcg-target-con-str.h
15
@@ -XXX,XX +XXX,XX @@
37
@@ -XXX,XX +XXX,XX @@
16
+/* SPDX-License-Identifier: MIT */
38
17
+/*
39
#include "../generic/signal.h"
18
+ * Define S390 target-specific operand constraints.
40
19
+ * Copyright (c) 2021 Linaro
41
+#define TARGET_SA_RESTORER 0x04000000
20
+ */
21
+
42
+
22
+/*
43
#define TARGET_SEGV_MTEAERR 8 /* Asynchronous ARM MTE error */
23
+ * Define constraint letters for register sets:
44
#define TARGET_SEGV_MTESERR 9 /* Synchronous ARM MTE exception */
24
+ * REGS(letter, register_mask)
45
25
+ */
46
diff --git a/linux-user/arm/target_signal.h b/linux-user/arm/target_signal.h
26
+REGS('r', ALL_GENERAL_REGS)
47
index XXXXXXX..XXXXXXX 100644
27
+REGS('L', ALL_GENERAL_REGS & ~SOFTMMU_RESERVE_REGS)
48
--- a/linux-user/arm/target_signal.h
28
+/*
49
+++ b/linux-user/arm/target_signal.h
29
+ * A (single) even/odd pair for division.
50
@@ -XXX,XX +XXX,XX @@
30
+ * TODO: Add something to the register allocator to allow
51
31
+ * this kind of regno+1 pairing to be done more generally.
52
#include "../generic/signal.h"
32
+ */
53
33
+REGS('a', 1u << TCG_REG_R2)
54
+#define TARGET_SA_RESTORER 0x04000000
34
+REGS('b', 1u << TCG_REG_R3)
35
+
55
+
36
+/*
56
#define TARGET_ARCH_HAS_SETUP_FRAME
37
+ * Define constraint letters for constants:
57
#define TARGET_ARCH_HAS_SIGTRAMP_PAGE 1
38
+ * CONST(letter, TCG_CT_CONST_* bit set)
58
39
+ */
59
diff --git a/linux-user/generic/signal.h b/linux-user/generic/signal.h
40
+CONST('A', TCG_CT_CONST_S33)
41
+CONST('I', TCG_CT_CONST_S16)
42
+CONST('J', TCG_CT_CONST_S32)
43
+CONST('Z', TCG_CT_CONST_ZERO)
44
diff --git a/tcg/s390/tcg-target.h b/tcg/s390/tcg-target.h
45
index XXXXXXX..XXXXXXX 100644
60
index XXXXXXX..XXXXXXX 100644
46
--- a/tcg/s390/tcg-target.h
61
--- a/linux-user/generic/signal.h
47
+++ b/tcg/s390/tcg-target.h
62
+++ b/linux-user/generic/signal.h
48
@@ -XXX,XX +XXX,XX @@ static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_rx,
63
@@ -XXX,XX +XXX,XX @@
49
#define TCG_TARGET_NEED_LDST_LABELS
64
#define TARGET_SA_RESTART 0x10000000
65
#define TARGET_SA_NODEFER 0x40000000
66
#define TARGET_SA_RESETHAND 0x80000000
67
-#define TARGET_SA_RESTORER 0x04000000
68
69
#define TARGET_SIGHUP 1
70
#define TARGET_SIGINT 2
71
diff --git a/linux-user/i386/target_signal.h b/linux-user/i386/target_signal.h
72
index XXXXXXX..XXXXXXX 100644
73
--- a/linux-user/i386/target_signal.h
74
+++ b/linux-user/i386/target_signal.h
75
@@ -XXX,XX +XXX,XX @@
76
77
#include "../generic/signal.h"
78
79
+#define TARGET_SA_RESTORER 0x04000000
80
+
81
#define TARGET_ARCH_HAS_SETUP_FRAME
82
#define TARGET_ARCH_HAS_SIGTRAMP_PAGE 1
83
84
diff --git a/linux-user/m68k/target_signal.h b/linux-user/m68k/target_signal.h
85
index XXXXXXX..XXXXXXX 100644
86
--- a/linux-user/m68k/target_signal.h
87
+++ b/linux-user/m68k/target_signal.h
88
@@ -XXX,XX +XXX,XX @@
89
90
#include "../generic/signal.h"
91
92
+#define TARGET_ARCH_HAS_SA_RESTORER 1
93
#define TARGET_ARCH_HAS_SETUP_FRAME
94
#define TARGET_ARCH_HAS_SIGTRAMP_PAGE 1
95
96
diff --git a/linux-user/microblaze/target_signal.h b/linux-user/microblaze/target_signal.h
97
index XXXXXXX..XXXXXXX 100644
98
--- a/linux-user/microblaze/target_signal.h
99
+++ b/linux-user/microblaze/target_signal.h
100
@@ -XXX,XX +XXX,XX @@
101
102
#include "../generic/signal.h"
103
104
+#define TARGET_SA_RESTORER 0x04000000
105
+
106
#define TARGET_ARCH_HAS_SIGTRAMP_PAGE 1
107
108
#endif /* MICROBLAZE_TARGET_SIGNAL_H */
109
diff --git a/linux-user/ppc/target_signal.h b/linux-user/ppc/target_signal.h
110
index XXXXXXX..XXXXXXX 100644
111
--- a/linux-user/ppc/target_signal.h
112
+++ b/linux-user/ppc/target_signal.h
113
@@ -XXX,XX +XXX,XX @@
114
115
#include "../generic/signal.h"
116
117
+#define TARGET_SA_RESTORER 0x04000000
118
+
119
#if !defined(TARGET_PPC64)
120
#define TARGET_ARCH_HAS_SETUP_FRAME
50
#endif
121
#endif
51
#define TCG_TARGET_NEED_POOL_LABELS
122
diff --git a/linux-user/s390x/target_signal.h b/linux-user/s390x/target_signal.h
52
+#define TCG_TARGET_CON_STR_H
123
index XXXXXXX..XXXXXXX 100644
124
--- a/linux-user/s390x/target_signal.h
125
+++ b/linux-user/s390x/target_signal.h
126
@@ -XXX,XX +XXX,XX @@
127
128
#include "../generic/signal.h"
129
130
+#define TARGET_SA_RESTORER 0x04000000
131
+
132
#define TARGET_ARCH_HAS_SETUP_FRAME
133
#define TARGET_ARCH_HAS_SIGTRAMP_PAGE 1
134
135
diff --git a/linux-user/sh4/target_signal.h b/linux-user/sh4/target_signal.h
136
index XXXXXXX..XXXXXXX 100644
137
--- a/linux-user/sh4/target_signal.h
138
+++ b/linux-user/sh4/target_signal.h
139
@@ -XXX,XX +XXX,XX @@
140
141
#include "../generic/signal.h"
142
143
+#define TARGET_SA_RESTORER 0x04000000
144
+
145
#define TARGET_ARCH_HAS_SETUP_FRAME
146
#define TARGET_ARCH_HAS_SIGTRAMP_PAGE 1
147
148
diff --git a/linux-user/x86_64/target_signal.h b/linux-user/x86_64/target_signal.h
149
index XXXXXXX..XXXXXXX 100644
150
--- a/linux-user/x86_64/target_signal.h
151
+++ b/linux-user/x86_64/target_signal.h
152
@@ -XXX,XX +XXX,XX @@
153
154
#include "../generic/signal.h"
155
156
+#define TARGET_SA_RESTORER 0x04000000
157
+
158
/* For x86_64, use of SA_RESTORER is mandatory. */
159
#define TARGET_ARCH_HAS_SIGTRAMP_PAGE 0
160
161
diff --git a/linux-user/xtensa/target_signal.h b/linux-user/xtensa/target_signal.h
162
index XXXXXXX..XXXXXXX 100644
163
--- a/linux-user/xtensa/target_signal.h
164
+++ b/linux-user/xtensa/target_signal.h
165
@@ -XXX,XX +XXX,XX @@
166
167
#include "../generic/signal.h"
168
169
+#define TARGET_SA_RESTORER 0x04000000
170
+
171
#define TARGET_ARCH_HAS_SIGTRAMP_PAGE 1
53
172
54
#endif
173
#endif
55
diff --git a/tcg/s390/tcg-target.c.inc b/tcg/s390/tcg-target.c.inc
56
index XXXXXXX..XXXXXXX 100644
57
--- a/tcg/s390/tcg-target.c.inc
58
+++ b/tcg/s390/tcg-target.c.inc
59
@@ -XXX,XX +XXX,XX @@
60
#define TCG_CT_CONST_S33 0x400
61
#define TCG_CT_CONST_ZERO 0x800
62
63
+#define ALL_GENERAL_REGS MAKE_64BIT_MASK(0, 16)
64
+/*
65
+ * For softmmu, we need to avoid conflicts with the first 3
66
+ * argument registers to perform the tlb lookup, and to call
67
+ * the helper function.
68
+ */
69
+#ifdef CONFIG_SOFTMMU
70
+#define SOFTMMU_RESERVE_REGS MAKE_64BIT_MASK(TCG_REG_R2, 3)
71
+#else
72
+#define SOFTMMU_RESERVE_REGS 0
73
+#endif
74
+
75
+
76
/* Several places within the instruction set 0 means "no register"
77
rather than TCG_REG_R0. */
78
#define TCG_REG_NONE 0
79
@@ -XXX,XX +XXX,XX @@ static bool patch_reloc(tcg_insn_unit *src_rw, int type,
80
return false;
81
}
82
83
-/* parse target specific constraints */
84
-static const char *target_parse_constraint(TCGArgConstraint *ct,
85
- const char *ct_str, TCGType type)
86
-{
87
- switch (*ct_str++) {
88
- case 'r': /* all registers */
89
- ct->regs = 0xffff;
90
- break;
91
- case 'L': /* qemu_ld/st constraint */
92
- ct->regs = 0xffff;
93
- tcg_regset_reset_reg(ct->regs, TCG_REG_R2);
94
- tcg_regset_reset_reg(ct->regs, TCG_REG_R3);
95
- tcg_regset_reset_reg(ct->regs, TCG_REG_R4);
96
- break;
97
- case 'a': /* force R2 for division */
98
- ct->regs = 0;
99
- tcg_regset_set_reg(ct->regs, TCG_REG_R2);
100
- break;
101
- case 'b': /* force R3 for division */
102
- ct->regs = 0;
103
- tcg_regset_set_reg(ct->regs, TCG_REG_R3);
104
- break;
105
- case 'A':
106
- ct->ct |= TCG_CT_CONST_S33;
107
- break;
108
- case 'I':
109
- ct->ct |= TCG_CT_CONST_S16;
110
- break;
111
- case 'J':
112
- ct->ct |= TCG_CT_CONST_S32;
113
- break;
114
- case 'Z':
115
- ct->ct |= TCG_CT_CONST_ZERO;
116
- break;
117
- default:
118
- return NULL;
119
- }
120
- return ct_str;
121
-}
122
-
123
/* Test if a constant matches the constraint. */
124
static int tcg_target_const_match(tcg_target_long val, TCGType type,
125
const TCGArgConstraint *arg_ct)
126
--
174
--
127
2.25.1
175
2.43.0
128
176
129
177
diff view generated by jsdifflib
[PULL 07/24] tcg/aarch64: Split out target constraints to tcg-target-con-str.h
[PULL 22/24] target/sparc: Fix register selection for all F*TOx and FxTO* instructions
1
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
1
From: Mikael Szreder <git@miszr.win>
2
3
A bug was introduced in commit 0bba7572d40d which causes the fdtox
4
and fqtox instructions to incorrectly select the destination registers.
5
More information and a test program can be found in issue #2802.
6
7
Fixes: 0bba7572d40d ("target/sparc: Perform DFPREG/QFPREG in decodetree")
8
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2802
9
Signed-off-by: Mikael Szreder <git@miszr.win>
10
Acked-by: Artyom Tarasenko <atar4qemu@gmail.com>
11
[rth: Squash patches together, since the second fixes a typo in the first.]
2
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
13
Message-ID: <20250205090333.19626-3-git@miszr.win>
3
---
14
---
4
tcg/aarch64/tcg-target-con-str.h | 24 +++++++++++++++
15
target/sparc/insns.decode | 12 ++++++------
5
tcg/aarch64/tcg-target.h | 1 +
16
1 file changed, 6 insertions(+), 6 deletions(-)
6
tcg/aarch64/tcg-target.c.inc | 51 +++++---------------------------
7
3 files changed, 33 insertions(+), 43 deletions(-)
8
create mode 100644 tcg/aarch64/tcg-target-con-str.h
9
17
10
diff --git a/tcg/aarch64/tcg-target-con-str.h b/tcg/aarch64/tcg-target-con-str.h
18
diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode
11
new file mode 100644
12
index XXXXXXX..XXXXXXX
13
--- /dev/null
14
+++ b/tcg/aarch64/tcg-target-con-str.h
15
@@ -XXX,XX +XXX,XX @@
16
+/* SPDX-License-Identifier: GPL-2.0-or-later */
17
+/*
18
+ * Define AArch64 target-specific operand constraints.
19
+ * Copyright (c) 2021 Linaro
20
+ */
21
+
22
+/*
23
+ * Define constraint letters for register sets:
24
+ * REGS(letter, register_mask)
25
+ */
26
+REGS('r', ALL_GENERAL_REGS)
27
+REGS('l', ALL_QLDST_REGS)
28
+REGS('w', ALL_VECTOR_REGS)
29
+
30
+/*
31
+ * Define constraint letters for constants:
32
+ * CONST(letter, TCG_CT_CONST_* bit set)
33
+ */
34
+CONST('A', TCG_CT_CONST_AIMM)
35
+CONST('L', TCG_CT_CONST_LIMM)
36
+CONST('M', TCG_CT_CONST_MONE)
37
+CONST('O', TCG_CT_CONST_ORRI)
38
+CONST('N', TCG_CT_CONST_ANDI)
39
+CONST('Z', TCG_CT_CONST_ZERO)
40
diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h
41
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
42
--- a/tcg/aarch64/tcg-target.h
20
--- a/target/sparc/insns.decode
43
+++ b/tcg/aarch64/tcg-target.h
21
+++ b/target/sparc/insns.decode
44
@@ -XXX,XX +XXX,XX @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t);
22
@@ -XXX,XX +XXX,XX @@ FdMULq 10 ..... 110100 ..... 0 0110 1110 ..... @q_d_d
45
#define TCG_TARGET_NEED_LDST_LABELS
23
FNHADDs 10 ..... 110100 ..... 0 0111 0001 ..... @r_r_r
46
#endif
24
FNHADDd 10 ..... 110100 ..... 0 0111 0010 ..... @d_d_d
47
#define TCG_TARGET_NEED_POOL_LABELS
25
FNsMULd 10 ..... 110100 ..... 0 0111 1001 ..... @d_r_r
48
+#define TCG_TARGET_CON_STR_H
26
-FsTOx 10 ..... 110100 00000 0 1000 0001 ..... @r_r2
49
27
-FdTOx 10 ..... 110100 00000 0 1000 0010 ..... @r_d2
50
#endif /* AARCH64_TCG_TARGET_H */
28
-FqTOx 10 ..... 110100 00000 0 1000 0011 ..... @r_q2
51
diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc
29
-FxTOs 10 ..... 110100 00000 0 1000 0100 ..... @r_r2
52
index XXXXXXX..XXXXXXX 100644
30
-FxTOd 10 ..... 110100 00000 0 1000 1000 ..... @d_r2
53
--- a/tcg/aarch64/tcg-target.c.inc
31
-FxTOq 10 ..... 110100 00000 0 1000 1100 ..... @q_r2
54
+++ b/tcg/aarch64/tcg-target.c.inc
32
+FsTOx 10 ..... 110100 00000 0 1000 0001 ..... @d_r2
55
@@ -XXX,XX +XXX,XX @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
33
+FdTOx 10 ..... 110100 00000 0 1000 0010 ..... @d_d2
56
#define TCG_CT_CONST_ORRI 0x1000
34
+FqTOx 10 ..... 110100 00000 0 1000 0011 ..... @d_q2
57
#define TCG_CT_CONST_ANDI 0x2000
35
+FxTOs 10 ..... 110100 00000 0 1000 0100 ..... @r_d2
58
36
+FxTOd 10 ..... 110100 00000 0 1000 1000 ..... @d_d2
59
-/* parse target specific constraints */
37
+FxTOq 10 ..... 110100 00000 0 1000 1100 ..... @q_d2
60
-static const char *target_parse_constraint(TCGArgConstraint *ct,
38
FiTOs 10 ..... 110100 00000 0 1100 0100 ..... @r_r2
61
- const char *ct_str, TCGType type)
39
FdTOs 10 ..... 110100 00000 0 1100 0110 ..... @r_d2
62
-{
40
FqTOs 10 ..... 110100 00000 0 1100 0111 ..... @r_q2
63
- switch (*ct_str++) {
64
- case 'r': /* general registers */
65
- ct->regs |= 0xffffffffu;
66
- break;
67
- case 'w': /* advsimd registers */
68
- ct->regs |= 0xffffffff00000000ull;
69
- break;
70
- case 'l': /* qemu_ld / qemu_st address, data_reg */
71
- ct->regs = 0xffffffffu;
72
+#define ALL_GENERAL_REGS 0xffffffffu
73
+#define ALL_VECTOR_REGS 0xffffffff00000000ull
74
+
75
#ifdef CONFIG_SOFTMMU
76
- /* x0 and x1 will be overwritten when reading the tlb entry,
77
- and x2, and x3 for helper args, better to avoid using them. */
78
- tcg_regset_reset_reg(ct->regs, TCG_REG_X0);
79
- tcg_regset_reset_reg(ct->regs, TCG_REG_X1);
80
- tcg_regset_reset_reg(ct->regs, TCG_REG_X2);
81
- tcg_regset_reset_reg(ct->regs, TCG_REG_X3);
82
+#define ALL_QLDST_REGS \
83
+ (ALL_GENERAL_REGS & ~((1 << TCG_REG_X0) | (1 << TCG_REG_X1) | \
84
+ (1 << TCG_REG_X2) | (1 << TCG_REG_X3)))
85
+#else
86
+#define ALL_QLDST_REGS ALL_GENERAL_REGS
87
#endif
88
- break;
89
- case 'A': /* Valid for arithmetic immediate (positive or negative). */
90
- ct->ct |= TCG_CT_CONST_AIMM;
91
- break;
92
- case 'L': /* Valid for logical immediate. */
93
- ct->ct |= TCG_CT_CONST_LIMM;
94
- break;
95
- case 'M': /* minus one */
96
- ct->ct |= TCG_CT_CONST_MONE;
97
- break;
98
- case 'O': /* vector orr/bic immediate */
99
- ct->ct |= TCG_CT_CONST_ORRI;
100
- break;
101
- case 'N': /* vector orr/bic immediate, inverted */
102
- ct->ct |= TCG_CT_CONST_ANDI;
103
- break;
104
- case 'Z': /* zero */
105
- ct->ct |= TCG_CT_CONST_ZERO;
106
- break;
107
- default:
108
- return NULL;
109
- }
110
- return ct_str;
111
-}
112
113
/* Match a constant valid for addition (12-bit, optionally shifted). */
114
static inline bool is_aimm(uint64_t val)
115
--
41
--
116
2.25.1
42
2.43.0
117
118
diff view generated by jsdifflib
[PULL 01/24] tcg/tci: Drop L and S constraints
[PULL 23/24] target/sparc: Fix gdbstub incorrectly handling registers f32-f62
1
These are identical to the 'r' constraint.
1
From: Mikael Szreder <git@miszr.win>
2
2
3
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
3
The gdbstub implementation for the Sparc architecture would
4
incorrectly calculate the the floating point register offset.
5
This resulted in, for example, registers f32 and f34 to point to
6
the same value.
7
8
The issue was caused by the confusion between even register numbers
9
and even register indexes. For example, the register index of f32 is 64
10
and f34 is 65.
11
12
Fixes: 30038fd81808 ("target-sparc: Change fpr representation to doubles.")
13
Signed-off-by: Mikael Szreder <git@miszr.win>
14
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
15
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
16
Message-ID: <20250214070343.11501-1-git@miszr.win>
5
---
17
---
6
tcg/tci/tcg-target.c.inc | 10 ++++------
18
target/sparc/gdbstub.c | 18 ++++++++++++++----
7
1 file changed, 4 insertions(+), 6 deletions(-)
19
1 file changed, 14 insertions(+), 4 deletions(-)
8
20
9
diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
21
diff --git a/target/sparc/gdbstub.c b/target/sparc/gdbstub.c
10
index XXXXXXX..XXXXXXX 100644
22
index XXXXXXX..XXXXXXX 100644
11
--- a/tcg/tci/tcg-target.c.inc
23
--- a/target/sparc/gdbstub.c
12
+++ b/tcg/tci/tcg-target.c.inc
24
+++ b/target/sparc/gdbstub.c
13
@@ -XXX,XX +XXX,XX @@
25
@@ -XXX,XX +XXX,XX @@ int sparc_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
14
# define R64 "r"
26
}
15
#endif
27
}
16
#if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
28
if (n < 80) {
17
-# define L "L", "L"
29
- /* f32-f62 (double width, even numbers only) */
18
-# define S "S", "S"
30
- return gdb_get_reg64(mem_buf, env->fpr[(n - 32) / 2].ll);
19
+# define L "r", "r"
31
+ /* f32-f62 (16 double width registers, even register numbers only)
20
+# define S "r", "r"
32
+ * n == 64: f32 : env->fpr[16]
21
#else
33
+ * n == 65: f34 : env->fpr[17]
22
-# define L "L"
34
+ * etc...
23
-# define S "S"
35
+ * n == 79: f62 : env->fpr[31]
24
+# define L "r"
36
+ */
25
+# define S "r"
37
+ return gdb_get_reg64(mem_buf, env->fpr[(n - 64) + 16].ll);
26
#endif
38
}
27
39
switch (n) {
28
/* TODO: documentation. */
40
case 80:
29
@@ -XXX,XX +XXX,XX @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
41
@@ -XXX,XX +XXX,XX @@ int sparc_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
30
{
42
}
31
switch (*ct_str++) {
43
return 4;
32
case 'r':
44
} else if (n < 80) {
33
- case 'L': /* qemu_ld constraint */
45
- /* f32-f62 (double width, even numbers only) */
34
- case 'S': /* qemu_st constraint */
46
- env->fpr[(n - 32) / 2].ll = tmp;
35
ct->regs = BIT(TCG_TARGET_NB_REGS) - 1;
47
+ /* f32-f62 (16 double width registers, even register numbers only)
36
break;
48
+ * n == 64: f32 : env->fpr[16]
37
default:
49
+ * n == 65: f34 : env->fpr[17]
50
+ * etc...
51
+ * n == 79: f62 : env->fpr[31]
52
+ */
53
+ env->fpr[(n - 64) + 16].ll = tmp;
54
} else {
55
switch (n) {
56
case 80:
38
--
57
--
39
2.25.1
58
2.43.0
40
41
diff view generated by jsdifflib
[PULL 11/24] tcg/riscv: Split out target constraints to tcg-target-con-str.h
[PULL 24/24] target/sparc: fake UltraSPARC T1 PCR and PIC registers
1
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
1
From: Artyom Tarasenko <atar4qemu@gmail.com>
2
3
Fake access to
4
PCR Performance Control Register
5
and
6
PIC Performance Instrumentation Counter.
7
8
Ignore writes in privileged mode, and return 0 on reads.
9
10
This allows booting Tribblix, MilaX and v9os under Niagara target.
11
12
Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
13
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
14
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
15
Message-ID: <20250209211248.50383-1-atar4qemu@gmail.com>
3
---
16
---
4
tcg/riscv/tcg-target-con-str.h | 21 ++++++++++++++
17
target/sparc/translate.c | 19 +++++++++++++++++++
5
tcg/riscv/tcg-target.h | 1 +
18
target/sparc/insns.decode | 7 ++++++-
6
tcg/riscv/tcg-target.c.inc | 52 +++++++++-------------------------
19
2 files changed, 25 insertions(+), 1 deletion(-)
7
3 files changed, 35 insertions(+), 39 deletions(-)
8
create mode 100644 tcg/riscv/tcg-target-con-str.h
9
20
10
diff --git a/tcg/riscv/tcg-target-con-str.h b/tcg/riscv/tcg-target-con-str.h
21
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
11
new file mode 100644
22
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX
23
--- a/target/sparc/translate.c
13
--- /dev/null
24
+++ b/target/sparc/translate.c
14
+++ b/tcg/riscv/tcg-target-con-str.h
25
@@ -XXX,XX +XXX,XX @@ static TCGv do_rd_leon3_config(DisasContext *dc, TCGv dst)
15
@@ -XXX,XX +XXX,XX @@
26
16
+/* SPDX-License-Identifier: MIT */
27
TRANS(RDASR17, ASR17, do_rd_special, true, a->rd, do_rd_leon3_config)
17
+/*
28
18
+ * Define RISC-V target-specific operand constraints.
29
+static TCGv do_rdpic(DisasContext *dc, TCGv dst)
19
+ * Copyright (c) 2021 Linaro
30
+{
20
+ */
31
+ return tcg_constant_tl(0);
32
+}
21
+
33
+
22
+/*
34
+TRANS(RDPIC, HYPV, do_rd_special, supervisor(dc), a->rd, do_rdpic)
23
+ * Define constraint letters for register sets:
24
+ * REGS(letter, register_mask)
25
+ */
26
+REGS('r', ALL_GENERAL_REGS)
27
+REGS('L', ALL_GENERAL_REGS & ~SOFTMMU_RESERVE_REGS)
28
+
29
+/*
30
+ * Define constraint letters for constants:
31
+ * CONST(letter, TCG_CT_CONST_* bit set)
32
+ */
33
+CONST('I', TCG_CT_CONST_S12)
34
+CONST('N', TCG_CT_CONST_N12)
35
+CONST('M', TCG_CT_CONST_M12)
36
+CONST('Z', TCG_CT_CONST_ZERO)
37
diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h
38
index XXXXXXX..XXXXXXX 100644
39
--- a/tcg/riscv/tcg-target.h
40
+++ b/tcg/riscv/tcg-target.h
41
@@ -XXX,XX +XXX,XX @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t);
42
#define TCG_TARGET_NEED_POOL_LABELS
43
44
#define TCG_TARGET_HAS_MEMORY_BSWAP 0
45
+#define TCG_TARGET_CON_STR_H
46
47
#endif
48
diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
49
index XXXXXXX..XXXXXXX 100644
50
--- a/tcg/riscv/tcg-target.c.inc
51
+++ b/tcg/riscv/tcg-target.c.inc
52
@@ -XXX,XX +XXX,XX @@ static const int tcg_target_call_oarg_regs[] = {
53
#define TCG_CT_CONST_N12 0x400
54
#define TCG_CT_CONST_M12 0x800
55
56
+#define ALL_GENERAL_REGS MAKE_64BIT_MASK(0, 32)
57
+/*
58
+ * For softmmu, we need to avoid conflicts with the first 5
59
+ * argument registers to call the helper. Some of these are
60
+ * also used for the tlb lookup.
61
+ */
62
+#ifdef CONFIG_SOFTMMU
63
+#define SOFTMMU_RESERVE_REGS MAKE_64BIT_MASK(TCG_REG_A0, 5)
64
+#else
65
+#define SOFTMMU_RESERVE_REGS 0
66
+#endif
67
+
35
+
68
+
36
+
69
static inline tcg_target_long sextreg(tcg_target_long val, int pos, int len)
37
static TCGv do_rdccr(DisasContext *dc, TCGv dst)
70
{
38
{
71
if (TCG_TARGET_REG_BITS == 32) {
39
gen_helper_rdccr(dst, tcg_env);
72
@@ -XXX,XX +XXX,XX @@ static inline tcg_target_long sextreg(tcg_target_long val, int pos, int len)
40
@@ -XXX,XX +XXX,XX @@ static void do_wrfprs(DisasContext *dc, TCGv src)
73
}
41
74
}
42
TRANS(WRFPRS, 64, do_wr_special, a, true, do_wrfprs)
75
43
76
-/* parse target specific constraints */
44
+static bool do_priv_nop(DisasContext *dc, bool priv)
77
-static const char *target_parse_constraint(TCGArgConstraint *ct,
45
+{
78
- const char *ct_str, TCGType type)
46
+ if (!priv) {
79
-{
47
+ return raise_priv(dc);
80
- switch (*ct_str++) {
48
+ }
81
- case 'r':
49
+ return advance_pc(dc);
82
- ct->regs = 0xffffffff;
50
+}
83
- break;
51
+
84
- case 'L':
52
+TRANS(WRPCR, HYPV, do_priv_nop, supervisor(dc))
85
- /* qemu_ld/qemu_st constraint */
53
+TRANS(WRPIC, HYPV, do_priv_nop, supervisor(dc))
86
- ct->regs = 0xffffffff;
54
+
87
- /* qemu_ld/qemu_st uses TCG_REG_TMP0 */
55
static void do_wrgsr(DisasContext *dc, TCGv src)
88
-#if defined(CONFIG_SOFTMMU)
56
{
89
- tcg_regset_reset_reg(ct->regs, tcg_target_call_iarg_regs[0]);
57
gen_trap_ifnofpu(dc);
90
- tcg_regset_reset_reg(ct->regs, tcg_target_call_iarg_regs[1]);
58
diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode
91
- tcg_regset_reset_reg(ct->regs, tcg_target_call_iarg_regs[2]);
59
index XXXXXXX..XXXXXXX 100644
92
- tcg_regset_reset_reg(ct->regs, tcg_target_call_iarg_regs[3]);
60
--- a/target/sparc/insns.decode
93
- tcg_regset_reset_reg(ct->regs, tcg_target_call_iarg_regs[4]);
61
+++ b/target/sparc/insns.decode
94
-#endif
62
@@ -XXX,XX +XXX,XX @@ CALL 01 i:s30
95
- break;
63
RDTICK 10 rd:5 101000 00100 0 0000000000000
96
- case 'I':
64
RDPC 10 rd:5 101000 00101 0 0000000000000
97
- ct->ct |= TCG_CT_CONST_S12;
65
RDFPRS 10 rd:5 101000 00110 0 0000000000000
98
- break;
66
- RDASR17 10 rd:5 101000 10001 0 0000000000000
99
- case 'N':
67
+ {
100
- ct->ct |= TCG_CT_CONST_N12;
68
+ RDASR17 10 rd:5 101000 10001 0 0000000000000
101
- break;
69
+ RDPIC 10 rd:5 101000 10001 0 0000000000000
102
- case 'M':
70
+ }
103
- ct->ct |= TCG_CT_CONST_M12;
71
RDGSR 10 rd:5 101000 10011 0 0000000000000
104
- break;
72
RDSOFTINT 10 rd:5 101000 10110 0 0000000000000
105
- case 'Z':
73
RDTICK_CMPR 10 rd:5 101000 10111 0 0000000000000
106
- /* we can use a zero immediate as a zero register argument. */
74
@@ -XXX,XX +XXX,XX @@ CALL 01 i:s30
107
- ct->ct |= TCG_CT_CONST_ZERO;
75
WRCCR 10 00010 110000 ..... . ............. @n_r_ri
108
- break;
76
WRASI 10 00011 110000 ..... . ............. @n_r_ri
109
- default:
77
WRFPRS 10 00110 110000 ..... . ............. @n_r_ri
110
- return NULL;
78
+ WRPCR 10 10000 110000 01000 0 0000000000000
111
- }
79
+ WRPIC 10 10001 110000 01000 0 0000000000000
112
- return ct_str;
80
{
113
-}
81
WRGSR 10 10011 110000 ..... . ............. @n_r_ri
114
-
82
WRPOWERDOWN 10 10011 110000 ..... . ............. @n_r_ri
115
/* test if a constant matches the constraint */
116
static int tcg_target_const_match(tcg_target_long val, TCGType type,
117
const TCGArgConstraint *arg_ct)
118
--
83
--
119
2.25.1
84
2.43.0
120
121
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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