Series comparison

-[PULL 00/24] tcg patch queue
+[PULL v3 00/44] tcg patch queue
-The following changes since commit 77f3804ab7ed94b471a14acb260e5aeacf26193f:
+Version 3: Rebase and fix a minor patch conflict.
-  Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into staging (2021-02-02 16:47:51 +0000)
 r~
 The following changes since commit c6f5e042d89e79206cd1ce5525d3df219f13c3cc:
   Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20210913-3' into staging (2021-09-13 21:06:15 +0100)
 are available in the Git repository at:
-  https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20210202
+  https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20210914
-for you to fetch changes up to 0c823e596877a30fd6c17a1ae9f98218a53055ea:
+for you to fetch changes up to a5b759b6dca7daf87fa5007a7f5784bf22f3830f:
-  tcg: Remove TCG_TARGET_CON_SET_H (2021-02-02 12:12:43 -1000)
+  tcg/arm: More use of the TCGReg enum (2021-09-14 07:59:43 -0700)
 ----------------------------------------------------------------
-TCG backend constraints cleanup
+Fix translation race condition for user-only.
 Fix tcg/i386 encoding for VPSLLVQ, VPSRLVQ.
 Fix tcg/arm tcg_out_vec_op signature.
 Fix tcg/ppc (32bit) build with clang.
 Remove dupluate TCG_KICK_PERIOD definition.
 Remove unused tcg_global_reg_new.
 Restrict cpu_exec_interrupt and its callees to sysemu.
 Cleanups for tcg/arm.
 ----------------------------------------------------------------
-Richard Henderson (24):
+Bin Meng (1):
-      tcg/tci: Drop L and S constraints
+      tcg: Remove tcg_global_reg_new defines
       tcg/tci: Remove TCG_TARGET_HAS_* ifdefs
       tcg/i386: Move constraint type check to tcg_target_const_match
       tcg/i386: Tidy register constraint definitions
       tcg/i386: Split out target constraints to tcg-target-con-str.h
       tcg/arm: Split out target constraints to tcg-target-con-str.h
       tcg/aarch64: Split out target constraints to tcg-target-con-str.h
       tcg/ppc: Split out target constraints to tcg-target-con-str.h
       tcg/tci: Split out target constraints to tcg-target-con-str.h
       tcg/mips: Split out target constraints to tcg-target-con-str.h
       tcg/riscv: Split out target constraints to tcg-target-con-str.h
       tcg/s390: Split out target constraints to tcg-target-con-str.h
       tcg/sparc: Split out target constraints to tcg-target-con-str.h
       tcg: Remove TCG_TARGET_CON_STR_H
       tcg/i386: Split out constraint sets to tcg-target-con-set.h
       tcg/aarch64: Split out constraint sets to tcg-target-con-set.h
       tcg/arm: Split out constraint sets to tcg-target-con-set.h
       tcg/mips: Split out constraint sets to tcg-target-con-set.h
       tcg/ppc: Split out constraint sets to tcg-target-con-set.h
       tcg/riscv: Split out constraint sets to tcg-target-con-set.h
       tcg/s390: Split out constraint sets to tcg-target-con-set.h
       tcg/sparc: Split out constraint sets to tcg-target-con-set.h
       tcg/tci: Split out constraint sets to tcg-target-con-set.h
       tcg: Remove TCG_TARGET_CON_SET_H
- tcg/aarch64/tcg-target-con-set.h |  36 ++++
+Ilya Leoshkevich (3):
- tcg/aarch64/tcg-target-con-str.h |  24 +++
+      accel/tcg: Add DisasContextBase argument to translator_ld*
- tcg/arm/tcg-target-con-set.h     |  35 ++++
+      accel/tcg: Clear PAGE_WRITE before translation
- tcg/arm/tcg-target-con-str.h     |  22 +++
+      accel/tcg/user-exec: Fix read-modify-write of code on s390 hosts
  tcg/i386/tcg-target-con-set.h    |  55 ++++++
  tcg/i386/tcg-target-con-str.h    |  33 ++++
  tcg/mips/tcg-target-con-set.h    |  36 ++++
  tcg/mips/tcg-target-con-str.h    |  24 +++
  tcg/ppc/tcg-target-con-set.h     |  42 +++++
  tcg/ppc/tcg-target-con-str.h     |  30 ++++
  tcg/riscv/tcg-target-con-set.h   |  30 ++++
  tcg/riscv/tcg-target-con-str.h   |  21 +++
  tcg/s390/tcg-target-con-set.h    |  29 ++++
  tcg/s390/tcg-target-con-str.h    |  28 +++
  tcg/sparc/tcg-target-con-set.h   |  32 ++++
  tcg/sparc/tcg-target-con-str.h   |  23 +++
  tcg/sparc/tcg-target.h           |   4 -
  tcg/tci/tcg-target-con-set.h     |  25 +++
  tcg/tci/tcg-target-con-str.h     |  11 ++
  tcg/tcg.c                        | 136 +++++++++++++--
  tcg/aarch64/tcg-target.c.inc     | 137 ++++-----------
  tcg/arm/tcg-target.c.inc         | 168 ++++++------------
  tcg/i386/tcg-target.c.inc        | 317 +++++++++++-----------------------
  tcg/mips/tcg-target.c.inc        | 173 ++++++-------------
  tcg/ppc/tcg-target.c.inc         | 209 ++++++++---------------
  tcg/riscv/tcg-target.c.inc       | 135 ++++-----------
  tcg/s390/tcg-target.c.inc        | 174 +++++++------------
  tcg/sparc/tcg-target.c.inc       | 156 ++++++-----------
  tcg/tci/tcg-target.c.inc         | 359 ++++++++++++++-------------------------
 files changed, 1244 insertions(+), 1260 deletions(-)
  create mode 100644 tcg/aarch64/tcg-target-con-set.h
  create mode 100644 tcg/aarch64/tcg-target-con-str.h
  create mode 100644 tcg/arm/tcg-target-con-set.h
  create mode 100644 tcg/arm/tcg-target-con-str.h
  create mode 100644 tcg/i386/tcg-target-con-set.h
  create mode 100644 tcg/i386/tcg-target-con-str.h
  create mode 100644 tcg/mips/tcg-target-con-set.h
  create mode 100644 tcg/mips/tcg-target-con-str.h
  create mode 100644 tcg/ppc/tcg-target-con-set.h
  create mode 100644 tcg/ppc/tcg-target-con-str.h
  create mode 100644 tcg/riscv/tcg-target-con-set.h
  create mode 100644 tcg/riscv/tcg-target-con-str.h
  create mode 100644 tcg/s390/tcg-target-con-set.h
  create mode 100644 tcg/s390/tcg-target-con-str.h
  create mode 100644 tcg/sparc/tcg-target-con-set.h
  create mode 100644 tcg/sparc/tcg-target-con-str.h
  create mode 100644 tcg/tci/tcg-target-con-set.h
  create mode 100644 tcg/tci/tcg-target-con-str.h
+Jose R. Ziviani (1):
+      tcg/arm: Fix tcg_out_vec_op function signature
+Luc Michel (1):
+      accel/tcg: remove redundant TCG_KICK_PERIOD define
+Philippe Mathieu-Daudé (25):
+      target/avr: Remove pointless use of CONFIG_USER_ONLY definition
+      target/i386: Restrict sysemu-only fpu_helper helpers
+      target/i386: Simplify TARGET_X86_64 #ifdef'ry
+      target/xtensa: Restrict do_transaction_failed() to sysemu
+      accel/tcg: Rename user-mode do_interrupt hack as fake_user_interrupt
+      target/alpha: Restrict cpu_exec_interrupt() handler to sysemu
+      target/arm: Restrict cpu_exec_interrupt() handler to sysemu
+      target/cris: Restrict cpu_exec_interrupt() handler to sysemu
+      target/hppa: Restrict cpu_exec_interrupt() handler to sysemu
+      target/i386: Restrict cpu_exec_interrupt() handler to sysemu
+      target/i386: Move x86_cpu_exec_interrupt() under sysemu/ folder
+      target/m68k: Restrict cpu_exec_interrupt() handler to sysemu
+      target/microblaze: Restrict cpu_exec_interrupt() handler to sysemu
+      target/mips: Restrict cpu_exec_interrupt() handler to sysemu
+      target/nios2: Restrict cpu_exec_interrupt() handler to sysemu
+      target/openrisc: Restrict cpu_exec_interrupt() handler to sysemu
+      target/ppc: Restrict cpu_exec_interrupt() handler to sysemu
+      target/riscv: Restrict cpu_exec_interrupt() handler to sysemu
+      target/sh4: Restrict cpu_exec_interrupt() handler to sysemu
+      target/sparc: Restrict cpu_exec_interrupt() handler to sysemu
+      target/rx: Restrict cpu_exec_interrupt() handler to sysemu
+      target/xtensa: Restrict cpu_exec_interrupt() handler to sysemu
+      accel/tcg: Restrict TCGCPUOps::cpu_exec_interrupt() to sysemu
+      user: Remove cpu_get_pic_interrupt() stubs
+      user: Mark cpu_loop() with noreturn attribute
+Richard Henderson (13):
+      tcg/i386: Split P_VEXW from P_REXW
+      tcg/ppc: Replace TCG_TARGET_CALL_DARWIN with _CALL_DARWIN
+      tcg/ppc: Ensure _CALL_SYSV is set for 32-bit ELF
+      tcg/arm: Remove fallback definition of __ARM_ARCH
+      tcg/arm: Standardize on tcg_out_<branch>_{reg,imm}
+      tcg/arm: Simplify use_armv5t_instructions
+      tcg/arm: Support armv4t in tcg_out_goto and tcg_out_call
+      tcg/arm: Split out tcg_out_ldstm
+      tcg/arm: Simplify usage of encode_imm
+      tcg/arm: Drop inline markers
+      tcg/arm: Give enum arm_cond_code_e a typedef and use it
+      tcg/arm: More use of the ARMInsn enum
+      tcg/arm: More use of the TCGReg enum
+ bsd-user/qemu.h                           |   2 +-
+ include/exec/translate-all.h              |   1 +
+ include/exec/translator.h                 |  44 +--
+ include/hw/core/tcg-cpu-ops.h             |  26 +-
+ include/tcg/tcg-op.h                      |   2 -
+ linux-user/qemu.h                         |   2 +-
+ target/alpha/cpu.h                        |   2 +-
+ target/arm/arm_ldst.h                     |  12 +-
+ target/arm/cpu.h                          |   3 +-
+ target/cris/cpu.h                         |   2 +-
+ target/hppa/cpu.h                         |   4 +-
+ target/i386/cpu.h                         |   3 +
+ target/i386/tcg/helper-tcg.h              |   2 +
+ target/m68k/cpu.h                         |   2 +
+ target/microblaze/cpu.h                   |   2 +
+ target/mips/tcg/tcg-internal.h            |   5 +-
+ target/openrisc/cpu.h                     |   5 +-
+ target/ppc/cpu.h                          |   4 +-
+ target/riscv/cpu.h                        |   2 +-
+ target/rx/cpu.h                           |   2 +
+ target/sh4/cpu.h                          |   4 +-
+ target/xtensa/cpu.h                       |   2 +
+ tcg/arm/tcg-target.h                      |  27 +-
+ accel/tcg/cpu-exec.c                      |  14 +-
+ accel/tcg/tcg-accel-ops-rr.c              |   2 -
+ accel/tcg/translate-all.c                 |  59 ++--
+ accel/tcg/translator.c                    |  39 +++
+ accel/tcg/user-exec.c                     |  48 ++-
+ bsd-user/i386/target_arch_cpu.c           |   5 -
+ bsd-user/x86_64/target_arch_cpu.c         |   5 -
+ linux-user/main.c                         |   7 -
+ target/alpha/cpu.c                        |   2 +-
+ target/alpha/helper.c                     |   5 +-
+ target/alpha/translate.c                  |   2 +-
+ target/arm/cpu.c                          |   7 +-
+ target/arm/cpu_tcg.c                      |   6 +-
+ target/arm/translate-a64.c                |   2 +-
+ target/arm/translate.c                    |   9 +-
+ target/avr/cpu.c                          |   3 -
+ target/cris/cpu.c                         |   4 +-
+ target/cris/helper.c                      |  17 +-
+ target/hexagon/translate.c                |   3 +-
+ target/hppa/cpu.c                         |   2 +-
+ target/hppa/int_helper.c                  |   7 +-
+ target/hppa/translate.c                   |   5 +-
+ target/i386/tcg/seg_helper.c              |  74 +----
+ target/i386/tcg/sysemu/seg_helper.c       |  62 ++++
+ target/i386/tcg/tcg-cpu.c                 |   8 +-
+ target/i386/tcg/translate.c               |  10 +-
+ target/m68k/cpu.c                         |   2 +-
+ target/m68k/op_helper.c                   |  16 +-
+ target/m68k/translate.c                   |   2 +-
+ target/microblaze/cpu.c                   |   2 +-
+ target/microblaze/helper.c                |  13 +-
+ target/mips/cpu.c                         |   2 +-
+ target/mips/tcg/exception.c               |  18 --
+ target/mips/tcg/sysemu/tlb_helper.c       |  18 ++
+ target/mips/tcg/translate.c               |   8 +-
+ target/mips/tcg/user/tlb_helper.c         |   5 -
+ target/nios2/cpu.c                        |   5 +-
+ target/openrisc/cpu.c                     |   2 +-
+ target/openrisc/interrupt.c               |   2 -
+ target/openrisc/translate.c               |   2 +-
+ target/ppc/cpu_init.c                     |   2 +-
+ target/ppc/excp_helper.c                  |  21 +-
+ target/ppc/translate.c                    |   5 +-
+ target/riscv/cpu.c                        |   2 +-
+ target/riscv/cpu_helper.c                 |   5 -
+ target/riscv/translate.c                  |   5 +-
+ target/rx/cpu.c                           |   2 +-
+ target/rx/helper.c                        |   4 +
+ target/s390x/tcg/translate.c              |  16 +-
+ target/sh4/cpu.c                          |   2 +-
+ target/sh4/helper.c                       |   9 +-
+ target/sh4/translate.c                    |   4 +-
+ target/sparc/cpu.c                        |   4 +-
+ target/sparc/translate.c                  |   2 +-
+ target/xtensa/cpu.c                       |   2 +-
+ target/xtensa/exc_helper.c                |   7 +-
+ target/xtensa/translate.c                 |   5 +-
+ target/mips/tcg/micromips_translate.c.inc |   2 +-
+ target/mips/tcg/mips16e_translate.c.inc   |   4 +-
+ target/mips/tcg/nanomips_translate.c.inc  |   4 +-
+ tcg/arm/tcg-target.c.inc                  | 517 ++++++++++++++++--------------
+ tcg/i386/tcg-target.c.inc                 |  13 +-
+ tcg/ppc/tcg-target.c.inc                  |  25 +-
+ target/openrisc/meson.build               |   6 +-
+files changed, 702 insertions(+), 630 deletions(-)

-[PULL 01/24] tcg/tci: Drop L and S constraints
+Deleted patch
-These are identical to the 'r' constraint.
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
----
- tcg/tci/tcg-target.c.inc | 10 ++++------
-file changed, 4 insertions(+), 6 deletions(-)
-diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
-index XXXXXXX..XXXXXXX 100644
---- a/tcg/tci/tcg-target.c.inc
-+++ b/tcg/tci/tcg-target.c.inc
-@@ -XXX,XX +XXX,XX @@
- # define R64    "r"
- #endif
- #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
--# define L      "L", "L"
--# define S      "S", "S"
-+# define L      "r", "r"
-+# define S      "r", "r"
- #else
--# define L      "L"
--# define S      "S"
-+# define L      "r"
-+# define S      "r"
- #endif
- /* TODO: documentation. */
-@@ -XXX,XX +XXX,XX @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
- {
-     switch (*ct_str++) {
-     case 'r':
--    case 'L':                   /* qemu_ld constraint */
--    case 'S':                   /* qemu_st constraint */
-         ct->regs = BIT(TCG_TARGET_NB_REGS) - 1;
-         break;
-     default:
---
-.25.1

-[PULL 02/24] tcg/tci: Remove TCG_TARGET_HAS_* ifdefs
+Deleted patch
-The opcodes always exist, regardless of whether or not they
-are enabled.  Remove the unnecessary ifdefs.
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
----
- tcg/tci/tcg-target.c.inc | 82 ----------------------------------------
-file changed, 82 deletions(-)
-diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
-index XXXXXXX..XXXXXXX 100644
---- a/tcg/tci/tcg-target.c.inc
-+++ b/tcg/tci/tcg-target.c.inc
-@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef tcg_target_op_defs[] = {
-     { INDEX_op_add_i32, { R, RI, RI } },
-     { INDEX_op_sub_i32, { R, RI, RI } },
-     { INDEX_op_mul_i32, { R, RI, RI } },
--#if TCG_TARGET_HAS_div_i32
-     { INDEX_op_div_i32, { R, R, R } },
-     { INDEX_op_divu_i32, { R, R, R } },
-     { INDEX_op_rem_i32, { R, R, R } },
-     { INDEX_op_remu_i32, { R, R, R } },
--#elif TCG_TARGET_HAS_div2_i32
--    { INDEX_op_div2_i32, { R, R, "0", "1", R } },
--    { INDEX_op_divu2_i32, { R, R, "0", "1", R } },
--#endif
-     /* TODO: Does R, RI, RI result in faster code than R, R, RI?
-        If both operands are constants, we can optimize. */
-     { INDEX_op_and_i32, { R, RI, RI } },
--#if TCG_TARGET_HAS_andc_i32
-     { INDEX_op_andc_i32, { R, RI, RI } },
--#endif
--#if TCG_TARGET_HAS_eqv_i32
-     { INDEX_op_eqv_i32, { R, RI, RI } },
--#endif
--#if TCG_TARGET_HAS_nand_i32
-     { INDEX_op_nand_i32, { R, RI, RI } },
--#endif
--#if TCG_TARGET_HAS_nor_i32
-     { INDEX_op_nor_i32, { R, RI, RI } },
--#endif
-     { INDEX_op_or_i32, { R, RI, RI } },
--#if TCG_TARGET_HAS_orc_i32
-     { INDEX_op_orc_i32, { R, RI, RI } },
--#endif
-     { INDEX_op_xor_i32, { R, RI, RI } },
-     { INDEX_op_shl_i32, { R, RI, RI } },
-     { INDEX_op_shr_i32, { R, RI, RI } },
-     { INDEX_op_sar_i32, { R, RI, RI } },
--#if TCG_TARGET_HAS_rot_i32
-     { INDEX_op_rotl_i32, { R, RI, RI } },
-     { INDEX_op_rotr_i32, { R, RI, RI } },
--#endif
--#if TCG_TARGET_HAS_deposit_i32
-     { INDEX_op_deposit_i32, { R, "0", R } },
--#endif
-     { INDEX_op_brcond_i32, { R, RI } },
-     { INDEX_op_setcond_i32, { R, R, RI } },
--#if TCG_TARGET_REG_BITS == 64
-     { INDEX_op_setcond_i64, { R, R, RI } },
--#endif /* TCG_TARGET_REG_BITS == 64 */
--#if TCG_TARGET_REG_BITS == 32
-     /* TODO: Support R, R, R, R, RI, RI? Will it be faster? */
-     { INDEX_op_add2_i32, { R, R, R, R, R, R } },
-     { INDEX_op_sub2_i32, { R, R, R, R, R, R } },
-     { INDEX_op_brcond2_i32, { R, R, RI, RI } },
-     { INDEX_op_mulu2_i32, { R, R, R, R } },
-     { INDEX_op_setcond2_i32, { R, R, R, RI, RI } },
--#endif
--#if TCG_TARGET_HAS_not_i32
-     { INDEX_op_not_i32, { R, R } },
--#endif
--#if TCG_TARGET_HAS_neg_i32
-     { INDEX_op_neg_i32, { R, R } },
--#endif
--#if TCG_TARGET_REG_BITS == 64
-     { INDEX_op_ld8u_i64, { R, R } },
-     { INDEX_op_ld8s_i64, { R, R } },
-     { INDEX_op_ld16u_i64, { R, R } },
-@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef tcg_target_op_defs[] = {
-     { INDEX_op_add_i64, { R, RI, RI } },
-     { INDEX_op_sub_i64, { R, RI, RI } },
-     { INDEX_op_mul_i64, { R, RI, RI } },
--#if TCG_TARGET_HAS_div_i64
-     { INDEX_op_div_i64, { R, R, R } },
-     { INDEX_op_divu_i64, { R, R, R } },
-     { INDEX_op_rem_i64, { R, R, R } },
-     { INDEX_op_remu_i64, { R, R, R } },
--#elif TCG_TARGET_HAS_div2_i64
--    { INDEX_op_div2_i64, { R, R, "0", "1", R } },
--    { INDEX_op_divu2_i64, { R, R, "0", "1", R } },
--#endif
-     { INDEX_op_and_i64, { R, RI, RI } },
--#if TCG_TARGET_HAS_andc_i64
-     { INDEX_op_andc_i64, { R, RI, RI } },
--#endif
--#if TCG_TARGET_HAS_eqv_i64
-     { INDEX_op_eqv_i64, { R, RI, RI } },
--#endif
--#if TCG_TARGET_HAS_nand_i64
-     { INDEX_op_nand_i64, { R, RI, RI } },
--#endif
--#if TCG_TARGET_HAS_nor_i64
-     { INDEX_op_nor_i64, { R, RI, RI } },
--#endif
-     { INDEX_op_or_i64, { R, RI, RI } },
--#if TCG_TARGET_HAS_orc_i64
-     { INDEX_op_orc_i64, { R, RI, RI } },
--#endif
-     { INDEX_op_xor_i64, { R, RI, RI } },
-     { INDEX_op_shl_i64, { R, RI, RI } },
-     { INDEX_op_shr_i64, { R, RI, RI } },
-     { INDEX_op_sar_i64, { R, RI, RI } },
--#if TCG_TARGET_HAS_rot_i64
-     { INDEX_op_rotl_i64, { R, RI, RI } },
-     { INDEX_op_rotr_i64, { R, RI, RI } },
--#endif
--#if TCG_TARGET_HAS_deposit_i64
-     { INDEX_op_deposit_i64, { R, "0", R } },
--#endif
-     { INDEX_op_brcond_i64, { R, RI } },
--#if TCG_TARGET_HAS_ext8s_i64
-     { INDEX_op_ext8s_i64, { R, R } },
--#endif
--#if TCG_TARGET_HAS_ext16s_i64
-     { INDEX_op_ext16s_i64, { R, R } },
--#endif
--#if TCG_TARGET_HAS_ext32s_i64
-     { INDEX_op_ext32s_i64, { R, R } },
--#endif
--#if TCG_TARGET_HAS_ext8u_i64
-     { INDEX_op_ext8u_i64, { R, R } },
--#endif
--#if TCG_TARGET_HAS_ext16u_i64
-     { INDEX_op_ext16u_i64, { R, R } },
--#endif
--#if TCG_TARGET_HAS_ext32u_i64
-     { INDEX_op_ext32u_i64, { R, R } },
--#endif
-     { INDEX_op_ext_i32_i64, { R, R } },
-     { INDEX_op_extu_i32_i64, { R, R } },
--#if TCG_TARGET_HAS_bswap16_i64
-     { INDEX_op_bswap16_i64, { R, R } },
--#endif
--#if TCG_TARGET_HAS_bswap32_i64
-     { INDEX_op_bswap32_i64, { R, R } },
--#endif
--#if TCG_TARGET_HAS_bswap64_i64
-     { INDEX_op_bswap64_i64, { R, R } },
--#endif
--#if TCG_TARGET_HAS_not_i64
-     { INDEX_op_not_i64, { R, R } },
--#endif
--#if TCG_TARGET_HAS_neg_i64
-     { INDEX_op_neg_i64, { R, R } },
--#endif
--#endif /* TCG_TARGET_REG_BITS == 64 */
-     { INDEX_op_qemu_ld_i32, { R, L } },
-     { INDEX_op_qemu_ld_i64, { R64, L } },
-@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef tcg_target_op_defs[] = {
-     { INDEX_op_qemu_st_i32, { R, S } },
-     { INDEX_op_qemu_st_i64, { R64, S } },
--#if TCG_TARGET_HAS_ext8s_i32
-     { INDEX_op_ext8s_i32, { R, R } },
--#endif
--#if TCG_TARGET_HAS_ext16s_i32
-     { INDEX_op_ext16s_i32, { R, R } },
--#endif
--#if TCG_TARGET_HAS_ext8u_i32
-     { INDEX_op_ext8u_i32, { R, R } },
--#endif
--#if TCG_TARGET_HAS_ext16u_i32
-     { INDEX_op_ext16u_i32, { R, R } },
--#endif
--#if TCG_TARGET_HAS_bswap16_i32
-     { INDEX_op_bswap16_i32, { R, R } },
--#endif
--#if TCG_TARGET_HAS_bswap32_i32
-     { INDEX_op_bswap32_i32, { R, R } },
--#endif
-     { INDEX_op_mb, { } },
-     { -1 },
---
-.25.1

-[PULL 03/24] tcg/i386: Move constraint type check to tcg_target_const_match
+Deleted patch
-Rather than check the type when filling in the constraint,
-check it when matching the constant.  This removes the only
-use of the type argument to target_parse_constraint.
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
----
- tcg/i386/tcg-target.c.inc | 28 +++++++++++++++++-----------
-file changed, 17 insertions(+), 11 deletions(-)
-diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
-index XXXXXXX..XXXXXXX 100644
---- a/tcg/i386/tcg-target.c.inc
-+++ b/tcg/i386/tcg-target.c.inc
-@@ -XXX,XX +XXX,XX @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
-         break;
-     case 'e':
--        ct->ct |= (type == TCG_TYPE_I32 ? TCG_CT_CONST : TCG_CT_CONST_S32);
-+        ct->ct |= TCG_CT_CONST_S32;
-         break;
-     case 'Z':
--        ct->ct |= (type == TCG_TYPE_I32 ? TCG_CT_CONST : TCG_CT_CONST_U32);
-+        ct->ct |= TCG_CT_CONST_U32;
-         break;
-     case 'I':
--        ct->ct |= (type == TCG_TYPE_I32 ? TCG_CT_CONST : TCG_CT_CONST_I32);
-+        ct->ct |= TCG_CT_CONST_I32;
-         break;
-     default:
-@@ -XXX,XX +XXX,XX @@ static inline int tcg_target_const_match(tcg_target_long val, TCGType type,
-     if (ct & TCG_CT_CONST) {
-         return 1;
-     }
--    if ((ct & TCG_CT_CONST_S32) && val == (int32_t)val) {
--        return 1;
--    }
--    if ((ct & TCG_CT_CONST_U32) && val == (uint32_t)val) {
--        return 1;
--    }
--    if ((ct & TCG_CT_CONST_I32) && ~val == (int32_t)~val) {
--        return 1;
-+    if (type == TCG_TYPE_I32) {
-+        if (ct & (TCG_CT_CONST_S32 | TCG_CT_CONST_U32 | TCG_CT_CONST_I32)) {
-+            return 1;
-+        }
-+    } else {
-+        if ((ct & TCG_CT_CONST_S32) && val == (int32_t)val) {
-+            return 1;
-+        }
-+        if ((ct & TCG_CT_CONST_U32) && val == (uint32_t)val) {
-+            return 1;
-+        }
-+        if ((ct & TCG_CT_CONST_I32) && ~val == (int32_t)~val) {
-+            return 1;
-+        }
-     }
-     if ((ct & TCG_CT_CONST_WSZ) && val == (type == TCG_TYPE_I32 ? 32 : 64)) {
-         return 1;
---
-.25.1

-[PULL 04/24] tcg/i386: Tidy register constraint definitions
+Deleted patch
-Create symbolic constants for all low-byte-addressable
-and second-byte-addressable registers.  Create a symbol
-for the registers that need reserving for softmmu.
-There is no functional change for 's', as this letter is
-only used for i386.  The BYTEL name is correct for the
-action we wish from the constraint.
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
----
- tcg/i386/tcg-target.c.inc | 40 +++++++++++++++++++--------------------
-file changed, 20 insertions(+), 20 deletions(-)
-diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
-index XXXXXXX..XXXXXXX 100644
---- a/tcg/i386/tcg-target.c.inc
-+++ b/tcg/i386/tcg-target.c.inc
-@@ -XXX,XX +XXX,XX @@ static const int tcg_target_call_oarg_regs[] = {
- # define TCG_REG_L1 TCG_REG_EDX
- #endif
-+#define ALL_BYTEH_REGS         0x0000000fu
-+#if TCG_TARGET_REG_BITS == 64
-+# define ALL_GENERAL_REGS      0x0000ffffu
-+# define ALL_VECTOR_REGS       0xffff0000u
-+# define ALL_BYTEL_REGS        ALL_GENERAL_REGS
-+#else
-+# define ALL_GENERAL_REGS      0x000000ffu
-+# define ALL_VECTOR_REGS       0x00ff0000u
-+# define ALL_BYTEL_REGS        ALL_BYTEH_REGS
-+#endif
-+#ifdef CONFIG_SOFTMMU
-+# define SOFTMMU_RESERVE_REGS  ((1 << TCG_REG_L0) | (1 << TCG_REG_L1))
-+#else
-+# define SOFTMMU_RESERVE_REGS  0
-+#endif
-+
- /* The host compiler should supply <cpuid.h> to enable runtime features
-    detection, as we're not going to go so far as our own inline assembly.
-    If not available, default values will be assumed.  */
-@@ -XXX,XX +XXX,XX @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
-     return true;
- }
--#if TCG_TARGET_REG_BITS == 64
--#define ALL_GENERAL_REGS   0x0000ffffu
--#define ALL_VECTOR_REGS    0xffff0000u
--#else
--#define ALL_GENERAL_REGS   0x000000ffu
--#define ALL_VECTOR_REGS    0x00ff0000u
--#endif
--
- /* parse target specific constraints */
- static const char *target_parse_constraint(TCGArgConstraint *ct,
-                                            const char *ct_str, TCGType type)
-@@ -XXX,XX +XXX,XX @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
-         break;
-     case 'q':
-         /* A register that can be used as a byte operand.  */
--        ct->regs = TCG_TARGET_REG_BITS == 64 ? 0xffff : 0xf;
-+        ct->regs |= ALL_BYTEL_REGS;
-         break;
-     case 'Q':
-         /* A register with an addressable second byte (e.g. %ah).  */
--        ct->regs = 0xf;
-+        ct->regs |= ALL_BYTEH_REGS;
-         break;
-     case 'r':
-         /* A general register.  */
-@@ -XXX,XX +XXX,XX @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
-     case 'L':
-         /* qemu_ld/st data+address constraint */
--        ct->regs = TCG_TARGET_REG_BITS == 64 ? 0xffff : 0xff;
--#ifdef CONFIG_SOFTMMU
--        tcg_regset_reset_reg(ct->regs, TCG_REG_L0);
--        tcg_regset_reset_reg(ct->regs, TCG_REG_L1);
--#endif
-+        ct->regs |= ALL_GENERAL_REGS & ~SOFTMMU_RESERVE_REGS;
-         break;
-     case 's':
-         /* qemu_st8_i32 data constraint */
--        ct->regs = 0xf;
--#ifdef CONFIG_SOFTMMU
--        tcg_regset_reset_reg(ct->regs, TCG_REG_L0);
--        tcg_regset_reset_reg(ct->regs, TCG_REG_L1);
--#endif
-+        ct->regs |= ALL_BYTEL_REGS & ~SOFTMMU_RESERVE_REGS;
-         break;
-     case 'e':
---
-.25.1

-[PULL 05/24] tcg/i386: Split out target constraints to tcg-target-con-str.h
+Deleted patch
-This eliminates the target-specific function target_parse_constraint
-and folds it into the single caller, process_op_defs.  Since this is
-done directly into the switch statement, duplicates are compilation
-errors rather than silently ignored at runtime.
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
----
- tcg/i386/tcg-target-con-str.h | 33 +++++++++++++++++
- tcg/i386/tcg-target.h         |  1 +
- tcg/tcg.c                     | 33 ++++++++++++++---
- tcg/i386/tcg-target.c.inc     | 69 -----------------------------------
-files changed, 62 insertions(+), 74 deletions(-)
- create mode 100644 tcg/i386/tcg-target-con-str.h
-diff --git a/tcg/i386/tcg-target-con-str.h b/tcg/i386/tcg-target-con-str.h
-new file mode 100644
-index XXXXXXX..XXXXXXX
---- /dev/null
-+++ b/tcg/i386/tcg-target-con-str.h
-@@ -XXX,XX +XXX,XX @@
-+/* SPDX-License-Identifier: MIT */
-+/*
-+ * Define i386 target-specific operand constraints.
-+ * Copyright (c) 2021 Linaro
-+ *
-+ */
-+
-+/*
-+ * Define constraint letters for register sets:
-+ * REGS(letter, register_mask)
-+ */
-+REGS('a', 1u << TCG_REG_EAX)
-+REGS('b', 1u << TCG_REG_EBX)
-+REGS('c', 1u << TCG_REG_ECX)
-+REGS('d', 1u << TCG_REG_EDX)
-+REGS('S', 1u << TCG_REG_ESI)
-+REGS('D', 1u << TCG_REG_EDI)
-+
-+REGS('r', ALL_GENERAL_REGS)
-+REGS('x', ALL_VECTOR_REGS)
-+REGS('q', ALL_BYTEL_REGS)     /* regs that can be used as a byte operand */
-+REGS('Q', ALL_BYTEH_REGS)     /* regs with a second byte (e.g. %ah) */
-+REGS('L', ALL_GENERAL_REGS & ~SOFTMMU_RESERVE_REGS)  /* qemu_ld/st */
-+REGS('s', ALL_BYTEL_REGS & ~SOFTMMU_RESERVE_REGS)    /* qemu_st8_i32 data */
-+
-+/*
-+ * Define constraint letters for constants:
-+ * CONST(letter, TCG_CT_CONST_* bit set)
-+ */
-+CONST('e', TCG_CT_CONST_S32)
-+CONST('I', TCG_CT_CONST_I32)
-+CONST('W', TCG_CT_CONST_WSZ)
-+CONST('Z', TCG_CT_CONST_U32)
-diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h
-index XXXXXXX..XXXXXXX 100644
---- a/tcg/i386/tcg-target.h
-+++ b/tcg/i386/tcg-target.h
-@@ -XXX,XX +XXX,XX @@ static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_rx,
- #define TCG_TARGET_NEED_LDST_LABELS
- #endif
- #define TCG_TARGET_NEED_POOL_LABELS
-+#define TCG_TARGET_CON_STR_H
- #endif
-diff --git a/tcg/tcg.c b/tcg/tcg.c
-index XXXXXXX..XXXXXXX 100644
---- a/tcg/tcg.c
-+++ b/tcg/tcg.c
-@@ -XXX,XX +XXX,XX @@ static void tcg_register_jit_int(const void *buf, size_t size,
-     __attribute__((unused));
- /* Forward declarations for functions declared and used in tcg-target.c.inc. */
-+#ifndef TCG_TARGET_CON_STR_H
- static const char *target_parse_constraint(TCGArgConstraint *ct,
-                                            const char *ct_str, TCGType type);
-+#endif
- static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg1,
-                        intptr_t arg2);
- static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg);
-@@ -XXX,XX +XXX,XX @@ static void process_op_defs(TCGContext *s)
-     for (op = 0; op < NB_OPS; op++) {
-         TCGOpDef *def = &tcg_op_defs[op];
-         const TCGTargetOpDef *tdefs;
--        TCGType type;
-         int i, nb_args;
-         if (def->flags & TCG_OPF_NOT_PRESENT) {
-@@ -XXX,XX +XXX,XX @@ static void process_op_defs(TCGContext *s)
-         /* Missing TCGTargetOpDef entry. */
-         tcg_debug_assert(tdefs != NULL);
--        type = (def->flags & TCG_OPF_64BIT ? TCG_TYPE_I64 : TCG_TYPE_I32);
-         for (i = 0; i < nb_args; i++) {
-             const char *ct_str = tdefs->args_ct_str[i];
-             /* Incomplete TCGTargetOpDef entry. */
-@@ -XXX,XX +XXX,XX @@ static void process_op_defs(TCGContext *s)
-                     def->args_ct[i].ct |= TCG_CT_CONST;
-                     ct_str++;
-                     break;
-+
-+#ifdef TCG_TARGET_CON_STR_H
-+                /* Include all of the target-specific constraints. */
-+
-+#undef CONST
-+#define CONST(CASE, MASK) \
-+    case CASE: def->args_ct[i].ct |= MASK; ct_str++; break;
-+#define REGS(CASE, MASK) \
-+    case CASE: def->args_ct[i].regs |= MASK; ct_str++; break;
-+
-+#include "tcg-target-con-str.h"
-+
-+#undef REGS
-+#undef CONST
-                 default:
--                    ct_str = target_parse_constraint(&def->args_ct[i],
--                                                     ct_str, type);
-                     /* Typo in TCGTargetOpDef constraint. */
--                    tcg_debug_assert(ct_str != NULL);
-+                    g_assert_not_reached();
-+#else
-+                default:
-+                    {
-+                        TCGType type = (def->flags & TCG_OPF_64BIT
-+                                        ? TCG_TYPE_I64 : TCG_TYPE_I32);
-+                        ct_str = target_parse_constraint(&def->args_ct[i],
-+                                                         ct_str, type);
-+                        /* Typo in TCGTargetOpDef constraint. */
-+                        tcg_debug_assert(ct_str != NULL);
-+                    }
-+#endif
-                 }
-             }
-         }
-diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
-index XXXXXXX..XXXXXXX 100644
---- a/tcg/i386/tcg-target.c.inc
-+++ b/tcg/i386/tcg-target.c.inc
-@@ -XXX,XX +XXX,XX @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
-     return true;
- }
--/* parse target specific constraints */
--static const char *target_parse_constraint(TCGArgConstraint *ct,
--                                           const char *ct_str, TCGType type)
--{
--    switch(*ct_str++) {
--    case 'a':
--        tcg_regset_set_reg(ct->regs, TCG_REG_EAX);
--        break;
--    case 'b':
--        tcg_regset_set_reg(ct->regs, TCG_REG_EBX);
--        break;
--    case 'c':
--        tcg_regset_set_reg(ct->regs, TCG_REG_ECX);
--        break;
--    case 'd':
--        tcg_regset_set_reg(ct->regs, TCG_REG_EDX);
--        break;
--    case 'S':
--        tcg_regset_set_reg(ct->regs, TCG_REG_ESI);
--        break;
--    case 'D':
--        tcg_regset_set_reg(ct->regs, TCG_REG_EDI);
--        break;
--    case 'q':
--        /* A register that can be used as a byte operand.  */
--        ct->regs |= ALL_BYTEL_REGS;
--        break;
--    case 'Q':
--        /* A register with an addressable second byte (e.g. %ah).  */
--        ct->regs |= ALL_BYTEH_REGS;
--        break;
--    case 'r':
--        /* A general register.  */
--        ct->regs |= ALL_GENERAL_REGS;
--        break;
--    case 'W':
--        /* With TZCNT/LZCNT, we can have operand-size as an input.  */
--        ct->ct |= TCG_CT_CONST_WSZ;
--        break;
--    case 'x':
--        /* A vector register.  */
--        ct->regs |= ALL_VECTOR_REGS;
--        break;
--
--    case 'L':
--        /* qemu_ld/st data+address constraint */
--        ct->regs |= ALL_GENERAL_REGS & ~SOFTMMU_RESERVE_REGS;
--        break;
--    case 's':
--        /* qemu_st8_i32 data constraint */
--        ct->regs |= ALL_BYTEL_REGS & ~SOFTMMU_RESERVE_REGS;
--        break;
--
--    case 'e':
--        ct->ct |= TCG_CT_CONST_S32;
--        break;
--    case 'Z':
--        ct->ct |= TCG_CT_CONST_U32;
--        break;
--    case 'I':
--        ct->ct |= TCG_CT_CONST_I32;
--        break;
--
--    default:
--        return NULL;
--    }
--    return ct_str;
--}
--
- /* test if a constant matches the constraint */
- static inline int tcg_target_const_match(tcg_target_long val, TCGType type,
-                                          const TCGArgConstraint *arg_ct)
---
-.25.1

-[PULL 06/24] tcg/arm: Split out target constraints to tcg-target-con-str.h
+Deleted patch
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
----
- tcg/arm/tcg-target-con-str.h | 22 +++++++++++
- tcg/arm/tcg-target.h         |  1 +
- tcg/arm/tcg-target.c.inc     | 74 +++++++++---------------------------
-files changed, 41 insertions(+), 56 deletions(-)
- create mode 100644 tcg/arm/tcg-target-con-str.h
-diff --git a/tcg/arm/tcg-target-con-str.h b/tcg/arm/tcg-target-con-str.h
-new file mode 100644
-index XXXXXXX..XXXXXXX
---- /dev/null
-+++ b/tcg/arm/tcg-target-con-str.h
-@@ -XXX,XX +XXX,XX @@
-+/* SPDX-License-Identifier: MIT */
-+/*
-+ * Define Arm target-specific operand constraints.
-+ * Copyright (c) 2021 Linaro
-+ */
-+
-+/*
-+ * Define constraint letters for register sets:
-+ * REGS(letter, register_mask)
-+ */
-+REGS('r', ALL_GENERAL_REGS)
-+REGS('l', ALL_QLOAD_REGS)
-+REGS('s', ALL_QSTORE_REGS)
-+
-+/*
-+ * Define constraint letters for constants:
-+ * CONST(letter, TCG_CT_CONST_* bit set)
-+ */
-+CONST('I', TCG_CT_CONST_ARM)
-+CONST('K', TCG_CT_CONST_INV)
-+CONST('N', TCG_CT_CONST_NEG)
-+CONST('Z', TCG_CT_CONST_ZERO)
-diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
-index XXXXXXX..XXXXXXX 100644
---- a/tcg/arm/tcg-target.h
-+++ b/tcg/arm/tcg-target.h
-@@ -XXX,XX +XXX,XX @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t);
- #define TCG_TARGET_NEED_LDST_LABELS
- #endif
- #define TCG_TARGET_NEED_POOL_LABELS
-+#define TCG_TARGET_CON_STR_H
- #endif
-diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
-index XXXXXXX..XXXXXXX 100644
---- a/tcg/arm/tcg-target.c.inc
-+++ b/tcg/arm/tcg-target.c.inc
-@@ -XXX,XX +XXX,XX @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
- #define TCG_CT_CONST_NEG  0x400
- #define TCG_CT_CONST_ZERO 0x800
--/* parse target specific constraints */
--static const char *target_parse_constraint(TCGArgConstraint *ct,
--                                           const char *ct_str, TCGType type)
--{
--    switch (*ct_str++) {
--    case 'I':
--        ct->ct |= TCG_CT_CONST_ARM;
--        break;
--    case 'K':
--        ct->ct |= TCG_CT_CONST_INV;
--        break;
--    case 'N': /* The gcc constraint letter is L, already used here.  */
--        ct->ct |= TCG_CT_CONST_NEG;
--        break;
--    case 'Z':
--        ct->ct |= TCG_CT_CONST_ZERO;
--        break;
-+#define ALL_GENERAL_REGS  0xffffu
--    case 'r':
--        ct->regs = 0xffff;
--        break;
--
--    /* qemu_ld address */
--    case 'l':
--        ct->regs = 0xffff;
-+/*
-+ * r0-r2 will be overwritten when reading the tlb entry (softmmu only)
-+ * and r0-r1 doing the byte swapping, so don't use these.
-+ * r3 is removed for softmmu to avoid clashes with helper arguments.
-+ */
- #ifdef CONFIG_SOFTMMU
--        /* r0-r2,lr will be overwritten when reading the tlb entry,
--           so don't use these. */
--        tcg_regset_reset_reg(ct->regs, TCG_REG_R0);
--        tcg_regset_reset_reg(ct->regs, TCG_REG_R1);
--        tcg_regset_reset_reg(ct->regs, TCG_REG_R2);
--        tcg_regset_reset_reg(ct->regs, TCG_REG_R3);
--        tcg_regset_reset_reg(ct->regs, TCG_REG_R14);
-+#define ALL_QLOAD_REGS \
-+    (ALL_GENERAL_REGS & ~((1 << TCG_REG_R0) | (1 << TCG_REG_R1) | \
-+                          (1 << TCG_REG_R2) | (1 << TCG_REG_R3) | \
-+                          (1 << TCG_REG_R14)))
-+#define ALL_QSTORE_REGS \
-+    (ALL_GENERAL_REGS & ~((1 << TCG_REG_R0) | (1 << TCG_REG_R1) | \
-+                          (1 << TCG_REG_R2) | (1 << TCG_REG_R14) | \
-+                          ((TARGET_LONG_BITS == 64) << TCG_REG_R3)))
-+#else
-+#define ALL_QLOAD_REGS   ALL_GENERAL_REGS
-+#define ALL_QSTORE_REGS \
-+    (ALL_GENERAL_REGS & ~((1 << TCG_REG_R0) | (1 << TCG_REG_R1)))
- #endif
--        break;
--
--    /* qemu_st address & data */
--    case 's':
--        ct->regs = 0xffff;
--        /* r0-r2 will be overwritten when reading the tlb entry (softmmu only)
--           and r0-r1 doing the byte swapping, so don't use these. */
--        tcg_regset_reset_reg(ct->regs, TCG_REG_R0);
--        tcg_regset_reset_reg(ct->regs, TCG_REG_R1);
--#if defined(CONFIG_SOFTMMU)
--        /* Avoid clashes with registers being used for helper args */
--        tcg_regset_reset_reg(ct->regs, TCG_REG_R2);
--#if TARGET_LONG_BITS == 64
--        /* Avoid clashes with registers being used for helper args */
--        tcg_regset_reset_reg(ct->regs, TCG_REG_R3);
--#endif
--        tcg_regset_reset_reg(ct->regs, TCG_REG_R14);
--#endif
--        break;
--
--    default:
--        return NULL;
--    }
--    return ct_str;
--}
- static inline uint32_t rotl(uint32_t val, int n)
- {
---
-.25.1

-[PULL 07/24] tcg/aarch64: Split out target constraints to tcg-target-con-str.h
+Deleted patch
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
----
- tcg/aarch64/tcg-target-con-str.h | 24 +++++++++++++++
- tcg/aarch64/tcg-target.h         |  1 +
- tcg/aarch64/tcg-target.c.inc     | 51 +++++---------------------------
-files changed, 33 insertions(+), 43 deletions(-)
- create mode 100644 tcg/aarch64/tcg-target-con-str.h
-diff --git a/tcg/aarch64/tcg-target-con-str.h b/tcg/aarch64/tcg-target-con-str.h
-new file mode 100644
-index XXXXXXX..XXXXXXX
---- /dev/null
-+++ b/tcg/aarch64/tcg-target-con-str.h
-@@ -XXX,XX +XXX,XX @@
-+/* SPDX-License-Identifier: GPL-2.0-or-later */
-+/*
-+ * Define AArch64 target-specific operand constraints.
-+ * Copyright (c) 2021 Linaro
-+ */
-+
-+/*
-+ * Define constraint letters for register sets:
-+ * REGS(letter, register_mask)
-+ */
-+REGS('r', ALL_GENERAL_REGS)
-+REGS('l', ALL_QLDST_REGS)
-+REGS('w', ALL_VECTOR_REGS)
-+
-+/*
-+ * Define constraint letters for constants:
-+ * CONST(letter, TCG_CT_CONST_* bit set)
-+ */
-+CONST('A', TCG_CT_CONST_AIMM)
-+CONST('L', TCG_CT_CONST_LIMM)
-+CONST('M', TCG_CT_CONST_MONE)
-+CONST('O', TCG_CT_CONST_ORRI)
-+CONST('N', TCG_CT_CONST_ANDI)
-+CONST('Z', TCG_CT_CONST_ZERO)
-diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h
-index XXXXXXX..XXXXXXX 100644
---- a/tcg/aarch64/tcg-target.h
-+++ b/tcg/aarch64/tcg-target.h
-@@ -XXX,XX +XXX,XX @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t);
- #define TCG_TARGET_NEED_LDST_LABELS
- #endif
- #define TCG_TARGET_NEED_POOL_LABELS
-+#define TCG_TARGET_CON_STR_H
- #endif /* AARCH64_TCG_TARGET_H */
-diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc
-index XXXXXXX..XXXXXXX 100644
---- a/tcg/aarch64/tcg-target.c.inc
-+++ b/tcg/aarch64/tcg-target.c.inc
-@@ -XXX,XX +XXX,XX @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
- #define TCG_CT_CONST_ORRI 0x1000
- #define TCG_CT_CONST_ANDI 0x2000
--/* parse target specific constraints */
--static const char *target_parse_constraint(TCGArgConstraint *ct,
--                                           const char *ct_str, TCGType type)
--{
--    switch (*ct_str++) {
--    case 'r': /* general registers */
--        ct->regs |= 0xffffffffu;
--        break;
--    case 'w': /* advsimd registers */
--        ct->regs |= 0xffffffff00000000ull;
--        break;
--    case 'l': /* qemu_ld / qemu_st address, data_reg */
--        ct->regs = 0xffffffffu;
-+#define ALL_GENERAL_REGS  0xffffffffu
-+#define ALL_VECTOR_REGS   0xffffffff00000000ull
-+
- #ifdef CONFIG_SOFTMMU
--        /* x0 and x1 will be overwritten when reading the tlb entry,
--           and x2, and x3 for helper args, better to avoid using them. */
--        tcg_regset_reset_reg(ct->regs, TCG_REG_X0);
--        tcg_regset_reset_reg(ct->regs, TCG_REG_X1);
--        tcg_regset_reset_reg(ct->regs, TCG_REG_X2);
--        tcg_regset_reset_reg(ct->regs, TCG_REG_X3);
-+#define ALL_QLDST_REGS \
-+    (ALL_GENERAL_REGS & ~((1 << TCG_REG_X0) | (1 << TCG_REG_X1) | \
-+                          (1 << TCG_REG_X2) | (1 << TCG_REG_X3)))
-+#else
-+#define ALL_QLDST_REGS   ALL_GENERAL_REGS
- #endif
--        break;
--    case 'A': /* Valid for arithmetic immediate (positive or negative).  */
--        ct->ct |= TCG_CT_CONST_AIMM;
--        break;
--    case 'L': /* Valid for logical immediate.  */
--        ct->ct |= TCG_CT_CONST_LIMM;
--        break;
--    case 'M': /* minus one */
--        ct->ct |= TCG_CT_CONST_MONE;
--        break;
--    case 'O': /* vector orr/bic immediate */
--        ct->ct |= TCG_CT_CONST_ORRI;
--        break;
--    case 'N': /* vector orr/bic immediate, inverted */
--        ct->ct |= TCG_CT_CONST_ANDI;
--        break;
--    case 'Z': /* zero */
--        ct->ct |= TCG_CT_CONST_ZERO;
--        break;
--    default:
--        return NULL;
--    }
--    return ct_str;
--}
- /* Match a constant valid for addition (12-bit, optionally shifted).  */
- static inline bool is_aimm(uint64_t val)
---
-.25.1

-[PULL 08/24] tcg/ppc: Split out target constraints to tcg-target-con-str.h
+Deleted patch
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
----
- tcg/ppc/tcg-target-con-str.h | 30 +++++++++++++++
- tcg/ppc/tcg-target.h         |  1 +
- tcg/ppc/tcg-target.c.inc     | 73 ++++++++----------------------------
-files changed, 46 insertions(+), 58 deletions(-)
- create mode 100644 tcg/ppc/tcg-target-con-str.h
-diff --git a/tcg/ppc/tcg-target-con-str.h b/tcg/ppc/tcg-target-con-str.h
-new file mode 100644
-index XXXXXXX..XXXXXXX
---- /dev/null
-+++ b/tcg/ppc/tcg-target-con-str.h
-@@ -XXX,XX +XXX,XX @@
-+/* SPDX-License-Identifier: MIT */
-+/*
-+ * Define PowerPC target-specific operand constraints.
-+ * Copyright (c) 2021 Linaro
-+ */
-+
-+/*
-+ * Define constraint letters for register sets:
-+ * REGS(letter, register_mask)
-+ */
-+REGS('r', ALL_GENERAL_REGS)
-+REGS('v', ALL_VECTOR_REGS)
-+REGS('A', 1u << TCG_REG_R3)
-+REGS('B', 1u << TCG_REG_R4)
-+REGS('C', 1u << TCG_REG_R5)
-+REGS('D', 1u << TCG_REG_R6)
-+REGS('L', ALL_QLOAD_REGS)
-+REGS('S', ALL_QSTORE_REGS)
-+
-+/*
-+ * Define constraint letters for constants:
-+ * CONST(letter, TCG_CT_CONST_* bit set)
-+ */
-+CONST('I', TCG_CT_CONST_S16)
-+CONST('J', TCG_CT_CONST_U16)
-+CONST('M', TCG_CT_CONST_MONE)
-+CONST('T', TCG_CT_CONST_S32)
-+CONST('U', TCG_CT_CONST_U32)
-+CONST('W', TCG_CT_CONST_WSZ)
-+CONST('Z', TCG_CT_CONST_ZERO)
-diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h
-index XXXXXXX..XXXXXXX 100644
---- a/tcg/ppc/tcg-target.h
-+++ b/tcg/ppc/tcg-target.h
-@@ -XXX,XX +XXX,XX @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t);
- #define TCG_TARGET_NEED_LDST_LABELS
- #endif
- #define TCG_TARGET_NEED_POOL_LABELS
-+#define TCG_TARGET_CON_STR_H
- #endif
-diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc
-index XXXXXXX..XXXXXXX 100644
---- a/tcg/ppc/tcg-target.c.inc
-+++ b/tcg/ppc/tcg-target.c.inc
-@@ -XXX,XX +XXX,XX @@
- #define TCG_CT_CONST_MONE 0x2000
- #define TCG_CT_CONST_WSZ  0x4000
-+#define ALL_GENERAL_REGS  0xffffffffu
-+#define ALL_VECTOR_REGS   0xffffffff00000000ull
-+
-+#ifdef CONFIG_SOFTMMU
-+#define ALL_QLOAD_REGS \
-+    (ALL_GENERAL_REGS & \
-+     ~((1 << TCG_REG_R3) | (1 << TCG_REG_R4) | (1 << TCG_REG_R5)))
-+#define ALL_QSTORE_REGS \
-+    (ALL_GENERAL_REGS & ~((1 << TCG_REG_R3) | (1 << TCG_REG_R4) | \
-+                          (1 << TCG_REG_R5) | (1 << TCG_REG_R6)))
-+#else
-+#define ALL_QLOAD_REGS  (ALL_GENERAL_REGS & ~(1 << TCG_REG_R3))
-+#define ALL_QSTORE_REGS ALL_QLOAD_REGS
-+#endif
-+
- TCGPowerISA have_isa;
- static bool have_isel;
- bool have_altivec;
-@@ -XXX,XX +XXX,XX @@ static bool reloc_pc14(tcg_insn_unit *src_rw, const tcg_insn_unit *target)
-     return false;
- }
--/* parse target specific constraints */
--static const char *target_parse_constraint(TCGArgConstraint *ct,
--                                           const char *ct_str, TCGType type)
--{
--    switch (*ct_str++) {
--    case 'A': case 'B': case 'C': case 'D':
--        tcg_regset_set_reg(ct->regs, 3 + ct_str[0] - 'A');
--        break;
--    case 'r':
--        ct->regs = 0xffffffff;
--        break;
--    case 'v':
--        ct->regs = 0xffffffff00000000ull;
--        break;
--    case 'L':                   /* qemu_ld constraint */
--        ct->regs = 0xffffffff;
--        tcg_regset_reset_reg(ct->regs, TCG_REG_R3);
--#ifdef CONFIG_SOFTMMU
--        tcg_regset_reset_reg(ct->regs, TCG_REG_R4);
--        tcg_regset_reset_reg(ct->regs, TCG_REG_R5);
--#endif
--        break;
--    case 'S':                   /* qemu_st constraint */
--        ct->regs = 0xffffffff;
--        tcg_regset_reset_reg(ct->regs, TCG_REG_R3);
--#ifdef CONFIG_SOFTMMU
--        tcg_regset_reset_reg(ct->regs, TCG_REG_R4);
--        tcg_regset_reset_reg(ct->regs, TCG_REG_R5);
--        tcg_regset_reset_reg(ct->regs, TCG_REG_R6);
--#endif
--        break;
--    case 'I':
--        ct->ct |= TCG_CT_CONST_S16;
--        break;
--    case 'J':
--        ct->ct |= TCG_CT_CONST_U16;
--        break;
--    case 'M':
--        ct->ct |= TCG_CT_CONST_MONE;
--        break;
--    case 'T':
--        ct->ct |= TCG_CT_CONST_S32;
--        break;
--    case 'U':
--        ct->ct |= TCG_CT_CONST_U32;
--        break;
--    case 'W':
--        ct->ct |= TCG_CT_CONST_WSZ;
--        break;
--    case 'Z':
--        ct->ct |= TCG_CT_CONST_ZERO;
--        break;
--    default:
--        return NULL;
--    }
--    return ct_str;
--}
--
- /* test if a constant matches the constraint */
- static int tcg_target_const_match(tcg_target_long val, TCGType type,
-                                   const TCGArgConstraint *arg_ct)
---
-.25.1

-[PULL 09/24] tcg/tci: Split out target constraints to tcg-target-con-str.h
+Deleted patch
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
----
- tcg/tci/tcg-target-con-str.h | 11 +++++++++++
- tcg/tci/tcg-target.h         |  2 ++
- tcg/tci/tcg-target.c.inc     | 14 --------------
-files changed, 13 insertions(+), 14 deletions(-)
- create mode 100644 tcg/tci/tcg-target-con-str.h
-diff --git a/tcg/tci/tcg-target-con-str.h b/tcg/tci/tcg-target-con-str.h
-new file mode 100644
-index XXXXXXX..XXXXXXX
---- /dev/null
-+++ b/tcg/tci/tcg-target-con-str.h
-@@ -XXX,XX +XXX,XX @@
-+/* SPDX-License-Identifier: MIT */
-+/*
-+ * Define TCI target-specific operand constraints.
-+ * Copyright (c) 2021 Linaro
-+ */
-+
-+/*
-+ * Define constraint letters for register sets:
-+ * REGS(letter, register_mask)
-+ */
-+REGS('r', MAKE_64BIT_MASK(0, TCG_TARGET_NB_REGS))
-diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h
-index XXXXXXX..XXXXXXX 100644
---- a/tcg/tci/tcg-target.h
-+++ b/tcg/tci/tcg-target.h
-@@ -XXX,XX +XXX,XX @@ static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_rx,
-     /* no need to flush icache explicitly */
- }
-+#define TCG_TARGET_CON_STR_H
-+
- #endif /* TCG_TARGET_H */
-diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
-index XXXXXXX..XXXXXXX 100644
---- a/tcg/tci/tcg-target.c.inc
-+++ b/tcg/tci/tcg-target.c.inc
-@@ -XXX,XX +XXX,XX @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
-     return true;
- }
--/* Parse target specific constraints. */
--static const char *target_parse_constraint(TCGArgConstraint *ct,
--                                           const char *ct_str, TCGType type)
--{
--    switch (*ct_str++) {
--    case 'r':
--        ct->regs = BIT(TCG_TARGET_NB_REGS) - 1;
--        break;
--    default:
--        return NULL;
--    }
--    return ct_str;
--}
--
- #if defined(CONFIG_DEBUG_TCG_INTERPRETER)
- /* Show current bytecode. Used by tcg interpreter. */
- void tci_disas(uint8_t opc)
---
-.25.1

-[PULL 10/24] tcg/mips: Split out target constraints to tcg-target-con-str.h
+Deleted patch
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
----
- tcg/mips/tcg-target-con-str.h | 24 +++++++++++
- tcg/mips/tcg-target.h         |  1 +
- tcg/mips/tcg-target.c.inc     | 77 ++++++++++-------------------------
-files changed, 46 insertions(+), 56 deletions(-)
- create mode 100644 tcg/mips/tcg-target-con-str.h
-diff --git a/tcg/mips/tcg-target-con-str.h b/tcg/mips/tcg-target-con-str.h
-new file mode 100644
-index XXXXXXX..XXXXXXX
---- /dev/null
-+++ b/tcg/mips/tcg-target-con-str.h
-@@ -XXX,XX +XXX,XX @@
-+/* SPDX-License-Identifier: MIT */
-+/*
-+ * Define MIPS target-specific operand constraints.
-+ * Copyright (c) 2021 Linaro
-+ */
-+
-+/*
-+ * Define constraint letters for register sets:
-+ * REGS(letter, register_mask)
-+ */
-+REGS('r', ALL_GENERAL_REGS)
-+REGS('L', ALL_QLOAD_REGS)
-+REGS('S', ALL_QSTORE_REGS)
-+
-+/*
-+ * Define constraint letters for constants:
-+ * CONST(letter, TCG_CT_CONST_* bit set)
-+ */
-+CONST('I', TCG_CT_CONST_U16)
-+CONST('J', TCG_CT_CONST_S16)
-+CONST('K', TCG_CT_CONST_P2M1)
-+CONST('N', TCG_CT_CONST_N16)
-+CONST('W', TCG_CT_CONST_WSZ)
-+CONST('Z', TCG_CT_CONST_ZERO)
-diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h
-index XXXXXXX..XXXXXXX 100644
---- a/tcg/mips/tcg-target.h
-+++ b/tcg/mips/tcg-target.h
-@@ -XXX,XX +XXX,XX @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t);
- #ifdef CONFIG_SOFTMMU
- #define TCG_TARGET_NEED_LDST_LABELS
- #endif
-+#define TCG_TARGET_CON_STR_H
- #endif
-diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc
-index XXXXXXX..XXXXXXX 100644
---- a/tcg/mips/tcg-target.c.inc
-+++ b/tcg/mips/tcg-target.c.inc
-@@ -XXX,XX +XXX,XX @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
- #define TCG_CT_CONST_N16  0x1000   /* "Negatable" 16-bit: -32767 - 32767 */
- #define TCG_CT_CONST_WSZ  0x2000   /* word size */
-+#define ALL_GENERAL_REGS  0xffffffffu
-+#define NOA0_REGS         (ALL_GENERAL_REGS & ~(1 << TCG_REG_A0))
-+
-+#ifdef CONFIG_SOFTMMU
-+#define ALL_QLOAD_REGS \
-+    (NOA0_REGS & ~((TCG_TARGET_REG_BITS < TARGET_LONG_BITS) << TCG_REG_A2))
-+#define ALL_QSTORE_REGS \
-+    (NOA0_REGS & ~(TCG_TARGET_REG_BITS < TARGET_LONG_BITS   \
-+                   ? (1 << TCG_REG_A2) | (1 << TCG_REG_A3)  \
-+                   : (1 << TCG_REG_A1)))
-+#else
-+#define ALL_QLOAD_REGS   NOA0_REGS
-+#define ALL_QSTORE_REGS  NOA0_REGS
-+#endif
-+
-+
- static inline bool is_p2m1(tcg_target_long val)
- {
-     return val && ((val + 1) & val) == 0;
- }
--/* parse target specific constraints */
--static const char *target_parse_constraint(TCGArgConstraint *ct,
--                                           const char *ct_str, TCGType type)
--{
--    switch(*ct_str++) {
--    case 'r':
--        ct->regs = 0xffffffff;
--        break;
--    case 'L': /* qemu_ld input arg constraint */
--        ct->regs = 0xffffffff;
--        tcg_regset_reset_reg(ct->regs, TCG_REG_A0);
--#if defined(CONFIG_SOFTMMU)
--        if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
--            tcg_regset_reset_reg(ct->regs, TCG_REG_A2);
--        }
--#endif
--        break;
--    case 'S': /* qemu_st constraint */
--        ct->regs = 0xffffffff;
--        tcg_regset_reset_reg(ct->regs, TCG_REG_A0);
--#if defined(CONFIG_SOFTMMU)
--        if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
--            tcg_regset_reset_reg(ct->regs, TCG_REG_A2);
--            tcg_regset_reset_reg(ct->regs, TCG_REG_A3);
--        } else {
--            tcg_regset_reset_reg(ct->regs, TCG_REG_A1);
--        }
--#endif
--        break;
--    case 'I':
--        ct->ct |= TCG_CT_CONST_U16;
--        break;
--    case 'J':
--        ct->ct |= TCG_CT_CONST_S16;
--        break;
--    case 'K':
--        ct->ct |= TCG_CT_CONST_P2M1;
--        break;
--    case 'N':
--        ct->ct |= TCG_CT_CONST_N16;
--        break;
--    case 'W':
--        ct->ct |= TCG_CT_CONST_WSZ;
--        break;
--    case 'Z':
--        /* We are cheating a bit here, using the fact that the register
--           ZERO is also the register number 0. Hence there is no need
--           to check for const_args in each instruction. */
--        ct->ct |= TCG_CT_CONST_ZERO;
--        break;
--    default:
--        return NULL;
--    }
--    return ct_str;
--}
--
- /* test if a constant matches the constraint */
- static inline int tcg_target_const_match(tcg_target_long val, TCGType type,
-                                          const TCGArgConstraint *arg_ct)
-@@ -XXX,XX +XXX,XX @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
-     TCGArg a0, a1, a2;
-     int c2;
-+    /*
-+     * Note that many operands use the constraint set "rZ".
-+     * We make use of the fact that 0 is the ZERO register,
-+     * and hence such cases need not check for const_args.
-+     */
-     a0 = args[0];
-     a1 = args[1];
-     a2 = args[2];
---
-.25.1

-[PULL 11/24] tcg/riscv: Split out target constraints to tcg-target-con-str.h
+Deleted patch
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
----
- tcg/riscv/tcg-target-con-str.h | 21 ++++++++++++++
- tcg/riscv/tcg-target.h         |  1 +
- tcg/riscv/tcg-target.c.inc     | 52 +++++++++-------------------------
-files changed, 35 insertions(+), 39 deletions(-)
- create mode 100644 tcg/riscv/tcg-target-con-str.h
-diff --git a/tcg/riscv/tcg-target-con-str.h b/tcg/riscv/tcg-target-con-str.h
-new file mode 100644
-index XXXXXXX..XXXXXXX
---- /dev/null
-+++ b/tcg/riscv/tcg-target-con-str.h
-@@ -XXX,XX +XXX,XX @@
-+/* SPDX-License-Identifier: MIT */
-+/*
-+ * Define RISC-V target-specific operand constraints.
-+ * Copyright (c) 2021 Linaro
-+ */
-+
-+/*
-+ * Define constraint letters for register sets:
-+ * REGS(letter, register_mask)
-+ */
-+REGS('r', ALL_GENERAL_REGS)
-+REGS('L', ALL_GENERAL_REGS & ~SOFTMMU_RESERVE_REGS)
-+
-+/*
-+ * Define constraint letters for constants:
-+ * CONST(letter, TCG_CT_CONST_* bit set)
-+ */
-+CONST('I', TCG_CT_CONST_S12)
-+CONST('N', TCG_CT_CONST_N12)
-+CONST('M', TCG_CT_CONST_M12)
-+CONST('Z', TCG_CT_CONST_ZERO)
-diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h
-index XXXXXXX..XXXXXXX 100644
---- a/tcg/riscv/tcg-target.h
-+++ b/tcg/riscv/tcg-target.h
-@@ -XXX,XX +XXX,XX @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t);
- #define TCG_TARGET_NEED_POOL_LABELS
- #define TCG_TARGET_HAS_MEMORY_BSWAP 0
-+#define TCG_TARGET_CON_STR_H
- #endif
-diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
-index XXXXXXX..XXXXXXX 100644
---- a/tcg/riscv/tcg-target.c.inc
-+++ b/tcg/riscv/tcg-target.c.inc
-@@ -XXX,XX +XXX,XX @@ static const int tcg_target_call_oarg_regs[] = {
- #define TCG_CT_CONST_N12   0x400
- #define TCG_CT_CONST_M12   0x800
-+#define ALL_GENERAL_REGS      MAKE_64BIT_MASK(0, 32)
-+/*
-+ * For softmmu, we need to avoid conflicts with the first 5
-+ * argument registers to call the helper.  Some of these are
-+ * also used for the tlb lookup.
-+ */
-+#ifdef CONFIG_SOFTMMU
-+#define SOFTMMU_RESERVE_REGS  MAKE_64BIT_MASK(TCG_REG_A0, 5)
-+#else
-+#define SOFTMMU_RESERVE_REGS  0
-+#endif
-+
-+
- static inline tcg_target_long sextreg(tcg_target_long val, int pos, int len)
- {
-     if (TCG_TARGET_REG_BITS == 32) {
-@@ -XXX,XX +XXX,XX @@ static inline tcg_target_long sextreg(tcg_target_long val, int pos, int len)
-     }
- }
--/* parse target specific constraints */
--static const char *target_parse_constraint(TCGArgConstraint *ct,
--                                           const char *ct_str, TCGType type)
--{
--    switch (*ct_str++) {
--    case 'r':
--        ct->regs = 0xffffffff;
--        break;
--    case 'L':
--        /* qemu_ld/qemu_st constraint */
--        ct->regs = 0xffffffff;
--        /* qemu_ld/qemu_st uses TCG_REG_TMP0 */
--#if defined(CONFIG_SOFTMMU)
--        tcg_regset_reset_reg(ct->regs, tcg_target_call_iarg_regs[0]);
--        tcg_regset_reset_reg(ct->regs, tcg_target_call_iarg_regs[1]);
--        tcg_regset_reset_reg(ct->regs, tcg_target_call_iarg_regs[2]);
--        tcg_regset_reset_reg(ct->regs, tcg_target_call_iarg_regs[3]);
--        tcg_regset_reset_reg(ct->regs, tcg_target_call_iarg_regs[4]);
--#endif
--        break;
--    case 'I':
--        ct->ct |= TCG_CT_CONST_S12;
--        break;
--    case 'N':
--        ct->ct |= TCG_CT_CONST_N12;
--        break;
--    case 'M':
--        ct->ct |= TCG_CT_CONST_M12;
--        break;
--    case 'Z':
--        /* we can use a zero immediate as a zero register argument. */
--        ct->ct |= TCG_CT_CONST_ZERO;
--        break;
--    default:
--        return NULL;
--    }
--    return ct_str;
--}
--
- /* test if a constant matches the constraint */
- static int tcg_target_const_match(tcg_target_long val, TCGType type,
-                                   const TCGArgConstraint *arg_ct)
---
-.25.1

-[PULL 12/24] tcg/s390: Split out target constraints to tcg-target-con-str.h
+Deleted patch
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
----
- tcg/s390/tcg-target-con-str.h | 28 ++++++++++++++++++
- tcg/s390/tcg-target.h         |  1 +
- tcg/s390/tcg-target.c.inc     | 53 +++++++++--------------------------
-files changed, 42 insertions(+), 40 deletions(-)
- create mode 100644 tcg/s390/tcg-target-con-str.h
-diff --git a/tcg/s390/tcg-target-con-str.h b/tcg/s390/tcg-target-con-str.h
-new file mode 100644
-index XXXXXXX..XXXXXXX
---- /dev/null
-+++ b/tcg/s390/tcg-target-con-str.h
-@@ -XXX,XX +XXX,XX @@
-+/* SPDX-License-Identifier: MIT */
-+/*
-+ * Define S390 target-specific operand constraints.
-+ * Copyright (c) 2021 Linaro
-+ */
-+
-+/*
-+ * Define constraint letters for register sets:
-+ * REGS(letter, register_mask)
-+ */
-+REGS('r', ALL_GENERAL_REGS)
-+REGS('L', ALL_GENERAL_REGS & ~SOFTMMU_RESERVE_REGS)
-+/*
-+ * A (single) even/odd pair for division.
-+ * TODO: Add something to the register allocator to allow
-+ * this kind of regno+1 pairing to be done more generally.
-+ */
-+REGS('a', 1u << TCG_REG_R2)
-+REGS('b', 1u << TCG_REG_R3)
-+
-+/*
-+ * Define constraint letters for constants:
-+ * CONST(letter, TCG_CT_CONST_* bit set)
-+ */
-+CONST('A', TCG_CT_CONST_S33)
-+CONST('I', TCG_CT_CONST_S16)
-+CONST('J', TCG_CT_CONST_S32)
-+CONST('Z', TCG_CT_CONST_ZERO)
-diff --git a/tcg/s390/tcg-target.h b/tcg/s390/tcg-target.h
-index XXXXXXX..XXXXXXX 100644
---- a/tcg/s390/tcg-target.h
-+++ b/tcg/s390/tcg-target.h
-@@ -XXX,XX +XXX,XX @@ static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_rx,
- #define TCG_TARGET_NEED_LDST_LABELS
- #endif
- #define TCG_TARGET_NEED_POOL_LABELS
-+#define TCG_TARGET_CON_STR_H
- #endif
-diff --git a/tcg/s390/tcg-target.c.inc b/tcg/s390/tcg-target.c.inc
-index XXXXXXX..XXXXXXX 100644
---- a/tcg/s390/tcg-target.c.inc
-+++ b/tcg/s390/tcg-target.c.inc
-@@ -XXX,XX +XXX,XX @@
- #define TCG_CT_CONST_S33   0x400
- #define TCG_CT_CONST_ZERO  0x800
-+#define ALL_GENERAL_REGS     MAKE_64BIT_MASK(0, 16)
-+/*
-+ * For softmmu, we need to avoid conflicts with the first 3
-+ * argument registers to perform the tlb lookup, and to call
-+ * the helper function.
-+ */
-+#ifdef CONFIG_SOFTMMU
-+#define SOFTMMU_RESERVE_REGS MAKE_64BIT_MASK(TCG_REG_R2, 3)
-+#else
-+#define SOFTMMU_RESERVE_REGS 0
-+#endif
-+
-+
- /* Several places within the instruction set 0 means "no register"
-    rather than TCG_REG_R0.  */
- #define TCG_REG_NONE    0
-@@ -XXX,XX +XXX,XX @@ static bool patch_reloc(tcg_insn_unit *src_rw, int type,
-     return false;
- }
--/* parse target specific constraints */
--static const char *target_parse_constraint(TCGArgConstraint *ct,
--                                           const char *ct_str, TCGType type)
--{
--    switch (*ct_str++) {
--    case 'r':                  /* all registers */
--        ct->regs = 0xffff;
--        break;
--    case 'L':                  /* qemu_ld/st constraint */
--        ct->regs = 0xffff;
--        tcg_regset_reset_reg(ct->regs, TCG_REG_R2);
--        tcg_regset_reset_reg(ct->regs, TCG_REG_R3);
--        tcg_regset_reset_reg(ct->regs, TCG_REG_R4);
--        break;
--    case 'a':                  /* force R2 for division */
--        ct->regs = 0;
--        tcg_regset_set_reg(ct->regs, TCG_REG_R2);
--        break;
--    case 'b':                  /* force R3 for division */
--        ct->regs = 0;
--        tcg_regset_set_reg(ct->regs, TCG_REG_R3);
--        break;
--    case 'A':
--        ct->ct |= TCG_CT_CONST_S33;
--        break;
--    case 'I':
--        ct->ct |= TCG_CT_CONST_S16;
--        break;
--    case 'J':
--        ct->ct |= TCG_CT_CONST_S32;
--        break;
--    case 'Z':
--        ct->ct |= TCG_CT_CONST_ZERO;
--        break;
--    default:
--        return NULL;
--    }
--    return ct_str;
--}
--
- /* Test if a constant matches the constraint. */
- static int tcg_target_const_match(tcg_target_long val, TCGType type,
-                                   const TCGArgConstraint *arg_ct)
---
-.25.1

-[PULL 13/24] tcg/sparc: Split out target constraints to tcg-target-con-str.h
+[PULL v3 01/44] accel/tcg: Add DisasContextBase argument to translator_ld*
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+From: Ilya Leoshkevich <iii@linux.ibm.com>
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com>
 [rth: Split out of a larger patch.]
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 ---
- tcg/sparc/tcg-target-con-str.h | 23 ++++++++++
+ include/exec/translator.h                 |  9 +++++----
- tcg/sparc/tcg-target.h         |  5 +--
+ target/arm/arm_ldst.h                     | 12 ++++++------
- tcg/sparc/tcg-target.c.inc     | 81 +++++++++++++---------------------
+ target/alpha/translate.c                  |  2 +-
-files changed, 55 insertions(+), 54 deletions(-)
+ target/arm/translate-a64.c                |  2 +-
- create mode 100644 tcg/sparc/tcg-target-con-str.h
+ target/arm/translate.c                    |  9 +++++----
  target/hexagon/translate.c                |  3 ++-
  target/hppa/translate.c                   |  2 +-
  target/i386/tcg/translate.c               | 10 +++++-----
  target/m68k/translate.c                   |  2 +-
  target/mips/tcg/translate.c               |  8 ++++----
  target/openrisc/translate.c               |  2 +-
  target/ppc/translate.c                    |  5 +++--
  target/riscv/translate.c                  |  5 +++--
  target/s390x/tcg/translate.c              | 16 +++++++++-------
  target/sh4/translate.c                    |  4 ++--
  target/sparc/translate.c                  |  2 +-
  target/xtensa/translate.c                 |  5 +++--
  target/mips/tcg/micromips_translate.c.inc |  2 +-
  target/mips/tcg/mips16e_translate.c.inc   |  4 ++--
  target/mips/tcg/nanomips_translate.c.inc  |  4 ++--
 files changed, 58 insertions(+), 50 deletions(-)
-diff --git a/tcg/sparc/tcg-target-con-str.h b/tcg/sparc/tcg-target-con-str.h
+diff --git a/include/exec/translator.h b/include/exec/translator.h
-new file mode 100644
+index XXXXXXX..XXXXXXX 100644
-index XXXXXXX..XXXXXXX
+--- a/include/exec/translator.h
---- /dev/null
++++ b/include/exec/translator.h
-+++ b/tcg/sparc/tcg-target-con-str.h
+@@ -XXX,XX +XXX,XX @@ bool translator_use_goto_tb(DisasContextBase *db, target_ulong dest);
  #define GEN_TRANSLATOR_LD(fullname, type, load_fn, swap_fn)             \
      static inline type                                                  \
 -    fullname ## _swap(CPUArchState *env, abi_ptr pc, bool do_swap)      \
 +    fullname ## _swap(CPUArchState *env, DisasContextBase *dcbase,      \
 +                      abi_ptr pc, bool do_swap)                         \
      {                                                                   \
          type ret = load_fn(env, pc);                                    \
          if (do_swap) {                                                  \
@@ -XXX,XX +XXX,XX @@ bool translator_use_goto_tb(DisasContextBase *db, target_ulong dest);
          plugin_insn_append(&ret, sizeof(ret));                          \
          return ret;                                                     \
      }                                                                   \
 -                                                                        \
 -    static inline type fullname(CPUArchState *env, abi_ptr pc)          \
 +    static inline type fullname(CPUArchState *env,                      \
 +                                DisasContextBase *dcbase, abi_ptr pc)   \
      {                                                                   \
 -        return fullname ## _swap(env, pc, false);                       \
 +        return fullname ## _swap(env, dcbase, pc, false);               \
      }
  GEN_TRANSLATOR_LD(translator_ldub, uint8_t, cpu_ldub_code, /* no swap */)
 diff --git a/target/arm/arm_ldst.h b/target/arm/arm_ldst.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/arm_ldst.h
 +++ b/target/arm/arm_ldst.h
 @@ -XXX,XX +XXX,XX @@
-+/* SPDX-License-Identifier: MIT */
+ #include "qemu/bswap.h"
-+/*
-+ * Define Sparc target-specific operand constraints.
+ /* Load an instruction and return it in the standard little-endian order */
-+ * Copyright (c) 2021 Linaro
+-static inline uint32_t arm_ldl_code(CPUARMState *env, target_ulong addr,
-+ */
+-                                    bool sctlr_b)
-+
++static inline uint32_t arm_ldl_code(CPUARMState *env, DisasContextBase *s,
-+/*
++                                    target_ulong addr, bool sctlr_b)
-+ * Define constraint letters for register sets:
+ {
-+ * REGS(letter, register_mask)
+-    return translator_ldl_swap(env, addr, bswap_code(sctlr_b));
-+ */
++    return translator_ldl_swap(env, s, addr, bswap_code(sctlr_b));
-+REGS('r', ALL_GENERAL_REGS)
+ }
-+REGS('R', ALL_GENERAL_REGS64)
-+REGS('s', ALL_QLDST_REGS)
+ /* Ditto, for a halfword (Thumb) instruction */
-+REGS('S', ALL_QLDST_REGS64)
+-static inline uint16_t arm_lduw_code(CPUARMState *env, target_ulong addr,
-+REGS('A', TARGET_LONG_BITS == 64 ? ALL_QLDST_REGS64 : ALL_QLDST_REGS)
+-                                     bool sctlr_b)
-+
++static inline uint16_t arm_lduw_code(CPUARMState *env, DisasContextBase* s,
-+/*
++                                     target_ulong addr, bool sctlr_b)
-+ * Define constraint letters for constants:
+ {
-+ * CONST(letter, TCG_CT_CONST_* bit set)
+ #ifndef CONFIG_USER_ONLY
-+ */
+     /* In big-endian (BE32) mode, adjacent Thumb instructions have been swapped
-+CONST('I', TCG_CT_CONST_S11)
+@@ -XXX,XX +XXX,XX @@ static inline uint16_t arm_lduw_code(CPUARMState *env, target_ulong addr,
-+CONST('J', TCG_CT_CONST_S13)
+         addr ^= 2;
-+CONST('Z', TCG_CT_CONST_ZERO)
+     }
 diff --git a/tcg/sparc/tcg-target.h b/tcg/sparc/tcg-target.h
 index XXXXXXX..XXXXXXX 100644
 --- a/tcg/sparc/tcg-target.h
 +++ b/tcg/sparc/tcg-target.h
@@ -XXX,XX +XXX,XX @@ typedef enum {
      TCG_REG_I7,
  } TCGReg;
 -#define TCG_CT_CONST_S11  0x100
 -#define TCG_CT_CONST_S13  0x200
 -#define TCG_CT_CONST_ZERO 0x400
 -
  /* used for function call generation */
  #define TCG_REG_CALL_STACK TCG_REG_O6
@@ -XXX,XX +XXX,XX @@ extern bool use_vis3_instructions;
  void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t);
  #define TCG_TARGET_NEED_POOL_LABELS
 +#define TCG_TARGET_CON_STR_H
  #endif
-diff --git a/tcg/sparc/tcg-target.c.inc b/tcg/sparc/tcg-target.c.inc
+-    return translator_lduw_swap(env, addr, bswap_code(sctlr_b));
-index XXXXXXX..XXXXXXX 100644
++    return translator_lduw_swap(env, s, addr, bswap_code(sctlr_b));
---- a/tcg/sparc/tcg-target.c.inc
+ }
-+++ b/tcg/sparc/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
  # define SPARC64 0
  #endif
+diff --git a/target/alpha/translate.c b/target/alpha/translate.c
--/* Note that sparcv8plus can only hold 64 bit quantities in %g and %o
+index XXXXXXX..XXXXXXX 100644
--   registers.  These are saved manually by the kernel in full 64-bit
+--- a/target/alpha/translate.c
--   slots.  The %i and %l registers are saved by the register window
++++ b/target/alpha/translate.c
--   mechanism, which only allocates space for 32 bits.  Given that this
+@@ -XXX,XX +XXX,XX @@ static void alpha_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
--   window spill/fill can happen on any signal, we must consider the
+ {
--   high bits of the %i and %l registers garbage at all times.  */
+     DisasContext *ctx = container_of(dcbase, DisasContext, base);
--#if SPARC64
+     CPUAlphaState *env = cpu->env_ptr;
--# define ALL_64  0xffffffffu
+-    uint32_t insn = translator_ldl(env, ctx->base.pc_next);
-+#define TCG_CT_CONST_S11  0x100
++    uint32_t insn = translator_ldl(env, &ctx->base, ctx->base.pc_next);
-+#define TCG_CT_CONST_S13  0x200
-+#define TCG_CT_CONST_ZERO 0x400
+     ctx->base.pc_next += 4;
-+
+     ctx->base.is_jmp = translate_one(ctx, insn);
-+/*
+diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
-+ * For softmmu, we need to avoid conflicts with the first 3
+index XXXXXXX..XXXXXXX 100644
-+ * argument registers to perform the tlb lookup, and to call
+--- a/target/arm/translate-a64.c
-+ * the helper function.
++++ b/target/arm/translate-a64.c
-+ */
+@@ -XXX,XX +XXX,XX @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
-+#ifdef CONFIG_SOFTMMU
+     }
-+#define SOFTMMU_RESERVE_REGS MAKE_64BIT_MASK(TCG_REG_O0, 3)
- #else
+     s->pc_curr = s->base.pc_next;
--# define ALL_64  0xffffu
+-    insn = arm_ldl_code(env, s->base.pc_next, s->sctlr_b);
-+#define SOFTMMU_RESERVE_REGS 0
++    insn = arm_ldl_code(env, &s->base, s->base.pc_next, s->sctlr_b);
      s->insn = insn;
      s->base.pc_next += 4;
 diff --git a/target/arm/translate.c b/target/arm/translate.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate.c
 +++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static bool insn_crosses_page(CPUARMState *env, DisasContext *s)
       * boundary, so we cross the page if the first 16 bits indicate
       * that this is a 32 bit insn.
       */
 -    uint16_t insn = arm_lduw_code(env, s->base.pc_next, s->sctlr_b);
 +    uint16_t insn = arm_lduw_code(env, &s->base, s->base.pc_next, s->sctlr_b);
      return !thumb_insn_is_16bit(s, s->base.pc_next, insn);
  }
@@ -XXX,XX +XXX,XX @@ static void arm_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
      }
      dc->pc_curr = dc->base.pc_next;
 -    insn = arm_ldl_code(env, dc->base.pc_next, dc->sctlr_b);
 +    insn = arm_ldl_code(env, &dc->base, dc->base.pc_next, dc->sctlr_b);
      dc->insn = insn;
      dc->base.pc_next += 4;
      disas_arm_insn(dc, insn);
@@ -XXX,XX +XXX,XX @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
      }
      dc->pc_curr = dc->base.pc_next;
 -    insn = arm_lduw_code(env, dc->base.pc_next, dc->sctlr_b);
 +    insn = arm_lduw_code(env, &dc->base, dc->base.pc_next, dc->sctlr_b);
      is_16bit = thumb_insn_is_16bit(dc, dc->base.pc_next, insn);
      dc->base.pc_next += 2;
      if (!is_16bit) {
 -        uint32_t insn2 = arm_lduw_code(env, dc->base.pc_next, dc->sctlr_b);
 +        uint32_t insn2 = arm_lduw_code(env, &dc->base, dc->base.pc_next,
 +                                       dc->sctlr_b);
          insn = insn << 16 | insn2;
          dc->base.pc_next += 2;
 diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/hexagon/translate.c
 +++ b/target/hexagon/translate.c
@@ -XXX,XX +XXX,XX @@ static int read_packet_words(CPUHexagonState *env, DisasContext *ctx,
      memset(words, 0, PACKET_WORDS_MAX * sizeof(uint32_t));
      for (nwords = 0; !found_end && nwords < PACKET_WORDS_MAX; nwords++) {
          words[nwords] =
 -            translator_ldl(env, ctx->base.pc_next + nwords * sizeof(uint32_t));
 +            translator_ldl(env, &ctx->base,
 +                           ctx->base.pc_next + nwords * sizeof(uint32_t));
          found_end = is_packet_end(words[nwords]);
      }
      if (!found_end) {
 diff --git a/target/hppa/translate.c b/target/hppa/translate.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/hppa/translate.c
 +++ b/target/hppa/translate.c
@@ -XXX,XX +XXX,XX @@ static void hppa_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
      {
          /* Always fetch the insn, even if nullified, so that we check
             the page permissions for execute.  */
 -        uint32_t insn = translator_ldl(env, ctx->base.pc_next);
 +        uint32_t insn = translator_ldl(env, &ctx->base, ctx->base.pc_next);
          /* Set up the IA queue for the next insn.
             This will be overwritten by a branch.  */
 diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/i386/tcg/translate.c
 +++ b/target/i386/tcg/translate.c
@@ -XXX,XX +XXX,XX @@ static uint64_t advance_pc(CPUX86State *env, DisasContext *s, int num_bytes)
  static inline uint8_t x86_ldub_code(CPUX86State *env, DisasContext *s)
  {
 -    return translator_ldub(env, advance_pc(env, s, 1));
 +    return translator_ldub(env, &s->base, advance_pc(env, s, 1));
  }
  static inline int16_t x86_ldsw_code(CPUX86State *env, DisasContext *s)
  {
 -    return translator_ldsw(env, advance_pc(env, s, 2));
 +    return translator_ldsw(env, &s->base, advance_pc(env, s, 2));
  }
  static inline uint16_t x86_lduw_code(CPUX86State *env, DisasContext *s)
  {
 -    return translator_lduw(env, advance_pc(env, s, 2));
 +    return translator_lduw(env, &s->base, advance_pc(env, s, 2));
  }
  static inline uint32_t x86_ldl_code(CPUX86State *env, DisasContext *s)
  {
 -    return translator_ldl(env, advance_pc(env, s, 4));
 +    return translator_ldl(env, &s->base, advance_pc(env, s, 4));
  }
  #ifdef TARGET_X86_64
  static inline uint64_t x86_ldq_code(CPUX86State *env, DisasContext *s)
  {
 -    return translator_ldq(env, advance_pc(env, s, 8));
 +    return translator_ldq(env, &s->base, advance_pc(env, s, 8));
  }
  #endif
-+/*
+diff --git a/target/m68k/translate.c b/target/m68k/translate.c
-+ * Note that sparcv8plus can only hold 64 bit quantities in %g and %o
+index XXXXXXX..XXXXXXX 100644
-+ * registers.  These are saved manually by the kernel in full 64-bit
+--- a/target/m68k/translate.c
-+ * slots.  The %i and %l registers are saved by the register window
++++ b/target/m68k/translate.c
-+ * mechanism, which only allocates space for 32 bits.  Given that this
+@@ -XXX,XX +XXX,XX @@ static TCGv gen_ldst(DisasContext *s, int opsize, TCGv addr, TCGv val,
-+ * window spill/fill can happen on any signal, we must consider the
+ static inline uint16_t read_im16(CPUM68KState *env, DisasContext *s)
-+ * high bits of the %i and %l registers garbage at all times.
+ {
-+ */
+     uint16_t im;
-+#define ALL_GENERAL_REGS     MAKE_64BIT_MASK(0, 32)
+-    im = translator_lduw(env, s->pc);
-+#if SPARC64
++    im = translator_lduw(env, &s->base, s->pc);
-+# define ALL_GENERAL_REGS64  ALL_GENERAL_REGS
+     s->pc += 2;
-+#else
+     return im;
-+# define ALL_GENERAL_REGS64  MAKE_64BIT_MASK(0, 16)
+ }
-+#endif
+diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
-+#define ALL_QLDST_REGS       (ALL_GENERAL_REGS & ~SOFTMMU_RESERVE_REGS)
+index XXXXXXX..XXXXXXX 100644
-+#define ALL_QLDST_REGS64     (ALL_GENERAL_REGS64 & ~SOFTMMU_RESERVE_REGS)
+--- a/target/mips/tcg/translate.c
-+
++++ b/target/mips/tcg/translate.c
- /* Define some temporary registers.  T2 is used for constant generation.  */
+@@ -XXX,XX +XXX,XX @@ static void mips_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
- #define TCG_REG_T1  TCG_REG_G1
- #define TCG_REG_T2  TCG_REG_O7
+     is_slot = ctx->hflags & MIPS_HFLAG_BMASK;
-@@ -XXX,XX +XXX,XX @@ static bool patch_reloc(tcg_insn_unit *src_rw, int type,
+     if (ctx->insn_flags & ISA_NANOMIPS32) {
-     return true;
+-        ctx->opcode = translator_lduw(env, ctx->base.pc_next);
- }
++        ctx->opcode = translator_lduw(env, &ctx->base, ctx->base.pc_next);
+         insn_bytes = decode_isa_nanomips(env, ctx);
--/* parse target specific constraints */
+     } else if (!(ctx->hflags & MIPS_HFLAG_M16)) {
--static const char *target_parse_constraint(TCGArgConstraint *ct,
+-        ctx->opcode = translator_ldl(env, ctx->base.pc_next);
--                                           const char *ct_str, TCGType type)
++        ctx->opcode = translator_ldl(env, &ctx->base, ctx->base.pc_next);
--{
+         insn_bytes = 4;
--    switch (*ct_str++) {
+         decode_opc(env, ctx);
--    case 'r':
+     } else if (ctx->insn_flags & ASE_MICROMIPS) {
--        ct->regs = 0xffffffff;
+-        ctx->opcode = translator_lduw(env, ctx->base.pc_next);
--        break;
++        ctx->opcode = translator_lduw(env, &ctx->base, ctx->base.pc_next);
--    case 'R':
+         insn_bytes = decode_isa_micromips(env, ctx);
--        ct->regs = ALL_64;
+     } else if (ctx->insn_flags & ASE_MIPS16) {
--        break;
+-        ctx->opcode = translator_lduw(env, ctx->base.pc_next);
--    case 'A': /* qemu_ld/st address constraint */
++        ctx->opcode = translator_lduw(env, &ctx->base, ctx->base.pc_next);
--        ct->regs = TARGET_LONG_BITS == 64 ? ALL_64 : 0xffffffff;
+         insn_bytes = decode_ase_mips16e(env, ctx);
--    reserve_helpers:
+     } else {
--        tcg_regset_reset_reg(ct->regs, TCG_REG_O0);
+         gen_reserved_instruction(ctx);
--        tcg_regset_reset_reg(ct->regs, TCG_REG_O1);
+diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c
--        tcg_regset_reset_reg(ct->regs, TCG_REG_O2);
+index XXXXXXX..XXXXXXX 100644
--        break;
+--- a/target/openrisc/translate.c
--    case 's': /* qemu_st data 32-bit constraint */
++++ b/target/openrisc/translate.c
--        ct->regs = 0xffffffff;
+@@ -XXX,XX +XXX,XX @@ static void openrisc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
--        goto reserve_helpers;
+ {
--    case 'S': /* qemu_st data 64-bit constraint */
+     DisasContext *dc = container_of(dcbase, DisasContext, base);
--        ct->regs = ALL_64;
+     OpenRISCCPU *cpu = OPENRISC_CPU(cs);
--        goto reserve_helpers;
+-    uint32_t insn = translator_ldl(&cpu->env, dc->base.pc_next);
--    case 'I':
++    uint32_t insn = translator_ldl(&cpu->env, &dc->base, dc->base.pc_next);
--        ct->ct |= TCG_CT_CONST_S11;
--        break;
+     if (!decode(dc, insn)) {
--    case 'J':
+         gen_illegal_exception(dc);
--        ct->ct |= TCG_CT_CONST_S13;
+diff --git a/target/ppc/translate.c b/target/ppc/translate.c
--        break;
+index XXXXXXX..XXXXXXX 100644
--    case 'Z':
+--- a/target/ppc/translate.c
--        ct->ct |= TCG_CT_CONST_ZERO;
++++ b/target/ppc/translate.c
--        break;
+@@ -XXX,XX +XXX,XX @@ static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
--    default:
+               ctx->base.pc_next, ctx->mem_idx, (int)msr_ir);
--        return NULL;
--    }
+     ctx->cia = pc = ctx->base.pc_next;
--    return ct_str;
+-    insn = translator_ldl_swap(env, pc, need_byteswap(ctx));
--}
++    insn = translator_ldl_swap(env, dcbase, pc, need_byteswap(ctx));
--
+     ctx->base.pc_next = pc += 4;
- /* test if a constant matches the constraint */
- static inline int tcg_target_const_match(tcg_target_long val, TCGType type,
+     if (!is_prefix_insn(ctx, insn)) {
-                                          const TCGArgConstraint *arg_ct)
+@@ -XXX,XX +XXX,XX @@ static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
-@@ -XXX,XX +XXX,XX @@ static void tcg_target_init(TCGContext *s)
+         gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_INSN);
          ok = true;
      } else {
 -        uint32_t insn2 = translator_ldl_swap(env, pc, need_byteswap(ctx));
 +        uint32_t insn2 = translator_ldl_swap(env, dcbase, pc,
 +                                             need_byteswap(ctx));
          ctx->base.pc_next = pc += 4;
          ok = decode_insn64(ctx, deposit64(insn2, 32, 32, insn));
      }
 diff --git a/target/riscv/translate.c b/target/riscv/translate.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/translate.c
 +++ b/target/riscv/translate.c
@@ -XXX,XX +XXX,XX @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
      } else {
          uint32_t opcode32 = opcode;
          opcode32 = deposit32(opcode32, 16, 16,
 -                             translator_lduw(env, ctx->base.pc_next + 2));
 +                             translator_lduw(env, &ctx->base,
 +                                             ctx->base.pc_next + 2));
          ctx->pc_succ_insn = ctx->base.pc_next + 4;
          if (!decode_insn32(ctx, opcode32)) {
              gen_exception_illegal(ctx);
@@ -XXX,XX +XXX,XX @@ static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
  {
      DisasContext *ctx = container_of(dcbase, DisasContext, base);
      CPURISCVState *env = cpu->env_ptr;
 -    uint16_t opcode16 = translator_lduw(env, ctx->base.pc_next);
 +    uint16_t opcode16 = translator_lduw(env, &ctx->base, ctx->base.pc_next);
      decode_opc(env, ctx, opcode16);
      ctx->base.pc_next = ctx->pc_succ_insn;
 diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/s390x/tcg/translate.c
 +++ b/target/s390x/tcg/translate.c
@@ -XXX,XX +XXX,XX @@ static void update_cc_op(DisasContext *s)
      }
  }
 -static inline uint64_t ld_code2(CPUS390XState *env, uint64_t pc)
 +static inline uint64_t ld_code2(CPUS390XState *env, DisasContext *s,
 +                                uint64_t pc)
  {
 -    return (uint64_t)cpu_lduw_code(env, pc);
 +    return (uint64_t)translator_lduw(env, &s->base, pc);
  }
 -static inline uint64_t ld_code4(CPUS390XState *env, uint64_t pc)
 +static inline uint64_t ld_code4(CPUS390XState *env, DisasContext *s,
 +                                uint64_t pc)
  {
 -    return (uint64_t)(uint32_t)cpu_ldl_code(env, pc);
 +    return (uint64_t)(uint32_t)translator_ldl(env, &s->base, pc);
  }
  static int get_mem_index(DisasContext *s)
@@ -XXX,XX +XXX,XX @@ static const DisasInsn *extract_insn(CPUS390XState *env, DisasContext *s)
          ilen = s->ex_value & 0xf;
          op = insn >> 56;
      } else {
 -        insn = ld_code2(env, pc);
 +        insn = ld_code2(env, s, pc);
          op = (insn >> 8) & 0xff;
          ilen = get_ilen(op);
          switch (ilen) {
@@ -XXX,XX +XXX,XX @@ static const DisasInsn *extract_insn(CPUS390XState *env, DisasContext *s)
              insn = insn << 48;
              break;
          case 4:
 -            insn = ld_code4(env, pc) << 32;
 +            insn = ld_code4(env, s, pc) << 32;
              break;
          case 6:
 -            insn = (insn << 48) | (ld_code4(env, pc + 2) << 16);
 +            insn = (insn << 48) | (ld_code4(env, s, pc + 2) << 16);
              break;
          default:
              g_assert_not_reached();
 diff --git a/target/sh4/translate.c b/target/sh4/translate.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/sh4/translate.c
 +++ b/target/sh4/translate.c
@@ -XXX,XX +XXX,XX @@ static void decode_gusa(DisasContext *ctx, CPUSH4State *env)
      /* Read all of the insns for the region.  */
      for (i = 0; i < max_insns; ++i) {
 -        insns[i] = translator_lduw(env, pc + i * 2);
 +        insns[i] = translator_lduw(env, &ctx->base, pc + i * 2);
      }
      ld_adr = ld_dst = ld_mop = -1;
@@ -XXX,XX +XXX,XX @@ static void sh4_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
      }
  #endif
--    tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffff;
+-    ctx->opcode = translator_lduw(env, ctx->base.pc_next);
--    tcg_target_available_regs[TCG_TYPE_I64] = ALL_64;
++    ctx->opcode = translator_lduw(env, &ctx->base, ctx->base.pc_next);
-+    tcg_target_available_regs[TCG_TYPE_I32] = ALL_GENERAL_REGS;
+     decode_opc(ctx);
-+    tcg_target_available_regs[TCG_TYPE_I64] = ALL_GENERAL_REGS64;
+     ctx->base.pc_next += 2;
+ }
-     tcg_target_call_clobber_regs = 0;
+diff --git a/target/sparc/translate.c b/target/sparc/translate.c
-     tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_G1);
+index XXXXXXX..XXXXXXX 100644
 --- a/target/sparc/translate.c
 +++ b/target/sparc/translate.c
@@ -XXX,XX +XXX,XX @@ static void sparc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
      CPUSPARCState *env = cs->env_ptr;
      unsigned int insn;
 -    insn = translator_ldl(env, dc->pc);
 +    insn = translator_ldl(env, &dc->base, dc->pc);
      dc->base.pc_next += 4;
      disas_sparc_insn(dc, insn);
 diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/xtensa/translate.c
 +++ b/target/xtensa/translate.c
@@ -XXX,XX +XXX,XX @@ static int arg_copy_compare(const void *a, const void *b)
  static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc)
  {
      xtensa_isa isa = dc->config->isa;
 -    unsigned char b[MAX_INSN_LENGTH] = {translator_ldub(env, dc->pc)};
 +    unsigned char b[MAX_INSN_LENGTH] = {translator_ldub(env, &dc->base,
 +                                                        dc->pc)};
      unsigned len = xtensa_op0_insn_len(dc, b[0]);
      xtensa_format fmt;
      int slot, slots;
@@ -XXX,XX +XXX,XX @@ static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc)
      dc->base.pc_next = dc->pc + len;
      for (i = 1; i < len; ++i) {
 -        b[i] = translator_ldub(env, dc->pc + i);
 +        b[i] = translator_ldub(env, &dc->base, dc->pc + i);
      }
      xtensa_insnbuf_from_chars(isa, dc->insnbuf, b, len);
      fmt = xtensa_format_decode(isa, dc->insnbuf);
 diff --git a/target/mips/tcg/micromips_translate.c.inc b/target/mips/tcg/micromips_translate.c.inc
 index XXXXXXX..XXXXXXX 100644
 --- a/target/mips/tcg/micromips_translate.c.inc
 +++ b/target/mips/tcg/micromips_translate.c.inc
@@ -XXX,XX +XXX,XX @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
      uint32_t op, minor, minor2, mips32_op;
      uint32_t cond, fmt, cc;
 -    insn = translator_lduw(env, ctx->base.pc_next + 2);
 +    insn = translator_lduw(env, &ctx->base, ctx->base.pc_next + 2);
      ctx->opcode = (ctx->opcode << 16) | insn;
      rt = (ctx->opcode >> 21) & 0x1f;
 diff --git a/target/mips/tcg/mips16e_translate.c.inc b/target/mips/tcg/mips16e_translate.c.inc
 index XXXXXXX..XXXXXXX 100644
 --- a/target/mips/tcg/mips16e_translate.c.inc
 +++ b/target/mips/tcg/mips16e_translate.c.inc
@@ -XXX,XX +XXX,XX @@ static void decode_i64_mips16(DisasContext *ctx,
  static int decode_extended_mips16_opc(CPUMIPSState *env, DisasContext *ctx)
  {
 -    int extend = translator_lduw(env, ctx->base.pc_next + 2);
 +    int extend = translator_lduw(env, &ctx->base, ctx->base.pc_next + 2);
      int op, rx, ry, funct, sa;
      int16_t imm, offset;
@@ -XXX,XX +XXX,XX @@ static int decode_ase_mips16e(CPUMIPSState *env, DisasContext *ctx)
          /* No delay slot, so just process as a normal instruction */
          break;
      case M16_OPC_JAL:
 -        offset = translator_lduw(env, ctx->base.pc_next + 2);
 +        offset = translator_lduw(env, &ctx->base, ctx->base.pc_next + 2);
          offset = (((ctx->opcode & 0x1f) << 21)
                    | ((ctx->opcode >> 5) & 0x1f) << 16
                    | offset) << 2;
 diff --git a/target/mips/tcg/nanomips_translate.c.inc b/target/mips/tcg/nanomips_translate.c.inc
 index XXXXXXX..XXXXXXX 100644
 --- a/target/mips/tcg/nanomips_translate.c.inc
 +++ b/target/mips/tcg/nanomips_translate.c.inc
@@ -XXX,XX +XXX,XX @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
      int offset;
      int imm;
 -    insn = translator_lduw(env, ctx->base.pc_next + 2);
 +    insn = translator_lduw(env, &ctx->base, ctx->base.pc_next + 2);
      ctx->opcode = (ctx->opcode << 16) | insn;
      rt = extract32(ctx->opcode, 21, 5);
@@ -XXX,XX +XXX,XX @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
          break;
      case NM_P48I:
          {
 -            insn = translator_lduw(env, ctx->base.pc_next + 4);
 +            insn = translator_lduw(env, &ctx->base, ctx->base.pc_next + 4);
              target_long addr_off = extract32(ctx->opcode, 0, 16) | insn << 16;
              switch (extract32(ctx->opcode, 16, 5)) {
              case NM_LI48:
 --
 .25.1

-[PULL 14/24] tcg: Remove TCG_TARGET_CON_STR_H
+Deleted patch
-All backends have now been converted to tcg-target-con-str.h,
-so we can remove the fallback code.
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
----
- tcg/aarch64/tcg-target.h |  1 -
- tcg/arm/tcg-target.h     |  1 -
- tcg/i386/tcg-target.h    |  1 -
- tcg/mips/tcg-target.h    |  1 -
- tcg/ppc/tcg-target.h     |  1 -
- tcg/riscv/tcg-target.h   |  1 -
- tcg/s390/tcg-target.h    |  1 -
- tcg/sparc/tcg-target.h   |  1 -
- tcg/tci/tcg-target.h     |  2 --
- tcg/tcg.c                | 16 ----------------
-files changed, 26 deletions(-)
-diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h
-index XXXXXXX..XXXXXXX 100644
---- a/tcg/aarch64/tcg-target.h
-+++ b/tcg/aarch64/tcg-target.h
-@@ -XXX,XX +XXX,XX @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t);
- #define TCG_TARGET_NEED_LDST_LABELS
- #endif
- #define TCG_TARGET_NEED_POOL_LABELS
--#define TCG_TARGET_CON_STR_H
- #endif /* AARCH64_TCG_TARGET_H */
-diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
-index XXXXXXX..XXXXXXX 100644
---- a/tcg/arm/tcg-target.h
-+++ b/tcg/arm/tcg-target.h
-@@ -XXX,XX +XXX,XX @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t);
- #define TCG_TARGET_NEED_LDST_LABELS
- #endif
- #define TCG_TARGET_NEED_POOL_LABELS
--#define TCG_TARGET_CON_STR_H
- #endif
-diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h
-index XXXXXXX..XXXXXXX 100644
---- a/tcg/i386/tcg-target.h
-+++ b/tcg/i386/tcg-target.h
-@@ -XXX,XX +XXX,XX @@ static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_rx,
- #define TCG_TARGET_NEED_LDST_LABELS
- #endif
- #define TCG_TARGET_NEED_POOL_LABELS
--#define TCG_TARGET_CON_STR_H
- #endif
-diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h
-index XXXXXXX..XXXXXXX 100644
---- a/tcg/mips/tcg-target.h
-+++ b/tcg/mips/tcg-target.h
-@@ -XXX,XX +XXX,XX @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t);
- #ifdef CONFIG_SOFTMMU
- #define TCG_TARGET_NEED_LDST_LABELS
- #endif
--#define TCG_TARGET_CON_STR_H
- #endif
-diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h
-index XXXXXXX..XXXXXXX 100644
---- a/tcg/ppc/tcg-target.h
-+++ b/tcg/ppc/tcg-target.h
-@@ -XXX,XX +XXX,XX @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t);
- #define TCG_TARGET_NEED_LDST_LABELS
- #endif
- #define TCG_TARGET_NEED_POOL_LABELS
--#define TCG_TARGET_CON_STR_H
- #endif
-diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h
-index XXXXXXX..XXXXXXX 100644
---- a/tcg/riscv/tcg-target.h
-+++ b/tcg/riscv/tcg-target.h
-@@ -XXX,XX +XXX,XX @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t);
- #define TCG_TARGET_NEED_POOL_LABELS
- #define TCG_TARGET_HAS_MEMORY_BSWAP 0
--#define TCG_TARGET_CON_STR_H
- #endif
-diff --git a/tcg/s390/tcg-target.h b/tcg/s390/tcg-target.h
-index XXXXXXX..XXXXXXX 100644
---- a/tcg/s390/tcg-target.h
-+++ b/tcg/s390/tcg-target.h
-@@ -XXX,XX +XXX,XX @@ static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_rx,
- #define TCG_TARGET_NEED_LDST_LABELS
- #endif
- #define TCG_TARGET_NEED_POOL_LABELS
--#define TCG_TARGET_CON_STR_H
- #endif
-diff --git a/tcg/sparc/tcg-target.h b/tcg/sparc/tcg-target.h
-index XXXXXXX..XXXXXXX 100644
---- a/tcg/sparc/tcg-target.h
-+++ b/tcg/sparc/tcg-target.h
-@@ -XXX,XX +XXX,XX @@ extern bool use_vis3_instructions;
- void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t);
- #define TCG_TARGET_NEED_POOL_LABELS
--#define TCG_TARGET_CON_STR_H
- #endif
-diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h
-index XXXXXXX..XXXXXXX 100644
---- a/tcg/tci/tcg-target.h
-+++ b/tcg/tci/tcg-target.h
-@@ -XXX,XX +XXX,XX @@ static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_rx,
-     /* no need to flush icache explicitly */
- }
--#define TCG_TARGET_CON_STR_H
--
- #endif /* TCG_TARGET_H */
-diff --git a/tcg/tcg.c b/tcg/tcg.c
-index XXXXXXX..XXXXXXX 100644
---- a/tcg/tcg.c
-+++ b/tcg/tcg.c
-@@ -XXX,XX +XXX,XX @@ static void tcg_register_jit_int(const void *buf, size_t size,
-     __attribute__((unused));
- /* Forward declarations for functions declared and used in tcg-target.c.inc. */
--#ifndef TCG_TARGET_CON_STR_H
--static const char *target_parse_constraint(TCGArgConstraint *ct,
--                                           const char *ct_str, TCGType type);
--#endif
- static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg1,
-                        intptr_t arg2);
- static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg);
-@@ -XXX,XX +XXX,XX @@ static void process_op_defs(TCGContext *s)
-                     ct_str++;
-                     break;
--#ifdef TCG_TARGET_CON_STR_H
-                 /* Include all of the target-specific constraints. */
- #undef CONST
-@@ -XXX,XX +XXX,XX @@ static void process_op_defs(TCGContext *s)
-                 default:
-                     /* Typo in TCGTargetOpDef constraint. */
-                     g_assert_not_reached();
--#else
--                default:
--                    {
--                        TCGType type = (def->flags & TCG_OPF_64BIT
--                                        ? TCG_TYPE_I64 : TCG_TYPE_I32);
--                        ct_str = target_parse_constraint(&def->args_ct[i],
--                                                         ct_str, type);
--                        /* Typo in TCGTargetOpDef constraint. */
--                        tcg_debug_assert(ct_str != NULL);
--                    }
--#endif
-                 }
-             }
-         }
---
-.25.1

-[PULL 15/24] tcg/i386: Split out constraint sets to tcg-target-con-set.h
+Deleted patch
-This exports the constraint sets from tcg_target_op_def to
-a place we will be able to manipulate more in future.
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
----
- tcg/i386/tcg-target-con-set.h |  55 ++++++++++
- tcg/i386/tcg-target.h         |   1 +
- tcg/tcg.c                     | 119 +++++++++++++++++++++
- tcg/i386/tcg-target.c.inc     | 194 ++++++++++++----------------------
-files changed, 242 insertions(+), 127 deletions(-)
- create mode 100644 tcg/i386/tcg-target-con-set.h
-diff --git a/tcg/i386/tcg-target-con-set.h b/tcg/i386/tcg-target-con-set.h
-new file mode 100644
-index XXXXXXX..XXXXXXX
---- /dev/null
-+++ b/tcg/i386/tcg-target-con-set.h
-@@ -XXX,XX +XXX,XX @@
-+/* SPDX-License-Identifier: MIT */
-+/*
-+ * Define i386 target-specific constraint sets.
-+ * Copyright (c) 2021 Linaro
-+ */
-+
-+/*
-+ * C_On_Im(...) defines a constraint set with <n> outputs and <m> inputs.
-+ * Each operand should be a sequence of constraint letters as defined by
-+ * tcg-target-con-str.h; the constraint combination is inclusive or.
-+ *
-+ * C_N1_Im(...) defines a constraint set with 1 output and <m> inputs,
-+ * except that the output must use a new register.
-+ */
-+C_O0_I1(r)
-+C_O0_I2(L, L)
-+C_O0_I2(qi, r)
-+C_O0_I2(re, r)
-+C_O0_I2(ri, r)
-+C_O0_I2(r, re)
-+C_O0_I2(s, L)
-+C_O0_I2(x, r)
-+C_O0_I3(L, L, L)
-+C_O0_I3(s, L, L)
-+C_O0_I4(L, L, L, L)
-+C_O0_I4(r, r, ri, ri)
-+C_O1_I1(r, 0)
-+C_O1_I1(r, L)
-+C_O1_I1(r, q)
-+C_O1_I1(r, r)
-+C_O1_I1(x, r)
-+C_O1_I1(x, x)
-+C_O1_I2(Q, 0, Q)
-+C_O1_I2(q, r, re)
-+C_O1_I2(r, 0, ci)
-+C_O1_I2(r, 0, r)
-+C_O1_I2(r, 0, re)
-+C_O1_I2(r, 0, reZ)
-+C_O1_I2(r, 0, ri)
-+C_O1_I2(r, 0, rI)
-+C_O1_I2(r, L, L)
-+C_O1_I2(r, r, re)
-+C_O1_I2(r, r, ri)
-+C_O1_I2(r, r, rI)
-+C_O1_I2(x, x, x)
-+C_N1_I2(r, r, r)
-+C_N1_I2(r, r, rW)
-+C_O1_I3(x, x, x, x)
-+C_O1_I4(r, r, re, r, 0)
-+C_O1_I4(r, r, r, ri, ri)
-+C_O2_I1(r, r, L)
-+C_O2_I2(a, d, a, r)
-+C_O2_I2(r, r, L, L)
-+C_O2_I3(a, d, 0, 1, r)
-+C_O2_I4(r, r, 0, 1, re, re)
-diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h
-index XXXXXXX..XXXXXXX 100644
---- a/tcg/i386/tcg-target.h
-+++ b/tcg/i386/tcg-target.h
-@@ -XXX,XX +XXX,XX @@ static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_rx,
- #define TCG_TARGET_NEED_LDST_LABELS
- #endif
- #define TCG_TARGET_NEED_POOL_LABELS
-+#define TCG_TARGET_CON_SET_H
- #endif
-diff --git a/tcg/tcg.c b/tcg/tcg.c
-index XXXXXXX..XXXXXXX 100644
---- a/tcg/tcg.c
-+++ b/tcg/tcg.c
-@@ -XXX,XX +XXX,XX @@
- /* Forward declarations for functions declared in tcg-target.c.inc and
-    used here. */
- static void tcg_target_init(TCGContext *s);
-+#ifndef TCG_TARGET_CON_SET_H
- static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode);
-+#endif
- static void tcg_target_qemu_prologue(TCGContext *s);
- static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
-                         intptr_t value, intptr_t addend);
-@@ -XXX,XX +XXX,XX @@ static void set_jmp_reset_offset(TCGContext *s, int which)
-     s->tb_jmp_reset_offset[which] = tcg_current_code_size(s);
- }
-+#ifdef TCG_TARGET_CON_SET_H
-+#define C_PFX1(P, A)                    P##A
-+#define C_PFX2(P, A, B)                 P##A##_##B
-+#define C_PFX3(P, A, B, C)              P##A##_##B##_##C
-+#define C_PFX4(P, A, B, C, D)           P##A##_##B##_##C##_##D
-+#define C_PFX5(P, A, B, C, D, E)        P##A##_##B##_##C##_##D##_##E
-+#define C_PFX6(P, A, B, C, D, E, F)     P##A##_##B##_##C##_##D##_##E##_##F
-+
-+/* Define an enumeration for the various combinations. */
-+
-+#define C_O0_I1(I1)                     C_PFX1(c_o0_i1_, I1),
-+#define C_O0_I2(I1, I2)                 C_PFX2(c_o0_i2_, I1, I2),
-+#define C_O0_I3(I1, I2, I3)             C_PFX3(c_o0_i3_, I1, I2, I3),
-+#define C_O0_I4(I1, I2, I3, I4)         C_PFX4(c_o0_i4_, I1, I2, I3, I4),
-+
-+#define C_O1_I1(O1, I1)                 C_PFX2(c_o1_i1_, O1, I1),
-+#define C_O1_I2(O1, I1, I2)             C_PFX3(c_o1_i2_, O1, I1, I2),
-+#define C_O1_I3(O1, I1, I2, I3)         C_PFX4(c_o1_i3_, O1, I1, I2, I3),
-+#define C_O1_I4(O1, I1, I2, I3, I4)     C_PFX5(c_o1_i4_, O1, I1, I2, I3, I4),
-+
-+#define C_N1_I2(O1, I1, I2)             C_PFX3(c_n1_i2_, O1, I1, I2),
-+
-+#define C_O2_I1(O1, O2, I1)             C_PFX3(c_o2_i1_, O1, O2, I1),
-+#define C_O2_I2(O1, O2, I1, I2)         C_PFX4(c_o2_i2_, O1, O2, I1, I2),
-+#define C_O2_I3(O1, O2, I1, I2, I3)     C_PFX5(c_o2_i3_, O1, O2, I1, I2, I3),
-+#define C_O2_I4(O1, O2, I1, I2, I3, I4) C_PFX6(c_o2_i4_, O1, O2, I1, I2, I3, I4),
-+
-+typedef enum {
-+#include "tcg-target-con-set.h"
-+} TCGConstraintSetIndex;
-+
-+static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode);
-+
-+#undef C_O0_I1
-+#undef C_O0_I2
-+#undef C_O0_I3
-+#undef C_O0_I4
-+#undef C_O1_I1
-+#undef C_O1_I2
-+#undef C_O1_I3
-+#undef C_O1_I4
-+#undef C_N1_I2
-+#undef C_O2_I1
-+#undef C_O2_I2
-+#undef C_O2_I3
-+#undef C_O2_I4
-+
-+/* Put all of the constraint sets into an array, indexed by the enum. */
-+
-+#define C_O0_I1(I1)                     { .args_ct_str = { #I1 } },
-+#define C_O0_I2(I1, I2)                 { .args_ct_str = { #I1, #I2 } },
-+#define C_O0_I3(I1, I2, I3)             { .args_ct_str = { #I1, #I2, #I3 } },
-+#define C_O0_I4(I1, I2, I3, I4)         { .args_ct_str = { #I1, #I2, #I3, #I4 } },
-+
-+#define C_O1_I1(O1, I1)                 { .args_ct_str = { #O1, #I1 } },
-+#define C_O1_I2(O1, I1, I2)             { .args_ct_str = { #O1, #I1, #I2 } },
-+#define C_O1_I3(O1, I1, I2, I3)         { .args_ct_str = { #O1, #I1, #I2, #I3 } },
-+#define C_O1_I4(O1, I1, I2, I3, I4)     { .args_ct_str = { #O1, #I1, #I2, #I3, #I4 } },
-+
-+#define C_N1_I2(O1, I1, I2)             { .args_ct_str = { "&" #O1, #I1, #I2 } },
-+
-+#define C_O2_I1(O1, O2, I1)             { .args_ct_str = { #O1, #O2, #I1 } },
-+#define C_O2_I2(O1, O2, I1, I2)         { .args_ct_str = { #O1, #O2, #I1, #I2 } },
-+#define C_O2_I3(O1, O2, I1, I2, I3)     { .args_ct_str = { #O1, #O2, #I1, #I2, #I3 } },
-+#define C_O2_I4(O1, O2, I1, I2, I3, I4) { .args_ct_str = { #O1, #O2, #I1, #I2, #I3, #I4 } },
-+
-+static const TCGTargetOpDef constraint_sets[] = {
-+#include "tcg-target-con-set.h"
-+};
-+
-+
-+#undef C_O0_I1
-+#undef C_O0_I2
-+#undef C_O0_I3
-+#undef C_O0_I4
-+#undef C_O1_I1
-+#undef C_O1_I2
-+#undef C_O1_I3
-+#undef C_O1_I4
-+#undef C_N1_I2
-+#undef C_O2_I1
-+#undef C_O2_I2
-+#undef C_O2_I3
-+#undef C_O2_I4
-+
-+/* Expand the enumerator to be returned from tcg_target_op_def(). */
-+
-+#define C_O0_I1(I1)                     C_PFX1(c_o0_i1_, I1)
-+#define C_O0_I2(I1, I2)                 C_PFX2(c_o0_i2_, I1, I2)
-+#define C_O0_I3(I1, I2, I3)             C_PFX3(c_o0_i3_, I1, I2, I3)
-+#define C_O0_I4(I1, I2, I3, I4)         C_PFX4(c_o0_i4_, I1, I2, I3, I4)
-+
-+#define C_O1_I1(O1, I1)                 C_PFX2(c_o1_i1_, O1, I1)
-+#define C_O1_I2(O1, I1, I2)             C_PFX3(c_o1_i2_, O1, I1, I2)
-+#define C_O1_I3(O1, I1, I2, I3)         C_PFX4(c_o1_i3_, O1, I1, I2, I3)
-+#define C_O1_I4(O1, I1, I2, I3, I4)     C_PFX5(c_o1_i4_, O1, I1, I2, I3, I4)
-+
-+#define C_N1_I2(O1, I1, I2)             C_PFX3(c_n1_i2_, O1, I1, I2)
-+
-+#define C_O2_I1(O1, O2, I1)             C_PFX3(c_o2_i1_, O1, O2, I1)
-+#define C_O2_I2(O1, O2, I1, I2)         C_PFX4(c_o2_i2_, O1, O2, I1, I2)
-+#define C_O2_I3(O1, O2, I1, I2, I3)     C_PFX5(c_o2_i3_, O1, O2, I1, I2, I3)
-+#define C_O2_I4(O1, O2, I1, I2, I3, I4) C_PFX6(c_o2_i4_, O1, O2, I1, I2, I3, I4)
-+
-+#endif /* TCG_TARGET_CON_SET_H */
-+
- #include "tcg-target.c.inc"
- /* compare a pointer @ptr and a tb_tc @s */
-@@ -XXX,XX +XXX,XX @@ static void process_op_defs(TCGContext *s)
-             continue;
-         }
-+#ifdef TCG_TARGET_CON_SET_H
-+        /*
-+         * Macro magic should make it impossible, but double-check that
-+         * the array index is in range.  Since the signness of an enum
-+         * is implementation defined, force the result to unsigned.
-+         */
-+        unsigned con_set = tcg_target_op_def(op);
-+        tcg_debug_assert(con_set < ARRAY_SIZE(constraint_sets));
-+        tdefs = &constraint_sets[con_set];
-+#else
-         tdefs = tcg_target_op_def(op);
-         /* Missing TCGTargetOpDef entry. */
-         tcg_debug_assert(tdefs != NULL);
-+#endif
-         for (i = 0; i < nb_args; i++) {
-             const char *ct_str = tdefs->args_ct_str[i];
-diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
-index XXXXXXX..XXXXXXX 100644
---- a/tcg/i386/tcg-target.c.inc
-+++ b/tcg/i386/tcg-target.c.inc
-@@ -XXX,XX +XXX,XX @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
-     }
- }
--static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
-+static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
- {
--    static const TCGTargetOpDef r = { .args_ct_str = { "r" } };
--    static const TCGTargetOpDef ri_r = { .args_ct_str = { "ri", "r" } };
--    static const TCGTargetOpDef re_r = { .args_ct_str = { "re", "r" } };
--    static const TCGTargetOpDef qi_r = { .args_ct_str = { "qi", "r" } };
--    static const TCGTargetOpDef r_r = { .args_ct_str = { "r", "r" } };
--    static const TCGTargetOpDef r_q = { .args_ct_str = { "r", "q" } };
--    static const TCGTargetOpDef r_re = { .args_ct_str = { "r", "re" } };
--    static const TCGTargetOpDef r_0 = { .args_ct_str = { "r", "0" } };
--    static const TCGTargetOpDef r_r_ri = { .args_ct_str = { "r", "r", "ri" } };
--    static const TCGTargetOpDef r_r_re = { .args_ct_str = { "r", "r", "re" } };
--    static const TCGTargetOpDef r_0_r = { .args_ct_str = { "r", "0", "r" } };
--    static const TCGTargetOpDef r_0_re = { .args_ct_str = { "r", "0", "re" } };
--    static const TCGTargetOpDef r_0_ci = { .args_ct_str = { "r", "0", "ci" } };
--    static const TCGTargetOpDef r_L = { .args_ct_str = { "r", "L" } };
--    static const TCGTargetOpDef L_L = { .args_ct_str = { "L", "L" } };
--    static const TCGTargetOpDef s_L = { .args_ct_str = { "s", "L" } };
--    static const TCGTargetOpDef r_L_L = { .args_ct_str = { "r", "L", "L" } };
--    static const TCGTargetOpDef r_r_L = { .args_ct_str = { "r", "r", "L" } };
--    static const TCGTargetOpDef L_L_L = { .args_ct_str = { "L", "L", "L" } };
--    static const TCGTargetOpDef s_L_L = { .args_ct_str = { "s", "L", "L" } };
--    static const TCGTargetOpDef r_r_L_L
--        = { .args_ct_str = { "r", "r", "L", "L" } };
--    static const TCGTargetOpDef L_L_L_L
--        = { .args_ct_str = { "L", "L", "L", "L" } };
--    static const TCGTargetOpDef x_x = { .args_ct_str = { "x", "x" } };
--    static const TCGTargetOpDef x_x_x = { .args_ct_str = { "x", "x", "x" } };
--    static const TCGTargetOpDef x_x_x_x
--        = { .args_ct_str = { "x", "x", "x", "x" } };
--    static const TCGTargetOpDef x_r = { .args_ct_str = { "x", "r" } };
--
-     switch (op) {
-     case INDEX_op_goto_ptr:
--        return &r;
-+        return C_O0_I1(r);
-     case INDEX_op_ld8u_i32:
-     case INDEX_op_ld8u_i64:
-@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
-     case INDEX_op_ld32u_i64:
-     case INDEX_op_ld32s_i64:
-     case INDEX_op_ld_i64:
--        return &r_r;
-+        return C_O1_I1(r, r);
-     case INDEX_op_st8_i32:
-     case INDEX_op_st8_i64:
--        return &qi_r;
-+        return C_O0_I2(qi, r);
-+
-     case INDEX_op_st16_i32:
-     case INDEX_op_st16_i64:
-     case INDEX_op_st_i32:
-     case INDEX_op_st32_i64:
--        return &ri_r;
-+        return C_O0_I2(ri, r);
-+
-     case INDEX_op_st_i64:
--        return &re_r;
-+        return C_O0_I2(re, r);
-     case INDEX_op_add_i32:
-     case INDEX_op_add_i64:
--        return &r_r_re;
-+        return C_O1_I2(r, r, re);
-+
-     case INDEX_op_sub_i32:
-     case INDEX_op_sub_i64:
-     case INDEX_op_mul_i32:
-@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
-     case INDEX_op_or_i64:
-     case INDEX_op_xor_i32:
-     case INDEX_op_xor_i64:
--        return &r_0_re;
-+        return C_O1_I2(r, 0, re);
-     case INDEX_op_and_i32:
-     case INDEX_op_and_i64:
--        {
--            static const TCGTargetOpDef and
--                = { .args_ct_str = { "r", "0", "reZ" } };
--            return &and;
--        }
--        break;
-+        return C_O1_I2(r, 0, reZ);
-+
-     case INDEX_op_andc_i32:
-     case INDEX_op_andc_i64:
--        {
--            static const TCGTargetOpDef andc
--                = { .args_ct_str = { "r", "r", "rI" } };
--            return &andc;
--        }
--        break;
-+        return C_O1_I2(r, r, rI);
-     case INDEX_op_shl_i32:
-     case INDEX_op_shl_i64:
-@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
-     case INDEX_op_shr_i64:
-     case INDEX_op_sar_i32:
-     case INDEX_op_sar_i64:
--        return have_bmi2 ? &r_r_ri : &r_0_ci;
-+        return have_bmi2 ? C_O1_I2(r, r, ri) : C_O1_I2(r, 0, ci);
-+
-     case INDEX_op_rotl_i32:
-     case INDEX_op_rotl_i64:
-     case INDEX_op_rotr_i32:
-     case INDEX_op_rotr_i64:
--        return &r_0_ci;
-+        return C_O1_I2(r, 0, ci);
-     case INDEX_op_brcond_i32:
-     case INDEX_op_brcond_i64:
--        return &r_re;
-+        return C_O0_I2(r, re);
-     case INDEX_op_bswap16_i32:
-     case INDEX_op_bswap16_i64:
-@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
-     case INDEX_op_not_i32:
-     case INDEX_op_not_i64:
-     case INDEX_op_extrh_i64_i32:
--        return &r_0;
-+        return C_O1_I1(r, 0);
-     case INDEX_op_ext8s_i32:
-     case INDEX_op_ext8s_i64:
-     case INDEX_op_ext8u_i32:
-     case INDEX_op_ext8u_i64:
--        return &r_q;
-+        return C_O1_I1(r, q);
-+
-     case INDEX_op_ext16s_i32:
-     case INDEX_op_ext16s_i64:
-     case INDEX_op_ext16u_i32:
-@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
-     case INDEX_op_sextract_i32:
-     case INDEX_op_ctpop_i32:
-     case INDEX_op_ctpop_i64:
--        return &r_r;
-+        return C_O1_I1(r, r);
-+
-     case INDEX_op_extract2_i32:
-     case INDEX_op_extract2_i64:
--        return &r_0_r;
-+        return C_O1_I2(r, 0, r);
-     case INDEX_op_deposit_i32:
-     case INDEX_op_deposit_i64:
--        {
--            static const TCGTargetOpDef dep
--                = { .args_ct_str = { "Q", "0", "Q" } };
--            return &dep;
--        }
-+        return C_O1_I2(Q, 0, Q);
-+
-     case INDEX_op_setcond_i32:
-     case INDEX_op_setcond_i64:
--        {
--            static const TCGTargetOpDef setc
--                = { .args_ct_str = { "q", "r", "re" } };
--            return &setc;
--        }
-+        return C_O1_I2(q, r, re);
-+
-     case INDEX_op_movcond_i32:
-     case INDEX_op_movcond_i64:
--        {
--            static const TCGTargetOpDef movc
--                = { .args_ct_str = { "r", "r", "re", "r", "0" } };
--            return &movc;
--        }
-+        return C_O1_I4(r, r, re, r, 0);
-+
-     case INDEX_op_div2_i32:
-     case INDEX_op_div2_i64:
-     case INDEX_op_divu2_i32:
-     case INDEX_op_divu2_i64:
--        {
--            static const TCGTargetOpDef div2
--                = { .args_ct_str = { "a", "d", "0", "1", "r" } };
--            return &div2;
--        }
-+        return C_O2_I3(a, d, 0, 1, r);
-+
-     case INDEX_op_mulu2_i32:
-     case INDEX_op_mulu2_i64:
-     case INDEX_op_muls2_i32:
-     case INDEX_op_muls2_i64:
--        {
--            static const TCGTargetOpDef mul2
--                = { .args_ct_str = { "a", "d", "a", "r" } };
--            return &mul2;
--        }
-+        return C_O2_I2(a, d, a, r);
-+
-     case INDEX_op_add2_i32:
-     case INDEX_op_add2_i64:
-     case INDEX_op_sub2_i32:
-     case INDEX_op_sub2_i64:
--        {
--            static const TCGTargetOpDef arith2
--                = { .args_ct_str = { "r", "r", "0", "1", "re", "re" } };
--            return &arith2;
--        }
-+        return C_O2_I4(r, r, 0, 1, re, re);
-+
-     case INDEX_op_ctz_i32:
-     case INDEX_op_ctz_i64:
--        {
--            static const TCGTargetOpDef ctz[2] = {
--                { .args_ct_str = { "&r", "r", "r" } },
--                { .args_ct_str = { "&r", "r", "rW" } },
--            };
--            return &ctz[have_bmi1];
--        }
-+        return have_bmi1 ? C_N1_I2(r, r, rW) : C_N1_I2(r, r, r);
-+
-     case INDEX_op_clz_i32:
-     case INDEX_op_clz_i64:
--        {
--            static const TCGTargetOpDef clz[2] = {
--                { .args_ct_str = { "&r", "r", "r" } },
--                { .args_ct_str = { "&r", "r", "rW" } },
--            };
--            return &clz[have_lzcnt];
--        }
-+        return have_lzcnt ? C_N1_I2(r, r, rW) : C_N1_I2(r, r, r);
-     case INDEX_op_qemu_ld_i32:
--        return TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &r_L : &r_L_L;
-+        return (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS
-+                ? C_O1_I1(r, L) : C_O1_I2(r, L, L));
-+
-     case INDEX_op_qemu_st_i32:
--        return TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &L_L : &L_L_L;
-+        return (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS
-+                ? C_O0_I2(L, L) : C_O0_I3(L, L, L));
-     case INDEX_op_qemu_st8_i32:
--        return TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &s_L : &s_L_L;
-+        return (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS
-+                ? C_O0_I2(s, L) : C_O0_I3(s, L, L));
-+
-     case INDEX_op_qemu_ld_i64:
--        return (TCG_TARGET_REG_BITS == 64 ? &r_L
--                : TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &r_r_L
--                : &r_r_L_L);
-+        return (TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, L)
-+                : TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? C_O2_I1(r, r, L)
-+                : C_O2_I2(r, r, L, L));
-+
-     case INDEX_op_qemu_st_i64:
--        return (TCG_TARGET_REG_BITS == 64 ? &L_L
--                : TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &L_L_L
--                : &L_L_L_L);
-+        return (TCG_TARGET_REG_BITS == 64 ? C_O0_I2(L, L)
-+                : TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? C_O0_I3(L, L, L)
-+                : C_O0_I4(L, L, L, L));
-     case INDEX_op_brcond2_i32:
--        {
--            static const TCGTargetOpDef b2
--                = { .args_ct_str = { "r", "r", "ri", "ri" } };
--            return &b2;
--        }
-+        return C_O0_I4(r, r, ri, ri);
-+
-     case INDEX_op_setcond2_i32:
--        {
--            static const TCGTargetOpDef s2
--                = { .args_ct_str = { "r", "r", "r", "ri", "ri" } };
--            return &s2;
--        }
-+        return C_O1_I4(r, r, r, ri, ri);
-     case INDEX_op_ld_vec:
--    case INDEX_op_st_vec:
-     case INDEX_op_dupm_vec:
--        return &x_r;
-+        return C_O1_I1(x, r);
-+
-+    case INDEX_op_st_vec:
-+        return C_O0_I2(x, r);
-     case INDEX_op_add_vec:
-     case INDEX_op_sub_vec:
-@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
- #if TCG_TARGET_REG_BITS == 32
-     case INDEX_op_dup2_vec:
- #endif
--        return &x_x_x;
-+        return C_O1_I2(x, x, x);
-+
-     case INDEX_op_abs_vec:
-     case INDEX_op_dup_vec:
-     case INDEX_op_shli_vec:
-     case INDEX_op_shri_vec:
-     case INDEX_op_sari_vec:
-     case INDEX_op_x86_psrldq_vec:
--        return &x_x;
-+        return C_O1_I1(x, x);
-+
-     case INDEX_op_x86_vpblendvb_vec:
--        return &x_x_x_x;
-+        return C_O1_I3(x, x, x, x);
-     default:
--        break;
-+        g_assert_not_reached();
-     }
--    return NULL;
- }
- int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
---
-.25.1

-[PULL 16/24] tcg/aarch64: Split out constraint sets to tcg-target-con-set.h
+Deleted patch
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
----
- tcg/aarch64/tcg-target-con-set.h | 36 +++++++++++++
- tcg/aarch64/tcg-target.h         |  1 +
- tcg/aarch64/tcg-target.c.inc     | 86 +++++++++++---------------------
-files changed, 65 insertions(+), 58 deletions(-)
- create mode 100644 tcg/aarch64/tcg-target-con-set.h
-diff --git a/tcg/aarch64/tcg-target-con-set.h b/tcg/aarch64/tcg-target-con-set.h
-new file mode 100644
-index XXXXXXX..XXXXXXX
---- /dev/null
-+++ b/tcg/aarch64/tcg-target-con-set.h
-@@ -XXX,XX +XXX,XX @@
-+/* SPDX-License-Identifier: GPL-2.0-or-later */
-+/*
-+ * Define AArch64 target-specific constraint sets.
-+ * Copyright (c) 2021 Linaro
-+ */
-+
-+/*
-+ * C_On_Im(...) defines a constraint set with <n> outputs and <m> inputs.
-+ * Each operand should be a sequence of constraint letters as defined by
-+ * tcg-target-con-str.h; the constraint combination is inclusive or.
-+ */
-+C_O0_I1(r)
-+C_O0_I2(lZ, l)
-+C_O0_I2(r, rA)
-+C_O0_I2(rZ, r)
-+C_O0_I2(w, r)
-+C_O1_I1(r, l)
-+C_O1_I1(r, r)
-+C_O1_I1(w, r)
-+C_O1_I1(w, w)
-+C_O1_I1(w, wr)
-+C_O1_I2(r, 0, rZ)
-+C_O1_I2(r, r, r)
-+C_O1_I2(r, r, rA)
-+C_O1_I2(r, r, rAL)
-+C_O1_I2(r, r, ri)
-+C_O1_I2(r, r, rL)
-+C_O1_I2(r, rZ, rZ)
-+C_O1_I2(w, 0, w)
-+C_O1_I2(w, w, w)
-+C_O1_I2(w, w, wN)
-+C_O1_I2(w, w, wO)
-+C_O1_I2(w, w, wZ)
-+C_O1_I3(w, w, w, w)
-+C_O1_I4(r, r, rA, rZ, rZ)
-+C_O2_I4(r, r, rZ, rZ, rA, rMZ)
-diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h
-index XXXXXXX..XXXXXXX 100644
---- a/tcg/aarch64/tcg-target.h
-+++ b/tcg/aarch64/tcg-target.h
-@@ -XXX,XX +XXX,XX @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t);
- #define TCG_TARGET_NEED_LDST_LABELS
- #endif
- #define TCG_TARGET_NEED_POOL_LABELS
-+#define TCG_TARGET_CON_SET_H
- #endif /* AARCH64_TCG_TARGET_H */
-diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc
-index XXXXXXX..XXXXXXX 100644
---- a/tcg/aarch64/tcg-target.c.inc
-+++ b/tcg/aarch64/tcg-target.c.inc
-@@ -XXX,XX +XXX,XX @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece,
-     va_end(va);
- }
--static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
-+static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
- {
--    static const TCGTargetOpDef r = { .args_ct_str = { "r" } };
--    static const TCGTargetOpDef r_r = { .args_ct_str = { "r", "r" } };
--    static const TCGTargetOpDef w_w = { .args_ct_str = { "w", "w" } };
--    static const TCGTargetOpDef w_r = { .args_ct_str = { "w", "r" } };
--    static const TCGTargetOpDef w_wr = { .args_ct_str = { "w", "wr" } };
--    static const TCGTargetOpDef r_l = { .args_ct_str = { "r", "l" } };
--    static const TCGTargetOpDef r_rA = { .args_ct_str = { "r", "rA" } };
--    static const TCGTargetOpDef rZ_r = { .args_ct_str = { "rZ", "r" } };
--    static const TCGTargetOpDef lZ_l = { .args_ct_str = { "lZ", "l" } };
--    static const TCGTargetOpDef r_r_r = { .args_ct_str = { "r", "r", "r" } };
--    static const TCGTargetOpDef w_w_w = { .args_ct_str = { "w", "w", "w" } };
--    static const TCGTargetOpDef w_0_w = { .args_ct_str = { "w", "0", "w" } };
--    static const TCGTargetOpDef w_w_wO = { .args_ct_str = { "w", "w", "wO" } };
--    static const TCGTargetOpDef w_w_wN = { .args_ct_str = { "w", "w", "wN" } };
--    static const TCGTargetOpDef w_w_wZ = { .args_ct_str = { "w", "w", "wZ" } };
--    static const TCGTargetOpDef r_r_ri = { .args_ct_str = { "r", "r", "ri" } };
--    static const TCGTargetOpDef r_r_rA = { .args_ct_str = { "r", "r", "rA" } };
--    static const TCGTargetOpDef r_r_rL = { .args_ct_str = { "r", "r", "rL" } };
--    static const TCGTargetOpDef r_r_rAL
--        = { .args_ct_str = { "r", "r", "rAL" } };
--    static const TCGTargetOpDef dep
--        = { .args_ct_str = { "r", "0", "rZ" } };
--    static const TCGTargetOpDef ext2
--        = { .args_ct_str = { "r", "rZ", "rZ" } };
--    static const TCGTargetOpDef movc
--        = { .args_ct_str = { "r", "r", "rA", "rZ", "rZ" } };
--    static const TCGTargetOpDef add2
--        = { .args_ct_str = { "r", "r", "rZ", "rZ", "rA", "rMZ" } };
--    static const TCGTargetOpDef w_w_w_w
--        = { .args_ct_str = { "w", "w", "w", "w" } };
--
-     switch (op) {
-     case INDEX_op_goto_ptr:
--        return &r;
-+        return C_O0_I1(r);
-     case INDEX_op_ld8u_i32:
-     case INDEX_op_ld8s_i32:
-@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
-     case INDEX_op_extract_i64:
-     case INDEX_op_sextract_i32:
-     case INDEX_op_sextract_i64:
--        return &r_r;
-+        return C_O1_I1(r, r);
-     case INDEX_op_st8_i32:
-     case INDEX_op_st16_i32:
-@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
-     case INDEX_op_st16_i64:
-     case INDEX_op_st32_i64:
-     case INDEX_op_st_i64:
--        return &rZ_r;
-+        return C_O0_I2(rZ, r);
-     case INDEX_op_add_i32:
-     case INDEX_op_add_i64:
-@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
-     case INDEX_op_sub_i64:
-     case INDEX_op_setcond_i32:
-     case INDEX_op_setcond_i64:
--        return &r_r_rA;
-+        return C_O1_I2(r, r, rA);
-     case INDEX_op_mul_i32:
-     case INDEX_op_mul_i64:
-@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
-     case INDEX_op_remu_i64:
-     case INDEX_op_muluh_i64:
-     case INDEX_op_mulsh_i64:
--        return &r_r_r;
-+        return C_O1_I2(r, r, r);
-     case INDEX_op_and_i32:
-     case INDEX_op_and_i64:
-@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
-     case INDEX_op_orc_i64:
-     case INDEX_op_eqv_i32:
-     case INDEX_op_eqv_i64:
--        return &r_r_rL;
-+        return C_O1_I2(r, r, rL);
-     case INDEX_op_shl_i32:
-     case INDEX_op_shr_i32:
-@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
-     case INDEX_op_sar_i64:
-     case INDEX_op_rotl_i64:
-     case INDEX_op_rotr_i64:
--        return &r_r_ri;
-+        return C_O1_I2(r, r, ri);
-     case INDEX_op_clz_i32:
-     case INDEX_op_ctz_i32:
-     case INDEX_op_clz_i64:
-     case INDEX_op_ctz_i64:
--        return &r_r_rAL;
-+        return C_O1_I2(r, r, rAL);
-     case INDEX_op_brcond_i32:
-     case INDEX_op_brcond_i64:
--        return &r_rA;
-+        return C_O0_I2(r, rA);
-     case INDEX_op_movcond_i32:
-     case INDEX_op_movcond_i64:
--        return &movc;
-+        return C_O1_I4(r, r, rA, rZ, rZ);
-     case INDEX_op_qemu_ld_i32:
-     case INDEX_op_qemu_ld_i64:
--        return &r_l;
-+        return C_O1_I1(r, l);
-     case INDEX_op_qemu_st_i32:
-     case INDEX_op_qemu_st_i64:
--        return &lZ_l;
-+        return C_O0_I2(lZ, l);
-     case INDEX_op_deposit_i32:
-     case INDEX_op_deposit_i64:
--        return &dep;
-+        return C_O1_I2(r, 0, rZ);
-     case INDEX_op_extract2_i32:
-     case INDEX_op_extract2_i64:
--        return &ext2;
-+        return C_O1_I2(r, rZ, rZ);
-     case INDEX_op_add2_i32:
-     case INDEX_op_add2_i64:
-     case INDEX_op_sub2_i32:
-     case INDEX_op_sub2_i64:
--        return &add2;
-+        return C_O2_I4(r, r, rZ, rZ, rA, rMZ);
-     case INDEX_op_add_vec:
-     case INDEX_op_sub_vec:
-@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
-     case INDEX_op_shrv_vec:
-     case INDEX_op_sarv_vec:
-     case INDEX_op_aa64_sshl_vec:
--        return &w_w_w;
-+        return C_O1_I2(w, w, w);
-     case INDEX_op_not_vec:
-     case INDEX_op_neg_vec:
-     case INDEX_op_abs_vec:
-     case INDEX_op_shli_vec:
-     case INDEX_op_shri_vec:
-     case INDEX_op_sari_vec:
--        return &w_w;
-+        return C_O1_I1(w, w);
-     case INDEX_op_ld_vec:
--    case INDEX_op_st_vec:
-     case INDEX_op_dupm_vec:
--        return &w_r;
-+        return C_O1_I1(w, r);
-+    case INDEX_op_st_vec:
-+        return C_O0_I2(w, r);
-     case INDEX_op_dup_vec:
--        return &w_wr;
-+        return C_O1_I1(w, wr);
-     case INDEX_op_or_vec:
-     case INDEX_op_andc_vec:
--        return &w_w_wO;
-+        return C_O1_I2(w, w, wO);
-     case INDEX_op_and_vec:
-     case INDEX_op_orc_vec:
--        return &w_w_wN;
-+        return C_O1_I2(w, w, wN);
-     case INDEX_op_cmp_vec:
--        return &w_w_wZ;
-+        return C_O1_I2(w, w, wZ);
-     case INDEX_op_bitsel_vec:
--        return &w_w_w_w;
-+        return C_O1_I3(w, w, w, w);
-     case INDEX_op_aa64_sli_vec:
--        return &w_0_w;
-+        return C_O1_I2(w, 0, w);
-     default:
--        return NULL;
-+        g_assert_not_reached();
-     }
- }
---
-.25.1

-[PULL 17/24] tcg/arm: Split out constraint sets to tcg-target-con-set.h
+Deleted patch
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
----
- tcg/arm/tcg-target-con-set.h | 35 ++++++++++++++
- tcg/arm/tcg-target.h         |  1 +
- tcg/arm/tcg-target.c.inc     | 94 ++++++++++++------------------------
-files changed, 68 insertions(+), 62 deletions(-)
- create mode 100644 tcg/arm/tcg-target-con-set.h
-diff --git a/tcg/arm/tcg-target-con-set.h b/tcg/arm/tcg-target-con-set.h
-new file mode 100644
-index XXXXXXX..XXXXXXX
---- /dev/null
-+++ b/tcg/arm/tcg-target-con-set.h
-@@ -XXX,XX +XXX,XX @@
-+/* SPDX-License-Identifier: MIT */
-+/*
-+ * Define Arm target-specific constraint sets.
-+ * Copyright (c) 2021 Linaro
-+ */
-+
-+/*
-+ * C_On_Im(...) defines a constraint set with <n> outputs and <m> inputs.
-+ * Each operand should be a sequence of constraint letters as defined by
-+ * tcg-target-con-str.h; the constraint combination is inclusive or.
-+ */
-+C_O0_I1(r)
-+C_O0_I2(r, r)
-+C_O0_I2(r, rIN)
-+C_O0_I2(s, s)
-+C_O0_I3(s, s, s)
-+C_O0_I4(r, r, rI, rI)
-+C_O0_I4(s, s, s, s)
-+C_O1_I1(r, l)
-+C_O1_I1(r, r)
-+C_O1_I2(r, 0, rZ)
-+C_O1_I2(r, l, l)
-+C_O1_I2(r, r, r)
-+C_O1_I2(r, r, rI)
-+C_O1_I2(r, r, rIK)
-+C_O1_I2(r, r, rIN)
-+C_O1_I2(r, r, ri)
-+C_O1_I2(r, rZ, rZ)
-+C_O1_I4(r, r, r, rI, rI)
-+C_O1_I4(r, r, rIN, rIK, 0)
-+C_O2_I1(r, r, l)
-+C_O2_I2(r, r, l, l)
-+C_O2_I2(r, r, r, r)
-+C_O2_I4(r, r, r, r, rIN, rIK)
-+C_O2_I4(r, r, rI, rI, rIN, rIK)
-diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
-index XXXXXXX..XXXXXXX 100644
---- a/tcg/arm/tcg-target.h
-+++ b/tcg/arm/tcg-target.h
-@@ -XXX,XX +XXX,XX @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t);
- #define TCG_TARGET_NEED_LDST_LABELS
- #endif
- #define TCG_TARGET_NEED_POOL_LABELS
-+#define TCG_TARGET_CON_SET_H
- #endif
-diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
-index XXXXXXX..XXXXXXX 100644
---- a/tcg/arm/tcg-target.c.inc
-+++ b/tcg/arm/tcg-target.c.inc
-@@ -XXX,XX +XXX,XX @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
-     }
- }
--static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
-+static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
- {
--    static const TCGTargetOpDef r = { .args_ct_str = { "r" } };
--    static const TCGTargetOpDef r_r = { .args_ct_str = { "r", "r" } };
--    static const TCGTargetOpDef s_s = { .args_ct_str = { "s", "s" } };
--    static const TCGTargetOpDef r_l = { .args_ct_str = { "r", "l" } };
--    static const TCGTargetOpDef r_r_r = { .args_ct_str = { "r", "r", "r" } };
--    static const TCGTargetOpDef r_r_l = { .args_ct_str = { "r", "r", "l" } };
--    static const TCGTargetOpDef r_l_l = { .args_ct_str = { "r", "l", "l" } };
--    static const TCGTargetOpDef s_s_s = { .args_ct_str = { "s", "s", "s" } };
--    static const TCGTargetOpDef r_r_ri = { .args_ct_str = { "r", "r", "ri" } };
--    static const TCGTargetOpDef r_r_rI = { .args_ct_str = { "r", "r", "rI" } };
--    static const TCGTargetOpDef r_r_rIN
--        = { .args_ct_str = { "r", "r", "rIN" } };
--    static const TCGTargetOpDef r_r_rIK
--        = { .args_ct_str = { "r", "r", "rIK" } };
--    static const TCGTargetOpDef r_r_r_r
--        = { .args_ct_str = { "r", "r", "r", "r" } };
--    static const TCGTargetOpDef r_r_l_l
--        = { .args_ct_str = { "r", "r", "l", "l" } };
--    static const TCGTargetOpDef s_s_s_s
--        = { .args_ct_str = { "s", "s", "s", "s" } };
--    static const TCGTargetOpDef br
--        = { .args_ct_str = { "r", "rIN" } };
--    static const TCGTargetOpDef ext2
--        = { .args_ct_str = { "r", "rZ", "rZ" } };
--    static const TCGTargetOpDef dep
--        = { .args_ct_str = { "r", "0", "rZ" } };
--    static const TCGTargetOpDef movc
--        = { .args_ct_str = { "r", "r", "rIN", "rIK", "0" } };
--    static const TCGTargetOpDef add2
--        = { .args_ct_str = { "r", "r", "r", "r", "rIN", "rIK" } };
--    static const TCGTargetOpDef sub2
--        = { .args_ct_str = { "r", "r", "rI", "rI", "rIN", "rIK" } };
--    static const TCGTargetOpDef br2
--        = { .args_ct_str = { "r", "r", "rI", "rI" } };
--    static const TCGTargetOpDef setc2
--        = { .args_ct_str = { "r", "r", "r", "rI", "rI" } };
--
-     switch (op) {
-     case INDEX_op_goto_ptr:
--        return &r;
-+        return C_O0_I1(r);
-     case INDEX_op_ld8u_i32:
-     case INDEX_op_ld8s_i32:
-     case INDEX_op_ld16u_i32:
-     case INDEX_op_ld16s_i32:
-     case INDEX_op_ld_i32:
--    case INDEX_op_st8_i32:
--    case INDEX_op_st16_i32:
--    case INDEX_op_st_i32:
-     case INDEX_op_neg_i32:
-     case INDEX_op_not_i32:
-     case INDEX_op_bswap16_i32:
-@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
-     case INDEX_op_ext16u_i32:
-     case INDEX_op_extract_i32:
-     case INDEX_op_sextract_i32:
--        return &r_r;
-+        return C_O1_I1(r, r);
-+
-+    case INDEX_op_st8_i32:
-+    case INDEX_op_st16_i32:
-+    case INDEX_op_st_i32:
-+        return C_O0_I2(r, r);
-     case INDEX_op_add_i32:
-     case INDEX_op_sub_i32:
-     case INDEX_op_setcond_i32:
--        return &r_r_rIN;
-+        return C_O1_I2(r, r, rIN);
-+
-     case INDEX_op_and_i32:
-     case INDEX_op_andc_i32:
-     case INDEX_op_clz_i32:
-     case INDEX_op_ctz_i32:
--        return &r_r_rIK;
-+        return C_O1_I2(r, r, rIK);
-+
-     case INDEX_op_mul_i32:
-     case INDEX_op_div_i32:
-     case INDEX_op_divu_i32:
--        return &r_r_r;
-+        return C_O1_I2(r, r, r);
-+
-     case INDEX_op_mulu2_i32:
-     case INDEX_op_muls2_i32:
--        return &r_r_r_r;
-+        return C_O2_I2(r, r, r, r);
-+
-     case INDEX_op_or_i32:
-     case INDEX_op_xor_i32:
--        return &r_r_rI;
-+        return C_O1_I2(r, r, rI);
-+
-     case INDEX_op_shl_i32:
-     case INDEX_op_shr_i32:
-     case INDEX_op_sar_i32:
-     case INDEX_op_rotl_i32:
-     case INDEX_op_rotr_i32:
--        return &r_r_ri;
-+        return C_O1_I2(r, r, ri);
-     case INDEX_op_brcond_i32:
--        return &br;
-+        return C_O0_I2(r, rIN);
-     case INDEX_op_deposit_i32:
--        return &dep;
-+        return C_O1_I2(r, 0, rZ);
-     case INDEX_op_extract2_i32:
--        return &ext2;
-+        return C_O1_I2(r, rZ, rZ);
-     case INDEX_op_movcond_i32:
--        return &movc;
-+        return C_O1_I4(r, r, rIN, rIK, 0);
-     case INDEX_op_add2_i32:
--        return &add2;
-+        return C_O2_I4(r, r, r, r, rIN, rIK);
-     case INDEX_op_sub2_i32:
--        return &sub2;
-+        return C_O2_I4(r, r, rI, rI, rIN, rIK);
-     case INDEX_op_brcond2_i32:
--        return &br2;
-+        return C_O0_I4(r, r, rI, rI);
-     case INDEX_op_setcond2_i32:
--        return &setc2;
-+        return C_O1_I4(r, r, r, rI, rI);
-     case INDEX_op_qemu_ld_i32:
--        return TARGET_LONG_BITS == 32 ? &r_l : &r_l_l;
-+        return TARGET_LONG_BITS == 32 ? C_O1_I1(r, l) : C_O1_I2(r, l, l);
-     case INDEX_op_qemu_ld_i64:
--        return TARGET_LONG_BITS == 32 ? &r_r_l : &r_r_l_l;
-+        return TARGET_LONG_BITS == 32 ? C_O2_I1(r, r, l) : C_O2_I2(r, r, l, l);
-     case INDEX_op_qemu_st_i32:
--        return TARGET_LONG_BITS == 32 ? &s_s : &s_s_s;
-+        return TARGET_LONG_BITS == 32 ? C_O0_I2(s, s) : C_O0_I3(s, s, s);
-     case INDEX_op_qemu_st_i64:
--        return TARGET_LONG_BITS == 32 ? &s_s_s : &s_s_s_s;
-+        return TARGET_LONG_BITS == 32 ? C_O0_I3(s, s, s) : C_O0_I4(s, s, s, s);
-     default:
--        return NULL;
-+        g_assert_not_reached();
-     }
- }
---
-.25.1

-[PULL 18/24] tcg/mips: Split out constraint sets to tcg-target-con-set.h
+Deleted patch
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
----
- tcg/mips/tcg-target-con-set.h | 36 +++++++++++++
- tcg/mips/tcg-target.h         |  1 +
- tcg/mips/tcg-target.c.inc     | 96 +++++++++++------------------------
-files changed, 66 insertions(+), 67 deletions(-)
- create mode 100644 tcg/mips/tcg-target-con-set.h
-diff --git a/tcg/mips/tcg-target-con-set.h b/tcg/mips/tcg-target-con-set.h
-new file mode 100644
-index XXXXXXX..XXXXXXX
---- /dev/null
-+++ b/tcg/mips/tcg-target-con-set.h
-@@ -XXX,XX +XXX,XX @@
-+/* SPDX-License-Identifier: MIT */
-+/*
-+ * Define MIPS target-specific constraint sets.
-+ * Copyright (c) 2021 Linaro
-+ */
-+
-+/*
-+ * C_On_Im(...) defines a constraint set with <n> outputs and <m> inputs.
-+ * Each operand should be a sequence of constraint letters as defined by
-+ * tcg-target-con-str.h; the constraint combination is inclusive or.
-+ */
-+C_O0_I1(r)
-+C_O0_I2(rZ, r)
-+C_O0_I2(rZ, rZ)
-+C_O0_I2(SZ, S)
-+C_O0_I3(SZ, S, S)
-+C_O0_I3(SZ, SZ, S)
-+C_O0_I4(rZ, rZ, rZ, rZ)
-+C_O0_I4(SZ, SZ, S, S)
-+C_O1_I1(r, L)
-+C_O1_I1(r, r)
-+C_O1_I2(r, 0, rZ)
-+C_O1_I2(r, L, L)
-+C_O1_I2(r, r, ri)
-+C_O1_I2(r, r, rI)
-+C_O1_I2(r, r, rIK)
-+C_O1_I2(r, r, rJ)
-+C_O1_I2(r, r, rWZ)
-+C_O1_I2(r, rZ, rN)
-+C_O1_I2(r, rZ, rZ)
-+C_O1_I4(r, rZ, rZ, rZ, 0)
-+C_O1_I4(r, rZ, rZ, rZ, rZ)
-+C_O2_I1(r, r, L)
-+C_O2_I2(r, r, L, L)
-+C_O2_I2(r, r, r, r)
-+C_O2_I4(r, r, rZ, rZ, rN, rN)
-diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h
-index XXXXXXX..XXXXXXX 100644
---- a/tcg/mips/tcg-target.h
-+++ b/tcg/mips/tcg-target.h
-@@ -XXX,XX +XXX,XX @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t);
- #ifdef CONFIG_SOFTMMU
- #define TCG_TARGET_NEED_LDST_LABELS
- #endif
-+#define TCG_TARGET_CON_SET_H
- #endif
-diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc
-index XXXXXXX..XXXXXXX 100644
---- a/tcg/mips/tcg-target.c.inc
-+++ b/tcg/mips/tcg-target.c.inc
-@@ -XXX,XX +XXX,XX @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
-     }
- }
--static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
-+static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
- {
--    static const TCGTargetOpDef r = { .args_ct_str = { "r" } };
--    static const TCGTargetOpDef r_r = { .args_ct_str = { "r", "r" } };
--    static const TCGTargetOpDef r_L = { .args_ct_str = { "r", "L" } };
--    static const TCGTargetOpDef rZ_r = { .args_ct_str = { "rZ", "r" } };
--    static const TCGTargetOpDef SZ_S = { .args_ct_str = { "SZ", "S" } };
--    static const TCGTargetOpDef rZ_rZ = { .args_ct_str = { "rZ", "rZ" } };
--    static const TCGTargetOpDef r_r_L = { .args_ct_str = { "r", "r", "L" } };
--    static const TCGTargetOpDef r_L_L = { .args_ct_str = { "r", "L", "L" } };
--    static const TCGTargetOpDef r_r_ri = { .args_ct_str = { "r", "r", "ri" } };
--    static const TCGTargetOpDef r_r_rI = { .args_ct_str = { "r", "r", "rI" } };
--    static const TCGTargetOpDef r_r_rJ = { .args_ct_str = { "r", "r", "rJ" } };
--    static const TCGTargetOpDef SZ_S_S = { .args_ct_str = { "SZ", "S", "S" } };
--    static const TCGTargetOpDef SZ_SZ_S
--        = { .args_ct_str = { "SZ", "SZ", "S" } };
--    static const TCGTargetOpDef SZ_SZ_S_S
--        = { .args_ct_str = { "SZ", "SZ", "S", "S" } };
--    static const TCGTargetOpDef r_rZ_rN
--        = { .args_ct_str = { "r", "rZ", "rN" } };
--    static const TCGTargetOpDef r_rZ_rZ
--        = { .args_ct_str = { "r", "rZ", "rZ" } };
--    static const TCGTargetOpDef r_r_rIK
--        = { .args_ct_str = { "r", "r", "rIK" } };
--    static const TCGTargetOpDef r_r_rWZ
--        = { .args_ct_str = { "r", "r", "rWZ" } };
--    static const TCGTargetOpDef r_r_r_r
--        = { .args_ct_str = { "r", "r", "r", "r" } };
--    static const TCGTargetOpDef r_r_L_L
--        = { .args_ct_str = { "r", "r", "L", "L" } };
--    static const TCGTargetOpDef dep
--        = { .args_ct_str = { "r", "0", "rZ" } };
--    static const TCGTargetOpDef movc
--        = { .args_ct_str = { "r", "rZ", "rZ", "rZ", "0" } };
--    static const TCGTargetOpDef movc_r6
--        = { .args_ct_str = { "r", "rZ", "rZ", "rZ", "rZ" } };
--    static const TCGTargetOpDef add2
--        = { .args_ct_str = { "r", "r", "rZ", "rZ", "rN", "rN" } };
--    static const TCGTargetOpDef br2
--        = { .args_ct_str = { "rZ", "rZ", "rZ", "rZ" } };
--    static const TCGTargetOpDef setc2
--        = { .args_ct_str = { "r", "rZ", "rZ", "rZ", "rZ" } };
--
-     switch (op) {
-     case INDEX_op_goto_ptr:
--        return &r;
-+        return C_O0_I1(r);
-     case INDEX_op_ld8u_i32:
-     case INDEX_op_ld8s_i32:
-@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
-     case INDEX_op_extrl_i64_i32:
-     case INDEX_op_extrh_i64_i32:
-     case INDEX_op_extract_i64:
--        return &r_r;
-+        return C_O1_I1(r, r);
-     case INDEX_op_st8_i32:
-     case INDEX_op_st16_i32:
-@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
-     case INDEX_op_st16_i64:
-     case INDEX_op_st32_i64:
-     case INDEX_op_st_i64:
--        return &rZ_r;
-+        return C_O0_I2(rZ, r);
-     case INDEX_op_add_i32:
-     case INDEX_op_add_i64:
--        return &r_r_rJ;
-+        return C_O1_I2(r, r, rJ);
-     case INDEX_op_sub_i32:
-     case INDEX_op_sub_i64:
--        return &r_rZ_rN;
-+        return C_O1_I2(r, rZ, rN);
-     case INDEX_op_mul_i32:
-     case INDEX_op_mulsh_i32:
-     case INDEX_op_muluh_i32:
-@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
-     case INDEX_op_remu_i64:
-     case INDEX_op_nor_i64:
-     case INDEX_op_setcond_i64:
--        return &r_rZ_rZ;
-+        return C_O1_I2(r, rZ, rZ);
-     case INDEX_op_muls2_i32:
-     case INDEX_op_mulu2_i32:
-     case INDEX_op_muls2_i64:
-     case INDEX_op_mulu2_i64:
--        return &r_r_r_r;
-+        return C_O2_I2(r, r, r, r);
-     case INDEX_op_and_i32:
-     case INDEX_op_and_i64:
--        return &r_r_rIK;
-+        return C_O1_I2(r, r, rIK);
-     case INDEX_op_or_i32:
-     case INDEX_op_xor_i32:
-     case INDEX_op_or_i64:
-     case INDEX_op_xor_i64:
--        return &r_r_rI;
-+        return C_O1_I2(r, r, rI);
-     case INDEX_op_shl_i32:
-     case INDEX_op_shr_i32:
-     case INDEX_op_sar_i32:
-@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
-     case INDEX_op_sar_i64:
-     case INDEX_op_rotr_i64:
-     case INDEX_op_rotl_i64:
--        return &r_r_ri;
-+        return C_O1_I2(r, r, ri);
-     case INDEX_op_clz_i32:
-     case INDEX_op_clz_i64:
--        return &r_r_rWZ;
-+        return C_O1_I2(r, r, rWZ);
-     case INDEX_op_deposit_i32:
-     case INDEX_op_deposit_i64:
--        return &dep;
-+        return C_O1_I2(r, 0, rZ);
-     case INDEX_op_brcond_i32:
-     case INDEX_op_brcond_i64:
--        return &rZ_rZ;
-+        return C_O0_I2(rZ, rZ);
-     case INDEX_op_movcond_i32:
-     case INDEX_op_movcond_i64:
--        return use_mips32r6_instructions ? &movc_r6 : &movc;
--
-+        return (use_mips32r6_instructions
-+                ? C_O1_I4(r, rZ, rZ, rZ, rZ)
-+                : C_O1_I4(r, rZ, rZ, rZ, 0));
-     case INDEX_op_add2_i32:
-     case INDEX_op_sub2_i32:
--        return &add2;
-+        return C_O2_I4(r, r, rZ, rZ, rN, rN);
-     case INDEX_op_setcond2_i32:
--        return &setc2;
-+        return C_O1_I4(r, rZ, rZ, rZ, rZ);
-     case INDEX_op_brcond2_i32:
--        return &br2;
-+        return C_O0_I4(rZ, rZ, rZ, rZ);
-     case INDEX_op_qemu_ld_i32:
-         return (TCG_TARGET_REG_BITS == 64 || TARGET_LONG_BITS == 32
--                ? &r_L : &r_L_L);
-+                ? C_O1_I1(r, L) : C_O1_I2(r, L, L));
-     case INDEX_op_qemu_st_i32:
-         return (TCG_TARGET_REG_BITS == 64 || TARGET_LONG_BITS == 32
--                ? &SZ_S : &SZ_S_S);
-+                ? C_O0_I2(SZ, S) : C_O0_I3(SZ, S, S));
-     case INDEX_op_qemu_ld_i64:
--        return (TCG_TARGET_REG_BITS == 64 ? &r_L
--                : TARGET_LONG_BITS == 32 ? &r_r_L : &r_r_L_L);
-+        return (TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, L)
-+                : TARGET_LONG_BITS == 32 ? C_O2_I1(r, r, L)
-+                : C_O2_I2(r, r, L, L));
-     case INDEX_op_qemu_st_i64:
--        return (TCG_TARGET_REG_BITS == 64 ? &SZ_S
--                : TARGET_LONG_BITS == 32 ? &SZ_SZ_S : &SZ_SZ_S_S);
-+        return (TCG_TARGET_REG_BITS == 64 ? C_O0_I2(SZ, S)
-+                : TARGET_LONG_BITS == 32 ? C_O0_I3(SZ, SZ, S)
-+                : C_O0_I4(SZ, SZ, S, S));
-     default:
--        return NULL;
-+        g_assert_not_reached();
-     }
- }
---
-.25.1

-[PULL 19/24] tcg/ppc: Split out constraint sets to tcg-target-con-set.h
+Deleted patch
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
----
- tcg/ppc/tcg-target-con-set.h |  42 +++++++++++
- tcg/ppc/tcg-target.h         |   1 +
- tcg/ppc/tcg-target.c.inc     | 136 +++++++++++++++--------------------
-files changed, 99 insertions(+), 80 deletions(-)
- create mode 100644 tcg/ppc/tcg-target-con-set.h
-diff --git a/tcg/ppc/tcg-target-con-set.h b/tcg/ppc/tcg-target-con-set.h
-new file mode 100644
-index XXXXXXX..XXXXXXX
---- /dev/null
-+++ b/tcg/ppc/tcg-target-con-set.h
-@@ -XXX,XX +XXX,XX @@
-+/* SPDX-License-Identifier: MIT */
-+/*
-+ * Define PowerPC target-specific constraint sets.
-+ * Copyright (c) 2021 Linaro
-+ */
-+
-+/*
-+ * C_On_Im(...) defines a constraint set with <n> outputs and <m> inputs.
-+ * Each operand should be a sequence of constraint letters as defined by
-+ * tcg-target-con-str.h; the constraint combination is inclusive or.
-+ */
-+C_O0_I1(r)
-+C_O0_I2(r, r)
-+C_O0_I2(r, ri)
-+C_O0_I2(S, S)
-+C_O0_I2(v, r)
-+C_O0_I3(S, S, S)
-+C_O0_I4(r, r, ri, ri)
-+C_O0_I4(S, S, S, S)
-+C_O1_I1(r, L)
-+C_O1_I1(r, r)
-+C_O1_I1(v, r)
-+C_O1_I1(v, v)
-+C_O1_I1(v, vr)
-+C_O1_I2(r, 0, rZ)
-+C_O1_I2(r, L, L)
-+C_O1_I2(r, rI, ri)
-+C_O1_I2(r, rI, rT)
-+C_O1_I2(r, r, r)
-+C_O1_I2(r, r, ri)
-+C_O1_I2(r, r, rI)
-+C_O1_I2(r, r, rT)
-+C_O1_I2(r, r, rU)
-+C_O1_I2(r, r, rZW)
-+C_O1_I2(v, v, v)
-+C_O1_I3(v, v, v, v)
-+C_O1_I4(r, r, ri, rZ, rZ)
-+C_O1_I4(r, r, r, ri, ri)
-+C_O2_I1(L, L, L)
-+C_O2_I2(L, L, L, L)
-+C_O2_I4(r, r, rI, rZM, r, r)
-+C_O2_I4(r, r, r, r, rI, rZM)
-diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h
-index XXXXXXX..XXXXXXX 100644
---- a/tcg/ppc/tcg-target.h
-+++ b/tcg/ppc/tcg-target.h
-@@ -XXX,XX +XXX,XX @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t);
- #define TCG_TARGET_NEED_LDST_LABELS
- #endif
- #define TCG_TARGET_NEED_POOL_LABELS
-+#define TCG_TARGET_CON_SET_H
- #endif
-diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc
-index XXXXXXX..XXXXXXX 100644
---- a/tcg/ppc/tcg-target.c.inc
-+++ b/tcg/ppc/tcg-target.c.inc
-@@ -XXX,XX +XXX,XX @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece,
-     va_end(va);
- }
--static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
-+static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
- {
--    static const TCGTargetOpDef r = { .args_ct_str = { "r" } };
--    static const TCGTargetOpDef r_r = { .args_ct_str = { "r", "r" } };
--    static const TCGTargetOpDef r_L = { .args_ct_str = { "r", "L" } };
--    static const TCGTargetOpDef S_S = { .args_ct_str = { "S", "S" } };
--    static const TCGTargetOpDef r_ri = { .args_ct_str = { "r", "ri" } };
--    static const TCGTargetOpDef r_r_r = { .args_ct_str = { "r", "r", "r" } };
--    static const TCGTargetOpDef r_L_L = { .args_ct_str = { "r", "L", "L" } };
--    static const TCGTargetOpDef L_L_L = { .args_ct_str = { "L", "L", "L" } };
--    static const TCGTargetOpDef S_S_S = { .args_ct_str = { "S", "S", "S" } };
--    static const TCGTargetOpDef r_r_ri = { .args_ct_str = { "r", "r", "ri" } };
--    static const TCGTargetOpDef r_r_rI = { .args_ct_str = { "r", "r", "rI" } };
--    static const TCGTargetOpDef r_r_rT = { .args_ct_str = { "r", "r", "rT" } };
--    static const TCGTargetOpDef r_r_rU = { .args_ct_str = { "r", "r", "rU" } };
--    static const TCGTargetOpDef r_rI_ri
--        = { .args_ct_str = { "r", "rI", "ri" } };
--    static const TCGTargetOpDef r_rI_rT
--        = { .args_ct_str = { "r", "rI", "rT" } };
--    static const TCGTargetOpDef r_r_rZW
--        = { .args_ct_str = { "r", "r", "rZW" } };
--    static const TCGTargetOpDef L_L_L_L
--        = { .args_ct_str = { "L", "L", "L", "L" } };
--    static const TCGTargetOpDef S_S_S_S
--        = { .args_ct_str = { "S", "S", "S", "S" } };
--    static const TCGTargetOpDef movc
--        = { .args_ct_str = { "r", "r", "ri", "rZ", "rZ" } };
--    static const TCGTargetOpDef dep
--        = { .args_ct_str = { "r", "0", "rZ" } };
--    static const TCGTargetOpDef br2
--        = { .args_ct_str = { "r", "r", "ri", "ri" } };
--    static const TCGTargetOpDef setc2
--        = { .args_ct_str = { "r", "r", "r", "ri", "ri" } };
--    static const TCGTargetOpDef add2
--        = { .args_ct_str = { "r", "r", "r", "r", "rI", "rZM" } };
--    static const TCGTargetOpDef sub2
--        = { .args_ct_str = { "r", "r", "rI", "rZM", "r", "r" } };
--    static const TCGTargetOpDef v_r = { .args_ct_str = { "v", "r" } };
--    static const TCGTargetOpDef v_vr = { .args_ct_str = { "v", "vr" } };
--    static const TCGTargetOpDef v_v = { .args_ct_str = { "v", "v" } };
--    static const TCGTargetOpDef v_v_v = { .args_ct_str = { "v", "v", "v" } };
--    static const TCGTargetOpDef v_v_v_v
--        = { .args_ct_str = { "v", "v", "v", "v" } };
--
-     switch (op) {
-     case INDEX_op_goto_ptr:
--        return &r;
-+        return C_O0_I1(r);
-     case INDEX_op_ld8u_i32:
-     case INDEX_op_ld8s_i32:
-     case INDEX_op_ld16u_i32:
-     case INDEX_op_ld16s_i32:
-     case INDEX_op_ld_i32:
--    case INDEX_op_st8_i32:
--    case INDEX_op_st16_i32:
--    case INDEX_op_st_i32:
-     case INDEX_op_ctpop_i32:
-     case INDEX_op_neg_i32:
-     case INDEX_op_not_i32:
-@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
-     case INDEX_op_ld32u_i64:
-     case INDEX_op_ld32s_i64:
-     case INDEX_op_ld_i64:
--    case INDEX_op_st8_i64:
--    case INDEX_op_st16_i64:
--    case INDEX_op_st32_i64:
--    case INDEX_op_st_i64:
-     case INDEX_op_ctpop_i64:
-     case INDEX_op_neg_i64:
-     case INDEX_op_not_i64:
-@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
-     case INDEX_op_bswap32_i64:
-     case INDEX_op_bswap64_i64:
-     case INDEX_op_extract_i64:
--        return &r_r;
-+        return C_O1_I1(r, r);
-+
-+    case INDEX_op_st8_i32:
-+    case INDEX_op_st16_i32:
-+    case INDEX_op_st_i32:
-+    case INDEX_op_st8_i64:
-+    case INDEX_op_st16_i64:
-+    case INDEX_op_st32_i64:
-+    case INDEX_op_st_i64:
-+        return C_O0_I2(r, r);
-     case INDEX_op_add_i32:
-     case INDEX_op_and_i32:
-@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
-     case INDEX_op_rotl_i64:
-     case INDEX_op_rotr_i64:
-     case INDEX_op_setcond_i64:
--        return &r_r_ri;
-+        return C_O1_I2(r, r, ri);
-+
-     case INDEX_op_mul_i32:
-     case INDEX_op_mul_i64:
--        return &r_r_rI;
-+        return C_O1_I2(r, r, rI);
-+
-     case INDEX_op_div_i32:
-     case INDEX_op_divu_i32:
-     case INDEX_op_nand_i32:
-@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
-     case INDEX_op_divu_i64:
-     case INDEX_op_mulsh_i64:
-     case INDEX_op_muluh_i64:
--        return &r_r_r;
-+        return C_O1_I2(r, r, r);
-+
-     case INDEX_op_sub_i32:
--        return &r_rI_ri;
-+        return C_O1_I2(r, rI, ri);
-     case INDEX_op_add_i64:
--        return &r_r_rT;
-+        return C_O1_I2(r, r, rT);
-     case INDEX_op_or_i64:
-     case INDEX_op_xor_i64:
--        return &r_r_rU;
-+        return C_O1_I2(r, r, rU);
-     case INDEX_op_sub_i64:
--        return &r_rI_rT;
-+        return C_O1_I2(r, rI, rT);
-     case INDEX_op_clz_i32:
-     case INDEX_op_ctz_i32:
-     case INDEX_op_clz_i64:
-     case INDEX_op_ctz_i64:
--        return &r_r_rZW;
-+        return C_O1_I2(r, r, rZW);
-     case INDEX_op_brcond_i32:
-     case INDEX_op_brcond_i64:
--        return &r_ri;
-+        return C_O0_I2(r, ri);
-     case INDEX_op_movcond_i32:
-     case INDEX_op_movcond_i64:
--        return &movc;
-+        return C_O1_I4(r, r, ri, rZ, rZ);
-     case INDEX_op_deposit_i32:
-     case INDEX_op_deposit_i64:
--        return &dep;
-+        return C_O1_I2(r, 0, rZ);
-     case INDEX_op_brcond2_i32:
--        return &br2;
-+        return C_O0_I4(r, r, ri, ri);
-     case INDEX_op_setcond2_i32:
--        return &setc2;
-+        return C_O1_I4(r, r, r, ri, ri);
-     case INDEX_op_add2_i64:
-     case INDEX_op_add2_i32:
--        return &add2;
-+        return C_O2_I4(r, r, r, r, rI, rZM);
-     case INDEX_op_sub2_i64:
-     case INDEX_op_sub2_i32:
--        return &sub2;
-+        return C_O2_I4(r, r, rI, rZM, r, r);
-     case INDEX_op_qemu_ld_i32:
-         return (TCG_TARGET_REG_BITS == 64 || TARGET_LONG_BITS == 32
--                ? &r_L : &r_L_L);
-+                ? C_O1_I1(r, L)
-+                : C_O1_I2(r, L, L));
-+
-     case INDEX_op_qemu_st_i32:
-         return (TCG_TARGET_REG_BITS == 64 || TARGET_LONG_BITS == 32
--                ? &S_S : &S_S_S);
-+                ? C_O0_I2(S, S)
-+                : C_O0_I3(S, S, S));
-+
-     case INDEX_op_qemu_ld_i64:
--        return (TCG_TARGET_REG_BITS == 64 ? &r_L
--                : TARGET_LONG_BITS == 32 ? &L_L_L : &L_L_L_L);
-+        return (TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, L)
-+                : TARGET_LONG_BITS == 32 ? C_O2_I1(L, L, L)
-+                : C_O2_I2(L, L, L, L));
-+
-     case INDEX_op_qemu_st_i64:
--        return (TCG_TARGET_REG_BITS == 64 ? &S_S
--                : TARGET_LONG_BITS == 32 ? &S_S_S : &S_S_S_S);
-+        return (TCG_TARGET_REG_BITS == 64 ? C_O0_I2(S, S)
-+                : TARGET_LONG_BITS == 32 ? C_O0_I3(S, S, S)
-+                : C_O0_I4(S, S, S, S));
-     case INDEX_op_add_vec:
-     case INDEX_op_sub_vec:
-@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
-     case INDEX_op_ppc_mulou_vec:
-     case INDEX_op_ppc_pkum_vec:
-     case INDEX_op_dup2_vec:
--        return &v_v_v;
-+        return C_O1_I2(v, v, v);
-+
-     case INDEX_op_not_vec:
-     case INDEX_op_neg_vec:
--        return &v_v;
-+        return C_O1_I1(v, v);
-+
-     case INDEX_op_dup_vec:
--        return have_isa_3_00 ? &v_vr : &v_v;
-+        return have_isa_3_00 ? C_O1_I1(v, vr) : C_O1_I1(v, v);
-+
-     case INDEX_op_ld_vec:
--    case INDEX_op_st_vec:
-     case INDEX_op_dupm_vec:
--        return &v_r;
-+        return C_O1_I1(v, r);
-+
-+    case INDEX_op_st_vec:
-+        return C_O0_I2(v, r);
-+
-     case INDEX_op_bitsel_vec:
-     case INDEX_op_ppc_msum_vec:
--        return &v_v_v_v;
-+        return C_O1_I3(v, v, v, v);
-     default:
--        return NULL;
-+        g_assert_not_reached();
-     }
- }
---
-.25.1

-[PULL 20/24] tcg/riscv: Split out constraint sets to tcg-target-con-set.h
+Deleted patch
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
----
- tcg/riscv/tcg-target-con-set.h | 30 ++++++++++++
- tcg/riscv/tcg-target.h         |  1 +
- tcg/riscv/tcg-target.c.inc     | 83 ++++++++++------------------------
-files changed, 54 insertions(+), 60 deletions(-)
- create mode 100644 tcg/riscv/tcg-target-con-set.h
-diff --git a/tcg/riscv/tcg-target-con-set.h b/tcg/riscv/tcg-target-con-set.h
-new file mode 100644
-index XXXXXXX..XXXXXXX
---- /dev/null
-+++ b/tcg/riscv/tcg-target-con-set.h
-@@ -XXX,XX +XXX,XX @@
-+/* SPDX-License-Identifier: MIT */
-+/*
-+ * Define RISC-V target-specific constraint sets.
-+ * Copyright (c) 2021 Linaro
-+ */
-+
-+/*
-+ * C_On_Im(...) defines a constraint set with <n> outputs and <m> inputs.
-+ * Each operand should be a sequence of constraint letters as defined by
-+ * tcg-target-con-str.h; the constraint combination is inclusive or.
-+ */
-+C_O0_I1(r)
-+C_O0_I2(LZ, L)
-+C_O0_I2(rZ, r)
-+C_O0_I2(rZ, rZ)
-+C_O0_I3(LZ, L, L)
-+C_O0_I3(LZ, LZ, L)
-+C_O0_I4(LZ, LZ, L, L)
-+C_O0_I4(rZ, rZ, rZ, rZ)
-+C_O1_I1(r, L)
-+C_O1_I1(r, r)
-+C_O1_I2(r, L, L)
-+C_O1_I2(r, r, ri)
-+C_O1_I2(r, r, rI)
-+C_O1_I2(r, rZ, rN)
-+C_O1_I2(r, rZ, rZ)
-+C_O1_I4(r, rZ, rZ, rZ, rZ)
-+C_O2_I1(r, r, L)
-+C_O2_I2(r, r, L, L)
-+C_O2_I4(r, r, rZ, rZ, rM, rM)
-diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h
-index XXXXXXX..XXXXXXX 100644
---- a/tcg/riscv/tcg-target.h
-+++ b/tcg/riscv/tcg-target.h
-@@ -XXX,XX +XXX,XX @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t);
- #define TCG_TARGET_NEED_POOL_LABELS
- #define TCG_TARGET_HAS_MEMORY_BSWAP 0
-+#define TCG_TARGET_CON_SET_H
- #endif
-diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
-index XXXXXXX..XXXXXXX 100644
---- a/tcg/riscv/tcg-target.c.inc
-+++ b/tcg/riscv/tcg-target.c.inc
-@@ -XXX,XX +XXX,XX @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
-     }
- }
--static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
-+static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
- {
--    static const TCGTargetOpDef r
--        = { .args_ct_str = { "r" } };
--    static const TCGTargetOpDef r_r
--        = { .args_ct_str = { "r", "r" } };
--    static const TCGTargetOpDef rZ_r
--        = { .args_ct_str = { "rZ", "r" } };
--    static const TCGTargetOpDef rZ_rZ
--        = { .args_ct_str = { "rZ", "rZ" } };
--    static const TCGTargetOpDef rZ_rZ_rZ_rZ
--        = { .args_ct_str = { "rZ", "rZ", "rZ", "rZ" } };
--    static const TCGTargetOpDef r_r_ri
--        = { .args_ct_str = { "r", "r", "ri" } };
--    static const TCGTargetOpDef r_r_rI
--        = { .args_ct_str = { "r", "r", "rI" } };
--    static const TCGTargetOpDef r_rZ_rN
--        = { .args_ct_str = { "r", "rZ", "rN" } };
--    static const TCGTargetOpDef r_rZ_rZ
--        = { .args_ct_str = { "r", "rZ", "rZ" } };
--    static const TCGTargetOpDef r_rZ_rZ_rZ_rZ
--        = { .args_ct_str = { "r", "rZ", "rZ", "rZ", "rZ" } };
--    static const TCGTargetOpDef r_L
--        = { .args_ct_str = { "r", "L" } };
--    static const TCGTargetOpDef r_r_L
--        = { .args_ct_str = { "r", "r", "L" } };
--    static const TCGTargetOpDef r_L_L
--        = { .args_ct_str = { "r", "L", "L" } };
--    static const TCGTargetOpDef r_r_L_L
--        = { .args_ct_str = { "r", "r", "L", "L" } };
--    static const TCGTargetOpDef LZ_L
--        = { .args_ct_str = { "LZ", "L" } };
--    static const TCGTargetOpDef LZ_L_L
--        = { .args_ct_str = { "LZ", "L", "L" } };
--    static const TCGTargetOpDef LZ_LZ_L
--        = { .args_ct_str = { "LZ", "LZ", "L" } };
--    static const TCGTargetOpDef LZ_LZ_L_L
--        = { .args_ct_str = { "LZ", "LZ", "L", "L" } };
--    static const TCGTargetOpDef r_r_rZ_rZ_rM_rM
--        = { .args_ct_str = { "r", "r", "rZ", "rZ", "rM", "rM" } };
--
-     switch (op) {
-     case INDEX_op_goto_ptr:
--        return &r;
-+        return C_O0_I1(r);
-     case INDEX_op_ld8u_i32:
-     case INDEX_op_ld8s_i32:
-@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
-     case INDEX_op_extrl_i64_i32:
-     case INDEX_op_extrh_i64_i32:
-     case INDEX_op_ext_i32_i64:
--        return &r_r;
-+        return C_O1_I1(r, r);
-     case INDEX_op_st8_i32:
-     case INDEX_op_st16_i32:
-@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
-     case INDEX_op_st16_i64:
-     case INDEX_op_st32_i64:
-     case INDEX_op_st_i64:
--        return &rZ_r;
-+        return C_O0_I2(rZ, r);
-     case INDEX_op_add_i32:
-     case INDEX_op_and_i32:
-@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
-     case INDEX_op_and_i64:
-     case INDEX_op_or_i64:
-     case INDEX_op_xor_i64:
--        return &r_r_rI;
-+        return C_O1_I2(r, r, rI);
-     case INDEX_op_sub_i32:
-     case INDEX_op_sub_i64:
--        return &r_rZ_rN;
-+        return C_O1_I2(r, rZ, rN);
-     case INDEX_op_mul_i32:
-     case INDEX_op_mulsh_i32:
-@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
-     case INDEX_op_rem_i64:
-     case INDEX_op_remu_i64:
-     case INDEX_op_setcond_i64:
--        return &r_rZ_rZ;
-+        return C_O1_I2(r, rZ, rZ);
-     case INDEX_op_shl_i32:
-     case INDEX_op_shr_i32:
-@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
-     case INDEX_op_shl_i64:
-     case INDEX_op_shr_i64:
-     case INDEX_op_sar_i64:
--        return &r_r_ri;
-+        return C_O1_I2(r, r, ri);
-     case INDEX_op_brcond_i32:
-     case INDEX_op_brcond_i64:
--        return &rZ_rZ;
-+        return C_O0_I2(rZ, rZ);
-     case INDEX_op_add2_i32:
-     case INDEX_op_add2_i64:
-     case INDEX_op_sub2_i32:
-     case INDEX_op_sub2_i64:
--        return &r_r_rZ_rZ_rM_rM;
-+        return C_O2_I4(r, r, rZ, rZ, rM, rM);
-     case INDEX_op_brcond2_i32:
--        return &rZ_rZ_rZ_rZ;
-+        return C_O0_I4(rZ, rZ, rZ, rZ);
-     case INDEX_op_setcond2_i32:
--        return &r_rZ_rZ_rZ_rZ;
-+        return C_O1_I4(r, rZ, rZ, rZ, rZ);
-     case INDEX_op_qemu_ld_i32:
--        return TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &r_L : &r_L_L;
-+        return (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS
-+                ? C_O1_I1(r, L) : C_O1_I2(r, L, L));
-     case INDEX_op_qemu_st_i32:
--        return TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &LZ_L : &LZ_L_L;
-+        return (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS
-+                ? C_O0_I2(LZ, L) : C_O0_I3(LZ, L, L));
-     case INDEX_op_qemu_ld_i64:
--        return TCG_TARGET_REG_BITS == 64 ? &r_L
--               : TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &r_r_L
--               : &r_r_L_L;
-+        return (TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, L)
-+               : TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? C_O2_I1(r, r, L)
-+               : C_O2_I2(r, r, L, L));
-     case INDEX_op_qemu_st_i64:
--        return TCG_TARGET_REG_BITS == 64 ? &LZ_L
--               : TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &LZ_LZ_L
--               : &LZ_LZ_L_L;
-+        return (TCG_TARGET_REG_BITS == 64 ? C_O0_I2(LZ, L)
-+               : TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? C_O0_I3(LZ, LZ, L)
-+               : C_O0_I4(LZ, LZ, L, L));
-     default:
--        return NULL;
-+        g_assert_not_reached();
-     }
- }
---
-.25.1

-[PULL 21/24] tcg/s390: Split out constraint sets to tcg-target-con-set.h
+Deleted patch
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
----
- tcg/s390/tcg-target-con-set.h |  29 ++++++++
- tcg/s390/tcg-target.h         |   1 +
- tcg/s390/tcg-target.c.inc     | 121 ++++++++++++++--------------------
-files changed, 81 insertions(+), 70 deletions(-)
- create mode 100644 tcg/s390/tcg-target-con-set.h
-diff --git a/tcg/s390/tcg-target-con-set.h b/tcg/s390/tcg-target-con-set.h
-new file mode 100644
-index XXXXXXX..XXXXXXX
---- /dev/null
-+++ b/tcg/s390/tcg-target-con-set.h
-@@ -XXX,XX +XXX,XX @@
-+/* SPDX-License-Identifier: MIT */
-+/*
-+ * Define S390 target-specific constraint sets.
-+ * Copyright (c) 2021 Linaro
-+ */
-+
-+/*
-+ * C_On_Im(...) defines a constraint set with <n> outputs and <m> inputs.
-+ * Each operand should be a sequence of constraint letters as defined by
-+ * tcg-target-con-str.h; the constraint combination is inclusive or.
-+ */
-+C_O0_I1(r)
-+C_O0_I2(L, L)
-+C_O0_I2(r, r)
-+C_O0_I2(r, ri)
-+C_O1_I1(r, L)
-+C_O1_I1(r, r)
-+C_O1_I2(r, 0, ri)
-+C_O1_I2(r, 0, rI)
-+C_O1_I2(r, 0, rJ)
-+C_O1_I2(r, r, ri)
-+C_O1_I2(r, rZ, r)
-+C_O1_I4(r, r, ri, r, 0)
-+C_O1_I4(r, r, ri, rI, 0)
-+C_O2_I2(b, a, 0, r)
-+C_O2_I3(b, a, 0, 1, r)
-+C_O2_I4(r, r, 0, 1, rA, r)
-+C_O2_I4(r, r, 0, 1, ri, r)
-+C_O2_I4(r, r, 0, 1, r, r)
-diff --git a/tcg/s390/tcg-target.h b/tcg/s390/tcg-target.h
-index XXXXXXX..XXXXXXX 100644
---- a/tcg/s390/tcg-target.h
-+++ b/tcg/s390/tcg-target.h
-@@ -XXX,XX +XXX,XX @@ static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_rx,
- #define TCG_TARGET_NEED_LDST_LABELS
- #endif
- #define TCG_TARGET_NEED_POOL_LABELS
-+#define TCG_TARGET_CON_SET_H
- #endif
-diff --git a/tcg/s390/tcg-target.c.inc b/tcg/s390/tcg-target.c.inc
-index XXXXXXX..XXXXXXX 100644
---- a/tcg/s390/tcg-target.c.inc
-+++ b/tcg/s390/tcg-target.c.inc
-@@ -XXX,XX +XXX,XX @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
-     }
- }
--static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
-+static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
- {
--    static const TCGTargetOpDef r = { .args_ct_str = { "r" } };
--    static const TCGTargetOpDef r_r = { .args_ct_str = { "r", "r" } };
--    static const TCGTargetOpDef r_L = { .args_ct_str = { "r", "L" } };
--    static const TCGTargetOpDef L_L = { .args_ct_str = { "L", "L" } };
--    static const TCGTargetOpDef r_ri = { .args_ct_str = { "r", "ri" } };
--    static const TCGTargetOpDef r_r_ri = { .args_ct_str = { "r", "r", "ri" } };
--    static const TCGTargetOpDef r_0_ri = { .args_ct_str = { "r", "0", "ri" } };
--    static const TCGTargetOpDef r_0_rI = { .args_ct_str = { "r", "0", "rI" } };
--    static const TCGTargetOpDef r_0_rJ = { .args_ct_str = { "r", "0", "rJ" } };
--    static const TCGTargetOpDef a2_r
--        = { .args_ct_str = { "r", "r", "0", "1", "r", "r" } };
--    static const TCGTargetOpDef a2_ri
--        = { .args_ct_str = { "r", "r", "0", "1", "ri", "r" } };
--    static const TCGTargetOpDef a2_rA
--        = { .args_ct_str = { "r", "r", "0", "1", "rA", "r" } };
--
-     switch (op) {
-     case INDEX_op_goto_ptr:
--        return &r;
-+        return C_O0_I1(r);
-     case INDEX_op_ld8u_i32:
-     case INDEX_op_ld8u_i64:
-@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
-     case INDEX_op_ld32u_i64:
-     case INDEX_op_ld32s_i64:
-     case INDEX_op_ld_i64:
-+        return C_O1_I1(r, r);
-+
-     case INDEX_op_st8_i32:
-     case INDEX_op_st8_i64:
-     case INDEX_op_st16_i32:
-@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
-     case INDEX_op_st_i32:
-     case INDEX_op_st32_i64:
-     case INDEX_op_st_i64:
--        return &r_r;
-+        return C_O0_I2(r, r);
-     case INDEX_op_add_i32:
-     case INDEX_op_add_i64:
--        return &r_r_ri;
-+    case INDEX_op_shl_i64:
-+    case INDEX_op_shr_i64:
-+    case INDEX_op_sar_i64:
-+    case INDEX_op_rotl_i32:
-+    case INDEX_op_rotl_i64:
-+    case INDEX_op_rotr_i32:
-+    case INDEX_op_rotr_i64:
-+    case INDEX_op_clz_i64:
-+    case INDEX_op_setcond_i32:
-+    case INDEX_op_setcond_i64:
-+        return C_O1_I2(r, r, ri);
-+
-     case INDEX_op_sub_i32:
-     case INDEX_op_sub_i64:
-     case INDEX_op_and_i32:
-@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
-     case INDEX_op_or_i64:
-     case INDEX_op_xor_i32:
-     case INDEX_op_xor_i64:
--        return (s390_facilities & FACILITY_DISTINCT_OPS ? &r_r_ri : &r_0_ri);
-+        return (s390_facilities & FACILITY_DISTINCT_OPS
-+                ? C_O1_I2(r, r, ri)
-+                : C_O1_I2(r, 0, ri));
-     case INDEX_op_mul_i32:
-         /* If we have the general-instruction-extensions, then we have
-            MULTIPLY SINGLE IMMEDIATE with a signed 32-bit, otherwise we
-            have only MULTIPLY HALFWORD IMMEDIATE, with a signed 16-bit.  */
--        return (s390_facilities & FACILITY_GEN_INST_EXT ? &r_0_ri : &r_0_rI);
-+        return (s390_facilities & FACILITY_GEN_INST_EXT
-+                ? C_O1_I2(r, 0, ri)
-+                : C_O1_I2(r, 0, rI));
-+
-     case INDEX_op_mul_i64:
--        return (s390_facilities & FACILITY_GEN_INST_EXT ? &r_0_rJ : &r_0_rI);
-+        return (s390_facilities & FACILITY_GEN_INST_EXT
-+                ? C_O1_I2(r, 0, rJ)
-+                : C_O1_I2(r, 0, rI));
-     case INDEX_op_shl_i32:
-     case INDEX_op_shr_i32:
-     case INDEX_op_sar_i32:
--        return (s390_facilities & FACILITY_DISTINCT_OPS ? &r_r_ri : &r_0_ri);
--
--    case INDEX_op_shl_i64:
--    case INDEX_op_shr_i64:
--    case INDEX_op_sar_i64:
--        return &r_r_ri;
--
--    case INDEX_op_rotl_i32:
--    case INDEX_op_rotl_i64:
--    case INDEX_op_rotr_i32:
--    case INDEX_op_rotr_i64:
--        return &r_r_ri;
-+        return (s390_facilities & FACILITY_DISTINCT_OPS
-+                ? C_O1_I2(r, r, ri)
-+                : C_O1_I2(r, 0, ri));
-     case INDEX_op_brcond_i32:
-     case INDEX_op_brcond_i64:
--        return &r_ri;
-+        return C_O0_I2(r, ri);
-     case INDEX_op_bswap16_i32:
-     case INDEX_op_bswap16_i64:
-@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
-     case INDEX_op_extu_i32_i64:
-     case INDEX_op_extract_i32:
-     case INDEX_op_extract_i64:
--        return &r_r;
--
--    case INDEX_op_clz_i64:
--    case INDEX_op_setcond_i32:
--    case INDEX_op_setcond_i64:
--        return &r_r_ri;
-+        return C_O1_I1(r, r);
-     case INDEX_op_qemu_ld_i32:
-     case INDEX_op_qemu_ld_i64:
--        return &r_L;
-+        return C_O1_I1(r, L);
-     case INDEX_op_qemu_st_i64:
-     case INDEX_op_qemu_st_i32:
--        return &L_L;
-+        return C_O0_I2(L, L);
-     case INDEX_op_deposit_i32:
-     case INDEX_op_deposit_i64:
--        {
--            static const TCGTargetOpDef dep
--                = { .args_ct_str = { "r", "rZ", "r" } };
--            return &dep;
--        }
-+        return C_O1_I2(r, rZ, r);
-+
-     case INDEX_op_movcond_i32:
-     case INDEX_op_movcond_i64:
--        {
--            static const TCGTargetOpDef movc
--                = { .args_ct_str = { "r", "r", "ri", "r", "0" } };
--            static const TCGTargetOpDef movc_l
--                = { .args_ct_str = { "r", "r", "ri", "rI", "0" } };
--            return (s390_facilities & FACILITY_LOAD_ON_COND2 ? &movc_l : &movc);
--        }
-+        return (s390_facilities & FACILITY_LOAD_ON_COND2
-+                ? C_O1_I4(r, r, ri, rI, 0)
-+                : C_O1_I4(r, r, ri, r, 0));
-+
-     case INDEX_op_div2_i32:
-     case INDEX_op_div2_i64:
-     case INDEX_op_divu2_i32:
-     case INDEX_op_divu2_i64:
--        {
--            static const TCGTargetOpDef div2
--                = { .args_ct_str = { "b", "a", "0", "1", "r" } };
--            return &div2;
--        }
-+        return C_O2_I3(b, a, 0, 1, r);
-+
-     case INDEX_op_mulu2_i64:
--        {
--            static const TCGTargetOpDef mul2
--                = { .args_ct_str = { "b", "a", "0", "r" } };
--            return &mul2;
--        }
-+        return C_O2_I2(b, a, 0, r);
-     case INDEX_op_add2_i32:
-     case INDEX_op_sub2_i32:
--        return (s390_facilities & FACILITY_EXT_IMM ? &a2_ri : &a2_r);
-+        return (s390_facilities & FACILITY_EXT_IMM
-+                ? C_O2_I4(r, r, 0, 1, ri, r)
-+                : C_O2_I4(r, r, 0, 1, r, r));
-+
-     case INDEX_op_add2_i64:
-     case INDEX_op_sub2_i64:
--        return (s390_facilities & FACILITY_EXT_IMM ? &a2_rA : &a2_r);
-+        return (s390_facilities & FACILITY_EXT_IMM
-+                ? C_O2_I4(r, r, 0, 1, rA, r)
-+                : C_O2_I4(r, r, 0, 1, r, r));
-     default:
--        break;
-+        g_assert_not_reached();
-     }
--    return NULL;
- }
- static void query_s390_facilities(void)
---
-.25.1

-[PULL 22/24] tcg/sparc: Split out constraint sets to tcg-target-con-set.h
+Deleted patch
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
----
- tcg/sparc/tcg-target-con-set.h | 32 +++++++++++++++
- tcg/sparc/tcg-target.h         |  1 +
- tcg/sparc/tcg-target.c.inc     | 75 +++++++++++-----------------------
-files changed, 56 insertions(+), 52 deletions(-)
- create mode 100644 tcg/sparc/tcg-target-con-set.h
-diff --git a/tcg/sparc/tcg-target-con-set.h b/tcg/sparc/tcg-target-con-set.h
-new file mode 100644
-index XXXXXXX..XXXXXXX
---- /dev/null
-+++ b/tcg/sparc/tcg-target-con-set.h
-@@ -XXX,XX +XXX,XX @@
-+/* SPDX-License-Identifier: MIT */
-+/*
-+ * Define Sparc target-specific constraint sets.
-+ * Copyright (c) 2021 Linaro
-+ */
-+
-+/*
-+ * C_On_Im(...) defines a constraint set with <n> outputs and <m> inputs.
-+ * Each operand should be a sequence of constraint letters as defined by
-+ * tcg-target-con-str.h; the constraint combination is inclusive or.
-+ */
-+C_O0_I1(r)
-+C_O0_I2(rZ, r)
-+C_O0_I2(RZ, r)
-+C_O0_I2(rZ, rJ)
-+C_O0_I2(RZ, RJ)
-+C_O0_I2(sZ, A)
-+C_O0_I2(SZ, A)
-+C_O1_I1(r, A)
-+C_O1_I1(R, A)
-+C_O1_I1(r, r)
-+C_O1_I1(r, R)
-+C_O1_I1(R, r)
-+C_O1_I1(R, R)
-+C_O1_I2(R, R, R)
-+C_O1_I2(r, rZ, rJ)
-+C_O1_I2(R, RZ, RJ)
-+C_O1_I4(r, rZ, rJ, rI, 0)
-+C_O1_I4(R, RZ, RJ, RI, 0)
-+C_O2_I2(r, r, rZ, rJ)
-+C_O2_I4(R, R, RZ, RZ, RJ, RI)
-+C_O2_I4(r, r, rZ, rZ, rJ, rJ)
-diff --git a/tcg/sparc/tcg-target.h b/tcg/sparc/tcg-target.h
-index XXXXXXX..XXXXXXX 100644
---- a/tcg/sparc/tcg-target.h
-+++ b/tcg/sparc/tcg-target.h
-@@ -XXX,XX +XXX,XX @@ extern bool use_vis3_instructions;
- void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t);
- #define TCG_TARGET_NEED_POOL_LABELS
-+#define TCG_TARGET_CON_SET_H
- #endif
-diff --git a/tcg/sparc/tcg-target.c.inc b/tcg/sparc/tcg-target.c.inc
-index XXXXXXX..XXXXXXX 100644
---- a/tcg/sparc/tcg-target.c.inc
-+++ b/tcg/sparc/tcg-target.c.inc
-@@ -XXX,XX +XXX,XX @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
-     }
- }
--static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
-+static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
- {
--    static const TCGTargetOpDef r = { .args_ct_str = { "r" } };
--    static const TCGTargetOpDef r_r = { .args_ct_str = { "r", "r" } };
--    static const TCGTargetOpDef R_r = { .args_ct_str = { "R", "r" } };
--    static const TCGTargetOpDef r_R = { .args_ct_str = { "r", "R" } };
--    static const TCGTargetOpDef R_R = { .args_ct_str = { "R", "R" } };
--    static const TCGTargetOpDef r_A = { .args_ct_str = { "r", "A" } };
--    static const TCGTargetOpDef R_A = { .args_ct_str = { "R", "A" } };
--    static const TCGTargetOpDef rZ_r = { .args_ct_str = { "rZ", "r" } };
--    static const TCGTargetOpDef RZ_r = { .args_ct_str = { "RZ", "r" } };
--    static const TCGTargetOpDef sZ_A = { .args_ct_str = { "sZ", "A" } };
--    static const TCGTargetOpDef SZ_A = { .args_ct_str = { "SZ", "A" } };
--    static const TCGTargetOpDef rZ_rJ = { .args_ct_str = { "rZ", "rJ" } };
--    static const TCGTargetOpDef RZ_RJ = { .args_ct_str = { "RZ", "RJ" } };
--    static const TCGTargetOpDef R_R_R = { .args_ct_str = { "R", "R", "R" } };
--    static const TCGTargetOpDef r_rZ_rJ
--        = { .args_ct_str = { "r", "rZ", "rJ" } };
--    static const TCGTargetOpDef R_RZ_RJ
--        = { .args_ct_str = { "R", "RZ", "RJ" } };
--    static const TCGTargetOpDef r_r_rZ_rJ
--        = { .args_ct_str = { "r", "r", "rZ", "rJ" } };
--    static const TCGTargetOpDef movc_32
--        = { .args_ct_str = { "r", "rZ", "rJ", "rI", "0" } };
--    static const TCGTargetOpDef movc_64
--        = { .args_ct_str = { "R", "RZ", "RJ", "RI", "0" } };
--    static const TCGTargetOpDef add2_32
--        = { .args_ct_str = { "r", "r", "rZ", "rZ", "rJ", "rJ" } };
--    static const TCGTargetOpDef add2_64
--        = { .args_ct_str = { "R", "R", "RZ", "RZ", "RJ", "RI" } };
--
-     switch (op) {
-     case INDEX_op_goto_ptr:
--        return &r;
-+        return C_O0_I1(r);
-     case INDEX_op_ld8u_i32:
-     case INDEX_op_ld8s_i32:
-@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
-     case INDEX_op_ld_i32:
-     case INDEX_op_neg_i32:
-     case INDEX_op_not_i32:
--        return &r_r;
-+        return C_O1_I1(r, r);
-     case INDEX_op_st8_i32:
-     case INDEX_op_st16_i32:
-     case INDEX_op_st_i32:
--        return &rZ_r;
-+        return C_O0_I2(rZ, r);
-     case INDEX_op_add_i32:
-     case INDEX_op_mul_i32:
-@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
-     case INDEX_op_shr_i32:
-     case INDEX_op_sar_i32:
-     case INDEX_op_setcond_i32:
--        return &r_rZ_rJ;
-+        return C_O1_I2(r, rZ, rJ);
-     case INDEX_op_brcond_i32:
--        return &rZ_rJ;
-+        return C_O0_I2(rZ, rJ);
-     case INDEX_op_movcond_i32:
--        return &movc_32;
-+        return C_O1_I4(r, rZ, rJ, rI, 0);
-     case INDEX_op_add2_i32:
-     case INDEX_op_sub2_i32:
--        return &add2_32;
-+        return C_O2_I4(r, r, rZ, rZ, rJ, rJ);
-     case INDEX_op_mulu2_i32:
-     case INDEX_op_muls2_i32:
--        return &r_r_rZ_rJ;
-+        return C_O2_I2(r, r, rZ, rJ);
-     case INDEX_op_ld8u_i64:
-     case INDEX_op_ld8s_i64:
-@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
-     case INDEX_op_ld_i64:
-     case INDEX_op_ext_i32_i64:
-     case INDEX_op_extu_i32_i64:
--        return &R_r;
-+        return C_O1_I1(R, r);
-     case INDEX_op_st8_i64:
-     case INDEX_op_st16_i64:
-     case INDEX_op_st32_i64:
-     case INDEX_op_st_i64:
--        return &RZ_r;
-+        return C_O0_I2(RZ, r);
-     case INDEX_op_add_i64:
-     case INDEX_op_mul_i64:
-@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
-     case INDEX_op_shr_i64:
-     case INDEX_op_sar_i64:
-     case INDEX_op_setcond_i64:
--        return &R_RZ_RJ;
-+        return C_O1_I2(R, RZ, RJ);
-     case INDEX_op_neg_i64:
-     case INDEX_op_not_i64:
-     case INDEX_op_ext32s_i64:
-     case INDEX_op_ext32u_i64:
--        return &R_R;
-+        return C_O1_I1(R, R);
-     case INDEX_op_extrl_i64_i32:
-     case INDEX_op_extrh_i64_i32:
--        return &r_R;
-+        return C_O1_I1(r, R);
-     case INDEX_op_brcond_i64:
--        return &RZ_RJ;
-+        return C_O0_I2(RZ, RJ);
-     case INDEX_op_movcond_i64:
--        return &movc_64;
-+        return C_O1_I4(R, RZ, RJ, RI, 0);
-     case INDEX_op_add2_i64:
-     case INDEX_op_sub2_i64:
--        return &add2_64;
-+        return C_O2_I4(R, R, RZ, RZ, RJ, RI);
-     case INDEX_op_muluh_i64:
--        return &R_R_R;
-+        return C_O1_I2(R, R, R);
-     case INDEX_op_qemu_ld_i32:
--        return &r_A;
-+        return C_O1_I1(r, A);
-     case INDEX_op_qemu_ld_i64:
--        return &R_A;
-+        return C_O1_I1(R, A);
-     case INDEX_op_qemu_st_i32:
--        return &sZ_A;
-+        return C_O0_I2(sZ, A);
-     case INDEX_op_qemu_st_i64:
--        return &SZ_A;
-+        return C_O0_I2(SZ, A);
-     default:
--        return NULL;
-+        g_assert_not_reached();
-     }
- }
---
-.25.1

-[PULL 23/24] tcg/tci: Split out constraint sets to tcg-target-con-set.h
+Deleted patch
-This requires finishing the conversion to tcg_target_op_def.
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
----
- tcg/tci/tcg-target-con-set.h |  25 ++++
- tcg/tci/tcg-target.h         |   2 +
- tcg/tci/tcg-target.c.inc     | 279 +++++++++++++++++------------------
-files changed, 161 insertions(+), 145 deletions(-)
- create mode 100644 tcg/tci/tcg-target-con-set.h
-diff --git a/tcg/tci/tcg-target-con-set.h b/tcg/tci/tcg-target-con-set.h
-new file mode 100644
-index XXXXXXX..XXXXXXX
---- /dev/null
-+++ b/tcg/tci/tcg-target-con-set.h
-@@ -XXX,XX +XXX,XX @@
-+/* SPDX-License-Identifier: MIT */
-+/*
-+ * TCI target-specific constraint sets.
-+ * Copyright (c) 2021 Linaro
-+ */
-+
-+/*
-+ * C_On_Im(...) defines a constraint set with <n> outputs and <m> inputs.
-+ * Each operand should be a sequence of constraint letters as defined by
-+ * tcg-target-con-str.h; the constraint combination is inclusive or.
-+ */
-+C_O0_I2(r, r)
-+C_O0_I2(r, ri)
-+C_O0_I3(r, r, r)
-+C_O0_I4(r, r, ri, ri)
-+C_O0_I4(r, r, r, r)
-+C_O1_I1(r, r)
-+C_O1_I2(r, 0, r)
-+C_O1_I2(r, ri, ri)
-+C_O1_I2(r, r, r)
-+C_O1_I2(r, r, ri)
-+C_O1_I4(r, r, r, ri, ri)
-+C_O2_I1(r, r, r)
-+C_O2_I2(r, r, r, r)
-+C_O2_I4(r, r, r, r, r, r)
-diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h
-index XXXXXXX..XXXXXXX 100644
---- a/tcg/tci/tcg-target.h
-+++ b/tcg/tci/tcg-target.h
-@@ -XXX,XX +XXX,XX @@ static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_rx,
-     /* no need to flush icache explicitly */
- }
-+#define TCG_TARGET_CON_SET_H
-+
- #endif /* TCG_TARGET_H */
-diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
-index XXXXXXX..XXXXXXX 100644
---- a/tcg/tci/tcg-target.c.inc
-+++ b/tcg/tci/tcg-target.c.inc
-@@ -XXX,XX +XXX,XX @@
- /* Bitfield n...m (in 32 bit value). */
- #define BITS(n, m) (((0xffffffffU << (31 - n)) >> (31 - n + m)) << m)
--/* Macros used in tcg_target_op_defs. */
--#define R       "r"
--#define RI      "ri"
--#if TCG_TARGET_REG_BITS == 32
--# define R64    "r", "r"
--#else
--# define R64    "r"
--#endif
--#if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
--# define L      "r", "r"
--# define S      "r", "r"
--#else
--# define L      "r"
--# define S      "r"
--#endif
--
--/* TODO: documentation. */
--static const TCGTargetOpDef tcg_target_op_defs[] = {
--    { INDEX_op_exit_tb, { NULL } },
--    { INDEX_op_goto_tb, { NULL } },
--    { INDEX_op_br, { NULL } },
--
--    { INDEX_op_ld8u_i32, { R, R } },
--    { INDEX_op_ld8s_i32, { R, R } },
--    { INDEX_op_ld16u_i32, { R, R } },
--    { INDEX_op_ld16s_i32, { R, R } },
--    { INDEX_op_ld_i32, { R, R } },
--    { INDEX_op_st8_i32, { R, R } },
--    { INDEX_op_st16_i32, { R, R } },
--    { INDEX_op_st_i32, { R, R } },
--
--    { INDEX_op_add_i32, { R, RI, RI } },
--    { INDEX_op_sub_i32, { R, RI, RI } },
--    { INDEX_op_mul_i32, { R, RI, RI } },
--    { INDEX_op_div_i32, { R, R, R } },
--    { INDEX_op_divu_i32, { R, R, R } },
--    { INDEX_op_rem_i32, { R, R, R } },
--    { INDEX_op_remu_i32, { R, R, R } },
--    /* TODO: Does R, RI, RI result in faster code than R, R, RI?
--       If both operands are constants, we can optimize. */
--    { INDEX_op_and_i32, { R, RI, RI } },
--    { INDEX_op_andc_i32, { R, RI, RI } },
--    { INDEX_op_eqv_i32, { R, RI, RI } },
--    { INDEX_op_nand_i32, { R, RI, RI } },
--    { INDEX_op_nor_i32, { R, RI, RI } },
--    { INDEX_op_or_i32, { R, RI, RI } },
--    { INDEX_op_orc_i32, { R, RI, RI } },
--    { INDEX_op_xor_i32, { R, RI, RI } },
--    { INDEX_op_shl_i32, { R, RI, RI } },
--    { INDEX_op_shr_i32, { R, RI, RI } },
--    { INDEX_op_sar_i32, { R, RI, RI } },
--    { INDEX_op_rotl_i32, { R, RI, RI } },
--    { INDEX_op_rotr_i32, { R, RI, RI } },
--    { INDEX_op_deposit_i32, { R, "0", R } },
--
--    { INDEX_op_brcond_i32, { R, RI } },
--
--    { INDEX_op_setcond_i32, { R, R, RI } },
--    { INDEX_op_setcond_i64, { R, R, RI } },
--
--    /* TODO: Support R, R, R, R, RI, RI? Will it be faster? */
--    { INDEX_op_add2_i32, { R, R, R, R, R, R } },
--    { INDEX_op_sub2_i32, { R, R, R, R, R, R } },
--    { INDEX_op_brcond2_i32, { R, R, RI, RI } },
--    { INDEX_op_mulu2_i32, { R, R, R, R } },
--    { INDEX_op_setcond2_i32, { R, R, R, RI, RI } },
--
--    { INDEX_op_not_i32, { R, R } },
--    { INDEX_op_neg_i32, { R, R } },
--
--    { INDEX_op_ld8u_i64, { R, R } },
--    { INDEX_op_ld8s_i64, { R, R } },
--    { INDEX_op_ld16u_i64, { R, R } },
--    { INDEX_op_ld16s_i64, { R, R } },
--    { INDEX_op_ld32u_i64, { R, R } },
--    { INDEX_op_ld32s_i64, { R, R } },
--    { INDEX_op_ld_i64, { R, R } },
--
--    { INDEX_op_st8_i64, { R, R } },
--    { INDEX_op_st16_i64, { R, R } },
--    { INDEX_op_st32_i64, { R, R } },
--    { INDEX_op_st_i64, { R, R } },
--
--    { INDEX_op_add_i64, { R, RI, RI } },
--    { INDEX_op_sub_i64, { R, RI, RI } },
--    { INDEX_op_mul_i64, { R, RI, RI } },
--    { INDEX_op_div_i64, { R, R, R } },
--    { INDEX_op_divu_i64, { R, R, R } },
--    { INDEX_op_rem_i64, { R, R, R } },
--    { INDEX_op_remu_i64, { R, R, R } },
--    { INDEX_op_and_i64, { R, RI, RI } },
--    { INDEX_op_andc_i64, { R, RI, RI } },
--    { INDEX_op_eqv_i64, { R, RI, RI } },
--    { INDEX_op_nand_i64, { R, RI, RI } },
--    { INDEX_op_nor_i64, { R, RI, RI } },
--    { INDEX_op_or_i64, { R, RI, RI } },
--    { INDEX_op_orc_i64, { R, RI, RI } },
--    { INDEX_op_xor_i64, { R, RI, RI } },
--    { INDEX_op_shl_i64, { R, RI, RI } },
--    { INDEX_op_shr_i64, { R, RI, RI } },
--    { INDEX_op_sar_i64, { R, RI, RI } },
--    { INDEX_op_rotl_i64, { R, RI, RI } },
--    { INDEX_op_rotr_i64, { R, RI, RI } },
--    { INDEX_op_deposit_i64, { R, "0", R } },
--    { INDEX_op_brcond_i64, { R, RI } },
--
--    { INDEX_op_ext8s_i64, { R, R } },
--    { INDEX_op_ext16s_i64, { R, R } },
--    { INDEX_op_ext32s_i64, { R, R } },
--    { INDEX_op_ext8u_i64, { R, R } },
--    { INDEX_op_ext16u_i64, { R, R } },
--    { INDEX_op_ext32u_i64, { R, R } },
--    { INDEX_op_ext_i32_i64, { R, R } },
--    { INDEX_op_extu_i32_i64, { R, R } },
--    { INDEX_op_bswap16_i64, { R, R } },
--    { INDEX_op_bswap32_i64, { R, R } },
--    { INDEX_op_bswap64_i64, { R, R } },
--    { INDEX_op_not_i64, { R, R } },
--    { INDEX_op_neg_i64, { R, R } },
--
--    { INDEX_op_qemu_ld_i32, { R, L } },
--    { INDEX_op_qemu_ld_i64, { R64, L } },
--
--    { INDEX_op_qemu_st_i32, { R, S } },
--    { INDEX_op_qemu_st_i64, { R64, S } },
--
--    { INDEX_op_ext8s_i32, { R, R } },
--    { INDEX_op_ext16s_i32, { R, R } },
--    { INDEX_op_ext8u_i32, { R, R } },
--    { INDEX_op_ext16u_i32, { R, R } },
--
--    { INDEX_op_bswap16_i32, { R, R } },
--    { INDEX_op_bswap32_i32, { R, R } },
--
--    { INDEX_op_mb, { } },
--    { -1 },
--};
--
--static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
-+static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
- {
--    int i, n = ARRAY_SIZE(tcg_target_op_defs);
-+    switch (op) {
-+    case INDEX_op_ld8u_i32:
-+    case INDEX_op_ld8s_i32:
-+    case INDEX_op_ld16u_i32:
-+    case INDEX_op_ld16s_i32:
-+    case INDEX_op_ld_i32:
-+    case INDEX_op_ld8u_i64:
-+    case INDEX_op_ld8s_i64:
-+    case INDEX_op_ld16u_i64:
-+    case INDEX_op_ld16s_i64:
-+    case INDEX_op_ld32u_i64:
-+    case INDEX_op_ld32s_i64:
-+    case INDEX_op_ld_i64:
-+    case INDEX_op_not_i32:
-+    case INDEX_op_not_i64:
-+    case INDEX_op_neg_i32:
-+    case INDEX_op_neg_i64:
-+    case INDEX_op_ext8s_i32:
-+    case INDEX_op_ext8s_i64:
-+    case INDEX_op_ext16s_i32:
-+    case INDEX_op_ext16s_i64:
-+    case INDEX_op_ext8u_i32:
-+    case INDEX_op_ext8u_i64:
-+    case INDEX_op_ext16u_i32:
-+    case INDEX_op_ext16u_i64:
-+    case INDEX_op_ext32s_i64:
-+    case INDEX_op_ext32u_i64:
-+    case INDEX_op_ext_i32_i64:
-+    case INDEX_op_extu_i32_i64:
-+    case INDEX_op_bswap16_i32:
-+    case INDEX_op_bswap16_i64:
-+    case INDEX_op_bswap32_i32:
-+    case INDEX_op_bswap32_i64:
-+    case INDEX_op_bswap64_i64:
-+        return C_O1_I1(r, r);
--    for (i = 0; i < n; ++i) {
--        if (tcg_target_op_defs[i].op == op) {
--            return &tcg_target_op_defs[i];
--        }
-+    case INDEX_op_st8_i32:
-+    case INDEX_op_st16_i32:
-+    case INDEX_op_st_i32:
-+    case INDEX_op_st8_i64:
-+    case INDEX_op_st16_i64:
-+    case INDEX_op_st32_i64:
-+    case INDEX_op_st_i64:
-+        return C_O0_I2(r, r);
-+
-+    case INDEX_op_div_i32:
-+    case INDEX_op_div_i64:
-+    case INDEX_op_divu_i32:
-+    case INDEX_op_divu_i64:
-+    case INDEX_op_rem_i32:
-+    case INDEX_op_rem_i64:
-+    case INDEX_op_remu_i32:
-+    case INDEX_op_remu_i64:
-+        return C_O1_I2(r, r, r);
-+
-+    case INDEX_op_add_i32:
-+    case INDEX_op_add_i64:
-+    case INDEX_op_sub_i32:
-+    case INDEX_op_sub_i64:
-+    case INDEX_op_mul_i32:
-+    case INDEX_op_mul_i64:
-+    case INDEX_op_and_i32:
-+    case INDEX_op_and_i64:
-+    case INDEX_op_andc_i32:
-+    case INDEX_op_andc_i64:
-+    case INDEX_op_eqv_i32:
-+    case INDEX_op_eqv_i64:
-+    case INDEX_op_nand_i32:
-+    case INDEX_op_nand_i64:
-+    case INDEX_op_nor_i32:
-+    case INDEX_op_nor_i64:
-+    case INDEX_op_or_i32:
-+    case INDEX_op_or_i64:
-+    case INDEX_op_orc_i32:
-+    case INDEX_op_orc_i64:
-+    case INDEX_op_xor_i32:
-+    case INDEX_op_xor_i64:
-+    case INDEX_op_shl_i32:
-+    case INDEX_op_shl_i64:
-+    case INDEX_op_shr_i32:
-+    case INDEX_op_shr_i64:
-+    case INDEX_op_sar_i32:
-+    case INDEX_op_sar_i64:
-+    case INDEX_op_rotl_i32:
-+    case INDEX_op_rotl_i64:
-+    case INDEX_op_rotr_i32:
-+    case INDEX_op_rotr_i64:
-+        /* TODO: Does R, RI, RI result in faster code than R, R, RI? */
-+        return C_O1_I2(r, ri, ri);
-+
-+    case INDEX_op_deposit_i32:
-+    case INDEX_op_deposit_i64:
-+        return C_O1_I2(r, 0, r);
-+
-+    case INDEX_op_brcond_i32:
-+    case INDEX_op_brcond_i64:
-+        return C_O0_I2(r, ri);
-+
-+    case INDEX_op_setcond_i32:
-+    case INDEX_op_setcond_i64:
-+        return C_O1_I2(r, r, ri);
-+
-+#if TCG_TARGET_REG_BITS == 32
-+    /* TODO: Support R, R, R, R, RI, RI? Will it be faster? */
-+    case INDEX_op_add2_i32:
-+    case INDEX_op_sub2_i32:
-+        return C_O2_I4(r, r, r, r, r, r);
-+    case INDEX_op_brcond2_i32:
-+        return C_O0_I4(r, r, ri, ri);
-+    case INDEX_op_mulu2_i32:
-+        return C_O2_I2(r, r, r, r);
-+    case INDEX_op_setcond2_i32:
-+        return C_O1_I4(r, r, r, ri, ri);
-+#endif
-+
-+    case INDEX_op_qemu_ld_i32:
-+        return (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS
-+                ? C_O1_I1(r, r)
-+                : C_O1_I2(r, r, r));
-+    case INDEX_op_qemu_ld_i64:
-+        return (TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, r)
-+                : TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? C_O2_I1(r, r, r)
-+                : C_O2_I2(r, r, r, r));
-+    case INDEX_op_qemu_st_i32:
-+        return (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS
-+                ? C_O0_I2(r, r)
-+                : C_O0_I3(r, r, r));
-+    case INDEX_op_qemu_st_i64:
-+        return (TCG_TARGET_REG_BITS == 64 ? C_O0_I2(r, r)
-+                : TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? C_O0_I3(r, r, r)
-+                : C_O0_I4(r, r, r, r));
-+
-+    default:
-+        g_assert_not_reached();
-     }
--    return NULL;
- }
- static const int tcg_target_reg_alloc_order[] = {
---
-.25.1

-[PULL 24/24] tcg: Remove TCG_TARGET_CON_SET_H
+Deleted patch
-All backends have now been converted to tcg-target-con-set.h,
-so we can remove the fallback code.
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
----
- tcg/aarch64/tcg-target.h |  1 -
- tcg/arm/tcg-target.h     |  1 -
- tcg/i386/tcg-target.h    |  1 -
- tcg/mips/tcg-target.h    |  1 -
- tcg/ppc/tcg-target.h     |  1 -
- tcg/riscv/tcg-target.h   |  1 -
- tcg/s390/tcg-target.h    |  1 -
- tcg/sparc/tcg-target.h   |  1 -
- tcg/tci/tcg-target.h     |  2 --
- tcg/tcg.c                | 12 ------------
-files changed, 22 deletions(-)
-diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h
-index XXXXXXX..XXXXXXX 100644
---- a/tcg/aarch64/tcg-target.h
-+++ b/tcg/aarch64/tcg-target.h
-@@ -XXX,XX +XXX,XX @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t);
- #define TCG_TARGET_NEED_LDST_LABELS
- #endif
- #define TCG_TARGET_NEED_POOL_LABELS
--#define TCG_TARGET_CON_SET_H
- #endif /* AARCH64_TCG_TARGET_H */
-diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
-index XXXXXXX..XXXXXXX 100644
---- a/tcg/arm/tcg-target.h
-+++ b/tcg/arm/tcg-target.h
-@@ -XXX,XX +XXX,XX @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t);
- #define TCG_TARGET_NEED_LDST_LABELS
- #endif
- #define TCG_TARGET_NEED_POOL_LABELS
--#define TCG_TARGET_CON_SET_H
- #endif
-diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h
-index XXXXXXX..XXXXXXX 100644
---- a/tcg/i386/tcg-target.h
-+++ b/tcg/i386/tcg-target.h
-@@ -XXX,XX +XXX,XX @@ static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_rx,
- #define TCG_TARGET_NEED_LDST_LABELS
- #endif
- #define TCG_TARGET_NEED_POOL_LABELS
--#define TCG_TARGET_CON_SET_H
- #endif
-diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h
-index XXXXXXX..XXXXXXX 100644
---- a/tcg/mips/tcg-target.h
-+++ b/tcg/mips/tcg-target.h
-@@ -XXX,XX +XXX,XX @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t);
- #ifdef CONFIG_SOFTMMU
- #define TCG_TARGET_NEED_LDST_LABELS
- #endif
--#define TCG_TARGET_CON_SET_H
- #endif
-diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h
-index XXXXXXX..XXXXXXX 100644
---- a/tcg/ppc/tcg-target.h
-+++ b/tcg/ppc/tcg-target.h
-@@ -XXX,XX +XXX,XX @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t);
- #define TCG_TARGET_NEED_LDST_LABELS
- #endif
- #define TCG_TARGET_NEED_POOL_LABELS
--#define TCG_TARGET_CON_SET_H
- #endif
-diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h
-index XXXXXXX..XXXXXXX 100644
---- a/tcg/riscv/tcg-target.h
-+++ b/tcg/riscv/tcg-target.h
-@@ -XXX,XX +XXX,XX @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t);
- #define TCG_TARGET_NEED_POOL_LABELS
- #define TCG_TARGET_HAS_MEMORY_BSWAP 0
--#define TCG_TARGET_CON_SET_H
- #endif
-diff --git a/tcg/s390/tcg-target.h b/tcg/s390/tcg-target.h
-index XXXXXXX..XXXXXXX 100644
---- a/tcg/s390/tcg-target.h
-+++ b/tcg/s390/tcg-target.h
-@@ -XXX,XX +XXX,XX @@ static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_rx,
- #define TCG_TARGET_NEED_LDST_LABELS
- #endif
- #define TCG_TARGET_NEED_POOL_LABELS
--#define TCG_TARGET_CON_SET_H
- #endif
-diff --git a/tcg/sparc/tcg-target.h b/tcg/sparc/tcg-target.h
-index XXXXXXX..XXXXXXX 100644
---- a/tcg/sparc/tcg-target.h
-+++ b/tcg/sparc/tcg-target.h
-@@ -XXX,XX +XXX,XX @@ extern bool use_vis3_instructions;
- void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t);
- #define TCG_TARGET_NEED_POOL_LABELS
--#define TCG_TARGET_CON_SET_H
- #endif
-diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h
-index XXXXXXX..XXXXXXX 100644
---- a/tcg/tci/tcg-target.h
-+++ b/tcg/tci/tcg-target.h
-@@ -XXX,XX +XXX,XX @@ static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_rx,
-     /* no need to flush icache explicitly */
- }
--#define TCG_TARGET_CON_SET_H
--
- #endif /* TCG_TARGET_H */
-diff --git a/tcg/tcg.c b/tcg/tcg.c
-index XXXXXXX..XXXXXXX 100644
---- a/tcg/tcg.c
-+++ b/tcg/tcg.c
-@@ -XXX,XX +XXX,XX @@
- /* Forward declarations for functions declared in tcg-target.c.inc and
-    used here. */
- static void tcg_target_init(TCGContext *s);
--#ifndef TCG_TARGET_CON_SET_H
--static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode);
--#endif
- static void tcg_target_qemu_prologue(TCGContext *s);
- static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
-                         intptr_t value, intptr_t addend);
-@@ -XXX,XX +XXX,XX @@ static void set_jmp_reset_offset(TCGContext *s, int which)
-     s->tb_jmp_reset_offset[which] = tcg_current_code_size(s);
- }
--#ifdef TCG_TARGET_CON_SET_H
- #define C_PFX1(P, A)                    P##A
- #define C_PFX2(P, A, B)                 P##A##_##B
- #define C_PFX3(P, A, B, C)              P##A##_##B##_##C
-@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef constraint_sets[] = {
- #define C_O2_I3(O1, O2, I1, I2, I3)     C_PFX5(c_o2_i3_, O1, O2, I1, I2, I3)
- #define C_O2_I4(O1, O2, I1, I2, I3, I4) C_PFX6(c_o2_i4_, O1, O2, I1, I2, I3, I4)
--#endif /* TCG_TARGET_CON_SET_H */
--
- #include "tcg-target.c.inc"
- /* compare a pointer @ptr and a tb_tc @s */
-@@ -XXX,XX +XXX,XX @@ static void process_op_defs(TCGContext *s)
-             continue;
-         }
--#ifdef TCG_TARGET_CON_SET_H
-         /*
-          * Macro magic should make it impossible, but double-check that
-          * the array index is in range.  Since the signness of an enum
-@@ -XXX,XX +XXX,XX @@ static void process_op_defs(TCGContext *s)
-         unsigned con_set = tcg_target_op_def(op);
-         tcg_debug_assert(con_set < ARRAY_SIZE(constraint_sets));
-         tdefs = &constraint_sets[con_set];
--#else
--        tdefs = tcg_target_op_def(op);
--        /* Missing TCGTargetOpDef entry. */
--        tcg_debug_assert(tdefs != NULL);
--#endif
-         for (i = 0; i < nb_args; i++) {
-             const char *ct_str = tdefs->args_ct_str[i];
---
-.25.1

The following changes since commit 77f3804ab7ed94b471a14acb260e5aeacf26193f:

Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into staging (2021-02-02 16:47:51 +0000)

are available in the Git repository at:

https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20210202

for you to fetch changes up to 0c823e596877a30fd6c17a1ae9f98218a53055ea:

tcg: Remove TCG_TARGET_CON_SET_H (2021-02-02 12:12:43 -1000)

----------------------------------------------------------------
TCG backend constraints cleanup

----------------------------------------------------------------
Richard Henderson (24):
      tcg/tci: Drop L and S constraints
      tcg/tci: Remove TCG_TARGET_HAS_* ifdefs
      tcg/i386: Move constraint type check to tcg_target_const_match
      tcg/i386: Tidy register constraint definitions
      tcg/i386: Split out target constraints to tcg-target-con-str.h
      tcg/arm: Split out target constraints to tcg-target-con-str.h
      tcg/aarch64: Split out target constraints to tcg-target-con-str.h
      tcg/ppc: Split out target constraints to tcg-target-con-str.h
      tcg/tci: Split out target constraints to tcg-target-con-str.h
      tcg/mips: Split out target constraints to tcg-target-con-str.h
      tcg/riscv: Split out target constraints to tcg-target-con-str.h
      tcg/s390: Split out target constraints to tcg-target-con-str.h
      tcg/sparc: Split out target constraints to tcg-target-con-str.h
      tcg: Remove TCG_TARGET_CON_STR_H
      tcg/i386: Split out constraint sets to tcg-target-con-set.h
      tcg/aarch64: Split out constraint sets to tcg-target-con-set.h
      tcg/arm: Split out constraint sets to tcg-target-con-set.h
      tcg/mips: Split out constraint sets to tcg-target-con-set.h
      tcg/ppc: Split out constraint sets to tcg-target-con-set.h
      tcg/riscv: Split out constraint sets to tcg-target-con-set.h
      tcg/s390: Split out constraint sets to tcg-target-con-set.h
      tcg/sparc: Split out constraint sets to tcg-target-con-set.h
      tcg/tci: Split out constraint sets to tcg-target-con-set.h
      tcg: Remove TCG_TARGET_CON_SET_H

tcg/aarch64/tcg-target-con-set.h |  36 ++++
 tcg/aarch64/tcg-target-con-str.h |  24 +++
 tcg/arm/tcg-target-con-set.h     |  35 ++++
 tcg/arm/tcg-target-con-str.h     |  22 +++
 tcg/i386/tcg-target-con-set.h    |  55 ++++++
 tcg/i386/tcg-target-con-str.h    |  33 ++++
 tcg/mips/tcg-target-con-set.h    |  36 ++++
 tcg/mips/tcg-target-con-str.h    |  24 +++
 tcg/ppc/tcg-target-con-set.h     |  42 +++++
 tcg/ppc/tcg-target-con-str.h     |  30 ++++
 tcg/riscv/tcg-target-con-set.h   |  30 ++++
 tcg/riscv/tcg-target-con-str.h   |  21 +++
 tcg/s390/tcg-target-con-set.h    |  29 ++++
 tcg/s390/tcg-target-con-str.h    |  28 +++
 tcg/sparc/tcg-target-con-set.h   |  32 ++++
 tcg/sparc/tcg-target-con-str.h   |  23 +++
 tcg/sparc/tcg-target.h           |   4 -
 tcg/tci/tcg-target-con-set.h     |  25 +++
 tcg/tci/tcg-target-con-str.h     |  11 ++
 tcg/tcg.c                        | 136 +++++++++++++--
 tcg/aarch64/tcg-target.c.inc     | 137 ++++-----------
 tcg/arm/tcg-target.c.inc         | 168 ++++++------------
 tcg/i386/tcg-target.c.inc        | 317 +++++++++++-----------------------
 tcg/mips/tcg-target.c.inc        | 173 ++++++-------------
 tcg/ppc/tcg-target.c.inc         | 209 ++++++++---------------
 tcg/riscv/tcg-target.c.inc       | 135 ++++-----------
 tcg/s390/tcg-target.c.inc        | 174 +++++++------------
 tcg/sparc/tcg-target.c.inc       | 156 ++++++-----------
 tcg/tci/tcg-target.c.inc         | 359 ++++++++++++++-------------------------
 29 files changed, 1244 insertions(+), 1260 deletions(-)
 create mode 100644 tcg/aarch64/tcg-target-con-set.h
 create mode 100644 tcg/aarch64/tcg-target-con-str.h
 create mode 100644 tcg/arm/tcg-target-con-set.h
 create mode 100644 tcg/arm/tcg-target-con-str.h
 create mode 100644 tcg/i386/tcg-target-con-set.h
 create mode 100644 tcg/i386/tcg-target-con-str.h
 create mode 100644 tcg/mips/tcg-target-con-set.h
 create mode 100644 tcg/mips/tcg-target-con-str.h
 create mode 100644 tcg/ppc/tcg-target-con-set.h
 create mode 100644 tcg/ppc/tcg-target-con-str.h
 create mode 100644 tcg/riscv/tcg-target-con-set.h
 create mode 100644 tcg/riscv/tcg-target-con-str.h
 create mode 100644 tcg/s390/tcg-target-con-set.h
 create mode 100644 tcg/s390/tcg-target-con-str.h
 create mode 100644 tcg/sparc/tcg-target-con-set.h
 create mode 100644 tcg/sparc/tcg-target-con-str.h
 create mode 100644 tcg/tci/tcg-target-con-set.h
 create mode 100644 tcg/tci/tcg-target-con-str.h

These are identical to the 'r' constraint.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/tci/tcg-target.c.inc | 10 ++++------
 1 file changed, 4 insertions(+), 6 deletions(-)

diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/tci/tcg-target.c.inc
+++ b/tcg/tci/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@
 # define R64    "r"
 #endif
 #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
-# define L      "L", "L"
-# define S      "S", "S"
+# define L      "r", "r"
+# define S      "r", "r"
 #else
-# define L      "L"
-# define S      "S"
+# define L      "r"
+# define S      "r"
 #endif
 
 /* TODO: documentation. */
@@ -XXX,XX +XXX,XX @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
 {
     switch (*ct_str++) {
     case 'r':
-    case 'L':                   /* qemu_ld constraint */
-    case 'S':                   /* qemu_st constraint */
         ct->regs = BIT(TCG_TARGET_NB_REGS) - 1;
         break;
     default:
-- 
2.25.1

The opcodes always exist, regardless of whether or not they
are enabled.  Remove the unnecessary ifdefs.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/tci/tcg-target.c.inc | 82 ----------------------------------------
 1 file changed, 82 deletions(-)

diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/tci/tcg-target.c.inc
+++ b/tcg/tci/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef tcg_target_op_defs[] = {
     { INDEX_op_add_i32, { R, RI, RI } },
     { INDEX_op_sub_i32, { R, RI, RI } },
     { INDEX_op_mul_i32, { R, RI, RI } },
-#if TCG_TARGET_HAS_div_i32
     { INDEX_op_div_i32, { R, R, R } },
     { INDEX_op_divu_i32, { R, R, R } },
     { INDEX_op_rem_i32, { R, R, R } },
     { INDEX_op_remu_i32, { R, R, R } },
-#elif TCG_TARGET_HAS_div2_i32
-    { INDEX_op_div2_i32, { R, R, "0", "1", R } },
-    { INDEX_op_divu2_i32, { R, R, "0", "1", R } },
-#endif
     /* TODO: Does R, RI, RI result in faster code than R, R, RI?
        If both operands are constants, we can optimize. */
     { INDEX_op_and_i32, { R, RI, RI } },
-#if TCG_TARGET_HAS_andc_i32
     { INDEX_op_andc_i32, { R, RI, RI } },
-#endif
-#if TCG_TARGET_HAS_eqv_i32
     { INDEX_op_eqv_i32, { R, RI, RI } },
-#endif
-#if TCG_TARGET_HAS_nand_i32
     { INDEX_op_nand_i32, { R, RI, RI } },
-#endif
-#if TCG_TARGET_HAS_nor_i32
     { INDEX_op_nor_i32, { R, RI, RI } },
-#endif
     { INDEX_op_or_i32, { R, RI, RI } },
-#if TCG_TARGET_HAS_orc_i32
     { INDEX_op_orc_i32, { R, RI, RI } },
-#endif
     { INDEX_op_xor_i32, { R, RI, RI } },
     { INDEX_op_shl_i32, { R, RI, RI } },
     { INDEX_op_shr_i32, { R, RI, RI } },
     { INDEX_op_sar_i32, { R, RI, RI } },
-#if TCG_TARGET_HAS_rot_i32
     { INDEX_op_rotl_i32, { R, RI, RI } },
     { INDEX_op_rotr_i32, { R, RI, RI } },
-#endif
-#if TCG_TARGET_HAS_deposit_i32
     { INDEX_op_deposit_i32, { R, "0", R } },
-#endif
 
     { INDEX_op_brcond_i32, { R, RI } },
 
     { INDEX_op_setcond_i32, { R, R, RI } },
-#if TCG_TARGET_REG_BITS == 64
     { INDEX_op_setcond_i64, { R, R, RI } },
-#endif /* TCG_TARGET_REG_BITS == 64 */
 
-#if TCG_TARGET_REG_BITS == 32
     /* TODO: Support R, R, R, R, RI, RI? Will it be faster? */
     { INDEX_op_add2_i32, { R, R, R, R, R, R } },
     { INDEX_op_sub2_i32, { R, R, R, R, R, R } },
     { INDEX_op_brcond2_i32, { R, R, RI, RI } },
     { INDEX_op_mulu2_i32, { R, R, R, R } },
     { INDEX_op_setcond2_i32, { R, R, R, RI, RI } },
-#endif
 
-#if TCG_TARGET_HAS_not_i32
     { INDEX_op_not_i32, { R, R } },
-#endif
-#if TCG_TARGET_HAS_neg_i32
     { INDEX_op_neg_i32, { R, R } },
-#endif
 
-#if TCG_TARGET_REG_BITS == 64
     { INDEX_op_ld8u_i64, { R, R } },
     { INDEX_op_ld8s_i64, { R, R } },
     { INDEX_op_ld16u_i64, { R, R } },
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef tcg_target_op_defs[] = {
     { INDEX_op_add_i64, { R, RI, RI } },
     { INDEX_op_sub_i64, { R, RI, RI } },
     { INDEX_op_mul_i64, { R, RI, RI } },
-#if TCG_TARGET_HAS_div_i64
     { INDEX_op_div_i64, { R, R, R } },
     { INDEX_op_divu_i64, { R, R, R } },
     { INDEX_op_rem_i64, { R, R, R } },
     { INDEX_op_remu_i64, { R, R, R } },
-#elif TCG_TARGET_HAS_div2_i64
-    { INDEX_op_div2_i64, { R, R, "0", "1", R } },
-    { INDEX_op_divu2_i64, { R, R, "0", "1", R } },
-#endif
     { INDEX_op_and_i64, { R, RI, RI } },
-#if TCG_TARGET_HAS_andc_i64
     { INDEX_op_andc_i64, { R, RI, RI } },
-#endif
-#if TCG_TARGET_HAS_eqv_i64
     { INDEX_op_eqv_i64, { R, RI, RI } },
-#endif
-#if TCG_TARGET_HAS_nand_i64
     { INDEX_op_nand_i64, { R, RI, RI } },
-#endif
-#if TCG_TARGET_HAS_nor_i64
     { INDEX_op_nor_i64, { R, RI, RI } },
-#endif
     { INDEX_op_or_i64, { R, RI, RI } },
-#if TCG_TARGET_HAS_orc_i64
     { INDEX_op_orc_i64, { R, RI, RI } },
-#endif
     { INDEX_op_xor_i64, { R, RI, RI } },
     { INDEX_op_shl_i64, { R, RI, RI } },
     { INDEX_op_shr_i64, { R, RI, RI } },
     { INDEX_op_sar_i64, { R, RI, RI } },
-#if TCG_TARGET_HAS_rot_i64
     { INDEX_op_rotl_i64, { R, RI, RI } },
     { INDEX_op_rotr_i64, { R, RI, RI } },
-#endif
-#if TCG_TARGET_HAS_deposit_i64
     { INDEX_op_deposit_i64, { R, "0", R } },
-#endif
     { INDEX_op_brcond_i64, { R, RI } },
 
-#if TCG_TARGET_HAS_ext8s_i64
     { INDEX_op_ext8s_i64, { R, R } },
-#endif
-#if TCG_TARGET_HAS_ext16s_i64
     { INDEX_op_ext16s_i64, { R, R } },
-#endif
-#if TCG_TARGET_HAS_ext32s_i64
     { INDEX_op_ext32s_i64, { R, R } },
-#endif
-#if TCG_TARGET_HAS_ext8u_i64
     { INDEX_op_ext8u_i64, { R, R } },
-#endif
-#if TCG_TARGET_HAS_ext16u_i64
     { INDEX_op_ext16u_i64, { R, R } },
-#endif
-#if TCG_TARGET_HAS_ext32u_i64
     { INDEX_op_ext32u_i64, { R, R } },
-#endif
     { INDEX_op_ext_i32_i64, { R, R } },
     { INDEX_op_extu_i32_i64, { R, R } },
-#if TCG_TARGET_HAS_bswap16_i64
     { INDEX_op_bswap16_i64, { R, R } },
-#endif
-#if TCG_TARGET_HAS_bswap32_i64
     { INDEX_op_bswap32_i64, { R, R } },
-#endif
-#if TCG_TARGET_HAS_bswap64_i64
     { INDEX_op_bswap64_i64, { R, R } },
-#endif
-#if TCG_TARGET_HAS_not_i64
     { INDEX_op_not_i64, { R, R } },
-#endif
-#if TCG_TARGET_HAS_neg_i64
     { INDEX_op_neg_i64, { R, R } },
-#endif
-#endif /* TCG_TARGET_REG_BITS == 64 */
 
     { INDEX_op_qemu_ld_i32, { R, L } },
     { INDEX_op_qemu_ld_i64, { R64, L } },
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef tcg_target_op_defs[] = {
     { INDEX_op_qemu_st_i32, { R, S } },
     { INDEX_op_qemu_st_i64, { R64, S } },
 
-#if TCG_TARGET_HAS_ext8s_i32
     { INDEX_op_ext8s_i32, { R, R } },
-#endif
-#if TCG_TARGET_HAS_ext16s_i32
     { INDEX_op_ext16s_i32, { R, R } },
-#endif
-#if TCG_TARGET_HAS_ext8u_i32
     { INDEX_op_ext8u_i32, { R, R } },
-#endif
-#if TCG_TARGET_HAS_ext16u_i32
     { INDEX_op_ext16u_i32, { R, R } },
-#endif
 
-#if TCG_TARGET_HAS_bswap16_i32
     { INDEX_op_bswap16_i32, { R, R } },
-#endif
-#if TCG_TARGET_HAS_bswap32_i32
     { INDEX_op_bswap32_i32, { R, R } },
-#endif
 
     { INDEX_op_mb, { } },
     { -1 },
-- 
2.25.1

Rather than check the type when filling in the constraint,
check it when matching the constant.  This removes the only
use of the type argument to target_parse_constraint.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/i386/tcg-target.c.inc | 28 +++++++++++++++++-----------
 1 file changed, 17 insertions(+), 11 deletions(-)

diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/i386/tcg-target.c.inc
+++ b/tcg/i386/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
         break;
 
     case 'e':
-        ct->ct |= (type == TCG_TYPE_I32 ? TCG_CT_CONST : TCG_CT_CONST_S32);
+        ct->ct |= TCG_CT_CONST_S32;
         break;
     case 'Z':
-        ct->ct |= (type == TCG_TYPE_I32 ? TCG_CT_CONST : TCG_CT_CONST_U32);
+        ct->ct |= TCG_CT_CONST_U32;
         break;
     case 'I':
-        ct->ct |= (type == TCG_TYPE_I32 ? TCG_CT_CONST : TCG_CT_CONST_I32);
+        ct->ct |= TCG_CT_CONST_I32;
         break;
 
     default:
@@ -XXX,XX +XXX,XX @@ static inline int tcg_target_const_match(tcg_target_long val, TCGType type,
     if (ct & TCG_CT_CONST) {
         return 1;
     }
-    if ((ct & TCG_CT_CONST_S32) && val == (int32_t)val) {
-        return 1;
-    }
-    if ((ct & TCG_CT_CONST_U32) && val == (uint32_t)val) {
-        return 1;
-    }
-    if ((ct & TCG_CT_CONST_I32) && ~val == (int32_t)~val) {
-        return 1;
+    if (type == TCG_TYPE_I32) {
+        if (ct & (TCG_CT_CONST_S32 | TCG_CT_CONST_U32 | TCG_CT_CONST_I32)) {
+            return 1;
+        }
+    } else {
+        if ((ct & TCG_CT_CONST_S32) && val == (int32_t)val) {
+            return 1;
+        }
+        if ((ct & TCG_CT_CONST_U32) && val == (uint32_t)val) {
+            return 1;
+        }
+        if ((ct & TCG_CT_CONST_I32) && ~val == (int32_t)~val) {
+            return 1;
+        }
     }
     if ((ct & TCG_CT_CONST_WSZ) && val == (type == TCG_TYPE_I32 ? 32 : 64)) {
         return 1;
-- 
2.25.1

Create symbolic constants for all low-byte-addressable
and second-byte-addressable registers.  Create a symbol
for the registers that need reserving for softmmu.

There is no functional change for 's', as this letter is
only used for i386.  The BYTEL name is correct for the
action we wish from the constraint.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/i386/tcg-target.c.inc | 40 +++++++++++++++++++--------------------
 1 file changed, 20 insertions(+), 20 deletions(-)

diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/i386/tcg-target.c.inc
+++ b/tcg/i386/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ static const int tcg_target_call_oarg_regs[] = {
 # define TCG_REG_L1 TCG_REG_EDX
 #endif
 
+#define ALL_BYTEH_REGS         0x0000000fu
+#if TCG_TARGET_REG_BITS == 64
+# define ALL_GENERAL_REGS      0x0000ffffu
+# define ALL_VECTOR_REGS       0xffff0000u
+# define ALL_BYTEL_REGS        ALL_GENERAL_REGS
+#else
+# define ALL_GENERAL_REGS      0x000000ffu
+# define ALL_VECTOR_REGS       0x00ff0000u
+# define ALL_BYTEL_REGS        ALL_BYTEH_REGS
+#endif
+#ifdef CONFIG_SOFTMMU
+# define SOFTMMU_RESERVE_REGS  ((1 << TCG_REG_L0) | (1 << TCG_REG_L1))
+#else
+# define SOFTMMU_RESERVE_REGS  0
+#endif
+
 /* The host compiler should supply <cpuid.h> to enable runtime features
    detection, as we're not going to go so far as our own inline assembly.
    If not available, default values will be assumed.  */
@@ -XXX,XX +XXX,XX @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
     return true;
 }
 
-#if TCG_TARGET_REG_BITS == 64
-#define ALL_GENERAL_REGS   0x0000ffffu
-#define ALL_VECTOR_REGS    0xffff0000u
-#else
-#define ALL_GENERAL_REGS   0x000000ffu
-#define ALL_VECTOR_REGS    0x00ff0000u
-#endif
-
 /* parse target specific constraints */
 static const char *target_parse_constraint(TCGArgConstraint *ct,
                                            const char *ct_str, TCGType type)
@@ -XXX,XX +XXX,XX @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
         break;
     case 'q':
         /* A register that can be used as a byte operand.  */
-        ct->regs = TCG_TARGET_REG_BITS == 64 ? 0xffff : 0xf;
+        ct->regs |= ALL_BYTEL_REGS;
         break;
     case 'Q':
         /* A register with an addressable second byte (e.g. %ah).  */
-        ct->regs = 0xf;
+        ct->regs |= ALL_BYTEH_REGS;
         break;
     case 'r':
         /* A general register.  */
@@ -XXX,XX +XXX,XX @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
 
     case 'L':
         /* qemu_ld/st data+address constraint */
-        ct->regs = TCG_TARGET_REG_BITS == 64 ? 0xffff : 0xff;
-#ifdef CONFIG_SOFTMMU
-        tcg_regset_reset_reg(ct->regs, TCG_REG_L0);
-        tcg_regset_reset_reg(ct->regs, TCG_REG_L1);
-#endif
+        ct->regs |= ALL_GENERAL_REGS & ~SOFTMMU_RESERVE_REGS;
         break;
     case 's':
         /* qemu_st8_i32 data constraint */
-        ct->regs = 0xf;
-#ifdef CONFIG_SOFTMMU
-        tcg_regset_reset_reg(ct->regs, TCG_REG_L0);
-        tcg_regset_reset_reg(ct->regs, TCG_REG_L1);
-#endif
+        ct->regs |= ALL_BYTEL_REGS & ~SOFTMMU_RESERVE_REGS;
         break;
 
     case 'e':
-- 
2.25.1

This eliminates the target-specific function target_parse_constraint
and folds it into the single caller, process_op_defs.  Since this is
done directly into the switch statement, duplicates are compilation
errors rather than silently ignored at runtime.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/i386/tcg-target-con-str.h | 33 +++++++++++++++++
 tcg/i386/tcg-target.h         |  1 +
 tcg/tcg.c                     | 33 ++++++++++++++---
 tcg/i386/tcg-target.c.inc     | 69 -----------------------------------
 4 files changed, 62 insertions(+), 74 deletions(-)
 create mode 100644 tcg/i386/tcg-target-con-str.h

diff --git a/tcg/i386/tcg-target-con-str.h b/tcg/i386/tcg-target-con-str.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/tcg/i386/tcg-target-con-str.h
@@ -XXX,XX +XXX,XX @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Define i386 target-specific operand constraints.
+ * Copyright (c) 2021 Linaro
+ *
+ */
+
+/*
+ * Define constraint letters for register sets:
+ * REGS(letter, register_mask)
+ */
+REGS('a', 1u << TCG_REG_EAX)
+REGS('b', 1u << TCG_REG_EBX)
+REGS('c', 1u << TCG_REG_ECX)
+REGS('d', 1u << TCG_REG_EDX)
+REGS('S', 1u << TCG_REG_ESI)
+REGS('D', 1u << TCG_REG_EDI)
+
+REGS('r', ALL_GENERAL_REGS)
+REGS('x', ALL_VECTOR_REGS)
+REGS('q', ALL_BYTEL_REGS)     /* regs that can be used as a byte operand */
+REGS('Q', ALL_BYTEH_REGS)     /* regs with a second byte (e.g. %ah) */
+REGS('L', ALL_GENERAL_REGS & ~SOFTMMU_RESERVE_REGS)  /* qemu_ld/st */
+REGS('s', ALL_BYTEL_REGS & ~SOFTMMU_RESERVE_REGS)    /* qemu_st8_i32 data */
+
+/*
+ * Define constraint letters for constants:
+ * CONST(letter, TCG_CT_CONST_* bit set)
+ */
+CONST('e', TCG_CT_CONST_S32)
+CONST('I', TCG_CT_CONST_I32)
+CONST('W', TCG_CT_CONST_WSZ)
+CONST('Z', TCG_CT_CONST_U32)
diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h
index XXXXXXX..XXXXXXX 100644
--- a/tcg/i386/tcg-target.h
+++ b/tcg/i386/tcg-target.h
@@ -XXX,XX +XXX,XX @@ static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_rx,
 #define TCG_TARGET_NEED_LDST_LABELS
 #endif
 #define TCG_TARGET_NEED_POOL_LABELS
+#define TCG_TARGET_CON_STR_H
 
 #endif
diff --git a/tcg/tcg.c b/tcg/tcg.c
index XXXXXXX..XXXXXXX 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -XXX,XX +XXX,XX @@ static void tcg_register_jit_int(const void *buf, size_t size,
     __attribute__((unused));
 
 /* Forward declarations for functions declared and used in tcg-target.c.inc. */
+#ifndef TCG_TARGET_CON_STR_H
 static const char *target_parse_constraint(TCGArgConstraint *ct,
                                            const char *ct_str, TCGType type);
+#endif
 static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg1,
                        intptr_t arg2);
 static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg);
@@ -XXX,XX +XXX,XX @@ static void process_op_defs(TCGContext *s)
     for (op = 0; op < NB_OPS; op++) {
         TCGOpDef *def = &tcg_op_defs[op];
         const TCGTargetOpDef *tdefs;
-        TCGType type;
         int i, nb_args;
 
         if (def->flags & TCG_OPF_NOT_PRESENT) {
@@ -XXX,XX +XXX,XX @@ static void process_op_defs(TCGContext *s)
         /* Missing TCGTargetOpDef entry. */
         tcg_debug_assert(tdefs != NULL);
 
-        type = (def->flags & TCG_OPF_64BIT ? TCG_TYPE_I64 : TCG_TYPE_I32);
         for (i = 0; i < nb_args; i++) {
             const char *ct_str = tdefs->args_ct_str[i];
             /* Incomplete TCGTargetOpDef entry. */
@@ -XXX,XX +XXX,XX @@ static void process_op_defs(TCGContext *s)
                     def->args_ct[i].ct |= TCG_CT_CONST;
                     ct_str++;
                     break;
+
+#ifdef TCG_TARGET_CON_STR_H
+                /* Include all of the target-specific constraints. */
+
+#undef CONST
+#define CONST(CASE, MASK) \
+    case CASE: def->args_ct[i].ct |= MASK; ct_str++; break;
+#define REGS(CASE, MASK) \
+    case CASE: def->args_ct[i].regs |= MASK; ct_str++; break;
+
+#include "tcg-target-con-str.h"
+
+#undef REGS
+#undef CONST
                 default:
-                    ct_str = target_parse_constraint(&def->args_ct[i],
-                                                     ct_str, type);
                     /* Typo in TCGTargetOpDef constraint. */
-                    tcg_debug_assert(ct_str != NULL);
+                    g_assert_not_reached();
+#else
+                default:
+                    {
+                        TCGType type = (def->flags & TCG_OPF_64BIT
+                                        ? TCG_TYPE_I64 : TCG_TYPE_I32);
+                        ct_str = target_parse_constraint(&def->args_ct[i],
+                                                         ct_str, type);
+                        /* Typo in TCGTargetOpDef constraint. */
+                        tcg_debug_assert(ct_str != NULL);
+                    }
+#endif
                 }
             }
         }
diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/i386/tcg-target.c.inc
+++ b/tcg/i386/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
     return true;
 }
 
-/* parse target specific constraints */
-static const char *target_parse_constraint(TCGArgConstraint *ct,
-                                           const char *ct_str, TCGType type)
-{
-    switch(*ct_str++) {
-    case 'a':
-        tcg_regset_set_reg(ct->regs, TCG_REG_EAX);
-        break;
-    case 'b':
-        tcg_regset_set_reg(ct->regs, TCG_REG_EBX);
-        break;
-    case 'c':
-        tcg_regset_set_reg(ct->regs, TCG_REG_ECX);
-        break;
-    case 'd':
-        tcg_regset_set_reg(ct->regs, TCG_REG_EDX);
-        break;
-    case 'S':
-        tcg_regset_set_reg(ct->regs, TCG_REG_ESI);
-        break;
-    case 'D':
-        tcg_regset_set_reg(ct->regs, TCG_REG_EDI);
-        break;
-    case 'q':
-        /* A register that can be used as a byte operand.  */
-        ct->regs |= ALL_BYTEL_REGS;
-        break;
-    case 'Q':
-        /* A register with an addressable second byte (e.g. %ah).  */
-        ct->regs |= ALL_BYTEH_REGS;
-        break;
-    case 'r':
-        /* A general register.  */
-        ct->regs |= ALL_GENERAL_REGS;
-        break;
-    case 'W':
-        /* With TZCNT/LZCNT, we can have operand-size as an input.  */
-        ct->ct |= TCG_CT_CONST_WSZ;
-        break;
-    case 'x':
-        /* A vector register.  */
-        ct->regs |= ALL_VECTOR_REGS;
-        break;
-
-    case 'L':
-        /* qemu_ld/st data+address constraint */
-        ct->regs |= ALL_GENERAL_REGS & ~SOFTMMU_RESERVE_REGS;
-        break;
-    case 's':
-        /* qemu_st8_i32 data constraint */
-        ct->regs |= ALL_BYTEL_REGS & ~SOFTMMU_RESERVE_REGS;
-        break;
-
-    case 'e':
-        ct->ct |= TCG_CT_CONST_S32;
-        break;
-    case 'Z':
-        ct->ct |= TCG_CT_CONST_U32;
-        break;
-    case 'I':
-        ct->ct |= TCG_CT_CONST_I32;
-        break;
-
-    default:
-        return NULL;
-    }
-    return ct_str;
-}
-
 /* test if a constant matches the constraint */
 static inline int tcg_target_const_match(tcg_target_long val, TCGType type,
                                          const TCGArgConstraint *arg_ct)
-- 
2.25.1

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/arm/tcg-target-con-str.h | 22 +++++++++++
 tcg/arm/tcg-target.h         |  1 +
 tcg/arm/tcg-target.c.inc     | 74 +++++++++---------------------------
 3 files changed, 41 insertions(+), 56 deletions(-)
 create mode 100644 tcg/arm/tcg-target-con-str.h

diff --git a/tcg/arm/tcg-target-con-str.h b/tcg/arm/tcg-target-con-str.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/tcg/arm/tcg-target-con-str.h
@@ -XXX,XX +XXX,XX @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Define Arm target-specific operand constraints.
+ * Copyright (c) 2021 Linaro
+ */
+
+/*
+ * Define constraint letters for register sets:
+ * REGS(letter, register_mask)
+ */
+REGS('r', ALL_GENERAL_REGS)
+REGS('l', ALL_QLOAD_REGS)
+REGS('s', ALL_QSTORE_REGS)
+
+/*
+ * Define constraint letters for constants:
+ * CONST(letter, TCG_CT_CONST_* bit set)
+ */
+CONST('I', TCG_CT_CONST_ARM)
+CONST('K', TCG_CT_CONST_INV)
+CONST('N', TCG_CT_CONST_NEG)
+CONST('Z', TCG_CT_CONST_ZERO)
diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
index XXXXXXX..XXXXXXX 100644
--- a/tcg/arm/tcg-target.h
+++ b/tcg/arm/tcg-target.h
@@ -XXX,XX +XXX,XX @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t);
 #define TCG_TARGET_NEED_LDST_LABELS
 #endif
 #define TCG_TARGET_NEED_POOL_LABELS
+#define TCG_TARGET_CON_STR_H
 
 #endif
diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/arm/tcg-target.c.inc
+++ b/tcg/arm/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
 #define TCG_CT_CONST_NEG  0x400
 #define TCG_CT_CONST_ZERO 0x800
 
-/* parse target specific constraints */
-static const char *target_parse_constraint(TCGArgConstraint *ct,
-                                           const char *ct_str, TCGType type)
-{
-    switch (*ct_str++) {
-    case 'I':
-        ct->ct |= TCG_CT_CONST_ARM;
-        break;
-    case 'K':
-        ct->ct |= TCG_CT_CONST_INV;
-        break;
-    case 'N': /* The gcc constraint letter is L, already used here.  */
-        ct->ct |= TCG_CT_CONST_NEG;
-        break;
-    case 'Z':
-        ct->ct |= TCG_CT_CONST_ZERO;
-        break;
+#define ALL_GENERAL_REGS  0xffffu
 
-    case 'r':
-        ct->regs = 0xffff;
-        break;
-
-    /* qemu_ld address */
-    case 'l':
-        ct->regs = 0xffff;
+/*
+ * r0-r2 will be overwritten when reading the tlb entry (softmmu only)
+ * and r0-r1 doing the byte swapping, so don't use these.
+ * r3 is removed for softmmu to avoid clashes with helper arguments.
+ */
 #ifdef CONFIG_SOFTMMU
-        /* r0-r2,lr will be overwritten when reading the tlb entry,
-           so don't use these. */
-        tcg_regset_reset_reg(ct->regs, TCG_REG_R0);
-        tcg_regset_reset_reg(ct->regs, TCG_REG_R1);
-        tcg_regset_reset_reg(ct->regs, TCG_REG_R2);
-        tcg_regset_reset_reg(ct->regs, TCG_REG_R3);
-        tcg_regset_reset_reg(ct->regs, TCG_REG_R14);
+#define ALL_QLOAD_REGS \
+    (ALL_GENERAL_REGS & ~((1 << TCG_REG_R0) | (1 << TCG_REG_R1) | \
+                          (1 << TCG_REG_R2) | (1 << TCG_REG_R3) | \
+                          (1 << TCG_REG_R14)))
+#define ALL_QSTORE_REGS \
+    (ALL_GENERAL_REGS & ~((1 << TCG_REG_R0) | (1 << TCG_REG_R1) | \
+                          (1 << TCG_REG_R2) | (1 << TCG_REG_R14) | \
+                          ((TARGET_LONG_BITS == 64) << TCG_REG_R3)))
+#else
+#define ALL_QLOAD_REGS   ALL_GENERAL_REGS
+#define ALL_QSTORE_REGS \
+    (ALL_GENERAL_REGS & ~((1 << TCG_REG_R0) | (1 << TCG_REG_R1)))
 #endif
-        break;
-
-    /* qemu_st address & data */
-    case 's':
-        ct->regs = 0xffff;
-        /* r0-r2 will be overwritten when reading the tlb entry (softmmu only)
-           and r0-r1 doing the byte swapping, so don't use these. */
-        tcg_regset_reset_reg(ct->regs, TCG_REG_R0);
-        tcg_regset_reset_reg(ct->regs, TCG_REG_R1);
-#if defined(CONFIG_SOFTMMU)
-        /* Avoid clashes with registers being used for helper args */
-        tcg_regset_reset_reg(ct->regs, TCG_REG_R2);
-#if TARGET_LONG_BITS == 64
-        /* Avoid clashes with registers being used for helper args */
-        tcg_regset_reset_reg(ct->regs, TCG_REG_R3);
-#endif
-        tcg_regset_reset_reg(ct->regs, TCG_REG_R14);
-#endif
-        break;
-
-    default:
-        return NULL;
-    }
-    return ct_str;
-}
 
 static inline uint32_t rotl(uint32_t val, int n)
 {
-- 
2.25.1

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/aarch64/tcg-target-con-str.h | 24 +++++++++++++++
 tcg/aarch64/tcg-target.h         |  1 +
 tcg/aarch64/tcg-target.c.inc     | 51 +++++---------------------------
 3 files changed, 33 insertions(+), 43 deletions(-)
 create mode 100644 tcg/aarch64/tcg-target-con-str.h

diff --git a/tcg/aarch64/tcg-target-con-str.h b/tcg/aarch64/tcg-target-con-str.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/tcg/aarch64/tcg-target-con-str.h
@@ -XXX,XX +XXX,XX @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Define AArch64 target-specific operand constraints.
+ * Copyright (c) 2021 Linaro
+ */
+
+/*
+ * Define constraint letters for register sets:
+ * REGS(letter, register_mask)
+ */
+REGS('r', ALL_GENERAL_REGS)
+REGS('l', ALL_QLDST_REGS)
+REGS('w', ALL_VECTOR_REGS)
+
+/*
+ * Define constraint letters for constants:
+ * CONST(letter, TCG_CT_CONST_* bit set)
+ */
+CONST('A', TCG_CT_CONST_AIMM)
+CONST('L', TCG_CT_CONST_LIMM)
+CONST('M', TCG_CT_CONST_MONE)
+CONST('O', TCG_CT_CONST_ORRI)
+CONST('N', TCG_CT_CONST_ANDI)
+CONST('Z', TCG_CT_CONST_ZERO)
diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h
index XXXXXXX..XXXXXXX 100644
--- a/tcg/aarch64/tcg-target.h
+++ b/tcg/aarch64/tcg-target.h
@@ -XXX,XX +XXX,XX @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t);
 #define TCG_TARGET_NEED_LDST_LABELS
 #endif
 #define TCG_TARGET_NEED_POOL_LABELS
+#define TCG_TARGET_CON_STR_H
 
 #endif /* AARCH64_TCG_TARGET_H */
diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/aarch64/tcg-target.c.inc
+++ b/tcg/aarch64/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
 #define TCG_CT_CONST_ORRI 0x1000
 #define TCG_CT_CONST_ANDI 0x2000
 
-/* parse target specific constraints */
-static const char *target_parse_constraint(TCGArgConstraint *ct,
-                                           const char *ct_str, TCGType type)
-{
-    switch (*ct_str++) {
-    case 'r': /* general registers */
-        ct->regs |= 0xffffffffu;
-        break;
-    case 'w': /* advsimd registers */
-        ct->regs |= 0xffffffff00000000ull;
-        break;
-    case 'l': /* qemu_ld / qemu_st address, data_reg */
-        ct->regs = 0xffffffffu;
+#define ALL_GENERAL_REGS  0xffffffffu
+#define ALL_VECTOR_REGS   0xffffffff00000000ull
+
 #ifdef CONFIG_SOFTMMU
-        /* x0 and x1 will be overwritten when reading the tlb entry,
-           and x2, and x3 for helper args, better to avoid using them. */
-        tcg_regset_reset_reg(ct->regs, TCG_REG_X0);
-        tcg_regset_reset_reg(ct->regs, TCG_REG_X1);
-        tcg_regset_reset_reg(ct->regs, TCG_REG_X2);
-        tcg_regset_reset_reg(ct->regs, TCG_REG_X3);
+#define ALL_QLDST_REGS \
+    (ALL_GENERAL_REGS & ~((1 << TCG_REG_X0) | (1 << TCG_REG_X1) | \
+                          (1 << TCG_REG_X2) | (1 << TCG_REG_X3)))
+#else
+#define ALL_QLDST_REGS   ALL_GENERAL_REGS
 #endif
-        break;
-    case 'A': /* Valid for arithmetic immediate (positive or negative).  */
-        ct->ct |= TCG_CT_CONST_AIMM;
-        break;
-    case 'L': /* Valid for logical immediate.  */
-        ct->ct |= TCG_CT_CONST_LIMM;
-        break;
-    case 'M': /* minus one */
-        ct->ct |= TCG_CT_CONST_MONE;
-        break;
-    case 'O': /* vector orr/bic immediate */
-        ct->ct |= TCG_CT_CONST_ORRI;
-        break;
-    case 'N': /* vector orr/bic immediate, inverted */
-        ct->ct |= TCG_CT_CONST_ANDI;
-        break;
-    case 'Z': /* zero */
-        ct->ct |= TCG_CT_CONST_ZERO;
-        break;
-    default:
-        return NULL;
-    }
-    return ct_str;
-}
 
 /* Match a constant valid for addition (12-bit, optionally shifted).  */
 static inline bool is_aimm(uint64_t val)
-- 
2.25.1

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/ppc/tcg-target-con-str.h | 30 +++++++++++++++
 tcg/ppc/tcg-target.h         |  1 +
 tcg/ppc/tcg-target.c.inc     | 73 ++++++++----------------------------
 3 files changed, 46 insertions(+), 58 deletions(-)
 create mode 100644 tcg/ppc/tcg-target-con-str.h

diff --git a/tcg/ppc/tcg-target-con-str.h b/tcg/ppc/tcg-target-con-str.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/tcg/ppc/tcg-target-con-str.h
@@ -XXX,XX +XXX,XX @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Define PowerPC target-specific operand constraints.
+ * Copyright (c) 2021 Linaro
+ */
+
+/*
+ * Define constraint letters for register sets:
+ * REGS(letter, register_mask)
+ */
+REGS('r', ALL_GENERAL_REGS)
+REGS('v', ALL_VECTOR_REGS)
+REGS('A', 1u << TCG_REG_R3)
+REGS('B', 1u << TCG_REG_R4)
+REGS('C', 1u << TCG_REG_R5)
+REGS('D', 1u << TCG_REG_R6)
+REGS('L', ALL_QLOAD_REGS)
+REGS('S', ALL_QSTORE_REGS)
+
+/*
+ * Define constraint letters for constants:
+ * CONST(letter, TCG_CT_CONST_* bit set)
+ */
+CONST('I', TCG_CT_CONST_S16)
+CONST('J', TCG_CT_CONST_U16)
+CONST('M', TCG_CT_CONST_MONE)
+CONST('T', TCG_CT_CONST_S32)
+CONST('U', TCG_CT_CONST_U32)
+CONST('W', TCG_CT_CONST_WSZ)
+CONST('Z', TCG_CT_CONST_ZERO)
diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h
index XXXXXXX..XXXXXXX 100644
--- a/tcg/ppc/tcg-target.h
+++ b/tcg/ppc/tcg-target.h
@@ -XXX,XX +XXX,XX @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t);
 #define TCG_TARGET_NEED_LDST_LABELS
 #endif
 #define TCG_TARGET_NEED_POOL_LABELS
+#define TCG_TARGET_CON_STR_H
 
 #endif
diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/ppc/tcg-target.c.inc
+++ b/tcg/ppc/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@
 #define TCG_CT_CONST_MONE 0x2000
 #define TCG_CT_CONST_WSZ  0x4000
 
+#define ALL_GENERAL_REGS  0xffffffffu
+#define ALL_VECTOR_REGS   0xffffffff00000000ull
+
+#ifdef CONFIG_SOFTMMU
+#define ALL_QLOAD_REGS \
+    (ALL_GENERAL_REGS & \
+     ~((1 << TCG_REG_R3) | (1 << TCG_REG_R4) | (1 << TCG_REG_R5)))
+#define ALL_QSTORE_REGS \
+    (ALL_GENERAL_REGS & ~((1 << TCG_REG_R3) | (1 << TCG_REG_R4) | \
+                          (1 << TCG_REG_R5) | (1 << TCG_REG_R6)))
+#else
+#define ALL_QLOAD_REGS  (ALL_GENERAL_REGS & ~(1 << TCG_REG_R3))
+#define ALL_QSTORE_REGS ALL_QLOAD_REGS
+#endif
+
 TCGPowerISA have_isa;
 static bool have_isel;
 bool have_altivec;
@@ -XXX,XX +XXX,XX @@ static bool reloc_pc14(tcg_insn_unit *src_rw, const tcg_insn_unit *target)
     return false;
 }
 
-/* parse target specific constraints */
-static const char *target_parse_constraint(TCGArgConstraint *ct,
-                                           const char *ct_str, TCGType type)
-{
-    switch (*ct_str++) {
-    case 'A': case 'B': case 'C': case 'D':
-        tcg_regset_set_reg(ct->regs, 3 + ct_str[0] - 'A');
-        break;
-    case 'r':
-        ct->regs = 0xffffffff;
-        break;
-    case 'v':
-        ct->regs = 0xffffffff00000000ull;
-        break;
-    case 'L':                   /* qemu_ld constraint */
-        ct->regs = 0xffffffff;
-        tcg_regset_reset_reg(ct->regs, TCG_REG_R3);
-#ifdef CONFIG_SOFTMMU
-        tcg_regset_reset_reg(ct->regs, TCG_REG_R4);
-        tcg_regset_reset_reg(ct->regs, TCG_REG_R5);
-#endif
-        break;
-    case 'S':                   /* qemu_st constraint */
-        ct->regs = 0xffffffff;
-        tcg_regset_reset_reg(ct->regs, TCG_REG_R3);
-#ifdef CONFIG_SOFTMMU
-        tcg_regset_reset_reg(ct->regs, TCG_REG_R4);
-        tcg_regset_reset_reg(ct->regs, TCG_REG_R5);
-        tcg_regset_reset_reg(ct->regs, TCG_REG_R6);
-#endif
-        break;
-    case 'I':
-        ct->ct |= TCG_CT_CONST_S16;
-        break;
-    case 'J':
-        ct->ct |= TCG_CT_CONST_U16;
-        break;
-    case 'M':
-        ct->ct |= TCG_CT_CONST_MONE;
-        break;
-    case 'T':
-        ct->ct |= TCG_CT_CONST_S32;
-        break;
-    case 'U':
-        ct->ct |= TCG_CT_CONST_U32;
-        break;
-    case 'W':
-        ct->ct |= TCG_CT_CONST_WSZ;
-        break;
-    case 'Z':
-        ct->ct |= TCG_CT_CONST_ZERO;
-        break;
-    default:
-        return NULL;
-    }
-    return ct_str;
-}
-
 /* test if a constant matches the constraint */
 static int tcg_target_const_match(tcg_target_long val, TCGType type,
                                   const TCGArgConstraint *arg_ct)
-- 
2.25.1

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/tci/tcg-target-con-str.h | 11 +++++++++++
 tcg/tci/tcg-target.h         |  2 ++
 tcg/tci/tcg-target.c.inc     | 14 --------------
 3 files changed, 13 insertions(+), 14 deletions(-)
 create mode 100644 tcg/tci/tcg-target-con-str.h

diff --git a/tcg/tci/tcg-target-con-str.h b/tcg/tci/tcg-target-con-str.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/tcg/tci/tcg-target-con-str.h
@@ -XXX,XX +XXX,XX @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Define TCI target-specific operand constraints.
+ * Copyright (c) 2021 Linaro
+ */
+
+/*
+ * Define constraint letters for register sets:
+ * REGS(letter, register_mask)
+ */
+REGS('r', MAKE_64BIT_MASK(0, TCG_TARGET_NB_REGS))
diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h
index XXXXXXX..XXXXXXX 100644
--- a/tcg/tci/tcg-target.h
+++ b/tcg/tci/tcg-target.h
@@ -XXX,XX +XXX,XX @@ static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_rx,
     /* no need to flush icache explicitly */
 }
 
+#define TCG_TARGET_CON_STR_H
+
 #endif /* TCG_TARGET_H */
diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/tci/tcg-target.c.inc
+++ b/tcg/tci/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
     return true;
 }
 
-/* Parse target specific constraints. */
-static const char *target_parse_constraint(TCGArgConstraint *ct,
-                                           const char *ct_str, TCGType type)
-{
-    switch (*ct_str++) {
-    case 'r':
-        ct->regs = BIT(TCG_TARGET_NB_REGS) - 1;
-        break;
-    default:
-        return NULL;
-    }
-    return ct_str;
-}
-
 #if defined(CONFIG_DEBUG_TCG_INTERPRETER)
 /* Show current bytecode. Used by tcg interpreter. */
 void tci_disas(uint8_t opc)
-- 
2.25.1

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/mips/tcg-target-con-str.h | 24 +++++++++++
 tcg/mips/tcg-target.h         |  1 +
 tcg/mips/tcg-target.c.inc     | 77 ++++++++++-------------------------
 3 files changed, 46 insertions(+), 56 deletions(-)
 create mode 100644 tcg/mips/tcg-target-con-str.h

diff --git a/tcg/mips/tcg-target-con-str.h b/tcg/mips/tcg-target-con-str.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/tcg/mips/tcg-target-con-str.h
@@ -XXX,XX +XXX,XX @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Define MIPS target-specific operand constraints.
+ * Copyright (c) 2021 Linaro
+ */
+
+/*
+ * Define constraint letters for register sets:
+ * REGS(letter, register_mask)
+ */
+REGS('r', ALL_GENERAL_REGS)
+REGS('L', ALL_QLOAD_REGS)
+REGS('S', ALL_QSTORE_REGS)
+
+/*
+ * Define constraint letters for constants:
+ * CONST(letter, TCG_CT_CONST_* bit set)
+ */
+CONST('I', TCG_CT_CONST_U16)
+CONST('J', TCG_CT_CONST_S16)
+CONST('K', TCG_CT_CONST_P2M1)
+CONST('N', TCG_CT_CONST_N16)
+CONST('W', TCG_CT_CONST_WSZ)
+CONST('Z', TCG_CT_CONST_ZERO)
diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h
index XXXXXXX..XXXXXXX 100644
--- a/tcg/mips/tcg-target.h
+++ b/tcg/mips/tcg-target.h
@@ -XXX,XX +XXX,XX @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t);
 #ifdef CONFIG_SOFTMMU
 #define TCG_TARGET_NEED_LDST_LABELS
 #endif
+#define TCG_TARGET_CON_STR_H
 
 #endif
diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/mips/tcg-target.c.inc
+++ b/tcg/mips/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
 #define TCG_CT_CONST_N16  0x1000   /* "Negatable" 16-bit: -32767 - 32767 */
 #define TCG_CT_CONST_WSZ  0x2000   /* word size */
 
+#define ALL_GENERAL_REGS  0xffffffffu
+#define NOA0_REGS         (ALL_GENERAL_REGS & ~(1 << TCG_REG_A0))
+
+#ifdef CONFIG_SOFTMMU
+#define ALL_QLOAD_REGS \
+    (NOA0_REGS & ~((TCG_TARGET_REG_BITS < TARGET_LONG_BITS) << TCG_REG_A2))
+#define ALL_QSTORE_REGS \
+    (NOA0_REGS & ~(TCG_TARGET_REG_BITS < TARGET_LONG_BITS   \
+                   ? (1 << TCG_REG_A2) | (1 << TCG_REG_A3)  \
+                   : (1 << TCG_REG_A1)))
+#else
+#define ALL_QLOAD_REGS   NOA0_REGS
+#define ALL_QSTORE_REGS  NOA0_REGS
+#endif
+
+
 static inline bool is_p2m1(tcg_target_long val)
 {
     return val && ((val + 1) & val) == 0;
 }
 
-/* parse target specific constraints */
-static const char *target_parse_constraint(TCGArgConstraint *ct,
-                                           const char *ct_str, TCGType type)
-{
-    switch(*ct_str++) {
-    case 'r':
-        ct->regs = 0xffffffff;
-        break;
-    case 'L': /* qemu_ld input arg constraint */
-        ct->regs = 0xffffffff;
-        tcg_regset_reset_reg(ct->regs, TCG_REG_A0);
-#if defined(CONFIG_SOFTMMU)
-        if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
-            tcg_regset_reset_reg(ct->regs, TCG_REG_A2);
-        }
-#endif
-        break;
-    case 'S': /* qemu_st constraint */
-        ct->regs = 0xffffffff;
-        tcg_regset_reset_reg(ct->regs, TCG_REG_A0);
-#if defined(CONFIG_SOFTMMU)
-        if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
-            tcg_regset_reset_reg(ct->regs, TCG_REG_A2);
-            tcg_regset_reset_reg(ct->regs, TCG_REG_A3);
-        } else {
-            tcg_regset_reset_reg(ct->regs, TCG_REG_A1);
-        }
-#endif
-        break;
-    case 'I':
-        ct->ct |= TCG_CT_CONST_U16;
-        break;
-    case 'J':
-        ct->ct |= TCG_CT_CONST_S16;
-        break;
-    case 'K':
-        ct->ct |= TCG_CT_CONST_P2M1;
-        break;
-    case 'N':
-        ct->ct |= TCG_CT_CONST_N16;
-        break;
-    case 'W':
-        ct->ct |= TCG_CT_CONST_WSZ;
-        break;
-    case 'Z':
-        /* We are cheating a bit here, using the fact that the register
-           ZERO is also the register number 0. Hence there is no need
-           to check for const_args in each instruction. */
-        ct->ct |= TCG_CT_CONST_ZERO;
-        break;
-    default:
-        return NULL;
-    }
-    return ct_str;
-}
-
 /* test if a constant matches the constraint */
 static inline int tcg_target_const_match(tcg_target_long val, TCGType type,
                                          const TCGArgConstraint *arg_ct)
@@ -XXX,XX +XXX,XX @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
     TCGArg a0, a1, a2;
     int c2;
 
+    /*
+     * Note that many operands use the constraint set "rZ".
+     * We make use of the fact that 0 is the ZERO register,
+     * and hence such cases need not check for const_args.
+     */
     a0 = args[0];
     a1 = args[1];
     a2 = args[2];
-- 
2.25.1

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/riscv/tcg-target-con-str.h | 21 ++++++++++++++
 tcg/riscv/tcg-target.h         |  1 +
 tcg/riscv/tcg-target.c.inc     | 52 +++++++++-------------------------
 3 files changed, 35 insertions(+), 39 deletions(-)
 create mode 100644 tcg/riscv/tcg-target-con-str.h

diff --git a/tcg/riscv/tcg-target-con-str.h b/tcg/riscv/tcg-target-con-str.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/tcg/riscv/tcg-target-con-str.h
@@ -XXX,XX +XXX,XX @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Define RISC-V target-specific operand constraints.
+ * Copyright (c) 2021 Linaro
+ */
+
+/*
+ * Define constraint letters for register sets:
+ * REGS(letter, register_mask)
+ */
+REGS('r', ALL_GENERAL_REGS)
+REGS('L', ALL_GENERAL_REGS & ~SOFTMMU_RESERVE_REGS)
+
+/*
+ * Define constraint letters for constants:
+ * CONST(letter, TCG_CT_CONST_* bit set)
+ */
+CONST('I', TCG_CT_CONST_S12)
+CONST('N', TCG_CT_CONST_N12)
+CONST('M', TCG_CT_CONST_M12)
+CONST('Z', TCG_CT_CONST_ZERO)
diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h
index XXXXXXX..XXXXXXX 100644
--- a/tcg/riscv/tcg-target.h
+++ b/tcg/riscv/tcg-target.h
@@ -XXX,XX +XXX,XX @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t);
 #define TCG_TARGET_NEED_POOL_LABELS
 
 #define TCG_TARGET_HAS_MEMORY_BSWAP 0
+#define TCG_TARGET_CON_STR_H
 
 #endif
diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/riscv/tcg-target.c.inc
+++ b/tcg/riscv/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ static const int tcg_target_call_oarg_regs[] = {
 #define TCG_CT_CONST_N12   0x400
 #define TCG_CT_CONST_M12   0x800
 
+#define ALL_GENERAL_REGS      MAKE_64BIT_MASK(0, 32)
+/*
+ * For softmmu, we need to avoid conflicts with the first 5
+ * argument registers to call the helper.  Some of these are
+ * also used for the tlb lookup.
+ */
+#ifdef CONFIG_SOFTMMU
+#define SOFTMMU_RESERVE_REGS  MAKE_64BIT_MASK(TCG_REG_A0, 5)
+#else
+#define SOFTMMU_RESERVE_REGS  0
+#endif
+
+
 static inline tcg_target_long sextreg(tcg_target_long val, int pos, int len)
 {
     if (TCG_TARGET_REG_BITS == 32) {
@@ -XXX,XX +XXX,XX @@ static inline tcg_target_long sextreg(tcg_target_long val, int pos, int len)
     }
 }
 
-/* parse target specific constraints */
-static const char *target_parse_constraint(TCGArgConstraint *ct,
-                                           const char *ct_str, TCGType type)
-{
-    switch (*ct_str++) {
-    case 'r':
-        ct->regs = 0xffffffff;
-        break;
-    case 'L':
-        /* qemu_ld/qemu_st constraint */
-        ct->regs = 0xffffffff;
-        /* qemu_ld/qemu_st uses TCG_REG_TMP0 */
-#if defined(CONFIG_SOFTMMU)
-        tcg_regset_reset_reg(ct->regs, tcg_target_call_iarg_regs[0]);
-        tcg_regset_reset_reg(ct->regs, tcg_target_call_iarg_regs[1]);
-        tcg_regset_reset_reg(ct->regs, tcg_target_call_iarg_regs[2]);
-        tcg_regset_reset_reg(ct->regs, tcg_target_call_iarg_regs[3]);
-        tcg_regset_reset_reg(ct->regs, tcg_target_call_iarg_regs[4]);
-#endif
-        break;
-    case 'I':
-        ct->ct |= TCG_CT_CONST_S12;
-        break;
-    case 'N':
-        ct->ct |= TCG_CT_CONST_N12;
-        break;
-    case 'M':
-        ct->ct |= TCG_CT_CONST_M12;
-        break;
-    case 'Z':
-        /* we can use a zero immediate as a zero register argument. */
-        ct->ct |= TCG_CT_CONST_ZERO;
-        break;
-    default:
-        return NULL;
-    }
-    return ct_str;
-}
-
 /* test if a constant matches the constraint */
 static int tcg_target_const_match(tcg_target_long val, TCGType type,
                                   const TCGArgConstraint *arg_ct)
-- 
2.25.1

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/s390/tcg-target-con-str.h | 28 ++++++++++++++++++
 tcg/s390/tcg-target.h         |  1 +
 tcg/s390/tcg-target.c.inc     | 53 +++++++++--------------------------
 3 files changed, 42 insertions(+), 40 deletions(-)
 create mode 100644 tcg/s390/tcg-target-con-str.h

diff --git a/tcg/s390/tcg-target-con-str.h b/tcg/s390/tcg-target-con-str.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/tcg/s390/tcg-target-con-str.h
@@ -XXX,XX +XXX,XX @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Define S390 target-specific operand constraints.
+ * Copyright (c) 2021 Linaro
+ */
+
+/*
+ * Define constraint letters for register sets:
+ * REGS(letter, register_mask)
+ */
+REGS('r', ALL_GENERAL_REGS)
+REGS('L', ALL_GENERAL_REGS & ~SOFTMMU_RESERVE_REGS)
+/*
+ * A (single) even/odd pair for division.
+ * TODO: Add something to the register allocator to allow
+ * this kind of regno+1 pairing to be done more generally.
+ */
+REGS('a', 1u << TCG_REG_R2)
+REGS('b', 1u << TCG_REG_R3)
+
+/*
+ * Define constraint letters for constants:
+ * CONST(letter, TCG_CT_CONST_* bit set)
+ */
+CONST('A', TCG_CT_CONST_S33)
+CONST('I', TCG_CT_CONST_S16)
+CONST('J', TCG_CT_CONST_S32)
+CONST('Z', TCG_CT_CONST_ZERO)
diff --git a/tcg/s390/tcg-target.h b/tcg/s390/tcg-target.h
index XXXXXXX..XXXXXXX 100644
--- a/tcg/s390/tcg-target.h
+++ b/tcg/s390/tcg-target.h
@@ -XXX,XX +XXX,XX @@ static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_rx,
 #define TCG_TARGET_NEED_LDST_LABELS
 #endif
 #define TCG_TARGET_NEED_POOL_LABELS
+#define TCG_TARGET_CON_STR_H
 
 #endif
diff --git a/tcg/s390/tcg-target.c.inc b/tcg/s390/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/s390/tcg-target.c.inc
+++ b/tcg/s390/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@
 #define TCG_CT_CONST_S33   0x400
 #define TCG_CT_CONST_ZERO  0x800
 
+#define ALL_GENERAL_REGS     MAKE_64BIT_MASK(0, 16)
+/*
+ * For softmmu, we need to avoid conflicts with the first 3
+ * argument registers to perform the tlb lookup, and to call
+ * the helper function.
+ */
+#ifdef CONFIG_SOFTMMU
+#define SOFTMMU_RESERVE_REGS MAKE_64BIT_MASK(TCG_REG_R2, 3)
+#else
+#define SOFTMMU_RESERVE_REGS 0
+#endif
+
+
 /* Several places within the instruction set 0 means "no register"
    rather than TCG_REG_R0.  */
 #define TCG_REG_NONE    0
@@ -XXX,XX +XXX,XX @@ static bool patch_reloc(tcg_insn_unit *src_rw, int type,
     return false;
 }
 
-/* parse target specific constraints */
-static const char *target_parse_constraint(TCGArgConstraint *ct,
-                                           const char *ct_str, TCGType type)
-{
-    switch (*ct_str++) {
-    case 'r':                  /* all registers */
-        ct->regs = 0xffff;
-        break;
-    case 'L':                  /* qemu_ld/st constraint */
-        ct->regs = 0xffff;
-        tcg_regset_reset_reg(ct->regs, TCG_REG_R2);
-        tcg_regset_reset_reg(ct->regs, TCG_REG_R3);
-        tcg_regset_reset_reg(ct->regs, TCG_REG_R4);
-        break;
-    case 'a':                  /* force R2 for division */
-        ct->regs = 0;
-        tcg_regset_set_reg(ct->regs, TCG_REG_R2);
-        break;
-    case 'b':                  /* force R3 for division */
-        ct->regs = 0;
-        tcg_regset_set_reg(ct->regs, TCG_REG_R3);
-        break;
-    case 'A':
-        ct->ct |= TCG_CT_CONST_S33;
-        break;
-    case 'I':
-        ct->ct |= TCG_CT_CONST_S16;
-        break;
-    case 'J':
-        ct->ct |= TCG_CT_CONST_S32;
-        break;
-    case 'Z':
-        ct->ct |= TCG_CT_CONST_ZERO;
-        break;
-    default:
-        return NULL;
-    }
-    return ct_str;
-}
-
 /* Test if a constant matches the constraint. */
 static int tcg_target_const_match(tcg_target_long val, TCGType type,
                                   const TCGArgConstraint *arg_ct)
-- 
2.25.1

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/sparc/tcg-target-con-str.h | 23 ++++++++++
 tcg/sparc/tcg-target.h         |  5 +--
 tcg/sparc/tcg-target.c.inc     | 81 +++++++++++++---------------------
 3 files changed, 55 insertions(+), 54 deletions(-)
 create mode 100644 tcg/sparc/tcg-target-con-str.h

diff --git a/tcg/sparc/tcg-target-con-str.h b/tcg/sparc/tcg-target-con-str.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/tcg/sparc/tcg-target-con-str.h
@@ -XXX,XX +XXX,XX @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Define Sparc target-specific operand constraints.
+ * Copyright (c) 2021 Linaro
+ */
+
+/*
+ * Define constraint letters for register sets:
+ * REGS(letter, register_mask)
+ */
+REGS('r', ALL_GENERAL_REGS)
+REGS('R', ALL_GENERAL_REGS64)
+REGS('s', ALL_QLDST_REGS)
+REGS('S', ALL_QLDST_REGS64)
+REGS('A', TARGET_LONG_BITS == 64 ? ALL_QLDST_REGS64 : ALL_QLDST_REGS)
+
+/*
+ * Define constraint letters for constants:
+ * CONST(letter, TCG_CT_CONST_* bit set)
+ */
+CONST('I', TCG_CT_CONST_S11)
+CONST('J', TCG_CT_CONST_S13)
+CONST('Z', TCG_CT_CONST_ZERO)
diff --git a/tcg/sparc/tcg-target.h b/tcg/sparc/tcg-target.h
index XXXXXXX..XXXXXXX 100644
--- a/tcg/sparc/tcg-target.h
+++ b/tcg/sparc/tcg-target.h
@@ -XXX,XX +XXX,XX @@ typedef enum {
     TCG_REG_I7,
 } TCGReg;
 
-#define TCG_CT_CONST_S11  0x100
-#define TCG_CT_CONST_S13  0x200
-#define TCG_CT_CONST_ZERO 0x400
-
 /* used for function call generation */
 #define TCG_REG_CALL_STACK TCG_REG_O6
 
@@ -XXX,XX +XXX,XX @@ extern bool use_vis3_instructions;
 void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t);
 
 #define TCG_TARGET_NEED_POOL_LABELS
+#define TCG_TARGET_CON_STR_H
 
 #endif
diff --git a/tcg/sparc/tcg-target.c.inc b/tcg/sparc/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/sparc/tcg-target.c.inc
+++ b/tcg/sparc/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
 # define SPARC64 0
 #endif
 
-/* Note that sparcv8plus can only hold 64 bit quantities in %g and %o
-   registers.  These are saved manually by the kernel in full 64-bit
-   slots.  The %i and %l registers are saved by the register window
-   mechanism, which only allocates space for 32 bits.  Given that this
-   window spill/fill can happen on any signal, we must consider the
-   high bits of the %i and %l registers garbage at all times.  */
-#if SPARC64
-# define ALL_64  0xffffffffu
+#define TCG_CT_CONST_S11  0x100
+#define TCG_CT_CONST_S13  0x200
+#define TCG_CT_CONST_ZERO 0x400
+
+/*
+ * For softmmu, we need to avoid conflicts with the first 3
+ * argument registers to perform the tlb lookup, and to call
+ * the helper function.
+ */
+#ifdef CONFIG_SOFTMMU
+#define SOFTMMU_RESERVE_REGS MAKE_64BIT_MASK(TCG_REG_O0, 3)
 #else
-# define ALL_64  0xffffu
+#define SOFTMMU_RESERVE_REGS 0
 #endif
 
+/*
+ * Note that sparcv8plus can only hold 64 bit quantities in %g and %o
+ * registers.  These are saved manually by the kernel in full 64-bit
+ * slots.  The %i and %l registers are saved by the register window
+ * mechanism, which only allocates space for 32 bits.  Given that this
+ * window spill/fill can happen on any signal, we must consider the
+ * high bits of the %i and %l registers garbage at all times.
+ */
+#define ALL_GENERAL_REGS     MAKE_64BIT_MASK(0, 32)
+#if SPARC64
+# define ALL_GENERAL_REGS64  ALL_GENERAL_REGS
+#else
+# define ALL_GENERAL_REGS64  MAKE_64BIT_MASK(0, 16)
+#endif
+#define ALL_QLDST_REGS       (ALL_GENERAL_REGS & ~SOFTMMU_RESERVE_REGS)
+#define ALL_QLDST_REGS64     (ALL_GENERAL_REGS64 & ~SOFTMMU_RESERVE_REGS)
+
 /* Define some temporary registers.  T2 is used for constant generation.  */
 #define TCG_REG_T1  TCG_REG_G1
 #define TCG_REG_T2  TCG_REG_O7
@@ -XXX,XX +XXX,XX @@ static bool patch_reloc(tcg_insn_unit *src_rw, int type,
     return true;
 }
 
-/* parse target specific constraints */
-static const char *target_parse_constraint(TCGArgConstraint *ct,
-                                           const char *ct_str, TCGType type)
-{
-    switch (*ct_str++) {
-    case 'r':
-        ct->regs = 0xffffffff;
-        break;
-    case 'R':
-        ct->regs = ALL_64;
-        break;
-    case 'A': /* qemu_ld/st address constraint */
-        ct->regs = TARGET_LONG_BITS == 64 ? ALL_64 : 0xffffffff;
-    reserve_helpers:
-        tcg_regset_reset_reg(ct->regs, TCG_REG_O0);
-        tcg_regset_reset_reg(ct->regs, TCG_REG_O1);
-        tcg_regset_reset_reg(ct->regs, TCG_REG_O2);
-        break;
-    case 's': /* qemu_st data 32-bit constraint */
-        ct->regs = 0xffffffff;
-        goto reserve_helpers;
-    case 'S': /* qemu_st data 64-bit constraint */
-        ct->regs = ALL_64;
-        goto reserve_helpers;
-    case 'I':
-        ct->ct |= TCG_CT_CONST_S11;
-        break;
-    case 'J':
-        ct->ct |= TCG_CT_CONST_S13;
-        break;
-    case 'Z':
-        ct->ct |= TCG_CT_CONST_ZERO;
-        break;
-    default:
-        return NULL;
-    }
-    return ct_str;
-}
-
 /* test if a constant matches the constraint */
 static inline int tcg_target_const_match(tcg_target_long val, TCGType type,
                                          const TCGArgConstraint *arg_ct)
@@ -XXX,XX +XXX,XX @@ static void tcg_target_init(TCGContext *s)
     }
 #endif
 
-    tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffff;
-    tcg_target_available_regs[TCG_TYPE_I64] = ALL_64;
+    tcg_target_available_regs[TCG_TYPE_I32] = ALL_GENERAL_REGS;
+    tcg_target_available_regs[TCG_TYPE_I64] = ALL_GENERAL_REGS64;
 
     tcg_target_call_clobber_regs = 0;
     tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_G1);
-- 
2.25.1

All backends have now been converted to tcg-target-con-str.h,
so we can remove the fallback code.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/aarch64/tcg-target.h |  1 -
 tcg/arm/tcg-target.h     |  1 -
 tcg/i386/tcg-target.h    |  1 -
 tcg/mips/tcg-target.h    |  1 -
 tcg/ppc/tcg-target.h     |  1 -
 tcg/riscv/tcg-target.h   |  1 -
 tcg/s390/tcg-target.h    |  1 -
 tcg/sparc/tcg-target.h   |  1 -
 tcg/tci/tcg-target.h     |  2 --
 tcg/tcg.c                | 16 ----------------
 10 files changed, 26 deletions(-)

diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h
index XXXXXXX..XXXXXXX 100644
--- a/tcg/aarch64/tcg-target.h
+++ b/tcg/aarch64/tcg-target.h
@@ -XXX,XX +XXX,XX @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t);
 #define TCG_TARGET_NEED_LDST_LABELS
 #endif
 #define TCG_TARGET_NEED_POOL_LABELS
-#define TCG_TARGET_CON_STR_H
 
 #endif /* AARCH64_TCG_TARGET_H */
diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
index XXXXXXX..XXXXXXX 100644
--- a/tcg/arm/tcg-target.h
+++ b/tcg/arm/tcg-target.h
@@ -XXX,XX +XXX,XX @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t);
 #define TCG_TARGET_NEED_LDST_LABELS
 #endif
 #define TCG_TARGET_NEED_POOL_LABELS
-#define TCG_TARGET_CON_STR_H
 
 #endif
diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h
index XXXXXXX..XXXXXXX 100644
--- a/tcg/i386/tcg-target.h
+++ b/tcg/i386/tcg-target.h
@@ -XXX,XX +XXX,XX @@ static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_rx,
 #define TCG_TARGET_NEED_LDST_LABELS
 #endif
 #define TCG_TARGET_NEED_POOL_LABELS
-#define TCG_TARGET_CON_STR_H
 
 #endif
diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h
index XXXXXXX..XXXXXXX 100644
--- a/tcg/mips/tcg-target.h
+++ b/tcg/mips/tcg-target.h
@@ -XXX,XX +XXX,XX @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t);
 #ifdef CONFIG_SOFTMMU
 #define TCG_TARGET_NEED_LDST_LABELS
 #endif
-#define TCG_TARGET_CON_STR_H
 
 #endif
diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h
index XXXXXXX..XXXXXXX 100644
--- a/tcg/ppc/tcg-target.h
+++ b/tcg/ppc/tcg-target.h
@@ -XXX,XX +XXX,XX @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t);
 #define TCG_TARGET_NEED_LDST_LABELS
 #endif
 #define TCG_TARGET_NEED_POOL_LABELS
-#define TCG_TARGET_CON_STR_H
 
 #endif
diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h
index XXXXXXX..XXXXXXX 100644
--- a/tcg/riscv/tcg-target.h
+++ b/tcg/riscv/tcg-target.h
@@ -XXX,XX +XXX,XX @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t);
 #define TCG_TARGET_NEED_POOL_LABELS
 
 #define TCG_TARGET_HAS_MEMORY_BSWAP 0
-#define TCG_TARGET_CON_STR_H
 
 #endif
diff --git a/tcg/s390/tcg-target.h b/tcg/s390/tcg-target.h
index XXXXXXX..XXXXXXX 100644
--- a/tcg/s390/tcg-target.h
+++ b/tcg/s390/tcg-target.h
@@ -XXX,XX +XXX,XX @@ static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_rx,
 #define TCG_TARGET_NEED_LDST_LABELS
 #endif
 #define TCG_TARGET_NEED_POOL_LABELS
-#define TCG_TARGET_CON_STR_H
 
 #endif
diff --git a/tcg/sparc/tcg-target.h b/tcg/sparc/tcg-target.h
index XXXXXXX..XXXXXXX 100644
--- a/tcg/sparc/tcg-target.h
+++ b/tcg/sparc/tcg-target.h
@@ -XXX,XX +XXX,XX @@ extern bool use_vis3_instructions;
 void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t);
 
 #define TCG_TARGET_NEED_POOL_LABELS
-#define TCG_TARGET_CON_STR_H
 
 #endif
diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h
index XXXXXXX..XXXXXXX 100644
--- a/tcg/tci/tcg-target.h
+++ b/tcg/tci/tcg-target.h
@@ -XXX,XX +XXX,XX @@ static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_rx,
     /* no need to flush icache explicitly */
 }
 
-#define TCG_TARGET_CON_STR_H
-
 #endif /* TCG_TARGET_H */
diff --git a/tcg/tcg.c b/tcg/tcg.c
index XXXXXXX..XXXXXXX 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -XXX,XX +XXX,XX @@ static void tcg_register_jit_int(const void *buf, size_t size,
     __attribute__((unused));
 
 /* Forward declarations for functions declared and used in tcg-target.c.inc. */
-#ifndef TCG_TARGET_CON_STR_H
-static const char *target_parse_constraint(TCGArgConstraint *ct,
-                                           const char *ct_str, TCGType type);
-#endif
 static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg1,
                        intptr_t arg2);
 static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg);
@@ -XXX,XX +XXX,XX @@ static void process_op_defs(TCGContext *s)
                     ct_str++;
                     break;
 
-#ifdef TCG_TARGET_CON_STR_H
                 /* Include all of the target-specific constraints. */
 
 #undef CONST
@@ -XXX,XX +XXX,XX @@ static void process_op_defs(TCGContext *s)
                 default:
                     /* Typo in TCGTargetOpDef constraint. */
                     g_assert_not_reached();
-#else
-                default:
-                    {
-                        TCGType type = (def->flags & TCG_OPF_64BIT
-                                        ? TCG_TYPE_I64 : TCG_TYPE_I32);
-                        ct_str = target_parse_constraint(&def->args_ct[i],
-                                                         ct_str, type);
-                        /* Typo in TCGTargetOpDef constraint. */
-                        tcg_debug_assert(ct_str != NULL);
-                    }
-#endif
                 }
             }
         }
-- 
2.25.1

This exports the constraint sets from tcg_target_op_def to
a place we will be able to manipulate more in future.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/i386/tcg-target-con-set.h |  55 ++++++++++
 tcg/i386/tcg-target.h         |   1 +
 tcg/tcg.c                     | 119 +++++++++++++++++++++
 tcg/i386/tcg-target.c.inc     | 194 ++++++++++++----------------------
 4 files changed, 242 insertions(+), 127 deletions(-)
 create mode 100644 tcg/i386/tcg-target-con-set.h

diff --git a/tcg/i386/tcg-target-con-set.h b/tcg/i386/tcg-target-con-set.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/tcg/i386/tcg-target-con-set.h
@@ -XXX,XX +XXX,XX @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Define i386 target-specific constraint sets.
+ * Copyright (c) 2021 Linaro
+ */
+
+/*
+ * C_On_Im(...) defines a constraint set with <n> outputs and <m> inputs.
+ * Each operand should be a sequence of constraint letters as defined by
+ * tcg-target-con-str.h; the constraint combination is inclusive or.
+ *
+ * C_N1_Im(...) defines a constraint set with 1 output and <m> inputs,
+ * except that the output must use a new register.
+ */
+C_O0_I1(r)
+C_O0_I2(L, L)
+C_O0_I2(qi, r)
+C_O0_I2(re, r)
+C_O0_I2(ri, r)
+C_O0_I2(r, re)
+C_O0_I2(s, L)
+C_O0_I2(x, r)
+C_O0_I3(L, L, L)
+C_O0_I3(s, L, L)
+C_O0_I4(L, L, L, L)
+C_O0_I4(r, r, ri, ri)
+C_O1_I1(r, 0)
+C_O1_I1(r, L)
+C_O1_I1(r, q)
+C_O1_I1(r, r)
+C_O1_I1(x, r)
+C_O1_I1(x, x)
+C_O1_I2(Q, 0, Q)
+C_O1_I2(q, r, re)
+C_O1_I2(r, 0, ci)
+C_O1_I2(r, 0, r)
+C_O1_I2(r, 0, re)
+C_O1_I2(r, 0, reZ)
+C_O1_I2(r, 0, ri)
+C_O1_I2(r, 0, rI)
+C_O1_I2(r, L, L)
+C_O1_I2(r, r, re)
+C_O1_I2(r, r, ri)
+C_O1_I2(r, r, rI)
+C_O1_I2(x, x, x)
+C_N1_I2(r, r, r)
+C_N1_I2(r, r, rW)
+C_O1_I3(x, x, x, x)
+C_O1_I4(r, r, re, r, 0)
+C_O1_I4(r, r, r, ri, ri)
+C_O2_I1(r, r, L)
+C_O2_I2(a, d, a, r)
+C_O2_I2(r, r, L, L)
+C_O2_I3(a, d, 0, 1, r)
+C_O2_I4(r, r, 0, 1, re, re)
diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h
index XXXXXXX..XXXXXXX 100644
--- a/tcg/i386/tcg-target.h
+++ b/tcg/i386/tcg-target.h
@@ -XXX,XX +XXX,XX @@ static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_rx,
 #define TCG_TARGET_NEED_LDST_LABELS
 #endif
 #define TCG_TARGET_NEED_POOL_LABELS
+#define TCG_TARGET_CON_SET_H
 
 #endif
diff --git a/tcg/tcg.c b/tcg/tcg.c
index XXXXXXX..XXXXXXX 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -XXX,XX +XXX,XX @@
 /* Forward declarations for functions declared in tcg-target.c.inc and
    used here. */
 static void tcg_target_init(TCGContext *s);
+#ifndef TCG_TARGET_CON_SET_H
 static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode);
+#endif
 static void tcg_target_qemu_prologue(TCGContext *s);
 static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
                         intptr_t value, intptr_t addend);
@@ -XXX,XX +XXX,XX @@ static void set_jmp_reset_offset(TCGContext *s, int which)
     s->tb_jmp_reset_offset[which] = tcg_current_code_size(s);
 }
 
+#ifdef TCG_TARGET_CON_SET_H
+#define C_PFX1(P, A)                    P##A
+#define C_PFX2(P, A, B)                 P##A##_##B
+#define C_PFX3(P, A, B, C)              P##A##_##B##_##C
+#define C_PFX4(P, A, B, C, D)           P##A##_##B##_##C##_##D
+#define C_PFX5(P, A, B, C, D, E)        P##A##_##B##_##C##_##D##_##E
+#define C_PFX6(P, A, B, C, D, E, F)     P##A##_##B##_##C##_##D##_##E##_##F
+
+/* Define an enumeration for the various combinations. */
+
+#define C_O0_I1(I1)                     C_PFX1(c_o0_i1_, I1),
+#define C_O0_I2(I1, I2)                 C_PFX2(c_o0_i2_, I1, I2),
+#define C_O0_I3(I1, I2, I3)             C_PFX3(c_o0_i3_, I1, I2, I3),
+#define C_O0_I4(I1, I2, I3, I4)         C_PFX4(c_o0_i4_, I1, I2, I3, I4),
+
+#define C_O1_I1(O1, I1)                 C_PFX2(c_o1_i1_, O1, I1),
+#define C_O1_I2(O1, I1, I2)             C_PFX3(c_o1_i2_, O1, I1, I2),
+#define C_O1_I3(O1, I1, I2, I3)         C_PFX4(c_o1_i3_, O1, I1, I2, I3),
+#define C_O1_I4(O1, I1, I2, I3, I4)     C_PFX5(c_o1_i4_, O1, I1, I2, I3, I4),
+
+#define C_N1_I2(O1, I1, I2)             C_PFX3(c_n1_i2_, O1, I1, I2),
+
+#define C_O2_I1(O1, O2, I1)             C_PFX3(c_o2_i1_, O1, O2, I1),
+#define C_O2_I2(O1, O2, I1, I2)         C_PFX4(c_o2_i2_, O1, O2, I1, I2),
+#define C_O2_I3(O1, O2, I1, I2, I3)     C_PFX5(c_o2_i3_, O1, O2, I1, I2, I3),
+#define C_O2_I4(O1, O2, I1, I2, I3, I4) C_PFX6(c_o2_i4_, O1, O2, I1, I2, I3, I4),
+
+typedef enum {
+#include "tcg-target-con-set.h"
+} TCGConstraintSetIndex;
+
+static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode);
+
+#undef C_O0_I1
+#undef C_O0_I2
+#undef C_O0_I3
+#undef C_O0_I4
+#undef C_O1_I1
+#undef C_O1_I2
+#undef C_O1_I3
+#undef C_O1_I4
+#undef C_N1_I2
+#undef C_O2_I1
+#undef C_O2_I2
+#undef C_O2_I3
+#undef C_O2_I4
+
+/* Put all of the constraint sets into an array, indexed by the enum. */
+
+#define C_O0_I1(I1)                     { .args_ct_str = { #I1 } },
+#define C_O0_I2(I1, I2)                 { .args_ct_str = { #I1, #I2 } },
+#define C_O0_I3(I1, I2, I3)             { .args_ct_str = { #I1, #I2, #I3 } },
+#define C_O0_I4(I1, I2, I3, I4)         { .args_ct_str = { #I1, #I2, #I3, #I4 } },
+
+#define C_O1_I1(O1, I1)                 { .args_ct_str = { #O1, #I1 } },
+#define C_O1_I2(O1, I1, I2)             { .args_ct_str = { #O1, #I1, #I2 } },
+#define C_O1_I3(O1, I1, I2, I3)         { .args_ct_str = { #O1, #I1, #I2, #I3 } },
+#define C_O1_I4(O1, I1, I2, I3, I4)     { .args_ct_str = { #O1, #I1, #I2, #I3, #I4 } },
+
+#define C_N1_I2(O1, I1, I2)             { .args_ct_str = { "&" #O1, #I1, #I2 } },
+
+#define C_O2_I1(O1, O2, I1)             { .args_ct_str = { #O1, #O2, #I1 } },
+#define C_O2_I2(O1, O2, I1, I2)         { .args_ct_str = { #O1, #O2, #I1, #I2 } },
+#define C_O2_I3(O1, O2, I1, I2, I3)     { .args_ct_str = { #O1, #O2, #I1, #I2, #I3 } },
+#define C_O2_I4(O1, O2, I1, I2, I3, I4) { .args_ct_str = { #O1, #O2, #I1, #I2, #I3, #I4 } },
+
+static const TCGTargetOpDef constraint_sets[] = {
+#include "tcg-target-con-set.h"
+};
+
+
+#undef C_O0_I1
+#undef C_O0_I2
+#undef C_O0_I3
+#undef C_O0_I4
+#undef C_O1_I1
+#undef C_O1_I2
+#undef C_O1_I3
+#undef C_O1_I4
+#undef C_N1_I2
+#undef C_O2_I1
+#undef C_O2_I2
+#undef C_O2_I3
+#undef C_O2_I4
+
+/* Expand the enumerator to be returned from tcg_target_op_def(). */
+
+#define C_O0_I1(I1)                     C_PFX1(c_o0_i1_, I1)
+#define C_O0_I2(I1, I2)                 C_PFX2(c_o0_i2_, I1, I2)
+#define C_O0_I3(I1, I2, I3)             C_PFX3(c_o0_i3_, I1, I2, I3)
+#define C_O0_I4(I1, I2, I3, I4)         C_PFX4(c_o0_i4_, I1, I2, I3, I4)
+
+#define C_O1_I1(O1, I1)                 C_PFX2(c_o1_i1_, O1, I1)
+#define C_O1_I2(O1, I1, I2)             C_PFX3(c_o1_i2_, O1, I1, I2)
+#define C_O1_I3(O1, I1, I2, I3)         C_PFX4(c_o1_i3_, O1, I1, I2, I3)
+#define C_O1_I4(O1, I1, I2, I3, I4)     C_PFX5(c_o1_i4_, O1, I1, I2, I3, I4)
+
+#define C_N1_I2(O1, I1, I2)             C_PFX3(c_n1_i2_, O1, I1, I2)
+
+#define C_O2_I1(O1, O2, I1)             C_PFX3(c_o2_i1_, O1, O2, I1)
+#define C_O2_I2(O1, O2, I1, I2)         C_PFX4(c_o2_i2_, O1, O2, I1, I2)
+#define C_O2_I3(O1, O2, I1, I2, I3)     C_PFX5(c_o2_i3_, O1, O2, I1, I2, I3)
+#define C_O2_I4(O1, O2, I1, I2, I3, I4) C_PFX6(c_o2_i4_, O1, O2, I1, I2, I3, I4)
+
+#endif /* TCG_TARGET_CON_SET_H */
+
 #include "tcg-target.c.inc"
 
 /* compare a pointer @ptr and a tb_tc @s */
@@ -XXX,XX +XXX,XX @@ static void process_op_defs(TCGContext *s)
             continue;
         }
 
+#ifdef TCG_TARGET_CON_SET_H
+        /*
+         * Macro magic should make it impossible, but double-check that
+         * the array index is in range.  Since the signness of an enum
+         * is implementation defined, force the result to unsigned.
+         */
+        unsigned con_set = tcg_target_op_def(op);
+        tcg_debug_assert(con_set < ARRAY_SIZE(constraint_sets));
+        tdefs = &constraint_sets[con_set];
+#else
         tdefs = tcg_target_op_def(op);
         /* Missing TCGTargetOpDef entry. */
         tcg_debug_assert(tdefs != NULL);
+#endif
 
         for (i = 0; i < nb_args; i++) {
             const char *ct_str = tdefs->args_ct_str[i];
diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/i386/tcg-target.c.inc
+++ b/tcg/i386/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
     }
 }
 
-static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
+static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
 {
-    static const TCGTargetOpDef r = { .args_ct_str = { "r" } };
-    static const TCGTargetOpDef ri_r = { .args_ct_str = { "ri", "r" } };
-    static const TCGTargetOpDef re_r = { .args_ct_str = { "re", "r" } };
-    static const TCGTargetOpDef qi_r = { .args_ct_str = { "qi", "r" } };
-    static const TCGTargetOpDef r_r = { .args_ct_str = { "r", "r" } };
-    static const TCGTargetOpDef r_q = { .args_ct_str = { "r", "q" } };
-    static const TCGTargetOpDef r_re = { .args_ct_str = { "r", "re" } };
-    static const TCGTargetOpDef r_0 = { .args_ct_str = { "r", "0" } };
-    static const TCGTargetOpDef r_r_ri = { .args_ct_str = { "r", "r", "ri" } };
-    static const TCGTargetOpDef r_r_re = { .args_ct_str = { "r", "r", "re" } };
-    static const TCGTargetOpDef r_0_r = { .args_ct_str = { "r", "0", "r" } };
-    static const TCGTargetOpDef r_0_re = { .args_ct_str = { "r", "0", "re" } };
-    static const TCGTargetOpDef r_0_ci = { .args_ct_str = { "r", "0", "ci" } };
-    static const TCGTargetOpDef r_L = { .args_ct_str = { "r", "L" } };
-    static const TCGTargetOpDef L_L = { .args_ct_str = { "L", "L" } };
-    static const TCGTargetOpDef s_L = { .args_ct_str = { "s", "L" } };
-    static const TCGTargetOpDef r_L_L = { .args_ct_str = { "r", "L", "L" } };
-    static const TCGTargetOpDef r_r_L = { .args_ct_str = { "r", "r", "L" } };
-    static const TCGTargetOpDef L_L_L = { .args_ct_str = { "L", "L", "L" } };
-    static const TCGTargetOpDef s_L_L = { .args_ct_str = { "s", "L", "L" } };
-    static const TCGTargetOpDef r_r_L_L
-        = { .args_ct_str = { "r", "r", "L", "L" } };
-    static const TCGTargetOpDef L_L_L_L
-        = { .args_ct_str = { "L", "L", "L", "L" } };
-    static const TCGTargetOpDef x_x = { .args_ct_str = { "x", "x" } };
-    static const TCGTargetOpDef x_x_x = { .args_ct_str = { "x", "x", "x" } };
-    static const TCGTargetOpDef x_x_x_x
-        = { .args_ct_str = { "x", "x", "x", "x" } };
-    static const TCGTargetOpDef x_r = { .args_ct_str = { "x", "r" } };
-
     switch (op) {
     case INDEX_op_goto_ptr:
-        return &r;
+        return C_O0_I1(r);
 
     case INDEX_op_ld8u_i32:
     case INDEX_op_ld8u_i64:
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
     case INDEX_op_ld32u_i64:
     case INDEX_op_ld32s_i64:
     case INDEX_op_ld_i64:
-        return &r_r;
+        return C_O1_I1(r, r);
 
     case INDEX_op_st8_i32:
     case INDEX_op_st8_i64:
-        return &qi_r;
+        return C_O0_I2(qi, r);
+
     case INDEX_op_st16_i32:
     case INDEX_op_st16_i64:
     case INDEX_op_st_i32:
     case INDEX_op_st32_i64:
-        return &ri_r;
+        return C_O0_I2(ri, r);
+
     case INDEX_op_st_i64:
-        return &re_r;
+        return C_O0_I2(re, r);
 
     case INDEX_op_add_i32:
     case INDEX_op_add_i64:
-        return &r_r_re;
+        return C_O1_I2(r, r, re);
+
     case INDEX_op_sub_i32:
     case INDEX_op_sub_i64:
     case INDEX_op_mul_i32:
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
     case INDEX_op_or_i64:
     case INDEX_op_xor_i32:
     case INDEX_op_xor_i64:
-        return &r_0_re;
+        return C_O1_I2(r, 0, re);
 
     case INDEX_op_and_i32:
     case INDEX_op_and_i64:
-        {
-            static const TCGTargetOpDef and
-                = { .args_ct_str = { "r", "0", "reZ" } };
-            return &and;
-        }
-        break;
+        return C_O1_I2(r, 0, reZ);
+
     case INDEX_op_andc_i32:
     case INDEX_op_andc_i64:
-        {
-            static const TCGTargetOpDef andc
-                = { .args_ct_str = { "r", "r", "rI" } };
-            return &andc;
-        }
-        break;
+        return C_O1_I2(r, r, rI);
 
     case INDEX_op_shl_i32:
     case INDEX_op_shl_i64:
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
     case INDEX_op_shr_i64:
     case INDEX_op_sar_i32:
     case INDEX_op_sar_i64:
-        return have_bmi2 ? &r_r_ri : &r_0_ci;
+        return have_bmi2 ? C_O1_I2(r, r, ri) : C_O1_I2(r, 0, ci);
+
     case INDEX_op_rotl_i32:
     case INDEX_op_rotl_i64:
     case INDEX_op_rotr_i32:
     case INDEX_op_rotr_i64:
-        return &r_0_ci;
+        return C_O1_I2(r, 0, ci);
 
     case INDEX_op_brcond_i32:
     case INDEX_op_brcond_i64:
-        return &r_re;
+        return C_O0_I2(r, re);
 
     case INDEX_op_bswap16_i32:
     case INDEX_op_bswap16_i64:
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
     case INDEX_op_not_i32:
     case INDEX_op_not_i64:
     case INDEX_op_extrh_i64_i32:
-        return &r_0;
+        return C_O1_I1(r, 0);
 
     case INDEX_op_ext8s_i32:
     case INDEX_op_ext8s_i64:
     case INDEX_op_ext8u_i32:
     case INDEX_op_ext8u_i64:
-        return &r_q;
+        return C_O1_I1(r, q);
+
     case INDEX_op_ext16s_i32:
     case INDEX_op_ext16s_i64:
     case INDEX_op_ext16u_i32:
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
     case INDEX_op_sextract_i32:
     case INDEX_op_ctpop_i32:
     case INDEX_op_ctpop_i64:
-        return &r_r;
+        return C_O1_I1(r, r);
+
     case INDEX_op_extract2_i32:
     case INDEX_op_extract2_i64:
-        return &r_0_r;
+        return C_O1_I2(r, 0, r);
 
     case INDEX_op_deposit_i32:
     case INDEX_op_deposit_i64:
-        {
-            static const TCGTargetOpDef dep
-                = { .args_ct_str = { "Q", "0", "Q" } };
-            return &dep;
-        }
+        return C_O1_I2(Q, 0, Q);
+
     case INDEX_op_setcond_i32:
     case INDEX_op_setcond_i64:
-        {
-            static const TCGTargetOpDef setc
-                = { .args_ct_str = { "q", "r", "re" } };
-            return &setc;
-        }
+        return C_O1_I2(q, r, re);
+
     case INDEX_op_movcond_i32:
     case INDEX_op_movcond_i64:
-        {
-            static const TCGTargetOpDef movc
-                = { .args_ct_str = { "r", "r", "re", "r", "0" } };
-            return &movc;
-        }
+        return C_O1_I4(r, r, re, r, 0);
+
     case INDEX_op_div2_i32:
     case INDEX_op_div2_i64:
     case INDEX_op_divu2_i32:
     case INDEX_op_divu2_i64:
-        {
-            static const TCGTargetOpDef div2
-                = { .args_ct_str = { "a", "d", "0", "1", "r" } };
-            return &div2;
-        }
+        return C_O2_I3(a, d, 0, 1, r);
+
     case INDEX_op_mulu2_i32:
     case INDEX_op_mulu2_i64:
     case INDEX_op_muls2_i32:
     case INDEX_op_muls2_i64:
-        {
-            static const TCGTargetOpDef mul2
-                = { .args_ct_str = { "a", "d", "a", "r" } };
-            return &mul2;
-        }
+        return C_O2_I2(a, d, a, r);
+
     case INDEX_op_add2_i32:
     case INDEX_op_add2_i64:
     case INDEX_op_sub2_i32:
     case INDEX_op_sub2_i64:
-        {
-            static const TCGTargetOpDef arith2
-                = { .args_ct_str = { "r", "r", "0", "1", "re", "re" } };
-            return &arith2;
-        }
+        return C_O2_I4(r, r, 0, 1, re, re);
+
     case INDEX_op_ctz_i32:
     case INDEX_op_ctz_i64:
-        {
-            static const TCGTargetOpDef ctz[2] = {
-                { .args_ct_str = { "&r", "r", "r" } },
-                { .args_ct_str = { "&r", "r", "rW" } },
-            };
-            return &ctz[have_bmi1];
-        }
+        return have_bmi1 ? C_N1_I2(r, r, rW) : C_N1_I2(r, r, r);
+
     case INDEX_op_clz_i32:
     case INDEX_op_clz_i64:
-        {
-            static const TCGTargetOpDef clz[2] = {
-                { .args_ct_str = { "&r", "r", "r" } },
-                { .args_ct_str = { "&r", "r", "rW" } },
-            };
-            return &clz[have_lzcnt];
-        }
+        return have_lzcnt ? C_N1_I2(r, r, rW) : C_N1_I2(r, r, r);
 
     case INDEX_op_qemu_ld_i32:
-        return TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &r_L : &r_L_L;
+        return (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS
+                ? C_O1_I1(r, L) : C_O1_I2(r, L, L));
+
     case INDEX_op_qemu_st_i32:
-        return TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &L_L : &L_L_L;
+        return (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS
+                ? C_O0_I2(L, L) : C_O0_I3(L, L, L));
     case INDEX_op_qemu_st8_i32:
-        return TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &s_L : &s_L_L;
+        return (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS
+                ? C_O0_I2(s, L) : C_O0_I3(s, L, L));
+
     case INDEX_op_qemu_ld_i64:
-        return (TCG_TARGET_REG_BITS == 64 ? &r_L
-                : TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &r_r_L
-                : &r_r_L_L);
+        return (TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, L)
+                : TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? C_O2_I1(r, r, L)
+                : C_O2_I2(r, r, L, L));
+
     case INDEX_op_qemu_st_i64:
-        return (TCG_TARGET_REG_BITS == 64 ? &L_L
-                : TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &L_L_L
-                : &L_L_L_L);
+        return (TCG_TARGET_REG_BITS == 64 ? C_O0_I2(L, L)
+                : TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? C_O0_I3(L, L, L)
+                : C_O0_I4(L, L, L, L));
 
     case INDEX_op_brcond2_i32:
-        {
-            static const TCGTargetOpDef b2
-                = { .args_ct_str = { "r", "r", "ri", "ri" } };
-            return &b2;
-        }
+        return C_O0_I4(r, r, ri, ri);
+
     case INDEX_op_setcond2_i32:
-        {
-            static const TCGTargetOpDef s2
-                = { .args_ct_str = { "r", "r", "r", "ri", "ri" } };
-            return &s2;
-        }
+        return C_O1_I4(r, r, r, ri, ri);
 
     case INDEX_op_ld_vec:
-    case INDEX_op_st_vec:
     case INDEX_op_dupm_vec:
-        return &x_r;
+        return C_O1_I1(x, r);
+
+    case INDEX_op_st_vec:
+        return C_O0_I2(x, r);
 
     case INDEX_op_add_vec:
     case INDEX_op_sub_vec:
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
 #if TCG_TARGET_REG_BITS == 32
     case INDEX_op_dup2_vec:
 #endif
-        return &x_x_x;
+        return C_O1_I2(x, x, x);
+
     case INDEX_op_abs_vec:
     case INDEX_op_dup_vec:
     case INDEX_op_shli_vec:
     case INDEX_op_shri_vec:
     case INDEX_op_sari_vec:
     case INDEX_op_x86_psrldq_vec:
-        return &x_x;
+        return C_O1_I1(x, x);
+
     case INDEX_op_x86_vpblendvb_vec:
-        return &x_x_x_x;
+        return C_O1_I3(x, x, x, x);
 
     default:
-        break;
+        g_assert_not_reached();
     }
-    return NULL;
 }
 
 int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
-- 
2.25.1

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/aarch64/tcg-target-con-set.h | 36 +++++++++++++
 tcg/aarch64/tcg-target.h         |  1 +
 tcg/aarch64/tcg-target.c.inc     | 86 +++++++++++---------------------
 3 files changed, 65 insertions(+), 58 deletions(-)
 create mode 100644 tcg/aarch64/tcg-target-con-set.h

diff --git a/tcg/aarch64/tcg-target-con-set.h b/tcg/aarch64/tcg-target-con-set.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/tcg/aarch64/tcg-target-con-set.h
@@ -XXX,XX +XXX,XX @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Define AArch64 target-specific constraint sets.
+ * Copyright (c) 2021 Linaro
+ */
+
+/*
+ * C_On_Im(...) defines a constraint set with <n> outputs and <m> inputs.
+ * Each operand should be a sequence of constraint letters as defined by
+ * tcg-target-con-str.h; the constraint combination is inclusive or.
+ */
+C_O0_I1(r)
+C_O0_I2(lZ, l)
+C_O0_I2(r, rA)
+C_O0_I2(rZ, r)
+C_O0_I2(w, r)
+C_O1_I1(r, l)
+C_O1_I1(r, r)
+C_O1_I1(w, r)
+C_O1_I1(w, w)
+C_O1_I1(w, wr)
+C_O1_I2(r, 0, rZ)
+C_O1_I2(r, r, r)
+C_O1_I2(r, r, rA)
+C_O1_I2(r, r, rAL)
+C_O1_I2(r, r, ri)
+C_O1_I2(r, r, rL)
+C_O1_I2(r, rZ, rZ)
+C_O1_I2(w, 0, w)
+C_O1_I2(w, w, w)
+C_O1_I2(w, w, wN)
+C_O1_I2(w, w, wO)
+C_O1_I2(w, w, wZ)
+C_O1_I3(w, w, w, w)
+C_O1_I4(r, r, rA, rZ, rZ)
+C_O2_I4(r, r, rZ, rZ, rA, rMZ)
diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h
index XXXXXXX..XXXXXXX 100644
--- a/tcg/aarch64/tcg-target.h
+++ b/tcg/aarch64/tcg-target.h
@@ -XXX,XX +XXX,XX @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t);
 #define TCG_TARGET_NEED_LDST_LABELS
 #endif
 #define TCG_TARGET_NEED_POOL_LABELS
+#define TCG_TARGET_CON_SET_H
 
 #endif /* AARCH64_TCG_TARGET_H */
diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/aarch64/tcg-target.c.inc
+++ b/tcg/aarch64/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece,
     va_end(va);
 }
 
-static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
+static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
 {
-    static const TCGTargetOpDef r = { .args_ct_str = { "r" } };
-    static const TCGTargetOpDef r_r = { .args_ct_str = { "r", "r" } };
-    static const TCGTargetOpDef w_w = { .args_ct_str = { "w", "w" } };
-    static const TCGTargetOpDef w_r = { .args_ct_str = { "w", "r" } };
-    static const TCGTargetOpDef w_wr = { .args_ct_str = { "w", "wr" } };
-    static const TCGTargetOpDef r_l = { .args_ct_str = { "r", "l" } };
-    static const TCGTargetOpDef r_rA = { .args_ct_str = { "r", "rA" } };
-    static const TCGTargetOpDef rZ_r = { .args_ct_str = { "rZ", "r" } };
-    static const TCGTargetOpDef lZ_l = { .args_ct_str = { "lZ", "l" } };
-    static const TCGTargetOpDef r_r_r = { .args_ct_str = { "r", "r", "r" } };
-    static const TCGTargetOpDef w_w_w = { .args_ct_str = { "w", "w", "w" } };
-    static const TCGTargetOpDef w_0_w = { .args_ct_str = { "w", "0", "w" } };
-    static const TCGTargetOpDef w_w_wO = { .args_ct_str = { "w", "w", "wO" } };
-    static const TCGTargetOpDef w_w_wN = { .args_ct_str = { "w", "w", "wN" } };
-    static const TCGTargetOpDef w_w_wZ = { .args_ct_str = { "w", "w", "wZ" } };
-    static const TCGTargetOpDef r_r_ri = { .args_ct_str = { "r", "r", "ri" } };
-    static const TCGTargetOpDef r_r_rA = { .args_ct_str = { "r", "r", "rA" } };
-    static const TCGTargetOpDef r_r_rL = { .args_ct_str = { "r", "r", "rL" } };
-    static const TCGTargetOpDef r_r_rAL
-        = { .args_ct_str = { "r", "r", "rAL" } };
-    static const TCGTargetOpDef dep
-        = { .args_ct_str = { "r", "0", "rZ" } };
-    static const TCGTargetOpDef ext2
-        = { .args_ct_str = { "r", "rZ", "rZ" } };
-    static const TCGTargetOpDef movc
-        = { .args_ct_str = { "r", "r", "rA", "rZ", "rZ" } };
-    static const TCGTargetOpDef add2
-        = { .args_ct_str = { "r", "r", "rZ", "rZ", "rA", "rMZ" } };
-    static const TCGTargetOpDef w_w_w_w
-        = { .args_ct_str = { "w", "w", "w", "w" } };
-
     switch (op) {
     case INDEX_op_goto_ptr:
-        return &r;
+        return C_O0_I1(r);
 
     case INDEX_op_ld8u_i32:
     case INDEX_op_ld8s_i32:
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
     case INDEX_op_extract_i64:
     case INDEX_op_sextract_i32:
     case INDEX_op_sextract_i64:
-        return &r_r;
+        return C_O1_I1(r, r);
 
     case INDEX_op_st8_i32:
     case INDEX_op_st16_i32:
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
     case INDEX_op_st16_i64:
     case INDEX_op_st32_i64:
     case INDEX_op_st_i64:
-        return &rZ_r;
+        return C_O0_I2(rZ, r);
 
     case INDEX_op_add_i32:
     case INDEX_op_add_i64:
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
     case INDEX_op_sub_i64:
     case INDEX_op_setcond_i32:
     case INDEX_op_setcond_i64:
-        return &r_r_rA;
+        return C_O1_I2(r, r, rA);
 
     case INDEX_op_mul_i32:
     case INDEX_op_mul_i64:
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
     case INDEX_op_remu_i64:
     case INDEX_op_muluh_i64:
     case INDEX_op_mulsh_i64:
-        return &r_r_r;
+        return C_O1_I2(r, r, r);
 
     case INDEX_op_and_i32:
     case INDEX_op_and_i64:
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
     case INDEX_op_orc_i64:
     case INDEX_op_eqv_i32:
     case INDEX_op_eqv_i64:
-        return &r_r_rL;
+        return C_O1_I2(r, r, rL);
 
     case INDEX_op_shl_i32:
     case INDEX_op_shr_i32:
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
     case INDEX_op_sar_i64:
     case INDEX_op_rotl_i64:
     case INDEX_op_rotr_i64:
-        return &r_r_ri;
+        return C_O1_I2(r, r, ri);
 
     case INDEX_op_clz_i32:
     case INDEX_op_ctz_i32:
     case INDEX_op_clz_i64:
     case INDEX_op_ctz_i64:
-        return &r_r_rAL;
+        return C_O1_I2(r, r, rAL);
 
     case INDEX_op_brcond_i32:
     case INDEX_op_brcond_i64:
-        return &r_rA;
+        return C_O0_I2(r, rA);
 
     case INDEX_op_movcond_i32:
     case INDEX_op_movcond_i64:
-        return &movc;
+        return C_O1_I4(r, r, rA, rZ, rZ);
 
     case INDEX_op_qemu_ld_i32:
     case INDEX_op_qemu_ld_i64:
-        return &r_l;
+        return C_O1_I1(r, l);
     case INDEX_op_qemu_st_i32:
     case INDEX_op_qemu_st_i64:
-        return &lZ_l;
+        return C_O0_I2(lZ, l);
 
     case INDEX_op_deposit_i32:
     case INDEX_op_deposit_i64:
-        return &dep;
+        return C_O1_I2(r, 0, rZ);
 
     case INDEX_op_extract2_i32:
     case INDEX_op_extract2_i64:
-        return &ext2;
+        return C_O1_I2(r, rZ, rZ);
 
     case INDEX_op_add2_i32:
     case INDEX_op_add2_i64:
     case INDEX_op_sub2_i32:
     case INDEX_op_sub2_i64:
-        return &add2;
+        return C_O2_I4(r, r, rZ, rZ, rA, rMZ);
 
     case INDEX_op_add_vec:
     case INDEX_op_sub_vec:
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
     case INDEX_op_shrv_vec:
     case INDEX_op_sarv_vec:
     case INDEX_op_aa64_sshl_vec:
-        return &w_w_w;
+        return C_O1_I2(w, w, w);
     case INDEX_op_not_vec:
     case INDEX_op_neg_vec:
     case INDEX_op_abs_vec:
     case INDEX_op_shli_vec:
     case INDEX_op_shri_vec:
     case INDEX_op_sari_vec:
-        return &w_w;
+        return C_O1_I1(w, w);
     case INDEX_op_ld_vec:
-    case INDEX_op_st_vec:
     case INDEX_op_dupm_vec:
-        return &w_r;
+        return C_O1_I1(w, r);
+    case INDEX_op_st_vec:
+        return C_O0_I2(w, r);
     case INDEX_op_dup_vec:
-        return &w_wr;
+        return C_O1_I1(w, wr);
     case INDEX_op_or_vec:
     case INDEX_op_andc_vec:
-        return &w_w_wO;
+        return C_O1_I2(w, w, wO);
     case INDEX_op_and_vec:
     case INDEX_op_orc_vec:
-        return &w_w_wN;
+        return C_O1_I2(w, w, wN);
     case INDEX_op_cmp_vec:
-        return &w_w_wZ;
+        return C_O1_I2(w, w, wZ);
     case INDEX_op_bitsel_vec:
-        return &w_w_w_w;
+        return C_O1_I3(w, w, w, w);
     case INDEX_op_aa64_sli_vec:
-        return &w_0_w;
+        return C_O1_I2(w, 0, w);
 
     default:
-        return NULL;
+        g_assert_not_reached();
     }
 }
 
-- 
2.25.1

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/arm/tcg-target-con-set.h | 35 ++++++++++++++
 tcg/arm/tcg-target.h         |  1 +
 tcg/arm/tcg-target.c.inc     | 94 ++++++++++++------------------------
 3 files changed, 68 insertions(+), 62 deletions(-)
 create mode 100644 tcg/arm/tcg-target-con-set.h

diff --git a/tcg/arm/tcg-target-con-set.h b/tcg/arm/tcg-target-con-set.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/tcg/arm/tcg-target-con-set.h
@@ -XXX,XX +XXX,XX @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Define Arm target-specific constraint sets.
+ * Copyright (c) 2021 Linaro
+ */
+
+/*
+ * C_On_Im(...) defines a constraint set with <n> outputs and <m> inputs.
+ * Each operand should be a sequence of constraint letters as defined by
+ * tcg-target-con-str.h; the constraint combination is inclusive or.
+ */
+C_O0_I1(r)
+C_O0_I2(r, r)
+C_O0_I2(r, rIN)
+C_O0_I2(s, s)
+C_O0_I3(s, s, s)
+C_O0_I4(r, r, rI, rI)
+C_O0_I4(s, s, s, s)
+C_O1_I1(r, l)
+C_O1_I1(r, r)
+C_O1_I2(r, 0, rZ)
+C_O1_I2(r, l, l)
+C_O1_I2(r, r, r)
+C_O1_I2(r, r, rI)
+C_O1_I2(r, r, rIK)
+C_O1_I2(r, r, rIN)
+C_O1_I2(r, r, ri)
+C_O1_I2(r, rZ, rZ)
+C_O1_I4(r, r, r, rI, rI)
+C_O1_I4(r, r, rIN, rIK, 0)
+C_O2_I1(r, r, l)
+C_O2_I2(r, r, l, l)
+C_O2_I2(r, r, r, r)
+C_O2_I4(r, r, r, r, rIN, rIK)
+C_O2_I4(r, r, rI, rI, rIN, rIK)
diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
index XXXXXXX..XXXXXXX 100644
--- a/tcg/arm/tcg-target.h
+++ b/tcg/arm/tcg-target.h
@@ -XXX,XX +XXX,XX @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t);
 #define TCG_TARGET_NEED_LDST_LABELS
 #endif
 #define TCG_TARGET_NEED_POOL_LABELS
+#define TCG_TARGET_CON_SET_H
 
 #endif
diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/arm/tcg-target.c.inc
+++ b/tcg/arm/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
     }
 }
 
-static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
+static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
 {
-    static const TCGTargetOpDef r = { .args_ct_str = { "r" } };
-    static const TCGTargetOpDef r_r = { .args_ct_str = { "r", "r" } };
-    static const TCGTargetOpDef s_s = { .args_ct_str = { "s", "s" } };
-    static const TCGTargetOpDef r_l = { .args_ct_str = { "r", "l" } };
-    static const TCGTargetOpDef r_r_r = { .args_ct_str = { "r", "r", "r" } };
-    static const TCGTargetOpDef r_r_l = { .args_ct_str = { "r", "r", "l" } };
-    static const TCGTargetOpDef r_l_l = { .args_ct_str = { "r", "l", "l" } };
-    static const TCGTargetOpDef s_s_s = { .args_ct_str = { "s", "s", "s" } };
-    static const TCGTargetOpDef r_r_ri = { .args_ct_str = { "r", "r", "ri" } };
-    static const TCGTargetOpDef r_r_rI = { .args_ct_str = { "r", "r", "rI" } };
-    static const TCGTargetOpDef r_r_rIN
-        = { .args_ct_str = { "r", "r", "rIN" } };
-    static const TCGTargetOpDef r_r_rIK
-        = { .args_ct_str = { "r", "r", "rIK" } };
-    static const TCGTargetOpDef r_r_r_r
-        = { .args_ct_str = { "r", "r", "r", "r" } };
-    static const TCGTargetOpDef r_r_l_l
-        = { .args_ct_str = { "r", "r", "l", "l" } };
-    static const TCGTargetOpDef s_s_s_s
-        = { .args_ct_str = { "s", "s", "s", "s" } };
-    static const TCGTargetOpDef br
-        = { .args_ct_str = { "r", "rIN" } };
-    static const TCGTargetOpDef ext2
-        = { .args_ct_str = { "r", "rZ", "rZ" } };
-    static const TCGTargetOpDef dep
-        = { .args_ct_str = { "r", "0", "rZ" } };
-    static const TCGTargetOpDef movc
-        = { .args_ct_str = { "r", "r", "rIN", "rIK", "0" } };
-    static const TCGTargetOpDef add2
-        = { .args_ct_str = { "r", "r", "r", "r", "rIN", "rIK" } };
-    static const TCGTargetOpDef sub2
-        = { .args_ct_str = { "r", "r", "rI", "rI", "rIN", "rIK" } };
-    static const TCGTargetOpDef br2
-        = { .args_ct_str = { "r", "r", "rI", "rI" } };
-    static const TCGTargetOpDef setc2
-        = { .args_ct_str = { "r", "r", "r", "rI", "rI" } };
-
     switch (op) {
     case INDEX_op_goto_ptr:
-        return &r;
+        return C_O0_I1(r);
 
     case INDEX_op_ld8u_i32:
     case INDEX_op_ld8s_i32:
     case INDEX_op_ld16u_i32:
     case INDEX_op_ld16s_i32:
     case INDEX_op_ld_i32:
-    case INDEX_op_st8_i32:
-    case INDEX_op_st16_i32:
-    case INDEX_op_st_i32:
     case INDEX_op_neg_i32:
     case INDEX_op_not_i32:
     case INDEX_op_bswap16_i32:
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
     case INDEX_op_ext16u_i32:
     case INDEX_op_extract_i32:
     case INDEX_op_sextract_i32:
-        return &r_r;
+        return C_O1_I1(r, r);
+
+    case INDEX_op_st8_i32:
+    case INDEX_op_st16_i32:
+    case INDEX_op_st_i32:
+        return C_O0_I2(r, r);
 
     case INDEX_op_add_i32:
     case INDEX_op_sub_i32:
     case INDEX_op_setcond_i32:
-        return &r_r_rIN;
+        return C_O1_I2(r, r, rIN);
+
     case INDEX_op_and_i32:
     case INDEX_op_andc_i32:
     case INDEX_op_clz_i32:
     case INDEX_op_ctz_i32:
-        return &r_r_rIK;
+        return C_O1_I2(r, r, rIK);
+
     case INDEX_op_mul_i32:
     case INDEX_op_div_i32:
     case INDEX_op_divu_i32:
-        return &r_r_r;
+        return C_O1_I2(r, r, r);
+
     case INDEX_op_mulu2_i32:
     case INDEX_op_muls2_i32:
-        return &r_r_r_r;
+        return C_O2_I2(r, r, r, r);
+
     case INDEX_op_or_i32:
     case INDEX_op_xor_i32:
-        return &r_r_rI;
+        return C_O1_I2(r, r, rI);
+
     case INDEX_op_shl_i32:
     case INDEX_op_shr_i32:
     case INDEX_op_sar_i32:
     case INDEX_op_rotl_i32:
     case INDEX_op_rotr_i32:
-        return &r_r_ri;
+        return C_O1_I2(r, r, ri);
 
     case INDEX_op_brcond_i32:
-        return &br;
+        return C_O0_I2(r, rIN);
     case INDEX_op_deposit_i32:
-        return &dep;
+        return C_O1_I2(r, 0, rZ);
     case INDEX_op_extract2_i32:
-        return &ext2;
+        return C_O1_I2(r, rZ, rZ);
     case INDEX_op_movcond_i32:
-        return &movc;
+        return C_O1_I4(r, r, rIN, rIK, 0);
     case INDEX_op_add2_i32:
-        return &add2;
+        return C_O2_I4(r, r, r, r, rIN, rIK);
     case INDEX_op_sub2_i32:
-        return &sub2;
+        return C_O2_I4(r, r, rI, rI, rIN, rIK);
     case INDEX_op_brcond2_i32:
-        return &br2;
+        return C_O0_I4(r, r, rI, rI);
     case INDEX_op_setcond2_i32:
-        return &setc2;
+        return C_O1_I4(r, r, r, rI, rI);
 
     case INDEX_op_qemu_ld_i32:
-        return TARGET_LONG_BITS == 32 ? &r_l : &r_l_l;
+        return TARGET_LONG_BITS == 32 ? C_O1_I1(r, l) : C_O1_I2(r, l, l);
     case INDEX_op_qemu_ld_i64:
-        return TARGET_LONG_BITS == 32 ? &r_r_l : &r_r_l_l;
+        return TARGET_LONG_BITS == 32 ? C_O2_I1(r, r, l) : C_O2_I2(r, r, l, l);
     case INDEX_op_qemu_st_i32:
-        return TARGET_LONG_BITS == 32 ? &s_s : &s_s_s;
+        return TARGET_LONG_BITS == 32 ? C_O0_I2(s, s) : C_O0_I3(s, s, s);
     case INDEX_op_qemu_st_i64:
-        return TARGET_LONG_BITS == 32 ? &s_s_s : &s_s_s_s;
+        return TARGET_LONG_BITS == 32 ? C_O0_I3(s, s, s) : C_O0_I4(s, s, s, s);
 
     default:
-        return NULL;
+        g_assert_not_reached();
     }
 }
 
-- 
2.25.1

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/mips/tcg-target-con-set.h | 36 +++++++++++++
 tcg/mips/tcg-target.h         |  1 +
 tcg/mips/tcg-target.c.inc     | 96 +++++++++++------------------------
 3 files changed, 66 insertions(+), 67 deletions(-)
 create mode 100644 tcg/mips/tcg-target-con-set.h

diff --git a/tcg/mips/tcg-target-con-set.h b/tcg/mips/tcg-target-con-set.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/tcg/mips/tcg-target-con-set.h
@@ -XXX,XX +XXX,XX @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Define MIPS target-specific constraint sets.
+ * Copyright (c) 2021 Linaro
+ */
+
+/*
+ * C_On_Im(...) defines a constraint set with <n> outputs and <m> inputs.
+ * Each operand should be a sequence of constraint letters as defined by
+ * tcg-target-con-str.h; the constraint combination is inclusive or.
+ */
+C_O0_I1(r)
+C_O0_I2(rZ, r)
+C_O0_I2(rZ, rZ)
+C_O0_I2(SZ, S)
+C_O0_I3(SZ, S, S)
+C_O0_I3(SZ, SZ, S)
+C_O0_I4(rZ, rZ, rZ, rZ)
+C_O0_I4(SZ, SZ, S, S)
+C_O1_I1(r, L)
+C_O1_I1(r, r)
+C_O1_I2(r, 0, rZ)
+C_O1_I2(r, L, L)
+C_O1_I2(r, r, ri)
+C_O1_I2(r, r, rI)
+C_O1_I2(r, r, rIK)
+C_O1_I2(r, r, rJ)
+C_O1_I2(r, r, rWZ)
+C_O1_I2(r, rZ, rN)
+C_O1_I2(r, rZ, rZ)
+C_O1_I4(r, rZ, rZ, rZ, 0)
+C_O1_I4(r, rZ, rZ, rZ, rZ)
+C_O2_I1(r, r, L)
+C_O2_I2(r, r, L, L)
+C_O2_I2(r, r, r, r)
+C_O2_I4(r, r, rZ, rZ, rN, rN)
diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h
index XXXXXXX..XXXXXXX 100644
--- a/tcg/mips/tcg-target.h
+++ b/tcg/mips/tcg-target.h
@@ -XXX,XX +XXX,XX @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t);
 #ifdef CONFIG_SOFTMMU
 #define TCG_TARGET_NEED_LDST_LABELS
 #endif
+#define TCG_TARGET_CON_SET_H
 
 #endif
diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/mips/tcg-target.c.inc
+++ b/tcg/mips/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
     }
 }
 
-static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
+static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
 {
-    static const TCGTargetOpDef r = { .args_ct_str = { "r" } };
-    static const TCGTargetOpDef r_r = { .args_ct_str = { "r", "r" } };
-    static const TCGTargetOpDef r_L = { .args_ct_str = { "r", "L" } };
-    static const TCGTargetOpDef rZ_r = { .args_ct_str = { "rZ", "r" } };
-    static const TCGTargetOpDef SZ_S = { .args_ct_str = { "SZ", "S" } };
-    static const TCGTargetOpDef rZ_rZ = { .args_ct_str = { "rZ", "rZ" } };
-    static const TCGTargetOpDef r_r_L = { .args_ct_str = { "r", "r", "L" } };
-    static const TCGTargetOpDef r_L_L = { .args_ct_str = { "r", "L", "L" } };
-    static const TCGTargetOpDef r_r_ri = { .args_ct_str = { "r", "r", "ri" } };
-    static const TCGTargetOpDef r_r_rI = { .args_ct_str = { "r", "r", "rI" } };
-    static const TCGTargetOpDef r_r_rJ = { .args_ct_str = { "r", "r", "rJ" } };
-    static const TCGTargetOpDef SZ_S_S = { .args_ct_str = { "SZ", "S", "S" } };
-    static const TCGTargetOpDef SZ_SZ_S
-        = { .args_ct_str = { "SZ", "SZ", "S" } };
-    static const TCGTargetOpDef SZ_SZ_S_S
-        = { .args_ct_str = { "SZ", "SZ", "S", "S" } };
-    static const TCGTargetOpDef r_rZ_rN
-        = { .args_ct_str = { "r", "rZ", "rN" } };
-    static const TCGTargetOpDef r_rZ_rZ
-        = { .args_ct_str = { "r", "rZ", "rZ" } };
-    static const TCGTargetOpDef r_r_rIK
-        = { .args_ct_str = { "r", "r", "rIK" } };
-    static const TCGTargetOpDef r_r_rWZ
-        = { .args_ct_str = { "r", "r", "rWZ" } };
-    static const TCGTargetOpDef r_r_r_r
-        = { .args_ct_str = { "r", "r", "r", "r" } };
-    static const TCGTargetOpDef r_r_L_L
-        = { .args_ct_str = { "r", "r", "L", "L" } };
-    static const TCGTargetOpDef dep
-        = { .args_ct_str = { "r", "0", "rZ" } };
-    static const TCGTargetOpDef movc
-        = { .args_ct_str = { "r", "rZ", "rZ", "rZ", "0" } };
-    static const TCGTargetOpDef movc_r6
-        = { .args_ct_str = { "r", "rZ", "rZ", "rZ", "rZ" } };
-    static const TCGTargetOpDef add2
-        = { .args_ct_str = { "r", "r", "rZ", "rZ", "rN", "rN" } };
-    static const TCGTargetOpDef br2
-        = { .args_ct_str = { "rZ", "rZ", "rZ", "rZ" } };
-    static const TCGTargetOpDef setc2
-        = { .args_ct_str = { "r", "rZ", "rZ", "rZ", "rZ" } };
-
     switch (op) {
     case INDEX_op_goto_ptr:
-        return &r;
+        return C_O0_I1(r);
 
     case INDEX_op_ld8u_i32:
     case INDEX_op_ld8s_i32:
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
     case INDEX_op_extrl_i64_i32:
     case INDEX_op_extrh_i64_i32:
     case INDEX_op_extract_i64:
-        return &r_r;
+        return C_O1_I1(r, r);
 
     case INDEX_op_st8_i32:
     case INDEX_op_st16_i32:
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
     case INDEX_op_st16_i64:
     case INDEX_op_st32_i64:
     case INDEX_op_st_i64:
-        return &rZ_r;
+        return C_O0_I2(rZ, r);
 
     case INDEX_op_add_i32:
     case INDEX_op_add_i64:
-        return &r_r_rJ;
+        return C_O1_I2(r, r, rJ);
     case INDEX_op_sub_i32:
     case INDEX_op_sub_i64:
-        return &r_rZ_rN;
+        return C_O1_I2(r, rZ, rN);
     case INDEX_op_mul_i32:
     case INDEX_op_mulsh_i32:
     case INDEX_op_muluh_i32:
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
     case INDEX_op_remu_i64:
     case INDEX_op_nor_i64:
     case INDEX_op_setcond_i64:
-        return &r_rZ_rZ;
+        return C_O1_I2(r, rZ, rZ);
     case INDEX_op_muls2_i32:
     case INDEX_op_mulu2_i32:
     case INDEX_op_muls2_i64:
     case INDEX_op_mulu2_i64:
-        return &r_r_r_r;
+        return C_O2_I2(r, r, r, r);
     case INDEX_op_and_i32:
     case INDEX_op_and_i64:
-        return &r_r_rIK;
+        return C_O1_I2(r, r, rIK);
     case INDEX_op_or_i32:
     case INDEX_op_xor_i32:
     case INDEX_op_or_i64:
     case INDEX_op_xor_i64:
-        return &r_r_rI;
+        return C_O1_I2(r, r, rI);
     case INDEX_op_shl_i32:
     case INDEX_op_shr_i32:
     case INDEX_op_sar_i32:
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
     case INDEX_op_sar_i64:
     case INDEX_op_rotr_i64:
     case INDEX_op_rotl_i64:
-        return &r_r_ri;
+        return C_O1_I2(r, r, ri);
     case INDEX_op_clz_i32:
     case INDEX_op_clz_i64:
-        return &r_r_rWZ;
+        return C_O1_I2(r, r, rWZ);
 
     case INDEX_op_deposit_i32:
     case INDEX_op_deposit_i64:
-        return &dep;
+        return C_O1_I2(r, 0, rZ);
     case INDEX_op_brcond_i32:
     case INDEX_op_brcond_i64:
-        return &rZ_rZ;
+        return C_O0_I2(rZ, rZ);
     case INDEX_op_movcond_i32:
     case INDEX_op_movcond_i64:
-        return use_mips32r6_instructions ? &movc_r6 : &movc;
-
+        return (use_mips32r6_instructions
+                ? C_O1_I4(r, rZ, rZ, rZ, rZ)
+                : C_O1_I4(r, rZ, rZ, rZ, 0));
     case INDEX_op_add2_i32:
     case INDEX_op_sub2_i32:
-        return &add2;
+        return C_O2_I4(r, r, rZ, rZ, rN, rN);
     case INDEX_op_setcond2_i32:
-        return &setc2;
+        return C_O1_I4(r, rZ, rZ, rZ, rZ);
     case INDEX_op_brcond2_i32:
-        return &br2;
+        return C_O0_I4(rZ, rZ, rZ, rZ);
 
     case INDEX_op_qemu_ld_i32:
         return (TCG_TARGET_REG_BITS == 64 || TARGET_LONG_BITS == 32
-                ? &r_L : &r_L_L);
+                ? C_O1_I1(r, L) : C_O1_I2(r, L, L));
     case INDEX_op_qemu_st_i32:
         return (TCG_TARGET_REG_BITS == 64 || TARGET_LONG_BITS == 32
-                ? &SZ_S : &SZ_S_S);
+                ? C_O0_I2(SZ, S) : C_O0_I3(SZ, S, S));
     case INDEX_op_qemu_ld_i64:
-        return (TCG_TARGET_REG_BITS == 64 ? &r_L
-                : TARGET_LONG_BITS == 32 ? &r_r_L : &r_r_L_L);
+        return (TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, L)
+                : TARGET_LONG_BITS == 32 ? C_O2_I1(r, r, L)
+                : C_O2_I2(r, r, L, L));
     case INDEX_op_qemu_st_i64:
-        return (TCG_TARGET_REG_BITS == 64 ? &SZ_S
-                : TARGET_LONG_BITS == 32 ? &SZ_SZ_S : &SZ_SZ_S_S);
+        return (TCG_TARGET_REG_BITS == 64 ? C_O0_I2(SZ, S)
+                : TARGET_LONG_BITS == 32 ? C_O0_I3(SZ, SZ, S)
+                : C_O0_I4(SZ, SZ, S, S));
 
     default:
-        return NULL;
+        g_assert_not_reached();
     }
 }
 
-- 
2.25.1

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/ppc/tcg-target-con-set.h |  42 +++++++++++
 tcg/ppc/tcg-target.h         |   1 +
 tcg/ppc/tcg-target.c.inc     | 136 +++++++++++++++--------------------
 3 files changed, 99 insertions(+), 80 deletions(-)
 create mode 100644 tcg/ppc/tcg-target-con-set.h

diff --git a/tcg/ppc/tcg-target-con-set.h b/tcg/ppc/tcg-target-con-set.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/tcg/ppc/tcg-target-con-set.h
@@ -XXX,XX +XXX,XX @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Define PowerPC target-specific constraint sets.
+ * Copyright (c) 2021 Linaro
+ */
+
+/*
+ * C_On_Im(...) defines a constraint set with <n> outputs and <m> inputs.
+ * Each operand should be a sequence of constraint letters as defined by
+ * tcg-target-con-str.h; the constraint combination is inclusive or.
+ */
+C_O0_I1(r)
+C_O0_I2(r, r)
+C_O0_I2(r, ri)
+C_O0_I2(S, S)
+C_O0_I2(v, r)
+C_O0_I3(S, S, S)
+C_O0_I4(r, r, ri, ri)
+C_O0_I4(S, S, S, S)
+C_O1_I1(r, L)
+C_O1_I1(r, r)
+C_O1_I1(v, r)
+C_O1_I1(v, v)
+C_O1_I1(v, vr)
+C_O1_I2(r, 0, rZ)
+C_O1_I2(r, L, L)
+C_O1_I2(r, rI, ri)
+C_O1_I2(r, rI, rT)
+C_O1_I2(r, r, r)
+C_O1_I2(r, r, ri)
+C_O1_I2(r, r, rI)
+C_O1_I2(r, r, rT)
+C_O1_I2(r, r, rU)
+C_O1_I2(r, r, rZW)
+C_O1_I2(v, v, v)
+C_O1_I3(v, v, v, v)
+C_O1_I4(r, r, ri, rZ, rZ)
+C_O1_I4(r, r, r, ri, ri)
+C_O2_I1(L, L, L)
+C_O2_I2(L, L, L, L)
+C_O2_I4(r, r, rI, rZM, r, r)
+C_O2_I4(r, r, r, r, rI, rZM)
diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h
index XXXXXXX..XXXXXXX 100644
--- a/tcg/ppc/tcg-target.h
+++ b/tcg/ppc/tcg-target.h
@@ -XXX,XX +XXX,XX @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t);
 #define TCG_TARGET_NEED_LDST_LABELS
 #endif
 #define TCG_TARGET_NEED_POOL_LABELS
+#define TCG_TARGET_CON_SET_H
 
 #endif
diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/ppc/tcg-target.c.inc
+++ b/tcg/ppc/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece,
     va_end(va);
 }
 
-static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
+static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
 {
-    static const TCGTargetOpDef r = { .args_ct_str = { "r" } };
-    static const TCGTargetOpDef r_r = { .args_ct_str = { "r", "r" } };
-    static const TCGTargetOpDef r_L = { .args_ct_str = { "r", "L" } };
-    static const TCGTargetOpDef S_S = { .args_ct_str = { "S", "S" } };
-    static const TCGTargetOpDef r_ri = { .args_ct_str = { "r", "ri" } };
-    static const TCGTargetOpDef r_r_r = { .args_ct_str = { "r", "r", "r" } };
-    static const TCGTargetOpDef r_L_L = { .args_ct_str = { "r", "L", "L" } };
-    static const TCGTargetOpDef L_L_L = { .args_ct_str = { "L", "L", "L" } };
-    static const TCGTargetOpDef S_S_S = { .args_ct_str = { "S", "S", "S" } };
-    static const TCGTargetOpDef r_r_ri = { .args_ct_str = { "r", "r", "ri" } };
-    static const TCGTargetOpDef r_r_rI = { .args_ct_str = { "r", "r", "rI" } };
-    static const TCGTargetOpDef r_r_rT = { .args_ct_str = { "r", "r", "rT" } };
-    static const TCGTargetOpDef r_r_rU = { .args_ct_str = { "r", "r", "rU" } };
-    static const TCGTargetOpDef r_rI_ri
-        = { .args_ct_str = { "r", "rI", "ri" } };
-    static const TCGTargetOpDef r_rI_rT
-        = { .args_ct_str = { "r", "rI", "rT" } };
-    static const TCGTargetOpDef r_r_rZW
-        = { .args_ct_str = { "r", "r", "rZW" } };
-    static const TCGTargetOpDef L_L_L_L
-        = { .args_ct_str = { "L", "L", "L", "L" } };
-    static const TCGTargetOpDef S_S_S_S
-        = { .args_ct_str = { "S", "S", "S", "S" } };
-    static const TCGTargetOpDef movc
-        = { .args_ct_str = { "r", "r", "ri", "rZ", "rZ" } };
-    static const TCGTargetOpDef dep
-        = { .args_ct_str = { "r", "0", "rZ" } };
-    static const TCGTargetOpDef br2
-        = { .args_ct_str = { "r", "r", "ri", "ri" } };
-    static const TCGTargetOpDef setc2
-        = { .args_ct_str = { "r", "r", "r", "ri", "ri" } };
-    static const TCGTargetOpDef add2
-        = { .args_ct_str = { "r", "r", "r", "r", "rI", "rZM" } };
-    static const TCGTargetOpDef sub2
-        = { .args_ct_str = { "r", "r", "rI", "rZM", "r", "r" } };
-    static const TCGTargetOpDef v_r = { .args_ct_str = { "v", "r" } };
-    static const TCGTargetOpDef v_vr = { .args_ct_str = { "v", "vr" } };
-    static const TCGTargetOpDef v_v = { .args_ct_str = { "v", "v" } };
-    static const TCGTargetOpDef v_v_v = { .args_ct_str = { "v", "v", "v" } };
-    static const TCGTargetOpDef v_v_v_v
-        = { .args_ct_str = { "v", "v", "v", "v" } };
-
     switch (op) {
     case INDEX_op_goto_ptr:
-        return &r;
+        return C_O0_I1(r);
 
     case INDEX_op_ld8u_i32:
     case INDEX_op_ld8s_i32:
     case INDEX_op_ld16u_i32:
     case INDEX_op_ld16s_i32:
     case INDEX_op_ld_i32:
-    case INDEX_op_st8_i32:
-    case INDEX_op_st16_i32:
-    case INDEX_op_st_i32:
     case INDEX_op_ctpop_i32:
     case INDEX_op_neg_i32:
     case INDEX_op_not_i32:
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
     case INDEX_op_ld32u_i64:
     case INDEX_op_ld32s_i64:
     case INDEX_op_ld_i64:
-    case INDEX_op_st8_i64:
-    case INDEX_op_st16_i64:
-    case INDEX_op_st32_i64:
-    case INDEX_op_st_i64:
     case INDEX_op_ctpop_i64:
     case INDEX_op_neg_i64:
     case INDEX_op_not_i64:
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
     case INDEX_op_bswap32_i64:
     case INDEX_op_bswap64_i64:
     case INDEX_op_extract_i64:
-        return &r_r;
+        return C_O1_I1(r, r);
+
+    case INDEX_op_st8_i32:
+    case INDEX_op_st16_i32:
+    case INDEX_op_st_i32:
+    case INDEX_op_st8_i64:
+    case INDEX_op_st16_i64:
+    case INDEX_op_st32_i64:
+    case INDEX_op_st_i64:
+        return C_O0_I2(r, r);
 
     case INDEX_op_add_i32:
     case INDEX_op_and_i32:
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
     case INDEX_op_rotl_i64:
     case INDEX_op_rotr_i64:
     case INDEX_op_setcond_i64:
-        return &r_r_ri;
+        return C_O1_I2(r, r, ri);
+
     case INDEX_op_mul_i32:
     case INDEX_op_mul_i64:
-        return &r_r_rI;
+        return C_O1_I2(r, r, rI);
+
     case INDEX_op_div_i32:
     case INDEX_op_divu_i32:
     case INDEX_op_nand_i32:
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
     case INDEX_op_divu_i64:
     case INDEX_op_mulsh_i64:
     case INDEX_op_muluh_i64:
-        return &r_r_r;
+        return C_O1_I2(r, r, r);
+
     case INDEX_op_sub_i32:
-        return &r_rI_ri;
+        return C_O1_I2(r, rI, ri);
     case INDEX_op_add_i64:
-        return &r_r_rT;
+        return C_O1_I2(r, r, rT);
     case INDEX_op_or_i64:
     case INDEX_op_xor_i64:
-        return &r_r_rU;
+        return C_O1_I2(r, r, rU);
     case INDEX_op_sub_i64:
-        return &r_rI_rT;
+        return C_O1_I2(r, rI, rT);
     case INDEX_op_clz_i32:
     case INDEX_op_ctz_i32:
     case INDEX_op_clz_i64:
     case INDEX_op_ctz_i64:
-        return &r_r_rZW;
+        return C_O1_I2(r, r, rZW);
 
     case INDEX_op_brcond_i32:
     case INDEX_op_brcond_i64:
-        return &r_ri;
+        return C_O0_I2(r, ri);
 
     case INDEX_op_movcond_i32:
     case INDEX_op_movcond_i64:
-        return &movc;
+        return C_O1_I4(r, r, ri, rZ, rZ);
     case INDEX_op_deposit_i32:
     case INDEX_op_deposit_i64:
-        return &dep;
+        return C_O1_I2(r, 0, rZ);
     case INDEX_op_brcond2_i32:
-        return &br2;
+        return C_O0_I4(r, r, ri, ri);
     case INDEX_op_setcond2_i32:
-        return &setc2;
+        return C_O1_I4(r, r, r, ri, ri);
     case INDEX_op_add2_i64:
     case INDEX_op_add2_i32:
-        return &add2;
+        return C_O2_I4(r, r, r, r, rI, rZM);
     case INDEX_op_sub2_i64:
     case INDEX_op_sub2_i32:
-        return &sub2;
+        return C_O2_I4(r, r, rI, rZM, r, r);
 
     case INDEX_op_qemu_ld_i32:
         return (TCG_TARGET_REG_BITS == 64 || TARGET_LONG_BITS == 32
-                ? &r_L : &r_L_L);
+                ? C_O1_I1(r, L)
+                : C_O1_I2(r, L, L));
+
     case INDEX_op_qemu_st_i32:
         return (TCG_TARGET_REG_BITS == 64 || TARGET_LONG_BITS == 32
-                ? &S_S : &S_S_S);
+                ? C_O0_I2(S, S)
+                : C_O0_I3(S, S, S));
+
     case INDEX_op_qemu_ld_i64:
-        return (TCG_TARGET_REG_BITS == 64 ? &r_L
-                : TARGET_LONG_BITS == 32 ? &L_L_L : &L_L_L_L);
+        return (TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, L)
+                : TARGET_LONG_BITS == 32 ? C_O2_I1(L, L, L)
+                : C_O2_I2(L, L, L, L));
+
     case INDEX_op_qemu_st_i64:
-        return (TCG_TARGET_REG_BITS == 64 ? &S_S
-                : TARGET_LONG_BITS == 32 ? &S_S_S : &S_S_S_S);
+        return (TCG_TARGET_REG_BITS == 64 ? C_O0_I2(S, S)
+                : TARGET_LONG_BITS == 32 ? C_O0_I3(S, S, S)
+                : C_O0_I4(S, S, S, S));
 
     case INDEX_op_add_vec:
     case INDEX_op_sub_vec:
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
     case INDEX_op_ppc_mulou_vec:
     case INDEX_op_ppc_pkum_vec:
     case INDEX_op_dup2_vec:
-        return &v_v_v;
+        return C_O1_I2(v, v, v);
+
     case INDEX_op_not_vec:
     case INDEX_op_neg_vec:
-        return &v_v;
+        return C_O1_I1(v, v);
+
     case INDEX_op_dup_vec:
-        return have_isa_3_00 ? &v_vr : &v_v;
+        return have_isa_3_00 ? C_O1_I1(v, vr) : C_O1_I1(v, v);
+
     case INDEX_op_ld_vec:
-    case INDEX_op_st_vec:
     case INDEX_op_dupm_vec:
-        return &v_r;
+        return C_O1_I1(v, r);
+
+    case INDEX_op_st_vec:
+        return C_O0_I2(v, r);
+
     case INDEX_op_bitsel_vec:
     case INDEX_op_ppc_msum_vec:
-        return &v_v_v_v;
+        return C_O1_I3(v, v, v, v);
 
     default:
-        return NULL;
+        g_assert_not_reached();
     }
 }
 
-- 
2.25.1

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/riscv/tcg-target-con-set.h | 30 ++++++++++++
 tcg/riscv/tcg-target.h         |  1 +
 tcg/riscv/tcg-target.c.inc     | 83 ++++++++++------------------------
 3 files changed, 54 insertions(+), 60 deletions(-)
 create mode 100644 tcg/riscv/tcg-target-con-set.h

diff --git a/tcg/riscv/tcg-target-con-set.h b/tcg/riscv/tcg-target-con-set.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/tcg/riscv/tcg-target-con-set.h
@@ -XXX,XX +XXX,XX @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Define RISC-V target-specific constraint sets.
+ * Copyright (c) 2021 Linaro
+ */
+
+/*
+ * C_On_Im(...) defines a constraint set with <n> outputs and <m> inputs.
+ * Each operand should be a sequence of constraint letters as defined by
+ * tcg-target-con-str.h; the constraint combination is inclusive or.
+ */
+C_O0_I1(r)
+C_O0_I2(LZ, L)
+C_O0_I2(rZ, r)
+C_O0_I2(rZ, rZ)
+C_O0_I3(LZ, L, L)
+C_O0_I3(LZ, LZ, L)
+C_O0_I4(LZ, LZ, L, L)
+C_O0_I4(rZ, rZ, rZ, rZ)
+C_O1_I1(r, L)
+C_O1_I1(r, r)
+C_O1_I2(r, L, L)
+C_O1_I2(r, r, ri)
+C_O1_I2(r, r, rI)
+C_O1_I2(r, rZ, rN)
+C_O1_I2(r, rZ, rZ)
+C_O1_I4(r, rZ, rZ, rZ, rZ)
+C_O2_I1(r, r, L)
+C_O2_I2(r, r, L, L)
+C_O2_I4(r, r, rZ, rZ, rM, rM)
diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h
index XXXXXXX..XXXXXXX 100644
--- a/tcg/riscv/tcg-target.h
+++ b/tcg/riscv/tcg-target.h
@@ -XXX,XX +XXX,XX @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t);
 #define TCG_TARGET_NEED_POOL_LABELS
 
 #define TCG_TARGET_HAS_MEMORY_BSWAP 0
+#define TCG_TARGET_CON_SET_H
 
 #endif
diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/riscv/tcg-target.c.inc
+++ b/tcg/riscv/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
     }
 }
 
-static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
+static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
 {
-    static const TCGTargetOpDef r
-        = { .args_ct_str = { "r" } };
-    static const TCGTargetOpDef r_r
-        = { .args_ct_str = { "r", "r" } };
-    static const TCGTargetOpDef rZ_r
-        = { .args_ct_str = { "rZ", "r" } };
-    static const TCGTargetOpDef rZ_rZ
-        = { .args_ct_str = { "rZ", "rZ" } };
-    static const TCGTargetOpDef rZ_rZ_rZ_rZ
-        = { .args_ct_str = { "rZ", "rZ", "rZ", "rZ" } };
-    static const TCGTargetOpDef r_r_ri
-        = { .args_ct_str = { "r", "r", "ri" } };
-    static const TCGTargetOpDef r_r_rI
-        = { .args_ct_str = { "r", "r", "rI" } };
-    static const TCGTargetOpDef r_rZ_rN
-        = { .args_ct_str = { "r", "rZ", "rN" } };
-    static const TCGTargetOpDef r_rZ_rZ
-        = { .args_ct_str = { "r", "rZ", "rZ" } };
-    static const TCGTargetOpDef r_rZ_rZ_rZ_rZ
-        = { .args_ct_str = { "r", "rZ", "rZ", "rZ", "rZ" } };
-    static const TCGTargetOpDef r_L
-        = { .args_ct_str = { "r", "L" } };
-    static const TCGTargetOpDef r_r_L
-        = { .args_ct_str = { "r", "r", "L" } };
-    static const TCGTargetOpDef r_L_L
-        = { .args_ct_str = { "r", "L", "L" } };
-    static const TCGTargetOpDef r_r_L_L
-        = { .args_ct_str = { "r", "r", "L", "L" } };
-    static const TCGTargetOpDef LZ_L
-        = { .args_ct_str = { "LZ", "L" } };
-    static const TCGTargetOpDef LZ_L_L
-        = { .args_ct_str = { "LZ", "L", "L" } };
-    static const TCGTargetOpDef LZ_LZ_L
-        = { .args_ct_str = { "LZ", "LZ", "L" } };
-    static const TCGTargetOpDef LZ_LZ_L_L
-        = { .args_ct_str = { "LZ", "LZ", "L", "L" } };
-    static const TCGTargetOpDef r_r_rZ_rZ_rM_rM
-        = { .args_ct_str = { "r", "r", "rZ", "rZ", "rM", "rM" } };
-
     switch (op) {
     case INDEX_op_goto_ptr:
-        return &r;
+        return C_O0_I1(r);
 
     case INDEX_op_ld8u_i32:
     case INDEX_op_ld8s_i32:
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
     case INDEX_op_extrl_i64_i32:
     case INDEX_op_extrh_i64_i32:
     case INDEX_op_ext_i32_i64:
-        return &r_r;
+        return C_O1_I1(r, r);
 
     case INDEX_op_st8_i32:
     case INDEX_op_st16_i32:
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
     case INDEX_op_st16_i64:
     case INDEX_op_st32_i64:
     case INDEX_op_st_i64:
-        return &rZ_r;
+        return C_O0_I2(rZ, r);
 
     case INDEX_op_add_i32:
     case INDEX_op_and_i32:
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
     case INDEX_op_and_i64:
     case INDEX_op_or_i64:
     case INDEX_op_xor_i64:
-        return &r_r_rI;
+        return C_O1_I2(r, r, rI);
 
     case INDEX_op_sub_i32:
     case INDEX_op_sub_i64:
-        return &r_rZ_rN;
+        return C_O1_I2(r, rZ, rN);
 
     case INDEX_op_mul_i32:
     case INDEX_op_mulsh_i32:
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
     case INDEX_op_rem_i64:
     case INDEX_op_remu_i64:
     case INDEX_op_setcond_i64:
-        return &r_rZ_rZ;
+        return C_O1_I2(r, rZ, rZ);
 
     case INDEX_op_shl_i32:
     case INDEX_op_shr_i32:
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
     case INDEX_op_shl_i64:
     case INDEX_op_shr_i64:
     case INDEX_op_sar_i64:
-        return &r_r_ri;
+        return C_O1_I2(r, r, ri);
 
     case INDEX_op_brcond_i32:
     case INDEX_op_brcond_i64:
-        return &rZ_rZ;
+        return C_O0_I2(rZ, rZ);
 
     case INDEX_op_add2_i32:
     case INDEX_op_add2_i64:
     case INDEX_op_sub2_i32:
     case INDEX_op_sub2_i64:
-        return &r_r_rZ_rZ_rM_rM;
+        return C_O2_I4(r, r, rZ, rZ, rM, rM);
 
     case INDEX_op_brcond2_i32:
-        return &rZ_rZ_rZ_rZ;
+        return C_O0_I4(rZ, rZ, rZ, rZ);
 
     case INDEX_op_setcond2_i32:
-        return &r_rZ_rZ_rZ_rZ;
+        return C_O1_I4(r, rZ, rZ, rZ, rZ);
 
     case INDEX_op_qemu_ld_i32:
-        return TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &r_L : &r_L_L;
+        return (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS
+                ? C_O1_I1(r, L) : C_O1_I2(r, L, L));
     case INDEX_op_qemu_st_i32:
-        return TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &LZ_L : &LZ_L_L;
+        return (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS
+                ? C_O0_I2(LZ, L) : C_O0_I3(LZ, L, L));
     case INDEX_op_qemu_ld_i64:
-        return TCG_TARGET_REG_BITS == 64 ? &r_L
-               : TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &r_r_L
-               : &r_r_L_L;
+        return (TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, L)
+               : TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? C_O2_I1(r, r, L)
+               : C_O2_I2(r, r, L, L));
     case INDEX_op_qemu_st_i64:
-        return TCG_TARGET_REG_BITS == 64 ? &LZ_L
-               : TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &LZ_LZ_L
-               : &LZ_LZ_L_L;
+        return (TCG_TARGET_REG_BITS == 64 ? C_O0_I2(LZ, L)
+               : TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? C_O0_I3(LZ, LZ, L)
+               : C_O0_I4(LZ, LZ, L, L));
 
     default:
-        return NULL;
+        g_assert_not_reached();
     }
 }
 
-- 
2.25.1

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/s390/tcg-target-con-set.h |  29 ++++++++
 tcg/s390/tcg-target.h         |   1 +
 tcg/s390/tcg-target.c.inc     | 121 ++++++++++++++--------------------
 3 files changed, 81 insertions(+), 70 deletions(-)
 create mode 100644 tcg/s390/tcg-target-con-set.h

diff --git a/tcg/s390/tcg-target-con-set.h b/tcg/s390/tcg-target-con-set.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/tcg/s390/tcg-target-con-set.h
@@ -XXX,XX +XXX,XX @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Define S390 target-specific constraint sets.
+ * Copyright (c) 2021 Linaro
+ */
+
+/*
+ * C_On_Im(...) defines a constraint set with <n> outputs and <m> inputs.
+ * Each operand should be a sequence of constraint letters as defined by
+ * tcg-target-con-str.h; the constraint combination is inclusive or.
+ */
+C_O0_I1(r)
+C_O0_I2(L, L)
+C_O0_I2(r, r)
+C_O0_I2(r, ri)
+C_O1_I1(r, L)
+C_O1_I1(r, r)
+C_O1_I2(r, 0, ri)
+C_O1_I2(r, 0, rI)
+C_O1_I2(r, 0, rJ)
+C_O1_I2(r, r, ri)
+C_O1_I2(r, rZ, r)
+C_O1_I4(r, r, ri, r, 0)
+C_O1_I4(r, r, ri, rI, 0)
+C_O2_I2(b, a, 0, r)
+C_O2_I3(b, a, 0, 1, r)
+C_O2_I4(r, r, 0, 1, rA, r)
+C_O2_I4(r, r, 0, 1, ri, r)
+C_O2_I4(r, r, 0, 1, r, r)
diff --git a/tcg/s390/tcg-target.h b/tcg/s390/tcg-target.h
index XXXXXXX..XXXXXXX 100644
--- a/tcg/s390/tcg-target.h
+++ b/tcg/s390/tcg-target.h
@@ -XXX,XX +XXX,XX @@ static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_rx,
 #define TCG_TARGET_NEED_LDST_LABELS
 #endif
 #define TCG_TARGET_NEED_POOL_LABELS
+#define TCG_TARGET_CON_SET_H
 
 #endif
diff --git a/tcg/s390/tcg-target.c.inc b/tcg/s390/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/s390/tcg-target.c.inc
+++ b/tcg/s390/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
     }
 }
 
-static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
+static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
 {
-    static const TCGTargetOpDef r = { .args_ct_str = { "r" } };
-    static const TCGTargetOpDef r_r = { .args_ct_str = { "r", "r" } };
-    static const TCGTargetOpDef r_L = { .args_ct_str = { "r", "L" } };
-    static const TCGTargetOpDef L_L = { .args_ct_str = { "L", "L" } };
-    static const TCGTargetOpDef r_ri = { .args_ct_str = { "r", "ri" } };
-    static const TCGTargetOpDef r_r_ri = { .args_ct_str = { "r", "r", "ri" } };
-    static const TCGTargetOpDef r_0_ri = { .args_ct_str = { "r", "0", "ri" } };
-    static const TCGTargetOpDef r_0_rI = { .args_ct_str = { "r", "0", "rI" } };
-    static const TCGTargetOpDef r_0_rJ = { .args_ct_str = { "r", "0", "rJ" } };
-    static const TCGTargetOpDef a2_r
-        = { .args_ct_str = { "r", "r", "0", "1", "r", "r" } };
-    static const TCGTargetOpDef a2_ri
-        = { .args_ct_str = { "r", "r", "0", "1", "ri", "r" } };
-    static const TCGTargetOpDef a2_rA
-        = { .args_ct_str = { "r", "r", "0", "1", "rA", "r" } };
-
     switch (op) {
     case INDEX_op_goto_ptr:
-        return &r;
+        return C_O0_I1(r);
 
     case INDEX_op_ld8u_i32:
     case INDEX_op_ld8u_i64:
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
     case INDEX_op_ld32u_i64:
     case INDEX_op_ld32s_i64:
     case INDEX_op_ld_i64:
+        return C_O1_I1(r, r);
+
     case INDEX_op_st8_i32:
     case INDEX_op_st8_i64:
     case INDEX_op_st16_i32:
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
     case INDEX_op_st_i32:
     case INDEX_op_st32_i64:
     case INDEX_op_st_i64:
-        return &r_r;
+        return C_O0_I2(r, r);
 
     case INDEX_op_add_i32:
     case INDEX_op_add_i64:
-        return &r_r_ri;
+    case INDEX_op_shl_i64:
+    case INDEX_op_shr_i64:
+    case INDEX_op_sar_i64:
+    case INDEX_op_rotl_i32:
+    case INDEX_op_rotl_i64:
+    case INDEX_op_rotr_i32:
+    case INDEX_op_rotr_i64:
+    case INDEX_op_clz_i64:
+    case INDEX_op_setcond_i32:
+    case INDEX_op_setcond_i64:
+        return C_O1_I2(r, r, ri);
+
     case INDEX_op_sub_i32:
     case INDEX_op_sub_i64:
     case INDEX_op_and_i32:
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
     case INDEX_op_or_i64:
     case INDEX_op_xor_i32:
     case INDEX_op_xor_i64:
-        return (s390_facilities & FACILITY_DISTINCT_OPS ? &r_r_ri : &r_0_ri);
+        return (s390_facilities & FACILITY_DISTINCT_OPS
+                ? C_O1_I2(r, r, ri)
+                : C_O1_I2(r, 0, ri));
 
     case INDEX_op_mul_i32:
         /* If we have the general-instruction-extensions, then we have
            MULTIPLY SINGLE IMMEDIATE with a signed 32-bit, otherwise we
            have only MULTIPLY HALFWORD IMMEDIATE, with a signed 16-bit.  */
-        return (s390_facilities & FACILITY_GEN_INST_EXT ? &r_0_ri : &r_0_rI);
+        return (s390_facilities & FACILITY_GEN_INST_EXT
+                ? C_O1_I2(r, 0, ri)
+                : C_O1_I2(r, 0, rI));
+
     case INDEX_op_mul_i64:
-        return (s390_facilities & FACILITY_GEN_INST_EXT ? &r_0_rJ : &r_0_rI);
+        return (s390_facilities & FACILITY_GEN_INST_EXT
+                ? C_O1_I2(r, 0, rJ)
+                : C_O1_I2(r, 0, rI));
 
     case INDEX_op_shl_i32:
     case INDEX_op_shr_i32:
     case INDEX_op_sar_i32:
-        return (s390_facilities & FACILITY_DISTINCT_OPS ? &r_r_ri : &r_0_ri);
-
-    case INDEX_op_shl_i64:
-    case INDEX_op_shr_i64:
-    case INDEX_op_sar_i64:
-        return &r_r_ri;
-
-    case INDEX_op_rotl_i32:
-    case INDEX_op_rotl_i64:
-    case INDEX_op_rotr_i32:
-    case INDEX_op_rotr_i64:
-        return &r_r_ri;
+        return (s390_facilities & FACILITY_DISTINCT_OPS
+                ? C_O1_I2(r, r, ri)
+                : C_O1_I2(r, 0, ri));
 
     case INDEX_op_brcond_i32:
     case INDEX_op_brcond_i64:
-        return &r_ri;
+        return C_O0_I2(r, ri);
 
     case INDEX_op_bswap16_i32:
     case INDEX_op_bswap16_i64:
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
     case INDEX_op_extu_i32_i64:
     case INDEX_op_extract_i32:
     case INDEX_op_extract_i64:
-        return &r_r;
-
-    case INDEX_op_clz_i64:
-    case INDEX_op_setcond_i32:
-    case INDEX_op_setcond_i64:
-        return &r_r_ri;
+        return C_O1_I1(r, r);
 
     case INDEX_op_qemu_ld_i32:
     case INDEX_op_qemu_ld_i64:
-        return &r_L;
+        return C_O1_I1(r, L);
     case INDEX_op_qemu_st_i64:
     case INDEX_op_qemu_st_i32:
-        return &L_L;
+        return C_O0_I2(L, L);
 
     case INDEX_op_deposit_i32:
     case INDEX_op_deposit_i64:
-        {
-            static const TCGTargetOpDef dep
-                = { .args_ct_str = { "r", "rZ", "r" } };
-            return &dep;
-        }
+        return C_O1_I2(r, rZ, r);
+
     case INDEX_op_movcond_i32:
     case INDEX_op_movcond_i64:
-        {
-            static const TCGTargetOpDef movc
-                = { .args_ct_str = { "r", "r", "ri", "r", "0" } };
-            static const TCGTargetOpDef movc_l
-                = { .args_ct_str = { "r", "r", "ri", "rI", "0" } };
-            return (s390_facilities & FACILITY_LOAD_ON_COND2 ? &movc_l : &movc);
-        }
+        return (s390_facilities & FACILITY_LOAD_ON_COND2
+                ? C_O1_I4(r, r, ri, rI, 0)
+                : C_O1_I4(r, r, ri, r, 0));
+
     case INDEX_op_div2_i32:
     case INDEX_op_div2_i64:
     case INDEX_op_divu2_i32:
     case INDEX_op_divu2_i64:
-        {
-            static const TCGTargetOpDef div2
-                = { .args_ct_str = { "b", "a", "0", "1", "r" } };
-            return &div2;
-        }
+        return C_O2_I3(b, a, 0, 1, r);
+
     case INDEX_op_mulu2_i64:
-        {
-            static const TCGTargetOpDef mul2
-                = { .args_ct_str = { "b", "a", "0", "r" } };
-            return &mul2;
-        }
+        return C_O2_I2(b, a, 0, r);
 
     case INDEX_op_add2_i32:
     case INDEX_op_sub2_i32:
-        return (s390_facilities & FACILITY_EXT_IMM ? &a2_ri : &a2_r);
+        return (s390_facilities & FACILITY_EXT_IMM
+                ? C_O2_I4(r, r, 0, 1, ri, r)
+                : C_O2_I4(r, r, 0, 1, r, r));
+
     case INDEX_op_add2_i64:
     case INDEX_op_sub2_i64:
-        return (s390_facilities & FACILITY_EXT_IMM ? &a2_rA : &a2_r);
+        return (s390_facilities & FACILITY_EXT_IMM
+                ? C_O2_I4(r, r, 0, 1, rA, r)
+                : C_O2_I4(r, r, 0, 1, r, r));
 
     default:
-        break;
+        g_assert_not_reached();
     }
-    return NULL;
 }
 
 static void query_s390_facilities(void)
-- 
2.25.1

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/sparc/tcg-target-con-set.h | 32 +++++++++++++++
 tcg/sparc/tcg-target.h         |  1 +
 tcg/sparc/tcg-target.c.inc     | 75 +++++++++++-----------------------
 3 files changed, 56 insertions(+), 52 deletions(-)
 create mode 100644 tcg/sparc/tcg-target-con-set.h

diff --git a/tcg/sparc/tcg-target-con-set.h b/tcg/sparc/tcg-target-con-set.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/tcg/sparc/tcg-target-con-set.h
@@ -XXX,XX +XXX,XX @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Define Sparc target-specific constraint sets.
+ * Copyright (c) 2021 Linaro
+ */
+
+/*
+ * C_On_Im(...) defines a constraint set with <n> outputs and <m> inputs.
+ * Each operand should be a sequence of constraint letters as defined by
+ * tcg-target-con-str.h; the constraint combination is inclusive or.
+ */
+C_O0_I1(r)
+C_O0_I2(rZ, r)
+C_O0_I2(RZ, r)
+C_O0_I2(rZ, rJ)
+C_O0_I2(RZ, RJ)
+C_O0_I2(sZ, A)
+C_O0_I2(SZ, A)
+C_O1_I1(r, A)
+C_O1_I1(R, A)
+C_O1_I1(r, r)
+C_O1_I1(r, R)
+C_O1_I1(R, r)
+C_O1_I1(R, R)
+C_O1_I2(R, R, R)
+C_O1_I2(r, rZ, rJ)
+C_O1_I2(R, RZ, RJ)
+C_O1_I4(r, rZ, rJ, rI, 0)
+C_O1_I4(R, RZ, RJ, RI, 0)
+C_O2_I2(r, r, rZ, rJ)
+C_O2_I4(R, R, RZ, RZ, RJ, RI)
+C_O2_I4(r, r, rZ, rZ, rJ, rJ)
diff --git a/tcg/sparc/tcg-target.h b/tcg/sparc/tcg-target.h
index XXXXXXX..XXXXXXX 100644
--- a/tcg/sparc/tcg-target.h
+++ b/tcg/sparc/tcg-target.h
@@ -XXX,XX +XXX,XX @@ extern bool use_vis3_instructions;
 void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t);
 
 #define TCG_TARGET_NEED_POOL_LABELS
+#define TCG_TARGET_CON_SET_H
 
 #endif
diff --git a/tcg/sparc/tcg-target.c.inc b/tcg/sparc/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/sparc/tcg-target.c.inc
+++ b/tcg/sparc/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
     }
 }
 
-static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
+static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
 {
-    static const TCGTargetOpDef r = { .args_ct_str = { "r" } };
-    static const TCGTargetOpDef r_r = { .args_ct_str = { "r", "r" } };
-    static const TCGTargetOpDef R_r = { .args_ct_str = { "R", "r" } };
-    static const TCGTargetOpDef r_R = { .args_ct_str = { "r", "R" } };
-    static const TCGTargetOpDef R_R = { .args_ct_str = { "R", "R" } };
-    static const TCGTargetOpDef r_A = { .args_ct_str = { "r", "A" } };
-    static const TCGTargetOpDef R_A = { .args_ct_str = { "R", "A" } };
-    static const TCGTargetOpDef rZ_r = { .args_ct_str = { "rZ", "r" } };
-    static const TCGTargetOpDef RZ_r = { .args_ct_str = { "RZ", "r" } };
-    static const TCGTargetOpDef sZ_A = { .args_ct_str = { "sZ", "A" } };
-    static const TCGTargetOpDef SZ_A = { .args_ct_str = { "SZ", "A" } };
-    static const TCGTargetOpDef rZ_rJ = { .args_ct_str = { "rZ", "rJ" } };
-    static const TCGTargetOpDef RZ_RJ = { .args_ct_str = { "RZ", "RJ" } };
-    static const TCGTargetOpDef R_R_R = { .args_ct_str = { "R", "R", "R" } };
-    static const TCGTargetOpDef r_rZ_rJ
-        = { .args_ct_str = { "r", "rZ", "rJ" } };
-    static const TCGTargetOpDef R_RZ_RJ
-        = { .args_ct_str = { "R", "RZ", "RJ" } };
-    static const TCGTargetOpDef r_r_rZ_rJ
-        = { .args_ct_str = { "r", "r", "rZ", "rJ" } };
-    static const TCGTargetOpDef movc_32
-        = { .args_ct_str = { "r", "rZ", "rJ", "rI", "0" } };
-    static const TCGTargetOpDef movc_64
-        = { .args_ct_str = { "R", "RZ", "RJ", "RI", "0" } };
-    static const TCGTargetOpDef add2_32
-        = { .args_ct_str = { "r", "r", "rZ", "rZ", "rJ", "rJ" } };
-    static const TCGTargetOpDef add2_64
-        = { .args_ct_str = { "R", "R", "RZ", "RZ", "RJ", "RI" } };
-
     switch (op) {
     case INDEX_op_goto_ptr:
-        return &r;
+        return C_O0_I1(r);
 
     case INDEX_op_ld8u_i32:
     case INDEX_op_ld8s_i32:
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
     case INDEX_op_ld_i32:
     case INDEX_op_neg_i32:
     case INDEX_op_not_i32:
-        return &r_r;
+        return C_O1_I1(r, r);
 
     case INDEX_op_st8_i32:
     case INDEX_op_st16_i32:
     case INDEX_op_st_i32:
-        return &rZ_r;
+        return C_O0_I2(rZ, r);
 
     case INDEX_op_add_i32:
     case INDEX_op_mul_i32:
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
     case INDEX_op_shr_i32:
     case INDEX_op_sar_i32:
     case INDEX_op_setcond_i32:
-        return &r_rZ_rJ;
+        return C_O1_I2(r, rZ, rJ);
 
     case INDEX_op_brcond_i32:
-        return &rZ_rJ;
+        return C_O0_I2(rZ, rJ);
     case INDEX_op_movcond_i32:
-        return &movc_32;
+        return C_O1_I4(r, rZ, rJ, rI, 0);
     case INDEX_op_add2_i32:
     case INDEX_op_sub2_i32:
-        return &add2_32;
+        return C_O2_I4(r, r, rZ, rZ, rJ, rJ);
     case INDEX_op_mulu2_i32:
     case INDEX_op_muls2_i32:
-        return &r_r_rZ_rJ;
+        return C_O2_I2(r, r, rZ, rJ);
 
     case INDEX_op_ld8u_i64:
     case INDEX_op_ld8s_i64:
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
     case INDEX_op_ld_i64:
     case INDEX_op_ext_i32_i64:
     case INDEX_op_extu_i32_i64:
-        return &R_r;
+        return C_O1_I1(R, r);
 
     case INDEX_op_st8_i64:
     case INDEX_op_st16_i64:
     case INDEX_op_st32_i64:
     case INDEX_op_st_i64:
-        return &RZ_r;
+        return C_O0_I2(RZ, r);
 
     case INDEX_op_add_i64:
     case INDEX_op_mul_i64:
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
     case INDEX_op_shr_i64:
     case INDEX_op_sar_i64:
     case INDEX_op_setcond_i64:
-        return &R_RZ_RJ;
+        return C_O1_I2(R, RZ, RJ);
 
     case INDEX_op_neg_i64:
     case INDEX_op_not_i64:
     case INDEX_op_ext32s_i64:
     case INDEX_op_ext32u_i64:
-        return &R_R;
+        return C_O1_I1(R, R);
 
     case INDEX_op_extrl_i64_i32:
     case INDEX_op_extrh_i64_i32:
-        return &r_R;
+        return C_O1_I1(r, R);
 
     case INDEX_op_brcond_i64:
-        return &RZ_RJ;
+        return C_O0_I2(RZ, RJ);
     case INDEX_op_movcond_i64:
-        return &movc_64;
+        return C_O1_I4(R, RZ, RJ, RI, 0);
     case INDEX_op_add2_i64:
     case INDEX_op_sub2_i64:
-        return &add2_64;
+        return C_O2_I4(R, R, RZ, RZ, RJ, RI);
     case INDEX_op_muluh_i64:
-        return &R_R_R;
+        return C_O1_I2(R, R, R);
 
     case INDEX_op_qemu_ld_i32:
-        return &r_A;
+        return C_O1_I1(r, A);
     case INDEX_op_qemu_ld_i64:
-        return &R_A;
+        return C_O1_I1(R, A);
     case INDEX_op_qemu_st_i32:
-        return &sZ_A;
+        return C_O0_I2(sZ, A);
     case INDEX_op_qemu_st_i64:
-        return &SZ_A;
+        return C_O0_I2(SZ, A);
 
     default:
-        return NULL;
+        g_assert_not_reached();
     }
 }
 
-- 
2.25.1

This requires finishing the conversion to tcg_target_op_def.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/tci/tcg-target-con-set.h |  25 ++++
 tcg/tci/tcg-target.h         |   2 +
 tcg/tci/tcg-target.c.inc     | 279 +++++++++++++++++------------------
 3 files changed, 161 insertions(+), 145 deletions(-)
 create mode 100644 tcg/tci/tcg-target-con-set.h

diff --git a/tcg/tci/tcg-target-con-set.h b/tcg/tci/tcg-target-con-set.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/tcg/tci/tcg-target-con-set.h
@@ -XXX,XX +XXX,XX @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * TCI target-specific constraint sets.
+ * Copyright (c) 2021 Linaro
+ */
+
+/*
+ * C_On_Im(...) defines a constraint set with <n> outputs and <m> inputs.
+ * Each operand should be a sequence of constraint letters as defined by
+ * tcg-target-con-str.h; the constraint combination is inclusive or.
+ */
+C_O0_I2(r, r)
+C_O0_I2(r, ri)
+C_O0_I3(r, r, r)
+C_O0_I4(r, r, ri, ri)
+C_O0_I4(r, r, r, r)
+C_O1_I1(r, r)
+C_O1_I2(r, 0, r)
+C_O1_I2(r, ri, ri)
+C_O1_I2(r, r, r)
+C_O1_I2(r, r, ri)
+C_O1_I4(r, r, r, ri, ri)
+C_O2_I1(r, r, r)
+C_O2_I2(r, r, r, r)
+C_O2_I4(r, r, r, r, r, r)
diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h
index XXXXXXX..XXXXXXX 100644
--- a/tcg/tci/tcg-target.h
+++ b/tcg/tci/tcg-target.h
@@ -XXX,XX +XXX,XX @@ static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_rx,
     /* no need to flush icache explicitly */
 }
 
+#define TCG_TARGET_CON_SET_H
+
 #endif /* TCG_TARGET_H */
diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/tci/tcg-target.c.inc
+++ b/tcg/tci/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@
 /* Bitfield n...m (in 32 bit value). */
 #define BITS(n, m) (((0xffffffffU << (31 - n)) >> (31 - n + m)) << m)
 
-/* Macros used in tcg_target_op_defs. */
-#define R       "r"
-#define RI      "ri"
-#if TCG_TARGET_REG_BITS == 32
-# define R64    "r", "r"
-#else
-# define R64    "r"
-#endif
-#if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
-# define L      "r", "r"
-# define S      "r", "r"
-#else
-# define L      "r"
-# define S      "r"
-#endif
-
-/* TODO: documentation. */
-static const TCGTargetOpDef tcg_target_op_defs[] = {
-    { INDEX_op_exit_tb, { NULL } },
-    { INDEX_op_goto_tb, { NULL } },
-    { INDEX_op_br, { NULL } },
-
-    { INDEX_op_ld8u_i32, { R, R } },
-    { INDEX_op_ld8s_i32, { R, R } },
-    { INDEX_op_ld16u_i32, { R, R } },
-    { INDEX_op_ld16s_i32, { R, R } },
-    { INDEX_op_ld_i32, { R, R } },
-    { INDEX_op_st8_i32, { R, R } },
-    { INDEX_op_st16_i32, { R, R } },
-    { INDEX_op_st_i32, { R, R } },
-
-    { INDEX_op_add_i32, { R, RI, RI } },
-    { INDEX_op_sub_i32, { R, RI, RI } },
-    { INDEX_op_mul_i32, { R, RI, RI } },
-    { INDEX_op_div_i32, { R, R, R } },
-    { INDEX_op_divu_i32, { R, R, R } },
-    { INDEX_op_rem_i32, { R, R, R } },
-    { INDEX_op_remu_i32, { R, R, R } },
-    /* TODO: Does R, RI, RI result in faster code than R, R, RI?
-       If both operands are constants, we can optimize. */
-    { INDEX_op_and_i32, { R, RI, RI } },
-    { INDEX_op_andc_i32, { R, RI, RI } },
-    { INDEX_op_eqv_i32, { R, RI, RI } },
-    { INDEX_op_nand_i32, { R, RI, RI } },
-    { INDEX_op_nor_i32, { R, RI, RI } },
-    { INDEX_op_or_i32, { R, RI, RI } },
-    { INDEX_op_orc_i32, { R, RI, RI } },
-    { INDEX_op_xor_i32, { R, RI, RI } },
-    { INDEX_op_shl_i32, { R, RI, RI } },
-    { INDEX_op_shr_i32, { R, RI, RI } },
-    { INDEX_op_sar_i32, { R, RI, RI } },
-    { INDEX_op_rotl_i32, { R, RI, RI } },
-    { INDEX_op_rotr_i32, { R, RI, RI } },
-    { INDEX_op_deposit_i32, { R, "0", R } },
-
-    { INDEX_op_brcond_i32, { R, RI } },
-
-    { INDEX_op_setcond_i32, { R, R, RI } },
-    { INDEX_op_setcond_i64, { R, R, RI } },
-
-    /* TODO: Support R, R, R, R, RI, RI? Will it be faster? */
-    { INDEX_op_add2_i32, { R, R, R, R, R, R } },
-    { INDEX_op_sub2_i32, { R, R, R, R, R, R } },
-    { INDEX_op_brcond2_i32, { R, R, RI, RI } },
-    { INDEX_op_mulu2_i32, { R, R, R, R } },
-    { INDEX_op_setcond2_i32, { R, R, R, RI, RI } },
-
-    { INDEX_op_not_i32, { R, R } },
-    { INDEX_op_neg_i32, { R, R } },
-
-    { INDEX_op_ld8u_i64, { R, R } },
-    { INDEX_op_ld8s_i64, { R, R } },
-    { INDEX_op_ld16u_i64, { R, R } },
-    { INDEX_op_ld16s_i64, { R, R } },
-    { INDEX_op_ld32u_i64, { R, R } },
-    { INDEX_op_ld32s_i64, { R, R } },
-    { INDEX_op_ld_i64, { R, R } },
-
-    { INDEX_op_st8_i64, { R, R } },
-    { INDEX_op_st16_i64, { R, R } },
-    { INDEX_op_st32_i64, { R, R } },
-    { INDEX_op_st_i64, { R, R } },
-
-    { INDEX_op_add_i64, { R, RI, RI } },
-    { INDEX_op_sub_i64, { R, RI, RI } },
-    { INDEX_op_mul_i64, { R, RI, RI } },
-    { INDEX_op_div_i64, { R, R, R } },
-    { INDEX_op_divu_i64, { R, R, R } },
-    { INDEX_op_rem_i64, { R, R, R } },
-    { INDEX_op_remu_i64, { R, R, R } },
-    { INDEX_op_and_i64, { R, RI, RI } },
-    { INDEX_op_andc_i64, { R, RI, RI } },
-    { INDEX_op_eqv_i64, { R, RI, RI } },
-    { INDEX_op_nand_i64, { R, RI, RI } },
-    { INDEX_op_nor_i64, { R, RI, RI } },
-    { INDEX_op_or_i64, { R, RI, RI } },
-    { INDEX_op_orc_i64, { R, RI, RI } },
-    { INDEX_op_xor_i64, { R, RI, RI } },
-    { INDEX_op_shl_i64, { R, RI, RI } },
-    { INDEX_op_shr_i64, { R, RI, RI } },
-    { INDEX_op_sar_i64, { R, RI, RI } },
-    { INDEX_op_rotl_i64, { R, RI, RI } },
-    { INDEX_op_rotr_i64, { R, RI, RI } },
-    { INDEX_op_deposit_i64, { R, "0", R } },
-    { INDEX_op_brcond_i64, { R, RI } },
-
-    { INDEX_op_ext8s_i64, { R, R } },
-    { INDEX_op_ext16s_i64, { R, R } },
-    { INDEX_op_ext32s_i64, { R, R } },
-    { INDEX_op_ext8u_i64, { R, R } },
-    { INDEX_op_ext16u_i64, { R, R } },
-    { INDEX_op_ext32u_i64, { R, R } },
-    { INDEX_op_ext_i32_i64, { R, R } },
-    { INDEX_op_extu_i32_i64, { R, R } },
-    { INDEX_op_bswap16_i64, { R, R } },
-    { INDEX_op_bswap32_i64, { R, R } },
-    { INDEX_op_bswap64_i64, { R, R } },
-    { INDEX_op_not_i64, { R, R } },
-    { INDEX_op_neg_i64, { R, R } },
-
-    { INDEX_op_qemu_ld_i32, { R, L } },
-    { INDEX_op_qemu_ld_i64, { R64, L } },
-
-    { INDEX_op_qemu_st_i32, { R, S } },
-    { INDEX_op_qemu_st_i64, { R64, S } },
-
-    { INDEX_op_ext8s_i32, { R, R } },
-    { INDEX_op_ext16s_i32, { R, R } },
-    { INDEX_op_ext8u_i32, { R, R } },
-    { INDEX_op_ext16u_i32, { R, R } },
-
-    { INDEX_op_bswap16_i32, { R, R } },
-    { INDEX_op_bswap32_i32, { R, R } },
-
-    { INDEX_op_mb, { } },
-    { -1 },
-};
-
-static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
+static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
 {
-    int i, n = ARRAY_SIZE(tcg_target_op_defs);
+    switch (op) {
+    case INDEX_op_ld8u_i32:
+    case INDEX_op_ld8s_i32:
+    case INDEX_op_ld16u_i32:
+    case INDEX_op_ld16s_i32:
+    case INDEX_op_ld_i32:
+    case INDEX_op_ld8u_i64:
+    case INDEX_op_ld8s_i64:
+    case INDEX_op_ld16u_i64:
+    case INDEX_op_ld16s_i64:
+    case INDEX_op_ld32u_i64:
+    case INDEX_op_ld32s_i64:
+    case INDEX_op_ld_i64:
+    case INDEX_op_not_i32:
+    case INDEX_op_not_i64:
+    case INDEX_op_neg_i32:
+    case INDEX_op_neg_i64:
+    case INDEX_op_ext8s_i32:
+    case INDEX_op_ext8s_i64:
+    case INDEX_op_ext16s_i32:
+    case INDEX_op_ext16s_i64:
+    case INDEX_op_ext8u_i32:
+    case INDEX_op_ext8u_i64:
+    case INDEX_op_ext16u_i32:
+    case INDEX_op_ext16u_i64:
+    case INDEX_op_ext32s_i64:
+    case INDEX_op_ext32u_i64:
+    case INDEX_op_ext_i32_i64:
+    case INDEX_op_extu_i32_i64:
+    case INDEX_op_bswap16_i32:
+    case INDEX_op_bswap16_i64:
+    case INDEX_op_bswap32_i32:
+    case INDEX_op_bswap32_i64:
+    case INDEX_op_bswap64_i64:
+        return C_O1_I1(r, r);
 
-    for (i = 0; i < n; ++i) {
-        if (tcg_target_op_defs[i].op == op) {
-            return &tcg_target_op_defs[i];
-        }
+    case INDEX_op_st8_i32:
+    case INDEX_op_st16_i32:
+    case INDEX_op_st_i32:
+    case INDEX_op_st8_i64:
+    case INDEX_op_st16_i64:
+    case INDEX_op_st32_i64:
+    case INDEX_op_st_i64:
+        return C_O0_I2(r, r);
+
+    case INDEX_op_div_i32:
+    case INDEX_op_div_i64:
+    case INDEX_op_divu_i32:
+    case INDEX_op_divu_i64:
+    case INDEX_op_rem_i32:
+    case INDEX_op_rem_i64:
+    case INDEX_op_remu_i32:
+    case INDEX_op_remu_i64:
+        return C_O1_I2(r, r, r);
+
+    case INDEX_op_add_i32:
+    case INDEX_op_add_i64:
+    case INDEX_op_sub_i32:
+    case INDEX_op_sub_i64:
+    case INDEX_op_mul_i32:
+    case INDEX_op_mul_i64:
+    case INDEX_op_and_i32:
+    case INDEX_op_and_i64:
+    case INDEX_op_andc_i32:
+    case INDEX_op_andc_i64:
+    case INDEX_op_eqv_i32:
+    case INDEX_op_eqv_i64:
+    case INDEX_op_nand_i32:
+    case INDEX_op_nand_i64:
+    case INDEX_op_nor_i32:
+    case INDEX_op_nor_i64:
+    case INDEX_op_or_i32:
+    case INDEX_op_or_i64:
+    case INDEX_op_orc_i32:
+    case INDEX_op_orc_i64:
+    case INDEX_op_xor_i32:
+    case INDEX_op_xor_i64:
+    case INDEX_op_shl_i32:
+    case INDEX_op_shl_i64:
+    case INDEX_op_shr_i32:
+    case INDEX_op_shr_i64:
+    case INDEX_op_sar_i32:
+    case INDEX_op_sar_i64:
+    case INDEX_op_rotl_i32:
+    case INDEX_op_rotl_i64:
+    case INDEX_op_rotr_i32:
+    case INDEX_op_rotr_i64:
+        /* TODO: Does R, RI, RI result in faster code than R, R, RI? */
+        return C_O1_I2(r, ri, ri);
+
+    case INDEX_op_deposit_i32:
+    case INDEX_op_deposit_i64:
+        return C_O1_I2(r, 0, r);
+
+    case INDEX_op_brcond_i32:
+    case INDEX_op_brcond_i64:
+        return C_O0_I2(r, ri);
+
+    case INDEX_op_setcond_i32:
+    case INDEX_op_setcond_i64:
+        return C_O1_I2(r, r, ri);
+
+#if TCG_TARGET_REG_BITS == 32
+    /* TODO: Support R, R, R, R, RI, RI? Will it be faster? */
+    case INDEX_op_add2_i32:
+    case INDEX_op_sub2_i32:
+        return C_O2_I4(r, r, r, r, r, r);
+    case INDEX_op_brcond2_i32:
+        return C_O0_I4(r, r, ri, ri);
+    case INDEX_op_mulu2_i32:
+        return C_O2_I2(r, r, r, r);
+    case INDEX_op_setcond2_i32:
+        return C_O1_I4(r, r, r, ri, ri);
+#endif
+
+    case INDEX_op_qemu_ld_i32:
+        return (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS
+                ? C_O1_I1(r, r)
+                : C_O1_I2(r, r, r));
+    case INDEX_op_qemu_ld_i64:
+        return (TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, r)
+                : TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? C_O2_I1(r, r, r)
+                : C_O2_I2(r, r, r, r));
+    case INDEX_op_qemu_st_i32:
+        return (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS
+                ? C_O0_I2(r, r)
+                : C_O0_I3(r, r, r));
+    case INDEX_op_qemu_st_i64:
+        return (TCG_TARGET_REG_BITS == 64 ? C_O0_I2(r, r)
+                : TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? C_O0_I3(r, r, r)
+                : C_O0_I4(r, r, r, r));
+
+    default:
+        g_assert_not_reached();
     }
-    return NULL;
 }
 
 static const int tcg_target_reg_alloc_order[] = {
-- 
2.25.1

All backends have now been converted to tcg-target-con-set.h,
so we can remove the fallback code.

diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h
index XXXXXXX..XXXXXXX 100644
--- a/tcg/aarch64/tcg-target.h
+++ b/tcg/aarch64/tcg-target.h
@@ -XXX,XX +XXX,XX @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t);
 #define TCG_TARGET_NEED_LDST_LABELS
 #endif
 #define TCG_TARGET_NEED_POOL_LABELS
-#define TCG_TARGET_CON_SET_H
 
 #endif /* AARCH64_TCG_TARGET_H */
diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
index XXXXXXX..XXXXXXX 100644
--- a/tcg/arm/tcg-target.h
+++ b/tcg/arm/tcg-target.h
@@ -XXX,XX +XXX,XX @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t);
 #define TCG_TARGET_NEED_LDST_LABELS
 #endif
 #define TCG_TARGET_NEED_POOL_LABELS
-#define TCG_TARGET_CON_SET_H
 
 #endif
diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h
index XXXXXXX..XXXXXXX 100644
--- a/tcg/i386/tcg-target.h
+++ b/tcg/i386/tcg-target.h
@@ -XXX,XX +XXX,XX @@ static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_rx,
 #define TCG_TARGET_NEED_LDST_LABELS
 #endif
 #define TCG_TARGET_NEED_POOL_LABELS
-#define TCG_TARGET_CON_SET_H
 
 #endif
diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h
index XXXXXXX..XXXXXXX 100644
--- a/tcg/mips/tcg-target.h
+++ b/tcg/mips/tcg-target.h
@@ -XXX,XX +XXX,XX @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t);
 #ifdef CONFIG_SOFTMMU
 #define TCG_TARGET_NEED_LDST_LABELS
 #endif
-#define TCG_TARGET_CON_SET_H
 
 #endif
diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h
index XXXXXXX..XXXXXXX 100644
--- a/tcg/ppc/tcg-target.h
+++ b/tcg/ppc/tcg-target.h
@@ -XXX,XX +XXX,XX @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t);
 #define TCG_TARGET_NEED_LDST_LABELS
 #endif
 #define TCG_TARGET_NEED_POOL_LABELS
-#define TCG_TARGET_CON_SET_H
 
 #endif
diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h
index XXXXXXX..XXXXXXX 100644
--- a/tcg/riscv/tcg-target.h
+++ b/tcg/riscv/tcg-target.h
@@ -XXX,XX +XXX,XX @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t);
 #define TCG_TARGET_NEED_POOL_LABELS
 
 #define TCG_TARGET_HAS_MEMORY_BSWAP 0
-#define TCG_TARGET_CON_SET_H
 
 #endif
diff --git a/tcg/s390/tcg-target.h b/tcg/s390/tcg-target.h
index XXXXXXX..XXXXXXX 100644
--- a/tcg/s390/tcg-target.h
+++ b/tcg/s390/tcg-target.h
@@ -XXX,XX +XXX,XX @@ static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_rx,
 #define TCG_TARGET_NEED_LDST_LABELS
 #endif
 #define TCG_TARGET_NEED_POOL_LABELS
-#define TCG_TARGET_CON_SET_H
 
 #endif
diff --git a/tcg/sparc/tcg-target.h b/tcg/sparc/tcg-target.h
index XXXXXXX..XXXXXXX 100644
--- a/tcg/sparc/tcg-target.h
+++ b/tcg/sparc/tcg-target.h
@@ -XXX,XX +XXX,XX @@ extern bool use_vis3_instructions;
 void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t);
 
 #define TCG_TARGET_NEED_POOL_LABELS
-#define TCG_TARGET_CON_SET_H
 
 #endif
diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h
index XXXXXXX..XXXXXXX 100644
--- a/tcg/tci/tcg-target.h
+++ b/tcg/tci/tcg-target.h
@@ -XXX,XX +XXX,XX @@ static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_rx,
     /* no need to flush icache explicitly */
 }
 
-#define TCG_TARGET_CON_SET_H
-
 #endif /* TCG_TARGET_H */
diff --git a/tcg/tcg.c b/tcg/tcg.c
index XXXXXXX..XXXXXXX 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -XXX,XX +XXX,XX @@
 /* Forward declarations for functions declared in tcg-target.c.inc and
    used here. */
 static void tcg_target_init(TCGContext *s);
-#ifndef TCG_TARGET_CON_SET_H
-static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode);
-#endif
 static void tcg_target_qemu_prologue(TCGContext *s);
 static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
                         intptr_t value, intptr_t addend);
@@ -XXX,XX +XXX,XX @@ static void set_jmp_reset_offset(TCGContext *s, int which)
     s->tb_jmp_reset_offset[which] = tcg_current_code_size(s);
 }
 
-#ifdef TCG_TARGET_CON_SET_H
 #define C_PFX1(P, A)                    P##A
 #define C_PFX2(P, A, B)                 P##A##_##B
 #define C_PFX3(P, A, B, C)              P##A##_##B##_##C
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef constraint_sets[] = {
 #define C_O2_I3(O1, O2, I1, I2, I3)     C_PFX5(c_o2_i3_, O1, O2, I1, I2, I3)
 #define C_O2_I4(O1, O2, I1, I2, I3, I4) C_PFX6(c_o2_i4_, O1, O2, I1, I2, I3, I4)
 
-#endif /* TCG_TARGET_CON_SET_H */
-
 #include "tcg-target.c.inc"
 
 /* compare a pointer @ptr and a tb_tc @s */
@@ -XXX,XX +XXX,XX @@ static void process_op_defs(TCGContext *s)
             continue;
         }
 
-#ifdef TCG_TARGET_CON_SET_H
         /*
          * Macro magic should make it impossible, but double-check that
          * the array index is in range.  Since the signness of an enum
@@ -XXX,XX +XXX,XX @@ static void process_op_defs(TCGContext *s)
         unsigned con_set = tcg_target_op_def(op);
         tcg_debug_assert(con_set < ARRAY_SIZE(constraint_sets));
         tdefs = &constraint_sets[con_set];
-#else
-        tdefs = tcg_target_op_def(op);
-        /* Missing TCGTargetOpDef entry. */
-        tcg_debug_assert(tdefs != NULL);
-#endif
 
         for (i = 0; i < nb_args; i++) {
             const char *ct_str = tdefs->args_ct_str[i];
-- 
2.25.1

Version 3: Rebase and fix a minor patch conflict.

The following changes since commit c6f5e042d89e79206cd1ce5525d3df219f13c3cc:

Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20210913-3' into staging (2021-09-13 21:06:15 +0100)

are available in the Git repository at:

https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20210914

for you to fetch changes up to a5b759b6dca7daf87fa5007a7f5784bf22f3830f:

tcg/arm: More use of the TCGReg enum (2021-09-14 07:59:43 -0700)

----------------------------------------------------------------
Fix translation race condition for user-only.
Fix tcg/i386 encoding for VPSLLVQ, VPSRLVQ.
Fix tcg/arm tcg_out_vec_op signature.
Fix tcg/ppc (32bit) build with clang.
Remove dupluate TCG_KICK_PERIOD definition.
Remove unused tcg_global_reg_new.
Restrict cpu_exec_interrupt and its callees to sysemu.
Cleanups for tcg/arm.

----------------------------------------------------------------
Bin Meng (1):
      tcg: Remove tcg_global_reg_new defines

Ilya Leoshkevich (3):
      accel/tcg: Add DisasContextBase argument to translator_ld*
      accel/tcg: Clear PAGE_WRITE before translation
      accel/tcg/user-exec: Fix read-modify-write of code on s390 hosts

Jose R. Ziviani (1):
      tcg/arm: Fix tcg_out_vec_op function signature

Luc Michel (1):
      accel/tcg: remove redundant TCG_KICK_PERIOD define

Philippe Mathieu-Daudé (25):
      target/avr: Remove pointless use of CONFIG_USER_ONLY definition
      target/i386: Restrict sysemu-only fpu_helper helpers
      target/i386: Simplify TARGET_X86_64 #ifdef'ry
      target/xtensa: Restrict do_transaction_failed() to sysemu
      accel/tcg: Rename user-mode do_interrupt hack as fake_user_interrupt
      target/alpha: Restrict cpu_exec_interrupt() handler to sysemu
      target/arm: Restrict cpu_exec_interrupt() handler to sysemu
      target/cris: Restrict cpu_exec_interrupt() handler to sysemu
      target/hppa: Restrict cpu_exec_interrupt() handler to sysemu
      target/i386: Restrict cpu_exec_interrupt() handler to sysemu
      target/i386: Move x86_cpu_exec_interrupt() under sysemu/ folder
      target/m68k: Restrict cpu_exec_interrupt() handler to sysemu
      target/microblaze: Restrict cpu_exec_interrupt() handler to sysemu
      target/mips: Restrict cpu_exec_interrupt() handler to sysemu
      target/nios2: Restrict cpu_exec_interrupt() handler to sysemu
      target/openrisc: Restrict cpu_exec_interrupt() handler to sysemu
      target/ppc: Restrict cpu_exec_interrupt() handler to sysemu
      target/riscv: Restrict cpu_exec_interrupt() handler to sysemu
      target/sh4: Restrict cpu_exec_interrupt() handler to sysemu
      target/sparc: Restrict cpu_exec_interrupt() handler to sysemu
      target/rx: Restrict cpu_exec_interrupt() handler to sysemu
      target/xtensa: Restrict cpu_exec_interrupt() handler to sysemu
      accel/tcg: Restrict TCGCPUOps::cpu_exec_interrupt() to sysemu
      user: Remove cpu_get_pic_interrupt() stubs
      user: Mark cpu_loop() with noreturn attribute

Richard Henderson (13):
      tcg/i386: Split P_VEXW from P_REXW
      tcg/ppc: Replace TCG_TARGET_CALL_DARWIN with _CALL_DARWIN
      tcg/ppc: Ensure _CALL_SYSV is set for 32-bit ELF
      tcg/arm: Remove fallback definition of __ARM_ARCH
      tcg/arm: Standardize on tcg_out_<branch>_{reg,imm}
      tcg/arm: Simplify use_armv5t_instructions
      tcg/arm: Support armv4t in tcg_out_goto and tcg_out_call
      tcg/arm: Split out tcg_out_ldstm
      tcg/arm: Simplify usage of encode_imm
      tcg/arm: Drop inline markers
      tcg/arm: Give enum arm_cond_code_e a typedef and use it
      tcg/arm: More use of the ARMInsn enum
      tcg/arm: More use of the TCGReg enum

From: Ilya Leoshkevich <iii@linux.ibm.com>

Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com>
[rth: Split out of a larger patch.]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 include/exec/translator.h                 |  9 +++++----
 target/arm/arm_ldst.h                     | 12 ++++++------
 target/alpha/translate.c                  |  2 +-
 target/arm/translate-a64.c                |  2 +-
 target/arm/translate.c                    |  9 +++++----
 target/hexagon/translate.c                |  3 ++-
 target/hppa/translate.c                   |  2 +-
 target/i386/tcg/translate.c               | 10 +++++-----
 target/m68k/translate.c                   |  2 +-
 target/mips/tcg/translate.c               |  8 ++++----
 target/openrisc/translate.c               |  2 +-
 target/ppc/translate.c                    |  5 +++--
 target/riscv/translate.c                  |  5 +++--
 target/s390x/tcg/translate.c              | 16 +++++++++-------
 target/sh4/translate.c                    |  4 ++--
 target/sparc/translate.c                  |  2 +-
 target/xtensa/translate.c                 |  5 +++--
 target/mips/tcg/micromips_translate.c.inc |  2 +-
 target/mips/tcg/mips16e_translate.c.inc   |  4 ++--
 target/mips/tcg/nanomips_translate.c.inc  |  4 ++--
 20 files changed, 58 insertions(+), 50 deletions(-)

diff --git a/include/exec/translator.h b/include/exec/translator.h
index XXXXXXX..XXXXXXX 100644
--- a/include/exec/translator.h
+++ b/include/exec/translator.h
@@ -XXX,XX +XXX,XX @@ bool translator_use_goto_tb(DisasContextBase *db, target_ulong dest);
 
 #define GEN_TRANSLATOR_LD(fullname, type, load_fn, swap_fn)             \
     static inline type                                                  \
-    fullname ## _swap(CPUArchState *env, abi_ptr pc, bool do_swap)      \
+    fullname ## _swap(CPUArchState *env, DisasContextBase *dcbase,      \
+                      abi_ptr pc, bool do_swap)                         \
     {                                                                   \
         type ret = load_fn(env, pc);                                    \
         if (do_swap) {                                                  \
@@ -XXX,XX +XXX,XX @@ bool translator_use_goto_tb(DisasContextBase *db, target_ulong dest);
         plugin_insn_append(&ret, sizeof(ret));                          \
         return ret;                                                     \
     }                                                                   \
-                                                                        \
-    static inline type fullname(CPUArchState *env, abi_ptr pc)          \
+    static inline type fullname(CPUArchState *env,                      \
+                                DisasContextBase *dcbase, abi_ptr pc)   \
     {                                                                   \
-        return fullname ## _swap(env, pc, false);                       \
+        return fullname ## _swap(env, dcbase, pc, false);               \
     }
 
 GEN_TRANSLATOR_LD(translator_ldub, uint8_t, cpu_ldub_code, /* no swap */)
diff --git a/target/arm/arm_ldst.h b/target/arm/arm_ldst.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/arm_ldst.h
+++ b/target/arm/arm_ldst.h
@@ -XXX,XX +XXX,XX @@
 #include "qemu/bswap.h"
 
 /* Load an instruction and return it in the standard little-endian order */
-static inline uint32_t arm_ldl_code(CPUARMState *env, target_ulong addr,
-                                    bool sctlr_b)
+static inline uint32_t arm_ldl_code(CPUARMState *env, DisasContextBase *s,
+                                    target_ulong addr, bool sctlr_b)
 {
-    return translator_ldl_swap(env, addr, bswap_code(sctlr_b));
+    return translator_ldl_swap(env, s, addr, bswap_code(sctlr_b));
 }
 
 /* Ditto, for a halfword (Thumb) instruction */
-static inline uint16_t arm_lduw_code(CPUARMState *env, target_ulong addr,
-                                     bool sctlr_b)
+static inline uint16_t arm_lduw_code(CPUARMState *env, DisasContextBase* s,
+                                     target_ulong addr, bool sctlr_b)
 {
 #ifndef CONFIG_USER_ONLY
     /* In big-endian (BE32) mode, adjacent Thumb instructions have been swapped
@@ -XXX,XX +XXX,XX @@ static inline uint16_t arm_lduw_code(CPUARMState *env, target_ulong addr,
         addr ^= 2;
     }
 #endif
-    return translator_lduw_swap(env, addr, bswap_code(sctlr_b));
+    return translator_lduw_swap(env, s, addr, bswap_code(sctlr_b));
 }
 
 #endif
diff --git a/target/alpha/translate.c b/target/alpha/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/alpha/translate.c
+++ b/target/alpha/translate.c
@@ -XXX,XX +XXX,XX @@ static void alpha_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
 {
     DisasContext *ctx = container_of(dcbase, DisasContext, base);
     CPUAlphaState *env = cpu->env_ptr;
-    uint32_t insn = translator_ldl(env, ctx->base.pc_next);
+    uint32_t insn = translator_ldl(env, &ctx->base, ctx->base.pc_next);
 
     ctx->base.pc_next += 4;
     ctx->base.is_jmp = translate_one(ctx, insn);
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -XXX,XX +XXX,XX @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
     }
 
     s->pc_curr = s->base.pc_next;
-    insn = arm_ldl_code(env, s->base.pc_next, s->sctlr_b);
+    insn = arm_ldl_code(env, &s->base, s->base.pc_next, s->sctlr_b);
     s->insn = insn;
     s->base.pc_next += 4;
 
diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static bool insn_crosses_page(CPUARMState *env, DisasContext *s)
      * boundary, so we cross the page if the first 16 bits indicate
      * that this is a 32 bit insn.
      */
-    uint16_t insn = arm_lduw_code(env, s->base.pc_next, s->sctlr_b);
+    uint16_t insn = arm_lduw_code(env, &s->base, s->base.pc_next, s->sctlr_b);
 
     return !thumb_insn_is_16bit(s, s->base.pc_next, insn);
 }
@@ -XXX,XX +XXX,XX @@ static void arm_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
     }
 
     dc->pc_curr = dc->base.pc_next;
-    insn = arm_ldl_code(env, dc->base.pc_next, dc->sctlr_b);
+    insn = arm_ldl_code(env, &dc->base, dc->base.pc_next, dc->sctlr_b);
     dc->insn = insn;
     dc->base.pc_next += 4;
     disas_arm_insn(dc, insn);
@@ -XXX,XX +XXX,XX @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
     }
 
     dc->pc_curr = dc->base.pc_next;
-    insn = arm_lduw_code(env, dc->base.pc_next, dc->sctlr_b);
+    insn = arm_lduw_code(env, &dc->base, dc->base.pc_next, dc->sctlr_b);
     is_16bit = thumb_insn_is_16bit(dc, dc->base.pc_next, insn);
     dc->base.pc_next += 2;
     if (!is_16bit) {
-        uint32_t insn2 = arm_lduw_code(env, dc->base.pc_next, dc->sctlr_b);
+        uint32_t insn2 = arm_lduw_code(env, &dc->base, dc->base.pc_next,
+                                       dc->sctlr_b);
 
         insn = insn << 16 | insn2;
         dc->base.pc_next += 2;
diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/hexagon/translate.c
+++ b/target/hexagon/translate.c
@@ -XXX,XX +XXX,XX @@ static int read_packet_words(CPUHexagonState *env, DisasContext *ctx,
     memset(words, 0, PACKET_WORDS_MAX * sizeof(uint32_t));
     for (nwords = 0; !found_end && nwords < PACKET_WORDS_MAX; nwords++) {
         words[nwords] =
-            translator_ldl(env, ctx->base.pc_next + nwords * sizeof(uint32_t));
+            translator_ldl(env, &ctx->base,
+                           ctx->base.pc_next + nwords * sizeof(uint32_t));
         found_end = is_packet_end(words[nwords]);
     }
     if (!found_end) {
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -XXX,XX +XXX,XX @@ static void hppa_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
     {
         /* Always fetch the insn, even if nullified, so that we check
            the page permissions for execute.  */
-        uint32_t insn = translator_ldl(env, ctx->base.pc_next);
+        uint32_t insn = translator_ldl(env, &ctx->base, ctx->base.pc_next);
 
         /* Set up the IA queue for the next insn.
            This will be overwritten by a branch.  */
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/i386/tcg/translate.c
+++ b/target/i386/tcg/translate.c
@@ -XXX,XX +XXX,XX @@ static uint64_t advance_pc(CPUX86State *env, DisasContext *s, int num_bytes)
 
 static inline uint8_t x86_ldub_code(CPUX86State *env, DisasContext *s)
 {
-    return translator_ldub(env, advance_pc(env, s, 1));
+    return translator_ldub(env, &s->base, advance_pc(env, s, 1));
 }
 
 static inline int16_t x86_ldsw_code(CPUX86State *env, DisasContext *s)
 {
-    return translator_ldsw(env, advance_pc(env, s, 2));
+    return translator_ldsw(env, &s->base, advance_pc(env, s, 2));
 }
 
 static inline uint16_t x86_lduw_code(CPUX86State *env, DisasContext *s)
 {
-    return translator_lduw(env, advance_pc(env, s, 2));
+    return translator_lduw(env, &s->base, advance_pc(env, s, 2));
 }
 
 static inline uint32_t x86_ldl_code(CPUX86State *env, DisasContext *s)
 {
-    return translator_ldl(env, advance_pc(env, s, 4));
+    return translator_ldl(env, &s->base, advance_pc(env, s, 4));
 }
 
 #ifdef TARGET_X86_64
 static inline uint64_t x86_ldq_code(CPUX86State *env, DisasContext *s)
 {
-    return translator_ldq(env, advance_pc(env, s, 8));
+    return translator_ldq(env, &s->base, advance_pc(env, s, 8));
 }
 #endif
 
diff --git a/target/m68k/translate.c b/target/m68k/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/m68k/translate.c
+++ b/target/m68k/translate.c
@@ -XXX,XX +XXX,XX @@ static TCGv gen_ldst(DisasContext *s, int opsize, TCGv addr, TCGv val,
 static inline uint16_t read_im16(CPUM68KState *env, DisasContext *s)
 {
     uint16_t im;
-    im = translator_lduw(env, s->pc);
+    im = translator_lduw(env, &s->base, s->pc);
     s->pc += 2;
     return im;
 }
diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/mips/tcg/translate.c
+++ b/target/mips/tcg/translate.c
@@ -XXX,XX +XXX,XX @@ static void mips_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
 
     is_slot = ctx->hflags & MIPS_HFLAG_BMASK;
     if (ctx->insn_flags & ISA_NANOMIPS32) {
-        ctx->opcode = translator_lduw(env, ctx->base.pc_next);
+        ctx->opcode = translator_lduw(env, &ctx->base, ctx->base.pc_next);
         insn_bytes = decode_isa_nanomips(env, ctx);
     } else if (!(ctx->hflags & MIPS_HFLAG_M16)) {
-        ctx->opcode = translator_ldl(env, ctx->base.pc_next);
+        ctx->opcode = translator_ldl(env, &ctx->base, ctx->base.pc_next);
         insn_bytes = 4;
         decode_opc(env, ctx);
     } else if (ctx->insn_flags & ASE_MICROMIPS) {
-        ctx->opcode = translator_lduw(env, ctx->base.pc_next);
+        ctx->opcode = translator_lduw(env, &ctx->base, ctx->base.pc_next);
         insn_bytes = decode_isa_micromips(env, ctx);
     } else if (ctx->insn_flags & ASE_MIPS16) {
-        ctx->opcode = translator_lduw(env, ctx->base.pc_next);
+        ctx->opcode = translator_lduw(env, &ctx->base, ctx->base.pc_next);
         insn_bytes = decode_ase_mips16e(env, ctx);
     } else {
         gen_reserved_instruction(ctx);
diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/openrisc/translate.c
+++ b/target/openrisc/translate.c
@@ -XXX,XX +XXX,XX @@ static void openrisc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
 {
     DisasContext *dc = container_of(dcbase, DisasContext, base);
     OpenRISCCPU *cpu = OPENRISC_CPU(cs);
-    uint32_t insn = translator_ldl(&cpu->env, dc->base.pc_next);
+    uint32_t insn = translator_ldl(&cpu->env, &dc->base, dc->base.pc_next);
 
     if (!decode(dc, insn)) {
         gen_illegal_exception(dc);
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -XXX,XX +XXX,XX @@ static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
               ctx->base.pc_next, ctx->mem_idx, (int)msr_ir);
 
     ctx->cia = pc = ctx->base.pc_next;
-    insn = translator_ldl_swap(env, pc, need_byteswap(ctx));
+    insn = translator_ldl_swap(env, dcbase, pc, need_byteswap(ctx));
     ctx->base.pc_next = pc += 4;
 
     if (!is_prefix_insn(ctx, insn)) {
@@ -XXX,XX +XXX,XX @@ static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
         gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_INSN);
         ok = true;
     } else {
-        uint32_t insn2 = translator_ldl_swap(env, pc, need_byteswap(ctx));
+        uint32_t insn2 = translator_ldl_swap(env, dcbase, pc,
+                                             need_byteswap(ctx));
         ctx->base.pc_next = pc += 4;
         ok = decode_insn64(ctx, deposit64(insn2, 32, 32, insn));
     }
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -XXX,XX +XXX,XX @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
     } else {
         uint32_t opcode32 = opcode;
         opcode32 = deposit32(opcode32, 16, 16,
-                             translator_lduw(env, ctx->base.pc_next + 2));
+                             translator_lduw(env, &ctx->base,
+                                             ctx->base.pc_next + 2));
         ctx->pc_succ_insn = ctx->base.pc_next + 4;
         if (!decode_insn32(ctx, opcode32)) {
             gen_exception_illegal(ctx);
@@ -XXX,XX +XXX,XX @@ static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
 {
     DisasContext *ctx = container_of(dcbase, DisasContext, base);
     CPURISCVState *env = cpu->env_ptr;
-    uint16_t opcode16 = translator_lduw(env, ctx->base.pc_next);
+    uint16_t opcode16 = translator_lduw(env, &ctx->base, ctx->base.pc_next);
 
     decode_opc(env, ctx, opcode16);
     ctx->base.pc_next = ctx->pc_succ_insn;
diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/s390x/tcg/translate.c
+++ b/target/s390x/tcg/translate.c
@@ -XXX,XX +XXX,XX @@ static void update_cc_op(DisasContext *s)
     }
 }
 
-static inline uint64_t ld_code2(CPUS390XState *env, uint64_t pc)
+static inline uint64_t ld_code2(CPUS390XState *env, DisasContext *s,
+                                uint64_t pc)
 {
-    return (uint64_t)cpu_lduw_code(env, pc);
+    return (uint64_t)translator_lduw(env, &s->base, pc);
 }
 
-static inline uint64_t ld_code4(CPUS390XState *env, uint64_t pc)
+static inline uint64_t ld_code4(CPUS390XState *env, DisasContext *s,
+                                uint64_t pc)
 {
-    return (uint64_t)(uint32_t)cpu_ldl_code(env, pc);
+    return (uint64_t)(uint32_t)translator_ldl(env, &s->base, pc);
 }
 
 static int get_mem_index(DisasContext *s)
@@ -XXX,XX +XXX,XX @@ static const DisasInsn *extract_insn(CPUS390XState *env, DisasContext *s)
         ilen = s->ex_value & 0xf;
         op = insn >> 56;
     } else {
-        insn = ld_code2(env, pc);
+        insn = ld_code2(env, s, pc);
         op = (insn >> 8) & 0xff;
         ilen = get_ilen(op);
         switch (ilen) {
@@ -XXX,XX +XXX,XX @@ static const DisasInsn *extract_insn(CPUS390XState *env, DisasContext *s)
             insn = insn << 48;
             break;
         case 4:
-            insn = ld_code4(env, pc) << 32;
+            insn = ld_code4(env, s, pc) << 32;
             break;
         case 6:
-            insn = (insn << 48) | (ld_code4(env, pc + 2) << 16);
+            insn = (insn << 48) | (ld_code4(env, s, pc + 2) << 16);
             break;
         default:
             g_assert_not_reached();
diff --git a/target/sh4/translate.c b/target/sh4/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/sh4/translate.c
+++ b/target/sh4/translate.c
@@ -XXX,XX +XXX,XX @@ static void decode_gusa(DisasContext *ctx, CPUSH4State *env)
 
     /* Read all of the insns for the region.  */
     for (i = 0; i < max_insns; ++i) {
-        insns[i] = translator_lduw(env, pc + i * 2);
+        insns[i] = translator_lduw(env, &ctx->base, pc + i * 2);
     }
 
     ld_adr = ld_dst = ld_mop = -1;
@@ -XXX,XX +XXX,XX @@ static void sh4_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
     }
 #endif
 
-    ctx->opcode = translator_lduw(env, ctx->base.pc_next);
+    ctx->opcode = translator_lduw(env, &ctx->base, ctx->base.pc_next);
     decode_opc(ctx);
     ctx->base.pc_next += 2;
 }
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/sparc/translate.c
+++ b/target/sparc/translate.c
@@ -XXX,XX +XXX,XX @@ static void sparc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
     CPUSPARCState *env = cs->env_ptr;
     unsigned int insn;
 
-    insn = translator_ldl(env, dc->pc);
+    insn = translator_ldl(env, &dc->base, dc->pc);
     dc->base.pc_next += 4;
     disas_sparc_insn(dc, insn);
 
diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/xtensa/translate.c
+++ b/target/xtensa/translate.c
@@ -XXX,XX +XXX,XX @@ static int arg_copy_compare(const void *a, const void *b)
 static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc)
 {
     xtensa_isa isa = dc->config->isa;
-    unsigned char b[MAX_INSN_LENGTH] = {translator_ldub(env, dc->pc)};
+    unsigned char b[MAX_INSN_LENGTH] = {translator_ldub(env, &dc->base,
+                                                        dc->pc)};
     unsigned len = xtensa_op0_insn_len(dc, b[0]);
     xtensa_format fmt;
     int slot, slots;
@@ -XXX,XX +XXX,XX @@ static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc)
 
     dc->base.pc_next = dc->pc + len;
     for (i = 1; i < len; ++i) {
-        b[i] = translator_ldub(env, dc->pc + i);
+        b[i] = translator_ldub(env, &dc->base, dc->pc + i);
     }
     xtensa_insnbuf_from_chars(isa, dc->insnbuf, b, len);
     fmt = xtensa_format_decode(isa, dc->insnbuf);
diff --git a/target/mips/tcg/micromips_translate.c.inc b/target/mips/tcg/micromips_translate.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/mips/tcg/micromips_translate.c.inc
+++ b/target/mips/tcg/micromips_translate.c.inc
@@ -XXX,XX +XXX,XX @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
     uint32_t op, minor, minor2, mips32_op;
     uint32_t cond, fmt, cc;
 
-    insn = translator_lduw(env, ctx->base.pc_next + 2);
+    insn = translator_lduw(env, &ctx->base, ctx->base.pc_next + 2);
     ctx->opcode = (ctx->opcode << 16) | insn;
 
     rt = (ctx->opcode >> 21) & 0x1f;
diff --git a/target/mips/tcg/mips16e_translate.c.inc b/target/mips/tcg/mips16e_translate.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/mips/tcg/mips16e_translate.c.inc
+++ b/target/mips/tcg/mips16e_translate.c.inc
@@ -XXX,XX +XXX,XX @@ static void decode_i64_mips16(DisasContext *ctx,
 
 static int decode_extended_mips16_opc(CPUMIPSState *env, DisasContext *ctx)
 {
-    int extend = translator_lduw(env, ctx->base.pc_next + 2);
+    int extend = translator_lduw(env, &ctx->base, ctx->base.pc_next + 2);
     int op, rx, ry, funct, sa;
     int16_t imm, offset;
 
@@ -XXX,XX +XXX,XX @@ static int decode_ase_mips16e(CPUMIPSState *env, DisasContext *ctx)
         /* No delay slot, so just process as a normal instruction */
         break;
     case M16_OPC_JAL:
-        offset = translator_lduw(env, ctx->base.pc_next + 2);
+        offset = translator_lduw(env, &ctx->base, ctx->base.pc_next + 2);
         offset = (((ctx->opcode & 0x1f) << 21)
                   | ((ctx->opcode >> 5) & 0x1f) << 16
                   | offset) << 2;
diff --git a/target/mips/tcg/nanomips_translate.c.inc b/target/mips/tcg/nanomips_translate.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/mips/tcg/nanomips_translate.c.inc
+++ b/target/mips/tcg/nanomips_translate.c.inc
@@ -XXX,XX +XXX,XX @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
     int offset;
     int imm;
 
-    insn = translator_lduw(env, ctx->base.pc_next + 2);
+    insn = translator_lduw(env, &ctx->base, ctx->base.pc_next + 2);
     ctx->opcode = (ctx->opcode << 16) | insn;
 
     rt = extract32(ctx->opcode, 21, 5);
@@ -XXX,XX +XXX,XX @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
         break;
     case NM_P48I:
         {
-            insn = translator_lduw(env, ctx->base.pc_next + 4);
+            insn = translator_lduw(env, &ctx->base, ctx->base.pc_next + 4);
             target_long addr_off = extract32(ctx->opcode, 0, 16) | insn << 16;
             switch (extract32(ctx->opcode, 16, 5)) {
             case NM_LI48:
-- 
2.25.1