Changes since v1:

* Added QEMU_ERROR to wrap __attribute__((error)) -- patch 12.

r~

The following changes since commit 77f7c747193662edfadeeb3118d63eed0eac51a6:

Merge remote-tracking branch 'remotes/huth-gitlab/tags/pull-request-2018-10-17' into staging (2018-10-18 13:40:19 +0100)

https://github.com/rth7680/qemu.git tags/pull-tcg-20181018

for you to fetch changes up to 403f290c0603f35f2d09c982bf5549b6d0803ec1:

cputlb: read CPUTLBEntry.addr_write atomically (2018-10-18 19:46:53 -0700)

Queued tcg patches.

Emilio G. Cota (10):

tcg: access cpu->icount_decr.u16.high with atomics

tcg: fix use of uninitialized variable under CONFIG_PROFILER

tcg: plug holes in struct TCGProfile

tcg: distribute tcg_time into TCG contexts

target/alpha: remove tlb_flush from alpha_cpu_initfn

target/unicore32: remove tlb_flush from uc32_init_fn

exec: introduce tlb_init

cputlb: fix assert_cpu_is_self macro

cputlb: serialize tlb updates with env->tlb_lock

cputlb: read CPUTLBEntry.addr_write atomically

Richard Henderson (11):

tcg: Implement CPU_LOG_TB_NOCHAIN during expansion

tcg: Add tlb_index and tlb_entry helpers

tcg: Split CONFIG_ATOMIC128

target/i386: Convert to HAVE_CMPXCHG128

target/arm: Convert to HAVE_CMPXCHG128

target/arm: Check HAVE_CMPXCHG128 at translate time

target/ppc: Convert to HAVE_CMPXCHG128 and HAVE_ATOMIC128

target/s390x: Convert to HAVE_CMPXCHG128 and HAVE_ATOMIC128

target/s390x: Split do_cdsg, do_lpq, do_stpq

target/s390x: Skip wout, cout helpers if op helper does not return

target/s390x: Check HAVE_ATOMIC128 and HAVE_CMPXCHG128 at translate

Rather than test NOCHAIN before linking, do not emit the

goto_tb opcode at all. We already do this for goto_ptr.

accel/tcg/cpu-exec.c | 2 +-

tcg/tcg-op.c | 9 ++++++++-

2 files changed, 9 insertions(+), 2 deletions(-)

diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c

--- a/accel/tcg/cpu-exec.c

+++ b/accel/tcg/cpu-exec.c

@@ -XXX,XX +XXX,XX @@ static inline TranslationBlock *tb_find(CPUState *cpu,

}

/* See if we can patch the calling TB. */

- if (last_tb && !qemu_loglevel_mask(CPU_LOG_TB_NOCHAIN)) {

+ if (last_tb) {

tb_add_jump(last_tb, tb_exit, tb);

}

return tb;

diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c

--- a/tcg/tcg-op.c

+++ b/tcg/tcg-op.c

@@ -XXX,XX +XXX,XX @@ void tcg_gen_exit_tb(TranslationBlock *tb, unsigned idx)

seen this numbered exit before, via tcg_gen_goto_tb. */

tcg_debug_assert(tcg_ctx->goto_tb_issue_mask & (1 << idx));

+ /* When not chaining, exit without indicating a link. */

+ if (qemu_loglevel_mask(CPU_LOG_TB_NOCHAIN)) {

+ val = 0;

+ }

} else {

/* This is an exit via the exitreq label. */

tcg_debug_assert(idx == TB_EXIT_REQUESTED);

@@ -XXX,XX +XXX,XX @@ void tcg_gen_goto_tb(unsigned idx)

tcg_debug_assert((tcg_ctx->goto_tb_issue_mask & (1 << idx)) == 0);

tcg_ctx->goto_tb_issue_mask |= 1 << idx;

- tcg_gen_op1i(INDEX_op_goto_tb, idx);

+ /* When not chaining, we simply fall through to the "fallback" exit. */

+ if (!qemu_loglevel_mask(CPU_LOG_TB_NOCHAIN)) {

+ tcg_gen_op1i(INDEX_op_goto_tb, idx);

+ }

void tcg_gen_lookup_and_goto_ptr(void)

2.17.2

From: "Emilio G. Cota" <cota@braap.org>

Consistently access u16.high with atomics to avoid

undefined behaviour in MTTCG.

Note that icount_decr.u16.low is only used in icount mode,

so regular accesses to it are OK.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Signed-off-by: Emilio G. Cota <cota@braap.org>

Message-Id: <20181010144853.13005-2-cota@braap.org>

accel/tcg/tcg-all.c | 2 +-

accel/tcg/translate-all.c | 2 +-

qom/cpu.c | 2 +-

3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/accel/tcg/tcg-all.c b/accel/tcg/tcg-all.c

--- a/accel/tcg/tcg-all.c

+++ b/accel/tcg/tcg-all.c

@@ -XXX,XX +XXX,XX @@ static void tcg_handle_interrupt(CPUState *cpu, int mask)

if (!qemu_cpu_is_self(cpu)) {

qemu_cpu_kick(cpu);

} else {

- cpu->icount_decr.u16.high = -1;

+ atomic_set(&cpu->icount_decr.u16.high, -1);

if (use_icount &&

!cpu->can_do_io

&& (mask & ~old_mask) != 0) {

diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c

index XXXXXXX..XXXXXXX 100644

--- a/accel/tcg/translate-all.c

+++ b/accel/tcg/translate-all.c

@@ -XXX,XX +XXX,XX @@ void cpu_interrupt(CPUState *cpu, int mask)

{

g_assert(qemu_mutex_iothread_locked());

cpu->interrupt_request |= mask;

- cpu->icount_decr.u16.high = -1;

+ atomic_set(&cpu->icount_decr.u16.high, -1);

/*

diff --git a/qom/cpu.c b/qom/cpu.c

--- a/qom/cpu.c

+++ b/qom/cpu.c

@@ -XXX,XX +XXX,XX @@ static void cpu_common_reset(CPUState *cpu)

cpu->mem_io_pc = 0;

cpu->mem_io_vaddr = 0;

cpu->icount_extra = 0;

- cpu->icount_decr.u32 = 0;

+ atomic_set(&cpu->icount_decr.u32, 0);

cpu->can_do_io = 1;

cpu->exception_index = -1;

cpu->crash_occurred = false;

2.17.2

From: "Emilio G. Cota" <cota@braap.org>

We forgot to initialize n in commit 15fa08f845 ("tcg: Dynamically

allocate TCGOps", 2017-12-29).

Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>

Signed-off-by: Emilio G. Cota <cota@braap.org>

Message-Id: <20181010144853.13005-3-cota@braap.org>

tcg/tcg.c | 2 +-

1 file changed, 1 insertion(+), 1 deletion(-)

@@ -XXX,XX +XXX,XX @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb)

#ifdef CONFIG_PROFILER

{

- int n;

+ int n = 0;

QTAILQ_FOREACH(op, &s->ops, link) {

n++;

2.17.2

From: "Emilio G. Cota" <cota@braap.org>

This plugs two 4-byte holes in 64-bit.

Signed-off-by: Emilio G. Cota <cota@braap.org>

Message-Id: <20181010144853.13005-4-cota@braap.org>

tcg/tcg.h | 2 +-

1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/tcg/tcg.h b/tcg/tcg.h

--- a/tcg/tcg.h

+++ b/tcg/tcg.h

@@ -XXX,XX +XXX,XX @@ typedef struct TCGProfile {

int64_t tb_count;

int64_t op_count; /* total insn count */

int op_count_max; /* max insn per TB */

- int64_t temp_count;

int temp_count_max;

+ int64_t temp_count;

int64_t del_op_count;

int64_t code_in_len;

int64_t code_out_len;