[PULL 00/46] target-arm queue
[PULL 00/24] target-arm queue
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The following changes since commit 7e7eb9f852a46b51a71ae9d82590b2e4d28827ee:
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The following changes since commit 5a67d7735d4162630769ef495cf813244fc850df:
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Merge remote-tracking branch 'remotes/armbru/tags/pull-qapi-2021-01-28' into staging (2021-01-28 22:43:18 +0000)
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Merge remote-tracking branch 'remotes/berrange-gitlab/tags/tls-deps-pull-request' into staging (2021-07-02 08:22:39 +0100)
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are available in the Git repository at:
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are available in the Git repository at:
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210129
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210702
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for you to fetch changes up to 11749122e1a86866591306d43603d2795a3dea1a:
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for you to fetch changes up to 04ea4d3cfd0a21b248ece8eb7a9436a3d9898dd8:
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hw/arm/stellaris: Remove board-creation reset of STELLARIS_SYS (2021-01-29 10:47:29 +0000)
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target/arm: Implement MVE shifts by register (2021-07-02 11:48:38 +0100)
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13
----------------------------------------------------------------
13
----------------------------------------------------------------
14
target-arm queue:
14
target-arm queue:
15
* Implement ID_PFR2
15
* more MVE instructions
16
* Conditionalize DBGDIDR
16
* hw/gpio/gpio_pwr: use shutdown function for reboot
17
* rename xlnx-zcu102.canbusN properties
17
* target/arm: Check NaN mode before silencing NaN
18
* provide powerdown/reset mechanism for secure firmware on 'virt' board
18
* tests: Boot and halt a Linux guest on the Raspberry Pi 2 machine
19
* hw/misc: Fix arith overflow in NPCM7XX PWM module
19
* hw/arm: Add basic power management to raspi.
20
* target/arm: Replace magic value by MMU_DATA_LOAD definition
20
* docs/system/arm: Add quanta-gbs-bmc, quanta-q7l1-bmc
21
* configure: fix preadv errors on Catalina macOS with new XCode
22
* Various configure and other cleanups in preparation for iOS support
23
* hvf: Add hypervisor entitlement to output binaries (needed for Big Sur)
24
* Implement pvpanic-pci device
25
* Convert the CMSDK timer devices to the Clock framework
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27
----------------------------------------------------------------
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----------------------------------------------------------------
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Alexander Graf (1):
23
Joe Komlodi (1):
29
hvf: Add hypervisor entitlement to output binaries
24
target/arm: Check NaN mode before silencing NaN
30
25
31
Hao Wu (1):
26
Maxim Uvarov (1):
32
hw/misc: Fix arith overflow in NPCM7XX PWM module
27
hw/gpio/gpio_pwr: use shutdown function for reboot
33
28
34
Joelle van Dyne (7):
29
Nolan Leake (1):
35
configure: cross-compiling with empty cross_prefix
30
hw/arm: Add basic power management to raspi.
36
osdep: build with non-working system() function
37
darwin: remove redundant dependency declaration
38
darwin: fix cross-compiling for Darwin
39
configure: cross compile should use x86_64 cpu_family
40
darwin: detect CoreAudio for build
41
darwin: remove 64-bit build detection on 32-bit OS
42
31
43
Maxim Uvarov (3):
32
Patrick Venture (2):
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hw: gpio: implement gpio-pwr driver for qemu reset/poweroff
33
docs/system/arm: Add quanta-q7l1-bmc reference
45
arm-virt: refactor gpios creation
34
docs/system/arm: Add quanta-gbs-bmc reference
46
arm-virt: add secure pl061 for reset/power down
47
35
48
Mihai Carabas (4):
36
Peter Maydell (18):
49
hw/misc/pvpanic: split-out generic and bus dependent code
37
target/arm: Fix MVE widening/narrowing VLDR/VSTR offset calculation
50
hw/misc/pvpanic: add PCI interface support
38
target/arm: Fix bugs in MVE VRMLALDAVH, VRMLSLDAVH
51
pvpanic : update pvpanic spec document
39
target/arm: Make asimd_imm_const() public
52
tests/qtest: add a test case for pvpanic-pci
40
target/arm: Use asimd_imm_const for A64 decode
53
41
target/arm: Use dup_const() instead of bitfield_replicate()
54
Paolo Bonzini (1):
42
target/arm: Implement MVE logical immediate insns
55
arm: rename xlnx-zcu102.canbusN properties
43
target/arm: Implement MVE vector shift left by immediate insns
56
44
target/arm: Implement MVE vector shift right by immediate insns
57
Peter Maydell (26):
45
target/arm: Implement MVE VSHLL
58
configure: Move preadv check to meson.build
46
target/arm: Implement MVE VSRI, VSLI
59
ptimer: Add new ptimer_set_period_from_clock() function
47
target/arm: Implement MVE VSHRN, VRSHRN
60
clock: Add new clock_has_source() function
48
target/arm: Implement MVE saturating narrowing shifts
61
tests: Add a simple test of the CMSDK APB timer
49
target/arm: Implement MVE VSHLC
62
tests: Add a simple test of the CMSDK APB watchdog
50
target/arm: Implement MVE VADDLV
63
tests: Add a simple test of the CMSDK APB dual timer
51
target/arm: Implement MVE long shifts by immediate
64
hw/timer/cmsdk-apb-timer: Rename CMSDKAPBTIMER struct to CMSDKAPBTimer
52
target/arm: Implement MVE long shifts by register
65
hw/timer/cmsdk-apb-timer: Add Clock input
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target/arm: Implement MVE shifts by immediate
66
hw/timer/cmsdk-apb-dualtimer: Add Clock input
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target/arm: Implement MVE shifts by register
67
hw/watchdog/cmsdk-apb-watchdog: Add Clock input
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hw/arm/armsse: Rename "MAINCLK" property to "MAINCLK_FRQ"
69
hw/arm/armsse: Wire up clocks
70
hw/arm/mps2: Inline CMSDK_APB_TIMER creation
71
hw/arm/mps2: Create and connect SYSCLK Clock
72
hw/arm/mps2-tz: Create and connect ARMSSE Clocks
73
hw/arm/musca: Create and connect ARMSSE Clocks
74
hw/arm/stellaris: Convert SSYS to QOM device
75
hw/arm/stellaris: Create Clock input for watchdog
76
hw/timer/cmsdk-apb-timer: Convert to use Clock input
77
hw/timer/cmsdk-apb-dualtimer: Convert to use Clock input
78
hw/watchdog/cmsdk-apb-watchdog: Convert to use Clock input
79
tests/qtest/cmsdk-apb-watchdog-test: Test clock changes
80
hw/arm/armsse: Use Clock to set system_clock_scale
81
arm: Don't set freq properties on CMSDK timer, dualtimer, watchdog, ARMSSE
82
arm: Remove frq properties on CMSDK timer, dualtimer, watchdog, ARMSSE
83
hw/arm/stellaris: Remove board-creation reset of STELLARIS_SYS
84
55
85
Philippe Mathieu-Daudé (1):
56
Philippe Mathieu-Daudé (1):
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target/arm: Replace magic value by MMU_DATA_LOAD definition
57
tests: Boot and halt a Linux guest on the Raspberry Pi 2 machine
87
58
88
Richard Henderson (2):
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docs/system/arm/aspeed.rst | 1 +
89
target/arm: Implement ID_PFR2
60
docs/system/arm/nuvoton.rst | 5 +-
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target/arm: Conditionalize DBGDIDR
61
include/hw/arm/bcm2835_peripherals.h | 3 +-
62
include/hw/misc/bcm2835_powermgt.h | 29 ++
63
target/arm/helper-mve.h | 108 +++++++
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target/arm/translate.h | 41 +++
65
target/arm/mve.decode | 177 ++++++++++-
66
target/arm/t32.decode | 71 ++++-
67
hw/arm/bcm2835_peripherals.c | 13 +-
68
hw/gpio/gpio_pwr.c | 2 +-
69
hw/misc/bcm2835_powermgt.c | 160 ++++++++++
70
target/arm/helper-a64.c | 12 +-
71
target/arm/mve_helper.c | 524 +++++++++++++++++++++++++++++++--
72
target/arm/translate-a64.c | 86 +-----
73
target/arm/translate-mve.c | 261 +++++++++++++++-
74
target/arm/translate-neon.c | 81 -----
75
target/arm/translate.c | 327 +++++++++++++++++++-
76
target/arm/vfp_helper.c | 24 +-
77
hw/misc/meson.build | 1 +
78
tests/acceptance/boot_linux_console.py | 43 +++
79
20 files changed, 1760 insertions(+), 209 deletions(-)
80
create mode 100644 include/hw/misc/bcm2835_powermgt.h
81
create mode 100644 hw/misc/bcm2835_powermgt.c
91
82
92
docs/devel/clocks.rst | 16 +++
93
docs/specs/pci-ids.txt | 1 +
94
docs/specs/pvpanic.txt | 13 ++-
95
docs/system/arm/virt.rst | 2 +
96
configure | 78 ++++++++------
97
meson.build | 34 ++++++-
98
include/hw/arm/armsse.h | 14 ++-
99
include/hw/arm/virt.h | 2 +
100
include/hw/clock.h | 15 +++
101
include/hw/misc/pvpanic.h | 24 ++++-
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include/hw/pci/pci.h | 1 +
103
include/hw/ptimer.h | 22 ++++
104
include/hw/timer/cmsdk-apb-dualtimer.h | 5 +-
105
include/hw/timer/cmsdk-apb-timer.h | 34 ++-----
106
include/hw/watchdog/cmsdk-apb-watchdog.h | 5 +-
107
include/qemu/osdep.h | 12 +++
108
include/qemu/typedefs.h | 1 +
109
target/arm/cpu.h | 1 +
110
hw/arm/armsse.c | 48 ++++++---
111
hw/arm/mps2-tz.c | 14 ++-
112
hw/arm/mps2.c | 28 ++++-
113
hw/arm/musca.c | 13 ++-
114
hw/arm/stellaris.c | 170 +++++++++++++++++++++++--------
115
hw/arm/virt.c | 111 ++++++++++++++++----
116
hw/arm/xlnx-zcu102.c | 4 +-
117
hw/core/ptimer.c | 34 +++++++
118
hw/gpio/gpio_pwr.c | 70 +++++++++++++
119
hw/misc/npcm7xx_pwm.c | 23 ++++-
120
hw/misc/pvpanic-isa.c | 94 +++++++++++++++++
121
hw/misc/pvpanic-pci.c | 94 +++++++++++++++++
122
hw/misc/pvpanic.c | 85 ++--------------
123
hw/timer/cmsdk-apb-dualtimer.c | 53 +++++++---
124
hw/timer/cmsdk-apb-timer.c | 55 +++++-----
125
hw/watchdog/cmsdk-apb-watchdog.c | 29 ++++--
126
target/arm/helper.c | 27 +++--
127
target/arm/kvm64.c | 2 +
128
tests/qtest/cmsdk-apb-dualtimer-test.c | 130 +++++++++++++++++++++++
129
tests/qtest/cmsdk-apb-timer-test.c | 75 ++++++++++++++
130
tests/qtest/cmsdk-apb-watchdog-test.c | 131 ++++++++++++++++++++++++
131
tests/qtest/npcm7xx_pwm-test.c | 4 +-
132
tests/qtest/pvpanic-pci-test.c | 94 +++++++++++++++++
133
tests/qtest/xlnx-can-test.c | 30 +++---
134
MAINTAINERS | 3 +
135
accel/hvf/entitlements.plist | 8 ++
136
hw/arm/Kconfig | 1 +
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hw/gpio/Kconfig | 3 +
138
hw/gpio/meson.build | 1 +
139
hw/i386/Kconfig | 2 +-
140
hw/misc/Kconfig | 12 ++-
141
hw/misc/meson.build | 4 +-
142
scripts/entitlement.sh | 13 +++
143
tests/qtest/meson.build | 6 +-
144
52 files changed, 1432 insertions(+), 319 deletions(-)
145
create mode 100644 hw/gpio/gpio_pwr.c
146
create mode 100644 hw/misc/pvpanic-isa.c
147
create mode 100644 hw/misc/pvpanic-pci.c
148
create mode 100644 tests/qtest/cmsdk-apb-dualtimer-test.c
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create mode 100644 tests/qtest/cmsdk-apb-timer-test.c
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create mode 100644 tests/qtest/cmsdk-apb-watchdog-test.c
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create mode 100644 tests/qtest/pvpanic-pci-test.c
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create mode 100644 accel/hvf/entitlements.plist
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create mode 100755 scripts/entitlement.sh
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diff view generated by jsdifflib
[PULL 01/46] target/arm: Implement ID_PFR2
Deleted patch
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From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
This was defined at some point before ARMv8.4, and will
4
shortly be used by new processor descriptions.
5
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Message-id: 20210120204400.1056582-1-richard.henderson@linaro.org
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/cpu.h | 1 +
12
target/arm/helper.c | 4 ++--
13
target/arm/kvm64.c | 2 ++
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3 files changed, 5 insertions(+), 2 deletions(-)
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16
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/cpu.h
19
+++ b/target/arm/cpu.h
20
@@ -XXX,XX +XXX,XX @@ struct ARMCPU {
21
uint32_t id_mmfr4;
22
uint32_t id_pfr0;
23
uint32_t id_pfr1;
24
+ uint32_t id_pfr2;
25
uint32_t mvfr0;
26
uint32_t mvfr1;
27
uint32_t mvfr2;
28
diff --git a/target/arm/helper.c b/target/arm/helper.c
29
index XXXXXXX..XXXXXXX 100644
30
--- a/target/arm/helper.c
31
+++ b/target/arm/helper.c
32
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
33
.access = PL1_R, .type = ARM_CP_CONST,
34
.accessfn = access_aa64_tid3,
35
.resetvalue = 0 },
36
- { .name = "MVFR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
37
+ { .name = "ID_PFR2", .state = ARM_CP_STATE_BOTH,
38
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 4,
39
.access = PL1_R, .type = ARM_CP_CONST,
40
.accessfn = access_aa64_tid3,
41
- .resetvalue = 0 },
42
+ .resetvalue = cpu->isar.id_pfr2 },
43
{ .name = "MVFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
44
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 5,
45
.access = PL1_R, .type = ARM_CP_CONST,
46
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
47
index XXXXXXX..XXXXXXX 100644
48
--- a/target/arm/kvm64.c
49
+++ b/target/arm/kvm64.c
50
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
51
ARM64_SYS_REG(3, 0, 0, 1, 0));
52
err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_pfr1,
53
ARM64_SYS_REG(3, 0, 0, 1, 1));
54
+ err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_pfr2,
55
+ ARM64_SYS_REG(3, 0, 0, 3, 4));
56
err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_dfr0,
57
ARM64_SYS_REG(3, 0, 0, 1, 2));
58
err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr0,
59
--
60
2.20.1
61
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diff view generated by jsdifflib
[PULL 20/46] pvpanic : update pvpanic spec document
[PULL 01/24] docs/system/arm: Add quanta-q7l1-bmc reference
1
From: Mihai Carabas <mihai.carabas@oracle.com>
1
From: Patrick Venture <venture@google.com>
2
2
3
Add pvpanic PCI device support details in docs/specs/pvpanic.txt.
3
Adds a line-item reference to the supported quanta-q71l-bmc aspeed
4
entry.
4
5
5
Signed-off-by: Mihai Carabas <mihai.carabas@oracle.com>
6
Signed-off-by: Patrick Venture <venture@google.com>
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Cédric Le Goater <clg@kaod.org>
8
Message-id: 20210615192848.1065297-2-venture@google.com
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
---
10
---
9
docs/specs/pvpanic.txt | 13 ++++++++++++-
11
docs/system/arm/aspeed.rst | 1 +
10
1 file changed, 12 insertions(+), 1 deletion(-)
12
1 file changed, 1 insertion(+)
11
13
12
diff --git a/docs/specs/pvpanic.txt b/docs/specs/pvpanic.txt
14
diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst
13
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
14
--- a/docs/specs/pvpanic.txt
16
--- a/docs/system/arm/aspeed.rst
15
+++ b/docs/specs/pvpanic.txt
17
+++ b/docs/system/arm/aspeed.rst
16
@@ -XXX,XX +XXX,XX @@
18
@@ -XXX,XX +XXX,XX @@ etc.
17
PVPANIC DEVICE
19
AST2400 SoC based machines :
18
==============
20
19
21
- ``palmetto-bmc`` OpenPOWER Palmetto POWER8 BMC
20
-pvpanic device is a simulated ISA device, through which a guest panic
22
+- ``quanta-q71l-bmc`` OpenBMC Quanta BMC
21
+pvpanic device is a simulated device, through which a guest panic
23
22
event is sent to qemu, and a QMP event is generated. This allows
24
AST2500 SoC based machines :
23
management apps (e.g. libvirt) to be notified and respond to the event.
24
25
@@ -XXX,XX +XXX,XX @@ The management app has the option of waiting for GUEST_PANICKED events,
26
and/or polling for guest-panicked RunState, to learn when the pvpanic
27
device has fired a panic event.
28
29
+The pvpanic device can be implemented as an ISA device (using IOPORT) or as a
30
+PCI device.
31
+
32
ISA Interface
33
-------------
34
35
@@ -XXX,XX +XXX,XX @@ bit 1: a guest panic has happened and will be handled by the guest;
36
the host should record it or report it, but should not affect
37
the execution of the guest.
38
39
+PCI Interface
40
+-------------
41
+
42
+The PCI interface is similar to the ISA interface except that it uses an MMIO
43
+address space provided by its BAR0, 1 byte long. Any machine with a PCI bus
44
+can enable a pvpanic device by adding '-device pvpanic-pci' to the command
45
+line.
46
+
47
ACPI Interface
48
--------------
49
25
50
--
26
--
51
2.20.1
27
2.20.1
52
28
53
29
diff view generated by jsdifflib
[PULL 07/46] hw/misc: Fix arith overflow in NPCM7XX PWM module
[PULL 02/24] docs/system/arm: Add quanta-gbs-bmc reference
1
From: Hao Wu <wuhaotsh@google.com>
1
From: Patrick Venture <venture@google.com>
2
2
3
Fix potential overflow problem when calculating pwm_duty.
3
Add line item reference to quanta-gbs-bmc machine.
4
1. Ensure p->cmr and p->cnr to be from [0,65535], according to the
5
hardware specification.
6
2. Changed duty to uint32_t. However, since MAX_DUTY * (p->cmr+1)
7
can excceed UINT32_MAX, we convert them to uint64_t in computation
8
and converted them back to uint32_t.
9
(duty is guaranteed to be <= MAX_DUTY so it won't overflow.)
10
4
11
Fixes: CID 1442342
5
Signed-off-by: Patrick Venture <venture@google.com>
12
Suggested-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Cédric Le Goater <clg@kaod.org>
13
Reviewed-by: Doug Evans <dje@google.com>
7
Message-id: 20210615192848.1065297-3-venture@google.com
14
Signed-off-by: Hao Wu <wuhaotsh@google.com>
8
[PMM: fixed underline Sphinx warning]
15
Message-id: 20210127011142.2122790-1-wuhaotsh@google.com
16
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
---
10
---
19
hw/misc/npcm7xx_pwm.c | 23 +++++++++++++++++++----
11
docs/system/arm/nuvoton.rst | 5 +++--
20
tests/qtest/npcm7xx_pwm-test.c | 4 ++--
12
1 file changed, 3 insertions(+), 2 deletions(-)
21
2 files changed, 21 insertions(+), 6 deletions(-)
22
13
23
diff --git a/hw/misc/npcm7xx_pwm.c b/hw/misc/npcm7xx_pwm.c
14
diff --git a/docs/system/arm/nuvoton.rst b/docs/system/arm/nuvoton.rst
24
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
25
--- a/hw/misc/npcm7xx_pwm.c
16
--- a/docs/system/arm/nuvoton.rst
26
+++ b/hw/misc/npcm7xx_pwm.c
17
+++ b/docs/system/arm/nuvoton.rst
27
@@ -XXX,XX +XXX,XX @@ REG32(NPCM7XX_PWM_PWDR3, 0x50);
18
@@ -XXX,XX +XXX,XX @@
28
#define NPCM7XX_CH_INV BIT(2)
19
-Nuvoton iBMC boards (``npcm750-evb``, ``quanta-gsj``)
29
#define NPCM7XX_CH_MOD BIT(3)
20
-=====================================================
30
21
+Nuvoton iBMC boards (``*-bmc``, ``npcm750-evb``, ``quanta-gsj``)
31
+#define NPCM7XX_MAX_CMR 65535
22
+================================================================
32
+#define NPCM7XX_MAX_CNR 65535
23
33
+
24
The `Nuvoton iBMC`_ chips (NPCM7xx) are a family of ARM-based SoCs that are
34
/* Offset of each PWM channel's prescaler in the PPR register. */
25
designed to be used as Baseboard Management Controllers (BMCs) in various
35
static const int npcm7xx_ppr_base[] = { 0, 0, 8, 8 };
26
@@ -XXX,XX +XXX,XX @@ segment. The following machines are based on this chip :
36
/* Offset of each PWM channel's clock selector in the CSR register. */
27
The NPCM730 SoC has two Cortex-A9 cores and is targeted for Data Center and
37
@@ -XXX,XX +XXX,XX @@ static uint32_t npcm7xx_pwm_calculate_freq(NPCM7xxPWM *p)
28
Hyperscale applications. The following machines are based on this chip :
38
29
39
static uint32_t npcm7xx_pwm_calculate_duty(NPCM7xxPWM *p)
30
+- ``quanta-gbs-bmc`` Quanta GBS server BMC
40
{
31
- ``quanta-gsj`` Quanta GSJ server BMC
41
- uint64_t duty;
32
42
+ uint32_t duty;
33
There are also two more SoCs, NPCM710 and NPCM705, which are single-core
43
44
if (p->running) {
45
if (p->cnr == 0) {
46
@@ -XXX,XX +XXX,XX @@ static uint32_t npcm7xx_pwm_calculate_duty(NPCM7xxPWM *p)
47
} else if (p->cmr >= p->cnr) {
48
duty = NPCM7XX_PWM_MAX_DUTY;
49
} else {
50
- duty = NPCM7XX_PWM_MAX_DUTY * (p->cmr + 1) / (p->cnr + 1);
51
+ duty = (uint64_t)NPCM7XX_PWM_MAX_DUTY * (p->cmr + 1) / (p->cnr + 1);
52
}
53
} else {
54
duty = 0;
55
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_pwm_write(void *opaque, hwaddr offset,
56
case A_NPCM7XX_PWM_CNR2:
57
case A_NPCM7XX_PWM_CNR3:
58
p = &s->pwm[npcm7xx_cnr_index(offset)];
59
- p->cnr = value;
60
+ if (value > NPCM7XX_MAX_CNR) {
61
+ qemu_log_mask(LOG_GUEST_ERROR,
62
+ "%s: invalid cnr value: %u", __func__, value);
63
+ p->cnr = NPCM7XX_MAX_CNR;
64
+ } else {
65
+ p->cnr = value;
66
+ }
67
npcm7xx_pwm_update_output(p);
68
break;
69
70
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_pwm_write(void *opaque, hwaddr offset,
71
case A_NPCM7XX_PWM_CMR2:
72
case A_NPCM7XX_PWM_CMR3:
73
p = &s->pwm[npcm7xx_cmr_index(offset)];
74
- p->cmr = value;
75
+ if (value > NPCM7XX_MAX_CMR) {
76
+ qemu_log_mask(LOG_GUEST_ERROR,
77
+ "%s: invalid cmr value: %u", __func__, value);
78
+ p->cmr = NPCM7XX_MAX_CMR;
79
+ } else {
80
+ p->cmr = value;
81
+ }
82
npcm7xx_pwm_update_output(p);
83
break;
84
85
diff --git a/tests/qtest/npcm7xx_pwm-test.c b/tests/qtest/npcm7xx_pwm-test.c
86
index XXXXXXX..XXXXXXX 100644
87
--- a/tests/qtest/npcm7xx_pwm-test.c
88
+++ b/tests/qtest/npcm7xx_pwm-test.c
89
@@ -XXX,XX +XXX,XX @@ static uint64_t pwm_compute_freq(QTestState *qts, uint32_t ppr, uint32_t csr,
90
91
static uint64_t pwm_compute_duty(uint32_t cnr, uint32_t cmr, bool inverted)
92
{
93
- uint64_t duty;
94
+ uint32_t duty;
95
96
if (cnr == 0) {
97
/* PWM is stopped. */
98
@@ -XXX,XX +XXX,XX @@ static uint64_t pwm_compute_duty(uint32_t cnr, uint32_t cmr, bool inverted)
99
} else if (cmr >= cnr) {
100
duty = MAX_DUTY;
101
} else {
102
- duty = MAX_DUTY * (cmr + 1) / (cnr + 1);
103
+ duty = (uint64_t)MAX_DUTY * (cmr + 1) / (cnr + 1);
104
}
105
106
if (inverted) {
107
--
34
--
108
2.20.1
35
2.20.1
109
36
110
37
diff view generated by jsdifflib
[PULL 19/46] hw/misc/pvpanic: add PCI interface support
[PULL 03/24] hw/arm: Add basic power management to raspi.
1
From: Mihai Carabas <mihai.carabas@oracle.com>
1
From: Nolan Leake <nolan@sigbus.net>
2
2
3
Add PCI interface support for PVPANIC device. Create a new file pvpanic-pci.c
3
This is just enough to make reboot and poweroff work. Works for
4
where the PCI specific routines reside and update the build system with the new
4
linux, u-boot, and the arm trusted firmware. Not tested, but should
5
files and config structure.
5
work for plan9, and bare-metal/hobby OSes, since they seem to generally
6
6
do what linux does for reset.
7
Signed-off-by: Mihai Carabas <mihai.carabas@oracle.com>
7
8
Reviewed-by: Gerd Hoffmann <kraxel@redhat.com>
8
The watchdog timer functionality is not yet implemented.
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
10
Signed-off-by: Mihai Carabas <mihai.carabas@oracle.com>
10
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/64
11
Signed-off-by: Nolan Leake <nolan@sigbus.net>
12
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
13
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
14
Message-id: 20210625210209.1870217-1-nolan@sigbus.net
15
[PMM: tweaked commit title; fixed region size to 0x200;
16
moved header file to include/]
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
18
---
13
docs/specs/pci-ids.txt | 1 +
19
include/hw/arm/bcm2835_peripherals.h | 3 +-
14
include/hw/misc/pvpanic.h | 1 +
20
include/hw/misc/bcm2835_powermgt.h | 29 +++++
15
include/hw/pci/pci.h | 1 +
21
hw/arm/bcm2835_peripherals.c | 13 ++-
16
hw/misc/pvpanic-pci.c | 94 +++++++++++++++++++++++++++++++++++++++
22
hw/misc/bcm2835_powermgt.c | 160 +++++++++++++++++++++++++++
17
hw/misc/Kconfig | 6 +++
23
hw/misc/meson.build | 1 +
18
hw/misc/meson.build | 1 +
24
5 files changed, 204 insertions(+), 2 deletions(-)
19
6 files changed, 104 insertions(+)
25
create mode 100644 include/hw/misc/bcm2835_powermgt.h
20
create mode 100644 hw/misc/pvpanic-pci.c
26
create mode 100644 hw/misc/bcm2835_powermgt.c
21
27
22
diff --git a/docs/specs/pci-ids.txt b/docs/specs/pci-ids.txt
28
diff --git a/include/hw/arm/bcm2835_peripherals.h b/include/hw/arm/bcm2835_peripherals.h
23
index XXXXXXX..XXXXXXX 100644
29
index XXXXXXX..XXXXXXX 100644
24
--- a/docs/specs/pci-ids.txt
30
--- a/include/hw/arm/bcm2835_peripherals.h
25
+++ b/docs/specs/pci-ids.txt
31
+++ b/include/hw/arm/bcm2835_peripherals.h
26
@@ -XXX,XX +XXX,XX @@ PCI devices (other than virtio):
27
1b36:000d PCI xhci usb host adapter
28
1b36:000f mdpy (mdev sample device), linux/samples/vfio-mdev/mdpy.c
29
1b36:0010 PCIe NVMe device (-device nvme)
30
+1b36:0011 PCI PVPanic device (-device pvpanic-pci)
31
32
All these devices are documented in docs/specs.
33
34
diff --git a/include/hw/misc/pvpanic.h b/include/hw/misc/pvpanic.h
35
index XXXXXXX..XXXXXXX 100644
36
--- a/include/hw/misc/pvpanic.h
37
+++ b/include/hw/misc/pvpanic.h
38
@@ -XXX,XX +XXX,XX @@
32
@@ -XXX,XX +XXX,XX @@
39
#include "qom/object.h"
33
#include "hw/misc/bcm2835_mphi.h"
40
34
#include "hw/misc/bcm2835_thermal.h"
41
#define TYPE_PVPANIC_ISA_DEVICE "pvpanic"
35
#include "hw/misc/bcm2835_cprman.h"
42
+#define TYPE_PVPANIC_PCI_DEVICE "pvpanic-pci"
36
+#include "hw/misc/bcm2835_powermgt.h"
43
37
#include "hw/sd/sdhci.h"
44
#define PVPANIC_IOPORT_PROP "ioport"
38
#include "hw/sd/bcm2835_sdhost.h"
45
39
#include "hw/gpio/bcm2835_gpio.h"
46
diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h
40
@@ -XXX,XX +XXX,XX @@ struct BCM2835PeripheralState {
47
index XXXXXXX..XXXXXXX 100644
41
BCM2835MphiState mphi;
48
--- a/include/hw/pci/pci.h
42
UnimplementedDeviceState txp;
49
+++ b/include/hw/pci/pci.h
43
UnimplementedDeviceState armtmr;
50
@@ -XXX,XX +XXX,XX @@ extern bool pci_available;
44
- UnimplementedDeviceState powermgt;
51
#define PCI_DEVICE_ID_REDHAT_PCIE_BRIDGE 0x000e
45
+ BCM2835PowerMgtState powermgt;
52
#define PCI_DEVICE_ID_REDHAT_MDPY 0x000f
46
BCM2835CprmanState cprman;
53
#define PCI_DEVICE_ID_REDHAT_NVME 0x0010
47
PL011State uart0;
54
+#define PCI_DEVICE_ID_REDHAT_PVPANIC 0x0011
48
BCM2835AuxState aux;
55
#define PCI_DEVICE_ID_REDHAT_QXL 0x0100
49
diff --git a/include/hw/misc/bcm2835_powermgt.h b/include/hw/misc/bcm2835_powermgt.h
56
57
#define FMT_PCIBUS PRIx64
58
diff --git a/hw/misc/pvpanic-pci.c b/hw/misc/pvpanic-pci.c
59
new file mode 100644
50
new file mode 100644
60
index XXXXXXX..XXXXXXX
51
index XXXXXXX..XXXXXXX
61
--- /dev/null
52
--- /dev/null
62
+++ b/hw/misc/pvpanic-pci.c
53
+++ b/include/hw/misc/bcm2835_powermgt.h
63
@@ -XXX,XX +XXX,XX @@
54
@@ -XXX,XX +XXX,XX @@
64
+/*
55
+/*
65
+ * QEMU simulated PCI pvpanic device.
56
+ * BCM2835 Power Management emulation
66
+ *
57
+ *
67
+ * Copyright (C) 2020 Oracle
58
+ * Copyright (C) 2017 Marcin Chojnacki <marcinch7@gmail.com>
68
+ *
59
+ * Copyright (C) 2021 Nolan Leake <nolan@sigbus.net>
69
+ * Authors:
70
+ * Mihai Carabas <mihai.carabas@oracle.com>
71
+ *
60
+ *
72
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
61
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
73
+ * See the COPYING file in the top-level directory.
62
+ * See the COPYING file in the top-level directory.
74
+ *
63
+ */
64
+
65
+#ifndef BCM2835_POWERMGT_H
66
+#define BCM2835_POWERMGT_H
67
+
68
+#include "hw/sysbus.h"
69
+#include "qom/object.h"
70
+
71
+#define TYPE_BCM2835_POWERMGT "bcm2835-powermgt"
72
+OBJECT_DECLARE_SIMPLE_TYPE(BCM2835PowerMgtState, BCM2835_POWERMGT)
73
+
74
+struct BCM2835PowerMgtState {
75
+ SysBusDevice busdev;
76
+ MemoryRegion iomem;
77
+
78
+ uint32_t rstc;
79
+ uint32_t rsts;
80
+ uint32_t wdog;
81
+};
82
+
83
+#endif
84
diff --git a/hw/arm/bcm2835_peripherals.c b/hw/arm/bcm2835_peripherals.c
85
index XXXXXXX..XXXXXXX 100644
86
--- a/hw/arm/bcm2835_peripherals.c
87
+++ b/hw/arm/bcm2835_peripherals.c
88
@@ -XXX,XX +XXX,XX @@ static void bcm2835_peripherals_init(Object *obj)
89
90
object_property_add_const_link(OBJECT(&s->dwc2), "dma-mr",
91
OBJECT(&s->gpu_bus_mr));
92
+
93
+ /* Power Management */
94
+ object_initialize_child(obj, "powermgt", &s->powermgt,
95
+ TYPE_BCM2835_POWERMGT);
96
}
97
98
static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp)
99
@@ -XXX,XX +XXX,XX @@ static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp)
100
qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ,
101
INTERRUPT_USB));
102
103
+ /* Power Management */
104
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->powermgt), errp)) {
105
+ return;
106
+ }
107
+
108
+ memory_region_add_subregion(&s->peri_mr, PM_OFFSET,
109
+ sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->powermgt), 0));
110
+
111
create_unimp(s, &s->txp, "bcm2835-txp", TXP_OFFSET, 0x1000);
112
create_unimp(s, &s->armtmr, "bcm2835-sp804", ARMCTRL_TIMER0_1_OFFSET, 0x40);
113
- create_unimp(s, &s->powermgt, "bcm2835-powermgt", PM_OFFSET, 0x114);
114
create_unimp(s, &s->i2s, "bcm2835-i2s", I2S_OFFSET, 0x100);
115
create_unimp(s, &s->smi, "bcm2835-smi", SMI_OFFSET, 0x100);
116
create_unimp(s, &s->spi[0], "bcm2835-spi0", SPI0_OFFSET, 0x20);
117
diff --git a/hw/misc/bcm2835_powermgt.c b/hw/misc/bcm2835_powermgt.c
118
new file mode 100644
119
index XXXXXXX..XXXXXXX
120
--- /dev/null
121
+++ b/hw/misc/bcm2835_powermgt.c
122
@@ -XXX,XX +XXX,XX @@
123
+/*
124
+ * BCM2835 Power Management emulation
125
+ *
126
+ * Copyright (C) 2017 Marcin Chojnacki <marcinch7@gmail.com>
127
+ * Copyright (C) 2021 Nolan Leake <nolan@sigbus.net>
128
+ *
129
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
130
+ * See the COPYING file in the top-level directory.
75
+ */
131
+ */
76
+
132
+
77
+#include "qemu/osdep.h"
133
+#include "qemu/osdep.h"
78
+#include "qemu/log.h"
134
+#include "qemu/log.h"
79
+#include "qemu/module.h"
135
+#include "qemu/module.h"
136
+#include "hw/misc/bcm2835_powermgt.h"
137
+#include "migration/vmstate.h"
80
+#include "sysemu/runstate.h"
138
+#include "sysemu/runstate.h"
81
+
139
+
82
+#include "hw/nvram/fw_cfg.h"
140
+#define PASSWORD 0x5a000000
83
+#include "hw/qdev-properties.h"
141
+#define PASSWORD_MASK 0xff000000
84
+#include "migration/vmstate.h"
142
+
85
+#include "hw/misc/pvpanic.h"
143
+#define R_RSTC 0x1c
86
+#include "qom/object.h"
144
+#define V_RSTC_RESET 0x20
87
+#include "hw/pci/pci.h"
145
+#define R_RSTS 0x20
88
+
146
+#define V_RSTS_POWEROFF 0x555 /* Linux uses partition 63 to indicate halt. */
89
+OBJECT_DECLARE_SIMPLE_TYPE(PVPanicPCIState, PVPANIC_PCI_DEVICE)
147
+#define R_WDOG 0x24
90
+
148
+
91
+/*
149
+static uint64_t bcm2835_powermgt_read(void *opaque, hwaddr offset,
92
+ * PVPanicPCIState for PCI device
150
+ unsigned size)
93
+ */
151
+{
94
+typedef struct PVPanicPCIState {
152
+ BCM2835PowerMgtState *s = (BCM2835PowerMgtState *)opaque;
95
+ PCIDevice dev;
153
+ uint32_t res = 0;
96
+ PVPanicState pvpanic;
154
+
97
+} PVPanicPCIState;
155
+ switch (offset) {
98
+
156
+ case R_RSTC:
99
+static const VMStateDescription vmstate_pvpanic_pci = {
157
+ res = s->rstc;
100
+ .name = "pvpanic-pci",
158
+ break;
159
+ case R_RSTS:
160
+ res = s->rsts;
161
+ break;
162
+ case R_WDOG:
163
+ res = s->wdog;
164
+ break;
165
+
166
+ default:
167
+ qemu_log_mask(LOG_UNIMP,
168
+ "bcm2835_powermgt_read: Unknown offset 0x%08"HWADDR_PRIx
169
+ "\n", offset);
170
+ res = 0;
171
+ break;
172
+ }
173
+
174
+ return res;
175
+}
176
+
177
+static void bcm2835_powermgt_write(void *opaque, hwaddr offset,
178
+ uint64_t value, unsigned size)
179
+{
180
+ BCM2835PowerMgtState *s = (BCM2835PowerMgtState *)opaque;
181
+
182
+ if ((value & PASSWORD_MASK) != PASSWORD) {
183
+ qemu_log_mask(LOG_GUEST_ERROR,
184
+ "bcm2835_powermgt_write: Bad password 0x%"PRIx64
185
+ " at offset 0x%08"HWADDR_PRIx"\n",
186
+ value, offset);
187
+ return;
188
+ }
189
+
190
+ value = value & ~PASSWORD_MASK;
191
+
192
+ switch (offset) {
193
+ case R_RSTC:
194
+ s->rstc = value;
195
+ if (value & V_RSTC_RESET) {
196
+ if ((s->rsts & 0xfff) == V_RSTS_POWEROFF) {
197
+ qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
198
+ } else {
199
+ qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
200
+ }
201
+ }
202
+ break;
203
+ case R_RSTS:
204
+ qemu_log_mask(LOG_UNIMP,
205
+ "bcm2835_powermgt_write: RSTS\n");
206
+ s->rsts = value;
207
+ break;
208
+ case R_WDOG:
209
+ qemu_log_mask(LOG_UNIMP,
210
+ "bcm2835_powermgt_write: WDOG\n");
211
+ s->wdog = value;
212
+ break;
213
+
214
+ default:
215
+ qemu_log_mask(LOG_UNIMP,
216
+ "bcm2835_powermgt_write: Unknown offset 0x%08"HWADDR_PRIx
217
+ "\n", offset);
218
+ break;
219
+ }
220
+}
221
+
222
+static const MemoryRegionOps bcm2835_powermgt_ops = {
223
+ .read = bcm2835_powermgt_read,
224
+ .write = bcm2835_powermgt_write,
225
+ .endianness = DEVICE_NATIVE_ENDIAN,
226
+ .impl.min_access_size = 4,
227
+ .impl.max_access_size = 4,
228
+};
229
+
230
+static const VMStateDescription vmstate_bcm2835_powermgt = {
231
+ .name = TYPE_BCM2835_POWERMGT,
101
+ .version_id = 1,
232
+ .version_id = 1,
102
+ .minimum_version_id = 1,
233
+ .minimum_version_id = 1,
103
+ .fields = (VMStateField[]) {
234
+ .fields = (VMStateField[]) {
104
+ VMSTATE_PCI_DEVICE(dev, PVPanicPCIState),
235
+ VMSTATE_UINT32(rstc, BCM2835PowerMgtState),
236
+ VMSTATE_UINT32(rsts, BCM2835PowerMgtState),
237
+ VMSTATE_UINT32(wdog, BCM2835PowerMgtState),
105
+ VMSTATE_END_OF_LIST()
238
+ VMSTATE_END_OF_LIST()
106
+ }
239
+ }
107
+};
240
+};
108
+
241
+
109
+static void pvpanic_pci_realizefn(PCIDevice *dev, Error **errp)
242
+static void bcm2835_powermgt_init(Object *obj)
110
+{
243
+{
111
+ PVPanicPCIState *s = PVPANIC_PCI_DEVICE(dev);
244
+ BCM2835PowerMgtState *s = BCM2835_POWERMGT(obj);
112
+ PVPanicState *ps = &s->pvpanic;
245
+
113
+
246
+ memory_region_init_io(&s->iomem, obj, &bcm2835_powermgt_ops, s,
114
+ pvpanic_setup_io(&s->pvpanic, DEVICE(s), 2);
247
+ TYPE_BCM2835_POWERMGT, 0x200);
115
+
248
+ sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem);
116
+ pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &ps->mr);
249
+}
117
+}
250
+
118
+
251
+static void bcm2835_powermgt_reset(DeviceState *dev)
119
+static Property pvpanic_pci_properties[] = {
252
+{
120
+ DEFINE_PROP_UINT8("events", PVPanicPCIState, pvpanic.events, PVPANIC_PANICKED | PVPANIC_CRASHLOADED),
253
+ BCM2835PowerMgtState *s = BCM2835_POWERMGT(dev);
121
+ DEFINE_PROP_END_OF_LIST(),
254
+
122
+};
255
+ /* https://elinux.org/BCM2835_registers#PM */
123
+
256
+ s->rstc = 0x00000102;
124
+static void pvpanic_pci_class_init(ObjectClass *klass, void *data)
257
+ s->rsts = 0x00001000;
258
+ s->wdog = 0x00000000;
259
+}
260
+
261
+static void bcm2835_powermgt_class_init(ObjectClass *klass, void *data)
125
+{
262
+{
126
+ DeviceClass *dc = DEVICE_CLASS(klass);
263
+ DeviceClass *dc = DEVICE_CLASS(klass);
127
+ PCIDeviceClass *pc = PCI_DEVICE_CLASS(klass);
264
+
128
+
265
+ dc->reset = bcm2835_powermgt_reset;
129
+ device_class_set_props(dc, pvpanic_pci_properties);
266
+ dc->vmsd = &vmstate_bcm2835_powermgt;
130
+
267
+}
131
+ pc->realize = pvpanic_pci_realizefn;
268
+
132
+ pc->vendor_id = PCI_VENDOR_ID_REDHAT;
269
+static TypeInfo bcm2835_powermgt_info = {
133
+ pc->device_id = PCI_DEVICE_ID_REDHAT_PVPANIC;
270
+ .name = TYPE_BCM2835_POWERMGT,
134
+ pc->revision = 1;
271
+ .parent = TYPE_SYS_BUS_DEVICE,
135
+ pc->class_id = PCI_CLASS_SYSTEM_OTHER;
272
+ .instance_size = sizeof(BCM2835PowerMgtState),
136
+ dc->vmsd = &vmstate_pvpanic_pci;
273
+ .class_init = bcm2835_powermgt_class_init,
137
+
274
+ .instance_init = bcm2835_powermgt_init,
138
+ set_bit(DEVICE_CATEGORY_MISC, dc->categories);
275
+};
139
+}
276
+
140
+
277
+static void bcm2835_powermgt_register_types(void)
141
+static TypeInfo pvpanic_pci_info = {
278
+{
142
+ .name = TYPE_PVPANIC_PCI_DEVICE,
279
+ type_register_static(&bcm2835_powermgt_info);
143
+ .parent = TYPE_PCI_DEVICE,
280
+}
144
+ .instance_size = sizeof(PVPanicPCIState),
281
+
145
+ .class_init = pvpanic_pci_class_init,
282
+type_init(bcm2835_powermgt_register_types)
146
+ .interfaces = (InterfaceInfo[]) {
147
+ { INTERFACE_CONVENTIONAL_PCI_DEVICE },
148
+ { }
149
+ }
150
+};
151
+
152
+static void pvpanic_register_types(void)
153
+{
154
+ type_register_static(&pvpanic_pci_info);
155
+}
156
+
157
+type_init(pvpanic_register_types);
158
diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig
159
index XXXXXXX..XXXXXXX 100644
160
--- a/hw/misc/Kconfig
161
+++ b/hw/misc/Kconfig
162
@@ -XXX,XX +XXX,XX @@ config IOTKIT_SYSINFO
163
config PVPANIC_COMMON
164
bool
165
166
+config PVPANIC_PCI
167
+ bool
168
+ default y if PCI_DEVICES
169
+ depends on PCI
170
+ select PVPANIC_COMMON
171
+
172
config PVPANIC_ISA
173
bool
174
depends on ISA_BUS
175
diff --git a/hw/misc/meson.build b/hw/misc/meson.build
283
diff --git a/hw/misc/meson.build b/hw/misc/meson.build
176
index XXXXXXX..XXXXXXX 100644
284
index XXXXXXX..XXXXXXX 100644
177
--- a/hw/misc/meson.build
285
--- a/hw/misc/meson.build
178
+++ b/hw/misc/meson.build
286
+++ b/hw/misc/meson.build
179
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_ARMSSE_CPUID', if_true: files('armsse-cpuid.c'))
287
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files(
180
softmmu_ss.add(when: 'CONFIG_ARMSSE_MHU', if_true: files('armsse-mhu.c'))
288
'bcm2835_rng.c',
181
289
'bcm2835_thermal.c',
182
softmmu_ss.add(when: 'CONFIG_PVPANIC_ISA', if_true: files('pvpanic-isa.c'))
290
'bcm2835_cprman.c',
183
+softmmu_ss.add(when: 'CONFIG_PVPANIC_PCI', if_true: files('pvpanic-pci.c'))
291
+ 'bcm2835_powermgt.c',
184
softmmu_ss.add(when: 'CONFIG_AUX', if_true: files('auxbus.c'))
292
))
185
softmmu_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files('aspeed_scu.c', 'aspeed_sdmc.c', 'aspeed_xdma.c'))
293
softmmu_ss.add(when: 'CONFIG_SLAVIO', if_true: files('slavio_misc.c'))
186
softmmu_ss.add(when: 'CONFIG_MSF2', if_true: files('msf2-sysreg.c'))
294
softmmu_ss.add(when: 'CONFIG_ZYNQ', if_true: files('zynq_slcr.c', 'zynq-xadc.c'))
187
--
295
--
188
2.20.1
296
2.20.1
189
297
190
298
diff view generated by jsdifflib
[PULL 08/46] target/arm: Replace magic value by MMU_DATA_LOAD definition
[PULL 04/24] tests: Boot and halt a Linux guest on the Raspberry Pi 2 machine
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
2
3
cpu_get_phys_page_debug() uses 'DATA LOAD' MMU access type.
3
Add a test booting and quickly shutdown a raspi2 machine,
4
to test the power management model:
5
6
(1/1) tests/acceptance/boot_linux_console.py:BootLinuxConsole.test_arm_raspi2_initrd:
7
console: [ 0.000000] Booting Linux on physical CPU 0xf00
8
console: [ 0.000000] Linux version 4.14.98-v7+ (dom@dom-XPS-13-9370) (gcc version 4.9.3 (crosstool-NG crosstool-ng-1.22.0-88-g8460611)) #1200 SMP Tue Feb 12 20:27:48 GMT 2019
9
console: [ 0.000000] CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7), cr=10c5387d
10
console: [ 0.000000] CPU: div instructions available: patching division code
11
console: [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
12
console: [ 0.000000] OF: fdt: Machine model: Raspberry Pi 2 Model B
13
...
14
console: Boot successful.
15
console: cat /proc/cpuinfo
16
console: / # cat /proc/cpuinfo
17
...
18
console: processor : 3
19
console: model name : ARMv7 Processor rev 5 (v7l)
20
console: BogoMIPS : 125.00
21
console: Features : half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt vfpd32 lpae evtstrm
22
console: CPU implementer : 0x41
23
console: CPU architecture: 7
24
console: CPU variant : 0x0
25
console: CPU part : 0xc07
26
console: CPU revision : 5
27
console: Hardware : BCM2835
28
console: Revision : 0000
29
console: Serial : 0000000000000000
30
console: cat /proc/iomem
31
console: / # cat /proc/iomem
32
console: 00000000-3bffffff : System RAM
33
console: 00008000-00afffff : Kernel code
34
console: 00c00000-00d468ef : Kernel data
35
console: 3f006000-3f006fff : dwc_otg
36
console: 3f007000-3f007eff : /soc/dma@7e007000
37
console: 3f00b880-3f00b8bf : /soc/mailbox@7e00b880
38
console: 3f100000-3f100027 : /soc/watchdog@7e100000
39
console: 3f101000-3f102fff : /soc/cprman@7e101000
40
console: 3f200000-3f2000b3 : /soc/gpio@7e200000
41
PASS (24.59 s)
42
RESULTS : PASS 1 | ERROR 0 | FAIL 0 | SKIP 0 | WARN 0 | INTERRUPT 0 | CANCEL 0
43
JOB TIME : 25.02 s
4
44
5
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
45
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
6
Message-id: 20210127232822.3530782-1-f4bug@amsat.org
46
Reviewed-by: Wainer dos Santos Moschetta <wainersm@redhat.com>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
47
Message-id: 20210531113837.1689775-1-f4bug@amsat.org
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
48
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
49
---
10
target/arm/helper.c | 2 +-
50
tests/acceptance/boot_linux_console.py | 43 ++++++++++++++++++++++++++
11
1 file changed, 1 insertion(+), 1 deletion(-)
51
1 file changed, 43 insertions(+)
12
52
13
diff --git a/target/arm/helper.c b/target/arm/helper.c
53
diff --git a/tests/acceptance/boot_linux_console.py b/tests/acceptance/boot_linux_console.py
14
index XXXXXXX..XXXXXXX 100644
54
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/helper.c
55
--- a/tests/acceptance/boot_linux_console.py
16
+++ b/target/arm/helper.c
56
+++ b/tests/acceptance/boot_linux_console.py
17
@@ -XXX,XX +XXX,XX @@ hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr,
57
@@ -XXX,XX +XXX,XX @@
18
58
from avocado import skip
19
*attrs = (MemTxAttrs) {};
59
from avocado import skipUnless
20
60
from avocado_qemu import Test
21
- ret = get_phys_addr(env, addr, 0, mmu_idx, &phys_addr,
61
+from avocado_qemu import exec_command
22
+ ret = get_phys_addr(env, addr, MMU_DATA_LOAD, mmu_idx, &phys_addr,
62
from avocado_qemu import exec_command_and_wait_for_pattern
23
attrs, &prot, &page_size, &fi, &cacheattrs);
63
from avocado_qemu import interrupt_interactive_console_until_pattern
24
64
from avocado_qemu import wait_for_console_pattern
25
if (ret) {
65
@@ -XXX,XX +XXX,XX @@ def test_arm_raspi2_uart0(self):
66
"""
67
self.do_test_arm_raspi2(0)
68
69
+ def test_arm_raspi2_initrd(self):
70
+ """
71
+ :avocado: tags=arch:arm
72
+ :avocado: tags=machine:raspi2
73
+ """
74
+ deb_url = ('http://archive.raspberrypi.org/debian/'
75
+ 'pool/main/r/raspberrypi-firmware/'
76
+ 'raspberrypi-kernel_1.20190215-1_armhf.deb')
77
+ deb_hash = 'cd284220b32128c5084037553db3c482426f3972'
78
+ deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash)
79
+ kernel_path = self.extract_from_deb(deb_path, '/boot/kernel7.img')
80
+ dtb_path = self.extract_from_deb(deb_path, '/boot/bcm2709-rpi-2-b.dtb')
81
+
82
+ initrd_url = ('https://github.com/groeck/linux-build-test/raw/'
83
+ '2eb0a73b5d5a28df3170c546ddaaa9757e1e0848/rootfs/'
84
+ 'arm/rootfs-armv7a.cpio.gz')
85
+ initrd_hash = '604b2e45cdf35045846b8bbfbf2129b1891bdc9c'
86
+ initrd_path_gz = self.fetch_asset(initrd_url, asset_hash=initrd_hash)
87
+ initrd_path = os.path.join(self.workdir, 'rootfs.cpio')
88
+ archive.gzip_uncompress(initrd_path_gz, initrd_path)
89
+
90
+ self.vm.set_console()
91
+ kernel_command_line = (self.KERNEL_COMMON_COMMAND_LINE +
92
+ 'earlycon=pl011,0x3f201000 console=ttyAMA0 '
93
+ 'panic=-1 noreboot ' +
94
+ 'dwc_otg.fiq_fsm_enable=0')
95
+ self.vm.add_args('-kernel', kernel_path,
96
+ '-dtb', dtb_path,
97
+ '-initrd', initrd_path,
98
+ '-append', kernel_command_line,
99
+ '-no-reboot')
100
+ self.vm.launch()
101
+ self.wait_for_console_pattern('Boot successful.')
102
+
103
+ exec_command_and_wait_for_pattern(self, 'cat /proc/cpuinfo',
104
+ 'BCM2835')
105
+ exec_command_and_wait_for_pattern(self, 'cat /proc/iomem',
106
+ '/soc/cprman@7e101000')
107
+ exec_command(self, 'halt')
108
+ # Wait for VM to shut down gracefully
109
+ self.vm.wait()
110
+
111
def test_arm_exynos4210_initrd(self):
112
"""
113
:avocado: tags=arch:arm
26
--
114
--
27
2.20.1
115
2.20.1
28
116
29
117
diff view generated by jsdifflib
[PULL 02/46] target/arm: Conditionalize DBGDIDR
[PULL 05/24] target/arm: Check NaN mode before silencing NaN
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Joe Komlodi <joe.komlodi@xilinx.com>
2
2
3
Only define the register if it exists for the cpu.
3
If the CPU is running in default NaN mode (FPCR.DN == 1) and we execute
4
FRSQRTE, FRECPE, or FRECPX with a signaling NaN, parts_silence_nan_frac() will
5
assert due to fpst->default_nan_mode being set.
4
6
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
To avoid this, we check to see what NaN mode we're running in before we call
6
Message-id: 20210120031656.737646-1-richard.henderson@linaro.org
8
floatxx_silence_nan().
9
10
Signed-off-by: Joe Komlodi <joe.komlodi@xilinx.com>
11
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
12
Message-id: 1624662174-175828-2-git-send-email-joe.komlodi@xilinx.com
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
13
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
15
---
10
target/arm/helper.c | 21 +++++++++++++++------
16
target/arm/helper-a64.c | 12 +++++++++---
11
1 file changed, 15 insertions(+), 6 deletions(-)
17
target/arm/vfp_helper.c | 24 ++++++++++++++++++------
18
2 files changed, 27 insertions(+), 9 deletions(-)
12
19
13
diff --git a/target/arm/helper.c b/target/arm/helper.c
20
diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
14
index XXXXXXX..XXXXXXX 100644
21
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/helper.c
22
--- a/target/arm/helper-a64.c
16
+++ b/target/arm/helper.c
23
+++ b/target/arm/helper-a64.c
17
@@ -XXX,XX +XXX,XX @@ static void define_debug_regs(ARMCPU *cpu)
24
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(frecpx_f16)(uint32_t a, void *fpstp)
18
*/
25
float16 nan = a;
19
int i;
26
if (float16_is_signaling_nan(a, fpst)) {
20
int wrps, brps, ctx_cmps;
27
float_raise(float_flag_invalid, fpst);
21
- ARMCPRegInfo dbgdidr = {
28
- nan = float16_silence_nan(a, fpst);
22
- .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0,
29
+ if (!fpst->default_nan_mode) {
23
- .access = PL0_R, .accessfn = access_tda,
30
+ nan = float16_silence_nan(a, fpst);
24
- .type = ARM_CP_CONST, .resetvalue = cpu->isar.dbgdidr,
31
+ }
25
- };
32
}
26
+
33
if (fpst->default_nan_mode) {
27
+ /*
34
nan = float16_default_nan(fpst);
28
+ * The Arm ARM says DBGDIDR is optional and deprecated if EL1 cannot
35
@@ -XXX,XX +XXX,XX @@ float32 HELPER(frecpx_f32)(float32 a, void *fpstp)
29
+ * use AArch32. Given that bit 15 is RES1, if the value is 0 then
36
float32 nan = a;
30
+ * the register must not exist for this cpu.
37
if (float32_is_signaling_nan(a, fpst)) {
31
+ */
38
float_raise(float_flag_invalid, fpst);
32
+ if (cpu->isar.dbgdidr != 0) {
39
- nan = float32_silence_nan(a, fpst);
33
+ ARMCPRegInfo dbgdidr = {
40
+ if (!fpst->default_nan_mode) {
34
+ .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0,
41
+ nan = float32_silence_nan(a, fpst);
35
+ .opc1 = 0, .opc2 = 0,
42
+ }
36
+ .access = PL0_R, .accessfn = access_tda,
43
}
37
+ .type = ARM_CP_CONST, .resetvalue = cpu->isar.dbgdidr,
44
if (fpst->default_nan_mode) {
38
+ };
45
nan = float32_default_nan(fpst);
39
+ define_one_arm_cp_reg(cpu, &dbgdidr);
46
@@ -XXX,XX +XXX,XX @@ float64 HELPER(frecpx_f64)(float64 a, void *fpstp)
40
+ }
47
float64 nan = a;
41
48
if (float64_is_signaling_nan(a, fpst)) {
42
/* Note that all these register fields hold "number of Xs minus 1". */
49
float_raise(float_flag_invalid, fpst);
43
brps = arm_num_brps(cpu);
50
- nan = float64_silence_nan(a, fpst);
44
@@ -XXX,XX +XXX,XX @@ static void define_debug_regs(ARMCPU *cpu)
51
+ if (!fpst->default_nan_mode) {
45
52
+ nan = float64_silence_nan(a, fpst);
46
assert(ctx_cmps <= brps);
53
+ }
47
54
}
48
- define_one_arm_cp_reg(cpu, &dbgdidr);
55
if (fpst->default_nan_mode) {
49
define_arm_cp_regs(cpu, debug_cp_reginfo);
56
nan = float64_default_nan(fpst);
50
57
diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c
51
if (arm_feature(&cpu->env, ARM_FEATURE_LPAE)) {
58
index XXXXXXX..XXXXXXX 100644
59
--- a/target/arm/vfp_helper.c
60
+++ b/target/arm/vfp_helper.c
61
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(recpe_f16)(uint32_t input, void *fpstp)
62
float16 nan = f16;
63
if (float16_is_signaling_nan(f16, fpst)) {
64
float_raise(float_flag_invalid, fpst);
65
- nan = float16_silence_nan(f16, fpst);
66
+ if (!fpst->default_nan_mode) {
67
+ nan = float16_silence_nan(f16, fpst);
68
+ }
69
}
70
if (fpst->default_nan_mode) {
71
nan = float16_default_nan(fpst);
72
@@ -XXX,XX +XXX,XX @@ float32 HELPER(recpe_f32)(float32 input, void *fpstp)
73
float32 nan = f32;
74
if (float32_is_signaling_nan(f32, fpst)) {
75
float_raise(float_flag_invalid, fpst);
76
- nan = float32_silence_nan(f32, fpst);
77
+ if (!fpst->default_nan_mode) {
78
+ nan = float32_silence_nan(f32, fpst);
79
+ }
80
}
81
if (fpst->default_nan_mode) {
82
nan = float32_default_nan(fpst);
83
@@ -XXX,XX +XXX,XX @@ float64 HELPER(recpe_f64)(float64 input, void *fpstp)
84
float64 nan = f64;
85
if (float64_is_signaling_nan(f64, fpst)) {
86
float_raise(float_flag_invalid, fpst);
87
- nan = float64_silence_nan(f64, fpst);
88
+ if (!fpst->default_nan_mode) {
89
+ nan = float64_silence_nan(f64, fpst);
90
+ }
91
}
92
if (fpst->default_nan_mode) {
93
nan = float64_default_nan(fpst);
94
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(rsqrte_f16)(uint32_t input, void *fpstp)
95
float16 nan = f16;
96
if (float16_is_signaling_nan(f16, s)) {
97
float_raise(float_flag_invalid, s);
98
- nan = float16_silence_nan(f16, s);
99
+ if (!s->default_nan_mode) {
100
+ nan = float16_silence_nan(f16, fpstp);
101
+ }
102
}
103
if (s->default_nan_mode) {
104
nan = float16_default_nan(s);
105
@@ -XXX,XX +XXX,XX @@ float32 HELPER(rsqrte_f32)(float32 input, void *fpstp)
106
float32 nan = f32;
107
if (float32_is_signaling_nan(f32, s)) {
108
float_raise(float_flag_invalid, s);
109
- nan = float32_silence_nan(f32, s);
110
+ if (!s->default_nan_mode) {
111
+ nan = float32_silence_nan(f32, fpstp);
112
+ }
113
}
114
if (s->default_nan_mode) {
115
nan = float32_default_nan(s);
116
@@ -XXX,XX +XXX,XX @@ float64 HELPER(rsqrte_f64)(float64 input, void *fpstp)
117
float64 nan = f64;
118
if (float64_is_signaling_nan(f64, s)) {
119
float_raise(float_flag_invalid, s);
120
- nan = float64_silence_nan(f64, s);
121
+ if (!s->default_nan_mode) {
122
+ nan = float64_silence_nan(f64, fpstp);
123
+ }
124
}
125
if (s->default_nan_mode) {
126
nan = float64_default_nan(s);
52
--
127
--
53
2.20.1
128
2.20.1
54
129
55
130
diff view generated by jsdifflib
[PULL 03/46] arm: rename xlnx-zcu102.canbusN properties
Deleted patch
1
From: Paolo Bonzini <pbonzini@redhat.com>
2
1
3
The properties to attach a CANBUS object to the xlnx-zcu102 machine have
4
a period in them. We want to use periods in properties for compound QAPI types,
5
and besides the "xlnx-zcu102." prefix is both unnecessary and different
6
from any other machine property name. Remove it.
7
8
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
9
Message-id: 20210118162537.779542-1-pbonzini@redhat.com
10
Reviewed-by: Vikram Garhwal <fnu.vikram@xilinx.com>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
hw/arm/xlnx-zcu102.c | 4 ++--
14
tests/qtest/xlnx-can-test.c | 30 +++++++++++++++---------------
15
2 files changed, 17 insertions(+), 17 deletions(-)
16
17
diff --git a/hw/arm/xlnx-zcu102.c b/hw/arm/xlnx-zcu102.c
18
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/arm/xlnx-zcu102.c
20
+++ b/hw/arm/xlnx-zcu102.c
21
@@ -XXX,XX +XXX,XX @@ static void xlnx_zcu102_machine_instance_init(Object *obj)
22
s->secure = false;
23
/* Default to virt (EL2) being disabled */
24
s->virt = false;
25
- object_property_add_link(obj, "xlnx-zcu102.canbus0", TYPE_CAN_BUS,
26
+ object_property_add_link(obj, "canbus0", TYPE_CAN_BUS,
27
(Object **)&s->canbus[0],
28
object_property_allow_set_link,
29
0);
30
31
- object_property_add_link(obj, "xlnx-zcu102.canbus1", TYPE_CAN_BUS,
32
+ object_property_add_link(obj, "canbus1", TYPE_CAN_BUS,
33
(Object **)&s->canbus[1],
34
object_property_allow_set_link,
35
0);
36
diff --git a/tests/qtest/xlnx-can-test.c b/tests/qtest/xlnx-can-test.c
37
index XXXXXXX..XXXXXXX 100644
38
--- a/tests/qtest/xlnx-can-test.c
39
+++ b/tests/qtest/xlnx-can-test.c
40
@@ -XXX,XX +XXX,XX @@ static void test_can_bus(void)
41
uint8_t can_timestamp = 1;
42
43
QTestState *qts = qtest_init("-machine xlnx-zcu102"
44
- " -object can-bus,id=canbus0"
45
- " -machine xlnx-zcu102.canbus0=canbus0"
46
- " -machine xlnx-zcu102.canbus1=canbus0"
47
+ " -object can-bus,id=canbus"
48
+ " -machine canbus0=canbus"
49
+ " -machine canbus1=canbus"
50
);
51
52
/* Configure the CAN0 and CAN1. */
53
@@ -XXX,XX +XXX,XX @@ static void test_can_loopback(void)
54
uint32_t status = 0;
55
56
QTestState *qts = qtest_init("-machine xlnx-zcu102"
57
- " -object can-bus,id=canbus0"
58
- " -machine xlnx-zcu102.canbus0=canbus0"
59
- " -machine xlnx-zcu102.canbus1=canbus0"
60
+ " -object can-bus,id=canbus"
61
+ " -machine canbus0=canbus"
62
+ " -machine canbus1=canbus"
63
);
64
65
/* Configure the CAN0 in loopback mode. */
66
@@ -XXX,XX +XXX,XX @@ static void test_can_filter(void)
67
uint8_t can_timestamp = 1;
68
69
QTestState *qts = qtest_init("-machine xlnx-zcu102"
70
- " -object can-bus,id=canbus0"
71
- " -machine xlnx-zcu102.canbus0=canbus0"
72
- " -machine xlnx-zcu102.canbus1=canbus0"
73
+ " -object can-bus,id=canbus"
74
+ " -machine canbus0=canbus"
75
+ " -machine canbus1=canbus"
76
);
77
78
/* Configure the CAN0 and CAN1. */
79
@@ -XXX,XX +XXX,XX @@ static void test_can_sleepmode(void)
80
uint8_t can_timestamp = 1;
81
82
QTestState *qts = qtest_init("-machine xlnx-zcu102"
83
- " -object can-bus,id=canbus0"
84
- " -machine xlnx-zcu102.canbus0=canbus0"
85
- " -machine xlnx-zcu102.canbus1=canbus0"
86
+ " -object can-bus,id=canbus"
87
+ " -machine canbus0=canbus"
88
+ " -machine canbus1=canbus"
89
);
90
91
/* Configure the CAN0. */
92
@@ -XXX,XX +XXX,XX @@ static void test_can_snoopmode(void)
93
uint8_t can_timestamp = 1;
94
95
QTestState *qts = qtest_init("-machine xlnx-zcu102"
96
- " -object can-bus,id=canbus0"
97
- " -machine xlnx-zcu102.canbus0=canbus0"
98
- " -machine xlnx-zcu102.canbus1=canbus0"
99
+ " -object can-bus,id=canbus"
100
+ " -machine canbus0=canbus"
101
+ " -machine canbus1=canbus"
102
);
103
104
/* Configure the CAN0. */
105
--
106
2.20.1
107
108
diff view generated by jsdifflib
[PULL 05/46] arm-virt: refactor gpios creation
[PULL 06/24] hw/gpio/gpio_pwr: use shutdown function for reboot
1
From: Maxim Uvarov <maxim.uvarov@linaro.org>
1
From: Maxim Uvarov <maxim.uvarov@linaro.org>
2
2
3
No functional change. Just refactor code to better
3
qemu has 2 type of functions: shutdown and reboot. Shutdown
4
support secure and normal world gpios.
4
function has to be used for machine shutdown. Otherwise we cause
5
a reset with a bogus "cause" value, when we intended a shutdown.
5
6
6
Signed-off-by: Maxim Uvarov <maxim.uvarov@linaro.org>
7
Signed-off-by: Maxim Uvarov <maxim.uvarov@linaro.org>
7
Reviewed-by: Andrew Jones <drjones@redhat.com>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Message-id: 20210625111842.3790-3-maxim.uvarov@linaro.org
10
[PMM: tweaked commit message]
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
12
---
10
hw/arm/virt.c | 57 ++++++++++++++++++++++++++++++++-------------------
13
hw/gpio/gpio_pwr.c | 2 +-
11
1 file changed, 36 insertions(+), 21 deletions(-)
14
1 file changed, 1 insertion(+), 1 deletion(-)
12
15
13
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
16
diff --git a/hw/gpio/gpio_pwr.c b/hw/gpio/gpio_pwr.c
14
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
15
--- a/hw/arm/virt.c
18
--- a/hw/gpio/gpio_pwr.c
16
+++ b/hw/arm/virt.c
19
+++ b/hw/gpio/gpio_pwr.c
17
@@ -XXX,XX +XXX,XX @@ static void virt_powerdown_req(Notifier *n, void *opaque)
20
@@ -XXX,XX +XXX,XX @@ static void gpio_pwr_reset(void *opaque, int n, int level)
21
static void gpio_pwr_shutdown(void *opaque, int n, int level)
22
{
23
if (level) {
24
- qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
25
+ qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
18
}
26
}
19
}
27
}
20
28
21
-static void create_gpio(const VirtMachineState *vms)
22
+static void create_gpio_keys(const VirtMachineState *vms,
23
+ DeviceState *pl061_dev,
24
+ uint32_t phandle)
25
+{
26
+ gpio_key_dev = sysbus_create_simple("gpio-key", -1,
27
+ qdev_get_gpio_in(pl061_dev, 3));
28
+
29
+ qemu_fdt_add_subnode(vms->fdt, "/gpio-keys");
30
+ qemu_fdt_setprop_string(vms->fdt, "/gpio-keys", "compatible", "gpio-keys");
31
+ qemu_fdt_setprop_cell(vms->fdt, "/gpio-keys", "#size-cells", 0);
32
+ qemu_fdt_setprop_cell(vms->fdt, "/gpio-keys", "#address-cells", 1);
33
+
34
+ qemu_fdt_add_subnode(vms->fdt, "/gpio-keys/poweroff");
35
+ qemu_fdt_setprop_string(vms->fdt, "/gpio-keys/poweroff",
36
+ "label", "GPIO Key Poweroff");
37
+ qemu_fdt_setprop_cell(vms->fdt, "/gpio-keys/poweroff", "linux,code",
38
+ KEY_POWER);
39
+ qemu_fdt_setprop_cells(vms->fdt, "/gpio-keys/poweroff",
40
+ "gpios", phandle, 3, 0);
41
+}
42
+
43
+static void create_gpio_devices(const VirtMachineState *vms, int gpio,
44
+ MemoryRegion *mem)
45
{
46
char *nodename;
47
DeviceState *pl061_dev;
48
- hwaddr base = vms->memmap[VIRT_GPIO].base;
49
- hwaddr size = vms->memmap[VIRT_GPIO].size;
50
- int irq = vms->irqmap[VIRT_GPIO];
51
+ hwaddr base = vms->memmap[gpio].base;
52
+ hwaddr size = vms->memmap[gpio].size;
53
+ int irq = vms->irqmap[gpio];
54
const char compat[] = "arm,pl061\0arm,primecell";
55
+ SysBusDevice *s;
56
57
- pl061_dev = sysbus_create_simple("pl061", base,
58
- qdev_get_gpio_in(vms->gic, irq));
59
+ pl061_dev = qdev_new("pl061");
60
+ s = SYS_BUS_DEVICE(pl061_dev);
61
+ sysbus_realize_and_unref(s, &error_fatal);
62
+ memory_region_add_subregion(mem, base, sysbus_mmio_get_region(s, 0));
63
+ sysbus_connect_irq(s, 0, qdev_get_gpio_in(vms->gic, irq));
64
65
uint32_t phandle = qemu_fdt_alloc_phandle(vms->fdt);
66
nodename = g_strdup_printf("/pl061@%" PRIx64, base);
67
@@ -XXX,XX +XXX,XX @@ static void create_gpio(const VirtMachineState *vms)
68
qemu_fdt_setprop_string(vms->fdt, nodename, "clock-names", "apb_pclk");
69
qemu_fdt_setprop_cell(vms->fdt, nodename, "phandle", phandle);
70
71
- gpio_key_dev = sysbus_create_simple("gpio-key", -1,
72
- qdev_get_gpio_in(pl061_dev, 3));
73
- qemu_fdt_add_subnode(vms->fdt, "/gpio-keys");
74
- qemu_fdt_setprop_string(vms->fdt, "/gpio-keys", "compatible", "gpio-keys");
75
- qemu_fdt_setprop_cell(vms->fdt, "/gpio-keys", "#size-cells", 0);
76
- qemu_fdt_setprop_cell(vms->fdt, "/gpio-keys", "#address-cells", 1);
77
-
78
- qemu_fdt_add_subnode(vms->fdt, "/gpio-keys/poweroff");
79
- qemu_fdt_setprop_string(vms->fdt, "/gpio-keys/poweroff",
80
- "label", "GPIO Key Poweroff");
81
- qemu_fdt_setprop_cell(vms->fdt, "/gpio-keys/poweroff", "linux,code",
82
- KEY_POWER);
83
- qemu_fdt_setprop_cells(vms->fdt, "/gpio-keys/poweroff",
84
- "gpios", phandle, 3, 0);
85
g_free(nodename);
86
+
87
+ /* Child gpio devices */
88
+ create_gpio_keys(vms, pl061_dev, phandle);
89
}
90
91
static void create_virtio_devices(const VirtMachineState *vms)
92
@@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine)
93
if (has_ged && aarch64 && firmware_loaded && virt_is_acpi_enabled(vms)) {
94
vms->acpi_dev = create_acpi_ged(vms);
95
} else {
96
- create_gpio(vms);
97
+ create_gpio_devices(vms, VIRT_GPIO, sysmem);
98
}
99
100
/* connect powerdown request */
101
--
29
--
102
2.20.1
30
2.20.1
103
31
104
32
diff view generated by jsdifflib
[PULL 43/46] hw/arm/armsse: Use Clock to set system_clock_scale
[PULL 07/24] target/arm: Fix MVE widening/narrowing VLDR/VSTR offset calculation
1
Use the MAINCLK Clock input to set the system_clock_scale variable
1
In do_ldst(), the calculation of the offset needs to be based on the
2
rather than using the mainclk_frq property.
2
size of the memory access, not the size of the elements in the
3
vector. This meant we were getting it wrong for the widening and
4
narrowing variants of the various VLDR and VSTR insns.
3
5
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Message-id: 20210628135835.6690-2-peter.maydell@linaro.org
7
Reviewed-by: Luc Michel <luc@lmichel.fr>
8
Message-id: 20210128114145.20536-23-peter.maydell@linaro.org
9
Message-id: 20210121190622.22000-23-peter.maydell@linaro.org
10
---
9
---
11
hw/arm/armsse.c | 24 +++++++++++++++++++-----
10
target/arm/translate-mve.c | 17 +++++++++--------
12
1 file changed, 19 insertions(+), 5 deletions(-)
11
1 file changed, 9 insertions(+), 8 deletions(-)
13
12
14
diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c
13
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
15
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/arm/armsse.c
15
--- a/target/arm/translate-mve.c
17
+++ b/hw/arm/armsse.c
16
+++ b/target/arm/translate-mve.c
18
@@ -XXX,XX +XXX,XX @@ static void armsse_forward_sec_resp_cfg(ARMSSE *s)
17
@@ -XXX,XX +XXX,XX @@ static bool mve_skip_first_beat(DisasContext *s)
19
qdev_connect_gpio_out(dev_splitter, 2, s->sec_resp_cfg_in);
18
}
20
}
19
}
21
20
22
+static void armsse_mainclk_update(void *opaque)
21
-static bool do_ldst(DisasContext *s, arg_VLDR_VSTR *a, MVEGenLdStFn *fn)
23
+{
22
+static bool do_ldst(DisasContext *s, arg_VLDR_VSTR *a, MVEGenLdStFn *fn,
24
+ ARMSSE *s = ARM_SSE(opaque);
23
+ unsigned msize)
25
+ /*
26
+ * Set system_clock_scale from our Clock input; this is what
27
+ * controls the tick rate of the CPU SysTick timer.
28
+ */
29
+ system_clock_scale = clock_ticks_to_ns(s->mainclk, 1);
30
+}
31
+
32
static void armsse_init(Object *obj)
33
{
24
{
34
ARMSSE *s = ARM_SSE(obj);
25
TCGv_i32 addr;
35
@@ -XXX,XX +XXX,XX @@ static void armsse_init(Object *obj)
26
uint32_t offset;
36
assert(info->sram_banks <= MAX_SRAM_BANKS);
27
@@ -XXX,XX +XXX,XX @@ static bool do_ldst(DisasContext *s, arg_VLDR_VSTR *a, MVEGenLdStFn *fn)
37
assert(info->num_cpus <= SSE_MAX_CPUS);
28
return true;
38
39
- s->mainclk = qdev_init_clock_in(DEVICE(s), "MAINCLK", NULL, NULL);
40
+ s->mainclk = qdev_init_clock_in(DEVICE(s), "MAINCLK",
41
+ armsse_mainclk_update, s);
42
s->s32kclk = qdev_init_clock_in(DEVICE(s), "S32KCLK", NULL, NULL);
43
44
memory_region_init(&s->container, obj, "armsse-container", UINT64_MAX);
45
@@ -XXX,XX +XXX,XX @@ static void armsse_realize(DeviceState *dev, Error **errp)
46
return;
47
}
29
}
48
30
49
- if (!s->mainclk_frq) {
31
- offset = a->imm << a->size;
50
- error_setg(errp, "MAINCLK_FRQ property was not set");
32
+ offset = a->imm << msize;
51
- return;
33
if (!a->a) {
52
+ if (!clock_has_source(s->mainclk)) {
34
offset = -offset;
53
+ error_setg(errp, "MAINCLK clock was not connected");
54
+ }
55
+ if (!clock_has_source(s->s32kclk)) {
56
+ error_setg(errp, "S32KCLK clock was not connected");
57
}
35
}
58
36
@@ -XXX,XX +XXX,XX @@ static bool trans_VLDR_VSTR(DisasContext *s, arg_VLDR_VSTR *a)
59
assert(info->num_cpus <= SSE_MAX_CPUS);
37
{ gen_helper_mve_vstrw, gen_helper_mve_vldrw },
60
@@ -XXX,XX +XXX,XX @@ static void armsse_realize(DeviceState *dev, Error **errp)
38
{ NULL, NULL }
61
*/
39
};
62
sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->container);
40
- return do_ldst(s, a, ldstfns[a->size][a->l]);
63
41
+ return do_ldst(s, a, ldstfns[a->size][a->l], a->size);
64
- system_clock_scale = NANOSECONDS_PER_SECOND / s->mainclk_frq;
65
+ /* Set initial system_clock_scale from MAINCLK */
66
+ armsse_mainclk_update(s);
67
}
42
}
68
43
69
static void armsse_idau_check(IDAUInterface *ii, uint32_t address,
44
-#define DO_VLDST_WIDE_NARROW(OP, SLD, ULD, ST) \
45
+#define DO_VLDST_WIDE_NARROW(OP, SLD, ULD, ST, MSIZE) \
46
static bool trans_##OP(DisasContext *s, arg_VLDR_VSTR *a) \
47
{ \
48
static MVEGenLdStFn * const ldstfns[2][2] = { \
49
{ gen_helper_mve_##ST, gen_helper_mve_##SLD }, \
50
{ NULL, gen_helper_mve_##ULD }, \
51
}; \
52
- return do_ldst(s, a, ldstfns[a->u][a->l]); \
53
+ return do_ldst(s, a, ldstfns[a->u][a->l], MSIZE); \
54
}
55
56
-DO_VLDST_WIDE_NARROW(VLDSTB_H, vldrb_sh, vldrb_uh, vstrb_h)
57
-DO_VLDST_WIDE_NARROW(VLDSTB_W, vldrb_sw, vldrb_uw, vstrb_w)
58
-DO_VLDST_WIDE_NARROW(VLDSTH_W, vldrh_sw, vldrh_uw, vstrh_w)
59
+DO_VLDST_WIDE_NARROW(VLDSTB_H, vldrb_sh, vldrb_uh, vstrb_h, MO_8)
60
+DO_VLDST_WIDE_NARROW(VLDSTB_W, vldrb_sw, vldrb_uw, vstrb_w, MO_8)
61
+DO_VLDST_WIDE_NARROW(VLDSTH_W, vldrh_sw, vldrh_uw, vstrh_w, MO_16)
62
63
static bool trans_VDUP(DisasContext *s, arg_VDUP *a)
64
{
70
--
65
--
71
2.20.1
66
2.20.1
72
67
73
68
diff view generated by jsdifflib
[PULL 42/46] tests/qtest/cmsdk-apb-watchdog-test: Test clock changes
[PULL 08/24] target/arm: Fix bugs in MVE VRMLALDAVH, VRMLSLDAVH
1
Now that the CMSDK APB watchdog uses its Clock input, it will
1
The initial implementation of the MVE VRMLALDAVH and VRMLSLDAVH
2
correctly respond when the system clock frequency is changed using
2
insns had some bugs:
3
the RCC register on in the Stellaris board system registers. Test
3
* the 32x32 multiply of elements was being done as 32x32->32,
4
that when the RCC register is written it causes the watchdog timer to
4
not 32x32->64
5
change speed.
5
* we were incorrectly maintaining the accumulator in its full
6
72-bit form across all 4 beats of the insn; in the pseudocode
7
it is squashed back into the 64 bits of the RdaHi:RdaLo
8
registers after each beat
6
9
10
In particular, fixing the second of these allows us to recast
11
the implementation to avoid 128-bit arithmetic entirely.
12
13
Since the element size here is always 4, we can also drop the
14
parameterization of ESIZE to make the code a little more readable.
15
16
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
18
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Reviewed-by: Luc Michel <luc@lmichel.fr>
19
Message-id: 20210628135835.6690-3-peter.maydell@linaro.org
10
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
11
Message-id: 20210128114145.20536-22-peter.maydell@linaro.org
12
Message-id: 20210121190622.22000-22-peter.maydell@linaro.org
13
---
20
---
14
tests/qtest/cmsdk-apb-watchdog-test.c | 52 +++++++++++++++++++++++++++
21
target/arm/mve_helper.c | 38 +++++++++++++++++++++-----------------
15
1 file changed, 52 insertions(+)
22
1 file changed, 21 insertions(+), 17 deletions(-)
16
23
17
diff --git a/tests/qtest/cmsdk-apb-watchdog-test.c b/tests/qtest/cmsdk-apb-watchdog-test.c
24
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
18
index XXXXXXX..XXXXXXX 100644
25
index XXXXXXX..XXXXXXX 100644
19
--- a/tests/qtest/cmsdk-apb-watchdog-test.c
26
--- a/target/arm/mve_helper.c
20
+++ b/tests/qtest/cmsdk-apb-watchdog-test.c
27
+++ b/target/arm/mve_helper.c
21
@@ -XXX,XX +XXX,XX @@
28
@@ -XXX,XX +XXX,XX @@
22
*/
29
*/
23
30
24
#include "qemu/osdep.h"
31
#include "qemu/osdep.h"
25
+#include "qemu/bitops.h"
32
-#include "qemu/int128.h"
26
#include "libqtest-single.h"
33
#include "cpu.h"
34
#include "internals.h"
35
#include "vec_internal.h"
36
@@ -XXX,XX +XXX,XX @@ DO_LDAV(vmlsldavsw, 4, int32_t, false, +=, -=)
37
DO_LDAV(vmlsldavxsw, 4, int32_t, true, +=, -=)
27
38
28
/*
39
/*
29
@@ -XXX,XX +XXX,XX @@
40
- * Rounding multiply add long dual accumulate high: we must keep
30
#define WDOGMIS 0x14
41
- * a 72-bit internal accumulator value and return the top 64 bits.
31
#define WDOGLOCK 0xc00
42
+ * Rounding multiply add long dual accumulate high. In the pseudocode
32
43
+ * this is implemented with a 72-bit internal accumulator value of which
33
+#define SSYS_BASE 0x400fe000
44
+ * the top 64 bits are returned. We optimize this to avoid having to
34
+#define RCC 0x60
45
+ * use 128-bit arithmetic -- we can do this because the 74-bit accumulator
35
+#define SYSDIV_SHIFT 23
46
+ * is squashed back into 64-bits after each beat.
36
+#define SYSDIV_LENGTH 4
47
*/
37
+
48
-#define DO_LDAVH(OP, ESIZE, TYPE, XCHG, EVENACC, ODDACC, TO128) \
38
static void test_watchdog(void)
49
+#define DO_LDAVH(OP, TYPE, LTYPE, XCHG, SUB) \
39
{
50
uint64_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vn, \
40
g_assert_cmpuint(readl(WDOG_BASE + WDOGRIS), ==, 0);
51
void *vm, uint64_t a) \
41
@@ -XXX,XX +XXX,XX @@ static void test_watchdog(void)
52
{ \
42
g_assert_cmpuint(readl(WDOG_BASE + WDOGRIS), ==, 0);
53
uint16_t mask = mve_element_mask(env); \
43
}
54
unsigned e; \
44
55
TYPE *n = vn, *m = vm; \
45
+static void test_clock_change(void)
56
- Int128 acc = int128_lshift(TO128(a), 8); \
46
+{
57
- for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \
47
+ uint32_t rcc;
58
+ for (e = 0; e < 16 / 4; e++, mask >>= 4) { \
48
+
59
if (mask & 1) { \
49
+ /*
60
+ LTYPE mul; \
50
+ * Test that writing to the stellaris board's RCC register to
61
if (e & 1) { \
51
+ * change the system clock frequency causes the watchdog
62
- acc = ODDACC(acc, TO128(n[H##ESIZE(e - 1 * XCHG)] * \
52
+ * to change the speed it counts at.
63
- m[H##ESIZE(e)])); \
53
+ */
64
+ mul = (LTYPE)n[H4(e - 1 * XCHG)] * m[H4(e)]; \
54
+ g_assert_cmpuint(readl(WDOG_BASE + WDOGRIS), ==, 0);
65
+ if (SUB) { \
55
+
66
+ mul = -mul; \
56
+ writel(WDOG_BASE + WDOGCONTROL, 1);
67
+ } \
57
+ writel(WDOG_BASE + WDOGLOAD, 1000);
68
} else { \
58
+
69
- acc = EVENACC(acc, TO128(n[H##ESIZE(e + 1 * XCHG)] * \
59
+ /* Step to just past the 500th tick */
70
- m[H##ESIZE(e)])); \
60
+ clock_step(80 * 500 + 1);
71
+ mul = (LTYPE)n[H4(e + 1 * XCHG)] * m[H4(e)]; \
61
+ g_assert_cmpuint(readl(WDOG_BASE + WDOGRIS), ==, 0);
72
} \
62
+ g_assert_cmpuint(readl(WDOG_BASE + WDOGVALUE), ==, 500);
73
- acc = int128_add(acc, int128_make64(1 << 7)); \
63
+
74
+ mul = (mul >> 8) + ((mul >> 7) & 1); \
64
+ /* Rewrite RCC.SYSDIV from 16 to 8, so the clock is now 40ns per tick */
75
+ a += mul; \
65
+ rcc = readl(SSYS_BASE + RCC);
76
} \
66
+ g_assert_cmpuint(extract32(rcc, SYSDIV_SHIFT, SYSDIV_LENGTH), ==, 0xf);
77
} \
67
+ rcc = deposit32(rcc, SYSDIV_SHIFT, SYSDIV_LENGTH, 7);
78
mve_advance_vpt(env); \
68
+ writel(SSYS_BASE + RCC, rcc);
79
- return int128_getlo(int128_rshift(acc, 8)); \
69
+
80
+ return a; \
70
+ /* Just past the 1000th tick: timer should have fired */
81
}
71
+ clock_step(40 * 500);
82
72
+ g_assert_cmpuint(readl(WDOG_BASE + WDOGRIS), ==, 1);
83
-DO_LDAVH(vrmlaldavhsw, 4, int32_t, false, int128_add, int128_add, int128_makes64)
73
+
84
-DO_LDAVH(vrmlaldavhxsw, 4, int32_t, true, int128_add, int128_add, int128_makes64)
74
+ g_assert_cmpuint(readl(WDOG_BASE + WDOGVALUE), ==, 0);
85
+DO_LDAVH(vrmlaldavhsw, int32_t, int64_t, false, false)
75
+
86
+DO_LDAVH(vrmlaldavhxsw, int32_t, int64_t, true, false)
76
+ /* VALUE reloads at following tick */
87
77
+ clock_step(41);
88
-DO_LDAVH(vrmlaldavhuw, 4, uint32_t, false, int128_add, int128_add, int128_make64)
78
+ g_assert_cmpuint(readl(WDOG_BASE + WDOGVALUE), ==, 1000);
89
+DO_LDAVH(vrmlaldavhuw, uint32_t, uint64_t, false, false)
79
+
90
80
+ /* Writing any value to WDOGINTCLR clears the interrupt and reloads */
91
-DO_LDAVH(vrmlsldavhsw, 4, int32_t, false, int128_add, int128_sub, int128_makes64)
81
+ clock_step(40 * 500);
92
-DO_LDAVH(vrmlsldavhxsw, 4, int32_t, true, int128_add, int128_sub, int128_makes64)
82
+ g_assert_cmpuint(readl(WDOG_BASE + WDOGVALUE), ==, 500);
93
+DO_LDAVH(vrmlsldavhsw, int32_t, int64_t, false, true)
83
+ g_assert_cmpuint(readl(WDOG_BASE + WDOGRIS), ==, 1);
94
+DO_LDAVH(vrmlsldavhxsw, int32_t, int64_t, true, true)
84
+ writel(WDOG_BASE + WDOGINTCLR, 0);
95
85
+ g_assert_cmpuint(readl(WDOG_BASE + WDOGVALUE), ==, 1000);
96
/* Vector add across vector */
86
+ g_assert_cmpuint(readl(WDOG_BASE + WDOGRIS), ==, 0);
97
#define DO_VADDV(OP, ESIZE, TYPE) \
87
+}
88
+
89
int main(int argc, char **argv)
90
{
91
int r;
92
@@ -XXX,XX +XXX,XX @@ int main(int argc, char **argv)
93
qtest_start("-machine lm3s811evb");
94
95
qtest_add_func("/cmsdk-apb-watchdog/watchdog", test_watchdog);
96
+ qtest_add_func("/cmsdk-apb-watchdog/watchdog_clock_change",
97
+ test_clock_change);
98
99
r = g_test_run();
100
101
--
98
--
102
2.20.1
99
2.20.1
103
100
104
101
diff view generated by jsdifflib
[PULL 22/46] ptimer: Add new ptimer_set_period_from_clock() function
[PULL 09/24] target/arm: Make asimd_imm_const() public
1
The ptimer API currently provides two methods for setting the period:
1
The function asimd_imm_const() in translate-neon.c is an
2
ptimer_set_period(), which takes a period in nanoseconds, and
2
implementation of the pseudocode AdvSIMDExpandImm(), which we will
3
ptimer_set_freq(), which takes a frequency in Hz. Neither of these
3
also want for MVE. Move the implementation to translate.c, with a
4
lines up nicely with the Clock API, because although both the Clock
4
prototype in translate.h.
5
and the ptimer track the frequency using a representation of whole
6
and fractional nanoseconds, conversion via either period-in-ns or
7
frequency-in-Hz will introduce a rounding error.
8
9
Add a new function ptimer_set_period_from_clock() which takes the
10
Clock object directly to avoid the rounding issues. This includes a
11
facility for the user to specify that there is a frequency divider
12
between the Clock proper and the timer, as some timer devices like
13
the CMSDK APB dualtimer need this.
14
15
To avoid having to drag in clock.h from ptimer.h we add the Clock
16
type to typedefs.h.
17
5
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
Reviewed-by: Luc Michel <luc@lmichel.fr>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
20
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Message-id: 20210628135835.6690-4-peter.maydell@linaro.org
21
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
22
Message-id: 20210128114145.20536-2-peter.maydell@linaro.org
23
Message-id: 20210121190622.22000-2-peter.maydell@linaro.org
24
---
9
---
25
include/hw/ptimer.h | 22 ++++++++++++++++++++++
10
target/arm/translate.h | 16 ++++++++++
26
include/qemu/typedefs.h | 1 +
11
target/arm/translate-neon.c | 63 -------------------------------------
27
hw/core/ptimer.c | 34 ++++++++++++++++++++++++++++++++++
12
target/arm/translate.c | 57 +++++++++++++++++++++++++++++++++
28
3 files changed, 57 insertions(+)
13
3 files changed, 73 insertions(+), 63 deletions(-)
29
14
30
diff --git a/include/hw/ptimer.h b/include/hw/ptimer.h
15
diff --git a/target/arm/translate.h b/target/arm/translate.h
31
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
32
--- a/include/hw/ptimer.h
17
--- a/target/arm/translate.h
33
+++ b/include/hw/ptimer.h
18
+++ b/target/arm/translate.h
34
@@ -XXX,XX +XXX,XX @@ void ptimer_transaction_commit(ptimer_state *s);
19
@@ -XXX,XX +XXX,XX @@ static inline MemOp finalize_memop(DisasContext *s, MemOp opc)
35
*/
20
return opc | s->be_data;
36
void ptimer_set_period(ptimer_state *s, int64_t period);
21
}
37
22
38
+/**
23
+/**
39
+ * ptimer_set_period_from_clock - Set counter increment from a Clock
24
+ * asimd_imm_const: Expand an encoded SIMD constant value
40
+ * @s: ptimer to configure
41
+ * @clk: pointer to Clock object to take period from
42
+ * @divisor: value to scale the clock frequency down by
43
+ *
25
+ *
44
+ * If the ptimer is being driven from a Clock, this is the preferred
26
+ * Expand a SIMD constant value. This is essentially the pseudocode
45
+ * way to tell the ptimer about the period, because it avoids any
27
+ * AdvSIMDExpandImm, except that we also perform the boolean NOT needed for
46
+ * possible rounding errors that might happen if the internal
28
+ * VMVN and VBIC (when cmode < 14 && op == 1).
47
+ * representation of the Clock period was converted to either a period
48
+ * in ns or a frequency in Hz.
49
+ *
29
+ *
50
+ * If the ptimer should run at the same frequency as the clock,
30
+ * The combination cmode == 15 op == 1 is a reserved encoding for AArch32;
51
+ * pass 1 as the @divisor; if the ptimer should run at half the
31
+ * callers must catch this.
52
+ * frequency, pass 2, and so on.
53
+ *
32
+ *
54
+ * This function will assert if it is called outside a
33
+ * cmode = 2,3,4,5,6,7,10,11,12,13 imm=0 was UNPREDICTABLE in v7A but
55
+ * ptimer_transaction_begin/commit block.
34
+ * is either not unpredictable or merely CONSTRAINED UNPREDICTABLE in v8A;
35
+ * we produce an immediate constant value of 0 in these cases.
56
+ */
36
+ */
57
+void ptimer_set_period_from_clock(ptimer_state *s, const Clock *clock,
37
+uint64_t asimd_imm_const(uint32_t imm, int cmode, int op);
58
+ unsigned int divisor);
59
+
38
+
60
/**
39
#endif /* TARGET_ARM_TRANSLATE_H */
61
* ptimer_set_freq - Set counter frequency in Hz
40
diff --git a/target/arm/translate-neon.c b/target/arm/translate-neon.c
62
* @s: ptimer to configure
63
diff --git a/include/qemu/typedefs.h b/include/qemu/typedefs.h
64
index XXXXXXX..XXXXXXX 100644
41
index XXXXXXX..XXXXXXX 100644
65
--- a/include/qemu/typedefs.h
42
--- a/target/arm/translate-neon.c
66
+++ b/include/qemu/typedefs.h
43
+++ b/target/arm/translate-neon.c
67
@@ -XXX,XX +XXX,XX @@ typedef struct BlockDriverState BlockDriverState;
44
@@ -XXX,XX +XXX,XX @@ DO_FP_2SH(VCVT_UH, gen_helper_gvec_vcvt_uh)
68
typedef struct BusClass BusClass;
45
DO_FP_2SH(VCVT_HS, gen_helper_gvec_vcvt_hs)
69
typedef struct BusState BusState;
46
DO_FP_2SH(VCVT_HU, gen_helper_gvec_vcvt_hu)
70
typedef struct Chardev Chardev;
47
71
+typedef struct Clock Clock;
48
-static uint64_t asimd_imm_const(uint32_t imm, int cmode, int op)
72
typedef struct CompatProperty CompatProperty;
49
-{
73
typedef struct CoMutex CoMutex;
50
- /*
74
typedef struct CPUAddressSpace CPUAddressSpace;
51
- * Expand the encoded constant.
75
diff --git a/hw/core/ptimer.c b/hw/core/ptimer.c
52
- * Note that cmode = 2,3,4,5,6,7,10,11,12,13 imm=0 is UNPREDICTABLE.
53
- * We choose to not special-case this and will behave as if a
54
- * valid constant encoding of 0 had been given.
55
- * cmode = 15 op = 1 must UNDEF; we assume decode has handled that.
56
- */
57
- switch (cmode) {
58
- case 0: case 1:
59
- /* no-op */
60
- break;
61
- case 2: case 3:
62
- imm <<= 8;
63
- break;
64
- case 4: case 5:
65
- imm <<= 16;
66
- break;
67
- case 6: case 7:
68
- imm <<= 24;
69
- break;
70
- case 8: case 9:
71
- imm |= imm << 16;
72
- break;
73
- case 10: case 11:
74
- imm = (imm << 8) | (imm << 24);
75
- break;
76
- case 12:
77
- imm = (imm << 8) | 0xff;
78
- break;
79
- case 13:
80
- imm = (imm << 16) | 0xffff;
81
- break;
82
- case 14:
83
- if (op) {
84
- /*
85
- * This is the only case where the top and bottom 32 bits
86
- * of the encoded constant differ.
87
- */
88
- uint64_t imm64 = 0;
89
- int n;
90
-
91
- for (n = 0; n < 8; n++) {
92
- if (imm & (1 << n)) {
93
- imm64 |= (0xffULL << (n * 8));
94
- }
95
- }
96
- return imm64;
97
- }
98
- imm |= (imm << 8) | (imm << 16) | (imm << 24);
99
- break;
100
- case 15:
101
- imm = ((imm & 0x80) << 24) | ((imm & 0x3f) << 19)
102
- | ((imm & 0x40) ? (0x1f << 25) : (1 << 30));
103
- break;
104
- }
105
- if (op) {
106
- imm = ~imm;
107
- }
108
- return dup_const(MO_32, imm);
109
-}
110
-
111
static bool do_1reg_imm(DisasContext *s, arg_1reg_imm *a,
112
GVecGen2iFn *fn)
113
{
114
diff --git a/target/arm/translate.c b/target/arm/translate.c
76
index XXXXXXX..XXXXXXX 100644
115
index XXXXXXX..XXXXXXX 100644
77
--- a/hw/core/ptimer.c
116
--- a/target/arm/translate.c
78
+++ b/hw/core/ptimer.c
117
+++ b/target/arm/translate.c
79
@@ -XXX,XX +XXX,XX @@
118
@@ -XXX,XX +XXX,XX @@ void arm_translate_init(void)
80
#include "sysemu/qtest.h"
119
a64_translate_init();
81
#include "block/aio.h"
82
#include "sysemu/cpus.h"
83
+#include "hw/clock.h"
84
85
#define DELTA_ADJUST 1
86
#define DELTA_NO_ADJUST -1
87
@@ -XXX,XX +XXX,XX @@ void ptimer_set_period(ptimer_state *s, int64_t period)
88
}
89
}
120
}
90
121
91
+/* Set counter increment interval from a Clock */
122
+uint64_t asimd_imm_const(uint32_t imm, int cmode, int op)
92
+void ptimer_set_period_from_clock(ptimer_state *s, const Clock *clk,
93
+ unsigned int divisor)
94
+{
123
+{
95
+ /*
124
+ /* Expand the encoded constant as per AdvSIMDExpandImm pseudocode */
96
+ * The raw clock period is a 64-bit value in units of 2^-32 ns;
125
+ switch (cmode) {
97
+ * put another way it's a 32.32 fixed-point ns value. Our internal
126
+ case 0: case 1:
98
+ * representation of the period is 64.32 fixed point ns, so
127
+ /* no-op */
99
+ * the conversion is simple.
128
+ break;
100
+ */
129
+ case 2: case 3:
101
+ uint64_t raw_period = clock_get(clk);
130
+ imm <<= 8;
102
+ uint64_t period_frac;
131
+ break;
132
+ case 4: case 5:
133
+ imm <<= 16;
134
+ break;
135
+ case 6: case 7:
136
+ imm <<= 24;
137
+ break;
138
+ case 8: case 9:
139
+ imm |= imm << 16;
140
+ break;
141
+ case 10: case 11:
142
+ imm = (imm << 8) | (imm << 24);
143
+ break;
144
+ case 12:
145
+ imm = (imm << 8) | 0xff;
146
+ break;
147
+ case 13:
148
+ imm = (imm << 16) | 0xffff;
149
+ break;
150
+ case 14:
151
+ if (op) {
152
+ /*
153
+ * This is the only case where the top and bottom 32 bits
154
+ * of the encoded constant differ.
155
+ */
156
+ uint64_t imm64 = 0;
157
+ int n;
103
+
158
+
104
+ assert(s->in_transaction);
159
+ for (n = 0; n < 8; n++) {
105
+ s->delta = ptimer_get_count(s);
160
+ if (imm & (1 << n)) {
106
+ s->period = extract64(raw_period, 32, 32);
161
+ imm64 |= (0xffULL << (n * 8));
107
+ period_frac = extract64(raw_period, 0, 32);
162
+ }
108
+ /*
163
+ }
109
+ * divisor specifies a possible frequency divisor between the
164
+ return imm64;
110
+ * clock and the timer, so it is a multiplier on the period.
165
+ }
111
+ * We do the multiply after splitting the raw period out into
166
+ imm |= (imm << 8) | (imm << 16) | (imm << 24);
112
+ * period and frac to avoid having to do a 32*64->96 multiply.
167
+ break;
113
+ */
168
+ case 15:
114
+ s->period *= divisor;
169
+ imm = ((imm & 0x80) << 24) | ((imm & 0x3f) << 19)
115
+ period_frac *= divisor;
170
+ | ((imm & 0x40) ? (0x1f << 25) : (1 << 30));
116
+ s->period += extract64(period_frac, 32, 32);
171
+ break;
117
+ s->period_frac = (uint32_t)period_frac;
118
+
119
+ if (s->enabled) {
120
+ s->need_reload = true;
121
+ }
172
+ }
173
+ if (op) {
174
+ imm = ~imm;
175
+ }
176
+ return dup_const(MO_32, imm);
122
+}
177
+}
123
+
178
+
124
/* Set counter frequency in Hz. */
179
/* Generate a label used for skipping this instruction */
125
void ptimer_set_freq(ptimer_state *s, uint32_t freq)
180
void arm_gen_condlabel(DisasContext *s)
126
{
181
{
127
--
182
--
128
2.20.1
183
2.20.1
129
184
130
185
diff view generated by jsdifflib
[PULL 31/46] hw/arm/armsse: Rename "MAINCLK" property to "MAINCLK_FRQ"
[PULL 10/24] target/arm: Use asimd_imm_const for A64 decode
1
While we transition the ARMSSE code from integer properties
1
The A64 AdvSIMD modified-immediate grouping uses almost the same
2
specifying clock frequencies to Clock objects, we want to have the
2
constant encoding that A32 Neon does; reuse asimd_imm_const() (to
3
device provide both at once. We want the final name of the main
3
which we add the AArch64-specific case for cmode 15 op 1) instead of
4
input Clock to be "MAINCLK", following the hardware name.
4
reimplementing it all.
5
Unfortunately creating an input Clock with a name X creates an
6
under-the-hood QOM property X; for "MAINCLK" this clashes with the
7
existing UINT32 property of that name.
8
9
Rename the UINT32 property to MAINCLK_FRQ so it can coexist with the
10
MAINCLK Clock; once the transition is complete MAINCLK_FRQ will be
11
deleted.
12
13
Commit created with:
14
perl -p -i -e 's/MAINCLK/MAINCLK_FRQ/g' hw/arm/{armsse,mps2-tz,musca}.c include/hw/arm/armsse.h
15
5
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
18
Reviewed-by: Luc Michel <luc@lmichel.fr>
8
Message-id: 20210628135835.6690-5-peter.maydell@linaro.org
19
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
20
Message-id: 20210128114145.20536-11-peter.maydell@linaro.org
21
Message-id: 20210121190622.22000-11-peter.maydell@linaro.org
22
---
9
---
23
include/hw/arm/armsse.h | 2 +-
10
target/arm/translate.h | 3 +-
24
hw/arm/armsse.c | 6 +++---
11
target/arm/translate-a64.c | 86 ++++----------------------------------
25
hw/arm/mps2-tz.c | 2 +-
12
target/arm/translate.c | 17 +++++++-
26
hw/arm/musca.c | 2 +-
13
3 files changed, 24 insertions(+), 82 deletions(-)
27
4 files changed, 6 insertions(+), 6 deletions(-)
28
14
29
diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h
15
diff --git a/target/arm/translate.h b/target/arm/translate.h
30
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
31
--- a/include/hw/arm/armsse.h
17
--- a/target/arm/translate.h
32
+++ b/include/hw/arm/armsse.h
18
+++ b/target/arm/translate.h
33
@@ -XXX,XX +XXX,XX @@
19
@@ -XXX,XX +XXX,XX @@ static inline MemOp finalize_memop(DisasContext *s, MemOp opc)
34
* QEMU interface:
20
* VMVN and VBIC (when cmode < 14 && op == 1).
35
* + QOM property "memory" is a MemoryRegion containing the devices provided
21
*
36
* by the board model.
22
* The combination cmode == 15 op == 1 is a reserved encoding for AArch32;
37
- * + QOM property "MAINCLK" is the frequency of the main system clock
23
- * callers must catch this.
38
+ * + QOM property "MAINCLK_FRQ" is the frequency of the main system clock
24
+ * callers must catch this; we return the 64-bit constant value defined
39
* + QOM property "EXP_NUMIRQ" sets the number of expansion interrupts.
25
+ * for AArch64.
40
* (In hardware, the SSE-200 permits the number of expansion interrupts
26
*
41
* for the two CPUs to be configured separately, but we restrict it to
27
* cmode = 2,3,4,5,6,7,10,11,12,13 imm=0 was UNPREDICTABLE in v7A but
42
diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c
28
* is either not unpredictable or merely CONSTRAINED UNPREDICTABLE in v8A;
29
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
43
index XXXXXXX..XXXXXXX 100644
30
index XXXXXXX..XXXXXXX 100644
44
--- a/hw/arm/armsse.c
31
--- a/target/arm/translate-a64.c
45
+++ b/hw/arm/armsse.c
32
+++ b/target/arm/translate-a64.c
46
@@ -XXX,XX +XXX,XX @@ static Property iotkit_properties[] = {
33
@@ -XXX,XX +XXX,XX @@ static void disas_simd_mod_imm(DisasContext *s, uint32_t insn)
47
DEFINE_PROP_LINK("memory", ARMSSE, board_memory, TYPE_MEMORY_REGION,
34
{
48
MemoryRegion *),
35
int rd = extract32(insn, 0, 5);
49
DEFINE_PROP_UINT32("EXP_NUMIRQ", ARMSSE, exp_numirq, 64),
36
int cmode = extract32(insn, 12, 4);
50
- DEFINE_PROP_UINT32("MAINCLK", ARMSSE, mainclk_frq, 0),
37
- int cmode_3_1 = extract32(cmode, 1, 3);
51
+ DEFINE_PROP_UINT32("MAINCLK_FRQ", ARMSSE, mainclk_frq, 0),
38
- int cmode_0 = extract32(cmode, 0, 1);
52
DEFINE_PROP_UINT32("SRAM_ADDR_WIDTH", ARMSSE, sram_addr_width, 15),
39
int o2 = extract32(insn, 11, 1);
53
DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000),
40
uint64_t abcdefgh = extract32(insn, 5, 5) | (extract32(insn, 16, 3) << 5);
54
DEFINE_PROP_BOOL("CPU0_FPU", ARMSSE, cpu_fpu[0], true),
41
bool is_neg = extract32(insn, 29, 1);
55
@@ -XXX,XX +XXX,XX @@ static Property armsse_properties[] = {
42
@@ -XXX,XX +XXX,XX @@ static void disas_simd_mod_imm(DisasContext *s, uint32_t insn)
56
DEFINE_PROP_LINK("memory", ARMSSE, board_memory, TYPE_MEMORY_REGION,
57
MemoryRegion *),
58
DEFINE_PROP_UINT32("EXP_NUMIRQ", ARMSSE, exp_numirq, 64),
59
- DEFINE_PROP_UINT32("MAINCLK", ARMSSE, mainclk_frq, 0),
60
+ DEFINE_PROP_UINT32("MAINCLK_FRQ", ARMSSE, mainclk_frq, 0),
61
DEFINE_PROP_UINT32("SRAM_ADDR_WIDTH", ARMSSE, sram_addr_width, 15),
62
DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000),
63
DEFINE_PROP_BOOL("CPU0_FPU", ARMSSE, cpu_fpu[0], false),
64
@@ -XXX,XX +XXX,XX @@ static void armsse_realize(DeviceState *dev, Error **errp)
65
}
66
67
if (!s->mainclk_frq) {
68
- error_setg(errp, "MAINCLK property was not set");
69
+ error_setg(errp, "MAINCLK_FRQ property was not set");
70
return;
43
return;
71
}
44
}
72
45
73
diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c
46
- /* See AdvSIMDExpandImm() in ARM ARM */
47
- switch (cmode_3_1) {
48
- case 0: /* Replicate(Zeros(24):imm8, 2) */
49
- case 1: /* Replicate(Zeros(16):imm8:Zeros(8), 2) */
50
- case 2: /* Replicate(Zeros(8):imm8:Zeros(16), 2) */
51
- case 3: /* Replicate(imm8:Zeros(24), 2) */
52
- {
53
- int shift = cmode_3_1 * 8;
54
- imm = bitfield_replicate(abcdefgh << shift, 32);
55
- break;
56
- }
57
- case 4: /* Replicate(Zeros(8):imm8, 4) */
58
- case 5: /* Replicate(imm8:Zeros(8), 4) */
59
- {
60
- int shift = (cmode_3_1 & 0x1) * 8;
61
- imm = bitfield_replicate(abcdefgh << shift, 16);
62
- break;
63
- }
64
- case 6:
65
- if (cmode_0) {
66
- /* Replicate(Zeros(8):imm8:Ones(16), 2) */
67
- imm = (abcdefgh << 16) | 0xffff;
68
- } else {
69
- /* Replicate(Zeros(16):imm8:Ones(8), 2) */
70
- imm = (abcdefgh << 8) | 0xff;
71
- }
72
- imm = bitfield_replicate(imm, 32);
73
- break;
74
- case 7:
75
- if (!cmode_0 && !is_neg) {
76
- imm = bitfield_replicate(abcdefgh, 8);
77
- } else if (!cmode_0 && is_neg) {
78
- int i;
79
- imm = 0;
80
- for (i = 0; i < 8; i++) {
81
- if ((abcdefgh) & (1 << i)) {
82
- imm |= 0xffULL << (i * 8);
83
- }
84
- }
85
- } else if (cmode_0) {
86
- if (is_neg) {
87
- imm = (abcdefgh & 0x3f) << 48;
88
- if (abcdefgh & 0x80) {
89
- imm |= 0x8000000000000000ULL;
90
- }
91
- if (abcdefgh & 0x40) {
92
- imm |= 0x3fc0000000000000ULL;
93
- } else {
94
- imm |= 0x4000000000000000ULL;
95
- }
96
- } else {
97
- if (o2) {
98
- /* FMOV (vector, immediate) - half-precision */
99
- imm = vfp_expand_imm(MO_16, abcdefgh);
100
- /* now duplicate across the lanes */
101
- imm = bitfield_replicate(imm, 16);
102
- } else {
103
- imm = (abcdefgh & 0x3f) << 19;
104
- if (abcdefgh & 0x80) {
105
- imm |= 0x80000000;
106
- }
107
- if (abcdefgh & 0x40) {
108
- imm |= 0x3e000000;
109
- } else {
110
- imm |= 0x40000000;
111
- }
112
- imm |= (imm << 32);
113
- }
114
- }
115
- }
116
- break;
117
- default:
118
- g_assert_not_reached();
119
- }
120
-
121
- if (cmode_3_1 != 7 && is_neg) {
122
- imm = ~imm;
123
+ if (cmode == 15 && o2 && !is_neg) {
124
+ /* FMOV (vector, immediate) - half-precision */
125
+ imm = vfp_expand_imm(MO_16, abcdefgh);
126
+ /* now duplicate across the lanes */
127
+ imm = bitfield_replicate(imm, 16);
128
+ } else {
129
+ imm = asimd_imm_const(abcdefgh, cmode, is_neg);
130
}
131
132
if (!((cmode & 0x9) == 0x1 || (cmode & 0xd) == 0x9)) {
133
diff --git a/target/arm/translate.c b/target/arm/translate.c
74
index XXXXXXX..XXXXXXX 100644
134
index XXXXXXX..XXXXXXX 100644
75
--- a/hw/arm/mps2-tz.c
135
--- a/target/arm/translate.c
76
+++ b/hw/arm/mps2-tz.c
136
+++ b/target/arm/translate.c
77
@@ -XXX,XX +XXX,XX @@ static void mps2tz_common_init(MachineState *machine)
137
@@ -XXX,XX +XXX,XX @@ uint64_t asimd_imm_const(uint32_t imm, int cmode, int op)
78
object_property_set_link(OBJECT(&mms->iotkit), "memory",
138
case 14:
79
OBJECT(system_memory), &error_abort);
139
if (op) {
80
qdev_prop_set_uint32(iotkitdev, "EXP_NUMIRQ", MPS2TZ_NUMIRQ);
140
/*
81
- qdev_prop_set_uint32(iotkitdev, "MAINCLK", SYSCLK_FRQ);
141
- * This is the only case where the top and bottom 32 bits
82
+ qdev_prop_set_uint32(iotkitdev, "MAINCLK_FRQ", SYSCLK_FRQ);
142
- * of the encoded constant differ.
83
sysbus_realize(SYS_BUS_DEVICE(&mms->iotkit), &error_fatal);
143
+ * This and cmode == 15 op == 1 are the only cases where
84
144
+ * the top and bottom 32 bits of the encoded constant differ.
85
/*
145
*/
86
diff --git a/hw/arm/musca.c b/hw/arm/musca.c
146
uint64_t imm64 = 0;
87
index XXXXXXX..XXXXXXX 100644
147
int n;
88
--- a/hw/arm/musca.c
148
@@ -XXX,XX +XXX,XX @@ uint64_t asimd_imm_const(uint32_t imm, int cmode, int op)
89
+++ b/hw/arm/musca.c
149
imm |= (imm << 8) | (imm << 16) | (imm << 24);
90
@@ -XXX,XX +XXX,XX @@ static void musca_init(MachineState *machine)
150
break;
91
qdev_prop_set_uint32(ssedev, "EXP_NUMIRQ", mmc->num_irqs);
151
case 15:
92
qdev_prop_set_uint32(ssedev, "init-svtor", mmc->init_svtor);
152
+ if (op) {
93
qdev_prop_set_uint32(ssedev, "SRAM_ADDR_WIDTH", mmc->sram_addr_width);
153
+ /* Reserved encoding for AArch32; valid for AArch64 */
94
- qdev_prop_set_uint32(ssedev, "MAINCLK", SYSCLK_FRQ);
154
+ uint64_t imm64 = (uint64_t)(imm & 0x3f) << 48;
95
+ qdev_prop_set_uint32(ssedev, "MAINCLK_FRQ", SYSCLK_FRQ);
155
+ if (imm & 0x80) {
96
/*
156
+ imm64 |= 0x8000000000000000ULL;
97
* Musca-A takes the default SSE-200 FPU/DSP settings (ie no for
157
+ }
98
* CPU0 and yes for CPU1); Musca-B1 explicitly enables them for CPU0.
158
+ if (imm & 0x40) {
159
+ imm64 |= 0x3fc0000000000000ULL;
160
+ } else {
161
+ imm64 |= 0x4000000000000000ULL;
162
+ }
163
+ return imm64;
164
+ }
165
imm = ((imm & 0x80) << 24) | ((imm & 0x3f) << 19)
166
| ((imm & 0x40) ? (0x1f << 25) : (1 << 30));
167
break;
99
--
168
--
100
2.20.1
169
2.20.1
101
170
102
171
diff view generated by jsdifflib
[PULL 32/46] hw/arm/armsse: Wire up clocks
[PULL 11/24] target/arm: Use dup_const() instead of bitfield_replicate()
1
Create two input clocks on the ARMSSE devices, one for the normal
1
Use dup_const() instead of bitfield_replicate() in
2
MAINCLK, and one for the 32KHz S32KCLK, and wire these up to the
2
disas_simd_mod_imm().
3
appropriate devices. The old property-based clock frequency setting
4
will remain in place until conversion is complete.
5
3
6
This is a migration compatibility break for machines mps2-an505,
4
(We can't replace the other use of bitfield_replicate() in this file,
7
mps2-an521, musca-a, musca-b1.
5
in logic_imm_decode_wmask(), because that location needs to handle 2
6
and 4 bit elements, which dup_const() cannot.)
8
7
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
11
Reviewed-by: Luc Michel <luc@lmichel.fr>
10
Message-id: 20210628135835.6690-6-peter.maydell@linaro.org
12
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
13
Message-id: 20210128114145.20536-12-peter.maydell@linaro.org
14
Message-id: 20210121190622.22000-12-peter.maydell@linaro.org
15
---
11
---
16
include/hw/arm/armsse.h | 6 ++++++
12
target/arm/translate-a64.c | 2 +-
17
hw/arm/armsse.c | 17 +++++++++++++++--
13
1 file changed, 1 insertion(+), 1 deletion(-)
18
2 files changed, 21 insertions(+), 2 deletions(-)
19
14
20
diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h
15
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
21
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
22
--- a/include/hw/arm/armsse.h
17
--- a/target/arm/translate-a64.c
23
+++ b/include/hw/arm/armsse.h
18
+++ b/target/arm/translate-a64.c
24
@@ -XXX,XX +XXX,XX @@
19
@@ -XXX,XX +XXX,XX @@ static void disas_simd_mod_imm(DisasContext *s, uint32_t insn)
25
* per-CPU identity and control register blocks
20
/* FMOV (vector, immediate) - half-precision */
26
*
21
imm = vfp_expand_imm(MO_16, abcdefgh);
27
* QEMU interface:
22
/* now duplicate across the lanes */
28
+ * + Clock input "MAINCLK": clock for CPUs and most peripherals
23
- imm = bitfield_replicate(imm, 16);
29
+ * + Clock input "S32KCLK": slow 32KHz clock used for a few peripherals
24
+ imm = dup_const(MO_16, imm);
30
* + QOM property "memory" is a MemoryRegion containing the devices provided
25
} else {
31
* by the board model.
26
imm = asimd_imm_const(abcdefgh, cmode, is_neg);
32
* + QOM property "MAINCLK_FRQ" is the frequency of the main system clock
33
@@ -XXX,XX +XXX,XX @@
34
#include "hw/misc/armsse-mhu.h"
35
#include "hw/misc/unimp.h"
36
#include "hw/or-irq.h"
37
+#include "hw/clock.h"
38
#include "hw/core/split-irq.h"
39
#include "hw/cpu/cluster.h"
40
#include "qom/object.h"
41
@@ -XXX,XX +XXX,XX @@ struct ARMSSE {
42
43
uint32_t nsccfg;
44
45
+ Clock *mainclk;
46
+ Clock *s32kclk;
47
+
48
/* Properties */
49
MemoryRegion *board_memory;
50
uint32_t exp_numirq;
51
diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c
52
index XXXXXXX..XXXXXXX 100644
53
--- a/hw/arm/armsse.c
54
+++ b/hw/arm/armsse.c
55
@@ -XXX,XX +XXX,XX @@
56
#include "hw/arm/armsse.h"
57
#include "hw/arm/boot.h"
58
#include "hw/irq.h"
59
+#include "hw/qdev-clock.h"
60
61
/* Format of the System Information block SYS_CONFIG register */
62
typedef enum SysConfigFormat {
63
@@ -XXX,XX +XXX,XX @@ static void armsse_init(Object *obj)
64
assert(info->sram_banks <= MAX_SRAM_BANKS);
65
assert(info->num_cpus <= SSE_MAX_CPUS);
66
67
+ s->mainclk = qdev_init_clock_in(DEVICE(s), "MAINCLK", NULL, NULL);
68
+ s->s32kclk = qdev_init_clock_in(DEVICE(s), "S32KCLK", NULL, NULL);
69
+
70
memory_region_init(&s->container, obj, "armsse-container", UINT64_MAX);
71
72
for (i = 0; i < info->num_cpus; i++) {
73
@@ -XXX,XX +XXX,XX @@ static void armsse_realize(DeviceState *dev, Error **errp)
74
* map its upstream ends to the right place in the container.
75
*/
76
qdev_prop_set_uint32(DEVICE(&s->timer0), "pclk-frq", s->mainclk_frq);
77
+ qdev_connect_clock_in(DEVICE(&s->timer0), "pclk", s->mainclk);
78
if (!sysbus_realize(SYS_BUS_DEVICE(&s->timer0), errp)) {
79
return;
80
}
81
@@ -XXX,XX +XXX,XX @@ static void armsse_realize(DeviceState *dev, Error **errp)
82
&error_abort);
83
84
qdev_prop_set_uint32(DEVICE(&s->timer1), "pclk-frq", s->mainclk_frq);
85
+ qdev_connect_clock_in(DEVICE(&s->timer1), "pclk", s->mainclk);
86
if (!sysbus_realize(SYS_BUS_DEVICE(&s->timer1), errp)) {
87
return;
88
}
89
@@ -XXX,XX +XXX,XX @@ static void armsse_realize(DeviceState *dev, Error **errp)
90
&error_abort);
91
92
qdev_prop_set_uint32(DEVICE(&s->dualtimer), "pclk-frq", s->mainclk_frq);
93
+ qdev_connect_clock_in(DEVICE(&s->dualtimer), "TIMCLK", s->mainclk);
94
if (!sysbus_realize(SYS_BUS_DEVICE(&s->dualtimer), errp)) {
95
return;
96
}
97
@@ -XXX,XX +XXX,XX @@ static void armsse_realize(DeviceState *dev, Error **errp)
98
* 0x4002f000: S32K timer
99
*/
100
qdev_prop_set_uint32(DEVICE(&s->s32ktimer), "pclk-frq", S32KCLK);
101
+ qdev_connect_clock_in(DEVICE(&s->s32ktimer), "pclk", s->s32kclk);
102
if (!sysbus_realize(SYS_BUS_DEVICE(&s->s32ktimer), errp)) {
103
return;
104
}
105
@@ -XXX,XX +XXX,XX @@ static void armsse_realize(DeviceState *dev, Error **errp)
106
qdev_get_gpio_in_named(DEVICE(&s->armv7m), "NMI", 0));
107
108
qdev_prop_set_uint32(DEVICE(&s->s32kwatchdog), "wdogclk-frq", S32KCLK);
109
+ qdev_connect_clock_in(DEVICE(&s->s32kwatchdog), "WDOGCLK", s->s32kclk);
110
if (!sysbus_realize(SYS_BUS_DEVICE(&s->s32kwatchdog), errp)) {
111
return;
112
}
113
@@ -XXX,XX +XXX,XX @@ static void armsse_realize(DeviceState *dev, Error **errp)
114
/* 0x40080000 .. 0x4008ffff : ARMSSE second Base peripheral region */
115
116
qdev_prop_set_uint32(DEVICE(&s->nswatchdog), "wdogclk-frq", s->mainclk_frq);
117
+ qdev_connect_clock_in(DEVICE(&s->nswatchdog), "WDOGCLK", s->mainclk);
118
if (!sysbus_realize(SYS_BUS_DEVICE(&s->nswatchdog), errp)) {
119
return;
120
}
121
@@ -XXX,XX +XXX,XX @@ static void armsse_realize(DeviceState *dev, Error **errp)
122
sysbus_mmio_map(SYS_BUS_DEVICE(&s->nswatchdog), 0, 0x40081000);
123
124
qdev_prop_set_uint32(DEVICE(&s->swatchdog), "wdogclk-frq", s->mainclk_frq);
125
+ qdev_connect_clock_in(DEVICE(&s->swatchdog), "WDOGCLK", s->mainclk);
126
if (!sysbus_realize(SYS_BUS_DEVICE(&s->swatchdog), errp)) {
127
return;
128
}
129
@@ -XXX,XX +XXX,XX @@ static void armsse_idau_check(IDAUInterface *ii, uint32_t address,
130
131
static const VMStateDescription armsse_vmstate = {
132
.name = "iotkit",
133
- .version_id = 1,
134
- .minimum_version_id = 1,
135
+ .version_id = 2,
136
+ .minimum_version_id = 2,
137
.fields = (VMStateField[]) {
138
+ VMSTATE_CLOCK(mainclk, ARMSSE),
139
+ VMSTATE_CLOCK(s32kclk, ARMSSE),
140
VMSTATE_UINT32(nsccfg, ARMSSE),
141
VMSTATE_END_OF_LIST()
142
}
27
}
143
--
28
--
144
2.20.1
29
2.20.1
145
30
146
31
diff view generated by jsdifflib
[PULL 24/46] tests: Add a simple test of the CMSDK APB timer
[PULL 12/24] target/arm: Implement MVE logical immediate insns
1
Add a simple test of the CMSDK APB timer, since we're about to do
1
Implement the MVE logical-immediate insns (VMOV, VMVN,
2
some refactoring of how it is clocked.
2
VORR and VBIC). These have essentially the same encoding
3
as their Neon equivalents, and we implement the decode
4
in the same way.
3
5
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Reviewed-by: Luc Michel <luc@lmichel.fr>
8
Message-id: 20210628135835.6690-7-peter.maydell@linaro.org
7
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Message-id: 20210128114145.20536-4-peter.maydell@linaro.org
9
Message-id: 20210121190622.22000-4-peter.maydell@linaro.org
10
---
9
---
11
tests/qtest/cmsdk-apb-timer-test.c | 75 ++++++++++++++++++++++++++++++
10
target/arm/helper-mve.h | 4 +++
12
MAINTAINERS | 1 +
11
target/arm/mve.decode | 17 +++++++++++++
13
tests/qtest/meson.build | 1 +
12
target/arm/mve_helper.c | 24 ++++++++++++++++++
14
3 files changed, 77 insertions(+)
13
target/arm/translate-mve.c | 50 ++++++++++++++++++++++++++++++++++++++
15
create mode 100644 tests/qtest/cmsdk-apb-timer-test.c
14
4 files changed, 95 insertions(+)
16
15
17
diff --git a/tests/qtest/cmsdk-apb-timer-test.c b/tests/qtest/cmsdk-apb-timer-test.c
16
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
18
new file mode 100644
17
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX
18
--- a/target/arm/helper-mve.h
20
--- /dev/null
19
+++ b/target/arm/helper-mve.h
21
+++ b/tests/qtest/cmsdk-apb-timer-test.c
20
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_vaddvsh, TCG_CALL_NO_WG, i32, env, ptr, i32)
21
DEF_HELPER_FLAGS_3(mve_vaddvuh, TCG_CALL_NO_WG, i32, env, ptr, i32)
22
DEF_HELPER_FLAGS_3(mve_vaddvsw, TCG_CALL_NO_WG, i32, env, ptr, i32)
23
DEF_HELPER_FLAGS_3(mve_vaddvuw, TCG_CALL_NO_WG, i32, env, ptr, i32)
24
+
25
+DEF_HELPER_FLAGS_3(mve_vmovi, TCG_CALL_NO_WG, void, env, ptr, i64)
26
+DEF_HELPER_FLAGS_3(mve_vandi, TCG_CALL_NO_WG, void, env, ptr, i64)
27
+DEF_HELPER_FLAGS_3(mve_vorri, TCG_CALL_NO_WG, void, env, ptr, i64)
28
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
29
index XXXXXXX..XXXXXXX 100644
30
--- a/target/arm/mve.decode
31
+++ b/target/arm/mve.decode
22
@@ -XXX,XX +XXX,XX @@
32
@@ -XXX,XX +XXX,XX @@
33
# VQDMULL has size in bit 28: 0 for 16 bit, 1 for 32 bit
34
%size_28 28:1 !function=plus_1
35
36
+# 1imm format immediate
37
+%imm_28_16_0 28:1 16:3 0:4
38
+
39
&vldr_vstr rn qd imm p a w size l u
40
&1op qd qm size
41
&2op qd qm qn size
42
&2scalar qd qn rm size
43
+&1imm qd imm cmode op
44
45
@vldr_vstr ....... . . . . l:1 rn:4 ... ...... imm:7 &vldr_vstr qd=%qd u=0
46
# Note that both Rn and Qd are 3 bits only (no D bit)
47
@@ -XXX,XX +XXX,XX @@
48
@2op_nosz .... .... .... .... .... .... .... .... &2op qd=%qd qm=%qm qn=%qn size=0
49
@2op_sz28 .... .... .... .... .... .... .... .... &2op qd=%qd qm=%qm qn=%qn \
50
size=%size_28
51
+@1imm .... .... .... .... .... cmode:4 .. op:1 . .... &1imm qd=%qd imm=%imm_28_16_0
52
53
# The _rev suffix indicates that Vn and Vm are reversed. This is
54
# the case for shifts. In the Arm ARM these insns are documented
55
@@ -XXX,XX +XXX,XX @@ VADDV 111 u:1 1110 1111 size:2 01 ... 0 1111 0 0 a:1 0 qm:3 0 rda=%rd
56
# Predicate operations
57
%mask_22_13 22:1 13:3
58
VPST 1111 1110 0 . 11 000 1 ... 0 1111 0100 1101 mask=%mask_22_13
59
+
60
+# Logical immediate operations (1 reg and modified-immediate)
61
+
62
+# The cmode/op bits here decode VORR/VBIC/VMOV/VMVN, but
63
+# not in a way we can conveniently represent in decodetree without
64
+# a lot of repetition:
65
+# VORR: op=0, (cmode & 1) && cmode < 12
66
+# VBIC: op=1, (cmode & 1) && cmode < 12
67
+# VMOV: everything else
68
+# So we have a single decode line and check the cmode/op in the
69
+# trans function.
70
+Vimm_1r 111 . 1111 1 . 00 0 ... ... 0 .... 0 1 . 1 .... @1imm
71
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
72
index XXXXXXX..XXXXXXX 100644
73
--- a/target/arm/mve_helper.c
74
+++ b/target/arm/mve_helper.c
75
@@ -XXX,XX +XXX,XX @@ DO_1OP(vnegw, 4, int32_t, DO_NEG)
76
DO_1OP(vfnegh, 8, uint64_t, DO_FNEGH)
77
DO_1OP(vfnegs, 8, uint64_t, DO_FNEGS)
78
23
+/*
79
+/*
24
+ * QTest testcase for the CMSDK APB timer device
80
+ * 1 operand immediates: Vda is destination and possibly also one source.
25
+ *
81
+ * All these insns work at 64-bit widths.
26
+ * Copyright (c) 2021 Linaro Limited
27
+ *
28
+ * This program is free software; you can redistribute it and/or modify it
29
+ * under the terms of the GNU General Public License as published by the
30
+ * Free Software Foundation; either version 2 of the License, or
31
+ * (at your option) any later version.
32
+ *
33
+ * This program is distributed in the hope that it will be useful, but WITHOUT
34
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
35
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
36
+ * for more details.
37
+ */
82
+ */
83
+#define DO_1OP_IMM(OP, FN) \
84
+ void HELPER(mve_##OP)(CPUARMState *env, void *vda, uint64_t imm) \
85
+ { \
86
+ uint64_t *da = vda; \
87
+ uint16_t mask = mve_element_mask(env); \
88
+ unsigned e; \
89
+ for (e = 0; e < 16 / 8; e++, mask >>= 8) { \
90
+ mergemask(&da[H8(e)], FN(da[H8(e)], imm), mask); \
91
+ } \
92
+ mve_advance_vpt(env); \
93
+ }
38
+
94
+
39
+#include "qemu/osdep.h"
95
+#define DO_MOVI(N, I) (I)
40
+#include "libqtest-single.h"
96
+#define DO_ANDI(N, I) ((N) & (I))
97
+#define DO_ORRI(N, I) ((N) | (I))
41
+
98
+
42
+/* IoTKit/ARMSSE-200 timer0; driven at 25MHz in mps2-an385, so 40ns per tick */
99
+DO_1OP_IMM(vmovi, DO_MOVI)
43
+#define TIMER_BASE 0x40000000
100
+DO_1OP_IMM(vandi, DO_ANDI)
101
+DO_1OP_IMM(vorri, DO_ORRI)
44
+
102
+
45
+#define CTRL 0
103
#define DO_2OP(OP, ESIZE, TYPE, FN) \
46
+#define VALUE 4
104
void HELPER(glue(mve_, OP))(CPUARMState *env, \
47
+#define RELOAD 8
105
void *vd, void *vn, void *vm) \
48
+#define INTSTATUS 0xc
106
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
107
index XXXXXXX..XXXXXXX 100644
108
--- a/target/arm/translate-mve.c
109
+++ b/target/arm/translate-mve.c
110
@@ -XXX,XX +XXX,XX @@ typedef void MVEGenTwoOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr);
111
typedef void MVEGenTwoOpScalarFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32);
112
typedef void MVEGenDualAccOpFn(TCGv_i64, TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i64);
113
typedef void MVEGenVADDVFn(TCGv_i32, TCGv_ptr, TCGv_ptr, TCGv_i32);
114
+typedef void MVEGenOneOpImmFn(TCGv_ptr, TCGv_ptr, TCGv_i64);
115
116
/* Return the offset of a Qn register (same semantics as aa32_vfp_qreg()) */
117
static inline long mve_qreg_offset(unsigned reg)
118
@@ -XXX,XX +XXX,XX @@ static bool trans_VADDV(DisasContext *s, arg_VADDV *a)
119
mve_update_eci(s);
120
return true;
121
}
49
+
122
+
50
+static void test_timer(void)
123
+static bool do_1imm(DisasContext *s, arg_1imm *a, MVEGenOneOpImmFn *fn)
51
+{
124
+{
52
+ g_assert_true(readl(TIMER_BASE + INTSTATUS) == 0);
125
+ TCGv_ptr qd;
126
+ uint64_t imm;
53
+
127
+
54
+ /* Start timer: will fire after 40 * 1000 == 40000 ns */
128
+ if (!dc_isar_feature(aa32_mve, s) ||
55
+ writel(TIMER_BASE + RELOAD, 1000);
129
+ !mve_check_qreg_bank(s, a->qd) ||
56
+ writel(TIMER_BASE + CTRL, 9);
130
+ !fn) {
131
+ return false;
132
+ }
133
+ if (!mve_eci_check(s) || !vfp_access_check(s)) {
134
+ return true;
135
+ }
57
+
136
+
58
+ /* Step to just past the 500th tick and check VALUE */
137
+ imm = asimd_imm_const(a->imm, a->cmode, a->op);
59
+ clock_step(40 * 500 + 1);
60
+ g_assert_cmpuint(readl(TIMER_BASE + INTSTATUS), ==, 0);
61
+ g_assert_cmpuint(readl(TIMER_BASE + VALUE), ==, 500);
62
+
138
+
63
+ /* Just past the 1000th tick: timer should have fired */
139
+ qd = mve_qreg_ptr(a->qd);
64
+ clock_step(40 * 500);
140
+ fn(cpu_env, qd, tcg_constant_i64(imm));
65
+ g_assert_cmpuint(readl(TIMER_BASE + INTSTATUS), ==, 1);
141
+ tcg_temp_free_ptr(qd);
66
+ g_assert_cmpuint(readl(TIMER_BASE + VALUE), ==, 0);
142
+ mve_update_eci(s);
67
+
143
+ return true;
68
+ /* VALUE reloads at the following tick */
69
+ clock_step(40);
70
+ g_assert_cmpuint(readl(TIMER_BASE + VALUE), ==, 1000);
71
+
72
+ /* Check write-1-to-clear behaviour of INTSTATUS */
73
+ writel(TIMER_BASE + INTSTATUS, 0);
74
+ g_assert_cmpuint(readl(TIMER_BASE + INTSTATUS), ==, 1);
75
+ writel(TIMER_BASE + INTSTATUS, 1);
76
+ g_assert_cmpuint(readl(TIMER_BASE + INTSTATUS), ==, 0);
77
+
78
+ /* Turn off the timer */
79
+ writel(TIMER_BASE + CTRL, 0);
80
+}
144
+}
81
+
145
+
82
+int main(int argc, char **argv)
146
+static bool trans_Vimm_1r(DisasContext *s, arg_1imm *a)
83
+{
147
+{
84
+ int r;
148
+ /* Handle decode of cmode/op here between VORR/VBIC/VMOV */
149
+ MVEGenOneOpImmFn *fn;
85
+
150
+
86
+ g_test_init(&argc, &argv, NULL);
151
+ if ((a->cmode & 1) && a->cmode < 12) {
87
+
152
+ if (a->op) {
88
+ qtest_start("-machine mps2-an385");
153
+ /*
89
+
154
+ * For op=1, the immediate will be inverted by asimd_imm_const(),
90
+ qtest_add_func("/cmsdk-apb-timer/timer", test_timer);
155
+ * so the VBIC becomes a logical AND operation.
91
+
156
+ */
92
+ r = g_test_run();
157
+ fn = gen_helper_mve_vandi;
93
+
158
+ } else {
94
+ qtest_end();
159
+ fn = gen_helper_mve_vorri;
95
+
160
+ }
96
+ return r;
161
+ } else {
162
+ /* There is one unallocated cmode/op combination in this space */
163
+ if (a->cmode == 15 && a->op == 1) {
164
+ return false;
165
+ }
166
+ /* asimd_imm_const() sorts out VMVNI vs VMOVI for us */
167
+ fn = gen_helper_mve_vmovi;
168
+ }
169
+ return do_1imm(s, a, fn);
97
+}
170
+}
98
diff --git a/MAINTAINERS b/MAINTAINERS
99
index XXXXXXX..XXXXXXX 100644
100
--- a/MAINTAINERS
101
+++ b/MAINTAINERS
102
@@ -XXX,XX +XXX,XX @@ F: include/hw/rtc/pl031.h
103
F: include/hw/arm/primecell.h
104
F: hw/timer/cmsdk-apb-timer.c
105
F: include/hw/timer/cmsdk-apb-timer.h
106
+F: tests/qtest/cmsdk-apb-timer-test.c
107
F: hw/timer/cmsdk-apb-dualtimer.c
108
F: include/hw/timer/cmsdk-apb-dualtimer.h
109
F: hw/char/cmsdk-apb-uart.c
110
diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
111
index XXXXXXX..XXXXXXX 100644
112
--- a/tests/qtest/meson.build
113
+++ b/tests/qtest/meson.build
114
@@ -XXX,XX +XXX,XX @@ qtests_npcm7xx = \
115
'npcm7xx_timer-test',
116
'npcm7xx_watchdog_timer-test']
117
qtests_arm = \
118
+ (config_all_devices.has_key('CONFIG_CMSDK_APB_TIMER') ? ['cmsdk-apb-timer-test'] : []) + \
119
(config_all_devices.has_key('CONFIG_PFLASH_CFI02') ? ['pflash-cfi02-test'] : []) + \
120
(config_all_devices.has_key('CONFIG_NPCM7XX') ? qtests_npcm7xx : []) + \
121
['arm-cpu-features',
122
--
171
--
123
2.20.1
172
2.20.1
124
173
125
174
diff view generated by jsdifflib
[PULL 26/46] tests: Add a simple test of the CMSDK APB dual timer
[PULL 13/24] target/arm: Implement MVE vector shift left by immediate insns
1
Add a simple test of the CMSDK dual timer, since we're about to do
1
Implement the MVE shift-vector-left-by-immediate insns VSHL, VQSHL
2
some refactoring of how it is clocked.
2
and VQSHLU.
3
4
The size-and-immediate encoding here is the same as Neon, and we
5
handle it the same way neon-dp.decode does.
3
6
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
Message-id: 20210628135835.6690-8-peter.maydell@linaro.org
7
Reviewed-by: Luc Michel <luc@lmichel.fr>
8
Message-id: 20210128114145.20536-6-peter.maydell@linaro.org
9
Message-id: 20210121190622.22000-6-peter.maydell@linaro.org
10
---
10
---
11
tests/qtest/cmsdk-apb-dualtimer-test.c | 130 +++++++++++++++++++++++++
11
target/arm/helper-mve.h | 16 +++++++++++
12
MAINTAINERS | 1 +
12
target/arm/mve.decode | 23 +++++++++++++++
13
tests/qtest/meson.build | 1 +
13
target/arm/mve_helper.c | 57 ++++++++++++++++++++++++++++++++++++++
14
3 files changed, 132 insertions(+)
14
target/arm/translate-mve.c | 51 ++++++++++++++++++++++++++++++++++
15
create mode 100644 tests/qtest/cmsdk-apb-dualtimer-test.c
15
4 files changed, 147 insertions(+)
16
16
17
diff --git a/tests/qtest/cmsdk-apb-dualtimer-test.c b/tests/qtest/cmsdk-apb-dualtimer-test.c
17
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
18
new file mode 100644
18
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX
19
--- a/target/arm/helper-mve.h
20
--- /dev/null
20
+++ b/target/arm/helper-mve.h
21
+++ b/tests/qtest/cmsdk-apb-dualtimer-test.c
21
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_vaddvuw, TCG_CALL_NO_WG, i32, env, ptr, i32)
22
DEF_HELPER_FLAGS_3(mve_vmovi, TCG_CALL_NO_WG, void, env, ptr, i64)
23
DEF_HELPER_FLAGS_3(mve_vandi, TCG_CALL_NO_WG, void, env, ptr, i64)
24
DEF_HELPER_FLAGS_3(mve_vorri, TCG_CALL_NO_WG, void, env, ptr, i64)
25
+
26
+DEF_HELPER_FLAGS_4(mve_vshli_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
27
+DEF_HELPER_FLAGS_4(mve_vshli_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
28
+DEF_HELPER_FLAGS_4(mve_vshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
29
+
30
+DEF_HELPER_FLAGS_4(mve_vqshli_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
31
+DEF_HELPER_FLAGS_4(mve_vqshli_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
32
+DEF_HELPER_FLAGS_4(mve_vqshli_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
33
+
34
+DEF_HELPER_FLAGS_4(mve_vqshli_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
35
+DEF_HELPER_FLAGS_4(mve_vqshli_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
36
+DEF_HELPER_FLAGS_4(mve_vqshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
37
+
38
+DEF_HELPER_FLAGS_4(mve_vqshlui_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
39
+DEF_HELPER_FLAGS_4(mve_vqshlui_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
40
+DEF_HELPER_FLAGS_4(mve_vqshlui_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
41
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
42
index XXXXXXX..XXXXXXX 100644
43
--- a/target/arm/mve.decode
44
+++ b/target/arm/mve.decode
22
@@ -XXX,XX +XXX,XX @@
45
@@ -XXX,XX +XXX,XX @@
23
+/*
46
&2op qd qm qn size
24
+ * QTest testcase for the CMSDK APB dualtimer device
47
&2scalar qd qn rm size
25
+ *
48
&1imm qd imm cmode op
26
+ * Copyright (c) 2021 Linaro Limited
49
+&2shift qd qm shift size
27
+ *
50
28
+ * This program is free software; you can redistribute it and/or modify it
51
@vldr_vstr ....... . . . . l:1 rn:4 ... ...... imm:7 &vldr_vstr qd=%qd u=0
29
+ * under the terms of the GNU General Public License as published by the
52
# Note that both Rn and Qd are 3 bits only (no D bit)
30
+ * Free Software Foundation; either version 2 of the License, or
53
@@ -XXX,XX +XXX,XX @@
31
+ * (at your option) any later version.
54
@2scalar .... .... .. size:2 .... .... .... .... rm:4 &2scalar qd=%qd qn=%qn
32
+ *
55
@2scalar_nosz .... .... .... .... .... .... .... rm:4 &2scalar qd=%qd qn=%qn
33
+ * This program is distributed in the hope that it will be useful, but WITHOUT
56
34
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
57
+@2_shl_b .... .... .. 001 shift:3 .... .... .... .... &2shift qd=%qd qm=%qm size=0
35
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
58
+@2_shl_h .... .... .. 01 shift:4 .... .... .... .... &2shift qd=%qd qm=%qm size=1
36
+ * for more details.
59
+@2_shl_w .... .... .. 1 shift:5 .... .... .... .... &2shift qd=%qd qm=%qm size=2
37
+ */
60
+
38
+
61
# Vector loads and stores
39
+#include "qemu/osdep.h"
62
40
+#include "libqtest-single.h"
63
# Widening loads and narrowing stores:
41
+
64
@@ -XXX,XX +XXX,XX @@ VPST 1111 1110 0 . 11 000 1 ... 0 1111 0100 1101 mask=%mask_22_13
42
+/* IoTKit/ARMSSE dualtimer; driven at 25MHz in mps2-an385, so 40ns per tick */
65
# So we have a single decode line and check the cmode/op in the
43
+#define TIMER_BASE 0x40002000
66
# trans function.
44
+
67
Vimm_1r 111 . 1111 1 . 00 0 ... ... 0 .... 0 1 . 1 .... @1imm
45
+#define TIMER1LOAD 0
68
+
46
+#define TIMER1VALUE 4
69
+# Shifts by immediate
47
+#define TIMER1CONTROL 8
70
+
48
+#define TIMER1INTCLR 0xc
71
+VSHLI 111 0 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_b
49
+#define TIMER1RIS 0x10
72
+VSHLI 111 0 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_h
50
+#define TIMER1MIS 0x14
73
+VSHLI 111 0 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_w
51
+#define TIMER1BGLOAD 0x18
74
+
52
+
75
+VQSHLI_S 111 0 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_b
53
+#define TIMER2LOAD 0x20
76
+VQSHLI_S 111 0 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_h
54
+#define TIMER2VALUE 0x24
77
+VQSHLI_S 111 0 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_w
55
+#define TIMER2CONTROL 0x28
78
+
56
+#define TIMER2INTCLR 0x2c
79
+VQSHLI_U 111 1 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_b
57
+#define TIMER2RIS 0x30
80
+VQSHLI_U 111 1 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_h
58
+#define TIMER2MIS 0x34
81
+VQSHLI_U 111 1 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_w
59
+#define TIMER2BGLOAD 0x38
82
+
60
+
83
+VQSHLUI 111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_b
61
+#define CTRL_ENABLE (1 << 7)
84
+VQSHLUI 111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_h
62
+#define CTRL_PERIODIC (1 << 6)
85
+VQSHLUI 111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_w
63
+#define CTRL_INTEN (1 << 5)
86
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
64
+#define CTRL_PRESCALE_1 (0 << 2)
87
index XXXXXXX..XXXXXXX 100644
65
+#define CTRL_PRESCALE_16 (1 << 2)
88
--- a/target/arm/mve_helper.c
66
+#define CTRL_PRESCALE_256 (2 << 2)
89
+++ b/target/arm/mve_helper.c
67
+#define CTRL_32BIT (1 << 1)
90
@@ -XXX,XX +XXX,XX @@ DO_2OP_SAT(vqsubsw, 4, int32_t, DO_SQSUB_W)
68
+#define CTRL_ONESHOT (1 << 0)
91
WRAP_QRSHL_HELPER(do_sqrshl_bhs, N, M, true, satp)
69
+
92
#define DO_UQRSHL_OP(N, M, satp) \
70
+static void test_dualtimer(void)
93
WRAP_QRSHL_HELPER(do_uqrshl_bhs, N, M, true, satp)
94
+#define DO_SUQSHL_OP(N, M, satp) \
95
+ WRAP_QRSHL_HELPER(do_suqrshl_bhs, N, M, false, satp)
96
97
DO_2OP_SAT_S(vqshls, DO_SQSHL_OP)
98
DO_2OP_SAT_U(vqshlu, DO_UQSHL_OP)
99
@@ -XXX,XX +XXX,XX @@ DO_VADDV(vaddvsw, 4, uint32_t)
100
DO_VADDV(vaddvub, 1, uint8_t)
101
DO_VADDV(vaddvuh, 2, uint16_t)
102
DO_VADDV(vaddvuw, 4, uint32_t)
103
+
104
+/* Shifts by immediate */
105
+#define DO_2SHIFT(OP, ESIZE, TYPE, FN) \
106
+ void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \
107
+ void *vm, uint32_t shift) \
108
+ { \
109
+ TYPE *d = vd, *m = vm; \
110
+ uint16_t mask = mve_element_mask(env); \
111
+ unsigned e; \
112
+ for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \
113
+ mergemask(&d[H##ESIZE(e)], \
114
+ FN(m[H##ESIZE(e)], shift), mask); \
115
+ } \
116
+ mve_advance_vpt(env); \
117
+ }
118
+
119
+#define DO_2SHIFT_SAT(OP, ESIZE, TYPE, FN) \
120
+ void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \
121
+ void *vm, uint32_t shift) \
122
+ { \
123
+ TYPE *d = vd, *m = vm; \
124
+ uint16_t mask = mve_element_mask(env); \
125
+ unsigned e; \
126
+ bool qc = false; \
127
+ for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \
128
+ bool sat = false; \
129
+ mergemask(&d[H##ESIZE(e)], \
130
+ FN(m[H##ESIZE(e)], shift, &sat), mask); \
131
+ qc |= sat & mask & 1; \
132
+ } \
133
+ if (qc) { \
134
+ env->vfp.qc[0] = qc; \
135
+ } \
136
+ mve_advance_vpt(env); \
137
+ }
138
+
139
+/* provide unsigned 2-op shift helpers for all sizes */
140
+#define DO_2SHIFT_U(OP, FN) \
141
+ DO_2SHIFT(OP##b, 1, uint8_t, FN) \
142
+ DO_2SHIFT(OP##h, 2, uint16_t, FN) \
143
+ DO_2SHIFT(OP##w, 4, uint32_t, FN)
144
+
145
+#define DO_2SHIFT_SAT_U(OP, FN) \
146
+ DO_2SHIFT_SAT(OP##b, 1, uint8_t, FN) \
147
+ DO_2SHIFT_SAT(OP##h, 2, uint16_t, FN) \
148
+ DO_2SHIFT_SAT(OP##w, 4, uint32_t, FN)
149
+#define DO_2SHIFT_SAT_S(OP, FN) \
150
+ DO_2SHIFT_SAT(OP##b, 1, int8_t, FN) \
151
+ DO_2SHIFT_SAT(OP##h, 2, int16_t, FN) \
152
+ DO_2SHIFT_SAT(OP##w, 4, int32_t, FN)
153
+
154
+DO_2SHIFT_U(vshli_u, DO_VSHLU)
155
+DO_2SHIFT_SAT_U(vqshli_u, DO_UQSHL_OP)
156
+DO_2SHIFT_SAT_S(vqshli_s, DO_SQSHL_OP)
157
+DO_2SHIFT_SAT_S(vqshlui_s, DO_SUQSHL_OP)
158
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
159
index XXXXXXX..XXXXXXX 100644
160
--- a/target/arm/translate-mve.c
161
+++ b/target/arm/translate-mve.c
162
@@ -XXX,XX +XXX,XX @@ typedef void MVEGenLdStFn(TCGv_ptr, TCGv_ptr, TCGv_i32);
163
typedef void MVEGenOneOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr);
164
typedef void MVEGenTwoOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr);
165
typedef void MVEGenTwoOpScalarFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32);
166
+typedef void MVEGenTwoOpShiftFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32);
167
typedef void MVEGenDualAccOpFn(TCGv_i64, TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i64);
168
typedef void MVEGenVADDVFn(TCGv_i32, TCGv_ptr, TCGv_ptr, TCGv_i32);
169
typedef void MVEGenOneOpImmFn(TCGv_ptr, TCGv_ptr, TCGv_i64);
170
@@ -XXX,XX +XXX,XX @@ static bool trans_Vimm_1r(DisasContext *s, arg_1imm *a)
171
}
172
return do_1imm(s, a, fn);
173
}
174
+
175
+static bool do_2shift(DisasContext *s, arg_2shift *a, MVEGenTwoOpShiftFn fn,
176
+ bool negateshift)
71
+{
177
+{
72
+ g_assert_true(readl(TIMER_BASE + TIMER1RIS) == 0);
178
+ TCGv_ptr qd, qm;
73
+
179
+ int shift = a->shift;
74
+ /* Start timer: will fire after 40000 ns */
180
+
75
+ writel(TIMER_BASE + TIMER1LOAD, 1000);
181
+ if (!dc_isar_feature(aa32_mve, s) ||
76
+ /* enable in free-running, wrapping, interrupt mode */
182
+ !mve_check_qreg_bank(s, a->qd | a->qm) ||
77
+ writel(TIMER_BASE + TIMER1CONTROL, CTRL_ENABLE | CTRL_INTEN);
183
+ !fn) {
78
+
184
+ return false;
79
+ /* Step to just past the 500th tick and check VALUE */
185
+ }
80
+ clock_step(500 * 40 + 1);
186
+ if (!mve_eci_check(s) || !vfp_access_check(s)) {
81
+ g_assert_cmpuint(readl(TIMER_BASE + TIMER1RIS), ==, 0);
187
+ return true;
82
+ g_assert_cmpuint(readl(TIMER_BASE + TIMER1VALUE), ==, 500);
188
+ }
83
+
84
+ /* Just past the 1000th tick: timer should have fired */
85
+ clock_step(500 * 40);
86
+ g_assert_cmpuint(readl(TIMER_BASE + TIMER1RIS), ==, 1);
87
+ g_assert_cmpuint(readl(TIMER_BASE + TIMER1VALUE), ==, 0);
88
+
189
+
89
+ /*
190
+ /*
90
+ * We are in free-running wrapping 16-bit mode, so on the following
191
+ * When we handle a right shift insn using a left-shift helper
91
+ * tick VALUE should have wrapped round to 0xffff.
192
+ * which permits a negative shift count to indicate a right-shift,
193
+ * we must negate the shift count.
92
+ */
194
+ */
93
+ clock_step(40);
195
+ if (negateshift) {
94
+ g_assert_cmpuint(readl(TIMER_BASE + TIMER1VALUE), ==, 0xffff);
196
+ shift = -shift;
95
+
197
+ }
96
+ /* Check that any write to INTCLR clears interrupt */
198
+
97
+ writel(TIMER_BASE + TIMER1INTCLR, 1);
199
+ qd = mve_qreg_ptr(a->qd);
98
+ g_assert_cmpuint(readl(TIMER_BASE + TIMER1RIS), ==, 0);
200
+ qm = mve_qreg_ptr(a->qm);
99
+
201
+ fn(cpu_env, qd, qm, tcg_constant_i32(shift));
100
+ /* Turn off the timer */
202
+ tcg_temp_free_ptr(qd);
101
+ writel(TIMER_BASE + TIMER1CONTROL, 0);
203
+ tcg_temp_free_ptr(qm);
204
+ mve_update_eci(s);
205
+ return true;
102
+}
206
+}
103
+
207
+
104
+static void test_prescale(void)
208
+#define DO_2SHIFT(INSN, FN, NEGATESHIFT) \
105
+{
209
+ static bool trans_##INSN(DisasContext *s, arg_2shift *a) \
106
+ g_assert_true(readl(TIMER_BASE + TIMER2RIS) == 0);
210
+ { \
107
+
211
+ static MVEGenTwoOpShiftFn * const fns[] = { \
108
+ /* Start timer: will fire after 40 * 256 * 1000 == 1024000 ns */
212
+ gen_helper_mve_##FN##b, \
109
+ writel(TIMER_BASE + TIMER2LOAD, 1000);
213
+ gen_helper_mve_##FN##h, \
110
+ /* enable in periodic, wrapping, interrupt mode, prescale 256 */
214
+ gen_helper_mve_##FN##w, \
111
+ writel(TIMER_BASE + TIMER2CONTROL,
215
+ NULL, \
112
+ CTRL_ENABLE | CTRL_INTEN | CTRL_PERIODIC | CTRL_PRESCALE_256);
216
+ }; \
113
+
217
+ return do_2shift(s, a, fns[a->size], NEGATESHIFT); \
114
+ /* Step to just past the 500th tick and check VALUE */
218
+ }
115
+ clock_step(40 * 256 * 501);
219
+
116
+ g_assert_cmpuint(readl(TIMER_BASE + TIMER2RIS), ==, 0);
220
+DO_2SHIFT(VSHLI, vshli_u, false)
117
+ g_assert_cmpuint(readl(TIMER_BASE + TIMER2VALUE), ==, 500);
221
+DO_2SHIFT(VQSHLI_S, vqshli_s, false)
118
+
222
+DO_2SHIFT(VQSHLI_U, vqshli_u, false)
119
+ /* Just past the 1000th tick: timer should have fired */
223
+DO_2SHIFT(VQSHLUI, vqshlui_s, false)
120
+ clock_step(40 * 256 * 500);
121
+ g_assert_cmpuint(readl(TIMER_BASE + TIMER2RIS), ==, 1);
122
+ g_assert_cmpuint(readl(TIMER_BASE + TIMER2VALUE), ==, 0);
123
+
124
+ /* In periodic mode the tick VALUE now reloads */
125
+ clock_step(40 * 256);
126
+ g_assert_cmpuint(readl(TIMER_BASE + TIMER2VALUE), ==, 1000);
127
+
128
+ /* Check that any write to INTCLR clears interrupt */
129
+ writel(TIMER_BASE + TIMER2INTCLR, 1);
130
+ g_assert_cmpuint(readl(TIMER_BASE + TIMER2RIS), ==, 0);
131
+
132
+ /* Turn off the timer */
133
+ writel(TIMER_BASE + TIMER2CONTROL, 0);
134
+}
135
+
136
+int main(int argc, char **argv)
137
+{
138
+ int r;
139
+
140
+ g_test_init(&argc, &argv, NULL);
141
+
142
+ qtest_start("-machine mps2-an385");
143
+
144
+ qtest_add_func("/cmsdk-apb-dualtimer/dualtimer", test_dualtimer);
145
+ qtest_add_func("/cmsdk-apb-dualtimer/prescale", test_prescale);
146
+
147
+ r = g_test_run();
148
+
149
+ qtest_end();
150
+
151
+ return r;
152
+}
153
diff --git a/MAINTAINERS b/MAINTAINERS
154
index XXXXXXX..XXXXXXX 100644
155
--- a/MAINTAINERS
156
+++ b/MAINTAINERS
157
@@ -XXX,XX +XXX,XX @@ F: include/hw/timer/cmsdk-apb-timer.h
158
F: tests/qtest/cmsdk-apb-timer-test.c
159
F: hw/timer/cmsdk-apb-dualtimer.c
160
F: include/hw/timer/cmsdk-apb-dualtimer.h
161
+F: tests/qtest/cmsdk-apb-dualtimer-test.c
162
F: hw/char/cmsdk-apb-uart.c
163
F: include/hw/char/cmsdk-apb-uart.h
164
F: hw/watchdog/cmsdk-apb-watchdog.c
165
diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
166
index XXXXXXX..XXXXXXX 100644
167
--- a/tests/qtest/meson.build
168
+++ b/tests/qtest/meson.build
169
@@ -XXX,XX +XXX,XX @@ qtests_npcm7xx = \
170
'npcm7xx_timer-test',
171
'npcm7xx_watchdog_timer-test']
172
qtests_arm = \
173
+ (config_all_devices.has_key('CONFIG_CMSDK_APB_DUALTIMER') ? ['cmsdk-apb-dualtimer-test'] : []) + \
174
(config_all_devices.has_key('CONFIG_CMSDK_APB_TIMER') ? ['cmsdk-apb-timer-test'] : []) + \
175
(config_all_devices.has_key('CONFIG_CMSDK_APB_WATCHDOG') ? ['cmsdk-apb-watchdog-test'] : []) + \
176
(config_all_devices.has_key('CONFIG_PFLASH_CFI02') ? ['pflash-cfi02-test'] : []) + \
177
--
224
--
178
2.20.1
225
2.20.1
179
226
180
227
diff view generated by jsdifflib
[PULL 18/46] hw/misc/pvpanic: split-out generic and bus dependent code
[PULL 14/24] target/arm: Implement MVE vector shift right by immediate insns
1
From: Mihai Carabas <mihai.carabas@oracle.com>
1
Implement the MVE vector shift right by immediate insns VSHRI and
2
VRSHRI. As with Neon, we implement these by using helper functions
3
which perform left shifts but allow negative shift counts to indicate
4
right shifts.
2
5
3
To ease the PCI device addition in next patches, split the code as follows:
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
- generic code (read/write/setup) is being kept in pvpanic.c
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
- ISA dependent code moved to pvpanic-isa.c
8
Message-id: 20210628135835.6690-9-peter.maydell@linaro.org
9
---
10
target/arm/helper-mve.h | 12 ++++++++++++
11
target/arm/translate.h | 20 ++++++++++++++++++++
12
target/arm/mve.decode | 28 ++++++++++++++++++++++++++++
13
target/arm/mve_helper.c | 7 +++++++
14
target/arm/translate-mve.c | 5 +++++
15
target/arm/translate-neon.c | 18 ------------------
16
6 files changed, 72 insertions(+), 18 deletions(-)
6
17
7
Also, rename:
18
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
8
- ISA_PVPANIC_DEVICE -> PVPANIC_ISA_DEVICE.
9
- TYPE_PVPANIC -> TYPE_PVPANIC_ISA.
10
- MemoryRegion io -> mr.
11
- pvpanic_ioport_* in pvpanic_*.
12
13
Update the build system with the new files and config structure.
14
15
Signed-off-by: Mihai Carabas <mihai.carabas@oracle.com>
16
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
---
19
include/hw/misc/pvpanic.h | 23 +++++++++-
20
hw/misc/pvpanic-isa.c | 94 +++++++++++++++++++++++++++++++++++++++
21
hw/misc/pvpanic.c | 85 +++--------------------------------
22
hw/i386/Kconfig | 2 +-
23
hw/misc/Kconfig | 6 ++-
24
hw/misc/meson.build | 3 +-
25
tests/qtest/meson.build | 2 +-
26
7 files changed, 130 insertions(+), 85 deletions(-)
27
create mode 100644 hw/misc/pvpanic-isa.c
28
29
diff --git a/include/hw/misc/pvpanic.h b/include/hw/misc/pvpanic.h
30
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
31
--- a/include/hw/misc/pvpanic.h
20
--- a/target/arm/helper-mve.h
32
+++ b/include/hw/misc/pvpanic.h
21
+++ b/target/arm/helper-mve.h
33
@@ -XXX,XX +XXX,XX @@
22
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_vmovi, TCG_CALL_NO_WG, void, env, ptr, i64)
34
23
DEF_HELPER_FLAGS_3(mve_vandi, TCG_CALL_NO_WG, void, env, ptr, i64)
35
#include "qom/object.h"
24
DEF_HELPER_FLAGS_3(mve_vorri, TCG_CALL_NO_WG, void, env, ptr, i64)
36
25
37
-#define TYPE_PVPANIC "pvpanic"
26
+DEF_HELPER_FLAGS_4(mve_vshli_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
38
+#define TYPE_PVPANIC_ISA_DEVICE "pvpanic"
27
+DEF_HELPER_FLAGS_4(mve_vshli_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
39
28
+DEF_HELPER_FLAGS_4(mve_vshli_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
40
#define PVPANIC_IOPORT_PROP "ioport"
41
42
+/* The bit of supported pv event, TODO: include uapi header and remove this */
43
+#define PVPANIC_F_PANICKED 0
44
+#define PVPANIC_F_CRASHLOADED 1
45
+
29
+
46
+/* The pv event value */
30
DEF_HELPER_FLAGS_4(mve_vshli_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
47
+#define PVPANIC_PANICKED (1 << PVPANIC_F_PANICKED)
31
DEF_HELPER_FLAGS_4(mve_vshli_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
48
+#define PVPANIC_CRASHLOADED (1 << PVPANIC_F_CRASHLOADED)
32
DEF_HELPER_FLAGS_4(mve_vshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
33
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vqshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
34
DEF_HELPER_FLAGS_4(mve_vqshlui_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
35
DEF_HELPER_FLAGS_4(mve_vqshlui_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
36
DEF_HELPER_FLAGS_4(mve_vqshlui_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
49
+
37
+
50
+/*
38
+DEF_HELPER_FLAGS_4(mve_vrshli_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
51
+ * PVPanicState for any device type
39
+DEF_HELPER_FLAGS_4(mve_vrshli_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
52
+ */
40
+DEF_HELPER_FLAGS_4(mve_vrshli_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
53
+typedef struct PVPanicState PVPanicState;
54
+struct PVPanicState {
55
+ MemoryRegion mr;
56
+ uint8_t events;
57
+};
58
+
41
+
59
+void pvpanic_setup_io(PVPanicState *s, DeviceState *dev, unsigned size);
42
+DEF_HELPER_FLAGS_4(mve_vrshli_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
60
+
43
+DEF_HELPER_FLAGS_4(mve_vrshli_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
61
static inline uint16_t pvpanic_port(void)
44
+DEF_HELPER_FLAGS_4(mve_vrshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
62
{
45
diff --git a/target/arm/translate.h b/target/arm/translate.h
63
- Object *o = object_resolve_path_type("", TYPE_PVPANIC, NULL);
46
index XXXXXXX..XXXXXXX 100644
64
+ Object *o = object_resolve_path_type("", TYPE_PVPANIC_ISA_DEVICE, NULL);
47
--- a/target/arm/translate.h
65
if (!o) {
48
+++ b/target/arm/translate.h
66
return 0;
49
@@ -XXX,XX +XXX,XX @@ static inline int times_2_plus_1(DisasContext *s, int x)
67
}
50
return x * 2 + 1;
68
diff --git a/hw/misc/pvpanic-isa.c b/hw/misc/pvpanic-isa.c
51
}
69
new file mode 100644
52
70
index XXXXXXX..XXXXXXX
53
+static inline int rsub_64(DisasContext *s, int x)
71
--- /dev/null
72
+++ b/hw/misc/pvpanic-isa.c
73
@@ -XXX,XX +XXX,XX @@
74
+/*
75
+ * QEMU simulated pvpanic device.
76
+ *
77
+ * Copyright Fujitsu, Corp. 2013
78
+ *
79
+ * Authors:
80
+ * Wen Congyang <wency@cn.fujitsu.com>
81
+ * Hu Tao <hutao@cn.fujitsu.com>
82
+ *
83
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
84
+ * See the COPYING file in the top-level directory.
85
+ *
86
+ */
87
+
88
+#include "qemu/osdep.h"
89
+#include "qemu/log.h"
90
+#include "qemu/module.h"
91
+#include "sysemu/runstate.h"
92
+
93
+#include "hw/nvram/fw_cfg.h"
94
+#include "hw/qdev-properties.h"
95
+#include "hw/misc/pvpanic.h"
96
+#include "qom/object.h"
97
+#include "hw/isa/isa.h"
98
+
99
+OBJECT_DECLARE_SIMPLE_TYPE(PVPanicISAState, PVPANIC_ISA_DEVICE)
100
+
101
+/*
102
+ * PVPanicISAState for ISA device and
103
+ * use ioport.
104
+ */
105
+struct PVPanicISAState {
106
+ ISADevice parent_obj;
107
+
108
+ uint16_t ioport;
109
+ PVPanicState pvpanic;
110
+};
111
+
112
+static void pvpanic_isa_initfn(Object *obj)
113
+{
54
+{
114
+ PVPanicISAState *s = PVPANIC_ISA_DEVICE(obj);
55
+ return 64 - x;
115
+
116
+ pvpanic_setup_io(&s->pvpanic, DEVICE(s), 1);
117
+}
56
+}
118
+
57
+
119
+static void pvpanic_isa_realizefn(DeviceState *dev, Error **errp)
58
+static inline int rsub_32(DisasContext *s, int x)
120
+{
59
+{
121
+ ISADevice *d = ISA_DEVICE(dev);
60
+ return 32 - x;
122
+ PVPanicISAState *s = PVPANIC_ISA_DEVICE(dev);
123
+ PVPanicState *ps = &s->pvpanic;
124
+ FWCfgState *fw_cfg = fw_cfg_find();
125
+ uint16_t *pvpanic_port;
126
+
127
+ if (!fw_cfg) {
128
+ return;
129
+ }
130
+
131
+ pvpanic_port = g_malloc(sizeof(*pvpanic_port));
132
+ *pvpanic_port = cpu_to_le16(s->ioport);
133
+ fw_cfg_add_file(fw_cfg, "etc/pvpanic-port", pvpanic_port,
134
+ sizeof(*pvpanic_port));
135
+
136
+ isa_register_ioport(d, &ps->mr, s->ioport);
137
+}
61
+}
138
+
62
+
139
+static Property pvpanic_isa_properties[] = {
63
+static inline int rsub_16(DisasContext *s, int x)
140
+ DEFINE_PROP_UINT16(PVPANIC_IOPORT_PROP, PVPanicISAState, ioport, 0x505),
141
+ DEFINE_PROP_UINT8("events", PVPanicISAState, pvpanic.events, PVPANIC_PANICKED | PVPANIC_CRASHLOADED),
142
+ DEFINE_PROP_END_OF_LIST(),
143
+};
144
+
145
+static void pvpanic_isa_class_init(ObjectClass *klass, void *data)
146
+{
64
+{
147
+ DeviceClass *dc = DEVICE_CLASS(klass);
65
+ return 16 - x;
148
+
149
+ dc->realize = pvpanic_isa_realizefn;
150
+ device_class_set_props(dc, pvpanic_isa_properties);
151
+ set_bit(DEVICE_CATEGORY_MISC, dc->categories);
152
+}
66
+}
153
+
67
+
154
+static TypeInfo pvpanic_isa_info = {
68
+static inline int rsub_8(DisasContext *s, int x)
155
+ .name = TYPE_PVPANIC_ISA_DEVICE,
156
+ .parent = TYPE_ISA_DEVICE,
157
+ .instance_size = sizeof(PVPanicISAState),
158
+ .instance_init = pvpanic_isa_initfn,
159
+ .class_init = pvpanic_isa_class_init,
160
+};
161
+
162
+static void pvpanic_register_types(void)
163
+{
69
+{
164
+ type_register_static(&pvpanic_isa_info);
70
+ return 8 - x;
165
+}
71
+}
166
+
72
+
167
+type_init(pvpanic_register_types)
73
static inline int arm_dc_feature(DisasContext *dc, int feature)
168
diff --git a/hw/misc/pvpanic.c b/hw/misc/pvpanic.c
74
{
75
return (dc->features & (1ULL << feature)) != 0;
76
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
169
index XXXXXXX..XXXXXXX 100644
77
index XXXXXXX..XXXXXXX 100644
170
--- a/hw/misc/pvpanic.c
78
--- a/target/arm/mve.decode
171
+++ b/hw/misc/pvpanic.c
79
+++ b/target/arm/mve.decode
172
@@ -XXX,XX +XXX,XX @@
80
@@ -XXX,XX +XXX,XX @@
173
#include "hw/misc/pvpanic.h"
81
@2_shl_h .... .... .. 01 shift:4 .... .... .... .... &2shift qd=%qd qm=%qm size=1
174
#include "qom/object.h"
82
@2_shl_w .... .... .. 1 shift:5 .... .... .... .... &2shift qd=%qd qm=%qm size=2
175
83
176
-/* The bit of supported pv event, TODO: include uapi header and remove this */
84
+# Right shifts are encoded as N - shift, where N is the element size in bits.
177
-#define PVPANIC_F_PANICKED 0
85
+%rshift_i5 16:5 !function=rsub_32
178
-#define PVPANIC_F_CRASHLOADED 1
86
+%rshift_i4 16:4 !function=rsub_16
179
-
87
+%rshift_i3 16:3 !function=rsub_8
180
-/* The pv event value */
88
+
181
-#define PVPANIC_PANICKED (1 << PVPANIC_F_PANICKED)
89
+@2_shr_b .... .... .. 001 ... .... .... .... .... &2shift qd=%qd qm=%qm \
182
-#define PVPANIC_CRASHLOADED (1 << PVPANIC_F_CRASHLOADED)
90
+ size=0 shift=%rshift_i3
183
-
91
+@2_shr_h .... .... .. 01 .... .... .... .... .... &2shift qd=%qd qm=%qm \
184
-typedef struct PVPanicState PVPanicState;
92
+ size=1 shift=%rshift_i4
185
-DECLARE_INSTANCE_CHECKER(PVPanicState, ISA_PVPANIC_DEVICE,
93
+@2_shr_w .... .... .. 1 ..... .... .... .... .... &2shift qd=%qd qm=%qm \
186
- TYPE_PVPANIC)
94
+ size=2 shift=%rshift_i5
187
-
95
+
188
static void handle_event(int event)
96
# Vector loads and stores
189
{
97
190
static bool logged;
98
# Widening loads and narrowing stores:
191
@@ -XXX,XX +XXX,XX @@ static void handle_event(int event)
99
@@ -XXX,XX +XXX,XX @@ VQSHLI_U 111 1 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_w
192
}
100
VQSHLUI 111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_b
101
VQSHLUI 111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_h
102
VQSHLUI 111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_w
103
+
104
+VSHRI_S 111 0 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_b
105
+VSHRI_S 111 0 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_h
106
+VSHRI_S 111 0 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_w
107
+
108
+VSHRI_U 111 1 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_b
109
+VSHRI_U 111 1 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_h
110
+VSHRI_U 111 1 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_w
111
+
112
+VRSHRI_S 111 0 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_b
113
+VRSHRI_S 111 0 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_h
114
+VRSHRI_S 111 0 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_w
115
+
116
+VRSHRI_U 111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_b
117
+VRSHRI_U 111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_h
118
+VRSHRI_U 111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_w
119
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
120
index XXXXXXX..XXXXXXX 100644
121
--- a/target/arm/mve_helper.c
122
+++ b/target/arm/mve_helper.c
123
@@ -XXX,XX +XXX,XX @@ DO_VADDV(vaddvuw, 4, uint32_t)
124
DO_2SHIFT(OP##b, 1, uint8_t, FN) \
125
DO_2SHIFT(OP##h, 2, uint16_t, FN) \
126
DO_2SHIFT(OP##w, 4, uint32_t, FN)
127
+#define DO_2SHIFT_S(OP, FN) \
128
+ DO_2SHIFT(OP##b, 1, int8_t, FN) \
129
+ DO_2SHIFT(OP##h, 2, int16_t, FN) \
130
+ DO_2SHIFT(OP##w, 4, int32_t, FN)
131
132
#define DO_2SHIFT_SAT_U(OP, FN) \
133
DO_2SHIFT_SAT(OP##b, 1, uint8_t, FN) \
134
@@ -XXX,XX +XXX,XX @@ DO_VADDV(vaddvuw, 4, uint32_t)
135
DO_2SHIFT_SAT(OP##w, 4, int32_t, FN)
136
137
DO_2SHIFT_U(vshli_u, DO_VSHLU)
138
+DO_2SHIFT_S(vshli_s, DO_VSHLS)
139
DO_2SHIFT_SAT_U(vqshli_u, DO_UQSHL_OP)
140
DO_2SHIFT_SAT_S(vqshli_s, DO_SQSHL_OP)
141
DO_2SHIFT_SAT_S(vqshlui_s, DO_SUQSHL_OP)
142
+DO_2SHIFT_U(vrshli_u, DO_VRSHLU)
143
+DO_2SHIFT_S(vrshli_s, DO_VRSHLS)
144
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
145
index XXXXXXX..XXXXXXX 100644
146
--- a/target/arm/translate-mve.c
147
+++ b/target/arm/translate-mve.c
148
@@ -XXX,XX +XXX,XX @@ DO_2SHIFT(VSHLI, vshli_u, false)
149
DO_2SHIFT(VQSHLI_S, vqshli_s, false)
150
DO_2SHIFT(VQSHLI_U, vqshli_u, false)
151
DO_2SHIFT(VQSHLUI, vqshlui_s, false)
152
+/* These right shifts use a left-shift helper with negated shift count */
153
+DO_2SHIFT(VSHRI_S, vshli_s, true)
154
+DO_2SHIFT(VSHRI_U, vshli_u, true)
155
+DO_2SHIFT(VRSHRI_S, vrshli_s, true)
156
+DO_2SHIFT(VRSHRI_U, vrshli_u, true)
157
diff --git a/target/arm/translate-neon.c b/target/arm/translate-neon.c
158
index XXXXXXX..XXXXXXX 100644
159
--- a/target/arm/translate-neon.c
160
+++ b/target/arm/translate-neon.c
161
@@ -XXX,XX +XXX,XX @@ static inline int plus1(DisasContext *s, int x)
162
return x + 1;
193
}
163
}
194
164
195
-#include "hw/isa/isa.h"
165
-static inline int rsub_64(DisasContext *s, int x)
196
-
197
-struct PVPanicState {
198
- ISADevice parent_obj;
199
-
200
- MemoryRegion io;
201
- uint16_t ioport;
202
- uint8_t events;
203
-};
204
-
205
/* return supported events on read */
206
-static uint64_t pvpanic_ioport_read(void *opaque, hwaddr addr, unsigned size)
207
+static uint64_t pvpanic_read(void *opaque, hwaddr addr, unsigned size)
208
{
209
PVPanicState *pvp = opaque;
210
return pvp->events;
211
}
212
213
-static void pvpanic_ioport_write(void *opaque, hwaddr addr, uint64_t val,
214
+static void pvpanic_write(void *opaque, hwaddr addr, uint64_t val,
215
unsigned size)
216
{
217
handle_event(val);
218
}
219
220
static const MemoryRegionOps pvpanic_ops = {
221
- .read = pvpanic_ioport_read,
222
- .write = pvpanic_ioport_write,
223
+ .read = pvpanic_read,
224
+ .write = pvpanic_write,
225
.impl = {
226
.min_access_size = 1,
227
.max_access_size = 1,
228
},
229
};
230
231
-static void pvpanic_isa_initfn(Object *obj)
232
+void pvpanic_setup_io(PVPanicState *s, DeviceState *dev, unsigned size)
233
{
234
- PVPanicState *s = ISA_PVPANIC_DEVICE(obj);
235
-
236
- memory_region_init_io(&s->io, OBJECT(s), &pvpanic_ops, s, "pvpanic", 1);
237
+ memory_region_init_io(&s->mr, OBJECT(dev), &pvpanic_ops, s, "pvpanic", size);
238
}
239
-
240
-static void pvpanic_isa_realizefn(DeviceState *dev, Error **errp)
241
-{
166
-{
242
- ISADevice *d = ISA_DEVICE(dev);
167
- return 64 - x;
243
- PVPanicState *s = ISA_PVPANIC_DEVICE(dev);
244
- FWCfgState *fw_cfg = fw_cfg_find();
245
- uint16_t *pvpanic_port;
246
-
247
- if (!fw_cfg) {
248
- return;
249
- }
250
-
251
- pvpanic_port = g_malloc(sizeof(*pvpanic_port));
252
- *pvpanic_port = cpu_to_le16(s->ioport);
253
- fw_cfg_add_file(fw_cfg, "etc/pvpanic-port", pvpanic_port,
254
- sizeof(*pvpanic_port));
255
-
256
- isa_register_ioport(d, &s->io, s->ioport);
257
-}
168
-}
258
-
169
-
259
-static Property pvpanic_isa_properties[] = {
170
-static inline int rsub_32(DisasContext *s, int x)
260
- DEFINE_PROP_UINT16(PVPANIC_IOPORT_PROP, PVPanicState, ioport, 0x505),
261
- DEFINE_PROP_UINT8("events", PVPanicState, events, PVPANIC_PANICKED | PVPANIC_CRASHLOADED),
262
- DEFINE_PROP_END_OF_LIST(),
263
-};
264
-
265
-static void pvpanic_isa_class_init(ObjectClass *klass, void *data)
266
-{
171
-{
267
- DeviceClass *dc = DEVICE_CLASS(klass);
172
- return 32 - x;
268
-
173
-}
269
- dc->realize = pvpanic_isa_realizefn;
174
-static inline int rsub_16(DisasContext *s, int x)
270
- device_class_set_props(dc, pvpanic_isa_properties);
175
-{
271
- set_bit(DEVICE_CATEGORY_MISC, dc->categories);
176
- return 16 - x;
177
-}
178
-static inline int rsub_8(DisasContext *s, int x)
179
-{
180
- return 8 - x;
272
-}
181
-}
273
-
182
-
274
-static TypeInfo pvpanic_isa_info = {
183
static inline int neon_3same_fp_size(DisasContext *s, int x)
275
- .name = TYPE_PVPANIC,
184
{
276
- .parent = TYPE_ISA_DEVICE,
185
/* Convert 0==fp32, 1==fp16 into a MO_* value */
277
- .instance_size = sizeof(PVPanicState),
278
- .instance_init = pvpanic_isa_initfn,
279
- .class_init = pvpanic_isa_class_init,
280
-};
281
-
282
-static void pvpanic_register_types(void)
283
-{
284
- type_register_static(&pvpanic_isa_info);
285
-}
286
-
287
-type_init(pvpanic_register_types)
288
diff --git a/hw/i386/Kconfig b/hw/i386/Kconfig
289
index XXXXXXX..XXXXXXX 100644
290
--- a/hw/i386/Kconfig
291
+++ b/hw/i386/Kconfig
292
@@ -XXX,XX +XXX,XX @@ config PC
293
imply ISA_DEBUG
294
imply PARALLEL
295
imply PCI_DEVICES
296
- imply PVPANIC
297
+ imply PVPANIC_ISA
298
imply QXL
299
imply SEV
300
imply SGA
301
diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig
302
index XXXXXXX..XXXXXXX 100644
303
--- a/hw/misc/Kconfig
304
+++ b/hw/misc/Kconfig
305
@@ -XXX,XX +XXX,XX @@ config IOTKIT_SYSCTL
306
config IOTKIT_SYSINFO
307
bool
308
309
-config PVPANIC
310
+config PVPANIC_COMMON
311
+ bool
312
+
313
+config PVPANIC_ISA
314
bool
315
depends on ISA_BUS
316
+ select PVPANIC_COMMON
317
318
config AUX
319
bool
320
diff --git a/hw/misc/meson.build b/hw/misc/meson.build
321
index XXXXXXX..XXXXXXX 100644
322
--- a/hw/misc/meson.build
323
+++ b/hw/misc/meson.build
324
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_EMC141X', if_true: files('emc141x.c'))
325
softmmu_ss.add(when: 'CONFIG_UNIMP', if_true: files('unimp.c'))
326
softmmu_ss.add(when: 'CONFIG_EMPTY_SLOT', if_true: files('empty_slot.c'))
327
softmmu_ss.add(when: 'CONFIG_LED', if_true: files('led.c'))
328
+softmmu_ss.add(when: 'CONFIG_PVPANIC_COMMON', if_true: files('pvpanic.c'))
329
330
# ARM devices
331
softmmu_ss.add(when: 'CONFIG_PL310', if_true: files('arm_l2x0.c'))
332
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_IOTKIT_SYSINFO', if_true: files('iotkit-sysinfo.c')
333
softmmu_ss.add(when: 'CONFIG_ARMSSE_CPUID', if_true: files('armsse-cpuid.c'))
334
softmmu_ss.add(when: 'CONFIG_ARMSSE_MHU', if_true: files('armsse-mhu.c'))
335
336
-softmmu_ss.add(when: 'CONFIG_PVPANIC', if_true: files('pvpanic.c'))
337
+softmmu_ss.add(when: 'CONFIG_PVPANIC_ISA', if_true: files('pvpanic-isa.c'))
338
softmmu_ss.add(when: 'CONFIG_AUX', if_true: files('auxbus.c'))
339
softmmu_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files('aspeed_scu.c', 'aspeed_sdmc.c', 'aspeed_xdma.c'))
340
softmmu_ss.add(when: 'CONFIG_MSF2', if_true: files('msf2-sysreg.c'))
341
diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
342
index XXXXXXX..XXXXXXX 100644
343
--- a/tests/qtest/meson.build
344
+++ b/tests/qtest/meson.build
345
@@ -XXX,XX +XXX,XX @@ qtests_i386 = \
346
(config_host.has_key('CONFIG_LINUX') and \
347
config_all_devices.has_key('CONFIG_ISA_IPMI_BT') ? ['ipmi-bt-test'] : []) + \
348
(config_all_devices.has_key('CONFIG_WDT_IB700') ? ['wdt_ib700-test'] : []) + \
349
- (config_all_devices.has_key('CONFIG_PVPANIC') ? ['pvpanic-test'] : []) + \
350
+ (config_all_devices.has_key('CONFIG_PVPANIC_ISA') ? ['pvpanic-test'] : []) + \
351
(config_all_devices.has_key('CONFIG_HDA') ? ['intel-hda-test'] : []) + \
352
(config_all_devices.has_key('CONFIG_I82801B11') ? ['i82801b11-test'] : []) + \
353
(config_all_devices.has_key('CONFIG_IOH3420') ? ['ioh3420-test'] : []) + \
354
--
186
--
355
2.20.1
187
2.20.1
356
188
357
189
diff view generated by jsdifflib
[PULL 37/46] hw/arm/stellaris: Convert SSYS to QOM device
[PULL 15/24] target/arm: Implement MVE VSHLL
1
Convert the SSYS code in the Stellaris boards (which encapsulates the
1
Implement the MVE VHLL (vector shift left long) insn. This has two
2
system registers) to a proper QOM device. This will provide us with
2
encodings: the T1 encoding is the usual shift-by-immediate format,
3
somewhere to put the output Clock whose frequency depends on the
3
and the T2 encoding is a special case where the shift count is always
4
setting of the PLL configuration registers.
4
equal to the element size.
5
6
This is a migration compatibility break for lm3s811evb, lm3s6965evb.
7
8
We use 3-phase reset here because the Clock will need to propagate
9
its value in the hold phase.
10
11
For the moment we reset the device during the board creation so that
12
the system_clock_scale global gets set; this will be removed in a
13
subsequent commit.
14
5
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
Reviewed-by: Luc Michel <luc@lmichel.fr>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
17
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Message-id: 20210628135835.6690-10-peter.maydell@linaro.org
18
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
19
Message-id: 20210128114145.20536-17-peter.maydell@linaro.org
20
Message-id: 20210121190622.22000-17-peter.maydell@linaro.org
21
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
22
---
9
---
23
hw/arm/stellaris.c | 132 ++++++++++++++++++++++++++++++++++++---------
10
target/arm/helper-mve.h | 9 +++++++
24
1 file changed, 107 insertions(+), 25 deletions(-)
11
target/arm/mve.decode | 53 +++++++++++++++++++++++++++++++++++---
12
target/arm/mve_helper.c | 32 +++++++++++++++++++++++
13
target/arm/translate-mve.c | 15 +++++++++++
14
4 files changed, 105 insertions(+), 4 deletions(-)
25
15
26
diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
16
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
27
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
28
--- a/hw/arm/stellaris.c
18
--- a/target/arm/helper-mve.h
29
+++ b/hw/arm/stellaris.c
19
+++ b/target/arm/helper-mve.h
30
@@ -XXX,XX +XXX,XX @@ static void stellaris_gptm_realize(DeviceState *dev, Error **errp)
20
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vrshli_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
31
21
DEF_HELPER_FLAGS_4(mve_vrshli_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
32
/* System controller. */
22
DEF_HELPER_FLAGS_4(mve_vrshli_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
33
23
DEF_HELPER_FLAGS_4(mve_vrshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
34
-typedef struct {
35
+#define TYPE_STELLARIS_SYS "stellaris-sys"
36
+OBJECT_DECLARE_SIMPLE_TYPE(ssys_state, STELLARIS_SYS)
37
+
24
+
38
+struct ssys_state {
25
+DEF_HELPER_FLAGS_4(mve_vshllbsb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
39
+ SysBusDevice parent_obj;
26
+DEF_HELPER_FLAGS_4(mve_vshllbsh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
27
+DEF_HELPER_FLAGS_4(mve_vshllbub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
28
+DEF_HELPER_FLAGS_4(mve_vshllbuh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
29
+DEF_HELPER_FLAGS_4(mve_vshlltsb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
30
+DEF_HELPER_FLAGS_4(mve_vshlltsh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
31
+DEF_HELPER_FLAGS_4(mve_vshlltub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
32
+DEF_HELPER_FLAGS_4(mve_vshlltuh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
33
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
34
index XXXXXXX..XXXXXXX 100644
35
--- a/target/arm/mve.decode
36
+++ b/target/arm/mve.decode
37
@@ -XXX,XX +XXX,XX @@
38
@2_shl_h .... .... .. 01 shift:4 .... .... .... .... &2shift qd=%qd qm=%qm size=1
39
@2_shl_w .... .... .. 1 shift:5 .... .... .... .... &2shift qd=%qd qm=%qm size=2
40
41
+@2_shll_b .... .... ... 01 shift:3 .... .... .... .... &2shift qd=%qd qm=%qm size=0
42
+@2_shll_h .... .... ... 1 shift:4 .... .... .... .... &2shift qd=%qd qm=%qm size=1
43
+# VSHLL encoding T2 where shift == esize
44
+@2_shll_esize_b .... .... .... 00 .. .... .... .... .... &2shift \
45
+ qd=%qd qm=%qm size=0 shift=8
46
+@2_shll_esize_h .... .... .... 01 .. .... .... .... .... &2shift \
47
+ qd=%qd qm=%qm size=1 shift=16
40
+
48
+
41
MemoryRegion iomem;
49
# Right shifts are encoded as N - shift, where N is the element size in bits.
42
uint32_t pborctl;
50
%rshift_i5 16:5 !function=rsub_32
43
uint32_t ldopctl;
51
%rshift_i4 16:4 !function=rsub_16
44
@@ -XXX,XX +XXX,XX @@ typedef struct {
52
@@ -XXX,XX +XXX,XX @@ VADD 1110 1111 0 . .. ... 0 ... 0 1000 . 1 . 0 ... 0 @2op
45
uint32_t dcgc[3];
53
VSUB 1111 1111 0 . .. ... 0 ... 0 1000 . 1 . 0 ... 0 @2op
46
uint32_t clkvclr;
54
VMUL 1110 1111 0 . .. ... 0 ... 0 1001 . 1 . 1 ... 0 @2op
47
uint32_t ldoarst;
55
48
+ qemu_irq irq;
56
-VMULH_S 111 0 1110 0 . .. ...1 ... 0 1110 . 0 . 0 ... 1 @2op
49
+ /* Properties (all read-only registers) */
57
-VMULH_U 111 1 1110 0 . .. ...1 ... 0 1110 . 0 . 0 ... 1 @2op
50
uint32_t user0;
58
+# The VSHLL T2 encoding is not a @2op pattern, but is here because it
51
uint32_t user1;
59
+# overlaps what would be size=0b11 VMULH/VRMULH
52
- qemu_irq irq;
60
+{
53
- stellaris_board_info *board;
61
+ VSHLL_BS 111 0 1110 0 . 11 .. 01 ... 0 1110 0 0 . 0 ... 1 @2_shll_esize_b
54
-} ssys_state;
62
+ VSHLL_BS 111 0 1110 0 . 11 .. 01 ... 0 1110 0 0 . 0 ... 1 @2_shll_esize_h
55
+ uint32_t did0;
63
56
+ uint32_t did1;
64
-VRMULH_S 111 0 1110 0 . .. ...1 ... 1 1110 . 0 . 0 ... 1 @2op
57
+ uint32_t dc0;
65
-VRMULH_U 111 1 1110 0 . .. ...1 ... 1 1110 . 0 . 0 ... 1 @2op
58
+ uint32_t dc1;
66
+ VMULH_S 111 0 1110 0 . .. ...1 ... 0 1110 . 0 . 0 ... 1 @2op
59
+ uint32_t dc2;
60
+ uint32_t dc3;
61
+ uint32_t dc4;
62
+};
63
64
static void ssys_update(ssys_state *s)
65
{
66
@@ -XXX,XX +XXX,XX @@ static uint32_t pllcfg_fury[16] = {
67
68
static int ssys_board_class(const ssys_state *s)
69
{
70
- uint32_t did0 = s->board->did0;
71
+ uint32_t did0 = s->did0;
72
switch (did0 & DID0_VER_MASK) {
73
case DID0_VER_0:
74
return DID0_CLASS_SANDSTORM;
75
@@ -XXX,XX +XXX,XX @@ static uint64_t ssys_read(void *opaque, hwaddr offset,
76
77
switch (offset) {
78
case 0x000: /* DID0 */
79
- return s->board->did0;
80
+ return s->did0;
81
case 0x004: /* DID1 */
82
- return s->board->did1;
83
+ return s->did1;
84
case 0x008: /* DC0 */
85
- return s->board->dc0;
86
+ return s->dc0;
87
case 0x010: /* DC1 */
88
- return s->board->dc1;
89
+ return s->dc1;
90
case 0x014: /* DC2 */
91
- return s->board->dc2;
92
+ return s->dc2;
93
case 0x018: /* DC3 */
94
- return s->board->dc3;
95
+ return s->dc3;
96
case 0x01c: /* DC4 */
97
- return s->board->dc4;
98
+ return s->dc4;
99
case 0x030: /* PBORCTL */
100
return s->pborctl;
101
case 0x034: /* LDOPCTL */
102
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps ssys_ops = {
103
.endianness = DEVICE_NATIVE_ENDIAN,
104
};
105
106
-static void ssys_reset(void *opaque)
107
+static void stellaris_sys_reset_enter(Object *obj, ResetType type)
108
{
109
- ssys_state *s = (ssys_state *)opaque;
110
+ ssys_state *s = STELLARIS_SYS(obj);
111
112
s->pborctl = 0x7ffd;
113
s->rcc = 0x078e3ac0;
114
@@ -XXX,XX +XXX,XX @@ static void ssys_reset(void *opaque)
115
s->rcgc[0] = 1;
116
s->scgc[0] = 1;
117
s->dcgc[0] = 1;
118
+}
67
+}
119
+
68
+
120
+static void stellaris_sys_reset_hold(Object *obj)
121
+{
69
+{
122
+ ssys_state *s = STELLARIS_SYS(obj);
70
+ VSHLL_BU 111 1 1110 0 . 11 .. 01 ... 0 1110 0 0 . 0 ... 1 @2_shll_esize_b
71
+ VSHLL_BU 111 1 1110 0 . 11 .. 01 ... 0 1110 0 0 . 0 ... 1 @2_shll_esize_h
123
+
72
+
124
ssys_calculate_system_clock(s);
73
+ VMULH_U 111 1 1110 0 . .. ...1 ... 0 1110 . 0 . 0 ... 1 @2op
125
}
126
127
+static void stellaris_sys_reset_exit(Object *obj)
128
+{
129
+}
74
+}
130
+
75
+
131
static int stellaris_sys_post_load(void *opaque, int version_id)
76
+{
132
{
77
+ VSHLL_TS 111 0 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_esize_b
133
ssys_state *s = opaque;
78
+ VSHLL_TS 111 0 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_esize_h
134
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_stellaris_sys = {
135
}
136
};
137
138
+static Property stellaris_sys_properties[] = {
139
+ DEFINE_PROP_UINT32("user0", ssys_state, user0, 0),
140
+ DEFINE_PROP_UINT32("user1", ssys_state, user1, 0),
141
+ DEFINE_PROP_UINT32("did0", ssys_state, did0, 0),
142
+ DEFINE_PROP_UINT32("did1", ssys_state, did1, 0),
143
+ DEFINE_PROP_UINT32("dc0", ssys_state, dc0, 0),
144
+ DEFINE_PROP_UINT32("dc1", ssys_state, dc1, 0),
145
+ DEFINE_PROP_UINT32("dc2", ssys_state, dc2, 0),
146
+ DEFINE_PROP_UINT32("dc3", ssys_state, dc3, 0),
147
+ DEFINE_PROP_UINT32("dc4", ssys_state, dc4, 0),
148
+ DEFINE_PROP_END_OF_LIST()
149
+};
150
+
79
+
151
+static void stellaris_sys_instance_init(Object *obj)
80
+ VRMULH_S 111 0 1110 0 . .. ...1 ... 1 1110 . 0 . 0 ... 1 @2op
152
+{
153
+ ssys_state *s = STELLARIS_SYS(obj);
154
+ SysBusDevice *sbd = SYS_BUS_DEVICE(s);
155
+
156
+ memory_region_init_io(&s->iomem, obj, &ssys_ops, s, "ssys", 0x00001000);
157
+ sysbus_init_mmio(sbd, &s->iomem);
158
+ sysbus_init_irq(sbd, &s->irq);
159
+}
81
+}
160
+
82
+
161
static int stellaris_sys_init(uint32_t base, qemu_irq irq,
83
+{
162
stellaris_board_info * board,
84
+ VSHLL_TU 111 1 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_esize_b
163
uint8_t *macaddr)
85
+ VSHLL_TU 111 1 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_esize_h
164
{
165
- ssys_state *s;
166
+ DeviceState *dev = qdev_new(TYPE_STELLARIS_SYS);
167
+ SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
168
169
- s = g_new0(ssys_state, 1);
170
- s->irq = irq;
171
- s->board = board;
172
/* Most devices come preprogrammed with a MAC address in the user data. */
173
- s->user0 = macaddr[0] | (macaddr[1] << 8) | (macaddr[2] << 16);
174
- s->user1 = macaddr[3] | (macaddr[4] << 8) | (macaddr[5] << 16);
175
+ qdev_prop_set_uint32(dev, "user0",
176
+ macaddr[0] | (macaddr[1] << 8) | (macaddr[2] << 16));
177
+ qdev_prop_set_uint32(dev, "user1",
178
+ macaddr[3] | (macaddr[4] << 8) | (macaddr[5] << 16));
179
+ qdev_prop_set_uint32(dev, "did0", board->did0);
180
+ qdev_prop_set_uint32(dev, "did1", board->did1);
181
+ qdev_prop_set_uint32(dev, "dc0", board->dc0);
182
+ qdev_prop_set_uint32(dev, "dc1", board->dc1);
183
+ qdev_prop_set_uint32(dev, "dc2", board->dc2);
184
+ qdev_prop_set_uint32(dev, "dc3", board->dc3);
185
+ qdev_prop_set_uint32(dev, "dc4", board->dc4);
186
+
86
+
187
+ sysbus_realize_and_unref(sbd, &error_fatal);
87
+ VRMULH_U 111 1 1110 0 . .. ...1 ... 1 1110 . 0 . 0 ... 1 @2op
188
+ sysbus_mmio_map(sbd, 0, base);
88
+}
189
+ sysbus_connect_irq(sbd, 0, irq);
89
90
VMAX_S 111 0 1111 0 . .. ... 0 ... 0 0110 . 1 . 0 ... 0 @2op
91
VMAX_U 111 1 1111 0 . .. ... 0 ... 0 0110 . 1 . 0 ... 0 @2op
92
@@ -XXX,XX +XXX,XX @@ VRSHRI_S 111 0 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_w
93
VRSHRI_U 111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_b
94
VRSHRI_U 111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_h
95
VRSHRI_U 111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_w
190
+
96
+
191
+ /*
97
+# VSHLL T1 encoding; the T2 VSHLL encoding is elsewhere in this file
192
+ * Normally we should not be resetting devices like this during
98
+VSHLL_BS 111 0 1110 1 . 1 .. ... ... 0 1111 0 1 . 0 ... 0 @2_shll_b
193
+ * board creation. For the moment we need to do so, because
99
+VSHLL_BS 111 0 1110 1 . 1 .. ... ... 0 1111 0 1 . 0 ... 0 @2_shll_h
194
+ * system_clock_scale will only get set when the STELLARIS_SYS
195
+ * device is reset, and we need its initial value to pass to
196
+ * the watchdog device. This hack can be removed once the
197
+ * watchdog has been converted to use a Clock input instead.
198
+ */
199
+ device_cold_reset(dev);
200
201
- memory_region_init_io(&s->iomem, NULL, &ssys_ops, s, "ssys", 0x00001000);
202
- memory_region_add_subregion(get_system_memory(), base, &s->iomem);
203
- ssys_reset(s);
204
- vmstate_register(NULL, VMSTATE_INSTANCE_ID_ANY, &vmstate_stellaris_sys, s);
205
return 0;
206
}
207
208
-
209
/* I2C controller. */
210
211
#define TYPE_STELLARIS_I2C "stellaris-i2c"
212
@@ -XXX,XX +XXX,XX @@ static const TypeInfo stellaris_adc_info = {
213
.class_init = stellaris_adc_class_init,
214
};
215
216
+static void stellaris_sys_class_init(ObjectClass *klass, void *data)
217
+{
218
+ DeviceClass *dc = DEVICE_CLASS(klass);
219
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
220
+
100
+
221
+ dc->vmsd = &vmstate_stellaris_sys;
101
+VSHLL_BU 111 1 1110 1 . 1 .. ... ... 0 1111 0 1 . 0 ... 0 @2_shll_b
222
+ rc->phases.enter = stellaris_sys_reset_enter;
102
+VSHLL_BU 111 1 1110 1 . 1 .. ... ... 0 1111 0 1 . 0 ... 0 @2_shll_h
223
+ rc->phases.hold = stellaris_sys_reset_hold;
224
+ rc->phases.exit = stellaris_sys_reset_exit;
225
+ device_class_set_props(dc, stellaris_sys_properties);
226
+}
227
+
103
+
228
+static const TypeInfo stellaris_sys_info = {
104
+VSHLL_TS 111 0 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_b
229
+ .name = TYPE_STELLARIS_SYS,
105
+VSHLL_TS 111 0 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_h
230
+ .parent = TYPE_SYS_BUS_DEVICE,
231
+ .instance_size = sizeof(ssys_state),
232
+ .instance_init = stellaris_sys_instance_init,
233
+ .class_init = stellaris_sys_class_init,
234
+};
235
+
106
+
236
static void stellaris_register_types(void)
107
+VSHLL_TU 111 1 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_b
237
{
108
+VSHLL_TU 111 1 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_h
238
type_register_static(&stellaris_i2c_info);
109
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
239
type_register_static(&stellaris_gptm_info);
110
index XXXXXXX..XXXXXXX 100644
240
type_register_static(&stellaris_adc_info);
111
--- a/target/arm/mve_helper.c
241
+ type_register_static(&stellaris_sys_info);
112
+++ b/target/arm/mve_helper.c
242
}
113
@@ -XXX,XX +XXX,XX @@ DO_2SHIFT_SAT_S(vqshli_s, DO_SQSHL_OP)
243
114
DO_2SHIFT_SAT_S(vqshlui_s, DO_SUQSHL_OP)
244
type_init(stellaris_register_types)
115
DO_2SHIFT_U(vrshli_u, DO_VRSHLU)
116
DO_2SHIFT_S(vrshli_s, DO_VRSHLS)
117
+
118
+/*
119
+ * Long shifts taking half-sized inputs from top or bottom of the input
120
+ * vector and producing a double-width result. ESIZE, TYPE are for
121
+ * the input, and LESIZE, LTYPE for the output.
122
+ * Unlike the normal shift helpers, we do not handle negative shift counts,
123
+ * because the long shift is strictly left-only.
124
+ */
125
+#define DO_VSHLL(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE) \
126
+ void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \
127
+ void *vm, uint32_t shift) \
128
+ { \
129
+ LTYPE *d = vd; \
130
+ TYPE *m = vm; \
131
+ uint16_t mask = mve_element_mask(env); \
132
+ unsigned le; \
133
+ assert(shift <= 16); \
134
+ for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \
135
+ LTYPE r = (LTYPE)m[H##ESIZE(le * 2 + TOP)] << shift; \
136
+ mergemask(&d[H##LESIZE(le)], r, mask); \
137
+ } \
138
+ mve_advance_vpt(env); \
139
+ }
140
+
141
+#define DO_VSHLL_ALL(OP, TOP) \
142
+ DO_VSHLL(OP##sb, TOP, 1, int8_t, 2, int16_t) \
143
+ DO_VSHLL(OP##ub, TOP, 1, uint8_t, 2, uint16_t) \
144
+ DO_VSHLL(OP##sh, TOP, 2, int16_t, 4, int32_t) \
145
+ DO_VSHLL(OP##uh, TOP, 2, uint16_t, 4, uint32_t) \
146
+
147
+DO_VSHLL_ALL(vshllb, false)
148
+DO_VSHLL_ALL(vshllt, true)
149
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
150
index XXXXXXX..XXXXXXX 100644
151
--- a/target/arm/translate-mve.c
152
+++ b/target/arm/translate-mve.c
153
@@ -XXX,XX +XXX,XX @@ DO_2SHIFT(VSHRI_S, vshli_s, true)
154
DO_2SHIFT(VSHRI_U, vshli_u, true)
155
DO_2SHIFT(VRSHRI_S, vrshli_s, true)
156
DO_2SHIFT(VRSHRI_U, vrshli_u, true)
157
+
158
+#define DO_VSHLL(INSN, FN) \
159
+ static bool trans_##INSN(DisasContext *s, arg_2shift *a) \
160
+ { \
161
+ static MVEGenTwoOpShiftFn * const fns[] = { \
162
+ gen_helper_mve_##FN##b, \
163
+ gen_helper_mve_##FN##h, \
164
+ }; \
165
+ return do_2shift(s, a, fns[a->size], false); \
166
+ }
167
+
168
+DO_VSHLL(VSHLL_BS, vshllbs)
169
+DO_VSHLL(VSHLL_BU, vshllbu)
170
+DO_VSHLL(VSHLL_TS, vshllts)
171
+DO_VSHLL(VSHLL_TU, vshlltu)
245
--
172
--
246
2.20.1
173
2.20.1
247
174
248
175
diff view generated by jsdifflib
[PULL 46/46] hw/arm/stellaris: Remove board-creation reset of STELLARIS_SYS
[PULL 16/24] target/arm: Implement MVE VSRI, VSLI
1
Now that the watchdog device uses its Clock input rather than being
1
Implement the MVE VSRI and VSLI insns, which perform a
2
passed the value of system_clock_scale at creation time, we can
2
shift-and-insert operation.
3
remove the hack where we reset the STELLARIS_SYS at board creation
4
time to force it to set system_clock_scale. Instead it will be reset
5
at the usual point in startup and will inform the watchdog of the
6
clock frequency at that point.
7
3
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Luc Michel <luc@lmichel.fr>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
6
Message-id: 20210628135835.6690-11-peter.maydell@linaro.org
11
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
12
Message-id: 20210128114145.20536-26-peter.maydell@linaro.org
13
Message-id: 20210121190622.22000-26-peter.maydell@linaro.org
14
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
15
---
7
---
16
hw/arm/stellaris.c | 10 ----------
8
target/arm/helper-mve.h | 8 ++++++++
17
1 file changed, 10 deletions(-)
9
target/arm/mve.decode | 9 ++++++++
10
target/arm/mve_helper.c | 42 ++++++++++++++++++++++++++++++++++++++
11
target/arm/translate-mve.c | 3 +++
12
4 files changed, 62 insertions(+)
18
13
19
diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
14
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
20
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
21
--- a/hw/arm/stellaris.c
16
--- a/target/arm/helper-mve.h
22
+++ b/hw/arm/stellaris.c
17
+++ b/target/arm/helper-mve.h
23
@@ -XXX,XX +XXX,XX @@ static DeviceState *stellaris_sys_init(uint32_t base, qemu_irq irq,
18
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vshlltsb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
24
sysbus_mmio_map(sbd, 0, base);
19
DEF_HELPER_FLAGS_4(mve_vshlltsh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
25
sysbus_connect_irq(sbd, 0, irq);
20
DEF_HELPER_FLAGS_4(mve_vshlltub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
26
21
DEF_HELPER_FLAGS_4(mve_vshlltuh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
27
- /*
22
+
28
- * Normally we should not be resetting devices like this during
23
+DEF_HELPER_FLAGS_4(mve_vsrib, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
29
- * board creation. For the moment we need to do so, because
24
+DEF_HELPER_FLAGS_4(mve_vsrih, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
30
- * system_clock_scale will only get set when the STELLARIS_SYS
25
+DEF_HELPER_FLAGS_4(mve_vsriw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
31
- * device is reset, and we need its initial value to pass to
26
+
32
- * the watchdog device. This hack can be removed once the
27
+DEF_HELPER_FLAGS_4(mve_vslib, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
33
- * watchdog has been converted to use a Clock input instead.
28
+DEF_HELPER_FLAGS_4(mve_vslih, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
34
- */
29
+DEF_HELPER_FLAGS_4(mve_vsliw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
35
- device_cold_reset(dev);
30
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
36
-
31
index XXXXXXX..XXXXXXX 100644
37
return dev;
32
--- a/target/arm/mve.decode
38
}
33
+++ b/target/arm/mve.decode
39
34
@@ -XXX,XX +XXX,XX @@ VSHLL_TS 111 0 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_h
35
36
VSHLL_TU 111 1 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_b
37
VSHLL_TU 111 1 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_h
38
+
39
+# Shift-and-insert
40
+VSRI 111 1 1111 1 . ... ... ... 0 0100 0 1 . 1 ... 0 @2_shr_b
41
+VSRI 111 1 1111 1 . ... ... ... 0 0100 0 1 . 1 ... 0 @2_shr_h
42
+VSRI 111 1 1111 1 . ... ... ... 0 0100 0 1 . 1 ... 0 @2_shr_w
43
+
44
+VSLI 111 1 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_b
45
+VSLI 111 1 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_h
46
+VSLI 111 1 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_w
47
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
48
index XXXXXXX..XXXXXXX 100644
49
--- a/target/arm/mve_helper.c
50
+++ b/target/arm/mve_helper.c
51
@@ -XXX,XX +XXX,XX @@ DO_2SHIFT_SAT_S(vqshlui_s, DO_SUQSHL_OP)
52
DO_2SHIFT_U(vrshli_u, DO_VRSHLU)
53
DO_2SHIFT_S(vrshli_s, DO_VRSHLS)
54
55
+/* Shift-and-insert; we always work with 64 bits at a time */
56
+#define DO_2SHIFT_INSERT(OP, ESIZE, SHIFTFN, MASKFN) \
57
+ void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \
58
+ void *vm, uint32_t shift) \
59
+ { \
60
+ uint64_t *d = vd, *m = vm; \
61
+ uint16_t mask; \
62
+ uint64_t shiftmask; \
63
+ unsigned e; \
64
+ if (shift == 0 || shift == ESIZE * 8) { \
65
+ /* \
66
+ * Only VSLI can shift by 0; only VSRI can shift by <dt>. \
67
+ * The generic logic would give the right answer for 0 but \
68
+ * fails for <dt>. \
69
+ */ \
70
+ goto done; \
71
+ } \
72
+ assert(shift < ESIZE * 8); \
73
+ mask = mve_element_mask(env); \
74
+ /* ESIZE / 2 gives the MO_* value if ESIZE is in [1,2,4] */ \
75
+ shiftmask = dup_const(ESIZE / 2, MASKFN(ESIZE * 8, shift)); \
76
+ for (e = 0; e < 16 / 8; e++, mask >>= 8) { \
77
+ uint64_t r = (SHIFTFN(m[H8(e)], shift) & shiftmask) | \
78
+ (d[H8(e)] & ~shiftmask); \
79
+ mergemask(&d[H8(e)], r, mask); \
80
+ } \
81
+done: \
82
+ mve_advance_vpt(env); \
83
+ }
84
+
85
+#define DO_SHL(N, SHIFT) ((N) << (SHIFT))
86
+#define DO_SHR(N, SHIFT) ((N) >> (SHIFT))
87
+#define SHL_MASK(EBITS, SHIFT) MAKE_64BIT_MASK((SHIFT), (EBITS) - (SHIFT))
88
+#define SHR_MASK(EBITS, SHIFT) MAKE_64BIT_MASK(0, (EBITS) - (SHIFT))
89
+
90
+DO_2SHIFT_INSERT(vsrib, 1, DO_SHR, SHR_MASK)
91
+DO_2SHIFT_INSERT(vsrih, 2, DO_SHR, SHR_MASK)
92
+DO_2SHIFT_INSERT(vsriw, 4, DO_SHR, SHR_MASK)
93
+DO_2SHIFT_INSERT(vslib, 1, DO_SHL, SHL_MASK)
94
+DO_2SHIFT_INSERT(vslih, 2, DO_SHL, SHL_MASK)
95
+DO_2SHIFT_INSERT(vsliw, 4, DO_SHL, SHL_MASK)
96
+
97
/*
98
* Long shifts taking half-sized inputs from top or bottom of the input
99
* vector and producing a double-width result. ESIZE, TYPE are for
100
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
101
index XXXXXXX..XXXXXXX 100644
102
--- a/target/arm/translate-mve.c
103
+++ b/target/arm/translate-mve.c
104
@@ -XXX,XX +XXX,XX @@ DO_2SHIFT(VSHRI_U, vshli_u, true)
105
DO_2SHIFT(VRSHRI_S, vrshli_s, true)
106
DO_2SHIFT(VRSHRI_U, vrshli_u, true)
107
108
+DO_2SHIFT(VSRI, vsri, false)
109
+DO_2SHIFT(VSLI, vsli, false)
110
+
111
#define DO_VSHLL(INSN, FN) \
112
static bool trans_##INSN(DisasContext *s, arg_2shift *a) \
113
{ \
40
--
114
--
41
2.20.1
115
2.20.1
42
116
43
117
diff view generated by jsdifflib
[PULL 25/46] tests: Add a simple test of the CMSDK APB watchdog
[PULL 17/24] target/arm: Implement MVE VSHRN, VRSHRN
1
Add a simple test of the CMSDK watchdog, since we're about to do some
1
Implement the MVE shift-right-and-narrow insn VSHRN and VRSHRN.
2
refactoring of how it is clocked.
2
3
do_urshr() is borrowed from sve_helper.c.
3
4
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Luc Michel <luc@lmichel.fr>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
7
Message-id: 20210628135835.6690-12-peter.maydell@linaro.org
7
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Message-id: 20210128114145.20536-5-peter.maydell@linaro.org
9
Message-id: 20210121190622.22000-5-peter.maydell@linaro.org
10
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
11
---
8
---
12
tests/qtest/cmsdk-apb-watchdog-test.c | 79 +++++++++++++++++++++++++++
9
target/arm/helper-mve.h | 10 ++++++++++
13
MAINTAINERS | 1 +
10
target/arm/mve.decode | 11 +++++++++++
14
tests/qtest/meson.build | 1 +
11
target/arm/mve_helper.c | 40 ++++++++++++++++++++++++++++++++++++++
15
3 files changed, 81 insertions(+)
12
target/arm/translate-mve.c | 15 ++++++++++++++
16
create mode 100644 tests/qtest/cmsdk-apb-watchdog-test.c
13
4 files changed, 76 insertions(+)
17
14
18
diff --git a/tests/qtest/cmsdk-apb-watchdog-test.c b/tests/qtest/cmsdk-apb-watchdog-test.c
15
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
19
new file mode 100644
16
index XXXXXXX..XXXXXXX 100644
20
index XXXXXXX..XXXXXXX
17
--- a/target/arm/helper-mve.h
21
--- /dev/null
18
+++ b/target/arm/helper-mve.h
22
+++ b/tests/qtest/cmsdk-apb-watchdog-test.c
19
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vsriw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
23
@@ -XXX,XX +XXX,XX @@
20
DEF_HELPER_FLAGS_4(mve_vslib, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
24
+/*
21
DEF_HELPER_FLAGS_4(mve_vslih, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
25
+ * QTest testcase for the CMSDK APB watchdog device
22
DEF_HELPER_FLAGS_4(mve_vsliw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
26
+ *
27
+ * Copyright (c) 2021 Linaro Limited
28
+ *
29
+ * This program is free software; you can redistribute it and/or modify it
30
+ * under the terms of the GNU General Public License as published by the
31
+ * Free Software Foundation; either version 2 of the License, or
32
+ * (at your option) any later version.
33
+ *
34
+ * This program is distributed in the hope that it will be useful, but WITHOUT
35
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
36
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
37
+ * for more details.
38
+ */
39
+
23
+
40
+#include "qemu/osdep.h"
24
+DEF_HELPER_FLAGS_4(mve_vshrnbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
41
+#include "libqtest-single.h"
25
+DEF_HELPER_FLAGS_4(mve_vshrnbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
26
+DEF_HELPER_FLAGS_4(mve_vshrntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
27
+DEF_HELPER_FLAGS_4(mve_vshrnth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
28
+
29
+DEF_HELPER_FLAGS_4(mve_vrshrnbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
30
+DEF_HELPER_FLAGS_4(mve_vrshrnbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
31
+DEF_HELPER_FLAGS_4(mve_vrshrntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
32
+DEF_HELPER_FLAGS_4(mve_vrshrnth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
33
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
34
index XXXXXXX..XXXXXXX 100644
35
--- a/target/arm/mve.decode
36
+++ b/target/arm/mve.decode
37
@@ -XXX,XX +XXX,XX @@ VSRI 111 1 1111 1 . ... ... ... 0 0100 0 1 . 1 ... 0 @2_shr_w
38
VSLI 111 1 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_b
39
VSLI 111 1 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_h
40
VSLI 111 1 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_w
41
+
42
+# Narrowing shifts (which only support b and h sizes)
43
+VSHRNB 111 0 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_b
44
+VSHRNB 111 0 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_h
45
+VSHRNT 111 0 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_b
46
+VSHRNT 111 0 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_h
47
+
48
+VRSHRNB 111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_b
49
+VRSHRNB 111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_h
50
+VRSHRNT 111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_b
51
+VRSHRNT 111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_h
52
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
53
index XXXXXXX..XXXXXXX 100644
54
--- a/target/arm/mve_helper.c
55
+++ b/target/arm/mve_helper.c
56
@@ -XXX,XX +XXX,XX @@ DO_2SHIFT_INSERT(vsliw, 4, DO_SHL, SHL_MASK)
57
58
DO_VSHLL_ALL(vshllb, false)
59
DO_VSHLL_ALL(vshllt, true)
42
+
60
+
43
+/*
61
+/*
44
+ * lm3s811evb watchdog; at board startup this runs at 200MHz / 16 == 12.5MHz,
62
+ * Narrowing right shifts, taking a double sized input, shifting it
45
+ * which is 80ns per tick.
63
+ * and putting the result in either the top or bottom half of the output.
64
+ * ESIZE, TYPE are the output, and LESIZE, LTYPE the input.
46
+ */
65
+ */
47
+#define WDOG_BASE 0x40000000
66
+#define DO_VSHRN(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE, FN) \
67
+ void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \
68
+ void *vm, uint32_t shift) \
69
+ { \
70
+ LTYPE *m = vm; \
71
+ TYPE *d = vd; \
72
+ uint16_t mask = mve_element_mask(env); \
73
+ unsigned le; \
74
+ for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \
75
+ TYPE r = FN(m[H##LESIZE(le)], shift); \
76
+ mergemask(&d[H##ESIZE(le * 2 + TOP)], r, mask); \
77
+ } \
78
+ mve_advance_vpt(env); \
79
+ }
48
+
80
+
49
+#define WDOGLOAD 0
81
+#define DO_VSHRN_ALL(OP, FN) \
50
+#define WDOGVALUE 4
82
+ DO_VSHRN(OP##bb, false, 1, uint8_t, 2, uint16_t, FN) \
51
+#define WDOGCONTROL 8
83
+ DO_VSHRN(OP##bh, false, 2, uint16_t, 4, uint32_t, FN) \
52
+#define WDOGINTCLR 0xc
84
+ DO_VSHRN(OP##tb, true, 1, uint8_t, 2, uint16_t, FN) \
53
+#define WDOGRIS 0x10
85
+ DO_VSHRN(OP##th, true, 2, uint16_t, 4, uint32_t, FN)
54
+#define WDOGMIS 0x14
55
+#define WDOGLOCK 0xc00
56
+
86
+
57
+static void test_watchdog(void)
87
+static inline uint64_t do_urshr(uint64_t x, unsigned sh)
58
+{
88
+{
59
+ g_assert_cmpuint(readl(WDOG_BASE + WDOGRIS), ==, 0);
89
+ if (likely(sh < 64)) {
60
+
90
+ return (x >> sh) + ((x >> (sh - 1)) & 1);
61
+ writel(WDOG_BASE + WDOGCONTROL, 1);
91
+ } else if (sh == 64) {
62
+ writel(WDOG_BASE + WDOGLOAD, 1000);
92
+ return x >> 63;
63
+
93
+ } else {
64
+ /* Step to just past the 500th tick */
94
+ return 0;
65
+ clock_step(500 * 80 + 1);
95
+ }
66
+ g_assert_cmpuint(readl(WDOG_BASE + WDOGRIS), ==, 0);
67
+ g_assert_cmpuint(readl(WDOG_BASE + WDOGVALUE), ==, 500);
68
+
69
+ /* Just past the 1000th tick: timer should have fired */
70
+ clock_step(500 * 80);
71
+ g_assert_cmpuint(readl(WDOG_BASE + WDOGRIS), ==, 1);
72
+ g_assert_cmpuint(readl(WDOG_BASE + WDOGVALUE), ==, 0);
73
+
74
+ /* VALUE reloads at following tick */
75
+ clock_step(80);
76
+ g_assert_cmpuint(readl(WDOG_BASE + WDOGVALUE), ==, 1000);
77
+
78
+ /* Writing any value to WDOGINTCLR clears the interrupt and reloads */
79
+ clock_step(500 * 80);
80
+ g_assert_cmpuint(readl(WDOG_BASE + WDOGVALUE), ==, 500);
81
+ g_assert_cmpuint(readl(WDOG_BASE + WDOGRIS), ==, 1);
82
+ writel(WDOG_BASE + WDOGINTCLR, 0);
83
+ g_assert_cmpuint(readl(WDOG_BASE + WDOGVALUE), ==, 1000);
84
+ g_assert_cmpuint(readl(WDOG_BASE + WDOGRIS), ==, 0);
85
+}
96
+}
86
+
97
+
87
+int main(int argc, char **argv)
98
+DO_VSHRN_ALL(vshrn, DO_SHR)
88
+{
99
+DO_VSHRN_ALL(vrshrn, do_urshr)
89
+ int r;
100
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
101
index XXXXXXX..XXXXXXX 100644
102
--- a/target/arm/translate-mve.c
103
+++ b/target/arm/translate-mve.c
104
@@ -XXX,XX +XXX,XX @@ DO_VSHLL(VSHLL_BS, vshllbs)
105
DO_VSHLL(VSHLL_BU, vshllbu)
106
DO_VSHLL(VSHLL_TS, vshllts)
107
DO_VSHLL(VSHLL_TU, vshlltu)
90
+
108
+
91
+ g_test_init(&argc, &argv, NULL);
109
+#define DO_2SHIFT_N(INSN, FN) \
110
+ static bool trans_##INSN(DisasContext *s, arg_2shift *a) \
111
+ { \
112
+ static MVEGenTwoOpShiftFn * const fns[] = { \
113
+ gen_helper_mve_##FN##b, \
114
+ gen_helper_mve_##FN##h, \
115
+ }; \
116
+ return do_2shift(s, a, fns[a->size], false); \
117
+ }
92
+
118
+
93
+ qtest_start("-machine lm3s811evb");
119
+DO_2SHIFT_N(VSHRNB, vshrnb)
94
+
120
+DO_2SHIFT_N(VSHRNT, vshrnt)
95
+ qtest_add_func("/cmsdk-apb-watchdog/watchdog", test_watchdog);
121
+DO_2SHIFT_N(VRSHRNB, vrshrnb)
96
+
122
+DO_2SHIFT_N(VRSHRNT, vrshrnt)
97
+ r = g_test_run();
98
+
99
+ qtest_end();
100
+
101
+ return r;
102
+}
103
diff --git a/MAINTAINERS b/MAINTAINERS
104
index XXXXXXX..XXXXXXX 100644
105
--- a/MAINTAINERS
106
+++ b/MAINTAINERS
107
@@ -XXX,XX +XXX,XX @@ F: hw/char/cmsdk-apb-uart.c
108
F: include/hw/char/cmsdk-apb-uart.h
109
F: hw/watchdog/cmsdk-apb-watchdog.c
110
F: include/hw/watchdog/cmsdk-apb-watchdog.h
111
+F: tests/qtest/cmsdk-apb-watchdog-test.c
112
F: hw/misc/tz-ppc.c
113
F: include/hw/misc/tz-ppc.h
114
F: hw/misc/tz-mpc.c
115
diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
116
index XXXXXXX..XXXXXXX 100644
117
--- a/tests/qtest/meson.build
118
+++ b/tests/qtest/meson.build
119
@@ -XXX,XX +XXX,XX @@ qtests_npcm7xx = \
120
'npcm7xx_watchdog_timer-test']
121
qtests_arm = \
122
(config_all_devices.has_key('CONFIG_CMSDK_APB_TIMER') ? ['cmsdk-apb-timer-test'] : []) + \
123
+ (config_all_devices.has_key('CONFIG_CMSDK_APB_WATCHDOG') ? ['cmsdk-apb-watchdog-test'] : []) + \
124
(config_all_devices.has_key('CONFIG_PFLASH_CFI02') ? ['pflash-cfi02-test'] : []) + \
125
(config_all_devices.has_key('CONFIG_NPCM7XX') ? qtests_npcm7xx : []) + \
126
['arm-cpu-features',
127
--
123
--
128
2.20.1
124
2.20.1
129
125
130
126
diff view generated by jsdifflib
[PULL 40/46] hw/timer/cmsdk-apb-dualtimer: Convert to use Clock input
[PULL 18/24] target/arm: Implement MVE saturating narrowing shifts
1
Switch the CMSDK APB dualtimer device over to using its Clock input;
1
Implement the MVE saturating shift-right-and-narrow insns
2
the pclk-frq property is now ignored.
2
VQSHRN, VQSHRUN, VQRSHRN and VQRSHRUN.
3
4
do_srshr() is borrowed from sve_helper.c.
3
5
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Luc Michel <luc@lmichel.fr>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Message-id: 20210628135835.6690-13-peter.maydell@linaro.org
7
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Message-id: 20210128114145.20536-20-peter.maydell@linaro.org
9
Message-id: 20210121190622.22000-20-peter.maydell@linaro.org
10
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
11
---
9
---
12
hw/timer/cmsdk-apb-dualtimer.c | 42 ++++++++++++++++++++++++++++++----
10
target/arm/helper-mve.h | 30 +++++++++++
13
1 file changed, 37 insertions(+), 5 deletions(-)
11
target/arm/mve.decode | 28 ++++++++++
14
12
target/arm/mve_helper.c | 104 +++++++++++++++++++++++++++++++++++++
15
diff --git a/hw/timer/cmsdk-apb-dualtimer.c b/hw/timer/cmsdk-apb-dualtimer.c
13
target/arm/translate-mve.c | 12 +++++
16
index XXXXXXX..XXXXXXX 100644
14
4 files changed, 174 insertions(+)
17
--- a/hw/timer/cmsdk-apb-dualtimer.c
15
18
+++ b/hw/timer/cmsdk-apb-dualtimer.c
16
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
19
@@ -XXX,XX +XXX,XX @@ static void cmsdk_apb_dualtimer_update(CMSDKAPBDualTimer *s)
17
index XXXXXXX..XXXXXXX 100644
20
qemu_set_irq(s->timerintc, timintc);
18
--- a/target/arm/helper-mve.h
19
+++ b/target/arm/helper-mve.h
20
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vrshrnbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
21
DEF_HELPER_FLAGS_4(mve_vrshrnbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
22
DEF_HELPER_FLAGS_4(mve_vrshrntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
23
DEF_HELPER_FLAGS_4(mve_vrshrnth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
24
+
25
+DEF_HELPER_FLAGS_4(mve_vqshrnb_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
26
+DEF_HELPER_FLAGS_4(mve_vqshrnb_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
27
+DEF_HELPER_FLAGS_4(mve_vqshrnt_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
28
+DEF_HELPER_FLAGS_4(mve_vqshrnt_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
29
+
30
+DEF_HELPER_FLAGS_4(mve_vqshrnb_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
31
+DEF_HELPER_FLAGS_4(mve_vqshrnb_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
32
+DEF_HELPER_FLAGS_4(mve_vqshrnt_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
33
+DEF_HELPER_FLAGS_4(mve_vqshrnt_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
34
+
35
+DEF_HELPER_FLAGS_4(mve_vqshrunbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
36
+DEF_HELPER_FLAGS_4(mve_vqshrunbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
37
+DEF_HELPER_FLAGS_4(mve_vqshruntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
38
+DEF_HELPER_FLAGS_4(mve_vqshrunth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
39
+
40
+DEF_HELPER_FLAGS_4(mve_vqrshrnb_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
41
+DEF_HELPER_FLAGS_4(mve_vqrshrnb_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
42
+DEF_HELPER_FLAGS_4(mve_vqrshrnt_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
43
+DEF_HELPER_FLAGS_4(mve_vqrshrnt_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
44
+
45
+DEF_HELPER_FLAGS_4(mve_vqrshrnb_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
46
+DEF_HELPER_FLAGS_4(mve_vqrshrnb_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
47
+DEF_HELPER_FLAGS_4(mve_vqrshrnt_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
48
+DEF_HELPER_FLAGS_4(mve_vqrshrnt_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
49
+
50
+DEF_HELPER_FLAGS_4(mve_vqrshrunbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
51
+DEF_HELPER_FLAGS_4(mve_vqrshrunbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
52
+DEF_HELPER_FLAGS_4(mve_vqrshruntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
53
+DEF_HELPER_FLAGS_4(mve_vqrshrunth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
54
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
55
index XXXXXXX..XXXXXXX 100644
56
--- a/target/arm/mve.decode
57
+++ b/target/arm/mve.decode
58
@@ -XXX,XX +XXX,XX @@ VRSHRNB 111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_b
59
VRSHRNB 111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_h
60
VRSHRNT 111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_b
61
VRSHRNT 111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_h
62
+
63
+VQSHRNB_S 111 0 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 0 @2_shr_b
64
+VQSHRNB_S 111 0 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 0 @2_shr_h
65
+VQSHRNT_S 111 0 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 0 @2_shr_b
66
+VQSHRNT_S 111 0 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 0 @2_shr_h
67
+VQSHRNB_U 111 1 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 0 @2_shr_b
68
+VQSHRNB_U 111 1 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 0 @2_shr_h
69
+VQSHRNT_U 111 1 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 0 @2_shr_b
70
+VQSHRNT_U 111 1 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 0 @2_shr_h
71
+
72
+VQSHRUNB 111 0 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_b
73
+VQSHRUNB 111 0 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_h
74
+VQSHRUNT 111 0 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_b
75
+VQSHRUNT 111 0 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_h
76
+
77
+VQRSHRNB_S 111 0 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 1 @2_shr_b
78
+VQRSHRNB_S 111 0 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 1 @2_shr_h
79
+VQRSHRNT_S 111 0 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 1 @2_shr_b
80
+VQRSHRNT_S 111 0 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 1 @2_shr_h
81
+VQRSHRNB_U 111 1 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 1 @2_shr_b
82
+VQRSHRNB_U 111 1 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 1 @2_shr_h
83
+VQRSHRNT_U 111 1 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 1 @2_shr_b
84
+VQRSHRNT_U 111 1 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 1 @2_shr_h
85
+
86
+VQRSHRUNB 111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_b
87
+VQRSHRUNB 111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_h
88
+VQRSHRUNT 111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_b
89
+VQRSHRUNT 111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_h
90
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
91
index XXXXXXX..XXXXXXX 100644
92
--- a/target/arm/mve_helper.c
93
+++ b/target/arm/mve_helper.c
94
@@ -XXX,XX +XXX,XX @@ static inline uint64_t do_urshr(uint64_t x, unsigned sh)
95
}
21
}
96
}
22
97
23
+static int cmsdk_dualtimermod_divisor(CMSDKAPBDualTimerModule *m)
98
+static inline int64_t do_srshr(int64_t x, unsigned sh)
24
+{
99
+{
25
+ /* Return the divisor set by the current CONTROL.PRESCALE value */
100
+ if (likely(sh < 64)) {
26
+ switch (FIELD_EX32(m->control, CONTROL, PRESCALE)) {
101
+ return (x >> sh) + ((x >> (sh - 1)) & 1);
27
+ case 0:
102
+ } else {
28
+ return 1;
103
+ /* Rounding the sign bit always produces 0. */
29
+ case 1:
104
+ return 0;
30
+ return 16;
31
+ case 2:
32
+ case 3: /* UNDEFINED, we treat like 2 (and complained when it was set) */
33
+ return 256;
34
+ default:
35
+ g_assert_not_reached();
36
+ }
105
+ }
37
+}
106
+}
38
+
107
+
39
static void cmsdk_dualtimermod_write_control(CMSDKAPBDualTimerModule *m,
108
DO_VSHRN_ALL(vshrn, DO_SHR)
40
uint32_t newctrl)
109
DO_VSHRN_ALL(vrshrn, do_urshr)
41
{
110
+
42
@@ -XXX,XX +XXX,XX @@ static void cmsdk_dualtimermod_write_control(CMSDKAPBDualTimerModule *m,
111
+static inline int32_t do_sat_bhs(int64_t val, int64_t min, int64_t max,
43
default:
112
+ bool *satp)
44
g_assert_not_reached();
45
}
46
- ptimer_set_freq(m->timer, m->parent->pclk_frq / divisor);
47
+ ptimer_set_period_from_clock(m->timer, m->parent->timclk, divisor);
48
}
49
50
if (changed & R_CONTROL_MODE_MASK) {
51
@@ -XXX,XX +XXX,XX @@ static void cmsdk_dualtimermod_reset(CMSDKAPBDualTimerModule *m)
52
* limit must both be set to 0xffff, so we wrap at 16 bits.
53
*/
54
ptimer_set_limit(m->timer, 0xffff, 1);
55
- ptimer_set_freq(m->timer, m->parent->pclk_frq);
56
+ ptimer_set_period_from_clock(m->timer, m->parent->timclk,
57
+ cmsdk_dualtimermod_divisor(m));
58
ptimer_transaction_commit(m->timer);
59
}
60
61
@@ -XXX,XX +XXX,XX @@ static void cmsdk_apb_dualtimer_reset(DeviceState *dev)
62
s->timeritop = 0;
63
}
64
65
+static void cmsdk_apb_dualtimer_clk_update(void *opaque)
66
+{
113
+{
67
+ CMSDKAPBDualTimer *s = CMSDK_APB_DUALTIMER(opaque);
114
+ if (val > max) {
68
+ int i;
115
+ *satp = true;
69
+
116
+ return max;
70
+ for (i = 0; i < ARRAY_SIZE(s->timermod); i++) {
117
+ } else if (val < min) {
71
+ CMSDKAPBDualTimerModule *m = &s->timermod[i];
118
+ *satp = true;
72
+ ptimer_transaction_begin(m->timer);
119
+ return min;
73
+ ptimer_set_period_from_clock(m->timer, m->parent->timclk,
120
+ } else {
74
+ cmsdk_dualtimermod_divisor(m));
121
+ return val;
75
+ ptimer_transaction_commit(m->timer);
76
+ }
122
+ }
77
+}
123
+}
78
+
124
+
79
static void cmsdk_apb_dualtimer_init(Object *obj)
125
+/* Saturating narrowing right shifts */
80
{
126
+#define DO_VSHRN_SAT(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE, FN) \
81
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
127
+ void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \
82
@@ -XXX,XX +XXX,XX @@ static void cmsdk_apb_dualtimer_init(Object *obj)
128
+ void *vm, uint32_t shift) \
83
for (i = 0; i < ARRAY_SIZE(s->timermod); i++) {
129
+ { \
84
sysbus_init_irq(sbd, &s->timermod[i].timerint);
130
+ LTYPE *m = vm; \
85
}
131
+ TYPE *d = vd; \
86
- s->timclk = qdev_init_clock_in(DEVICE(s), "TIMCLK", NULL, NULL);
132
+ uint16_t mask = mve_element_mask(env); \
87
+ s->timclk = qdev_init_clock_in(DEVICE(s), "TIMCLK",
133
+ bool qc = false; \
88
+ cmsdk_apb_dualtimer_clk_update, s);
134
+ unsigned le; \
89
}
135
+ for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \
90
136
+ bool sat = false; \
91
static void cmsdk_apb_dualtimer_realize(DeviceState *dev, Error **errp)
137
+ TYPE r = FN(m[H##LESIZE(le)], shift, &sat); \
92
@@ -XXX,XX +XXX,XX @@ static void cmsdk_apb_dualtimer_realize(DeviceState *dev, Error **errp)
138
+ mergemask(&d[H##ESIZE(le * 2 + TOP)], r, mask); \
93
CMSDKAPBDualTimer *s = CMSDK_APB_DUALTIMER(dev);
139
+ qc |= sat && (mask & 1 << (TOP * ESIZE)); \
94
int i;
140
+ } \
95
141
+ if (qc) { \
96
- if (s->pclk_frq == 0) {
142
+ env->vfp.qc[0] = qc; \
97
- error_setg(errp, "CMSDK APB timer: pclk-frq property must be set");
143
+ } \
98
+ if (!clock_has_source(s->timclk)) {
144
+ mve_advance_vpt(env); \
99
+ error_setg(errp, "CMSDK APB dualtimer: TIMCLK clock must be connected");
145
+ }
100
return;
146
+
101
}
147
+#define DO_VSHRN_SAT_UB(BOP, TOP, FN) \
102
148
+ DO_VSHRN_SAT(BOP, false, 1, uint8_t, 2, uint16_t, FN) \
149
+ DO_VSHRN_SAT(TOP, true, 1, uint8_t, 2, uint16_t, FN)
150
+
151
+#define DO_VSHRN_SAT_UH(BOP, TOP, FN) \
152
+ DO_VSHRN_SAT(BOP, false, 2, uint16_t, 4, uint32_t, FN) \
153
+ DO_VSHRN_SAT(TOP, true, 2, uint16_t, 4, uint32_t, FN)
154
+
155
+#define DO_VSHRN_SAT_SB(BOP, TOP, FN) \
156
+ DO_VSHRN_SAT(BOP, false, 1, int8_t, 2, int16_t, FN) \
157
+ DO_VSHRN_SAT(TOP, true, 1, int8_t, 2, int16_t, FN)
158
+
159
+#define DO_VSHRN_SAT_SH(BOP, TOP, FN) \
160
+ DO_VSHRN_SAT(BOP, false, 2, int16_t, 4, int32_t, FN) \
161
+ DO_VSHRN_SAT(TOP, true, 2, int16_t, 4, int32_t, FN)
162
+
163
+#define DO_SHRN_SB(N, M, SATP) \
164
+ do_sat_bhs((int64_t)(N) >> (M), INT8_MIN, INT8_MAX, SATP)
165
+#define DO_SHRN_UB(N, M, SATP) \
166
+ do_sat_bhs((uint64_t)(N) >> (M), 0, UINT8_MAX, SATP)
167
+#define DO_SHRUN_B(N, M, SATP) \
168
+ do_sat_bhs((int64_t)(N) >> (M), 0, UINT8_MAX, SATP)
169
+
170
+#define DO_SHRN_SH(N, M, SATP) \
171
+ do_sat_bhs((int64_t)(N) >> (M), INT16_MIN, INT16_MAX, SATP)
172
+#define DO_SHRN_UH(N, M, SATP) \
173
+ do_sat_bhs((uint64_t)(N) >> (M), 0, UINT16_MAX, SATP)
174
+#define DO_SHRUN_H(N, M, SATP) \
175
+ do_sat_bhs((int64_t)(N) >> (M), 0, UINT16_MAX, SATP)
176
+
177
+#define DO_RSHRN_SB(N, M, SATP) \
178
+ do_sat_bhs(do_srshr(N, M), INT8_MIN, INT8_MAX, SATP)
179
+#define DO_RSHRN_UB(N, M, SATP) \
180
+ do_sat_bhs(do_urshr(N, M), 0, UINT8_MAX, SATP)
181
+#define DO_RSHRUN_B(N, M, SATP) \
182
+ do_sat_bhs(do_srshr(N, M), 0, UINT8_MAX, SATP)
183
+
184
+#define DO_RSHRN_SH(N, M, SATP) \
185
+ do_sat_bhs(do_srshr(N, M), INT16_MIN, INT16_MAX, SATP)
186
+#define DO_RSHRN_UH(N, M, SATP) \
187
+ do_sat_bhs(do_urshr(N, M), 0, UINT16_MAX, SATP)
188
+#define DO_RSHRUN_H(N, M, SATP) \
189
+ do_sat_bhs(do_srshr(N, M), 0, UINT16_MAX, SATP)
190
+
191
+DO_VSHRN_SAT_SB(vqshrnb_sb, vqshrnt_sb, DO_SHRN_SB)
192
+DO_VSHRN_SAT_SH(vqshrnb_sh, vqshrnt_sh, DO_SHRN_SH)
193
+DO_VSHRN_SAT_UB(vqshrnb_ub, vqshrnt_ub, DO_SHRN_UB)
194
+DO_VSHRN_SAT_UH(vqshrnb_uh, vqshrnt_uh, DO_SHRN_UH)
195
+DO_VSHRN_SAT_SB(vqshrunbb, vqshruntb, DO_SHRUN_B)
196
+DO_VSHRN_SAT_SH(vqshrunbh, vqshrunth, DO_SHRUN_H)
197
+
198
+DO_VSHRN_SAT_SB(vqrshrnb_sb, vqrshrnt_sb, DO_RSHRN_SB)
199
+DO_VSHRN_SAT_SH(vqrshrnb_sh, vqrshrnt_sh, DO_RSHRN_SH)
200
+DO_VSHRN_SAT_UB(vqrshrnb_ub, vqrshrnt_ub, DO_RSHRN_UB)
201
+DO_VSHRN_SAT_UH(vqrshrnb_uh, vqrshrnt_uh, DO_RSHRN_UH)
202
+DO_VSHRN_SAT_SB(vqrshrunbb, vqrshruntb, DO_RSHRUN_B)
203
+DO_VSHRN_SAT_SH(vqrshrunbh, vqrshrunth, DO_RSHRUN_H)
204
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
205
index XXXXXXX..XXXXXXX 100644
206
--- a/target/arm/translate-mve.c
207
+++ b/target/arm/translate-mve.c
208
@@ -XXX,XX +XXX,XX @@ DO_2SHIFT_N(VSHRNB, vshrnb)
209
DO_2SHIFT_N(VSHRNT, vshrnt)
210
DO_2SHIFT_N(VRSHRNB, vrshrnb)
211
DO_2SHIFT_N(VRSHRNT, vrshrnt)
212
+DO_2SHIFT_N(VQSHRNB_S, vqshrnb_s)
213
+DO_2SHIFT_N(VQSHRNT_S, vqshrnt_s)
214
+DO_2SHIFT_N(VQSHRNB_U, vqshrnb_u)
215
+DO_2SHIFT_N(VQSHRNT_U, vqshrnt_u)
216
+DO_2SHIFT_N(VQSHRUNB, vqshrunb)
217
+DO_2SHIFT_N(VQSHRUNT, vqshrunt)
218
+DO_2SHIFT_N(VQRSHRNB_S, vqrshrnb_s)
219
+DO_2SHIFT_N(VQRSHRNT_S, vqrshrnt_s)
220
+DO_2SHIFT_N(VQRSHRNB_U, vqrshrnb_u)
221
+DO_2SHIFT_N(VQRSHRNT_U, vqrshrnt_u)
222
+DO_2SHIFT_N(VQRSHRUNB, vqrshrunb)
223
+DO_2SHIFT_N(VQRSHRUNT, vqrshrunt)
103
--
224
--
104
2.20.1
225
2.20.1
105
226
106
227
diff view generated by jsdifflib
[PULL 33/46] hw/arm/mps2: Inline CMSDK_APB_TIMER creation
[PULL 19/24] target/arm: Implement MVE VSHLC
1
The old-style convenience function cmsdk_apb_timer_create() for
1
Implement the MVE VSHLC insn, which performs a shift left of the
2
creating CMSDK_APB_TIMER objects is used in only two places in
2
entire vector with carry in bits provided from a general purpose
3
mps2.c. Most of the rest of the code in that file uses the new
3
register and carry out bits written back to that register.
4
"initialize in place" coding style.
5
6
We want to connect up a Clock object which should be done between the
7
object creation and realization; rather than adding a Clock* argument
8
to the convenience function, convert the timer creation code in
9
mps2.c to the same style as is used already for the watchdog,
10
dualtimer and other devices, and delete the now-unused convenience
11
function.
12
4
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
15
Reviewed-by: Luc Michel <luc@lmichel.fr>
7
Message-id: 20210628135835.6690-14-peter.maydell@linaro.org
16
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
17
Message-id: 20210128114145.20536-13-peter.maydell@linaro.org
18
Message-id: 20210121190622.22000-13-peter.maydell@linaro.org
19
---
8
---
20
include/hw/timer/cmsdk-apb-timer.h | 21 ---------------------
9
target/arm/helper-mve.h | 2 ++
21
hw/arm/mps2.c | 18 ++++++++++++++++--
10
target/arm/mve.decode | 2 ++
22
2 files changed, 16 insertions(+), 23 deletions(-)
11
target/arm/mve_helper.c | 38 ++++++++++++++++++++++++++++++++++++++
12
target/arm/translate-mve.c | 30 ++++++++++++++++++++++++++++++
13
4 files changed, 72 insertions(+)
23
14
24
diff --git a/include/hw/timer/cmsdk-apb-timer.h b/include/hw/timer/cmsdk-apb-timer.h
15
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
25
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
26
--- a/include/hw/timer/cmsdk-apb-timer.h
17
--- a/target/arm/helper-mve.h
27
+++ b/include/hw/timer/cmsdk-apb-timer.h
18
+++ b/target/arm/helper-mve.h
28
@@ -XXX,XX +XXX,XX @@ struct CMSDKAPBTimer {
19
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vqrshrunbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
29
uint32_t intstatus;
20
DEF_HELPER_FLAGS_4(mve_vqrshrunbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
30
};
21
DEF_HELPER_FLAGS_4(mve_vqrshruntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
31
22
DEF_HELPER_FLAGS_4(mve_vqrshrunth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
32
-/**
23
+
33
- * cmsdk_apb_timer_create - convenience function to create TYPE_CMSDK_APB_TIMER
24
+DEF_HELPER_FLAGS_4(mve_vshlc, TCG_CALL_NO_WG, i32, env, ptr, i32, i32)
34
- * @addr: location in system memory to map registers
25
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
35
- * @pclk_frq: frequency in Hz of the PCLK clock (used for calculating baud rate)
36
- */
37
-static inline DeviceState *cmsdk_apb_timer_create(hwaddr addr,
38
- qemu_irq timerint,
39
- uint32_t pclk_frq)
40
-{
41
- DeviceState *dev;
42
- SysBusDevice *s;
43
-
44
- dev = qdev_new(TYPE_CMSDK_APB_TIMER);
45
- s = SYS_BUS_DEVICE(dev);
46
- qdev_prop_set_uint32(dev, "pclk-frq", pclk_frq);
47
- sysbus_realize_and_unref(s, &error_fatal);
48
- sysbus_mmio_map(s, 0, addr);
49
- sysbus_connect_irq(s, 0, timerint);
50
- return dev;
51
-}
52
-
53
#endif
54
diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c
55
index XXXXXXX..XXXXXXX 100644
26
index XXXXXXX..XXXXXXX 100644
56
--- a/hw/arm/mps2.c
27
--- a/target/arm/mve.decode
57
+++ b/hw/arm/mps2.c
28
+++ b/target/arm/mve.decode
58
@@ -XXX,XX +XXX,XX @@ struct MPS2MachineState {
29
@@ -XXX,XX +XXX,XX @@ VQRSHRUNB 111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_b
59
/* CMSDK APB subsystem */
30
VQRSHRUNB 111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_h
60
CMSDKAPBDualTimer dualtimer;
31
VQRSHRUNT 111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_b
61
CMSDKAPBWatchdog watchdog;
32
VQRSHRUNT 111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_h
62
+ CMSDKAPBTimer timer[2];
63
};
64
65
#define TYPE_MPS2_MACHINE "mps2"
66
@@ -XXX,XX +XXX,XX @@ static void mps2_common_init(MachineState *machine)
67
}
68
69
/* CMSDK APB subsystem */
70
- cmsdk_apb_timer_create(0x40000000, qdev_get_gpio_in(armv7m, 8), SYSCLK_FRQ);
71
- cmsdk_apb_timer_create(0x40001000, qdev_get_gpio_in(armv7m, 9), SYSCLK_FRQ);
72
+ for (i = 0; i < ARRAY_SIZE(mms->timer); i++) {
73
+ g_autofree char *name = g_strdup_printf("timer%d", i);
74
+ hwaddr base = 0x40000000 + i * 0x1000;
75
+ int irqno = 8 + i;
76
+ SysBusDevice *sbd;
77
+
33
+
78
+ object_initialize_child(OBJECT(mms), name, &mms->timer[i],
34
+VSHLC 111 0 1110 1 . 1 imm:5 ... 0 1111 1100 rdm:4 qd=%qd
79
+ TYPE_CMSDK_APB_TIMER);
35
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
80
+ sbd = SYS_BUS_DEVICE(&mms->timer[i]);
36
index XXXXXXX..XXXXXXX 100644
81
+ qdev_prop_set_uint32(DEVICE(&mms->timer[i]), "pclk-frq", SYSCLK_FRQ);
37
--- a/target/arm/mve_helper.c
82
+ sysbus_realize_and_unref(sbd, &error_fatal);
38
+++ b/target/arm/mve_helper.c
83
+ sysbus_mmio_map(sbd, 0, base);
39
@@ -XXX,XX +XXX,XX @@ DO_VSHRN_SAT_UB(vqrshrnb_ub, vqrshrnt_ub, DO_RSHRN_UB)
84
+ sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(armv7m, irqno));
40
DO_VSHRN_SAT_UH(vqrshrnb_uh, vqrshrnt_uh, DO_RSHRN_UH)
41
DO_VSHRN_SAT_SB(vqrshrunbb, vqrshruntb, DO_RSHRUN_B)
42
DO_VSHRN_SAT_SH(vqrshrunbh, vqrshrunth, DO_RSHRUN_H)
43
+
44
+uint32_t HELPER(mve_vshlc)(CPUARMState *env, void *vd, uint32_t rdm,
45
+ uint32_t shift)
46
+{
47
+ uint32_t *d = vd;
48
+ uint16_t mask = mve_element_mask(env);
49
+ unsigned e;
50
+ uint32_t r;
51
+
52
+ /*
53
+ * For each 32-bit element, we shift it left, bringing in the
54
+ * low 'shift' bits of rdm at the bottom. Bits shifted out at
55
+ * the top become the new rdm, if the predicate mask permits.
56
+ * The final rdm value is returned to update the register.
57
+ * shift == 0 here means "shift by 32 bits".
58
+ */
59
+ if (shift == 0) {
60
+ for (e = 0; e < 16 / 4; e++, mask >>= 4) {
61
+ r = rdm;
62
+ if (mask & 1) {
63
+ rdm = d[H4(e)];
64
+ }
65
+ mergemask(&d[H4(e)], r, mask);
66
+ }
67
+ } else {
68
+ uint32_t shiftmask = MAKE_64BIT_MASK(0, shift);
69
+
70
+ for (e = 0; e < 16 / 4; e++, mask >>= 4) {
71
+ r = (d[H4(e)] << shift) | (rdm & shiftmask);
72
+ if (mask & 1) {
73
+ rdm = d[H4(e)] >> (32 - shift);
74
+ }
75
+ mergemask(&d[H4(e)], r, mask);
76
+ }
77
+ }
78
+ mve_advance_vpt(env);
79
+ return rdm;
80
+}
81
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
82
index XXXXXXX..XXXXXXX 100644
83
--- a/target/arm/translate-mve.c
84
+++ b/target/arm/translate-mve.c
85
@@ -XXX,XX +XXX,XX @@ DO_2SHIFT_N(VQRSHRNB_U, vqrshrnb_u)
86
DO_2SHIFT_N(VQRSHRNT_U, vqrshrnt_u)
87
DO_2SHIFT_N(VQRSHRUNB, vqrshrunb)
88
DO_2SHIFT_N(VQRSHRUNT, vqrshrunt)
89
+
90
+static bool trans_VSHLC(DisasContext *s, arg_VSHLC *a)
91
+{
92
+ /*
93
+ * Whole Vector Left Shift with Carry. The carry is taken
94
+ * from a general purpose register and written back there.
95
+ * An imm of 0 means "shift by 32".
96
+ */
97
+ TCGv_ptr qd;
98
+ TCGv_i32 rdm;
99
+
100
+ if (!dc_isar_feature(aa32_mve, s) || !mve_check_qreg_bank(s, a->qd)) {
101
+ return false;
102
+ }
103
+ if (a->rdm == 13 || a->rdm == 15) {
104
+ /* CONSTRAINED UNPREDICTABLE: we UNDEF */
105
+ return false;
106
+ }
107
+ if (!mve_eci_check(s) || !vfp_access_check(s)) {
108
+ return true;
85
+ }
109
+ }
86
+
110
+
87
object_initialize_child(OBJECT(mms), "dualtimer", &mms->dualtimer,
111
+ qd = mve_qreg_ptr(a->qd);
88
TYPE_CMSDK_APB_DUALTIMER);
112
+ rdm = load_reg(s, a->rdm);
89
qdev_prop_set_uint32(DEVICE(&mms->dualtimer), "pclk-frq", SYSCLK_FRQ);
113
+ gen_helper_mve_vshlc(rdm, cpu_env, qd, rdm, tcg_constant_i32(a->imm));
114
+ store_reg(s, a->rdm, rdm);
115
+ tcg_temp_free_ptr(qd);
116
+ mve_update_eci(s);
117
+ return true;
118
+}
90
--
119
--
91
2.20.1
120
2.20.1
92
121
93
122
diff view generated by jsdifflib
[PULL 41/46] hw/watchdog/cmsdk-apb-watchdog: Convert to use Clock input
[PULL 20/24] target/arm: Implement MVE VADDLV
1
Switch the CMSDK APB watchdog device over to using its Clock input;
1
Implement the MVE VADDLV insn; this is similar to VADDV, except
2
the wdogclk_frq property is now ignored.
2
that it accumulates 32-bit elements into a 64-bit accumulator
3
stored in a pair of general-purpose registers.
3
4
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Reviewed-by: Luc Michel <luc@lmichel.fr>
7
Message-id: 20210628135835.6690-15-peter.maydell@linaro.org
7
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Message-id: 20210128114145.20536-21-peter.maydell@linaro.org
9
Message-id: 20210121190622.22000-21-peter.maydell@linaro.org
10
---
8
---
11
hw/watchdog/cmsdk-apb-watchdog.c | 18 ++++++++++++++----
9
target/arm/helper-mve.h | 3 ++
12
1 file changed, 14 insertions(+), 4 deletions(-)
10
target/arm/mve.decode | 6 +++-
11
target/arm/mve_helper.c | 19 ++++++++++++
12
target/arm/translate-mve.c | 63 ++++++++++++++++++++++++++++++++++++++
13
4 files changed, 90 insertions(+), 1 deletion(-)
13
14
14
diff --git a/hw/watchdog/cmsdk-apb-watchdog.c b/hw/watchdog/cmsdk-apb-watchdog.c
15
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
15
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/watchdog/cmsdk-apb-watchdog.c
17
--- a/target/arm/helper-mve.h
17
+++ b/hw/watchdog/cmsdk-apb-watchdog.c
18
+++ b/target/arm/helper-mve.h
18
@@ -XXX,XX +XXX,XX @@ static void cmsdk_apb_watchdog_reset(DeviceState *dev)
19
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_vaddvuh, TCG_CALL_NO_WG, i32, env, ptr, i32)
19
ptimer_transaction_commit(s->timer);
20
DEF_HELPER_FLAGS_3(mve_vaddvsw, TCG_CALL_NO_WG, i32, env, ptr, i32)
21
DEF_HELPER_FLAGS_3(mve_vaddvuw, TCG_CALL_NO_WG, i32, env, ptr, i32)
22
23
+DEF_HELPER_FLAGS_3(mve_vaddlv_s, TCG_CALL_NO_WG, i64, env, ptr, i64)
24
+DEF_HELPER_FLAGS_3(mve_vaddlv_u, TCG_CALL_NO_WG, i64, env, ptr, i64)
25
+
26
DEF_HELPER_FLAGS_3(mve_vmovi, TCG_CALL_NO_WG, void, env, ptr, i64)
27
DEF_HELPER_FLAGS_3(mve_vandi, TCG_CALL_NO_WG, void, env, ptr, i64)
28
DEF_HELPER_FLAGS_3(mve_vorri, TCG_CALL_NO_WG, void, env, ptr, i64)
29
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
30
index XXXXXXX..XXXXXXX 100644
31
--- a/target/arm/mve.decode
32
+++ b/target/arm/mve.decode
33
@@ -XXX,XX +XXX,XX @@ VQDMULH_scalar 1110 1110 0 . .. ... 1 ... 0 1110 . 110 .... @2scalar
34
VQRDMULH_scalar 1111 1110 0 . .. ... 1 ... 0 1110 . 110 .... @2scalar
35
36
# Vector add across vector
37
-VADDV 111 u:1 1110 1111 size:2 01 ... 0 1111 0 0 a:1 0 qm:3 0 rda=%rdalo
38
+{
39
+ VADDV 111 u:1 1110 1111 size:2 01 ... 0 1111 0 0 a:1 0 qm:3 0 rda=%rdalo
40
+ VADDLV 111 u:1 1110 1 ... 1001 ... 0 1111 00 a:1 0 qm:3 0 \
41
+ rdahi=%rdahi rdalo=%rdalo
42
+}
43
44
# Predicate operations
45
%mask_22_13 22:1 13:3
46
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
47
index XXXXXXX..XXXXXXX 100644
48
--- a/target/arm/mve_helper.c
49
+++ b/target/arm/mve_helper.c
50
@@ -XXX,XX +XXX,XX @@ DO_VADDV(vaddvub, 1, uint8_t)
51
DO_VADDV(vaddvuh, 2, uint16_t)
52
DO_VADDV(vaddvuw, 4, uint32_t)
53
54
+#define DO_VADDLV(OP, TYPE, LTYPE) \
55
+ uint64_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vm, \
56
+ uint64_t ra) \
57
+ { \
58
+ uint16_t mask = mve_element_mask(env); \
59
+ unsigned e; \
60
+ TYPE *m = vm; \
61
+ for (e = 0; e < 16 / 4; e++, mask >>= 4) { \
62
+ if (mask & 1) { \
63
+ ra += (LTYPE)m[H4(e)]; \
64
+ } \
65
+ } \
66
+ mve_advance_vpt(env); \
67
+ return ra; \
68
+ } \
69
+
70
+DO_VADDLV(vaddlv_s, int32_t, int64_t)
71
+DO_VADDLV(vaddlv_u, uint32_t, uint64_t)
72
+
73
/* Shifts by immediate */
74
#define DO_2SHIFT(OP, ESIZE, TYPE, FN) \
75
void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \
76
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
77
index XXXXXXX..XXXXXXX 100644
78
--- a/target/arm/translate-mve.c
79
+++ b/target/arm/translate-mve.c
80
@@ -XXX,XX +XXX,XX @@ static bool trans_VADDV(DisasContext *s, arg_VADDV *a)
81
return true;
20
}
82
}
21
83
22
+static void cmsdk_apb_watchdog_clk_update(void *opaque)
84
+static bool trans_VADDLV(DisasContext *s, arg_VADDLV *a)
23
+{
85
+{
24
+ CMSDKAPBWatchdog *s = CMSDK_APB_WATCHDOG(opaque);
86
+ /*
87
+ * Vector Add Long Across Vector: accumulate the 32-bit
88
+ * elements of the vector into a 64-bit result stored in
89
+ * a pair of general-purpose registers.
90
+ * No need to check Qm's bank: it is only 3 bits in decode.
91
+ */
92
+ TCGv_ptr qm;
93
+ TCGv_i64 rda;
94
+ TCGv_i32 rdalo, rdahi;
25
+
95
+
26
+ ptimer_transaction_begin(s->timer);
96
+ if (!dc_isar_feature(aa32_mve, s)) {
27
+ ptimer_set_period_from_clock(s->timer, s->wdogclk, 1);
97
+ return false;
28
+ ptimer_transaction_commit(s->timer);
98
+ }
99
+ /*
100
+ * rdahi == 13 is UNPREDICTABLE; rdahi == 15 is a related
101
+ * encoding; rdalo always has bit 0 clear so cannot be 13 or 15.
102
+ */
103
+ if (a->rdahi == 13 || a->rdahi == 15) {
104
+ return false;
105
+ }
106
+ if (!mve_eci_check(s) || !vfp_access_check(s)) {
107
+ return true;
108
+ }
109
+
110
+ /*
111
+ * This insn is subject to beat-wise execution. Partial execution
112
+ * of an A=0 (no-accumulate) insn which does not execute the first
113
+ * beat must start with the current value of RdaHi:RdaLo, not zero.
114
+ */
115
+ if (a->a || mve_skip_first_beat(s)) {
116
+ /* Accumulate input from RdaHi:RdaLo */
117
+ rda = tcg_temp_new_i64();
118
+ rdalo = load_reg(s, a->rdalo);
119
+ rdahi = load_reg(s, a->rdahi);
120
+ tcg_gen_concat_i32_i64(rda, rdalo, rdahi);
121
+ tcg_temp_free_i32(rdalo);
122
+ tcg_temp_free_i32(rdahi);
123
+ } else {
124
+ /* Accumulate starting at zero */
125
+ rda = tcg_const_i64(0);
126
+ }
127
+
128
+ qm = mve_qreg_ptr(a->qm);
129
+ if (a->u) {
130
+ gen_helper_mve_vaddlv_u(rda, cpu_env, qm, rda);
131
+ } else {
132
+ gen_helper_mve_vaddlv_s(rda, cpu_env, qm, rda);
133
+ }
134
+ tcg_temp_free_ptr(qm);
135
+
136
+ rdalo = tcg_temp_new_i32();
137
+ rdahi = tcg_temp_new_i32();
138
+ tcg_gen_extrl_i64_i32(rdalo, rda);
139
+ tcg_gen_extrh_i64_i32(rdahi, rda);
140
+ store_reg(s, a->rdalo, rdalo);
141
+ store_reg(s, a->rdahi, rdahi);
142
+ tcg_temp_free_i64(rda);
143
+ mve_update_eci(s);
144
+ return true;
29
+}
145
+}
30
+
146
+
31
static void cmsdk_apb_watchdog_init(Object *obj)
147
static bool do_1imm(DisasContext *s, arg_1imm *a, MVEGenOneOpImmFn *fn)
32
{
148
{
33
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
149
TCGv_ptr qd;
34
@@ -XXX,XX +XXX,XX @@ static void cmsdk_apb_watchdog_init(Object *obj)
35
s, "cmsdk-apb-watchdog", 0x1000);
36
sysbus_init_mmio(sbd, &s->iomem);
37
sysbus_init_irq(sbd, &s->wdogint);
38
- s->wdogclk = qdev_init_clock_in(DEVICE(s), "WDOGCLK", NULL, NULL);
39
+ s->wdogclk = qdev_init_clock_in(DEVICE(s), "WDOGCLK",
40
+ cmsdk_apb_watchdog_clk_update, s);
41
42
s->is_luminary = false;
43
s->id = cmsdk_apb_watchdog_id;
44
@@ -XXX,XX +XXX,XX @@ static void cmsdk_apb_watchdog_realize(DeviceState *dev, Error **errp)
45
{
46
CMSDKAPBWatchdog *s = CMSDK_APB_WATCHDOG(dev);
47
48
- if (s->wdogclk_frq == 0) {
49
+ if (!clock_has_source(s->wdogclk)) {
50
error_setg(errp,
51
- "CMSDK APB watchdog: wdogclk-frq property must be set");
52
+ "CMSDK APB watchdog: WDOGCLK clock must be connected");
53
return;
54
}
55
56
@@ -XXX,XX +XXX,XX @@ static void cmsdk_apb_watchdog_realize(DeviceState *dev, Error **errp)
57
PTIMER_POLICY_NO_COUNTER_ROUND_DOWN);
58
59
ptimer_transaction_begin(s->timer);
60
- ptimer_set_freq(s->timer, s->wdogclk_frq);
61
+ ptimer_set_period_from_clock(s->timer, s->wdogclk, 1);
62
ptimer_transaction_commit(s->timer);
63
}
64
65
--
150
--
66
2.20.1
151
2.20.1
67
152
68
153
diff view generated by jsdifflib
[PULL 28/46] hw/timer/cmsdk-apb-timer: Add Clock input
[PULL 21/24] target/arm: Implement MVE long shifts by immediate
1
As the first step in converting the CMSDK_APB_TIMER device to the
1
The MVE extension to v8.1M includes some new shift instructions which
2
Clock framework, add a Clock input. For the moment we do nothing
2
sit entirely within the non-coprocessor part of the encoding space
3
with this clock; we will change the behaviour from using the pclk-frq
3
and which operate only on general-purpose registers. They take up
4
property to using the Clock once all the users of this device have
4
the space which was previously UNPREDICTABLE MOVS and ORRS encodings
5
been converted to wire up the Clock.
5
with Rm == 13 or 15.
6
6
7
Since the device doesn't already have a doc comment for its "QEMU
7
Implement the long shifts by immediate, which perform shifts on a
8
interface", we add one including the new Clock.
8
pair of general-purpose registers treated as a 64-bit quantity, with
9
9
an immediate shift count between 1 and 32.
10
This is a migration compatibility break for machines mps2-an505,
10
11
mps2-an521, musca-a, musca-b1.
11
Awkwardly, because the MOVS and ORRS trans functions do not UNDEF for
12
the Rm==13,15 case, we need to explicitly emit code to UNDEF for the
13
cases where v8.1M now requires that. (Trying to change MOVS and ORRS
14
is too difficult, because the functions that generate the code are
15
shared between a dozen different kinds of arithmetic or logical
16
instruction for all A32, T16 and T32 encodings, and for some insns
17
and some encodings Rm==13,15 are valid.)
18
19
We make the helper functions we need for UQSHLL and SQSHLL take
20
a 32-bit value which the helper casts to int8_t because we'll need
21
these helpers also for the shift-by-register insns, where the shift
22
count might be < 0 or > 32.
12
23
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
24
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
25
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
15
Reviewed-by: Luc Michel <luc@lmichel.fr>
26
Message-id: 20210628135835.6690-16-peter.maydell@linaro.org
16
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
17
Message-id: 20210128114145.20536-8-peter.maydell@linaro.org
18
Message-id: 20210121190622.22000-8-peter.maydell@linaro.org
19
---
27
---
20
include/hw/timer/cmsdk-apb-timer.h | 9 +++++++++
28
target/arm/helper-mve.h | 3 ++
21
hw/timer/cmsdk-apb-timer.c | 7 +++++--
29
target/arm/translate.h | 1 +
22
2 files changed, 14 insertions(+), 2 deletions(-)
30
target/arm/t32.decode | 28 +++++++++++++
23
31
target/arm/mve_helper.c | 10 +++++
24
diff --git a/include/hw/timer/cmsdk-apb-timer.h b/include/hw/timer/cmsdk-apb-timer.h
32
target/arm/translate.c | 90 +++++++++++++++++++++++++++++++++++++++++
25
index XXXXXXX..XXXXXXX 100644
33
5 files changed, 132 insertions(+)
26
--- a/include/hw/timer/cmsdk-apb-timer.h
34
27
+++ b/include/hw/timer/cmsdk-apb-timer.h
35
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
36
index XXXXXXX..XXXXXXX 100644
37
--- a/target/arm/helper-mve.h
38
+++ b/target/arm/helper-mve.h
39
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vqrshruntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
40
DEF_HELPER_FLAGS_4(mve_vqrshrunth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
41
42
DEF_HELPER_FLAGS_4(mve_vshlc, TCG_CALL_NO_WG, i32, env, ptr, i32, i32)
43
+
44
+DEF_HELPER_FLAGS_3(mve_sqshll, TCG_CALL_NO_RWG, i64, env, i64, i32)
45
+DEF_HELPER_FLAGS_3(mve_uqshll, TCG_CALL_NO_RWG, i64, env, i64, i32)
46
diff --git a/target/arm/translate.h b/target/arm/translate.h
47
index XXXXXXX..XXXXXXX 100644
48
--- a/target/arm/translate.h
49
+++ b/target/arm/translate.h
50
@@ -XXX,XX +XXX,XX @@ typedef void CryptoTwoOpFn(TCGv_ptr, TCGv_ptr);
51
typedef void CryptoThreeOpIntFn(TCGv_ptr, TCGv_ptr, TCGv_i32);
52
typedef void CryptoThreeOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr);
53
typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp);
54
+typedef void WideShiftImmFn(TCGv_i64, TCGv_i64, int64_t shift);
55
56
/**
57
* arm_tbflags_from_tb:
58
diff --git a/target/arm/t32.decode b/target/arm/t32.decode
59
index XXXXXXX..XXXXXXX 100644
60
--- a/target/arm/t32.decode
61
+++ b/target/arm/t32.decode
28
@@ -XXX,XX +XXX,XX @@
62
@@ -XXX,XX +XXX,XX @@
29
#include "hw/qdev-properties.h"
63
&mcr !extern cp opc1 crn crm opc2 rt
30
#include "hw/sysbus.h"
64
&mcrr !extern cp opc1 crm rt rt2
31
#include "hw/ptimer.h"
65
32
+#include "hw/clock.h"
66
+&mve_shl_ri rdalo rdahi shim
33
#include "qom/object.h"
67
+
34
68
+# rdahi: bits [3:1] from insn, bit 0 is 1
35
#define TYPE_CMSDK_APB_TIMER "cmsdk-apb-timer"
69
+# rdalo: bits [3:1] from insn, bit 0 is 0
36
OBJECT_DECLARE_SIMPLE_TYPE(CMSDKAPBTimer, CMSDK_APB_TIMER)
70
+%rdahi_9 9:3 !function=times_2_plus_1
71
+%rdalo_17 17:3 !function=times_2
72
+
73
# Data-processing (register)
74
75
%imm5_12_6 12:3 6:2
76
@@ -XXX,XX +XXX,XX @@
77
@S_xrr_shi ....... .... . rn:4 .... .... .. shty:2 rm:4 \
78
&s_rrr_shi shim=%imm5_12_6 s=1 rd=0
79
80
+@mve_shl_ri ....... .... . ... . . ... ... . .. .. .... \
81
+ &mve_shl_ri shim=%imm5_12_6 rdalo=%rdalo_17 rdahi=%rdahi_9
82
+
83
{
84
TST_xrri 1110101 0000 1 .... 0 ... 1111 .... .... @S_xrr_shi
85
AND_rrri 1110101 0000 . .... 0 ... .... .... .... @s_rrr_shi
86
}
87
BIC_rrri 1110101 0001 . .... 0 ... .... .... .... @s_rrr_shi
88
{
89
+ # The v8.1M MVE shift insns overlap in encoding with MOVS/ORRS
90
+ # and are distinguished by having Rm==13 or 15. Those are UNPREDICTABLE
91
+ # cases for MOVS/ORRS. We decode the MVE cases first, ensuring that
92
+ # they explicitly call unallocated_encoding() for cases that must UNDEF
93
+ # (eg "using a new shift insn on a v8.1M CPU without MVE"), and letting
94
+ # the rest fall through (where ORR_rrri and MOV_rxri will end up
95
+ # handling them as r13 and r15 accesses with the same semantics as A32).
96
+ [
97
+ LSLL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 00 1111 @mve_shl_ri
98
+ LSRL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 01 1111 @mve_shl_ri
99
+ ASRL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 10 1111 @mve_shl_ri
100
+
101
+ UQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 00 1111 @mve_shl_ri
102
+ URSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 01 1111 @mve_shl_ri
103
+ SRSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 10 1111 @mve_shl_ri
104
+ SQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 11 1111 @mve_shl_ri
105
+ ]
106
+
107
MOV_rxri 1110101 0010 . 1111 0 ... .... .... .... @s_rxr_shi
108
ORR_rrri 1110101 0010 . .... 0 ... .... .... .... @s_rrr_shi
109
}
110
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
111
index XXXXXXX..XXXXXXX 100644
112
--- a/target/arm/mve_helper.c
113
+++ b/target/arm/mve_helper.c
114
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(mve_vshlc)(CPUARMState *env, void *vd, uint32_t rdm,
115
mve_advance_vpt(env);
116
return rdm;
117
}
118
+
119
+uint64_t HELPER(mve_sqshll)(CPUARMState *env, uint64_t n, uint32_t shift)
120
+{
121
+ return do_sqrshl_d(n, (int8_t)shift, false, &env->QF);
122
+}
123
+
124
+uint64_t HELPER(mve_uqshll)(CPUARMState *env, uint64_t n, uint32_t shift)
125
+{
126
+ return do_uqrshl_d(n, (int8_t)shift, false, &env->QF);
127
+}
128
diff --git a/target/arm/translate.c b/target/arm/translate.c
129
index XXXXXXX..XXXXXXX 100644
130
--- a/target/arm/translate.c
131
+++ b/target/arm/translate.c
132
@@ -XXX,XX +XXX,XX @@ static bool trans_MOVT(DisasContext *s, arg_MOVW *a)
133
return true;
134
}
37
135
38
+/*
136
+/*
39
+ * QEMU interface:
137
+ * v8.1M MVE wide-shifts
40
+ * + QOM property "pclk-frq": frequency at which the timer is clocked
41
+ * + Clock input "pclk": clock for the timer
42
+ * + sysbus MMIO region 0: the register bank
43
+ * + sysbus IRQ 0: timer interrupt TIMERINT
44
+ */
138
+ */
45
struct CMSDKAPBTimer {
139
+static bool do_mve_shl_ri(DisasContext *s, arg_mve_shl_ri *a,
46
/*< private >*/
140
+ WideShiftImmFn *fn)
47
SysBusDevice parent_obj;
141
+{
48
@@ -XXX,XX +XXX,XX @@ struct CMSDKAPBTimer {
142
+ TCGv_i64 rda;
49
qemu_irq timerint;
143
+ TCGv_i32 rdalo, rdahi;
50
uint32_t pclk_frq;
144
+
51
struct ptimer_state *timer;
145
+ if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) {
52
+ Clock *pclk;
146
+ /* Decode falls through to ORR/MOV UNPREDICTABLE handling */
53
147
+ return false;
54
uint32_t ctrl;
148
+ }
55
uint32_t value;
149
+ if (a->rdahi == 15) {
56
diff --git a/hw/timer/cmsdk-apb-timer.c b/hw/timer/cmsdk-apb-timer.c
150
+ /* These are a different encoding (SQSHL/SRSHR/UQSHL/URSHR) */
57
index XXXXXXX..XXXXXXX 100644
151
+ return false;
58
--- a/hw/timer/cmsdk-apb-timer.c
152
+ }
59
+++ b/hw/timer/cmsdk-apb-timer.c
153
+ if (!dc_isar_feature(aa32_mve, s) ||
60
@@ -XXX,XX +XXX,XX @@
154
+ !arm_dc_feature(s, ARM_FEATURE_M_MAIN) ||
61
#include "hw/sysbus.h"
155
+ a->rdahi == 13) {
62
#include "hw/irq.h"
156
+ /* RdaHi == 13 is UNPREDICTABLE; we choose to UNDEF */
63
#include "hw/registerfields.h"
157
+ unallocated_encoding(s);
64
+#include "hw/qdev-clock.h"
158
+ return true;
65
#include "hw/timer/cmsdk-apb-timer.h"
159
+ }
66
#include "migration/vmstate.h"
160
+
67
161
+ if (a->shim == 0) {
68
@@ -XXX,XX +XXX,XX @@ static void cmsdk_apb_timer_init(Object *obj)
162
+ a->shim = 32;
69
s, "cmsdk-apb-timer", 0x1000);
163
+ }
70
sysbus_init_mmio(sbd, &s->iomem);
164
+
71
sysbus_init_irq(sbd, &s->timerint);
165
+ rda = tcg_temp_new_i64();
72
+ s->pclk = qdev_init_clock_in(DEVICE(s), "pclk", NULL, NULL);
166
+ rdalo = load_reg(s, a->rdalo);
73
}
167
+ rdahi = load_reg(s, a->rdahi);
74
168
+ tcg_gen_concat_i32_i64(rda, rdalo, rdahi);
75
static void cmsdk_apb_timer_realize(DeviceState *dev, Error **errp)
169
+
76
@@ -XXX,XX +XXX,XX @@ static void cmsdk_apb_timer_realize(DeviceState *dev, Error **errp)
170
+ fn(rda, rda, a->shim);
77
171
+
78
static const VMStateDescription cmsdk_apb_timer_vmstate = {
172
+ tcg_gen_extrl_i64_i32(rdalo, rda);
79
.name = "cmsdk-apb-timer",
173
+ tcg_gen_extrh_i64_i32(rdahi, rda);
80
- .version_id = 1,
174
+ store_reg(s, a->rdalo, rdalo);
81
- .minimum_version_id = 1,
175
+ store_reg(s, a->rdahi, rdahi);
82
+ .version_id = 2,
176
+ tcg_temp_free_i64(rda);
83
+ .minimum_version_id = 2,
177
+
84
.fields = (VMStateField[]) {
178
+ return true;
85
VMSTATE_PTIMER(timer, CMSDKAPBTimer),
179
+}
86
+ VMSTATE_CLOCK(pclk, CMSDKAPBTimer),
180
+
87
VMSTATE_UINT32(ctrl, CMSDKAPBTimer),
181
+static bool trans_ASRL_ri(DisasContext *s, arg_mve_shl_ri *a)
88
VMSTATE_UINT32(value, CMSDKAPBTimer),
182
+{
89
VMSTATE_UINT32(reload, CMSDKAPBTimer),
183
+ return do_mve_shl_ri(s, a, tcg_gen_sari_i64);
184
+}
185
+
186
+static bool trans_LSLL_ri(DisasContext *s, arg_mve_shl_ri *a)
187
+{
188
+ return do_mve_shl_ri(s, a, tcg_gen_shli_i64);
189
+}
190
+
191
+static bool trans_LSRL_ri(DisasContext *s, arg_mve_shl_ri *a)
192
+{
193
+ return do_mve_shl_ri(s, a, tcg_gen_shri_i64);
194
+}
195
+
196
+static void gen_mve_sqshll(TCGv_i64 r, TCGv_i64 n, int64_t shift)
197
+{
198
+ gen_helper_mve_sqshll(r, cpu_env, n, tcg_constant_i32(shift));
199
+}
200
+
201
+static bool trans_SQSHLL_ri(DisasContext *s, arg_mve_shl_ri *a)
202
+{
203
+ return do_mve_shl_ri(s, a, gen_mve_sqshll);
204
+}
205
+
206
+static void gen_mve_uqshll(TCGv_i64 r, TCGv_i64 n, int64_t shift)
207
+{
208
+ gen_helper_mve_uqshll(r, cpu_env, n, tcg_constant_i32(shift));
209
+}
210
+
211
+static bool trans_UQSHLL_ri(DisasContext *s, arg_mve_shl_ri *a)
212
+{
213
+ return do_mve_shl_ri(s, a, gen_mve_uqshll);
214
+}
215
+
216
+static bool trans_SRSHRL_ri(DisasContext *s, arg_mve_shl_ri *a)
217
+{
218
+ return do_mve_shl_ri(s, a, gen_srshr64_i64);
219
+}
220
+
221
+static bool trans_URSHRL_ri(DisasContext *s, arg_mve_shl_ri *a)
222
+{
223
+ return do_mve_shl_ri(s, a, gen_urshr64_i64);
224
+}
225
+
226
/*
227
* Multiply and multiply accumulate
228
*/
90
--
229
--
91
2.20.1
230
2.20.1
92
231
93
232
diff view generated by jsdifflib
[PULL 30/46] hw/watchdog/cmsdk-apb-watchdog: Add Clock input
[PULL 22/24] target/arm: Implement MVE long shifts by register
1
As the first step in converting the CMSDK_APB_TIMER device to the
1
Implement the MVE long shifts by register, which perform shifts on a
2
Clock framework, add a Clock input. For the moment we do nothing
2
pair of general-purpose registers treated as a 64-bit quantity, with
3
with this clock; we will change the behaviour from using the
3
the shift count in another general-purpose register, which might be
4
wdogclk-frq property to using the Clock once all the users of this
4
either positive or negative.
5
device have been converted to wire up the Clock.
5
6
6
Like the long-shifts-by-immediate, these encodings sit in the space
7
This is a migration compatibility break for machines mps2-an385,
7
that was previously the UNPREDICTABLE MOVS/ORRS with Rm==13,15.
8
mps2-an386, mps2-an500, mps2-an511, mps2-an505, mps2-an521, musca-a,
8
Because LSLL_rr and ASRL_rr overlap with both MOV_rxri/ORR_rrri and
9
musca-b1, lm3s811evb, lm3s6965evb.
9
also with CSEL (as one of the previously-UNPREDICTABLE Rm==13 cases),
10
we have to move the CSEL pattern into the same decodetree group.
10
11
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
13
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
13
Reviewed-by: Luc Michel <luc@lmichel.fr>
14
Message-id: 20210628135835.6690-17-peter.maydell@linaro.org
14
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
15
Message-id: 20210128114145.20536-10-peter.maydell@linaro.org
16
Message-id: 20210121190622.22000-10-peter.maydell@linaro.org
17
---
15
---
18
include/hw/watchdog/cmsdk-apb-watchdog.h | 3 +++
16
target/arm/helper-mve.h | 6 +++
19
hw/watchdog/cmsdk-apb-watchdog.c | 7 +++++--
17
target/arm/translate.h | 1 +
20
2 files changed, 8 insertions(+), 2 deletions(-)
18
target/arm/t32.decode | 16 +++++--
21
19
target/arm/mve_helper.c | 93 +++++++++++++++++++++++++++++++++++++++++
22
diff --git a/include/hw/watchdog/cmsdk-apb-watchdog.h b/include/hw/watchdog/cmsdk-apb-watchdog.h
20
target/arm/translate.c | 69 ++++++++++++++++++++++++++++++
23
index XXXXXXX..XXXXXXX 100644
21
5 files changed, 182 insertions(+), 3 deletions(-)
24
--- a/include/hw/watchdog/cmsdk-apb-watchdog.h
22
25
+++ b/include/hw/watchdog/cmsdk-apb-watchdog.h
23
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
24
index XXXXXXX..XXXXXXX 100644
25
--- a/target/arm/helper-mve.h
26
+++ b/target/arm/helper-mve.h
27
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vqrshrunth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
28
29
DEF_HELPER_FLAGS_4(mve_vshlc, TCG_CALL_NO_WG, i32, env, ptr, i32, i32)
30
31
+DEF_HELPER_FLAGS_3(mve_sshrl, TCG_CALL_NO_RWG, i64, env, i64, i32)
32
+DEF_HELPER_FLAGS_3(mve_ushll, TCG_CALL_NO_RWG, i64, env, i64, i32)
33
DEF_HELPER_FLAGS_3(mve_sqshll, TCG_CALL_NO_RWG, i64, env, i64, i32)
34
DEF_HELPER_FLAGS_3(mve_uqshll, TCG_CALL_NO_RWG, i64, env, i64, i32)
35
+DEF_HELPER_FLAGS_3(mve_sqrshrl, TCG_CALL_NO_RWG, i64, env, i64, i32)
36
+DEF_HELPER_FLAGS_3(mve_uqrshll, TCG_CALL_NO_RWG, i64, env, i64, i32)
37
+DEF_HELPER_FLAGS_3(mve_sqrshrl48, TCG_CALL_NO_RWG, i64, env, i64, i32)
38
+DEF_HELPER_FLAGS_3(mve_uqrshll48, TCG_CALL_NO_RWG, i64, env, i64, i32)
39
diff --git a/target/arm/translate.h b/target/arm/translate.h
40
index XXXXXXX..XXXXXXX 100644
41
--- a/target/arm/translate.h
42
+++ b/target/arm/translate.h
43
@@ -XXX,XX +XXX,XX @@ typedef void CryptoThreeOpIntFn(TCGv_ptr, TCGv_ptr, TCGv_i32);
44
typedef void CryptoThreeOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr);
45
typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp);
46
typedef void WideShiftImmFn(TCGv_i64, TCGv_i64, int64_t shift);
47
+typedef void WideShiftFn(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i32);
48
49
/**
50
* arm_tbflags_from_tb:
51
diff --git a/target/arm/t32.decode b/target/arm/t32.decode
52
index XXXXXXX..XXXXXXX 100644
53
--- a/target/arm/t32.decode
54
+++ b/target/arm/t32.decode
26
@@ -XXX,XX +XXX,XX @@
55
@@ -XXX,XX +XXX,XX @@
27
*
56
&mcrr !extern cp opc1 crm rt rt2
28
* QEMU interface:
57
29
* + QOM property "wdogclk-frq": frequency at which the watchdog is clocked
58
&mve_shl_ri rdalo rdahi shim
30
+ * + Clock input "WDOGCLK": clock for the watchdog's timer
59
+&mve_shl_rr rdalo rdahi rm
31
* + sysbus MMIO region 0: the register bank
60
32
* + sysbus IRQ 0: watchdog interrupt
61
# rdahi: bits [3:1] from insn, bit 0 is 1
33
*
62
# rdalo: bits [3:1] from insn, bit 0 is 0
34
@@ -XXX,XX +XXX,XX @@
63
@@ -XXX,XX +XXX,XX @@
35
64
36
#include "hw/sysbus.h"
65
@mve_shl_ri ....... .... . ... . . ... ... . .. .. .... \
37
#include "hw/ptimer.h"
66
&mve_shl_ri shim=%imm5_12_6 rdalo=%rdalo_17 rdahi=%rdahi_9
38
+#include "hw/clock.h"
67
+@mve_shl_rr ....... .... . ... . rm:4 ... . .. .. .... \
39
#include "qom/object.h"
68
+ &mve_shl_rr rdalo=%rdalo_17 rdahi=%rdahi_9
40
69
41
#define TYPE_CMSDK_APB_WATCHDOG "cmsdk-apb-watchdog"
70
{
42
@@ -XXX,XX +XXX,XX @@ struct CMSDKAPBWatchdog {
71
TST_xrri 1110101 0000 1 .... 0 ... 1111 .... .... @S_xrr_shi
43
uint32_t wdogclk_frq;
72
@@ -XXX,XX +XXX,XX @@ BIC_rrri 1110101 0001 . .... 0 ... .... .... .... @s_rrr_shi
44
bool is_luminary;
73
URSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 01 1111 @mve_shl_ri
45
struct ptimer_state *timer;
74
SRSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 10 1111 @mve_shl_ri
46
+ Clock *wdogclk;
75
SQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 11 1111 @mve_shl_ri
47
76
+
48
uint32_t control;
77
+ LSLL_rr 1110101 0010 1 ... 0 .... ... 1 0000 1101 @mve_shl_rr
49
uint32_t intstatus;
78
+ ASRL_rr 1110101 0010 1 ... 0 .... ... 1 0010 1101 @mve_shl_rr
50
diff --git a/hw/watchdog/cmsdk-apb-watchdog.c b/hw/watchdog/cmsdk-apb-watchdog.c
79
+ UQRSHLL64_rr 1110101 0010 1 ... 1 .... ... 1 0000 1101 @mve_shl_rr
51
index XXXXXXX..XXXXXXX 100644
80
+ SQRSHRL64_rr 1110101 0010 1 ... 1 .... ... 1 0010 1101 @mve_shl_rr
52
--- a/hw/watchdog/cmsdk-apb-watchdog.c
81
+ UQRSHLL48_rr 1110101 0010 1 ... 1 .... ... 1 1000 1101 @mve_shl_rr
53
+++ b/hw/watchdog/cmsdk-apb-watchdog.c
82
+ SQRSHRL48_rr 1110101 0010 1 ... 1 .... ... 1 1010 1101 @mve_shl_rr
54
@@ -XXX,XX +XXX,XX @@
83
]
55
#include "hw/irq.h"
84
56
#include "hw/qdev-properties.h"
85
MOV_rxri 1110101 0010 . 1111 0 ... .... .... .... @s_rxr_shi
57
#include "hw/registerfields.h"
86
ORR_rrri 1110101 0010 . .... 0 ... .... .... .... @s_rrr_shi
58
+#include "hw/qdev-clock.h"
87
+
59
#include "hw/watchdog/cmsdk-apb-watchdog.h"
88
+ # v8.1M CSEL and friends
60
#include "migration/vmstate.h"
89
+ CSEL 1110101 0010 1 rn:4 10 op:2 rd:4 fcond:4 rm:4
61
90
}
62
@@ -XXX,XX +XXX,XX @@ static void cmsdk_apb_watchdog_init(Object *obj)
91
{
63
s, "cmsdk-apb-watchdog", 0x1000);
92
MVN_rxri 1110101 0011 . 1111 0 ... .... .... .... @s_rxr_shi
64
sysbus_init_mmio(sbd, &s->iomem);
93
@@ -XXX,XX +XXX,XX @@ SBC_rrri 1110101 1011 . .... 0 ... .... .... .... @s_rrr_shi
65
sysbus_init_irq(sbd, &s->wdogint);
94
}
66
+ s->wdogclk = qdev_init_clock_in(DEVICE(s), "WDOGCLK", NULL, NULL);
95
RSB_rrri 1110101 1110 . .... 0 ... .... .... .... @s_rrr_shi
67
96
68
s->is_luminary = false;
97
-# v8.1M CSEL and friends
69
s->id = cmsdk_apb_watchdog_id;
98
-CSEL 1110101 0010 1 rn:4 10 op:2 rd:4 fcond:4 rm:4
70
@@ -XXX,XX +XXX,XX @@ static void cmsdk_apb_watchdog_realize(DeviceState *dev, Error **errp)
99
-
71
100
# Data-processing (register-shifted register)
72
static const VMStateDescription cmsdk_apb_watchdog_vmstate = {
101
73
.name = "cmsdk-apb-watchdog",
102
MOV_rxrr 1111 1010 0 shty:2 s:1 rm:4 1111 rd:4 0000 rs:4 \
74
- .version_id = 1,
103
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
75
- .minimum_version_id = 1,
104
index XXXXXXX..XXXXXXX 100644
76
+ .version_id = 2,
105
--- a/target/arm/mve_helper.c
77
+ .minimum_version_id = 2,
106
+++ b/target/arm/mve_helper.c
78
.fields = (VMStateField[]) {
107
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(mve_vshlc)(CPUARMState *env, void *vd, uint32_t rdm,
79
+ VMSTATE_CLOCK(wdogclk, CMSDKAPBWatchdog),
108
return rdm;
80
VMSTATE_PTIMER(timer, CMSDKAPBWatchdog),
109
}
81
VMSTATE_UINT32(control, CMSDKAPBWatchdog),
110
82
VMSTATE_UINT32(intstatus, CMSDKAPBWatchdog),
111
+uint64_t HELPER(mve_sshrl)(CPUARMState *env, uint64_t n, uint32_t shift)
112
+{
113
+ return do_sqrshl_d(n, -(int8_t)shift, false, NULL);
114
+}
115
+
116
+uint64_t HELPER(mve_ushll)(CPUARMState *env, uint64_t n, uint32_t shift)
117
+{
118
+ return do_uqrshl_d(n, (int8_t)shift, false, NULL);
119
+}
120
+
121
uint64_t HELPER(mve_sqshll)(CPUARMState *env, uint64_t n, uint32_t shift)
122
{
123
return do_sqrshl_d(n, (int8_t)shift, false, &env->QF);
124
@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(mve_uqshll)(CPUARMState *env, uint64_t n, uint32_t shift)
125
{
126
return do_uqrshl_d(n, (int8_t)shift, false, &env->QF);
127
}
128
+
129
+uint64_t HELPER(mve_sqrshrl)(CPUARMState *env, uint64_t n, uint32_t shift)
130
+{
131
+ return do_sqrshl_d(n, -(int8_t)shift, true, &env->QF);
132
+}
133
+
134
+uint64_t HELPER(mve_uqrshll)(CPUARMState *env, uint64_t n, uint32_t shift)
135
+{
136
+ return do_uqrshl_d(n, (int8_t)shift, true, &env->QF);
137
+}
138
+
139
+/* Operate on 64-bit values, but saturate at 48 bits */
140
+static inline int64_t do_sqrshl48_d(int64_t src, int64_t shift,
141
+ bool round, uint32_t *sat)
142
+{
143
+ if (shift <= -48) {
144
+ /* Rounding the sign bit always produces 0. */
145
+ if (round) {
146
+ return 0;
147
+ }
148
+ return src >> 63;
149
+ } else if (shift < 0) {
150
+ if (round) {
151
+ src >>= -shift - 1;
152
+ return (src >> 1) + (src & 1);
153
+ }
154
+ return src >> -shift;
155
+ } else if (shift < 48) {
156
+ int64_t val = src << shift;
157
+ int64_t extval = sextract64(val, 0, 48);
158
+ if (!sat || val == extval) {
159
+ return extval;
160
+ }
161
+ } else if (!sat || src == 0) {
162
+ return 0;
163
+ }
164
+
165
+ *sat = 1;
166
+ return (1ULL << 47) - (src >= 0);
167
+}
168
+
169
+/* Operate on 64-bit values, but saturate at 48 bits */
170
+static inline uint64_t do_uqrshl48_d(uint64_t src, int64_t shift,
171
+ bool round, uint32_t *sat)
172
+{
173
+ uint64_t val, extval;
174
+
175
+ if (shift <= -(48 + round)) {
176
+ return 0;
177
+ } else if (shift < 0) {
178
+ if (round) {
179
+ val = src >> (-shift - 1);
180
+ val = (val >> 1) + (val & 1);
181
+ } else {
182
+ val = src >> -shift;
183
+ }
184
+ extval = extract64(val, 0, 48);
185
+ if (!sat || val == extval) {
186
+ return extval;
187
+ }
188
+ } else if (shift < 48) {
189
+ uint64_t val = src << shift;
190
+ uint64_t extval = extract64(val, 0, 48);
191
+ if (!sat || val == extval) {
192
+ return extval;
193
+ }
194
+ } else if (!sat || src == 0) {
195
+ return 0;
196
+ }
197
+
198
+ *sat = 1;
199
+ return MAKE_64BIT_MASK(0, 48);
200
+}
201
+
202
+uint64_t HELPER(mve_sqrshrl48)(CPUARMState *env, uint64_t n, uint32_t shift)
203
+{
204
+ return do_sqrshl48_d(n, -(int8_t)shift, true, &env->QF);
205
+}
206
+
207
+uint64_t HELPER(mve_uqrshll48)(CPUARMState *env, uint64_t n, uint32_t shift)
208
+{
209
+ return do_uqrshl48_d(n, (int8_t)shift, true, &env->QF);
210
+}
211
diff --git a/target/arm/translate.c b/target/arm/translate.c
212
index XXXXXXX..XXXXXXX 100644
213
--- a/target/arm/translate.c
214
+++ b/target/arm/translate.c
215
@@ -XXX,XX +XXX,XX @@ static bool trans_URSHRL_ri(DisasContext *s, arg_mve_shl_ri *a)
216
return do_mve_shl_ri(s, a, gen_urshr64_i64);
217
}
218
219
+static bool do_mve_shl_rr(DisasContext *s, arg_mve_shl_rr *a, WideShiftFn *fn)
220
+{
221
+ TCGv_i64 rda;
222
+ TCGv_i32 rdalo, rdahi;
223
+
224
+ if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) {
225
+ /* Decode falls through to ORR/MOV UNPREDICTABLE handling */
226
+ return false;
227
+ }
228
+ if (a->rdahi == 15) {
229
+ /* These are a different encoding (SQSHL/SRSHR/UQSHL/URSHR) */
230
+ return false;
231
+ }
232
+ if (!dc_isar_feature(aa32_mve, s) ||
233
+ !arm_dc_feature(s, ARM_FEATURE_M_MAIN) ||
234
+ a->rdahi == 13 || a->rm == 13 || a->rm == 15 ||
235
+ a->rm == a->rdahi || a->rm == a->rdalo) {
236
+ /* These rdahi/rdalo/rm cases are UNPREDICTABLE; we choose to UNDEF */
237
+ unallocated_encoding(s);
238
+ return true;
239
+ }
240
+
241
+ rda = tcg_temp_new_i64();
242
+ rdalo = load_reg(s, a->rdalo);
243
+ rdahi = load_reg(s, a->rdahi);
244
+ tcg_gen_concat_i32_i64(rda, rdalo, rdahi);
245
+
246
+ /* The helper takes care of the sign-extension of the low 8 bits of Rm */
247
+ fn(rda, cpu_env, rda, cpu_R[a->rm]);
248
+
249
+ tcg_gen_extrl_i64_i32(rdalo, rda);
250
+ tcg_gen_extrh_i64_i32(rdahi, rda);
251
+ store_reg(s, a->rdalo, rdalo);
252
+ store_reg(s, a->rdahi, rdahi);
253
+ tcg_temp_free_i64(rda);
254
+
255
+ return true;
256
+}
257
+
258
+static bool trans_LSLL_rr(DisasContext *s, arg_mve_shl_rr *a)
259
+{
260
+ return do_mve_shl_rr(s, a, gen_helper_mve_ushll);
261
+}
262
+
263
+static bool trans_ASRL_rr(DisasContext *s, arg_mve_shl_rr *a)
264
+{
265
+ return do_mve_shl_rr(s, a, gen_helper_mve_sshrl);
266
+}
267
+
268
+static bool trans_UQRSHLL64_rr(DisasContext *s, arg_mve_shl_rr *a)
269
+{
270
+ return do_mve_shl_rr(s, a, gen_helper_mve_uqrshll);
271
+}
272
+
273
+static bool trans_SQRSHRL64_rr(DisasContext *s, arg_mve_shl_rr *a)
274
+{
275
+ return do_mve_shl_rr(s, a, gen_helper_mve_sqrshrl);
276
+}
277
+
278
+static bool trans_UQRSHLL48_rr(DisasContext *s, arg_mve_shl_rr *a)
279
+{
280
+ return do_mve_shl_rr(s, a, gen_helper_mve_uqrshll48);
281
+}
282
+
283
+static bool trans_SQRSHRL48_rr(DisasContext *s, arg_mve_shl_rr *a)
284
+{
285
+ return do_mve_shl_rr(s, a, gen_helper_mve_sqrshrl48);
286
+}
287
+
288
/*
289
* Multiply and multiply accumulate
290
*/
83
--
291
--
84
2.20.1
292
2.20.1
85
293
86
294
diff view generated by jsdifflib
[PULL 39/46] hw/timer/cmsdk-apb-timer: Convert to use Clock input
[PULL 23/24] target/arm: Implement MVE shifts by immediate
1
Switch the CMSDK APB timer device over to using its Clock input; the
1
Implement the MVE shifts by immediate, which perform shifts
2
pclk-frq property is now ignored.
2
on a single general-purpose register.
3
4
These patterns overlap with the long-shift-by-immediates,
5
so we have to rearrange the grouping a little here.
3
6
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Reviewed-by: Luc Michel <luc@lmichel.fr>
9
Message-id: 20210628135835.6690-18-peter.maydell@linaro.org
7
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Message-id: 20210128114145.20536-19-peter.maydell@linaro.org
9
Message-id: 20210121190622.22000-19-peter.maydell@linaro.org
10
---
10
---
11
hw/timer/cmsdk-apb-timer.c | 18 ++++++++++++++----
11
target/arm/helper-mve.h | 3 ++
12
1 file changed, 14 insertions(+), 4 deletions(-)
12
target/arm/translate.h | 1 +
13
13
target/arm/t32.decode | 31 ++++++++++++++-----
14
diff --git a/hw/timer/cmsdk-apb-timer.c b/hw/timer/cmsdk-apb-timer.c
14
target/arm/mve_helper.c | 10 ++++++
15
index XXXXXXX..XXXXXXX 100644
15
target/arm/translate.c | 68 +++++++++++++++++++++++++++++++++++++++--
16
--- a/hw/timer/cmsdk-apb-timer.c
16
5 files changed, 104 insertions(+), 9 deletions(-)
17
+++ b/hw/timer/cmsdk-apb-timer.c
17
18
@@ -XXX,XX +XXX,XX @@ static void cmsdk_apb_timer_reset(DeviceState *dev)
18
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
19
ptimer_transaction_commit(s->timer);
19
index XXXXXXX..XXXXXXX 100644
20
--- a/target/arm/helper-mve.h
21
+++ b/target/arm/helper-mve.h
22
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_sqrshrl, TCG_CALL_NO_RWG, i64, env, i64, i32)
23
DEF_HELPER_FLAGS_3(mve_uqrshll, TCG_CALL_NO_RWG, i64, env, i64, i32)
24
DEF_HELPER_FLAGS_3(mve_sqrshrl48, TCG_CALL_NO_RWG, i64, env, i64, i32)
25
DEF_HELPER_FLAGS_3(mve_uqrshll48, TCG_CALL_NO_RWG, i64, env, i64, i32)
26
+
27
+DEF_HELPER_FLAGS_3(mve_uqshl, TCG_CALL_NO_RWG, i32, env, i32, i32)
28
+DEF_HELPER_FLAGS_3(mve_sqshl, TCG_CALL_NO_RWG, i32, env, i32, i32)
29
diff --git a/target/arm/translate.h b/target/arm/translate.h
30
index XXXXXXX..XXXXXXX 100644
31
--- a/target/arm/translate.h
32
+++ b/target/arm/translate.h
33
@@ -XXX,XX +XXX,XX @@ typedef void CryptoThreeOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr);
34
typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp);
35
typedef void WideShiftImmFn(TCGv_i64, TCGv_i64, int64_t shift);
36
typedef void WideShiftFn(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i32);
37
+typedef void ShiftImmFn(TCGv_i32, TCGv_i32, int32_t shift);
38
39
/**
40
* arm_tbflags_from_tb:
41
diff --git a/target/arm/t32.decode b/target/arm/t32.decode
42
index XXXXXXX..XXXXXXX 100644
43
--- a/target/arm/t32.decode
44
+++ b/target/arm/t32.decode
45
@@ -XXX,XX +XXX,XX @@
46
47
&mve_shl_ri rdalo rdahi shim
48
&mve_shl_rr rdalo rdahi rm
49
+&mve_sh_ri rda shim
50
51
# rdahi: bits [3:1] from insn, bit 0 is 1
52
# rdalo: bits [3:1] from insn, bit 0 is 0
53
@@ -XXX,XX +XXX,XX @@
54
&mve_shl_ri shim=%imm5_12_6 rdalo=%rdalo_17 rdahi=%rdahi_9
55
@mve_shl_rr ....... .... . ... . rm:4 ... . .. .. .... \
56
&mve_shl_rr rdalo=%rdalo_17 rdahi=%rdahi_9
57
+@mve_sh_ri ....... .... . rda:4 . ... ... . .. .. .... \
58
+ &mve_sh_ri shim=%imm5_12_6
59
60
{
61
TST_xrri 1110101 0000 1 .... 0 ... 1111 .... .... @S_xrr_shi
62
@@ -XXX,XX +XXX,XX @@ BIC_rrri 1110101 0001 . .... 0 ... .... .... .... @s_rrr_shi
63
# the rest fall through (where ORR_rrri and MOV_rxri will end up
64
# handling them as r13 and r15 accesses with the same semantics as A32).
65
[
66
- LSLL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 00 1111 @mve_shl_ri
67
- LSRL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 01 1111 @mve_shl_ri
68
- ASRL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 10 1111 @mve_shl_ri
69
+ {
70
+ UQSHL_ri 1110101 0010 1 .... 0 ... 1111 .. 00 1111 @mve_sh_ri
71
+ LSLL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 00 1111 @mve_shl_ri
72
+ UQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 00 1111 @mve_shl_ri
73
+ }
74
75
- UQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 00 1111 @mve_shl_ri
76
- URSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 01 1111 @mve_shl_ri
77
- SRSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 10 1111 @mve_shl_ri
78
- SQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 11 1111 @mve_shl_ri
79
+ {
80
+ URSHR_ri 1110101 0010 1 .... 0 ... 1111 .. 01 1111 @mve_sh_ri
81
+ LSRL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 01 1111 @mve_shl_ri
82
+ URSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 01 1111 @mve_shl_ri
83
+ }
84
+
85
+ {
86
+ SRSHR_ri 1110101 0010 1 .... 0 ... 1111 .. 10 1111 @mve_sh_ri
87
+ ASRL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 10 1111 @mve_shl_ri
88
+ SRSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 10 1111 @mve_shl_ri
89
+ }
90
+
91
+ {
92
+ SQSHL_ri 1110101 0010 1 .... 0 ... 1111 .. 11 1111 @mve_sh_ri
93
+ SQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 11 1111 @mve_shl_ri
94
+ }
95
96
LSLL_rr 1110101 0010 1 ... 0 .... ... 1 0000 1101 @mve_shl_rr
97
ASRL_rr 1110101 0010 1 ... 0 .... ... 1 0010 1101 @mve_shl_rr
98
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
99
index XXXXXXX..XXXXXXX 100644
100
--- a/target/arm/mve_helper.c
101
+++ b/target/arm/mve_helper.c
102
@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(mve_uqrshll48)(CPUARMState *env, uint64_t n, uint32_t shift)
103
{
104
return do_uqrshl48_d(n, (int8_t)shift, true, &env->QF);
20
}
105
}
21
106
+
22
+static void cmsdk_apb_timer_clk_update(void *opaque)
107
+uint32_t HELPER(mve_uqshl)(CPUARMState *env, uint32_t n, uint32_t shift)
23
+{
108
+{
24
+ CMSDKAPBTimer *s = CMSDK_APB_TIMER(opaque);
109
+ return do_uqrshl_bhs(n, (int8_t)shift, 32, false, &env->QF);
25
+
110
+}
26
+ ptimer_transaction_begin(s->timer);
111
+
27
+ ptimer_set_period_from_clock(s->timer, s->pclk, 1);
112
+uint32_t HELPER(mve_sqshl)(CPUARMState *env, uint32_t n, uint32_t shift)
28
+ ptimer_transaction_commit(s->timer);
113
+{
29
+}
114
+ return do_sqrshl_bhs(n, (int8_t)shift, 32, false, &env->QF);
30
+
115
+}
31
static void cmsdk_apb_timer_init(Object *obj)
116
diff --git a/target/arm/translate.c b/target/arm/translate.c
32
{
117
index XXXXXXX..XXXXXXX 100644
33
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
118
--- a/target/arm/translate.c
34
@@ -XXX,XX +XXX,XX @@ static void cmsdk_apb_timer_init(Object *obj)
119
+++ b/target/arm/translate.c
35
s, "cmsdk-apb-timer", 0x1000);
120
@@ -XXX,XX +XXX,XX @@ static void gen_srshr16_i64(TCGv_i64 d, TCGv_i64 a, int64_t sh)
36
sysbus_init_mmio(sbd, &s->iomem);
121
37
sysbus_init_irq(sbd, &s->timerint);
122
static void gen_srshr32_i32(TCGv_i32 d, TCGv_i32 a, int32_t sh)
38
- s->pclk = qdev_init_clock_in(DEVICE(s), "pclk", NULL, NULL);
123
{
39
+ s->pclk = qdev_init_clock_in(DEVICE(s), "pclk",
124
- TCGv_i32 t = tcg_temp_new_i32();
40
+ cmsdk_apb_timer_clk_update, s);
125
+ TCGv_i32 t;
126
127
+ /* Handle shift by the input size for the benefit of trans_SRSHR_ri */
128
+ if (sh == 32) {
129
+ tcg_gen_movi_i32(d, 0);
130
+ return;
131
+ }
132
+ t = tcg_temp_new_i32();
133
tcg_gen_extract_i32(t, a, sh - 1, 1);
134
tcg_gen_sari_i32(d, a, sh);
135
tcg_gen_add_i32(d, d, t);
136
@@ -XXX,XX +XXX,XX @@ static void gen_urshr16_i64(TCGv_i64 d, TCGv_i64 a, int64_t sh)
137
138
static void gen_urshr32_i32(TCGv_i32 d, TCGv_i32 a, int32_t sh)
139
{
140
- TCGv_i32 t = tcg_temp_new_i32();
141
+ TCGv_i32 t;
142
143
+ /* Handle shift by the input size for the benefit of trans_URSHR_ri */
144
+ if (sh == 32) {
145
+ tcg_gen_extract_i32(d, a, sh - 1, 1);
146
+ return;
147
+ }
148
+ t = tcg_temp_new_i32();
149
tcg_gen_extract_i32(t, a, sh - 1, 1);
150
tcg_gen_shri_i32(d, a, sh);
151
tcg_gen_add_i32(d, d, t);
152
@@ -XXX,XX +XXX,XX @@ static bool trans_SQRSHRL48_rr(DisasContext *s, arg_mve_shl_rr *a)
153
return do_mve_shl_rr(s, a, gen_helper_mve_sqrshrl48);
41
}
154
}
42
155
43
static void cmsdk_apb_timer_realize(DeviceState *dev, Error **errp)
156
+static bool do_mve_sh_ri(DisasContext *s, arg_mve_sh_ri *a, ShiftImmFn *fn)
44
{
157
+{
45
CMSDKAPBTimer *s = CMSDK_APB_TIMER(dev);
158
+ if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) {
46
159
+ /* Decode falls through to ORR/MOV UNPREDICTABLE handling */
47
- if (s->pclk_frq == 0) {
160
+ return false;
48
- error_setg(errp, "CMSDK APB timer: pclk-frq property must be set");
161
+ }
49
+ if (!clock_has_source(s->pclk)) {
162
+ if (!dc_isar_feature(aa32_mve, s) ||
50
+ error_setg(errp, "CMSDK APB timer: pclk clock must be connected");
163
+ !arm_dc_feature(s, ARM_FEATURE_M_MAIN) ||
51
return;
164
+ a->rda == 13 || a->rda == 15) {
52
}
165
+ /* These rda cases are UNPREDICTABLE; we choose to UNDEF */
53
166
+ unallocated_encoding(s);
54
@@ -XXX,XX +XXX,XX @@ static void cmsdk_apb_timer_realize(DeviceState *dev, Error **errp)
167
+ return true;
55
PTIMER_POLICY_NO_COUNTER_ROUND_DOWN);
168
+ }
56
169
+
57
ptimer_transaction_begin(s->timer);
170
+ if (a->shim == 0) {
58
- ptimer_set_freq(s->timer, s->pclk_frq);
171
+ a->shim = 32;
59
+ ptimer_set_period_from_clock(s->timer, s->pclk, 1);
172
+ }
60
ptimer_transaction_commit(s->timer);
173
+ fn(cpu_R[a->rda], cpu_R[a->rda], a->shim);
61
}
174
+
62
175
+ return true;
176
+}
177
+
178
+static bool trans_URSHR_ri(DisasContext *s, arg_mve_sh_ri *a)
179
+{
180
+ return do_mve_sh_ri(s, a, gen_urshr32_i32);
181
+}
182
+
183
+static bool trans_SRSHR_ri(DisasContext *s, arg_mve_sh_ri *a)
184
+{
185
+ return do_mve_sh_ri(s, a, gen_srshr32_i32);
186
+}
187
+
188
+static void gen_mve_sqshl(TCGv_i32 r, TCGv_i32 n, int32_t shift)
189
+{
190
+ gen_helper_mve_sqshl(r, cpu_env, n, tcg_constant_i32(shift));
191
+}
192
+
193
+static bool trans_SQSHL_ri(DisasContext *s, arg_mve_sh_ri *a)
194
+{
195
+ return do_mve_sh_ri(s, a, gen_mve_sqshl);
196
+}
197
+
198
+static void gen_mve_uqshl(TCGv_i32 r, TCGv_i32 n, int32_t shift)
199
+{
200
+ gen_helper_mve_uqshl(r, cpu_env, n, tcg_constant_i32(shift));
201
+}
202
+
203
+static bool trans_UQSHL_ri(DisasContext *s, arg_mve_sh_ri *a)
204
+{
205
+ return do_mve_sh_ri(s, a, gen_mve_uqshl);
206
+}
207
+
208
/*
209
* Multiply and multiply accumulate
210
*/
63
--
211
--
64
2.20.1
212
2.20.1
65
213
66
214
diff view generated by jsdifflib
[PULL 04/46] hw: gpio: implement gpio-pwr driver for qemu reset/poweroff
[PULL 24/24] target/arm: Implement MVE shifts by register
1
From: Maxim Uvarov <maxim.uvarov@linaro.org>
1
Implement the MVE shifts by register, which perform
2
shifts on a single general-purpose register.
2
3
3
Implement gpio-pwr driver to allow reboot and poweroff machine.
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
This is simple driver with just 2 gpios lines. Current use case
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
is to reboot and poweroff virt machine in secure mode. Secure
6
Message-id: 20210628135835.6690-19-peter.maydell@linaro.org
6
pl066 gpio chip is needed for that.
7
---
8
target/arm/helper-mve.h | 2 ++
9
target/arm/translate.h | 1 +
10
target/arm/t32.decode | 18 ++++++++++++++----
11
target/arm/mve_helper.c | 10 ++++++++++
12
target/arm/translate.c | 30 ++++++++++++++++++++++++++++++
13
5 files changed, 57 insertions(+), 4 deletions(-)
7
14
8
Signed-off-by: Maxim Uvarov <maxim.uvarov@linaro.org>
15
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
9
Reviewed-by: Hao Wu <wuhaotsh@google.com>
16
index XXXXXXX..XXXXXXX 100644
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
17
--- a/target/arm/helper-mve.h
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
+++ b/target/arm/helper-mve.h
12
---
19
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_uqrshll48, TCG_CALL_NO_RWG, i64, env, i64, i32)
13
hw/gpio/gpio_pwr.c | 70 +++++++++++++++++++++++++++++++++++++++++++++
20
14
hw/gpio/Kconfig | 3 ++
21
DEF_HELPER_FLAGS_3(mve_uqshl, TCG_CALL_NO_RWG, i32, env, i32, i32)
15
hw/gpio/meson.build | 1 +
22
DEF_HELPER_FLAGS_3(mve_sqshl, TCG_CALL_NO_RWG, i32, env, i32, i32)
16
3 files changed, 74 insertions(+)
23
+DEF_HELPER_FLAGS_3(mve_uqrshl, TCG_CALL_NO_RWG, i32, env, i32, i32)
17
create mode 100644 hw/gpio/gpio_pwr.c
24
+DEF_HELPER_FLAGS_3(mve_sqrshr, TCG_CALL_NO_RWG, i32, env, i32, i32)
18
25
diff --git a/target/arm/translate.h b/target/arm/translate.h
19
diff --git a/hw/gpio/gpio_pwr.c b/hw/gpio/gpio_pwr.c
26
index XXXXXXX..XXXXXXX 100644
20
new file mode 100644
27
--- a/target/arm/translate.h
21
index XXXXXXX..XXXXXXX
28
+++ b/target/arm/translate.h
22
--- /dev/null
29
@@ -XXX,XX +XXX,XX @@ typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp);
23
+++ b/hw/gpio/gpio_pwr.c
30
typedef void WideShiftImmFn(TCGv_i64, TCGv_i64, int64_t shift);
31
typedef void WideShiftFn(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i32);
32
typedef void ShiftImmFn(TCGv_i32, TCGv_i32, int32_t shift);
33
+typedef void ShiftFn(TCGv_i32, TCGv_ptr, TCGv_i32, TCGv_i32);
34
35
/**
36
* arm_tbflags_from_tb:
37
diff --git a/target/arm/t32.decode b/target/arm/t32.decode
38
index XXXXXXX..XXXXXXX 100644
39
--- a/target/arm/t32.decode
40
+++ b/target/arm/t32.decode
24
@@ -XXX,XX +XXX,XX @@
41
@@ -XXX,XX +XXX,XX @@
25
+/*
42
&mve_shl_ri rdalo rdahi shim
26
+ * GPIO qemu power controller
43
&mve_shl_rr rdalo rdahi rm
27
+ *
44
&mve_sh_ri rda shim
28
+ * Copyright (c) 2020 Linaro Limited
45
+&mve_sh_rr rda rm
29
+ *
46
30
+ * Author: Maxim Uvarov <maxim.uvarov@linaro.org>
47
# rdahi: bits [3:1] from insn, bit 0 is 1
31
+ *
48
# rdalo: bits [3:1] from insn, bit 0 is 0
32
+ * Virtual gpio driver which can be used on top of pl061
49
@@ -XXX,XX +XXX,XX @@
33
+ * to reboot and shutdown qemu virtual machine. One of use
50
&mve_shl_rr rdalo=%rdalo_17 rdahi=%rdahi_9
34
+ * case is gpio driver for secure world application (ARM
51
@mve_sh_ri ....... .... . rda:4 . ... ... . .. .. .... \
35
+ * Trusted Firmware.).
52
&mve_sh_ri shim=%imm5_12_6
36
+ *
53
+@mve_sh_rr ....... .... . rda:4 rm:4 .... .... .... &mve_sh_rr
37
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
54
38
+ * See the COPYING file in the top-level directory.
55
{
39
+ * SPDX-License-Identifier: GPL-2.0-or-later
56
TST_xrri 1110101 0000 1 .... 0 ... 1111 .... .... @S_xrr_shi
40
+ */
57
@@ -XXX,XX +XXX,XX @@ BIC_rrri 1110101 0001 . .... 0 ... .... .... .... @s_rrr_shi
58
SQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 11 1111 @mve_shl_ri
59
}
60
61
- LSLL_rr 1110101 0010 1 ... 0 .... ... 1 0000 1101 @mve_shl_rr
62
- ASRL_rr 1110101 0010 1 ... 0 .... ... 1 0010 1101 @mve_shl_rr
63
- UQRSHLL64_rr 1110101 0010 1 ... 1 .... ... 1 0000 1101 @mve_shl_rr
64
- SQRSHRL64_rr 1110101 0010 1 ... 1 .... ... 1 0010 1101 @mve_shl_rr
65
+ {
66
+ UQRSHL_rr 1110101 0010 1 .... .... 1111 0000 1101 @mve_sh_rr
67
+ LSLL_rr 1110101 0010 1 ... 0 .... ... 1 0000 1101 @mve_shl_rr
68
+ UQRSHLL64_rr 1110101 0010 1 ... 1 .... ... 1 0000 1101 @mve_shl_rr
69
+ }
41
+
70
+
42
+/*
71
+ {
43
+ * QEMU interface:
72
+ SQRSHR_rr 1110101 0010 1 .... .... 1111 0010 1101 @mve_sh_rr
44
+ * two named input GPIO lines:
73
+ ASRL_rr 1110101 0010 1 ... 0 .... ... 1 0010 1101 @mve_shl_rr
45
+ * 'reset' : when asserted, trigger system reset
74
+ SQRSHRL64_rr 1110101 0010 1 ... 1 .... ... 1 0010 1101 @mve_shl_rr
46
+ * 'shutdown' : when asserted, trigger system shutdown
75
+ }
47
+ */
48
+
76
+
49
+#include "qemu/osdep.h"
77
UQRSHLL48_rr 1110101 0010 1 ... 1 .... ... 1 1000 1101 @mve_shl_rr
50
+#include "hw/sysbus.h"
78
SQRSHRL48_rr 1110101 0010 1 ... 1 .... ... 1 1010 1101 @mve_shl_rr
51
+#include "sysemu/runstate.h"
79
]
80
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
81
index XXXXXXX..XXXXXXX 100644
82
--- a/target/arm/mve_helper.c
83
+++ b/target/arm/mve_helper.c
84
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(mve_sqshl)(CPUARMState *env, uint32_t n, uint32_t shift)
85
{
86
return do_sqrshl_bhs(n, (int8_t)shift, 32, false, &env->QF);
87
}
52
+
88
+
53
+#define TYPE_GPIOPWR "gpio-pwr"
89
+uint32_t HELPER(mve_uqrshl)(CPUARMState *env, uint32_t n, uint32_t shift)
54
+OBJECT_DECLARE_SIMPLE_TYPE(GPIO_PWR_State, GPIOPWR)
55
+
56
+struct GPIO_PWR_State {
57
+ SysBusDevice parent_obj;
58
+};
59
+
60
+static void gpio_pwr_reset(void *opaque, int n, int level)
61
+{
90
+{
62
+ if (level) {
91
+ return do_uqrshl_bhs(n, (int8_t)shift, 32, true, &env->QF);
63
+ qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
64
+ }
65
+}
92
+}
66
+
93
+
67
+static void gpio_pwr_shutdown(void *opaque, int n, int level)
94
+uint32_t HELPER(mve_sqrshr)(CPUARMState *env, uint32_t n, uint32_t shift)
68
+{
95
+{
69
+ if (level) {
96
+ return do_sqrshl_bhs(n, -(int8_t)shift, 32, true, &env->QF);
70
+ qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
97
+}
98
diff --git a/target/arm/translate.c b/target/arm/translate.c
99
index XXXXXXX..XXXXXXX 100644
100
--- a/target/arm/translate.c
101
+++ b/target/arm/translate.c
102
@@ -XXX,XX +XXX,XX @@ static bool trans_UQSHL_ri(DisasContext *s, arg_mve_sh_ri *a)
103
return do_mve_sh_ri(s, a, gen_mve_uqshl);
104
}
105
106
+static bool do_mve_sh_rr(DisasContext *s, arg_mve_sh_rr *a, ShiftFn *fn)
107
+{
108
+ if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) {
109
+ /* Decode falls through to ORR/MOV UNPREDICTABLE handling */
110
+ return false;
71
+ }
111
+ }
112
+ if (!dc_isar_feature(aa32_mve, s) ||
113
+ !arm_dc_feature(s, ARM_FEATURE_M_MAIN) ||
114
+ a->rda == 13 || a->rda == 15 || a->rm == 13 || a->rm == 15 ||
115
+ a->rm == a->rda) {
116
+ /* These rda/rm cases are UNPREDICTABLE; we choose to UNDEF */
117
+ unallocated_encoding(s);
118
+ return true;
119
+ }
120
+
121
+ /* The helper takes care of the sign-extension of the low 8 bits of Rm */
122
+ fn(cpu_R[a->rda], cpu_env, cpu_R[a->rda], cpu_R[a->rm]);
123
+ return true;
72
+}
124
+}
73
+
125
+
74
+static void gpio_pwr_init(Object *obj)
126
+static bool trans_SQRSHR_rr(DisasContext *s, arg_mve_sh_rr *a)
75
+{
127
+{
76
+ DeviceState *dev = DEVICE(obj);
128
+ return do_mve_sh_rr(s, a, gen_helper_mve_sqrshr);
77
+
78
+ qdev_init_gpio_in_named(dev, gpio_pwr_reset, "reset", 1);
79
+ qdev_init_gpio_in_named(dev, gpio_pwr_shutdown, "shutdown", 1);
80
+}
129
+}
81
+
130
+
82
+static const TypeInfo gpio_pwr_info = {
131
+static bool trans_UQRSHL_rr(DisasContext *s, arg_mve_sh_rr *a)
83
+ .name = TYPE_GPIOPWR,
84
+ .parent = TYPE_SYS_BUS_DEVICE,
85
+ .instance_size = sizeof(GPIO_PWR_State),
86
+ .instance_init = gpio_pwr_init,
87
+};
88
+
89
+static void gpio_pwr_register_types(void)
90
+{
132
+{
91
+ type_register_static(&gpio_pwr_info);
133
+ return do_mve_sh_rr(s, a, gen_helper_mve_uqrshl);
92
+}
134
+}
93
+
135
+
94
+type_init(gpio_pwr_register_types)
136
/*
95
diff --git a/hw/gpio/Kconfig b/hw/gpio/Kconfig
137
* Multiply and multiply accumulate
96
index XXXXXXX..XXXXXXX 100644
138
*/
97
--- a/hw/gpio/Kconfig
98
+++ b/hw/gpio/Kconfig
99
@@ -XXX,XX +XXX,XX @@ config PL061
100
config GPIO_KEY
101
bool
102
103
+config GPIO_PWR
104
+ bool
105
+
106
config SIFIVE_GPIO
107
bool
108
diff --git a/hw/gpio/meson.build b/hw/gpio/meson.build
109
index XXXXXXX..XXXXXXX 100644
110
--- a/hw/gpio/meson.build
111
+++ b/hw/gpio/meson.build
112
@@ -XXX,XX +XXX,XX @@
113
softmmu_ss.add(when: 'CONFIG_E500', if_true: files('mpc8xxx.c'))
114
softmmu_ss.add(when: 'CONFIG_GPIO_KEY', if_true: files('gpio_key.c'))
115
+softmmu_ss.add(when: 'CONFIG_GPIO_PWR', if_true: files('gpio_pwr.c'))
116
softmmu_ss.add(when: 'CONFIG_MAX7310', if_true: files('max7310.c'))
117
softmmu_ss.add(when: 'CONFIG_PL061', if_true: files('pl061.c'))
118
softmmu_ss.add(when: 'CONFIG_PUV3', if_true: files('puv3_gpio.c'))
119
--
139
--
120
2.20.1
140
2.20.1
121
141
122
142
diff view generated by jsdifflib
[PULL 06/46] arm-virt: add secure pl061 for reset/power down
Deleted patch
1
From: Maxim Uvarov <maxim.uvarov@linaro.org>
2
1
3
Add secure pl061 for reset/power down machine from
4
the secure world (Arm Trusted Firmware). Connect it
5
with gpio-pwr driver.
6
7
Signed-off-by: Maxim Uvarov <maxim.uvarov@linaro.org>
8
Reviewed-by: Andrew Jones <drjones@redhat.com>
9
[PMM: Added mention of the new device to the documentation]
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
docs/system/arm/virt.rst | 2 ++
13
include/hw/arm/virt.h | 2 ++
14
hw/arm/virt.c | 56 +++++++++++++++++++++++++++++++++++++++-
15
hw/arm/Kconfig | 1 +
16
4 files changed, 60 insertions(+), 1 deletion(-)
17
18
diff --git a/docs/system/arm/virt.rst b/docs/system/arm/virt.rst
19
index XXXXXXX..XXXXXXX 100644
20
--- a/docs/system/arm/virt.rst
21
+++ b/docs/system/arm/virt.rst
22
@@ -XXX,XX +XXX,XX @@ The virt board supports:
23
- Secure-World-only devices if the CPU has TrustZone:
24
25
- A second PL011 UART
26
+ - A second PL061 GPIO controller, with GPIO lines for triggering
27
+ a system reset or system poweroff
28
- A secure flash memory
29
- 16MB of secure RAM
30
31
diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
32
index XXXXXXX..XXXXXXX 100644
33
--- a/include/hw/arm/virt.h
34
+++ b/include/hw/arm/virt.h
35
@@ -XXX,XX +XXX,XX @@ enum {
36
VIRT_GPIO,
37
VIRT_SECURE_UART,
38
VIRT_SECURE_MEM,
39
+ VIRT_SECURE_GPIO,
40
VIRT_PCDIMM_ACPI,
41
VIRT_ACPI_GED,
42
VIRT_NVDIMM_ACPI,
43
@@ -XXX,XX +XXX,XX @@ struct VirtMachineClass {
44
bool kvm_no_adjvtime;
45
bool no_kvm_steal_time;
46
bool acpi_expose_flash;
47
+ bool no_secure_gpio;
48
};
49
50
struct VirtMachineState {
51
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
52
index XXXXXXX..XXXXXXX 100644
53
--- a/hw/arm/virt.c
54
+++ b/hw/arm/virt.c
55
@@ -XXX,XX +XXX,XX @@ static const MemMapEntry base_memmap[] = {
56
[VIRT_ACPI_GED] = { 0x09080000, ACPI_GED_EVT_SEL_LEN },
57
[VIRT_NVDIMM_ACPI] = { 0x09090000, NVDIMM_ACPI_IO_LEN},
58
[VIRT_PVTIME] = { 0x090a0000, 0x00010000 },
59
+ [VIRT_SECURE_GPIO] = { 0x090b0000, 0x00001000 },
60
[VIRT_MMIO] = { 0x0a000000, 0x00000200 },
61
/* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */
62
[VIRT_PLATFORM_BUS] = { 0x0c000000, 0x02000000 },
63
@@ -XXX,XX +XXX,XX @@ static void create_gpio_keys(const VirtMachineState *vms,
64
"gpios", phandle, 3, 0);
65
}
66
67
+#define SECURE_GPIO_POWEROFF 0
68
+#define SECURE_GPIO_RESET 1
69
+
70
+static void create_secure_gpio_pwr(const VirtMachineState *vms,
71
+ DeviceState *pl061_dev,
72
+ uint32_t phandle)
73
+{
74
+ DeviceState *gpio_pwr_dev;
75
+
76
+ /* gpio-pwr */
77
+ gpio_pwr_dev = sysbus_create_simple("gpio-pwr", -1, NULL);
78
+
79
+ /* connect secure pl061 to gpio-pwr */
80
+ qdev_connect_gpio_out(pl061_dev, SECURE_GPIO_RESET,
81
+ qdev_get_gpio_in_named(gpio_pwr_dev, "reset", 0));
82
+ qdev_connect_gpio_out(pl061_dev, SECURE_GPIO_POWEROFF,
83
+ qdev_get_gpio_in_named(gpio_pwr_dev, "shutdown", 0));
84
+
85
+ qemu_fdt_add_subnode(vms->fdt, "/gpio-poweroff");
86
+ qemu_fdt_setprop_string(vms->fdt, "/gpio-poweroff", "compatible",
87
+ "gpio-poweroff");
88
+ qemu_fdt_setprop_cells(vms->fdt, "/gpio-poweroff",
89
+ "gpios", phandle, SECURE_GPIO_POWEROFF, 0);
90
+ qemu_fdt_setprop_string(vms->fdt, "/gpio-poweroff", "status", "disabled");
91
+ qemu_fdt_setprop_string(vms->fdt, "/gpio-poweroff", "secure-status",
92
+ "okay");
93
+
94
+ qemu_fdt_add_subnode(vms->fdt, "/gpio-restart");
95
+ qemu_fdt_setprop_string(vms->fdt, "/gpio-restart", "compatible",
96
+ "gpio-restart");
97
+ qemu_fdt_setprop_cells(vms->fdt, "/gpio-restart",
98
+ "gpios", phandle, SECURE_GPIO_RESET, 0);
99
+ qemu_fdt_setprop_string(vms->fdt, "/gpio-restart", "status", "disabled");
100
+ qemu_fdt_setprop_string(vms->fdt, "/gpio-restart", "secure-status",
101
+ "okay");
102
+}
103
+
104
static void create_gpio_devices(const VirtMachineState *vms, int gpio,
105
MemoryRegion *mem)
106
{
107
@@ -XXX,XX +XXX,XX @@ static void create_gpio_devices(const VirtMachineState *vms, int gpio,
108
qemu_fdt_setprop_string(vms->fdt, nodename, "clock-names", "apb_pclk");
109
qemu_fdt_setprop_cell(vms->fdt, nodename, "phandle", phandle);
110
111
+ if (gpio != VIRT_GPIO) {
112
+ /* Mark as not usable by the normal world */
113
+ qemu_fdt_setprop_string(vms->fdt, nodename, "status", "disabled");
114
+ qemu_fdt_setprop_string(vms->fdt, nodename, "secure-status", "okay");
115
+ }
116
g_free(nodename);
117
118
/* Child gpio devices */
119
- create_gpio_keys(vms, pl061_dev, phandle);
120
+ if (gpio == VIRT_GPIO) {
121
+ create_gpio_keys(vms, pl061_dev, phandle);
122
+ } else {
123
+ create_secure_gpio_pwr(vms, pl061_dev, phandle);
124
+ }
125
}
126
127
static void create_virtio_devices(const VirtMachineState *vms)
128
@@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine)
129
create_gpio_devices(vms, VIRT_GPIO, sysmem);
130
}
131
132
+ if (vms->secure && !vmc->no_secure_gpio) {
133
+ create_gpio_devices(vms, VIRT_SECURE_GPIO, secure_sysmem);
134
+ }
135
+
136
/* connect powerdown request */
137
vms->powerdown_notifier.notify = virt_powerdown_req;
138
qemu_register_powerdown_notifier(&vms->powerdown_notifier);
139
@@ -XXX,XX +XXX,XX @@ DEFINE_VIRT_MACHINE_AS_LATEST(6, 0)
140
141
static void virt_machine_5_2_options(MachineClass *mc)
142
{
143
+ VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
144
+
145
virt_machine_6_0_options(mc);
146
compat_props_add(mc->compat_props, hw_compat_5_2, hw_compat_5_2_len);
147
+ vmc->no_secure_gpio = true;
148
}
149
DEFINE_VIRT_MACHINE(5, 2)
150
151
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
152
index XXXXXXX..XXXXXXX 100644
153
--- a/hw/arm/Kconfig
154
+++ b/hw/arm/Kconfig
155
@@ -XXX,XX +XXX,XX @@ config ARM_VIRT
156
select PL011 # UART
157
select PL031 # RTC
158
select PL061 # GPIO
159
+ select GPIO_PWR
160
select PLATFORM_BUS
161
select SMBIOS
162
select VIRTIO_MMIO
163
--
164
2.20.1
165
166
diff view generated by jsdifflib
[PULL 09/46] configure: Move preadv check to meson.build
Deleted patch
1
Move the preadv availability check to meson.build. This is what we
2
want to be doing for host-OS-feature-checks anyway, but it also fixes
3
a problem with building for macOS with the most recent XCode SDK on a
4
Catalina host.
5
1
6
On that configuration, 'preadv()' is provided as a weak symbol, so
7
that programs can be built with optional support for it and make a
8
runtime availability check to see whether the preadv() they have is a
9
working one or one which they must not call because it will
10
runtime-assert. QEMU's configure test passes (unless you're building
11
with --enable-werror) because the test program using preadv()
12
compiles, but then QEMU crashes at runtime when preadv() is called,
13
with errors like:
14
15
dyld: lazy symbol binding failed: Symbol not found: _preadv
16
Referenced from: /Users/pm215/src/qemu/./build/x86/tests/test-replication
17
Expected in: /usr/lib/libSystem.B.dylib
18
19
dyld: Symbol not found: _preadv
20
Referenced from: /Users/pm215/src/qemu/./build/x86/tests/test-replication
21
Expected in: /usr/lib/libSystem.B.dylib
22
23
Meson's own function availability check has a special case for macOS
24
which adds '-Wl,-no_weak_imports' to the compiler flags, which forces
25
the test to require the real function, not the macOS-version-too-old
26
stub.
27
28
So this commit fixes the bug where macOS builds on Catalina currently
29
require --disable-werror.
30
31
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
32
Acked-by: Paolo Bonzini <pbonzini@redhat.com>
33
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
34
Message-id: 20210126155846.17109-1-peter.maydell@linaro.org
35
---
36
configure | 16 ----------------
37
meson.build | 4 +++-
38
2 files changed, 3 insertions(+), 17 deletions(-)
39
40
diff --git a/configure b/configure
41
index XXXXXXX..XXXXXXX 100755
42
--- a/configure
43
+++ b/configure
44
@@ -XXX,XX +XXX,XX @@ if compile_prog "" "" ; then
45
iovec=yes
46
fi
47
48
-##########################################
49
-# preadv probe
50
-cat > $TMPC <<EOF
51
-#include <sys/types.h>
52
-#include <sys/uio.h>
53
-#include <unistd.h>
54
-int main(void) { return preadv(0, 0, 0, 0); }
55
-EOF
56
-preadv=no
57
-if compile_prog "" "" ; then
58
- preadv=yes
59
-fi
60
-
61
##########################################
62
# fdt probe
63
64
@@ -XXX,XX +XXX,XX @@ fi
65
if test "$iovec" = "yes" ; then
66
echo "CONFIG_IOVEC=y" >> $config_host_mak
67
fi
68
-if test "$preadv" = "yes" ; then
69
- echo "CONFIG_PREADV=y" >> $config_host_mak
70
-fi
71
if test "$membarrier" = "yes" ; then
72
echo "CONFIG_MEMBARRIER=y" >> $config_host_mak
73
fi
74
diff --git a/meson.build b/meson.build
75
index XXXXXXX..XXXXXXX 100644
76
--- a/meson.build
77
+++ b/meson.build
78
@@ -XXX,XX +XXX,XX @@ config_host_data.set('HAVE_PTY_H', cc.has_header('pty.h'))
79
config_host_data.set('HAVE_SYS_IOCCOM_H', cc.has_header('sys/ioccom.h'))
80
config_host_data.set('HAVE_SYS_KCOV_H', cc.has_header('sys/kcov.h'))
81
82
+config_host_data.set('CONFIG_PREADV', cc.has_function('preadv', prefix: '#include <sys/uio.h>'))
83
+
84
ignored = ['CONFIG_QEMU_INTERP_PREFIX'] # actually per-target
85
arrays = ['CONFIG_AUDIO_DRIVERS', 'CONFIG_BDRV_RW_WHITELIST', 'CONFIG_BDRV_RO_WHITELIST']
86
strings = ['HOST_DSOSUF', 'CONFIG_IASL']
87
@@ -XXX,XX +XXX,XX @@ summary_info += {'PIE': get_option('b_pie')}
88
summary_info += {'static build': config_host.has_key('CONFIG_STATIC')}
89
summary_info += {'malloc trim support': has_malloc_trim}
90
summary_info += {'membarrier': config_host.has_key('CONFIG_MEMBARRIER')}
91
-summary_info += {'preadv support': config_host.has_key('CONFIG_PREADV')}
92
+summary_info += {'preadv support': config_host_data.get('CONFIG_PREADV')}
93
summary_info += {'fdatasync': config_host.has_key('CONFIG_FDATASYNC')}
94
summary_info += {'madvise': config_host.has_key('CONFIG_MADVISE')}
95
summary_info += {'posix_madvise': config_host.has_key('CONFIG_POSIX_MADVISE')}
96
--
97
2.20.1
98
99
diff view generated by jsdifflib
[PULL 10/46] configure: cross-compiling with empty cross_prefix
Deleted patch
1
From: Joelle van Dyne <j@getutm.app>
2
1
3
The iOS toolchain does not use the host prefix naming convention. So we
4
need to enable cross-compile options while allowing the PREFIX to be
5
blank.
6
7
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Signed-off-by: Joelle van Dyne <j@getutm.app>
9
Message-id: 20210126012457.39046-3-j@getutm.app
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
configure | 6 ++++--
13
1 file changed, 4 insertions(+), 2 deletions(-)
14
15
diff --git a/configure b/configure
16
index XXXXXXX..XXXXXXX 100755
17
--- a/configure
18
+++ b/configure
19
@@ -XXX,XX +XXX,XX @@ cpu=""
20
iasl="iasl"
21
interp_prefix="/usr/gnemul/qemu-%M"
22
static="no"
23
+cross_compile="no"
24
cross_prefix=""
25
audio_drv_list=""
26
block_drv_rw_whitelist=""
27
@@ -XXX,XX +XXX,XX @@ for opt do
28
optarg=$(expr "x$opt" : 'x[^=]*=\(.*\)')
29
case "$opt" in
30
--cross-prefix=*) cross_prefix="$optarg"
31
+ cross_compile="yes"
32
;;
33
--cc=*) CC="$optarg"
34
;;
35
@@ -XXX,XX +XXX,XX @@ $(echo Deprecated targets: $deprecated_targets_list | \
36
--target-list-exclude=LIST exclude a set of targets from the default target-list
37
38
Advanced options (experts only):
39
- --cross-prefix=PREFIX use PREFIX for compile tools [$cross_prefix]
40
+ --cross-prefix=PREFIX use PREFIX for compile tools, PREFIX can be blank [$cross_prefix]
41
--cc=CC use C compiler CC [$cc]
42
--iasl=IASL use ACPI compiler IASL [$iasl]
43
--host-cc=CC use C compiler CC [$host_cc] for code run at
44
@@ -XXX,XX +XXX,XX @@ if has $sdl2_config; then
45
fi
46
echo "strip = [$(meson_quote $strip)]" >> $cross
47
echo "windres = [$(meson_quote $windres)]" >> $cross
48
-if test -n "$cross_prefix"; then
49
+if test "$cross_compile" = "yes"; then
50
cross_arg="--cross-file config-meson.cross"
51
echo "[host_machine]" >> $cross
52
if test "$mingw32" = "yes" ; then
53
--
54
2.20.1
55
56
diff view generated by jsdifflib
[PULL 11/46] osdep: build with non-working system() function
Deleted patch
1
From: Joelle van Dyne <j@getutm.app>
2
1
3
Build without error on hosts without a working system(). If system()
4
is called, return -1 with ENOSYS.
5
6
Signed-off-by: Joelle van Dyne <j@getutm.app>
7
Message-id: 20210126012457.39046-6-j@getutm.app
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
meson.build | 1 +
12
include/qemu/osdep.h | 12 ++++++++++++
13
2 files changed, 13 insertions(+)
14
15
diff --git a/meson.build b/meson.build
16
index XXXXXXX..XXXXXXX 100644
17
--- a/meson.build
18
+++ b/meson.build
19
@@ -XXX,XX +XXX,XX @@ config_host_data.set('HAVE_DRM_H', cc.has_header('libdrm/drm.h'))
20
config_host_data.set('HAVE_PTY_H', cc.has_header('pty.h'))
21
config_host_data.set('HAVE_SYS_IOCCOM_H', cc.has_header('sys/ioccom.h'))
22
config_host_data.set('HAVE_SYS_KCOV_H', cc.has_header('sys/kcov.h'))
23
+config_host_data.set('HAVE_SYSTEM_FUNCTION', cc.has_function('system', prefix: '#include <stdlib.h>'))
24
25
config_host_data.set('CONFIG_PREADV', cc.has_function('preadv', prefix: '#include <sys/uio.h>'))
26
27
diff --git a/include/qemu/osdep.h b/include/qemu/osdep.h
28
index XXXXXXX..XXXXXXX 100644
29
--- a/include/qemu/osdep.h
30
+++ b/include/qemu/osdep.h
31
@@ -XXX,XX +XXX,XX @@ static inline void qemu_thread_jit_write(void) {}
32
static inline void qemu_thread_jit_execute(void) {}
33
#endif
34
35
+/**
36
+ * Platforms which do not support system() return ENOSYS
37
+ */
38
+#ifndef HAVE_SYSTEM_FUNCTION
39
+#define system platform_does_not_support_system
40
+static inline int platform_does_not_support_system(const char *command)
41
+{
42
+ errno = ENOSYS;
43
+ return -1;
44
+}
45
+#endif /* !HAVE_SYSTEM_FUNCTION */
46
+
47
#endif
48
--
49
2.20.1
50
51
diff view generated by jsdifflib
[PULL 12/46] darwin: remove redundant dependency declaration
Deleted patch
1
From: Joelle van Dyne <j@getutm.app>
2
1
3
Meson will find CoreFoundation, IOKit, and Cocoa as needed.
4
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Joelle van Dyne <j@getutm.app>
7
Message-id: 20210126012457.39046-7-j@getutm.app
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
configure | 1 -
11
1 file changed, 1 deletion(-)
12
13
diff --git a/configure b/configure
14
index XXXXXXX..XXXXXXX 100755
15
--- a/configure
16
+++ b/configure
17
@@ -XXX,XX +XXX,XX @@ Darwin)
18
fi
19
audio_drv_list="coreaudio try-sdl"
20
audio_possible_drivers="coreaudio sdl"
21
- QEMU_LDFLAGS="-framework CoreFoundation -framework IOKit $QEMU_LDFLAGS"
22
# Disable attempts to use ObjectiveC features in os/object.h since they
23
# won't work when we're compiling with gcc as a C compiler.
24
QEMU_CFLAGS="-DOS_OBJECT_USE_OBJC=0 $QEMU_CFLAGS"
25
--
26
2.20.1
27
28
diff view generated by jsdifflib
[PULL 13/46] darwin: fix cross-compiling for Darwin
Deleted patch
1
From: Joelle van Dyne <j@getutm.app>
2
1
3
Add objc to the Meson cross file as well as detection of Darwin.
4
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Joelle van Dyne <j@getutm.app>
7
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Message-id: 20210126012457.39046-8-j@getutm.app
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
configure | 4 ++++
12
1 file changed, 4 insertions(+)
13
14
diff --git a/configure b/configure
15
index XXXXXXX..XXXXXXX 100755
16
--- a/configure
17
+++ b/configure
18
@@ -XXX,XX +XXX,XX @@ echo "cpp_link_args = [${LDFLAGS:+$(meson_quote $LDFLAGS)}]" >> $cross
19
echo "[binaries]" >> $cross
20
echo "c = [$(meson_quote $cc)]" >> $cross
21
test -n "$cxx" && echo "cpp = [$(meson_quote $cxx)]" >> $cross
22
+test -n "$objcc" && echo "objc = [$(meson_quote $objcc)]" >> $cross
23
echo "ar = [$(meson_quote $ar)]" >> $cross
24
echo "nm = [$(meson_quote $nm)]" >> $cross
25
echo "pkgconfig = [$(meson_quote $pkg_config_exe)]" >> $cross
26
@@ -XXX,XX +XXX,XX @@ if test "$cross_compile" = "yes"; then
27
if test "$linux" = "yes" ; then
28
echo "system = 'linux'" >> $cross
29
fi
30
+ if test "$darwin" = "yes" ; then
31
+ echo "system = 'darwin'" >> $cross
32
+ fi
33
case "$ARCH" in
34
i386|x86_64)
35
echo "cpu_family = 'x86'" >> $cross
36
--
37
2.20.1
38
39
diff view generated by jsdifflib
[PULL 14/46] configure: cross compile should use x86_64 cpu_family
Deleted patch
1
From: Joelle van Dyne <j@getutm.app>
2
1
3
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
4
Signed-off-by: Joelle van Dyne <j@getutm.app>
5
Message-id: 20210126012457.39046-9-j@getutm.app
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
configure | 5 ++++-
9
1 file changed, 4 insertions(+), 1 deletion(-)
10
11
diff --git a/configure b/configure
12
index XXXXXXX..XXXXXXX 100755
13
--- a/configure
14
+++ b/configure
15
@@ -XXX,XX +XXX,XX @@ if test "$cross_compile" = "yes"; then
16
echo "system = 'darwin'" >> $cross
17
fi
18
case "$ARCH" in
19
- i386|x86_64)
20
+ i386)
21
echo "cpu_family = 'x86'" >> $cross
22
;;
23
+ x86_64)
24
+ echo "cpu_family = 'x86_64'" >> $cross
25
+ ;;
26
ppc64le)
27
echo "cpu_family = 'ppc64'" >> $cross
28
;;
29
--
30
2.20.1
31
32
diff view generated by jsdifflib
[PULL 15/46] darwin: detect CoreAudio for build
Deleted patch
1
From: Joelle van Dyne <j@getutm.app>
2
1
3
On iOS there is no CoreAudio, so we should not assume Darwin always
4
has it.
5
6
Signed-off-by: Joelle van Dyne <j@getutm.app>
7
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Message-id: 20210126012457.39046-11-j@getutm.app
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
configure | 35 +++++++++++++++++++++++++++++++++--
12
1 file changed, 33 insertions(+), 2 deletions(-)
13
14
diff --git a/configure b/configure
15
index XXXXXXX..XXXXXXX 100755
16
--- a/configure
17
+++ b/configure
18
@@ -XXX,XX +XXX,XX @@ fdt="auto"
19
netmap="no"
20
sdl="auto"
21
sdl_image="auto"
22
+coreaudio="auto"
23
virtiofsd="auto"
24
virtfs="auto"
25
libudev="auto"
26
@@ -XXX,XX +XXX,XX @@ Darwin)
27
QEMU_CFLAGS="-arch x86_64 $QEMU_CFLAGS"
28
QEMU_LDFLAGS="-arch x86_64 $QEMU_LDFLAGS"
29
fi
30
- audio_drv_list="coreaudio try-sdl"
31
+ audio_drv_list="try-coreaudio try-sdl"
32
audio_possible_drivers="coreaudio sdl"
33
# Disable attempts to use ObjectiveC features in os/object.h since they
34
# won't work when we're compiling with gcc as a C compiler.
35
@@ -XXX,XX +XXX,XX @@ EOF
36
fi
37
fi
38
39
+##########################################
40
+# detect CoreAudio
41
+if test "$coreaudio" != "no" ; then
42
+ coreaudio_libs="-framework CoreAudio"
43
+ cat > $TMPC << EOF
44
+#include <CoreAudio/CoreAudio.h>
45
+int main(void)
46
+{
47
+ return (int)AudioGetCurrentHostTime();
48
+}
49
+EOF
50
+ if compile_prog "" "$coreaudio_libs" ; then
51
+ coreaudio=yes
52
+ else
53
+ coreaudio=no
54
+ fi
55
+fi
56
+
57
##########################################
58
# Sound support libraries probe
59
60
@@ -XXX,XX +XXX,XX @@ for drv in $audio_drv_list; do
61
fi
62
;;
63
64
- coreaudio)
65
+ coreaudio | try-coreaudio)
66
+ if test "$coreaudio" = "no"; then
67
+ if test "$drv" = "try-coreaudio"; then
68
+ audio_drv_list=$(echo "$audio_drv_list" | sed -e 's/try-coreaudio//')
69
+ else
70
+ error_exit "$drv check failed" \
71
+ "Make sure to have the $drv is available."
72
+ fi
73
+ else
74
coreaudio_libs="-framework CoreAudio"
75
+ if test "$drv" = "try-coreaudio"; then
76
+ audio_drv_list=$(echo "$audio_drv_list" | sed -e 's/try-coreaudio/coreaudio/')
77
+ fi
78
+ fi
79
;;
80
81
dsound)
82
--
83
2.20.1
84
85
diff view generated by jsdifflib
[PULL 16/46] darwin: remove 64-bit build detection on 32-bit OS
Deleted patch
1
From: Joelle van Dyne <j@getutm.app>
2
1
3
A workaround added in early days of 64-bit OSX forced x86_64 if the
4
host machine had 64-bit support. This creates issues when cross-
5
compiling for ARM64. Additionally, the user can always use --cpu=* to
6
manually set the host CPU and therefore this workaround should be
7
removed.
8
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Joelle van Dyne <j@getutm.app>
11
Message-id: 20210126012457.39046-12-j@getutm.app
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
14
configure | 11 -----------
15
1 file changed, 11 deletions(-)
16
17
diff --git a/configure b/configure
18
index XXXXXXX..XXXXXXX 100755
19
--- a/configure
20
+++ b/configure
21
@@ -XXX,XX +XXX,XX @@ fi
22
# the correct CPU with the --cpu option.
23
case $targetos in
24
Darwin)
25
- # on Leopard most of the system is 32-bit, so we have to ask the kernel if we can
26
- # run 64-bit userspace code.
27
- # If the user didn't specify a CPU explicitly and the kernel says this is
28
- # 64 bit hw, then assume x86_64. Otherwise fall through to the usual detection code.
29
- if test -z "$cpu" && test "$(sysctl -n hw.optional.x86_64)" = "1"; then
30
- cpu="x86_64"
31
- fi
32
HOST_DSOSUF=".dylib"
33
;;
34
SunOS)
35
@@ -XXX,XX +XXX,XX @@ OpenBSD)
36
Darwin)
37
bsd="yes"
38
darwin="yes"
39
- if [ "$cpu" = "x86_64" ] ; then
40
- QEMU_CFLAGS="-arch x86_64 $QEMU_CFLAGS"
41
- QEMU_LDFLAGS="-arch x86_64 $QEMU_LDFLAGS"
42
- fi
43
audio_drv_list="try-coreaudio try-sdl"
44
audio_possible_drivers="coreaudio sdl"
45
# Disable attempts to use ObjectiveC features in os/object.h since they
46
--
47
2.20.1
48
49
diff view generated by jsdifflib
[PULL 17/46] hvf: Add hypervisor entitlement to output binaries
Deleted patch
1
From: Alexander Graf <agraf@csgraf.de>
2
1
3
In macOS 11, QEMU only gets access to Hypervisor.framework if it has the
4
respective entitlement. Add an entitlement template and automatically self
5
sign and apply the entitlement in the build.
6
7
Signed-off-by: Alexander Graf <agraf@csgraf.de>
8
Reviewed-by: Roman Bolshakov <r.bolshakov@yadro.com>
9
Tested-by: Roman Bolshakov <r.bolshakov@yadro.com>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
meson.build | 29 +++++++++++++++++++++++++----
13
accel/hvf/entitlements.plist | 8 ++++++++
14
scripts/entitlement.sh | 13 +++++++++++++
15
3 files changed, 46 insertions(+), 4 deletions(-)
16
create mode 100644 accel/hvf/entitlements.plist
17
create mode 100755 scripts/entitlement.sh
18
19
diff --git a/meson.build b/meson.build
20
index XXXXXXX..XXXXXXX 100644
21
--- a/meson.build
22
+++ b/meson.build
23
@@ -XXX,XX +XXX,XX @@ foreach target : target_dirs
24
}]
25
endif
26
foreach exe: execs
27
- emulators += {exe['name']:
28
- executable(exe['name'], exe['sources'],
29
- install: true,
30
+ exe_name = exe['name']
31
+ exe_sign = 'CONFIG_HVF' in config_target
32
+ if exe_sign
33
+ exe_name += '-unsigned'
34
+ endif
35
+
36
+ emulator = executable(exe_name, exe['sources'],
37
+ install: not exe_sign,
38
c_args: c_args,
39
dependencies: arch_deps + deps + exe['dependencies'],
40
objects: lib.extract_all_objects(recursive: true),
41
@@ -XXX,XX +XXX,XX @@ foreach target : target_dirs
42
link_depends: [block_syms, qemu_syms] + exe.get('link_depends', []),
43
link_args: link_args,
44
gui_app: exe['gui'])
45
- }
46
+
47
+ if exe_sign
48
+ emulators += {exe['name'] : custom_target(exe['name'],
49
+ install: true,
50
+ install_dir: get_option('bindir'),
51
+ depends: emulator,
52
+ output: exe['name'],
53
+ command: [
54
+ meson.current_source_dir() / 'scripts/entitlement.sh',
55
+ meson.current_build_dir() / exe_name,
56
+ meson.current_build_dir() / exe['name'],
57
+ meson.current_source_dir() / 'accel/hvf/entitlements.plist'
58
+ ])
59
+ }
60
+ else
61
+ emulators += {exe['name']: emulator}
62
+ endif
63
64
if 'CONFIG_TRACE_SYSTEMTAP' in config_host
65
foreach stp: [
66
diff --git a/accel/hvf/entitlements.plist b/accel/hvf/entitlements.plist
67
new file mode 100644
68
index XXXXXXX..XXXXXXX
69
--- /dev/null
70
+++ b/accel/hvf/entitlements.plist
71
@@ -XXX,XX +XXX,XX @@
72
+<?xml version="1.0" encoding="UTF-8"?>
73
+<!DOCTYPE plist PUBLIC "-//Apple//DTD PLIST 1.0//EN" "http://www.apple.com/DTDs/PropertyList-1.0.dtd">
74
+<plist version="1.0">
75
+<dict>
76
+ <key>com.apple.security.hypervisor</key>
77
+ <true/>
78
+</dict>
79
+</plist>
80
diff --git a/scripts/entitlement.sh b/scripts/entitlement.sh
81
new file mode 100755
82
index XXXXXXX..XXXXXXX
83
--- /dev/null
84
+++ b/scripts/entitlement.sh
85
@@ -XXX,XX +XXX,XX @@
86
+#!/bin/sh -e
87
+#
88
+# Helper script for the build process to apply entitlements
89
+
90
+SRC="$1"
91
+DST="$2"
92
+ENTITLEMENT="$3"
93
+
94
+trap 'rm "$DST.tmp"' exit
95
+cp -af "$SRC" "$DST.tmp"
96
+codesign --entitlements "$ENTITLEMENT" --force -s - "$DST.tmp"
97
+mv "$DST.tmp" "$DST"
98
+trap '' exit
99
--
100
2.20.1
101
102
diff view generated by jsdifflib
[PULL 21/46] tests/qtest: add a test case for pvpanic-pci
Deleted patch
1
From: Mihai Carabas <mihai.carabas@oracle.com>
2
1
3
Add a test case for pvpanic-pci device. The scenario is the same as pvpanic
4
ISA device, but is using the PCI bus.
5
6
Signed-off-by: Mihai Carabas <mihai.carabas@oracle.com>
7
Acked-by: Thomas Huth <thuth@redhat.com>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Mihai Carabas <mihai.carabas@oracle.com>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
tests/qtest/pvpanic-pci-test.c | 94 ++++++++++++++++++++++++++++++++++
13
tests/qtest/meson.build | 1 +
14
2 files changed, 95 insertions(+)
15
create mode 100644 tests/qtest/pvpanic-pci-test.c
16
17
diff --git a/tests/qtest/pvpanic-pci-test.c b/tests/qtest/pvpanic-pci-test.c
18
new file mode 100644
19
index XXXXXXX..XXXXXXX
20
--- /dev/null
21
+++ b/tests/qtest/pvpanic-pci-test.c
22
@@ -XXX,XX +XXX,XX @@
23
+/*
24
+ * QTest testcase for PV Panic PCI device
25
+ *
26
+ * Copyright (C) 2020 Oracle
27
+ *
28
+ * Authors:
29
+ * Mihai Carabas <mihai.carabas@oracle.com>
30
+ *
31
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
32
+ * See the COPYING file in the top-level directory.
33
+ *
34
+ */
35
+
36
+#include "qemu/osdep.h"
37
+#include "libqos/libqtest.h"
38
+#include "qapi/qmp/qdict.h"
39
+#include "libqos/pci.h"
40
+#include "libqos/pci-pc.h"
41
+#include "hw/pci/pci_regs.h"
42
+
43
+static void test_panic_nopause(void)
44
+{
45
+ uint8_t val;
46
+ QDict *response, *data;
47
+ QTestState *qts;
48
+ QPCIBus *pcibus;
49
+ QPCIDevice *dev;
50
+ QPCIBar bar;
51
+
52
+ qts = qtest_init("-device pvpanic-pci,addr=04.0 -action panic=none");
53
+ pcibus = qpci_new_pc(qts, NULL);
54
+ dev = qpci_device_find(pcibus, QPCI_DEVFN(0x4, 0x0));
55
+ qpci_device_enable(dev);
56
+ bar = qpci_iomap(dev, 0, NULL);
57
+
58
+ qpci_memread(dev, bar, 0, &val, sizeof(val));
59
+ g_assert_cmpuint(val, ==, 3);
60
+
61
+ val = 1;
62
+ qpci_memwrite(dev, bar, 0, &val, sizeof(val));
63
+
64
+ response = qtest_qmp_eventwait_ref(qts, "GUEST_PANICKED");
65
+ g_assert(qdict_haskey(response, "data"));
66
+ data = qdict_get_qdict(response, "data");
67
+ g_assert(qdict_haskey(data, "action"));
68
+ g_assert_cmpstr(qdict_get_str(data, "action"), ==, "run");
69
+ qobject_unref(response);
70
+
71
+ qtest_quit(qts);
72
+}
73
+
74
+static void test_panic(void)
75
+{
76
+ uint8_t val;
77
+ QDict *response, *data;
78
+ QTestState *qts;
79
+ QPCIBus *pcibus;
80
+ QPCIDevice *dev;
81
+ QPCIBar bar;
82
+
83
+ qts = qtest_init("-device pvpanic-pci,addr=04.0 -action panic=pause");
84
+ pcibus = qpci_new_pc(qts, NULL);
85
+ dev = qpci_device_find(pcibus, QPCI_DEVFN(0x4, 0x0));
86
+ qpci_device_enable(dev);
87
+ bar = qpci_iomap(dev, 0, NULL);
88
+
89
+ qpci_memread(dev, bar, 0, &val, sizeof(val));
90
+ g_assert_cmpuint(val, ==, 3);
91
+
92
+ val = 1;
93
+ qpci_memwrite(dev, bar, 0, &val, sizeof(val));
94
+
95
+ response = qtest_qmp_eventwait_ref(qts, "GUEST_PANICKED");
96
+ g_assert(qdict_haskey(response, "data"));
97
+ data = qdict_get_qdict(response, "data");
98
+ g_assert(qdict_haskey(data, "action"));
99
+ g_assert_cmpstr(qdict_get_str(data, "action"), ==, "pause");
100
+ qobject_unref(response);
101
+
102
+ qtest_quit(qts);
103
+}
104
+
105
+int main(int argc, char **argv)
106
+{
107
+ int ret;
108
+
109
+ g_test_init(&argc, &argv, NULL);
110
+ qtest_add_func("/pvpanic-pci/panic", test_panic);
111
+ qtest_add_func("/pvpanic-pci/panic-nopause", test_panic_nopause);
112
+
113
+ ret = g_test_run();
114
+
115
+ return ret;
116
+}
117
diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
118
index XXXXXXX..XXXXXXX 100644
119
--- a/tests/qtest/meson.build
120
+++ b/tests/qtest/meson.build
121
@@ -XXX,XX +XXX,XX @@ qtests_i386 = \
122
config_all_devices.has_key('CONFIG_ISA_IPMI_BT') ? ['ipmi-bt-test'] : []) + \
123
(config_all_devices.has_key('CONFIG_WDT_IB700') ? ['wdt_ib700-test'] : []) + \
124
(config_all_devices.has_key('CONFIG_PVPANIC_ISA') ? ['pvpanic-test'] : []) + \
125
+ (config_all_devices.has_key('CONFIG_PVPANIC_PCI') ? ['pvpanic-pci-test'] : []) + \
126
(config_all_devices.has_key('CONFIG_HDA') ? ['intel-hda-test'] : []) + \
127
(config_all_devices.has_key('CONFIG_I82801B11') ? ['i82801b11-test'] : []) + \
128
(config_all_devices.has_key('CONFIG_IOH3420') ? ['ioh3420-test'] : []) + \
129
--
130
2.20.1
131
132
diff view generated by jsdifflib
[PULL 23/46] clock: Add new clock_has_source() function
Deleted patch
1
Add a function for checking whether a clock has a source. This is
2
useful for devices which have input clocks that must be wired up by
3
the board as it allows them to fail in realize rather than ploughing
4
on with a zero-period clock.
5
1
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Luc Michel <luc@lmichel.fr>
8
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
10
Message-id: 20210128114145.20536-3-peter.maydell@linaro.org
11
Message-id: 20210121190622.22000-3-peter.maydell@linaro.org
12
---
13
docs/devel/clocks.rst | 16 ++++++++++++++++
14
include/hw/clock.h | 15 +++++++++++++++
15
2 files changed, 31 insertions(+)
16
17
diff --git a/docs/devel/clocks.rst b/docs/devel/clocks.rst
18
index XXXXXXX..XXXXXXX 100644
19
--- a/docs/devel/clocks.rst
20
+++ b/docs/devel/clocks.rst
21
@@ -XXX,XX +XXX,XX @@ object during device instance init. For example:
22
/* set initial value to 10ns / 100MHz */
23
clock_set_ns(clk, 10);
24
25
+To enforce that the clock is wired up by the board code, you can
26
+call ``clock_has_source()`` in your device's realize method:
27
+
28
+.. code-block:: c
29
+
30
+ if (!clock_has_source(s->clk)) {
31
+ error_setg(errp, "MyDevice: clk input must be connected");
32
+ return;
33
+ }
34
+
35
+Note that this only checks that the clock has been wired up; it is
36
+still possible that the output clock connected to it is disabled
37
+or has not yet been configured, in which case the period will be
38
+zero. You should use the clock callback to find out when the clock
39
+period changes.
40
+
41
Fetching clock frequency/period
42
-------------------------------
43
44
diff --git a/include/hw/clock.h b/include/hw/clock.h
45
index XXXXXXX..XXXXXXX 100644
46
--- a/include/hw/clock.h
47
+++ b/include/hw/clock.h
48
@@ -XXX,XX +XXX,XX @@ void clock_clear_callback(Clock *clk);
49
*/
50
void clock_set_source(Clock *clk, Clock *src);
51
52
+/**
53
+ * clock_has_source:
54
+ * @clk: the clock
55
+ *
56
+ * Returns true if the clock has a source clock connected to it.
57
+ * This is useful for devices which have input clocks which must
58
+ * be connected by the board/SoC code which creates them. The
59
+ * device code can use this to check in its realize method that
60
+ * the clock has been connected.
61
+ */
62
+static inline bool clock_has_source(const Clock *clk)
63
+{
64
+ return clk->source != NULL;
65
+}
66
+
67
/**
68
* clock_set:
69
* @clk: the clock to initialize.
70
--
71
2.20.1
72
73
diff view generated by jsdifflib
[PULL 27/46] hw/timer/cmsdk-apb-timer: Rename CMSDKAPBTIMER struct to CMSDKAPBTimer
Deleted patch
1
The state struct for the CMSDK APB timer device doesn't follow our
2
usual naming convention of camelcase -- "CMSDK" and "APB" are both
3
acronyms, but "TIMER" is not so should not be all-uppercase.
4
Globally rename the struct to "CMSDKAPBTimer" (bringing it into line
5
with CMSDKAPBWatchdog and CMSDKAPBDualTimer; CMSDKAPBUART remains
6
as-is because "UART" is an acronym).
7
1
8
Commit created with:
9
perl -p -i -e 's/CMSDKAPBTIMER/CMSDKAPBTimer/g' hw/timer/cmsdk-apb-timer.c include/hw/arm/armsse.h include/hw/timer/cmsdk-apb-timer.h
10
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
13
Reviewed-by: Luc Michel <luc@lmichel.fr>
14
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
15
Message-id: 20210128114145.20536-7-peter.maydell@linaro.org
16
Message-id: 20210121190622.22000-7-peter.maydell@linaro.org
17
---
18
include/hw/arm/armsse.h | 6 +++---
19
include/hw/timer/cmsdk-apb-timer.h | 4 ++--
20
hw/timer/cmsdk-apb-timer.c | 28 ++++++++++++++--------------
21
3 files changed, 19 insertions(+), 19 deletions(-)
22
23
diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h
24
index XXXXXXX..XXXXXXX 100644
25
--- a/include/hw/arm/armsse.h
26
+++ b/include/hw/arm/armsse.h
27
@@ -XXX,XX +XXX,XX @@ struct ARMSSE {
28
TZPPC apb_ppc0;
29
TZPPC apb_ppc1;
30
TZMPC mpc[IOTS_NUM_MPC];
31
- CMSDKAPBTIMER timer0;
32
- CMSDKAPBTIMER timer1;
33
- CMSDKAPBTIMER s32ktimer;
34
+ CMSDKAPBTimer timer0;
35
+ CMSDKAPBTimer timer1;
36
+ CMSDKAPBTimer s32ktimer;
37
qemu_or_irq ppc_irq_orgate;
38
SplitIRQ sec_resp_splitter;
39
SplitIRQ ppc_irq_splitter[NUM_PPCS];
40
diff --git a/include/hw/timer/cmsdk-apb-timer.h b/include/hw/timer/cmsdk-apb-timer.h
41
index XXXXXXX..XXXXXXX 100644
42
--- a/include/hw/timer/cmsdk-apb-timer.h
43
+++ b/include/hw/timer/cmsdk-apb-timer.h
44
@@ -XXX,XX +XXX,XX @@
45
#include "qom/object.h"
46
47
#define TYPE_CMSDK_APB_TIMER "cmsdk-apb-timer"
48
-OBJECT_DECLARE_SIMPLE_TYPE(CMSDKAPBTIMER, CMSDK_APB_TIMER)
49
+OBJECT_DECLARE_SIMPLE_TYPE(CMSDKAPBTimer, CMSDK_APB_TIMER)
50
51
-struct CMSDKAPBTIMER {
52
+struct CMSDKAPBTimer {
53
/*< private >*/
54
SysBusDevice parent_obj;
55
56
diff --git a/hw/timer/cmsdk-apb-timer.c b/hw/timer/cmsdk-apb-timer.c
57
index XXXXXXX..XXXXXXX 100644
58
--- a/hw/timer/cmsdk-apb-timer.c
59
+++ b/hw/timer/cmsdk-apb-timer.c
60
@@ -XXX,XX +XXX,XX @@ static const int timer_id[] = {
61
0x0d, 0xf0, 0x05, 0xb1, /* CID0..CID3 */
62
};
63
64
-static void cmsdk_apb_timer_update(CMSDKAPBTIMER *s)
65
+static void cmsdk_apb_timer_update(CMSDKAPBTimer *s)
66
{
67
qemu_set_irq(s->timerint, !!(s->intstatus & R_INTSTATUS_IRQ_MASK));
68
}
69
70
static uint64_t cmsdk_apb_timer_read(void *opaque, hwaddr offset, unsigned size)
71
{
72
- CMSDKAPBTIMER *s = CMSDK_APB_TIMER(opaque);
73
+ CMSDKAPBTimer *s = CMSDK_APB_TIMER(opaque);
74
uint64_t r;
75
76
switch (offset) {
77
@@ -XXX,XX +XXX,XX @@ static uint64_t cmsdk_apb_timer_read(void *opaque, hwaddr offset, unsigned size)
78
static void cmsdk_apb_timer_write(void *opaque, hwaddr offset, uint64_t value,
79
unsigned size)
80
{
81
- CMSDKAPBTIMER *s = CMSDK_APB_TIMER(opaque);
82
+ CMSDKAPBTimer *s = CMSDK_APB_TIMER(opaque);
83
84
trace_cmsdk_apb_timer_write(offset, value, size);
85
86
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps cmsdk_apb_timer_ops = {
87
88
static void cmsdk_apb_timer_tick(void *opaque)
89
{
90
- CMSDKAPBTIMER *s = CMSDK_APB_TIMER(opaque);
91
+ CMSDKAPBTimer *s = CMSDK_APB_TIMER(opaque);
92
93
if (s->ctrl & R_CTRL_IRQEN_MASK) {
94
s->intstatus |= R_INTSTATUS_IRQ_MASK;
95
@@ -XXX,XX +XXX,XX @@ static void cmsdk_apb_timer_tick(void *opaque)
96
97
static void cmsdk_apb_timer_reset(DeviceState *dev)
98
{
99
- CMSDKAPBTIMER *s = CMSDK_APB_TIMER(dev);
100
+ CMSDKAPBTimer *s = CMSDK_APB_TIMER(dev);
101
102
trace_cmsdk_apb_timer_reset();
103
s->ctrl = 0;
104
@@ -XXX,XX +XXX,XX @@ static void cmsdk_apb_timer_reset(DeviceState *dev)
105
static void cmsdk_apb_timer_init(Object *obj)
106
{
107
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
108
- CMSDKAPBTIMER *s = CMSDK_APB_TIMER(obj);
109
+ CMSDKAPBTimer *s = CMSDK_APB_TIMER(obj);
110
111
memory_region_init_io(&s->iomem, obj, &cmsdk_apb_timer_ops,
112
s, "cmsdk-apb-timer", 0x1000);
113
@@ -XXX,XX +XXX,XX @@ static void cmsdk_apb_timer_init(Object *obj)
114
115
static void cmsdk_apb_timer_realize(DeviceState *dev, Error **errp)
116
{
117
- CMSDKAPBTIMER *s = CMSDK_APB_TIMER(dev);
118
+ CMSDKAPBTimer *s = CMSDK_APB_TIMER(dev);
119
120
if (s->pclk_frq == 0) {
121
error_setg(errp, "CMSDK APB timer: pclk-frq property must be set");
122
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription cmsdk_apb_timer_vmstate = {
123
.version_id = 1,
124
.minimum_version_id = 1,
125
.fields = (VMStateField[]) {
126
- VMSTATE_PTIMER(timer, CMSDKAPBTIMER),
127
- VMSTATE_UINT32(ctrl, CMSDKAPBTIMER),
128
- VMSTATE_UINT32(value, CMSDKAPBTIMER),
129
- VMSTATE_UINT32(reload, CMSDKAPBTIMER),
130
- VMSTATE_UINT32(intstatus, CMSDKAPBTIMER),
131
+ VMSTATE_PTIMER(timer, CMSDKAPBTimer),
132
+ VMSTATE_UINT32(ctrl, CMSDKAPBTimer),
133
+ VMSTATE_UINT32(value, CMSDKAPBTimer),
134
+ VMSTATE_UINT32(reload, CMSDKAPBTimer),
135
+ VMSTATE_UINT32(intstatus, CMSDKAPBTimer),
136
VMSTATE_END_OF_LIST()
137
}
138
};
139
140
static Property cmsdk_apb_timer_properties[] = {
141
- DEFINE_PROP_UINT32("pclk-frq", CMSDKAPBTIMER, pclk_frq, 0),
142
+ DEFINE_PROP_UINT32("pclk-frq", CMSDKAPBTimer, pclk_frq, 0),
143
DEFINE_PROP_END_OF_LIST(),
144
};
145
146
@@ -XXX,XX +XXX,XX @@ static void cmsdk_apb_timer_class_init(ObjectClass *klass, void *data)
147
static const TypeInfo cmsdk_apb_timer_info = {
148
.name = TYPE_CMSDK_APB_TIMER,
149
.parent = TYPE_SYS_BUS_DEVICE,
150
- .instance_size = sizeof(CMSDKAPBTIMER),
151
+ .instance_size = sizeof(CMSDKAPBTimer),
152
.instance_init = cmsdk_apb_timer_init,
153
.class_init = cmsdk_apb_timer_class_init,
154
};
155
--
156
2.20.1
157
158
diff view generated by jsdifflib
[PULL 29/46] hw/timer/cmsdk-apb-dualtimer: Add Clock input
Deleted patch
1
As the first step in converting the CMSDK_APB_DUALTIMER device to the
2
Clock framework, add a Clock input. For the moment we do nothing
3
with this clock; we will change the behaviour from using the pclk-frq
4
property to using the Clock once all the users of this device have
5
been converted to wire up the Clock.
6
1
7
We take the opportunity to correct the name of the clock input to
8
match the hardware -- the dual timer names the clock which drives the
9
timers TIMCLK. (It does also have a 'pclk' input, which is used only
10
for the register and APB bus logic; on the SSE-200 these clocks are
11
both connected together.)
12
13
This is a migration compatibility break for machines mps2-an385,
14
mps2-an386, mps2-an500, mps2-an511, mps2-an505, mps2-an521, musca-a,
15
musca-b1.
16
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
19
Reviewed-by: Luc Michel <luc@lmichel.fr>
20
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
21
Message-id: 20210128114145.20536-9-peter.maydell@linaro.org
22
Message-id: 20210121190622.22000-9-peter.maydell@linaro.org
23
---
24
include/hw/timer/cmsdk-apb-dualtimer.h | 3 +++
25
hw/timer/cmsdk-apb-dualtimer.c | 7 +++++--
26
2 files changed, 8 insertions(+), 2 deletions(-)
27
28
diff --git a/include/hw/timer/cmsdk-apb-dualtimer.h b/include/hw/timer/cmsdk-apb-dualtimer.h
29
index XXXXXXX..XXXXXXX 100644
30
--- a/include/hw/timer/cmsdk-apb-dualtimer.h
31
+++ b/include/hw/timer/cmsdk-apb-dualtimer.h
32
@@ -XXX,XX +XXX,XX @@
33
*
34
* QEMU interface:
35
* + QOM property "pclk-frq": frequency at which the timer is clocked
36
+ * + Clock input "TIMCLK": clock (for both timers)
37
* + sysbus MMIO region 0: the register bank
38
* + sysbus IRQ 0: combined timer interrupt TIMINTC
39
* + sysbus IRO 1: timer block 1 interrupt TIMINT1
40
@@ -XXX,XX +XXX,XX @@
41
42
#include "hw/sysbus.h"
43
#include "hw/ptimer.h"
44
+#include "hw/clock.h"
45
#include "qom/object.h"
46
47
#define TYPE_CMSDK_APB_DUALTIMER "cmsdk-apb-dualtimer"
48
@@ -XXX,XX +XXX,XX @@ struct CMSDKAPBDualTimer {
49
MemoryRegion iomem;
50
qemu_irq timerintc;
51
uint32_t pclk_frq;
52
+ Clock *timclk;
53
54
CMSDKAPBDualTimerModule timermod[CMSDK_APB_DUALTIMER_NUM_MODULES];
55
uint32_t timeritcr;
56
diff --git a/hw/timer/cmsdk-apb-dualtimer.c b/hw/timer/cmsdk-apb-dualtimer.c
57
index XXXXXXX..XXXXXXX 100644
58
--- a/hw/timer/cmsdk-apb-dualtimer.c
59
+++ b/hw/timer/cmsdk-apb-dualtimer.c
60
@@ -XXX,XX +XXX,XX @@
61
#include "hw/irq.h"
62
#include "hw/qdev-properties.h"
63
#include "hw/registerfields.h"
64
+#include "hw/qdev-clock.h"
65
#include "hw/timer/cmsdk-apb-dualtimer.h"
66
#include "migration/vmstate.h"
67
68
@@ -XXX,XX +XXX,XX @@ static void cmsdk_apb_dualtimer_init(Object *obj)
69
for (i = 0; i < ARRAY_SIZE(s->timermod); i++) {
70
sysbus_init_irq(sbd, &s->timermod[i].timerint);
71
}
72
+ s->timclk = qdev_init_clock_in(DEVICE(s), "TIMCLK", NULL, NULL);
73
}
74
75
static void cmsdk_apb_dualtimer_realize(DeviceState *dev, Error **errp)
76
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription cmsdk_dualtimermod_vmstate = {
77
78
static const VMStateDescription cmsdk_apb_dualtimer_vmstate = {
79
.name = "cmsdk-apb-dualtimer",
80
- .version_id = 1,
81
- .minimum_version_id = 1,
82
+ .version_id = 2,
83
+ .minimum_version_id = 2,
84
.fields = (VMStateField[]) {
85
+ VMSTATE_CLOCK(timclk, CMSDKAPBDualTimer),
86
VMSTATE_STRUCT_ARRAY(timermod, CMSDKAPBDualTimer,
87
CMSDK_APB_DUALTIMER_NUM_MODULES,
88
1, cmsdk_dualtimermod_vmstate,
89
--
90
2.20.1
91
92
diff view generated by jsdifflib
[PULL 34/46] hw/arm/mps2: Create and connect SYSCLK Clock
Deleted patch
1
Create a fixed-frequency Clock object to be the SYSCLK, and wire it
2
up to the devices that require it.
3
1
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
6
Reviewed-by: Luc Michel <luc@lmichel.fr>
7
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Message-id: 20210128114145.20536-14-peter.maydell@linaro.org
9
Message-id: 20210121190622.22000-14-peter.maydell@linaro.org
10
---
11
hw/arm/mps2.c | 9 +++++++++
12
1 file changed, 9 insertions(+)
13
14
diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/arm/mps2.c
17
+++ b/hw/arm/mps2.c
18
@@ -XXX,XX +XXX,XX @@
19
#include "hw/net/lan9118.h"
20
#include "net/net.h"
21
#include "hw/watchdog/cmsdk-apb-watchdog.h"
22
+#include "hw/qdev-clock.h"
23
#include "qom/object.h"
24
25
typedef enum MPS2FPGAType {
26
@@ -XXX,XX +XXX,XX @@ struct MPS2MachineState {
27
CMSDKAPBDualTimer dualtimer;
28
CMSDKAPBWatchdog watchdog;
29
CMSDKAPBTimer timer[2];
30
+ Clock *sysclk;
31
};
32
33
#define TYPE_MPS2_MACHINE "mps2"
34
@@ -XXX,XX +XXX,XX @@ static void mps2_common_init(MachineState *machine)
35
exit(EXIT_FAILURE);
36
}
37
38
+ /* This clock doesn't need migration because it is fixed-frequency */
39
+ mms->sysclk = clock_new(OBJECT(machine), "SYSCLK");
40
+ clock_set_hz(mms->sysclk, SYSCLK_FRQ);
41
+
42
/* The FPGA images have an odd combination of different RAMs,
43
* because in hardware they are different implementations and
44
* connected to different buses, giving varying performance/size
45
@@ -XXX,XX +XXX,XX @@ static void mps2_common_init(MachineState *machine)
46
TYPE_CMSDK_APB_TIMER);
47
sbd = SYS_BUS_DEVICE(&mms->timer[i]);
48
qdev_prop_set_uint32(DEVICE(&mms->timer[i]), "pclk-frq", SYSCLK_FRQ);
49
+ qdev_connect_clock_in(DEVICE(&mms->timer[i]), "pclk", mms->sysclk);
50
sysbus_realize_and_unref(sbd, &error_fatal);
51
sysbus_mmio_map(sbd, 0, base);
52
sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(armv7m, irqno));
53
@@ -XXX,XX +XXX,XX @@ static void mps2_common_init(MachineState *machine)
54
object_initialize_child(OBJECT(mms), "dualtimer", &mms->dualtimer,
55
TYPE_CMSDK_APB_DUALTIMER);
56
qdev_prop_set_uint32(DEVICE(&mms->dualtimer), "pclk-frq", SYSCLK_FRQ);
57
+ qdev_connect_clock_in(DEVICE(&mms->dualtimer), "TIMCLK", mms->sysclk);
58
sysbus_realize(SYS_BUS_DEVICE(&mms->dualtimer), &error_fatal);
59
sysbus_connect_irq(SYS_BUS_DEVICE(&mms->dualtimer), 0,
60
qdev_get_gpio_in(armv7m, 10));
61
@@ -XXX,XX +XXX,XX @@ static void mps2_common_init(MachineState *machine)
62
object_initialize_child(OBJECT(mms), "watchdog", &mms->watchdog,
63
TYPE_CMSDK_APB_WATCHDOG);
64
qdev_prop_set_uint32(DEVICE(&mms->watchdog), "wdogclk-frq", SYSCLK_FRQ);
65
+ qdev_connect_clock_in(DEVICE(&mms->watchdog), "WDOGCLK", mms->sysclk);
66
sysbus_realize(SYS_BUS_DEVICE(&mms->watchdog), &error_fatal);
67
sysbus_connect_irq(SYS_BUS_DEVICE(&mms->watchdog), 0,
68
qdev_get_gpio_in_named(armv7m, "NMI", 0));
69
--
70
2.20.1
71
72
diff view generated by jsdifflib
[PULL 35/46] hw/arm/mps2-tz: Create and connect ARMSSE Clocks
Deleted patch
1
Create and connect the two clocks needed by the ARMSSE.
2
1
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
5
Reviewed-by: Luc Michel <luc@lmichel.fr>
6
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
7
Message-id: 20210128114145.20536-15-peter.maydell@linaro.org
8
Message-id: 20210121190622.22000-15-peter.maydell@linaro.org
9
---
10
hw/arm/mps2-tz.c | 13 +++++++++++++
11
1 file changed, 13 insertions(+)
12
13
diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c
14
index XXXXXXX..XXXXXXX 100644
15
--- a/hw/arm/mps2-tz.c
16
+++ b/hw/arm/mps2-tz.c
17
@@ -XXX,XX +XXX,XX @@
18
#include "hw/net/lan9118.h"
19
#include "net/net.h"
20
#include "hw/core/split-irq.h"
21
+#include "hw/qdev-clock.h"
22
#include "qom/object.h"
23
24
#define MPS2TZ_NUMIRQ 92
25
@@ -XXX,XX +XXX,XX @@ struct MPS2TZMachineState {
26
qemu_or_irq uart_irq_orgate;
27
DeviceState *lan9118;
28
SplitIRQ cpu_irq_splitter[MPS2TZ_NUMIRQ];
29
+ Clock *sysclk;
30
+ Clock *s32kclk;
31
};
32
33
#define TYPE_MPS2TZ_MACHINE "mps2tz"
34
@@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_TYPE(MPS2TZMachineState, MPS2TZMachineClass, MPS2TZ_MACHINE)
35
36
/* Main SYSCLK frequency in Hz */
37
#define SYSCLK_FRQ 20000000
38
+/* Slow 32Khz S32KCLK frequency in Hz */
39
+#define S32KCLK_FRQ (32 * 1000)
40
41
/* Create an alias of an entire original MemoryRegion @orig
42
* located at @base in the memory map.
43
@@ -XXX,XX +XXX,XX @@ static void mps2tz_common_init(MachineState *machine)
44
exit(EXIT_FAILURE);
45
}
46
47
+ /* These clocks don't need migration because they are fixed-frequency */
48
+ mms->sysclk = clock_new(OBJECT(machine), "SYSCLK");
49
+ clock_set_hz(mms->sysclk, SYSCLK_FRQ);
50
+ mms->s32kclk = clock_new(OBJECT(machine), "S32KCLK");
51
+ clock_set_hz(mms->s32kclk, S32KCLK_FRQ);
52
+
53
object_initialize_child(OBJECT(machine), TYPE_IOTKIT, &mms->iotkit,
54
mmc->armsse_type);
55
iotkitdev = DEVICE(&mms->iotkit);
56
@@ -XXX,XX +XXX,XX @@ static void mps2tz_common_init(MachineState *machine)
57
OBJECT(system_memory), &error_abort);
58
qdev_prop_set_uint32(iotkitdev, "EXP_NUMIRQ", MPS2TZ_NUMIRQ);
59
qdev_prop_set_uint32(iotkitdev, "MAINCLK_FRQ", SYSCLK_FRQ);
60
+ qdev_connect_clock_in(iotkitdev, "MAINCLK", mms->sysclk);
61
+ qdev_connect_clock_in(iotkitdev, "S32KCLK", mms->s32kclk);
62
sysbus_realize(SYS_BUS_DEVICE(&mms->iotkit), &error_fatal);
63
64
/*
65
--
66
2.20.1
67
68
diff view generated by jsdifflib
[PULL 36/46] hw/arm/musca: Create and connect ARMSSE Clocks
Deleted patch
1
Create and connect the two clocks needed by the ARMSSE.
2
1
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
5
Reviewed-by: Luc Michel <luc@lmichel.fr>
6
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
7
Message-id: 20210128114145.20536-16-peter.maydell@linaro.org
8
Message-id: 20210121190622.22000-16-peter.maydell@linaro.org
9
---
10
hw/arm/musca.c | 12 ++++++++++++
11
1 file changed, 12 insertions(+)
12
13
diff --git a/hw/arm/musca.c b/hw/arm/musca.c
14
index XXXXXXX..XXXXXXX 100644
15
--- a/hw/arm/musca.c
16
+++ b/hw/arm/musca.c
17
@@ -XXX,XX +XXX,XX @@
18
#include "hw/misc/tz-ppc.h"
19
#include "hw/misc/unimp.h"
20
#include "hw/rtc/pl031.h"
21
+#include "hw/qdev-clock.h"
22
#include "qom/object.h"
23
24
#define MUSCA_NUMIRQ_MAX 96
25
@@ -XXX,XX +XXX,XX @@ struct MuscaMachineState {
26
UnimplementedDeviceState sdio;
27
UnimplementedDeviceState gpio;
28
UnimplementedDeviceState cryptoisland;
29
+ Clock *sysclk;
30
+ Clock *s32kclk;
31
};
32
33
#define TYPE_MUSCA_MACHINE "musca"
34
@@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_TYPE(MuscaMachineState, MuscaMachineClass, MUSCA_MACHINE)
35
* don't model that in our SSE-200 model yet.
36
*/
37
#define SYSCLK_FRQ 40000000
38
+/* Slow 32Khz S32KCLK frequency in Hz */
39
+#define S32KCLK_FRQ (32 * 1000)
40
41
static qemu_irq get_sse_irq_in(MuscaMachineState *mms, int irqno)
42
{
43
@@ -XXX,XX +XXX,XX @@ static void musca_init(MachineState *machine)
44
exit(1);
45
}
46
47
+ mms->sysclk = clock_new(OBJECT(machine), "SYSCLK");
48
+ clock_set_hz(mms->sysclk, SYSCLK_FRQ);
49
+ mms->s32kclk = clock_new(OBJECT(machine), "S32KCLK");
50
+ clock_set_hz(mms->s32kclk, S32KCLK_FRQ);
51
+
52
object_initialize_child(OBJECT(machine), "sse-200", &mms->sse,
53
TYPE_SSE200);
54
ssedev = DEVICE(&mms->sse);
55
@@ -XXX,XX +XXX,XX @@ static void musca_init(MachineState *machine)
56
qdev_prop_set_uint32(ssedev, "init-svtor", mmc->init_svtor);
57
qdev_prop_set_uint32(ssedev, "SRAM_ADDR_WIDTH", mmc->sram_addr_width);
58
qdev_prop_set_uint32(ssedev, "MAINCLK_FRQ", SYSCLK_FRQ);
59
+ qdev_connect_clock_in(ssedev, "MAINCLK", mms->sysclk);
60
+ qdev_connect_clock_in(ssedev, "S32KCLK", mms->s32kclk);
61
/*
62
* Musca-A takes the default SSE-200 FPU/DSP settings (ie no for
63
* CPU0 and yes for CPU1); Musca-B1 explicitly enables them for CPU0.
64
--
65
2.20.1
66
67
diff view generated by jsdifflib
[PULL 38/46] hw/arm/stellaris: Create Clock input for watchdog
Deleted patch
1
Create and connect the Clock input for the watchdog device on the
2
Stellaris boards. Because the Stellaris boards model the ability to
3
change the clock rate by programming PLL registers, we have to create
4
an output Clock on the ssys_state device and wire it up to the
5
watchdog.
6
1
7
Note that the old comment on ssys_calculate_system_clock() got the
8
units wrong -- system_clock_scale is in nanoseconds, not
9
milliseconds. Improve the commentary to clarify how we are
10
calculating the period.
11
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Reviewed-by: Luc Michel <luc@lmichel.fr>
14
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
15
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
16
Message-id: 20210128114145.20536-18-peter.maydell@linaro.org
17
Message-id: 20210121190622.22000-18-peter.maydell@linaro.org
18
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
19
---
20
hw/arm/stellaris.c | 43 +++++++++++++++++++++++++++++++------------
21
1 file changed, 31 insertions(+), 12 deletions(-)
22
23
diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
24
index XXXXXXX..XXXXXXX 100644
25
--- a/hw/arm/stellaris.c
26
+++ b/hw/arm/stellaris.c
27
@@ -XXX,XX +XXX,XX @@
28
#include "hw/watchdog/cmsdk-apb-watchdog.h"
29
#include "migration/vmstate.h"
30
#include "hw/misc/unimp.h"
31
+#include "hw/qdev-clock.h"
32
#include "cpu.h"
33
#include "qom/object.h"
34
35
@@ -XXX,XX +XXX,XX @@ struct ssys_state {
36
uint32_t clkvclr;
37
uint32_t ldoarst;
38
qemu_irq irq;
39
+ Clock *sysclk;
40
/* Properties (all read-only registers) */
41
uint32_t user0;
42
uint32_t user1;
43
@@ -XXX,XX +XXX,XX @@ static bool ssys_use_rcc2(ssys_state *s)
44
}
45
46
/*
47
- * Caculate the sys. clock period in ms.
48
+ * Calculate the system clock period. We only want to propagate
49
+ * this change to the rest of the system if we're not being called
50
+ * from migration post-load.
51
*/
52
-static void ssys_calculate_system_clock(ssys_state *s)
53
+static void ssys_calculate_system_clock(ssys_state *s, bool propagate_clock)
54
{
55
+ /*
56
+ * SYSDIV field specifies divisor: 0 == /1, 1 == /2, etc. Input
57
+ * clock is 200MHz, which is a period of 5 ns. Dividing the clock
58
+ * frequency by X is the same as multiplying the period by X.
59
+ */
60
if (ssys_use_rcc2(s)) {
61
system_clock_scale = 5 * (((s->rcc2 >> 23) & 0x3f) + 1);
62
} else {
63
system_clock_scale = 5 * (((s->rcc >> 23) & 0xf) + 1);
64
}
65
+ clock_set_ns(s->sysclk, system_clock_scale);
66
+ if (propagate_clock) {
67
+ clock_propagate(s->sysclk);
68
+ }
69
}
70
71
static void ssys_write(void *opaque, hwaddr offset,
72
@@ -XXX,XX +XXX,XX @@ static void ssys_write(void *opaque, hwaddr offset,
73
s->int_status |= (1 << 6);
74
}
75
s->rcc = value;
76
- ssys_calculate_system_clock(s);
77
+ ssys_calculate_system_clock(s, true);
78
break;
79
case 0x070: /* RCC2 */
80
if (ssys_board_class(s) == DID0_CLASS_SANDSTORM) {
81
@@ -XXX,XX +XXX,XX @@ static void ssys_write(void *opaque, hwaddr offset,
82
s->int_status |= (1 << 6);
83
}
84
s->rcc2 = value;
85
- ssys_calculate_system_clock(s);
86
+ ssys_calculate_system_clock(s, true);
87
break;
88
case 0x100: /* RCGC0 */
89
s->rcgc[0] = value;
90
@@ -XXX,XX +XXX,XX @@ static void stellaris_sys_reset_hold(Object *obj)
91
{
92
ssys_state *s = STELLARIS_SYS(obj);
93
94
- ssys_calculate_system_clock(s);
95
+ /* OK to propagate clocks from the hold phase */
96
+ ssys_calculate_system_clock(s, true);
97
}
98
99
static void stellaris_sys_reset_exit(Object *obj)
100
@@ -XXX,XX +XXX,XX @@ static int stellaris_sys_post_load(void *opaque, int version_id)
101
{
102
ssys_state *s = opaque;
103
104
- ssys_calculate_system_clock(s);
105
+ ssys_calculate_system_clock(s, false);
106
107
return 0;
108
}
109
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_stellaris_sys = {
110
VMSTATE_UINT32_ARRAY(dcgc, ssys_state, 3),
111
VMSTATE_UINT32(clkvclr, ssys_state),
112
VMSTATE_UINT32(ldoarst, ssys_state),
113
+ /* No field for sysclk -- handled in post-load instead */
114
VMSTATE_END_OF_LIST()
115
}
116
};
117
@@ -XXX,XX +XXX,XX @@ static void stellaris_sys_instance_init(Object *obj)
118
memory_region_init_io(&s->iomem, obj, &ssys_ops, s, "ssys", 0x00001000);
119
sysbus_init_mmio(sbd, &s->iomem);
120
sysbus_init_irq(sbd, &s->irq);
121
+ s->sysclk = qdev_init_clock_out(DEVICE(s), "SYSCLK");
122
}
123
124
-static int stellaris_sys_init(uint32_t base, qemu_irq irq,
125
- stellaris_board_info * board,
126
- uint8_t *macaddr)
127
+static DeviceState *stellaris_sys_init(uint32_t base, qemu_irq irq,
128
+ stellaris_board_info *board,
129
+ uint8_t *macaddr)
130
{
131
DeviceState *dev = qdev_new(TYPE_STELLARIS_SYS);
132
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
133
@@ -XXX,XX +XXX,XX @@ static int stellaris_sys_init(uint32_t base, qemu_irq irq,
134
*/
135
device_cold_reset(dev);
136
137
- return 0;
138
+ return dev;
139
}
140
141
/* I2C controller. */
142
@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
143
int flash_size;
144
I2CBus *i2c;
145
DeviceState *dev;
146
+ DeviceState *ssys_dev;
147
int i;
148
int j;
149
150
@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
151
}
152
}
153
154
- stellaris_sys_init(0x400fe000, qdev_get_gpio_in(nvic, 28),
155
- board, nd_table[0].macaddr.a);
156
+ ssys_dev = stellaris_sys_init(0x400fe000, qdev_get_gpio_in(nvic, 28),
157
+ board, nd_table[0].macaddr.a);
158
159
160
if (board->dc1 & (1 << 3)) { /* watchdog present */
161
@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
162
/* system_clock_scale is valid now */
163
uint32_t mainclk = NANOSECONDS_PER_SECOND / system_clock_scale;
164
qdev_prop_set_uint32(dev, "wdogclk-frq", mainclk);
165
+ qdev_connect_clock_in(dev, "WDOGCLK",
166
+ qdev_get_clock_out(ssys_dev, "SYSCLK"));
167
168
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
169
sysbus_mmio_map(SYS_BUS_DEVICE(dev),
170
--
171
2.20.1
172
173
diff view generated by jsdifflib
[PULL 44/46] arm: Don't set freq properties on CMSDK timer, dualtimer, watchdog, ARMSSE
Deleted patch
1
Remove all the code that sets frequency properties on the CMSDK
2
timer, dualtimer and watchdog devices and on the ARMSSE SoC device:
3
these properties are unused now that the devices rely on their Clock
4
inputs instead.
5
1
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Reviewed-by: Luc Michel <luc@lmichel.fr>
9
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
10
Message-id: 20210128114145.20536-24-peter.maydell@linaro.org
11
Message-id: 20210121190622.22000-24-peter.maydell@linaro.org
12
---
13
hw/arm/armsse.c | 7 -------
14
hw/arm/mps2-tz.c | 1 -
15
hw/arm/mps2.c | 3 ---
16
hw/arm/musca.c | 1 -
17
hw/arm/stellaris.c | 3 ---
18
5 files changed, 15 deletions(-)
19
20
diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c
21
index XXXXXXX..XXXXXXX 100644
22
--- a/hw/arm/armsse.c
23
+++ b/hw/arm/armsse.c
24
@@ -XXX,XX +XXX,XX @@ static void armsse_realize(DeviceState *dev, Error **errp)
25
* it to the appropriate PPC port; then we can realize the PPC and
26
* map its upstream ends to the right place in the container.
27
*/
28
- qdev_prop_set_uint32(DEVICE(&s->timer0), "pclk-frq", s->mainclk_frq);
29
qdev_connect_clock_in(DEVICE(&s->timer0), "pclk", s->mainclk);
30
if (!sysbus_realize(SYS_BUS_DEVICE(&s->timer0), errp)) {
31
return;
32
@@ -XXX,XX +XXX,XX @@ static void armsse_realize(DeviceState *dev, Error **errp)
33
object_property_set_link(OBJECT(&s->apb_ppc0), "port[0]", OBJECT(mr),
34
&error_abort);
35
36
- qdev_prop_set_uint32(DEVICE(&s->timer1), "pclk-frq", s->mainclk_frq);
37
qdev_connect_clock_in(DEVICE(&s->timer1), "pclk", s->mainclk);
38
if (!sysbus_realize(SYS_BUS_DEVICE(&s->timer1), errp)) {
39
return;
40
@@ -XXX,XX +XXX,XX @@ static void armsse_realize(DeviceState *dev, Error **errp)
41
object_property_set_link(OBJECT(&s->apb_ppc0), "port[1]", OBJECT(mr),
42
&error_abort);
43
44
- qdev_prop_set_uint32(DEVICE(&s->dualtimer), "pclk-frq", s->mainclk_frq);
45
qdev_connect_clock_in(DEVICE(&s->dualtimer), "TIMCLK", s->mainclk);
46
if (!sysbus_realize(SYS_BUS_DEVICE(&s->dualtimer), errp)) {
47
return;
48
@@ -XXX,XX +XXX,XX @@ static void armsse_realize(DeviceState *dev, Error **errp)
49
/* Devices behind APB PPC1:
50
* 0x4002f000: S32K timer
51
*/
52
- qdev_prop_set_uint32(DEVICE(&s->s32ktimer), "pclk-frq", S32KCLK);
53
qdev_connect_clock_in(DEVICE(&s->s32ktimer), "pclk", s->s32kclk);
54
if (!sysbus_realize(SYS_BUS_DEVICE(&s->s32ktimer), errp)) {
55
return;
56
@@ -XXX,XX +XXX,XX @@ static void armsse_realize(DeviceState *dev, Error **errp)
57
qdev_connect_gpio_out(DEVICE(&s->nmi_orgate), 0,
58
qdev_get_gpio_in_named(DEVICE(&s->armv7m), "NMI", 0));
59
60
- qdev_prop_set_uint32(DEVICE(&s->s32kwatchdog), "wdogclk-frq", S32KCLK);
61
qdev_connect_clock_in(DEVICE(&s->s32kwatchdog), "WDOGCLK", s->s32kclk);
62
if (!sysbus_realize(SYS_BUS_DEVICE(&s->s32kwatchdog), errp)) {
63
return;
64
@@ -XXX,XX +XXX,XX @@ static void armsse_realize(DeviceState *dev, Error **errp)
65
66
/* 0x40080000 .. 0x4008ffff : ARMSSE second Base peripheral region */
67
68
- qdev_prop_set_uint32(DEVICE(&s->nswatchdog), "wdogclk-frq", s->mainclk_frq);
69
qdev_connect_clock_in(DEVICE(&s->nswatchdog), "WDOGCLK", s->mainclk);
70
if (!sysbus_realize(SYS_BUS_DEVICE(&s->nswatchdog), errp)) {
71
return;
72
@@ -XXX,XX +XXX,XX @@ static void armsse_realize(DeviceState *dev, Error **errp)
73
armsse_get_common_irq_in(s, 1));
74
sysbus_mmio_map(SYS_BUS_DEVICE(&s->nswatchdog), 0, 0x40081000);
75
76
- qdev_prop_set_uint32(DEVICE(&s->swatchdog), "wdogclk-frq", s->mainclk_frq);
77
qdev_connect_clock_in(DEVICE(&s->swatchdog), "WDOGCLK", s->mainclk);
78
if (!sysbus_realize(SYS_BUS_DEVICE(&s->swatchdog), errp)) {
79
return;
80
diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c
81
index XXXXXXX..XXXXXXX 100644
82
--- a/hw/arm/mps2-tz.c
83
+++ b/hw/arm/mps2-tz.c
84
@@ -XXX,XX +XXX,XX @@ static void mps2tz_common_init(MachineState *machine)
85
object_property_set_link(OBJECT(&mms->iotkit), "memory",
86
OBJECT(system_memory), &error_abort);
87
qdev_prop_set_uint32(iotkitdev, "EXP_NUMIRQ", MPS2TZ_NUMIRQ);
88
- qdev_prop_set_uint32(iotkitdev, "MAINCLK_FRQ", SYSCLK_FRQ);
89
qdev_connect_clock_in(iotkitdev, "MAINCLK", mms->sysclk);
90
qdev_connect_clock_in(iotkitdev, "S32KCLK", mms->s32kclk);
91
sysbus_realize(SYS_BUS_DEVICE(&mms->iotkit), &error_fatal);
92
diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c
93
index XXXXXXX..XXXXXXX 100644
94
--- a/hw/arm/mps2.c
95
+++ b/hw/arm/mps2.c
96
@@ -XXX,XX +XXX,XX @@ static void mps2_common_init(MachineState *machine)
97
object_initialize_child(OBJECT(mms), name, &mms->timer[i],
98
TYPE_CMSDK_APB_TIMER);
99
sbd = SYS_BUS_DEVICE(&mms->timer[i]);
100
- qdev_prop_set_uint32(DEVICE(&mms->timer[i]), "pclk-frq", SYSCLK_FRQ);
101
qdev_connect_clock_in(DEVICE(&mms->timer[i]), "pclk", mms->sysclk);
102
sysbus_realize_and_unref(sbd, &error_fatal);
103
sysbus_mmio_map(sbd, 0, base);
104
@@ -XXX,XX +XXX,XX @@ static void mps2_common_init(MachineState *machine)
105
106
object_initialize_child(OBJECT(mms), "dualtimer", &mms->dualtimer,
107
TYPE_CMSDK_APB_DUALTIMER);
108
- qdev_prop_set_uint32(DEVICE(&mms->dualtimer), "pclk-frq", SYSCLK_FRQ);
109
qdev_connect_clock_in(DEVICE(&mms->dualtimer), "TIMCLK", mms->sysclk);
110
sysbus_realize(SYS_BUS_DEVICE(&mms->dualtimer), &error_fatal);
111
sysbus_connect_irq(SYS_BUS_DEVICE(&mms->dualtimer), 0,
112
@@ -XXX,XX +XXX,XX @@ static void mps2_common_init(MachineState *machine)
113
sysbus_mmio_map(SYS_BUS_DEVICE(&mms->dualtimer), 0, 0x40002000);
114
object_initialize_child(OBJECT(mms), "watchdog", &mms->watchdog,
115
TYPE_CMSDK_APB_WATCHDOG);
116
- qdev_prop_set_uint32(DEVICE(&mms->watchdog), "wdogclk-frq", SYSCLK_FRQ);
117
qdev_connect_clock_in(DEVICE(&mms->watchdog), "WDOGCLK", mms->sysclk);
118
sysbus_realize(SYS_BUS_DEVICE(&mms->watchdog), &error_fatal);
119
sysbus_connect_irq(SYS_BUS_DEVICE(&mms->watchdog), 0,
120
diff --git a/hw/arm/musca.c b/hw/arm/musca.c
121
index XXXXXXX..XXXXXXX 100644
122
--- a/hw/arm/musca.c
123
+++ b/hw/arm/musca.c
124
@@ -XXX,XX +XXX,XX @@ static void musca_init(MachineState *machine)
125
qdev_prop_set_uint32(ssedev, "EXP_NUMIRQ", mmc->num_irqs);
126
qdev_prop_set_uint32(ssedev, "init-svtor", mmc->init_svtor);
127
qdev_prop_set_uint32(ssedev, "SRAM_ADDR_WIDTH", mmc->sram_addr_width);
128
- qdev_prop_set_uint32(ssedev, "MAINCLK_FRQ", SYSCLK_FRQ);
129
qdev_connect_clock_in(ssedev, "MAINCLK", mms->sysclk);
130
qdev_connect_clock_in(ssedev, "S32KCLK", mms->s32kclk);
131
/*
132
diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
133
index XXXXXXX..XXXXXXX 100644
134
--- a/hw/arm/stellaris.c
135
+++ b/hw/arm/stellaris.c
136
@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
137
if (board->dc1 & (1 << 3)) { /* watchdog present */
138
dev = qdev_new(TYPE_LUMINARY_WATCHDOG);
139
140
- /* system_clock_scale is valid now */
141
- uint32_t mainclk = NANOSECONDS_PER_SECOND / system_clock_scale;
142
- qdev_prop_set_uint32(dev, "wdogclk-frq", mainclk);
143
qdev_connect_clock_in(dev, "WDOGCLK",
144
qdev_get_clock_out(ssys_dev, "SYSCLK"));
145
146
--
147
2.20.1
148
149
diff view generated by jsdifflib
[PULL 45/46] arm: Remove frq properties on CMSDK timer, dualtimer, watchdog, ARMSSE
Deleted patch
1
Now no users are setting the frq properties on the CMSDK timer,
2
dualtimer, watchdog or ARMSSE SoC devices, we can remove the
3
properties and the struct fields that back them.
4
1
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
7
Reviewed-by: Luc Michel <luc@lmichel.fr>
8
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
Message-id: 20210128114145.20536-25-peter.maydell@linaro.org
10
Message-id: 20210121190622.22000-25-peter.maydell@linaro.org
11
---
12
include/hw/arm/armsse.h | 2 --
13
include/hw/timer/cmsdk-apb-dualtimer.h | 2 --
14
include/hw/timer/cmsdk-apb-timer.h | 2 --
15
include/hw/watchdog/cmsdk-apb-watchdog.h | 2 --
16
hw/arm/armsse.c | 2 --
17
hw/timer/cmsdk-apb-dualtimer.c | 6 ------
18
hw/timer/cmsdk-apb-timer.c | 6 ------
19
hw/watchdog/cmsdk-apb-watchdog.c | 6 ------
20
8 files changed, 28 deletions(-)
21
22
diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h
23
index XXXXXXX..XXXXXXX 100644
24
--- a/include/hw/arm/armsse.h
25
+++ b/include/hw/arm/armsse.h
26
@@ -XXX,XX +XXX,XX @@
27
* + Clock input "S32KCLK": slow 32KHz clock used for a few peripherals
28
* + QOM property "memory" is a MemoryRegion containing the devices provided
29
* by the board model.
30
- * + QOM property "MAINCLK_FRQ" is the frequency of the main system clock
31
* + QOM property "EXP_NUMIRQ" sets the number of expansion interrupts.
32
* (In hardware, the SSE-200 permits the number of expansion interrupts
33
* for the two CPUs to be configured separately, but we restrict it to
34
@@ -XXX,XX +XXX,XX @@ struct ARMSSE {
35
/* Properties */
36
MemoryRegion *board_memory;
37
uint32_t exp_numirq;
38
- uint32_t mainclk_frq;
39
uint32_t sram_addr_width;
40
uint32_t init_svtor;
41
bool cpu_fpu[SSE_MAX_CPUS];
42
diff --git a/include/hw/timer/cmsdk-apb-dualtimer.h b/include/hw/timer/cmsdk-apb-dualtimer.h
43
index XXXXXXX..XXXXXXX 100644
44
--- a/include/hw/timer/cmsdk-apb-dualtimer.h
45
+++ b/include/hw/timer/cmsdk-apb-dualtimer.h
46
@@ -XXX,XX +XXX,XX @@
47
* https://developer.arm.com/products/system-design/system-design-kits/cortex-m-system-design-kit
48
*
49
* QEMU interface:
50
- * + QOM property "pclk-frq": frequency at which the timer is clocked
51
* + Clock input "TIMCLK": clock (for both timers)
52
* + sysbus MMIO region 0: the register bank
53
* + sysbus IRQ 0: combined timer interrupt TIMINTC
54
@@ -XXX,XX +XXX,XX @@ struct CMSDKAPBDualTimer {
55
/*< public >*/
56
MemoryRegion iomem;
57
qemu_irq timerintc;
58
- uint32_t pclk_frq;
59
Clock *timclk;
60
61
CMSDKAPBDualTimerModule timermod[CMSDK_APB_DUALTIMER_NUM_MODULES];
62
diff --git a/include/hw/timer/cmsdk-apb-timer.h b/include/hw/timer/cmsdk-apb-timer.h
63
index XXXXXXX..XXXXXXX 100644
64
--- a/include/hw/timer/cmsdk-apb-timer.h
65
+++ b/include/hw/timer/cmsdk-apb-timer.h
66
@@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_SIMPLE_TYPE(CMSDKAPBTimer, CMSDK_APB_TIMER)
67
68
/*
69
* QEMU interface:
70
- * + QOM property "pclk-frq": frequency at which the timer is clocked
71
* + Clock input "pclk": clock for the timer
72
* + sysbus MMIO region 0: the register bank
73
* + sysbus IRQ 0: timer interrupt TIMERINT
74
@@ -XXX,XX +XXX,XX @@ struct CMSDKAPBTimer {
75
/*< public >*/
76
MemoryRegion iomem;
77
qemu_irq timerint;
78
- uint32_t pclk_frq;
79
struct ptimer_state *timer;
80
Clock *pclk;
81
82
diff --git a/include/hw/watchdog/cmsdk-apb-watchdog.h b/include/hw/watchdog/cmsdk-apb-watchdog.h
83
index XXXXXXX..XXXXXXX 100644
84
--- a/include/hw/watchdog/cmsdk-apb-watchdog.h
85
+++ b/include/hw/watchdog/cmsdk-apb-watchdog.h
86
@@ -XXX,XX +XXX,XX @@
87
* https://developer.arm.com/products/system-design/system-design-kits/cortex-m-system-design-kit
88
*
89
* QEMU interface:
90
- * + QOM property "wdogclk-frq": frequency at which the watchdog is clocked
91
* + Clock input "WDOGCLK": clock for the watchdog's timer
92
* + sysbus MMIO region 0: the register bank
93
* + sysbus IRQ 0: watchdog interrupt
94
@@ -XXX,XX +XXX,XX @@ struct CMSDKAPBWatchdog {
95
/*< public >*/
96
MemoryRegion iomem;
97
qemu_irq wdogint;
98
- uint32_t wdogclk_frq;
99
bool is_luminary;
100
struct ptimer_state *timer;
101
Clock *wdogclk;
102
diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c
103
index XXXXXXX..XXXXXXX 100644
104
--- a/hw/arm/armsse.c
105
+++ b/hw/arm/armsse.c
106
@@ -XXX,XX +XXX,XX @@ static Property iotkit_properties[] = {
107
DEFINE_PROP_LINK("memory", ARMSSE, board_memory, TYPE_MEMORY_REGION,
108
MemoryRegion *),
109
DEFINE_PROP_UINT32("EXP_NUMIRQ", ARMSSE, exp_numirq, 64),
110
- DEFINE_PROP_UINT32("MAINCLK_FRQ", ARMSSE, mainclk_frq, 0),
111
DEFINE_PROP_UINT32("SRAM_ADDR_WIDTH", ARMSSE, sram_addr_width, 15),
112
DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000),
113
DEFINE_PROP_BOOL("CPU0_FPU", ARMSSE, cpu_fpu[0], true),
114
@@ -XXX,XX +XXX,XX @@ static Property armsse_properties[] = {
115
DEFINE_PROP_LINK("memory", ARMSSE, board_memory, TYPE_MEMORY_REGION,
116
MemoryRegion *),
117
DEFINE_PROP_UINT32("EXP_NUMIRQ", ARMSSE, exp_numirq, 64),
118
- DEFINE_PROP_UINT32("MAINCLK_FRQ", ARMSSE, mainclk_frq, 0),
119
DEFINE_PROP_UINT32("SRAM_ADDR_WIDTH", ARMSSE, sram_addr_width, 15),
120
DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000),
121
DEFINE_PROP_BOOL("CPU0_FPU", ARMSSE, cpu_fpu[0], false),
122
diff --git a/hw/timer/cmsdk-apb-dualtimer.c b/hw/timer/cmsdk-apb-dualtimer.c
123
index XXXXXXX..XXXXXXX 100644
124
--- a/hw/timer/cmsdk-apb-dualtimer.c
125
+++ b/hw/timer/cmsdk-apb-dualtimer.c
126
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription cmsdk_apb_dualtimer_vmstate = {
127
}
128
};
129
130
-static Property cmsdk_apb_dualtimer_properties[] = {
131
- DEFINE_PROP_UINT32("pclk-frq", CMSDKAPBDualTimer, pclk_frq, 0),
132
- DEFINE_PROP_END_OF_LIST(),
133
-};
134
-
135
static void cmsdk_apb_dualtimer_class_init(ObjectClass *klass, void *data)
136
{
137
DeviceClass *dc = DEVICE_CLASS(klass);
138
@@ -XXX,XX +XXX,XX @@ static void cmsdk_apb_dualtimer_class_init(ObjectClass *klass, void *data)
139
dc->realize = cmsdk_apb_dualtimer_realize;
140
dc->vmsd = &cmsdk_apb_dualtimer_vmstate;
141
dc->reset = cmsdk_apb_dualtimer_reset;
142
- device_class_set_props(dc, cmsdk_apb_dualtimer_properties);
143
}
144
145
static const TypeInfo cmsdk_apb_dualtimer_info = {
146
diff --git a/hw/timer/cmsdk-apb-timer.c b/hw/timer/cmsdk-apb-timer.c
147
index XXXXXXX..XXXXXXX 100644
148
--- a/hw/timer/cmsdk-apb-timer.c
149
+++ b/hw/timer/cmsdk-apb-timer.c
150
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription cmsdk_apb_timer_vmstate = {
151
}
152
};
153
154
-static Property cmsdk_apb_timer_properties[] = {
155
- DEFINE_PROP_UINT32("pclk-frq", CMSDKAPBTimer, pclk_frq, 0),
156
- DEFINE_PROP_END_OF_LIST(),
157
-};
158
-
159
static void cmsdk_apb_timer_class_init(ObjectClass *klass, void *data)
160
{
161
DeviceClass *dc = DEVICE_CLASS(klass);
162
@@ -XXX,XX +XXX,XX @@ static void cmsdk_apb_timer_class_init(ObjectClass *klass, void *data)
163
dc->realize = cmsdk_apb_timer_realize;
164
dc->vmsd = &cmsdk_apb_timer_vmstate;
165
dc->reset = cmsdk_apb_timer_reset;
166
- device_class_set_props(dc, cmsdk_apb_timer_properties);
167
}
168
169
static const TypeInfo cmsdk_apb_timer_info = {
170
diff --git a/hw/watchdog/cmsdk-apb-watchdog.c b/hw/watchdog/cmsdk-apb-watchdog.c
171
index XXXXXXX..XXXXXXX 100644
172
--- a/hw/watchdog/cmsdk-apb-watchdog.c
173
+++ b/hw/watchdog/cmsdk-apb-watchdog.c
174
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription cmsdk_apb_watchdog_vmstate = {
175
}
176
};
177
178
-static Property cmsdk_apb_watchdog_properties[] = {
179
- DEFINE_PROP_UINT32("wdogclk-frq", CMSDKAPBWatchdog, wdogclk_frq, 0),
180
- DEFINE_PROP_END_OF_LIST(),
181
-};
182
-
183
static void cmsdk_apb_watchdog_class_init(ObjectClass *klass, void *data)
184
{
185
DeviceClass *dc = DEVICE_CLASS(klass);
186
@@ -XXX,XX +XXX,XX @@ static void cmsdk_apb_watchdog_class_init(ObjectClass *klass, void *data)
187
dc->realize = cmsdk_apb_watchdog_realize;
188
dc->vmsd = &cmsdk_apb_watchdog_vmstate;
189
dc->reset = cmsdk_apb_watchdog_reset;
190
- device_class_set_props(dc, cmsdk_apb_watchdog_properties);
191
}
192
193
static const TypeInfo cmsdk_apb_watchdog_info = {
194
--
195
2.20.1
196
197
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