[PULL 00/10] tcg patch queue
[PULL v2.5 00/27] tcg patch queue
1
The following changes since commit 0e32462630687a18039464511bd0447ada5709c3:
1
v2: Fix target/loongarch printf formats for vaddr
2
Include two more reviewed patches.
2
3
3
Merge remote-tracking branch 'remotes/vivier2/tags/linux-user-for-6.0-pull-request' into staging (2021-01-22 10:35:55 +0000)
4
This time with actual pull urls. :-/
5
6
r~
7
8
9
The following changes since commit db7aa99ef894e88fc5eedf02ca2579b8c344b2ec:
10
11
Merge tag 'hw-misc-20250216' of https://github.com/philmd/qemu into staging (2025-02-16 20:48:06 -0500)
4
12
5
are available in the Git repository at:
13
are available in the Git repository at:
6
14
7
https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20210123
15
https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20250215-2
8
16
9
for you to fetch changes up to 2e34067e9959f149a904cf1255985d3b68b52566:
17
for you to fetch changes up to a39bdd0f4ba96fcbb6b5bcb6e89591d2b24f52eb:
10
18
11
tcg: Toggle page execution for Apple Silicon (2021-01-22 12:48:01 -1000)
19
tcg: Remove TCG_TARGET_HAS_{br,set}cond2 from riscv and loongarch64 (2025-02-17 09:52:07 -0800)
12
20
13
----------------------------------------------------------------
21
----------------------------------------------------------------
14
Fix tcg constant segv.
22
tcg: Remove last traces of TCG_TARGET_NEED_POOL_LABELS
15
Optimize inline dup_const for MO_64.
23
tcg: Cleanups after disallowing 64-on-32
16
Update the cpu running flag in cpu_exec_step_atomic
24
tcg: Introduce constraint for zero register
17
Some tidy up of tcg vs other accelerators
25
tcg: Remove TCG_TARGET_HAS_{br,set}cond2 from riscv and loongarch64
26
tcg/i386: Use tcg_{high,unsigned}_cond in tcg_out_brcond2
27
linux-user: Move TARGET_SA_RESTORER out of generic/signal.h
28
linux-user: Fix alignment when unmapping excess reservation
29
target/sparc: Fix register selection for all F*TOx and FxTO* instructions
30
target/sparc: Fix gdbstub incorrectly handling registers f32-f62
31
target/sparc: fake UltraSPARC T1 PCR and PIC registers
18
32
19
----------------------------------------------------------------
33
----------------------------------------------------------------
20
Douglas Crosher (1):
34
Andreas Schwab (1):
21
tcg: update the cpu running flag in cpu_exec_step_atomic
35
linux-user: Move TARGET_SA_RESTORER out of generic/signal.h
22
36
23
Philippe Mathieu-Daudé (4):
37
Artyom Tarasenko (1):
24
accel/tcg: Make cpu_gen_init() static
38
target/sparc: fake UltraSPARC T1 PCR and PIC registers
25
accel/tcg: Restrict tb_gen_code() from other accelerators
26
accel/tcg: Declare missing cpu_loop_exit*() stubs
27
accel/tcg: Restrict cpu_io_recompile() from other accelerators
28
39
29
Richard Henderson (4):
40
Fabiano Rosas (1):
30
qemu/compiler: Split out qemu_build_not_reached_always
41
elfload: Fix alignment when unmapping excess reservation
31
tcg: Optimize inline dup_const for MO_64
32
tcg: Increase the static number of temporaries
33
accel/tcg: Move tb_flush_jmp_cache() to cputlb.c
34
42
35
Roman Bolshakov (1):
43
Mikael Szreder (2):
36
tcg: Toggle page execution for Apple Silicon
44
target/sparc: Fix register selection for all F*TOx and FxTO* instructions
45
target/sparc: Fix gdbstub incorrectly handling registers f32-f62
37
46
38
accel/tcg/internal.h | 20 ++++++++++++++++++++
47
Richard Henderson (22):
39
include/exec/exec-all.h | 11 -----------
48
tcg: Remove last traces of TCG_TARGET_NEED_POOL_LABELS
40
include/qemu/compiler.h | 5 +++--
49
tcg: Remove TCG_OVERSIZED_GUEST
41
include/qemu/osdep.h | 28 ++++++++++++++++++++++++++++
50
tcg: Drop support for two address registers in gen_ldst
42
include/tcg/tcg.h | 5 +++--
51
tcg: Merge INDEX_op_qemu_*_{a32,a64}_*
43
accel/stubs/tcg-stub.c | 10 ++++++++++
52
tcg/arm: Drop addrhi from prepare_host_addr
44
accel/tcg/cpu-exec.c | 7 +++++++
53
tcg/i386: Drop addrhi from prepare_host_addr
45
accel/tcg/cputlb.c | 19 +++++++++++++++++++
54
tcg/mips: Drop addrhi from prepare_host_addr
46
accel/tcg/translate-all.c | 23 +++++------------------
55
tcg/ppc: Drop addrhi from prepare_host_addr
47
tcg/tcg.c | 7 ++++---
56
tcg: Replace addr{lo,hi}_reg with addr_reg in TCGLabelQemuLdst
48
10 files changed, 99 insertions(+), 36 deletions(-)
57
plugins: Fix qemu_plugin_read_memory_vaddr parameters
49
create mode 100644 accel/tcg/internal.h
58
accel/tcg: Fix tlb_set_page_with_attrs, tlb_set_page
59
target/loongarch: Use VADDR_PRIx for logging pc_next
60
include/exec: Change vaddr to uintptr_t
61
include/exec: Use uintptr_t in CPUTLBEntry
62
tcg: Introduce the 'z' constraint for a hardware zero register
63
tcg/aarch64: Use 'z' constraint
64
tcg/loongarch64: Use 'z' constraint
65
tcg/mips: Use 'z' constraint
66
tcg/riscv: Use 'z' constraint
67
tcg/sparc64: Use 'z' constraint
68
tcg/i386: Use tcg_{high,unsigned}_cond in tcg_out_brcond2
69
tcg: Remove TCG_TARGET_HAS_{br,set}cond2 from riscv and loongarch64
50
70
71
include/exec/tlb-common.h | 10 +-
72
include/exec/vaddr.h | 16 +-
73
include/qemu/atomic.h | 18 +-
74
include/tcg/oversized-guest.h | 23 ---
75
include/tcg/tcg-opc.h | 28 +--
76
include/tcg/tcg.h | 3 +-
77
linux-user/aarch64/target_signal.h | 2 +
78
linux-user/arm/target_signal.h | 2 +
79
linux-user/generic/signal.h | 1 -
80
linux-user/i386/target_signal.h | 2 +
81
linux-user/m68k/target_signal.h | 1 +
82
linux-user/microblaze/target_signal.h | 2 +
83
linux-user/ppc/target_signal.h | 2 +
84
linux-user/s390x/target_signal.h | 2 +
85
linux-user/sh4/target_signal.h | 2 +
86
linux-user/x86_64/target_signal.h | 2 +
87
linux-user/xtensa/target_signal.h | 2 +
88
tcg/aarch64/tcg-target-con-set.h | 12 +-
89
tcg/aarch64/tcg-target.h | 2 +
90
tcg/loongarch64/tcg-target-con-set.h | 15 +-
91
tcg/loongarch64/tcg-target-con-str.h | 1 -
92
tcg/loongarch64/tcg-target-has.h | 2 -
93
tcg/loongarch64/tcg-target.h | 2 +
94
tcg/mips/tcg-target-con-set.h | 26 +--
95
tcg/mips/tcg-target-con-str.h | 1 -
96
tcg/mips/tcg-target.h | 2 +
97
tcg/riscv/tcg-target-con-set.h | 10 +-
98
tcg/riscv/tcg-target-con-str.h | 1 -
99
tcg/riscv/tcg-target-has.h | 2 -
100
tcg/riscv/tcg-target.h | 2 +
101
tcg/sparc64/tcg-target-con-set.h | 12 +-
102
tcg/sparc64/tcg-target-con-str.h | 1 -
103
tcg/sparc64/tcg-target.h | 3 +-
104
tcg/tci/tcg-target.h | 1 -
105
accel/tcg/cputlb.c | 32 +---
106
accel/tcg/tcg-all.c | 9 +-
107
linux-user/elfload.c | 4 +-
108
plugins/api.c | 2 +-
109
target/arm/ptw.c | 34 ----
110
target/loongarch/tcg/translate.c | 2 +-
111
target/riscv/cpu_helper.c | 13 +-
112
target/sparc/gdbstub.c | 18 +-
113
target/sparc/translate.c | 19 +++
114
tcg/optimize.c | 21 +--
115
tcg/tcg-op-ldst.c | 103 +++--------
116
tcg/tcg.c | 97 +++++------
117
tcg/tci.c | 119 +++----------
118
docs/devel/multi-thread-tcg.rst | 1 -
119
docs/devel/tcg-ops.rst | 4 +-
120
target/loongarch/tcg/insn_trans/trans_atomic.c.inc | 2 +-
121
target/sparc/insns.decode | 19 ++-
122
tcg/aarch64/tcg-target.c.inc | 86 ++++------
123
tcg/arm/tcg-target.c.inc | 114 ++++---------
124
tcg/i386/tcg-target.c.inc | 190 +++++----------------
125
tcg/loongarch64/tcg-target.c.inc | 72 +++-----
126
tcg/mips/tcg-target.c.inc | 169 ++++++------------
127
tcg/ppc/tcg-target.c.inc | 164 +++++-------------
128
tcg/riscv/tcg-target.c.inc | 56 +++---
129
tcg/s390x/tcg-target.c.inc | 40 ++---
130
tcg/sparc64/tcg-target.c.inc | 45 ++---
131
tcg/tci/tcg-target.c.inc | 60 ++-----
132
61 files changed, 548 insertions(+), 1160 deletions(-)
133
delete mode 100644 include/tcg/oversized-guest.h
diff view generated by jsdifflib
[PULL 01/10] tcg: update the cpu running flag in cpu_exec_step_atomic
Deleted patch
1
From: Douglas Crosher <dtc-ubuntu@scieneer.com>
2
1
3
The cpu_exec_step_atomic() function is called with the cpu->running
4
clear and proceeds to run target code without setting this flag. If
5
this target code generates an exception then handle_cpu_signal() will
6
unnecessarily abort. For example if atomic code generates a memory
7
protection fault.
8
9
This patch at least sets and clears this running flag, and adds some
10
assertions to help detect other cases.
11
12
Signed-off-by: Douglas Crosher <dtc-ubuntu@scieneer.com>
13
Message-Id: <a272c656-f7c5-019d-1cc0-499b8f80f2fc@scieneer.com>
14
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
15
---
16
accel/tcg/cpu-exec.c | 4 ++++
17
1 file changed, 4 insertions(+)
18
19
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
20
index XXXXXXX..XXXXXXX 100644
21
--- a/accel/tcg/cpu-exec.c
22
+++ b/accel/tcg/cpu-exec.c
23
@@ -XXX,XX +XXX,XX @@ void cpu_exec_step_atomic(CPUState *cpu)
24
25
if (sigsetjmp(cpu->jmp_env, 0) == 0) {
26
start_exclusive();
27
+ g_assert(cpu == current_cpu);
28
+ g_assert(!cpu->running);
29
+ cpu->running = true;
30
31
tb = tb_lookup__cpu_state(cpu, &pc, &cs_base, &flags, cf_mask);
32
if (tb == NULL) {
33
@@ -XXX,XX +XXX,XX @@ void cpu_exec_step_atomic(CPUState *cpu)
34
*/
35
g_assert(cpu_in_exclusive_context(cpu));
36
parallel_cpus = true;
37
+ cpu->running = false;
38
end_exclusive();
39
}
40
41
--
42
2.25.1
43
44
diff view generated by jsdifflib
[PULL 02/10] qemu/compiler: Split out qemu_build_not_reached_always
Deleted patch
1
Provide a symbol that can always be used to signal an error,
2
regardless of optimization. Usage of this should be protected
3
by e.g. __builtin_constant_p, which guards for optimization.
4
1
5
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
---
8
include/qemu/compiler.h | 5 +++--
9
1 file changed, 3 insertions(+), 2 deletions(-)
10
11
diff --git a/include/qemu/compiler.h b/include/qemu/compiler.h
12
index XXXXXXX..XXXXXXX 100644
13
--- a/include/qemu/compiler.h
14
+++ b/include/qemu/compiler.h
15
@@ -XXX,XX +XXX,XX @@
16
* supports QEMU_ERROR, this will be reported at compile time; otherwise
17
* this will be reported at link time due to the missing symbol.
18
*/
19
-#if defined(__OPTIMIZE__) && !defined(__NO_INLINE__)
20
extern void QEMU_NORETURN QEMU_ERROR("code path is reachable")
21
- qemu_build_not_reached(void);
22
+ qemu_build_not_reached_always(void);
23
+#if defined(__OPTIMIZE__) && !defined(__NO_INLINE__)
24
+#define qemu_build_not_reached() qemu_build_not_reached_always()
25
#else
26
#define qemu_build_not_reached() g_assert_not_reached()
27
#endif
28
--
29
2.25.1
30
31
diff view generated by jsdifflib
[PULL 03/10] tcg: Optimize inline dup_const for MO_64
Deleted patch
1
Avoid the out-of-line function call for immediate MO_64.
2
In addition, diagnose all invalid constants at compile-time.
3
1
4
Reviewed-by: David Hildenbrand <david@redhat.com>
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
---
7
include/tcg/tcg.h | 3 ++-
8
1 file changed, 2 insertions(+), 1 deletion(-)
9
10
diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h
11
index XXXXXXX..XXXXXXX 100644
12
--- a/include/tcg/tcg.h
13
+++ b/include/tcg/tcg.h
14
@@ -XXX,XX +XXX,XX @@ uint64_t dup_const(unsigned vece, uint64_t c);
15
? ( (VECE) == MO_8 ? 0x0101010101010101ull * (uint8_t)(C) \
16
: (VECE) == MO_16 ? 0x0001000100010001ull * (uint16_t)(C) \
17
: (VECE) == MO_32 ? 0x0000000100000001ull * (uint32_t)(C) \
18
- : dup_const(VECE, C)) \
19
+ : (VECE) == MO_64 ? (uint64_t)(C) \
20
+ : (qemu_build_not_reached_always(), 0)) \
21
: dup_const(VECE, C))
22
23
24
--
25
2.25.1
26
27
diff view generated by jsdifflib
[PULL 04/10] tcg: Increase the static number of temporaries
Deleted patch
1
This isn't a total or permanent solution to the problem of running
2
out of temporaries, but it puts off the issue for a bit.
3
1
4
Make the assert in tcg_temp_alloc unconditional. If we do run out
5
of temps, this can fail much later as a weird SIGSEGV, due to the
6
buffer overrun of the temp array.
7
8
Remove the inlines from tcg_temp_alloc and tcg_global_alloc.
9
10
Buglink: https://bugs.launchpad.net/bugs/1912065
11
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
12
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
13
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
14
---
15
include/tcg/tcg.h | 2 +-
16
tcg/tcg.c | 6 +++---
17
2 files changed, 4 insertions(+), 4 deletions(-)
18
19
diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h
20
index XXXXXXX..XXXXXXX 100644
21
--- a/include/tcg/tcg.h
22
+++ b/include/tcg/tcg.h
23
@@ -XXX,XX +XXX,XX @@ typedef struct TCGPool {
24
25
#define TCG_POOL_CHUNK_SIZE 32768
26
27
-#define TCG_MAX_TEMPS 512
28
+#define TCG_MAX_TEMPS 1024
29
#define TCG_MAX_INSNS 512
30
31
/* when the size of the arguments of a called function is smaller than
32
diff --git a/tcg/tcg.c b/tcg/tcg.c
33
index XXXXXXX..XXXXXXX 100644
34
--- a/tcg/tcg.c
35
+++ b/tcg/tcg.c
36
@@ -XXX,XX +XXX,XX @@ void tcg_func_start(TCGContext *s)
37
QSIMPLEQ_INIT(&s->labels);
38
}
39
40
-static inline TCGTemp *tcg_temp_alloc(TCGContext *s)
41
+static TCGTemp *tcg_temp_alloc(TCGContext *s)
42
{
43
int n = s->nb_temps++;
44
- tcg_debug_assert(n < TCG_MAX_TEMPS);
45
+ g_assert(n < TCG_MAX_TEMPS);
46
return memset(&s->temps[n], 0, sizeof(TCGTemp));
47
}
48
49
-static inline TCGTemp *tcg_global_alloc(TCGContext *s)
50
+static TCGTemp *tcg_global_alloc(TCGContext *s)
51
{
52
TCGTemp *ts;
53
54
--
55
2.25.1
56
57
diff view generated by jsdifflib
[PULL 05/10] accel/tcg: Make cpu_gen_init() static
Deleted patch
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
1
3
cpu_gen_init() is TCG specific, only used in tcg/translate-all.c.
4
No need to export it to other accelerators, declare it statically.
5
6
Reviewed-by: Claudio Fontana <cfontana@suse.de>
7
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Message-Id: <20210117164813.4101761-2-f4bug@amsat.org>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
---
11
include/exec/exec-all.h | 2 --
12
accel/tcg/translate-all.c | 2 +-
13
2 files changed, 1 insertion(+), 3 deletions(-)
14
15
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
16
index XXXXXXX..XXXXXXX 100644
17
--- a/include/exec/exec-all.h
18
+++ b/include/exec/exec-all.h
19
@@ -XXX,XX +XXX,XX @@ void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int max_insns);
20
void restore_state_to_opc(CPUArchState *env, TranslationBlock *tb,
21
target_ulong *data);
22
23
-void cpu_gen_init(void);
24
-
25
/**
26
* cpu_restore_state:
27
* @cpu: the vCPU state is to be restore to
28
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
29
index XXXXXXX..XXXXXXX 100644
30
--- a/accel/tcg/translate-all.c
31
+++ b/accel/tcg/translate-all.c
32
@@ -XXX,XX +XXX,XX @@ static void page_table_config_init(void)
33
assert(v_l2_levels >= 0);
34
}
35
36
-void cpu_gen_init(void)
37
+static void cpu_gen_init(void)
38
{
39
tcg_context_init(&tcg_init_ctx);
40
}
41
--
42
2.25.1
43
44
diff view generated by jsdifflib
[PULL 06/10] accel/tcg: Move tb_flush_jmp_cache() to cputlb.c
Deleted patch
1
Move and make the function static, as the only users
2
are here in cputlb.c.
3
1
4
Suggested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
---
7
include/exec/exec-all.h | 3 ---
8
accel/tcg/cputlb.c | 18 ++++++++++++++++++
9
accel/tcg/translate-all.c | 17 -----------------
10
3 files changed, 18 insertions(+), 20 deletions(-)
11
12
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
13
index XXXXXXX..XXXXXXX 100644
14
--- a/include/exec/exec-all.h
15
+++ b/include/exec/exec-all.h
16
@@ -XXX,XX +XXX,XX @@ tb_page_addr_t get_page_addr_code_hostp(CPUArchState *env, target_ulong addr,
17
void tlb_reset_dirty(CPUState *cpu, ram_addr_t start1, ram_addr_t length);
18
void tlb_set_dirty(CPUState *cpu, target_ulong vaddr);
19
20
-/* exec.c */
21
-void tb_flush_jmp_cache(CPUState *cpu, target_ulong addr);
22
-
23
MemoryRegionSection *
24
address_space_translate_for_iotlb(CPUState *cpu, int asidx, hwaddr addr,
25
hwaddr *xlat, hwaddr *plen,
26
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
27
index XXXXXXX..XXXXXXX 100644
28
--- a/accel/tcg/cputlb.c
29
+++ b/accel/tcg/cputlb.c
30
@@ -XXX,XX +XXX,XX @@
31
#include "exec/address-spaces.h"
32
#include "exec/cpu_ldst.h"
33
#include "exec/cputlb.h"
34
+#include "exec/tb-hash.h"
35
#include "exec/memory-internal.h"
36
#include "exec/ram_addr.h"
37
#include "tcg/tcg.h"
38
@@ -XXX,XX +XXX,XX @@ static void tlb_window_reset(CPUTLBDesc *desc, int64_t ns,
39
desc->window_max_entries = max_entries;
40
}
41
42
+static void tb_jmp_cache_clear_page(CPUState *cpu, target_ulong page_addr)
43
+{
44
+ unsigned int i, i0 = tb_jmp_cache_hash_page(page_addr);
45
+
46
+ for (i = 0; i < TB_JMP_PAGE_SIZE; i++) {
47
+ qatomic_set(&cpu->tb_jmp_cache[i0 + i], NULL);
48
+ }
49
+}
50
+
51
+static void tb_flush_jmp_cache(CPUState *cpu, target_ulong addr)
52
+{
53
+ /* Discard jump cache entries for any tb which might potentially
54
+ overlap the flushed page. */
55
+ tb_jmp_cache_clear_page(cpu, addr - TARGET_PAGE_SIZE);
56
+ tb_jmp_cache_clear_page(cpu, addr);
57
+}
58
+
59
/**
60
* tlb_mmu_resize_locked() - perform TLB resize bookkeeping; resize if necessary
61
* @desc: The CPUTLBDesc portion of the TLB
62
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
63
index XXXXXXX..XXXXXXX 100644
64
--- a/accel/tcg/translate-all.c
65
+++ b/accel/tcg/translate-all.c
66
@@ -XXX,XX +XXX,XX @@ void cpu_io_recompile(CPUState *cpu, uintptr_t retaddr)
67
cpu_loop_exit_noexc(cpu);
68
}
69
70
-static void tb_jmp_cache_clear_page(CPUState *cpu, target_ulong page_addr)
71
-{
72
- unsigned int i, i0 = tb_jmp_cache_hash_page(page_addr);
73
-
74
- for (i = 0; i < TB_JMP_PAGE_SIZE; i++) {
75
- qatomic_set(&cpu->tb_jmp_cache[i0 + i], NULL);
76
- }
77
-}
78
-
79
-void tb_flush_jmp_cache(CPUState *cpu, target_ulong addr)
80
-{
81
- /* Discard jump cache entries for any tb which might potentially
82
- overlap the flushed page. */
83
- tb_jmp_cache_clear_page(cpu, addr - TARGET_PAGE_SIZE);
84
- tb_jmp_cache_clear_page(cpu, addr);
85
-}
86
-
87
static void print_qht_statistics(struct qht_stats hst)
88
{
89
uint32_t hgram_opts;
90
--
91
2.25.1
92
93
diff view generated by jsdifflib
[PULL 07/10] accel/tcg: Restrict tb_gen_code() from other accelerators
Deleted patch
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
1
3
tb_gen_code() is only called within TCG accelerator, declare it locally.
4
5
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
6
Message-Id: <20210117164813.4101761-4-f4bug@amsat.org>
7
[rth: Adjust vs changed tb_flush_jmp_cache patch.]
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
---
10
accel/tcg/internal.h | 18 ++++++++++++++++++
11
include/exec/exec-all.h | 5 -----
12
accel/tcg/cpu-exec.c | 1 +
13
accel/tcg/translate-all.c | 1 +
14
4 files changed, 20 insertions(+), 5 deletions(-)
15
create mode 100644 accel/tcg/internal.h
16
17
diff --git a/accel/tcg/internal.h b/accel/tcg/internal.h
18
new file mode 100644
19
index XXXXXXX..XXXXXXX
20
--- /dev/null
21
+++ b/accel/tcg/internal.h
22
@@ -XXX,XX +XXX,XX @@
23
+/*
24
+ * Internal execution defines for qemu
25
+ *
26
+ * Copyright (c) 2003 Fabrice Bellard
27
+ *
28
+ * SPDX-License-Identifier: LGPL-2.1-or-later
29
+ */
30
+
31
+#ifndef ACCEL_TCG_INTERNAL_H
32
+#define ACCEL_TCG_INTERNAL_H
33
+
34
+#include "exec/exec-all.h"
35
+
36
+TranslationBlock *tb_gen_code(CPUState *cpu, target_ulong pc,
37
+ target_ulong cs_base, uint32_t flags,
38
+ int cflags);
39
+
40
+#endif /* ACCEL_TCG_INTERNAL_H */
41
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
42
index XXXXXXX..XXXXXXX 100644
43
--- a/include/exec/exec-all.h
44
+++ b/include/exec/exec-all.h
45
@@ -XXX,XX +XXX,XX @@ bool cpu_restore_state(CPUState *cpu, uintptr_t searched_pc, bool will_exit);
46
47
void QEMU_NORETURN cpu_loop_exit_noexc(CPUState *cpu);
48
void QEMU_NORETURN cpu_io_recompile(CPUState *cpu, uintptr_t retaddr);
49
-TranslationBlock *tb_gen_code(CPUState *cpu,
50
- target_ulong pc, target_ulong cs_base,
51
- uint32_t flags,
52
- int cflags);
53
-
54
void QEMU_NORETURN cpu_loop_exit(CPUState *cpu);
55
void QEMU_NORETURN cpu_loop_exit_restore(CPUState *cpu, uintptr_t pc);
56
void QEMU_NORETURN cpu_loop_exit_atomic(CPUState *cpu, uintptr_t pc);
57
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
58
index XXXXXXX..XXXXXXX 100644
59
--- a/accel/tcg/cpu-exec.c
60
+++ b/accel/tcg/cpu-exec.c
61
@@ -XXX,XX +XXX,XX @@
62
#include "exec/cpu-all.h"
63
#include "sysemu/cpu-timers.h"
64
#include "sysemu/replay.h"
65
+#include "internal.h"
66
67
/* -icount align implementation. */
68
69
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
70
index XXXXXXX..XXXXXXX 100644
71
--- a/accel/tcg/translate-all.c
72
+++ b/accel/tcg/translate-all.c
73
@@ -XXX,XX +XXX,XX @@
74
#include "sysemu/cpu-timers.h"
75
#include "sysemu/tcg.h"
76
#include "qapi/error.h"
77
+#include "internal.h"
78
79
/* #define DEBUG_TB_INVALIDATE */
80
/* #define DEBUG_TB_FLUSH */
81
--
82
2.25.1
83
84
diff view generated by jsdifflib
[PULL 08/10] accel/tcg: Declare missing cpu_loop_exit*() stubs
Deleted patch
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
1
3
cpu_loop_exit*() functions are declared in accel/tcg/cpu-exec-common.c,
4
and are not available when TCG accelerator is not built. Add stubs so
5
linking without TCG succeed.
6
7
Problematic files:
8
9
- hw/semihosting/console.c in qemu_semihosting_console_inc()
10
- hw/ppc/spapr_hcall.c in h_confer()
11
- hw/s390x/ipl.c in s390_ipl_reset_request()
12
- hw/misc/mips_itu.c
13
14
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
15
Message-Id: <20210117164813.4101761-5-f4bug@amsat.org>
16
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
17
---
18
accel/stubs/tcg-stub.c | 10 ++++++++++
19
1 file changed, 10 insertions(+)
20
21
diff --git a/accel/stubs/tcg-stub.c b/accel/stubs/tcg-stub.c
22
index XXXXXXX..XXXXXXX 100644
23
--- a/accel/stubs/tcg-stub.c
24
+++ b/accel/stubs/tcg-stub.c
25
@@ -XXX,XX +XXX,XX @@ void *probe_access(CPUArchState *env, target_ulong addr, int size,
26
/* Handled by hardware accelerator. */
27
g_assert_not_reached();
28
}
29
+
30
+void QEMU_NORETURN cpu_loop_exit(CPUState *cpu)
31
+{
32
+ g_assert_not_reached();
33
+}
34
+
35
+void QEMU_NORETURN cpu_loop_exit_restore(CPUState *cpu, uintptr_t pc)
36
+{
37
+ g_assert_not_reached();
38
+}
39
--
40
2.25.1
41
42
diff view generated by jsdifflib
[PULL 09/10] accel/tcg: Restrict cpu_io_recompile() from other accelerators
Deleted patch
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
1
3
As cpu_io_recompile() is only called within TCG accelerator
4
in cputlb.c, declare it locally.
5
6
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
7
Message-Id: <20210117164813.4101761-6-f4bug@amsat.org>
8
[rth: Adjust vs changed tb_flush_jmp_cache patch.]
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
---
11
accel/tcg/internal.h | 2 ++
12
include/exec/exec-all.h | 1 -
13
accel/tcg/cputlb.c | 1 +
14
3 files changed, 3 insertions(+), 1 deletion(-)
15
16
diff --git a/accel/tcg/internal.h b/accel/tcg/internal.h
17
index XXXXXXX..XXXXXXX 100644
18
--- a/accel/tcg/internal.h
19
+++ b/accel/tcg/internal.h
20
@@ -XXX,XX +XXX,XX @@ TranslationBlock *tb_gen_code(CPUState *cpu, target_ulong pc,
21
target_ulong cs_base, uint32_t flags,
22
int cflags);
23
24
+void QEMU_NORETURN cpu_io_recompile(CPUState *cpu, uintptr_t retaddr);
25
+
26
#endif /* ACCEL_TCG_INTERNAL_H */
27
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
28
index XXXXXXX..XXXXXXX 100644
29
--- a/include/exec/exec-all.h
30
+++ b/include/exec/exec-all.h
31
@@ -XXX,XX +XXX,XX @@ void restore_state_to_opc(CPUArchState *env, TranslationBlock *tb,
32
bool cpu_restore_state(CPUState *cpu, uintptr_t searched_pc, bool will_exit);
33
34
void QEMU_NORETURN cpu_loop_exit_noexc(CPUState *cpu);
35
-void QEMU_NORETURN cpu_io_recompile(CPUState *cpu, uintptr_t retaddr);
36
void QEMU_NORETURN cpu_loop_exit(CPUState *cpu);
37
void QEMU_NORETURN cpu_loop_exit_restore(CPUState *cpu, uintptr_t pc);
38
void QEMU_NORETURN cpu_loop_exit_atomic(CPUState *cpu, uintptr_t pc);
39
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
40
index XXXXXXX..XXXXXXX 100644
41
--- a/accel/tcg/cputlb.c
42
+++ b/accel/tcg/cputlb.c
43
@@ -XXX,XX +XXX,XX @@
44
#include "exec/translate-all.h"
45
#include "trace/trace-root.h"
46
#include "trace/mem.h"
47
+#include "internal.h"
48
#ifdef CONFIG_PLUGIN
49
#include "qemu/plugin-memory.h"
50
#endif
51
--
52
2.25.1
53
54
diff view generated by jsdifflib
[PULL 10/10] tcg: Toggle page execution for Apple Silicon
Deleted patch
1
From: Roman Bolshakov <r.bolshakov@yadro.com>
2
1
3
Pages can't be both write and executable at the same time on Apple
4
Silicon. macOS provides public API to switch write protection [1] for
5
JIT applications, like TCG.
6
7
1. https://developer.apple.com/documentation/apple_silicon/porting_just-in-time_compilers_to_apple_silicon
8
9
Tested-by: Alexander Graf <agraf@csgraf.de>
10
Signed-off-by: Roman Bolshakov <r.bolshakov@yadro.com>
11
Message-Id: <20210113032806.18220-1-r.bolshakov@yadro.com>
12
[rth: Inline the qemu_thread_jit_* functions;
13
drop the MAP_JIT change for a follow-on patch.]
14
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
15
---
16
include/qemu/osdep.h | 28 ++++++++++++++++++++++++++++
17
accel/tcg/cpu-exec.c | 2 ++
18
accel/tcg/translate-all.c | 3 +++
19
tcg/tcg.c | 1 +
20
4 files changed, 34 insertions(+)
21
22
diff --git a/include/qemu/osdep.h b/include/qemu/osdep.h
23
index XXXXXXX..XXXXXXX 100644
24
--- a/include/qemu/osdep.h
25
+++ b/include/qemu/osdep.h
26
@@ -XXX,XX +XXX,XX @@ extern int daemon(int, int);
27
#include "sysemu/os-posix.h"
28
#endif
29
30
+#ifdef __APPLE__
31
+#include <AvailabilityMacros.h>
32
+#endif
33
+
34
#include "glib-compat.h"
35
#include "qemu/typedefs.h"
36
37
@@ -XXX,XX +XXX,XX @@ char *qemu_get_host_name(Error **errp);
38
*/
39
size_t qemu_get_host_physmem(void);
40
41
+/*
42
+ * Toggle write/execute on the pages marked MAP_JIT
43
+ * for the current thread.
44
+ */
45
+#if defined(MAC_OS_VERSION_11_0) && \
46
+ MAC_OS_X_VERSION_MAX_ALLOWED >= MAC_OS_VERSION_11_0
47
+static inline void qemu_thread_jit_execute(void)
48
+{
49
+ if (__builtin_available(macOS 11.0, *)) {
50
+ pthread_jit_write_protect_np(true);
51
+ }
52
+}
53
+
54
+static inline void qemu_thread_jit_write(void)
55
+{
56
+ if (__builtin_available(macOS 11.0, *)) {
57
+ pthread_jit_write_protect_np(false);
58
+ }
59
+}
60
+#else
61
+static inline void qemu_thread_jit_write(void) {}
62
+static inline void qemu_thread_jit_execute(void) {}
63
+#endif
64
+
65
#endif
66
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
67
index XXXXXXX..XXXXXXX 100644
68
--- a/accel/tcg/cpu-exec.c
69
+++ b/accel/tcg/cpu-exec.c
70
@@ -XXX,XX +XXX,XX @@ cpu_tb_exec(CPUState *cpu, TranslationBlock *itb, int *tb_exit)
71
}
72
#endif /* DEBUG_DISAS */
73
74
+ qemu_thread_jit_execute();
75
ret = tcg_qemu_tb_exec(env, tb_ptr);
76
cpu->can_do_io = 1;
77
/*
78
@@ -XXX,XX +XXX,XX @@ static inline void tb_add_jump(TranslationBlock *tb, int n,
79
{
80
uintptr_t old;
81
82
+ qemu_thread_jit_write();
83
assert(n < ARRAY_SIZE(tb->jmp_list_next));
84
qemu_spin_lock(&tb_next->jmp_lock);
85
86
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
87
index XXXXXXX..XXXXXXX 100644
88
--- a/accel/tcg/translate-all.c
89
+++ b/accel/tcg/translate-all.c
90
@@ -XXX,XX +XXX,XX @@ static void do_tb_phys_invalidate(TranslationBlock *tb, bool rm_from_page_list)
91
92
static void tb_phys_invalidate__locked(TranslationBlock *tb)
93
{
94
+ qemu_thread_jit_write();
95
do_tb_phys_invalidate(tb, true);
96
+ qemu_thread_jit_execute();
97
}
98
99
/* invalidate one TB
100
@@ -XXX,XX +XXX,XX @@ TranslationBlock *tb_gen_code(CPUState *cpu,
101
#endif
102
103
assert_memory_lock();
104
+ qemu_thread_jit_write();
105
106
phys_pc = get_page_addr_code(env, pc);
107
108
diff --git a/tcg/tcg.c b/tcg/tcg.c
109
index XXXXXXX..XXXXXXX 100644
110
--- a/tcg/tcg.c
111
+++ b/tcg/tcg.c
112
@@ -XXX,XX +XXX,XX @@ void tcg_prologue_init(TCGContext *s)
113
s->pool_labels = NULL;
114
#endif
115
116
+ qemu_thread_jit_write();
117
/* Generate the prologue. */
118
tcg_target_qemu_prologue(s);
119
120
--
121
2.25.1
122
123
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

© 2016 - 2025 Red Hat, Inc.