[PULL 00/10] tcg patch queue
[PULL 00/24] tcg patch queue
1
The following changes since commit 0e32462630687a18039464511bd0447ada5709c3:
1
With a couple of linux-user and target/sparc patches thrown in for good measure.
2
2
3
Merge remote-tracking branch 'remotes/vivier2/tags/linux-user-for-6.0-pull-request' into staging (2021-01-22 10:35:55 +0000)
3
r~
4
5
6
The following changes since commit 495de0fd82d8bb2d7035f82d9869cfeb48de2f9e:
7
8
Merge tag 'pull-trivial-patches' of https://gitlab.com/mjt0k/qemu into staging (2025-02-14 08:19:05 -0500)
4
9
5
are available in the Git repository at:
10
are available in the Git repository at:
6
11
7
https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20210123
12
https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20250215
8
13
9
for you to fetch changes up to 2e34067e9959f149a904cf1255985d3b68b52566:
14
for you to fetch changes up to 2132751069134114814c7e1609e9cf644f077aad:
10
15
11
tcg: Toggle page execution for Apple Silicon (2021-01-22 12:48:01 -1000)
16
target/sparc: fake UltraSPARC T1 PCR and PIC registers (2025-02-15 12:04:13 -0800)
12
17
13
----------------------------------------------------------------
18
----------------------------------------------------------------
14
Fix tcg constant segv.
19
tcg: Remove last traces of TCG_TARGET_NEED_POOL_LABELS
15
Optimize inline dup_const for MO_64.
20
tcg: Cleanups after disallowing 64-on-32
16
Update the cpu running flag in cpu_exec_step_atomic
21
tcg: Introduce constraint for zero register
17
Some tidy up of tcg vs other accelerators
22
linux-user: Move TARGET_SA_RESTORER out of generic/signal.h
23
linux-user: Fix alignment when unmapping excess reservation
24
target/sparc: Fix register selection for all F*TOx and FxTO* instructions
25
target/sparc: Fix gdbstub incorrectly handling registers f32-f62
26
target/sparc: fake UltraSPARC T1 PCR and PIC registers
18
27
19
----------------------------------------------------------------
28
----------------------------------------------------------------
20
Douglas Crosher (1):
29
Andreas Schwab (1):
21
tcg: update the cpu running flag in cpu_exec_step_atomic
30
linux-user: Move TARGET_SA_RESTORER out of generic/signal.h
22
31
23
Philippe Mathieu-Daudé (4):
32
Artyom Tarasenko (1):
24
accel/tcg: Make cpu_gen_init() static
33
target/sparc: fake UltraSPARC T1 PCR and PIC registers
25
accel/tcg: Restrict tb_gen_code() from other accelerators
26
accel/tcg: Declare missing cpu_loop_exit*() stubs
27
accel/tcg: Restrict cpu_io_recompile() from other accelerators
28
34
29
Richard Henderson (4):
35
Fabiano Rosas (1):
30
qemu/compiler: Split out qemu_build_not_reached_always
36
elfload: Fix alignment when unmapping excess reservation
31
tcg: Optimize inline dup_const for MO_64
32
tcg: Increase the static number of temporaries
33
accel/tcg: Move tb_flush_jmp_cache() to cputlb.c
34
37
35
Roman Bolshakov (1):
38
Mikael Szreder (2):
36
tcg: Toggle page execution for Apple Silicon
39
target/sparc: Fix register selection for all F*TOx and FxTO* instructions
40
target/sparc: Fix gdbstub incorrectly handling registers f32-f62
37
41
38
accel/tcg/internal.h | 20 ++++++++++++++++++++
42
Richard Henderson (19):
39
include/exec/exec-all.h | 11 -----------
43
tcg: Remove last traces of TCG_TARGET_NEED_POOL_LABELS
40
include/qemu/compiler.h | 5 +++--
44
tcg: Remove TCG_OVERSIZED_GUEST
41
include/qemu/osdep.h | 28 ++++++++++++++++++++++++++++
45
tcg: Drop support for two address registers in gen_ldst
42
include/tcg/tcg.h | 5 +++--
46
tcg: Merge INDEX_op_qemu_*_{a32,a64}_*
43
accel/stubs/tcg-stub.c | 10 ++++++++++
47
tcg/arm: Drop addrhi from prepare_host_addr
44
accel/tcg/cpu-exec.c | 7 +++++++
48
tcg/i386: Drop addrhi from prepare_host_addr
45
accel/tcg/cputlb.c | 19 +++++++++++++++++++
49
tcg/mips: Drop addrhi from prepare_host_addr
46
accel/tcg/translate-all.c | 23 +++++------------------
50
tcg/ppc: Drop addrhi from prepare_host_addr
47
tcg/tcg.c | 7 ++++---
51
tcg: Replace addr{lo,hi}_reg with addr_reg in TCGLabelQemuLdst
48
10 files changed, 99 insertions(+), 36 deletions(-)
52
plugins: Fix qemu_plugin_read_memory_vaddr parameters
49
create mode 100644 accel/tcg/internal.h
53
accel/tcg: Fix tlb_set_page_with_attrs, tlb_set_page
54
include/exec: Change vaddr to uintptr_t
55
include/exec: Use uintptr_t in CPUTLBEntry
56
tcg: Introduce the 'z' constraint for a hardware zero register
57
tcg/aarch64: Use 'z' constraint
58
tcg/loongarch64: Use 'z' constraint
59
tcg/mips: Use 'z' constraint
60
tcg/riscv: Use 'z' constraint
61
tcg/sparc64: Use 'z' constraint
50
62
63
include/exec/tlb-common.h | 10 +-
64
include/exec/vaddr.h | 16 ++--
65
include/qemu/atomic.h | 18 +---
66
include/tcg/oversized-guest.h | 23 -----
67
include/tcg/tcg-opc.h | 28 ++----
68
include/tcg/tcg.h | 3 +-
69
linux-user/aarch64/target_signal.h | 2 +
70
linux-user/arm/target_signal.h | 2 +
71
linux-user/generic/signal.h | 1 -
72
linux-user/i386/target_signal.h | 2 +
73
linux-user/m68k/target_signal.h | 1 +
74
linux-user/microblaze/target_signal.h | 2 +
75
linux-user/ppc/target_signal.h | 2 +
76
linux-user/s390x/target_signal.h | 2 +
77
linux-user/sh4/target_signal.h | 2 +
78
linux-user/x86_64/target_signal.h | 2 +
79
linux-user/xtensa/target_signal.h | 2 +
80
tcg/aarch64/tcg-target-con-set.h | 12 +--
81
tcg/aarch64/tcg-target.h | 2 +
82
tcg/loongarch64/tcg-target-con-set.h | 15 ++-
83
tcg/loongarch64/tcg-target-con-str.h | 1 -
84
tcg/loongarch64/tcg-target.h | 2 +
85
tcg/mips/tcg-target-con-set.h | 26 +++---
86
tcg/mips/tcg-target-con-str.h | 1 -
87
tcg/mips/tcg-target.h | 2 +
88
tcg/riscv/tcg-target-con-set.h | 10 +-
89
tcg/riscv/tcg-target-con-str.h | 1 -
90
tcg/riscv/tcg-target.h | 2 +
91
tcg/sparc64/tcg-target-con-set.h | 12 +--
92
tcg/sparc64/tcg-target-con-str.h | 1 -
93
tcg/sparc64/tcg-target.h | 3 +-
94
tcg/tci/tcg-target.h | 1 -
95
accel/tcg/cputlb.c | 32 ++-----
96
accel/tcg/tcg-all.c | 9 +-
97
linux-user/elfload.c | 4 +-
98
plugins/api.c | 2 +-
99
target/arm/ptw.c | 34 -------
100
target/riscv/cpu_helper.c | 13 +--
101
target/sparc/gdbstub.c | 18 +++-
102
target/sparc/translate.c | 19 ++++
103
tcg/optimize.c | 21 ++---
104
tcg/tcg-op-ldst.c | 103 +++++----------------
105
tcg/tcg.c | 97 +++++++++----------
106
tcg/tci.c | 119 +++++-------------------
107
docs/devel/multi-thread-tcg.rst | 1 -
108
docs/devel/tcg-ops.rst | 4 +-
109
target/sparc/insns.decode | 19 ++--
110
tcg/aarch64/tcg-target.c.inc | 86 +++++++----------
111
tcg/arm/tcg-target.c.inc | 104 ++++++---------------
112
tcg/i386/tcg-target.c.inc | 125 +++++++------------------
113
tcg/loongarch64/tcg-target.c.inc | 72 ++++++---------
114
tcg/mips/tcg-target.c.inc | 169 +++++++++++-----------------------
115
tcg/ppc/tcg-target.c.inc | 164 ++++++++-------------------------
116
tcg/riscv/tcg-target.c.inc | 56 +++++------
117
tcg/s390x/tcg-target.c.inc | 40 +++-----
118
tcg/sparc64/tcg-target.c.inc | 45 ++++-----
119
tcg/tci/tcg-target.c.inc | 60 +++---------
120
57 files changed, 536 insertions(+), 1089 deletions(-)
121
delete mode 100644 include/tcg/oversized-guest.h
diff view generated by jsdifflib
New patch
[PULL 01/24] tcg: Remove last traces of TCG_TARGET_NEED_POOL_LABELS
1
These should have been removed with the rest. There are
2
a couple of hosts which can emit guest_base into the
3
constant pool: aarch64, mips64, ppc64, riscv64.
1
4
5
Fixes: a417ef835058 ("tcg: Remove TCG_TARGET_NEED_LDST_LABELS and TCG_TARGET_NEED_POOL_LABELS")
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
---
8
tcg/tci/tcg-target.h | 1 -
9
tcg/tcg.c | 4 ----
10
2 files changed, 5 deletions(-)
11
12
diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h
13
index XXXXXXX..XXXXXXX 100644
14
--- a/tcg/tci/tcg-target.h
15
+++ b/tcg/tci/tcg-target.h
16
@@ -XXX,XX +XXX,XX @@ typedef enum {
17
} TCGReg;
18
19
#define HAVE_TCG_QEMU_TB_EXEC
20
-#define TCG_TARGET_NEED_POOL_LABELS
21
22
#endif /* TCG_TARGET_H */
23
diff --git a/tcg/tcg.c b/tcg/tcg.c
24
index XXXXXXX..XXXXXXX 100644
25
--- a/tcg/tcg.c
26
+++ b/tcg/tcg.c
27
@@ -XXX,XX +XXX,XX @@ void tcg_prologue_init(void)
28
tcg_qemu_tb_exec = (tcg_prologue_fn *)tcg_splitwx_to_rx(s->code_ptr);
29
#endif
30
31
-#ifdef TCG_TARGET_NEED_POOL_LABELS
32
s->pool_labels = NULL;
33
-#endif
34
35
qemu_thread_jit_write();
36
/* Generate the prologue. */
37
tcg_target_qemu_prologue(s);
38
39
-#ifdef TCG_TARGET_NEED_POOL_LABELS
40
/* Allow the prologue to put e.g. guest_base into a pool entry. */
41
{
42
int result = tcg_out_pool_finalize(s);
43
tcg_debug_assert(result == 0);
44
}
45
-#endif
46
47
prologue_size = tcg_current_code_size(s);
48
perf_report_prologue(s->code_gen_ptr, prologue_size);
49
--
50
2.43.0
diff view generated by jsdifflib
[PULL 09/10] accel/tcg: Restrict cpu_io_recompile() from other accelerators
[PULL 02/24] tcg: Remove TCG_OVERSIZED_GUEST
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
This is now prohibited in configuration.
2
2
3
As cpu_io_recompile() is only called within TCG accelerator
3
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
4
in cputlb.c, declare it locally.
5
6
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
7
Message-Id: <20210117164813.4101761-6-f4bug@amsat.org>
8
[rth: Adjust vs changed tb_flush_jmp_cache patch.]
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
---
5
---
11
accel/tcg/internal.h | 2 ++
6
include/qemu/atomic.h | 18 +++--------------
12
include/exec/exec-all.h | 1 -
7
include/tcg/oversized-guest.h | 23 ----------------------
13
accel/tcg/cputlb.c | 1 +
8
accel/tcg/cputlb.c | 7 -------
14
3 files changed, 3 insertions(+), 1 deletion(-)
9
accel/tcg/tcg-all.c | 9 ++++-----
15
10
target/arm/ptw.c | 34 ---------------------------------
16
diff --git a/accel/tcg/internal.h b/accel/tcg/internal.h
11
target/riscv/cpu_helper.c | 13 +------------
17
index XXXXXXX..XXXXXXX 100644
12
docs/devel/multi-thread-tcg.rst | 1 -
18
--- a/accel/tcg/internal.h
13
7 files changed, 8 insertions(+), 97 deletions(-)
19
+++ b/accel/tcg/internal.h
14
delete mode 100644 include/tcg/oversized-guest.h
20
@@ -XXX,XX +XXX,XX @@ TranslationBlock *tb_gen_code(CPUState *cpu, target_ulong pc,
15
21
target_ulong cs_base, uint32_t flags,
16
diff --git a/include/qemu/atomic.h b/include/qemu/atomic.h
22
int cflags);
17
index XXXXXXX..XXXXXXX 100644
23
18
--- a/include/qemu/atomic.h
24
+void QEMU_NORETURN cpu_io_recompile(CPUState *cpu, uintptr_t retaddr);
19
+++ b/include/qemu/atomic.h
25
+
20
@@ -XXX,XX +XXX,XX @@
26
#endif /* ACCEL_TCG_INTERNAL_H */
21
*/
27
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
22
#define signal_barrier() __atomic_signal_fence(__ATOMIC_SEQ_CST)
28
index XXXXXXX..XXXXXXX 100644
23
29
--- a/include/exec/exec-all.h
24
-/* Sanity check that the size of an atomic operation isn't "overly large".
30
+++ b/include/exec/exec-all.h
25
+/*
31
@@ -XXX,XX +XXX,XX @@ void restore_state_to_opc(CPUArchState *env, TranslationBlock *tb,
26
+ * Sanity check that the size of an atomic operation isn't "overly large".
32
bool cpu_restore_state(CPUState *cpu, uintptr_t searched_pc, bool will_exit);
27
* Despite the fact that e.g. i686 has 64-bit atomic operations, we do not
33
28
* want to use them because we ought not need them, and this lets us do a
34
void QEMU_NORETURN cpu_loop_exit_noexc(CPUState *cpu);
29
* bit of sanity checking that other 32-bit hosts might build.
35
-void QEMU_NORETURN cpu_io_recompile(CPUState *cpu, uintptr_t retaddr);
30
- *
36
void QEMU_NORETURN cpu_loop_exit(CPUState *cpu);
31
- * That said, we have a problem on 64-bit ILP32 hosts in that in order to
37
void QEMU_NORETURN cpu_loop_exit_restore(CPUState *cpu, uintptr_t pc);
32
- * sync with TCG_OVERSIZED_GUEST, this must match TCG_TARGET_REG_BITS.
38
void QEMU_NORETURN cpu_loop_exit_atomic(CPUState *cpu, uintptr_t pc);
33
- * We'd prefer not want to pull in everything else TCG related, so handle
34
- * those few cases by hand.
35
- *
36
- * Note that x32 is fully detected with __x86_64__ + _ILP32, and that for
37
- * Sparc we always force the use of sparcv9 in configure. MIPS n32 (ILP32) &
38
- * n64 (LP64) ABIs are both detected using __mips64.
39
*/
40
-#if defined(__x86_64__) || defined(__sparc__) || defined(__mips64)
41
-# define ATOMIC_REG_SIZE 8
42
-#else
43
-# define ATOMIC_REG_SIZE sizeof(void *)
44
-#endif
45
+#define ATOMIC_REG_SIZE sizeof(void *)
46
47
/* Weak atomic operations prevent the compiler moving other
48
* loads/stores past the atomic operation load/store. However there is
49
diff --git a/include/tcg/oversized-guest.h b/include/tcg/oversized-guest.h
50
deleted file mode 100644
51
index XXXXXXX..XXXXXXX
52
--- a/include/tcg/oversized-guest.h
53
+++ /dev/null
54
@@ -XXX,XX +XXX,XX @@
55
-/* SPDX-License-Identifier: MIT */
56
-/*
57
- * Define TCG_OVERSIZED_GUEST
58
- * Copyright (c) 2008 Fabrice Bellard
59
- */
60
-
61
-#ifndef EXEC_TCG_OVERSIZED_GUEST_H
62
-#define EXEC_TCG_OVERSIZED_GUEST_H
63
-
64
-#include "tcg-target-reg-bits.h"
65
-#include "cpu-param.h"
66
-
67
-/*
68
- * Oversized TCG guests make things like MTTCG hard
69
- * as we can't use atomics for cputlb updates.
70
- */
71
-#if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
72
-#define TCG_OVERSIZED_GUEST 1
73
-#else
74
-#define TCG_OVERSIZED_GUEST 0
75
-#endif
76
-
77
-#endif
39
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
78
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
40
index XXXXXXX..XXXXXXX 100644
79
index XXXXXXX..XXXXXXX 100644
41
--- a/accel/tcg/cputlb.c
80
--- a/accel/tcg/cputlb.c
42
+++ b/accel/tcg/cputlb.c
81
+++ b/accel/tcg/cputlb.c
43
@@ -XXX,XX +XXX,XX @@
82
@@ -XXX,XX +XXX,XX @@
44
#include "exec/translate-all.h"
45
#include "trace/trace-root.h"
46
#include "trace/mem.h"
47
+#include "internal.h"
48
#ifdef CONFIG_PLUGIN
49
#include "qemu/plugin-memory.h"
83
#include "qemu/plugin-memory.h"
50
#endif
84
#endif
85
#include "tcg/tcg-ldst.h"
86
-#include "tcg/oversized-guest.h"
87
88
/* DEBUG defines, enable DEBUG_TLB_LOG to log to the CPU_LOG_MMU target */
89
/* #define DEBUG_TLB */
90
@@ -XXX,XX +XXX,XX @@ static inline uint64_t tlb_read_idx(const CPUTLBEntry *entry,
91
return qatomic_read(ptr);
92
#else
93
const uint64_t *ptr = &entry->addr_idx[access_type];
94
-# if TCG_OVERSIZED_GUEST
95
- return *ptr;
96
-# else
97
/* ofs might correspond to .addr_write, so use qatomic_read */
98
return qatomic_read(ptr);
99
-# endif
100
#endif
101
}
102
103
@@ -XXX,XX +XXX,XX @@ static void tlb_reset_dirty_range_locked(CPUTLBEntry *tlb_entry,
104
uint32_t *ptr_write = (uint32_t *)&tlb_entry->addr_write;
105
ptr_write += HOST_BIG_ENDIAN;
106
qatomic_set(ptr_write, *ptr_write | TLB_NOTDIRTY);
107
-#elif TCG_OVERSIZED_GUEST
108
- tlb_entry->addr_write |= TLB_NOTDIRTY;
109
#else
110
qatomic_set(&tlb_entry->addr_write,
111
tlb_entry->addr_write | TLB_NOTDIRTY);
112
diff --git a/accel/tcg/tcg-all.c b/accel/tcg/tcg-all.c
113
index XXXXXXX..XXXXXXX 100644
114
--- a/accel/tcg/tcg-all.c
115
+++ b/accel/tcg/tcg-all.c
116
@@ -XXX,XX +XXX,XX @@
117
#include "exec/replay-core.h"
118
#include "system/cpu-timers.h"
119
#include "tcg/startup.h"
120
-#include "tcg/oversized-guest.h"
121
#include "qapi/error.h"
122
#include "qemu/error-report.h"
123
#include "qemu/accel.h"
124
@@ -XXX,XX +XXX,XX @@
125
#include "hw/boards.h"
126
#endif
127
#include "internal-common.h"
128
+#include "cpu-param.h"
129
+
130
131
struct TCGState {
132
AccelState parent_obj;
133
@@ -XXX,XX +XXX,XX @@ DECLARE_INSTANCE_CHECKER(TCGState, TCG_STATE,
134
135
static bool default_mttcg_enabled(void)
136
{
137
- if (icount_enabled() || TCG_OVERSIZED_GUEST) {
138
+ if (icount_enabled()) {
139
return false;
140
}
141
#ifdef TARGET_SUPPORTS_MTTCG
142
@@ -XXX,XX +XXX,XX @@ static void tcg_set_thread(Object *obj, const char *value, Error **errp)
143
TCGState *s = TCG_STATE(obj);
144
145
if (strcmp(value, "multi") == 0) {
146
- if (TCG_OVERSIZED_GUEST) {
147
- error_setg(errp, "No MTTCG when guest word size > hosts");
148
- } else if (icount_enabled()) {
149
+ if (icount_enabled()) {
150
error_setg(errp, "No MTTCG when icount is enabled");
151
} else {
152
#ifndef TARGET_SUPPORTS_MTTCG
153
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
154
index XXXXXXX..XXXXXXX 100644
155
--- a/target/arm/ptw.c
156
+++ b/target/arm/ptw.c
157
@@ -XXX,XX +XXX,XX @@
158
#include "internals.h"
159
#include "cpu-features.h"
160
#include "idau.h"
161
-#ifdef CONFIG_TCG
162
-# include "tcg/oversized-guest.h"
163
-#endif
164
165
typedef struct S1Translate {
166
/*
167
@@ -XXX,XX +XXX,XX @@ static uint64_t arm_casq_ptw(CPUARMState *env, uint64_t old_val,
168
ptw->out_rw = true;
169
}
170
171
-#ifdef CONFIG_ATOMIC64
172
if (ptw->out_be) {
173
old_val = cpu_to_be64(old_val);
174
new_val = cpu_to_be64(new_val);
175
@@ -XXX,XX +XXX,XX @@ static uint64_t arm_casq_ptw(CPUARMState *env, uint64_t old_val,
176
cur_val = qatomic_cmpxchg__nocheck((uint64_t *)host, old_val, new_val);
177
cur_val = le64_to_cpu(cur_val);
178
}
179
-#else
180
- /*
181
- * We can't support the full 64-bit atomic cmpxchg on the host.
182
- * Because this is only used for FEAT_HAFDBS, which is only for AA64,
183
- * we know that TCG_OVERSIZED_GUEST is set, which means that we are
184
- * running in round-robin mode and could only race with dma i/o.
185
- */
186
-#if !TCG_OVERSIZED_GUEST
187
-# error "Unexpected configuration"
188
-#endif
189
- bool locked = bql_locked();
190
- if (!locked) {
191
- bql_lock();
192
- }
193
- if (ptw->out_be) {
194
- cur_val = ldq_be_p(host);
195
- if (cur_val == old_val) {
196
- stq_be_p(host, new_val);
197
- }
198
- } else {
199
- cur_val = ldq_le_p(host);
200
- if (cur_val == old_val) {
201
- stq_le_p(host, new_val);
202
- }
203
- }
204
- if (!locked) {
205
- bql_unlock();
206
- }
207
-#endif
208
-
209
return cur_val;
210
#else
211
/* AArch32 does not have FEAT_HADFS; non-TCG guests only use debug-mode. */
212
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
213
index XXXXXXX..XXXXXXX 100644
214
--- a/target/riscv/cpu_helper.c
215
+++ b/target/riscv/cpu_helper.c
216
@@ -XXX,XX +XXX,XX @@
217
#include "system/cpu-timers.h"
218
#include "cpu_bits.h"
219
#include "debug.h"
220
-#include "tcg/oversized-guest.h"
221
#include "pmp.h"
222
223
int riscv_env_mmu_index(CPURISCVState *env, bool ifetch)
224
@@ -XXX,XX +XXX,XX @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
225
hwaddr pte_addr;
226
int i;
227
228
-#if !TCG_OVERSIZED_GUEST
229
-restart:
230
-#endif
231
+ restart:
232
for (i = 0; i < levels; i++, ptshift -= ptidxbits) {
233
target_ulong idx;
234
if (i == 0) {
235
@@ -XXX,XX +XXX,XX @@ restart:
236
false, MEMTXATTRS_UNSPECIFIED);
237
if (memory_region_is_ram(mr)) {
238
target_ulong *pte_pa = qemu_map_ram_ptr(mr->ram_block, addr1);
239
-#if TCG_OVERSIZED_GUEST
240
- /*
241
- * MTTCG is not enabled on oversized TCG guests so
242
- * page table updates do not need to be atomic
243
- */
244
- *pte_pa = pte = updated_pte;
245
-#else
246
target_ulong old_pte;
247
if (riscv_cpu_sxl(env) == MXL_RV32) {
248
old_pte = qatomic_cmpxchg((uint32_t *)pte_pa, pte, updated_pte);
249
@@ -XXX,XX +XXX,XX @@ restart:
250
goto restart;
251
}
252
pte = updated_pte;
253
-#endif
254
} else {
255
/*
256
* Misconfigured PTE in ROM (AD bits are not preset) or
257
diff --git a/docs/devel/multi-thread-tcg.rst b/docs/devel/multi-thread-tcg.rst
258
index XXXXXXX..XXXXXXX 100644
259
--- a/docs/devel/multi-thread-tcg.rst
260
+++ b/docs/devel/multi-thread-tcg.rst
261
@@ -XXX,XX +XXX,XX @@ if:
262
263
* forced by --accel tcg,thread=single
264
* enabling --icount mode
265
-* 64 bit guests on 32 bit hosts (TCG_OVERSIZED_GUEST)
266
267
In the general case of running translated code there should be no
268
inter-vCPU dependencies and all vCPUs should be able to run at full
51
--
269
--
52
2.25.1
270
2.43.0
53
271
54
272
diff view generated by jsdifflib
[PULL 10/10] tcg: Toggle page execution for Apple Silicon
[PULL 03/24] tcg: Drop support for two address registers in gen_ldst
1
From: Roman Bolshakov <r.bolshakov@yadro.com>
1
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2
3
Pages can't be both write and executable at the same time on Apple
4
Silicon. macOS provides public API to switch write protection [1] for
5
JIT applications, like TCG.
6
7
1. https://developer.apple.com/documentation/apple_silicon/porting_just-in-time_compilers_to_apple_silicon
8
9
Tested-by: Alexander Graf <agraf@csgraf.de>
10
Signed-off-by: Roman Bolshakov <r.bolshakov@yadro.com>
11
Message-Id: <20210113032806.18220-1-r.bolshakov@yadro.com>
12
[rth: Inline the qemu_thread_jit_* functions;
13
drop the MAP_JIT change for a follow-on patch.]
14
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
15
---
3
---
16
include/qemu/osdep.h | 28 ++++++++++++++++++++++++++++
4
tcg/tcg-op-ldst.c | 21 +++------------------
17
accel/tcg/cpu-exec.c | 2 ++
5
tcg/tcg.c | 4 +---
18
accel/tcg/translate-all.c | 3 +++
6
2 files changed, 4 insertions(+), 21 deletions(-)
19
tcg/tcg.c | 1 +
20
4 files changed, 34 insertions(+)
21
7
22
diff --git a/include/qemu/osdep.h b/include/qemu/osdep.h
8
diff --git a/tcg/tcg-op-ldst.c b/tcg/tcg-op-ldst.c
23
index XXXXXXX..XXXXXXX 100644
9
index XXXXXXX..XXXXXXX 100644
24
--- a/include/qemu/osdep.h
10
--- a/tcg/tcg-op-ldst.c
25
+++ b/include/qemu/osdep.h
11
+++ b/tcg/tcg-op-ldst.c
26
@@ -XXX,XX +XXX,XX @@ extern int daemon(int, int);
12
@@ -XXX,XX +XXX,XX @@ static MemOp tcg_canonicalize_memop(MemOp op, bool is64, bool st)
27
#include "sysemu/os-posix.h"
13
static void gen_ldst(TCGOpcode opc, TCGType type, TCGTemp *vl, TCGTemp *vh,
28
#endif
14
TCGTemp *addr, MemOpIdx oi)
29
15
{
30
+#ifdef __APPLE__
16
- if (TCG_TARGET_REG_BITS == 64 || tcg_ctx->addr_type == TCG_TYPE_I32) {
31
+#include <AvailabilityMacros.h>
17
- if (vh) {
32
+#endif
18
- tcg_gen_op4(opc, type, temp_arg(vl), temp_arg(vh),
33
+
19
- temp_arg(addr), oi);
34
#include "glib-compat.h"
20
- } else {
35
#include "qemu/typedefs.h"
21
- tcg_gen_op3(opc, type, temp_arg(vl), temp_arg(addr), oi);
36
22
- }
37
@@ -XXX,XX +XXX,XX @@ char *qemu_get_host_name(Error **errp);
23
+ if (vh) {
38
*/
24
+ tcg_gen_op4(opc, type, temp_arg(vl), temp_arg(vh), temp_arg(addr), oi);
39
size_t qemu_get_host_physmem(void);
25
} else {
40
26
- /* See TCGV_LOW/HIGH. */
41
+/*
27
- TCGTemp *al = addr + HOST_BIG_ENDIAN;
42
+ * Toggle write/execute on the pages marked MAP_JIT
28
- TCGTemp *ah = addr + !HOST_BIG_ENDIAN;
43
+ * for the current thread.
29
-
44
+ */
30
- if (vh) {
45
+#if defined(MAC_OS_VERSION_11_0) && \
31
- tcg_gen_op5(opc, type, temp_arg(vl), temp_arg(vh),
46
+ MAC_OS_X_VERSION_MAX_ALLOWED >= MAC_OS_VERSION_11_0
32
- temp_arg(al), temp_arg(ah), oi);
47
+static inline void qemu_thread_jit_execute(void)
33
- } else {
48
+{
34
- tcg_gen_op4(opc, type, temp_arg(vl),
49
+ if (__builtin_available(macOS 11.0, *)) {
35
- temp_arg(al), temp_arg(ah), oi);
50
+ pthread_jit_write_protect_np(true);
36
- }
51
+ }
37
+ tcg_gen_op3(opc, type, temp_arg(vl), temp_arg(addr), oi);
52
+}
53
+
54
+static inline void qemu_thread_jit_write(void)
55
+{
56
+ if (__builtin_available(macOS 11.0, *)) {
57
+ pthread_jit_write_protect_np(false);
58
+ }
59
+}
60
+#else
61
+static inline void qemu_thread_jit_write(void) {}
62
+static inline void qemu_thread_jit_execute(void) {}
63
+#endif
64
+
65
#endif
66
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
67
index XXXXXXX..XXXXXXX 100644
68
--- a/accel/tcg/cpu-exec.c
69
+++ b/accel/tcg/cpu-exec.c
70
@@ -XXX,XX +XXX,XX @@ cpu_tb_exec(CPUState *cpu, TranslationBlock *itb, int *tb_exit)
71
}
38
}
72
#endif /* DEBUG_DISAS */
73
74
+ qemu_thread_jit_execute();
75
ret = tcg_qemu_tb_exec(env, tb_ptr);
76
cpu->can_do_io = 1;
77
/*
78
@@ -XXX,XX +XXX,XX @@ static inline void tb_add_jump(TranslationBlock *tb, int n,
79
{
80
uintptr_t old;
81
82
+ qemu_thread_jit_write();
83
assert(n < ARRAY_SIZE(tb->jmp_list_next));
84
qemu_spin_lock(&tb_next->jmp_lock);
85
86
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
87
index XXXXXXX..XXXXXXX 100644
88
--- a/accel/tcg/translate-all.c
89
+++ b/accel/tcg/translate-all.c
90
@@ -XXX,XX +XXX,XX @@ static void do_tb_phys_invalidate(TranslationBlock *tb, bool rm_from_page_list)
91
92
static void tb_phys_invalidate__locked(TranslationBlock *tb)
93
{
94
+ qemu_thread_jit_write();
95
do_tb_phys_invalidate(tb, true);
96
+ qemu_thread_jit_execute();
97
}
39
}
98
99
/* invalidate one TB
100
@@ -XXX,XX +XXX,XX @@ TranslationBlock *tb_gen_code(CPUState *cpu,
101
#endif
102
103
assert_memory_lock();
104
+ qemu_thread_jit_write();
105
106
phys_pc = get_page_addr_code(env, pc);
107
40
108
diff --git a/tcg/tcg.c b/tcg/tcg.c
41
diff --git a/tcg/tcg.c b/tcg/tcg.c
109
index XXXXXXX..XXXXXXX 100644
42
index XXXXXXX..XXXXXXX 100644
110
--- a/tcg/tcg.c
43
--- a/tcg/tcg.c
111
+++ b/tcg/tcg.c
44
+++ b/tcg/tcg.c
112
@@ -XXX,XX +XXX,XX @@ void tcg_prologue_init(TCGContext *s)
45
@@ -XXX,XX +XXX,XX @@ void tcg_func_start(TCGContext *s)
113
s->pool_labels = NULL;
46
s->emit_before_op = NULL;
114
#endif
47
QSIMPLEQ_INIT(&s->labels);
115
48
116
+ qemu_thread_jit_write();
49
- tcg_debug_assert(s->addr_type == TCG_TYPE_I32 ||
117
/* Generate the prologue. */
50
- s->addr_type == TCG_TYPE_I64);
118
tcg_target_qemu_prologue(s);
51
-
52
+ tcg_debug_assert(s->addr_type <= TCG_TYPE_REG);
53
tcg_debug_assert(s->insn_start_words > 0);
54
}
119
55
120
--
56
--
121
2.25.1
57
2.43.0
122
58
123
59
diff view generated by jsdifflib
New patch
[PULL 04/24] tcg: Merge INDEX_op_qemu_*_{a32,a64}_*
1
Since 64-on-32 is now unsupported, guest addresses always
2
fit in one host register. Drop the replication of opcodes.
1
3
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
---
6
include/tcg/tcg-opc.h | 28 ++------
7
tcg/optimize.c | 21 ++----
8
tcg/tcg-op-ldst.c | 82 +++++----------------
9
tcg/tcg.c | 42 ++++-------
10
tcg/tci.c | 119 ++++++-------------------------
11
tcg/aarch64/tcg-target.c.inc | 36 ++++------
12
tcg/arm/tcg-target.c.inc | 40 +++--------
13
tcg/i386/tcg-target.c.inc | 69 ++++--------------
14
tcg/loongarch64/tcg-target.c.inc | 36 ++++------
15
tcg/mips/tcg-target.c.inc | 51 +++----------
16
tcg/ppc/tcg-target.c.inc | 68 ++++--------------
17
tcg/riscv/tcg-target.c.inc | 24 +++----
18
tcg/s390x/tcg-target.c.inc | 36 ++++------
19
tcg/sparc64/tcg-target.c.inc | 24 +++----
20
tcg/tci/tcg-target.c.inc | 60 ++++------------
21
15 files changed, 177 insertions(+), 559 deletions(-)
22
23
diff --git a/include/tcg/tcg-opc.h b/include/tcg/tcg-opc.h
24
index XXXXXXX..XXXXXXX 100644
25
--- a/include/tcg/tcg-opc.h
26
+++ b/include/tcg/tcg-opc.h
27
@@ -XXX,XX +XXX,XX @@ DEF(goto_ptr, 0, 1, 0, TCG_OPF_BB_EXIT | TCG_OPF_BB_END)
28
DEF(plugin_cb, 0, 0, 1, TCG_OPF_NOT_PRESENT)
29
DEF(plugin_mem_cb, 0, 1, 1, TCG_OPF_NOT_PRESENT)
30
31
-/* Replicate ld/st ops for 32 and 64-bit guest addresses. */
32
-DEF(qemu_ld_a32_i32, 1, 1, 1,
33
+DEF(qemu_ld_i32, 1, 1, 1,
34
TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
35
-DEF(qemu_st_a32_i32, 0, 1 + 1, 1,
36
+DEF(qemu_st_i32, 0, 1 + 1, 1,
37
TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
38
-DEF(qemu_ld_a32_i64, DATA64_ARGS, 1, 1,
39
+DEF(qemu_ld_i64, DATA64_ARGS, 1, 1,
40
TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
41
-DEF(qemu_st_a32_i64, 0, DATA64_ARGS + 1, 1,
42
- TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
43
-
44
-DEF(qemu_ld_a64_i32, 1, DATA64_ARGS, 1,
45
- TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
46
-DEF(qemu_st_a64_i32, 0, 1 + DATA64_ARGS, 1,
47
- TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
48
-DEF(qemu_ld_a64_i64, DATA64_ARGS, DATA64_ARGS, 1,
49
- TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
50
-DEF(qemu_st_a64_i64, 0, DATA64_ARGS + DATA64_ARGS, 1,
51
+DEF(qemu_st_i64, 0, DATA64_ARGS + 1, 1,
52
TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
53
54
/* Only used by i386 to cope with stupid register constraints. */
55
-DEF(qemu_st8_a32_i32, 0, 1 + 1, 1,
56
- TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
57
-DEF(qemu_st8_a64_i32, 0, 1 + DATA64_ARGS, 1,
58
+DEF(qemu_st8_i32, 0, 1 + 1, 1,
59
TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
60
61
/* Only for 64-bit hosts at the moment. */
62
-DEF(qemu_ld_a32_i128, 2, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
63
-DEF(qemu_ld_a64_i128, 2, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
64
-DEF(qemu_st_a32_i128, 0, 3, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
65
-DEF(qemu_st_a64_i128, 0, 3, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
66
+DEF(qemu_ld_i128, 2, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
67
+DEF(qemu_st_i128, 0, 3, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
68
69
/* Host vector support. */
70
71
diff --git a/tcg/optimize.c b/tcg/optimize.c
72
index XXXXXXX..XXXXXXX 100644
73
--- a/tcg/optimize.c
74
+++ b/tcg/optimize.c
75
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
76
CASE_OP_32_64_VEC(orc):
77
done = fold_orc(&ctx, op);
78
break;
79
- case INDEX_op_qemu_ld_a32_i32:
80
- case INDEX_op_qemu_ld_a64_i32:
81
+ case INDEX_op_qemu_ld_i32:
82
done = fold_qemu_ld_1reg(&ctx, op);
83
break;
84
- case INDEX_op_qemu_ld_a32_i64:
85
- case INDEX_op_qemu_ld_a64_i64:
86
+ case INDEX_op_qemu_ld_i64:
87
if (TCG_TARGET_REG_BITS == 64) {
88
done = fold_qemu_ld_1reg(&ctx, op);
89
break;
90
}
91
QEMU_FALLTHROUGH;
92
- case INDEX_op_qemu_ld_a32_i128:
93
- case INDEX_op_qemu_ld_a64_i128:
94
+ case INDEX_op_qemu_ld_i128:
95
done = fold_qemu_ld_2reg(&ctx, op);
96
break;
97
- case INDEX_op_qemu_st8_a32_i32:
98
- case INDEX_op_qemu_st8_a64_i32:
99
- case INDEX_op_qemu_st_a32_i32:
100
- case INDEX_op_qemu_st_a64_i32:
101
- case INDEX_op_qemu_st_a32_i64:
102
- case INDEX_op_qemu_st_a64_i64:
103
- case INDEX_op_qemu_st_a32_i128:
104
- case INDEX_op_qemu_st_a64_i128:
105
+ case INDEX_op_qemu_st8_i32:
106
+ case INDEX_op_qemu_st_i32:
107
+ case INDEX_op_qemu_st_i64:
108
+ case INDEX_op_qemu_st_i128:
109
done = fold_qemu_st(&ctx, op);
110
break;
111
CASE_OP_32_64(rem):
112
diff --git a/tcg/tcg-op-ldst.c b/tcg/tcg-op-ldst.c
113
index XXXXXXX..XXXXXXX 100644
114
--- a/tcg/tcg-op-ldst.c
115
+++ b/tcg/tcg-op-ldst.c
116
@@ -XXX,XX +XXX,XX @@ static void tcg_gen_qemu_ld_i32_int(TCGv_i32 val, TCGTemp *addr,
117
MemOp orig_memop;
118
MemOpIdx orig_oi, oi;
119
TCGv_i64 copy_addr;
120
- TCGOpcode opc;
121
122
tcg_gen_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD);
123
orig_memop = memop = tcg_canonicalize_memop(memop, 0, 0);
124
@@ -XXX,XX +XXX,XX @@ static void tcg_gen_qemu_ld_i32_int(TCGv_i32 val, TCGTemp *addr,
125
}
126
127
copy_addr = plugin_maybe_preserve_addr(addr);
128
- if (tcg_ctx->addr_type == TCG_TYPE_I32) {
129
- opc = INDEX_op_qemu_ld_a32_i32;
130
- } else {
131
- opc = INDEX_op_qemu_ld_a64_i32;
132
- }
133
- gen_ldst(opc, TCG_TYPE_I32, tcgv_i32_temp(val), NULL, addr, oi);
134
+ gen_ldst(INDEX_op_qemu_ld_i32, TCG_TYPE_I32,
135
+ tcgv_i32_temp(val), NULL, addr, oi);
136
plugin_gen_mem_callbacks_i32(val, copy_addr, addr, orig_oi,
137
QEMU_PLUGIN_MEM_R);
138
139
@@ -XXX,XX +XXX,XX @@ static void tcg_gen_qemu_st_i32_int(TCGv_i32 val, TCGTemp *addr,
140
}
141
142
if (TCG_TARGET_HAS_qemu_st8_i32 && (memop & MO_SIZE) == MO_8) {
143
- if (tcg_ctx->addr_type == TCG_TYPE_I32) {
144
- opc = INDEX_op_qemu_st8_a32_i32;
145
- } else {
146
- opc = INDEX_op_qemu_st8_a64_i32;
147
- }
148
+ opc = INDEX_op_qemu_st8_i32;
149
} else {
150
- if (tcg_ctx->addr_type == TCG_TYPE_I32) {
151
- opc = INDEX_op_qemu_st_a32_i32;
152
- } else {
153
- opc = INDEX_op_qemu_st_a64_i32;
154
- }
155
+ opc = INDEX_op_qemu_st_i32;
156
}
157
gen_ldst(opc, TCG_TYPE_I32, tcgv_i32_temp(val), NULL, addr, oi);
158
plugin_gen_mem_callbacks_i32(val, NULL, addr, orig_oi, QEMU_PLUGIN_MEM_W);
159
@@ -XXX,XX +XXX,XX @@ static void tcg_gen_qemu_ld_i64_int(TCGv_i64 val, TCGTemp *addr,
160
MemOp orig_memop;
161
MemOpIdx orig_oi, oi;
162
TCGv_i64 copy_addr;
163
- TCGOpcode opc;
164
165
if (TCG_TARGET_REG_BITS == 32 && (memop & MO_SIZE) < MO_64) {
166
tcg_gen_qemu_ld_i32_int(TCGV_LOW(val), addr, idx, memop);
167
@@ -XXX,XX +XXX,XX @@ static void tcg_gen_qemu_ld_i64_int(TCGv_i64 val, TCGTemp *addr,
168
}
169
170
copy_addr = plugin_maybe_preserve_addr(addr);
171
- if (tcg_ctx->addr_type == TCG_TYPE_I32) {
172
- opc = INDEX_op_qemu_ld_a32_i64;
173
- } else {
174
- opc = INDEX_op_qemu_ld_a64_i64;
175
- }
176
- gen_ldst_i64(opc, val, addr, oi);
177
+ gen_ldst_i64(INDEX_op_qemu_ld_i64, val, addr, oi);
178
plugin_gen_mem_callbacks_i64(val, copy_addr, addr, orig_oi,
179
QEMU_PLUGIN_MEM_R);
180
181
@@ -XXX,XX +XXX,XX @@ static void tcg_gen_qemu_st_i64_int(TCGv_i64 val, TCGTemp *addr,
182
{
183
TCGv_i64 swap = NULL;
184
MemOpIdx orig_oi, oi;
185
- TCGOpcode opc;
186
187
if (TCG_TARGET_REG_BITS == 32 && (memop & MO_SIZE) < MO_64) {
188
tcg_gen_qemu_st_i32_int(TCGV_LOW(val), addr, idx, memop);
189
@@ -XXX,XX +XXX,XX @@ static void tcg_gen_qemu_st_i64_int(TCGv_i64 val, TCGTemp *addr,
190
oi = make_memop_idx(memop, idx);
191
}
192
193
- if (tcg_ctx->addr_type == TCG_TYPE_I32) {
194
- opc = INDEX_op_qemu_st_a32_i64;
195
- } else {
196
- opc = INDEX_op_qemu_st_a64_i64;
197
- }
198
- gen_ldst_i64(opc, val, addr, oi);
199
+ gen_ldst_i64(INDEX_op_qemu_st_i64, val, addr, oi);
200
plugin_gen_mem_callbacks_i64(val, NULL, addr, orig_oi, QEMU_PLUGIN_MEM_W);
201
202
if (swap) {
203
@@ -XXX,XX +XXX,XX @@ static void tcg_gen_qemu_ld_i128_int(TCGv_i128 val, TCGTemp *addr,
204
{
205
MemOpIdx orig_oi;
206
TCGv_i64 ext_addr = NULL;
207
- TCGOpcode opc;
208
209
check_max_alignment(memop_alignment_bits(memop));
210
tcg_gen_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD);
211
@@ -XXX,XX +XXX,XX @@ static void tcg_gen_qemu_ld_i128_int(TCGv_i128 val, TCGTemp *addr,
212
hi = TCGV128_HIGH(val);
213
}
214
215
- if (tcg_ctx->addr_type == TCG_TYPE_I32) {
216
- opc = INDEX_op_qemu_ld_a32_i128;
217
- } else {
218
- opc = INDEX_op_qemu_ld_a64_i128;
219
- }
220
- gen_ldst(opc, TCG_TYPE_I128, tcgv_i64_temp(lo),
221
+ gen_ldst(INDEX_op_qemu_ld_i128, TCG_TYPE_I128, tcgv_i64_temp(lo),
222
tcgv_i64_temp(hi), addr, oi);
223
224
if (need_bswap) {
225
@@ -XXX,XX +XXX,XX @@ static void tcg_gen_qemu_ld_i128_int(TCGv_i128 val, TCGTemp *addr,
226
canonicalize_memop_i128_as_i64(mop, memop);
227
need_bswap = (mop[0] ^ memop) & MO_BSWAP;
228
229
- if (tcg_ctx->addr_type == TCG_TYPE_I32) {
230
- opc = INDEX_op_qemu_ld_a32_i64;
231
- } else {
232
- opc = INDEX_op_qemu_ld_a64_i64;
233
- }
234
-
235
/*
236
* Since there are no global TCGv_i128, there is no visible state
237
* changed if the second load faults. Load directly into the two
238
@@ -XXX,XX +XXX,XX @@ static void tcg_gen_qemu_ld_i128_int(TCGv_i128 val, TCGTemp *addr,
239
y = TCGV128_LOW(val);
240
}
241
242
- gen_ldst_i64(opc, x, addr, make_memop_idx(mop[0], idx));
243
+ gen_ldst_i64(INDEX_op_qemu_ld_i64, x, addr,
244
+ make_memop_idx(mop[0], idx));
245
246
if (need_bswap) {
247
tcg_gen_bswap64_i64(x, x);
248
@@ -XXX,XX +XXX,XX @@ static void tcg_gen_qemu_ld_i128_int(TCGv_i128 val, TCGTemp *addr,
249
addr_p8 = tcgv_i64_temp(t);
250
}
251
252
- gen_ldst_i64(opc, y, addr_p8, make_memop_idx(mop[1], idx));
253
+ gen_ldst_i64(INDEX_op_qemu_ld_i64, y, addr_p8,
254
+ make_memop_idx(mop[1], idx));
255
tcg_temp_free_internal(addr_p8);
256
257
if (need_bswap) {
258
@@ -XXX,XX +XXX,XX @@ static void tcg_gen_qemu_st_i128_int(TCGv_i128 val, TCGTemp *addr,
259
{
260
MemOpIdx orig_oi;
261
TCGv_i64 ext_addr = NULL;
262
- TCGOpcode opc;
263
264
check_max_alignment(memop_alignment_bits(memop));
265
tcg_gen_req_mo(TCG_MO_ST_LD | TCG_MO_ST_ST);
266
@@ -XXX,XX +XXX,XX @@ static void tcg_gen_qemu_st_i128_int(TCGv_i128 val, TCGTemp *addr,
267
hi = TCGV128_HIGH(val);
268
}
269
270
- if (tcg_ctx->addr_type == TCG_TYPE_I32) {
271
- opc = INDEX_op_qemu_st_a32_i128;
272
- } else {
273
- opc = INDEX_op_qemu_st_a64_i128;
274
- }
275
- gen_ldst(opc, TCG_TYPE_I128, tcgv_i64_temp(lo),
276
- tcgv_i64_temp(hi), addr, oi);
277
+ gen_ldst(INDEX_op_qemu_st_i128, TCG_TYPE_I128,
278
+ tcgv_i64_temp(lo), tcgv_i64_temp(hi), addr, oi);
279
280
if (need_bswap) {
281
tcg_temp_free_i64(lo);
282
@@ -XXX,XX +XXX,XX @@ static void tcg_gen_qemu_st_i128_int(TCGv_i128 val, TCGTemp *addr,
283
284
canonicalize_memop_i128_as_i64(mop, memop);
285
286
- if (tcg_ctx->addr_type == TCG_TYPE_I32) {
287
- opc = INDEX_op_qemu_st_a32_i64;
288
- } else {
289
- opc = INDEX_op_qemu_st_a64_i64;
290
- }
291
-
292
if ((memop & MO_BSWAP) == MO_LE) {
293
x = TCGV128_LOW(val);
294
y = TCGV128_HIGH(val);
295
@@ -XXX,XX +XXX,XX @@ static void tcg_gen_qemu_st_i128_int(TCGv_i128 val, TCGTemp *addr,
296
x = b;
297
}
298
299
- gen_ldst_i64(opc, x, addr, make_memop_idx(mop[0], idx));
300
+ gen_ldst_i64(INDEX_op_qemu_st_i64, x, addr,
301
+ make_memop_idx(mop[0], idx));
302
303
if (tcg_ctx->addr_type == TCG_TYPE_I32) {
304
TCGv_i32 t = tcg_temp_ebb_new_i32();
305
@@ -XXX,XX +XXX,XX @@ static void tcg_gen_qemu_st_i128_int(TCGv_i128 val, TCGTemp *addr,
306
307
if (b) {
308
tcg_gen_bswap64_i64(b, y);
309
- gen_ldst_i64(opc, b, addr_p8, make_memop_idx(mop[1], idx));
310
+ gen_ldst_i64(INDEX_op_qemu_st_i64, b, addr_p8,
311
+ make_memop_idx(mop[1], idx));
312
tcg_temp_free_i64(b);
313
} else {
314
- gen_ldst_i64(opc, y, addr_p8, make_memop_idx(mop[1], idx));
315
+ gen_ldst_i64(INDEX_op_qemu_st_i64, y, addr_p8,
316
+ make_memop_idx(mop[1], idx));
317
}
318
tcg_temp_free_internal(addr_p8);
319
} else {
320
diff --git a/tcg/tcg.c b/tcg/tcg.c
321
index XXXXXXX..XXXXXXX 100644
322
--- a/tcg/tcg.c
323
+++ b/tcg/tcg.c
324
@@ -XXX,XX +XXX,XX @@ bool tcg_op_supported(TCGOpcode op, TCGType type, unsigned flags)
325
case INDEX_op_exit_tb:
326
case INDEX_op_goto_tb:
327
case INDEX_op_goto_ptr:
328
- case INDEX_op_qemu_ld_a32_i32:
329
- case INDEX_op_qemu_ld_a64_i32:
330
- case INDEX_op_qemu_st_a32_i32:
331
- case INDEX_op_qemu_st_a64_i32:
332
- case INDEX_op_qemu_ld_a32_i64:
333
- case INDEX_op_qemu_ld_a64_i64:
334
- case INDEX_op_qemu_st_a32_i64:
335
- case INDEX_op_qemu_st_a64_i64:
336
+ case INDEX_op_qemu_ld_i32:
337
+ case INDEX_op_qemu_st_i32:
338
+ case INDEX_op_qemu_ld_i64:
339
+ case INDEX_op_qemu_st_i64:
340
return true;
341
342
- case INDEX_op_qemu_st8_a32_i32:
343
- case INDEX_op_qemu_st8_a64_i32:
344
+ case INDEX_op_qemu_st8_i32:
345
return TCG_TARGET_HAS_qemu_st8_i32;
346
347
- case INDEX_op_qemu_ld_a32_i128:
348
- case INDEX_op_qemu_ld_a64_i128:
349
- case INDEX_op_qemu_st_a32_i128:
350
- case INDEX_op_qemu_st_a64_i128:
351
+ case INDEX_op_qemu_ld_i128:
352
+ case INDEX_op_qemu_st_i128:
353
return TCG_TARGET_HAS_qemu_ldst_i128;
354
355
case INDEX_op_mov_i32:
356
@@ -XXX,XX +XXX,XX @@ void tcg_dump_ops(TCGContext *s, FILE *f, bool have_prefs)
357
}
358
i = 1;
359
break;
360
- case INDEX_op_qemu_ld_a32_i32:
361
- case INDEX_op_qemu_ld_a64_i32:
362
- case INDEX_op_qemu_st_a32_i32:
363
- case INDEX_op_qemu_st_a64_i32:
364
- case INDEX_op_qemu_st8_a32_i32:
365
- case INDEX_op_qemu_st8_a64_i32:
366
- case INDEX_op_qemu_ld_a32_i64:
367
- case INDEX_op_qemu_ld_a64_i64:
368
- case INDEX_op_qemu_st_a32_i64:
369
- case INDEX_op_qemu_st_a64_i64:
370
- case INDEX_op_qemu_ld_a32_i128:
371
- case INDEX_op_qemu_ld_a64_i128:
372
- case INDEX_op_qemu_st_a32_i128:
373
- case INDEX_op_qemu_st_a64_i128:
374
+ case INDEX_op_qemu_ld_i32:
375
+ case INDEX_op_qemu_st_i32:
376
+ case INDEX_op_qemu_st8_i32:
377
+ case INDEX_op_qemu_ld_i64:
378
+ case INDEX_op_qemu_st_i64:
379
+ case INDEX_op_qemu_ld_i128:
380
+ case INDEX_op_qemu_st_i128:
381
{
382
const char *s_al, *s_op, *s_at;
383
MemOpIdx oi = op->args[k++];
384
diff --git a/tcg/tci.c b/tcg/tci.c
385
index XXXXXXX..XXXXXXX 100644
386
--- a/tcg/tci.c
387
+++ b/tcg/tci.c
388
@@ -XXX,XX +XXX,XX @@ static void tci_args_rrrbb(uint32_t insn, TCGReg *r0, TCGReg *r1,
389
*i4 = extract32(insn, 26, 6);
390
}
391
392
-static void tci_args_rrrrr(uint32_t insn, TCGReg *r0, TCGReg *r1,
393
- TCGReg *r2, TCGReg *r3, TCGReg *r4)
394
-{
395
- *r0 = extract32(insn, 8, 4);
396
- *r1 = extract32(insn, 12, 4);
397
- *r2 = extract32(insn, 16, 4);
398
- *r3 = extract32(insn, 20, 4);
399
- *r4 = extract32(insn, 24, 4);
400
-}
401
-
402
static void tci_args_rrrr(uint32_t insn,
403
TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGReg *r3)
404
{
405
@@ -XXX,XX +XXX,XX @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
406
tb_ptr = ptr;
407
break;
408
409
- case INDEX_op_qemu_ld_a32_i32:
410
+ case INDEX_op_qemu_ld_i32:
411
tci_args_rrm(insn, &r0, &r1, &oi);
412
- taddr = (uint32_t)regs[r1];
413
- goto do_ld_i32;
414
- case INDEX_op_qemu_ld_a64_i32:
415
- if (TCG_TARGET_REG_BITS == 64) {
416
- tci_args_rrm(insn, &r0, &r1, &oi);
417
- taddr = regs[r1];
418
- } else {
419
- tci_args_rrrr(insn, &r0, &r1, &r2, &r3);
420
- taddr = tci_uint64(regs[r2], regs[r1]);
421
- oi = regs[r3];
422
- }
423
- do_ld_i32:
424
+ taddr = regs[r1];
425
regs[r0] = tci_qemu_ld(env, taddr, oi, tb_ptr);
426
break;
427
428
- case INDEX_op_qemu_ld_a32_i64:
429
- if (TCG_TARGET_REG_BITS == 64) {
430
- tci_args_rrm(insn, &r0, &r1, &oi);
431
- taddr = (uint32_t)regs[r1];
432
- } else {
433
- tci_args_rrrr(insn, &r0, &r1, &r2, &r3);
434
- taddr = (uint32_t)regs[r2];
435
- oi = regs[r3];
436
- }
437
- goto do_ld_i64;
438
- case INDEX_op_qemu_ld_a64_i64:
439
+ case INDEX_op_qemu_ld_i64:
440
if (TCG_TARGET_REG_BITS == 64) {
441
tci_args_rrm(insn, &r0, &r1, &oi);
442
taddr = regs[r1];
443
} else {
444
- tci_args_rrrrr(insn, &r0, &r1, &r2, &r3, &r4);
445
- taddr = tci_uint64(regs[r3], regs[r2]);
446
- oi = regs[r4];
447
+ tci_args_rrrr(insn, &r0, &r1, &r2, &r3);
448
+ taddr = regs[r2];
449
+ oi = regs[r3];
450
}
451
- do_ld_i64:
452
tmp64 = tci_qemu_ld(env, taddr, oi, tb_ptr);
453
if (TCG_TARGET_REG_BITS == 32) {
454
tci_write_reg64(regs, r1, r0, tmp64);
455
@@ -XXX,XX +XXX,XX @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
456
}
457
break;
458
459
- case INDEX_op_qemu_st_a32_i32:
460
+ case INDEX_op_qemu_st_i32:
461
tci_args_rrm(insn, &r0, &r1, &oi);
462
- taddr = (uint32_t)regs[r1];
463
- goto do_st_i32;
464
- case INDEX_op_qemu_st_a64_i32:
465
- if (TCG_TARGET_REG_BITS == 64) {
466
- tci_args_rrm(insn, &r0, &r1, &oi);
467
- taddr = regs[r1];
468
- } else {
469
- tci_args_rrrr(insn, &r0, &r1, &r2, &r3);
470
- taddr = tci_uint64(regs[r2], regs[r1]);
471
- oi = regs[r3];
472
- }
473
- do_st_i32:
474
+ taddr = regs[r1];
475
tci_qemu_st(env, taddr, regs[r0], oi, tb_ptr);
476
break;
477
478
- case INDEX_op_qemu_st_a32_i64:
479
- if (TCG_TARGET_REG_BITS == 64) {
480
- tci_args_rrm(insn, &r0, &r1, &oi);
481
- tmp64 = regs[r0];
482
- taddr = (uint32_t)regs[r1];
483
- } else {
484
- tci_args_rrrr(insn, &r0, &r1, &r2, &r3);
485
- tmp64 = tci_uint64(regs[r1], regs[r0]);
486
- taddr = (uint32_t)regs[r2];
487
- oi = regs[r3];
488
- }
489
- goto do_st_i64;
490
- case INDEX_op_qemu_st_a64_i64:
491
+ case INDEX_op_qemu_st_i64:
492
if (TCG_TARGET_REG_BITS == 64) {
493
tci_args_rrm(insn, &r0, &r1, &oi);
494
tmp64 = regs[r0];
495
taddr = regs[r1];
496
} else {
497
- tci_args_rrrrr(insn, &r0, &r1, &r2, &r3, &r4);
498
+ tci_args_rrrr(insn, &r0, &r1, &r2, &r3);
499
tmp64 = tci_uint64(regs[r1], regs[r0]);
500
- taddr = tci_uint64(regs[r3], regs[r2]);
501
- oi = regs[r4];
502
+ taddr = regs[r2];
503
+ oi = regs[r3];
504
}
505
- do_st_i64:
506
tci_qemu_st(env, taddr, tmp64, oi, tb_ptr);
507
break;
508
509
@@ -XXX,XX +XXX,XX @@ int print_insn_tci(bfd_vma addr, disassemble_info *info)
510
str_r(r3), str_r(r4), str_r(r5));
511
break;
512
513
- case INDEX_op_qemu_ld_a32_i32:
514
- case INDEX_op_qemu_st_a32_i32:
515
- len = 1 + 1;
516
- goto do_qemu_ldst;
517
- case INDEX_op_qemu_ld_a32_i64:
518
- case INDEX_op_qemu_st_a32_i64:
519
- case INDEX_op_qemu_ld_a64_i32:
520
- case INDEX_op_qemu_st_a64_i32:
521
- len = 1 + DIV_ROUND_UP(64, TCG_TARGET_REG_BITS);
522
- goto do_qemu_ldst;
523
- case INDEX_op_qemu_ld_a64_i64:
524
- case INDEX_op_qemu_st_a64_i64:
525
- len = 2 * DIV_ROUND_UP(64, TCG_TARGET_REG_BITS);
526
- goto do_qemu_ldst;
527
- do_qemu_ldst:
528
- switch (len) {
529
- case 2:
530
- tci_args_rrm(insn, &r0, &r1, &oi);
531
- info->fprintf_func(info->stream, "%-12s %s, %s, %x",
532
- op_name, str_r(r0), str_r(r1), oi);
533
- break;
534
- case 3:
535
+ case INDEX_op_qemu_ld_i64:
536
+ case INDEX_op_qemu_st_i64:
537
+ if (TCG_TARGET_REG_BITS == 32) {
538
tci_args_rrrr(insn, &r0, &r1, &r2, &r3);
539
info->fprintf_func(info->stream, "%-12s %s, %s, %s, %s",
540
op_name, str_r(r0), str_r(r1),
541
str_r(r2), str_r(r3));
542
break;
543
- case 4:
544
- tci_args_rrrrr(insn, &r0, &r1, &r2, &r3, &r4);
545
- info->fprintf_func(info->stream, "%-12s %s, %s, %s, %s, %s",
546
- op_name, str_r(r0), str_r(r1),
547
- str_r(r2), str_r(r3), str_r(r4));
548
- break;
549
- default:
550
- g_assert_not_reached();
551
}
552
+ /* fall through */
553
+ case INDEX_op_qemu_ld_i32:
554
+ case INDEX_op_qemu_st_i32:
555
+ tci_args_rrm(insn, &r0, &r1, &oi);
556
+ info->fprintf_func(info->stream, "%-12s %s, %s, %x",
557
+ op_name, str_r(r0), str_r(r1), oi);
558
break;
559
560
case 0:
561
diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc
562
index XXXXXXX..XXXXXXX 100644
563
--- a/tcg/aarch64/tcg-target.c.inc
564
+++ b/tcg/aarch64/tcg-target.c.inc
565
@@ -XXX,XX +XXX,XX @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType ext,
566
tcg_out_insn(s, 3506, CSEL, ext, a0, REG0(3), REG0(4), args[5]);
567
break;
568
569
- case INDEX_op_qemu_ld_a32_i32:
570
- case INDEX_op_qemu_ld_a64_i32:
571
- case INDEX_op_qemu_ld_a32_i64:
572
- case INDEX_op_qemu_ld_a64_i64:
573
+ case INDEX_op_qemu_ld_i32:
574
+ case INDEX_op_qemu_ld_i64:
575
tcg_out_qemu_ld(s, a0, a1, a2, ext);
576
break;
577
- case INDEX_op_qemu_st_a32_i32:
578
- case INDEX_op_qemu_st_a64_i32:
579
- case INDEX_op_qemu_st_a32_i64:
580
- case INDEX_op_qemu_st_a64_i64:
581
+ case INDEX_op_qemu_st_i32:
582
+ case INDEX_op_qemu_st_i64:
583
tcg_out_qemu_st(s, REG0(0), a1, a2, ext);
584
break;
585
- case INDEX_op_qemu_ld_a32_i128:
586
- case INDEX_op_qemu_ld_a64_i128:
587
+ case INDEX_op_qemu_ld_i128:
588
tcg_out_qemu_ldst_i128(s, a0, a1, a2, args[3], true);
589
break;
590
- case INDEX_op_qemu_st_a32_i128:
591
- case INDEX_op_qemu_st_a64_i128:
592
+ case INDEX_op_qemu_st_i128:
593
tcg_out_qemu_ldst_i128(s, REG0(0), REG0(1), a2, args[3], false);
594
break;
595
596
@@ -XXX,XX +XXX,XX @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
597
case INDEX_op_movcond_i64:
598
return C_O1_I4(r, r, rC, rZ, rZ);
599
600
- case INDEX_op_qemu_ld_a32_i32:
601
- case INDEX_op_qemu_ld_a64_i32:
602
- case INDEX_op_qemu_ld_a32_i64:
603
- case INDEX_op_qemu_ld_a64_i64:
604
+ case INDEX_op_qemu_ld_i32:
605
+ case INDEX_op_qemu_ld_i64:
606
return C_O1_I1(r, r);
607
- case INDEX_op_qemu_ld_a32_i128:
608
- case INDEX_op_qemu_ld_a64_i128:
609
+ case INDEX_op_qemu_ld_i128:
610
return C_O2_I1(r, r, r);
611
- case INDEX_op_qemu_st_a32_i32:
612
- case INDEX_op_qemu_st_a64_i32:
613
- case INDEX_op_qemu_st_a32_i64:
614
- case INDEX_op_qemu_st_a64_i64:
615
+ case INDEX_op_qemu_st_i32:
616
+ case INDEX_op_qemu_st_i64:
617
return C_O0_I2(rZ, r);
618
- case INDEX_op_qemu_st_a32_i128:
619
- case INDEX_op_qemu_st_a64_i128:
620
+ case INDEX_op_qemu_st_i128:
621
return C_O0_I3(rZ, rZ, r);
622
623
case INDEX_op_deposit_i32:
624
diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
625
index XXXXXXX..XXXXXXX 100644
626
--- a/tcg/arm/tcg-target.c.inc
627
+++ b/tcg/arm/tcg-target.c.inc
628
@@ -XXX,XX +XXX,XX @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
629
ARITH_MOV, args[0], 0, 0);
630
break;
631
632
- case INDEX_op_qemu_ld_a32_i32:
633
+ case INDEX_op_qemu_ld_i32:
634
tcg_out_qemu_ld(s, args[0], -1, args[1], -1, args[2], TCG_TYPE_I32);
635
break;
636
- case INDEX_op_qemu_ld_a64_i32:
637
- tcg_out_qemu_ld(s, args[0], -1, args[1], args[2],
638
- args[3], TCG_TYPE_I32);
639
- break;
640
- case INDEX_op_qemu_ld_a32_i64:
641
+ case INDEX_op_qemu_ld_i64:
642
tcg_out_qemu_ld(s, args[0], args[1], args[2], -1,
643
args[3], TCG_TYPE_I64);
644
break;
645
- case INDEX_op_qemu_ld_a64_i64:
646
- tcg_out_qemu_ld(s, args[0], args[1], args[2], args[3],
647
- args[4], TCG_TYPE_I64);
648
- break;
649
650
- case INDEX_op_qemu_st_a32_i32:
651
+ case INDEX_op_qemu_st_i32:
652
tcg_out_qemu_st(s, args[0], -1, args[1], -1, args[2], TCG_TYPE_I32);
653
break;
654
- case INDEX_op_qemu_st_a64_i32:
655
- tcg_out_qemu_st(s, args[0], -1, args[1], args[2],
656
- args[3], TCG_TYPE_I32);
657
- break;
658
- case INDEX_op_qemu_st_a32_i64:
659
+ case INDEX_op_qemu_st_i64:
660
tcg_out_qemu_st(s, args[0], args[1], args[2], -1,
661
args[3], TCG_TYPE_I64);
662
break;
663
- case INDEX_op_qemu_st_a64_i64:
664
- tcg_out_qemu_st(s, args[0], args[1], args[2], args[3],
665
- args[4], TCG_TYPE_I64);
666
- break;
667
668
case INDEX_op_bswap16_i32:
669
tcg_out_bswap16(s, COND_AL, args[0], args[1], args[2]);
670
@@ -XXX,XX +XXX,XX @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
671
case INDEX_op_setcond2_i32:
672
return C_O1_I4(r, r, r, rI, rI);
673
674
- case INDEX_op_qemu_ld_a32_i32:
675
+ case INDEX_op_qemu_ld_i32:
676
return C_O1_I1(r, q);
677
- case INDEX_op_qemu_ld_a64_i32:
678
- return C_O1_I2(r, q, q);
679
- case INDEX_op_qemu_ld_a32_i64:
680
+ case INDEX_op_qemu_ld_i64:
681
return C_O2_I1(e, p, q);
682
- case INDEX_op_qemu_ld_a64_i64:
683
- return C_O2_I2(e, p, q, q);
684
- case INDEX_op_qemu_st_a32_i32:
685
+ case INDEX_op_qemu_st_i32:
686
return C_O0_I2(q, q);
687
- case INDEX_op_qemu_st_a64_i32:
688
- return C_O0_I3(q, q, q);
689
- case INDEX_op_qemu_st_a32_i64:
690
+ case INDEX_op_qemu_st_i64:
691
return C_O0_I3(Q, p, q);
692
- case INDEX_op_qemu_st_a64_i64:
693
- return C_O0_I4(Q, p, q, q);
694
695
case INDEX_op_st_vec:
696
return C_O0_I2(w, r);
697
diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
698
index XXXXXXX..XXXXXXX 100644
699
--- a/tcg/i386/tcg-target.c.inc
700
+++ b/tcg/i386/tcg-target.c.inc
701
@@ -XXX,XX +XXX,XX @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
702
tcg_out_modrm(s, OPC_GRP3_Ev + rexw, EXT3_NOT, a0);
703
break;
704
705
- case INDEX_op_qemu_ld_a64_i32:
706
- if (TCG_TARGET_REG_BITS == 32) {
707
- tcg_out_qemu_ld(s, a0, -1, a1, a2, args[3], TCG_TYPE_I32);
708
- break;
709
- }
710
- /* fall through */
711
- case INDEX_op_qemu_ld_a32_i32:
712
+ case INDEX_op_qemu_ld_i32:
713
tcg_out_qemu_ld(s, a0, -1, a1, -1, a2, TCG_TYPE_I32);
714
break;
715
- case INDEX_op_qemu_ld_a32_i64:
716
+ case INDEX_op_qemu_ld_i64:
717
if (TCG_TARGET_REG_BITS == 64) {
718
tcg_out_qemu_ld(s, a0, -1, a1, -1, a2, TCG_TYPE_I64);
719
} else {
720
tcg_out_qemu_ld(s, a0, a1, a2, -1, args[3], TCG_TYPE_I64);
721
}
722
break;
723
- case INDEX_op_qemu_ld_a64_i64:
724
- if (TCG_TARGET_REG_BITS == 64) {
725
- tcg_out_qemu_ld(s, a0, -1, a1, -1, a2, TCG_TYPE_I64);
726
- } else {
727
- tcg_out_qemu_ld(s, a0, a1, a2, args[3], args[4], TCG_TYPE_I64);
728
- }
729
- break;
730
- case INDEX_op_qemu_ld_a32_i128:
731
- case INDEX_op_qemu_ld_a64_i128:
732
+ case INDEX_op_qemu_ld_i128:
733
tcg_debug_assert(TCG_TARGET_REG_BITS == 64);
734
tcg_out_qemu_ld(s, a0, a1, a2, -1, args[3], TCG_TYPE_I128);
735
break;
736
737
- case INDEX_op_qemu_st_a64_i32:
738
- case INDEX_op_qemu_st8_a64_i32:
739
- if (TCG_TARGET_REG_BITS == 32) {
740
- tcg_out_qemu_st(s, a0, -1, a1, a2, args[3], TCG_TYPE_I32);
741
- break;
742
- }
743
- /* fall through */
744
- case INDEX_op_qemu_st_a32_i32:
745
- case INDEX_op_qemu_st8_a32_i32:
746
+ case INDEX_op_qemu_st_i32:
747
+ case INDEX_op_qemu_st8_i32:
748
tcg_out_qemu_st(s, a0, -1, a1, -1, a2, TCG_TYPE_I32);
749
break;
750
- case INDEX_op_qemu_st_a32_i64:
751
+ case INDEX_op_qemu_st_i64:
752
if (TCG_TARGET_REG_BITS == 64) {
753
tcg_out_qemu_st(s, a0, -1, a1, -1, a2, TCG_TYPE_I64);
754
} else {
755
tcg_out_qemu_st(s, a0, a1, a2, -1, args[3], TCG_TYPE_I64);
756
}
757
break;
758
- case INDEX_op_qemu_st_a64_i64:
759
- if (TCG_TARGET_REG_BITS == 64) {
760
- tcg_out_qemu_st(s, a0, -1, a1, -1, a2, TCG_TYPE_I64);
761
- } else {
762
- tcg_out_qemu_st(s, a0, a1, a2, args[3], args[4], TCG_TYPE_I64);
763
- }
764
- break;
765
- case INDEX_op_qemu_st_a32_i128:
766
- case INDEX_op_qemu_st_a64_i128:
767
+ case INDEX_op_qemu_st_i128:
768
tcg_debug_assert(TCG_TARGET_REG_BITS == 64);
769
tcg_out_qemu_st(s, a0, a1, a2, -1, args[3], TCG_TYPE_I128);
770
break;
771
@@ -XXX,XX +XXX,XX @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
772
case INDEX_op_clz_i64:
773
return have_lzcnt ? C_N1_I2(r, r, rW) : C_N1_I2(r, r, r);
774
775
- case INDEX_op_qemu_ld_a32_i32:
776
+ case INDEX_op_qemu_ld_i32:
777
return C_O1_I1(r, L);
778
- case INDEX_op_qemu_ld_a64_i32:
779
- return TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, L) : C_O1_I2(r, L, L);
780
781
- case INDEX_op_qemu_st_a32_i32:
782
+ case INDEX_op_qemu_st_i32:
783
return C_O0_I2(L, L);
784
- case INDEX_op_qemu_st_a64_i32:
785
- return TCG_TARGET_REG_BITS == 64 ? C_O0_I2(L, L) : C_O0_I3(L, L, L);
786
- case INDEX_op_qemu_st8_a32_i32:
787
+ case INDEX_op_qemu_st8_i32:
788
return C_O0_I2(s, L);
789
- case INDEX_op_qemu_st8_a64_i32:
790
- return TCG_TARGET_REG_BITS == 64 ? C_O0_I2(s, L) : C_O0_I3(s, L, L);
791
792
- case INDEX_op_qemu_ld_a32_i64:
793
+ case INDEX_op_qemu_ld_i64:
794
return TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, L) : C_O2_I1(r, r, L);
795
- case INDEX_op_qemu_ld_a64_i64:
796
- return TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, L) : C_O2_I2(r, r, L, L);
797
798
- case INDEX_op_qemu_st_a32_i64:
799
+ case INDEX_op_qemu_st_i64:
800
return TCG_TARGET_REG_BITS == 64 ? C_O0_I2(L, L) : C_O0_I3(L, L, L);
801
- case INDEX_op_qemu_st_a64_i64:
802
- return TCG_TARGET_REG_BITS == 64 ? C_O0_I2(L, L) : C_O0_I4(L, L, L, L);
803
804
- case INDEX_op_qemu_ld_a32_i128:
805
- case INDEX_op_qemu_ld_a64_i128:
806
+ case INDEX_op_qemu_ld_i128:
807
tcg_debug_assert(TCG_TARGET_REG_BITS == 64);
808
return C_O2_I1(r, r, L);
809
- case INDEX_op_qemu_st_a32_i128:
810
- case INDEX_op_qemu_st_a64_i128:
811
+ case INDEX_op_qemu_st_i128:
812
tcg_debug_assert(TCG_TARGET_REG_BITS == 64);
813
return C_O0_I3(L, L, L);
814
815
diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc
816
index XXXXXXX..XXXXXXX 100644
817
--- a/tcg/loongarch64/tcg-target.c.inc
818
+++ b/tcg/loongarch64/tcg-target.c.inc
819
@@ -XXX,XX +XXX,XX @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
820
tcg_out_ldst(s, OPC_ST_D, a0, a1, a2);
821
break;
822
823
- case INDEX_op_qemu_ld_a32_i32:
824
- case INDEX_op_qemu_ld_a64_i32:
825
+ case INDEX_op_qemu_ld_i32:
826
tcg_out_qemu_ld(s, a0, a1, a2, TCG_TYPE_I32);
827
break;
828
- case INDEX_op_qemu_ld_a32_i64:
829
- case INDEX_op_qemu_ld_a64_i64:
830
+ case INDEX_op_qemu_ld_i64:
831
tcg_out_qemu_ld(s, a0, a1, a2, TCG_TYPE_I64);
832
break;
833
- case INDEX_op_qemu_ld_a32_i128:
834
- case INDEX_op_qemu_ld_a64_i128:
835
+ case INDEX_op_qemu_ld_i128:
836
tcg_out_qemu_ldst_i128(s, a0, a1, a2, a3, true);
837
break;
838
- case INDEX_op_qemu_st_a32_i32:
839
- case INDEX_op_qemu_st_a64_i32:
840
+ case INDEX_op_qemu_st_i32:
841
tcg_out_qemu_st(s, a0, a1, a2, TCG_TYPE_I32);
842
break;
843
- case INDEX_op_qemu_st_a32_i64:
844
- case INDEX_op_qemu_st_a64_i64:
845
+ case INDEX_op_qemu_st_i64:
846
tcg_out_qemu_st(s, a0, a1, a2, TCG_TYPE_I64);
847
break;
848
- case INDEX_op_qemu_st_a32_i128:
849
- case INDEX_op_qemu_st_a64_i128:
850
+ case INDEX_op_qemu_st_i128:
851
tcg_out_qemu_ldst_i128(s, a0, a1, a2, a3, false);
852
break;
853
854
@@ -XXX,XX +XXX,XX @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
855
case INDEX_op_st32_i64:
856
case INDEX_op_st_i32:
857
case INDEX_op_st_i64:
858
- case INDEX_op_qemu_st_a32_i32:
859
- case INDEX_op_qemu_st_a64_i32:
860
- case INDEX_op_qemu_st_a32_i64:
861
- case INDEX_op_qemu_st_a64_i64:
862
+ case INDEX_op_qemu_st_i32:
863
+ case INDEX_op_qemu_st_i64:
864
return C_O0_I2(rZ, r);
865
866
- case INDEX_op_qemu_ld_a32_i128:
867
- case INDEX_op_qemu_ld_a64_i128:
868
+ case INDEX_op_qemu_ld_i128:
869
return C_N2_I1(r, r, r);
870
871
- case INDEX_op_qemu_st_a32_i128:
872
- case INDEX_op_qemu_st_a64_i128:
873
+ case INDEX_op_qemu_st_i128:
874
return C_O0_I3(r, r, r);
875
876
case INDEX_op_brcond_i32:
877
@@ -XXX,XX +XXX,XX @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
878
case INDEX_op_ld32u_i64:
879
case INDEX_op_ld_i32:
880
case INDEX_op_ld_i64:
881
- case INDEX_op_qemu_ld_a32_i32:
882
- case INDEX_op_qemu_ld_a64_i32:
883
- case INDEX_op_qemu_ld_a32_i64:
884
- case INDEX_op_qemu_ld_a64_i64:
885
+ case INDEX_op_qemu_ld_i32:
886
+ case INDEX_op_qemu_ld_i64:
887
return C_O1_I1(r, r);
888
889
case INDEX_op_andc_i32:
890
diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc
891
index XXXXXXX..XXXXXXX 100644
892
--- a/tcg/mips/tcg-target.c.inc
893
+++ b/tcg/mips/tcg-target.c.inc
894
@@ -XXX,XX +XXX,XX @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
895
tcg_out_setcond2(s, args[5], a0, a1, a2, args[3], args[4]);
896
break;
897
898
- case INDEX_op_qemu_ld_a64_i32:
899
- if (TCG_TARGET_REG_BITS == 32) {
900
- tcg_out_qemu_ld(s, a0, 0, a1, a2, args[3], TCG_TYPE_I32);
901
- break;
902
- }
903
- /* fall through */
904
- case INDEX_op_qemu_ld_a32_i32:
905
+ case INDEX_op_qemu_ld_i32:
906
tcg_out_qemu_ld(s, a0, 0, a1, 0, a2, TCG_TYPE_I32);
907
break;
908
- case INDEX_op_qemu_ld_a32_i64:
909
+ case INDEX_op_qemu_ld_i64:
910
if (TCG_TARGET_REG_BITS == 64) {
911
tcg_out_qemu_ld(s, a0, 0, a1, 0, a2, TCG_TYPE_I64);
912
} else {
913
tcg_out_qemu_ld(s, a0, a1, a2, 0, args[3], TCG_TYPE_I64);
914
}
915
break;
916
- case INDEX_op_qemu_ld_a64_i64:
917
- if (TCG_TARGET_REG_BITS == 64) {
918
- tcg_out_qemu_ld(s, a0, 0, a1, 0, a2, TCG_TYPE_I64);
919
- } else {
920
- tcg_out_qemu_ld(s, a0, a1, a2, args[3], args[4], TCG_TYPE_I64);
921
- }
922
- break;
923
924
- case INDEX_op_qemu_st_a64_i32:
925
- if (TCG_TARGET_REG_BITS == 32) {
926
- tcg_out_qemu_st(s, a0, 0, a1, a2, args[3], TCG_TYPE_I32);
927
- break;
928
- }
929
- /* fall through */
930
- case INDEX_op_qemu_st_a32_i32:
931
+ case INDEX_op_qemu_st_i32:
932
tcg_out_qemu_st(s, a0, 0, a1, 0, a2, TCG_TYPE_I32);
933
break;
934
- case INDEX_op_qemu_st_a32_i64:
935
+ case INDEX_op_qemu_st_i64:
936
if (TCG_TARGET_REG_BITS == 64) {
937
tcg_out_qemu_st(s, a0, 0, a1, 0, a2, TCG_TYPE_I64);
938
} else {
939
tcg_out_qemu_st(s, a0, a1, a2, 0, args[3], TCG_TYPE_I64);
940
}
941
break;
942
- case INDEX_op_qemu_st_a64_i64:
943
- if (TCG_TARGET_REG_BITS == 64) {
944
- tcg_out_qemu_st(s, a0, 0, a1, 0, a2, TCG_TYPE_I64);
945
- } else {
946
- tcg_out_qemu_st(s, a0, a1, a2, args[3], args[4], TCG_TYPE_I64);
947
- }
948
- break;
949
950
case INDEX_op_add2_i32:
951
tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5],
952
@@ -XXX,XX +XXX,XX @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
953
case INDEX_op_brcond2_i32:
954
return C_O0_I4(rZ, rZ, rZ, rZ);
955
956
- case INDEX_op_qemu_ld_a32_i32:
957
+ case INDEX_op_qemu_ld_i32:
958
return C_O1_I1(r, r);
959
- case INDEX_op_qemu_ld_a64_i32:
960
- return TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, r) : C_O1_I2(r, r, r);
961
- case INDEX_op_qemu_st_a32_i32:
962
+ case INDEX_op_qemu_st_i32:
963
return C_O0_I2(rZ, r);
964
- case INDEX_op_qemu_st_a64_i32:
965
- return TCG_TARGET_REG_BITS == 64 ? C_O0_I2(rZ, r) : C_O0_I3(rZ, r, r);
966
- case INDEX_op_qemu_ld_a32_i64:
967
+ case INDEX_op_qemu_ld_i64:
968
return TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, r) : C_O2_I1(r, r, r);
969
- case INDEX_op_qemu_ld_a64_i64:
970
- return TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, r) : C_O2_I2(r, r, r, r);
971
- case INDEX_op_qemu_st_a32_i64:
972
+ case INDEX_op_qemu_st_i64:
973
return TCG_TARGET_REG_BITS == 64 ? C_O0_I2(rZ, r) : C_O0_I3(rZ, rZ, r);
974
- case INDEX_op_qemu_st_a64_i64:
975
- return (TCG_TARGET_REG_BITS == 64 ? C_O0_I2(rZ, r)
976
- : C_O0_I4(rZ, rZ, r, r));
977
978
default:
979
return C_NotImplemented;
980
diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc
981
index XXXXXXX..XXXXXXX 100644
982
--- a/tcg/ppc/tcg-target.c.inc
983
+++ b/tcg/ppc/tcg-target.c.inc
984
@@ -XXX,XX +XXX,XX @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
985
tcg_out32(s, MODUD | TAB(args[0], args[1], args[2]));
986
break;
987
988
- case INDEX_op_qemu_ld_a64_i32:
989
- if (TCG_TARGET_REG_BITS == 32) {
990
- tcg_out_qemu_ld(s, args[0], -1, args[1], args[2],
991
- args[3], TCG_TYPE_I32);
992
- break;
993
- }
994
- /* fall through */
995
- case INDEX_op_qemu_ld_a32_i32:
996
+ case INDEX_op_qemu_ld_i32:
997
tcg_out_qemu_ld(s, args[0], -1, args[1], -1, args[2], TCG_TYPE_I32);
998
break;
999
- case INDEX_op_qemu_ld_a32_i64:
1000
+ case INDEX_op_qemu_ld_i64:
1001
if (TCG_TARGET_REG_BITS == 64) {
1002
tcg_out_qemu_ld(s, args[0], -1, args[1], -1,
1003
args[2], TCG_TYPE_I64);
1004
@@ -XXX,XX +XXX,XX @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
1005
args[3], TCG_TYPE_I64);
1006
}
1007
break;
1008
- case INDEX_op_qemu_ld_a64_i64:
1009
- if (TCG_TARGET_REG_BITS == 64) {
1010
- tcg_out_qemu_ld(s, args[0], -1, args[1], -1,
1011
- args[2], TCG_TYPE_I64);
1012
- } else {
1013
- tcg_out_qemu_ld(s, args[0], args[1], args[2], args[3],
1014
- args[4], TCG_TYPE_I64);
1015
- }
1016
- break;
1017
- case INDEX_op_qemu_ld_a32_i128:
1018
- case INDEX_op_qemu_ld_a64_i128:
1019
+ case INDEX_op_qemu_ld_i128:
1020
tcg_debug_assert(TCG_TARGET_REG_BITS == 64);
1021
tcg_out_qemu_ldst_i128(s, args[0], args[1], args[2], args[3], true);
1022
break;
1023
1024
- case INDEX_op_qemu_st_a64_i32:
1025
- if (TCG_TARGET_REG_BITS == 32) {
1026
- tcg_out_qemu_st(s, args[0], -1, args[1], args[2],
1027
- args[3], TCG_TYPE_I32);
1028
- break;
1029
- }
1030
- /* fall through */
1031
- case INDEX_op_qemu_st_a32_i32:
1032
+ case INDEX_op_qemu_st_i32:
1033
tcg_out_qemu_st(s, args[0], -1, args[1], -1, args[2], TCG_TYPE_I32);
1034
break;
1035
- case INDEX_op_qemu_st_a32_i64:
1036
+ case INDEX_op_qemu_st_i64:
1037
if (TCG_TARGET_REG_BITS == 64) {
1038
tcg_out_qemu_st(s, args[0], -1, args[1], -1,
1039
args[2], TCG_TYPE_I64);
1040
@@ -XXX,XX +XXX,XX @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
1041
args[3], TCG_TYPE_I64);
1042
}
1043
break;
1044
- case INDEX_op_qemu_st_a64_i64:
1045
- if (TCG_TARGET_REG_BITS == 64) {
1046
- tcg_out_qemu_st(s, args[0], -1, args[1], -1,
1047
- args[2], TCG_TYPE_I64);
1048
- } else {
1049
- tcg_out_qemu_st(s, args[0], args[1], args[2], args[3],
1050
- args[4], TCG_TYPE_I64);
1051
- }
1052
- break;
1053
- case INDEX_op_qemu_st_a32_i128:
1054
- case INDEX_op_qemu_st_a64_i128:
1055
+ case INDEX_op_qemu_st_i128:
1056
tcg_debug_assert(TCG_TARGET_REG_BITS == 64);
1057
tcg_out_qemu_ldst_i128(s, args[0], args[1], args[2], args[3], false);
1058
break;
1059
@@ -XXX,XX +XXX,XX @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
1060
case INDEX_op_sub2_i32:
1061
return C_O2_I4(r, r, rI, rZM, r, r);
1062
1063
- case INDEX_op_qemu_ld_a32_i32:
1064
+ case INDEX_op_qemu_ld_i32:
1065
return C_O1_I1(r, r);
1066
- case INDEX_op_qemu_ld_a64_i32:
1067
- return TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, r) : C_O1_I2(r, r, r);
1068
- case INDEX_op_qemu_ld_a32_i64:
1069
+ case INDEX_op_qemu_ld_i64:
1070
return TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, r) : C_O2_I1(r, r, r);
1071
- case INDEX_op_qemu_ld_a64_i64:
1072
- return TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, r) : C_O2_I2(r, r, r, r);
1073
1074
- case INDEX_op_qemu_st_a32_i32:
1075
+ case INDEX_op_qemu_st_i32:
1076
return C_O0_I2(r, r);
1077
- case INDEX_op_qemu_st_a64_i32:
1078
+ case INDEX_op_qemu_st_i64:
1079
return TCG_TARGET_REG_BITS == 64 ? C_O0_I2(r, r) : C_O0_I3(r, r, r);
1080
- case INDEX_op_qemu_st_a32_i64:
1081
- return TCG_TARGET_REG_BITS == 64 ? C_O0_I2(r, r) : C_O0_I3(r, r, r);
1082
- case INDEX_op_qemu_st_a64_i64:
1083
- return TCG_TARGET_REG_BITS == 64 ? C_O0_I2(r, r) : C_O0_I4(r, r, r, r);
1084
1085
- case INDEX_op_qemu_ld_a32_i128:
1086
- case INDEX_op_qemu_ld_a64_i128:
1087
+ case INDEX_op_qemu_ld_i128:
1088
return C_N1O1_I1(o, m, r);
1089
- case INDEX_op_qemu_st_a32_i128:
1090
- case INDEX_op_qemu_st_a64_i128:
1091
+ case INDEX_op_qemu_st_i128:
1092
return C_O0_I3(o, m, r);
1093
1094
case INDEX_op_add_vec:
1095
diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
1096
index XXXXXXX..XXXXXXX 100644
1097
--- a/tcg/riscv/tcg-target.c.inc
1098
+++ b/tcg/riscv/tcg-target.c.inc
1099
@@ -XXX,XX +XXX,XX @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
1100
args[3], const_args[3], args[4], const_args[4]);
1101
break;
1102
1103
- case INDEX_op_qemu_ld_a32_i32:
1104
- case INDEX_op_qemu_ld_a64_i32:
1105
+ case INDEX_op_qemu_ld_i32:
1106
tcg_out_qemu_ld(s, a0, a1, a2, TCG_TYPE_I32);
1107
break;
1108
- case INDEX_op_qemu_ld_a32_i64:
1109
- case INDEX_op_qemu_ld_a64_i64:
1110
+ case INDEX_op_qemu_ld_i64:
1111
tcg_out_qemu_ld(s, a0, a1, a2, TCG_TYPE_I64);
1112
break;
1113
- case INDEX_op_qemu_st_a32_i32:
1114
- case INDEX_op_qemu_st_a64_i32:
1115
+ case INDEX_op_qemu_st_i32:
1116
tcg_out_qemu_st(s, a0, a1, a2, TCG_TYPE_I32);
1117
break;
1118
- case INDEX_op_qemu_st_a32_i64:
1119
- case INDEX_op_qemu_st_a64_i64:
1120
+ case INDEX_op_qemu_st_i64:
1121
tcg_out_qemu_st(s, a0, a1, a2, TCG_TYPE_I64);
1122
break;
1123
1124
@@ -XXX,XX +XXX,XX @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
1125
case INDEX_op_sub2_i64:
1126
return C_O2_I4(r, r, rZ, rZ, rM, rM);
1127
1128
- case INDEX_op_qemu_ld_a32_i32:
1129
- case INDEX_op_qemu_ld_a64_i32:
1130
- case INDEX_op_qemu_ld_a32_i64:
1131
- case INDEX_op_qemu_ld_a64_i64:
1132
+ case INDEX_op_qemu_ld_i32:
1133
+ case INDEX_op_qemu_ld_i64:
1134
return C_O1_I1(r, r);
1135
- case INDEX_op_qemu_st_a32_i32:
1136
- case INDEX_op_qemu_st_a64_i32:
1137
- case INDEX_op_qemu_st_a32_i64:
1138
- case INDEX_op_qemu_st_a64_i64:
1139
+ case INDEX_op_qemu_st_i32:
1140
+ case INDEX_op_qemu_st_i64:
1141
return C_O0_I2(rZ, r);
1142
1143
case INDEX_op_st_vec:
1144
diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc
1145
index XXXXXXX..XXXXXXX 100644
1146
--- a/tcg/s390x/tcg-target.c.inc
1147
+++ b/tcg/s390x/tcg-target.c.inc
1148
@@ -XXX,XX +XXX,XX @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
1149
args[2], const_args[2], args[3], const_args[3], args[4]);
1150
break;
1151
1152
- case INDEX_op_qemu_ld_a32_i32:
1153
- case INDEX_op_qemu_ld_a64_i32:
1154
+ case INDEX_op_qemu_ld_i32:
1155
tcg_out_qemu_ld(s, args[0], args[1], args[2], TCG_TYPE_I32);
1156
break;
1157
- case INDEX_op_qemu_ld_a32_i64:
1158
- case INDEX_op_qemu_ld_a64_i64:
1159
+ case INDEX_op_qemu_ld_i64:
1160
tcg_out_qemu_ld(s, args[0], args[1], args[2], TCG_TYPE_I64);
1161
break;
1162
- case INDEX_op_qemu_st_a32_i32:
1163
- case INDEX_op_qemu_st_a64_i32:
1164
+ case INDEX_op_qemu_st_i32:
1165
tcg_out_qemu_st(s, args[0], args[1], args[2], TCG_TYPE_I32);
1166
break;
1167
- case INDEX_op_qemu_st_a32_i64:
1168
- case INDEX_op_qemu_st_a64_i64:
1169
+ case INDEX_op_qemu_st_i64:
1170
tcg_out_qemu_st(s, args[0], args[1], args[2], TCG_TYPE_I64);
1171
break;
1172
- case INDEX_op_qemu_ld_a32_i128:
1173
- case INDEX_op_qemu_ld_a64_i128:
1174
+ case INDEX_op_qemu_ld_i128:
1175
tcg_out_qemu_ldst_i128(s, args[0], args[1], args[2], args[3], true);
1176
break;
1177
- case INDEX_op_qemu_st_a32_i128:
1178
- case INDEX_op_qemu_st_a64_i128:
1179
+ case INDEX_op_qemu_st_i128:
1180
tcg_out_qemu_ldst_i128(s, args[0], args[1], args[2], args[3], false);
1181
break;
1182
1183
@@ -XXX,XX +XXX,XX @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
1184
case INDEX_op_ctpop_i64:
1185
return C_O1_I1(r, r);
1186
1187
- case INDEX_op_qemu_ld_a32_i32:
1188
- case INDEX_op_qemu_ld_a64_i32:
1189
- case INDEX_op_qemu_ld_a32_i64:
1190
- case INDEX_op_qemu_ld_a64_i64:
1191
+ case INDEX_op_qemu_ld_i32:
1192
+ case INDEX_op_qemu_ld_i64:
1193
return C_O1_I1(r, r);
1194
- case INDEX_op_qemu_st_a32_i64:
1195
- case INDEX_op_qemu_st_a64_i64:
1196
- case INDEX_op_qemu_st_a32_i32:
1197
- case INDEX_op_qemu_st_a64_i32:
1198
+ case INDEX_op_qemu_st_i64:
1199
+ case INDEX_op_qemu_st_i32:
1200
return C_O0_I2(r, r);
1201
- case INDEX_op_qemu_ld_a32_i128:
1202
- case INDEX_op_qemu_ld_a64_i128:
1203
+ case INDEX_op_qemu_ld_i128:
1204
return C_O2_I1(o, m, r);
1205
- case INDEX_op_qemu_st_a32_i128:
1206
- case INDEX_op_qemu_st_a64_i128:
1207
+ case INDEX_op_qemu_st_i128:
1208
return C_O0_I3(o, m, r);
1209
1210
case INDEX_op_deposit_i32:
1211
diff --git a/tcg/sparc64/tcg-target.c.inc b/tcg/sparc64/tcg-target.c.inc
1212
index XXXXXXX..XXXXXXX 100644
1213
--- a/tcg/sparc64/tcg-target.c.inc
1214
+++ b/tcg/sparc64/tcg-target.c.inc
1215
@@ -XXX,XX +XXX,XX @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
1216
tcg_out_arithi(s, a1, a0, 32, SHIFT_SRLX);
1217
break;
1218
1219
- case INDEX_op_qemu_ld_a32_i32:
1220
- case INDEX_op_qemu_ld_a64_i32:
1221
+ case INDEX_op_qemu_ld_i32:
1222
tcg_out_qemu_ld(s, a0, a1, a2, TCG_TYPE_I32);
1223
break;
1224
- case INDEX_op_qemu_ld_a32_i64:
1225
- case INDEX_op_qemu_ld_a64_i64:
1226
+ case INDEX_op_qemu_ld_i64:
1227
tcg_out_qemu_ld(s, a0, a1, a2, TCG_TYPE_I64);
1228
break;
1229
- case INDEX_op_qemu_st_a32_i32:
1230
- case INDEX_op_qemu_st_a64_i32:
1231
+ case INDEX_op_qemu_st_i32:
1232
tcg_out_qemu_st(s, a0, a1, a2, TCG_TYPE_I32);
1233
break;
1234
- case INDEX_op_qemu_st_a32_i64:
1235
- case INDEX_op_qemu_st_a64_i64:
1236
+ case INDEX_op_qemu_st_i64:
1237
tcg_out_qemu_st(s, a0, a1, a2, TCG_TYPE_I64);
1238
break;
1239
1240
@@ -XXX,XX +XXX,XX @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
1241
case INDEX_op_extu_i32_i64:
1242
case INDEX_op_extract_i64:
1243
case INDEX_op_sextract_i64:
1244
- case INDEX_op_qemu_ld_a32_i32:
1245
- case INDEX_op_qemu_ld_a64_i32:
1246
- case INDEX_op_qemu_ld_a32_i64:
1247
- case INDEX_op_qemu_ld_a64_i64:
1248
+ case INDEX_op_qemu_ld_i32:
1249
+ case INDEX_op_qemu_ld_i64:
1250
return C_O1_I1(r, r);
1251
1252
case INDEX_op_st8_i32:
1253
@@ -XXX,XX +XXX,XX @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
1254
case INDEX_op_st_i32:
1255
case INDEX_op_st32_i64:
1256
case INDEX_op_st_i64:
1257
- case INDEX_op_qemu_st_a32_i32:
1258
- case INDEX_op_qemu_st_a64_i32:
1259
- case INDEX_op_qemu_st_a32_i64:
1260
- case INDEX_op_qemu_st_a64_i64:
1261
+ case INDEX_op_qemu_st_i32:
1262
+ case INDEX_op_qemu_st_i64:
1263
return C_O0_I2(rZ, r);
1264
1265
case INDEX_op_add_i32:
1266
diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
1267
index XXXXXXX..XXXXXXX 100644
1268
--- a/tcg/tci/tcg-target.c.inc
1269
+++ b/tcg/tci/tcg-target.c.inc
1270
@@ -XXX,XX +XXX,XX @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
1271
case INDEX_op_setcond2_i32:
1272
return C_O1_I4(r, r, r, r, r);
1273
1274
- case INDEX_op_qemu_ld_a32_i32:
1275
+ case INDEX_op_qemu_ld_i32:
1276
return C_O1_I1(r, r);
1277
- case INDEX_op_qemu_ld_a64_i32:
1278
- return TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, r) : C_O1_I2(r, r, r);
1279
- case INDEX_op_qemu_ld_a32_i64:
1280
+ case INDEX_op_qemu_ld_i64:
1281
return TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, r) : C_O2_I1(r, r, r);
1282
- case INDEX_op_qemu_ld_a64_i64:
1283
- return TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, r) : C_O2_I2(r, r, r, r);
1284
- case INDEX_op_qemu_st_a32_i32:
1285
+ case INDEX_op_qemu_st_i32:
1286
return C_O0_I2(r, r);
1287
- case INDEX_op_qemu_st_a64_i32:
1288
+ case INDEX_op_qemu_st_i64:
1289
return TCG_TARGET_REG_BITS == 64 ? C_O0_I2(r, r) : C_O0_I3(r, r, r);
1290
- case INDEX_op_qemu_st_a32_i64:
1291
- return TCG_TARGET_REG_BITS == 64 ? C_O0_I2(r, r) : C_O0_I3(r, r, r);
1292
- case INDEX_op_qemu_st_a64_i64:
1293
- return TCG_TARGET_REG_BITS == 64 ? C_O0_I2(r, r) : C_O0_I4(r, r, r, r);
1294
1295
default:
1296
return C_NotImplemented;
1297
@@ -XXX,XX +XXX,XX @@ static void tcg_out_op_rrrbb(TCGContext *s, TCGOpcode op, TCGReg r0,
1298
tcg_out32(s, insn);
1299
}
1300
1301
-static void tcg_out_op_rrrrr(TCGContext *s, TCGOpcode op, TCGReg r0,
1302
- TCGReg r1, TCGReg r2, TCGReg r3, TCGReg r4)
1303
-{
1304
- tcg_insn_unit insn = 0;
1305
-
1306
- insn = deposit32(insn, 0, 8, op);
1307
- insn = deposit32(insn, 8, 4, r0);
1308
- insn = deposit32(insn, 12, 4, r1);
1309
- insn = deposit32(insn, 16, 4, r2);
1310
- insn = deposit32(insn, 20, 4, r3);
1311
- insn = deposit32(insn, 24, 4, r4);
1312
- tcg_out32(s, insn);
1313
-}
1314
-
1315
static void tcg_out_op_rrrr(TCGContext *s, TCGOpcode op,
1316
TCGReg r0, TCGReg r1, TCGReg r2, TCGReg r3)
1317
{
1318
@@ -XXX,XX +XXX,XX @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
1319
tcg_out_op_rrrr(s, opc, args[0], args[1], args[2], args[3]);
1320
break;
1321
1322
- case INDEX_op_qemu_ld_a32_i32:
1323
- case INDEX_op_qemu_st_a32_i32:
1324
- tcg_out_op_rrm(s, opc, args[0], args[1], args[2]);
1325
- break;
1326
- case INDEX_op_qemu_ld_a64_i32:
1327
- case INDEX_op_qemu_st_a64_i32:
1328
- case INDEX_op_qemu_ld_a32_i64:
1329
- case INDEX_op_qemu_st_a32_i64:
1330
- if (TCG_TARGET_REG_BITS == 64) {
1331
- tcg_out_op_rrm(s, opc, args[0], args[1], args[2]);
1332
- } else {
1333
+ case INDEX_op_qemu_ld_i64:
1334
+ case INDEX_op_qemu_st_i64:
1335
+ if (TCG_TARGET_REG_BITS == 32) {
1336
tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_TMP, args[3]);
1337
tcg_out_op_rrrr(s, opc, args[0], args[1], args[2], TCG_REG_TMP);
1338
+ break;
1339
}
1340
- break;
1341
- case INDEX_op_qemu_ld_a64_i64:
1342
- case INDEX_op_qemu_st_a64_i64:
1343
- if (TCG_TARGET_REG_BITS == 64) {
1344
- tcg_out_op_rrm(s, opc, args[0], args[1], args[2]);
1345
+ /* fall through */
1346
+ case INDEX_op_qemu_ld_i32:
1347
+ case INDEX_op_qemu_st_i32:
1348
+ if (TCG_TARGET_REG_BITS == 64 && s->addr_type == TCG_TYPE_I32) {
1349
+ tcg_out_ext32u(s, TCG_REG_TMP, args[1]);
1350
+ tcg_out_op_rrm(s, opc, args[0], TCG_REG_TMP, args[2]);
1351
} else {
1352
- tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_TMP, args[4]);
1353
- tcg_out_op_rrrrr(s, opc, args[0], args[1],
1354
- args[2], args[3], TCG_REG_TMP);
1355
+ tcg_out_op_rrm(s, opc, args[0], args[1], args[2]);
1356
}
1357
break;
1358
1359
--
1360
2.43.0
diff view generated by jsdifflib
New patch
[PULL 05/24] tcg/arm: Drop addrhi from prepare_host_addr
1
The guest address will now always be TCG_TYPE_I32.
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
---
5
tcg/arm/tcg-target.c.inc | 63 ++++++++++++++--------------------------
6
1 file changed, 21 insertions(+), 42 deletions(-)
7
8
diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
9
index XXXXXXX..XXXXXXX 100644
10
--- a/tcg/arm/tcg-target.c.inc
11
+++ b/tcg/arm/tcg-target.c.inc
12
@@ -XXX,XX +XXX,XX @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
13
#define MIN_TLB_MASK_TABLE_OFS -256
14
15
static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
16
- TCGReg addrlo, TCGReg addrhi,
17
- MemOpIdx oi, bool is_ld)
18
+ TCGReg addr, MemOpIdx oi, bool is_ld)
19
{
20
TCGLabelQemuLdst *ldst = NULL;
21
MemOp opc = get_memop(oi);
22
@@ -XXX,XX +XXX,XX @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
23
if (tcg_use_softmmu) {
24
*h = (HostAddress){
25
.cond = COND_AL,
26
- .base = addrlo,
27
+ .base = addr,
28
.index = TCG_REG_R1,
29
.index_scratch = true,
30
};
31
} else {
32
*h = (HostAddress){
33
.cond = COND_AL,
34
- .base = addrlo,
35
+ .base = addr,
36
.index = guest_base ? TCG_REG_GUEST_BASE : -1,
37
.index_scratch = false,
38
};
39
@@ -XXX,XX +XXX,XX @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
40
ldst = new_ldst_label(s);
41
ldst->is_ld = is_ld;
42
ldst->oi = oi;
43
- ldst->addrlo_reg = addrlo;
44
- ldst->addrhi_reg = addrhi;
45
+ ldst->addrlo_reg = addr;
46
47
/* Load cpu->neg.tlb.f[mmu_idx].{mask,table} into {r0,r1}. */
48
QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, mask) != 0);
49
@@ -XXX,XX +XXX,XX @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
50
tcg_out_ldrd_8(s, COND_AL, TCG_REG_R0, TCG_AREG0, fast_off);
51
52
/* Extract the tlb index from the address into R0. */
53
- tcg_out_dat_reg(s, COND_AL, ARITH_AND, TCG_REG_R0, TCG_REG_R0, addrlo,
54
+ tcg_out_dat_reg(s, COND_AL, ARITH_AND, TCG_REG_R0, TCG_REG_R0, addr,
55
SHIFT_IMM_LSR(s->page_bits - CPU_TLB_ENTRY_BITS));
56
57
/*
58
* Add the tlb_table pointer, creating the CPUTLBEntry address in R1.
59
- * Load the tlb comparator into R2/R3 and the fast path addend into R1.
60
+ * Load the tlb comparator into R2 and the fast path addend into R1.
61
*/
62
QEMU_BUILD_BUG_ON(HOST_BIG_ENDIAN);
63
if (cmp_off == 0) {
64
- if (s->addr_type == TCG_TYPE_I32) {
65
- tcg_out_ld32_rwb(s, COND_AL, TCG_REG_R2,
66
- TCG_REG_R1, TCG_REG_R0);
67
- } else {
68
- tcg_out_ldrd_rwb(s, COND_AL, TCG_REG_R2,
69
- TCG_REG_R1, TCG_REG_R0);
70
- }
71
+ tcg_out_ld32_rwb(s, COND_AL, TCG_REG_R2, TCG_REG_R1, TCG_REG_R0);
72
} else {
73
tcg_out_dat_reg(s, COND_AL, ARITH_ADD,
74
TCG_REG_R1, TCG_REG_R1, TCG_REG_R0, 0);
75
- if (s->addr_type == TCG_TYPE_I32) {
76
- tcg_out_ld32_12(s, COND_AL, TCG_REG_R2, TCG_REG_R1, cmp_off);
77
- } else {
78
- tcg_out_ldrd_8(s, COND_AL, TCG_REG_R2, TCG_REG_R1, cmp_off);
79
- }
80
+ tcg_out_ld32_12(s, COND_AL, TCG_REG_R2, TCG_REG_R1, cmp_off);
81
}
82
83
/* Load the tlb addend. */
84
@@ -XXX,XX +XXX,XX @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
85
* This leaves the least significant alignment bits unchanged, and of
86
* course must be zero.
87
*/
88
- t_addr = addrlo;
89
+ t_addr = addr;
90
if (a_mask < s_mask) {
91
t_addr = TCG_REG_R0;
92
tcg_out_dat_imm(s, COND_AL, ARITH_ADD, t_addr,
93
- addrlo, s_mask - a_mask);
94
+ addr, s_mask - a_mask);
95
}
96
if (use_armv7_instructions && s->page_bits <= 16) {
97
tcg_out_movi32(s, COND_AL, TCG_REG_TMP, ~(s->page_mask | a_mask));
98
@@ -XXX,XX +XXX,XX @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
99
} else {
100
if (a_mask) {
101
tcg_debug_assert(a_mask <= 0xff);
102
- tcg_out_dat_imm(s, COND_AL, ARITH_TST, 0, addrlo, a_mask);
103
+ tcg_out_dat_imm(s, COND_AL, ARITH_TST, 0, addr, a_mask);
104
}
105
tcg_out_dat_reg(s, COND_AL, ARITH_MOV, TCG_REG_TMP, 0, t_addr,
106
SHIFT_IMM_LSR(s->page_bits));
107
@@ -XXX,XX +XXX,XX @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
108
0, TCG_REG_R2, TCG_REG_TMP,
109
SHIFT_IMM_LSL(s->page_bits));
110
}
111
-
112
- if (s->addr_type != TCG_TYPE_I32) {
113
- tcg_out_dat_reg(s, COND_EQ, ARITH_CMP, 0, TCG_REG_R3, addrhi, 0);
114
- }
115
} else if (a_mask) {
116
ldst = new_ldst_label(s);
117
ldst->is_ld = is_ld;
118
ldst->oi = oi;
119
- ldst->addrlo_reg = addrlo;
120
- ldst->addrhi_reg = addrhi;
121
+ ldst->addrlo_reg = addr;
122
123
/* We are expecting alignment to max out at 7 */
124
tcg_debug_assert(a_mask <= 0xff);
125
/* tst addr, #mask */
126
- tcg_out_dat_imm(s, COND_AL, ARITH_TST, 0, addrlo, a_mask);
127
+ tcg_out_dat_imm(s, COND_AL, ARITH_TST, 0, addr, a_mask);
128
}
129
130
return ldst;
131
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_ld_direct(TCGContext *s, MemOp opc, TCGReg datalo,
132
}
133
134
static void tcg_out_qemu_ld(TCGContext *s, TCGReg datalo, TCGReg datahi,
135
- TCGReg addrlo, TCGReg addrhi,
136
- MemOpIdx oi, TCGType data_type)
137
+ TCGReg addr, MemOpIdx oi, TCGType data_type)
138
{
139
MemOp opc = get_memop(oi);
140
TCGLabelQemuLdst *ldst;
141
HostAddress h;
142
143
- ldst = prepare_host_addr(s, &h, addrlo, addrhi, oi, true);
144
+ ldst = prepare_host_addr(s, &h, addr, oi, true);
145
if (ldst) {
146
ldst->type = data_type;
147
ldst->datalo_reg = datalo;
148
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_st_direct(TCGContext *s, MemOp opc, TCGReg datalo,
149
}
150
151
static void tcg_out_qemu_st(TCGContext *s, TCGReg datalo, TCGReg datahi,
152
- TCGReg addrlo, TCGReg addrhi,
153
- MemOpIdx oi, TCGType data_type)
154
+ TCGReg addr, MemOpIdx oi, TCGType data_type)
155
{
156
MemOp opc = get_memop(oi);
157
TCGLabelQemuLdst *ldst;
158
HostAddress h;
159
160
- ldst = prepare_host_addr(s, &h, addrlo, addrhi, oi, false);
161
+ ldst = prepare_host_addr(s, &h, addr, oi, false);
162
if (ldst) {
163
ldst->type = data_type;
164
ldst->datalo_reg = datalo;
165
@@ -XXX,XX +XXX,XX @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
166
break;
167
168
case INDEX_op_qemu_ld_i32:
169
- tcg_out_qemu_ld(s, args[0], -1, args[1], -1, args[2], TCG_TYPE_I32);
170
+ tcg_out_qemu_ld(s, args[0], -1, args[1], args[2], TCG_TYPE_I32);
171
break;
172
case INDEX_op_qemu_ld_i64:
173
- tcg_out_qemu_ld(s, args[0], args[1], args[2], -1,
174
- args[3], TCG_TYPE_I64);
175
+ tcg_out_qemu_ld(s, args[0], args[1], args[2], args[3], TCG_TYPE_I64);
176
break;
177
178
case INDEX_op_qemu_st_i32:
179
- tcg_out_qemu_st(s, args[0], -1, args[1], -1, args[2], TCG_TYPE_I32);
180
+ tcg_out_qemu_st(s, args[0], -1, args[1], args[2], TCG_TYPE_I32);
181
break;
182
case INDEX_op_qemu_st_i64:
183
- tcg_out_qemu_st(s, args[0], args[1], args[2], -1,
184
- args[3], TCG_TYPE_I64);
185
+ tcg_out_qemu_st(s, args[0], args[1], args[2], args[3], TCG_TYPE_I64);
186
break;
187
188
case INDEX_op_bswap16_i32:
189
--
190
2.43.0
diff view generated by jsdifflib
New patch
[PULL 06/24] tcg/i386: Drop addrhi from prepare_host_addr
1
The guest address will now always fit in one register.
1
2
3
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
---
6
tcg/i386/tcg-target.c.inc | 56 ++++++++++++++-------------------------
7
1 file changed, 20 insertions(+), 36 deletions(-)
8
9
diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
10
index XXXXXXX..XXXXXXX 100644
11
--- a/tcg/i386/tcg-target.c.inc
12
+++ b/tcg/i386/tcg-target.c.inc
13
@@ -XXX,XX +XXX,XX @@ static inline int setup_guest_base_seg(void)
14
* is required and fill in @h with the host address for the fast path.
15
*/
16
static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
17
- TCGReg addrlo, TCGReg addrhi,
18
- MemOpIdx oi, bool is_ld)
19
+ TCGReg addr, MemOpIdx oi, bool is_ld)
20
{
21
TCGLabelQemuLdst *ldst = NULL;
22
MemOp opc = get_memop(oi);
23
@@ -XXX,XX +XXX,XX @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
24
} else {
25
*h = x86_guest_base;
26
}
27
- h->base = addrlo;
28
+ h->base = addr;
29
h->aa = atom_and_align_for_opc(s, opc, MO_ATOM_IFALIGN, s_bits == MO_128);
30
a_mask = (1 << h->aa.align) - 1;
31
32
@@ -XXX,XX +XXX,XX @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
33
ldst = new_ldst_label(s);
34
ldst->is_ld = is_ld;
35
ldst->oi = oi;
36
- ldst->addrlo_reg = addrlo;
37
- ldst->addrhi_reg = addrhi;
38
+ ldst->addrlo_reg = addr;
39
40
if (TCG_TARGET_REG_BITS == 64) {
41
ttype = s->addr_type;
42
@@ -XXX,XX +XXX,XX @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
43
}
44
}
45
46
- tcg_out_mov(s, tlbtype, TCG_REG_L0, addrlo);
47
+ tcg_out_mov(s, tlbtype, TCG_REG_L0, addr);
48
tcg_out_shifti(s, SHIFT_SHR + tlbrexw, TCG_REG_L0,
49
s->page_bits - CPU_TLB_ENTRY_BITS);
50
51
@@ -XXX,XX +XXX,XX @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
52
* check that we don't cross pages for the complete access.
53
*/
54
if (a_mask >= s_mask) {
55
- tcg_out_mov(s, ttype, TCG_REG_L1, addrlo);
56
+ tcg_out_mov(s, ttype, TCG_REG_L1, addr);
57
} else {
58
tcg_out_modrm_offset(s, OPC_LEA + trexw, TCG_REG_L1,
59
- addrlo, s_mask - a_mask);
60
+ addr, s_mask - a_mask);
61
}
62
tlb_mask = s->page_mask | a_mask;
63
tgen_arithi(s, ARITH_AND + trexw, TCG_REG_L1, tlb_mask, 0);
64
@@ -XXX,XX +XXX,XX @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
65
ldst->label_ptr[0] = s->code_ptr;
66
s->code_ptr += 4;
67
68
- if (TCG_TARGET_REG_BITS == 32 && s->addr_type == TCG_TYPE_I64) {
69
- /* cmp 4(TCG_REG_L0), addrhi */
70
- tcg_out_modrm_offset(s, OPC_CMP_GvEv, addrhi,
71
- TCG_REG_L0, cmp_ofs + 4);
72
-
73
- /* jne slow_path */
74
- tcg_out_opc(s, OPC_JCC_long + JCC_JNE, 0, 0, 0);
75
- ldst->label_ptr[1] = s->code_ptr;
76
- s->code_ptr += 4;
77
- }
78
-
79
/* TLB Hit. */
80
tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_L0, TCG_REG_L0,
81
offsetof(CPUTLBEntry, addend));
82
@@ -XXX,XX +XXX,XX @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
83
ldst = new_ldst_label(s);
84
ldst->is_ld = is_ld;
85
ldst->oi = oi;
86
- ldst->addrlo_reg = addrlo;
87
- ldst->addrhi_reg = addrhi;
88
+ ldst->addrlo_reg = addr;
89
90
/* jne slow_path */
91
- jcc = tcg_out_cmp(s, TCG_COND_TSTNE, addrlo, a_mask, true, false);
92
+ jcc = tcg_out_cmp(s, TCG_COND_TSTNE, addr, a_mask, true, false);
93
tcg_out_opc(s, OPC_JCC_long + jcc, 0, 0, 0);
94
ldst->label_ptr[0] = s->code_ptr;
95
s->code_ptr += 4;
96
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg datalo, TCGReg datahi,
97
}
98
99
static void tcg_out_qemu_ld(TCGContext *s, TCGReg datalo, TCGReg datahi,
100
- TCGReg addrlo, TCGReg addrhi,
101
- MemOpIdx oi, TCGType data_type)
102
+ TCGReg addr, MemOpIdx oi, TCGType data_type)
103
{
104
TCGLabelQemuLdst *ldst;
105
HostAddress h;
106
107
- ldst = prepare_host_addr(s, &h, addrlo, addrhi, oi, true);
108
+ ldst = prepare_host_addr(s, &h, addr, oi, true);
109
tcg_out_qemu_ld_direct(s, datalo, datahi, h, data_type, get_memop(oi));
110
111
if (ldst) {
112
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg datalo, TCGReg datahi,
113
}
114
115
static void tcg_out_qemu_st(TCGContext *s, TCGReg datalo, TCGReg datahi,
116
- TCGReg addrlo, TCGReg addrhi,
117
- MemOpIdx oi, TCGType data_type)
118
+ TCGReg addr, MemOpIdx oi, TCGType data_type)
119
{
120
TCGLabelQemuLdst *ldst;
121
HostAddress h;
122
123
- ldst = prepare_host_addr(s, &h, addrlo, addrhi, oi, false);
124
+ ldst = prepare_host_addr(s, &h, addr, oi, false);
125
tcg_out_qemu_st_direct(s, datalo, datahi, h, get_memop(oi));
126
127
if (ldst) {
128
@@ -XXX,XX +XXX,XX @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
129
break;
130
131
case INDEX_op_qemu_ld_i32:
132
- tcg_out_qemu_ld(s, a0, -1, a1, -1, a2, TCG_TYPE_I32);
133
+ tcg_out_qemu_ld(s, a0, -1, a1, a2, TCG_TYPE_I32);
134
break;
135
case INDEX_op_qemu_ld_i64:
136
if (TCG_TARGET_REG_BITS == 64) {
137
- tcg_out_qemu_ld(s, a0, -1, a1, -1, a2, TCG_TYPE_I64);
138
+ tcg_out_qemu_ld(s, a0, -1, a1, a2, TCG_TYPE_I64);
139
} else {
140
- tcg_out_qemu_ld(s, a0, a1, a2, -1, args[3], TCG_TYPE_I64);
141
+ tcg_out_qemu_ld(s, a0, a1, a2, args[3], TCG_TYPE_I64);
142
}
143
break;
144
case INDEX_op_qemu_ld_i128:
145
tcg_debug_assert(TCG_TARGET_REG_BITS == 64);
146
- tcg_out_qemu_ld(s, a0, a1, a2, -1, args[3], TCG_TYPE_I128);
147
+ tcg_out_qemu_ld(s, a0, a1, a2, args[3], TCG_TYPE_I128);
148
break;
149
150
case INDEX_op_qemu_st_i32:
151
case INDEX_op_qemu_st8_i32:
152
- tcg_out_qemu_st(s, a0, -1, a1, -1, a2, TCG_TYPE_I32);
153
+ tcg_out_qemu_st(s, a0, -1, a1, a2, TCG_TYPE_I32);
154
break;
155
case INDEX_op_qemu_st_i64:
156
if (TCG_TARGET_REG_BITS == 64) {
157
- tcg_out_qemu_st(s, a0, -1, a1, -1, a2, TCG_TYPE_I64);
158
+ tcg_out_qemu_st(s, a0, -1, a1, a2, TCG_TYPE_I64);
159
} else {
160
- tcg_out_qemu_st(s, a0, a1, a2, -1, args[3], TCG_TYPE_I64);
161
+ tcg_out_qemu_st(s, a0, a1, a2, args[3], TCG_TYPE_I64);
162
}
163
break;
164
case INDEX_op_qemu_st_i128:
165
tcg_debug_assert(TCG_TARGET_REG_BITS == 64);
166
- tcg_out_qemu_st(s, a0, a1, a2, -1, args[3], TCG_TYPE_I128);
167
+ tcg_out_qemu_st(s, a0, a1, a2, args[3], TCG_TYPE_I128);
168
break;
169
170
OP_32_64(mulu2):
171
--
172
2.43.0
173
174
diff view generated by jsdifflib
New patch
[PULL 07/24] tcg/mips: Drop addrhi from prepare_host_addr
1
The guest address will now always fit in one register.
1
2
3
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
---
6
tcg/mips/tcg-target.c.inc | 62 ++++++++++++++-------------------------
7
1 file changed, 22 insertions(+), 40 deletions(-)
8
9
diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc
10
index XXXXXXX..XXXXXXX 100644
11
--- a/tcg/mips/tcg-target.c.inc
12
+++ b/tcg/mips/tcg-target.c.inc
13
@@ -XXX,XX +XXX,XX @@ bool tcg_target_has_memory_bswap(MemOp memop)
14
* is required and fill in @h with the host address for the fast path.
15
*/
16
static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
17
- TCGReg addrlo, TCGReg addrhi,
18
- MemOpIdx oi, bool is_ld)
19
+ TCGReg addr, MemOpIdx oi, bool is_ld)
20
{
21
TCGType addr_type = s->addr_type;
22
TCGLabelQemuLdst *ldst = NULL;
23
@@ -XXX,XX +XXX,XX @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
24
ldst = new_ldst_label(s);
25
ldst->is_ld = is_ld;
26
ldst->oi = oi;
27
- ldst->addrlo_reg = addrlo;
28
- ldst->addrhi_reg = addrhi;
29
+ ldst->addrlo_reg = addr;
30
31
/* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */
32
tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP0, TCG_AREG0, mask_off);
33
@@ -XXX,XX +XXX,XX @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
34
35
/* Extract the TLB index from the address into TMP3. */
36
if (TCG_TARGET_REG_BITS == 32 || addr_type == TCG_TYPE_I32) {
37
- tcg_out_opc_sa(s, OPC_SRL, TCG_TMP3, addrlo,
38
+ tcg_out_opc_sa(s, OPC_SRL, TCG_TMP3, addr,
39
s->page_bits - CPU_TLB_ENTRY_BITS);
40
} else {
41
- tcg_out_dsrl(s, TCG_TMP3, addrlo,
42
- s->page_bits - CPU_TLB_ENTRY_BITS);
43
+ tcg_out_dsrl(s, TCG_TMP3, addr, s->page_bits - CPU_TLB_ENTRY_BITS);
44
}
45
tcg_out_opc_reg(s, OPC_AND, TCG_TMP3, TCG_TMP3, TCG_TMP0);
46
47
@@ -XXX,XX +XXX,XX @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
48
tcg_out_opc_imm(s, (TCG_TARGET_REG_BITS == 32
49
|| addr_type == TCG_TYPE_I32
50
? OPC_ADDIU : OPC_DADDIU),
51
- TCG_TMP2, addrlo, s_mask - a_mask);
52
+ TCG_TMP2, addr, s_mask - a_mask);
53
tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, TCG_TMP2);
54
} else {
55
- tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, addrlo);
56
+ tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, addr);
57
}
58
59
/* Zero extend a 32-bit guest address for a 64-bit host. */
60
if (TCG_TARGET_REG_BITS == 64 && addr_type == TCG_TYPE_I32) {
61
- tcg_out_ext32u(s, TCG_TMP2, addrlo);
62
- addrlo = TCG_TMP2;
63
+ tcg_out_ext32u(s, TCG_TMP2, addr);
64
+ addr = TCG_TMP2;
65
}
66
67
ldst->label_ptr[0] = s->code_ptr;
68
tcg_out_opc_br(s, OPC_BNE, TCG_TMP1, TCG_TMP0);
69
70
- /* Load and test the high half tlb comparator. */
71
- if (TCG_TARGET_REG_BITS == 32 && addr_type != TCG_TYPE_I32) {
72
- /* delay slot */
73
- tcg_out_ldst(s, OPC_LW, TCG_TMP0, TCG_TMP3, cmp_off + HI_OFF);
74
-
75
- /* Load the tlb addend for the fast path. */
76
- tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP3, TCG_TMP3, add_off);
77
-
78
- ldst->label_ptr[1] = s->code_ptr;
79
- tcg_out_opc_br(s, OPC_BNE, addrhi, TCG_TMP0);
80
- }
81
-
82
/* delay slot */
83
base = TCG_TMP3;
84
- tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_TMP3, addrlo);
85
+ tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_TMP3, addr);
86
} else {
87
if (a_mask && (use_mips32r6_instructions || a_bits != s_bits)) {
88
ldst = new_ldst_label(s);
89
90
ldst->is_ld = is_ld;
91
ldst->oi = oi;
92
- ldst->addrlo_reg = addrlo;
93
- ldst->addrhi_reg = addrhi;
94
+ ldst->addrlo_reg = addr;
95
96
/* We are expecting a_bits to max out at 7, much lower than ANDI. */
97
tcg_debug_assert(a_bits < 16);
98
- tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP0, addrlo, a_mask);
99
+ tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP0, addr, a_mask);
100
101
ldst->label_ptr[0] = s->code_ptr;
102
if (use_mips32r6_instructions) {
103
@@ -XXX,XX +XXX,XX @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
104
}
105
}
106
107
- base = addrlo;
108
+ base = addr;
109
if (TCG_TARGET_REG_BITS == 64 && addr_type == TCG_TYPE_I32) {
110
tcg_out_ext32u(s, TCG_REG_A0, base);
111
base = TCG_REG_A0;
112
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_ld_unalign(TCGContext *s, TCGReg lo, TCGReg hi,
113
}
114
115
static void tcg_out_qemu_ld(TCGContext *s, TCGReg datalo, TCGReg datahi,
116
- TCGReg addrlo, TCGReg addrhi,
117
- MemOpIdx oi, TCGType data_type)
118
+ TCGReg addr, MemOpIdx oi, TCGType data_type)
119
{
120
MemOp opc = get_memop(oi);
121
TCGLabelQemuLdst *ldst;
122
HostAddress h;
123
124
- ldst = prepare_host_addr(s, &h, addrlo, addrhi, oi, true);
125
+ ldst = prepare_host_addr(s, &h, addr, oi, true);
126
127
if (use_mips32r6_instructions || h.aa.align >= (opc & MO_SIZE)) {
128
tcg_out_qemu_ld_direct(s, datalo, datahi, h.base, opc, data_type);
129
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_st_unalign(TCGContext *s, TCGReg lo, TCGReg hi,
130
}
131
132
static void tcg_out_qemu_st(TCGContext *s, TCGReg datalo, TCGReg datahi,
133
- TCGReg addrlo, TCGReg addrhi,
134
- MemOpIdx oi, TCGType data_type)
135
+ TCGReg addr, MemOpIdx oi, TCGType data_type)
136
{
137
MemOp opc = get_memop(oi);
138
TCGLabelQemuLdst *ldst;
139
HostAddress h;
140
141
- ldst = prepare_host_addr(s, &h, addrlo, addrhi, oi, false);
142
+ ldst = prepare_host_addr(s, &h, addr, oi, false);
143
144
if (use_mips32r6_instructions || h.aa.align >= (opc & MO_SIZE)) {
145
tcg_out_qemu_st_direct(s, datalo, datahi, h.base, opc);
146
@@ -XXX,XX +XXX,XX @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
147
break;
148
149
case INDEX_op_qemu_ld_i32:
150
- tcg_out_qemu_ld(s, a0, 0, a1, 0, a2, TCG_TYPE_I32);
151
+ tcg_out_qemu_ld(s, a0, 0, a1, a2, TCG_TYPE_I32);
152
break;
153
case INDEX_op_qemu_ld_i64:
154
if (TCG_TARGET_REG_BITS == 64) {
155
- tcg_out_qemu_ld(s, a0, 0, a1, 0, a2, TCG_TYPE_I64);
156
+ tcg_out_qemu_ld(s, a0, 0, a1, a2, TCG_TYPE_I64);
157
} else {
158
- tcg_out_qemu_ld(s, a0, a1, a2, 0, args[3], TCG_TYPE_I64);
159
+ tcg_out_qemu_ld(s, a0, a1, a2, args[3], TCG_TYPE_I64);
160
}
161
break;
162
163
case INDEX_op_qemu_st_i32:
164
- tcg_out_qemu_st(s, a0, 0, a1, 0, a2, TCG_TYPE_I32);
165
+ tcg_out_qemu_st(s, a0, 0, a1, a2, TCG_TYPE_I32);
166
break;
167
case INDEX_op_qemu_st_i64:
168
if (TCG_TARGET_REG_BITS == 64) {
169
- tcg_out_qemu_st(s, a0, 0, a1, 0, a2, TCG_TYPE_I64);
170
+ tcg_out_qemu_st(s, a0, 0, a1, a2, TCG_TYPE_I64);
171
} else {
172
- tcg_out_qemu_st(s, a0, a1, a2, 0, args[3], TCG_TYPE_I64);
173
+ tcg_out_qemu_st(s, a0, a1, a2, args[3], TCG_TYPE_I64);
174
}
175
break;
176
177
--
178
2.43.0
179
180
diff view generated by jsdifflib
New patch
[PULL 08/24] tcg/ppc: Drop addrhi from prepare_host_addr
1
1
The guest address will now always fit in one register.
2
3
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
---
6
tcg/ppc/tcg-target.c.inc | 75 ++++++++++++----------------------------
7
1 file changed, 23 insertions(+), 52 deletions(-)
8
9
diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc
10
index XXXXXXX..XXXXXXX 100644
11
--- a/tcg/ppc/tcg-target.c.inc
12
+++ b/tcg/ppc/tcg-target.c.inc
13
@@ -XXX,XX +XXX,XX @@ bool tcg_target_has_memory_bswap(MemOp memop)
14
* is required and fill in @h with the host address for the fast path.
15
*/
16
static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
17
- TCGReg addrlo, TCGReg addrhi,
18
- MemOpIdx oi, bool is_ld)
19
+ TCGReg addr, MemOpIdx oi, bool is_ld)
20
{
21
TCGType addr_type = s->addr_type;
22
TCGLabelQemuLdst *ldst = NULL;
23
@@ -XXX,XX +XXX,XX @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
24
ldst = new_ldst_label(s);
25
ldst->is_ld = is_ld;
26
ldst->oi = oi;
27
- ldst->addrlo_reg = addrlo;
28
- ldst->addrhi_reg = addrhi;
29
+ ldst->addrlo_reg = addr;
30
31
/* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */
32
tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, TCG_AREG0, mask_off);
33
@@ -XXX,XX +XXX,XX @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
34
35
/* Extract the page index, shifted into place for tlb index. */
36
if (TCG_TARGET_REG_BITS == 32) {
37
- tcg_out_shri32(s, TCG_REG_R0, addrlo,
38
+ tcg_out_shri32(s, TCG_REG_R0, addr,
39
s->page_bits - CPU_TLB_ENTRY_BITS);
40
} else {
41
- tcg_out_shri64(s, TCG_REG_R0, addrlo,
42
+ tcg_out_shri64(s, TCG_REG_R0, addr,
43
s->page_bits - CPU_TLB_ENTRY_BITS);
44
}
45
tcg_out32(s, AND | SAB(TCG_REG_TMP1, TCG_REG_TMP1, TCG_REG_R0));
46
@@ -XXX,XX +XXX,XX @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
47
if (a_bits < s_bits) {
48
a_bits = s_bits;
49
}
50
- tcg_out_rlw(s, RLWINM, TCG_REG_R0, addrlo, 0,
51
+ tcg_out_rlw(s, RLWINM, TCG_REG_R0, addr, 0,
52
(32 - a_bits) & 31, 31 - s->page_bits);
53
} else {
54
- TCGReg t = addrlo;
55
+ TCGReg t = addr;
56
57
/*
58
* If the access is unaligned, we need to make sure we fail if we
59
@@ -XXX,XX +XXX,XX @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
60
}
61
}
62
63
- if (TCG_TARGET_REG_BITS == 32 && addr_type != TCG_TYPE_I32) {
64
- /* Low part comparison into cr7. */
65
- tcg_out_cmp(s, TCG_COND_EQ, TCG_REG_R0, TCG_REG_TMP2,
66
- 0, 7, TCG_TYPE_I32);
67
-
68
- /* Load the high part TLB comparator into TMP2. */
69
- tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_TMP2, TCG_REG_TMP1,
70
- cmp_off + 4 * !HOST_BIG_ENDIAN);
71
-
72
- /* Load addend, deferred for this case. */
73
- tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, TCG_REG_TMP1,
74
- offsetof(CPUTLBEntry, addend));
75
-
76
- /* High part comparison into cr6. */
77
- tcg_out_cmp(s, TCG_COND_EQ, addrhi, TCG_REG_TMP2,
78
- 0, 6, TCG_TYPE_I32);
79
-
80
- /* Combine comparisons into cr0. */
81
- tcg_out32(s, CRAND | BT(0, CR_EQ) | BA(6, CR_EQ) | BB(7, CR_EQ));
82
- } else {
83
- /* Full comparison into cr0. */
84
- tcg_out_cmp(s, TCG_COND_EQ, TCG_REG_R0, TCG_REG_TMP2,
85
- 0, 0, addr_type);
86
- }
87
+ /* Full comparison into cr0. */
88
+ tcg_out_cmp(s, TCG_COND_EQ, TCG_REG_R0, TCG_REG_TMP2, 0, 0, addr_type);
89
90
/* Load a pointer into the current opcode w/conditional branch-link. */
91
ldst->label_ptr[0] = s->code_ptr;
92
@@ -XXX,XX +XXX,XX @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
93
ldst = new_ldst_label(s);
94
ldst->is_ld = is_ld;
95
ldst->oi = oi;
96
- ldst->addrlo_reg = addrlo;
97
- ldst->addrhi_reg = addrhi;
98
+ ldst->addrlo_reg = addr;
99
100
/* We are expecting a_bits to max out at 7, much lower than ANDI. */
101
tcg_debug_assert(a_bits < 16);
102
- tcg_out32(s, ANDI | SAI(addrlo, TCG_REG_R0, (1 << a_bits) - 1));
103
+ tcg_out32(s, ANDI | SAI(addr, TCG_REG_R0, (1 << a_bits) - 1));
104
105
ldst->label_ptr[0] = s->code_ptr;
106
tcg_out32(s, BC | BI(0, CR_EQ) | BO_COND_FALSE | LK);
107
@@ -XXX,XX +XXX,XX @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
108
109
if (TCG_TARGET_REG_BITS == 64 && addr_type == TCG_TYPE_I32) {
110
/* Zero-extend the guest address for use in the host address. */
111
- tcg_out_ext32u(s, TCG_REG_TMP2, addrlo);
112
+ tcg_out_ext32u(s, TCG_REG_TMP2, addr);
113
h->index = TCG_REG_TMP2;
114
} else {
115
- h->index = addrlo;
116
+ h->index = addr;
117
}
118
119
return ldst;
120
}
121
122
static void tcg_out_qemu_ld(TCGContext *s, TCGReg datalo, TCGReg datahi,
123
- TCGReg addrlo, TCGReg addrhi,
124
- MemOpIdx oi, TCGType data_type)
125
+ TCGReg addr, MemOpIdx oi, TCGType data_type)
126
{
127
MemOp opc = get_memop(oi);
128
TCGLabelQemuLdst *ldst;
129
HostAddress h;
130
131
- ldst = prepare_host_addr(s, &h, addrlo, addrhi, oi, true);
132
+ ldst = prepare_host_addr(s, &h, addr, oi, true);
133
134
if (TCG_TARGET_REG_BITS == 32 && (opc & MO_SIZE) == MO_64) {
135
if (opc & MO_BSWAP) {
136
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg datalo, TCGReg datahi,
137
}
138
139
static void tcg_out_qemu_st(TCGContext *s, TCGReg datalo, TCGReg datahi,
140
- TCGReg addrlo, TCGReg addrhi,
141
- MemOpIdx oi, TCGType data_type)
142
+ TCGReg addr, MemOpIdx oi, TCGType data_type)
143
{
144
MemOp opc = get_memop(oi);
145
TCGLabelQemuLdst *ldst;
146
HostAddress h;
147
148
- ldst = prepare_host_addr(s, &h, addrlo, addrhi, oi, false);
149
+ ldst = prepare_host_addr(s, &h, addr, oi, false);
150
151
if (TCG_TARGET_REG_BITS == 32 && (opc & MO_SIZE) == MO_64) {
152
if (opc & MO_BSWAP) {
153
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_ldst_i128(TCGContext *s, TCGReg datalo, TCGReg datahi,
154
uint32_t insn;
155
TCGReg index;
156
157
- ldst = prepare_host_addr(s, &h, addr_reg, -1, oi, is_ld);
158
+ ldst = prepare_host_addr(s, &h, addr_reg, oi, is_ld);
159
160
/* Compose the final address, as LQ/STQ have no indexing. */
161
index = h.index;
162
@@ -XXX,XX +XXX,XX @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
163
break;
164
165
case INDEX_op_qemu_ld_i32:
166
- tcg_out_qemu_ld(s, args[0], -1, args[1], -1, args[2], TCG_TYPE_I32);
167
+ tcg_out_qemu_ld(s, args[0], -1, args[1], args[2], TCG_TYPE_I32);
168
break;
169
case INDEX_op_qemu_ld_i64:
170
if (TCG_TARGET_REG_BITS == 64) {
171
- tcg_out_qemu_ld(s, args[0], -1, args[1], -1,
172
- args[2], TCG_TYPE_I64);
173
+ tcg_out_qemu_ld(s, args[0], -1, args[1], args[2], TCG_TYPE_I64);
174
} else {
175
- tcg_out_qemu_ld(s, args[0], args[1], args[2], -1,
176
+ tcg_out_qemu_ld(s, args[0], args[1], args[2],
177
args[3], TCG_TYPE_I64);
178
}
179
break;
180
@@ -XXX,XX +XXX,XX @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
181
break;
182
183
case INDEX_op_qemu_st_i32:
184
- tcg_out_qemu_st(s, args[0], -1, args[1], -1, args[2], TCG_TYPE_I32);
185
+ tcg_out_qemu_st(s, args[0], -1, args[1], args[2], TCG_TYPE_I32);
186
break;
187
case INDEX_op_qemu_st_i64:
188
if (TCG_TARGET_REG_BITS == 64) {
189
- tcg_out_qemu_st(s, args[0], -1, args[1], -1,
190
- args[2], TCG_TYPE_I64);
191
+ tcg_out_qemu_st(s, args[0], -1, args[1], args[2], TCG_TYPE_I64);
192
} else {
193
- tcg_out_qemu_st(s, args[0], args[1], args[2], -1,
194
+ tcg_out_qemu_st(s, args[0], args[1], args[2],
195
args[3], TCG_TYPE_I64);
196
}
197
break;
198
--
199
2.43.0
200
201
diff view generated by jsdifflib
New patch
[PULL 09/24] tcg: Replace addr{lo, hi}_reg with addr_reg in TCGLabelQemuLdst
1
1
There is now always only one guest address register.
2
3
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
---
6
tcg/tcg.c | 18 +++++++++---------
7
tcg/aarch64/tcg-target.c.inc | 4 ++--
8
tcg/arm/tcg-target.c.inc | 4 ++--
9
tcg/i386/tcg-target.c.inc | 4 ++--
10
tcg/loongarch64/tcg-target.c.inc | 4 ++--
11
tcg/mips/tcg-target.c.inc | 4 ++--
12
tcg/ppc/tcg-target.c.inc | 4 ++--
13
tcg/riscv/tcg-target.c.inc | 4 ++--
14
tcg/s390x/tcg-target.c.inc | 4 ++--
15
tcg/sparc64/tcg-target.c.inc | 4 ++--
16
10 files changed, 27 insertions(+), 27 deletions(-)
17
18
diff --git a/tcg/tcg.c b/tcg/tcg.c
19
index XXXXXXX..XXXXXXX 100644
20
--- a/tcg/tcg.c
21
+++ b/tcg/tcg.c
22
@@ -XXX,XX +XXX,XX @@ struct TCGLabelQemuLdst {
23
bool is_ld; /* qemu_ld: true, qemu_st: false */
24
MemOpIdx oi;
25
TCGType type; /* result type of a load */
26
- TCGReg addrlo_reg; /* reg index for low word of guest virtual addr */
27
- TCGReg addrhi_reg; /* reg index for high word of guest virtual addr */
28
+ TCGReg addr_reg; /* reg index for guest virtual addr */
29
TCGReg datalo_reg; /* reg index for low word to be loaded or stored */
30
TCGReg datahi_reg; /* reg index for high word to be loaded or stored */
31
const tcg_insn_unit *raddr; /* addr of the next IR of qemu_ld/st IR */
32
@@ -XXX,XX +XXX,XX @@ static void tcg_out_ld_helper_args(TCGContext *s, const TCGLabelQemuLdst *ldst,
33
*/
34
tcg_out_helper_add_mov(mov, loc + HOST_BIG_ENDIAN,
35
TCG_TYPE_I32, TCG_TYPE_I32,
36
- ldst->addrlo_reg, -1);
37
+ ldst->addr_reg, -1);
38
tcg_out_helper_load_slots(s, 1, mov, parm);
39
40
tcg_out_helper_load_imm(s, loc[!HOST_BIG_ENDIAN].arg_slot,
41
@@ -XXX,XX +XXX,XX @@ static void tcg_out_ld_helper_args(TCGContext *s, const TCGLabelQemuLdst *ldst,
42
next_arg += 2;
43
} else {
44
nmov = tcg_out_helper_add_mov(mov, loc, TCG_TYPE_I64, s->addr_type,
45
- ldst->addrlo_reg, ldst->addrhi_reg);
46
+ ldst->addr_reg, -1);
47
tcg_out_helper_load_slots(s, nmov, mov, parm);
48
next_arg += nmov;
49
}
50
@@ -XXX,XX +XXX,XX @@ static void tcg_out_st_helper_args(TCGContext *s, const TCGLabelQemuLdst *ldst,
51
52
/* Handle addr argument. */
53
loc = &info->in[next_arg];
54
- if (TCG_TARGET_REG_BITS == 32 && s->addr_type == TCG_TYPE_I32) {
55
+ tcg_debug_assert(s->addr_type <= TCG_TYPE_REG);
56
+ if (TCG_TARGET_REG_BITS == 32) {
57
/*
58
- * 32-bit host with 32-bit guest: zero-extend the guest address
59
+ * 32-bit host (and thus 32-bit guest): zero-extend the guest address
60
* to 64-bits for the helper by storing the low part. Later,
61
* after we have processed the register inputs, we will load a
62
* zero for the high part.
63
*/
64
tcg_out_helper_add_mov(mov, loc + HOST_BIG_ENDIAN,
65
TCG_TYPE_I32, TCG_TYPE_I32,
66
- ldst->addrlo_reg, -1);
67
+ ldst->addr_reg, -1);
68
next_arg += 2;
69
nmov += 1;
70
} else {
71
n = tcg_out_helper_add_mov(mov, loc, TCG_TYPE_I64, s->addr_type,
72
- ldst->addrlo_reg, ldst->addrhi_reg);
73
+ ldst->addr_reg, -1);
74
next_arg += n;
75
nmov += n;
76
}
77
@@ -XXX,XX +XXX,XX @@ static void tcg_out_st_helper_args(TCGContext *s, const TCGLabelQemuLdst *ldst,
78
g_assert_not_reached();
79
}
80
81
- if (TCG_TARGET_REG_BITS == 32 && s->addr_type == TCG_TYPE_I32) {
82
+ if (TCG_TARGET_REG_BITS == 32) {
83
/* Zero extend the address by loading a zero for the high part. */
84
loc = &info->in[1 + !HOST_BIG_ENDIAN];
85
tcg_out_helper_load_imm(s, loc->arg_slot, TCG_TYPE_I32, 0, parm);
86
diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc
87
index XXXXXXX..XXXXXXX 100644
88
--- a/tcg/aarch64/tcg-target.c.inc
89
+++ b/tcg/aarch64/tcg-target.c.inc
90
@@ -XXX,XX +XXX,XX @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
91
ldst = new_ldst_label(s);
92
ldst->is_ld = is_ld;
93
ldst->oi = oi;
94
- ldst->addrlo_reg = addr_reg;
95
+ ldst->addr_reg = addr_reg;
96
97
mask_type = (s->page_bits + s->tlb_dyn_max_bits > 32
98
? TCG_TYPE_I64 : TCG_TYPE_I32);
99
@@ -XXX,XX +XXX,XX @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
100
101
ldst->is_ld = is_ld;
102
ldst->oi = oi;
103
- ldst->addrlo_reg = addr_reg;
104
+ ldst->addr_reg = addr_reg;
105
106
/* tst addr, #mask */
107
tcg_out_logicali(s, I3404_ANDSI, 0, TCG_REG_XZR, addr_reg, a_mask);
108
diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
109
index XXXXXXX..XXXXXXX 100644
110
--- a/tcg/arm/tcg-target.c.inc
111
+++ b/tcg/arm/tcg-target.c.inc
112
@@ -XXX,XX +XXX,XX @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
113
ldst = new_ldst_label(s);
114
ldst->is_ld = is_ld;
115
ldst->oi = oi;
116
- ldst->addrlo_reg = addr;
117
+ ldst->addr_reg = addr;
118
119
/* Load cpu->neg.tlb.f[mmu_idx].{mask,table} into {r0,r1}. */
120
QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, mask) != 0);
121
@@ -XXX,XX +XXX,XX @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
122
ldst = new_ldst_label(s);
123
ldst->is_ld = is_ld;
124
ldst->oi = oi;
125
- ldst->addrlo_reg = addr;
126
+ ldst->addr_reg = addr;
127
128
/* We are expecting alignment to max out at 7 */
129
tcg_debug_assert(a_mask <= 0xff);
130
diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
131
index XXXXXXX..XXXXXXX 100644
132
--- a/tcg/i386/tcg-target.c.inc
133
+++ b/tcg/i386/tcg-target.c.inc
134
@@ -XXX,XX +XXX,XX @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
135
ldst = new_ldst_label(s);
136
ldst->is_ld = is_ld;
137
ldst->oi = oi;
138
- ldst->addrlo_reg = addr;
139
+ ldst->addr_reg = addr;
140
141
if (TCG_TARGET_REG_BITS == 64) {
142
ttype = s->addr_type;
143
@@ -XXX,XX +XXX,XX @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
144
ldst = new_ldst_label(s);
145
ldst->is_ld = is_ld;
146
ldst->oi = oi;
147
- ldst->addrlo_reg = addr;
148
+ ldst->addr_reg = addr;
149
150
/* jne slow_path */
151
jcc = tcg_out_cmp(s, TCG_COND_TSTNE, addr, a_mask, true, false);
152
diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc
153
index XXXXXXX..XXXXXXX 100644
154
--- a/tcg/loongarch64/tcg-target.c.inc
155
+++ b/tcg/loongarch64/tcg-target.c.inc
156
@@ -XXX,XX +XXX,XX @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
157
ldst = new_ldst_label(s);
158
ldst->is_ld = is_ld;
159
ldst->oi = oi;
160
- ldst->addrlo_reg = addr_reg;
161
+ ldst->addr_reg = addr_reg;
162
163
tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP0, TCG_AREG0, mask_ofs);
164
tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, TCG_AREG0, table_ofs);
165
@@ -XXX,XX +XXX,XX @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
166
167
ldst->is_ld = is_ld;
168
ldst->oi = oi;
169
- ldst->addrlo_reg = addr_reg;
170
+ ldst->addr_reg = addr_reg;
171
172
/*
173
* Without micro-architecture details, we don't know which of
174
diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc
175
index XXXXXXX..XXXXXXX 100644
176
--- a/tcg/mips/tcg-target.c.inc
177
+++ b/tcg/mips/tcg-target.c.inc
178
@@ -XXX,XX +XXX,XX @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
179
ldst = new_ldst_label(s);
180
ldst->is_ld = is_ld;
181
ldst->oi = oi;
182
- ldst->addrlo_reg = addr;
183
+ ldst->addr_reg = addr;
184
185
/* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */
186
tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP0, TCG_AREG0, mask_off);
187
@@ -XXX,XX +XXX,XX @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
188
189
ldst->is_ld = is_ld;
190
ldst->oi = oi;
191
- ldst->addrlo_reg = addr;
192
+ ldst->addr_reg = addr;
193
194
/* We are expecting a_bits to max out at 7, much lower than ANDI. */
195
tcg_debug_assert(a_bits < 16);
196
diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc
197
index XXXXXXX..XXXXXXX 100644
198
--- a/tcg/ppc/tcg-target.c.inc
199
+++ b/tcg/ppc/tcg-target.c.inc
200
@@ -XXX,XX +XXX,XX @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
201
ldst = new_ldst_label(s);
202
ldst->is_ld = is_ld;
203
ldst->oi = oi;
204
- ldst->addrlo_reg = addr;
205
+ ldst->addr_reg = addr;
206
207
/* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */
208
tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, TCG_AREG0, mask_off);
209
@@ -XXX,XX +XXX,XX @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
210
ldst = new_ldst_label(s);
211
ldst->is_ld = is_ld;
212
ldst->oi = oi;
213
- ldst->addrlo_reg = addr;
214
+ ldst->addr_reg = addr;
215
216
/* We are expecting a_bits to max out at 7, much lower than ANDI. */
217
tcg_debug_assert(a_bits < 16);
218
diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
219
index XXXXXXX..XXXXXXX 100644
220
--- a/tcg/riscv/tcg-target.c.inc
221
+++ b/tcg/riscv/tcg-target.c.inc
222
@@ -XXX,XX +XXX,XX @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, TCGReg *pbase,
223
ldst = new_ldst_label(s);
224
ldst->is_ld = is_ld;
225
ldst->oi = oi;
226
- ldst->addrlo_reg = addr_reg;
227
+ ldst->addr_reg = addr_reg;
228
229
init_setting_vtype(s);
230
231
@@ -XXX,XX +XXX,XX @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, TCGReg *pbase,
232
ldst = new_ldst_label(s);
233
ldst->is_ld = is_ld;
234
ldst->oi = oi;
235
- ldst->addrlo_reg = addr_reg;
236
+ ldst->addr_reg = addr_reg;
237
238
init_setting_vtype(s);
239
240
diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc
241
index XXXXXXX..XXXXXXX 100644
242
--- a/tcg/s390x/tcg-target.c.inc
243
+++ b/tcg/s390x/tcg-target.c.inc
244
@@ -XXX,XX +XXX,XX @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
245
ldst = new_ldst_label(s);
246
ldst->is_ld = is_ld;
247
ldst->oi = oi;
248
- ldst->addrlo_reg = addr_reg;
249
+ ldst->addr_reg = addr_reg;
250
251
tcg_out_sh64(s, RSY_SRLG, TCG_TMP0, addr_reg, TCG_REG_NONE,
252
s->page_bits - CPU_TLB_ENTRY_BITS);
253
@@ -XXX,XX +XXX,XX @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
254
ldst = new_ldst_label(s);
255
ldst->is_ld = is_ld;
256
ldst->oi = oi;
257
- ldst->addrlo_reg = addr_reg;
258
+ ldst->addr_reg = addr_reg;
259
260
tcg_debug_assert(a_mask <= 0xffff);
261
tcg_out_insn(s, RI, TMLL, addr_reg, a_mask);
262
diff --git a/tcg/sparc64/tcg-target.c.inc b/tcg/sparc64/tcg-target.c.inc
263
index XXXXXXX..XXXXXXX 100644
264
--- a/tcg/sparc64/tcg-target.c.inc
265
+++ b/tcg/sparc64/tcg-target.c.inc
266
@@ -XXX,XX +XXX,XX @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
267
ldst = new_ldst_label(s);
268
ldst->is_ld = is_ld;
269
ldst->oi = oi;
270
- ldst->addrlo_reg = addr_reg;
271
+ ldst->addr_reg = addr_reg;
272
ldst->label_ptr[0] = s->code_ptr;
273
274
/* bne,pn %[xi]cc, label0 */
275
@@ -XXX,XX +XXX,XX @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
276
ldst = new_ldst_label(s);
277
ldst->is_ld = is_ld;
278
ldst->oi = oi;
279
- ldst->addrlo_reg = addr_reg;
280
+ ldst->addr_reg = addr_reg;
281
ldst->label_ptr[0] = s->code_ptr;
282
283
/* bne,pn %icc, label0 */
284
--
285
2.43.0
286
287
diff view generated by jsdifflib
[PULL 08/10] accel/tcg: Declare missing cpu_loop_exit*() stubs
[PULL 10/24] plugins: Fix qemu_plugin_read_memory_vaddr parameters
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
The declaration uses uint64_t for addr.
2
2
3
cpu_loop_exit*() functions are declared in accel/tcg/cpu-exec-common.c,
3
Fixes: 595cd9ce2ec ("plugins: add plugin API to read guest memory")
4
and are not available when TCG accelerator is not built. Add stubs so
4
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
5
linking without TCG succeed.
6
7
Problematic files:
8
9
- hw/semihosting/console.c in qemu_semihosting_console_inc()
10
- hw/ppc/spapr_hcall.c in h_confer()
11
- hw/s390x/ipl.c in s390_ipl_reset_request()
12
- hw/misc/mips_itu.c
13
14
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
15
Message-Id: <20210117164813.4101761-5-f4bug@amsat.org>
16
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
17
---
6
---
18
accel/stubs/tcg-stub.c | 10 ++++++++++
7
plugins/api.c | 2 +-
19
1 file changed, 10 insertions(+)
8
1 file changed, 1 insertion(+), 1 deletion(-)
20
9
21
diff --git a/accel/stubs/tcg-stub.c b/accel/stubs/tcg-stub.c
10
diff --git a/plugins/api.c b/plugins/api.c
22
index XXXXXXX..XXXXXXX 100644
11
index XXXXXXX..XXXXXXX 100644
23
--- a/accel/stubs/tcg-stub.c
12
--- a/plugins/api.c
24
+++ b/accel/stubs/tcg-stub.c
13
+++ b/plugins/api.c
25
@@ -XXX,XX +XXX,XX @@ void *probe_access(CPUArchState *env, target_ulong addr, int size,
14
@@ -XXX,XX +XXX,XX @@ GArray *qemu_plugin_get_registers(void)
26
/* Handled by hardware accelerator. */
15
return create_register_handles(regs);
27
g_assert_not_reached();
28
}
16
}
29
+
17
30
+void QEMU_NORETURN cpu_loop_exit(CPUState *cpu)
18
-bool qemu_plugin_read_memory_vaddr(vaddr addr, GByteArray *data, size_t len)
31
+{
19
+bool qemu_plugin_read_memory_vaddr(uint64_t addr, GByteArray *data, size_t len)
32
+ g_assert_not_reached();
20
{
33
+}
21
g_assert(current_cpu);
34
+
22
35
+void QEMU_NORETURN cpu_loop_exit_restore(CPUState *cpu, uintptr_t pc)
36
+{
37
+ g_assert_not_reached();
38
+}
39
--
23
--
40
2.25.1
24
2.43.0
41
25
42
26
diff view generated by jsdifflib
New patch
[PULL 11/24] accel/tcg: Fix tlb_set_page_with_attrs, tlb_set_page
1
The declarations use vaddr for size.
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
---
5
accel/tcg/cputlb.c | 4 ++--
6
1 file changed, 2 insertions(+), 2 deletions(-)
7
8
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
9
index XXXXXXX..XXXXXXX 100644
10
--- a/accel/tcg/cputlb.c
11
+++ b/accel/tcg/cputlb.c
12
@@ -XXX,XX +XXX,XX @@ void tlb_set_page_full(CPUState *cpu, int mmu_idx,
13
14
void tlb_set_page_with_attrs(CPUState *cpu, vaddr addr,
15
hwaddr paddr, MemTxAttrs attrs, int prot,
16
- int mmu_idx, uint64_t size)
17
+ int mmu_idx, vaddr size)
18
{
19
CPUTLBEntryFull full = {
20
.phys_addr = paddr,
21
@@ -XXX,XX +XXX,XX @@ void tlb_set_page_with_attrs(CPUState *cpu, vaddr addr,
22
23
void tlb_set_page(CPUState *cpu, vaddr addr,
24
hwaddr paddr, int prot,
25
- int mmu_idx, uint64_t size)
26
+ int mmu_idx, vaddr size)
27
{
28
tlb_set_page_with_attrs(cpu, addr, paddr, MEMTXATTRS_UNSPECIFIED,
29
prot, mmu_idx, size);
30
--
31
2.43.0
diff view generated by jsdifflib
[PULL 02/10] qemu/compiler: Split out qemu_build_not_reached_always
[PULL 12/24] include/exec: Change vaddr to uintptr_t
1
Provide a symbol that can always be used to signal an error,
1
Since we no longer support 64-bit guests on 32-bit hosts,
2
regardless of optimization. Usage of this should be protected
2
we can use a 32-bit type on a 32-bit host.
3
by e.g. __builtin_constant_p, which guards for optimization.
4
3
5
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
4
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
---
6
---
8
include/qemu/compiler.h | 5 +++--
7
include/exec/vaddr.h | 16 +++++++++-------
9
1 file changed, 3 insertions(+), 2 deletions(-)
8
1 file changed, 9 insertions(+), 7 deletions(-)
10
9
11
diff --git a/include/qemu/compiler.h b/include/qemu/compiler.h
10
diff --git a/include/exec/vaddr.h b/include/exec/vaddr.h
12
index XXXXXXX..XXXXXXX 100644
11
index XXXXXXX..XXXXXXX 100644
13
--- a/include/qemu/compiler.h
12
--- a/include/exec/vaddr.h
14
+++ b/include/qemu/compiler.h
13
+++ b/include/exec/vaddr.h
15
@@ -XXX,XX +XXX,XX @@
14
@@ -XXX,XX +XXX,XX @@
16
* supports QEMU_ERROR, this will be reported at compile time; otherwise
15
/**
17
* this will be reported at link time due to the missing symbol.
16
* vaddr:
17
* Type wide enough to contain any #target_ulong virtual address.
18
+ * We do not support 64-bit guest on 32-host and detect at configure time.
19
+ * Therefore, a host pointer width will always fit a guest pointer.
18
*/
20
*/
19
-#if defined(__OPTIMIZE__) && !defined(__NO_INLINE__)
21
-typedef uint64_t vaddr;
20
extern void QEMU_NORETURN QEMU_ERROR("code path is reachable")
22
-#define VADDR_PRId PRId64
21
- qemu_build_not_reached(void);
23
-#define VADDR_PRIu PRIu64
22
+ qemu_build_not_reached_always(void);
24
-#define VADDR_PRIo PRIo64
23
+#if defined(__OPTIMIZE__) && !defined(__NO_INLINE__)
25
-#define VADDR_PRIx PRIx64
24
+#define qemu_build_not_reached() qemu_build_not_reached_always()
26
-#define VADDR_PRIX PRIX64
25
#else
27
-#define VADDR_MAX UINT64_MAX
26
#define qemu_build_not_reached() g_assert_not_reached()
28
+typedef uintptr_t vaddr;
29
+#define VADDR_PRId PRIdPTR
30
+#define VADDR_PRIu PRIuPTR
31
+#define VADDR_PRIo PRIoPTR
32
+#define VADDR_PRIx PRIxPTR
33
+#define VADDR_PRIX PRIXPTR
34
+#define VADDR_MAX UINTPTR_MAX
35
27
#endif
36
#endif
28
--
37
--
29
2.25.1
38
2.43.0
30
39
31
40
diff view generated by jsdifflib
[PULL 06/10] accel/tcg: Move tb_flush_jmp_cache() to cputlb.c
[PULL 13/24] include/exec: Use uintptr_t in CPUTLBEntry
1
Move and make the function static, as the only users
1
Since we no longer support 64-bit guests on 32-bit hosts,
2
are here in cputlb.c.
2
we can use a 32-bit type on a 32-bit host. This shrinks
3
the size of the structure to 16 bytes on a 32-bit host.
3
4
4
Suggested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
5
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
---
7
---
7
include/exec/exec-all.h | 3 ---
8
include/exec/tlb-common.h | 10 +++++-----
8
accel/tcg/cputlb.c | 18 ++++++++++++++++++
9
accel/tcg/cputlb.c | 21 ++++-----------------
9
accel/tcg/translate-all.c | 17 -----------------
10
tcg/arm/tcg-target.c.inc | 1 -
10
3 files changed, 18 insertions(+), 20 deletions(-)
11
tcg/mips/tcg-target.c.inc | 12 +++++-------
12
tcg/ppc/tcg-target.c.inc | 21 +++++----------------
13
5 files changed, 19 insertions(+), 46 deletions(-)
11
14
12
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
15
diff --git a/include/exec/tlb-common.h b/include/exec/tlb-common.h
13
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
14
--- a/include/exec/exec-all.h
17
--- a/include/exec/tlb-common.h
15
+++ b/include/exec/exec-all.h
18
+++ b/include/exec/tlb-common.h
16
@@ -XXX,XX +XXX,XX @@ tb_page_addr_t get_page_addr_code_hostp(CPUArchState *env, target_ulong addr,
19
@@ -XXX,XX +XXX,XX @@
17
void tlb_reset_dirty(CPUState *cpu, ram_addr_t start1, ram_addr_t length);
20
#ifndef EXEC_TLB_COMMON_H
18
void tlb_set_dirty(CPUState *cpu, target_ulong vaddr);
21
#define EXEC_TLB_COMMON_H 1
19
22
20
-/* exec.c */
23
-#define CPU_TLB_ENTRY_BITS 5
21
-void tb_flush_jmp_cache(CPUState *cpu, target_ulong addr);
24
+#define CPU_TLB_ENTRY_BITS (HOST_LONG_BITS == 32 ? 4 : 5)
22
-
25
23
MemoryRegionSection *
26
/* Minimalized TLB entry for use by TCG fast path. */
24
address_space_translate_for_iotlb(CPUState *cpu, int asidx, hwaddr addr,
27
typedef union CPUTLBEntry {
25
hwaddr *xlat, hwaddr *plen,
28
struct {
29
- uint64_t addr_read;
30
- uint64_t addr_write;
31
- uint64_t addr_code;
32
+ uintptr_t addr_read;
33
+ uintptr_t addr_write;
34
+ uintptr_t addr_code;
35
/*
36
* Addend to virtual address to get host address. IO accesses
37
* use the corresponding iotlb value.
38
@@ -XXX,XX +XXX,XX @@ typedef union CPUTLBEntry {
39
* Padding to get a power of two size, as well as index
40
* access to addr_{read,write,code}.
41
*/
42
- uint64_t addr_idx[(1 << CPU_TLB_ENTRY_BITS) / sizeof(uint64_t)];
43
+ uintptr_t addr_idx[(1 << CPU_TLB_ENTRY_BITS) / sizeof(uintptr_t)];
44
} CPUTLBEntry;
45
46
QEMU_BUILD_BUG_ON(sizeof(CPUTLBEntry) != (1 << CPU_TLB_ENTRY_BITS));
26
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
47
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
27
index XXXXXXX..XXXXXXX 100644
48
index XXXXXXX..XXXXXXX 100644
28
--- a/accel/tcg/cputlb.c
49
--- a/accel/tcg/cputlb.c
29
+++ b/accel/tcg/cputlb.c
50
+++ b/accel/tcg/cputlb.c
30
@@ -XXX,XX +XXX,XX @@
51
@@ -XXX,XX +XXX,XX @@ static inline uint64_t tlb_read_idx(const CPUTLBEntry *entry,
31
#include "exec/address-spaces.h"
52
{
32
#include "exec/cpu_ldst.h"
53
/* Do not rearrange the CPUTLBEntry structure members. */
33
#include "exec/cputlb.h"
54
QEMU_BUILD_BUG_ON(offsetof(CPUTLBEntry, addr_read) !=
34
+#include "exec/tb-hash.h"
55
- MMU_DATA_LOAD * sizeof(uint64_t));
35
#include "exec/memory-internal.h"
56
+ MMU_DATA_LOAD * sizeof(uintptr_t));
36
#include "exec/ram_addr.h"
57
QEMU_BUILD_BUG_ON(offsetof(CPUTLBEntry, addr_write) !=
37
#include "tcg/tcg.h"
58
- MMU_DATA_STORE * sizeof(uint64_t));
38
@@ -XXX,XX +XXX,XX @@ static void tlb_window_reset(CPUTLBDesc *desc, int64_t ns,
59
+ MMU_DATA_STORE * sizeof(uintptr_t));
39
desc->window_max_entries = max_entries;
60
QEMU_BUILD_BUG_ON(offsetof(CPUTLBEntry, addr_code) !=
61
- MMU_INST_FETCH * sizeof(uint64_t));
62
+ MMU_INST_FETCH * sizeof(uintptr_t));
63
64
-#if TARGET_LONG_BITS == 32
65
- /* Use qatomic_read, in case of addr_write; only care about low bits. */
66
- const uint32_t *ptr = (uint32_t *)&entry->addr_idx[access_type];
67
- ptr += HOST_BIG_ENDIAN;
68
- return qatomic_read(ptr);
69
-#else
70
- const uint64_t *ptr = &entry->addr_idx[access_type];
71
+ const uintptr_t *ptr = &entry->addr_idx[access_type];
72
/* ofs might correspond to .addr_write, so use qatomic_read */
73
return qatomic_read(ptr);
74
-#endif
40
}
75
}
41
76
42
+static void tb_jmp_cache_clear_page(CPUState *cpu, target_ulong page_addr)
77
static inline uint64_t tlb_addr_write(const CPUTLBEntry *entry)
43
+{
78
@@ -XXX,XX +XXX,XX @@ static void tlb_reset_dirty_range_locked(CPUTLBEntry *tlb_entry,
44
+ unsigned int i, i0 = tb_jmp_cache_hash_page(page_addr);
79
addr &= TARGET_PAGE_MASK;
45
+
80
addr += tlb_entry->addend;
46
+ for (i = 0; i < TB_JMP_PAGE_SIZE; i++) {
81
if ((addr - start) < length) {
47
+ qatomic_set(&cpu->tb_jmp_cache[i0 + i], NULL);
82
-#if TARGET_LONG_BITS == 32
48
+ }
83
- uint32_t *ptr_write = (uint32_t *)&tlb_entry->addr_write;
49
+}
84
- ptr_write += HOST_BIG_ENDIAN;
50
+
85
- qatomic_set(ptr_write, *ptr_write | TLB_NOTDIRTY);
51
+static void tb_flush_jmp_cache(CPUState *cpu, target_ulong addr)
86
-#else
52
+{
87
qatomic_set(&tlb_entry->addr_write,
53
+ /* Discard jump cache entries for any tb which might potentially
88
tlb_entry->addr_write | TLB_NOTDIRTY);
54
+ overlap the flushed page. */
89
-#endif
55
+ tb_jmp_cache_clear_page(cpu, addr - TARGET_PAGE_SIZE);
90
}
56
+ tb_jmp_cache_clear_page(cpu, addr);
91
}
57
+}
92
}
58
+
93
diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
59
/**
60
* tlb_mmu_resize_locked() - perform TLB resize bookkeeping; resize if necessary
61
* @desc: The CPUTLBDesc portion of the TLB
62
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
63
index XXXXXXX..XXXXXXX 100644
94
index XXXXXXX..XXXXXXX 100644
64
--- a/accel/tcg/translate-all.c
95
--- a/tcg/arm/tcg-target.c.inc
65
+++ b/accel/tcg/translate-all.c
96
+++ b/tcg/arm/tcg-target.c.inc
66
@@ -XXX,XX +XXX,XX @@ void cpu_io_recompile(CPUState *cpu, uintptr_t retaddr)
97
@@ -XXX,XX +XXX,XX @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
67
cpu_loop_exit_noexc(cpu);
98
* Add the tlb_table pointer, creating the CPUTLBEntry address in R1.
68
}
99
* Load the tlb comparator into R2 and the fast path addend into R1.
69
100
*/
70
-static void tb_jmp_cache_clear_page(CPUState *cpu, target_ulong page_addr)
101
- QEMU_BUILD_BUG_ON(HOST_BIG_ENDIAN);
71
-{
102
if (cmp_off == 0) {
72
- unsigned int i, i0 = tb_jmp_cache_hash_page(page_addr);
103
tcg_out_ld32_rwb(s, COND_AL, TCG_REG_R2, TCG_REG_R1, TCG_REG_R0);
73
-
104
} else {
74
- for (i = 0; i < TB_JMP_PAGE_SIZE; i++) {
105
diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc
75
- qatomic_set(&cpu->tb_jmp_cache[i0 + i], NULL);
106
index XXXXXXX..XXXXXXX 100644
76
- }
107
--- a/tcg/mips/tcg-target.c.inc
77
-}
108
+++ b/tcg/mips/tcg-target.c.inc
78
-
109
@@ -XXX,XX +XXX,XX @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
79
-void tb_flush_jmp_cache(CPUState *cpu, target_ulong addr)
110
/* Add the tlb_table pointer, creating the CPUTLBEntry address. */
80
-{
111
tcg_out_opc_reg(s, ALIAS_PADD, TCG_TMP3, TCG_TMP3, TCG_TMP1);
81
- /* Discard jump cache entries for any tb which might potentially
112
82
- overlap the flushed page. */
113
- if (TCG_TARGET_REG_BITS == 32 || addr_type == TCG_TYPE_I32) {
83
- tb_jmp_cache_clear_page(cpu, addr - TARGET_PAGE_SIZE);
114
- /* Load the (low half) tlb comparator. */
84
- tb_jmp_cache_clear_page(cpu, addr);
115
+ /* Load the tlb comparator. */
85
-}
116
+ if (TCG_TARGET_REG_BITS == 64 && addr_type == TCG_TYPE_I32) {
86
-
117
tcg_out_ld(s, TCG_TYPE_I32, TCG_TMP0, TCG_TMP3,
87
static void print_qht_statistics(struct qht_stats hst)
118
cmp_off + HOST_BIG_ENDIAN * 4);
88
{
119
} else {
89
uint32_t hgram_opts;
120
- tcg_out_ld(s, TCG_TYPE_I64, TCG_TMP0, TCG_TMP3, cmp_off);
121
+ tcg_out_ld(s, TCG_TYPE_REG, TCG_TMP0, TCG_TMP3, cmp_off);
122
}
123
124
- if (TCG_TARGET_REG_BITS == 64 || addr_type == TCG_TYPE_I32) {
125
- /* Load the tlb addend for the fast path. */
126
- tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP3, TCG_TMP3, add_off);
127
- }
128
+ /* Load the tlb addend for the fast path. */
129
+ tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP3, TCG_TMP3, add_off);
130
131
/*
132
* Mask the page bits, keeping the alignment bits to compare against.
133
diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc
134
index XXXXXXX..XXXXXXX 100644
135
--- a/tcg/ppc/tcg-target.c.inc
136
+++ b/tcg/ppc/tcg-target.c.inc
137
@@ -XXX,XX +XXX,XX @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
138
tcg_out32(s, AND | SAB(TCG_REG_TMP1, TCG_REG_TMP1, TCG_REG_R0));
139
140
/*
141
- * Load the (low part) TLB comparator into TMP2.
142
+ * Load the TLB comparator into TMP2.
143
* For 64-bit host, always load the entire 64-bit slot for simplicity.
144
* We will ignore the high bits with tcg_out_cmp(..., addr_type).
145
*/
146
- if (TCG_TARGET_REG_BITS == 64) {
147
- if (cmp_off == 0) {
148
- tcg_out32(s, LDUX | TAB(TCG_REG_TMP2,
149
- TCG_REG_TMP1, TCG_REG_TMP2));
150
- } else {
151
- tcg_out32(s, ADD | TAB(TCG_REG_TMP1,
152
- TCG_REG_TMP1, TCG_REG_TMP2));
153
- tcg_out_ld(s, TCG_TYPE_I64, TCG_REG_TMP2,
154
- TCG_REG_TMP1, cmp_off);
155
- }
156
- } else if (cmp_off == 0 && !HOST_BIG_ENDIAN) {
157
- tcg_out32(s, LWZUX | TAB(TCG_REG_TMP2,
158
- TCG_REG_TMP1, TCG_REG_TMP2));
159
+ if (cmp_off == 0) {
160
+ tcg_out32(s, (TCG_TARGET_REG_BITS == 64 ? LDUX : LWZUX)
161
+ | TAB(TCG_REG_TMP2, TCG_REG_TMP1, TCG_REG_TMP2));
162
} else {
163
tcg_out32(s, ADD | TAB(TCG_REG_TMP1, TCG_REG_TMP1, TCG_REG_TMP2));
164
- tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_TMP2, TCG_REG_TMP1,
165
- cmp_off + 4 * HOST_BIG_ENDIAN);
166
+ tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP2, TCG_REG_TMP1, cmp_off);
167
}
168
169
/*
90
--
170
--
91
2.25.1
171
2.43.0
92
172
93
173
diff view generated by jsdifflib
[PULL 04/10] tcg: Increase the static number of temporaries
[PULL 14/24] tcg: Introduce the 'z' constraint for a hardware zero register
1
This isn't a total or permanent solution to the problem of running
1
For loongarch, mips, riscv and sparc, a zero register is
2
out of temporaries, but it puts off the issue for a bit.
2
available all the time. For aarch64, register index 31
3
depends on context: sometimes it is the stack pointer,
4
and sometimes it is the zero register.
3
5
4
Make the assert in tcg_temp_alloc unconditional. If we do run out
6
Introduce a new general-purpose constraint which maps 0
5
of temps, this can fail much later as a weird SIGSEGV, due to the
7
to TCG_REG_ZERO, if defined. This differs from existing
6
buffer overrun of the temp array.
8
constant constraints in that const_arg[*] is recorded as
9
false, indicating that the value is in a register.
7
10
8
Remove the inlines from tcg_temp_alloc and tcg_global_alloc.
11
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
9
10
Buglink: https://bugs.launchpad.net/bugs/1912065
11
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
12
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
13
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
14
---
13
---
15
include/tcg/tcg.h | 2 +-
14
include/tcg/tcg.h | 3 ++-
16
tcg/tcg.c | 6 +++---
15
tcg/aarch64/tcg-target.h | 2 ++
17
2 files changed, 4 insertions(+), 4 deletions(-)
16
tcg/loongarch64/tcg-target.h | 2 ++
17
tcg/mips/tcg-target.h | 2 ++
18
tcg/riscv/tcg-target.h | 2 ++
19
tcg/sparc64/tcg-target.h | 3 ++-
20
tcg/tcg.c | 29 ++++++++++++++++++++++-------
21
docs/devel/tcg-ops.rst | 4 +++-
22
8 files changed, 37 insertions(+), 10 deletions(-)
18
23
19
diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h
24
diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h
20
index XXXXXXX..XXXXXXX 100644
25
index XXXXXXX..XXXXXXX 100644
21
--- a/include/tcg/tcg.h
26
--- a/include/tcg/tcg.h
22
+++ b/include/tcg/tcg.h
27
+++ b/include/tcg/tcg.h
23
@@ -XXX,XX +XXX,XX @@ typedef struct TCGPool {
28
@@ -XXX,XX +XXX,XX @@ void tb_target_set_jmp_target(const TranslationBlock *, int,
24
29
25
#define TCG_POOL_CHUNK_SIZE 32768
30
void tcg_set_frame(TCGContext *s, TCGReg reg, intptr_t start, intptr_t size);
26
31
27
-#define TCG_MAX_TEMPS 512
32
-#define TCG_CT_CONST 1 /* any constant of register size */
28
+#define TCG_MAX_TEMPS 1024
33
+#define TCG_CT_CONST 1 /* any constant of register size */
29
#define TCG_MAX_INSNS 512
34
+#define TCG_CT_REG_ZERO 2 /* zero, in TCG_REG_ZERO */
30
35
31
/* when the size of the arguments of a called function is smaller than
36
typedef struct TCGArgConstraint {
37
unsigned ct : 16;
38
diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h
39
index XXXXXXX..XXXXXXX 100644
40
--- a/tcg/aarch64/tcg-target.h
41
+++ b/tcg/aarch64/tcg-target.h
42
@@ -XXX,XX +XXX,XX @@ typedef enum {
43
TCG_AREG0 = TCG_REG_X19,
44
} TCGReg;
45
46
+#define TCG_REG_ZERO TCG_REG_XZR
47
+
48
#define TCG_TARGET_NB_REGS 64
49
50
#endif /* AARCH64_TCG_TARGET_H */
51
diff --git a/tcg/loongarch64/tcg-target.h b/tcg/loongarch64/tcg-target.h
52
index XXXXXXX..XXXXXXX 100644
53
--- a/tcg/loongarch64/tcg-target.h
54
+++ b/tcg/loongarch64/tcg-target.h
55
@@ -XXX,XX +XXX,XX @@ typedef enum {
56
TCG_VEC_TMP0 = TCG_REG_V23,
57
} TCGReg;
58
59
+#define TCG_REG_ZERO TCG_REG_ZERO
60
+
61
#endif /* LOONGARCH_TCG_TARGET_H */
62
diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h
63
index XXXXXXX..XXXXXXX 100644
64
--- a/tcg/mips/tcg-target.h
65
+++ b/tcg/mips/tcg-target.h
66
@@ -XXX,XX +XXX,XX @@ typedef enum {
67
TCG_AREG0 = TCG_REG_S8,
68
} TCGReg;
69
70
+#define TCG_REG_ZERO TCG_REG_ZERO
71
+
72
#endif
73
diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h
74
index XXXXXXX..XXXXXXX 100644
75
--- a/tcg/riscv/tcg-target.h
76
+++ b/tcg/riscv/tcg-target.h
77
@@ -XXX,XX +XXX,XX @@ typedef enum {
78
TCG_REG_TMP2 = TCG_REG_T4,
79
} TCGReg;
80
81
+#define TCG_REG_ZERO TCG_REG_ZERO
82
+
83
#endif
84
diff --git a/tcg/sparc64/tcg-target.h b/tcg/sparc64/tcg-target.h
85
index XXXXXXX..XXXXXXX 100644
86
--- a/tcg/sparc64/tcg-target.h
87
+++ b/tcg/sparc64/tcg-target.h
88
@@ -XXX,XX +XXX,XX @@ typedef enum {
89
TCG_REG_I7,
90
} TCGReg;
91
92
-#define TCG_AREG0 TCG_REG_I0
93
+#define TCG_AREG0 TCG_REG_I0
94
+#define TCG_REG_ZERO TCG_REG_G0
95
96
#endif
32
diff --git a/tcg/tcg.c b/tcg/tcg.c
97
diff --git a/tcg/tcg.c b/tcg/tcg.c
33
index XXXXXXX..XXXXXXX 100644
98
index XXXXXXX..XXXXXXX 100644
34
--- a/tcg/tcg.c
99
--- a/tcg/tcg.c
35
+++ b/tcg/tcg.c
100
+++ b/tcg/tcg.c
36
@@ -XXX,XX +XXX,XX @@ void tcg_func_start(TCGContext *s)
101
@@ -XXX,XX +XXX,XX @@ static void process_constraint_sets(void)
37
QSIMPLEQ_INIT(&s->labels);
102
case 'i':
38
}
103
args_ct[i].ct |= TCG_CT_CONST;
39
104
break;
40
-static inline TCGTemp *tcg_temp_alloc(TCGContext *s)
105
+#ifdef TCG_REG_ZERO
41
+static TCGTemp *tcg_temp_alloc(TCGContext *s)
106
+ case 'z':
42
{
107
+ args_ct[i].ct |= TCG_CT_REG_ZERO;
43
int n = s->nb_temps++;
108
+ break;
44
- tcg_debug_assert(n < TCG_MAX_TEMPS);
109
+#endif
45
+ g_assert(n < TCG_MAX_TEMPS);
110
46
return memset(&s->temps[n], 0, sizeof(TCGTemp));
111
/* Include all of the target-specific constraints. */
47
}
112
48
113
@@ -XXX,XX +XXX,XX @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
49
-static inline TCGTemp *tcg_global_alloc(TCGContext *s)
114
arg_ct = &args_ct[i];
50
+static TCGTemp *tcg_global_alloc(TCGContext *s)
115
ts = arg_temp(arg);
51
{
116
52
TCGTemp *ts;
117
- if (ts->val_type == TEMP_VAL_CONST
118
- && tcg_target_const_match(ts->val, arg_ct->ct, ts->type,
119
- op_cond, TCGOP_VECE(op))) {
120
- /* constant is OK for instruction */
121
- const_args[i] = 1;
122
- new_args[i] = ts->val;
123
- continue;
124
+ if (ts->val_type == TEMP_VAL_CONST) {
125
+#ifdef TCG_REG_ZERO
126
+ if (ts->val == 0 && (arg_ct->ct & TCG_CT_REG_ZERO)) {
127
+ /* Hardware zero register: indicate register via non-const. */
128
+ const_args[i] = 0;
129
+ new_args[i] = TCG_REG_ZERO;
130
+ continue;
131
+ }
132
+#endif
133
+
134
+ if (tcg_target_const_match(ts->val, arg_ct->ct, ts->type,
135
+ op_cond, TCGOP_VECE(op))) {
136
+ /* constant is OK for instruction */
137
+ const_args[i] = 1;
138
+ new_args[i] = ts->val;
139
+ continue;
140
+ }
141
}
142
143
reg = ts->reg;
144
diff --git a/docs/devel/tcg-ops.rst b/docs/devel/tcg-ops.rst
145
index XXXXXXX..XXXXXXX 100644
146
--- a/docs/devel/tcg-ops.rst
147
+++ b/docs/devel/tcg-ops.rst
148
@@ -XXX,XX +XXX,XX @@ operation uses a constant input constraint which does not allow all
149
constants, it must also accept registers in order to have a fallback.
150
The constraint '``i``' is defined generically to accept any constant.
151
The constraint '``r``' is not defined generically, but is consistently
152
-used by each backend to indicate all registers.
153
+used by each backend to indicate all registers. If ``TCG_REG_ZERO``
154
+is defined by the backend, the constraint '``z``' is defined generically
155
+to map constant 0 to the hardware zero register.
156
157
The movi_i32 and movi_i64 operations must accept any constants.
53
158
54
--
159
--
55
2.25.1
160
2.43.0
56
161
57
162
diff view generated by jsdifflib
New patch
[PULL 15/24] tcg/aarch64: Use 'z' constraint
1
Note that 'Z' is still used for addsub2.
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
---
5
tcg/aarch64/tcg-target-con-set.h | 12 ++++-----
6
tcg/aarch64/tcg-target.c.inc | 46 ++++++++++++++------------------
7
2 files changed, 26 insertions(+), 32 deletions(-)
8
9
diff --git a/tcg/aarch64/tcg-target-con-set.h b/tcg/aarch64/tcg-target-con-set.h
10
index XXXXXXX..XXXXXXX 100644
11
--- a/tcg/aarch64/tcg-target-con-set.h
12
+++ b/tcg/aarch64/tcg-target-con-set.h
13
@@ -XXX,XX +XXX,XX @@
14
*/
15
C_O0_I1(r)
16
C_O0_I2(r, rC)
17
-C_O0_I2(rZ, r)
18
+C_O0_I2(rz, r)
19
C_O0_I2(w, r)
20
-C_O0_I3(rZ, rZ, r)
21
+C_O0_I3(rz, rz, r)
22
C_O1_I1(r, r)
23
C_O1_I1(w, r)
24
C_O1_I1(w, w)
25
C_O1_I1(w, wr)
26
-C_O1_I2(r, 0, rZ)
27
+C_O1_I2(r, 0, rz)
28
C_O1_I2(r, r, r)
29
C_O1_I2(r, r, rA)
30
C_O1_I2(r, r, rAL)
31
C_O1_I2(r, r, rC)
32
C_O1_I2(r, r, ri)
33
C_O1_I2(r, r, rL)
34
-C_O1_I2(r, rZ, rZ)
35
+C_O1_I2(r, rz, rz)
36
C_O1_I2(w, 0, w)
37
C_O1_I2(w, w, w)
38
C_O1_I2(w, w, wN)
39
C_O1_I2(w, w, wO)
40
C_O1_I2(w, w, wZ)
41
C_O1_I3(w, w, w, w)
42
-C_O1_I4(r, r, rC, rZ, rZ)
43
+C_O1_I4(r, r, rC, rz, rz)
44
C_O2_I1(r, r, r)
45
-C_O2_I4(r, r, rZ, rZ, rA, rMZ)
46
+C_O2_I4(r, r, rz, rz, rA, rMZ)
47
diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc
48
index XXXXXXX..XXXXXXX 100644
49
--- a/tcg/aarch64/tcg-target.c.inc
50
+++ b/tcg/aarch64/tcg-target.c.inc
51
@@ -XXX,XX +XXX,XX @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType ext,
52
TCGArg a2 = args[2];
53
int c2 = const_args[2];
54
55
- /* Some operands are defined with "rZ" constraint, a register or
56
- the zero register. These need not actually test args[I] == 0. */
57
-#define REG0(I) (const_args[I] ? TCG_REG_XZR : (TCGReg)args[I])
58
-
59
switch (opc) {
60
case INDEX_op_goto_ptr:
61
tcg_out_insn(s, 3207, BR, a0);
62
@@ -XXX,XX +XXX,XX @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType ext,
63
64
case INDEX_op_st8_i32:
65
case INDEX_op_st8_i64:
66
- tcg_out_ldst(s, I3312_STRB, REG0(0), a1, a2, 0);
67
+ tcg_out_ldst(s, I3312_STRB, a0, a1, a2, 0);
68
break;
69
case INDEX_op_st16_i32:
70
case INDEX_op_st16_i64:
71
- tcg_out_ldst(s, I3312_STRH, REG0(0), a1, a2, 1);
72
+ tcg_out_ldst(s, I3312_STRH, a0, a1, a2, 1);
73
break;
74
case INDEX_op_st_i32:
75
case INDEX_op_st32_i64:
76
- tcg_out_ldst(s, I3312_STRW, REG0(0), a1, a2, 2);
77
+ tcg_out_ldst(s, I3312_STRW, a0, a1, a2, 2);
78
break;
79
case INDEX_op_st_i64:
80
- tcg_out_ldst(s, I3312_STRX, REG0(0), a1, a2, 3);
81
+ tcg_out_ldst(s, I3312_STRX, a0, a1, a2, 3);
82
break;
83
84
case INDEX_op_add_i32:
85
@@ -XXX,XX +XXX,XX @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType ext,
86
/* FALLTHRU */
87
case INDEX_op_movcond_i64:
88
tcg_out_cmp(s, ext, args[5], a1, a2, c2);
89
- tcg_out_insn(s, 3506, CSEL, ext, a0, REG0(3), REG0(4), args[5]);
90
+ tcg_out_insn(s, 3506, CSEL, ext, a0, args[3], args[4], args[5]);
91
break;
92
93
case INDEX_op_qemu_ld_i32:
94
@@ -XXX,XX +XXX,XX @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType ext,
95
break;
96
case INDEX_op_qemu_st_i32:
97
case INDEX_op_qemu_st_i64:
98
- tcg_out_qemu_st(s, REG0(0), a1, a2, ext);
99
+ tcg_out_qemu_st(s, a0, a1, a2, ext);
100
break;
101
case INDEX_op_qemu_ld_i128:
102
tcg_out_qemu_ldst_i128(s, a0, a1, a2, args[3], true);
103
break;
104
case INDEX_op_qemu_st_i128:
105
- tcg_out_qemu_ldst_i128(s, REG0(0), REG0(1), a2, args[3], false);
106
+ tcg_out_qemu_ldst_i128(s, a0, a1, a2, args[3], false);
107
break;
108
109
case INDEX_op_bswap64_i64:
110
@@ -XXX,XX +XXX,XX @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType ext,
111
112
case INDEX_op_deposit_i64:
113
case INDEX_op_deposit_i32:
114
- tcg_out_dep(s, ext, a0, REG0(2), args[3], args[4]);
115
+ tcg_out_dep(s, ext, a0, a2, args[3], args[4]);
116
break;
117
118
case INDEX_op_extract_i64:
119
@@ -XXX,XX +XXX,XX @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType ext,
120
121
case INDEX_op_extract2_i64:
122
case INDEX_op_extract2_i32:
123
- tcg_out_extr(s, ext, a0, REG0(2), REG0(1), args[3]);
124
+ tcg_out_extr(s, ext, a0, a2, a1, args[3]);
125
break;
126
127
case INDEX_op_add2_i32:
128
- tcg_out_addsub2(s, TCG_TYPE_I32, a0, a1, REG0(2), REG0(3),
129
+ tcg_out_addsub2(s, TCG_TYPE_I32, a0, a1, a2, args[3],
130
(int32_t)args[4], args[5], const_args[4],
131
const_args[5], false);
132
break;
133
case INDEX_op_add2_i64:
134
- tcg_out_addsub2(s, TCG_TYPE_I64, a0, a1, REG0(2), REG0(3), args[4],
135
+ tcg_out_addsub2(s, TCG_TYPE_I64, a0, a1, a2, args[3], args[4],
136
args[5], const_args[4], const_args[5], false);
137
break;
138
case INDEX_op_sub2_i32:
139
- tcg_out_addsub2(s, TCG_TYPE_I32, a0, a1, REG0(2), REG0(3),
140
+ tcg_out_addsub2(s, TCG_TYPE_I32, a0, a1, a2, args[3],
141
(int32_t)args[4], args[5], const_args[4],
142
const_args[5], true);
143
break;
144
case INDEX_op_sub2_i64:
145
- tcg_out_addsub2(s, TCG_TYPE_I64, a0, a1, REG0(2), REG0(3), args[4],
146
+ tcg_out_addsub2(s, TCG_TYPE_I64, a0, a1, a2, args[3], args[4],
147
args[5], const_args[4], const_args[5], true);
148
break;
149
150
@@ -XXX,XX +XXX,XX @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType ext,
151
default:
152
g_assert_not_reached();
153
}
154
-
155
-#undef REG0
156
}
157
158
static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
159
@@ -XXX,XX +XXX,XX @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
160
case INDEX_op_st16_i64:
161
case INDEX_op_st32_i64:
162
case INDEX_op_st_i64:
163
- return C_O0_I2(rZ, r);
164
+ return C_O0_I2(rz, r);
165
166
case INDEX_op_add_i32:
167
case INDEX_op_add_i64:
168
@@ -XXX,XX +XXX,XX @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
169
170
case INDEX_op_movcond_i32:
171
case INDEX_op_movcond_i64:
172
- return C_O1_I4(r, r, rC, rZ, rZ);
173
+ return C_O1_I4(r, r, rC, rz, rz);
174
175
case INDEX_op_qemu_ld_i32:
176
case INDEX_op_qemu_ld_i64:
177
@@ -XXX,XX +XXX,XX @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
178
return C_O2_I1(r, r, r);
179
case INDEX_op_qemu_st_i32:
180
case INDEX_op_qemu_st_i64:
181
- return C_O0_I2(rZ, r);
182
+ return C_O0_I2(rz, r);
183
case INDEX_op_qemu_st_i128:
184
- return C_O0_I3(rZ, rZ, r);
185
+ return C_O0_I3(rz, rz, r);
186
187
case INDEX_op_deposit_i32:
188
case INDEX_op_deposit_i64:
189
- return C_O1_I2(r, 0, rZ);
190
+ return C_O1_I2(r, 0, rz);
191
192
case INDEX_op_extract2_i32:
193
case INDEX_op_extract2_i64:
194
- return C_O1_I2(r, rZ, rZ);
195
+ return C_O1_I2(r, rz, rz);
196
197
case INDEX_op_add2_i32:
198
case INDEX_op_add2_i64:
199
case INDEX_op_sub2_i32:
200
case INDEX_op_sub2_i64:
201
- return C_O2_I4(r, r, rZ, rZ, rA, rMZ);
202
+ return C_O2_I4(r, r, rz, rz, rA, rMZ);
203
204
case INDEX_op_add_vec:
205
case INDEX_op_sub_vec:
206
--
207
2.43.0
diff view generated by jsdifflib
[PULL 07/10] accel/tcg: Restrict tb_gen_code() from other accelerators
[PULL 16/24] tcg/loongarch64: Use 'z' constraint
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
Replace target-specific 'Z' with generic 'z'.
2
2
3
tb_gen_code() is only called within TCG accelerator, declare it locally.
3
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
4
5
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
6
Message-Id: <20210117164813.4101761-4-f4bug@amsat.org>
7
[rth: Adjust vs changed tb_flush_jmp_cache patch.]
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
---
5
---
10
accel/tcg/internal.h | 18 ++++++++++++++++++
6
tcg/loongarch64/tcg-target-con-set.h | 15 ++++++-------
11
include/exec/exec-all.h | 5 -----
7
tcg/loongarch64/tcg-target-con-str.h | 1 -
12
accel/tcg/cpu-exec.c | 1 +
8
tcg/loongarch64/tcg-target.c.inc | 32 ++++++++++++----------------
13
accel/tcg/translate-all.c | 1 +
9
3 files changed, 21 insertions(+), 27 deletions(-)
14
4 files changed, 20 insertions(+), 5 deletions(-)
15
create mode 100644 accel/tcg/internal.h
16
10
17
diff --git a/accel/tcg/internal.h b/accel/tcg/internal.h
11
diff --git a/tcg/loongarch64/tcg-target-con-set.h b/tcg/loongarch64/tcg-target-con-set.h
18
new file mode 100644
12
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX
13
--- a/tcg/loongarch64/tcg-target-con-set.h
20
--- /dev/null
14
+++ b/tcg/loongarch64/tcg-target-con-set.h
21
+++ b/accel/tcg/internal.h
22
@@ -XXX,XX +XXX,XX @@
15
@@ -XXX,XX +XXX,XX @@
23
+/*
16
* tcg-target-con-str.h; the constraint combination is inclusive or.
24
+ * Internal execution defines for qemu
17
*/
25
+ *
18
C_O0_I1(r)
26
+ * Copyright (c) 2003 Fabrice Bellard
19
-C_O0_I2(rZ, r)
27
+ *
20
-C_O0_I2(rZ, rZ)
28
+ * SPDX-License-Identifier: LGPL-2.1-or-later
21
+C_O0_I2(rz, r)
29
+ */
22
+C_O0_I2(rz, rz)
30
+
23
C_O0_I2(w, r)
31
+#ifndef ACCEL_TCG_INTERNAL_H
24
C_O0_I3(r, r, r)
32
+#define ACCEL_TCG_INTERNAL_H
25
C_O1_I1(r, r)
33
+
26
@@ -XXX,XX +XXX,XX @@ C_O1_I2(r, r, rI)
34
+#include "exec/exec-all.h"
27
C_O1_I2(r, r, rJ)
35
+
28
C_O1_I2(r, r, rU)
36
+TranslationBlock *tb_gen_code(CPUState *cpu, target_ulong pc,
29
C_O1_I2(r, r, rW)
37
+ target_ulong cs_base, uint32_t flags,
30
-C_O1_I2(r, r, rZ)
38
+ int cflags);
31
-C_O1_I2(r, 0, rZ)
39
+
32
-C_O1_I2(r, rZ, ri)
40
+#endif /* ACCEL_TCG_INTERNAL_H */
33
-C_O1_I2(r, rZ, rJ)
41
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
34
-C_O1_I2(r, rZ, rZ)
35
+C_O1_I2(r, 0, rz)
36
+C_O1_I2(r, rz, ri)
37
+C_O1_I2(r, rz, rJ)
38
+C_O1_I2(r, rz, rz)
39
C_O1_I2(w, w, w)
40
C_O1_I2(w, w, wM)
41
C_O1_I2(w, w, wA)
42
C_O1_I3(w, w, w, w)
43
-C_O1_I4(r, rZ, rJ, rZ, rZ)
44
+C_O1_I4(r, rz, rJ, rz, rz)
45
C_N2_I1(r, r, r)
46
diff --git a/tcg/loongarch64/tcg-target-con-str.h b/tcg/loongarch64/tcg-target-con-str.h
42
index XXXXXXX..XXXXXXX 100644
47
index XXXXXXX..XXXXXXX 100644
43
--- a/include/exec/exec-all.h
48
--- a/tcg/loongarch64/tcg-target-con-str.h
44
+++ b/include/exec/exec-all.h
49
+++ b/tcg/loongarch64/tcg-target-con-str.h
45
@@ -XXX,XX +XXX,XX @@ bool cpu_restore_state(CPUState *cpu, uintptr_t searched_pc, bool will_exit);
50
@@ -XXX,XX +XXX,XX @@ REGS('w', ALL_VECTOR_REGS)
46
51
CONST('I', TCG_CT_CONST_S12)
47
void QEMU_NORETURN cpu_loop_exit_noexc(CPUState *cpu);
52
CONST('J', TCG_CT_CONST_S32)
48
void QEMU_NORETURN cpu_io_recompile(CPUState *cpu, uintptr_t retaddr);
53
CONST('U', TCG_CT_CONST_U12)
49
-TranslationBlock *tb_gen_code(CPUState *cpu,
54
-CONST('Z', TCG_CT_CONST_ZERO)
50
- target_ulong pc, target_ulong cs_base,
55
CONST('C', TCG_CT_CONST_C12)
51
- uint32_t flags,
56
CONST('W', TCG_CT_CONST_WSZ)
52
- int cflags);
57
CONST('M', TCG_CT_CONST_VCMP)
53
-
58
diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc
54
void QEMU_NORETURN cpu_loop_exit(CPUState *cpu);
55
void QEMU_NORETURN cpu_loop_exit_restore(CPUState *cpu, uintptr_t pc);
56
void QEMU_NORETURN cpu_loop_exit_atomic(CPUState *cpu, uintptr_t pc);
57
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
58
index XXXXXXX..XXXXXXX 100644
59
index XXXXXXX..XXXXXXX 100644
59
--- a/accel/tcg/cpu-exec.c
60
--- a/tcg/loongarch64/tcg-target.c.inc
60
+++ b/accel/tcg/cpu-exec.c
61
+++ b/tcg/loongarch64/tcg-target.c.inc
61
@@ -XXX,XX +XXX,XX @@
62
@@ -XXX,XX +XXX,XX @@ static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot)
62
#include "exec/cpu-all.h"
63
63
#include "sysemu/cpu-timers.h"
64
#define TCG_GUEST_BASE_REG TCG_REG_S1
64
#include "sysemu/replay.h"
65
65
+#include "internal.h"
66
-#define TCG_CT_CONST_ZERO 0x100
66
67
-#define TCG_CT_CONST_S12 0x200
67
/* -icount align implementation. */
68
-#define TCG_CT_CONST_S32 0x400
68
69
-#define TCG_CT_CONST_U12 0x800
69
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
70
-#define TCG_CT_CONST_C12 0x1000
70
index XXXXXXX..XXXXXXX 100644
71
-#define TCG_CT_CONST_WSZ 0x2000
71
--- a/accel/tcg/translate-all.c
72
-#define TCG_CT_CONST_VCMP 0x4000
72
+++ b/accel/tcg/translate-all.c
73
-#define TCG_CT_CONST_VADD 0x8000
73
@@ -XXX,XX +XXX,XX @@
74
+#define TCG_CT_CONST_S12 0x100
74
#include "sysemu/cpu-timers.h"
75
+#define TCG_CT_CONST_S32 0x200
75
#include "sysemu/tcg.h"
76
+#define TCG_CT_CONST_U12 0x400
76
#include "qapi/error.h"
77
+#define TCG_CT_CONST_C12 0x800
77
+#include "internal.h"
78
+#define TCG_CT_CONST_WSZ 0x1000
78
79
+#define TCG_CT_CONST_VCMP 0x2000
79
/* #define DEBUG_TB_INVALIDATE */
80
+#define TCG_CT_CONST_VADD 0x4000
80
/* #define DEBUG_TB_FLUSH */
81
82
#define ALL_GENERAL_REGS MAKE_64BIT_MASK(0, 32)
83
#define ALL_VECTOR_REGS MAKE_64BIT_MASK(32, 32)
84
@@ -XXX,XX +XXX,XX @@ static bool tcg_target_const_match(int64_t val, int ct,
85
if (ct & TCG_CT_CONST) {
86
return true;
87
}
88
- if ((ct & TCG_CT_CONST_ZERO) && val == 0) {
89
- return true;
90
- }
91
if ((ct & TCG_CT_CONST_S12) && val == sextreg(val, 0, 12)) {
92
return true;
93
}
94
@@ -XXX,XX +XXX,XX @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
95
case INDEX_op_st_i64:
96
case INDEX_op_qemu_st_i32:
97
case INDEX_op_qemu_st_i64:
98
- return C_O0_I2(rZ, r);
99
+ return C_O0_I2(rz, r);
100
101
case INDEX_op_qemu_ld_i128:
102
return C_N2_I1(r, r, r);
103
@@ -XXX,XX +XXX,XX @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
104
105
case INDEX_op_brcond_i32:
106
case INDEX_op_brcond_i64:
107
- return C_O0_I2(rZ, rZ);
108
+ return C_O0_I2(rz, rz);
109
110
case INDEX_op_ext8s_i32:
111
case INDEX_op_ext8s_i64:
112
@@ -XXX,XX +XXX,XX @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
113
case INDEX_op_deposit_i32:
114
case INDEX_op_deposit_i64:
115
/* Must deposit into the same register as input */
116
- return C_O1_I2(r, 0, rZ);
117
+ return C_O1_I2(r, 0, rz);
118
119
case INDEX_op_sub_i32:
120
case INDEX_op_setcond_i32:
121
- return C_O1_I2(r, rZ, ri);
122
+ return C_O1_I2(r, rz, ri);
123
case INDEX_op_sub_i64:
124
case INDEX_op_setcond_i64:
125
- return C_O1_I2(r, rZ, rJ);
126
+ return C_O1_I2(r, rz, rJ);
127
128
case INDEX_op_mul_i32:
129
case INDEX_op_mul_i64:
130
@@ -XXX,XX +XXX,XX @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
131
case INDEX_op_rem_i64:
132
case INDEX_op_remu_i32:
133
case INDEX_op_remu_i64:
134
- return C_O1_I2(r, rZ, rZ);
135
+ return C_O1_I2(r, rz, rz);
136
137
case INDEX_op_movcond_i32:
138
case INDEX_op_movcond_i64:
139
- return C_O1_I4(r, rZ, rJ, rZ, rZ);
140
+ return C_O1_I4(r, rz, rJ, rz, rz);
141
142
case INDEX_op_ld_vec:
143
case INDEX_op_dupm_vec:
81
--
144
--
82
2.25.1
145
2.43.0
83
146
84
147
diff view generated by jsdifflib
[PULL 05/10] accel/tcg: Make cpu_gen_init() static
[PULL 17/24] tcg/mips: Use 'z' constraint
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
Replace target-specific 'Z' with generic 'z'.
2
2
3
cpu_gen_init() is TCG specific, only used in tcg/translate-all.c.
3
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
4
No need to export it to other accelerators, declare it statically.
5
6
Reviewed-by: Claudio Fontana <cfontana@suse.de>
7
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Message-Id: <20210117164813.4101761-2-f4bug@amsat.org>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
---
5
---
11
include/exec/exec-all.h | 2 --
6
tcg/mips/tcg-target-con-set.h | 26 ++++++++++-----------
12
accel/tcg/translate-all.c | 2 +-
7
tcg/mips/tcg-target-con-str.h | 1 -
13
2 files changed, 1 insertion(+), 3 deletions(-)
8
tcg/mips/tcg-target.c.inc | 44 ++++++++++++++---------------------
9
3 files changed, 31 insertions(+), 40 deletions(-)
14
10
15
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
11
diff --git a/tcg/mips/tcg-target-con-set.h b/tcg/mips/tcg-target-con-set.h
16
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
17
--- a/include/exec/exec-all.h
13
--- a/tcg/mips/tcg-target-con-set.h
18
+++ b/include/exec/exec-all.h
14
+++ b/tcg/mips/tcg-target-con-set.h
19
@@ -XXX,XX +XXX,XX @@ void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int max_insns);
15
@@ -XXX,XX +XXX,XX @@
20
void restore_state_to_opc(CPUArchState *env, TranslationBlock *tb,
16
* tcg-target-con-str.h; the constraint combination is inclusive or.
21
target_ulong *data);
17
*/
22
18
C_O0_I1(r)
23
-void cpu_gen_init(void);
19
-C_O0_I2(rZ, r)
24
-
20
-C_O0_I2(rZ, rZ)
25
/**
21
-C_O0_I3(rZ, r, r)
26
* cpu_restore_state:
22
-C_O0_I3(rZ, rZ, r)
27
* @cpu: the vCPU state is to be restore to
23
-C_O0_I4(rZ, rZ, rZ, rZ)
28
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
24
-C_O0_I4(rZ, rZ, r, r)
25
+C_O0_I2(rz, r)
26
+C_O0_I2(rz, rz)
27
+C_O0_I3(rz, r, r)
28
+C_O0_I3(rz, rz, r)
29
+C_O0_I4(rz, rz, rz, rz)
30
+C_O0_I4(rz, rz, r, r)
31
C_O1_I1(r, r)
32
-C_O1_I2(r, 0, rZ)
33
+C_O1_I2(r, 0, rz)
34
C_O1_I2(r, r, r)
35
C_O1_I2(r, r, ri)
36
C_O1_I2(r, r, rI)
37
C_O1_I2(r, r, rIK)
38
C_O1_I2(r, r, rJ)
39
-C_O1_I2(r, r, rWZ)
40
-C_O1_I2(r, rZ, rN)
41
-C_O1_I2(r, rZ, rZ)
42
-C_O1_I4(r, rZ, rZ, rZ, 0)
43
-C_O1_I4(r, rZ, rZ, rZ, rZ)
44
+C_O1_I2(r, r, rzW)
45
+C_O1_I2(r, rz, rN)
46
+C_O1_I2(r, rz, rz)
47
+C_O1_I4(r, rz, rz, rz, 0)
48
+C_O1_I4(r, rz, rz, rz, rz)
49
C_O2_I1(r, r, r)
50
C_O2_I2(r, r, r, r)
51
-C_O2_I4(r, r, rZ, rZ, rN, rN)
52
+C_O2_I4(r, r, rz, rz, rN, rN)
53
diff --git a/tcg/mips/tcg-target-con-str.h b/tcg/mips/tcg-target-con-str.h
29
index XXXXXXX..XXXXXXX 100644
54
index XXXXXXX..XXXXXXX 100644
30
--- a/accel/tcg/translate-all.c
55
--- a/tcg/mips/tcg-target-con-str.h
31
+++ b/accel/tcg/translate-all.c
56
+++ b/tcg/mips/tcg-target-con-str.h
32
@@ -XXX,XX +XXX,XX @@ static void page_table_config_init(void)
57
@@ -XXX,XX +XXX,XX @@ CONST('J', TCG_CT_CONST_S16)
33
assert(v_l2_levels >= 0);
58
CONST('K', TCG_CT_CONST_P2M1)
59
CONST('N', TCG_CT_CONST_N16)
60
CONST('W', TCG_CT_CONST_WSZ)
61
-CONST('Z', TCG_CT_CONST_ZERO)
62
diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc
63
index XXXXXXX..XXXXXXX 100644
64
--- a/tcg/mips/tcg-target.c.inc
65
+++ b/tcg/mips/tcg-target.c.inc
66
@@ -XXX,XX +XXX,XX @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
67
g_assert_not_reached();
34
}
68
}
35
69
36
-void cpu_gen_init(void)
70
-#define TCG_CT_CONST_ZERO 0x100
37
+static void cpu_gen_init(void)
71
-#define TCG_CT_CONST_U16 0x200 /* Unsigned 16-bit: 0 - 0xffff. */
72
-#define TCG_CT_CONST_S16 0x400 /* Signed 16-bit: -32768 - 32767 */
73
-#define TCG_CT_CONST_P2M1 0x800 /* Power of 2 minus 1. */
74
-#define TCG_CT_CONST_N16 0x1000 /* "Negatable" 16-bit: -32767 - 32767 */
75
-#define TCG_CT_CONST_WSZ 0x2000 /* word size */
76
+#define TCG_CT_CONST_U16 0x100 /* Unsigned 16-bit: 0 - 0xffff. */
77
+#define TCG_CT_CONST_S16 0x200 /* Signed 16-bit: -32768 - 32767 */
78
+#define TCG_CT_CONST_P2M1 0x400 /* Power of 2 minus 1. */
79
+#define TCG_CT_CONST_N16 0x800 /* "Negatable" 16-bit: -32767 - 32767 */
80
+#define TCG_CT_CONST_WSZ 0x1000 /* word size */
81
82
#define ALL_GENERAL_REGS 0xffffffffu
83
84
@@ -XXX,XX +XXX,XX @@ static bool tcg_target_const_match(int64_t val, int ct,
38
{
85
{
39
tcg_context_init(&tcg_init_ctx);
86
if (ct & TCG_CT_CONST) {
40
}
87
return 1;
88
- } else if ((ct & TCG_CT_CONST_ZERO) && val == 0) {
89
- return 1;
90
} else if ((ct & TCG_CT_CONST_U16) && val == (uint16_t)val) {
91
return 1;
92
} else if ((ct & TCG_CT_CONST_S16) && val == (int16_t)val) {
93
@@ -XXX,XX +XXX,XX @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
94
TCGArg a0, a1, a2;
95
int c2;
96
97
- /*
98
- * Note that many operands use the constraint set "rZ".
99
- * We make use of the fact that 0 is the ZERO register,
100
- * and hence such cases need not check for const_args.
101
- */
102
a0 = args[0];
103
a1 = args[1];
104
a2 = args[2];
105
@@ -XXX,XX +XXX,XX @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
106
case INDEX_op_st16_i64:
107
case INDEX_op_st32_i64:
108
case INDEX_op_st_i64:
109
- return C_O0_I2(rZ, r);
110
+ return C_O0_I2(rz, r);
111
112
case INDEX_op_add_i32:
113
case INDEX_op_add_i64:
114
return C_O1_I2(r, r, rJ);
115
case INDEX_op_sub_i32:
116
case INDEX_op_sub_i64:
117
- return C_O1_I2(r, rZ, rN);
118
+ return C_O1_I2(r, rz, rN);
119
case INDEX_op_mul_i32:
120
case INDEX_op_mulsh_i32:
121
case INDEX_op_muluh_i32:
122
@@ -XXX,XX +XXX,XX @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
123
case INDEX_op_remu_i64:
124
case INDEX_op_nor_i64:
125
case INDEX_op_setcond_i64:
126
- return C_O1_I2(r, rZ, rZ);
127
+ return C_O1_I2(r, rz, rz);
128
case INDEX_op_muls2_i32:
129
case INDEX_op_mulu2_i32:
130
case INDEX_op_muls2_i64:
131
@@ -XXX,XX +XXX,XX @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
132
return C_O1_I2(r, r, ri);
133
case INDEX_op_clz_i32:
134
case INDEX_op_clz_i64:
135
- return C_O1_I2(r, r, rWZ);
136
+ return C_O1_I2(r, r, rzW);
137
138
case INDEX_op_deposit_i32:
139
case INDEX_op_deposit_i64:
140
- return C_O1_I2(r, 0, rZ);
141
+ return C_O1_I2(r, 0, rz);
142
case INDEX_op_brcond_i32:
143
case INDEX_op_brcond_i64:
144
- return C_O0_I2(rZ, rZ);
145
+ return C_O0_I2(rz, rz);
146
case INDEX_op_movcond_i32:
147
case INDEX_op_movcond_i64:
148
return (use_mips32r6_instructions
149
- ? C_O1_I4(r, rZ, rZ, rZ, rZ)
150
- : C_O1_I4(r, rZ, rZ, rZ, 0));
151
+ ? C_O1_I4(r, rz, rz, rz, rz)
152
+ : C_O1_I4(r, rz, rz, rz, 0));
153
case INDEX_op_add2_i32:
154
case INDEX_op_sub2_i32:
155
- return C_O2_I4(r, r, rZ, rZ, rN, rN);
156
+ return C_O2_I4(r, r, rz, rz, rN, rN);
157
case INDEX_op_setcond2_i32:
158
- return C_O1_I4(r, rZ, rZ, rZ, rZ);
159
+ return C_O1_I4(r, rz, rz, rz, rz);
160
case INDEX_op_brcond2_i32:
161
- return C_O0_I4(rZ, rZ, rZ, rZ);
162
+ return C_O0_I4(rz, rz, rz, rz);
163
164
case INDEX_op_qemu_ld_i32:
165
return C_O1_I1(r, r);
166
case INDEX_op_qemu_st_i32:
167
- return C_O0_I2(rZ, r);
168
+ return C_O0_I2(rz, r);
169
case INDEX_op_qemu_ld_i64:
170
return TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, r) : C_O2_I1(r, r, r);
171
case INDEX_op_qemu_st_i64:
172
- return TCG_TARGET_REG_BITS == 64 ? C_O0_I2(rZ, r) : C_O0_I3(rZ, rZ, r);
173
+ return TCG_TARGET_REG_BITS == 64 ? C_O0_I2(rz, r) : C_O0_I3(rz, rz, r);
174
175
default:
176
return C_NotImplemented;
41
--
177
--
42
2.25.1
178
2.43.0
43
179
44
180
diff view generated by jsdifflib
[PULL 01/10] tcg: update the cpu running flag in cpu_exec_step_atomic
[PULL 18/24] tcg/riscv: Use 'z' constraint
1
From: Douglas Crosher <dtc-ubuntu@scieneer.com>
1
Replace target-specific 'Z' with generic 'z'.
2
2
3
The cpu_exec_step_atomic() function is called with the cpu->running
3
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
4
clear and proceeds to run target code without setting this flag. If
5
this target code generates an exception then handle_cpu_signal() will
6
unnecessarily abort. For example if atomic code generates a memory
7
protection fault.
8
9
This patch at least sets and clears this running flag, and adds some
10
assertions to help detect other cases.
11
12
Signed-off-by: Douglas Crosher <dtc-ubuntu@scieneer.com>
13
Message-Id: <a272c656-f7c5-019d-1cc0-499b8f80f2fc@scieneer.com>
14
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
15
---
5
---
16
accel/tcg/cpu-exec.c | 4 ++++
6
tcg/riscv/tcg-target-con-set.h | 10 +++++-----
17
1 file changed, 4 insertions(+)
7
tcg/riscv/tcg-target-con-str.h | 1 -
8
tcg/riscv/tcg-target.c.inc | 28 ++++++++++++----------------
9
3 files changed, 17 insertions(+), 22 deletions(-)
18
10
19
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
11
diff --git a/tcg/riscv/tcg-target-con-set.h b/tcg/riscv/tcg-target-con-set.h
20
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
21
--- a/accel/tcg/cpu-exec.c
13
--- a/tcg/riscv/tcg-target-con-set.h
22
+++ b/accel/tcg/cpu-exec.c
14
+++ b/tcg/riscv/tcg-target-con-set.h
23
@@ -XXX,XX +XXX,XX @@ void cpu_exec_step_atomic(CPUState *cpu)
15
@@ -XXX,XX +XXX,XX @@
24
16
* tcg-target-con-str.h; the constraint combination is inclusive or.
25
if (sigsetjmp(cpu->jmp_env, 0) == 0) {
17
*/
26
start_exclusive();
18
C_O0_I1(r)
27
+ g_assert(cpu == current_cpu);
19
-C_O0_I2(rZ, r)
28
+ g_assert(!cpu->running);
20
-C_O0_I2(rZ, rZ)
29
+ cpu->running = true;
21
+C_O0_I2(rz, r)
30
22
+C_O0_I2(rz, rz)
31
tb = tb_lookup__cpu_state(cpu, &pc, &cs_base, &flags, cf_mask);
23
C_O1_I1(r, r)
32
if (tb == NULL) {
24
C_O1_I2(r, r, ri)
33
@@ -XXX,XX +XXX,XX @@ void cpu_exec_step_atomic(CPUState *cpu)
25
C_O1_I2(r, r, rI)
34
*/
26
C_O1_I2(r, r, rJ)
35
g_assert(cpu_in_exclusive_context(cpu));
27
-C_O1_I2(r, rZ, rN)
36
parallel_cpus = true;
28
-C_O1_I2(r, rZ, rZ)
37
+ cpu->running = false;
29
+C_O1_I2(r, rz, rN)
38
end_exclusive();
30
+C_O1_I2(r, rz, rz)
31
C_N1_I2(r, r, rM)
32
C_O1_I4(r, r, rI, rM, rM)
33
-C_O2_I4(r, r, rZ, rZ, rM, rM)
34
+C_O2_I4(r, r, rz, rz, rM, rM)
35
C_O0_I2(v, r)
36
C_O1_I1(v, r)
37
C_O1_I1(v, v)
38
diff --git a/tcg/riscv/tcg-target-con-str.h b/tcg/riscv/tcg-target-con-str.h
39
index XXXXXXX..XXXXXXX 100644
40
--- a/tcg/riscv/tcg-target-con-str.h
41
+++ b/tcg/riscv/tcg-target-con-str.h
42
@@ -XXX,XX +XXX,XX @@ CONST('K', TCG_CT_CONST_S5)
43
CONST('L', TCG_CT_CONST_CMP_VI)
44
CONST('N', TCG_CT_CONST_N12)
45
CONST('M', TCG_CT_CONST_M12)
46
-CONST('Z', TCG_CT_CONST_ZERO)
47
diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
48
index XXXXXXX..XXXXXXX 100644
49
--- a/tcg/riscv/tcg-target.c.inc
50
+++ b/tcg/riscv/tcg-target.c.inc
51
@@ -XXX,XX +XXX,XX @@ static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot)
52
return TCG_REG_A0 + slot;
39
}
53
}
40
54
55
-#define TCG_CT_CONST_ZERO 0x100
56
-#define TCG_CT_CONST_S12 0x200
57
-#define TCG_CT_CONST_N12 0x400
58
-#define TCG_CT_CONST_M12 0x800
59
-#define TCG_CT_CONST_J12 0x1000
60
-#define TCG_CT_CONST_S5 0x2000
61
-#define TCG_CT_CONST_CMP_VI 0x4000
62
+#define TCG_CT_CONST_S12 0x100
63
+#define TCG_CT_CONST_N12 0x200
64
+#define TCG_CT_CONST_M12 0x400
65
+#define TCG_CT_CONST_J12 0x800
66
+#define TCG_CT_CONST_S5 0x1000
67
+#define TCG_CT_CONST_CMP_VI 0x2000
68
69
#define ALL_GENERAL_REGS MAKE_64BIT_MASK(0, 32)
70
#define ALL_VECTOR_REGS MAKE_64BIT_MASK(32, 32)
71
@@ -XXX,XX +XXX,XX @@ static bool tcg_target_const_match(int64_t val, int ct,
72
if (ct & TCG_CT_CONST) {
73
return 1;
74
}
75
- if ((ct & TCG_CT_CONST_ZERO) && val == 0) {
76
- return 1;
77
- }
78
if (type >= TCG_TYPE_V64) {
79
/* Val is replicated by VECE; extract the highest element. */
80
val >>= (-8 << vece) & 63;
81
@@ -XXX,XX +XXX,XX @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
82
case INDEX_op_st16_i64:
83
case INDEX_op_st32_i64:
84
case INDEX_op_st_i64:
85
- return C_O0_I2(rZ, r);
86
+ return C_O0_I2(rz, r);
87
88
case INDEX_op_add_i32:
89
case INDEX_op_and_i32:
90
@@ -XXX,XX +XXX,XX @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
91
92
case INDEX_op_sub_i32:
93
case INDEX_op_sub_i64:
94
- return C_O1_I2(r, rZ, rN);
95
+ return C_O1_I2(r, rz, rN);
96
97
case INDEX_op_mul_i32:
98
case INDEX_op_mulsh_i32:
99
@@ -XXX,XX +XXX,XX @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
100
case INDEX_op_divu_i64:
101
case INDEX_op_rem_i64:
102
case INDEX_op_remu_i64:
103
- return C_O1_I2(r, rZ, rZ);
104
+ return C_O1_I2(r, rz, rz);
105
106
case INDEX_op_shl_i32:
107
case INDEX_op_shr_i32:
108
@@ -XXX,XX +XXX,XX @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
109
110
case INDEX_op_brcond_i32:
111
case INDEX_op_brcond_i64:
112
- return C_O0_I2(rZ, rZ);
113
+ return C_O0_I2(rz, rz);
114
115
case INDEX_op_movcond_i32:
116
case INDEX_op_movcond_i64:
117
@@ -XXX,XX +XXX,XX @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
118
case INDEX_op_add2_i64:
119
case INDEX_op_sub2_i32:
120
case INDEX_op_sub2_i64:
121
- return C_O2_I4(r, r, rZ, rZ, rM, rM);
122
+ return C_O2_I4(r, r, rz, rz, rM, rM);
123
124
case INDEX_op_qemu_ld_i32:
125
case INDEX_op_qemu_ld_i64:
126
return C_O1_I1(r, r);
127
case INDEX_op_qemu_st_i32:
128
case INDEX_op_qemu_st_i64:
129
- return C_O0_I2(rZ, r);
130
+ return C_O0_I2(rz, r);
131
132
case INDEX_op_st_vec:
133
return C_O0_I2(v, r);
41
--
134
--
42
2.25.1
135
2.43.0
43
136
44
137
diff view generated by jsdifflib
[PULL 03/10] tcg: Optimize inline dup_const for MO_64
[PULL 19/24] tcg/sparc64: Use 'z' constraint
1
Avoid the out-of-line function call for immediate MO_64.
1
Replace target-specific 'Z' with generic 'z'.
2
In addition, diagnose all invalid constants at compile-time.
3
2
4
Reviewed-by: David Hildenbrand <david@redhat.com>
3
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
---
5
---
7
include/tcg/tcg.h | 3 ++-
6
tcg/sparc64/tcg-target-con-set.h | 12 ++++++------
8
1 file changed, 2 insertions(+), 1 deletion(-)
7
tcg/sparc64/tcg-target-con-str.h | 1 -
8
tcg/sparc64/tcg-target.c.inc | 17 +++++++----------
9
3 files changed, 13 insertions(+), 17 deletions(-)
9
10
10
diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h
11
diff --git a/tcg/sparc64/tcg-target-con-set.h b/tcg/sparc64/tcg-target-con-set.h
11
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
12
--- a/include/tcg/tcg.h
13
--- a/tcg/sparc64/tcg-target-con-set.h
13
+++ b/include/tcg/tcg.h
14
+++ b/tcg/sparc64/tcg-target-con-set.h
14
@@ -XXX,XX +XXX,XX @@ uint64_t dup_const(unsigned vece, uint64_t c);
15
@@ -XXX,XX +XXX,XX @@
15
? ( (VECE) == MO_8 ? 0x0101010101010101ull * (uint8_t)(C) \
16
* tcg-target-con-str.h; the constraint combination is inclusive or.
16
: (VECE) == MO_16 ? 0x0001000100010001ull * (uint16_t)(C) \
17
*/
17
: (VECE) == MO_32 ? 0x0000000100000001ull * (uint32_t)(C) \
18
C_O0_I1(r)
18
- : dup_const(VECE, C)) \
19
-C_O0_I2(rZ, r)
19
+ : (VECE) == MO_64 ? (uint64_t)(C) \
20
-C_O0_I2(rZ, rJ)
20
+ : (qemu_build_not_reached_always(), 0)) \
21
+C_O0_I2(rz, r)
21
: dup_const(VECE, C))
22
+C_O0_I2(rz, rJ)
22
23
C_O1_I1(r, r)
24
C_O1_I2(r, r, r)
25
-C_O1_I2(r, rZ, rJ)
26
-C_O1_I4(r, rZ, rJ, rI, 0)
27
-C_O2_I2(r, r, rZ, rJ)
28
-C_O2_I4(r, r, rZ, rZ, rJ, rJ)
29
+C_O1_I2(r, rz, rJ)
30
+C_O1_I4(r, rz, rJ, rI, 0)
31
+C_O2_I2(r, r, rz, rJ)
32
+C_O2_I4(r, r, rz, rz, rJ, rJ)
33
diff --git a/tcg/sparc64/tcg-target-con-str.h b/tcg/sparc64/tcg-target-con-str.h
34
index XXXXXXX..XXXXXXX 100644
35
--- a/tcg/sparc64/tcg-target-con-str.h
36
+++ b/tcg/sparc64/tcg-target-con-str.h
37
@@ -XXX,XX +XXX,XX @@ REGS('r', ALL_GENERAL_REGS)
38
*/
39
CONST('I', TCG_CT_CONST_S11)
40
CONST('J', TCG_CT_CONST_S13)
41
-CONST('Z', TCG_CT_CONST_ZERO)
42
diff --git a/tcg/sparc64/tcg-target.c.inc b/tcg/sparc64/tcg-target.c.inc
43
index XXXXXXX..XXXXXXX 100644
44
--- a/tcg/sparc64/tcg-target.c.inc
45
+++ b/tcg/sparc64/tcg-target.c.inc
46
@@ -XXX,XX +XXX,XX @@ static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
47
48
#define TCG_CT_CONST_S11 0x100
49
#define TCG_CT_CONST_S13 0x200
50
-#define TCG_CT_CONST_ZERO 0x400
51
52
#define ALL_GENERAL_REGS MAKE_64BIT_MASK(0, 32)
53
54
@@ -XXX,XX +XXX,XX @@ static bool tcg_target_const_match(int64_t val, int ct,
55
val = (int32_t)val;
56
}
57
58
- if ((ct & TCG_CT_CONST_ZERO) && val == 0) {
59
- return 1;
60
- } else if ((ct & TCG_CT_CONST_S11) && check_fit_tl(val, 11)) {
61
+ if ((ct & TCG_CT_CONST_S11) && check_fit_tl(val, 11)) {
62
return 1;
63
} else if ((ct & TCG_CT_CONST_S13) && check_fit_tl(val, 13)) {
64
return 1;
65
@@ -XXX,XX +XXX,XX @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
66
case INDEX_op_st_i64:
67
case INDEX_op_qemu_st_i32:
68
case INDEX_op_qemu_st_i64:
69
- return C_O0_I2(rZ, r);
70
+ return C_O0_I2(rz, r);
71
72
case INDEX_op_add_i32:
73
case INDEX_op_add_i64:
74
@@ -XXX,XX +XXX,XX @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
75
case INDEX_op_setcond_i64:
76
case INDEX_op_negsetcond_i32:
77
case INDEX_op_negsetcond_i64:
78
- return C_O1_I2(r, rZ, rJ);
79
+ return C_O1_I2(r, rz, rJ);
80
81
case INDEX_op_brcond_i32:
82
case INDEX_op_brcond_i64:
83
- return C_O0_I2(rZ, rJ);
84
+ return C_O0_I2(rz, rJ);
85
case INDEX_op_movcond_i32:
86
case INDEX_op_movcond_i64:
87
- return C_O1_I4(r, rZ, rJ, rI, 0);
88
+ return C_O1_I4(r, rz, rJ, rI, 0);
89
case INDEX_op_add2_i32:
90
case INDEX_op_add2_i64:
91
case INDEX_op_sub2_i32:
92
case INDEX_op_sub2_i64:
93
- return C_O2_I4(r, r, rZ, rZ, rJ, rJ);
94
+ return C_O2_I4(r, r, rz, rz, rJ, rJ);
95
case INDEX_op_mulu2_i32:
96
case INDEX_op_muls2_i32:
97
- return C_O2_I2(r, r, rZ, rJ);
98
+ return C_O2_I2(r, r, rz, rJ);
99
case INDEX_op_muluh_i64:
100
return C_O1_I2(r, r, r);
23
101
24
--
102
--
25
2.25.1
103
2.43.0
26
104
27
105
diff view generated by jsdifflib
New patch
[PULL 20/24] elfload: Fix alignment when unmapping excess reservation
1
From: Fabiano Rosas <farosas@suse.de>
1
2
3
When complying with the alignment requested in the ELF and unmapping
4
the excess reservation, having align_end not aligned to the guest page
5
causes the unmap to be rejected by the alignment check at
6
target_munmap and later brk adjustments hit an EEXIST.
7
8
Fix by aligning the start of region to be unmapped.
9
10
Fixes: c81d1fafa6 ("linux-user: Honor elf alignment when placing images")
11
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1913
12
Signed-off-by: Fabiano Rosas <farosas@suse.de>
13
[rth: Align load_end as well.]
14
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
15
Message-ID: <20250213143558.10504-1-farosas@suse.de>
16
---
17
linux-user/elfload.c | 4 ++--
18
1 file changed, 2 insertions(+), 2 deletions(-)
19
20
diff --git a/linux-user/elfload.c b/linux-user/elfload.c
21
index XXXXXXX..XXXXXXX 100644
22
--- a/linux-user/elfload.c
23
+++ b/linux-user/elfload.c
24
@@ -XXX,XX +XXX,XX @@ static void load_elf_image(const char *image_name, const ImageSource *src,
25
26
if (align_size != reserve_size) {
27
abi_ulong align_addr = ROUND_UP(load_addr, align);
28
- abi_ulong align_end = align_addr + reserve_size;
29
- abi_ulong load_end = load_addr + align_size;
30
+ abi_ulong align_end = TARGET_PAGE_ALIGN(align_addr + reserve_size);
31
+ abi_ulong load_end = TARGET_PAGE_ALIGN(load_addr + align_size);
32
33
if (align_addr != load_addr) {
34
target_munmap(load_addr, align_addr - load_addr);
35
--
36
2.43.0
diff view generated by jsdifflib
New patch
[PULL 21/24] linux-user: Move TARGET_SA_RESTORER out of generic/signal.h
1
From: Andreas Schwab <schwab@suse.de>
1
2
3
SA_RESTORER and the associated sa_restorer field of struct sigaction are
4
an obsolete feature, not expected to be used by future architectures.
5
They are also absent on RISC-V, LoongArch, Hexagon and OpenRISC, but
6
defined due to their use of generic/signal.h. This leads to corrupted
7
data and out-of-bounds accesses.
8
9
Move the definition of TARGET_SA_RESTORER out of generic/signal.h into the
10
target_signal.h files that need it. Note that m68k has the sa_restorer
11
field, but does not use it and does not define SA_RESTORER.
12
13
Reported-by: Thomas Weißschuh <thomas@t-8ch.de>
14
Signed-off-by: Andreas Schwab <schwab@suse.de>
15
Reviewed-by: Thomas Weißschuh <thomas@t-8ch.de>
16
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
17
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
18
Message-ID: <mvmed060xc9.fsf@suse.de>
19
---
20
linux-user/aarch64/target_signal.h | 2 ++
21
linux-user/arm/target_signal.h | 2 ++
22
linux-user/generic/signal.h | 1 -
23
linux-user/i386/target_signal.h | 2 ++
24
linux-user/m68k/target_signal.h | 1 +
25
linux-user/microblaze/target_signal.h | 2 ++
26
linux-user/ppc/target_signal.h | 2 ++
27
linux-user/s390x/target_signal.h | 2 ++
28
linux-user/sh4/target_signal.h | 2 ++
29
linux-user/x86_64/target_signal.h | 2 ++
30
linux-user/xtensa/target_signal.h | 2 ++
31
11 files changed, 19 insertions(+), 1 deletion(-)
32
33
diff --git a/linux-user/aarch64/target_signal.h b/linux-user/aarch64/target_signal.h
34
index XXXXXXX..XXXXXXX 100644
35
--- a/linux-user/aarch64/target_signal.h
36
+++ b/linux-user/aarch64/target_signal.h
37
@@ -XXX,XX +XXX,XX @@
38
39
#include "../generic/signal.h"
40
41
+#define TARGET_SA_RESTORER 0x04000000
42
+
43
#define TARGET_SEGV_MTEAERR 8 /* Asynchronous ARM MTE error */
44
#define TARGET_SEGV_MTESERR 9 /* Synchronous ARM MTE exception */
45
46
diff --git a/linux-user/arm/target_signal.h b/linux-user/arm/target_signal.h
47
index XXXXXXX..XXXXXXX 100644
48
--- a/linux-user/arm/target_signal.h
49
+++ b/linux-user/arm/target_signal.h
50
@@ -XXX,XX +XXX,XX @@
51
52
#include "../generic/signal.h"
53
54
+#define TARGET_SA_RESTORER 0x04000000
55
+
56
#define TARGET_ARCH_HAS_SETUP_FRAME
57
#define TARGET_ARCH_HAS_SIGTRAMP_PAGE 1
58
59
diff --git a/linux-user/generic/signal.h b/linux-user/generic/signal.h
60
index XXXXXXX..XXXXXXX 100644
61
--- a/linux-user/generic/signal.h
62
+++ b/linux-user/generic/signal.h
63
@@ -XXX,XX +XXX,XX @@
64
#define TARGET_SA_RESTART 0x10000000
65
#define TARGET_SA_NODEFER 0x40000000
66
#define TARGET_SA_RESETHAND 0x80000000
67
-#define TARGET_SA_RESTORER 0x04000000
68
69
#define TARGET_SIGHUP 1
70
#define TARGET_SIGINT 2
71
diff --git a/linux-user/i386/target_signal.h b/linux-user/i386/target_signal.h
72
index XXXXXXX..XXXXXXX 100644
73
--- a/linux-user/i386/target_signal.h
74
+++ b/linux-user/i386/target_signal.h
75
@@ -XXX,XX +XXX,XX @@
76
77
#include "../generic/signal.h"
78
79
+#define TARGET_SA_RESTORER 0x04000000
80
+
81
#define TARGET_ARCH_HAS_SETUP_FRAME
82
#define TARGET_ARCH_HAS_SIGTRAMP_PAGE 1
83
84
diff --git a/linux-user/m68k/target_signal.h b/linux-user/m68k/target_signal.h
85
index XXXXXXX..XXXXXXX 100644
86
--- a/linux-user/m68k/target_signal.h
87
+++ b/linux-user/m68k/target_signal.h
88
@@ -XXX,XX +XXX,XX @@
89
90
#include "../generic/signal.h"
91
92
+#define TARGET_ARCH_HAS_SA_RESTORER 1
93
#define TARGET_ARCH_HAS_SETUP_FRAME
94
#define TARGET_ARCH_HAS_SIGTRAMP_PAGE 1
95
96
diff --git a/linux-user/microblaze/target_signal.h b/linux-user/microblaze/target_signal.h
97
index XXXXXXX..XXXXXXX 100644
98
--- a/linux-user/microblaze/target_signal.h
99
+++ b/linux-user/microblaze/target_signal.h
100
@@ -XXX,XX +XXX,XX @@
101
102
#include "../generic/signal.h"
103
104
+#define TARGET_SA_RESTORER 0x04000000
105
+
106
#define TARGET_ARCH_HAS_SIGTRAMP_PAGE 1
107
108
#endif /* MICROBLAZE_TARGET_SIGNAL_H */
109
diff --git a/linux-user/ppc/target_signal.h b/linux-user/ppc/target_signal.h
110
index XXXXXXX..XXXXXXX 100644
111
--- a/linux-user/ppc/target_signal.h
112
+++ b/linux-user/ppc/target_signal.h
113
@@ -XXX,XX +XXX,XX @@
114
115
#include "../generic/signal.h"
116
117
+#define TARGET_SA_RESTORER 0x04000000
118
+
119
#if !defined(TARGET_PPC64)
120
#define TARGET_ARCH_HAS_SETUP_FRAME
121
#endif
122
diff --git a/linux-user/s390x/target_signal.h b/linux-user/s390x/target_signal.h
123
index XXXXXXX..XXXXXXX 100644
124
--- a/linux-user/s390x/target_signal.h
125
+++ b/linux-user/s390x/target_signal.h
126
@@ -XXX,XX +XXX,XX @@
127
128
#include "../generic/signal.h"
129
130
+#define TARGET_SA_RESTORER 0x04000000
131
+
132
#define TARGET_ARCH_HAS_SETUP_FRAME
133
#define TARGET_ARCH_HAS_SIGTRAMP_PAGE 1
134
135
diff --git a/linux-user/sh4/target_signal.h b/linux-user/sh4/target_signal.h
136
index XXXXXXX..XXXXXXX 100644
137
--- a/linux-user/sh4/target_signal.h
138
+++ b/linux-user/sh4/target_signal.h
139
@@ -XXX,XX +XXX,XX @@
140
141
#include "../generic/signal.h"
142
143
+#define TARGET_SA_RESTORER 0x04000000
144
+
145
#define TARGET_ARCH_HAS_SETUP_FRAME
146
#define TARGET_ARCH_HAS_SIGTRAMP_PAGE 1
147
148
diff --git a/linux-user/x86_64/target_signal.h b/linux-user/x86_64/target_signal.h
149
index XXXXXXX..XXXXXXX 100644
150
--- a/linux-user/x86_64/target_signal.h
151
+++ b/linux-user/x86_64/target_signal.h
152
@@ -XXX,XX +XXX,XX @@
153
154
#include "../generic/signal.h"
155
156
+#define TARGET_SA_RESTORER 0x04000000
157
+
158
/* For x86_64, use of SA_RESTORER is mandatory. */
159
#define TARGET_ARCH_HAS_SIGTRAMP_PAGE 0
160
161
diff --git a/linux-user/xtensa/target_signal.h b/linux-user/xtensa/target_signal.h
162
index XXXXXXX..XXXXXXX 100644
163
--- a/linux-user/xtensa/target_signal.h
164
+++ b/linux-user/xtensa/target_signal.h
165
@@ -XXX,XX +XXX,XX @@
166
167
#include "../generic/signal.h"
168
169
+#define TARGET_SA_RESTORER 0x04000000
170
+
171
#define TARGET_ARCH_HAS_SIGTRAMP_PAGE 1
172
173
#endif
174
--
175
2.43.0
176
177
diff view generated by jsdifflib
New patch
[PULL 22/24] target/sparc: Fix register selection for all F*TOx and FxTO* instructions
1
From: Mikael Szreder <git@miszr.win>
1
2
3
A bug was introduced in commit 0bba7572d40d which causes the fdtox
4
and fqtox instructions to incorrectly select the destination registers.
5
More information and a test program can be found in issue #2802.
6
7
Fixes: 0bba7572d40d ("target/sparc: Perform DFPREG/QFPREG in decodetree")
8
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2802
9
Signed-off-by: Mikael Szreder <git@miszr.win>
10
Acked-by: Artyom Tarasenko <atar4qemu@gmail.com>
11
[rth: Squash patches together, since the second fixes a typo in the first.]
12
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
13
Message-ID: <20250205090333.19626-3-git@miszr.win>
14
---
15
target/sparc/insns.decode | 12 ++++++------
16
1 file changed, 6 insertions(+), 6 deletions(-)
17
18
diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode
19
index XXXXXXX..XXXXXXX 100644
20
--- a/target/sparc/insns.decode
21
+++ b/target/sparc/insns.decode
22
@@ -XXX,XX +XXX,XX @@ FdMULq 10 ..... 110100 ..... 0 0110 1110 ..... @q_d_d
23
FNHADDs 10 ..... 110100 ..... 0 0111 0001 ..... @r_r_r
24
FNHADDd 10 ..... 110100 ..... 0 0111 0010 ..... @d_d_d
25
FNsMULd 10 ..... 110100 ..... 0 0111 1001 ..... @d_r_r
26
-FsTOx 10 ..... 110100 00000 0 1000 0001 ..... @r_r2
27
-FdTOx 10 ..... 110100 00000 0 1000 0010 ..... @r_d2
28
-FqTOx 10 ..... 110100 00000 0 1000 0011 ..... @r_q2
29
-FxTOs 10 ..... 110100 00000 0 1000 0100 ..... @r_r2
30
-FxTOd 10 ..... 110100 00000 0 1000 1000 ..... @d_r2
31
-FxTOq 10 ..... 110100 00000 0 1000 1100 ..... @q_r2
32
+FsTOx 10 ..... 110100 00000 0 1000 0001 ..... @d_r2
33
+FdTOx 10 ..... 110100 00000 0 1000 0010 ..... @d_d2
34
+FqTOx 10 ..... 110100 00000 0 1000 0011 ..... @d_q2
35
+FxTOs 10 ..... 110100 00000 0 1000 0100 ..... @r_d2
36
+FxTOd 10 ..... 110100 00000 0 1000 1000 ..... @d_d2
37
+FxTOq 10 ..... 110100 00000 0 1000 1100 ..... @q_d2
38
FiTOs 10 ..... 110100 00000 0 1100 0100 ..... @r_r2
39
FdTOs 10 ..... 110100 00000 0 1100 0110 ..... @r_d2
40
FqTOs 10 ..... 110100 00000 0 1100 0111 ..... @r_q2
41
--
42
2.43.0
diff view generated by jsdifflib
New patch
[PULL 23/24] target/sparc: Fix gdbstub incorrectly handling registers f32-f62
1
From: Mikael Szreder <git@miszr.win>
1
2
3
The gdbstub implementation for the Sparc architecture would
4
incorrectly calculate the the floating point register offset.
5
This resulted in, for example, registers f32 and f34 to point to
6
the same value.
7
8
The issue was caused by the confusion between even register numbers
9
and even register indexes. For example, the register index of f32 is 64
10
and f34 is 65.
11
12
Fixes: 30038fd81808 ("target-sparc: Change fpr representation to doubles.")
13
Signed-off-by: Mikael Szreder <git@miszr.win>
14
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
15
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
16
Message-ID: <20250214070343.11501-1-git@miszr.win>
17
---
18
target/sparc/gdbstub.c | 18 ++++++++++++++----
19
1 file changed, 14 insertions(+), 4 deletions(-)
20
21
diff --git a/target/sparc/gdbstub.c b/target/sparc/gdbstub.c
22
index XXXXXXX..XXXXXXX 100644
23
--- a/target/sparc/gdbstub.c
24
+++ b/target/sparc/gdbstub.c
25
@@ -XXX,XX +XXX,XX @@ int sparc_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
26
}
27
}
28
if (n < 80) {
29
- /* f32-f62 (double width, even numbers only) */
30
- return gdb_get_reg64(mem_buf, env->fpr[(n - 32) / 2].ll);
31
+ /* f32-f62 (16 double width registers, even register numbers only)
32
+ * n == 64: f32 : env->fpr[16]
33
+ * n == 65: f34 : env->fpr[17]
34
+ * etc...
35
+ * n == 79: f62 : env->fpr[31]
36
+ */
37
+ return gdb_get_reg64(mem_buf, env->fpr[(n - 64) + 16].ll);
38
}
39
switch (n) {
40
case 80:
41
@@ -XXX,XX +XXX,XX @@ int sparc_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
42
}
43
return 4;
44
} else if (n < 80) {
45
- /* f32-f62 (double width, even numbers only) */
46
- env->fpr[(n - 32) / 2].ll = tmp;
47
+ /* f32-f62 (16 double width registers, even register numbers only)
48
+ * n == 64: f32 : env->fpr[16]
49
+ * n == 65: f34 : env->fpr[17]
50
+ * etc...
51
+ * n == 79: f62 : env->fpr[31]
52
+ */
53
+ env->fpr[(n - 64) + 16].ll = tmp;
54
} else {
55
switch (n) {
56
case 80:
57
--
58
2.43.0
diff view generated by jsdifflib
New patch
[PULL 24/24] target/sparc: fake UltraSPARC T1 PCR and PIC registers
1
From: Artyom Tarasenko <atar4qemu@gmail.com>
1
2
3
Fake access to
4
PCR Performance Control Register
5
and
6
PIC Performance Instrumentation Counter.
7
8
Ignore writes in privileged mode, and return 0 on reads.
9
10
This allows booting Tribblix, MilaX and v9os under Niagara target.
11
12
Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
13
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
14
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
15
Message-ID: <20250209211248.50383-1-atar4qemu@gmail.com>
16
---
17
target/sparc/translate.c | 19 +++++++++++++++++++
18
target/sparc/insns.decode | 7 ++++++-
19
2 files changed, 25 insertions(+), 1 deletion(-)
20
21
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
22
index XXXXXXX..XXXXXXX 100644
23
--- a/target/sparc/translate.c
24
+++ b/target/sparc/translate.c
25
@@ -XXX,XX +XXX,XX @@ static TCGv do_rd_leon3_config(DisasContext *dc, TCGv dst)
26
27
TRANS(RDASR17, ASR17, do_rd_special, true, a->rd, do_rd_leon3_config)
28
29
+static TCGv do_rdpic(DisasContext *dc, TCGv dst)
30
+{
31
+ return tcg_constant_tl(0);
32
+}
33
+
34
+TRANS(RDPIC, HYPV, do_rd_special, supervisor(dc), a->rd, do_rdpic)
35
+
36
+
37
static TCGv do_rdccr(DisasContext *dc, TCGv dst)
38
{
39
gen_helper_rdccr(dst, tcg_env);
40
@@ -XXX,XX +XXX,XX @@ static void do_wrfprs(DisasContext *dc, TCGv src)
41
42
TRANS(WRFPRS, 64, do_wr_special, a, true, do_wrfprs)
43
44
+static bool do_priv_nop(DisasContext *dc, bool priv)
45
+{
46
+ if (!priv) {
47
+ return raise_priv(dc);
48
+ }
49
+ return advance_pc(dc);
50
+}
51
+
52
+TRANS(WRPCR, HYPV, do_priv_nop, supervisor(dc))
53
+TRANS(WRPIC, HYPV, do_priv_nop, supervisor(dc))
54
+
55
static void do_wrgsr(DisasContext *dc, TCGv src)
56
{
57
gen_trap_ifnofpu(dc);
58
diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode
59
index XXXXXXX..XXXXXXX 100644
60
--- a/target/sparc/insns.decode
61
+++ b/target/sparc/insns.decode
62
@@ -XXX,XX +XXX,XX @@ CALL 01 i:s30
63
RDTICK 10 rd:5 101000 00100 0 0000000000000
64
RDPC 10 rd:5 101000 00101 0 0000000000000
65
RDFPRS 10 rd:5 101000 00110 0 0000000000000
66
- RDASR17 10 rd:5 101000 10001 0 0000000000000
67
+ {
68
+ RDASR17 10 rd:5 101000 10001 0 0000000000000
69
+ RDPIC 10 rd:5 101000 10001 0 0000000000000
70
+ }
71
RDGSR 10 rd:5 101000 10011 0 0000000000000
72
RDSOFTINT 10 rd:5 101000 10110 0 0000000000000
73
RDTICK_CMPR 10 rd:5 101000 10111 0 0000000000000
74
@@ -XXX,XX +XXX,XX @@ CALL 01 i:s30
75
WRCCR 10 00010 110000 ..... . ............. @n_r_ri
76
WRASI 10 00011 110000 ..... . ............. @n_r_ri
77
WRFPRS 10 00110 110000 ..... . ............. @n_r_ri
78
+ WRPCR 10 10000 110000 01000 0 0000000000000
79
+ WRPIC 10 10001 110000 01000 0 0000000000000
80
{
81
WRGSR 10 10011 110000 ..... . ............. @n_r_ri
82
WRPOWERDOWN 10 10011 110000 ..... . ............. @n_r_ri
83
--
84
2.43.0
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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