cpsr has been treated as being the same as spsr, but it isn't.
Since PSTATE_SS isn't in cpsr, remove it and move it into env->pstate.

Signed-off-by: Rebecca Cran <rebecca@nuviainc.com>
---
 target/arm/helper-a64.c | 4 +---
 target/arm/helper.c     | 4 ++--
 target/arm/op_helper.c  | 9 +--------
 3 files changed, 4 insertions(+), 13 deletions(-)

diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
index c426c23d2c4e..0d2ac7bb7ee3 100644
--- a/target/arm/helper-a64.c
+++ b/target/arm/helper-a64.c
@@ -1000,9 +1000,7 @@ void HELPER(exception_return)(CPUARMState *env, uint64_t new_pc)
          */
         mask = aarch32_cpsr_valid_mask(env->features, &env_archcpu(env)->isar);
         cpsr_write(env, spsr, mask, CPSRWriteRaw);
-        if (!arm_singlestep_active(env)) {
-            env->uncached_cpsr &= ~PSTATE_SS;
-        }
+        env->pstate &= ~PSTATE_SS;
         aarch64_sync_64_to_32(env);
 
         if (spsr & CPSR_T) {
diff --git a/target/arm/helper.c b/target/arm/helper.c
index d2ead3fcbdbd..01b50316046b 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -9402,8 +9402,8 @@ static void take_aarch32_exception(CPUARMState *env, int new_mode,
      * For exceptions taken to AArch32 we must clear the SS bit in both
      * PSTATE and in the old-state value we save to SPSR_<mode>, so zero it now.
      */
-    env->uncached_cpsr &= ~PSTATE_SS;
-    env->spsr = cpsr_read(env);
+    env->pstate &= ~PSTATE_SS;
+    env->spsr &= ~PSTATE_SS;
     /* Clear IT bits.  */
     env->condexec_bits = 0;
     /* Switch to the new mode, and to the correct instruction set.  */
diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
index 5e0f123043b5..65cb37d088f8 100644
--- a/target/arm/op_helper.c
+++ b/target/arm/op_helper.c
@@ -389,14 +389,7 @@ void HELPER(exception_bkpt_insn)(CPUARMState *env, uint32_t syndrome)
 
 uint32_t HELPER(cpsr_read)(CPUARMState *env)
 {
-    /*
-     * We store the ARMv8 PSTATE.SS bit in env->uncached_cpsr.
-     * This is convenient for populating SPSR_ELx, but must be
-     * hidden from aarch32 mode, where it is not visible.
-     *
-     * TODO: ARMv8.4-DIT -- need to move SS somewhere else.
-     */
-    return cpsr_read(env) & ~(CPSR_EXEC | PSTATE_SS);
+    return cpsr_read(env) & ~CPSR_EXEC;
 }
 
 void HELPER(cpsr_write)(CPUARMState *env, uint32_t val, uint32_t mask)
-- 
2.26.2

On 1/21/21 6:45 PM, Rebecca Cran wrote:
> cpsr has been treated as being the same as spsr, but it isn't.
> Since PSTATE_SS isn't in cpsr, remove it and move it into env->pstate.
> 
> Signed-off-by: Rebecca Cran <rebecca@nuviainc.com>
> ---
>  target/arm/helper-a64.c | 4 +---
>  target/arm/helper.c     | 4 ++--
>  target/arm/op_helper.c  | 9 +--------
>  3 files changed, 4 insertions(+), 13 deletions(-)
> 
> diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
> index c426c23d2c4e..0d2ac7bb7ee3 100644
> --- a/target/arm/helper-a64.c
> +++ b/target/arm/helper-a64.c
> @@ -1000,9 +1000,7 @@ void HELPER(exception_return)(CPUARMState *env, uint64_t new_pc)
>           */
>          mask = aarch32_cpsr_valid_mask(env->features, &env_archcpu(env)->isar);
>          cpsr_write(env, spsr, mask, CPSRWriteRaw);
> -        if (!arm_singlestep_active(env)) {
> -            env->uncached_cpsr &= ~PSTATE_SS;
> -        }
> +        env->pstate &= ~PSTATE_SS;

Why are you removing the singlestep check?

>          aarch64_sync_64_to_32(env);
>  
>          if (spsr & CPSR_T) {
> diff --git a/target/arm/helper.c b/target/arm/helper.c
> index d2ead3fcbdbd..01b50316046b 100644
> --- a/target/arm/helper.c
> +++ b/target/arm/helper.c
> @@ -9402,8 +9402,8 @@ static void take_aarch32_exception(CPUARMState *env, int new_mode,
>       * For exceptions taken to AArch32 we must clear the SS bit in both
>       * PSTATE and in the old-state value we save to SPSR_<mode>, so zero it now.
>       */
> -    env->uncached_cpsr &= ~PSTATE_SS;
> -    env->spsr = cpsr_read(env);
> +    env->pstate &= ~PSTATE_SS;
> +    env->spsr &= ~PSTATE_SS;

This loses the saving of cpsr into spsr.


r~

On 1/22/21 2:03 PM, Richard Henderson wrote:
> On 1/21/21 6:45 PM, Rebecca Cran wrote:

>>           cpsr_write(env, spsr, mask, CPSRWriteRaw);
>> -        if (!arm_singlestep_active(env)) {
>> -            env->uncached_cpsr &= ~PSTATE_SS;
>> -        }
>> +        env->pstate &= ~PSTATE_SS;
> 
> Why are you removing the singlestep check?

>> -    env->uncached_cpsr &= ~PSTATE_SS;
>> -    env->spsr = cpsr_read(env);
>> +    env->pstate &= ~PSTATE_SS;
>> +    env->spsr &= ~PSTATE_SS;
> 
> This loses the saving of cpsr into spsr.

Oh, right. I've fixed both this and the above issue in the next revision 
which I'll send out early next week (giving a chance for any extra 
feedback).

Thanks.
-- 
Rebecca Cran