[v1] target/arm: Implement ID_PFR2

[PATCH] target/arm: Implement ID_PFR2

Richard Henderson posted 1 patch 4 years, 10 months ago

Diff against v3
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git fetch https://github.com/patchew-project/qemu tags/patchew/20210120035233.948436-1-richard.henderson@linaro.org

Maintainers: Peter Maydell <peter.maydell@linaro.org>

There is a newer version of this series

target/arm/cpu.h    | 1 +
target/arm/helper.c | 4 ++--
2 files changed, 3 insertions(+), 2 deletions(-)

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[PATCH] target/arm: Implement ID_PFR2

Posted by Richard Henderson 4 years, 10 months ago

This was defined at some point before ARMv8.4, and will
shortly be used by new processor descriptions.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---

I've pulled this out of a largely defunct 2019 branch.  This will
be required for the cortex-a76.  Aside from simplistic isar changes,
this is unchanged from its April 2019 review, so I did keep the r-b.


r~
---
 target/arm/cpu.h    | 1 +
 target/arm/helper.c | 4 ++--
 2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index df0d677833..d080239863 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -922,6 +922,7 @@ struct ARMCPU {
         uint32_t id_mmfr4;
         uint32_t id_pfr0;
         uint32_t id_pfr1;
+        uint32_t id_pfr2;
         uint32_t mvfr0;
         uint32_t mvfr1;
         uint32_t mvfr2;
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 10102aab3c..677a4aa79e 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -7671,11 +7671,11 @@ void register_cp_regs_for_features(ARMCPU *cpu)
               .access = PL1_R, .type = ARM_CP_CONST,
               .accessfn = access_aa64_tid3,
               .resetvalue = 0 },
-            { .name = "MVFR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
+            { .name = "ID_PFR2", .state = ARM_CP_STATE_BOTH,
               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 4,
               .access = PL1_R, .type = ARM_CP_CONST,
               .accessfn = access_aa64_tid3,
-              .resetvalue = 0 },
+              .resetvalue = cpu->isar.id_pfr2 },
             { .name = "MVFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 5,
               .access = PL1_R, .type = ARM_CP_CONST,
-- 
2.25.1

Re: [PATCH] target/arm: Implement ID_PFR2

Posted by Richard Henderson 4 years, 10 months ago

On 1/19/21 5:52 PM, Richard Henderson wrote:
> This was defined at some point before ARMv8.4, and will
> shortly be used by new processor descriptions.
> 
> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> 
> I've pulled this out of a largely defunct 2019 branch.  This will
> be required for the cortex-a76.  Aside from simplistic isar changes,
> this is unchanged from its April 2019 review, so I did keep the r-b.
> 

Ho hum, the patch is missing the change to kvm64 to pull the value out of the
test vm.


r~