[PULL v2 00/29] target-arm queue
[PULL v2 00/61] target-arm queue
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v2: drop pvpanic-pci patches.
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This pullreq is (1) my GICv4 patches (2) most of the first third of RTH's
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cleanup patchset (3) one patch fixing an smmuv3 bug...
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The following changes since commit f1fcb6851aba6dd9838886dc179717a11e344a1c:
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v2 changes: fix build failure on aarch64 hosts by moving the
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gicv3_add_its() and gicv3_foreach_its() functions to
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arm_gicv3_its_common.h.
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Merge remote-tracking branch 'remotes/huth-gitlab/tags/pull-request-2021-01-19' into staging (2021-01-19 11:57:07 +0000)
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thanks
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-- PMM
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The following changes since commit a74782936dc6e979ce371dabda4b1c05624ea87f:
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Merge tag 'pull-migration-20220421a' of https://gitlab.com/dagrh/qemu into staging (2022-04-21 18:48:18 -0700)
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are available in the Git repository at:
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are available in the Git repository at:
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210119-1
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220422-1
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for you to fetch changes up to b93f4fbdc48283a39089469c44a5529d79dc40a8:
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for you to fetch changes up to c3ca7d56c4790c2223122f7e84b71161cd36dbce:
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docs: Build and install all the docs in a single manual (2021-01-19 15:45:14 +0000)
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hw/arm/smmuv3: Pass the actual perm to returned IOMMUTLBEntry in smmuv3_translate() (2022-04-22 14:44:55 +0100)
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----------------------------------------------------------------
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----------------------------------------------------------------
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target-arm queue:
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target-arm queue:
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* Implement IMPDEF pauth algorithm
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* Implement GICv4 emulation
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* Support ARMv8.4-SEL2
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* Some cleanup patches in target/arm
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* Fix bug where we were truncating predicate vector lengths in SVE insns
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* hw/arm/smmuv3: Pass the actual perm to returned IOMMUTLBEntry in smmuv3_translate()
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* npcm7xx_adc-test: Fix memleak in adc_qom_set
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* target/arm/m_helper: Silence GCC 10 maybe-uninitialized error
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* docs: Build and install all the docs in a single manual
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----------------------------------------------------------------
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----------------------------------------------------------------
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Gan Qixin (1):
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Peter Maydell (41):
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npcm7xx_adc-test: Fix memleak in adc_qom_set
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hw/intc/arm_gicv3_its: Add missing blank line
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hw/intc/arm_gicv3: Sanity-check num-cpu property
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hw/intc/arm_gicv3: Insist that redist region capacity matches CPU count
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hw/intc/arm_gicv3: Report correct PIDR0 values for ID registers
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target/arm/cpu.c: ignore VIRQ and VFIQ if no EL2
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hw/intc/arm_gicv3_its: Factor out "is intid a valid LPI ID?"
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hw/intc/arm_gicv3_its: Implement GITS_BASER2 for GICv4
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hw/intc/arm_gicv3_its: Implement VMAPI and VMAPTI
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hw/intc/arm_gicv3_its: Implement VMAPP
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hw/intc/arm_gicv3_its: Distinguish success and error cases of CMD_CONTINUE
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hw/intc/arm_gicv3_its: Factor out "find ITE given devid, eventid"
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hw/intc/arm_gicv3_its: Factor out CTE lookup sequence
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hw/intc/arm_gicv3_its: Split out process_its_cmd() physical interrupt code
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hw/intc/arm_gicv3_its: Handle virtual interrupts in process_its_cmd()
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hw/intc/arm_gicv3: Keep pointers to every connected ITS
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hw/intc/arm_gicv3_its: Implement VMOVP
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hw/intc/arm_gicv3_its: Implement VSYNC
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hw/intc/arm_gicv3_its: Implement INV command properly
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hw/intc/arm_gicv3_its: Implement INV for virtual interrupts
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hw/intc/arm_gicv3_its: Implement VMOVI
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hw/intc/arm_gicv3_its: Implement VINVALL
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hw/intc/arm_gicv3: Implement GICv4's new redistributor frame
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hw/intc/arm_gicv3: Implement new GICv4 redistributor registers
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hw/intc/arm_gicv3_cpuif: Split "update vIRQ/vFIQ" from gicv3_cpuif_virt_update()
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hw/intc/arm_gicv3_cpuif: Support vLPIs
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hw/intc/arm_gicv3_cpuif: Don't recalculate maintenance irq unnecessarily
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hw/intc/arm_gicv3_redist: Factor out "update hpplpi for one LPI" logic
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hw/intc/arm_gicv3_redist: Factor out "update hpplpi for all LPIs" logic
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hw/intc/arm_gicv3_redist: Recalculate hppvlpi on VPENDBASER writes
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hw/intc/arm_gicv3_redist: Factor out "update bit in pending table" code
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hw/intc/arm_gicv3_redist: Implement gicv3_redist_process_vlpi()
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hw/intc/arm_gicv3_redist: Implement gicv3_redist_vlpi_pending()
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hw/intc/arm_gicv3_redist: Use set_pending_table_bit() in mov handling
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hw/intc/arm_gicv3_redist: Implement gicv3_redist_mov_vlpi()
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hw/intc/arm_gicv3_redist: Implement gicv3_redist_vinvall()
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hw/intc/arm_gicv3_redist: Implement gicv3_redist_inv_vlpi()
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hw/intc/arm_gicv3: Update ID and feature registers for GICv4
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hw/intc/arm_gicv3: Allow 'revision' property to be set to 4
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hw/arm/virt: Use VIRT_GIC_VERSION_* enum values in create_gic()
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hw/arm/virt: Abstract out calculation of redistributor region capacity
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hw/arm/virt: Support TCG GICv4
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Peter Maydell (1):
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Richard Henderson (19):
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docs: Build and install all the docs in a single manual
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target/arm: Update ISAR fields for ARMv8.8
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target/arm: Update SCR_EL3 bits to ARMv8.8
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target/arm: Update SCTLR bits to ARMv9.2
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target/arm: Change DisasContext.aarch64 to bool
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target/arm: Change CPUArchState.aarch64 to bool
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target/arm: Extend store_cpu_offset to take field size
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target/arm: Change DisasContext.thumb to bool
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target/arm: Change CPUArchState.thumb to bool
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target/arm: Remove fpexc32_access
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target/arm: Split out set_btype_raw
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target/arm: Split out gen_rebuild_hflags
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target/arm: Simplify GEN_SHIFT in translate.c
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target/arm: Simplify gen_sar
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target/arm: Simplify aa32 DISAS_WFI
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target/arm: Use tcg_constant in translate-m-nocp.c
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target/arm: Use tcg_constant in translate-neon.c
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target/arm: Use smin/smax for do_sat_addsub_32
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target/arm: Use tcg_constant in translate-vfp.c
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target/arm: Use tcg_constant_i32 in translate.h
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Philippe Mathieu-Daudé (1):
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Xiang Chen (1):
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target/arm/m_helper: Silence GCC 10 maybe-uninitialized error
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hw/arm/smmuv3: Pass the actual perm to returned IOMMUTLBEntry in smmuv3_translate()
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Richard Henderson (7):
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docs/system/arm/virt.rst | 5 +-
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target/arm: Implement an IMPDEF pauth algorithm
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hw/intc/gicv3_internal.h | 213 +++++++-
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target/arm: Add cpu properties to control pauth
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include/hw/arm/virt.h | 19 +-
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target/arm: Use object_property_add_bool for "sve" property
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include/hw/intc/arm_gicv3_common.h | 13 +
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target/arm: Introduce PREDDESC field definitions
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include/hw/intc/arm_gicv3_its_common.h | 19 +
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target/arm: Update PFIRST, PNEXT for pred_desc
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target/arm/cpu.h | 59 ++-
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target/arm: Update ZIP, UZP, TRN for pred_desc
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target/arm/translate-a32.h | 13 +-
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target/arm: Update REV, PUNPK for pred_desc
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target/arm/translate.h | 17 +-
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hw/arm/smmuv3.c | 2 +-
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Rémi Denis-Courmont (19):
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hw/arm/virt.c | 102 +++-
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target/arm: remove redundant tests
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hw/intc/arm_gicv3_common.c | 54 +-
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target/arm: add arm_is_el2_enabled() helper
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hw/intc/arm_gicv3_cpuif.c | 195 ++++++--
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target/arm: use arm_is_el2_enabled() where applicable
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hw/intc/arm_gicv3_dist.c | 7 +-
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target/arm: use arm_hcr_el2_eff() where applicable
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hw/intc/arm_gicv3_its.c | 876 +++++++++++++++++++++++++++------
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target/arm: factor MDCR_EL2 common handling
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hw/intc/arm_gicv3_its_kvm.c | 2 +
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target/arm: Define isar_feature function to test for presence of SEL2
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hw/intc/arm_gicv3_kvm.c | 5 +
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target/arm: add 64-bit S-EL2 to EL exception table
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hw/intc/arm_gicv3_redist.c | 480 +++++++++++++++---
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target/arm: add MMU stage 1 for Secure EL2
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linux-user/arm/cpu_loop.c | 2 +-
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target/arm: add ARMv8.4-SEL2 system registers
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target/arm/cpu.c | 16 +-
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target/arm: handle VMID change in secure state
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target/arm/helper-a64.c | 4 +-
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target/arm: do S1_ptw_translate() before address space lookup
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target/arm/helper.c | 19 +-
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target/arm: translate NS bit in page-walks
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target/arm/hvf/hvf.c | 2 +-
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target/arm: generalize 2-stage page-walk condition
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target/arm/m_helper.c | 6 +-
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target/arm: secure stage 2 translation regime
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target/arm/op_helper.c | 13 -
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target/arm: set HPFAR_EL2.NS on secure stage 2 faults
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target/arm/translate-a64.c | 50 +-
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target/arm: revector to run-time pick target EL
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target/arm/translate-m-nocp.c | 12 +-
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target/arm: Implement SCR_EL2.EEL2
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target/arm/translate-neon.c | 21 +-
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target/arm: enable Secure EL2 in max CPU
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target/arm/translate-sve.c | 9 +-
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target/arm: refactor vae1_tlbmask()
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target/arm/translate-vfp.c | 76 +--
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target/arm/translate.c | 101 ++--
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docs/conf.py | 46 ++++-
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hw/intc/trace-events | 18 +-
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docs/devel/conf.py | 15 --
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31 files changed, 1890 insertions(+), 540 deletions(-)
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docs/index.html.in | 17 --
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docs/interop/conf.py | 28 ---
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docs/meson.build | 64 +++---
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docs/specs/conf.py | 16 --
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docs/system/arm/cpu-features.rst | 21 ++
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docs/system/conf.py | 28 ---
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docs/tools/conf.py | 37 ----
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docs/user/conf.py | 15 --
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include/qemu/xxhash.h | 98 +++++++++
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target/arm/cpu-param.h | 2 +-
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target/arm/cpu.h | 107 ++++++++--
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target/arm/internals.h | 45 +++++
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target/arm/cpu.c | 23 ++-
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target/arm/cpu64.c | 65 ++++--
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target/arm/helper-a64.c | 8 +-
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target/arm/helper.c | 414 ++++++++++++++++++++++++++-------------
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target/arm/m_helper.c | 2 +-
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target/arm/monitor.c | 1 +
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target/arm/op_helper.c | 4 +-
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target/arm/pauth_helper.c | 27 ++-
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target/arm/sve_helper.c | 33 ++--
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target/arm/tlb_helper.c | 3 +
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target/arm/translate-a64.c | 4 +
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target/arm/translate-sve.c | 31 ++-
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target/arm/translate.c | 36 +++-
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tests/qtest/arm-cpu-features.c | 13 ++
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tests/qtest/npcm7xx_adc-test.c | 1 +
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.gitlab-ci.yml | 4 +-
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30 files changed, 770 insertions(+), 438 deletions(-)
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delete mode 100644 docs/devel/conf.py
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delete mode 100644 docs/index.html.in
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delete mode 100644 docs/interop/conf.py
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delete mode 100644 docs/specs/conf.py
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delete mode 100644 docs/system/conf.py
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delete mode 100644 docs/tools/conf.py
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delete mode 100644 docs/user/conf.py
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