Series comparison

-[PULL v2 00/29] target-arm queue
+[PULL v3 00/23] target-arm queue
-v2: drop pvpanic-pci patches.
+v3: really fix the format string nit (oops)
-The following changes since commit f1fcb6851aba6dd9838886dc179717a11e344a1c:
+The following changes since commit eae587e8e3694b1aceab23239493fb4c7e1a80f5:
-  Merge remote-tracking branch 'remotes/huth-gitlab/tags/pull-request-2021-01-19' into staging (2021-01-19 11:57:07 +0000)
+  Merge remote-tracking branch 'remotes/armbru/tags/pull-qapi-2021-09-13' into staging (2021-09-13 11:00:30 +0100)
 are available in the Git repository at:
-  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210119-1
+  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210913-2
-for you to fetch changes up to b93f4fbdc48283a39089469c44a5529d79dc40a8:
+for you to fetch changes up to eec607843ca81eccab238fce86222be9c78b3675:
-  docs: Build and install all the docs in a single manual (2021-01-19 15:45:14 +0000)
+  hw/arm/mps2.c: Mark internal-only I2C buses as 'full' (2021-09-13 19:45:02 +0100)
 ----------------------------------------------------------------
 target-arm queue:
- * Implement IMPDEF pauth algorithm
+ * mark MPS2/MPS3 board-internal i2c buses as 'full' so that command
- * Support ARMv8.4-SEL2
+   line user-created devices are not plugged into them
- * Fix bug where we were truncating predicate vector lengths in SVE insns
+ * Take an exception if PSTATE.IL is set
- * npcm7xx_adc-test: Fix memleak in adc_qom_set
+ * Support an emulated ITS in the virt board
- * target/arm/m_helper: Silence GCC 10 maybe-uninitialized error
+ * Add support for kudo-bmc board
- * docs: Build and install all the docs in a single manual
+ * Probe for KVM_CAP_ARM_VM_IPA_SIZE when creating scratch VM
  * cadence_uart: Fix clock handling issues that prevented
    u-boot from running
 ----------------------------------------------------------------
-Gan Qixin (1):
+Bin Meng (6):
-      npcm7xx_adc-test: Fix memleak in adc_qom_set
+      hw/misc: zynq_slcr: Correctly compute output clocks in the reset exit phase
       hw/char: cadence_uart: Disable transmit when input clock is disabled
       hw/char: cadence_uart: Move clock/reset check to uart_can_receive()
       hw/char: cadence_uart: Convert to memop_with_attrs() ops
       hw/char: cadence_uart: Ignore access when unclocked or in reset for uart_{read, write}()
       hw/char: cadence_uart: Log a guest error when device is unclocked or in reset
-Peter Maydell (1):
+Chris Rauer (1):
-      docs: Build and install all the docs in a single manual
+      hw/arm: Add support for kudo-bmc board.
-Philippe Mathieu-Daudé (1):
+Marc Zyngier (1):
-      target/arm/m_helper: Silence GCC 10 maybe-uninitialized error
+      hw/arm/virt: KVM: Probe for KVM_CAP_ARM_VM_IPA_SIZE when creating scratch VM
-Richard Henderson (7):
+Peter Maydell (5):
-      target/arm: Implement an IMPDEF pauth algorithm
+      target/arm: Take an exception if PSTATE.IL is set
-      target/arm: Add cpu properties to control pauth
+      qdev: Support marking individual buses as 'full'
-      target/arm: Use object_property_add_bool for "sve" property
+      hw/arm/mps2-tz.c: Add extra data parameter to MakeDevFn
-      target/arm: Introduce PREDDESC field definitions
+      hw/arm/mps2-tz.c: Mark internal-only I2C buses as 'full'
-      target/arm: Update PFIRST, PNEXT for pred_desc
+      hw/arm/mps2.c: Mark internal-only I2C buses as 'full'
       target/arm: Update ZIP, UZP, TRN for pred_desc
       target/arm: Update REV, PUNPK for pred_desc
-Rémi Denis-Courmont (19):
+Richard Henderson (1):
-      target/arm: remove redundant tests
+      target/arm: Merge disas_a64_insn into aarch64_tr_translate_insn
       target/arm: add arm_is_el2_enabled() helper
       target/arm: use arm_is_el2_enabled() where applicable
       target/arm: use arm_hcr_el2_eff() where applicable
       target/arm: factor MDCR_EL2 common handling
       target/arm: Define isar_feature function to test for presence of SEL2
       target/arm: add 64-bit S-EL2 to EL exception table
       target/arm: add MMU stage 1 for Secure EL2
       target/arm: add ARMv8.4-SEL2 system registers
       target/arm: handle VMID change in secure state
       target/arm: do S1_ptw_translate() before address space lookup
       target/arm: translate NS bit in page-walks
       target/arm: generalize 2-stage page-walk condition
       target/arm: secure stage 2 translation regime
       target/arm: set HPFAR_EL2.NS on secure stage 2 faults
       target/arm: revector to run-time pick target EL
       target/arm: Implement SCR_EL2.EEL2
       target/arm: enable Secure EL2 in max CPU
       target/arm: refactor vae1_tlbmask()
- docs/conf.py                     |  46 ++++-
+Shashi Mallela (9):
- docs/devel/conf.py               |  15 --
+      hw/intc: GICv3 ITS initial framework
- docs/index.html.in               |  17 --
+      hw/intc: GICv3 ITS register definitions added
- docs/interop/conf.py             |  28 ---
+      hw/intc: GICv3 ITS command queue framework
- docs/meson.build                 |  64 +++---
+      hw/intc: GICv3 ITS Command processing
- docs/specs/conf.py               |  16 --
+      hw/intc: GICv3 ITS Feature enablement
- docs/system/arm/cpu-features.rst |  21 ++
+      hw/intc: GICv3 redistributor ITS processing
- docs/system/conf.py              |  28 ---
+      tests/data/acpi/virt: Add IORT files for ITS
- docs/tools/conf.py               |  37 ----
+      hw/arm/virt: add ITS support in virt GIC
- docs/user/conf.py                |  15 --
+      tests/data/acpi/virt: Update IORT files for ITS
  include/qemu/xxhash.h            |  98 +++++++++
  target/arm/cpu-param.h           |   2 +-
  target/arm/cpu.h                 | 107 ++++++++--
  target/arm/internals.h           |  45 +++++
  target/arm/cpu.c                 |  23 ++-
  target/arm/cpu64.c               |  65 ++++--
  target/arm/helper-a64.c          |   8 +-
  target/arm/helper.c              | 414 ++++++++++++++++++++++++++-------------
  target/arm/m_helper.c            |   2 +-
  target/arm/monitor.c             |   1 +
  target/arm/op_helper.c           |   4 +-
  target/arm/pauth_helper.c        |  27 ++-
  target/arm/sve_helper.c          |  33 ++--
  target/arm/tlb_helper.c          |   3 +
  target/arm/translate-a64.c       |   4 +
  target/arm/translate-sve.c       |  31 ++-
  target/arm/translate.c           |  36 +++-
  tests/qtest/arm-cpu-features.c   |  13 ++
  tests/qtest/npcm7xx_adc-test.c   |   1 +
  .gitlab-ci.yml                   |   4 +-
 files changed, 770 insertions(+), 438 deletions(-)
  delete mode 100644 docs/devel/conf.py
  delete mode 100644 docs/index.html.in
  delete mode 100644 docs/interop/conf.py
  delete mode 100644 docs/specs/conf.py
  delete mode 100644 docs/system/conf.py
  delete mode 100644 docs/tools/conf.py
  delete mode 100644 docs/user/conf.py
+ docs/system/arm/nuvoton.rst            |    1 +
+ hw/intc/gicv3_internal.h               |  188 ++++-
+ include/hw/arm/virt.h                  |    2 +
+ include/hw/intc/arm_gicv3_common.h     |   13 +
+ include/hw/intc/arm_gicv3_its_common.h |   32 +-
+ include/hw/qdev-core.h                 |   24 +
+ target/arm/cpu.h                       |    1 +
+ target/arm/kvm_arm.h                   |    4 +-
+ target/arm/syndrome.h                  |    5 +
+ target/arm/translate.h                 |    2 +
+ hw/arm/mps2-tz.c                       |   92 ++-
+ hw/arm/mps2.c                          |   12 +-
+ hw/arm/npcm7xx_boards.c                |   34 +
+ hw/arm/virt.c                          |   29 +-
+ hw/char/cadence_uart.c                 |   61 +-
+ hw/intc/arm_gicv3.c                    |   14 +
+ hw/intc/arm_gicv3_common.c             |   13 +
+ hw/intc/arm_gicv3_cpuif.c              |    7 +-
+ hw/intc/arm_gicv3_dist.c               |    5 +-
+ hw/intc/arm_gicv3_its.c                | 1322 ++++++++++++++++++++++++++++++++
+ hw/intc/arm_gicv3_its_common.c         |    7 +-
+ hw/intc/arm_gicv3_its_kvm.c            |    2 +-
+ hw/intc/arm_gicv3_redist.c             |  153 +++-
+ hw/misc/zynq_slcr.c                    |   31 +-
+ softmmu/qdev-monitor.c                 |    7 +-
+ target/arm/helper-a64.c                |    1 +
+ target/arm/helper.c                    |    8 +
+ target/arm/kvm.c                       |    7 +-
+ target/arm/translate-a64.c             |  255 +++---
+ target/arm/translate.c                 |   21 +
+ hw/intc/meson.build                    |    1 +
+ tests/data/acpi/virt/IORT              |  Bin 0 -> 124 bytes
+ tests/data/acpi/virt/IORT.memhp        |  Bin 0 -> 124 bytes
+ tests/data/acpi/virt/IORT.numamem      |  Bin 0 -> 124 bytes
+ tests/data/acpi/virt/IORT.pxb          |  Bin 0 -> 124 bytes
+files changed, 2144 insertions(+), 210 deletions(-)
+ create mode 100644 hw/intc/arm_gicv3_its.c
+ create mode 100644 tests/data/acpi/virt/IORT
+ create mode 100644 tests/data/acpi/virt/IORT.memhp
+ create mode 100644 tests/data/acpi/virt/IORT.numamem
+ create mode 100644 tests/data/acpi/virt/IORT.pxb

v2: drop pvpanic-pci patches.

The following changes since commit f1fcb6851aba6dd9838886dc179717a11e344a1c:

Merge remote-tracking branch 'remotes/huth-gitlab/tags/pull-request-2021-01-19' into staging (2021-01-19 11:57:07 +0000)

are available in the Git repository at:

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210119-1

for you to fetch changes up to b93f4fbdc48283a39089469c44a5529d79dc40a8:

docs: Build and install all the docs in a single manual (2021-01-19 15:45:14 +0000)

----------------------------------------------------------------
target-arm queue:
 * Implement IMPDEF pauth algorithm
 * Support ARMv8.4-SEL2
 * Fix bug where we were truncating predicate vector lengths in SVE insns
 * npcm7xx_adc-test: Fix memleak in adc_qom_set
 * target/arm/m_helper: Silence GCC 10 maybe-uninitialized error
 * docs: Build and install all the docs in a single manual

----------------------------------------------------------------
Gan Qixin (1):
      npcm7xx_adc-test: Fix memleak in adc_qom_set

Peter Maydell (1):
      docs: Build and install all the docs in a single manual

Philippe Mathieu-Daudé (1):
      target/arm/m_helper: Silence GCC 10 maybe-uninitialized error

Richard Henderson (7):
      target/arm: Implement an IMPDEF pauth algorithm
      target/arm: Add cpu properties to control pauth
      target/arm: Use object_property_add_bool for "sve" property
      target/arm: Introduce PREDDESC field definitions
      target/arm: Update PFIRST, PNEXT for pred_desc
      target/arm: Update ZIP, UZP, TRN for pred_desc
      target/arm: Update REV, PUNPK for pred_desc

Rémi Denis-Courmont (19):
      target/arm: remove redundant tests
      target/arm: add arm_is_el2_enabled() helper
      target/arm: use arm_is_el2_enabled() where applicable
      target/arm: use arm_hcr_el2_eff() where applicable
      target/arm: factor MDCR_EL2 common handling
      target/arm: Define isar_feature function to test for presence of SEL2
      target/arm: add 64-bit S-EL2 to EL exception table
      target/arm: add MMU stage 1 for Secure EL2
      target/arm: add ARMv8.4-SEL2 system registers
      target/arm: handle VMID change in secure state
      target/arm: do S1_ptw_translate() before address space lookup
      target/arm: translate NS bit in page-walks
      target/arm: generalize 2-stage page-walk condition
      target/arm: secure stage 2 translation regime
      target/arm: set HPFAR_EL2.NS on secure stage 2 faults
      target/arm: revector to run-time pick target EL
      target/arm: Implement SCR_EL2.EEL2
      target/arm: enable Secure EL2 in max CPU
      target/arm: refactor vae1_tlbmask()

v3: really fix the format string nit (oops)

The following changes since commit eae587e8e3694b1aceab23239493fb4c7e1a80f5:

Merge remote-tracking branch 'remotes/armbru/tags/pull-qapi-2021-09-13' into staging (2021-09-13 11:00:30 +0100)

are available in the Git repository at:

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210913-2

for you to fetch changes up to eec607843ca81eccab238fce86222be9c78b3675:

hw/arm/mps2.c: Mark internal-only I2C buses as 'full' (2021-09-13 19:45:02 +0100)

----------------------------------------------------------------
target-arm queue:
 * mark MPS2/MPS3 board-internal i2c buses as 'full' so that command
   line user-created devices are not plugged into them
 * Take an exception if PSTATE.IL is set
 * Support an emulated ITS in the virt board
 * Add support for kudo-bmc board
 * Probe for KVM_CAP_ARM_VM_IPA_SIZE when creating scratch VM
 * cadence_uart: Fix clock handling issues that prevented
   u-boot from running

----------------------------------------------------------------
Bin Meng (6):
      hw/misc: zynq_slcr: Correctly compute output clocks in the reset exit phase
      hw/char: cadence_uart: Disable transmit when input clock is disabled
      hw/char: cadence_uart: Move clock/reset check to uart_can_receive()
      hw/char: cadence_uart: Convert to memop_with_attrs() ops
      hw/char: cadence_uart: Ignore access when unclocked or in reset for uart_{read, write}()
      hw/char: cadence_uart: Log a guest error when device is unclocked or in reset

Chris Rauer (1):
      hw/arm: Add support for kudo-bmc board.

Marc Zyngier (1):
      hw/arm/virt: KVM: Probe for KVM_CAP_ARM_VM_IPA_SIZE when creating scratch VM

Peter Maydell (5):
      target/arm: Take an exception if PSTATE.IL is set
      qdev: Support marking individual buses as 'full'
      hw/arm/mps2-tz.c: Add extra data parameter to MakeDevFn
      hw/arm/mps2-tz.c: Mark internal-only I2C buses as 'full'
      hw/arm/mps2.c: Mark internal-only I2C buses as 'full'

Richard Henderson (1):
      target/arm: Merge disas_a64_insn into aarch64_tr_translate_insn

Shashi Mallela (9):
      hw/intc: GICv3 ITS initial framework
      hw/intc: GICv3 ITS register definitions added
      hw/intc: GICv3 ITS command queue framework
      hw/intc: GICv3 ITS Command processing
      hw/intc: GICv3 ITS Feature enablement
      hw/intc: GICv3 redistributor ITS processing
      tests/data/acpi/virt: Add IORT files for ITS
      hw/arm/virt: add ITS support in virt GIC
      tests/data/acpi/virt: Update IORT files for ITS