[PULL v2 00/29] target-arm queue
[PULL v2 00/54] target-arm queue
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v2: drop pvpanic-pci patches.
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v1->v2: fix format-string errors on 32-bit hosts in xilinx csu dma model.
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The following changes since commit f1fcb6851aba6dd9838886dc179717a11e344a1c:
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-- PMM
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Merge remote-tracking branch 'remotes/huth-gitlab/tags/pull-request-2021-01-19' into staging (2021-01-19 11:57:07 +0000)
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The following changes since commit 0436c55edf6b357ff56e2a5bf688df8636f83456:
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Merge remote-tracking branch 'remotes/bonzini-gitlab/tags/for-upstream' into staging (2021-03-08 13:51:41 +0000)
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are available in the Git repository at:
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are available in the Git repository at:
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210119-1
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210310
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for you to fetch changes up to b93f4fbdc48283a39089469c44a5529d79dc40a8:
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for you to fetch changes up to 81b3ddaf8772ec6f88d372e52f9b433cfa46bc46:
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docs: Build and install all the docs in a single manual (2021-01-19 15:45:14 +0000)
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hw/timer/renesas_tmr: Fix use of uninitialized data in read_tcnt() (2021-03-10 13:54:51 +0000)
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----------------------------------------------------------------
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----------------------------------------------------------------
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target-arm queue:
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target-arm queue:
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* Implement IMPDEF pauth algorithm
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* Add new mps3-an547 board
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* Support ARMv8.4-SEL2
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* target/arm: Restrict v7A TCG cpus to TCG accel
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* Fix bug where we were truncating predicate vector lengths in SVE insns
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* Implement a Xilinx CSU DMA model
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* npcm7xx_adc-test: Fix memleak in adc_qom_set
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* hw/timer/renesas_tmr: Fix use of uninitialized data in read_tcnt()
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* target/arm/m_helper: Silence GCC 10 maybe-uninitialized error
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* docs: Build and install all the docs in a single manual
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----------------------------------------------------------------
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----------------------------------------------------------------
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Gan Qixin (1):
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Peter Maydell (48):
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npcm7xx_adc-test: Fix memleak in adc_qom_set
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clock: Add ClockEvent parameter to callbacks
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clock: Add ClockPreUpdate callback event type
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Peter Maydell (1):
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clock: Add clock_ns_to_ticks() function
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docs: Build and install all the docs in a single manual
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hw/timer/npcm7xx_timer: Use new clock_ns_to_ticks()
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hw/arm/armsse: Introduce SSE subsystem version property
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hw/misc/iotkit-sysctl: Remove is_sse200 flag
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hw/misc/iotkit-secctl.c: Implement SSE-300 PID register values
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hw/misc/iotkit-sysinfo.c: Implement SSE-300 PID register values
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hw/arm/armsse.c: Use correct SYS_CONFIG0 register value for SSE-300
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hw/misc/iotkit-sysinfo.c: Implement SYS_CONFIG1 and IIDR
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hw/timer/sse-counter: Model the SSE Subsystem System Counter
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hw/timer/sse-timer: Model the SSE Subsystem System Timer
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hw/misc/iotkit-sysctl: Add SSE-300 cases which match SSE-200 behaviour
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hw/misc/iotkit-sysctl: Handle CPU_WAIT, NMI_ENABLE for SSE-300
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hw/misc/iotkit-sysctl: Handle INITSVTOR* for SSE-300
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hw/misc/iotkit-sysctl: Implement dummy version of SSE-300 PWRCTRL register
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hw/misc/iotkit-sysctl: Handle SSE-300 changes to PDCM_PD_*_SENSE registers
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hw/misc/iotkit-sysctl: Implement SSE-200 and SSE-300 PID register values
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hw/arm/Kconfig: Move ARMSSE_CPUID and ARMSSE_MHU stanzas to hw/misc
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hw/misc/sse-cpu-pwrctrl: Implement SSE-300 CPU<N>_PWRCTRL register block
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hw/arm/armsse: Use an array for apb_ppc fields in the state structure
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hw/arm/armsse: Add a define for number of IRQs used by the SSE itself
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hw/arm/armsse: Add framework for data-driven device placement
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hw/arm/armsse: Move dual-timer device into data-driven framework
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hw/arm/armsse: Move watchdogs into data-driven framework
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hw/arm/armsse: Move s32ktimer into data-driven framework
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hw/arm/armsse: Move sysinfo register block into data-driven framework
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hw/arm/armsse: Move sysctl register block into data-driven framework
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hw/arm/armsse: Move PPUs into data-driven framework
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hw/arm/armsse: Add missing SSE-200 SYS_PPU
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hw/arm/armsse: Indirect irq_is_common[] through ARMSSEInfo
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hw/arm/armsse: Add support for SSE variants with a system counter
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hw/arm/armsse: Add support for TYPE_SSE_TIMER in ARMSSEDeviceInfo
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hw/arm/armsse: Support variants with ARMSSE_CPU_PWRCTRL block
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hw/arm/armsse: Add SSE-300 support
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hw/arm/mps2-tz: Make UART overflow IRQ board-specific
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hw/misc/mps2-fpgaio: Fold counters subsection into main vmstate
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hw/misc/mps2-fpgaio: Support AN547 DBGCTRL register
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hw/misc/mps2-scc: Implement changes for AN547
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hw/arm/mps2-tz: Support running APB peripherals on different clock
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hw/arm/mps2-tz: Make initsvtor0 setting board-specific
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hw/arm/mps2-tz: Add new mps3-an547 board
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docs/system/arm/mps2.rst: Document the new mps3-an547 board
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tests/qtest/sse-timer-test: Add simple test of the SSE counter
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tests/qtest/sse-timer-test: Test the system timer
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tests/qtest/sse-timer-test: Test counter scaling changes
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hw/timer/renesas_tmr: Prefix constants for CSS values with CSS_
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hw/timer/renesas_tmr: Fix use of uninitialized data in read_tcnt()
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Philippe Mathieu-Daudé (1):
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Philippe Mathieu-Daudé (1):
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target/arm/m_helper: Silence GCC 10 maybe-uninitialized error
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target/arm: Restrict v7A TCG cpus to TCG accel
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Richard Henderson (7):
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Xuzhou Cheng (5):
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target/arm: Implement an IMPDEF pauth algorithm
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hw/dma: Implement a Xilinx CSU DMA model
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target/arm: Add cpu properties to control pauth
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hw/arm: xlnx-zynqmp: Clean up coding convention issues
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target/arm: Use object_property_add_bool for "sve" property
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hw/arm: xlnx-zynqmp: Connect a Xilinx CSU DMA module for QSPI
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target/arm: Introduce PREDDESC field definitions
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hw/ssi: xilinx_spips: Clean up coding convention issues
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target/arm: Update PFIRST, PNEXT for pred_desc
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hw/ssi: xilinx_spips: Remove DMA related dead codes from zynqmp_spips
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target/arm: Update ZIP, UZP, TRN for pred_desc
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target/arm: Update REV, PUNPK for pred_desc
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Rémi Denis-Courmont (19):
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docs/devel/clocks.rst | 71 ++-
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target/arm: remove redundant tests
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docs/system/arm/mps2.rst | 6 +-
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target/arm: add arm_is_el2_enabled() helper
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include/hw/arm/armsse-version.h | 42 ++
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target/arm: use arm_is_el2_enabled() where applicable
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include/hw/arm/armsse.h | 40 +-
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target/arm: use arm_hcr_el2_eff() where applicable
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include/hw/arm/xlnx-zynqmp.h | 5 +-
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target/arm: factor MDCR_EL2 common handling
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include/hw/clock.h | 63 ++-
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target/arm: Define isar_feature function to test for presence of SEL2
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include/hw/dma/xlnx_csu_dma.h | 52 ++
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target/arm: add 64-bit S-EL2 to EL exception table
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include/hw/misc/armsse-cpu-pwrctrl.h | 40 ++
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target/arm: add MMU stage 1 for Secure EL2
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include/hw/misc/iotkit-secctl.h | 2 +
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target/arm: add ARMv8.4-SEL2 system registers
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include/hw/misc/iotkit-sysctl.h | 13 +-
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target/arm: handle VMID change in secure state
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include/hw/misc/iotkit-sysinfo.h | 2 +
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target/arm: do S1_ptw_translate() before address space lookup
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include/hw/misc/mps2-fpgaio.h | 2 +
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target/arm: translate NS bit in page-walks
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include/hw/qdev-clock.h | 17 +-
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target/arm: generalize 2-stage page-walk condition
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include/hw/ssi/xilinx_spips.h | 2 +-
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target/arm: secure stage 2 translation regime
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include/hw/timer/sse-counter.h | 105 ++++
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target/arm: set HPFAR_EL2.NS on secure stage 2 faults
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include/hw/timer/sse-timer.h | 53 ++
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target/arm: revector to run-time pick target EL
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hw/adc/npcm7xx_adc.c | 2 +-
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target/arm: Implement SCR_EL2.EEL2
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hw/arm/armsse.c | 1008 +++++++++++++++++++++++++---------
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target/arm: enable Secure EL2 in max CPU
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hw/arm/mps2-tz.c | 168 +++++-
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target/arm: refactor vae1_tlbmask()
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hw/arm/xlnx-zynqmp.c | 21 +-
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hw/char/cadence_uart.c | 4 +-
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hw/char/ibex_uart.c | 4 +-
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hw/char/pl011.c | 5 +-
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hw/core/clock.c | 24 +-
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hw/core/qdev-clock.c | 8 +-
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hw/dma/xlnx_csu_dma.c | 745 +++++++++++++++++++++++++
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hw/mips/cps.c | 2 +-
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hw/misc/armsse-cpu-pwrctrl.c | 149 +++++
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hw/misc/bcm2835_cprman.c | 23 +-
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hw/misc/iotkit-secctl.c | 50 +-
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hw/misc/iotkit-sysctl.c | 522 +++++++++++++++---
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hw/misc/iotkit-sysinfo.c | 51 +-
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hw/misc/mps2-fpgaio.c | 52 +-
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hw/misc/mps2-scc.c | 15 +-
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hw/misc/npcm7xx_clk.c | 26 +-
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hw/misc/npcm7xx_pwm.c | 2 +-
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hw/misc/zynq_slcr.c | 5 +-
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hw/ssi/xilinx_spips.c | 33 +-
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hw/timer/cmsdk-apb-dualtimer.c | 5 +-
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hw/timer/cmsdk-apb-timer.c | 4 +-
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hw/timer/npcm7xx_timer.c | 6 +-
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hw/timer/renesas_tmr.c | 33 +-
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hw/timer/sse-counter.c | 474 ++++++++++++++++
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hw/timer/sse-timer.c | 470 ++++++++++++++++
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hw/watchdog/cmsdk-apb-watchdog.c | 5 +-
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target/arm/cpu.c | 335 -----------
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target/arm/cpu_tcg.c | 318 +++++++++++
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target/mips/cpu.c | 2 +-
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tests/qtest/sse-timer-test.c | 240 ++++++++
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MAINTAINERS | 7 +
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hw/arm/Kconfig | 10 +-
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hw/dma/Kconfig | 4 +
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hw/dma/meson.build | 1 +
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hw/misc/Kconfig | 9 +
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hw/misc/meson.build | 1 +
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hw/misc/trace-events | 4 +
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hw/timer/Kconfig | 6 +
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hw/timer/meson.build | 2 +
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hw/timer/trace-events | 12 +
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tests/qtest/meson.build | 1 +
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60 files changed, 4537 insertions(+), 846 deletions(-)
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create mode 100644 include/hw/arm/armsse-version.h
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create mode 100644 include/hw/dma/xlnx_csu_dma.h
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create mode 100644 include/hw/misc/armsse-cpu-pwrctrl.h
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create mode 100644 include/hw/timer/sse-counter.h
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create mode 100644 include/hw/timer/sse-timer.h
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create mode 100644 hw/dma/xlnx_csu_dma.c
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create mode 100644 hw/misc/armsse-cpu-pwrctrl.c
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create mode 100644 hw/timer/sse-counter.c
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create mode 100644 hw/timer/sse-timer.c
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create mode 100644 tests/qtest/sse-timer-test.c
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docs/conf.py | 46 ++++-
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docs/devel/conf.py | 15 --
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docs/index.html.in | 17 --
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docs/interop/conf.py | 28 ---
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docs/meson.build | 64 +++---
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docs/specs/conf.py | 16 --
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docs/system/arm/cpu-features.rst | 21 ++
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docs/system/conf.py | 28 ---
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docs/tools/conf.py | 37 ----
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docs/user/conf.py | 15 --
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include/qemu/xxhash.h | 98 +++++++++
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target/arm/cpu-param.h | 2 +-
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target/arm/cpu.h | 107 ++++++++--
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target/arm/internals.h | 45 +++++
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target/arm/cpu.c | 23 ++-
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target/arm/cpu64.c | 65 ++++--
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target/arm/helper-a64.c | 8 +-
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target/arm/helper.c | 414 ++++++++++++++++++++++++++-------------
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target/arm/m_helper.c | 2 +-
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target/arm/monitor.c | 1 +
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target/arm/op_helper.c | 4 +-
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target/arm/pauth_helper.c | 27 ++-
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target/arm/sve_helper.c | 33 ++--
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target/arm/tlb_helper.c | 3 +
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target/arm/translate-a64.c | 4 +
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target/arm/translate-sve.c | 31 ++-
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target/arm/translate.c | 36 +++-
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tests/qtest/arm-cpu-features.c | 13 ++
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tests/qtest/npcm7xx_adc-test.c | 1 +
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.gitlab-ci.yml | 4 +-
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30 files changed, 770 insertions(+), 438 deletions(-)
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delete mode 100644 docs/devel/conf.py
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delete mode 100644 docs/index.html.in
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delete mode 100644 docs/interop/conf.py
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delete mode 100644 docs/specs/conf.py
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delete mode 100644 docs/system/conf.py
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delete mode 100644 docs/tools/conf.py
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delete mode 100644 docs/user/conf.py
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