| 1 | v2: drop pvpanic-pci patches. | 1 | Massively slimmed down v2: MemTag broke bsd-user, and the npcm7xx |
|---|---|---|---|
| 2 | ethernet device failed 'make check' on big-endian hosts. | ||
| 2 | 3 | ||
| 3 | The following changes since commit f1fcb6851aba6dd9838886dc179717a11e344a1c: | 4 | -- PMM |
| 4 | 5 | ||
| 5 | Merge remote-tracking branch 'remotes/huth-gitlab/tags/pull-request-2021-01-19' into staging (2021-01-19 11:57:07 +0000) | 6 | The following changes since commit 83339e21d05c824ebc9131d644f25c23d0e41ecf: |
| 7 | |||
| 8 | Merge remote-tracking branch 'remotes/stefanha-gitlab/tags/block-pull-request' into staging (2021-02-10 15:42:20 +0000) | ||
| 6 | 9 | ||
| 7 | are available in the Git repository at: | 10 | are available in the Git repository at: |
| 8 | 11 | ||
| 9 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210119-1 | 12 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210211-1 |
| 10 | 13 | ||
| 11 | for you to fetch changes up to b93f4fbdc48283a39089469c44a5529d79dc40a8: | 14 | for you to fetch changes up to d3c1183ffeb71ca3a783eae3d7e1c51e71e8a621: |
| 12 | 15 | ||
| 13 | docs: Build and install all the docs in a single manual (2021-01-19 15:45:14 +0000) | 16 | target/arm: Correctly initialize MDCR_EL2.HPMN (2021-02-11 19:48:09 +0000) |
| 14 | 17 | ||
| 15 | ---------------------------------------------------------------- | 18 | ---------------------------------------------------------------- |
| 16 | target-arm queue: | 19 | target-arm queue: |
| 17 | * Implement IMPDEF pauth algorithm | 20 | * Correctly initialize MDCR_EL2.HPMN |
| 18 | * Support ARMv8.4-SEL2 | 21 | * versal: Use nr_apu_cpus in favor of hard coding 2 |
| 19 | * Fix bug where we were truncating predicate vector lengths in SVE insns | 22 | * accel/tcg: Add URL of clang bug to comment about our workaround |
| 20 | * npcm7xx_adc-test: Fix memleak in adc_qom_set | 23 | * Add support for FEAT_DIT, Data Independent Timing |
| 21 | * target/arm/m_helper: Silence GCC 10 maybe-uninitialized error | 24 | * Remove GPIO from unimplemented NPCM7XX |
| 22 | * docs: Build and install all the docs in a single manual | 25 | * Fix SCR RES1 handling |
| 26 | * Don't migrate CPUARMState.features | ||
| 23 | 27 | ||
| 24 | ---------------------------------------------------------------- | 28 | ---------------------------------------------------------------- |
| 25 | Gan Qixin (1): | 29 | Aaron Lindsay (1): |
| 26 | npcm7xx_adc-test: Fix memleak in adc_qom_set | 30 | target/arm: Don't migrate CPUARMState.features |
| 27 | 31 | ||
| 28 | Peter Maydell (1): | 32 | Daniel Müller (1): |
| 29 | docs: Build and install all the docs in a single manual | 33 | target/arm: Correctly initialize MDCR_EL2.HPMN |
| 30 | 34 | ||
| 31 | Philippe Mathieu-Daudé (1): | 35 | Edgar E. Iglesias (1): |
| 32 | target/arm/m_helper: Silence GCC 10 maybe-uninitialized error | 36 | hw/arm: versal: Use nr_apu_cpus in favor of hard coding 2 |
| 33 | 37 | ||
| 34 | Richard Henderson (7): | 38 | Hao Wu (1): |
| 35 | target/arm: Implement an IMPDEF pauth algorithm | 39 | hw/arm: Remove GPIO from unimplemented NPCM7XX |
| 36 | target/arm: Add cpu properties to control pauth | ||
| 37 | target/arm: Use object_property_add_bool for "sve" property | ||
| 38 | target/arm: Introduce PREDDESC field definitions | ||
| 39 | target/arm: Update PFIRST, PNEXT for pred_desc | ||
| 40 | target/arm: Update ZIP, UZP, TRN for pred_desc | ||
| 41 | target/arm: Update REV, PUNPK for pred_desc | ||
| 42 | 40 | ||
| 43 | Rémi Denis-Courmont (19): | 41 | Mike Nawrocki (1): |
| 44 | target/arm: remove redundant tests | 42 | target/arm: Fix SCR RES1 handling |
| 45 | target/arm: add arm_is_el2_enabled() helper | ||
| 46 | target/arm: use arm_is_el2_enabled() where applicable | ||
| 47 | target/arm: use arm_hcr_el2_eff() where applicable | ||
| 48 | target/arm: factor MDCR_EL2 common handling | ||
| 49 | target/arm: Define isar_feature function to test for presence of SEL2 | ||
| 50 | target/arm: add 64-bit S-EL2 to EL exception table | ||
| 51 | target/arm: add MMU stage 1 for Secure EL2 | ||
| 52 | target/arm: add ARMv8.4-SEL2 system registers | ||
| 53 | target/arm: handle VMID change in secure state | ||
| 54 | target/arm: do S1_ptw_translate() before address space lookup | ||
| 55 | target/arm: translate NS bit in page-walks | ||
| 56 | target/arm: generalize 2-stage page-walk condition | ||
| 57 | target/arm: secure stage 2 translation regime | ||
| 58 | target/arm: set HPFAR_EL2.NS on secure stage 2 faults | ||
| 59 | target/arm: revector to run-time pick target EL | ||
| 60 | target/arm: Implement SCR_EL2.EEL2 | ||
| 61 | target/arm: enable Secure EL2 in max CPU | ||
| 62 | target/arm: refactor vae1_tlbmask() | ||
| 63 | 43 | ||
| 64 | docs/conf.py | 46 ++++- | 44 | Peter Maydell (2): |
| 65 | docs/devel/conf.py | 15 -- | 45 | arm: Update infocenter.arm.com URLs |
| 66 | docs/index.html.in | 17 -- | 46 | accel/tcg: Add URL of clang bug to comment about our workaround |
| 67 | docs/interop/conf.py | 28 --- | ||
| 68 | docs/meson.build | 64 +++--- | ||
| 69 | docs/specs/conf.py | 16 -- | ||
| 70 | docs/system/arm/cpu-features.rst | 21 ++ | ||
| 71 | docs/system/conf.py | 28 --- | ||
| 72 | docs/tools/conf.py | 37 ---- | ||
| 73 | docs/user/conf.py | 15 -- | ||
| 74 | include/qemu/xxhash.h | 98 +++++++++ | ||
| 75 | target/arm/cpu-param.h | 2 +- | ||
| 76 | target/arm/cpu.h | 107 ++++++++-- | ||
| 77 | target/arm/internals.h | 45 +++++ | ||
| 78 | target/arm/cpu.c | 23 ++- | ||
| 79 | target/arm/cpu64.c | 65 ++++-- | ||
| 80 | target/arm/helper-a64.c | 8 +- | ||
| 81 | target/arm/helper.c | 414 ++++++++++++++++++++++++++------------- | ||
| 82 | target/arm/m_helper.c | 2 +- | ||
| 83 | target/arm/monitor.c | 1 + | ||
| 84 | target/arm/op_helper.c | 4 +- | ||
| 85 | target/arm/pauth_helper.c | 27 ++- | ||
| 86 | target/arm/sve_helper.c | 33 ++-- | ||
| 87 | target/arm/tlb_helper.c | 3 + | ||
| 88 | target/arm/translate-a64.c | 4 + | ||
| 89 | target/arm/translate-sve.c | 31 ++- | ||
| 90 | target/arm/translate.c | 36 +++- | ||
| 91 | tests/qtest/arm-cpu-features.c | 13 ++ | ||
| 92 | tests/qtest/npcm7xx_adc-test.c | 1 + | ||
| 93 | .gitlab-ci.yml | 4 +- | ||
| 94 | 30 files changed, 770 insertions(+), 438 deletions(-) | ||
| 95 | delete mode 100644 docs/devel/conf.py | ||
| 96 | delete mode 100644 docs/index.html.in | ||
| 97 | delete mode 100644 docs/interop/conf.py | ||
| 98 | delete mode 100644 docs/specs/conf.py | ||
| 99 | delete mode 100644 docs/system/conf.py | ||
| 100 | delete mode 100644 docs/tools/conf.py | ||
| 101 | delete mode 100644 docs/user/conf.py | ||
| 102 | 47 | ||
| 48 | Rebecca Cran (4): | ||
| 49 | target/arm: Add support for FEAT_DIT, Data Independent Timing | ||
| 50 | target/arm: Support AA32 DIT by moving PSTATE_SS from cpsr into env->pstate | ||
| 51 | target/arm: Set ID_AA64PFR0.DIT and ID_PFR0.DIT to 1 for "max" AA64 CPU | ||
| 52 | target/arm: Set ID_PFR0.DIT to 1 for "max" 32-bit CPU | ||
| 53 | |||
| 54 | include/hw/dma/pl080.h | 7 ++-- | ||
| 55 | include/hw/misc/arm_integrator_debug.h | 2 +- | ||
| 56 | include/hw/ssi/pl022.h | 5 ++- | ||
| 57 | target/arm/cpu.h | 17 ++++++++ | ||
| 58 | target/arm/internals.h | 6 +++ | ||
| 59 | accel/tcg/cpu-exec.c | 25 +++++++++--- | ||
| 60 | hw/arm/aspeed_ast2600.c | 2 +- | ||
| 61 | hw/arm/musca.c | 4 +- | ||
| 62 | hw/arm/npcm7xx.c | 8 ---- | ||
| 63 | hw/arm/xlnx-versal.c | 4 +- | ||
| 64 | hw/misc/arm_integrator_debug.c | 2 +- | ||
| 65 | hw/timer/arm_timer.c | 7 ++-- | ||
| 66 | target/arm/cpu.c | 4 ++ | ||
| 67 | target/arm/cpu64.c | 5 +++ | ||
| 68 | target/arm/helper-a64.c | 27 +++++++++++-- | ||
| 69 | target/arm/helper.c | 71 +++++++++++++++++++++++++++------- | ||
| 70 | target/arm/machine.c | 2 +- | ||
| 71 | target/arm/op_helper.c | 9 +---- | ||
| 72 | target/arm/translate-a64.c | 12 ++++++ | ||
| 73 | 19 files changed, 164 insertions(+), 55 deletions(-) | ||
| 74 | diff view generated by jsdifflib |