[PULL 00/12] riscv-to-apply queue
[PULL 00/28] riscv-to-apply queue
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The following changes since commit 825a215c003cd028e26c7d19aa5049d957345f43:
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The following changes since commit ad10b4badc1dd5b28305f9b9f1168cf0aa3ae946:
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Merge remote-tracking branch 'remotes/kraxel/tags/audio-20210115-pull-request' into staging (2021-01-15 22:21:21 +0000)
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Merge tag 'pull-error-2024-05-27' of https://repo.or.cz/qemu/armbru into staging (2024-05-27 06:40:42 -0700)
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are available in the Git repository at:
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are available in the Git repository at:
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6
7
git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20210117-3
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https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20240528
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8
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for you to fetch changes up to a8259b53230782f5e0a0d66013655c4ed5d71b7e:
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for you to fetch changes up to 1806da76cb81088ea026ca3441551782b850e393:
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riscv: Pass RISCVHartArrayState by pointer (2021-01-16 14:34:46 -0800)
11
target/riscv: raise an exception when CSRRS/CSRRC writes a read-only CSR (2024-05-28 12:20:27 +1000)
12
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13
----------------------------------------------------------------
13
----------------------------------------------------------------
14
First RISC-V PR for 6.0
14
RISC-V PR for 9.1
15
15
16
This PR:
16
* APLICs add child earlier than realize
17
- Fixes some issues with the m25p80
17
* Fix exposure of Zkr
18
- Improves GDB support for RISC-V
18
* Raise exceptions on wrs.nto
19
- Fixes some Linux boot issues, specifiaclly 32-bit boot failures
19
* Implement SBI debug console (DBCN) calls for KVM
20
- Enforces PMP exceptions correctly
20
* Support 64-bit addresses for initrd
21
- Fixes some Coverity issues
21
* Change RISCV_EXCP_SEMIHOST exception number to 63
22
* Tolerate KVM disable ext errors
23
* Set tval in breakpoints
24
* Add support for Zve32x extension
25
* Add support for Zve64x extension
26
* Relax vector register check in RISCV gdbstub
27
* Fix the element agnostic Vector function problem
28
* Fix Zvkb extension config
29
* Implement dynamic establishment of custom decoder
30
* Add th.sxstatus CSR emulation
31
* Fix Zvfhmin checking for vfwcvt.f.f.v and vfncvt.f.f.w instructions
32
* Check single width operator for vector fp widen instructions
33
* Check single width operator for vfncvt.rod.f.f.w
34
* Remove redudant SEW checking for vector fp narrow/widen instructions
35
* Prioritize pmp errors in raise_mmu_exception()
36
* Do not set mtval2 for non guest-page faults
37
* Remove experimental prefix from "B" extension
38
* Fixup CBO extension register calculation
39
* Fix the hart bit setting of AIA
40
* Fix reg_width in ricsv_gen_dynamic_vector_feature()
41
* Decode all of the pmpcfg and pmpaddr CSRs
42
* Raise an exception when CSRRS/CSRRC writes a read-only CSR
22
43
23
----------------------------------------------------------------
44
----------------------------------------------------------------
24
Alistair Francis (1):
45
Alexei Filippov (1):
25
riscv: Pass RISCVHartArrayState by pointer
46
target/riscv: do not set mtval2 for non guest-page faults
26
47
27
Atish Patra (2):
48
Alistair Francis (2):
28
RISC-V: Place DTB at 3GB boundary instead of 4GB
49
target/riscv: rvzicbo: Fixup CBO extension register calculation
29
target/riscv/pmp: Raise exception if no PMP entry is configured
50
disas/riscv: Decode all of the pmpcfg and pmpaddr CSRs
30
51
31
Bin Meng (6):
52
Andrew Jones (2):
32
hw/block: m25p80: Don't write to flash if write is disabled
53
target/riscv/kvm: Fix exposure of Zkr
33
hw/riscv: sifive_u: Use SIFIVE_U_CPU for mc->default_cpu_type
54
target/riscv: Raise exceptions on wrs.nto
34
target/riscv: Make csr_ops[CSR_TABLE_SIZE] external
35
target/riscv: Add CSR name in the CSR function table
36
target/riscv: Generate the GDB XML file for CSR registers dynamically
37
target/riscv: Remove built-in GDB XML files for CSRs
38
55
39
Green Wan (1):
56
Cheng Yang (1):
40
hw/misc/sifive_u_otp: handling the fails of blk_pread and blk_pwrite
57
hw/riscv/boot.c: Support 64-bit address for initrd
41
58
42
Sylvain Pelissier (1):
59
Christoph Müllner (1):
43
gdb: riscv: Add target description
60
riscv: thead: Add th.sxstatus CSR emulation
44
61
45
Xuzhou Cheng (1):
62
Clément Léger (1):
46
hw/block: m25p80: Implement AAI-WP command support for SST flashes
63
target/riscv: change RISCV_EXCP_SEMIHOST exception number to 63
47
64
48
default-configs/targets/riscv32-linux-user.mak | 2 +-
65
Daniel Henrique Barboza (6):
49
default-configs/targets/riscv32-softmmu.mak | 2 +-
66
target/riscv/kvm: implement SBI debug console (DBCN) calls
50
default-configs/targets/riscv64-linux-user.mak | 2 +-
67
target/riscv/kvm: tolerate KVM disable ext errors
51
default-configs/targets/riscv64-softmmu.mak | 2 +-
68
target/riscv/debug: set tval=pc in breakpoint exceptions
52
include/hw/riscv/boot.h | 6 +-
69
trans_privileged.c.inc: set (m|s)tval on ebreak breakpoint
53
target/riscv/cpu.h | 11 +
70
target/riscv: prioritize pmp errors in raise_mmu_exception()
54
target/riscv/pmp.h | 1 +
71
riscv, gdbstub.c: fix reg_width in ricsv_gen_dynamic_vector_feature()
55
hw/block/m25p80.c | 74 ++++++
56
hw/misc/sifive_u_otp.c | 31 ++-
57
hw/riscv/boot.c | 18 +-
58
hw/riscv/sifive_u.c | 16 +-
59
hw/riscv/spike.c | 8 +-
60
hw/riscv/virt.c | 8 +-
61
target/riscv/cpu.c | 25 ++
62
target/riscv/csr.c | 342 ++++++++++++++++++-------
63
target/riscv/gdbstub.c | 308 ++++------------------
64
target/riscv/op_helper.c | 5 +
65
target/riscv/pmp.c | 4 +-
66
gdb-xml/riscv-32bit-csr.xml | 250 ------------------
67
gdb-xml/riscv-64bit-csr.xml | 250 ------------------
68
20 files changed, 463 insertions(+), 902 deletions(-)
69
delete mode 100644 gdb-xml/riscv-32bit-csr.xml
70
delete mode 100644 gdb-xml/riscv-64bit-csr.xml
71
72
73
Huang Tao (2):
74
target/riscv: Fix the element agnostic function problem
75
target/riscv: Implement dynamic establishment of custom decoder
76
77
Jason Chien (3):
78
target/riscv: Add support for Zve32x extension
79
target/riscv: Add support for Zve64x extension
80
target/riscv: Relax vector register check in RISCV gdbstub
81
82
Max Chou (4):
83
target/riscv: rvv: Fix Zvfhmin checking for vfwcvt.f.f.v and vfncvt.f.f.w instructions
84
target/riscv: rvv: Check single width operator for vector fp widen instructions
85
target/riscv: rvv: Check single width operator for vfncvt.rod.f.f.w
86
target/riscv: rvv: Remove redudant SEW checking for vector fp narrow/widen instructions
87
88
Rob Bradford (1):
89
target/riscv: Remove experimental prefix from "B" extension
90
91
Yangyu Chen (1):
92
target/riscv/cpu.c: fix Zvkb extension config
93
94
Yong-Xuan Wang (1):
95
target/riscv/kvm.c: Fix the hart bit setting of AIA
96
97
Yu-Ming Chang (1):
98
target/riscv: raise an exception when CSRRS/CSRRC writes a read-only CSR
99
100
yang.zhang (1):
101
hw/intc/riscv_aplic: APLICs should add child earlier than realize
102
103
MAINTAINERS | 1 +
104
target/riscv/cpu.h | 11 ++
105
target/riscv/cpu_bits.h | 2 +-
106
target/riscv/cpu_cfg.h | 2 +
107
target/riscv/helper.h | 1 +
108
target/riscv/sbi_ecall_interface.h | 17 +++
109
target/riscv/tcg/tcg-cpu.h | 15 +++
110
disas/riscv.c | 65 +++++++++-
111
hw/intc/riscv_aplic.c | 8 +-
112
hw/riscv/boot.c | 4 +-
113
target/riscv/cpu.c | 10 +-
114
target/riscv/cpu_helper.c | 37 +++---
115
target/riscv/csr.c | 71 +++++++++--
116
target/riscv/debug.c | 3 +
117
target/riscv/gdbstub.c | 8 +-
118
target/riscv/kvm/kvm-cpu.c | 157 ++++++++++++++++++++++++-
119
target/riscv/op_helper.c | 17 ++-
120
target/riscv/tcg/tcg-cpu.c | 50 +++++---
121
target/riscv/th_csr.c | 79 +++++++++++++
122
target/riscv/translate.c | 31 +++--
123
target/riscv/vector_internals.c | 22 ++++
124
target/riscv/insn_trans/trans_privileged.c.inc | 2 +
125
target/riscv/insn_trans/trans_rvv.c.inc | 46 +++++---
126
target/riscv/insn_trans/trans_rvzawrs.c.inc | 29 +++--
127
target/riscv/insn_trans/trans_rvzicbo.c.inc | 16 ++-
128
target/riscv/meson.build | 1 +
129
26 files changed, 596 insertions(+), 109 deletions(-)
130
create mode 100644 target/riscv/th_csr.c
131
diff view generated by jsdifflib
New patch
[PULL 01/28] hw/intc/riscv_aplic: APLICs should add child earlier than realize
1
From: "yang.zhang" <yang.zhang@hexintek.com>
1
2
3
Since only root APLICs can have hw IRQ lines, aplic->parent should
4
be initialized first.
5
6
Fixes: e8f79343cf ("hw/intc: Add RISC-V AIA APLIC device emulation")
7
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
8
Signed-off-by: yang.zhang <yang.zhang@hexintek.com>
9
Cc: qemu-stable <qemu-stable@nongnu.org>
10
Message-ID: <20240409014445.278-1-gaoshanliukou@163.com>
11
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
12
---
13
hw/intc/riscv_aplic.c | 8 ++++----
14
1 file changed, 4 insertions(+), 4 deletions(-)
15
16
diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/intc/riscv_aplic.c
19
+++ b/hw/intc/riscv_aplic.c
20
@@ -XXX,XX +XXX,XX @@ DeviceState *riscv_aplic_create(hwaddr addr, hwaddr size,
21
qdev_prop_set_bit(dev, "msimode", msimode);
22
qdev_prop_set_bit(dev, "mmode", mmode);
23
24
+ if (parent) {
25
+ riscv_aplic_add_child(parent, dev);
26
+ }
27
+
28
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
29
30
if (!is_kvm_aia(msimode)) {
31
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
32
}
33
34
- if (parent) {
35
- riscv_aplic_add_child(parent, dev);
36
- }
37
-
38
if (!msimode) {
39
for (i = 0; i < num_harts; i++) {
40
CPUState *cpu = cpu_by_arch_id(hartid_base + i);
41
--
42
2.45.1
diff view generated by jsdifflib
[PULL 08/12] target/riscv: Make csr_ops[CSR_TABLE_SIZE] external
[PULL 02/28] target/riscv/kvm: Fix exposure of Zkr
1
From: Bin Meng <bin.meng@windriver.com>
1
From: Andrew Jones <ajones@ventanamicro.com>
2
2
3
In preparation to generate the CSR register list for GDB stub
3
The Zkr extension may only be exposed to KVM guests if the VMM
4
dynamically, change csr_ops[] to non-static so that it can be
4
implements the SEED CSR. Use the same implementation as TCG.
5
referenced externally.
6
5
7
Signed-off-by: Bin Meng <bin.meng@windriver.com>
6
Without this patch, running with a KVM which does not forward the
8
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
7
SEED CSR access to QEMU will result in an ILL exception being
9
Message-id: 1610427124-49887-2-git-send-email-bmeng.cn@gmail.com
8
injected into the guest (this results in Linux guests crashing on
9
boot). And, when running with a KVM which does forward the access,
10
QEMU will crash, since QEMU doesn't know what to do with the exit.
11
12
Fixes: 3108e2f1c69d ("target/riscv/kvm: update KVM exts to Linux 6.8")
13
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
14
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
15
Cc: qemu-stable <qemu-stable@nongnu.org>
16
Message-ID: <20240422134605.534207-2-ajones@ventanamicro.com>
10
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
17
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
11
---
18
---
12
target/riscv/cpu.h | 8 ++++++++
19
target/riscv/cpu.h | 3 +++
13
target/riscv/csr.c | 10 +---------
20
target/riscv/csr.c | 18 ++++++++++++++----
14
2 files changed, 9 insertions(+), 9 deletions(-)
21
target/riscv/kvm/kvm-cpu.c | 25 +++++++++++++++++++++++++
22
3 files changed, 42 insertions(+), 4 deletions(-)
15
23
16
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
24
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
17
index XXXXXXX..XXXXXXX 100644
25
index XXXXXXX..XXXXXXX 100644
18
--- a/target/riscv/cpu.h
26
--- a/target/riscv/cpu.h
19
+++ b/target/riscv/cpu.h
27
+++ b/target/riscv/cpu.h
20
@@ -XXX,XX +XXX,XX @@ typedef struct {
28
@@ -XXX,XX +XXX,XX @@ void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops);
21
riscv_csr_op_fn op;
29
22
} riscv_csr_operations;
30
void riscv_cpu_register_gdb_regs_for_features(CPUState *cs);
23
31
24
+/* CSR function table constants */
32
+target_ulong riscv_new_csr_seed(target_ulong new_value,
25
+enum {
33
+ target_ulong write_mask);
26
+ CSR_TABLE_SIZE = 0x1000
27
+};
28
+
34
+
29
+/* CSR function table */
35
uint8_t satp_mode_max_from_map(uint32_t map);
30
+extern riscv_csr_operations csr_ops[];
36
const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit);
31
+
32
void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops);
33
void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops);
34
37
35
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
38
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
36
index XXXXXXX..XXXXXXX 100644
39
index XXXXXXX..XXXXXXX 100644
37
--- a/target/riscv/csr.c
40
--- a/target/riscv/csr.c
38
+++ b/target/riscv/csr.c
41
+++ b/target/riscv/csr.c
39
@@ -XXX,XX +XXX,XX @@
42
@@ -XXX,XX +XXX,XX @@ static RISCVException write_upmbase(CPURISCVState *env, int csrno,
40
#include "qemu/main-loop.h"
43
#endif
41
#include "exec/exec-all.h"
44
42
45
/* Crypto Extension */
43
-/* CSR function table */
46
-static RISCVException rmw_seed(CPURISCVState *env, int csrno,
44
-static riscv_csr_operations csr_ops[];
47
- target_ulong *ret_value,
45
-
48
- target_ulong new_value,
46
-/* CSR function table constants */
49
- target_ulong write_mask)
47
-enum {
50
+target_ulong riscv_new_csr_seed(target_ulong new_value,
48
- CSR_TABLE_SIZE = 0x1000
51
+ target_ulong write_mask)
49
-};
50
-
51
/* CSR function table public API */
52
void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops)
53
{
52
{
54
@@ -XXX,XX +XXX,XX @@ int riscv_csrrw_debug(CPURISCVState *env, int csrno, target_ulong *ret_value,
53
uint16_t random_v;
54
Error *random_e = NULL;
55
@@ -XXX,XX +XXX,XX @@ static RISCVException rmw_seed(CPURISCVState *env, int csrno,
56
rval = random_v | SEED_OPST_ES16;
57
}
58
59
+ return rval;
60
+}
61
+
62
+static RISCVException rmw_seed(CPURISCVState *env, int csrno,
63
+ target_ulong *ret_value,
64
+ target_ulong new_value,
65
+ target_ulong write_mask)
66
+{
67
+ target_ulong rval;
68
+
69
+ rval = riscv_new_csr_seed(new_value, write_mask);
70
+
71
if (ret_value) {
72
*ret_value = rval;
73
}
74
diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
75
index XXXXXXX..XXXXXXX 100644
76
--- a/target/riscv/kvm/kvm-cpu.c
77
+++ b/target/riscv/kvm/kvm-cpu.c
78
@@ -XXX,XX +XXX,XX @@ static int kvm_riscv_handle_sbi(CPUState *cs, struct kvm_run *run)
79
return ret;
55
}
80
}
56
81
57
/* Control and Status Register function table */
82
+static int kvm_riscv_handle_csr(CPUState *cs, struct kvm_run *run)
58
-static riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
83
+{
59
+riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
84
+ target_ulong csr_num = run->riscv_csr.csr_num;
60
/* User Floating-Point CSRs */
85
+ target_ulong new_value = run->riscv_csr.new_value;
61
[CSR_FFLAGS] = { fs, read_fflags, write_fflags },
86
+ target_ulong write_mask = run->riscv_csr.write_mask;
62
[CSR_FRM] = { fs, read_frm, write_frm },
87
+ int ret = 0;
88
+
89
+ switch (csr_num) {
90
+ case CSR_SEED:
91
+ run->riscv_csr.ret_value = riscv_new_csr_seed(new_value, write_mask);
92
+ break;
93
+ default:
94
+ qemu_log_mask(LOG_UNIMP,
95
+ "%s: un-handled CSR EXIT for CSR %lx\n",
96
+ __func__, csr_num);
97
+ ret = -1;
98
+ break;
99
+ }
100
+
101
+ return ret;
102
+}
103
+
104
int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
105
{
106
int ret = 0;
107
@@ -XXX,XX +XXX,XX @@ int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
108
case KVM_EXIT_RISCV_SBI:
109
ret = kvm_riscv_handle_sbi(cs, run);
110
break;
111
+ case KVM_EXIT_RISCV_CSR:
112
+ ret = kvm_riscv_handle_csr(cs, run);
113
+ break;
114
default:
115
qemu_log_mask(LOG_UNIMP, "%s: un-handled exit reason %d\n",
116
__func__, run->exit_reason);
63
--
117
--
64
2.29.2
118
2.45.1
65
66
diff view generated by jsdifflib
[PULL 05/12] target/riscv/pmp: Raise exception if no PMP entry is configured
[PULL 03/28] target/riscv: Raise exceptions on wrs.nto
1
From: Atish Patra <atish.patra@wdc.com>
1
From: Andrew Jones <ajones@ventanamicro.com>
2
2
3
As per the privilege specification, any access from S/U mode should fail
3
Implementing wrs.nto to always just return is consistent with the
4
if no pmp region is configured.
4
specification, as the instruction is permitted to terminate the
5
stall for any reason, but it's not useful for virtualization, where
6
we'd like the guest to trap to the hypervisor in order to allow
7
scheduling of the lock holding VCPU. Change to always immediately
8
raise exceptions when the appropriate conditions are present,
9
otherwise continue to just return. Note, immediately raising
10
exceptions is also consistent with the specification since the
11
time limit that should expire prior to the exception is
12
implementation-specific.
5
13
6
Signed-off-by: Atish Patra <atish.patra@wdc.com>
14
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
15
Reviewed-by: Christoph Müllner <christoph.muellner@vrull.eu>
16
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
7
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
17
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
8
Message-id: 20201223192553.332508-1-atish.patra@wdc.com
18
Message-ID: <20240424142808.62936-2-ajones@ventanamicro.com>
9
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
19
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
10
---
20
---
11
target/riscv/pmp.h | 1 +
21
target/riscv/helper.h | 1 +
12
target/riscv/op_helper.c | 5 +++++
22
target/riscv/op_helper.c | 11 ++++++++
13
target/riscv/pmp.c | 4 ++--
23
target/riscv/insn_trans/trans_rvzawrs.c.inc | 29 ++++++++++++++-------
14
3 files changed, 8 insertions(+), 2 deletions(-)
24
3 files changed, 32 insertions(+), 9 deletions(-)
15
25
16
diff --git a/target/riscv/pmp.h b/target/riscv/pmp.h
26
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
17
index XXXXXXX..XXXXXXX 100644
27
index XXXXXXX..XXXXXXX 100644
18
--- a/target/riscv/pmp.h
28
--- a/target/riscv/helper.h
19
+++ b/target/riscv/pmp.h
29
+++ b/target/riscv/helper.h
20
@@ -XXX,XX +XXX,XX @@ bool pmp_is_range_in_tlb(CPURISCVState *env, hwaddr tlb_sa,
30
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_6(csrrw_i128, tl, env, int, tl, tl, tl, tl)
21
target_ulong *tlb_size);
31
DEF_HELPER_1(sret, tl, env)
22
void pmp_update_rule_addr(CPURISCVState *env, uint32_t pmp_index);
32
DEF_HELPER_1(mret, tl, env)
23
void pmp_update_rule_nums(CPURISCVState *env);
33
DEF_HELPER_1(wfi, void, env)
24
+uint32_t pmp_get_num_rules(CPURISCVState *env);
34
+DEF_HELPER_1(wrs_nto, void, env)
25
35
DEF_HELPER_1(tlb_flush, void, env)
26
#endif
36
DEF_HELPER_1(tlb_flush_all, void, env)
37
/* Native Debug */
27
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
38
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
28
index XXXXXXX..XXXXXXX 100644
39
index XXXXXXX..XXXXXXX 100644
29
--- a/target/riscv/op_helper.c
40
--- a/target/riscv/op_helper.c
30
+++ b/target/riscv/op_helper.c
41
+++ b/target/riscv/op_helper.c
31
@@ -XXX,XX +XXX,XX @@ target_ulong helper_mret(CPURISCVState *env, target_ulong cpu_pc_deb)
42
@@ -XXX,XX +XXX,XX @@ void helper_wfi(CPURISCVState *env)
32
43
}
33
uint64_t mstatus = env->mstatus;
44
}
34
target_ulong prev_priv = get_field(mstatus, MSTATUS_MPP);
45
35
+
46
+void helper_wrs_nto(CPURISCVState *env)
36
+ if (!pmp_get_num_rules(env) && (prev_priv != PRV_M)) {
47
+{
48
+ if (env->virt_enabled && (env->priv == PRV_S || env->priv == PRV_U) &&
49
+ get_field(env->hstatus, HSTATUS_VTW) &&
50
+ !get_field(env->mstatus, MSTATUS_TW)) {
51
+ riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETPC());
52
+ } else if (env->priv != PRV_M && get_field(env->mstatus, MSTATUS_TW)) {
37
+ riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
53
+ riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
38
+ }
54
+ }
55
+}
39
+
56
+
40
target_ulong prev_virt = get_field(env->mstatus, MSTATUS_MPV);
57
void helper_tlb_flush(CPURISCVState *env)
41
mstatus = set_field(mstatus, MSTATUS_MIE,
58
{
42
get_field(mstatus, MSTATUS_MPIE));
59
CPUState *cs = env_cpu(env);
43
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
60
diff --git a/target/riscv/insn_trans/trans_rvzawrs.c.inc b/target/riscv/insn_trans/trans_rvzawrs.c.inc
44
index XXXXXXX..XXXXXXX 100644
61
index XXXXXXX..XXXXXXX 100644
45
--- a/target/riscv/pmp.c
62
--- a/target/riscv/insn_trans/trans_rvzawrs.c.inc
46
+++ b/target/riscv/pmp.c
63
+++ b/target/riscv/insn_trans/trans_rvzawrs.c.inc
47
@@ -XXX,XX +XXX,XX @@ static inline int pmp_is_locked(CPURISCVState *env, uint32_t pmp_index)
64
@@ -XXX,XX +XXX,XX @@
48
/*
65
* this program. If not, see <http://www.gnu.org/licenses/>.
49
* Count the number of active rules.
50
*/
66
*/
51
-static inline uint32_t pmp_get_num_rules(CPURISCVState *env)
67
52
+uint32_t pmp_get_num_rules(CPURISCVState *env)
68
-static bool trans_wrs(DisasContext *ctx)
69
+static bool trans_wrs_sto(DisasContext *ctx, arg_wrs_sto *a)
53
{
70
{
54
return env->pmp_state.num_rules;
71
if (!ctx->cfg_ptr->ext_zawrs) {
72
return false;
73
@@ -XXX,XX +XXX,XX @@ static bool trans_wrs(DisasContext *ctx)
74
return true;
55
}
75
}
56
@@ -XXX,XX +XXX,XX @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
76
57
77
-#define GEN_TRANS_WRS(insn) \
58
/* Short cut if no rules */
78
-static bool trans_ ## insn(DisasContext *ctx, arg_ ## insn *a) \
59
if (0 == pmp_get_num_rules(env)) {
79
-{ \
60
- return true;
80
- (void)a; \
61
+ return (env->priv == PRV_M) ? true : false;
81
- return trans_wrs(ctx); \
62
}
82
-}
63
83
+static bool trans_wrs_nto(DisasContext *ctx, arg_wrs_nto *a)
64
if (size == 0) {
84
+{
85
+ if (!ctx->cfg_ptr->ext_zawrs) {
86
+ return false;
87
+ }
88
89
-GEN_TRANS_WRS(wrs_nto)
90
-GEN_TRANS_WRS(wrs_sto)
91
+ /*
92
+ * Depending on the mode of execution, mstatus.TW and hstatus.VTW, wrs.nto
93
+ * should raise an exception when the implementation-specific bounded time
94
+ * limit has expired. Our time limit is zero, so we either return
95
+ * immediately, as does our implementation of wrs.sto, or raise an
96
+ * exception, as handled by the wrs.nto helper.
97
+ */
98
+#ifndef CONFIG_USER_ONLY
99
+ gen_helper_wrs_nto(tcg_env);
100
+#endif
101
+
102
+ /* We only get here when helper_wrs_nto() doesn't raise an exception. */
103
+ return trans_wrs_sto(ctx, NULL);
104
+}
65
--
105
--
66
2.29.2
106
2.45.1
67
107
68
108
diff view generated by jsdifflib
New patch
[PULL 04/28] target/riscv/kvm: implement SBI debug console (DBCN) calls
1
1
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
2
3
SBI defines a Debug Console extension "DBCN" that will, in time, replace
4
the legacy console putchar and getchar SBI extensions.
5
6
The appeal of the DBCN extension is that it allows multiple bytes to be
7
read/written in the SBI console in a single SBI call.
8
9
As far as KVM goes, the DBCN calls are forwarded by an in-kernel KVM
10
module to userspace. But this will only happens if the KVM module
11
actually supports this SBI extension and we activate it.
12
13
We'll check for DBCN support during init time, checking if get-reg-list
14
is advertising KVM_RISCV_SBI_EXT_DBCN. In that case, we'll enable it via
15
kvm_set_one_reg() during kvm_arch_init_vcpu().
16
17
Finally, change kvm_riscv_handle_sbi() to handle the incoming calls for
18
SBI_EXT_DBCN, reading and writing as required.
19
20
A simple KVM guest with 'earlycon=sbi', running in an emulated RISC-V
21
host, takes around 20 seconds to boot without using DBCN. With this
22
patch we're taking around 14 seconds to boot due to the speed-up in the
23
terminal output. There's no change in boot time if the guest isn't
24
using earlycon.
25
26
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
27
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
28
Message-ID: <20240425155012.581366-1-dbarboza@ventanamicro.com>
29
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
30
---
31
target/riscv/sbi_ecall_interface.h | 17 +++++
32
target/riscv/kvm/kvm-cpu.c | 111 +++++++++++++++++++++++++++++
33
2 files changed, 128 insertions(+)
34
35
diff --git a/target/riscv/sbi_ecall_interface.h b/target/riscv/sbi_ecall_interface.h
36
index XXXXXXX..XXXXXXX 100644
37
--- a/target/riscv/sbi_ecall_interface.h
38
+++ b/target/riscv/sbi_ecall_interface.h
39
@@ -XXX,XX +XXX,XX @@
40
41
/* clang-format off */
42
43
+#define SBI_SUCCESS 0
44
+#define SBI_ERR_FAILED -1
45
+#define SBI_ERR_NOT_SUPPORTED -2
46
+#define SBI_ERR_INVALID_PARAM -3
47
+#define SBI_ERR_DENIED -4
48
+#define SBI_ERR_INVALID_ADDRESS -5
49
+#define SBI_ERR_ALREADY_AVAILABLE -6
50
+#define SBI_ERR_ALREADY_STARTED -7
51
+#define SBI_ERR_ALREADY_STOPPED -8
52
+#define SBI_ERR_NO_SHMEM -9
53
+
54
/* SBI Extension IDs */
55
#define SBI_EXT_0_1_SET_TIMER 0x0
56
#define SBI_EXT_0_1_CONSOLE_PUTCHAR 0x1
57
@@ -XXX,XX +XXX,XX @@
58
#define SBI_EXT_IPI 0x735049
59
#define SBI_EXT_RFENCE 0x52464E43
60
#define SBI_EXT_HSM 0x48534D
61
+#define SBI_EXT_DBCN 0x4442434E
62
63
/* SBI function IDs for BASE extension */
64
#define SBI_EXT_BASE_GET_SPEC_VERSION 0x0
65
@@ -XXX,XX +XXX,XX @@
66
#define SBI_EXT_HSM_HART_STOP 0x1
67
#define SBI_EXT_HSM_HART_GET_STATUS 0x2
68
69
+/* SBI function IDs for DBCN extension */
70
+#define SBI_EXT_DBCN_CONSOLE_WRITE 0x0
71
+#define SBI_EXT_DBCN_CONSOLE_READ 0x1
72
+#define SBI_EXT_DBCN_CONSOLE_WRITE_BYTE 0x2
73
+
74
#define SBI_HSM_HART_STATUS_STARTED 0x0
75
#define SBI_HSM_HART_STATUS_STOPPED 0x1
76
#define SBI_HSM_HART_STATUS_START_PENDING 0x2
77
diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
78
index XXXXXXX..XXXXXXX 100644
79
--- a/target/riscv/kvm/kvm-cpu.c
80
+++ b/target/riscv/kvm/kvm-cpu.c
81
@@ -XXX,XX +XXX,XX @@ static KVMCPUConfig kvm_v_vlenb = {
82
KVM_REG_RISCV_VECTOR_CSR_REG(vlenb)
83
};
84
85
+static KVMCPUConfig kvm_sbi_dbcn = {
86
+ .name = "sbi_dbcn",
87
+ .kvm_reg_id = KVM_REG_RISCV | KVM_REG_SIZE_U64 |
88
+ KVM_REG_RISCV_SBI_EXT | KVM_RISCV_SBI_EXT_DBCN
89
+};
90
+
91
static void kvm_riscv_update_cpu_cfg_isa_ext(RISCVCPU *cpu, CPUState *cs)
92
{
93
CPURISCVState *env = &cpu->env;
94
@@ -XXX,XX +XXX,XX @@ static int uint64_cmp(const void *a, const void *b)
95
return 0;
96
}
97
98
+static void kvm_riscv_check_sbi_dbcn_support(RISCVCPU *cpu,
99
+ KVMScratchCPU *kvmcpu,
100
+ struct kvm_reg_list *reglist)
101
+{
102
+ struct kvm_reg_list *reg_search;
103
+
104
+ reg_search = bsearch(&kvm_sbi_dbcn.kvm_reg_id, reglist->reg, reglist->n,
105
+ sizeof(uint64_t), uint64_cmp);
106
+
107
+ if (reg_search) {
108
+ kvm_sbi_dbcn.supported = true;
109
+ }
110
+}
111
+
112
static void kvm_riscv_read_vlenb(RISCVCPU *cpu, KVMScratchCPU *kvmcpu,
113
struct kvm_reg_list *reglist)
114
{
115
@@ -XXX,XX +XXX,XX @@ static void kvm_riscv_init_multiext_cfg(RISCVCPU *cpu, KVMScratchCPU *kvmcpu)
116
if (riscv_has_ext(&cpu->env, RVV)) {
117
kvm_riscv_read_vlenb(cpu, kvmcpu, reglist);
118
}
119
+
120
+ kvm_riscv_check_sbi_dbcn_support(cpu, kvmcpu, reglist);
121
}
122
123
static void riscv_init_kvm_registers(Object *cpu_obj)
124
@@ -XXX,XX +XXX,XX @@ static int kvm_vcpu_set_machine_ids(RISCVCPU *cpu, CPUState *cs)
125
return ret;
126
}
127
128
+static int kvm_vcpu_enable_sbi_dbcn(RISCVCPU *cpu, CPUState *cs)
129
+{
130
+ target_ulong reg = 1;
131
+
132
+ if (!kvm_sbi_dbcn.supported) {
133
+ return 0;
134
+ }
135
+
136
+ return kvm_set_one_reg(cs, kvm_sbi_dbcn.kvm_reg_id, &reg);
137
+}
138
+
139
int kvm_arch_init_vcpu(CPUState *cs)
140
{
141
int ret = 0;
142
@@ -XXX,XX +XXX,XX @@ int kvm_arch_init_vcpu(CPUState *cs)
143
kvm_riscv_update_cpu_misa_ext(cpu, cs);
144
kvm_riscv_update_cpu_cfg_isa_ext(cpu, cs);
145
146
+ ret = kvm_vcpu_enable_sbi_dbcn(cpu, cs);
147
+
148
return ret;
149
}
150
151
@@ -XXX,XX +XXX,XX @@ bool kvm_arch_stop_on_emulation_error(CPUState *cs)
152
return true;
153
}
154
155
+static void kvm_riscv_handle_sbi_dbcn(CPUState *cs, struct kvm_run *run)
156
+{
157
+ g_autofree uint8_t *buf = NULL;
158
+ RISCVCPU *cpu = RISCV_CPU(cs);
159
+ target_ulong num_bytes;
160
+ uint64_t addr;
161
+ unsigned char ch;
162
+ int ret;
163
+
164
+ switch (run->riscv_sbi.function_id) {
165
+ case SBI_EXT_DBCN_CONSOLE_READ:
166
+ case SBI_EXT_DBCN_CONSOLE_WRITE:
167
+ num_bytes = run->riscv_sbi.args[0];
168
+
169
+ if (num_bytes == 0) {
170
+ run->riscv_sbi.ret[0] = SBI_SUCCESS;
171
+ run->riscv_sbi.ret[1] = 0;
172
+ break;
173
+ }
174
+
175
+ addr = run->riscv_sbi.args[1];
176
+
177
+ /*
178
+ * Handle the case where a 32 bit CPU is running in a
179
+ * 64 bit addressing env.
180
+ */
181
+ if (riscv_cpu_mxl(&cpu->env) == MXL_RV32) {
182
+ addr |= (uint64_t)run->riscv_sbi.args[2] << 32;
183
+ }
184
+
185
+ buf = g_malloc0(num_bytes);
186
+
187
+ if (run->riscv_sbi.function_id == SBI_EXT_DBCN_CONSOLE_READ) {
188
+ ret = qemu_chr_fe_read_all(serial_hd(0)->be, buf, num_bytes);
189
+ if (ret < 0) {
190
+ error_report("SBI_EXT_DBCN_CONSOLE_READ: error when "
191
+ "reading chardev");
192
+ exit(1);
193
+ }
194
+
195
+ cpu_physical_memory_write(addr, buf, ret);
196
+ } else {
197
+ cpu_physical_memory_read(addr, buf, num_bytes);
198
+
199
+ ret = qemu_chr_fe_write_all(serial_hd(0)->be, buf, num_bytes);
200
+ if (ret < 0) {
201
+ error_report("SBI_EXT_DBCN_CONSOLE_WRITE: error when "
202
+ "writing chardev");
203
+ exit(1);
204
+ }
205
+ }
206
+
207
+ run->riscv_sbi.ret[0] = SBI_SUCCESS;
208
+ run->riscv_sbi.ret[1] = ret;
209
+ break;
210
+ case SBI_EXT_DBCN_CONSOLE_WRITE_BYTE:
211
+ ch = run->riscv_sbi.args[0];
212
+ ret = qemu_chr_fe_write(serial_hd(0)->be, &ch, sizeof(ch));
213
+
214
+ if (ret < 0) {
215
+ error_report("SBI_EXT_DBCN_CONSOLE_WRITE_BYTE: error when "
216
+ "writing chardev");
217
+ exit(1);
218
+ }
219
+
220
+ run->riscv_sbi.ret[0] = SBI_SUCCESS;
221
+ run->riscv_sbi.ret[1] = 0;
222
+ break;
223
+ default:
224
+ run->riscv_sbi.ret[0] = SBI_ERR_NOT_SUPPORTED;
225
+ }
226
+}
227
+
228
static int kvm_riscv_handle_sbi(CPUState *cs, struct kvm_run *run)
229
{
230
int ret = 0;
231
@@ -XXX,XX +XXX,XX @@ static int kvm_riscv_handle_sbi(CPUState *cs, struct kvm_run *run)
232
}
233
ret = 0;
234
break;
235
+ case SBI_EXT_DBCN:
236
+ kvm_riscv_handle_sbi_dbcn(cs, run);
237
+ break;
238
default:
239
qemu_log_mask(LOG_UNIMP,
240
"%s: un-handled SBI EXIT, specific reasons is %lu\n",
241
--
242
2.45.1
diff view generated by jsdifflib
[PULL 04/12] RISC-V: Place DTB at 3GB boundary instead of 4GB
[PULL 05/28] hw/riscv/boot.c: Support 64-bit address for initrd
1
From: Atish Patra <atish.patra@wdc.com>
1
From: Cheng Yang <yangcheng.work@foxmail.com>
2
2
3
Currently, we place the DTB at 2MB from 4GB or end of DRAM which ever is
3
Use qemu_fdt_setprop_u64() instead of qemu_fdt_setprop_cell()
4
lesser. However, Linux kernel can address only 1GB of memory for RV32.
4
to set the address of initrd in FDT to support 64-bit address.
5
Thus, it can not map anything beyond 3GB (assuming 2GB is the starting address).
6
As a result, it can not process DT and panic if opensbi dynamic firmware
7
is used. While at it, place the DTB further away to avoid in memory placement
8
issues in future.
9
5
10
Fix this by placing the DTB at 16MB from 3GB or end of DRAM whichever is lower.
6
Signed-off-by: Cheng Yang <yangcheng.work@foxmail.com>
11
7
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
12
Fixes: 66b1205bc5ab ("RISC-V: Copy the fdt in dram instead of ROM")
8
Message-ID: <tencent_A4482251DD0890F312758FA6B33F60815609@qq.com>
13
14
Reviewed-by: Bin Meng <bin.meng@windriver.com>
15
Tested-by: Bin Meng <bin.meng@windriver.com>
16
Signed-off-by: Atish Patra <atish.patra@wdc.com>
17
Message-id: 20210107091127.3407870-1-atish.patra@wdc.com
18
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
9
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
19
---
10
---
20
hw/riscv/boot.c | 8 ++++----
11
hw/riscv/boot.c | 4 ++--
21
1 file changed, 4 insertions(+), 4 deletions(-)
12
1 file changed, 2 insertions(+), 2 deletions(-)
22
13
23
diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
14
diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
24
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
25
--- a/hw/riscv/boot.c
16
--- a/hw/riscv/boot.c
26
+++ b/hw/riscv/boot.c
17
+++ b/hw/riscv/boot.c
27
@@ -XXX,XX +XXX,XX @@ uint32_t riscv_load_fdt(hwaddr dram_base, uint64_t mem_size, void *fdt)
18
@@ -XXX,XX +XXX,XX @@ static void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry)
28
/*
19
/* Some RISC-V machines (e.g. opentitan) don't have a fdt. */
29
* We should put fdt as far as possible to avoid kernel/initrd overwriting
20
if (fdt) {
30
* its content. But it should be addressable by 32 bit system as well.
21
end = start + size;
31
- * Thus, put it at an aligned address that less than fdt size from end of
22
- qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", start);
32
- * dram or 4GB whichever is lesser.
23
- qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", end);
33
+ * Thus, put it at an 16MB aligned address that less than fdt size from the
24
+ qemu_fdt_setprop_u64(fdt, "/chosen", "linux,initrd-start", start);
34
+ * end of dram or 3GB whichever is lesser.
25
+ qemu_fdt_setprop_u64(fdt, "/chosen", "linux,initrd-end", end);
35
*/
26
}
36
- temp = MIN(dram_end, 4096 * MiB);
27
}
37
- fdt_addr = QEMU_ALIGN_DOWN(temp - fdtsize, 2 * MiB);
28
38
+ temp = MIN(dram_end, 3072 * MiB);
39
+ fdt_addr = QEMU_ALIGN_DOWN(temp - fdtsize, 16 * MiB);
40
41
fdt_pack(fdt);
42
/* copy in the device tree */
43
--
29
--
44
2.29.2
30
2.45.1
45
46
diff view generated by jsdifflib
[PULL 11/12] target/riscv: Remove built-in GDB XML files for CSRs
[PULL 06/28] target/riscv: change RISCV_EXCP_SEMIHOST exception number to 63
1
From: Bin Meng <bin.meng@windriver.com>
1
From: Clément Léger <cleger@rivosinc.com>
2
2
3
Now that we have switched to generate the RISC-V CSR XML dynamically,
3
The current semihost exception number (16) is a reserved number (range
4
remove the built-in hardcoded XML files.
4
[16-17]). The upcoming double trap specification uses that number for
5
the double trap exception. Since the privileged spec (Table 22) defines
6
ranges for custom uses change the semihosting exception number to 63
7
which belongs to the range [48-63] in order to avoid any future
8
collisions with reserved exception.
5
9
6
Signed-off-by: Bin Meng <bin.meng@windriver.com>
10
Signed-off-by: Clément Léger <cleger@rivosinc.com>
11
7
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
12
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
8
Message-id: 20210116054123.5457-3-bmeng.cn@gmail.com
13
Message-ID: <20240422135840.1959967-1-cleger@rivosinc.com>
9
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
14
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
10
---
15
---
11
.../targets/riscv32-linux-user.mak | 2 +-
16
target/riscv/cpu_bits.h | 2 +-
12
default-configs/targets/riscv32-softmmu.mak | 2 +-
17
1 file changed, 1 insertion(+), 1 deletion(-)
13
.../targets/riscv64-linux-user.mak | 2 +-
14
default-configs/targets/riscv64-softmmu.mak | 2 +-
15
gdb-xml/riscv-32bit-csr.xml | 250 ------------------
16
gdb-xml/riscv-64bit-csr.xml | 250 ------------------
17
6 files changed, 4 insertions(+), 504 deletions(-)
18
delete mode 100644 gdb-xml/riscv-32bit-csr.xml
19
delete mode 100644 gdb-xml/riscv-64bit-csr.xml
20
18
21
diff --git a/default-configs/targets/riscv32-linux-user.mak b/default-configs/targets/riscv32-linux-user.mak
19
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
22
index XXXXXXX..XXXXXXX 100644
20
index XXXXXXX..XXXXXXX 100644
23
--- a/default-configs/targets/riscv32-linux-user.mak
21
--- a/target/riscv/cpu_bits.h
24
+++ b/default-configs/targets/riscv32-linux-user.mak
22
+++ b/target/riscv/cpu_bits.h
25
@@ -XXX,XX +XXX,XX @@
23
@@ -XXX,XX +XXX,XX @@ typedef enum RISCVException {
26
TARGET_ARCH=riscv32
24
RISCV_EXCP_INST_PAGE_FAULT = 0xc, /* since: priv-1.10.0 */
27
TARGET_BASE_ARCH=riscv
25
RISCV_EXCP_LOAD_PAGE_FAULT = 0xd, /* since: priv-1.10.0 */
28
TARGET_ABI_DIR=riscv
26
RISCV_EXCP_STORE_PAGE_FAULT = 0xf, /* since: priv-1.10.0 */
29
-TARGET_XML_FILES= gdb-xml/riscv-32bit-cpu.xml gdb-xml/riscv-32bit-fpu.xml gdb-xml/riscv-64bit-fpu.xml gdb-xml/riscv-32bit-csr.xml gdb-xml/riscv-32bit-virtual.xml
27
- RISCV_EXCP_SEMIHOST = 0x10,
30
+TARGET_XML_FILES= gdb-xml/riscv-32bit-cpu.xml gdb-xml/riscv-32bit-fpu.xml gdb-xml/riscv-64bit-fpu.xml gdb-xml/riscv-32bit-virtual.xml
28
RISCV_EXCP_INST_GUEST_PAGE_FAULT = 0x14,
31
diff --git a/default-configs/targets/riscv32-softmmu.mak b/default-configs/targets/riscv32-softmmu.mak
29
RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT = 0x15,
32
index XXXXXXX..XXXXXXX 100644
30
RISCV_EXCP_VIRT_INSTRUCTION_FAULT = 0x16,
33
--- a/default-configs/targets/riscv32-softmmu.mak
31
RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT = 0x17,
34
+++ b/default-configs/targets/riscv32-softmmu.mak
32
+ RISCV_EXCP_SEMIHOST = 0x3f,
35
@@ -XXX,XX +XXX,XX @@
33
} RISCVException;
36
TARGET_ARCH=riscv32
34
37
TARGET_BASE_ARCH=riscv
35
#define RISCV_EXCP_INT_FLAG 0x80000000
38
TARGET_SUPPORTS_MTTCG=y
39
-TARGET_XML_FILES= gdb-xml/riscv-32bit-cpu.xml gdb-xml/riscv-32bit-fpu.xml gdb-xml/riscv-64bit-fpu.xml gdb-xml/riscv-32bit-csr.xml gdb-xml/riscv-32bit-virtual.xml
40
+TARGET_XML_FILES= gdb-xml/riscv-32bit-cpu.xml gdb-xml/riscv-32bit-fpu.xml gdb-xml/riscv-64bit-fpu.xml gdb-xml/riscv-32bit-virtual.xml
41
TARGET_NEED_FDT=y
42
diff --git a/default-configs/targets/riscv64-linux-user.mak b/default-configs/targets/riscv64-linux-user.mak
43
index XXXXXXX..XXXXXXX 100644
44
--- a/default-configs/targets/riscv64-linux-user.mak
45
+++ b/default-configs/targets/riscv64-linux-user.mak
46
@@ -XXX,XX +XXX,XX @@
47
TARGET_ARCH=riscv64
48
TARGET_BASE_ARCH=riscv
49
TARGET_ABI_DIR=riscv
50
-TARGET_XML_FILES= gdb-xml/riscv-64bit-cpu.xml gdb-xml/riscv-32bit-fpu.xml gdb-xml/riscv-64bit-fpu.xml gdb-xml/riscv-64bit-csr.xml gdb-xml/riscv-64bit-virtual.xml
51
+TARGET_XML_FILES= gdb-xml/riscv-64bit-cpu.xml gdb-xml/riscv-32bit-fpu.xml gdb-xml/riscv-64bit-fpu.xml gdb-xml/riscv-64bit-virtual.xml
52
diff --git a/default-configs/targets/riscv64-softmmu.mak b/default-configs/targets/riscv64-softmmu.mak
53
index XXXXXXX..XXXXXXX 100644
54
--- a/default-configs/targets/riscv64-softmmu.mak
55
+++ b/default-configs/targets/riscv64-softmmu.mak
56
@@ -XXX,XX +XXX,XX @@
57
TARGET_ARCH=riscv64
58
TARGET_BASE_ARCH=riscv
59
TARGET_SUPPORTS_MTTCG=y
60
-TARGET_XML_FILES= gdb-xml/riscv-64bit-cpu.xml gdb-xml/riscv-32bit-fpu.xml gdb-xml/riscv-64bit-fpu.xml gdb-xml/riscv-64bit-csr.xml gdb-xml/riscv-64bit-virtual.xml
61
+TARGET_XML_FILES= gdb-xml/riscv-64bit-cpu.xml gdb-xml/riscv-32bit-fpu.xml gdb-xml/riscv-64bit-fpu.xml gdb-xml/riscv-64bit-virtual.xml
62
TARGET_NEED_FDT=y
63
diff --git a/gdb-xml/riscv-32bit-csr.xml b/gdb-xml/riscv-32bit-csr.xml
64
deleted file mode 100644
65
index XXXXXXX..XXXXXXX
66
--- a/gdb-xml/riscv-32bit-csr.xml
67
+++ /dev/null
68
@@ -XXX,XX +XXX,XX @@
69
-<?xml version="1.0"?>
70
-<!-- Copyright (C) 2018-2019 Free Software Foundation, Inc.
71
-
72
- Copying and distribution of this file, with or without modification,
73
- are permitted in any medium without royalty provided the copyright
74
- notice and this notice are preserved. -->
75
-
76
-<!DOCTYPE feature SYSTEM "gdb-target.dtd">
77
-<feature name="org.gnu.gdb.riscv.csr">
78
- <reg name="ustatus" bitsize="32"/>
79
- <reg name="uie" bitsize="32"/>
80
- <reg name="utvec" bitsize="32"/>
81
- <reg name="uscratch" bitsize="32"/>
82
- <reg name="uepc" bitsize="32"/>
83
- <reg name="ucause" bitsize="32"/>
84
- <reg name="utval" bitsize="32"/>
85
- <reg name="uip" bitsize="32"/>
86
- <reg name="fflags" bitsize="32"/>
87
- <reg name="frm" bitsize="32"/>
88
- <reg name="fcsr" bitsize="32"/>
89
- <reg name="cycle" bitsize="32"/>
90
- <reg name="time" bitsize="32"/>
91
- <reg name="instret" bitsize="32"/>
92
- <reg name="hpmcounter3" bitsize="32"/>
93
- <reg name="hpmcounter4" bitsize="32"/>
94
- <reg name="hpmcounter5" bitsize="32"/>
95
- <reg name="hpmcounter6" bitsize="32"/>
96
- <reg name="hpmcounter7" bitsize="32"/>
97
- <reg name="hpmcounter8" bitsize="32"/>
98
- <reg name="hpmcounter9" bitsize="32"/>
99
- <reg name="hpmcounter10" bitsize="32"/>
100
- <reg name="hpmcounter11" bitsize="32"/>
101
- <reg name="hpmcounter12" bitsize="32"/>
102
- <reg name="hpmcounter13" bitsize="32"/>
103
- <reg name="hpmcounter14" bitsize="32"/>
104
- <reg name="hpmcounter15" bitsize="32"/>
105
- <reg name="hpmcounter16" bitsize="32"/>
106
- <reg name="hpmcounter17" bitsize="32"/>
107
- <reg name="hpmcounter18" bitsize="32"/>
108
- <reg name="hpmcounter19" bitsize="32"/>
109
- <reg name="hpmcounter20" bitsize="32"/>
110
- <reg name="hpmcounter21" bitsize="32"/>
111
- <reg name="hpmcounter22" bitsize="32"/>
112
- <reg name="hpmcounter23" bitsize="32"/>
113
- <reg name="hpmcounter24" bitsize="32"/>
114
- <reg name="hpmcounter25" bitsize="32"/>
115
- <reg name="hpmcounter26" bitsize="32"/>
116
- <reg name="hpmcounter27" bitsize="32"/>
117
- <reg name="hpmcounter28" bitsize="32"/>
118
- <reg name="hpmcounter29" bitsize="32"/>
119
- <reg name="hpmcounter30" bitsize="32"/>
120
- <reg name="hpmcounter31" bitsize="32"/>
121
- <reg name="cycleh" bitsize="32"/>
122
- <reg name="timeh" bitsize="32"/>
123
- <reg name="instreth" bitsize="32"/>
124
- <reg name="hpmcounter3h" bitsize="32"/>
125
- <reg name="hpmcounter4h" bitsize="32"/>
126
- <reg name="hpmcounter5h" bitsize="32"/>
127
- <reg name="hpmcounter6h" bitsize="32"/>
128
- <reg name="hpmcounter7h" bitsize="32"/>
129
- <reg name="hpmcounter8h" bitsize="32"/>
130
- <reg name="hpmcounter9h" bitsize="32"/>
131
- <reg name="hpmcounter10h" bitsize="32"/>
132
- <reg name="hpmcounter11h" bitsize="32"/>
133
- <reg name="hpmcounter12h" bitsize="32"/>
134
- <reg name="hpmcounter13h" bitsize="32"/>
135
- <reg name="hpmcounter14h" bitsize="32"/>
136
- <reg name="hpmcounter15h" bitsize="32"/>
137
- <reg name="hpmcounter16h" bitsize="32"/>
138
- <reg name="hpmcounter17h" bitsize="32"/>
139
- <reg name="hpmcounter18h" bitsize="32"/>
140
- <reg name="hpmcounter19h" bitsize="32"/>
141
- <reg name="hpmcounter20h" bitsize="32"/>
142
- <reg name="hpmcounter21h" bitsize="32"/>
143
- <reg name="hpmcounter22h" bitsize="32"/>
144
- <reg name="hpmcounter23h" bitsize="32"/>
145
- <reg name="hpmcounter24h" bitsize="32"/>
146
- <reg name="hpmcounter25h" bitsize="32"/>
147
- <reg name="hpmcounter26h" bitsize="32"/>
148
- <reg name="hpmcounter27h" bitsize="32"/>
149
- <reg name="hpmcounter28h" bitsize="32"/>
150
- <reg name="hpmcounter29h" bitsize="32"/>
151
- <reg name="hpmcounter30h" bitsize="32"/>
152
- <reg name="hpmcounter31h" bitsize="32"/>
153
- <reg name="sstatus" bitsize="32"/>
154
- <reg name="sedeleg" bitsize="32"/>
155
- <reg name="sideleg" bitsize="32"/>
156
- <reg name="sie" bitsize="32"/>
157
- <reg name="stvec" bitsize="32"/>
158
- <reg name="scounteren" bitsize="32"/>
159
- <reg name="sscratch" bitsize="32"/>
160
- <reg name="sepc" bitsize="32"/>
161
- <reg name="scause" bitsize="32"/>
162
- <reg name="stval" bitsize="32"/>
163
- <reg name="sip" bitsize="32"/>
164
- <reg name="satp" bitsize="32"/>
165
- <reg name="mvendorid" bitsize="32"/>
166
- <reg name="marchid" bitsize="32"/>
167
- <reg name="mimpid" bitsize="32"/>
168
- <reg name="mhartid" bitsize="32"/>
169
- <reg name="mstatus" bitsize="32"/>
170
- <reg name="misa" bitsize="32"/>
171
- <reg name="medeleg" bitsize="32"/>
172
- <reg name="mideleg" bitsize="32"/>
173
- <reg name="mie" bitsize="32"/>
174
- <reg name="mtvec" bitsize="32"/>
175
- <reg name="mcounteren" bitsize="32"/>
176
- <reg name="mscratch" bitsize="32"/>
177
- <reg name="mepc" bitsize="32"/>
178
- <reg name="mcause" bitsize="32"/>
179
- <reg name="mtval" bitsize="32"/>
180
- <reg name="mip" bitsize="32"/>
181
- <reg name="pmpcfg0" bitsize="32"/>
182
- <reg name="pmpcfg1" bitsize="32"/>
183
- <reg name="pmpcfg2" bitsize="32"/>
184
- <reg name="pmpcfg3" bitsize="32"/>
185
- <reg name="pmpaddr0" bitsize="32"/>
186
- <reg name="pmpaddr1" bitsize="32"/>
187
- <reg name="pmpaddr2" bitsize="32"/>
188
- <reg name="pmpaddr3" bitsize="32"/>
189
- <reg name="pmpaddr4" bitsize="32"/>
190
- <reg name="pmpaddr5" bitsize="32"/>
191
- <reg name="pmpaddr6" bitsize="32"/>
192
- <reg name="pmpaddr7" bitsize="32"/>
193
- <reg name="pmpaddr8" bitsize="32"/>
194
- <reg name="pmpaddr9" bitsize="32"/>
195
- <reg name="pmpaddr10" bitsize="32"/>
196
- <reg name="pmpaddr11" bitsize="32"/>
197
- <reg name="pmpaddr12" bitsize="32"/>
198
- <reg name="pmpaddr13" bitsize="32"/>
199
- <reg name="pmpaddr14" bitsize="32"/>
200
- <reg name="pmpaddr15" bitsize="32"/>
201
- <reg name="mcycle" bitsize="32"/>
202
- <reg name="minstret" bitsize="32"/>
203
- <reg name="mhpmcounter3" bitsize="32"/>
204
- <reg name="mhpmcounter4" bitsize="32"/>
205
- <reg name="mhpmcounter5" bitsize="32"/>
206
- <reg name="mhpmcounter6" bitsize="32"/>
207
- <reg name="mhpmcounter7" bitsize="32"/>
208
- <reg name="mhpmcounter8" bitsize="32"/>
209
- <reg name="mhpmcounter9" bitsize="32"/>
210
- <reg name="mhpmcounter10" bitsize="32"/>
211
- <reg name="mhpmcounter11" bitsize="32"/>
212
- <reg name="mhpmcounter12" bitsize="32"/>
213
- <reg name="mhpmcounter13" bitsize="32"/>
214
- <reg name="mhpmcounter14" bitsize="32"/>
215
- <reg name="mhpmcounter15" bitsize="32"/>
216
- <reg name="mhpmcounter16" bitsize="32"/>
217
- <reg name="mhpmcounter17" bitsize="32"/>
218
- <reg name="mhpmcounter18" bitsize="32"/>
219
- <reg name="mhpmcounter19" bitsize="32"/>
220
- <reg name="mhpmcounter20" bitsize="32"/>
221
- <reg name="mhpmcounter21" bitsize="32"/>
222
- <reg name="mhpmcounter22" bitsize="32"/>
223
- <reg name="mhpmcounter23" bitsize="32"/>
224
- <reg name="mhpmcounter24" bitsize="32"/>
225
- <reg name="mhpmcounter25" bitsize="32"/>
226
- <reg name="mhpmcounter26" bitsize="32"/>
227
- <reg name="mhpmcounter27" bitsize="32"/>
228
- <reg name="mhpmcounter28" bitsize="32"/>
229
- <reg name="mhpmcounter29" bitsize="32"/>
230
- <reg name="mhpmcounter30" bitsize="32"/>
231
- <reg name="mhpmcounter31" bitsize="32"/>
232
- <reg name="mcycleh" bitsize="32"/>
233
- <reg name="minstreth" bitsize="32"/>
234
- <reg name="mhpmcounter3h" bitsize="32"/>
235
- <reg name="mhpmcounter4h" bitsize="32"/>
236
- <reg name="mhpmcounter5h" bitsize="32"/>
237
- <reg name="mhpmcounter6h" bitsize="32"/>
238
- <reg name="mhpmcounter7h" bitsize="32"/>
239
- <reg name="mhpmcounter8h" bitsize="32"/>
240
- <reg name="mhpmcounter9h" bitsize="32"/>
241
- <reg name="mhpmcounter10h" bitsize="32"/>
242
- <reg name="mhpmcounter11h" bitsize="32"/>
243
- <reg name="mhpmcounter12h" bitsize="32"/>
244
- <reg name="mhpmcounter13h" bitsize="32"/>
245
- <reg name="mhpmcounter14h" bitsize="32"/>
246
- <reg name="mhpmcounter15h" bitsize="32"/>
247
- <reg name="mhpmcounter16h" bitsize="32"/>
248
- <reg name="mhpmcounter17h" bitsize="32"/>
249
- <reg name="mhpmcounter18h" bitsize="32"/>
250
- <reg name="mhpmcounter19h" bitsize="32"/>
251
- <reg name="mhpmcounter20h" bitsize="32"/>
252
- <reg name="mhpmcounter21h" bitsize="32"/>
253
- <reg name="mhpmcounter22h" bitsize="32"/>
254
- <reg name="mhpmcounter23h" bitsize="32"/>
255
- <reg name="mhpmcounter24h" bitsize="32"/>
256
- <reg name="mhpmcounter25h" bitsize="32"/>
257
- <reg name="mhpmcounter26h" bitsize="32"/>
258
- <reg name="mhpmcounter27h" bitsize="32"/>
259
- <reg name="mhpmcounter28h" bitsize="32"/>
260
- <reg name="mhpmcounter29h" bitsize="32"/>
261
- <reg name="mhpmcounter30h" bitsize="32"/>
262
- <reg name="mhpmcounter31h" bitsize="32"/>
263
- <reg name="mhpmevent3" bitsize="32"/>
264
- <reg name="mhpmevent4" bitsize="32"/>
265
- <reg name="mhpmevent5" bitsize="32"/>
266
- <reg name="mhpmevent6" bitsize="32"/>
267
- <reg name="mhpmevent7" bitsize="32"/>
268
- <reg name="mhpmevent8" bitsize="32"/>
269
- <reg name="mhpmevent9" bitsize="32"/>
270
- <reg name="mhpmevent10" bitsize="32"/>
271
- <reg name="mhpmevent11" bitsize="32"/>
272
- <reg name="mhpmevent12" bitsize="32"/>
273
- <reg name="mhpmevent13" bitsize="32"/>
274
- <reg name="mhpmevent14" bitsize="32"/>
275
- <reg name="mhpmevent15" bitsize="32"/>
276
- <reg name="mhpmevent16" bitsize="32"/>
277
- <reg name="mhpmevent17" bitsize="32"/>
278
- <reg name="mhpmevent18" bitsize="32"/>
279
- <reg name="mhpmevent19" bitsize="32"/>
280
- <reg name="mhpmevent20" bitsize="32"/>
281
- <reg name="mhpmevent21" bitsize="32"/>
282
- <reg name="mhpmevent22" bitsize="32"/>
283
- <reg name="mhpmevent23" bitsize="32"/>
284
- <reg name="mhpmevent24" bitsize="32"/>
285
- <reg name="mhpmevent25" bitsize="32"/>
286
- <reg name="mhpmevent26" bitsize="32"/>
287
- <reg name="mhpmevent27" bitsize="32"/>
288
- <reg name="mhpmevent28" bitsize="32"/>
289
- <reg name="mhpmevent29" bitsize="32"/>
290
- <reg name="mhpmevent30" bitsize="32"/>
291
- <reg name="mhpmevent31" bitsize="32"/>
292
- <reg name="tselect" bitsize="32"/>
293
- <reg name="tdata1" bitsize="32"/>
294
- <reg name="tdata2" bitsize="32"/>
295
- <reg name="tdata3" bitsize="32"/>
296
- <reg name="dcsr" bitsize="32"/>
297
- <reg name="dpc" bitsize="32"/>
298
- <reg name="dscratch" bitsize="32"/>
299
- <reg name="hstatus" bitsize="32"/>
300
- <reg name="hedeleg" bitsize="32"/>
301
- <reg name="hideleg" bitsize="32"/>
302
- <reg name="hie" bitsize="32"/>
303
- <reg name="htvec" bitsize="32"/>
304
- <reg name="hscratch" bitsize="32"/>
305
- <reg name="hepc" bitsize="32"/>
306
- <reg name="hcause" bitsize="32"/>
307
- <reg name="hbadaddr" bitsize="32"/>
308
- <reg name="hip" bitsize="32"/>
309
- <reg name="mbase" bitsize="32"/>
310
- <reg name="mbound" bitsize="32"/>
311
- <reg name="mibase" bitsize="32"/>
312
- <reg name="mibound" bitsize="32"/>
313
- <reg name="mdbase" bitsize="32"/>
314
- <reg name="mdbound" bitsize="32"/>
315
- <reg name="mucounteren" bitsize="32"/>
316
- <reg name="mscounteren" bitsize="32"/>
317
- <reg name="mhcounteren" bitsize="32"/>
318
-</feature>
319
diff --git a/gdb-xml/riscv-64bit-csr.xml b/gdb-xml/riscv-64bit-csr.xml
320
deleted file mode 100644
321
index XXXXXXX..XXXXXXX
322
--- a/gdb-xml/riscv-64bit-csr.xml
323
+++ /dev/null
324
@@ -XXX,XX +XXX,XX @@
325
-<?xml version="1.0"?>
326
-<!-- Copyright (C) 2018-2019 Free Software Foundation, Inc.
327
-
328
- Copying and distribution of this file, with or without modification,
329
- are permitted in any medium without royalty provided the copyright
330
- notice and this notice are preserved. -->
331
-
332
-<!DOCTYPE feature SYSTEM "gdb-target.dtd">
333
-<feature name="org.gnu.gdb.riscv.csr">
334
- <reg name="ustatus" bitsize="64"/>
335
- <reg name="uie" bitsize="64"/>
336
- <reg name="utvec" bitsize="64"/>
337
- <reg name="uscratch" bitsize="64"/>
338
- <reg name="uepc" bitsize="64"/>
339
- <reg name="ucause" bitsize="64"/>
340
- <reg name="utval" bitsize="64"/>
341
- <reg name="uip" bitsize="64"/>
342
- <reg name="fflags" bitsize="64"/>
343
- <reg name="frm" bitsize="64"/>
344
- <reg name="fcsr" bitsize="64"/>
345
- <reg name="cycle" bitsize="64"/>
346
- <reg name="time" bitsize="64"/>
347
- <reg name="instret" bitsize="64"/>
348
- <reg name="hpmcounter3" bitsize="64"/>
349
- <reg name="hpmcounter4" bitsize="64"/>
350
- <reg name="hpmcounter5" bitsize="64"/>
351
- <reg name="hpmcounter6" bitsize="64"/>
352
- <reg name="hpmcounter7" bitsize="64"/>
353
- <reg name="hpmcounter8" bitsize="64"/>
354
- <reg name="hpmcounter9" bitsize="64"/>
355
- <reg name="hpmcounter10" bitsize="64"/>
356
- <reg name="hpmcounter11" bitsize="64"/>
357
- <reg name="hpmcounter12" bitsize="64"/>
358
- <reg name="hpmcounter13" bitsize="64"/>
359
- <reg name="hpmcounter14" bitsize="64"/>
360
- <reg name="hpmcounter15" bitsize="64"/>
361
- <reg name="hpmcounter16" bitsize="64"/>
362
- <reg name="hpmcounter17" bitsize="64"/>
363
- <reg name="hpmcounter18" bitsize="64"/>
364
- <reg name="hpmcounter19" bitsize="64"/>
365
- <reg name="hpmcounter20" bitsize="64"/>
366
- <reg name="hpmcounter21" bitsize="64"/>
367
- <reg name="hpmcounter22" bitsize="64"/>
368
- <reg name="hpmcounter23" bitsize="64"/>
369
- <reg name="hpmcounter24" bitsize="64"/>
370
- <reg name="hpmcounter25" bitsize="64"/>
371
- <reg name="hpmcounter26" bitsize="64"/>
372
- <reg name="hpmcounter27" bitsize="64"/>
373
- <reg name="hpmcounter28" bitsize="64"/>
374
- <reg name="hpmcounter29" bitsize="64"/>
375
- <reg name="hpmcounter30" bitsize="64"/>
376
- <reg name="hpmcounter31" bitsize="64"/>
377
- <reg name="cycleh" bitsize="64"/>
378
- <reg name="timeh" bitsize="64"/>
379
- <reg name="instreth" bitsize="64"/>
380
- <reg name="hpmcounter3h" bitsize="64"/>
381
- <reg name="hpmcounter4h" bitsize="64"/>
382
- <reg name="hpmcounter5h" bitsize="64"/>
383
- <reg name="hpmcounter6h" bitsize="64"/>
384
- <reg name="hpmcounter7h" bitsize="64"/>
385
- <reg name="hpmcounter8h" bitsize="64"/>
386
- <reg name="hpmcounter9h" bitsize="64"/>
387
- <reg name="hpmcounter10h" bitsize="64"/>
388
- <reg name="hpmcounter11h" bitsize="64"/>
389
- <reg name="hpmcounter12h" bitsize="64"/>
390
- <reg name="hpmcounter13h" bitsize="64"/>
391
- <reg name="hpmcounter14h" bitsize="64"/>
392
- <reg name="hpmcounter15h" bitsize="64"/>
393
- <reg name="hpmcounter16h" bitsize="64"/>
394
- <reg name="hpmcounter17h" bitsize="64"/>
395
- <reg name="hpmcounter18h" bitsize="64"/>
396
- <reg name="hpmcounter19h" bitsize="64"/>
397
- <reg name="hpmcounter20h" bitsize="64"/>
398
- <reg name="hpmcounter21h" bitsize="64"/>
399
- <reg name="hpmcounter22h" bitsize="64"/>
400
- <reg name="hpmcounter23h" bitsize="64"/>
401
- <reg name="hpmcounter24h" bitsize="64"/>
402
- <reg name="hpmcounter25h" bitsize="64"/>
403
- <reg name="hpmcounter26h" bitsize="64"/>
404
- <reg name="hpmcounter27h" bitsize="64"/>
405
- <reg name="hpmcounter28h" bitsize="64"/>
406
- <reg name="hpmcounter29h" bitsize="64"/>
407
- <reg name="hpmcounter30h" bitsize="64"/>
408
- <reg name="hpmcounter31h" bitsize="64"/>
409
- <reg name="sstatus" bitsize="64"/>
410
- <reg name="sedeleg" bitsize="64"/>
411
- <reg name="sideleg" bitsize="64"/>
412
- <reg name="sie" bitsize="64"/>
413
- <reg name="stvec" bitsize="64"/>
414
- <reg name="scounteren" bitsize="64"/>
415
- <reg name="sscratch" bitsize="64"/>
416
- <reg name="sepc" bitsize="64"/>
417
- <reg name="scause" bitsize="64"/>
418
- <reg name="stval" bitsize="64"/>
419
- <reg name="sip" bitsize="64"/>
420
- <reg name="satp" bitsize="64"/>
421
- <reg name="mvendorid" bitsize="64"/>
422
- <reg name="marchid" bitsize="64"/>
423
- <reg name="mimpid" bitsize="64"/>
424
- <reg name="mhartid" bitsize="64"/>
425
- <reg name="mstatus" bitsize="64"/>
426
- <reg name="misa" bitsize="64"/>
427
- <reg name="medeleg" bitsize="64"/>
428
- <reg name="mideleg" bitsize="64"/>
429
- <reg name="mie" bitsize="64"/>
430
- <reg name="mtvec" bitsize="64"/>
431
- <reg name="mcounteren" bitsize="64"/>
432
- <reg name="mscratch" bitsize="64"/>
433
- <reg name="mepc" bitsize="64"/>
434
- <reg name="mcause" bitsize="64"/>
435
- <reg name="mtval" bitsize="64"/>
436
- <reg name="mip" bitsize="64"/>
437
- <reg name="pmpcfg0" bitsize="64"/>
438
- <reg name="pmpcfg1" bitsize="64"/>
439
- <reg name="pmpcfg2" bitsize="64"/>
440
- <reg name="pmpcfg3" bitsize="64"/>
441
- <reg name="pmpaddr0" bitsize="64"/>
442
- <reg name="pmpaddr1" bitsize="64"/>
443
- <reg name="pmpaddr2" bitsize="64"/>
444
- <reg name="pmpaddr3" bitsize="64"/>
445
- <reg name="pmpaddr4" bitsize="64"/>
446
- <reg name="pmpaddr5" bitsize="64"/>
447
- <reg name="pmpaddr6" bitsize="64"/>
448
- <reg name="pmpaddr7" bitsize="64"/>
449
- <reg name="pmpaddr8" bitsize="64"/>
450
- <reg name="pmpaddr9" bitsize="64"/>
451
- <reg name="pmpaddr10" bitsize="64"/>
452
- <reg name="pmpaddr11" bitsize="64"/>
453
- <reg name="pmpaddr12" bitsize="64"/>
454
- <reg name="pmpaddr13" bitsize="64"/>
455
- <reg name="pmpaddr14" bitsize="64"/>
456
- <reg name="pmpaddr15" bitsize="64"/>
457
- <reg name="mcycle" bitsize="64"/>
458
- <reg name="minstret" bitsize="64"/>
459
- <reg name="mhpmcounter3" bitsize="64"/>
460
- <reg name="mhpmcounter4" bitsize="64"/>
461
- <reg name="mhpmcounter5" bitsize="64"/>
462
- <reg name="mhpmcounter6" bitsize="64"/>
463
- <reg name="mhpmcounter7" bitsize="64"/>
464
- <reg name="mhpmcounter8" bitsize="64"/>
465
- <reg name="mhpmcounter9" bitsize="64"/>
466
- <reg name="mhpmcounter10" bitsize="64"/>
467
- <reg name="mhpmcounter11" bitsize="64"/>
468
- <reg name="mhpmcounter12" bitsize="64"/>
469
- <reg name="mhpmcounter13" bitsize="64"/>
470
- <reg name="mhpmcounter14" bitsize="64"/>
471
- <reg name="mhpmcounter15" bitsize="64"/>
472
- <reg name="mhpmcounter16" bitsize="64"/>
473
- <reg name="mhpmcounter17" bitsize="64"/>
474
- <reg name="mhpmcounter18" bitsize="64"/>
475
- <reg name="mhpmcounter19" bitsize="64"/>
476
- <reg name="mhpmcounter20" bitsize="64"/>
477
- <reg name="mhpmcounter21" bitsize="64"/>
478
- <reg name="mhpmcounter22" bitsize="64"/>
479
- <reg name="mhpmcounter23" bitsize="64"/>
480
- <reg name="mhpmcounter24" bitsize="64"/>
481
- <reg name="mhpmcounter25" bitsize="64"/>
482
- <reg name="mhpmcounter26" bitsize="64"/>
483
- <reg name="mhpmcounter27" bitsize="64"/>
484
- <reg name="mhpmcounter28" bitsize="64"/>
485
- <reg name="mhpmcounter29" bitsize="64"/>
486
- <reg name="mhpmcounter30" bitsize="64"/>
487
- <reg name="mhpmcounter31" bitsize="64"/>
488
- <reg name="mcycleh" bitsize="64"/>
489
- <reg name="minstreth" bitsize="64"/>
490
- <reg name="mhpmcounter3h" bitsize="64"/>
491
- <reg name="mhpmcounter4h" bitsize="64"/>
492
- <reg name="mhpmcounter5h" bitsize="64"/>
493
- <reg name="mhpmcounter6h" bitsize="64"/>
494
- <reg name="mhpmcounter7h" bitsize="64"/>
495
- <reg name="mhpmcounter8h" bitsize="64"/>
496
- <reg name="mhpmcounter9h" bitsize="64"/>
497
- <reg name="mhpmcounter10h" bitsize="64"/>
498
- <reg name="mhpmcounter11h" bitsize="64"/>
499
- <reg name="mhpmcounter12h" bitsize="64"/>
500
- <reg name="mhpmcounter13h" bitsize="64"/>
501
- <reg name="mhpmcounter14h" bitsize="64"/>
502
- <reg name="mhpmcounter15h" bitsize="64"/>
503
- <reg name="mhpmcounter16h" bitsize="64"/>
504
- <reg name="mhpmcounter17h" bitsize="64"/>
505
- <reg name="mhpmcounter18h" bitsize="64"/>
506
- <reg name="mhpmcounter19h" bitsize="64"/>
507
- <reg name="mhpmcounter20h" bitsize="64"/>
508
- <reg name="mhpmcounter21h" bitsize="64"/>
509
- <reg name="mhpmcounter22h" bitsize="64"/>
510
- <reg name="mhpmcounter23h" bitsize="64"/>
511
- <reg name="mhpmcounter24h" bitsize="64"/>
512
- <reg name="mhpmcounter25h" bitsize="64"/>
513
- <reg name="mhpmcounter26h" bitsize="64"/>
514
- <reg name="mhpmcounter27h" bitsize="64"/>
515
- <reg name="mhpmcounter28h" bitsize="64"/>
516
- <reg name="mhpmcounter29h" bitsize="64"/>
517
- <reg name="mhpmcounter30h" bitsize="64"/>
518
- <reg name="mhpmcounter31h" bitsize="64"/>
519
- <reg name="mhpmevent3" bitsize="64"/>
520
- <reg name="mhpmevent4" bitsize="64"/>
521
- <reg name="mhpmevent5" bitsize="64"/>
522
- <reg name="mhpmevent6" bitsize="64"/>
523
- <reg name="mhpmevent7" bitsize="64"/>
524
- <reg name="mhpmevent8" bitsize="64"/>
525
- <reg name="mhpmevent9" bitsize="64"/>
526
- <reg name="mhpmevent10" bitsize="64"/>
527
- <reg name="mhpmevent11" bitsize="64"/>
528
- <reg name="mhpmevent12" bitsize="64"/>
529
- <reg name="mhpmevent13" bitsize="64"/>
530
- <reg name="mhpmevent14" bitsize="64"/>
531
- <reg name="mhpmevent15" bitsize="64"/>
532
- <reg name="mhpmevent16" bitsize="64"/>
533
- <reg name="mhpmevent17" bitsize="64"/>
534
- <reg name="mhpmevent18" bitsize="64"/>
535
- <reg name="mhpmevent19" bitsize="64"/>
536
- <reg name="mhpmevent20" bitsize="64"/>
537
- <reg name="mhpmevent21" bitsize="64"/>
538
- <reg name="mhpmevent22" bitsize="64"/>
539
- <reg name="mhpmevent23" bitsize="64"/>
540
- <reg name="mhpmevent24" bitsize="64"/>
541
- <reg name="mhpmevent25" bitsize="64"/>
542
- <reg name="mhpmevent26" bitsize="64"/>
543
- <reg name="mhpmevent27" bitsize="64"/>
544
- <reg name="mhpmevent28" bitsize="64"/>
545
- <reg name="mhpmevent29" bitsize="64"/>
546
- <reg name="mhpmevent30" bitsize="64"/>
547
- <reg name="mhpmevent31" bitsize="64"/>
548
- <reg name="tselect" bitsize="64"/>
549
- <reg name="tdata1" bitsize="64"/>
550
- <reg name="tdata2" bitsize="64"/>
551
- <reg name="tdata3" bitsize="64"/>
552
- <reg name="dcsr" bitsize="64"/>
553
- <reg name="dpc" bitsize="64"/>
554
- <reg name="dscratch" bitsize="64"/>
555
- <reg name="hstatus" bitsize="64"/>
556
- <reg name="hedeleg" bitsize="64"/>
557
- <reg name="hideleg" bitsize="64"/>
558
- <reg name="hie" bitsize="64"/>
559
- <reg name="htvec" bitsize="64"/>
560
- <reg name="hscratch" bitsize="64"/>
561
- <reg name="hepc" bitsize="64"/>
562
- <reg name="hcause" bitsize="64"/>
563
- <reg name="hbadaddr" bitsize="64"/>
564
- <reg name="hip" bitsize="64"/>
565
- <reg name="mbase" bitsize="64"/>
566
- <reg name="mbound" bitsize="64"/>
567
- <reg name="mibase" bitsize="64"/>
568
- <reg name="mibound" bitsize="64"/>
569
- <reg name="mdbase" bitsize="64"/>
570
- <reg name="mdbound" bitsize="64"/>
571
- <reg name="mucounteren" bitsize="64"/>
572
- <reg name="mscounteren" bitsize="64"/>
573
- <reg name="mhcounteren" bitsize="64"/>
574
-</feature>
575
--
36
--
576
2.29.2
37
2.45.1
577
38
578
39
diff view generated by jsdifflib
New patch
[PULL 07/28] target/riscv/kvm: tolerate KVM disable ext errors
1
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
1
2
3
Running a KVM guest using a 6.9-rc3 kernel, in a 6.8 host that has zkr
4
enabled, will fail with a kernel oops SIGILL right at the start. The
5
reason is that we can't expose zkr without implementing the SEED CSR.
6
Disabling zkr in the guest would be a workaround, but if the KVM doesn't
7
allow it we'll error out and never boot.
8
9
In hindsight this is too strict. If we keep proceeding, despite not
10
disabling the extension in the KVM vcpu, we'll not add the extension in
11
the riscv,isa. The guest kernel will be unaware of the extension, i.e.
12
it doesn't matter if the KVM vcpu has it enabled underneath or not. So
13
it's ok to keep booting in this case.
14
15
Change our current logic to not error out if we fail to disable an
16
extension in kvm_set_one_reg(), but show a warning and keep booting. It
17
is important to throw a warning because we must make the user aware that
18
the extension is still available in the vcpu, meaning that an
19
ill-behaved guest can ignore the riscv,isa settings and use the
20
extension.
21
22
The case we're handling happens with an EINVAL error code. If we fail to
23
disable the extension in KVM for any other reason, error out.
24
25
We'll also keep erroring out when we fail to enable an extension in KVM,
26
since adding the extension in riscv,isa at this point will cause a guest
27
malfunction because the extension isn't enabled in the vcpu.
28
29
Suggested-by: Andrew Jones <ajones@ventanamicro.com>
30
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
31
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
32
Cc: qemu-stable <qemu-stable@nongnu.org>
33
Message-ID: <20240422171425.333037-2-dbarboza@ventanamicro.com>
34
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
35
---
36
target/riscv/kvm/kvm-cpu.c | 12 ++++++++----
37
1 file changed, 8 insertions(+), 4 deletions(-)
38
39
diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
40
index XXXXXXX..XXXXXXX 100644
41
--- a/target/riscv/kvm/kvm-cpu.c
42
+++ b/target/riscv/kvm/kvm-cpu.c
43
@@ -XXX,XX +XXX,XX @@ static void kvm_riscv_update_cpu_cfg_isa_ext(RISCVCPU *cpu, CPUState *cs)
44
reg = kvm_cpu_cfg_get(cpu, multi_ext_cfg);
45
ret = kvm_set_one_reg(cs, id, &reg);
46
if (ret != 0) {
47
- error_report("Unable to %s extension %s in KVM, error %d",
48
- reg ? "enable" : "disable",
49
- multi_ext_cfg->name, ret);
50
- exit(EXIT_FAILURE);
51
+ if (!reg && ret == -EINVAL) {
52
+ warn_report("KVM cannot disable extension %s",
53
+ multi_ext_cfg->name);
54
+ } else {
55
+ error_report("Unable to enable extension %s in KVM, error %d",
56
+ multi_ext_cfg->name, ret);
57
+ exit(EXIT_FAILURE);
58
+ }
59
}
60
}
61
}
62
--
63
2.45.1
diff view generated by jsdifflib
New patch
[PULL 08/28] target/riscv/debug: set tval=pc in breakpoint exceptions
1
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
1
2
3
We're not setting (s/m)tval when triggering breakpoints of type 2
4
(mcontrol) and 6 (mcontrol6). According to the debug spec section
5
5.7.12, "Match Control Type 6":
6
7
"The Privileged Spec says that breakpoint exceptions that occur on
8
instruction fetches, loads, or stores update the tval CSR with either
9
zero or the faulting virtual address. The faulting virtual address for
10
an mcontrol6 trigger with action = 0 is the address being accessed and
11
which caused that trigger to fire."
12
13
A similar text is also found in the Debug spec section 5.7.11 w.r.t.
14
mcontrol.
15
16
Note that what we're doing ATM is not violating the spec, but it's
17
simple enough to set mtval/stval and it makes life easier for any
18
software that relies on this info.
19
20
Given that we always use action = 0, save the faulting address for the
21
mcontrol and mcontrol6 trigger breakpoints into env->badaddr, which is
22
used as as scratch area for traps with address information. 'tval' is
23
then set during riscv_cpu_do_interrupt().
24
25
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
26
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
27
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
28
Message-ID: <20240416230437.1869024-2-dbarboza@ventanamicro.com>
29
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
30
---
31
target/riscv/cpu_helper.c | 1 +
32
target/riscv/debug.c | 3 +++
33
2 files changed, 4 insertions(+)
34
35
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
36
index XXXXXXX..XXXXXXX 100644
37
--- a/target/riscv/cpu_helper.c
38
+++ b/target/riscv/cpu_helper.c
39
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
40
tval = env->bins;
41
break;
42
case RISCV_EXCP_BREAKPOINT:
43
+ tval = env->badaddr;
44
if (cs->watchpoint_hit) {
45
tval = cs->watchpoint_hit->hitaddr;
46
cs->watchpoint_hit = NULL;
47
diff --git a/target/riscv/debug.c b/target/riscv/debug.c
48
index XXXXXXX..XXXXXXX 100644
49
--- a/target/riscv/debug.c
50
+++ b/target/riscv/debug.c
51
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_debug_check_breakpoint(CPUState *cs)
52
if ((ctrl & TYPE2_EXEC) && (bp->pc == pc)) {
53
/* check U/S/M bit against current privilege level */
54
if ((ctrl >> 3) & BIT(env->priv)) {
55
+ env->badaddr = pc;
56
return true;
57
}
58
}
59
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_debug_check_breakpoint(CPUState *cs)
60
if (env->virt_enabled) {
61
/* check VU/VS bit against current privilege level */
62
if ((ctrl >> 23) & BIT(env->priv)) {
63
+ env->badaddr = pc;
64
return true;
65
}
66
} else {
67
/* check U/S/M bit against current privilege level */
68
if ((ctrl >> 3) & BIT(env->priv)) {
69
+ env->badaddr = pc;
70
return true;
71
}
72
}
73
--
74
2.45.1
diff view generated by jsdifflib
New patch
[PULL 09/28] trans_privileged.c.inc: set (m|s)tval on ebreak breakpoint
1
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
1
2
3
Privileged spec section 4.1.9 mentions:
4
5
"When a trap is taken into S-mode, stval is written with
6
exception-specific information to assist software in handling the trap.
7
(...)
8
9
If stval is written with a nonzero value when a breakpoint,
10
address-misaligned, access-fault, or page-fault exception occurs on an
11
instruction fetch, load, or store, then stval will contain the faulting
12
virtual address."
13
14
A similar text is found for mtval in section 3.1.16.
15
16
Setting mtval/stval in this scenario is optional, but some softwares read
17
these regs when handling ebreaks.
18
19
Write 'badaddr' in all ebreak breakpoints to write the appropriate
20
'tval' during riscv_do_cpu_interrrupt().
21
22
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
23
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
24
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
25
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
26
Message-ID: <20240416230437.1869024-3-dbarboza@ventanamicro.com>
27
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
28
---
29
target/riscv/insn_trans/trans_privileged.c.inc | 2 ++
30
1 file changed, 2 insertions(+)
31
32
diff --git a/target/riscv/insn_trans/trans_privileged.c.inc b/target/riscv/insn_trans/trans_privileged.c.inc
33
index XXXXXXX..XXXXXXX 100644
34
--- a/target/riscv/insn_trans/trans_privileged.c.inc
35
+++ b/target/riscv/insn_trans/trans_privileged.c.inc
36
@@ -XXX,XX +XXX,XX @@ static bool trans_ebreak(DisasContext *ctx, arg_ebreak *a)
37
if (pre == 0x01f01013 && ebreak == 0x00100073 && post == 0x40705013) {
38
generate_exception(ctx, RISCV_EXCP_SEMIHOST);
39
} else {
40
+ tcg_gen_st_tl(tcg_constant_tl(ebreak_addr), tcg_env,
41
+ offsetof(CPURISCVState, badaddr));
42
generate_exception(ctx, RISCV_EXCP_BREAKPOINT);
43
}
44
return true;
45
--
46
2.45.1
diff view generated by jsdifflib
New patch
[PULL 10/28] target/riscv: Add support for Zve32x extension
1
From: Jason Chien <jason.chien@sifive.com>
1
2
3
Add support for Zve32x extension and replace some checks for Zve32f with
4
Zve32x, since Zve32f depends on Zve32x.
5
6
Signed-off-by: Jason Chien <jason.chien@sifive.com>
7
Reviewed-by: Frank Chang <frank.chang@sifive.com>
8
Reviewed-by: Max Chou <max.chou@sifive.com>
9
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
10
Message-ID: <20240328022343.6871-2-jason.chien@sifive.com>
11
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
12
---
13
target/riscv/cpu_cfg.h | 1 +
14
target/riscv/cpu.c | 2 ++
15
target/riscv/cpu_helper.c | 2 +-
16
target/riscv/csr.c | 2 +-
17
target/riscv/tcg/tcg-cpu.c | 16 ++++++++--------
18
target/riscv/insn_trans/trans_rvv.c.inc | 4 ++--
19
6 files changed, 15 insertions(+), 12 deletions(-)
20
21
diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
22
index XXXXXXX..XXXXXXX 100644
23
--- a/target/riscv/cpu_cfg.h
24
+++ b/target/riscv/cpu_cfg.h
25
@@ -XXX,XX +XXX,XX @@ struct RISCVCPUConfig {
26
bool ext_zhinx;
27
bool ext_zhinxmin;
28
bool ext_zve32f;
29
+ bool ext_zve32x;
30
bool ext_zve64f;
31
bool ext_zve64d;
32
bool ext_zvbb;
33
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
34
index XXXXXXX..XXXXXXX 100644
35
--- a/target/riscv/cpu.c
36
+++ b/target/riscv/cpu.c
37
@@ -XXX,XX +XXX,XX @@ const RISCVIsaExtData isa_edata_arr[] = {
38
ISA_EXT_DATA_ENTRY(zvbb, PRIV_VERSION_1_12_0, ext_zvbb),
39
ISA_EXT_DATA_ENTRY(zvbc, PRIV_VERSION_1_12_0, ext_zvbc),
40
ISA_EXT_DATA_ENTRY(zve32f, PRIV_VERSION_1_10_0, ext_zve32f),
41
+ ISA_EXT_DATA_ENTRY(zve32x, PRIV_VERSION_1_10_0, ext_zve32x),
42
ISA_EXT_DATA_ENTRY(zve64f, PRIV_VERSION_1_10_0, ext_zve64f),
43
ISA_EXT_DATA_ENTRY(zve64d, PRIV_VERSION_1_10_0, ext_zve64d),
44
ISA_EXT_DATA_ENTRY(zvfbfmin, PRIV_VERSION_1_12_0, ext_zvfbfmin),
45
@@ -XXX,XX +XXX,XX @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
46
MULTI_EXT_CFG_BOOL("zfh", ext_zfh, false),
47
MULTI_EXT_CFG_BOOL("zfhmin", ext_zfhmin, false),
48
MULTI_EXT_CFG_BOOL("zve32f", ext_zve32f, false),
49
+ MULTI_EXT_CFG_BOOL("zve32x", ext_zve32x, false),
50
MULTI_EXT_CFG_BOOL("zve64f", ext_zve64f, false),
51
MULTI_EXT_CFG_BOOL("zve64d", ext_zve64d, false),
52
MULTI_EXT_CFG_BOOL("zvfbfmin", ext_zvfbfmin, false),
53
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
54
index XXXXXXX..XXXXXXX 100644
55
--- a/target/riscv/cpu_helper.c
56
+++ b/target/riscv/cpu_helper.c
57
@@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc,
58
*pc = env->xl == MXL_RV32 ? env->pc & UINT32_MAX : env->pc;
59
*cs_base = 0;
60
61
- if (cpu->cfg.ext_zve32f) {
62
+ if (cpu->cfg.ext_zve32x) {
63
/*
64
* If env->vl equals to VLMAX, we can use generic vector operation
65
* expanders (GVEC) to accerlate the vector operations.
66
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
67
index XXXXXXX..XXXXXXX 100644
68
--- a/target/riscv/csr.c
69
+++ b/target/riscv/csr.c
70
@@ -XXX,XX +XXX,XX @@ static RISCVException fs(CPURISCVState *env, int csrno)
71
72
static RISCVException vs(CPURISCVState *env, int csrno)
73
{
74
- if (riscv_cpu_cfg(env)->ext_zve32f) {
75
+ if (riscv_cpu_cfg(env)->ext_zve32x) {
76
#if !defined(CONFIG_USER_ONLY)
77
if (!env->debugger && !riscv_cpu_vector_enabled(env)) {
78
return RISCV_EXCP_ILLEGAL_INST;
79
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
80
index XXXXXXX..XXXXXXX 100644
81
--- a/target/riscv/tcg/tcg-cpu.c
82
+++ b/target/riscv/tcg/tcg-cpu.c
83
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
84
return;
85
}
86
87
- if (cpu->cfg.ext_zve32f && !riscv_has_ext(env, RVF)) {
88
- error_setg(errp, "Zve32f/Zve64f extensions require F extension");
89
- return;
90
+ /* The Zve32f extension depends on the Zve32x extension */
91
+ if (cpu->cfg.ext_zve32f) {
92
+ if (!riscv_has_ext(env, RVF)) {
93
+ error_setg(errp, "Zve32f/Zve64f extensions require F extension");
94
+ return;
95
+ }
96
+ cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve32x), true);
97
}
98
99
if (cpu->cfg.ext_zvfh) {
100
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
101
cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvbc), true);
102
}
103
104
- /*
105
- * In principle Zve*x would also suffice here, were they supported
106
- * in qemu
107
- */
108
if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkb || cpu->cfg.ext_zvkg ||
109
cpu->cfg.ext_zvkned || cpu->cfg.ext_zvknha || cpu->cfg.ext_zvksed ||
110
- cpu->cfg.ext_zvksh) && !cpu->cfg.ext_zve32f) {
111
+ cpu->cfg.ext_zvksh) && !cpu->cfg.ext_zve32x) {
112
error_setg(errp,
113
"Vector crypto extensions require V or Zve* extensions");
114
return;
115
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
116
index XXXXXXX..XXXXXXX 100644
117
--- a/target/riscv/insn_trans/trans_rvv.c.inc
118
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
119
@@ -XXX,XX +XXX,XX @@ static bool do_vsetvl(DisasContext *s, int rd, int rs1, TCGv s2)
120
{
121
TCGv s1, dst;
122
123
- if (!require_rvv(s) || !s->cfg_ptr->ext_zve32f) {
124
+ if (!require_rvv(s) || !s->cfg_ptr->ext_zve32x) {
125
return false;
126
}
127
128
@@ -XXX,XX +XXX,XX @@ static bool do_vsetivli(DisasContext *s, int rd, TCGv s1, TCGv s2)
129
{
130
TCGv dst;
131
132
- if (!require_rvv(s) || !s->cfg_ptr->ext_zve32f) {
133
+ if (!require_rvv(s) || !s->cfg_ptr->ext_zve32x) {
134
return false;
135
}
136
137
--
138
2.45.1
diff view generated by jsdifflib
[PULL 12/12] riscv: Pass RISCVHartArrayState by pointer
[PULL 11/28] target/riscv: Add support for Zve64x extension
1
We were accidently passing RISCVHartArrayState by value instead of
1
From: Jason Chien <jason.chien@sifive.com>
2
pointer. The type is 824 bytes long so let's correct that and pass it by
3
pointer instead.
4
2
5
Fixes: Coverity CID 1438099
3
Add support for Zve64x extension. Enabling Zve64f enables Zve64x and
6
Fixes: Coverity CID 1438100
4
enabling Zve64x enables Zve32x according to their dependency.
7
Fixes: Coverity CID 1438101
5
6
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2107
7
Signed-off-by: Jason Chien <jason.chien@sifive.com>
8
Reviewed-by: Frank Chang <frank.chang@sifive.com>
9
Reviewed-by: Max Chou <max.chou@sifive.com>
10
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
11
Message-ID: <20240328022343.6871-3-jason.chien@sifive.com>
8
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
12
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
9
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
10
Reviewed-by: Bin Meng <bin.meng@windriver.com>
11
Message-id: f3e04424723e0e222769991896cc82308fd23f76.1610751609.git.alistair.francis@wdc.com
12
---
13
---
13
include/hw/riscv/boot.h | 6 +++---
14
target/riscv/cpu_cfg.h | 1 +
14
hw/riscv/boot.c | 10 ++++------
15
target/riscv/cpu.c | 2 ++
15
hw/riscv/sifive_u.c | 10 +++++-----
16
target/riscv/tcg/tcg-cpu.c | 17 +++++++++++------
16
hw/riscv/spike.c | 8 ++++----
17
3 files changed, 14 insertions(+), 6 deletions(-)
17
hw/riscv/virt.c | 8 ++++----
18
5 files changed, 20 insertions(+), 22 deletions(-)
19
18
20
diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h
19
diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
21
index XXXXXXX..XXXXXXX 100644
20
index XXXXXXX..XXXXXXX 100644
22
--- a/include/hw/riscv/boot.h
21
--- a/target/riscv/cpu_cfg.h
23
+++ b/include/hw/riscv/boot.h
22
+++ b/target/riscv/cpu_cfg.h
24
@@ -XXX,XX +XXX,XX @@
23
@@ -XXX,XX +XXX,XX @@ struct RISCVCPUConfig {
25
#include "hw/loader.h"
24
bool ext_zve32x;
26
#include "hw/riscv/riscv_hart.h"
25
bool ext_zve64f;
27
26
bool ext_zve64d;
28
-bool riscv_is_32bit(RISCVHartArrayState harts);
27
+ bool ext_zve64x;
29
+bool riscv_is_32bit(RISCVHartArrayState *harts);
28
bool ext_zvbb;
30
29
bool ext_zvbc;
31
-target_ulong riscv_calc_kernel_start_addr(RISCVHartArrayState harts,
30
bool ext_zvkb;
32
+target_ulong riscv_calc_kernel_start_addr(RISCVHartArrayState *harts,
31
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
33
target_ulong firmware_end_addr);
34
target_ulong riscv_find_and_load_firmware(MachineState *machine,
35
const char *default_machine_firmware,
36
@@ -XXX,XX +XXX,XX @@ target_ulong riscv_load_kernel(const char *kernel_filename,
37
hwaddr riscv_load_initrd(const char *filename, uint64_t mem_size,
38
uint64_t kernel_entry, hwaddr *start);
39
uint32_t riscv_load_fdt(hwaddr dram_start, uint64_t dram_size, void *fdt);
40
-void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState harts,
41
+void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState *harts,
42
hwaddr saddr,
43
hwaddr rom_base, hwaddr rom_size,
44
uint64_t kernel_entry,
45
diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
46
index XXXXXXX..XXXXXXX 100644
32
index XXXXXXX..XXXXXXX 100644
47
--- a/hw/riscv/boot.c
33
--- a/target/riscv/cpu.c
48
+++ b/hw/riscv/boot.c
34
+++ b/target/riscv/cpu.c
49
@@ -XXX,XX +XXX,XX @@
35
@@ -XXX,XX +XXX,XX @@ const RISCVIsaExtData isa_edata_arr[] = {
50
36
ISA_EXT_DATA_ENTRY(zve32x, PRIV_VERSION_1_10_0, ext_zve32x),
51
#include <libfdt.h>
37
ISA_EXT_DATA_ENTRY(zve64f, PRIV_VERSION_1_10_0, ext_zve64f),
52
38
ISA_EXT_DATA_ENTRY(zve64d, PRIV_VERSION_1_10_0, ext_zve64d),
53
-bool riscv_is_32bit(RISCVHartArrayState harts)
39
+ ISA_EXT_DATA_ENTRY(zve64x, PRIV_VERSION_1_10_0, ext_zve64x),
54
+bool riscv_is_32bit(RISCVHartArrayState *harts)
40
ISA_EXT_DATA_ENTRY(zvfbfmin, PRIV_VERSION_1_12_0, ext_zvfbfmin),
55
{
41
ISA_EXT_DATA_ENTRY(zvfbfwma, PRIV_VERSION_1_12_0, ext_zvfbfwma),
56
- RISCVCPU hart = harts.harts[0];
42
ISA_EXT_DATA_ENTRY(zvfh, PRIV_VERSION_1_12_0, ext_zvfh),
57
-
43
@@ -XXX,XX +XXX,XX @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
58
- return riscv_cpu_is_32bit(&hart.env);
44
MULTI_EXT_CFG_BOOL("zve32x", ext_zve32x, false),
59
+ return riscv_cpu_is_32bit(&harts->harts[0].env);
45
MULTI_EXT_CFG_BOOL("zve64f", ext_zve64f, false),
60
}
46
MULTI_EXT_CFG_BOOL("zve64d", ext_zve64d, false),
61
47
+ MULTI_EXT_CFG_BOOL("zve64x", ext_zve64x, false),
62
-target_ulong riscv_calc_kernel_start_addr(RISCVHartArrayState harts,
48
MULTI_EXT_CFG_BOOL("zvfbfmin", ext_zvfbfmin, false),
63
+target_ulong riscv_calc_kernel_start_addr(RISCVHartArrayState *harts,
49
MULTI_EXT_CFG_BOOL("zvfbfwma", ext_zvfbfwma, false),
64
target_ulong firmware_end_addr) {
50
MULTI_EXT_CFG_BOOL("zvfh", ext_zvfh, false),
65
if (riscv_is_32bit(harts)) {
51
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
66
return QEMU_ALIGN_UP(firmware_end_addr, 4 * MiB);
67
@@ -XXX,XX +XXX,XX @@ void riscv_rom_copy_firmware_info(MachineState *machine, hwaddr rom_base,
68
&address_space_memory);
69
}
70
71
-void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState harts,
72
+void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState *harts,
73
hwaddr start_addr,
74
hwaddr rom_base, hwaddr rom_size,
75
uint64_t kernel_entry,
76
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
77
index XXXXXXX..XXXXXXX 100644
52
index XXXXXXX..XXXXXXX 100644
78
--- a/hw/riscv/sifive_u.c
53
--- a/target/riscv/tcg/tcg-cpu.c
79
+++ b/hw/riscv/sifive_u.c
54
+++ b/target/riscv/tcg/tcg-cpu.c
80
@@ -XXX,XX +XXX,XX @@ static void sifive_u_machine_init(MachineState *machine)
55
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
81
56
82
/* create device tree */
57
/* The Zve64d extension depends on the Zve64f extension */
83
create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline,
58
if (cpu->cfg.ext_zve64d) {
84
- riscv_is_32bit(s->soc.u_cpus));
59
+ if (!riscv_has_ext(env, RVD)) {
85
+ riscv_is_32bit(&s->soc.u_cpus));
60
+ error_setg(errp, "Zve64d/V extensions require D extension");
86
61
+ return;
87
if (s->start_in_flash) {
62
+ }
88
/*
63
cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve64f), true);
89
@@ -XXX,XX +XXX,XX @@ static void sifive_u_machine_init(MachineState *machine)
90
break;
91
}
64
}
92
65
93
- if (riscv_is_32bit(s->soc.u_cpus)) {
66
- /* The Zve64f extension depends on the Zve32f extension */
94
+ if (riscv_is_32bit(&s->soc.u_cpus)) {
67
+ /* The Zve64f extension depends on the Zve64x and Zve32f extensions */
95
firmware_end_addr = riscv_find_and_load_firmware(machine,
68
if (cpu->cfg.ext_zve64f) {
96
"opensbi-riscv32-generic-fw_dynamic.bin",
69
+ cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve64x), true);
97
start_addr, NULL);
70
cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve32f), true);
98
@@ -XXX,XX +XXX,XX @@ static void sifive_u_machine_init(MachineState *machine)
99
}
71
}
100
72
101
if (machine->kernel_filename) {
73
- if (cpu->cfg.ext_zve64d && !riscv_has_ext(env, RVD)) {
102
- kernel_start_addr = riscv_calc_kernel_start_addr(s->soc.u_cpus,
74
- error_setg(errp, "Zve64d/V extensions require D extension");
103
+ kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc.u_cpus,
75
- return;
104
firmware_end_addr);
76
+ /* The Zve64x extension depends on the Zve32x extension */
105
77
+ if (cpu->cfg.ext_zve64x) {
106
kernel_entry = riscv_load_kernel(machine->kernel_filename,
78
+ cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve32x), true);
107
@@ -XXX,XX +XXX,XX @@ static void sifive_u_machine_init(MachineState *machine)
108
/* Compute the fdt load address in dram */
109
fdt_load_addr = riscv_load_fdt(memmap[SIFIVE_U_DEV_DRAM].base,
110
machine->ram_size, s->fdt);
111
- if (!riscv_is_32bit(s->soc.u_cpus)) {
112
+ if (!riscv_is_32bit(&s->soc.u_cpus)) {
113
start_addr_hi32 = (uint64_t)start_addr >> 32;
114
}
79
}
115
80
116
@@ -XXX,XX +XXX,XX @@ static void sifive_u_machine_init(MachineState *machine)
81
/* The Zve32f extension depends on the Zve32x extension */
117
0x00000000,
82
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
118
/* fw_dyn: */
83
return;
119
};
120
- if (riscv_is_32bit(s->soc.u_cpus)) {
121
+ if (riscv_is_32bit(&s->soc.u_cpus)) {
122
reset_vec[4] = 0x0202a583; /* lw a1, 32(t0) */
123
reset_vec[5] = 0x0182a283; /* lw t0, 24(t0) */
124
} else {
125
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
126
index XXXXXXX..XXXXXXX 100644
127
--- a/hw/riscv/spike.c
128
+++ b/hw/riscv/spike.c
129
@@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine)
130
131
/* create device tree */
132
create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline,
133
- riscv_is_32bit(s->soc[0]));
134
+ riscv_is_32bit(&s->soc[0]));
135
136
/* boot rom */
137
memory_region_init_rom(mask_rom, NULL, "riscv.spike.mrom",
138
@@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine)
139
* keeping ELF files here was intentional because BIN files don't work
140
* for the Spike machine as HTIF emulation depends on ELF parsing.
141
*/
142
- if (riscv_is_32bit(s->soc[0])) {
143
+ if (riscv_is_32bit(&s->soc[0])) {
144
firmware_end_addr = riscv_find_and_load_firmware(machine,
145
"opensbi-riscv32-generic-fw_dynamic.elf",
146
memmap[SPIKE_DRAM].base,
147
@@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine)
148
}
84
}
149
85
150
if (machine->kernel_filename) {
86
- if ((cpu->cfg.ext_zvbc || cpu->cfg.ext_zvknhb) && !cpu->cfg.ext_zve64f) {
151
- kernel_start_addr = riscv_calc_kernel_start_addr(s->soc[0],
87
+ if ((cpu->cfg.ext_zvbc || cpu->cfg.ext_zvknhb) && !cpu->cfg.ext_zve64x) {
152
+ kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc[0],
88
error_setg(
153
firmware_end_addr);
89
errp,
154
90
- "Zvbc and Zvknhb extensions require V or Zve64{f,d} extensions");
155
kernel_entry = riscv_load_kernel(machine->kernel_filename,
91
+ "Zvbc and Zvknhb extensions require V or Zve64x extensions");
156
@@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine)
92
return;
157
fdt_load_addr = riscv_load_fdt(memmap[SPIKE_DRAM].base,
158
machine->ram_size, s->fdt);
159
/* load the reset vector */
160
- riscv_setup_rom_reset_vec(machine, s->soc[0], memmap[SPIKE_DRAM].base,
161
+ riscv_setup_rom_reset_vec(machine, &s->soc[0], memmap[SPIKE_DRAM].base,
162
memmap[SPIKE_MROM].base,
163
memmap[SPIKE_MROM].size, kernel_entry,
164
fdt_load_addr, s->fdt);
165
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
166
index XXXXXXX..XXXXXXX 100644
167
--- a/hw/riscv/virt.c
168
+++ b/hw/riscv/virt.c
169
@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
170
171
/* create device tree */
172
create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline,
173
- riscv_is_32bit(s->soc[0]));
174
+ riscv_is_32bit(&s->soc[0]));
175
176
/* boot rom */
177
memory_region_init_rom(mask_rom, NULL, "riscv_virt_board.mrom",
178
@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
179
memory_region_add_subregion(system_memory, memmap[VIRT_MROM].base,
180
mask_rom);
181
182
- if (riscv_is_32bit(s->soc[0])) {
183
+ if (riscv_is_32bit(&s->soc[0])) {
184
firmware_end_addr = riscv_find_and_load_firmware(machine,
185
"opensbi-riscv32-generic-fw_dynamic.bin",
186
start_addr, NULL);
187
@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
188
}
93
}
189
94
190
if (machine->kernel_filename) {
191
- kernel_start_addr = riscv_calc_kernel_start_addr(s->soc[0],
192
+ kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc[0],
193
firmware_end_addr);
194
195
kernel_entry = riscv_load_kernel(machine->kernel_filename,
196
@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
197
fdt_load_addr = riscv_load_fdt(memmap[VIRT_DRAM].base,
198
machine->ram_size, s->fdt);
199
/* load the reset vector */
200
- riscv_setup_rom_reset_vec(machine, s->soc[0], start_addr,
201
+ riscv_setup_rom_reset_vec(machine, &s->soc[0], start_addr,
202
virt_memmap[VIRT_MROM].base,
203
virt_memmap[VIRT_MROM].size, kernel_entry,
204
fdt_load_addr, s->fdt);
205
--
95
--
206
2.29.2
96
2.45.1
207
208
diff view generated by jsdifflib
New patch
[PULL 12/28] target/riscv: Relax vector register check in RISCV gdbstub
1
From: Jason Chien <jason.chien@sifive.com>
1
2
3
In current implementation, the gdbstub allows reading vector registers
4
only if V extension is supported. However, all vector extensions and
5
vector crypto extensions have the vector registers and they all depend
6
on Zve32x. The gdbstub should check for Zve32x instead.
7
8
Signed-off-by: Jason Chien <jason.chien@sifive.com>
9
Reviewed-by: Frank Chang <frank.chang@sifive.com>
10
Reviewed-by: Max Chou <max.chou@sifive.com>
11
Message-ID: <20240328022343.6871-4-jason.chien@sifive.com>
12
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
13
---
14
target/riscv/gdbstub.c | 2 +-
15
1 file changed, 1 insertion(+), 1 deletion(-)
16
17
diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
18
index XXXXXXX..XXXXXXX 100644
19
--- a/target/riscv/gdbstub.c
20
+++ b/target/riscv/gdbstub.c
21
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs)
22
gdb_find_static_feature("riscv-32bit-fpu.xml"),
23
0);
24
}
25
- if (env->misa_ext & RVV) {
26
+ if (cpu->cfg.ext_zve32x) {
27
gdb_register_coprocessor(cs, riscv_gdb_get_vector,
28
riscv_gdb_set_vector,
29
ricsv_gen_dynamic_vector_feature(cs, cs->gdb_num_regs),
30
--
31
2.45.1
diff view generated by jsdifflib
New patch
[PULL 13/28] target/riscv: Fix the element agnostic function problem
1
From: Huang Tao <eric.huang@linux.alibaba.com>
1
2
3
In RVV and vcrypto instructions, the masked and tail elements are set to 1s
4
using vext_set_elems_1s function if the vma/vta bit is set. It is the element
5
agnostic policy.
6
7
However, this function can't deal the big endian situation. This patch fixes
8
the problem by adding handling of such case.
9
10
Signed-off-by: Huang Tao <eric.huang@linux.alibaba.com>
11
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
12
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
13
Cc: qemu-stable <qemu-stable@nongnu.org>
14
Message-ID: <20240325021654.6594-1-eric.huang@linux.alibaba.com>
15
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
16
---
17
target/riscv/vector_internals.c | 22 ++++++++++++++++++++++
18
1 file changed, 22 insertions(+)
19
20
diff --git a/target/riscv/vector_internals.c b/target/riscv/vector_internals.c
21
index XXXXXXX..XXXXXXX 100644
22
--- a/target/riscv/vector_internals.c
23
+++ b/target/riscv/vector_internals.c
24
@@ -XXX,XX +XXX,XX @@ void vext_set_elems_1s(void *base, uint32_t is_agnostic, uint32_t cnt,
25
if (tot - cnt == 0) {
26
return ;
27
}
28
+
29
+ if (HOST_BIG_ENDIAN) {
30
+ /*
31
+ * Deal the situation when the elements are insdie
32
+ * only one uint64 block including setting the
33
+ * masked-off element.
34
+ */
35
+ if (((tot - 1) ^ cnt) < 8) {
36
+ memset(base + H1(tot - 1), -1, tot - cnt);
37
+ return;
38
+ }
39
+ /*
40
+ * Otherwise, at least cross two uint64_t blocks.
41
+ * Set first unaligned block.
42
+ */
43
+ if (cnt % 8 != 0) {
44
+ uint32_t j = ROUND_UP(cnt, 8);
45
+ memset(base + H1(j - 1), -1, j - cnt);
46
+ cnt = j;
47
+ }
48
+ /* Set other 64bit aligend blocks */
49
+ }
50
memset(base + cnt, -1, tot - cnt);
51
}
52
53
--
54
2.45.1
diff view generated by jsdifflib
[PULL 03/12] gdb: riscv: Add target description
[PULL 14/28] target/riscv/cpu.c: fix Zvkb extension config
1
From: Sylvain Pelissier <sylvain.pelissier@gmail.com>
1
From: Yangyu Chen <cyy@cyyself.name>
2
2
3
Target description is not currently implemented in RISC-V
3
This code has a typo that writes zvkb to zvkg, causing users can't
4
architecture. Thus GDB won't set it properly when attached.
4
enable zvkb through the config. This patch gets this fixed.
5
The patch implements the target description response.
6
5
7
Signed-off-by: Sylvain Pelissier <sylvain.pelissier@gmail.com>
6
Signed-off-by: Yangyu Chen <cyy@cyyself.name>
8
Reviewed-by: Bin Meng <bin.meng@windriver.com>
7
Fixes: ea61ef7097d0 ("target/riscv: Move vector crypto extensions to riscv_cpu_extensions")
8
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
9
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
9
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
10
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
10
Reviewed-by: Max Chou <max.chou@sifive.com>
11
Message-id: 20210106204141.14027-1-sylvain.pelissier@gmail.com
11
Reviewed-by:  Weiwei Li <liwei1518@gmail.com>
12
Message-ID: <tencent_7E34EEF0F90B9A68BF38BEE09EC6D4877C0A@qq.com>
13
Cc: qemu-stable <qemu-stable@nongnu.org>
12
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
14
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
13
---
15
---
14
target/riscv/cpu.c | 13 +++++++++++++
16
target/riscv/cpu.c | 2 +-
15
1 file changed, 13 insertions(+)
17
1 file changed, 1 insertion(+), 1 deletion(-)
16
18
17
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
19
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
18
index XXXXXXX..XXXXXXX 100644
20
index XXXXXXX..XXXXXXX 100644
19
--- a/target/riscv/cpu.c
21
--- a/target/riscv/cpu.c
20
+++ b/target/riscv/cpu.c
22
+++ b/target/riscv/cpu.c
21
@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_properties[] = {
23
@@ -XXX,XX +XXX,XX @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
22
DEFINE_PROP_END_OF_LIST(),
24
/* Vector cryptography extensions */
23
};
25
MULTI_EXT_CFG_BOOL("zvbb", ext_zvbb, false),
24
26
MULTI_EXT_CFG_BOOL("zvbc", ext_zvbc, false),
25
+static gchar *riscv_gdb_arch_name(CPUState *cs)
27
- MULTI_EXT_CFG_BOOL("zvkb", ext_zvkg, false),
26
+{
28
+ MULTI_EXT_CFG_BOOL("zvkb", ext_zvkb, false),
27
+ RISCVCPU *cpu = RISCV_CPU(cs);
29
MULTI_EXT_CFG_BOOL("zvkg", ext_zvkg, false),
28
+ CPURISCVState *env = &cpu->env;
30
MULTI_EXT_CFG_BOOL("zvkned", ext_zvkned, false),
29
+
31
MULTI_EXT_CFG_BOOL("zvknha", ext_zvknha, false),
30
+ if (riscv_cpu_is_32bit(env)) {
31
+ return g_strdup("riscv:rv32");
32
+ } else {
33
+ return g_strdup("riscv:rv64");
34
+ }
35
+}
36
+
37
static void riscv_cpu_class_init(ObjectClass *c, void *data)
38
{
39
RISCVCPUClass *mcc = RISCV_CPU_CLASS(c);
40
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
41
/* For now, mark unmigratable: */
42
cc->vmsd = &vmstate_riscv_cpu;
43
#endif
44
+ cc->gdb_arch_name = riscv_gdb_arch_name;
45
#ifdef CONFIG_TCG
46
cc->tcg_initialize = riscv_translate_init;
47
cc->tlb_fill = riscv_cpu_tlb_fill;
48
--
32
--
49
2.29.2
33
2.45.1
50
34
51
35
diff view generated by jsdifflib
[PULL 10/12] target/riscv: Generate the GDB XML file for CSR registers dynamically
[PULL 15/28] target/riscv: Implement dynamic establishment of custom decoder
1
From: Bin Meng <bin.meng@windriver.com>
1
From: Huang Tao <eric.huang@linux.alibaba.com>
2
2
3
At present QEMU RISC-V uses a hardcoded XML to report the feature
3
In this patch, we modify the decoder to be a freely composable data
4
"org.gnu.gdb.riscv.csr" [1]. There are two major issues with the
4
structure instead of a hardcoded one. It can be dynamically builded up
5
approach being used currently:
5
according to the extensions.
6
This approach has several benefits:
7
1. Provides support for heterogeneous cpu architectures. As we add decoder in
8
RISCVCPU, each cpu can have their own decoder, and the decoders can be
9
different due to cpu's features.
10
2. Improve the decoding efficiency. We run the guard_func to see if the decoder
11
can be added to the dynamic_decoder when building up the decoder. Therefore,
12
there is no need to run the guard_func when decoding each instruction. It can
13
improve the decoding efficiency
14
3. For vendor or dynamic cpus, it allows them to customize their own decoder
15
functions to improve decoding efficiency, especially when vendor-defined
16
instruction sets increase. Because of dynamic building up, it can skip the other
17
decoder guard functions when decoding.
18
4. Pre patch for allowing adding a vendor decoder before decode_insn32() with minimal
19
overhead for users that don't need this particular vendor decoder.
6
20
7
- The XML does not specify the "regnum" field of a CSR entry, hence
21
Signed-off-by: Huang Tao <eric.huang@linux.alibaba.com>
8
consecutive numbers are used by the remote GDB client to access
22
Suggested-by: Christoph Muellner <christoph.muellner@vrull.eu>
9
CSRs. In QEMU we have to maintain a map table to convert the GDB
23
Co-authored-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
10
number to the hardware number which is error prone.
24
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
11
- The XML contains some CSRs that QEMU does not implement at all,
12
which causes an "E14" response sent to remote GDB client.
13
14
Change to generate the CSR register list dynamically, based on the
15
availability presented in the CSR function table. This new approach
16
will reflect a correct list of CSRs that QEMU actually implements.
17
18
[1] https://sourceware.org/gdb/current/onlinedocs/gdb/RISC_002dV-Features.html#RISC_002dV-Features
19
20
Signed-off-by: Bin Meng <bin.meng@windriver.com>
21
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
25
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
22
Message-id: 20210116054123.5457-2-bmeng.cn@gmail.com
26
Message-ID: <20240506023607.29544-1-eric.huang@linux.alibaba.com>
23
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
27
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
24
---
28
---
25
target/riscv/cpu.h | 2 +
29
target/riscv/cpu.h | 1 +
26
target/riscv/cpu.c | 12 ++
30
target/riscv/tcg/tcg-cpu.h | 15 +++++++++++++++
27
target/riscv/gdbstub.c | 308 ++++++-----------------------------------
31
target/riscv/cpu.c | 1 +
28
3 files changed, 58 insertions(+), 264 deletions(-)
32
target/riscv/tcg/tcg-cpu.c | 15 +++++++++++++++
33
target/riscv/translate.c | 31 +++++++++++++++----------------
34
5 files changed, 47 insertions(+), 16 deletions(-)
29
35
30
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
36
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
31
index XXXXXXX..XXXXXXX 100644
37
index XXXXXXX..XXXXXXX 100644
32
--- a/target/riscv/cpu.h
38
--- a/target/riscv/cpu.h
33
+++ b/target/riscv/cpu.h
39
+++ b/target/riscv/cpu.h
34
@@ -XXX,XX +XXX,XX @@ struct RISCVCPU {
40
@@ -XXX,XX +XXX,XX @@ struct ArchCPU {
35
CPUNegativeOffsetState neg;
41
uint32_t pmu_avail_ctrs;
36
CPURISCVState env;
42
/* Mapping of events to counters */
37
43
GHashTable *pmu_event_ctr_map;
38
+ char *dyn_csr_xml;
44
+ const GPtrArray *decoders;
45
};
46
47
/**
48
diff --git a/target/riscv/tcg/tcg-cpu.h b/target/riscv/tcg/tcg-cpu.h
49
index XXXXXXX..XXXXXXX 100644
50
--- a/target/riscv/tcg/tcg-cpu.h
51
+++ b/target/riscv/tcg/tcg-cpu.h
52
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp);
53
void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error **errp);
54
bool riscv_cpu_tcg_compatible(RISCVCPU *cpu);
55
56
+struct DisasContext;
57
+struct RISCVCPUConfig;
58
+typedef struct RISCVDecoder {
59
+ bool (*guard_func)(const struct RISCVCPUConfig *);
60
+ bool (*riscv_cpu_decode_fn)(struct DisasContext *, uint32_t);
61
+} RISCVDecoder;
39
+
62
+
40
/* Configuration Settings */
63
+typedef bool (*riscv_cpu_decode_fn)(struct DisasContext *, uint32_t);
41
struct {
64
+
42
bool ext_i;
65
+extern const size_t decoder_table_size;
66
+
67
+extern const RISCVDecoder decoder_table[];
68
+
69
+void riscv_tcg_cpu_finalize_dynamic_decoder(RISCVCPU *cpu);
70
+
71
#endif
43
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
72
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
44
index XXXXXXX..XXXXXXX 100644
73
index XXXXXXX..XXXXXXX 100644
45
--- a/target/riscv/cpu.c
74
--- a/target/riscv/cpu.c
46
+++ b/target/riscv/cpu.c
75
+++ b/target/riscv/cpu.c
47
@@ -XXX,XX +XXX,XX @@ static gchar *riscv_gdb_arch_name(CPUState *cs)
76
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_finalize_features(RISCVCPU *cpu, Error **errp)
77
error_propagate(errp, local_err);
78
return;
79
}
80
+ riscv_tcg_cpu_finalize_dynamic_decoder(cpu);
81
} else if (kvm_enabled()) {
82
riscv_kvm_cpu_finalize_features(cpu, &local_err);
83
if (local_err != NULL) {
84
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
85
index XXXXXXX..XXXXXXX 100644
86
--- a/target/riscv/tcg/tcg-cpu.c
87
+++ b/target/riscv/tcg/tcg-cpu.c
88
@@ -XXX,XX +XXX,XX @@ void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error **errp)
48
}
89
}
49
}
90
}
50
91
51
+static const char *riscv_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname)
92
+void riscv_tcg_cpu_finalize_dynamic_decoder(RISCVCPU *cpu)
52
+{
93
+{
53
+ RISCVCPU *cpu = RISCV_CPU(cs);
94
+ GPtrArray *dynamic_decoders;
54
+
95
+ dynamic_decoders = g_ptr_array_sized_new(decoder_table_size);
55
+ if (strcmp(xmlname, "riscv-csr.xml") == 0) {
96
+ for (size_t i = 0; i < decoder_table_size; ++i) {
56
+ return cpu->dyn_csr_xml;
97
+ if (decoder_table[i].guard_func &&
57
+ }
98
+ decoder_table[i].guard_func(&cpu->cfg)) {
58
+
99
+ g_ptr_array_add(dynamic_decoders,
59
+ return NULL;
100
+ (gpointer)decoder_table[i].riscv_cpu_decode_fn);
60
+}
61
+
62
static void riscv_cpu_class_init(ObjectClass *c, void *data)
63
{
64
RISCVCPUClass *mcc = RISCV_CPU_CLASS(c);
65
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
66
cc->vmsd = &vmstate_riscv_cpu;
67
#endif
68
cc->gdb_arch_name = riscv_gdb_arch_name;
69
+ cc->gdb_get_dynamic_xml = riscv_gdb_get_dynamic_xml;
70
#ifdef CONFIG_TCG
71
cc->tcg_initialize = riscv_translate_init;
72
cc->tlb_fill = riscv_cpu_tlb_fill;
73
diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
74
index XXXXXXX..XXXXXXX 100644
75
--- a/target/riscv/gdbstub.c
76
+++ b/target/riscv/gdbstub.c
77
@@ -XXX,XX +XXX,XX @@
78
#include "exec/gdbstub.h"
79
#include "cpu.h"
80
81
-/*
82
- * The GDB CSR xml files list them in documentation order, not numerical order,
83
- * and are missing entries for unnamed CSRs. So we need to map the gdb numbers
84
- * to the hardware numbers.
85
- */
86
-
87
-static int csr_register_map[] = {
88
- CSR_USTATUS,
89
- CSR_UIE,
90
- CSR_UTVEC,
91
- CSR_USCRATCH,
92
- CSR_UEPC,
93
- CSR_UCAUSE,
94
- CSR_UTVAL,
95
- CSR_UIP,
96
- CSR_FFLAGS,
97
- CSR_FRM,
98
- CSR_FCSR,
99
- CSR_CYCLE,
100
- CSR_TIME,
101
- CSR_INSTRET,
102
- CSR_HPMCOUNTER3,
103
- CSR_HPMCOUNTER4,
104
- CSR_HPMCOUNTER5,
105
- CSR_HPMCOUNTER6,
106
- CSR_HPMCOUNTER7,
107
- CSR_HPMCOUNTER8,
108
- CSR_HPMCOUNTER9,
109
- CSR_HPMCOUNTER10,
110
- CSR_HPMCOUNTER11,
111
- CSR_HPMCOUNTER12,
112
- CSR_HPMCOUNTER13,
113
- CSR_HPMCOUNTER14,
114
- CSR_HPMCOUNTER15,
115
- CSR_HPMCOUNTER16,
116
- CSR_HPMCOUNTER17,
117
- CSR_HPMCOUNTER18,
118
- CSR_HPMCOUNTER19,
119
- CSR_HPMCOUNTER20,
120
- CSR_HPMCOUNTER21,
121
- CSR_HPMCOUNTER22,
122
- CSR_HPMCOUNTER23,
123
- CSR_HPMCOUNTER24,
124
- CSR_HPMCOUNTER25,
125
- CSR_HPMCOUNTER26,
126
- CSR_HPMCOUNTER27,
127
- CSR_HPMCOUNTER28,
128
- CSR_HPMCOUNTER29,
129
- CSR_HPMCOUNTER30,
130
- CSR_HPMCOUNTER31,
131
- CSR_CYCLEH,
132
- CSR_TIMEH,
133
- CSR_INSTRETH,
134
- CSR_HPMCOUNTER3H,
135
- CSR_HPMCOUNTER4H,
136
- CSR_HPMCOUNTER5H,
137
- CSR_HPMCOUNTER6H,
138
- CSR_HPMCOUNTER7H,
139
- CSR_HPMCOUNTER8H,
140
- CSR_HPMCOUNTER9H,
141
- CSR_HPMCOUNTER10H,
142
- CSR_HPMCOUNTER11H,
143
- CSR_HPMCOUNTER12H,
144
- CSR_HPMCOUNTER13H,
145
- CSR_HPMCOUNTER14H,
146
- CSR_HPMCOUNTER15H,
147
- CSR_HPMCOUNTER16H,
148
- CSR_HPMCOUNTER17H,
149
- CSR_HPMCOUNTER18H,
150
- CSR_HPMCOUNTER19H,
151
- CSR_HPMCOUNTER20H,
152
- CSR_HPMCOUNTER21H,
153
- CSR_HPMCOUNTER22H,
154
- CSR_HPMCOUNTER23H,
155
- CSR_HPMCOUNTER24H,
156
- CSR_HPMCOUNTER25H,
157
- CSR_HPMCOUNTER26H,
158
- CSR_HPMCOUNTER27H,
159
- CSR_HPMCOUNTER28H,
160
- CSR_HPMCOUNTER29H,
161
- CSR_HPMCOUNTER30H,
162
- CSR_HPMCOUNTER31H,
163
- CSR_SSTATUS,
164
- CSR_SEDELEG,
165
- CSR_SIDELEG,
166
- CSR_SIE,
167
- CSR_STVEC,
168
- CSR_SCOUNTEREN,
169
- CSR_SSCRATCH,
170
- CSR_SEPC,
171
- CSR_SCAUSE,
172
- CSR_STVAL,
173
- CSR_SIP,
174
- CSR_SATP,
175
- CSR_MVENDORID,
176
- CSR_MARCHID,
177
- CSR_MIMPID,
178
- CSR_MHARTID,
179
- CSR_MSTATUS,
180
- CSR_MISA,
181
- CSR_MEDELEG,
182
- CSR_MIDELEG,
183
- CSR_MIE,
184
- CSR_MTVEC,
185
- CSR_MCOUNTEREN,
186
- CSR_MSCRATCH,
187
- CSR_MEPC,
188
- CSR_MCAUSE,
189
- CSR_MTVAL,
190
- CSR_MIP,
191
- CSR_MTINST,
192
- CSR_MTVAL2,
193
- CSR_PMPCFG0,
194
- CSR_PMPCFG1,
195
- CSR_PMPCFG2,
196
- CSR_PMPCFG3,
197
- CSR_PMPADDR0,
198
- CSR_PMPADDR1,
199
- CSR_PMPADDR2,
200
- CSR_PMPADDR3,
201
- CSR_PMPADDR4,
202
- CSR_PMPADDR5,
203
- CSR_PMPADDR6,
204
- CSR_PMPADDR7,
205
- CSR_PMPADDR8,
206
- CSR_PMPADDR9,
207
- CSR_PMPADDR10,
208
- CSR_PMPADDR11,
209
- CSR_PMPADDR12,
210
- CSR_PMPADDR13,
211
- CSR_PMPADDR14,
212
- CSR_PMPADDR15,
213
- CSR_MCYCLE,
214
- CSR_MINSTRET,
215
- CSR_MHPMCOUNTER3,
216
- CSR_MHPMCOUNTER4,
217
- CSR_MHPMCOUNTER5,
218
- CSR_MHPMCOUNTER6,
219
- CSR_MHPMCOUNTER7,
220
- CSR_MHPMCOUNTER8,
221
- CSR_MHPMCOUNTER9,
222
- CSR_MHPMCOUNTER10,
223
- CSR_MHPMCOUNTER11,
224
- CSR_MHPMCOUNTER12,
225
- CSR_MHPMCOUNTER13,
226
- CSR_MHPMCOUNTER14,
227
- CSR_MHPMCOUNTER15,
228
- CSR_MHPMCOUNTER16,
229
- CSR_MHPMCOUNTER17,
230
- CSR_MHPMCOUNTER18,
231
- CSR_MHPMCOUNTER19,
232
- CSR_MHPMCOUNTER20,
233
- CSR_MHPMCOUNTER21,
234
- CSR_MHPMCOUNTER22,
235
- CSR_MHPMCOUNTER23,
236
- CSR_MHPMCOUNTER24,
237
- CSR_MHPMCOUNTER25,
238
- CSR_MHPMCOUNTER26,
239
- CSR_MHPMCOUNTER27,
240
- CSR_MHPMCOUNTER28,
241
- CSR_MHPMCOUNTER29,
242
- CSR_MHPMCOUNTER30,
243
- CSR_MHPMCOUNTER31,
244
- CSR_MCYCLEH,
245
- CSR_MINSTRETH,
246
- CSR_MHPMCOUNTER3H,
247
- CSR_MHPMCOUNTER4H,
248
- CSR_MHPMCOUNTER5H,
249
- CSR_MHPMCOUNTER6H,
250
- CSR_MHPMCOUNTER7H,
251
- CSR_MHPMCOUNTER8H,
252
- CSR_MHPMCOUNTER9H,
253
- CSR_MHPMCOUNTER10H,
254
- CSR_MHPMCOUNTER11H,
255
- CSR_MHPMCOUNTER12H,
256
- CSR_MHPMCOUNTER13H,
257
- CSR_MHPMCOUNTER14H,
258
- CSR_MHPMCOUNTER15H,
259
- CSR_MHPMCOUNTER16H,
260
- CSR_MHPMCOUNTER17H,
261
- CSR_MHPMCOUNTER18H,
262
- CSR_MHPMCOUNTER19H,
263
- CSR_MHPMCOUNTER20H,
264
- CSR_MHPMCOUNTER21H,
265
- CSR_MHPMCOUNTER22H,
266
- CSR_MHPMCOUNTER23H,
267
- CSR_MHPMCOUNTER24H,
268
- CSR_MHPMCOUNTER25H,
269
- CSR_MHPMCOUNTER26H,
270
- CSR_MHPMCOUNTER27H,
271
- CSR_MHPMCOUNTER28H,
272
- CSR_MHPMCOUNTER29H,
273
- CSR_MHPMCOUNTER30H,
274
- CSR_MHPMCOUNTER31H,
275
- CSR_MHPMEVENT3,
276
- CSR_MHPMEVENT4,
277
- CSR_MHPMEVENT5,
278
- CSR_MHPMEVENT6,
279
- CSR_MHPMEVENT7,
280
- CSR_MHPMEVENT8,
281
- CSR_MHPMEVENT9,
282
- CSR_MHPMEVENT10,
283
- CSR_MHPMEVENT11,
284
- CSR_MHPMEVENT12,
285
- CSR_MHPMEVENT13,
286
- CSR_MHPMEVENT14,
287
- CSR_MHPMEVENT15,
288
- CSR_MHPMEVENT16,
289
- CSR_MHPMEVENT17,
290
- CSR_MHPMEVENT18,
291
- CSR_MHPMEVENT19,
292
- CSR_MHPMEVENT20,
293
- CSR_MHPMEVENT21,
294
- CSR_MHPMEVENT22,
295
- CSR_MHPMEVENT23,
296
- CSR_MHPMEVENT24,
297
- CSR_MHPMEVENT25,
298
- CSR_MHPMEVENT26,
299
- CSR_MHPMEVENT27,
300
- CSR_MHPMEVENT28,
301
- CSR_MHPMEVENT29,
302
- CSR_MHPMEVENT30,
303
- CSR_MHPMEVENT31,
304
- CSR_TSELECT,
305
- CSR_TDATA1,
306
- CSR_TDATA2,
307
- CSR_TDATA3,
308
- CSR_DCSR,
309
- CSR_DPC,
310
- CSR_DSCRATCH,
311
- CSR_HSTATUS,
312
- CSR_HEDELEG,
313
- CSR_HIDELEG,
314
- CSR_HIE,
315
- CSR_HCOUNTEREN,
316
- CSR_HTVAL,
317
- CSR_HIP,
318
- CSR_HTINST,
319
- CSR_HGATP,
320
- CSR_MBASE,
321
- CSR_MBOUND,
322
- CSR_MIBASE,
323
- CSR_MIBOUND,
324
- CSR_MDBASE,
325
- CSR_MDBOUND,
326
- CSR_MUCOUNTEREN,
327
- CSR_MSCOUNTEREN,
328
- CSR_MHCOUNTEREN,
329
-};
330
-
331
int riscv_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
332
{
333
RISCVCPU *cpu = RISCV_CPU(cs);
334
@@ -XXX,XX +XXX,XX @@ static int riscv_gdb_get_fpu(CPURISCVState *env, GByteArray *buf, int n)
335
target_ulong val = 0;
336
int result;
337
/*
338
- * CSR_FFLAGS is at index 8 in csr_register, and gdb says it is FP
339
+ * CSR_FFLAGS is at index 1 in csr_register, and gdb says it is FP
340
* register 33, so we recalculate the map index.
341
* This also works for CSR_FRM and CSR_FCSR.
342
*/
343
- result = riscv_csrrw_debug(env, n - 33 + csr_register_map[8], &val,
344
+ result = riscv_csrrw_debug(env, n - 32, &val,
345
0, 0);
346
if (result == 0) {
347
return gdb_get_regl(buf, val);
348
@@ -XXX,XX +XXX,XX @@ static int riscv_gdb_set_fpu(CPURISCVState *env, uint8_t *mem_buf, int n)
349
target_ulong val = ldtul_p(mem_buf);
350
int result;
351
/*
352
- * CSR_FFLAGS is at index 8 in csr_register, and gdb says it is FP
353
+ * CSR_FFLAGS is at index 1 in csr_register, and gdb says it is FP
354
* register 33, so we recalculate the map index.
355
* This also works for CSR_FRM and CSR_FCSR.
356
*/
357
- result = riscv_csrrw_debug(env, n - 33 + csr_register_map[8], NULL,
358
+ result = riscv_csrrw_debug(env, n - 32, NULL,
359
val, -1);
360
if (result == 0) {
361
return sizeof(target_ulong);
362
@@ -XXX,XX +XXX,XX @@ static int riscv_gdb_set_fpu(CPURISCVState *env, uint8_t *mem_buf, int n)
363
364
static int riscv_gdb_get_csr(CPURISCVState *env, GByteArray *buf, int n)
365
{
366
- if (n < ARRAY_SIZE(csr_register_map)) {
367
+ if (n < CSR_TABLE_SIZE) {
368
target_ulong val = 0;
369
int result;
370
371
- result = riscv_csrrw_debug(env, csr_register_map[n], &val, 0, 0);
372
+ result = riscv_csrrw_debug(env, n, &val, 0, 0);
373
if (result == 0) {
374
return gdb_get_regl(buf, val);
375
}
376
@@ -XXX,XX +XXX,XX @@ static int riscv_gdb_get_csr(CPURISCVState *env, GByteArray *buf, int n)
377
378
static int riscv_gdb_set_csr(CPURISCVState *env, uint8_t *mem_buf, int n)
379
{
380
- if (n < ARRAY_SIZE(csr_register_map)) {
381
+ if (n < CSR_TABLE_SIZE) {
382
target_ulong val = ldtul_p(mem_buf);
383
int result;
384
385
- result = riscv_csrrw_debug(env, csr_register_map[n], NULL, val, -1);
386
+ result = riscv_csrrw_debug(env, n, NULL, val, -1);
387
if (result == 0) {
388
return sizeof(target_ulong);
389
}
390
@@ -XXX,XX +XXX,XX @@ static int riscv_gdb_set_virtual(CPURISCVState *cs, uint8_t *mem_buf, int n)
391
return 0;
392
}
393
394
+static int riscv_gen_dynamic_csr_xml(CPUState *cs, int base_reg)
395
+{
396
+ RISCVCPU *cpu = RISCV_CPU(cs);
397
+ CPURISCVState *env = &cpu->env;
398
+ GString *s = g_string_new(NULL);
399
+ riscv_csr_predicate_fn predicate;
400
+ int bitsize = riscv_cpu_is_32bit(env) ? 32 : 64;
401
+ int i;
402
+
403
+ g_string_printf(s, "<?xml version=\"1.0\"?>");
404
+ g_string_append_printf(s, "<!DOCTYPE feature SYSTEM \"gdb-target.dtd\">");
405
+ g_string_append_printf(s, "<feature name=\"org.gnu.gdb.riscv.csr\">");
406
+
407
+ for (i = 0; i < CSR_TABLE_SIZE; i++) {
408
+ predicate = csr_ops[i].predicate;
409
+ if (predicate && !predicate(env, i)) {
410
+ if (csr_ops[i].name) {
411
+ g_string_append_printf(s, "<reg name=\"%s\"", csr_ops[i].name);
412
+ } else {
413
+ g_string_append_printf(s, "<reg name=\"csr%03x\"", i);
414
+ }
415
+ g_string_append_printf(s, " bitsize=\"%d\"", bitsize);
416
+ g_string_append_printf(s, " regnum=\"%d\"/>", base_reg + i);
417
+ }
101
+ }
418
+ }
102
+ }
419
+
103
+
420
+ g_string_append_printf(s, "</feature>");
104
+ cpu->decoders = dynamic_decoders;
421
+
422
+ cpu->dyn_csr_xml = g_string_free(s, false);
423
+ return CSR_TABLE_SIZE;
424
+}
105
+}
425
+
106
+
426
void riscv_cpu_register_gdb_regs_for_features(CPUState *cs)
107
bool riscv_cpu_tcg_compatible(RISCVCPU *cpu)
427
{
108
{
428
RISCVCPU *cpu = RISCV_CPU(cs);
109
return object_dynamic_cast(OBJECT(cpu), TYPE_RISCV_CPU_HOST) == NULL;
429
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs)
110
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
430
36, "riscv-32bit-fpu.xml", 0);
111
index XXXXXXX..XXXXXXX 100644
431
}
112
--- a/target/riscv/translate.c
432
#if defined(TARGET_RISCV32)
113
+++ b/target/riscv/translate.c
433
- gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr,
114
@@ -XXX,XX +XXX,XX @@
434
- 240, "riscv-32bit-csr.xml", 0);
115
#include "exec/helper-info.c.inc"
116
#undef HELPER_H
117
118
+#include "tcg/tcg-cpu.h"
119
+
120
/* global register indices */
121
static TCGv cpu_gpr[32], cpu_gprh[32], cpu_pc, cpu_vl, cpu_vstart;
122
static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */
123
@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
124
/* FRM is known to contain a valid value. */
125
bool frm_valid;
126
bool insn_start_updated;
127
+ const GPtrArray *decoders;
128
} DisasContext;
129
130
static inline bool has_ext(DisasContext *ctx, uint32_t ext)
131
@@ -XXX,XX +XXX,XX @@ static inline int insn_len(uint16_t first_word)
132
return (first_word & 3) == 3 ? 4 : 2;
133
}
134
135
+const RISCVDecoder decoder_table[] = {
136
+ { always_true_p, decode_insn32 },
137
+ { has_xthead_p, decode_xthead},
138
+ { has_XVentanaCondOps_p, decode_XVentanaCodeOps},
139
+};
140
+
141
+const size_t decoder_table_size = ARRAY_SIZE(decoder_table);
142
+
143
static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
144
{
145
- /*
146
- * A table with predicate (i.e., guard) functions and decoder functions
147
- * that are tested in-order until a decoder matches onto the opcode.
148
- */
149
- static const struct {
150
- bool (*guard_func)(const RISCVCPUConfig *);
151
- bool (*decode_func)(DisasContext *, uint32_t);
152
- } decoders[] = {
153
- { always_true_p, decode_insn32 },
154
- { has_xthead_p, decode_xthead },
155
- { has_XVentanaCondOps_p, decode_XVentanaCodeOps },
156
- };
435
-
157
-
436
gdb_register_coprocessor(cs, riscv_gdb_get_virtual, riscv_gdb_set_virtual,
158
ctx->virt_inst_excp = false;
437
1, "riscv-32bit-virtual.xml", 0);
159
ctx->cur_insn_len = insn_len(opcode);
438
#elif defined(TARGET_RISCV64)
160
/* Check for compressed insn */
439
- gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr,
161
@@ -XXX,XX +XXX,XX @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
440
- 240, "riscv-64bit-csr.xml", 0);
162
ctx->base.pc_next + 2));
441
-
163
ctx->opcode = opcode32;
442
gdb_register_coprocessor(cs, riscv_gdb_get_virtual, riscv_gdb_set_virtual,
164
443
1, "riscv-64bit-virtual.xml", 0);
165
- for (size_t i = 0; i < ARRAY_SIZE(decoders); ++i) {
444
#endif
166
- if (decoders[i].guard_func(ctx->cfg_ptr) &&
445
+
167
- decoders[i].decode_func(ctx, opcode32)) {
446
+ gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr,
168
+ for (guint i = 0; i < ctx->decoders->len; ++i) {
447
+ riscv_gen_dynamic_csr_xml(cs, cs->gdb_num_regs),
169
+ riscv_cpu_decode_fn func = g_ptr_array_index(ctx->decoders, i);
448
+ "riscv-csr.xml", 0);
170
+ if (func(ctx, opcode32)) {
171
return;
172
}
173
}
174
@@ -XXX,XX +XXX,XX @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
175
ctx->itrigger = FIELD_EX32(tb_flags, TB_FLAGS, ITRIGGER);
176
ctx->zero = tcg_constant_tl(0);
177
ctx->virt_inst_excp = false;
178
+ ctx->decoders = cpu->decoders;
449
}
179
}
180
181
static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu)
450
--
182
--
451
2.29.2
183
2.45.1
452
453
diff view generated by jsdifflib
[PULL 02/12] hw/block: m25p80: Implement AAI-WP command support for SST flashes
[PULL 16/28] riscv: thead: Add th.sxstatus CSR emulation
1
From: Xuzhou Cheng <xuzhou.cheng@windriver.com>
1
From: Christoph Müllner <christoph.muellner@vrull.eu>
2
2
3
Auto Address Increment (AAI) Word-Program is a special command of
3
The th.sxstatus CSR can be used to identify available custom extension
4
SST flashes. AAI-WP allows multiple bytes of data to be programmed
4
on T-Head CPUs. The CSR is documented here:
5
without re-issuing the next sequential address location.
5
https://github.com/T-head-Semi/thead-extension-spec/blob/master/xtheadsxstatus.adoc
6
6
7
Signed-off-by: Xuzhou Cheng <xuzhou.cheng@windriver.com>
7
An important property of this patch is, that the th.sxstatus MAEE field
8
Signed-off-by: Bin Meng <bin.meng@windriver.com>
8
is not set (indicating that XTheadMae is not available).
9
Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
9
XTheadMae is a memory attribute extension (similar to Svpbmt) which is
10
Message-id: 1608688825-81519-2-git-send-email-bmeng.cn@gmail.com
10
implemented in many T-Head CPUs (C906, C910, etc.) and utilizes bits
11
in PTEs that are marked as reserved. QEMU maintainers prefer to not
12
implement XTheadMae, so we need give kernels a mechanism to identify
13
if XTheadMae is available in a system or not. And this patch introduces
14
this mechanism in QEMU in a way that's compatible with real HW
15
(i.e., probing the th.sxstatus.MAEE bit).
16
17
Further context can be found on the list:
18
https://lists.gnu.org/archive/html/qemu-devel/2024-02/msg00775.html
19
20
Reviewed-by: LIU Zhiwei <zhiwe_liu@linux.alibaba.com>
21
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
22
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
23
Message-ID: <20240429073656.2486732-1-christoph.muellner@vrull.eu>
11
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
24
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
12
---
25
---
13
hw/block/m25p80.c | 73 +++++++++++++++++++++++++++++++++++++++++++++++
26
MAINTAINERS | 1 +
14
1 file changed, 73 insertions(+)
27
target/riscv/cpu.h | 3 ++
28
target/riscv/cpu.c | 1 +
29
target/riscv/th_csr.c | 79 ++++++++++++++++++++++++++++++++++++++++
30
target/riscv/meson.build | 1 +
31
5 files changed, 85 insertions(+)
32
create mode 100644 target/riscv/th_csr.c
15
33
16
diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
34
diff --git a/MAINTAINERS b/MAINTAINERS
17
index XXXXXXX..XXXXXXX 100644
35
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/block/m25p80.c
36
--- a/MAINTAINERS
19
+++ b/hw/block/m25p80.c
37
+++ b/MAINTAINERS
20
@@ -XXX,XX +XXX,XX @@ typedef enum {
38
@@ -XXX,XX +XXX,XX @@ L: qemu-riscv@nongnu.org
21
QPP_4 = 0x34,
39
S: Supported
22
RDID_90 = 0x90,
40
F: target/riscv/insn_trans/trans_xthead.c.inc
23
RDID_AB = 0xab,
41
F: target/riscv/xthead*.decode
24
+ AAI_WP = 0xad,
42
+F: target/riscv/th_*
25
43
F: disas/riscv-xthead*
26
ERASE_4K = 0x20,
44
27
ERASE4_4K = 0x21,
45
RISC-V XVentanaCondOps extension
28
@@ -XXX,XX +XXX,XX @@ struct Flash {
46
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
29
bool four_bytes_address_mode;
47
index XXXXXXX..XXXXXXX 100644
30
bool reset_enable;
48
--- a/target/riscv/cpu.h
31
bool quad_enable;
49
+++ b/target/riscv/cpu.h
32
+ bool aai_enable;
50
@@ -XXX,XX +XXX,XX @@ target_ulong riscv_new_csr_seed(target_ulong new_value,
33
uint8_t ear;
51
uint8_t satp_mode_max_from_map(uint32_t map);
34
52
const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit);
35
int64_t dirty_page;
53
36
@@ -XXX,XX +XXX,XX @@ static void complete_collecting_data(Flash *s)
54
+/* Implemented in th_csr.c */
37
case PP4_4:
55
+void th_register_custom_csrs(RISCVCPU *cpu);
38
s->state = STATE_PAGE_PROGRAM;
56
+
39
break;
57
#endif /* RISCV_CPU_H */
40
+ case AAI_WP:
58
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
41
+ /* AAI programming starts from the even address */
59
index XXXXXXX..XXXXXXX 100644
42
+ s->cur_addr &= ~BIT(0);
60
--- a/target/riscv/cpu.c
43
+ s->state = STATE_PAGE_PROGRAM;
61
+++ b/target/riscv/cpu.c
44
+ break;
62
@@ -XXX,XX +XXX,XX @@ static void rv64_thead_c906_cpu_init(Object *obj)
45
case READ:
63
cpu->cfg.mvendorid = THEAD_VENDOR_ID;
46
case READ4:
64
#ifndef CONFIG_USER_ONLY
47
case FAST_READ:
65
set_satp_mode_max_supported(cpu, VM_1_10_SV39);
48
@@ -XXX,XX +XXX,XX @@ static void reset_memory(Flash *s)
66
+ th_register_custom_csrs(cpu);
49
s->write_enable = false;
67
#endif
50
s->reset_enable = false;
68
51
s->quad_enable = false;
69
/* inherited from parent obj via riscv_cpu_init() */
52
+ s->aai_enable = false;
70
diff --git a/target/riscv/th_csr.c b/target/riscv/th_csr.c
53
71
new file mode 100644
54
switch (get_man(s)) {
72
index XXXXXXX..XXXXXXX
55
case MAN_NUMONYX:
73
--- /dev/null
56
@@ -XXX,XX +XXX,XX @@ static void decode_qio_read_cmd(Flash *s)
74
+++ b/target/riscv/th_csr.c
57
s->state = STATE_COLLECTING_DATA;
75
@@ -XXX,XX +XXX,XX @@
58
}
76
+/*
59
77
+ * T-Head-specific CSRs.
60
+static bool is_valid_aai_cmd(uint32_t cmd)
78
+ *
79
+ * Copyright (c) 2024 VRULL GmbH
80
+ *
81
+ * This program is free software; you can redistribute it and/or modify it
82
+ * under the terms and conditions of the GNU General Public License,
83
+ * version 2 or later, as published by the Free Software Foundation.
84
+ *
85
+ * This program is distributed in the hope it will be useful, but WITHOUT
86
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
87
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
88
+ * more details.
89
+ *
90
+ * You should have received a copy of the GNU General Public License along with
91
+ * this program. If not, see <http://www.gnu.org/licenses/>.
92
+ */
93
+
94
+#include "qemu/osdep.h"
95
+#include "cpu.h"
96
+#include "cpu_vendorid.h"
97
+
98
+#define CSR_TH_SXSTATUS 0x5c0
99
+
100
+/* TH_SXSTATUS bits */
101
+#define TH_SXSTATUS_UCME BIT(16)
102
+#define TH_SXSTATUS_MAEE BIT(21)
103
+#define TH_SXSTATUS_THEADISAEE BIT(22)
104
+
105
+typedef struct {
106
+ int csrno;
107
+ int (*insertion_test)(RISCVCPU *cpu);
108
+ riscv_csr_operations csr_ops;
109
+} riscv_csr;
110
+
111
+static RISCVException smode(CPURISCVState *env, int csrno)
61
+{
112
+{
62
+ return cmd == AAI_WP || cmd == WRDI || cmd == RDSR;
113
+ if (riscv_has_ext(env, RVS)) {
114
+ return RISCV_EXCP_NONE;
115
+ }
116
+
117
+ return RISCV_EXCP_ILLEGAL_INST;
63
+}
118
+}
64
+
119
+
65
static void decode_new_cmd(Flash *s, uint32_t value)
120
+static int test_thead_mvendorid(RISCVCPU *cpu)
66
{
121
+{
67
int i;
122
+ if (cpu->cfg.mvendorid != THEAD_VENDOR_ID) {
68
@@ -XXX,XX +XXX,XX @@ static void decode_new_cmd(Flash *s, uint32_t value)
123
+ return -1;
69
s->reset_enable = false;
70
}
71
72
+ if (get_man(s) == MAN_SST && s->aai_enable && !is_valid_aai_cmd(value)) {
73
+ qemu_log_mask(LOG_GUEST_ERROR,
74
+ "M25P80: Invalid cmd within AAI programming sequence");
75
+ }
124
+ }
76
+
125
+
77
switch (value) {
126
+ return 0;
78
79
case ERASE_4K:
80
@@ -XXX,XX +XXX,XX @@ static void decode_new_cmd(Flash *s, uint32_t value)
81
82
case WRDI:
83
s->write_enable = false;
84
+ if (get_man(s) == MAN_SST) {
85
+ s->aai_enable = false;
86
+ }
87
break;
88
case WREN:
89
s->write_enable = true;
90
@@ -XXX,XX +XXX,XX @@ static void decode_new_cmd(Flash *s, uint32_t value)
91
if (get_man(s) == MAN_MACRONIX) {
92
s->data[0] |= (!!s->quad_enable) << 6;
93
}
94
+ if (get_man(s) == MAN_SST) {
95
+ s->data[0] |= (!!s->aai_enable) << 6;
96
+ }
97
+
98
s->pos = 0;
99
s->len = 1;
100
s->data_read_loop = true;
101
@@ -XXX,XX +XXX,XX @@ static void decode_new_cmd(Flash *s, uint32_t value)
102
case RSTQIO:
103
s->quad_enable = false;
104
break;
105
+ case AAI_WP:
106
+ if (get_man(s) == MAN_SST) {
107
+ if (s->write_enable) {
108
+ if (s->aai_enable) {
109
+ s->state = STATE_PAGE_PROGRAM;
110
+ } else {
111
+ s->aai_enable = true;
112
+ s->needed_bytes = get_addr_length(s);
113
+ s->state = STATE_COLLECTING_DATA;
114
+ }
115
+ } else {
116
+ qemu_log_mask(LOG_GUEST_ERROR,
117
+ "M25P80: AAI_WP with write protect\n");
118
+ }
119
+ } else {
120
+ qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Unknown cmd %x\n", value);
121
+ }
122
+ break;
123
default:
124
s->pos = 0;
125
s->len = 1;
126
@@ -XXX,XX +XXX,XX @@ static uint32_t m25p80_transfer8(SSIPeripheral *ss, uint32_t tx)
127
trace_m25p80_page_program(s, s->cur_addr, (uint8_t)tx);
128
flash_write8(s, s->cur_addr, (uint8_t)tx);
129
s->cur_addr = (s->cur_addr + 1) & (s->size - 1);
130
+
131
+ if (get_man(s) == MAN_SST && s->aai_enable && s->cur_addr == 0) {
132
+ /*
133
+ * There is no wrap mode during AAI programming once the highest
134
+ * unprotected memory address is reached. The Write-Enable-Latch
135
+ * bit is automatically reset, and AAI programming mode aborts.
136
+ */
137
+ s->write_enable = false;
138
+ s->aai_enable = false;
139
+ }
140
+
141
break;
142
143
case STATE_READ:
144
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_m25p80_data_read_loop = {
145
}
146
};
147
148
+static bool m25p80_aai_enable_needed(void *opaque)
149
+{
150
+ Flash *s = (Flash *)opaque;
151
+
152
+ return s->aai_enable;
153
+}
127
+}
154
+
128
+
155
+static const VMStateDescription vmstate_m25p80_aai_enable = {
129
+static RISCVException read_th_sxstatus(CPURISCVState *env, int csrno,
156
+ .name = "m25p80/aai_enable",
130
+ target_ulong *val)
157
+ .version_id = 1,
131
+{
158
+ .minimum_version_id = 1,
132
+ /* We don't set MAEE here, because QEMU does not implement MAEE. */
159
+ .needed = m25p80_aai_enable_needed,
133
+ *val = TH_SXSTATUS_UCME | TH_SXSTATUS_THEADISAEE;
160
+ .fields = (VMStateField[]) {
134
+ return RISCV_EXCP_NONE;
161
+ VMSTATE_BOOL(aai_enable, Flash),
135
+}
162
+ VMSTATE_END_OF_LIST()
136
+
137
+static riscv_csr th_csr_list[] = {
138
+ {
139
+ .csrno = CSR_TH_SXSTATUS,
140
+ .insertion_test = test_thead_mvendorid,
141
+ .csr_ops = { "th.sxstatus", smode, read_th_sxstatus }
163
+ }
142
+ }
164
+};
143
+};
165
+
144
+
166
static const VMStateDescription vmstate_m25p80 = {
145
+void th_register_custom_csrs(RISCVCPU *cpu)
167
.name = "m25p80",
146
+{
168
.version_id = 0,
147
+ for (size_t i = 0; i < ARRAY_SIZE(th_csr_list); i++) {
169
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_m25p80 = {
148
+ int csrno = th_csr_list[i].csrno;
170
},
149
+ riscv_csr_operations *csr_ops = &th_csr_list[i].csr_ops;
171
.subsections = (const VMStateDescription * []) {
150
+ if (!th_csr_list[i].insertion_test(cpu)) {
172
&vmstate_m25p80_data_read_loop,
151
+ riscv_set_csr_ops(csrno, csr_ops);
173
+ &vmstate_m25p80_aai_enable,
152
+ }
174
NULL
153
+ }
175
}
154
+}
176
};
155
diff --git a/target/riscv/meson.build b/target/riscv/meson.build
156
index XXXXXXX..XXXXXXX 100644
157
--- a/target/riscv/meson.build
158
+++ b/target/riscv/meson.build
159
@@ -XXX,XX +XXX,XX @@ riscv_system_ss.add(files(
160
'monitor.c',
161
'machine.c',
162
'pmu.c',
163
+ 'th_csr.c',
164
'time_helper.c',
165
'riscv-qmp-cmds.c',
166
))
177
--
167
--
178
2.29.2
168
2.45.1
179
169
180
170
diff view generated by jsdifflib
New patch
[PULL 17/28] target/riscv: rvv: Fix Zvfhmin checking for vfwcvt.f.f.v and vfncvt.f.f.w instructions
1
From: Max Chou <max.chou@sifive.com>
1
2
3
According v spec 18.4, only the vfwcvt.f.f.v and vfncvt.f.f.w
4
instructions will be affected by Zvfhmin extension.
5
And the vfwcvt.f.f.v and vfncvt.f.f.w instructions only support the
6
conversions of
7
8
* From 1*SEW(16/32) to 2*SEW(32/64)
9
* From 2*SEW(32/64) to 1*SEW(16/32)
10
11
Signed-off-by: Max Chou <max.chou@sifive.com>
12
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
13
Cc: qemu-stable <qemu-stable@nongnu.org>
14
Message-ID: <20240322092600.1198921-2-max.chou@sifive.com>
15
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
16
---
17
target/riscv/insn_trans/trans_rvv.c.inc | 20 ++++++++++++++++++--
18
1 file changed, 18 insertions(+), 2 deletions(-)
19
20
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
21
index XXXXXXX..XXXXXXX 100644
22
--- a/target/riscv/insn_trans/trans_rvv.c.inc
23
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
24
@@ -XXX,XX +XXX,XX @@ static bool require_rvf(DisasContext *s)
25
}
26
}
27
28
+static bool require_rvfmin(DisasContext *s)
29
+{
30
+ if (s->mstatus_fs == EXT_STATUS_DISABLED) {
31
+ return false;
32
+ }
33
+
34
+ switch (s->sew) {
35
+ case MO_16:
36
+ return s->cfg_ptr->ext_zvfhmin;
37
+ case MO_32:
38
+ return s->cfg_ptr->ext_zve32f;
39
+ default:
40
+ return false;
41
+ }
42
+}
43
+
44
static bool require_scale_rvf(DisasContext *s)
45
{
46
if (s->mstatus_fs == EXT_STATUS_DISABLED) {
47
@@ -XXX,XX +XXX,XX @@ static bool require_scale_rvfmin(DisasContext *s)
48
}
49
50
switch (s->sew) {
51
- case MO_8:
52
- return s->cfg_ptr->ext_zvfhmin;
53
case MO_16:
54
return s->cfg_ptr->ext_zve32f;
55
case MO_32:
56
@@ -XXX,XX +XXX,XX @@ static bool opxfv_widen_check(DisasContext *s, arg_rmr *a)
57
static bool opffv_widen_check(DisasContext *s, arg_rmr *a)
58
{
59
return opfv_widen_check(s, a) &&
60
+ require_rvfmin(s) &&
61
require_scale_rvfmin(s) &&
62
(s->sew != MO_8);
63
}
64
@@ -XXX,XX +XXX,XX @@ static bool opfxv_narrow_check(DisasContext *s, arg_rmr *a)
65
static bool opffv_narrow_check(DisasContext *s, arg_rmr *a)
66
{
67
return opfv_narrow_check(s, a) &&
68
+ require_rvfmin(s) &&
69
require_scale_rvfmin(s) &&
70
(s->sew != MO_8);
71
}
72
--
73
2.45.1
diff view generated by jsdifflib
[PULL 06/12] hw/riscv: sifive_u: Use SIFIVE_U_CPU for mc->default_cpu_type
[PULL 18/28] target/riscv: rvv: Check single width operator for vector fp widen instructions
1
From: Bin Meng <bin.meng@windriver.com>
1
From: Max Chou <max.chou@sifive.com>
2
2
3
SIFIVE_U_CPU is conditionally set to SIFIVE_U34 or SIFIVE_U54, hence
3
The require_scale_rvf function only checks the double width operator for
4
there is no need to use #idef to set the mc->default_cpu_type.
4
the vector floating point widen instructions, so most of the widen
5
checking functions need to add require_rvf for single width operator.
5
6
6
Signed-off-by: Bin Meng <bin.meng@windriver.com>
7
The vfwcvt.f.x.v and vfwcvt.f.xu.v instructions convert single width
7
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
integer to double width float, so the opfxv_widen_check function doesn’t
8
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
9
need require_rvf for the single width operator(integer).
9
Message-id: 20210109143637.29645-1-bmeng.cn@gmail.com
10
11
Signed-off-by: Max Chou <max.chou@sifive.com>
12
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
13
Cc: qemu-stable <qemu-stable@nongnu.org>
14
Message-ID: <20240322092600.1198921-3-max.chou@sifive.com>
10
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
15
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
11
---
16
---
12
hw/riscv/sifive_u.c | 6 +-----
17
target/riscv/insn_trans/trans_rvv.c.inc | 5 +++++
13
1 file changed, 1 insertion(+), 5 deletions(-)
18
1 file changed, 5 insertions(+)
14
19
15
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
20
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
16
index XXXXXXX..XXXXXXX 100644
21
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/riscv/sifive_u.c
22
--- a/target/riscv/insn_trans/trans_rvv.c.inc
18
+++ b/hw/riscv/sifive_u.c
23
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
19
@@ -XXX,XX +XXX,XX @@ static void sifive_u_machine_class_init(ObjectClass *oc, void *data)
24
@@ -XXX,XX +XXX,XX @@ GEN_OPFVF_TRANS(vfrsub_vf, opfvf_check)
20
mc->init = sifive_u_machine_init;
25
static bool opfvv_widen_check(DisasContext *s, arg_rmrr *a)
21
mc->max_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + SIFIVE_U_COMPUTE_CPU_COUNT;
26
{
22
mc->min_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + 1;
27
return require_rvv(s) &&
23
-#if defined(TARGET_RISCV32)
28
+ require_rvf(s) &&
24
- mc->default_cpu_type = TYPE_RISCV_CPU_SIFIVE_U34;
29
require_scale_rvf(s) &&
25
-#elif defined(TARGET_RISCV64)
30
(s->sew != MO_8) &&
26
- mc->default_cpu_type = TYPE_RISCV_CPU_SIFIVE_U54;
31
vext_check_isa_ill(s) &&
27
-#endif
32
@@ -XXX,XX +XXX,XX @@ GEN_OPFVV_WIDEN_TRANS(vfwsub_vv, opfvv_widen_check)
28
+ mc->default_cpu_type = SIFIVE_U_CPU;
33
static bool opfvf_widen_check(DisasContext *s, arg_rmrr *a)
29
mc->default_cpus = mc->min_cpus;
34
{
30
35
return require_rvv(s) &&
31
object_class_property_add_bool(oc, "start-in-flash",
36
+ require_rvf(s) &&
37
require_scale_rvf(s) &&
38
(s->sew != MO_8) &&
39
vext_check_isa_ill(s) &&
40
@@ -XXX,XX +XXX,XX @@ GEN_OPFVF_WIDEN_TRANS(vfwsub_vf)
41
static bool opfwv_widen_check(DisasContext *s, arg_rmrr *a)
42
{
43
return require_rvv(s) &&
44
+ require_rvf(s) &&
45
require_scale_rvf(s) &&
46
(s->sew != MO_8) &&
47
vext_check_isa_ill(s) &&
48
@@ -XXX,XX +XXX,XX @@ GEN_OPFWV_WIDEN_TRANS(vfwsub_wv)
49
static bool opfwf_widen_check(DisasContext *s, arg_rmrr *a)
50
{
51
return require_rvv(s) &&
52
+ require_rvf(s) &&
53
require_scale_rvf(s) &&
54
(s->sew != MO_8) &&
55
vext_check_isa_ill(s) &&
56
@@ -XXX,XX +XXX,XX @@ GEN_OPFVV_TRANS(vfredmin_vs, freduction_check)
57
static bool freduction_widen_check(DisasContext *s, arg_rmrr *a)
58
{
59
return reduction_widen_check(s, a) &&
60
+ require_rvf(s) &&
61
require_scale_rvf(s) &&
62
(s->sew != MO_8);
63
}
32
--
64
--
33
2.29.2
65
2.45.1
34
66
35
67
diff view generated by jsdifflib
New patch
[PULL 19/28] target/riscv: rvv: Check single width operator for vfncvt.rod.f.f.w
1
From: Max Chou <max.chou@sifive.com>
1
2
3
The opfv_narrow_check needs to check the single width float operator by
4
require_rvf.
5
6
Signed-off-by: Max Chou <max.chou@sifive.com>
7
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
8
Cc: qemu-stable <qemu-stable@nongnu.org>
9
Message-ID: <20240322092600.1198921-4-max.chou@sifive.com>
10
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
11
---
12
target/riscv/insn_trans/trans_rvv.c.inc | 1 +
13
1 file changed, 1 insertion(+)
14
15
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
16
index XXXXXXX..XXXXXXX 100644
17
--- a/target/riscv/insn_trans/trans_rvv.c.inc
18
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
19
@@ -XXX,XX +XXX,XX @@ static bool opffv_narrow_check(DisasContext *s, arg_rmr *a)
20
static bool opffv_rod_narrow_check(DisasContext *s, arg_rmr *a)
21
{
22
return opfv_narrow_check(s, a) &&
23
+ require_rvf(s) &&
24
require_scale_rvf(s) &&
25
(s->sew != MO_8);
26
}
27
--
28
2.45.1
diff view generated by jsdifflib
New patch
[PULL 20/28] target/riscv: rvv: Remove redudant SEW checking for vector fp narrow/widen instructions
1
From: Max Chou <max.chou@sifive.com>
1
2
3
If the checking functions check both the single and double width
4
operators at the same time, then the single width operator checking
5
functions (require_rvf[min]) will check whether the SEW is 8.
6
7
Signed-off-by: Max Chou <max.chou@sifive.com>
8
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
9
Cc: qemu-stable <qemu-stable@nongnu.org>
10
Message-ID: <20240322092600.1198921-5-max.chou@sifive.com>
11
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
12
---
13
target/riscv/insn_trans/trans_rvv.c.inc | 16 ++++------------
14
1 file changed, 4 insertions(+), 12 deletions(-)
15
16
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/riscv/insn_trans/trans_rvv.c.inc
19
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
20
@@ -XXX,XX +XXX,XX @@ static bool opfvv_widen_check(DisasContext *s, arg_rmrr *a)
21
return require_rvv(s) &&
22
require_rvf(s) &&
23
require_scale_rvf(s) &&
24
- (s->sew != MO_8) &&
25
vext_check_isa_ill(s) &&
26
vext_check_dss(s, a->rd, a->rs1, a->rs2, a->vm);
27
}
28
@@ -XXX,XX +XXX,XX @@ static bool opfvf_widen_check(DisasContext *s, arg_rmrr *a)
29
return require_rvv(s) &&
30
require_rvf(s) &&
31
require_scale_rvf(s) &&
32
- (s->sew != MO_8) &&
33
vext_check_isa_ill(s) &&
34
vext_check_ds(s, a->rd, a->rs2, a->vm);
35
}
36
@@ -XXX,XX +XXX,XX @@ static bool opfwv_widen_check(DisasContext *s, arg_rmrr *a)
37
return require_rvv(s) &&
38
require_rvf(s) &&
39
require_scale_rvf(s) &&
40
- (s->sew != MO_8) &&
41
vext_check_isa_ill(s) &&
42
vext_check_dds(s, a->rd, a->rs1, a->rs2, a->vm);
43
}
44
@@ -XXX,XX +XXX,XX @@ static bool opfwf_widen_check(DisasContext *s, arg_rmrr *a)
45
return require_rvv(s) &&
46
require_rvf(s) &&
47
require_scale_rvf(s) &&
48
- (s->sew != MO_8) &&
49
vext_check_isa_ill(s) &&
50
vext_check_dd(s, a->rd, a->rs2, a->vm);
51
}
52
@@ -XXX,XX +XXX,XX @@ static bool opffv_widen_check(DisasContext *s, arg_rmr *a)
53
{
54
return opfv_widen_check(s, a) &&
55
require_rvfmin(s) &&
56
- require_scale_rvfmin(s) &&
57
- (s->sew != MO_8);
58
+ require_scale_rvfmin(s);
59
}
60
61
#define GEN_OPFV_WIDEN_TRANS(NAME, CHECK, HELPER, FRM) \
62
@@ -XXX,XX +XXX,XX @@ static bool opffv_narrow_check(DisasContext *s, arg_rmr *a)
63
{
64
return opfv_narrow_check(s, a) &&
65
require_rvfmin(s) &&
66
- require_scale_rvfmin(s) &&
67
- (s->sew != MO_8);
68
+ require_scale_rvfmin(s);
69
}
70
71
static bool opffv_rod_narrow_check(DisasContext *s, arg_rmr *a)
72
{
73
return opfv_narrow_check(s, a) &&
74
require_rvf(s) &&
75
- require_scale_rvf(s) &&
76
- (s->sew != MO_8);
77
+ require_scale_rvf(s);
78
}
79
80
#define GEN_OPFV_NARROW_TRANS(NAME, CHECK, HELPER, FRM) \
81
@@ -XXX,XX +XXX,XX @@ static bool freduction_widen_check(DisasContext *s, arg_rmrr *a)
82
{
83
return reduction_widen_check(s, a) &&
84
require_rvf(s) &&
85
- require_scale_rvf(s) &&
86
- (s->sew != MO_8);
87
+ require_scale_rvf(s);
88
}
89
90
GEN_OPFVV_WIDEN_TRANS(vfwredusum_vs, freduction_widen_check)
91
--
92
2.45.1
diff view generated by jsdifflib
New patch
[PULL 21/28] target/riscv: prioritize pmp errors in raise_mmu_exception()
1
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
1
2
3
raise_mmu_exception(), as is today, is prioritizing guest page faults by
4
checking first if virt_enabled && !first_stage, and then considering the
5
regular inst/load/store faults.
6
7
There's no mention in the spec about guest page fault being a higher
8
priority that PMP faults. In fact, privileged spec section 3.7.1 says:
9
10
"Attempting to fetch an instruction from a PMP region that does not have
11
execute permissions raises an instruction access-fault exception.
12
Attempting to execute a load or load-reserved instruction which accesses
13
a physical address within a PMP region without read permissions raises a
14
load access-fault exception. Attempting to execute a store,
15
store-conditional, or AMO instruction which accesses a physical address
16
within a PMP region without write permissions raises a store
17
access-fault exception."
18
19
So, in fact, we're doing it wrong - PMP faults should always be thrown,
20
regardless of also being a first or second stage fault.
21
22
The way riscv_cpu_tlb_fill() and get_physical_address() work is
23
adequate: a TRANSLATE_PMP_FAIL error is immediately reported and
24
reflected in the 'pmp_violation' flag. What we need is to change
25
raise_mmu_exception() to prioritize it.
26
27
Reported-by: Joseph Chan <jchan@ventanamicro.com>
28
Fixes: 82d53adfbb ("target/riscv/cpu_helper.c: Invalid exception on MMU translation stage")
29
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
30
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
31
Message-ID: <20240413105929.7030-1-alexei.filippov@syntacore.com>
32
Cc: qemu-stable <qemu-stable@nongnu.org>
33
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
34
---
35
target/riscv/cpu_helper.c | 22 ++++++++++++----------
36
1 file changed, 12 insertions(+), 10 deletions(-)
37
38
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
39
index XXXXXXX..XXXXXXX 100644
40
--- a/target/riscv/cpu_helper.c
41
+++ b/target/riscv/cpu_helper.c
42
@@ -XXX,XX +XXX,XX @@ static void raise_mmu_exception(CPURISCVState *env, target_ulong address,
43
44
switch (access_type) {
45
case MMU_INST_FETCH:
46
- if (env->virt_enabled && !first_stage) {
47
+ if (pmp_violation) {
48
+ cs->exception_index = RISCV_EXCP_INST_ACCESS_FAULT;
49
+ } else if (env->virt_enabled && !first_stage) {
50
cs->exception_index = RISCV_EXCP_INST_GUEST_PAGE_FAULT;
51
} else {
52
- cs->exception_index = pmp_violation ?
53
- RISCV_EXCP_INST_ACCESS_FAULT : RISCV_EXCP_INST_PAGE_FAULT;
54
+ cs->exception_index = RISCV_EXCP_INST_PAGE_FAULT;
55
}
56
break;
57
case MMU_DATA_LOAD:
58
- if (two_stage && !first_stage) {
59
+ if (pmp_violation) {
60
+ cs->exception_index = RISCV_EXCP_LOAD_ACCESS_FAULT;
61
+ } else if (two_stage && !first_stage) {
62
cs->exception_index = RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT;
63
} else {
64
- cs->exception_index = pmp_violation ?
65
- RISCV_EXCP_LOAD_ACCESS_FAULT : RISCV_EXCP_LOAD_PAGE_FAULT;
66
+ cs->exception_index = RISCV_EXCP_LOAD_PAGE_FAULT;
67
}
68
break;
69
case MMU_DATA_STORE:
70
- if (two_stage && !first_stage) {
71
+ if (pmp_violation) {
72
+ cs->exception_index = RISCV_EXCP_STORE_AMO_ACCESS_FAULT;
73
+ } else if (two_stage && !first_stage) {
74
cs->exception_index = RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT;
75
} else {
76
- cs->exception_index = pmp_violation ?
77
- RISCV_EXCP_STORE_AMO_ACCESS_FAULT :
78
- RISCV_EXCP_STORE_PAGE_FAULT;
79
+ cs->exception_index = RISCV_EXCP_STORE_PAGE_FAULT;
80
}
81
break;
82
default:
83
--
84
2.45.1
diff view generated by jsdifflib
New patch
[PULL 22/28] target/riscv: do not set mtval2 for non guest-page faults
1
From: Alexei Filippov <alexei.filippov@syntacore.com>
1
2
3
Previous patch fixed the PMP priority in raise_mmu_exception() but we're still
4
setting mtval2 incorrectly. In riscv_cpu_tlb_fill(), after pmp check in 2 stage
5
translation part, mtval2 will be set in case of successes 2 stage translation but
6
failed pmp check.
7
8
In this case we gonna set mtval2 via env->guest_phys_fault_addr in context of
9
riscv_cpu_tlb_fill(), as this was a guest-page-fault, but it didn't and mtval2
10
should be zero, according to RISCV privileged spec sect. 9.4.4: When a guest
11
page-fault is taken into M-mode, mtval2 is written with either zero or guest
12
physical address that faulted, shifted by 2 bits. *For other traps, mtval2
13
is set to zero...*
14
15
Signed-off-by: Alexei Filippov <alexei.filippov@syntacore.com>
16
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
17
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
18
Message-ID: <20240503103052.6819-1-alexei.filippov@syntacore.com>
19
Cc: qemu-stable <qemu-stable@nongnu.org>
20
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
21
---
22
target/riscv/cpu_helper.c | 12 ++++++------
23
1 file changed, 6 insertions(+), 6 deletions(-)
24
25
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
26
index XXXXXXX..XXXXXXX 100644
27
--- a/target/riscv/cpu_helper.c
28
+++ b/target/riscv/cpu_helper.c
29
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
30
__func__, pa, ret, prot_pmp, tlb_size);
31
32
prot &= prot_pmp;
33
- }
34
-
35
- if (ret != TRANSLATE_SUCCESS) {
36
+ } else {
37
/*
38
* Guest physical address translation failed, this is a HS
39
* level exception
40
*/
41
first_stage_error = false;
42
- env->guest_phys_fault_addr = (im_address |
43
- (address &
44
- (TARGET_PAGE_SIZE - 1))) >> 2;
45
+ if (ret != TRANSLATE_PMP_FAIL) {
46
+ env->guest_phys_fault_addr = (im_address |
47
+ (address &
48
+ (TARGET_PAGE_SIZE - 1))) >> 2;
49
+ }
50
}
51
}
52
} else {
53
--
54
2.45.1
diff view generated by jsdifflib
New patch
[PULL 23/28] target/riscv: Remove experimental prefix from "B" extension
1
From: Rob Bradford <rbradford@rivosinc.com>
1
2
3
This extension has now been ratified:
4
https://jira.riscv.org/browse/RVS-2006 so the "x-" prefix can be
5
removed.
6
7
Since this is now a ratified extension add it to the list of extensions
8
included in the "max" CPU variant.
9
10
Signed-off-by: Rob Bradford <rbradford@rivosinc.com>
11
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
12
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
13
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
14
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
15
Message-ID: <20240514110217.22516-1-rbradford@rivosinc.com>
16
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
17
---
18
target/riscv/cpu.c | 2 +-
19
target/riscv/tcg/tcg-cpu.c | 2 +-
20
2 files changed, 2 insertions(+), 2 deletions(-)
21
22
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
23
index XXXXXXX..XXXXXXX 100644
24
--- a/target/riscv/cpu.c
25
+++ b/target/riscv/cpu.c
26
@@ -XXX,XX +XXX,XX @@ static const MISAExtInfo misa_ext_info_arr[] = {
27
MISA_EXT_INFO(RVJ, "x-j", "Dynamic translated languages"),
28
MISA_EXT_INFO(RVV, "v", "Vector operations"),
29
MISA_EXT_INFO(RVG, "g", "General purpose (IMAFD_Zicsr_Zifencei)"),
30
- MISA_EXT_INFO(RVB, "x-b", "Bit manipulation (Zba_Zbb_Zbs)")
31
+ MISA_EXT_INFO(RVB, "b", "Bit manipulation (Zba_Zbb_Zbs)")
32
};
33
34
static void riscv_cpu_validate_misa_mxl(RISCVCPUClass *mcc)
35
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
36
index XXXXXXX..XXXXXXX 100644
37
--- a/target/riscv/tcg/tcg-cpu.c
38
+++ b/target/riscv/tcg/tcg-cpu.c
39
@@ -XXX,XX +XXX,XX @@ static void riscv_init_max_cpu_extensions(Object *obj)
40
const RISCVCPUMultiExtConfig *prop;
41
42
/* Enable RVG, RVJ and RVV that are disabled by default */
43
- riscv_cpu_set_misa_ext(env, env->misa_ext | RVG | RVJ | RVV);
44
+ riscv_cpu_set_misa_ext(env, env->misa_ext | RVB | RVG | RVJ | RVV);
45
46
for (prop = riscv_cpu_extensions; prop && prop->name; prop++) {
47
isa_ext_update_enabled(cpu, prop->offset, true);
48
--
49
2.45.1
diff view generated by jsdifflib
New patch
[PULL 24/28] target/riscv: rvzicbo: Fixup CBO extension register calculation
1
From: Alistair Francis <alistair23@gmail.com>
1
2
3
When running the instruction
4
5
```
6
cbo.flush 0(x0)
7
```
8
9
QEMU would segfault.
10
11
The issue was in cpu_gpr[a->rs1] as QEMU does not have cpu_gpr[0]
12
allocated.
13
14
In order to fix this let's use the existing get_address()
15
helper. This also has the benefit of performing pointer mask
16
calculations on the address specified in rs1.
17
18
The pointer masking specificiation specifically states:
19
20
"""
21
Cache Management Operations: All instructions in Zicbom, Zicbop and Zicboz
22
"""
23
24
So this is the correct behaviour and we previously have been incorrectly
25
not masking the address.
26
27
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
28
Reported-by: Fabian Thomas <fabian.thomas@cispa.de>
29
Fixes: e05da09b7cfd ("target/riscv: implement Zicbom extension")
30
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
31
Cc: qemu-stable <qemu-stable@nongnu.org>
32
Message-ID: <20240514023910.301766-1-alistair.francis@wdc.com>
33
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
34
---
35
target/riscv/insn_trans/trans_rvzicbo.c.inc | 16 ++++++++++++----
36
1 file changed, 12 insertions(+), 4 deletions(-)
37
38
diff --git a/target/riscv/insn_trans/trans_rvzicbo.c.inc b/target/riscv/insn_trans/trans_rvzicbo.c.inc
39
index XXXXXXX..XXXXXXX 100644
40
--- a/target/riscv/insn_trans/trans_rvzicbo.c.inc
41
+++ b/target/riscv/insn_trans/trans_rvzicbo.c.inc
42
@@ -XXX,XX +XXX,XX @@
43
static bool trans_cbo_clean(DisasContext *ctx, arg_cbo_clean *a)
44
{
45
REQUIRE_ZICBOM(ctx);
46
- gen_helper_cbo_clean_flush(tcg_env, cpu_gpr[a->rs1]);
47
+ TCGv src = get_address(ctx, a->rs1, 0);
48
+
49
+ gen_helper_cbo_clean_flush(tcg_env, src);
50
return true;
51
}
52
53
static bool trans_cbo_flush(DisasContext *ctx, arg_cbo_flush *a)
54
{
55
REQUIRE_ZICBOM(ctx);
56
- gen_helper_cbo_clean_flush(tcg_env, cpu_gpr[a->rs1]);
57
+ TCGv src = get_address(ctx, a->rs1, 0);
58
+
59
+ gen_helper_cbo_clean_flush(tcg_env, src);
60
return true;
61
}
62
63
static bool trans_cbo_inval(DisasContext *ctx, arg_cbo_inval *a)
64
{
65
REQUIRE_ZICBOM(ctx);
66
- gen_helper_cbo_inval(tcg_env, cpu_gpr[a->rs1]);
67
+ TCGv src = get_address(ctx, a->rs1, 0);
68
+
69
+ gen_helper_cbo_inval(tcg_env, src);
70
return true;
71
}
72
73
static bool trans_cbo_zero(DisasContext *ctx, arg_cbo_zero *a)
74
{
75
REQUIRE_ZICBOZ(ctx);
76
- gen_helper_cbo_zero(tcg_env, cpu_gpr[a->rs1]);
77
+ TCGv src = get_address(ctx, a->rs1, 0);
78
+
79
+ gen_helper_cbo_zero(tcg_env, src);
80
return true;
81
}
82
--
83
2.45.1
diff view generated by jsdifflib
[PULL 01/12] hw/block: m25p80: Don't write to flash if write is disabled
[PULL 25/28] target/riscv/kvm.c: Fix the hart bit setting of AIA
1
From: Bin Meng <bin.meng@windriver.com>
1
From: Yong-Xuan Wang <yongxuan.wang@sifive.com>
2
2
3
When write is disabled, the write to flash should be avoided
3
In AIA spec, each hart (or each hart within a group) has a unique hart
4
in flash_write8().
4
number to locate the memory pages of interrupt files in the address
5
space. The number of bits required to represent any hart number is equal
6
to ceil(log2(hmax + 1)), where hmax is the largest hart number among
7
groups.
5
8
6
Fixes: 82a2499011a7 ("m25p80: Initial implementation of SPI flash device")
9
However, if the largest hart number among groups is a power of 2, QEMU
7
Signed-off-by: Bin Meng <bin.meng@windriver.com>
10
will pass an inaccurate hart-index-bit setting to Linux. For example, when
8
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
11
the guest OS has 4 harts, only ceil(log2(3 + 1)) = 2 bits are sufficient
9
Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
12
to represent 4 harts, but we passes 3 to Linux. The code needs to be
10
Message-id: 1608688825-81519-1-git-send-email-bmeng.cn@gmail.com
13
updated to ensure accurate hart-index-bit settings.
14
15
Additionally, a Linux patch[1] is necessary to correctly recover the hart
16
index when the guest OS has only 1 hart, where the hart-index-bit is 0.
17
18
[1] https://lore.kernel.org/lkml/20240415064905.25184-1-yongxuan.wang@sifive.com/t/
19
20
Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com>
21
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
22
Cc: qemu-stable <qemu-stable@nongnu.org>
23
Message-ID: <20240515091129.28116-1-yongxuan.wang@sifive.com>
11
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
24
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
12
---
25
---
13
hw/block/m25p80.c | 1 +
26
target/riscv/kvm/kvm-cpu.c | 9 ++++++++-
14
1 file changed, 1 insertion(+)
27
1 file changed, 8 insertions(+), 1 deletion(-)
15
28
16
diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
29
diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
17
index XXXXXXX..XXXXXXX 100644
30
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/block/m25p80.c
31
--- a/target/riscv/kvm/kvm-cpu.c
19
+++ b/hw/block/m25p80.c
32
+++ b/target/riscv/kvm/kvm-cpu.c
20
@@ -XXX,XX +XXX,XX @@ void flash_write8(Flash *s, uint32_t addr, uint8_t data)
33
@@ -XXX,XX +XXX,XX @@ void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift,
21
34
}
22
if (!s->write_enable) {
23
qemu_log_mask(LOG_GUEST_ERROR, "M25P80: write with write protect!\n");
24
+ return;
25
}
35
}
26
36
27
if ((prev ^ data) & data) {
37
- hart_bits = find_last_bit(&max_hart_per_socket, BITS_PER_LONG) + 1;
38
+
39
+ if (max_hart_per_socket > 1) {
40
+ max_hart_per_socket--;
41
+ hart_bits = find_last_bit(&max_hart_per_socket, BITS_PER_LONG) + 1;
42
+ } else {
43
+ hart_bits = 0;
44
+ }
45
+
46
ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG,
47
KVM_DEV_RISCV_AIA_CONFIG_HART_BITS,
48
&hart_bits, true, NULL);
28
--
49
--
29
2.29.2
50
2.45.1
30
31
diff view generated by jsdifflib
[PULL 07/12] hw/misc/sifive_u_otp: handling the fails of blk_pread and blk_pwrite
[PULL 26/28] riscv, gdbstub.c: fix reg_width in ricsv_gen_dynamic_vector_feature()
1
From: Green Wan <green.wan@sifive.com>
1
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
2
2
3
Fix code coverage issues by checking return value and handling fail case
3
Commit 33a24910ae changed 'reg_width' to use 'vlenb', i.e. vector length
4
of blk_pread() and blk_pwrite(). Return default value 0xff if read fails.
4
in bytes, when in this context we want 'reg_width' as the length in
5
bits.
5
6
6
Fixes: Coverity CID 1435959
7
Fix 'reg_width' back to the value in bits like 7cb59921c05a
7
Fixes: Coverity CID 1435960
8
("target/riscv/gdbstub.c: use 'vlenb' instead of shifting 'vlen'") set
8
Fixes: Coverity CID 1435961
9
beforehand.
9
Signed-off-by: Green Wan <green.wan@sifive.com>
10
11
While we're at it, rename 'reg_width' to 'bitsize' to provide a bit more
12
clarity about what the variable represents. 'bitsize' is also used in
13
riscv_gen_dynamic_csr_feature() with the same purpose, i.e. as an input to
14
gdb_feature_builder_append_reg().
15
16
Cc: Akihiko Odaki <akihiko.odaki@daynix.com>
17
Cc: Alex Bennée <alex.bennee@linaro.org>
18
Reported-by: Robin Dapp <rdapp.gcc@gmail.com>
19
Fixes: 33a24910ae ("target/riscv: Use GDBFeature for dynamic XML")
20
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
21
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
22
Acked-by: Alex Bennée <alex.bennee@linaro.org>
23
Reviewed-by: Akihiko Odaki <akihiko.odaki@daynix.com>
10
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
24
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
11
Message-id: 20201104092900.21214-1-green.wan@sifive.com
25
Cc: qemu-stable <qemu-stable@nongnu.org>
26
Message-ID: <20240517203054.880861-2-dbarboza@ventanamicro.com>
12
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
27
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
13
---
28
---
14
hw/misc/sifive_u_otp.c | 31 +++++++++++++++++++++++--------
29
target/riscv/gdbstub.c | 6 +++---
15
1 file changed, 23 insertions(+), 8 deletions(-)
30
1 file changed, 3 insertions(+), 3 deletions(-)
16
31
17
diff --git a/hw/misc/sifive_u_otp.c b/hw/misc/sifive_u_otp.c
32
diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
18
index XXXXXXX..XXXXXXX 100644
33
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/misc/sifive_u_otp.c
34
--- a/target/riscv/gdbstub.c
20
+++ b/hw/misc/sifive_u_otp.c
35
+++ b/target/riscv/gdbstub.c
21
@@ -XXX,XX +XXX,XX @@ static uint64_t sifive_u_otp_read(void *opaque, hwaddr addr, unsigned int size)
36
@@ -XXX,XX +XXX,XX @@ static GDBFeature *riscv_gen_dynamic_csr_feature(CPUState *cs, int base_reg)
22
if (s->blk) {
37
static GDBFeature *ricsv_gen_dynamic_vector_feature(CPUState *cs, int base_reg)
23
int32_t buf;
38
{
24
39
RISCVCPU *cpu = RISCV_CPU(cs);
25
- blk_pread(s->blk, s->pa * SIFIVE_U_OTP_FUSE_WORD, &buf,
40
- int reg_width = cpu->cfg.vlenb;
26
- SIFIVE_U_OTP_FUSE_WORD);
41
+ int bitsize = cpu->cfg.vlenb << 3;
27
+ if (blk_pread(s->blk, s->pa * SIFIVE_U_OTP_FUSE_WORD, &buf,
42
GDBFeatureBuilder builder;
28
+ SIFIVE_U_OTP_FUSE_WORD) < 0) {
43
int i;
29
+ qemu_log_mask(LOG_GUEST_ERROR,
44
30
+ "read error index<%d>\n", s->pa);
45
@@ -XXX,XX +XXX,XX @@ static GDBFeature *ricsv_gen_dynamic_vector_feature(CPUState *cs, int base_reg)
31
+ return 0xff;
46
32
+ }
47
/* First define types and totals in a whole VL */
33
+
48
for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) {
34
return buf;
49
- int count = reg_width / vec_lanes[i].size;
35
}
50
+ int count = bitsize / vec_lanes[i].size;
36
51
gdb_feature_builder_append_tag(
37
@@ -XXX,XX +XXX,XX @@ static void sifive_u_otp_write(void *opaque, hwaddr addr,
52
&builder, "<vector id=\"%s\" type=\"%s\" count=\"%d\"/>",
38
53
vec_lanes[i].id, vec_lanes[i].gdb_type, count);
39
/* write to backend */
54
@@ -XXX,XX +XXX,XX @@ static GDBFeature *ricsv_gen_dynamic_vector_feature(CPUState *cs, int base_reg)
40
if (s->blk) {
55
/* Define vector registers */
41
- blk_pwrite(s->blk, s->pa * SIFIVE_U_OTP_FUSE_WORD,
56
for (i = 0; i < 32; i++) {
42
- &s->fuse[s->pa], SIFIVE_U_OTP_FUSE_WORD, 0);
57
gdb_feature_builder_append_reg(&builder, g_strdup_printf("v%d", i),
43
+ if (blk_pwrite(s->blk, s->pa * SIFIVE_U_OTP_FUSE_WORD,
58
- reg_width, i, "riscv_vector", "vector");
44
+ &s->fuse[s->pa], SIFIVE_U_OTP_FUSE_WORD,
59
+ bitsize, i, "riscv_vector", "vector");
45
+ 0) < 0) {
46
+ qemu_log_mask(LOG_GUEST_ERROR,
47
+ "write error index<%d>\n", s->pa);
48
+ }
49
}
50
51
/* update written bit */
52
@@ -XXX,XX +XXX,XX @@ static void sifive_u_otp_reset(DeviceState *dev)
53
int index = SIFIVE_U_OTP_SERIAL_ADDR;
54
55
serial_data = s->serial;
56
- blk_pwrite(s->blk, index * SIFIVE_U_OTP_FUSE_WORD,
57
- &serial_data, SIFIVE_U_OTP_FUSE_WORD, 0);
58
+ if (blk_pwrite(s->blk, index * SIFIVE_U_OTP_FUSE_WORD,
59
+ &serial_data, SIFIVE_U_OTP_FUSE_WORD, 0) < 0) {
60
+ qemu_log_mask(LOG_GUEST_ERROR,
61
+ "write error index<%d>\n", index);
62
+ }
63
64
serial_data = ~(s->serial);
65
- blk_pwrite(s->blk, (index + 1) * SIFIVE_U_OTP_FUSE_WORD,
66
- &serial_data, SIFIVE_U_OTP_FUSE_WORD, 0);
67
+ if (blk_pwrite(s->blk, (index + 1) * SIFIVE_U_OTP_FUSE_WORD,
68
+ &serial_data, SIFIVE_U_OTP_FUSE_WORD, 0) < 0) {
69
+ qemu_log_mask(LOG_GUEST_ERROR,
70
+ "write error index<%d>\n", index + 1);
71
+ }
72
}
60
}
73
61
74
/* Initialize write-once map */
62
gdb_feature_builder_end(&builder);
75
--
63
--
76
2.29.2
64
2.45.1
77
65
78
66
diff view generated by jsdifflib
New patch
[PULL 27/28] disas/riscv: Decode all of the pmpcfg and pmpaddr CSRs
1
From: Alistair Francis <alistair23@gmail.com>
1
2
3
Previously we only listed a single pmpcfg CSR and the first 16 pmpaddr
4
CSRs. This patch fixes this to list all 16 pmpcfg and all 64 pmpaddr
5
CSRs are part of the disassembly.
6
7
Reported-by: Eric DeVolder <eric_devolder@yahoo.com>
8
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
9
Fixes: ea10325917 ("RISC-V Disassembler")
10
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
11
Cc: qemu-stable <qemu-stable@nongnu.org>
12
Message-ID: <20240514051615.330979-1-alistair.francis@wdc.com>
13
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
14
---
15
disas/riscv.c | 65 ++++++++++++++++++++++++++++++++++++++++++++++++++-
16
1 file changed, 64 insertions(+), 1 deletion(-)
17
18
diff --git a/disas/riscv.c b/disas/riscv.c
19
index XXXXXXX..XXXXXXX 100644
20
--- a/disas/riscv.c
21
+++ b/disas/riscv.c
22
@@ -XXX,XX +XXX,XX @@ static const char *csr_name(int csrno)
23
case 0x0383: return "mibound";
24
case 0x0384: return "mdbase";
25
case 0x0385: return "mdbound";
26
- case 0x03a0: return "pmpcfg3";
27
+ case 0x03a0: return "pmpcfg0";
28
+ case 0x03a1: return "pmpcfg1";
29
+ case 0x03a2: return "pmpcfg2";
30
+ case 0x03a3: return "pmpcfg3";
31
+ case 0x03a4: return "pmpcfg4";
32
+ case 0x03a5: return "pmpcfg5";
33
+ case 0x03a6: return "pmpcfg6";
34
+ case 0x03a7: return "pmpcfg7";
35
+ case 0x03a8: return "pmpcfg8";
36
+ case 0x03a9: return "pmpcfg9";
37
+ case 0x03aa: return "pmpcfg10";
38
+ case 0x03ab: return "pmpcfg11";
39
+ case 0x03ac: return "pmpcfg12";
40
+ case 0x03ad: return "pmpcfg13";
41
+ case 0x03ae: return "pmpcfg14";
42
+ case 0x03af: return "pmpcfg15";
43
case 0x03b0: return "pmpaddr0";
44
case 0x03b1: return "pmpaddr1";
45
case 0x03b2: return "pmpaddr2";
46
@@ -XXX,XX +XXX,XX @@ static const char *csr_name(int csrno)
47
case 0x03bd: return "pmpaddr13";
48
case 0x03be: return "pmpaddr14";
49
case 0x03bf: return "pmpaddr15";
50
+ case 0x03c0: return "pmpaddr16";
51
+ case 0x03c1: return "pmpaddr17";
52
+ case 0x03c2: return "pmpaddr18";
53
+ case 0x03c3: return "pmpaddr19";
54
+ case 0x03c4: return "pmpaddr20";
55
+ case 0x03c5: return "pmpaddr21";
56
+ case 0x03c6: return "pmpaddr22";
57
+ case 0x03c7: return "pmpaddr23";
58
+ case 0x03c8: return "pmpaddr24";
59
+ case 0x03c9: return "pmpaddr25";
60
+ case 0x03ca: return "pmpaddr26";
61
+ case 0x03cb: return "pmpaddr27";
62
+ case 0x03cc: return "pmpaddr28";
63
+ case 0x03cd: return "pmpaddr29";
64
+ case 0x03ce: return "pmpaddr30";
65
+ case 0x03cf: return "pmpaddr31";
66
+ case 0x03d0: return "pmpaddr32";
67
+ case 0x03d1: return "pmpaddr33";
68
+ case 0x03d2: return "pmpaddr34";
69
+ case 0x03d3: return "pmpaddr35";
70
+ case 0x03d4: return "pmpaddr36";
71
+ case 0x03d5: return "pmpaddr37";
72
+ case 0x03d6: return "pmpaddr38";
73
+ case 0x03d7: return "pmpaddr39";
74
+ case 0x03d8: return "pmpaddr40";
75
+ case 0x03d9: return "pmpaddr41";
76
+ case 0x03da: return "pmpaddr42";
77
+ case 0x03db: return "pmpaddr43";
78
+ case 0x03dc: return "pmpaddr44";
79
+ case 0x03dd: return "pmpaddr45";
80
+ case 0x03de: return "pmpaddr46";
81
+ case 0x03df: return "pmpaddr47";
82
+ case 0x03e0: return "pmpaddr48";
83
+ case 0x03e1: return "pmpaddr49";
84
+ case 0x03e2: return "pmpaddr50";
85
+ case 0x03e3: return "pmpaddr51";
86
+ case 0x03e4: return "pmpaddr52";
87
+ case 0x03e5: return "pmpaddr53";
88
+ case 0x03e6: return "pmpaddr54";
89
+ case 0x03e7: return "pmpaddr55";
90
+ case 0x03e8: return "pmpaddr56";
91
+ case 0x03e9: return "pmpaddr57";
92
+ case 0x03ea: return "pmpaddr58";
93
+ case 0x03eb: return "pmpaddr59";
94
+ case 0x03ec: return "pmpaddr60";
95
+ case 0x03ed: return "pmpaddr61";
96
+ case 0x03ee: return "pmpaddr62";
97
+ case 0x03ef: return "pmpaddr63";
98
case 0x0780: return "mtohost";
99
case 0x0781: return "mfromhost";
100
case 0x0782: return "mreset";
101
--
102
2.45.1
diff view generated by jsdifflib
[PULL 09/12] target/riscv: Add CSR name in the CSR function table
[PULL 28/28] target/riscv: raise an exception when CSRRS/CSRRC writes a read-only CSR
1
From: Bin Meng <bin.meng@windriver.com>
1
From: Yu-Ming Chang <yumin686@andestech.com>
2
2
3
In preparation to generate the CSR register list for GDB stub
3
Both CSRRS and CSRRC always read the addressed CSR and cause any read side
4
dynamically, let's add the CSR name in the CSR function table.
4
effects regardless of rs1 and rd fields. Note that if rs1 specifies a register
5
holding a zero value other than x0, the instruction will still attempt to write
6
the unmodified value back to the CSR and will cause any attendant side effects.
5
7
6
Signed-off-by: Bin Meng <bin.meng@windriver.com>
8
So if CSRRS or CSRRC tries to write a read-only CSR with rs1 which specifies
9
a register holding a zero value, an illegal instruction exception should be
10
raised.
11
12
Signed-off-by: Yu-Ming Chang <yumin686@andestech.com>
7
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
13
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
8
Message-id: 1610427124-49887-3-git-send-email-bmeng.cn@gmail.com
14
Message-ID: <20240403070823.80897-1-yumin686@andestech.com>
9
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
15
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
10
---
16
---
11
target/riscv/cpu.h | 1 +
17
target/riscv/cpu.h | 4 ++++
12
target/riscv/csr.c | 332 +++++++++++++++++++++++++++++++++------------
18
target/riscv/csr.c | 51 ++++++++++++++++++++++++++++++++++++----
13
2 files changed, 249 insertions(+), 84 deletions(-)
19
target/riscv/op_helper.c | 6 ++---
20
3 files changed, 53 insertions(+), 8 deletions(-)
14
21
15
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
22
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
16
index XXXXXXX..XXXXXXX 100644
23
index XXXXXXX..XXXXXXX 100644
17
--- a/target/riscv/cpu.h
24
--- a/target/riscv/cpu.h
18
+++ b/target/riscv/cpu.h
25
+++ b/target/riscv/cpu.h
19
@@ -XXX,XX +XXX,XX @@ typedef int (*riscv_csr_op_fn)(CPURISCVState *env, int csrno,
26
@@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc,
20
target_ulong *ret_value, target_ulong new_value, target_ulong write_mask);
27
void riscv_cpu_update_mask(CPURISCVState *env);
21
28
bool riscv_cpu_is_32bit(RISCVCPU *cpu);
22
typedef struct {
29
23
+ const char *name;
30
+RISCVException riscv_csrr(CPURISCVState *env, int csrno,
24
riscv_csr_predicate_fn predicate;
31
+ target_ulong *ret_value);
25
riscv_csr_read_fn read;
32
RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
26
riscv_csr_write_fn write;
33
target_ulong *ret_value,
34
target_ulong new_value, target_ulong write_mask);
35
@@ -XXX,XX +XXX,XX @@ typedef RISCVException (*riscv_csr_op_fn)(CPURISCVState *env, int csrno,
36
target_ulong new_value,
37
target_ulong write_mask);
38
39
+RISCVException riscv_csrr_i128(CPURISCVState *env, int csrno,
40
+ Int128 *ret_value);
41
RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno,
42
Int128 *ret_value,
43
Int128 new_value, Int128 write_mask);
27
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
44
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
28
index XXXXXXX..XXXXXXX 100644
45
index XXXXXXX..XXXXXXX 100644
29
--- a/target/riscv/csr.c
46
--- a/target/riscv/csr.c
30
+++ b/target/riscv/csr.c
47
+++ b/target/riscv/csr.c
31
@@ -XXX,XX +XXX,XX @@ int riscv_csrrw_debug(CPURISCVState *env, int csrno, target_ulong *ret_value,
48
@@ -XXX,XX +XXX,XX @@ static RISCVException rmw_seed(CPURISCVState *env, int csrno,
32
/* Control and Status Register function table */
49
33
riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
50
static inline RISCVException riscv_csrrw_check(CPURISCVState *env,
34
/* User Floating-Point CSRs */
51
int csrno,
35
- [CSR_FFLAGS] = { fs, read_fflags, write_fflags },
52
- bool write_mask)
36
- [CSR_FRM] = { fs, read_frm, write_frm },
53
+ bool write)
37
- [CSR_FCSR] = { fs, read_fcsr, write_fcsr },
54
{
38
+ [CSR_FFLAGS] = { "fflags", fs, read_fflags, write_fflags },
55
/* check privileges and return RISCV_EXCP_ILLEGAL_INST if check fails */
39
+ [CSR_FRM] = { "frm", fs, read_frm, write_frm },
56
bool read_only = get_field(csrno, 0xC00) == 3;
40
+ [CSR_FCSR] = { "fcsr", fs, read_fcsr, write_fcsr },
57
@@ -XXX,XX +XXX,XX @@ static inline RISCVException riscv_csrrw_check(CPURISCVState *env,
41
/* Vector CSRs */
58
}
42
- [CSR_VSTART] = { vs, read_vstart, write_vstart },
59
43
- [CSR_VXSAT] = { vs, read_vxsat, write_vxsat },
60
/* read / write check */
44
- [CSR_VXRM] = { vs, read_vxrm, write_vxrm },
61
- if (write_mask && read_only) {
45
- [CSR_VL] = { vs, read_vl },
62
+ if (write && read_only) {
46
- [CSR_VTYPE] = { vs, read_vtype },
63
return RISCV_EXCP_ILLEGAL_INST;
47
+ [CSR_VSTART] = { "vstart", vs, read_vstart, write_vstart },
64
}
48
+ [CSR_VXSAT] = { "vxsat", vs, read_vxsat, write_vxsat },
65
49
+ [CSR_VXRM] = { "vxrm", vs, read_vxrm, write_vxrm },
66
@@ -XXX,XX +XXX,XX @@ static RISCVException riscv_csrrw_do64(CPURISCVState *env, int csrno,
50
+ [CSR_VL] = { "vl", vs, read_vl },
67
return RISCV_EXCP_NONE;
51
+ [CSR_VTYPE] = { "vtype", vs, read_vtype },
68
}
52
/* User Timers and Counters */
69
53
- [CSR_CYCLE] = { ctr, read_instret },
70
+RISCVException riscv_csrr(CPURISCVState *env, int csrno,
54
- [CSR_INSTRET] = { ctr, read_instret },
71
+ target_ulong *ret_value)
55
- [CSR_CYCLEH] = { ctr32, read_instreth },
72
+{
56
- [CSR_INSTRETH] = { ctr32, read_instreth },
73
+ RISCVException ret = riscv_csrrw_check(env, csrno, false);
57
-
74
+ if (ret != RISCV_EXCP_NONE) {
58
- /* In privileged mode, the monitor will have to emulate TIME CSRs only if
75
+ return ret;
59
- * rdtime callback is not provided by machine/platform emulation */
76
+ }
60
- [CSR_TIME] = { ctr, read_time },
77
+
61
- [CSR_TIMEH] = { ctr32, read_timeh },
78
+ return riscv_csrrw_do64(env, csrno, ret_value, 0, 0);
62
+ [CSR_CYCLE] = { "cycle", ctr, read_instret },
79
+}
63
+ [CSR_INSTRET] = { "instret", ctr, read_instret },
80
+
64
+ [CSR_CYCLEH] = { "cycleh", ctr32, read_instreth },
81
RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
65
+ [CSR_INSTRETH] = { "instreth", ctr32, read_instreth },
82
target_ulong *ret_value,
83
target_ulong new_value, target_ulong write_mask)
84
{
85
- RISCVException ret = riscv_csrrw_check(env, csrno, write_mask);
86
+ RISCVException ret = riscv_csrrw_check(env, csrno, true);
87
if (ret != RISCV_EXCP_NONE) {
88
return ret;
89
}
90
@@ -XXX,XX +XXX,XX @@ static RISCVException riscv_csrrw_do128(CPURISCVState *env, int csrno,
91
return RISCV_EXCP_NONE;
92
}
93
94
+RISCVException riscv_csrr_i128(CPURISCVState *env, int csrno,
95
+ Int128 *ret_value)
96
+{
97
+ RISCVException ret;
98
+
99
+ ret = riscv_csrrw_check(env, csrno, false);
100
+ if (ret != RISCV_EXCP_NONE) {
101
+ return ret;
102
+ }
103
+
104
+ if (csr_ops[csrno].read128) {
105
+ return riscv_csrrw_do128(env, csrno, ret_value,
106
+ int128_zero(), int128_zero());
107
+ }
66
+
108
+
67
+ /*
109
+ /*
68
+ * In privileged mode, the monitor will have to emulate TIME CSRs only if
110
+ * Fall back to 64-bit version for now, if the 128-bit alternative isn't
69
+ * rdtime callback is not provided by machine/platform emulation.
111
+ * at all defined.
112
+ * Note, some CSRs don't need to extend to MXLEN (64 upper bits non
113
+ * significant), for those, this fallback is correctly handling the
114
+ * accesses
70
+ */
115
+ */
71
+ [CSR_TIME] = { "time", ctr, read_time },
116
+ target_ulong old_value;
72
+ [CSR_TIMEH] = { "timeh", ctr32, read_timeh },
117
+ ret = riscv_csrrw_do64(env, csrno, &old_value,
73
118
+ (target_ulong)0,
74
#if !defined(CONFIG_USER_ONLY)
119
+ (target_ulong)0);
75
/* Machine Timers and Counters */
120
+ if (ret == RISCV_EXCP_NONE && ret_value) {
76
- [CSR_MCYCLE] = { any, read_instret },
121
+ *ret_value = int128_make64(old_value);
77
- [CSR_MINSTRET] = { any, read_instret },
122
+ }
78
- [CSR_MCYCLEH] = { any32, read_instreth },
123
+ return ret;
79
- [CSR_MINSTRETH] = { any32, read_instreth },
124
+}
80
+ [CSR_MCYCLE] = { "mcycle", any, read_instret },
81
+ [CSR_MINSTRET] = { "minstret", any, read_instret },
82
+ [CSR_MCYCLEH] = { "mcycleh", any32, read_instreth },
83
+ [CSR_MINSTRETH] = { "minstreth", any32, read_instreth },
84
85
/* Machine Information Registers */
86
- [CSR_MVENDORID] = { any, read_zero },
87
- [CSR_MARCHID] = { any, read_zero },
88
- [CSR_MIMPID] = { any, read_zero },
89
- [CSR_MHARTID] = { any, read_mhartid },
90
+ [CSR_MVENDORID] = { "mvendorid", any, read_zero },
91
+ [CSR_MARCHID] = { "marchid", any, read_zero },
92
+ [CSR_MIMPID] = { "mimpid", any, read_zero },
93
+ [CSR_MHARTID] = { "mhartid", any, read_mhartid },
94
95
/* Machine Trap Setup */
96
- [CSR_MSTATUS] = { any, read_mstatus, write_mstatus },
97
- [CSR_MISA] = { any, read_misa, write_misa },
98
- [CSR_MIDELEG] = { any, read_mideleg, write_mideleg },
99
- [CSR_MEDELEG] = { any, read_medeleg, write_medeleg },
100
- [CSR_MIE] = { any, read_mie, write_mie },
101
- [CSR_MTVEC] = { any, read_mtvec, write_mtvec },
102
- [CSR_MCOUNTEREN] = { any, read_mcounteren, write_mcounteren },
103
+ [CSR_MSTATUS] = { "mstatus", any, read_mstatus, write_mstatus },
104
+ [CSR_MISA] = { "misa", any, read_misa, write_misa },
105
+ [CSR_MIDELEG] = { "mideleg", any, read_mideleg, write_mideleg },
106
+ [CSR_MEDELEG] = { "medeleg", any, read_medeleg, write_medeleg },
107
+ [CSR_MIE] = { "mie", any, read_mie, write_mie },
108
+ [CSR_MTVEC] = { "mtvec", any, read_mtvec, write_mtvec },
109
+ [CSR_MCOUNTEREN] = { "mcounteren", any, read_mcounteren, write_mcounteren },
110
111
- [CSR_MSTATUSH] = { any32, read_mstatush, write_mstatush },
112
+ [CSR_MSTATUSH] = { "mstatush", any32, read_mstatush, write_mstatush },
113
114
- [CSR_MSCOUNTEREN] = { any, read_mscounteren, write_mscounteren },
115
+ [CSR_MSCOUNTEREN] = { "msounteren", any, read_mscounteren, write_mscounteren },
116
117
/* Machine Trap Handling */
118
- [CSR_MSCRATCH] = { any, read_mscratch, write_mscratch },
119
- [CSR_MEPC] = { any, read_mepc, write_mepc },
120
- [CSR_MCAUSE] = { any, read_mcause, write_mcause },
121
- [CSR_MBADADDR] = { any, read_mbadaddr, write_mbadaddr },
122
- [CSR_MIP] = { any, NULL, NULL, rmw_mip },
123
+ [CSR_MSCRATCH] = { "mscratch", any, read_mscratch, write_mscratch },
124
+ [CSR_MEPC] = { "mepc", any, read_mepc, write_mepc },
125
+ [CSR_MCAUSE] = { "mcause", any, read_mcause, write_mcause },
126
+ [CSR_MBADADDR] = { "mbadaddr", any, read_mbadaddr, write_mbadaddr },
127
+ [CSR_MIP] = { "mip", any, NULL, NULL, rmw_mip },
128
129
/* Supervisor Trap Setup */
130
- [CSR_SSTATUS] = { smode, read_sstatus, write_sstatus },
131
- [CSR_SIE] = { smode, read_sie, write_sie },
132
- [CSR_STVEC] = { smode, read_stvec, write_stvec },
133
- [CSR_SCOUNTEREN] = { smode, read_scounteren, write_scounteren },
134
+ [CSR_SSTATUS] = { "sstatus", smode, read_sstatus, write_sstatus },
135
+ [CSR_SIE] = { "sie", smode, read_sie, write_sie },
136
+ [CSR_STVEC] = { "stvec", smode, read_stvec, write_stvec },
137
+ [CSR_SCOUNTEREN] = { "scounteren", smode, read_scounteren, write_scounteren },
138
139
/* Supervisor Trap Handling */
140
- [CSR_SSCRATCH] = { smode, read_sscratch, write_sscratch },
141
- [CSR_SEPC] = { smode, read_sepc, write_sepc },
142
- [CSR_SCAUSE] = { smode, read_scause, write_scause },
143
- [CSR_SBADADDR] = { smode, read_sbadaddr, write_sbadaddr },
144
- [CSR_SIP] = { smode, NULL, NULL, rmw_sip },
145
+ [CSR_SSCRATCH] = { "sscratch", smode, read_sscratch, write_sscratch },
146
+ [CSR_SEPC] = { "sepc", smode, read_sepc, write_sepc },
147
+ [CSR_SCAUSE] = { "scause", smode, read_scause, write_scause },
148
+ [CSR_SBADADDR] = { "sbadaddr", smode, read_sbadaddr, write_sbadaddr },
149
+ [CSR_SIP] = { "sip", smode, NULL, NULL, rmw_sip },
150
151
/* Supervisor Protection and Translation */
152
- [CSR_SATP] = { smode, read_satp, write_satp },
153
-
154
- [CSR_HSTATUS] = { hmode, read_hstatus, write_hstatus },
155
- [CSR_HEDELEG] = { hmode, read_hedeleg, write_hedeleg },
156
- [CSR_HIDELEG] = { hmode, read_hideleg, write_hideleg },
157
- [CSR_HVIP] = { hmode, NULL, NULL, rmw_hvip },
158
- [CSR_HIP] = { hmode, NULL, NULL, rmw_hip },
159
- [CSR_HIE] = { hmode, read_hie, write_hie },
160
- [CSR_HCOUNTEREN] = { hmode, read_hcounteren, write_hcounteren },
161
- [CSR_HGEIE] = { hmode, read_hgeie, write_hgeie },
162
- [CSR_HTVAL] = { hmode, read_htval, write_htval },
163
- [CSR_HTINST] = { hmode, read_htinst, write_htinst },
164
- [CSR_HGEIP] = { hmode, read_hgeip, write_hgeip },
165
- [CSR_HGATP] = { hmode, read_hgatp, write_hgatp },
166
- [CSR_HTIMEDELTA] = { hmode, read_htimedelta, write_htimedelta },
167
- [CSR_HTIMEDELTAH] = { hmode32, read_htimedeltah, write_htimedeltah},
168
-
169
- [CSR_VSSTATUS] = { hmode, read_vsstatus, write_vsstatus },
170
- [CSR_VSIP] = { hmode, NULL, NULL, rmw_vsip },
171
- [CSR_VSIE] = { hmode, read_vsie, write_vsie },
172
- [CSR_VSTVEC] = { hmode, read_vstvec, write_vstvec },
173
- [CSR_VSSCRATCH] = { hmode, read_vsscratch, write_vsscratch },
174
- [CSR_VSEPC] = { hmode, read_vsepc, write_vsepc },
175
- [CSR_VSCAUSE] = { hmode, read_vscause, write_vscause },
176
- [CSR_VSTVAL] = { hmode, read_vstval, write_vstval },
177
- [CSR_VSATP] = { hmode, read_vsatp, write_vsatp },
178
-
179
- [CSR_MTVAL2] = { hmode, read_mtval2, write_mtval2 },
180
- [CSR_MTINST] = { hmode, read_mtinst, write_mtinst },
181
+ [CSR_SATP] = { "satp", smode, read_satp, write_satp },
182
+
125
+
183
+ [CSR_HSTATUS] = { "hstatus", hmode, read_hstatus, write_hstatus },
126
RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno,
184
+ [CSR_HEDELEG] = { "hedeleg", hmode, read_hedeleg, write_hedeleg },
127
Int128 *ret_value,
185
+ [CSR_HIDELEG] = { "hideleg", hmode, read_hideleg, write_hideleg },
128
Int128 new_value, Int128 write_mask)
186
+ [CSR_HVIP] = { "hvip", hmode, NULL, NULL, rmw_hvip },
129
{
187
+ [CSR_HIP] = { "hip", hmode, NULL, NULL, rmw_hip },
130
RISCVException ret;
188
+ [CSR_HIE] = { "hie", hmode, read_hie, write_hie },
131
189
+ [CSR_HCOUNTEREN] = { "hcounteren", hmode, read_hcounteren, write_hcounteren },
132
- ret = riscv_csrrw_check(env, csrno, int128_nz(write_mask));
190
+ [CSR_HGEIE] = { "hgeie", hmode, read_hgeie, write_hgeie },
133
+ ret = riscv_csrrw_check(env, csrno, true);
191
+ [CSR_HTVAL] = { "htval", hmode, read_htval, write_htval },
134
if (ret != RISCV_EXCP_NONE) {
192
+ [CSR_HTINST] = { "htinst", hmode, read_htinst, write_htinst },
135
return ret;
193
+ [CSR_HGEIP] = { "hgeip", hmode, read_hgeip, write_hgeip },
136
}
194
+ [CSR_HGATP] = { "hgatp", hmode, read_hgatp, write_hgatp },
137
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
195
+ [CSR_HTIMEDELTA] = { "htimedelta", hmode, read_htimedelta, write_htimedelta },
138
index XXXXXXX..XXXXXXX 100644
196
+ [CSR_HTIMEDELTAH] = { "htimedeltah", hmode32, read_htimedeltah, write_htimedeltah },
139
--- a/target/riscv/op_helper.c
197
+
140
+++ b/target/riscv/op_helper.c
198
+ [CSR_VSSTATUS] = { "vsstatus", hmode, read_vsstatus, write_vsstatus },
141
@@ -XXX,XX +XXX,XX @@ target_ulong helper_csrr(CPURISCVState *env, int csr)
199
+ [CSR_VSIP] = { "vsip", hmode, NULL, NULL, rmw_vsip },
142
}
200
+ [CSR_VSIE] = { "vsie", hmode, read_vsie, write_vsie },
143
201
+ [CSR_VSTVEC] = { "vstvec", hmode, read_vstvec, write_vstvec },
144
target_ulong val = 0;
202
+ [CSR_VSSCRATCH] = { "vsscratch", hmode, read_vsscratch, write_vsscratch },
145
- RISCVException ret = riscv_csrrw(env, csr, &val, 0, 0);
203
+ [CSR_VSEPC] = { "vsepc", hmode, read_vsepc, write_vsepc },
146
+ RISCVException ret = riscv_csrr(env, csr, &val);
204
+ [CSR_VSCAUSE] = { "vscause", hmode, read_vscause, write_vscause },
147
205
+ [CSR_VSTVAL] = { "vstval", hmode, read_vstval, write_vstval },
148
if (ret != RISCV_EXCP_NONE) {
206
+ [CSR_VSATP] = { "vsatp", hmode, read_vsatp, write_vsatp },
149
riscv_raise_exception(env, ret, GETPC());
207
+
150
@@ -XXX,XX +XXX,XX @@ target_ulong helper_csrrw(CPURISCVState *env, int csr,
208
+ [CSR_MTVAL2] = { "mtval2", hmode, read_mtval2, write_mtval2 },
151
target_ulong helper_csrr_i128(CPURISCVState *env, int csr)
209
+ [CSR_MTINST] = { "mtinst", hmode, read_mtinst, write_mtinst },
152
{
210
153
Int128 rv = int128_zero();
211
/* Physical Memory Protection */
154
- RISCVException ret = riscv_csrrw_i128(env, csr, &rv,
212
- [CSR_PMPCFG0 ... CSR_PMPCFG3] = { pmp, read_pmpcfg, write_pmpcfg },
155
- int128_zero(),
213
- [CSR_PMPADDR0 ... CSR_PMPADDR15] = { pmp, read_pmpaddr, write_pmpaddr },
156
- int128_zero());
214
+ [CSR_PMPCFG0] = { "pmpcfg0", pmp, read_pmpcfg, write_pmpcfg },
157
+ RISCVException ret = riscv_csrr_i128(env, csr, &rv);
215
+ [CSR_PMPCFG1] = { "pmpcfg1", pmp, read_pmpcfg, write_pmpcfg },
158
216
+ [CSR_PMPCFG2] = { "pmpcfg2", pmp, read_pmpcfg, write_pmpcfg },
159
if (ret != RISCV_EXCP_NONE) {
217
+ [CSR_PMPCFG3] = { "pmpcfg3", pmp, read_pmpcfg, write_pmpcfg },
160
riscv_raise_exception(env, ret, GETPC());
218
+ [CSR_PMPADDR0] = { "pmpaddr0", pmp, read_pmpaddr, write_pmpaddr },
219
+ [CSR_PMPADDR1] = { "pmpaddr1", pmp, read_pmpaddr, write_pmpaddr },
220
+ [CSR_PMPADDR2] = { "pmpaddr2", pmp, read_pmpaddr, write_pmpaddr },
221
+ [CSR_PMPADDR3] = { "pmpaddr3", pmp, read_pmpaddr, write_pmpaddr },
222
+ [CSR_PMPADDR4] = { "pmpaddr4", pmp, read_pmpaddr, write_pmpaddr },
223
+ [CSR_PMPADDR5] = { "pmpaddr5", pmp, read_pmpaddr, write_pmpaddr },
224
+ [CSR_PMPADDR6] = { "pmpaddr6", pmp, read_pmpaddr, write_pmpaddr },
225
+ [CSR_PMPADDR7] = { "pmpaddr7", pmp, read_pmpaddr, write_pmpaddr },
226
+ [CSR_PMPADDR8] = { "pmpaddr8", pmp, read_pmpaddr, write_pmpaddr },
227
+ [CSR_PMPADDR9] = { "pmpaddr9", pmp, read_pmpaddr, write_pmpaddr },
228
+ [CSR_PMPADDR10] = { "pmpaddr10", pmp, read_pmpaddr, write_pmpaddr },
229
+ [CSR_PMPADDR11] = { "pmpaddr11", pmp, read_pmpaddr, write_pmpaddr },
230
+ [CSR_PMPADDR12] = { "pmpaddr12", pmp, read_pmpaddr, write_pmpaddr },
231
+ [CSR_PMPADDR13] = { "pmpaddr13", pmp, read_pmpaddr, write_pmpaddr },
232
+ [CSR_PMPADDR14] = { "pmpaddr14", pmp, read_pmpaddr, write_pmpaddr },
233
+ [CSR_PMPADDR15] = { "pmpaddr15", pmp, read_pmpaddr, write_pmpaddr },
234
235
/* Performance Counters */
236
- [CSR_HPMCOUNTER3 ... CSR_HPMCOUNTER31] = { ctr, read_zero },
237
- [CSR_MHPMCOUNTER3 ... CSR_MHPMCOUNTER31] = { any, read_zero },
238
- [CSR_MHPMEVENT3 ... CSR_MHPMEVENT31] = { any, read_zero },
239
- [CSR_HPMCOUNTER3H ... CSR_HPMCOUNTER31H] = { ctr32, read_zero },
240
- [CSR_MHPMCOUNTER3H ... CSR_MHPMCOUNTER31H] = { any32, read_zero },
241
+ [CSR_HPMCOUNTER3] = { "hpmcounter3", ctr, read_zero },
242
+ [CSR_HPMCOUNTER4] = { "hpmcounter4", ctr, read_zero },
243
+ [CSR_HPMCOUNTER5] = { "hpmcounter5", ctr, read_zero },
244
+ [CSR_HPMCOUNTER6] = { "hpmcounter6", ctr, read_zero },
245
+ [CSR_HPMCOUNTER7] = { "hpmcounter7", ctr, read_zero },
246
+ [CSR_HPMCOUNTER8] = { "hpmcounter8", ctr, read_zero },
247
+ [CSR_HPMCOUNTER9] = { "hpmcounter9", ctr, read_zero },
248
+ [CSR_HPMCOUNTER10] = { "hpmcounter10", ctr, read_zero },
249
+ [CSR_HPMCOUNTER11] = { "hpmcounter11", ctr, read_zero },
250
+ [CSR_HPMCOUNTER12] = { "hpmcounter12", ctr, read_zero },
251
+ [CSR_HPMCOUNTER13] = { "hpmcounter13", ctr, read_zero },
252
+ [CSR_HPMCOUNTER14] = { "hpmcounter14", ctr, read_zero },
253
+ [CSR_HPMCOUNTER15] = { "hpmcounter15", ctr, read_zero },
254
+ [CSR_HPMCOUNTER16] = { "hpmcounter16", ctr, read_zero },
255
+ [CSR_HPMCOUNTER17] = { "hpmcounter17", ctr, read_zero },
256
+ [CSR_HPMCOUNTER18] = { "hpmcounter18", ctr, read_zero },
257
+ [CSR_HPMCOUNTER19] = { "hpmcounter19", ctr, read_zero },
258
+ [CSR_HPMCOUNTER20] = { "hpmcounter20", ctr, read_zero },
259
+ [CSR_HPMCOUNTER21] = { "hpmcounter21", ctr, read_zero },
260
+ [CSR_HPMCOUNTER22] = { "hpmcounter22", ctr, read_zero },
261
+ [CSR_HPMCOUNTER23] = { "hpmcounter23", ctr, read_zero },
262
+ [CSR_HPMCOUNTER24] = { "hpmcounter24", ctr, read_zero },
263
+ [CSR_HPMCOUNTER25] = { "hpmcounter25", ctr, read_zero },
264
+ [CSR_HPMCOUNTER26] = { "hpmcounter26", ctr, read_zero },
265
+ [CSR_HPMCOUNTER27] = { "hpmcounter27", ctr, read_zero },
266
+ [CSR_HPMCOUNTER28] = { "hpmcounter28", ctr, read_zero },
267
+ [CSR_HPMCOUNTER29] = { "hpmcounter29", ctr, read_zero },
268
+ [CSR_HPMCOUNTER30] = { "hpmcounter30", ctr, read_zero },
269
+ [CSR_HPMCOUNTER31] = { "hpmcounter31", ctr, read_zero },
270
+
271
+ [CSR_MHPMCOUNTER3] = { "mhpmcounter3", any, read_zero },
272
+ [CSR_MHPMCOUNTER4] = { "mhpmcounter4", any, read_zero },
273
+ [CSR_MHPMCOUNTER5] = { "mhpmcounter5", any, read_zero },
274
+ [CSR_MHPMCOUNTER6] = { "mhpmcounter6", any, read_zero },
275
+ [CSR_MHPMCOUNTER7] = { "mhpmcounter7", any, read_zero },
276
+ [CSR_MHPMCOUNTER8] = { "mhpmcounter8", any, read_zero },
277
+ [CSR_MHPMCOUNTER9] = { "mhpmcounter9", any, read_zero },
278
+ [CSR_MHPMCOUNTER10] = { "mhpmcounter10", any, read_zero },
279
+ [CSR_MHPMCOUNTER11] = { "mhpmcounter11", any, read_zero },
280
+ [CSR_MHPMCOUNTER12] = { "mhpmcounter12", any, read_zero },
281
+ [CSR_MHPMCOUNTER13] = { "mhpmcounter13", any, read_zero },
282
+ [CSR_MHPMCOUNTER14] = { "mhpmcounter14", any, read_zero },
283
+ [CSR_MHPMCOUNTER15] = { "mhpmcounter15", any, read_zero },
284
+ [CSR_MHPMCOUNTER16] = { "mhpmcounter16", any, read_zero },
285
+ [CSR_MHPMCOUNTER17] = { "mhpmcounter17", any, read_zero },
286
+ [CSR_MHPMCOUNTER18] = { "mhpmcounter18", any, read_zero },
287
+ [CSR_MHPMCOUNTER19] = { "mhpmcounter19", any, read_zero },
288
+ [CSR_MHPMCOUNTER20] = { "mhpmcounter20", any, read_zero },
289
+ [CSR_MHPMCOUNTER21] = { "mhpmcounter21", any, read_zero },
290
+ [CSR_MHPMCOUNTER22] = { "mhpmcounter22", any, read_zero },
291
+ [CSR_MHPMCOUNTER23] = { "mhpmcounter23", any, read_zero },
292
+ [CSR_MHPMCOUNTER24] = { "mhpmcounter24", any, read_zero },
293
+ [CSR_MHPMCOUNTER25] = { "mhpmcounter25", any, read_zero },
294
+ [CSR_MHPMCOUNTER26] = { "mhpmcounter26", any, read_zero },
295
+ [CSR_MHPMCOUNTER27] = { "mhpmcounter27", any, read_zero },
296
+ [CSR_MHPMCOUNTER28] = { "mhpmcounter28", any, read_zero },
297
+ [CSR_MHPMCOUNTER29] = { "mhpmcounter29", any, read_zero },
298
+ [CSR_MHPMCOUNTER30] = { "mhpmcounter30", any, read_zero },
299
+ [CSR_MHPMCOUNTER31] = { "mhpmcounter31", any, read_zero },
300
+
301
+ [CSR_MHPMEVENT3] = { "mhpmevent3", any, read_zero },
302
+ [CSR_MHPMEVENT4] = { "mhpmevent4", any, read_zero },
303
+ [CSR_MHPMEVENT5] = { "mhpmevent5", any, read_zero },
304
+ [CSR_MHPMEVENT6] = { "mhpmevent6", any, read_zero },
305
+ [CSR_MHPMEVENT7] = { "mhpmevent7", any, read_zero },
306
+ [CSR_MHPMEVENT8] = { "mhpmevent8", any, read_zero },
307
+ [CSR_MHPMEVENT9] = { "mhpmevent9", any, read_zero },
308
+ [CSR_MHPMEVENT10] = { "mhpmevent10", any, read_zero },
309
+ [CSR_MHPMEVENT11] = { "mhpmevent11", any, read_zero },
310
+ [CSR_MHPMEVENT12] = { "mhpmevent12", any, read_zero },
311
+ [CSR_MHPMEVENT13] = { "mhpmevent13", any, read_zero },
312
+ [CSR_MHPMEVENT14] = { "mhpmevent14", any, read_zero },
313
+ [CSR_MHPMEVENT15] = { "mhpmevent15", any, read_zero },
314
+ [CSR_MHPMEVENT16] = { "mhpmevent16", any, read_zero },
315
+ [CSR_MHPMEVENT17] = { "mhpmevent17", any, read_zero },
316
+ [CSR_MHPMEVENT18] = { "mhpmevent18", any, read_zero },
317
+ [CSR_MHPMEVENT19] = { "mhpmevent19", any, read_zero },
318
+ [CSR_MHPMEVENT20] = { "mhpmevent20", any, read_zero },
319
+ [CSR_MHPMEVENT21] = { "mhpmevent21", any, read_zero },
320
+ [CSR_MHPMEVENT22] = { "mhpmevent22", any, read_zero },
321
+ [CSR_MHPMEVENT23] = { "mhpmevent23", any, read_zero },
322
+ [CSR_MHPMEVENT24] = { "mhpmevent24", any, read_zero },
323
+ [CSR_MHPMEVENT25] = { "mhpmevent25", any, read_zero },
324
+ [CSR_MHPMEVENT26] = { "mhpmevent26", any, read_zero },
325
+ [CSR_MHPMEVENT27] = { "mhpmevent27", any, read_zero },
326
+ [CSR_MHPMEVENT28] = { "mhpmevent28", any, read_zero },
327
+ [CSR_MHPMEVENT29] = { "mhpmevent29", any, read_zero },
328
+ [CSR_MHPMEVENT30] = { "mhpmevent30", any, read_zero },
329
+ [CSR_MHPMEVENT31] = { "mhpmevent31", any, read_zero },
330
+
331
+ [CSR_HPMCOUNTER3H] = { "hpmcounter3h", ctr32, read_zero },
332
+ [CSR_HPMCOUNTER4H] = { "hpmcounter4h", ctr32, read_zero },
333
+ [CSR_HPMCOUNTER5H] = { "hpmcounter5h", ctr32, read_zero },
334
+ [CSR_HPMCOUNTER6H] = { "hpmcounter6h", ctr32, read_zero },
335
+ [CSR_HPMCOUNTER7H] = { "hpmcounter7h", ctr32, read_zero },
336
+ [CSR_HPMCOUNTER8H] = { "hpmcounter8h", ctr32, read_zero },
337
+ [CSR_HPMCOUNTER9H] = { "hpmcounter9h", ctr32, read_zero },
338
+ [CSR_HPMCOUNTER10H] = { "hpmcounter10h", ctr32, read_zero },
339
+ [CSR_HPMCOUNTER11H] = { "hpmcounter11h", ctr32, read_zero },
340
+ [CSR_HPMCOUNTER12H] = { "hpmcounter12h", ctr32, read_zero },
341
+ [CSR_HPMCOUNTER13H] = { "hpmcounter13h", ctr32, read_zero },
342
+ [CSR_HPMCOUNTER14H] = { "hpmcounter14h", ctr32, read_zero },
343
+ [CSR_HPMCOUNTER15H] = { "hpmcounter15h", ctr32, read_zero },
344
+ [CSR_HPMCOUNTER16H] = { "hpmcounter16h", ctr32, read_zero },
345
+ [CSR_HPMCOUNTER17H] = { "hpmcounter17h", ctr32, read_zero },
346
+ [CSR_HPMCOUNTER18H] = { "hpmcounter18h", ctr32, read_zero },
347
+ [CSR_HPMCOUNTER19H] = { "hpmcounter19h", ctr32, read_zero },
348
+ [CSR_HPMCOUNTER20H] = { "hpmcounter20h", ctr32, read_zero },
349
+ [CSR_HPMCOUNTER21H] = { "hpmcounter21h", ctr32, read_zero },
350
+ [CSR_HPMCOUNTER22H] = { "hpmcounter22h", ctr32, read_zero },
351
+ [CSR_HPMCOUNTER23H] = { "hpmcounter23h", ctr32, read_zero },
352
+ [CSR_HPMCOUNTER24H] = { "hpmcounter24h", ctr32, read_zero },
353
+ [CSR_HPMCOUNTER25H] = { "hpmcounter25h", ctr32, read_zero },
354
+ [CSR_HPMCOUNTER26H] = { "hpmcounter26h", ctr32, read_zero },
355
+ [CSR_HPMCOUNTER27H] = { "hpmcounter27h", ctr32, read_zero },
356
+ [CSR_HPMCOUNTER28H] = { "hpmcounter28h", ctr32, read_zero },
357
+ [CSR_HPMCOUNTER29H] = { "hpmcounter29h", ctr32, read_zero },
358
+ [CSR_HPMCOUNTER30H] = { "hpmcounter30h", ctr32, read_zero },
359
+ [CSR_HPMCOUNTER31H] = { "hpmcounter31h", ctr32, read_zero },
360
+
361
+ [CSR_MHPMCOUNTER3H] = { "mhpmcounter3h", any32, read_zero },
362
+ [CSR_MHPMCOUNTER4H] = { "mhpmcounter4h", any32, read_zero },
363
+ [CSR_MHPMCOUNTER5H] = { "mhpmcounter5h", any32, read_zero },
364
+ [CSR_MHPMCOUNTER6H] = { "mhpmcounter6h", any32, read_zero },
365
+ [CSR_MHPMCOUNTER7H] = { "mhpmcounter7h", any32, read_zero },
366
+ [CSR_MHPMCOUNTER8H] = { "mhpmcounter8h", any32, read_zero },
367
+ [CSR_MHPMCOUNTER9H] = { "mhpmcounter9h", any32, read_zero },
368
+ [CSR_MHPMCOUNTER10H] = { "mhpmcounter10h", any32, read_zero },
369
+ [CSR_MHPMCOUNTER11H] = { "mhpmcounter11h", any32, read_zero },
370
+ [CSR_MHPMCOUNTER12H] = { "mhpmcounter12h", any32, read_zero },
371
+ [CSR_MHPMCOUNTER13H] = { "mhpmcounter13h", any32, read_zero },
372
+ [CSR_MHPMCOUNTER14H] = { "mhpmcounter14h", any32, read_zero },
373
+ [CSR_MHPMCOUNTER15H] = { "mhpmcounter15h", any32, read_zero },
374
+ [CSR_MHPMCOUNTER16H] = { "mhpmcounter16h", any32, read_zero },
375
+ [CSR_MHPMCOUNTER17H] = { "mhpmcounter17h", any32, read_zero },
376
+ [CSR_MHPMCOUNTER18H] = { "mhpmcounter18h", any32, read_zero },
377
+ [CSR_MHPMCOUNTER19H] = { "mhpmcounter19h", any32, read_zero },
378
+ [CSR_MHPMCOUNTER20H] = { "mhpmcounter20h", any32, read_zero },
379
+ [CSR_MHPMCOUNTER21H] = { "mhpmcounter21h", any32, read_zero },
380
+ [CSR_MHPMCOUNTER22H] = { "mhpmcounter22h", any32, read_zero },
381
+ [CSR_MHPMCOUNTER23H] = { "mhpmcounter23h", any32, read_zero },
382
+ [CSR_MHPMCOUNTER24H] = { "mhpmcounter24h", any32, read_zero },
383
+ [CSR_MHPMCOUNTER25H] = { "mhpmcounter25h", any32, read_zero },
384
+ [CSR_MHPMCOUNTER26H] = { "mhpmcounter26h", any32, read_zero },
385
+ [CSR_MHPMCOUNTER27H] = { "mhpmcounter27h", any32, read_zero },
386
+ [CSR_MHPMCOUNTER28H] = { "mhpmcounter28h", any32, read_zero },
387
+ [CSR_MHPMCOUNTER29H] = { "mhpmcounter29h", any32, read_zero },
388
+ [CSR_MHPMCOUNTER30H] = { "mhpmcounter30h", any32, read_zero },
389
+ [CSR_MHPMCOUNTER31H] = { "mhpmcounter31h", any32, read_zero },
390
#endif /* !CONFIG_USER_ONLY */
391
};
392
--
161
--
393
2.29.2
162
2.45.1
394
395
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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