| 1 | The following changes since commit 825a215c003cd028e26c7d19aa5049d957345f43: | 1 | From: Alistair Francis <alistair.francis@wdc.com> |
|---|---|---|---|
| 2 | 2 | ||
| 3 | Merge remote-tracking branch 'remotes/kraxel/tags/audio-20210115-pull-request' into staging (2021-01-15 22:21:21 +0000) | 3 | The following changes since commit c5fbdd60cf1fb52f01bdfe342b6fa65d5343e1b1: |
| 4 | |||
| 5 | Merge tag 'qemu-sparc-20211121' of git://github.com/mcayland/qemu into staging (2021-11-21 14:12:25 +0100) | ||
| 4 | 6 | ||
| 5 | are available in the Git repository at: | 7 | are available in the Git repository at: |
| 6 | 8 | ||
| 7 | git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20210117-3 | 9 | git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20211122 |
| 8 | 10 | ||
| 9 | for you to fetch changes up to a8259b53230782f5e0a0d66013655c4ed5d71b7e: | 11 | for you to fetch changes up to 526e7443027c71fe7b04c29df529e1f9f425f9e3: |
| 10 | 12 | ||
| 11 | riscv: Pass RISCVHartArrayState by pointer (2021-01-16 14:34:46 -0800) | 13 | hw/misc/sifive_u_otp: Do not reset OTP content on hardware reset (2021-11-22 10:46:22 +1000) |
| 12 | 14 | ||
| 13 | ---------------------------------------------------------------- | 15 | ---------------------------------------------------------------- |
| 14 | First RISC-V PR for 6.0 | 16 | Seventh RISC-V PR for QEMU 6.2 |
| 15 | 17 | ||
| 16 | This PR: | 18 | - Deprecate IF_NONE for SiFive OTP |
| 17 | - Fixes some issues with the m25p80 | 19 | - Don't reset SiFive OTP content |
| 18 | - Improves GDB support for RISC-V | ||
| 19 | - Fixes some Linux boot issues, specifiaclly 32-bit boot failures | ||
| 20 | - Enforces PMP exceptions correctly | ||
| 21 | - Fixes some Coverity issues | ||
| 22 | 20 | ||
| 23 | ---------------------------------------------------------------- | 21 | ---------------------------------------------------------------- |
| 24 | Alistair Francis (1): | 22 | Philippe Mathieu-Daudé (1): |
| 25 | riscv: Pass RISCVHartArrayState by pointer | 23 | hw/misc/sifive_u_otp: Do not reset OTP content on hardware reset |
| 26 | 24 | ||
| 27 | Atish Patra (2): | 25 | Thomas Huth (1): |
| 28 | RISC-V: Place DTB at 3GB boundary instead of 4GB | 26 | hw/misc/sifive_u_otp: Use IF_PFLASH for the OTP device instead of IF_NONE |
| 29 | target/riscv/pmp: Raise exception if no PMP entry is configured | ||
| 30 | 27 | ||
| 31 | Bin Meng (6): | 28 | docs/about/deprecated.rst | 6 ++++++ |
| 32 | hw/block: m25p80: Don't write to flash if write is disabled | 29 | hw/misc/sifive_u_otp.c | 22 +++++++++++++--------- |
| 33 | hw/riscv: sifive_u: Use SIFIVE_U_CPU for mc->default_cpu_type | 30 | 2 files changed, 19 insertions(+), 9 deletions(-) |
| 34 | target/riscv: Make csr_ops[CSR_TABLE_SIZE] external | ||
| 35 | target/riscv: Add CSR name in the CSR function table | ||
| 36 | target/riscv: Generate the GDB XML file for CSR registers dynamically | ||
| 37 | target/riscv: Remove built-in GDB XML files for CSRs | ||
| 38 | 31 | ||
| 39 | Green Wan (1): | ||
| 40 | hw/misc/sifive_u_otp: handling the fails of blk_pread and blk_pwrite | ||
| 41 | |||
| 42 | Sylvain Pelissier (1): | ||
| 43 | gdb: riscv: Add target description | ||
| 44 | |||
| 45 | Xuzhou Cheng (1): | ||
| 46 | hw/block: m25p80: Implement AAI-WP command support for SST flashes | ||
| 47 | |||
| 48 | default-configs/targets/riscv32-linux-user.mak | 2 +- | ||
| 49 | default-configs/targets/riscv32-softmmu.mak | 2 +- | ||
| 50 | default-configs/targets/riscv64-linux-user.mak | 2 +- | ||
| 51 | default-configs/targets/riscv64-softmmu.mak | 2 +- | ||
| 52 | include/hw/riscv/boot.h | 6 +- | ||
| 53 | target/riscv/cpu.h | 11 + | ||
| 54 | target/riscv/pmp.h | 1 + | ||
| 55 | hw/block/m25p80.c | 74 ++++++ | ||
| 56 | hw/misc/sifive_u_otp.c | 31 ++- | ||
| 57 | hw/riscv/boot.c | 18 +- | ||
| 58 | hw/riscv/sifive_u.c | 16 +- | ||
| 59 | hw/riscv/spike.c | 8 +- | ||
| 60 | hw/riscv/virt.c | 8 +- | ||
| 61 | target/riscv/cpu.c | 25 ++ | ||
| 62 | target/riscv/csr.c | 342 ++++++++++++++++++------- | ||
| 63 | target/riscv/gdbstub.c | 308 ++++------------------ | ||
| 64 | target/riscv/op_helper.c | 5 + | ||
| 65 | target/riscv/pmp.c | 4 +- | ||
| 66 | gdb-xml/riscv-32bit-csr.xml | 250 ------------------ | ||
| 67 | gdb-xml/riscv-64bit-csr.xml | 250 ------------------ | ||
| 68 | 20 files changed, 463 insertions(+), 902 deletions(-) | ||
| 69 | delete mode 100644 gdb-xml/riscv-32bit-csr.xml | ||
| 70 | delete mode 100644 gdb-xml/riscv-64bit-csr.xml | ||
| 71 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | From: Bin Meng <bin.meng@windriver.com> | ||
| 2 | 1 | ||
| 3 | When write is disabled, the write to flash should be avoided | ||
| 4 | in flash_write8(). | ||
| 5 | |||
| 6 | Fixes: 82a2499011a7 ("m25p80: Initial implementation of SPI flash device") | ||
| 7 | Signed-off-by: Bin Meng <bin.meng@windriver.com> | ||
| 8 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
| 9 | Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com> | ||
| 10 | Message-id: 1608688825-81519-1-git-send-email-bmeng.cn@gmail.com | ||
| 11 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 12 | --- | ||
| 13 | hw/block/m25p80.c | 1 + | ||
| 14 | 1 file changed, 1 insertion(+) | ||
| 15 | |||
| 16 | diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c | ||
| 17 | index XXXXXXX..XXXXXXX 100644 | ||
| 18 | --- a/hw/block/m25p80.c | ||
| 19 | +++ b/hw/block/m25p80.c | ||
| 20 | @@ -XXX,XX +XXX,XX @@ void flash_write8(Flash *s, uint32_t addr, uint8_t data) | ||
| 21 | |||
| 22 | if (!s->write_enable) { | ||
| 23 | qemu_log_mask(LOG_GUEST_ERROR, "M25P80: write with write protect!\n"); | ||
| 24 | + return; | ||
| 25 | } | ||
| 26 | |||
| 27 | if ((prev ^ data) & data) { | ||
| 28 | -- | ||
| 29 | 2.29.2 | ||
| 30 | |||
| 31 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | From: Xuzhou Cheng <xuzhou.cheng@windriver.com> | ||
| 2 | 1 | ||
| 3 | Auto Address Increment (AAI) Word-Program is a special command of | ||
| 4 | SST flashes. AAI-WP allows multiple bytes of data to be programmed | ||
| 5 | without re-issuing the next sequential address location. | ||
| 6 | |||
| 7 | Signed-off-by: Xuzhou Cheng <xuzhou.cheng@windriver.com> | ||
| 8 | Signed-off-by: Bin Meng <bin.meng@windriver.com> | ||
| 9 | Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com> | ||
| 10 | Message-id: 1608688825-81519-2-git-send-email-bmeng.cn@gmail.com | ||
| 11 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 12 | --- | ||
| 13 | hw/block/m25p80.c | 73 +++++++++++++++++++++++++++++++++++++++++++++++ | ||
| 14 | 1 file changed, 73 insertions(+) | ||
| 15 | |||
| 16 | diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c | ||
| 17 | index XXXXXXX..XXXXXXX 100644 | ||
| 18 | --- a/hw/block/m25p80.c | ||
| 19 | +++ b/hw/block/m25p80.c | ||
| 20 | @@ -XXX,XX +XXX,XX @@ typedef enum { | ||
| 21 | QPP_4 = 0x34, | ||
| 22 | RDID_90 = 0x90, | ||
| 23 | RDID_AB = 0xab, | ||
| 24 | + AAI_WP = 0xad, | ||
| 25 | |||
| 26 | ERASE_4K = 0x20, | ||
| 27 | ERASE4_4K = 0x21, | ||
| 28 | @@ -XXX,XX +XXX,XX @@ struct Flash { | ||
| 29 | bool four_bytes_address_mode; | ||
| 30 | bool reset_enable; | ||
| 31 | bool quad_enable; | ||
| 32 | + bool aai_enable; | ||
| 33 | uint8_t ear; | ||
| 34 | |||
| 35 | int64_t dirty_page; | ||
| 36 | @@ -XXX,XX +XXX,XX @@ static void complete_collecting_data(Flash *s) | ||
| 37 | case PP4_4: | ||
| 38 | s->state = STATE_PAGE_PROGRAM; | ||
| 39 | break; | ||
| 40 | + case AAI_WP: | ||
| 41 | + /* AAI programming starts from the even address */ | ||
| 42 | + s->cur_addr &= ~BIT(0); | ||
| 43 | + s->state = STATE_PAGE_PROGRAM; | ||
| 44 | + break; | ||
| 45 | case READ: | ||
| 46 | case READ4: | ||
| 47 | case FAST_READ: | ||
| 48 | @@ -XXX,XX +XXX,XX @@ static void reset_memory(Flash *s) | ||
| 49 | s->write_enable = false; | ||
| 50 | s->reset_enable = false; | ||
| 51 | s->quad_enable = false; | ||
| 52 | + s->aai_enable = false; | ||
| 53 | |||
| 54 | switch (get_man(s)) { | ||
| 55 | case MAN_NUMONYX: | ||
| 56 | @@ -XXX,XX +XXX,XX @@ static void decode_qio_read_cmd(Flash *s) | ||
| 57 | s->state = STATE_COLLECTING_DATA; | ||
| 58 | } | ||
| 59 | |||
| 60 | +static bool is_valid_aai_cmd(uint32_t cmd) | ||
| 61 | +{ | ||
| 62 | + return cmd == AAI_WP || cmd == WRDI || cmd == RDSR; | ||
| 63 | +} | ||
| 64 | + | ||
| 65 | static void decode_new_cmd(Flash *s, uint32_t value) | ||
| 66 | { | ||
| 67 | int i; | ||
| 68 | @@ -XXX,XX +XXX,XX @@ static void decode_new_cmd(Flash *s, uint32_t value) | ||
| 69 | s->reset_enable = false; | ||
| 70 | } | ||
| 71 | |||
| 72 | + if (get_man(s) == MAN_SST && s->aai_enable && !is_valid_aai_cmd(value)) { | ||
| 73 | + qemu_log_mask(LOG_GUEST_ERROR, | ||
| 74 | + "M25P80: Invalid cmd within AAI programming sequence"); | ||
| 75 | + } | ||
| 76 | + | ||
| 77 | switch (value) { | ||
| 78 | |||
| 79 | case ERASE_4K: | ||
| 80 | @@ -XXX,XX +XXX,XX @@ static void decode_new_cmd(Flash *s, uint32_t value) | ||
| 81 | |||
| 82 | case WRDI: | ||
| 83 | s->write_enable = false; | ||
| 84 | + if (get_man(s) == MAN_SST) { | ||
| 85 | + s->aai_enable = false; | ||
| 86 | + } | ||
| 87 | break; | ||
| 88 | case WREN: | ||
| 89 | s->write_enable = true; | ||
| 90 | @@ -XXX,XX +XXX,XX @@ static void decode_new_cmd(Flash *s, uint32_t value) | ||
| 91 | if (get_man(s) == MAN_MACRONIX) { | ||
| 92 | s->data[0] |= (!!s->quad_enable) << 6; | ||
| 93 | } | ||
| 94 | + if (get_man(s) == MAN_SST) { | ||
| 95 | + s->data[0] |= (!!s->aai_enable) << 6; | ||
| 96 | + } | ||
| 97 | + | ||
| 98 | s->pos = 0; | ||
| 99 | s->len = 1; | ||
| 100 | s->data_read_loop = true; | ||
| 101 | @@ -XXX,XX +XXX,XX @@ static void decode_new_cmd(Flash *s, uint32_t value) | ||
| 102 | case RSTQIO: | ||
| 103 | s->quad_enable = false; | ||
| 104 | break; | ||
| 105 | + case AAI_WP: | ||
| 106 | + if (get_man(s) == MAN_SST) { | ||
| 107 | + if (s->write_enable) { | ||
| 108 | + if (s->aai_enable) { | ||
| 109 | + s->state = STATE_PAGE_PROGRAM; | ||
| 110 | + } else { | ||
| 111 | + s->aai_enable = true; | ||
| 112 | + s->needed_bytes = get_addr_length(s); | ||
| 113 | + s->state = STATE_COLLECTING_DATA; | ||
| 114 | + } | ||
| 115 | + } else { | ||
| 116 | + qemu_log_mask(LOG_GUEST_ERROR, | ||
| 117 | + "M25P80: AAI_WP with write protect\n"); | ||
| 118 | + } | ||
| 119 | + } else { | ||
| 120 | + qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Unknown cmd %x\n", value); | ||
| 121 | + } | ||
| 122 | + break; | ||
| 123 | default: | ||
| 124 | s->pos = 0; | ||
| 125 | s->len = 1; | ||
| 126 | @@ -XXX,XX +XXX,XX @@ static uint32_t m25p80_transfer8(SSIPeripheral *ss, uint32_t tx) | ||
| 127 | trace_m25p80_page_program(s, s->cur_addr, (uint8_t)tx); | ||
| 128 | flash_write8(s, s->cur_addr, (uint8_t)tx); | ||
| 129 | s->cur_addr = (s->cur_addr + 1) & (s->size - 1); | ||
| 130 | + | ||
| 131 | + if (get_man(s) == MAN_SST && s->aai_enable && s->cur_addr == 0) { | ||
| 132 | + /* | ||
| 133 | + * There is no wrap mode during AAI programming once the highest | ||
| 134 | + * unprotected memory address is reached. The Write-Enable-Latch | ||
| 135 | + * bit is automatically reset, and AAI programming mode aborts. | ||
| 136 | + */ | ||
| 137 | + s->write_enable = false; | ||
| 138 | + s->aai_enable = false; | ||
| 139 | + } | ||
| 140 | + | ||
| 141 | break; | ||
| 142 | |||
| 143 | case STATE_READ: | ||
| 144 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_m25p80_data_read_loop = { | ||
| 145 | } | ||
| 146 | }; | ||
| 147 | |||
| 148 | +static bool m25p80_aai_enable_needed(void *opaque) | ||
| 149 | +{ | ||
| 150 | + Flash *s = (Flash *)opaque; | ||
| 151 | + | ||
| 152 | + return s->aai_enable; | ||
| 153 | +} | ||
| 154 | + | ||
| 155 | +static const VMStateDescription vmstate_m25p80_aai_enable = { | ||
| 156 | + .name = "m25p80/aai_enable", | ||
| 157 | + .version_id = 1, | ||
| 158 | + .minimum_version_id = 1, | ||
| 159 | + .needed = m25p80_aai_enable_needed, | ||
| 160 | + .fields = (VMStateField[]) { | ||
| 161 | + VMSTATE_BOOL(aai_enable, Flash), | ||
| 162 | + VMSTATE_END_OF_LIST() | ||
| 163 | + } | ||
| 164 | +}; | ||
| 165 | + | ||
| 166 | static const VMStateDescription vmstate_m25p80 = { | ||
| 167 | .name = "m25p80", | ||
| 168 | .version_id = 0, | ||
| 169 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_m25p80 = { | ||
| 170 | }, | ||
| 171 | .subsections = (const VMStateDescription * []) { | ||
| 172 | &vmstate_m25p80_data_read_loop, | ||
| 173 | + &vmstate_m25p80_aai_enable, | ||
| 174 | NULL | ||
| 175 | } | ||
| 176 | }; | ||
| 177 | -- | ||
| 178 | 2.29.2 | ||
| 179 | |||
| 180 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | From: Sylvain Pelissier <sylvain.pelissier@gmail.com> | ||
| 2 | 1 | ||
| 3 | Target description is not currently implemented in RISC-V | ||
| 4 | architecture. Thus GDB won't set it properly when attached. | ||
| 5 | The patch implements the target description response. | ||
| 6 | |||
| 7 | Signed-off-by: Sylvain Pelissier <sylvain.pelissier@gmail.com> | ||
| 8 | Reviewed-by: Bin Meng <bin.meng@windriver.com> | ||
| 9 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 10 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
| 11 | Message-id: 20210106204141.14027-1-sylvain.pelissier@gmail.com | ||
| 12 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 13 | --- | ||
| 14 | target/riscv/cpu.c | 13 +++++++++++++ | ||
| 15 | 1 file changed, 13 insertions(+) | ||
| 16 | |||
| 17 | diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c | ||
| 18 | index XXXXXXX..XXXXXXX 100644 | ||
| 19 | --- a/target/riscv/cpu.c | ||
| 20 | +++ b/target/riscv/cpu.c | ||
| 21 | @@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_properties[] = { | ||
| 22 | DEFINE_PROP_END_OF_LIST(), | ||
| 23 | }; | ||
| 24 | |||
| 25 | +static gchar *riscv_gdb_arch_name(CPUState *cs) | ||
| 26 | +{ | ||
| 27 | + RISCVCPU *cpu = RISCV_CPU(cs); | ||
| 28 | + CPURISCVState *env = &cpu->env; | ||
| 29 | + | ||
| 30 | + if (riscv_cpu_is_32bit(env)) { | ||
| 31 | + return g_strdup("riscv:rv32"); | ||
| 32 | + } else { | ||
| 33 | + return g_strdup("riscv:rv64"); | ||
| 34 | + } | ||
| 35 | +} | ||
| 36 | + | ||
| 37 | static void riscv_cpu_class_init(ObjectClass *c, void *data) | ||
| 38 | { | ||
| 39 | RISCVCPUClass *mcc = RISCV_CPU_CLASS(c); | ||
| 40 | @@ -XXX,XX +XXX,XX @@ static void riscv_cpu_class_init(ObjectClass *c, void *data) | ||
| 41 | /* For now, mark unmigratable: */ | ||
| 42 | cc->vmsd = &vmstate_riscv_cpu; | ||
| 43 | #endif | ||
| 44 | + cc->gdb_arch_name = riscv_gdb_arch_name; | ||
| 45 | #ifdef CONFIG_TCG | ||
| 46 | cc->tcg_initialize = riscv_translate_init; | ||
| 47 | cc->tlb_fill = riscv_cpu_tlb_fill; | ||
| 48 | -- | ||
| 49 | 2.29.2 | ||
| 50 | |||
| 51 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | From: Atish Patra <atish.patra@wdc.com> | ||
| 2 | 1 | ||
| 3 | Currently, we place the DTB at 2MB from 4GB or end of DRAM which ever is | ||
| 4 | lesser. However, Linux kernel can address only 1GB of memory for RV32. | ||
| 5 | Thus, it can not map anything beyond 3GB (assuming 2GB is the starting address). | ||
| 6 | As a result, it can not process DT and panic if opensbi dynamic firmware | ||
| 7 | is used. While at it, place the DTB further away to avoid in memory placement | ||
| 8 | issues in future. | ||
| 9 | |||
| 10 | Fix this by placing the DTB at 16MB from 3GB or end of DRAM whichever is lower. | ||
| 11 | |||
| 12 | Fixes: 66b1205bc5ab ("RISC-V: Copy the fdt in dram instead of ROM") | ||
| 13 | |||
| 14 | Reviewed-by: Bin Meng <bin.meng@windriver.com> | ||
| 15 | Tested-by: Bin Meng <bin.meng@windriver.com> | ||
| 16 | Signed-off-by: Atish Patra <atish.patra@wdc.com> | ||
| 17 | Message-id: 20210107091127.3407870-1-atish.patra@wdc.com | ||
| 18 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 19 | --- | ||
| 20 | hw/riscv/boot.c | 8 ++++---- | ||
| 21 | 1 file changed, 4 insertions(+), 4 deletions(-) | ||
| 22 | |||
| 23 | diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c | ||
| 24 | index XXXXXXX..XXXXXXX 100644 | ||
| 25 | --- a/hw/riscv/boot.c | ||
| 26 | +++ b/hw/riscv/boot.c | ||
| 27 | @@ -XXX,XX +XXX,XX @@ uint32_t riscv_load_fdt(hwaddr dram_base, uint64_t mem_size, void *fdt) | ||
| 28 | /* | ||
| 29 | * We should put fdt as far as possible to avoid kernel/initrd overwriting | ||
| 30 | * its content. But it should be addressable by 32 bit system as well. | ||
| 31 | - * Thus, put it at an aligned address that less than fdt size from end of | ||
| 32 | - * dram or 4GB whichever is lesser. | ||
| 33 | + * Thus, put it at an 16MB aligned address that less than fdt size from the | ||
| 34 | + * end of dram or 3GB whichever is lesser. | ||
| 35 | */ | ||
| 36 | - temp = MIN(dram_end, 4096 * MiB); | ||
| 37 | - fdt_addr = QEMU_ALIGN_DOWN(temp - fdtsize, 2 * MiB); | ||
| 38 | + temp = MIN(dram_end, 3072 * MiB); | ||
| 39 | + fdt_addr = QEMU_ALIGN_DOWN(temp - fdtsize, 16 * MiB); | ||
| 40 | |||
| 41 | fdt_pack(fdt); | ||
| 42 | /* copy in the device tree */ | ||
| 43 | -- | ||
| 44 | 2.29.2 | ||
| 45 | |||
| 46 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | From: Atish Patra <atish.patra@wdc.com> | ||
| 2 | 1 | ||
| 3 | As per the privilege specification, any access from S/U mode should fail | ||
| 4 | if no pmp region is configured. | ||
| 5 | |||
| 6 | Signed-off-by: Atish Patra <atish.patra@wdc.com> | ||
| 7 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 8 | Message-id: 20201223192553.332508-1-atish.patra@wdc.com | ||
| 9 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 10 | --- | ||
| 11 | target/riscv/pmp.h | 1 + | ||
| 12 | target/riscv/op_helper.c | 5 +++++ | ||
| 13 | target/riscv/pmp.c | 4 ++-- | ||
| 14 | 3 files changed, 8 insertions(+), 2 deletions(-) | ||
| 15 | |||
| 16 | diff --git a/target/riscv/pmp.h b/target/riscv/pmp.h | ||
| 17 | index XXXXXXX..XXXXXXX 100644 | ||
| 18 | --- a/target/riscv/pmp.h | ||
| 19 | +++ b/target/riscv/pmp.h | ||
| 20 | @@ -XXX,XX +XXX,XX @@ bool pmp_is_range_in_tlb(CPURISCVState *env, hwaddr tlb_sa, | ||
| 21 | target_ulong *tlb_size); | ||
| 22 | void pmp_update_rule_addr(CPURISCVState *env, uint32_t pmp_index); | ||
| 23 | void pmp_update_rule_nums(CPURISCVState *env); | ||
| 24 | +uint32_t pmp_get_num_rules(CPURISCVState *env); | ||
| 25 | |||
| 26 | #endif | ||
| 27 | diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c | ||
| 28 | index XXXXXXX..XXXXXXX 100644 | ||
| 29 | --- a/target/riscv/op_helper.c | ||
| 30 | +++ b/target/riscv/op_helper.c | ||
| 31 | @@ -XXX,XX +XXX,XX @@ target_ulong helper_mret(CPURISCVState *env, target_ulong cpu_pc_deb) | ||
| 32 | |||
| 33 | uint64_t mstatus = env->mstatus; | ||
| 34 | target_ulong prev_priv = get_field(mstatus, MSTATUS_MPP); | ||
| 35 | + | ||
| 36 | + if (!pmp_get_num_rules(env) && (prev_priv != PRV_M)) { | ||
| 37 | + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); | ||
| 38 | + } | ||
| 39 | + | ||
| 40 | target_ulong prev_virt = get_field(env->mstatus, MSTATUS_MPV); | ||
| 41 | mstatus = set_field(mstatus, MSTATUS_MIE, | ||
| 42 | get_field(mstatus, MSTATUS_MPIE)); | ||
| 43 | diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c | ||
| 44 | index XXXXXXX..XXXXXXX 100644 | ||
| 45 | --- a/target/riscv/pmp.c | ||
| 46 | +++ b/target/riscv/pmp.c | ||
| 47 | @@ -XXX,XX +XXX,XX @@ static inline int pmp_is_locked(CPURISCVState *env, uint32_t pmp_index) | ||
| 48 | /* | ||
| 49 | * Count the number of active rules. | ||
| 50 | */ | ||
| 51 | -static inline uint32_t pmp_get_num_rules(CPURISCVState *env) | ||
| 52 | +uint32_t pmp_get_num_rules(CPURISCVState *env) | ||
| 53 | { | ||
| 54 | return env->pmp_state.num_rules; | ||
| 55 | } | ||
| 56 | @@ -XXX,XX +XXX,XX @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr, | ||
| 57 | |||
| 58 | /* Short cut if no rules */ | ||
| 59 | if (0 == pmp_get_num_rules(env)) { | ||
| 60 | - return true; | ||
| 61 | + return (env->priv == PRV_M) ? true : false; | ||
| 62 | } | ||
| 63 | |||
| 64 | if (size == 0) { | ||
| 65 | -- | ||
| 66 | 2.29.2 | ||
| 67 | |||
| 68 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | From: Bin Meng <bin.meng@windriver.com> | ||
| 2 | 1 | ||
| 3 | SIFIVE_U_CPU is conditionally set to SIFIVE_U34 or SIFIVE_U54, hence | ||
| 4 | there is no need to use #idef to set the mc->default_cpu_type. | ||
| 5 | |||
| 6 | Signed-off-by: Bin Meng <bin.meng@windriver.com> | ||
| 7 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
| 8 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 9 | Message-id: 20210109143637.29645-1-bmeng.cn@gmail.com | ||
| 10 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 11 | --- | ||
| 12 | hw/riscv/sifive_u.c | 6 +----- | ||
| 13 | 1 file changed, 1 insertion(+), 5 deletions(-) | ||
| 14 | |||
| 15 | diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c | ||
| 16 | index XXXXXXX..XXXXXXX 100644 | ||
| 17 | --- a/hw/riscv/sifive_u.c | ||
| 18 | +++ b/hw/riscv/sifive_u.c | ||
| 19 | @@ -XXX,XX +XXX,XX @@ static void sifive_u_machine_class_init(ObjectClass *oc, void *data) | ||
| 20 | mc->init = sifive_u_machine_init; | ||
| 21 | mc->max_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + SIFIVE_U_COMPUTE_CPU_COUNT; | ||
| 22 | mc->min_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + 1; | ||
| 23 | -#if defined(TARGET_RISCV32) | ||
| 24 | - mc->default_cpu_type = TYPE_RISCV_CPU_SIFIVE_U34; | ||
| 25 | -#elif defined(TARGET_RISCV64) | ||
| 26 | - mc->default_cpu_type = TYPE_RISCV_CPU_SIFIVE_U54; | ||
| 27 | -#endif | ||
| 28 | + mc->default_cpu_type = SIFIVE_U_CPU; | ||
| 29 | mc->default_cpus = mc->min_cpus; | ||
| 30 | |||
| 31 | object_class_property_add_bool(oc, "start-in-flash", | ||
| 32 | -- | ||
| 33 | 2.29.2 | ||
| 34 | |||
| 35 | diff view generated by jsdifflib |
| 1 | From: Bin Meng <bin.meng@windriver.com> | 1 | From: Thomas Huth <thuth@redhat.com> |
|---|---|---|---|
| 2 | 2 | ||
| 3 | At present QEMU RISC-V uses a hardcoded XML to report the feature | 3 | Configuring a drive with "if=none" is meant for creation of a backend |
| 4 | "org.gnu.gdb.riscv.csr" [1]. There are two major issues with the | 4 | only, it should not get automatically assigned to a device frontend. |
| 5 | approach being used currently: | 5 | Use "if=pflash" for the One-Time-Programmable device instead (like |
| 6 | it is e.g. also done for the efuse device in hw/arm/xlnx-zcu102.c). | ||
| 6 | 7 | ||
| 7 | - The XML does not specify the "regnum" field of a CSR entry, hence | 8 | Since the old way of configuring the device has already been published |
| 8 | consecutive numbers are used by the remote GDB client to access | 9 | with the previous QEMU versions, we cannot remove this immediately, but |
| 9 | CSRs. In QEMU we have to maintain a map table to convert the GDB | 10 | have to deprecate it and support it for at least two more releases. |
| 10 | number to the hardware number which is error prone. | ||
| 11 | - The XML contains some CSRs that QEMU does not implement at all, | ||
| 12 | which causes an "E14" response sent to remote GDB client. | ||
| 13 | 11 | ||
| 14 | Change to generate the CSR register list dynamically, based on the | 12 | Signed-off-by: Thomas Huth <thuth@redhat.com> |
| 15 | availability presented in the CSR function table. This new approach | 13 | Acked-by: Philippe Mathieu-Daudé <philmd@redhat.com> |
| 16 | will reflect a correct list of CSRs that QEMU actually implements. | 14 | Reviewed-by: Markus Armbruster <armbru@redhat.com> |
| 17 | |||
| 18 | [1] https://sourceware.org/gdb/current/onlinedocs/gdb/RISC_002dV-Features.html#RISC_002dV-Features | ||
| 19 | |||
| 20 | Signed-off-by: Bin Meng <bin.meng@windriver.com> | ||
| 21 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | 15 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> |
| 22 | Message-id: 20210116054123.5457-2-bmeng.cn@gmail.com | 16 | Message-id: 20211119102549.217755-1-thuth@redhat.com |
| 23 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | 17 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
| 24 | --- | 18 | --- |
| 25 | target/riscv/cpu.h | 2 + | 19 | docs/about/deprecated.rst | 6 ++++++ |
| 26 | target/riscv/cpu.c | 12 ++ | 20 | hw/misc/sifive_u_otp.c | 9 ++++++++- |
| 27 | target/riscv/gdbstub.c | 308 ++++++----------------------------------- | 21 | 2 files changed, 14 insertions(+), 1 deletion(-) |
| 28 | 3 files changed, 58 insertions(+), 264 deletions(-) | ||
| 29 | 22 | ||
| 30 | diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h | 23 | diff --git a/docs/about/deprecated.rst b/docs/about/deprecated.rst |
| 31 | index XXXXXXX..XXXXXXX 100644 | 24 | index XXXXXXX..XXXXXXX 100644 |
| 32 | --- a/target/riscv/cpu.h | 25 | --- a/docs/about/deprecated.rst |
| 33 | +++ b/target/riscv/cpu.h | 26 | +++ b/docs/about/deprecated.rst |
| 34 | @@ -XXX,XX +XXX,XX @@ struct RISCVCPU { | 27 | @@ -XXX,XX +XXX,XX @@ as short-form boolean values, and passed to plugins as ``arg_name=on``. |
| 35 | CPUNegativeOffsetState neg; | 28 | However, short-form booleans are deprecated and full explicit ``arg_name=on`` |
| 36 | CPURISCVState env; | 29 | form is preferred. |
| 37 | 30 | ||
| 38 | + char *dyn_csr_xml; | 31 | +``-drive if=none`` for the sifive_u OTP device (since 6.2) |
| 32 | +'''''''''''''''''''''''''''''''''''''''''''''''''''''''''' | ||
| 39 | + | 33 | + |
| 40 | /* Configuration Settings */ | 34 | +Using ``-drive if=none`` to configure the OTP device of the sifive_u |
| 41 | struct { | 35 | +RISC-V machine is deprecated. Use ``-drive if=pflash`` instead. |
| 42 | bool ext_i; | 36 | + |
| 43 | diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c | 37 | |
| 38 | QEMU Machine Protocol (QMP) commands | ||
| 39 | ------------------------------------ | ||
| 40 | diff --git a/hw/misc/sifive_u_otp.c b/hw/misc/sifive_u_otp.c | ||
| 44 | index XXXXXXX..XXXXXXX 100644 | 41 | index XXXXXXX..XXXXXXX 100644 |
| 45 | --- a/target/riscv/cpu.c | 42 | --- a/hw/misc/sifive_u_otp.c |
| 46 | +++ b/target/riscv/cpu.c | 43 | +++ b/hw/misc/sifive_u_otp.c |
| 47 | @@ -XXX,XX +XXX,XX @@ static gchar *riscv_gdb_arch_name(CPUState *cs) | 44 | @@ -XXX,XX +XXX,XX @@ static void sifive_u_otp_realize(DeviceState *dev, Error **errp) |
| 48 | } | 45 | TYPE_SIFIVE_U_OTP, SIFIVE_U_OTP_REG_SIZE); |
| 49 | } | 46 | sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->mmio); |
| 50 | 47 | ||
| 51 | +static const char *riscv_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname) | 48 | - dinfo = drive_get_next(IF_NONE); |
| 52 | +{ | 49 | + dinfo = drive_get_next(IF_PFLASH); |
| 53 | + RISCVCPU *cpu = RISCV_CPU(cs); | 50 | + if (!dinfo) { |
| 54 | + | 51 | + dinfo = drive_get_next(IF_NONE); |
| 55 | + if (strcmp(xmlname, "riscv-csr.xml") == 0) { | 52 | + if (dinfo) { |
| 56 | + return cpu->dyn_csr_xml; | 53 | + warn_report("using \"-drive if=none\" for the OTP is deprecated, " |
| 57 | + } | 54 | + "use \"-drive if=pflash\" instead."); |
| 58 | + | ||
| 59 | + return NULL; | ||
| 60 | +} | ||
| 61 | + | ||
| 62 | static void riscv_cpu_class_init(ObjectClass *c, void *data) | ||
| 63 | { | ||
| 64 | RISCVCPUClass *mcc = RISCV_CPU_CLASS(c); | ||
| 65 | @@ -XXX,XX +XXX,XX @@ static void riscv_cpu_class_init(ObjectClass *c, void *data) | ||
| 66 | cc->vmsd = &vmstate_riscv_cpu; | ||
| 67 | #endif | ||
| 68 | cc->gdb_arch_name = riscv_gdb_arch_name; | ||
| 69 | + cc->gdb_get_dynamic_xml = riscv_gdb_get_dynamic_xml; | ||
| 70 | #ifdef CONFIG_TCG | ||
| 71 | cc->tcg_initialize = riscv_translate_init; | ||
| 72 | cc->tlb_fill = riscv_cpu_tlb_fill; | ||
| 73 | diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c | ||
| 74 | index XXXXXXX..XXXXXXX 100644 | ||
| 75 | --- a/target/riscv/gdbstub.c | ||
| 76 | +++ b/target/riscv/gdbstub.c | ||
| 77 | @@ -XXX,XX +XXX,XX @@ | ||
| 78 | #include "exec/gdbstub.h" | ||
| 79 | #include "cpu.h" | ||
| 80 | |||
| 81 | -/* | ||
| 82 | - * The GDB CSR xml files list them in documentation order, not numerical order, | ||
| 83 | - * and are missing entries for unnamed CSRs. So we need to map the gdb numbers | ||
| 84 | - * to the hardware numbers. | ||
| 85 | - */ | ||
| 86 | - | ||
| 87 | -static int csr_register_map[] = { | ||
| 88 | - CSR_USTATUS, | ||
| 89 | - CSR_UIE, | ||
| 90 | - CSR_UTVEC, | ||
| 91 | - CSR_USCRATCH, | ||
| 92 | - CSR_UEPC, | ||
| 93 | - CSR_UCAUSE, | ||
| 94 | - CSR_UTVAL, | ||
| 95 | - CSR_UIP, | ||
| 96 | - CSR_FFLAGS, | ||
| 97 | - CSR_FRM, | ||
| 98 | - CSR_FCSR, | ||
| 99 | - CSR_CYCLE, | ||
| 100 | - CSR_TIME, | ||
| 101 | - CSR_INSTRET, | ||
| 102 | - CSR_HPMCOUNTER3, | ||
| 103 | - CSR_HPMCOUNTER4, | ||
| 104 | - CSR_HPMCOUNTER5, | ||
| 105 | - CSR_HPMCOUNTER6, | ||
| 106 | - CSR_HPMCOUNTER7, | ||
| 107 | - CSR_HPMCOUNTER8, | ||
| 108 | - CSR_HPMCOUNTER9, | ||
| 109 | - CSR_HPMCOUNTER10, | ||
| 110 | - CSR_HPMCOUNTER11, | ||
| 111 | - CSR_HPMCOUNTER12, | ||
| 112 | - CSR_HPMCOUNTER13, | ||
| 113 | - CSR_HPMCOUNTER14, | ||
| 114 | - CSR_HPMCOUNTER15, | ||
| 115 | - CSR_HPMCOUNTER16, | ||
| 116 | - CSR_HPMCOUNTER17, | ||
| 117 | - CSR_HPMCOUNTER18, | ||
| 118 | - CSR_HPMCOUNTER19, | ||
| 119 | - CSR_HPMCOUNTER20, | ||
| 120 | - CSR_HPMCOUNTER21, | ||
| 121 | - CSR_HPMCOUNTER22, | ||
| 122 | - CSR_HPMCOUNTER23, | ||
| 123 | - CSR_HPMCOUNTER24, | ||
| 124 | - CSR_HPMCOUNTER25, | ||
| 125 | - CSR_HPMCOUNTER26, | ||
| 126 | - CSR_HPMCOUNTER27, | ||
| 127 | - CSR_HPMCOUNTER28, | ||
| 128 | - CSR_HPMCOUNTER29, | ||
| 129 | - CSR_HPMCOUNTER30, | ||
| 130 | - CSR_HPMCOUNTER31, | ||
| 131 | - CSR_CYCLEH, | ||
| 132 | - CSR_TIMEH, | ||
| 133 | - CSR_INSTRETH, | ||
| 134 | - CSR_HPMCOUNTER3H, | ||
| 135 | - CSR_HPMCOUNTER4H, | ||
| 136 | - CSR_HPMCOUNTER5H, | ||
| 137 | - CSR_HPMCOUNTER6H, | ||
| 138 | - CSR_HPMCOUNTER7H, | ||
| 139 | - CSR_HPMCOUNTER8H, | ||
| 140 | - CSR_HPMCOUNTER9H, | ||
| 141 | - CSR_HPMCOUNTER10H, | ||
| 142 | - CSR_HPMCOUNTER11H, | ||
| 143 | - CSR_HPMCOUNTER12H, | ||
| 144 | - CSR_HPMCOUNTER13H, | ||
| 145 | - CSR_HPMCOUNTER14H, | ||
| 146 | - CSR_HPMCOUNTER15H, | ||
| 147 | - CSR_HPMCOUNTER16H, | ||
| 148 | - CSR_HPMCOUNTER17H, | ||
| 149 | - CSR_HPMCOUNTER18H, | ||
| 150 | - CSR_HPMCOUNTER19H, | ||
| 151 | - CSR_HPMCOUNTER20H, | ||
| 152 | - CSR_HPMCOUNTER21H, | ||
| 153 | - CSR_HPMCOUNTER22H, | ||
| 154 | - CSR_HPMCOUNTER23H, | ||
| 155 | - CSR_HPMCOUNTER24H, | ||
| 156 | - CSR_HPMCOUNTER25H, | ||
| 157 | - CSR_HPMCOUNTER26H, | ||
| 158 | - CSR_HPMCOUNTER27H, | ||
| 159 | - CSR_HPMCOUNTER28H, | ||
| 160 | - CSR_HPMCOUNTER29H, | ||
| 161 | - CSR_HPMCOUNTER30H, | ||
| 162 | - CSR_HPMCOUNTER31H, | ||
| 163 | - CSR_SSTATUS, | ||
| 164 | - CSR_SEDELEG, | ||
| 165 | - CSR_SIDELEG, | ||
| 166 | - CSR_SIE, | ||
| 167 | - CSR_STVEC, | ||
| 168 | - CSR_SCOUNTEREN, | ||
| 169 | - CSR_SSCRATCH, | ||
| 170 | - CSR_SEPC, | ||
| 171 | - CSR_SCAUSE, | ||
| 172 | - CSR_STVAL, | ||
| 173 | - CSR_SIP, | ||
| 174 | - CSR_SATP, | ||
| 175 | - CSR_MVENDORID, | ||
| 176 | - CSR_MARCHID, | ||
| 177 | - CSR_MIMPID, | ||
| 178 | - CSR_MHARTID, | ||
| 179 | - CSR_MSTATUS, | ||
| 180 | - CSR_MISA, | ||
| 181 | - CSR_MEDELEG, | ||
| 182 | - CSR_MIDELEG, | ||
| 183 | - CSR_MIE, | ||
| 184 | - CSR_MTVEC, | ||
| 185 | - CSR_MCOUNTEREN, | ||
| 186 | - CSR_MSCRATCH, | ||
| 187 | - CSR_MEPC, | ||
| 188 | - CSR_MCAUSE, | ||
| 189 | - CSR_MTVAL, | ||
| 190 | - CSR_MIP, | ||
| 191 | - CSR_MTINST, | ||
| 192 | - CSR_MTVAL2, | ||
| 193 | - CSR_PMPCFG0, | ||
| 194 | - CSR_PMPCFG1, | ||
| 195 | - CSR_PMPCFG2, | ||
| 196 | - CSR_PMPCFG3, | ||
| 197 | - CSR_PMPADDR0, | ||
| 198 | - CSR_PMPADDR1, | ||
| 199 | - CSR_PMPADDR2, | ||
| 200 | - CSR_PMPADDR3, | ||
| 201 | - CSR_PMPADDR4, | ||
| 202 | - CSR_PMPADDR5, | ||
| 203 | - CSR_PMPADDR6, | ||
| 204 | - CSR_PMPADDR7, | ||
| 205 | - CSR_PMPADDR8, | ||
| 206 | - CSR_PMPADDR9, | ||
| 207 | - CSR_PMPADDR10, | ||
| 208 | - CSR_PMPADDR11, | ||
| 209 | - CSR_PMPADDR12, | ||
| 210 | - CSR_PMPADDR13, | ||
| 211 | - CSR_PMPADDR14, | ||
| 212 | - CSR_PMPADDR15, | ||
| 213 | - CSR_MCYCLE, | ||
| 214 | - CSR_MINSTRET, | ||
| 215 | - CSR_MHPMCOUNTER3, | ||
| 216 | - CSR_MHPMCOUNTER4, | ||
| 217 | - CSR_MHPMCOUNTER5, | ||
| 218 | - CSR_MHPMCOUNTER6, | ||
| 219 | - CSR_MHPMCOUNTER7, | ||
| 220 | - CSR_MHPMCOUNTER8, | ||
| 221 | - CSR_MHPMCOUNTER9, | ||
| 222 | - CSR_MHPMCOUNTER10, | ||
| 223 | - CSR_MHPMCOUNTER11, | ||
| 224 | - CSR_MHPMCOUNTER12, | ||
| 225 | - CSR_MHPMCOUNTER13, | ||
| 226 | - CSR_MHPMCOUNTER14, | ||
| 227 | - CSR_MHPMCOUNTER15, | ||
| 228 | - CSR_MHPMCOUNTER16, | ||
| 229 | - CSR_MHPMCOUNTER17, | ||
| 230 | - CSR_MHPMCOUNTER18, | ||
| 231 | - CSR_MHPMCOUNTER19, | ||
| 232 | - CSR_MHPMCOUNTER20, | ||
| 233 | - CSR_MHPMCOUNTER21, | ||
| 234 | - CSR_MHPMCOUNTER22, | ||
| 235 | - CSR_MHPMCOUNTER23, | ||
| 236 | - CSR_MHPMCOUNTER24, | ||
| 237 | - CSR_MHPMCOUNTER25, | ||
| 238 | - CSR_MHPMCOUNTER26, | ||
| 239 | - CSR_MHPMCOUNTER27, | ||
| 240 | - CSR_MHPMCOUNTER28, | ||
| 241 | - CSR_MHPMCOUNTER29, | ||
| 242 | - CSR_MHPMCOUNTER30, | ||
| 243 | - CSR_MHPMCOUNTER31, | ||
| 244 | - CSR_MCYCLEH, | ||
| 245 | - CSR_MINSTRETH, | ||
| 246 | - CSR_MHPMCOUNTER3H, | ||
| 247 | - CSR_MHPMCOUNTER4H, | ||
| 248 | - CSR_MHPMCOUNTER5H, | ||
| 249 | - CSR_MHPMCOUNTER6H, | ||
| 250 | - CSR_MHPMCOUNTER7H, | ||
| 251 | - CSR_MHPMCOUNTER8H, | ||
| 252 | - CSR_MHPMCOUNTER9H, | ||
| 253 | - CSR_MHPMCOUNTER10H, | ||
| 254 | - CSR_MHPMCOUNTER11H, | ||
| 255 | - CSR_MHPMCOUNTER12H, | ||
| 256 | - CSR_MHPMCOUNTER13H, | ||
| 257 | - CSR_MHPMCOUNTER14H, | ||
| 258 | - CSR_MHPMCOUNTER15H, | ||
| 259 | - CSR_MHPMCOUNTER16H, | ||
| 260 | - CSR_MHPMCOUNTER17H, | ||
| 261 | - CSR_MHPMCOUNTER18H, | ||
| 262 | - CSR_MHPMCOUNTER19H, | ||
| 263 | - CSR_MHPMCOUNTER20H, | ||
| 264 | - CSR_MHPMCOUNTER21H, | ||
| 265 | - CSR_MHPMCOUNTER22H, | ||
| 266 | - CSR_MHPMCOUNTER23H, | ||
| 267 | - CSR_MHPMCOUNTER24H, | ||
| 268 | - CSR_MHPMCOUNTER25H, | ||
| 269 | - CSR_MHPMCOUNTER26H, | ||
| 270 | - CSR_MHPMCOUNTER27H, | ||
| 271 | - CSR_MHPMCOUNTER28H, | ||
| 272 | - CSR_MHPMCOUNTER29H, | ||
| 273 | - CSR_MHPMCOUNTER30H, | ||
| 274 | - CSR_MHPMCOUNTER31H, | ||
| 275 | - CSR_MHPMEVENT3, | ||
| 276 | - CSR_MHPMEVENT4, | ||
| 277 | - CSR_MHPMEVENT5, | ||
| 278 | - CSR_MHPMEVENT6, | ||
| 279 | - CSR_MHPMEVENT7, | ||
| 280 | - CSR_MHPMEVENT8, | ||
| 281 | - CSR_MHPMEVENT9, | ||
| 282 | - CSR_MHPMEVENT10, | ||
| 283 | - CSR_MHPMEVENT11, | ||
| 284 | - CSR_MHPMEVENT12, | ||
| 285 | - CSR_MHPMEVENT13, | ||
| 286 | - CSR_MHPMEVENT14, | ||
| 287 | - CSR_MHPMEVENT15, | ||
| 288 | - CSR_MHPMEVENT16, | ||
| 289 | - CSR_MHPMEVENT17, | ||
| 290 | - CSR_MHPMEVENT18, | ||
| 291 | - CSR_MHPMEVENT19, | ||
| 292 | - CSR_MHPMEVENT20, | ||
| 293 | - CSR_MHPMEVENT21, | ||
| 294 | - CSR_MHPMEVENT22, | ||
| 295 | - CSR_MHPMEVENT23, | ||
| 296 | - CSR_MHPMEVENT24, | ||
| 297 | - CSR_MHPMEVENT25, | ||
| 298 | - CSR_MHPMEVENT26, | ||
| 299 | - CSR_MHPMEVENT27, | ||
| 300 | - CSR_MHPMEVENT28, | ||
| 301 | - CSR_MHPMEVENT29, | ||
| 302 | - CSR_MHPMEVENT30, | ||
| 303 | - CSR_MHPMEVENT31, | ||
| 304 | - CSR_TSELECT, | ||
| 305 | - CSR_TDATA1, | ||
| 306 | - CSR_TDATA2, | ||
| 307 | - CSR_TDATA3, | ||
| 308 | - CSR_DCSR, | ||
| 309 | - CSR_DPC, | ||
| 310 | - CSR_DSCRATCH, | ||
| 311 | - CSR_HSTATUS, | ||
| 312 | - CSR_HEDELEG, | ||
| 313 | - CSR_HIDELEG, | ||
| 314 | - CSR_HIE, | ||
| 315 | - CSR_HCOUNTEREN, | ||
| 316 | - CSR_HTVAL, | ||
| 317 | - CSR_HIP, | ||
| 318 | - CSR_HTINST, | ||
| 319 | - CSR_HGATP, | ||
| 320 | - CSR_MBASE, | ||
| 321 | - CSR_MBOUND, | ||
| 322 | - CSR_MIBASE, | ||
| 323 | - CSR_MIBOUND, | ||
| 324 | - CSR_MDBASE, | ||
| 325 | - CSR_MDBOUND, | ||
| 326 | - CSR_MUCOUNTEREN, | ||
| 327 | - CSR_MSCOUNTEREN, | ||
| 328 | - CSR_MHCOUNTEREN, | ||
| 329 | -}; | ||
| 330 | - | ||
| 331 | int riscv_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) | ||
| 332 | { | ||
| 333 | RISCVCPU *cpu = RISCV_CPU(cs); | ||
| 334 | @@ -XXX,XX +XXX,XX @@ static int riscv_gdb_get_fpu(CPURISCVState *env, GByteArray *buf, int n) | ||
| 335 | target_ulong val = 0; | ||
| 336 | int result; | ||
| 337 | /* | ||
| 338 | - * CSR_FFLAGS is at index 8 in csr_register, and gdb says it is FP | ||
| 339 | + * CSR_FFLAGS is at index 1 in csr_register, and gdb says it is FP | ||
| 340 | * register 33, so we recalculate the map index. | ||
| 341 | * This also works for CSR_FRM and CSR_FCSR. | ||
| 342 | */ | ||
| 343 | - result = riscv_csrrw_debug(env, n - 33 + csr_register_map[8], &val, | ||
| 344 | + result = riscv_csrrw_debug(env, n - 32, &val, | ||
| 345 | 0, 0); | ||
| 346 | if (result == 0) { | ||
| 347 | return gdb_get_regl(buf, val); | ||
| 348 | @@ -XXX,XX +XXX,XX @@ static int riscv_gdb_set_fpu(CPURISCVState *env, uint8_t *mem_buf, int n) | ||
| 349 | target_ulong val = ldtul_p(mem_buf); | ||
| 350 | int result; | ||
| 351 | /* | ||
| 352 | - * CSR_FFLAGS is at index 8 in csr_register, and gdb says it is FP | ||
| 353 | + * CSR_FFLAGS is at index 1 in csr_register, and gdb says it is FP | ||
| 354 | * register 33, so we recalculate the map index. | ||
| 355 | * This also works for CSR_FRM and CSR_FCSR. | ||
| 356 | */ | ||
| 357 | - result = riscv_csrrw_debug(env, n - 33 + csr_register_map[8], NULL, | ||
| 358 | + result = riscv_csrrw_debug(env, n - 32, NULL, | ||
| 359 | val, -1); | ||
| 360 | if (result == 0) { | ||
| 361 | return sizeof(target_ulong); | ||
| 362 | @@ -XXX,XX +XXX,XX @@ static int riscv_gdb_set_fpu(CPURISCVState *env, uint8_t *mem_buf, int n) | ||
| 363 | |||
| 364 | static int riscv_gdb_get_csr(CPURISCVState *env, GByteArray *buf, int n) | ||
| 365 | { | ||
| 366 | - if (n < ARRAY_SIZE(csr_register_map)) { | ||
| 367 | + if (n < CSR_TABLE_SIZE) { | ||
| 368 | target_ulong val = 0; | ||
| 369 | int result; | ||
| 370 | |||
| 371 | - result = riscv_csrrw_debug(env, csr_register_map[n], &val, 0, 0); | ||
| 372 | + result = riscv_csrrw_debug(env, n, &val, 0, 0); | ||
| 373 | if (result == 0) { | ||
| 374 | return gdb_get_regl(buf, val); | ||
| 375 | } | ||
| 376 | @@ -XXX,XX +XXX,XX @@ static int riscv_gdb_get_csr(CPURISCVState *env, GByteArray *buf, int n) | ||
| 377 | |||
| 378 | static int riscv_gdb_set_csr(CPURISCVState *env, uint8_t *mem_buf, int n) | ||
| 379 | { | ||
| 380 | - if (n < ARRAY_SIZE(csr_register_map)) { | ||
| 381 | + if (n < CSR_TABLE_SIZE) { | ||
| 382 | target_ulong val = ldtul_p(mem_buf); | ||
| 383 | int result; | ||
| 384 | |||
| 385 | - result = riscv_csrrw_debug(env, csr_register_map[n], NULL, val, -1); | ||
| 386 | + result = riscv_csrrw_debug(env, n, NULL, val, -1); | ||
| 387 | if (result == 0) { | ||
| 388 | return sizeof(target_ulong); | ||
| 389 | } | ||
| 390 | @@ -XXX,XX +XXX,XX @@ static int riscv_gdb_set_virtual(CPURISCVState *cs, uint8_t *mem_buf, int n) | ||
| 391 | return 0; | ||
| 392 | } | ||
| 393 | |||
| 394 | +static int riscv_gen_dynamic_csr_xml(CPUState *cs, int base_reg) | ||
| 395 | +{ | ||
| 396 | + RISCVCPU *cpu = RISCV_CPU(cs); | ||
| 397 | + CPURISCVState *env = &cpu->env; | ||
| 398 | + GString *s = g_string_new(NULL); | ||
| 399 | + riscv_csr_predicate_fn predicate; | ||
| 400 | + int bitsize = riscv_cpu_is_32bit(env) ? 32 : 64; | ||
| 401 | + int i; | ||
| 402 | + | ||
| 403 | + g_string_printf(s, "<?xml version=\"1.0\"?>"); | ||
| 404 | + g_string_append_printf(s, "<!DOCTYPE feature SYSTEM \"gdb-target.dtd\">"); | ||
| 405 | + g_string_append_printf(s, "<feature name=\"org.gnu.gdb.riscv.csr\">"); | ||
| 406 | + | ||
| 407 | + for (i = 0; i < CSR_TABLE_SIZE; i++) { | ||
| 408 | + predicate = csr_ops[i].predicate; | ||
| 409 | + if (predicate && !predicate(env, i)) { | ||
| 410 | + if (csr_ops[i].name) { | ||
| 411 | + g_string_append_printf(s, "<reg name=\"%s\"", csr_ops[i].name); | ||
| 412 | + } else { | ||
| 413 | + g_string_append_printf(s, "<reg name=\"csr%03x\"", i); | ||
| 414 | + } | ||
| 415 | + g_string_append_printf(s, " bitsize=\"%d\"", bitsize); | ||
| 416 | + g_string_append_printf(s, " regnum=\"%d\"/>", base_reg + i); | ||
| 417 | + } | 55 | + } |
| 418 | + } | 56 | + } |
| 419 | + | 57 | if (dinfo) { |
| 420 | + g_string_append_printf(s, "</feature>"); | 58 | int ret; |
| 421 | + | 59 | uint64_t perm; |
| 422 | + cpu->dyn_csr_xml = g_string_free(s, false); | ||
| 423 | + return CSR_TABLE_SIZE; | ||
| 424 | +} | ||
| 425 | + | ||
| 426 | void riscv_cpu_register_gdb_regs_for_features(CPUState *cs) | ||
| 427 | { | ||
| 428 | RISCVCPU *cpu = RISCV_CPU(cs); | ||
| 429 | @@ -XXX,XX +XXX,XX @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs) | ||
| 430 | 36, "riscv-32bit-fpu.xml", 0); | ||
| 431 | } | ||
| 432 | #if defined(TARGET_RISCV32) | ||
| 433 | - gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr, | ||
| 434 | - 240, "riscv-32bit-csr.xml", 0); | ||
| 435 | - | ||
| 436 | gdb_register_coprocessor(cs, riscv_gdb_get_virtual, riscv_gdb_set_virtual, | ||
| 437 | 1, "riscv-32bit-virtual.xml", 0); | ||
| 438 | #elif defined(TARGET_RISCV64) | ||
| 439 | - gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr, | ||
| 440 | - 240, "riscv-64bit-csr.xml", 0); | ||
| 441 | - | ||
| 442 | gdb_register_coprocessor(cs, riscv_gdb_get_virtual, riscv_gdb_set_virtual, | ||
| 443 | 1, "riscv-64bit-virtual.xml", 0); | ||
| 444 | #endif | ||
| 445 | + | ||
| 446 | + gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr, | ||
| 447 | + riscv_gen_dynamic_csr_xml(cs, cs->gdb_num_regs), | ||
| 448 | + "riscv-csr.xml", 0); | ||
| 449 | } | ||
| 450 | -- | 60 | -- |
| 451 | 2.29.2 | 61 | 2.31.1 |
| 452 | 62 | ||
| 453 | 63 | diff view generated by jsdifflib |
| 1 | From: Green Wan <green.wan@sifive.com> | 1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> |
|---|---|---|---|
| 2 | 2 | ||
| 3 | Fix code coverage issues by checking return value and handling fail case | 3 | Once a "One Time Programmable" is programmed, it shouldn't be reset. |
| 4 | of blk_pread() and blk_pwrite(). Return default value 0xff if read fails. | ||
| 5 | 4 | ||
| 6 | Fixes: Coverity CID 1435959 | 5 | Do not re-initialize the OTP content in the DeviceReset handler, |
| 7 | Fixes: Coverity CID 1435960 | 6 | initialize it once in the DeviceRealize one. |
| 8 | Fixes: Coverity CID 1435961 | 7 | |
| 9 | Signed-off-by: Green Wan <green.wan@sifive.com> | 8 | Fixes: 9fb45c62ae8 ("riscv: sifive: Implement a model for SiFive FU540 OTP") |
| 9 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
| 10 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | 10 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> |
| 11 | Message-id: 20201104092900.21214-1-green.wan@sifive.com | 11 | Message-Id: <20211119104757.331579-1-f4bug@amsat.org> |
| 12 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | 12 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
| 13 | --- | 13 | --- |
| 14 | hw/misc/sifive_u_otp.c | 31 +++++++++++++++++++++++-------- | 14 | hw/misc/sifive_u_otp.c | 13 +++++-------- |
| 15 | 1 file changed, 23 insertions(+), 8 deletions(-) | 15 | 1 file changed, 5 insertions(+), 8 deletions(-) |
| 16 | 16 | ||
| 17 | diff --git a/hw/misc/sifive_u_otp.c b/hw/misc/sifive_u_otp.c | 17 | diff --git a/hw/misc/sifive_u_otp.c b/hw/misc/sifive_u_otp.c |
| 18 | index XXXXXXX..XXXXXXX 100644 | 18 | index XXXXXXX..XXXXXXX 100644 |
| 19 | --- a/hw/misc/sifive_u_otp.c | 19 | --- a/hw/misc/sifive_u_otp.c |
| 20 | +++ b/hw/misc/sifive_u_otp.c | 20 | +++ b/hw/misc/sifive_u_otp.c |
| 21 | @@ -XXX,XX +XXX,XX @@ static uint64_t sifive_u_otp_read(void *opaque, hwaddr addr, unsigned int size) | 21 | @@ -XXX,XX +XXX,XX @@ static void sifive_u_otp_realize(DeviceState *dev, Error **errp) |
| 22 | if (s->blk) { | 22 | |
| 23 | int32_t buf; | 23 | if (blk_pread(s->blk, 0, s->fuse, filesize) != filesize) { |
| 24 | 24 | error_setg(errp, "failed to read the initial flash content"); | |
| 25 | - blk_pread(s->blk, s->pa * SIFIVE_U_OTP_FUSE_WORD, &buf, | 25 | + return; |
| 26 | - SIFIVE_U_OTP_FUSE_WORD); | ||
| 27 | + if (blk_pread(s->blk, s->pa * SIFIVE_U_OTP_FUSE_WORD, &buf, | ||
| 28 | + SIFIVE_U_OTP_FUSE_WORD) < 0) { | ||
| 29 | + qemu_log_mask(LOG_GUEST_ERROR, | ||
| 30 | + "read error index<%d>\n", s->pa); | ||
| 31 | + return 0xff; | ||
| 32 | + } | ||
| 33 | + | ||
| 34 | return buf; | ||
| 35 | } | 26 | } |
| 36 | 27 | } | |
| 37 | @@ -XXX,XX +XXX,XX @@ static void sifive_u_otp_write(void *opaque, hwaddr addr, | 28 | } |
| 38 | 29 | -} | |
| 39 | /* write to backend */ | 30 | - |
| 40 | if (s->blk) { | 31 | -static void sifive_u_otp_reset(DeviceState *dev) |
| 41 | - blk_pwrite(s->blk, s->pa * SIFIVE_U_OTP_FUSE_WORD, | 32 | -{ |
| 42 | - &s->fuse[s->pa], SIFIVE_U_OTP_FUSE_WORD, 0); | 33 | - SiFiveUOTPState *s = SIFIVE_U_OTP(dev); |
| 43 | + if (blk_pwrite(s->blk, s->pa * SIFIVE_U_OTP_FUSE_WORD, | 34 | |
| 44 | + &s->fuse[s->pa], SIFIVE_U_OTP_FUSE_WORD, | 35 | /* Initialize all fuses' initial value to 0xFFs */ |
| 45 | + 0) < 0) { | 36 | memset(s->fuse, 0xff, sizeof(s->fuse)); |
| 46 | + qemu_log_mask(LOG_GUEST_ERROR, | ||
| 47 | + "write error index<%d>\n", s->pa); | ||
| 48 | + } | ||
| 49 | } | ||
| 50 | |||
| 51 | /* update written bit */ | ||
| 52 | @@ -XXX,XX +XXX,XX @@ static void sifive_u_otp_reset(DeviceState *dev) | 37 | @@ -XXX,XX +XXX,XX @@ static void sifive_u_otp_reset(DeviceState *dev) |
| 53 | int index = SIFIVE_U_OTP_SERIAL_ADDR; | ||
| 54 | |||
| 55 | serial_data = s->serial; | 38 | serial_data = s->serial; |
| 56 | - blk_pwrite(s->blk, index * SIFIVE_U_OTP_FUSE_WORD, | 39 | if (blk_pwrite(s->blk, index * SIFIVE_U_OTP_FUSE_WORD, |
| 57 | - &serial_data, SIFIVE_U_OTP_FUSE_WORD, 0); | 40 | &serial_data, SIFIVE_U_OTP_FUSE_WORD, 0) < 0) { |
| 58 | + if (blk_pwrite(s->blk, index * SIFIVE_U_OTP_FUSE_WORD, | 41 | - error_report("write error index<%d>", index); |
| 59 | + &serial_data, SIFIVE_U_OTP_FUSE_WORD, 0) < 0) { | 42 | + error_setg(errp, "failed to write index<%d>", index); |
| 60 | + qemu_log_mask(LOG_GUEST_ERROR, | 43 | + return; |
| 61 | + "write error index<%d>\n", index); | 44 | } |
| 62 | + } | ||
| 63 | 45 | ||
| 64 | serial_data = ~(s->serial); | 46 | serial_data = ~(s->serial); |
| 65 | - blk_pwrite(s->blk, (index + 1) * SIFIVE_U_OTP_FUSE_WORD, | 47 | if (blk_pwrite(s->blk, (index + 1) * SIFIVE_U_OTP_FUSE_WORD, |
| 66 | - &serial_data, SIFIVE_U_OTP_FUSE_WORD, 0); | 48 | &serial_data, SIFIVE_U_OTP_FUSE_WORD, 0) < 0) { |
| 67 | + if (blk_pwrite(s->blk, (index + 1) * SIFIVE_U_OTP_FUSE_WORD, | 49 | - error_report("write error index<%d>", index + 1); |
| 68 | + &serial_data, SIFIVE_U_OTP_FUSE_WORD, 0) < 0) { | 50 | + error_setg(errp, "failed to write index<%d>", index + 1); |
| 69 | + qemu_log_mask(LOG_GUEST_ERROR, | 51 | + return; |
| 70 | + "write error index<%d>\n", index + 1); | 52 | } |
| 71 | + } | ||
| 72 | } | 53 | } |
| 73 | 54 | ||
| 74 | /* Initialize write-once map */ | 55 | @@ -XXX,XX +XXX,XX @@ static void sifive_u_otp_class_init(ObjectClass *klass, void *data) |
| 56 | |||
| 57 | device_class_set_props(dc, sifive_u_otp_properties); | ||
| 58 | dc->realize = sifive_u_otp_realize; | ||
| 59 | - dc->reset = sifive_u_otp_reset; | ||
| 60 | } | ||
| 61 | |||
| 62 | static const TypeInfo sifive_u_otp_info = { | ||
| 75 | -- | 63 | -- |
| 76 | 2.29.2 | 64 | 2.31.1 |
| 77 | 65 | ||
| 78 | 66 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | From: Bin Meng <bin.meng@windriver.com> | ||
| 2 | 1 | ||
| 3 | In preparation to generate the CSR register list for GDB stub | ||
| 4 | dynamically, change csr_ops[] to non-static so that it can be | ||
| 5 | referenced externally. | ||
| 6 | |||
| 7 | Signed-off-by: Bin Meng <bin.meng@windriver.com> | ||
| 8 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 9 | Message-id: 1610427124-49887-2-git-send-email-bmeng.cn@gmail.com | ||
| 10 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 11 | --- | ||
| 12 | target/riscv/cpu.h | 8 ++++++++ | ||
| 13 | target/riscv/csr.c | 10 +--------- | ||
| 14 | 2 files changed, 9 insertions(+), 9 deletions(-) | ||
| 15 | |||
| 16 | diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h | ||
| 17 | index XXXXXXX..XXXXXXX 100644 | ||
| 18 | --- a/target/riscv/cpu.h | ||
| 19 | +++ b/target/riscv/cpu.h | ||
| 20 | @@ -XXX,XX +XXX,XX @@ typedef struct { | ||
| 21 | riscv_csr_op_fn op; | ||
| 22 | } riscv_csr_operations; | ||
| 23 | |||
| 24 | +/* CSR function table constants */ | ||
| 25 | +enum { | ||
| 26 | + CSR_TABLE_SIZE = 0x1000 | ||
| 27 | +}; | ||
| 28 | + | ||
| 29 | +/* CSR function table */ | ||
| 30 | +extern riscv_csr_operations csr_ops[]; | ||
| 31 | + | ||
| 32 | void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops); | ||
| 33 | void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops); | ||
| 34 | |||
| 35 | diff --git a/target/riscv/csr.c b/target/riscv/csr.c | ||
| 36 | index XXXXXXX..XXXXXXX 100644 | ||
| 37 | --- a/target/riscv/csr.c | ||
| 38 | +++ b/target/riscv/csr.c | ||
| 39 | @@ -XXX,XX +XXX,XX @@ | ||
| 40 | #include "qemu/main-loop.h" | ||
| 41 | #include "exec/exec-all.h" | ||
| 42 | |||
| 43 | -/* CSR function table */ | ||
| 44 | -static riscv_csr_operations csr_ops[]; | ||
| 45 | - | ||
| 46 | -/* CSR function table constants */ | ||
| 47 | -enum { | ||
| 48 | - CSR_TABLE_SIZE = 0x1000 | ||
| 49 | -}; | ||
| 50 | - | ||
| 51 | /* CSR function table public API */ | ||
| 52 | void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops) | ||
| 53 | { | ||
| 54 | @@ -XXX,XX +XXX,XX @@ int riscv_csrrw_debug(CPURISCVState *env, int csrno, target_ulong *ret_value, | ||
| 55 | } | ||
| 56 | |||
| 57 | /* Control and Status Register function table */ | ||
| 58 | -static riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { | ||
| 59 | +riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { | ||
| 60 | /* User Floating-Point CSRs */ | ||
| 61 | [CSR_FFLAGS] = { fs, read_fflags, write_fflags }, | ||
| 62 | [CSR_FRM] = { fs, read_frm, write_frm }, | ||
| 63 | -- | ||
| 64 | 2.29.2 | ||
| 65 | |||
| 66 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | From: Bin Meng <bin.meng@windriver.com> | ||
| 2 | 1 | ||
| 3 | In preparation to generate the CSR register list for GDB stub | ||
| 4 | dynamically, let's add the CSR name in the CSR function table. | ||
| 5 | |||
| 6 | Signed-off-by: Bin Meng <bin.meng@windriver.com> | ||
| 7 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 8 | Message-id: 1610427124-49887-3-git-send-email-bmeng.cn@gmail.com | ||
| 9 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 10 | --- | ||
| 11 | target/riscv/cpu.h | 1 + | ||
| 12 | target/riscv/csr.c | 332 +++++++++++++++++++++++++++++++++------------ | ||
| 13 | 2 files changed, 249 insertions(+), 84 deletions(-) | ||
| 14 | |||
| 15 | diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h | ||
| 16 | index XXXXXXX..XXXXXXX 100644 | ||
| 17 | --- a/target/riscv/cpu.h | ||
| 18 | +++ b/target/riscv/cpu.h | ||
| 19 | @@ -XXX,XX +XXX,XX @@ typedef int (*riscv_csr_op_fn)(CPURISCVState *env, int csrno, | ||
| 20 | target_ulong *ret_value, target_ulong new_value, target_ulong write_mask); | ||
| 21 | |||
| 22 | typedef struct { | ||
| 23 | + const char *name; | ||
| 24 | riscv_csr_predicate_fn predicate; | ||
| 25 | riscv_csr_read_fn read; | ||
| 26 | riscv_csr_write_fn write; | ||
| 27 | diff --git a/target/riscv/csr.c b/target/riscv/csr.c | ||
| 28 | index XXXXXXX..XXXXXXX 100644 | ||
| 29 | --- a/target/riscv/csr.c | ||
| 30 | +++ b/target/riscv/csr.c | ||
| 31 | @@ -XXX,XX +XXX,XX @@ int riscv_csrrw_debug(CPURISCVState *env, int csrno, target_ulong *ret_value, | ||
| 32 | /* Control and Status Register function table */ | ||
| 33 | riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { | ||
| 34 | /* User Floating-Point CSRs */ | ||
| 35 | - [CSR_FFLAGS] = { fs, read_fflags, write_fflags }, | ||
| 36 | - [CSR_FRM] = { fs, read_frm, write_frm }, | ||
| 37 | - [CSR_FCSR] = { fs, read_fcsr, write_fcsr }, | ||
| 38 | + [CSR_FFLAGS] = { "fflags", fs, read_fflags, write_fflags }, | ||
| 39 | + [CSR_FRM] = { "frm", fs, read_frm, write_frm }, | ||
| 40 | + [CSR_FCSR] = { "fcsr", fs, read_fcsr, write_fcsr }, | ||
| 41 | /* Vector CSRs */ | ||
| 42 | - [CSR_VSTART] = { vs, read_vstart, write_vstart }, | ||
| 43 | - [CSR_VXSAT] = { vs, read_vxsat, write_vxsat }, | ||
| 44 | - [CSR_VXRM] = { vs, read_vxrm, write_vxrm }, | ||
| 45 | - [CSR_VL] = { vs, read_vl }, | ||
| 46 | - [CSR_VTYPE] = { vs, read_vtype }, | ||
| 47 | + [CSR_VSTART] = { "vstart", vs, read_vstart, write_vstart }, | ||
| 48 | + [CSR_VXSAT] = { "vxsat", vs, read_vxsat, write_vxsat }, | ||
| 49 | + [CSR_VXRM] = { "vxrm", vs, read_vxrm, write_vxrm }, | ||
| 50 | + [CSR_VL] = { "vl", vs, read_vl }, | ||
| 51 | + [CSR_VTYPE] = { "vtype", vs, read_vtype }, | ||
| 52 | /* User Timers and Counters */ | ||
| 53 | - [CSR_CYCLE] = { ctr, read_instret }, | ||
| 54 | - [CSR_INSTRET] = { ctr, read_instret }, | ||
| 55 | - [CSR_CYCLEH] = { ctr32, read_instreth }, | ||
| 56 | - [CSR_INSTRETH] = { ctr32, read_instreth }, | ||
| 57 | - | ||
| 58 | - /* In privileged mode, the monitor will have to emulate TIME CSRs only if | ||
| 59 | - * rdtime callback is not provided by machine/platform emulation */ | ||
| 60 | - [CSR_TIME] = { ctr, read_time }, | ||
| 61 | - [CSR_TIMEH] = { ctr32, read_timeh }, | ||
| 62 | + [CSR_CYCLE] = { "cycle", ctr, read_instret }, | ||
| 63 | + [CSR_INSTRET] = { "instret", ctr, read_instret }, | ||
| 64 | + [CSR_CYCLEH] = { "cycleh", ctr32, read_instreth }, | ||
| 65 | + [CSR_INSTRETH] = { "instreth", ctr32, read_instreth }, | ||
| 66 | + | ||
| 67 | + /* | ||
| 68 | + * In privileged mode, the monitor will have to emulate TIME CSRs only if | ||
| 69 | + * rdtime callback is not provided by machine/platform emulation. | ||
| 70 | + */ | ||
| 71 | + [CSR_TIME] = { "time", ctr, read_time }, | ||
| 72 | + [CSR_TIMEH] = { "timeh", ctr32, read_timeh }, | ||
| 73 | |||
| 74 | #if !defined(CONFIG_USER_ONLY) | ||
| 75 | /* Machine Timers and Counters */ | ||
| 76 | - [CSR_MCYCLE] = { any, read_instret }, | ||
| 77 | - [CSR_MINSTRET] = { any, read_instret }, | ||
| 78 | - [CSR_MCYCLEH] = { any32, read_instreth }, | ||
| 79 | - [CSR_MINSTRETH] = { any32, read_instreth }, | ||
| 80 | + [CSR_MCYCLE] = { "mcycle", any, read_instret }, | ||
| 81 | + [CSR_MINSTRET] = { "minstret", any, read_instret }, | ||
| 82 | + [CSR_MCYCLEH] = { "mcycleh", any32, read_instreth }, | ||
| 83 | + [CSR_MINSTRETH] = { "minstreth", any32, read_instreth }, | ||
| 84 | |||
| 85 | /* Machine Information Registers */ | ||
| 86 | - [CSR_MVENDORID] = { any, read_zero }, | ||
| 87 | - [CSR_MARCHID] = { any, read_zero }, | ||
| 88 | - [CSR_MIMPID] = { any, read_zero }, | ||
| 89 | - [CSR_MHARTID] = { any, read_mhartid }, | ||
| 90 | + [CSR_MVENDORID] = { "mvendorid", any, read_zero }, | ||
| 91 | + [CSR_MARCHID] = { "marchid", any, read_zero }, | ||
| 92 | + [CSR_MIMPID] = { "mimpid", any, read_zero }, | ||
| 93 | + [CSR_MHARTID] = { "mhartid", any, read_mhartid }, | ||
| 94 | |||
| 95 | /* Machine Trap Setup */ | ||
| 96 | - [CSR_MSTATUS] = { any, read_mstatus, write_mstatus }, | ||
| 97 | - [CSR_MISA] = { any, read_misa, write_misa }, | ||
| 98 | - [CSR_MIDELEG] = { any, read_mideleg, write_mideleg }, | ||
| 99 | - [CSR_MEDELEG] = { any, read_medeleg, write_medeleg }, | ||
| 100 | - [CSR_MIE] = { any, read_mie, write_mie }, | ||
| 101 | - [CSR_MTVEC] = { any, read_mtvec, write_mtvec }, | ||
| 102 | - [CSR_MCOUNTEREN] = { any, read_mcounteren, write_mcounteren }, | ||
| 103 | + [CSR_MSTATUS] = { "mstatus", any, read_mstatus, write_mstatus }, | ||
| 104 | + [CSR_MISA] = { "misa", any, read_misa, write_misa }, | ||
| 105 | + [CSR_MIDELEG] = { "mideleg", any, read_mideleg, write_mideleg }, | ||
| 106 | + [CSR_MEDELEG] = { "medeleg", any, read_medeleg, write_medeleg }, | ||
| 107 | + [CSR_MIE] = { "mie", any, read_mie, write_mie }, | ||
| 108 | + [CSR_MTVEC] = { "mtvec", any, read_mtvec, write_mtvec }, | ||
| 109 | + [CSR_MCOUNTEREN] = { "mcounteren", any, read_mcounteren, write_mcounteren }, | ||
| 110 | |||
| 111 | - [CSR_MSTATUSH] = { any32, read_mstatush, write_mstatush }, | ||
| 112 | + [CSR_MSTATUSH] = { "mstatush", any32, read_mstatush, write_mstatush }, | ||
| 113 | |||
| 114 | - [CSR_MSCOUNTEREN] = { any, read_mscounteren, write_mscounteren }, | ||
| 115 | + [CSR_MSCOUNTEREN] = { "msounteren", any, read_mscounteren, write_mscounteren }, | ||
| 116 | |||
| 117 | /* Machine Trap Handling */ | ||
| 118 | - [CSR_MSCRATCH] = { any, read_mscratch, write_mscratch }, | ||
| 119 | - [CSR_MEPC] = { any, read_mepc, write_mepc }, | ||
| 120 | - [CSR_MCAUSE] = { any, read_mcause, write_mcause }, | ||
| 121 | - [CSR_MBADADDR] = { any, read_mbadaddr, write_mbadaddr }, | ||
| 122 | - [CSR_MIP] = { any, NULL, NULL, rmw_mip }, | ||
| 123 | + [CSR_MSCRATCH] = { "mscratch", any, read_mscratch, write_mscratch }, | ||
| 124 | + [CSR_MEPC] = { "mepc", any, read_mepc, write_mepc }, | ||
| 125 | + [CSR_MCAUSE] = { "mcause", any, read_mcause, write_mcause }, | ||
| 126 | + [CSR_MBADADDR] = { "mbadaddr", any, read_mbadaddr, write_mbadaddr }, | ||
| 127 | + [CSR_MIP] = { "mip", any, NULL, NULL, rmw_mip }, | ||
| 128 | |||
| 129 | /* Supervisor Trap Setup */ | ||
| 130 | - [CSR_SSTATUS] = { smode, read_sstatus, write_sstatus }, | ||
| 131 | - [CSR_SIE] = { smode, read_sie, write_sie }, | ||
| 132 | - [CSR_STVEC] = { smode, read_stvec, write_stvec }, | ||
| 133 | - [CSR_SCOUNTEREN] = { smode, read_scounteren, write_scounteren }, | ||
| 134 | + [CSR_SSTATUS] = { "sstatus", smode, read_sstatus, write_sstatus }, | ||
| 135 | + [CSR_SIE] = { "sie", smode, read_sie, write_sie }, | ||
| 136 | + [CSR_STVEC] = { "stvec", smode, read_stvec, write_stvec }, | ||
| 137 | + [CSR_SCOUNTEREN] = { "scounteren", smode, read_scounteren, write_scounteren }, | ||
| 138 | |||
| 139 | /* Supervisor Trap Handling */ | ||
| 140 | - [CSR_SSCRATCH] = { smode, read_sscratch, write_sscratch }, | ||
| 141 | - [CSR_SEPC] = { smode, read_sepc, write_sepc }, | ||
| 142 | - [CSR_SCAUSE] = { smode, read_scause, write_scause }, | ||
| 143 | - [CSR_SBADADDR] = { smode, read_sbadaddr, write_sbadaddr }, | ||
| 144 | - [CSR_SIP] = { smode, NULL, NULL, rmw_sip }, | ||
| 145 | + [CSR_SSCRATCH] = { "sscratch", smode, read_sscratch, write_sscratch }, | ||
| 146 | + [CSR_SEPC] = { "sepc", smode, read_sepc, write_sepc }, | ||
| 147 | + [CSR_SCAUSE] = { "scause", smode, read_scause, write_scause }, | ||
| 148 | + [CSR_SBADADDR] = { "sbadaddr", smode, read_sbadaddr, write_sbadaddr }, | ||
| 149 | + [CSR_SIP] = { "sip", smode, NULL, NULL, rmw_sip }, | ||
| 150 | |||
| 151 | /* Supervisor Protection and Translation */ | ||
| 152 | - [CSR_SATP] = { smode, read_satp, write_satp }, | ||
| 153 | - | ||
| 154 | - [CSR_HSTATUS] = { hmode, read_hstatus, write_hstatus }, | ||
| 155 | - [CSR_HEDELEG] = { hmode, read_hedeleg, write_hedeleg }, | ||
| 156 | - [CSR_HIDELEG] = { hmode, read_hideleg, write_hideleg }, | ||
| 157 | - [CSR_HVIP] = { hmode, NULL, NULL, rmw_hvip }, | ||
| 158 | - [CSR_HIP] = { hmode, NULL, NULL, rmw_hip }, | ||
| 159 | - [CSR_HIE] = { hmode, read_hie, write_hie }, | ||
| 160 | - [CSR_HCOUNTEREN] = { hmode, read_hcounteren, write_hcounteren }, | ||
| 161 | - [CSR_HGEIE] = { hmode, read_hgeie, write_hgeie }, | ||
| 162 | - [CSR_HTVAL] = { hmode, read_htval, write_htval }, | ||
| 163 | - [CSR_HTINST] = { hmode, read_htinst, write_htinst }, | ||
| 164 | - [CSR_HGEIP] = { hmode, read_hgeip, write_hgeip }, | ||
| 165 | - [CSR_HGATP] = { hmode, read_hgatp, write_hgatp }, | ||
| 166 | - [CSR_HTIMEDELTA] = { hmode, read_htimedelta, write_htimedelta }, | ||
| 167 | - [CSR_HTIMEDELTAH] = { hmode32, read_htimedeltah, write_htimedeltah}, | ||
| 168 | - | ||
| 169 | - [CSR_VSSTATUS] = { hmode, read_vsstatus, write_vsstatus }, | ||
| 170 | - [CSR_VSIP] = { hmode, NULL, NULL, rmw_vsip }, | ||
| 171 | - [CSR_VSIE] = { hmode, read_vsie, write_vsie }, | ||
| 172 | - [CSR_VSTVEC] = { hmode, read_vstvec, write_vstvec }, | ||
| 173 | - [CSR_VSSCRATCH] = { hmode, read_vsscratch, write_vsscratch }, | ||
| 174 | - [CSR_VSEPC] = { hmode, read_vsepc, write_vsepc }, | ||
| 175 | - [CSR_VSCAUSE] = { hmode, read_vscause, write_vscause }, | ||
| 176 | - [CSR_VSTVAL] = { hmode, read_vstval, write_vstval }, | ||
| 177 | - [CSR_VSATP] = { hmode, read_vsatp, write_vsatp }, | ||
| 178 | - | ||
| 179 | - [CSR_MTVAL2] = { hmode, read_mtval2, write_mtval2 }, | ||
| 180 | - [CSR_MTINST] = { hmode, read_mtinst, write_mtinst }, | ||
| 181 | + [CSR_SATP] = { "satp", smode, read_satp, write_satp }, | ||
| 182 | + | ||
| 183 | + [CSR_HSTATUS] = { "hstatus", hmode, read_hstatus, write_hstatus }, | ||
| 184 | + [CSR_HEDELEG] = { "hedeleg", hmode, read_hedeleg, write_hedeleg }, | ||
| 185 | + [CSR_HIDELEG] = { "hideleg", hmode, read_hideleg, write_hideleg }, | ||
| 186 | + [CSR_HVIP] = { "hvip", hmode, NULL, NULL, rmw_hvip }, | ||
| 187 | + [CSR_HIP] = { "hip", hmode, NULL, NULL, rmw_hip }, | ||
| 188 | + [CSR_HIE] = { "hie", hmode, read_hie, write_hie }, | ||
| 189 | + [CSR_HCOUNTEREN] = { "hcounteren", hmode, read_hcounteren, write_hcounteren }, | ||
| 190 | + [CSR_HGEIE] = { "hgeie", hmode, read_hgeie, write_hgeie }, | ||
| 191 | + [CSR_HTVAL] = { "htval", hmode, read_htval, write_htval }, | ||
| 192 | + [CSR_HTINST] = { "htinst", hmode, read_htinst, write_htinst }, | ||
| 193 | + [CSR_HGEIP] = { "hgeip", hmode, read_hgeip, write_hgeip }, | ||
| 194 | + [CSR_HGATP] = { "hgatp", hmode, read_hgatp, write_hgatp }, | ||
| 195 | + [CSR_HTIMEDELTA] = { "htimedelta", hmode, read_htimedelta, write_htimedelta }, | ||
| 196 | + [CSR_HTIMEDELTAH] = { "htimedeltah", hmode32, read_htimedeltah, write_htimedeltah }, | ||
| 197 | + | ||
| 198 | + [CSR_VSSTATUS] = { "vsstatus", hmode, read_vsstatus, write_vsstatus }, | ||
| 199 | + [CSR_VSIP] = { "vsip", hmode, NULL, NULL, rmw_vsip }, | ||
| 200 | + [CSR_VSIE] = { "vsie", hmode, read_vsie, write_vsie }, | ||
| 201 | + [CSR_VSTVEC] = { "vstvec", hmode, read_vstvec, write_vstvec }, | ||
| 202 | + [CSR_VSSCRATCH] = { "vsscratch", hmode, read_vsscratch, write_vsscratch }, | ||
| 203 | + [CSR_VSEPC] = { "vsepc", hmode, read_vsepc, write_vsepc }, | ||
| 204 | + [CSR_VSCAUSE] = { "vscause", hmode, read_vscause, write_vscause }, | ||
| 205 | + [CSR_VSTVAL] = { "vstval", hmode, read_vstval, write_vstval }, | ||
| 206 | + [CSR_VSATP] = { "vsatp", hmode, read_vsatp, write_vsatp }, | ||
| 207 | + | ||
| 208 | + [CSR_MTVAL2] = { "mtval2", hmode, read_mtval2, write_mtval2 }, | ||
| 209 | + [CSR_MTINST] = { "mtinst", hmode, read_mtinst, write_mtinst }, | ||
| 210 | |||
| 211 | /* Physical Memory Protection */ | ||
| 212 | - [CSR_PMPCFG0 ... CSR_PMPCFG3] = { pmp, read_pmpcfg, write_pmpcfg }, | ||
| 213 | - [CSR_PMPADDR0 ... CSR_PMPADDR15] = { pmp, read_pmpaddr, write_pmpaddr }, | ||
| 214 | + [CSR_PMPCFG0] = { "pmpcfg0", pmp, read_pmpcfg, write_pmpcfg }, | ||
| 215 | + [CSR_PMPCFG1] = { "pmpcfg1", pmp, read_pmpcfg, write_pmpcfg }, | ||
| 216 | + [CSR_PMPCFG2] = { "pmpcfg2", pmp, read_pmpcfg, write_pmpcfg }, | ||
| 217 | + [CSR_PMPCFG3] = { "pmpcfg3", pmp, read_pmpcfg, write_pmpcfg }, | ||
| 218 | + [CSR_PMPADDR0] = { "pmpaddr0", pmp, read_pmpaddr, write_pmpaddr }, | ||
| 219 | + [CSR_PMPADDR1] = { "pmpaddr1", pmp, read_pmpaddr, write_pmpaddr }, | ||
| 220 | + [CSR_PMPADDR2] = { "pmpaddr2", pmp, read_pmpaddr, write_pmpaddr }, | ||
| 221 | + [CSR_PMPADDR3] = { "pmpaddr3", pmp, read_pmpaddr, write_pmpaddr }, | ||
| 222 | + [CSR_PMPADDR4] = { "pmpaddr4", pmp, read_pmpaddr, write_pmpaddr }, | ||
| 223 | + [CSR_PMPADDR5] = { "pmpaddr5", pmp, read_pmpaddr, write_pmpaddr }, | ||
| 224 | + [CSR_PMPADDR6] = { "pmpaddr6", pmp, read_pmpaddr, write_pmpaddr }, | ||
| 225 | + [CSR_PMPADDR7] = { "pmpaddr7", pmp, read_pmpaddr, write_pmpaddr }, | ||
| 226 | + [CSR_PMPADDR8] = { "pmpaddr8", pmp, read_pmpaddr, write_pmpaddr }, | ||
| 227 | + [CSR_PMPADDR9] = { "pmpaddr9", pmp, read_pmpaddr, write_pmpaddr }, | ||
| 228 | + [CSR_PMPADDR10] = { "pmpaddr10", pmp, read_pmpaddr, write_pmpaddr }, | ||
| 229 | + [CSR_PMPADDR11] = { "pmpaddr11", pmp, read_pmpaddr, write_pmpaddr }, | ||
| 230 | + [CSR_PMPADDR12] = { "pmpaddr12", pmp, read_pmpaddr, write_pmpaddr }, | ||
| 231 | + [CSR_PMPADDR13] = { "pmpaddr13", pmp, read_pmpaddr, write_pmpaddr }, | ||
| 232 | + [CSR_PMPADDR14] = { "pmpaddr14", pmp, read_pmpaddr, write_pmpaddr }, | ||
| 233 | + [CSR_PMPADDR15] = { "pmpaddr15", pmp, read_pmpaddr, write_pmpaddr }, | ||
| 234 | |||
| 235 | /* Performance Counters */ | ||
| 236 | - [CSR_HPMCOUNTER3 ... CSR_HPMCOUNTER31] = { ctr, read_zero }, | ||
| 237 | - [CSR_MHPMCOUNTER3 ... CSR_MHPMCOUNTER31] = { any, read_zero }, | ||
| 238 | - [CSR_MHPMEVENT3 ... CSR_MHPMEVENT31] = { any, read_zero }, | ||
| 239 | - [CSR_HPMCOUNTER3H ... CSR_HPMCOUNTER31H] = { ctr32, read_zero }, | ||
| 240 | - [CSR_MHPMCOUNTER3H ... CSR_MHPMCOUNTER31H] = { any32, read_zero }, | ||
| 241 | + [CSR_HPMCOUNTER3] = { "hpmcounter3", ctr, read_zero }, | ||
| 242 | + [CSR_HPMCOUNTER4] = { "hpmcounter4", ctr, read_zero }, | ||
| 243 | + [CSR_HPMCOUNTER5] = { "hpmcounter5", ctr, read_zero }, | ||
| 244 | + [CSR_HPMCOUNTER6] = { "hpmcounter6", ctr, read_zero }, | ||
| 245 | + [CSR_HPMCOUNTER7] = { "hpmcounter7", ctr, read_zero }, | ||
| 246 | + [CSR_HPMCOUNTER8] = { "hpmcounter8", ctr, read_zero }, | ||
| 247 | + [CSR_HPMCOUNTER9] = { "hpmcounter9", ctr, read_zero }, | ||
| 248 | + [CSR_HPMCOUNTER10] = { "hpmcounter10", ctr, read_zero }, | ||
| 249 | + [CSR_HPMCOUNTER11] = { "hpmcounter11", ctr, read_zero }, | ||
| 250 | + [CSR_HPMCOUNTER12] = { "hpmcounter12", ctr, read_zero }, | ||
| 251 | + [CSR_HPMCOUNTER13] = { "hpmcounter13", ctr, read_zero }, | ||
| 252 | + [CSR_HPMCOUNTER14] = { "hpmcounter14", ctr, read_zero }, | ||
| 253 | + [CSR_HPMCOUNTER15] = { "hpmcounter15", ctr, read_zero }, | ||
| 254 | + [CSR_HPMCOUNTER16] = { "hpmcounter16", ctr, read_zero }, | ||
| 255 | + [CSR_HPMCOUNTER17] = { "hpmcounter17", ctr, read_zero }, | ||
| 256 | + [CSR_HPMCOUNTER18] = { "hpmcounter18", ctr, read_zero }, | ||
| 257 | + [CSR_HPMCOUNTER19] = { "hpmcounter19", ctr, read_zero }, | ||
| 258 | + [CSR_HPMCOUNTER20] = { "hpmcounter20", ctr, read_zero }, | ||
| 259 | + [CSR_HPMCOUNTER21] = { "hpmcounter21", ctr, read_zero }, | ||
| 260 | + [CSR_HPMCOUNTER22] = { "hpmcounter22", ctr, read_zero }, | ||
| 261 | + [CSR_HPMCOUNTER23] = { "hpmcounter23", ctr, read_zero }, | ||
| 262 | + [CSR_HPMCOUNTER24] = { "hpmcounter24", ctr, read_zero }, | ||
| 263 | + [CSR_HPMCOUNTER25] = { "hpmcounter25", ctr, read_zero }, | ||
| 264 | + [CSR_HPMCOUNTER26] = { "hpmcounter26", ctr, read_zero }, | ||
| 265 | + [CSR_HPMCOUNTER27] = { "hpmcounter27", ctr, read_zero }, | ||
| 266 | + [CSR_HPMCOUNTER28] = { "hpmcounter28", ctr, read_zero }, | ||
| 267 | + [CSR_HPMCOUNTER29] = { "hpmcounter29", ctr, read_zero }, | ||
| 268 | + [CSR_HPMCOUNTER30] = { "hpmcounter30", ctr, read_zero }, | ||
| 269 | + [CSR_HPMCOUNTER31] = { "hpmcounter31", ctr, read_zero }, | ||
| 270 | + | ||
| 271 | + [CSR_MHPMCOUNTER3] = { "mhpmcounter3", any, read_zero }, | ||
| 272 | + [CSR_MHPMCOUNTER4] = { "mhpmcounter4", any, read_zero }, | ||
| 273 | + [CSR_MHPMCOUNTER5] = { "mhpmcounter5", any, read_zero }, | ||
| 274 | + [CSR_MHPMCOUNTER6] = { "mhpmcounter6", any, read_zero }, | ||
| 275 | + [CSR_MHPMCOUNTER7] = { "mhpmcounter7", any, read_zero }, | ||
| 276 | + [CSR_MHPMCOUNTER8] = { "mhpmcounter8", any, read_zero }, | ||
| 277 | + [CSR_MHPMCOUNTER9] = { "mhpmcounter9", any, read_zero }, | ||
| 278 | + [CSR_MHPMCOUNTER10] = { "mhpmcounter10", any, read_zero }, | ||
| 279 | + [CSR_MHPMCOUNTER11] = { "mhpmcounter11", any, read_zero }, | ||
| 280 | + [CSR_MHPMCOUNTER12] = { "mhpmcounter12", any, read_zero }, | ||
| 281 | + [CSR_MHPMCOUNTER13] = { "mhpmcounter13", any, read_zero }, | ||
| 282 | + [CSR_MHPMCOUNTER14] = { "mhpmcounter14", any, read_zero }, | ||
| 283 | + [CSR_MHPMCOUNTER15] = { "mhpmcounter15", any, read_zero }, | ||
| 284 | + [CSR_MHPMCOUNTER16] = { "mhpmcounter16", any, read_zero }, | ||
| 285 | + [CSR_MHPMCOUNTER17] = { "mhpmcounter17", any, read_zero }, | ||
| 286 | + [CSR_MHPMCOUNTER18] = { "mhpmcounter18", any, read_zero }, | ||
| 287 | + [CSR_MHPMCOUNTER19] = { "mhpmcounter19", any, read_zero }, | ||
| 288 | + [CSR_MHPMCOUNTER20] = { "mhpmcounter20", any, read_zero }, | ||
| 289 | + [CSR_MHPMCOUNTER21] = { "mhpmcounter21", any, read_zero }, | ||
| 290 | + [CSR_MHPMCOUNTER22] = { "mhpmcounter22", any, read_zero }, | ||
| 291 | + [CSR_MHPMCOUNTER23] = { "mhpmcounter23", any, read_zero }, | ||
| 292 | + [CSR_MHPMCOUNTER24] = { "mhpmcounter24", any, read_zero }, | ||
| 293 | + [CSR_MHPMCOUNTER25] = { "mhpmcounter25", any, read_zero }, | ||
| 294 | + [CSR_MHPMCOUNTER26] = { "mhpmcounter26", any, read_zero }, | ||
| 295 | + [CSR_MHPMCOUNTER27] = { "mhpmcounter27", any, read_zero }, | ||
| 296 | + [CSR_MHPMCOUNTER28] = { "mhpmcounter28", any, read_zero }, | ||
| 297 | + [CSR_MHPMCOUNTER29] = { "mhpmcounter29", any, read_zero }, | ||
| 298 | + [CSR_MHPMCOUNTER30] = { "mhpmcounter30", any, read_zero }, | ||
| 299 | + [CSR_MHPMCOUNTER31] = { "mhpmcounter31", any, read_zero }, | ||
| 300 | + | ||
| 301 | + [CSR_MHPMEVENT3] = { "mhpmevent3", any, read_zero }, | ||
| 302 | + [CSR_MHPMEVENT4] = { "mhpmevent4", any, read_zero }, | ||
| 303 | + [CSR_MHPMEVENT5] = { "mhpmevent5", any, read_zero }, | ||
| 304 | + [CSR_MHPMEVENT6] = { "mhpmevent6", any, read_zero }, | ||
| 305 | + [CSR_MHPMEVENT7] = { "mhpmevent7", any, read_zero }, | ||
| 306 | + [CSR_MHPMEVENT8] = { "mhpmevent8", any, read_zero }, | ||
| 307 | + [CSR_MHPMEVENT9] = { "mhpmevent9", any, read_zero }, | ||
| 308 | + [CSR_MHPMEVENT10] = { "mhpmevent10", any, read_zero }, | ||
| 309 | + [CSR_MHPMEVENT11] = { "mhpmevent11", any, read_zero }, | ||
| 310 | + [CSR_MHPMEVENT12] = { "mhpmevent12", any, read_zero }, | ||
| 311 | + [CSR_MHPMEVENT13] = { "mhpmevent13", any, read_zero }, | ||
| 312 | + [CSR_MHPMEVENT14] = { "mhpmevent14", any, read_zero }, | ||
| 313 | + [CSR_MHPMEVENT15] = { "mhpmevent15", any, read_zero }, | ||
| 314 | + [CSR_MHPMEVENT16] = { "mhpmevent16", any, read_zero }, | ||
| 315 | + [CSR_MHPMEVENT17] = { "mhpmevent17", any, read_zero }, | ||
| 316 | + [CSR_MHPMEVENT18] = { "mhpmevent18", any, read_zero }, | ||
| 317 | + [CSR_MHPMEVENT19] = { "mhpmevent19", any, read_zero }, | ||
| 318 | + [CSR_MHPMEVENT20] = { "mhpmevent20", any, read_zero }, | ||
| 319 | + [CSR_MHPMEVENT21] = { "mhpmevent21", any, read_zero }, | ||
| 320 | + [CSR_MHPMEVENT22] = { "mhpmevent22", any, read_zero }, | ||
| 321 | + [CSR_MHPMEVENT23] = { "mhpmevent23", any, read_zero }, | ||
| 322 | + [CSR_MHPMEVENT24] = { "mhpmevent24", any, read_zero }, | ||
| 323 | + [CSR_MHPMEVENT25] = { "mhpmevent25", any, read_zero }, | ||
| 324 | + [CSR_MHPMEVENT26] = { "mhpmevent26", any, read_zero }, | ||
| 325 | + [CSR_MHPMEVENT27] = { "mhpmevent27", any, read_zero }, | ||
| 326 | + [CSR_MHPMEVENT28] = { "mhpmevent28", any, read_zero }, | ||
| 327 | + [CSR_MHPMEVENT29] = { "mhpmevent29", any, read_zero }, | ||
| 328 | + [CSR_MHPMEVENT30] = { "mhpmevent30", any, read_zero }, | ||
| 329 | + [CSR_MHPMEVENT31] = { "mhpmevent31", any, read_zero }, | ||
| 330 | + | ||
| 331 | + [CSR_HPMCOUNTER3H] = { "hpmcounter3h", ctr32, read_zero }, | ||
| 332 | + [CSR_HPMCOUNTER4H] = { "hpmcounter4h", ctr32, read_zero }, | ||
| 333 | + [CSR_HPMCOUNTER5H] = { "hpmcounter5h", ctr32, read_zero }, | ||
| 334 | + [CSR_HPMCOUNTER6H] = { "hpmcounter6h", ctr32, read_zero }, | ||
| 335 | + [CSR_HPMCOUNTER7H] = { "hpmcounter7h", ctr32, read_zero }, | ||
| 336 | + [CSR_HPMCOUNTER8H] = { "hpmcounter8h", ctr32, read_zero }, | ||
| 337 | + [CSR_HPMCOUNTER9H] = { "hpmcounter9h", ctr32, read_zero }, | ||
| 338 | + [CSR_HPMCOUNTER10H] = { "hpmcounter10h", ctr32, read_zero }, | ||
| 339 | + [CSR_HPMCOUNTER11H] = { "hpmcounter11h", ctr32, read_zero }, | ||
| 340 | + [CSR_HPMCOUNTER12H] = { "hpmcounter12h", ctr32, read_zero }, | ||
| 341 | + [CSR_HPMCOUNTER13H] = { "hpmcounter13h", ctr32, read_zero }, | ||
| 342 | + [CSR_HPMCOUNTER14H] = { "hpmcounter14h", ctr32, read_zero }, | ||
| 343 | + [CSR_HPMCOUNTER15H] = { "hpmcounter15h", ctr32, read_zero }, | ||
| 344 | + [CSR_HPMCOUNTER16H] = { "hpmcounter16h", ctr32, read_zero }, | ||
| 345 | + [CSR_HPMCOUNTER17H] = { "hpmcounter17h", ctr32, read_zero }, | ||
| 346 | + [CSR_HPMCOUNTER18H] = { "hpmcounter18h", ctr32, read_zero }, | ||
| 347 | + [CSR_HPMCOUNTER19H] = { "hpmcounter19h", ctr32, read_zero }, | ||
| 348 | + [CSR_HPMCOUNTER20H] = { "hpmcounter20h", ctr32, read_zero }, | ||
| 349 | + [CSR_HPMCOUNTER21H] = { "hpmcounter21h", ctr32, read_zero }, | ||
| 350 | + [CSR_HPMCOUNTER22H] = { "hpmcounter22h", ctr32, read_zero }, | ||
| 351 | + [CSR_HPMCOUNTER23H] = { "hpmcounter23h", ctr32, read_zero }, | ||
| 352 | + [CSR_HPMCOUNTER24H] = { "hpmcounter24h", ctr32, read_zero }, | ||
| 353 | + [CSR_HPMCOUNTER25H] = { "hpmcounter25h", ctr32, read_zero }, | ||
| 354 | + [CSR_HPMCOUNTER26H] = { "hpmcounter26h", ctr32, read_zero }, | ||
| 355 | + [CSR_HPMCOUNTER27H] = { "hpmcounter27h", ctr32, read_zero }, | ||
| 356 | + [CSR_HPMCOUNTER28H] = { "hpmcounter28h", ctr32, read_zero }, | ||
| 357 | + [CSR_HPMCOUNTER29H] = { "hpmcounter29h", ctr32, read_zero }, | ||
| 358 | + [CSR_HPMCOUNTER30H] = { "hpmcounter30h", ctr32, read_zero }, | ||
| 359 | + [CSR_HPMCOUNTER31H] = { "hpmcounter31h", ctr32, read_zero }, | ||
| 360 | + | ||
| 361 | + [CSR_MHPMCOUNTER3H] = { "mhpmcounter3h", any32, read_zero }, | ||
| 362 | + [CSR_MHPMCOUNTER4H] = { "mhpmcounter4h", any32, read_zero }, | ||
| 363 | + [CSR_MHPMCOUNTER5H] = { "mhpmcounter5h", any32, read_zero }, | ||
| 364 | + [CSR_MHPMCOUNTER6H] = { "mhpmcounter6h", any32, read_zero }, | ||
| 365 | + [CSR_MHPMCOUNTER7H] = { "mhpmcounter7h", any32, read_zero }, | ||
| 366 | + [CSR_MHPMCOUNTER8H] = { "mhpmcounter8h", any32, read_zero }, | ||
| 367 | + [CSR_MHPMCOUNTER9H] = { "mhpmcounter9h", any32, read_zero }, | ||
| 368 | + [CSR_MHPMCOUNTER10H] = { "mhpmcounter10h", any32, read_zero }, | ||
| 369 | + [CSR_MHPMCOUNTER11H] = { "mhpmcounter11h", any32, read_zero }, | ||
| 370 | + [CSR_MHPMCOUNTER12H] = { "mhpmcounter12h", any32, read_zero }, | ||
| 371 | + [CSR_MHPMCOUNTER13H] = { "mhpmcounter13h", any32, read_zero }, | ||
| 372 | + [CSR_MHPMCOUNTER14H] = { "mhpmcounter14h", any32, read_zero }, | ||
| 373 | + [CSR_MHPMCOUNTER15H] = { "mhpmcounter15h", any32, read_zero }, | ||
| 374 | + [CSR_MHPMCOUNTER16H] = { "mhpmcounter16h", any32, read_zero }, | ||
| 375 | + [CSR_MHPMCOUNTER17H] = { "mhpmcounter17h", any32, read_zero }, | ||
| 376 | + [CSR_MHPMCOUNTER18H] = { "mhpmcounter18h", any32, read_zero }, | ||
| 377 | + [CSR_MHPMCOUNTER19H] = { "mhpmcounter19h", any32, read_zero }, | ||
| 378 | + [CSR_MHPMCOUNTER20H] = { "mhpmcounter20h", any32, read_zero }, | ||
| 379 | + [CSR_MHPMCOUNTER21H] = { "mhpmcounter21h", any32, read_zero }, | ||
| 380 | + [CSR_MHPMCOUNTER22H] = { "mhpmcounter22h", any32, read_zero }, | ||
| 381 | + [CSR_MHPMCOUNTER23H] = { "mhpmcounter23h", any32, read_zero }, | ||
| 382 | + [CSR_MHPMCOUNTER24H] = { "mhpmcounter24h", any32, read_zero }, | ||
| 383 | + [CSR_MHPMCOUNTER25H] = { "mhpmcounter25h", any32, read_zero }, | ||
| 384 | + [CSR_MHPMCOUNTER26H] = { "mhpmcounter26h", any32, read_zero }, | ||
| 385 | + [CSR_MHPMCOUNTER27H] = { "mhpmcounter27h", any32, read_zero }, | ||
| 386 | + [CSR_MHPMCOUNTER28H] = { "mhpmcounter28h", any32, read_zero }, | ||
| 387 | + [CSR_MHPMCOUNTER29H] = { "mhpmcounter29h", any32, read_zero }, | ||
| 388 | + [CSR_MHPMCOUNTER30H] = { "mhpmcounter30h", any32, read_zero }, | ||
| 389 | + [CSR_MHPMCOUNTER31H] = { "mhpmcounter31h", any32, read_zero }, | ||
| 390 | #endif /* !CONFIG_USER_ONLY */ | ||
| 391 | }; | ||
| 392 | -- | ||
| 393 | 2.29.2 | ||
| 394 | |||
| 395 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | From: Bin Meng <bin.meng@windriver.com> | ||
| 2 | 1 | ||
| 3 | Now that we have switched to generate the RISC-V CSR XML dynamically, | ||
| 4 | remove the built-in hardcoded XML files. | ||
| 5 | |||
| 6 | Signed-off-by: Bin Meng <bin.meng@windriver.com> | ||
| 7 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 8 | Message-id: 20210116054123.5457-3-bmeng.cn@gmail.com | ||
| 9 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 10 | --- | ||
| 11 | .../targets/riscv32-linux-user.mak | 2 +- | ||
| 12 | default-configs/targets/riscv32-softmmu.mak | 2 +- | ||
| 13 | .../targets/riscv64-linux-user.mak | 2 +- | ||
| 14 | default-configs/targets/riscv64-softmmu.mak | 2 +- | ||
| 15 | gdb-xml/riscv-32bit-csr.xml | 250 ------------------ | ||
| 16 | gdb-xml/riscv-64bit-csr.xml | 250 ------------------ | ||
| 17 | 6 files changed, 4 insertions(+), 504 deletions(-) | ||
| 18 | delete mode 100644 gdb-xml/riscv-32bit-csr.xml | ||
| 19 | delete mode 100644 gdb-xml/riscv-64bit-csr.xml | ||
| 20 | |||
| 21 | diff --git a/default-configs/targets/riscv32-linux-user.mak b/default-configs/targets/riscv32-linux-user.mak | ||
| 22 | index XXXXXXX..XXXXXXX 100644 | ||
| 23 | --- a/default-configs/targets/riscv32-linux-user.mak | ||
| 24 | +++ b/default-configs/targets/riscv32-linux-user.mak | ||
| 25 | @@ -XXX,XX +XXX,XX @@ | ||
| 26 | TARGET_ARCH=riscv32 | ||
| 27 | TARGET_BASE_ARCH=riscv | ||
| 28 | TARGET_ABI_DIR=riscv | ||
| 29 | -TARGET_XML_FILES= gdb-xml/riscv-32bit-cpu.xml gdb-xml/riscv-32bit-fpu.xml gdb-xml/riscv-64bit-fpu.xml gdb-xml/riscv-32bit-csr.xml gdb-xml/riscv-32bit-virtual.xml | ||
| 30 | +TARGET_XML_FILES= gdb-xml/riscv-32bit-cpu.xml gdb-xml/riscv-32bit-fpu.xml gdb-xml/riscv-64bit-fpu.xml gdb-xml/riscv-32bit-virtual.xml | ||
| 31 | diff --git a/default-configs/targets/riscv32-softmmu.mak b/default-configs/targets/riscv32-softmmu.mak | ||
| 32 | index XXXXXXX..XXXXXXX 100644 | ||
| 33 | --- a/default-configs/targets/riscv32-softmmu.mak | ||
| 34 | +++ b/default-configs/targets/riscv32-softmmu.mak | ||
| 35 | @@ -XXX,XX +XXX,XX @@ | ||
| 36 | TARGET_ARCH=riscv32 | ||
| 37 | TARGET_BASE_ARCH=riscv | ||
| 38 | TARGET_SUPPORTS_MTTCG=y | ||
| 39 | -TARGET_XML_FILES= gdb-xml/riscv-32bit-cpu.xml gdb-xml/riscv-32bit-fpu.xml gdb-xml/riscv-64bit-fpu.xml gdb-xml/riscv-32bit-csr.xml gdb-xml/riscv-32bit-virtual.xml | ||
| 40 | +TARGET_XML_FILES= gdb-xml/riscv-32bit-cpu.xml gdb-xml/riscv-32bit-fpu.xml gdb-xml/riscv-64bit-fpu.xml gdb-xml/riscv-32bit-virtual.xml | ||
| 41 | TARGET_NEED_FDT=y | ||
| 42 | diff --git a/default-configs/targets/riscv64-linux-user.mak b/default-configs/targets/riscv64-linux-user.mak | ||
| 43 | index XXXXXXX..XXXXXXX 100644 | ||
| 44 | --- a/default-configs/targets/riscv64-linux-user.mak | ||
| 45 | +++ b/default-configs/targets/riscv64-linux-user.mak | ||
| 46 | @@ -XXX,XX +XXX,XX @@ | ||
| 47 | TARGET_ARCH=riscv64 | ||
| 48 | TARGET_BASE_ARCH=riscv | ||
| 49 | TARGET_ABI_DIR=riscv | ||
| 50 | -TARGET_XML_FILES= gdb-xml/riscv-64bit-cpu.xml gdb-xml/riscv-32bit-fpu.xml gdb-xml/riscv-64bit-fpu.xml gdb-xml/riscv-64bit-csr.xml gdb-xml/riscv-64bit-virtual.xml | ||
| 51 | +TARGET_XML_FILES= gdb-xml/riscv-64bit-cpu.xml gdb-xml/riscv-32bit-fpu.xml gdb-xml/riscv-64bit-fpu.xml gdb-xml/riscv-64bit-virtual.xml | ||
| 52 | diff --git a/default-configs/targets/riscv64-softmmu.mak b/default-configs/targets/riscv64-softmmu.mak | ||
| 53 | index XXXXXXX..XXXXXXX 100644 | ||
| 54 | --- a/default-configs/targets/riscv64-softmmu.mak | ||
| 55 | +++ b/default-configs/targets/riscv64-softmmu.mak | ||
| 56 | @@ -XXX,XX +XXX,XX @@ | ||
| 57 | TARGET_ARCH=riscv64 | ||
| 58 | TARGET_BASE_ARCH=riscv | ||
| 59 | TARGET_SUPPORTS_MTTCG=y | ||
| 60 | -TARGET_XML_FILES= gdb-xml/riscv-64bit-cpu.xml gdb-xml/riscv-32bit-fpu.xml gdb-xml/riscv-64bit-fpu.xml gdb-xml/riscv-64bit-csr.xml gdb-xml/riscv-64bit-virtual.xml | ||
| 61 | +TARGET_XML_FILES= gdb-xml/riscv-64bit-cpu.xml gdb-xml/riscv-32bit-fpu.xml gdb-xml/riscv-64bit-fpu.xml gdb-xml/riscv-64bit-virtual.xml | ||
| 62 | TARGET_NEED_FDT=y | ||
| 63 | diff --git a/gdb-xml/riscv-32bit-csr.xml b/gdb-xml/riscv-32bit-csr.xml | ||
| 64 | deleted file mode 100644 | ||
| 65 | index XXXXXXX..XXXXXXX | ||
| 66 | --- a/gdb-xml/riscv-32bit-csr.xml | ||
| 67 | +++ /dev/null | ||
| 68 | @@ -XXX,XX +XXX,XX @@ | ||
| 69 | -<?xml version="1.0"?> | ||
| 70 | -<!-- Copyright (C) 2018-2019 Free Software Foundation, Inc. | ||
| 71 | - | ||
| 72 | - Copying and distribution of this file, with or without modification, | ||
| 73 | - are permitted in any medium without royalty provided the copyright | ||
| 74 | - notice and this notice are preserved. --> | ||
| 75 | - | ||
| 76 | -<!DOCTYPE feature SYSTEM "gdb-target.dtd"> | ||
| 77 | -<feature name="org.gnu.gdb.riscv.csr"> | ||
| 78 | - <reg name="ustatus" bitsize="32"/> | ||
| 79 | - <reg name="uie" bitsize="32"/> | ||
| 80 | - <reg name="utvec" bitsize="32"/> | ||
| 81 | - <reg name="uscratch" bitsize="32"/> | ||
| 82 | - <reg name="uepc" bitsize="32"/> | ||
| 83 | - <reg name="ucause" bitsize="32"/> | ||
| 84 | - <reg name="utval" bitsize="32"/> | ||
| 85 | - <reg name="uip" bitsize="32"/> | ||
| 86 | - <reg name="fflags" bitsize="32"/> | ||
| 87 | - <reg name="frm" bitsize="32"/> | ||
| 88 | - <reg name="fcsr" bitsize="32"/> | ||
| 89 | - <reg name="cycle" bitsize="32"/> | ||
| 90 | - <reg name="time" bitsize="32"/> | ||
| 91 | - <reg name="instret" bitsize="32"/> | ||
| 92 | - <reg name="hpmcounter3" bitsize="32"/> | ||
| 93 | - <reg name="hpmcounter4" bitsize="32"/> | ||
| 94 | - <reg name="hpmcounter5" bitsize="32"/> | ||
| 95 | - <reg name="hpmcounter6" bitsize="32"/> | ||
| 96 | - <reg name="hpmcounter7" bitsize="32"/> | ||
| 97 | - <reg name="hpmcounter8" bitsize="32"/> | ||
| 98 | - <reg name="hpmcounter9" bitsize="32"/> | ||
| 99 | - <reg name="hpmcounter10" bitsize="32"/> | ||
| 100 | - <reg name="hpmcounter11" bitsize="32"/> | ||
| 101 | - <reg name="hpmcounter12" bitsize="32"/> | ||
| 102 | - <reg name="hpmcounter13" bitsize="32"/> | ||
| 103 | - <reg name="hpmcounter14" bitsize="32"/> | ||
| 104 | - <reg name="hpmcounter15" bitsize="32"/> | ||
| 105 | - <reg name="hpmcounter16" bitsize="32"/> | ||
| 106 | - <reg name="hpmcounter17" bitsize="32"/> | ||
| 107 | - <reg name="hpmcounter18" bitsize="32"/> | ||
| 108 | - <reg name="hpmcounter19" bitsize="32"/> | ||
| 109 | - <reg name="hpmcounter20" bitsize="32"/> | ||
| 110 | - <reg name="hpmcounter21" bitsize="32"/> | ||
| 111 | - <reg name="hpmcounter22" bitsize="32"/> | ||
| 112 | - <reg name="hpmcounter23" bitsize="32"/> | ||
| 113 | - <reg name="hpmcounter24" bitsize="32"/> | ||
| 114 | - <reg name="hpmcounter25" bitsize="32"/> | ||
| 115 | - <reg name="hpmcounter26" bitsize="32"/> | ||
| 116 | - <reg name="hpmcounter27" bitsize="32"/> | ||
| 117 | - <reg name="hpmcounter28" bitsize="32"/> | ||
| 118 | - <reg name="hpmcounter29" bitsize="32"/> | ||
| 119 | - <reg name="hpmcounter30" bitsize="32"/> | ||
| 120 | - <reg name="hpmcounter31" bitsize="32"/> | ||
| 121 | - <reg name="cycleh" bitsize="32"/> | ||
| 122 | - <reg name="timeh" bitsize="32"/> | ||
| 123 | - <reg name="instreth" bitsize="32"/> | ||
| 124 | - <reg name="hpmcounter3h" bitsize="32"/> | ||
| 125 | - <reg name="hpmcounter4h" bitsize="32"/> | ||
| 126 | - <reg name="hpmcounter5h" bitsize="32"/> | ||
| 127 | - <reg name="hpmcounter6h" bitsize="32"/> | ||
| 128 | - <reg name="hpmcounter7h" bitsize="32"/> | ||
| 129 | - <reg name="hpmcounter8h" bitsize="32"/> | ||
| 130 | - <reg name="hpmcounter9h" bitsize="32"/> | ||
| 131 | - <reg name="hpmcounter10h" bitsize="32"/> | ||
| 132 | - <reg name="hpmcounter11h" bitsize="32"/> | ||
| 133 | - <reg name="hpmcounter12h" bitsize="32"/> | ||
| 134 | - <reg name="hpmcounter13h" bitsize="32"/> | ||
| 135 | - <reg name="hpmcounter14h" bitsize="32"/> | ||
| 136 | - <reg name="hpmcounter15h" bitsize="32"/> | ||
| 137 | - <reg name="hpmcounter16h" bitsize="32"/> | ||
| 138 | - <reg name="hpmcounter17h" bitsize="32"/> | ||
| 139 | - <reg name="hpmcounter18h" bitsize="32"/> | ||
| 140 | - <reg name="hpmcounter19h" bitsize="32"/> | ||
| 141 | - <reg name="hpmcounter20h" bitsize="32"/> | ||
| 142 | - <reg name="hpmcounter21h" bitsize="32"/> | ||
| 143 | - <reg name="hpmcounter22h" bitsize="32"/> | ||
| 144 | - <reg name="hpmcounter23h" bitsize="32"/> | ||
| 145 | - <reg name="hpmcounter24h" bitsize="32"/> | ||
| 146 | - <reg name="hpmcounter25h" bitsize="32"/> | ||
| 147 | - <reg name="hpmcounter26h" bitsize="32"/> | ||
| 148 | - <reg name="hpmcounter27h" bitsize="32"/> | ||
| 149 | - <reg name="hpmcounter28h" bitsize="32"/> | ||
| 150 | - <reg name="hpmcounter29h" bitsize="32"/> | ||
| 151 | - <reg name="hpmcounter30h" bitsize="32"/> | ||
| 152 | - <reg name="hpmcounter31h" bitsize="32"/> | ||
| 153 | - <reg name="sstatus" bitsize="32"/> | ||
| 154 | - <reg name="sedeleg" bitsize="32"/> | ||
| 155 | - <reg name="sideleg" bitsize="32"/> | ||
| 156 | - <reg name="sie" bitsize="32"/> | ||
| 157 | - <reg name="stvec" bitsize="32"/> | ||
| 158 | - <reg name="scounteren" bitsize="32"/> | ||
| 159 | - <reg name="sscratch" bitsize="32"/> | ||
| 160 | - <reg name="sepc" bitsize="32"/> | ||
| 161 | - <reg name="scause" bitsize="32"/> | ||
| 162 | - <reg name="stval" bitsize="32"/> | ||
| 163 | - <reg name="sip" bitsize="32"/> | ||
| 164 | - <reg name="satp" bitsize="32"/> | ||
| 165 | - <reg name="mvendorid" bitsize="32"/> | ||
| 166 | - <reg name="marchid" bitsize="32"/> | ||
| 167 | - <reg name="mimpid" bitsize="32"/> | ||
| 168 | - <reg name="mhartid" bitsize="32"/> | ||
| 169 | - <reg name="mstatus" bitsize="32"/> | ||
| 170 | - <reg name="misa" bitsize="32"/> | ||
| 171 | - <reg name="medeleg" bitsize="32"/> | ||
| 172 | - <reg name="mideleg" bitsize="32"/> | ||
| 173 | - <reg name="mie" bitsize="32"/> | ||
| 174 | - <reg name="mtvec" bitsize="32"/> | ||
| 175 | - <reg name="mcounteren" bitsize="32"/> | ||
| 176 | - <reg name="mscratch" bitsize="32"/> | ||
| 177 | - <reg name="mepc" bitsize="32"/> | ||
| 178 | - <reg name="mcause" bitsize="32"/> | ||
| 179 | - <reg name="mtval" bitsize="32"/> | ||
| 180 | - <reg name="mip" bitsize="32"/> | ||
| 181 | - <reg name="pmpcfg0" bitsize="32"/> | ||
| 182 | - <reg name="pmpcfg1" bitsize="32"/> | ||
| 183 | - <reg name="pmpcfg2" bitsize="32"/> | ||
| 184 | - <reg name="pmpcfg3" bitsize="32"/> | ||
| 185 | - <reg name="pmpaddr0" bitsize="32"/> | ||
| 186 | - <reg name="pmpaddr1" bitsize="32"/> | ||
| 187 | - <reg name="pmpaddr2" bitsize="32"/> | ||
| 188 | - <reg name="pmpaddr3" bitsize="32"/> | ||
| 189 | - <reg name="pmpaddr4" bitsize="32"/> | ||
| 190 | - <reg name="pmpaddr5" bitsize="32"/> | ||
| 191 | - <reg name="pmpaddr6" bitsize="32"/> | ||
| 192 | - <reg name="pmpaddr7" bitsize="32"/> | ||
| 193 | - <reg name="pmpaddr8" bitsize="32"/> | ||
| 194 | - <reg name="pmpaddr9" bitsize="32"/> | ||
| 195 | - <reg name="pmpaddr10" bitsize="32"/> | ||
| 196 | - <reg name="pmpaddr11" bitsize="32"/> | ||
| 197 | - <reg name="pmpaddr12" bitsize="32"/> | ||
| 198 | - <reg name="pmpaddr13" bitsize="32"/> | ||
| 199 | - <reg name="pmpaddr14" bitsize="32"/> | ||
| 200 | - <reg name="pmpaddr15" bitsize="32"/> | ||
| 201 | - <reg name="mcycle" bitsize="32"/> | ||
| 202 | - <reg name="minstret" bitsize="32"/> | ||
| 203 | - <reg name="mhpmcounter3" bitsize="32"/> | ||
| 204 | - <reg name="mhpmcounter4" bitsize="32"/> | ||
| 205 | - <reg name="mhpmcounter5" bitsize="32"/> | ||
| 206 | - <reg name="mhpmcounter6" bitsize="32"/> | ||
| 207 | - <reg name="mhpmcounter7" bitsize="32"/> | ||
| 208 | - <reg name="mhpmcounter8" bitsize="32"/> | ||
| 209 | - <reg name="mhpmcounter9" bitsize="32"/> | ||
| 210 | - <reg name="mhpmcounter10" bitsize="32"/> | ||
| 211 | - <reg name="mhpmcounter11" bitsize="32"/> | ||
| 212 | - <reg name="mhpmcounter12" bitsize="32"/> | ||
| 213 | - <reg name="mhpmcounter13" bitsize="32"/> | ||
| 214 | - <reg name="mhpmcounter14" bitsize="32"/> | ||
| 215 | - <reg name="mhpmcounter15" bitsize="32"/> | ||
| 216 | - <reg name="mhpmcounter16" bitsize="32"/> | ||
| 217 | - <reg name="mhpmcounter17" bitsize="32"/> | ||
| 218 | - <reg name="mhpmcounter18" bitsize="32"/> | ||
| 219 | - <reg name="mhpmcounter19" bitsize="32"/> | ||
| 220 | - <reg name="mhpmcounter20" bitsize="32"/> | ||
| 221 | - <reg name="mhpmcounter21" bitsize="32"/> | ||
| 222 | - <reg name="mhpmcounter22" bitsize="32"/> | ||
| 223 | - <reg name="mhpmcounter23" bitsize="32"/> | ||
| 224 | - <reg name="mhpmcounter24" bitsize="32"/> | ||
| 225 | - <reg name="mhpmcounter25" bitsize="32"/> | ||
| 226 | - <reg name="mhpmcounter26" bitsize="32"/> | ||
| 227 | - <reg name="mhpmcounter27" bitsize="32"/> | ||
| 228 | - <reg name="mhpmcounter28" bitsize="32"/> | ||
| 229 | - <reg name="mhpmcounter29" bitsize="32"/> | ||
| 230 | - <reg name="mhpmcounter30" bitsize="32"/> | ||
| 231 | - <reg name="mhpmcounter31" bitsize="32"/> | ||
| 232 | - <reg name="mcycleh" bitsize="32"/> | ||
| 233 | - <reg name="minstreth" bitsize="32"/> | ||
| 234 | - <reg name="mhpmcounter3h" bitsize="32"/> | ||
| 235 | - <reg name="mhpmcounter4h" bitsize="32"/> | ||
| 236 | - <reg name="mhpmcounter5h" bitsize="32"/> | ||
| 237 | - <reg name="mhpmcounter6h" bitsize="32"/> | ||
| 238 | - <reg name="mhpmcounter7h" bitsize="32"/> | ||
| 239 | - <reg name="mhpmcounter8h" bitsize="32"/> | ||
| 240 | - <reg name="mhpmcounter9h" bitsize="32"/> | ||
| 241 | - <reg name="mhpmcounter10h" bitsize="32"/> | ||
| 242 | - <reg name="mhpmcounter11h" bitsize="32"/> | ||
| 243 | - <reg name="mhpmcounter12h" bitsize="32"/> | ||
| 244 | - <reg name="mhpmcounter13h" bitsize="32"/> | ||
| 245 | - <reg name="mhpmcounter14h" bitsize="32"/> | ||
| 246 | - <reg name="mhpmcounter15h" bitsize="32"/> | ||
| 247 | - <reg name="mhpmcounter16h" bitsize="32"/> | ||
| 248 | - <reg name="mhpmcounter17h" bitsize="32"/> | ||
| 249 | - <reg name="mhpmcounter18h" bitsize="32"/> | ||
| 250 | - <reg name="mhpmcounter19h" bitsize="32"/> | ||
| 251 | - <reg name="mhpmcounter20h" bitsize="32"/> | ||
| 252 | - <reg name="mhpmcounter21h" bitsize="32"/> | ||
| 253 | - <reg name="mhpmcounter22h" bitsize="32"/> | ||
| 254 | - <reg name="mhpmcounter23h" bitsize="32"/> | ||
| 255 | - <reg name="mhpmcounter24h" bitsize="32"/> | ||
| 256 | - <reg name="mhpmcounter25h" bitsize="32"/> | ||
| 257 | - <reg name="mhpmcounter26h" bitsize="32"/> | ||
| 258 | - <reg name="mhpmcounter27h" bitsize="32"/> | ||
| 259 | - <reg name="mhpmcounter28h" bitsize="32"/> | ||
| 260 | - <reg name="mhpmcounter29h" bitsize="32"/> | ||
| 261 | - <reg name="mhpmcounter30h" bitsize="32"/> | ||
| 262 | - <reg name="mhpmcounter31h" bitsize="32"/> | ||
| 263 | - <reg name="mhpmevent3" bitsize="32"/> | ||
| 264 | - <reg name="mhpmevent4" bitsize="32"/> | ||
| 265 | - <reg name="mhpmevent5" bitsize="32"/> | ||
| 266 | - <reg name="mhpmevent6" bitsize="32"/> | ||
| 267 | - <reg name="mhpmevent7" bitsize="32"/> | ||
| 268 | - <reg name="mhpmevent8" bitsize="32"/> | ||
| 269 | - <reg name="mhpmevent9" bitsize="32"/> | ||
| 270 | - <reg name="mhpmevent10" bitsize="32"/> | ||
| 271 | - <reg name="mhpmevent11" bitsize="32"/> | ||
| 272 | - <reg name="mhpmevent12" bitsize="32"/> | ||
| 273 | - <reg name="mhpmevent13" bitsize="32"/> | ||
| 274 | - <reg name="mhpmevent14" bitsize="32"/> | ||
| 275 | - <reg name="mhpmevent15" bitsize="32"/> | ||
| 276 | - <reg name="mhpmevent16" bitsize="32"/> | ||
| 277 | - <reg name="mhpmevent17" bitsize="32"/> | ||
| 278 | - <reg name="mhpmevent18" bitsize="32"/> | ||
| 279 | - <reg name="mhpmevent19" bitsize="32"/> | ||
| 280 | - <reg name="mhpmevent20" bitsize="32"/> | ||
| 281 | - <reg name="mhpmevent21" bitsize="32"/> | ||
| 282 | - <reg name="mhpmevent22" bitsize="32"/> | ||
| 283 | - <reg name="mhpmevent23" bitsize="32"/> | ||
| 284 | - <reg name="mhpmevent24" bitsize="32"/> | ||
| 285 | - <reg name="mhpmevent25" bitsize="32"/> | ||
| 286 | - <reg name="mhpmevent26" bitsize="32"/> | ||
| 287 | - <reg name="mhpmevent27" bitsize="32"/> | ||
| 288 | - <reg name="mhpmevent28" bitsize="32"/> | ||
| 289 | - <reg name="mhpmevent29" bitsize="32"/> | ||
| 290 | - <reg name="mhpmevent30" bitsize="32"/> | ||
| 291 | - <reg name="mhpmevent31" bitsize="32"/> | ||
| 292 | - <reg name="tselect" bitsize="32"/> | ||
| 293 | - <reg name="tdata1" bitsize="32"/> | ||
| 294 | - <reg name="tdata2" bitsize="32"/> | ||
| 295 | - <reg name="tdata3" bitsize="32"/> | ||
| 296 | - <reg name="dcsr" bitsize="32"/> | ||
| 297 | - <reg name="dpc" bitsize="32"/> | ||
| 298 | - <reg name="dscratch" bitsize="32"/> | ||
| 299 | - <reg name="hstatus" bitsize="32"/> | ||
| 300 | - <reg name="hedeleg" bitsize="32"/> | ||
| 301 | - <reg name="hideleg" bitsize="32"/> | ||
| 302 | - <reg name="hie" bitsize="32"/> | ||
| 303 | - <reg name="htvec" bitsize="32"/> | ||
| 304 | - <reg name="hscratch" bitsize="32"/> | ||
| 305 | - <reg name="hepc" bitsize="32"/> | ||
| 306 | - <reg name="hcause" bitsize="32"/> | ||
| 307 | - <reg name="hbadaddr" bitsize="32"/> | ||
| 308 | - <reg name="hip" bitsize="32"/> | ||
| 309 | - <reg name="mbase" bitsize="32"/> | ||
| 310 | - <reg name="mbound" bitsize="32"/> | ||
| 311 | - <reg name="mibase" bitsize="32"/> | ||
| 312 | - <reg name="mibound" bitsize="32"/> | ||
| 313 | - <reg name="mdbase" bitsize="32"/> | ||
| 314 | - <reg name="mdbound" bitsize="32"/> | ||
| 315 | - <reg name="mucounteren" bitsize="32"/> | ||
| 316 | - <reg name="mscounteren" bitsize="32"/> | ||
| 317 | - <reg name="mhcounteren" bitsize="32"/> | ||
| 318 | -</feature> | ||
| 319 | diff --git a/gdb-xml/riscv-64bit-csr.xml b/gdb-xml/riscv-64bit-csr.xml | ||
| 320 | deleted file mode 100644 | ||
| 321 | index XXXXXXX..XXXXXXX | ||
| 322 | --- a/gdb-xml/riscv-64bit-csr.xml | ||
| 323 | +++ /dev/null | ||
| 324 | @@ -XXX,XX +XXX,XX @@ | ||
| 325 | -<?xml version="1.0"?> | ||
| 326 | -<!-- Copyright (C) 2018-2019 Free Software Foundation, Inc. | ||
| 327 | - | ||
| 328 | - Copying and distribution of this file, with or without modification, | ||
| 329 | - are permitted in any medium without royalty provided the copyright | ||
| 330 | - notice and this notice are preserved. --> | ||
| 331 | - | ||
| 332 | -<!DOCTYPE feature SYSTEM "gdb-target.dtd"> | ||
| 333 | -<feature name="org.gnu.gdb.riscv.csr"> | ||
| 334 | - <reg name="ustatus" bitsize="64"/> | ||
| 335 | - <reg name="uie" bitsize="64"/> | ||
| 336 | - <reg name="utvec" bitsize="64"/> | ||
| 337 | - <reg name="uscratch" bitsize="64"/> | ||
| 338 | - <reg name="uepc" bitsize="64"/> | ||
| 339 | - <reg name="ucause" bitsize="64"/> | ||
| 340 | - <reg name="utval" bitsize="64"/> | ||
| 341 | - <reg name="uip" bitsize="64"/> | ||
| 342 | - <reg name="fflags" bitsize="64"/> | ||
| 343 | - <reg name="frm" bitsize="64"/> | ||
| 344 | - <reg name="fcsr" bitsize="64"/> | ||
| 345 | - <reg name="cycle" bitsize="64"/> | ||
| 346 | - <reg name="time" bitsize="64"/> | ||
| 347 | - <reg name="instret" bitsize="64"/> | ||
| 348 | - <reg name="hpmcounter3" bitsize="64"/> | ||
| 349 | - <reg name="hpmcounter4" bitsize="64"/> | ||
| 350 | - <reg name="hpmcounter5" bitsize="64"/> | ||
| 351 | - <reg name="hpmcounter6" bitsize="64"/> | ||
| 352 | - <reg name="hpmcounter7" bitsize="64"/> | ||
| 353 | - <reg name="hpmcounter8" bitsize="64"/> | ||
| 354 | - <reg name="hpmcounter9" bitsize="64"/> | ||
| 355 | - <reg name="hpmcounter10" bitsize="64"/> | ||
| 356 | - <reg name="hpmcounter11" bitsize="64"/> | ||
| 357 | - <reg name="hpmcounter12" bitsize="64"/> | ||
| 358 | - <reg name="hpmcounter13" bitsize="64"/> | ||
| 359 | - <reg name="hpmcounter14" bitsize="64"/> | ||
| 360 | - <reg name="hpmcounter15" bitsize="64"/> | ||
| 361 | - <reg name="hpmcounter16" bitsize="64"/> | ||
| 362 | - <reg name="hpmcounter17" bitsize="64"/> | ||
| 363 | - <reg name="hpmcounter18" bitsize="64"/> | ||
| 364 | - <reg name="hpmcounter19" bitsize="64"/> | ||
| 365 | - <reg name="hpmcounter20" bitsize="64"/> | ||
| 366 | - <reg name="hpmcounter21" bitsize="64"/> | ||
| 367 | - <reg name="hpmcounter22" bitsize="64"/> | ||
| 368 | - <reg name="hpmcounter23" bitsize="64"/> | ||
| 369 | - <reg name="hpmcounter24" bitsize="64"/> | ||
| 370 | - <reg name="hpmcounter25" bitsize="64"/> | ||
| 371 | - <reg name="hpmcounter26" bitsize="64"/> | ||
| 372 | - <reg name="hpmcounter27" bitsize="64"/> | ||
| 373 | - <reg name="hpmcounter28" bitsize="64"/> | ||
| 374 | - <reg name="hpmcounter29" bitsize="64"/> | ||
| 375 | - <reg name="hpmcounter30" bitsize="64"/> | ||
| 376 | - <reg name="hpmcounter31" bitsize="64"/> | ||
| 377 | - <reg name="cycleh" bitsize="64"/> | ||
| 378 | - <reg name="timeh" bitsize="64"/> | ||
| 379 | - <reg name="instreth" bitsize="64"/> | ||
| 380 | - <reg name="hpmcounter3h" bitsize="64"/> | ||
| 381 | - <reg name="hpmcounter4h" bitsize="64"/> | ||
| 382 | - <reg name="hpmcounter5h" bitsize="64"/> | ||
| 383 | - <reg name="hpmcounter6h" bitsize="64"/> | ||
| 384 | - <reg name="hpmcounter7h" bitsize="64"/> | ||
| 385 | - <reg name="hpmcounter8h" bitsize="64"/> | ||
| 386 | - <reg name="hpmcounter9h" bitsize="64"/> | ||
| 387 | - <reg name="hpmcounter10h" bitsize="64"/> | ||
| 388 | - <reg name="hpmcounter11h" bitsize="64"/> | ||
| 389 | - <reg name="hpmcounter12h" bitsize="64"/> | ||
| 390 | - <reg name="hpmcounter13h" bitsize="64"/> | ||
| 391 | - <reg name="hpmcounter14h" bitsize="64"/> | ||
| 392 | - <reg name="hpmcounter15h" bitsize="64"/> | ||
| 393 | - <reg name="hpmcounter16h" bitsize="64"/> | ||
| 394 | - <reg name="hpmcounter17h" bitsize="64"/> | ||
| 395 | - <reg name="hpmcounter18h" bitsize="64"/> | ||
| 396 | - <reg name="hpmcounter19h" bitsize="64"/> | ||
| 397 | - <reg name="hpmcounter20h" bitsize="64"/> | ||
| 398 | - <reg name="hpmcounter21h" bitsize="64"/> | ||
| 399 | - <reg name="hpmcounter22h" bitsize="64"/> | ||
| 400 | - <reg name="hpmcounter23h" bitsize="64"/> | ||
| 401 | - <reg name="hpmcounter24h" bitsize="64"/> | ||
| 402 | - <reg name="hpmcounter25h" bitsize="64"/> | ||
| 403 | - <reg name="hpmcounter26h" bitsize="64"/> | ||
| 404 | - <reg name="hpmcounter27h" bitsize="64"/> | ||
| 405 | - <reg name="hpmcounter28h" bitsize="64"/> | ||
| 406 | - <reg name="hpmcounter29h" bitsize="64"/> | ||
| 407 | - <reg name="hpmcounter30h" bitsize="64"/> | ||
| 408 | - <reg name="hpmcounter31h" bitsize="64"/> | ||
| 409 | - <reg name="sstatus" bitsize="64"/> | ||
| 410 | - <reg name="sedeleg" bitsize="64"/> | ||
| 411 | - <reg name="sideleg" bitsize="64"/> | ||
| 412 | - <reg name="sie" bitsize="64"/> | ||
| 413 | - <reg name="stvec" bitsize="64"/> | ||
| 414 | - <reg name="scounteren" bitsize="64"/> | ||
| 415 | - <reg name="sscratch" bitsize="64"/> | ||
| 416 | - <reg name="sepc" bitsize="64"/> | ||
| 417 | - <reg name="scause" bitsize="64"/> | ||
| 418 | - <reg name="stval" bitsize="64"/> | ||
| 419 | - <reg name="sip" bitsize="64"/> | ||
| 420 | - <reg name="satp" bitsize="64"/> | ||
| 421 | - <reg name="mvendorid" bitsize="64"/> | ||
| 422 | - <reg name="marchid" bitsize="64"/> | ||
| 423 | - <reg name="mimpid" bitsize="64"/> | ||
| 424 | - <reg name="mhartid" bitsize="64"/> | ||
| 425 | - <reg name="mstatus" bitsize="64"/> | ||
| 426 | - <reg name="misa" bitsize="64"/> | ||
| 427 | - <reg name="medeleg" bitsize="64"/> | ||
| 428 | - <reg name="mideleg" bitsize="64"/> | ||
| 429 | - <reg name="mie" bitsize="64"/> | ||
| 430 | - <reg name="mtvec" bitsize="64"/> | ||
| 431 | - <reg name="mcounteren" bitsize="64"/> | ||
| 432 | - <reg name="mscratch" bitsize="64"/> | ||
| 433 | - <reg name="mepc" bitsize="64"/> | ||
| 434 | - <reg name="mcause" bitsize="64"/> | ||
| 435 | - <reg name="mtval" bitsize="64"/> | ||
| 436 | - <reg name="mip" bitsize="64"/> | ||
| 437 | - <reg name="pmpcfg0" bitsize="64"/> | ||
| 438 | - <reg name="pmpcfg1" bitsize="64"/> | ||
| 439 | - <reg name="pmpcfg2" bitsize="64"/> | ||
| 440 | - <reg name="pmpcfg3" bitsize="64"/> | ||
| 441 | - <reg name="pmpaddr0" bitsize="64"/> | ||
| 442 | - <reg name="pmpaddr1" bitsize="64"/> | ||
| 443 | - <reg name="pmpaddr2" bitsize="64"/> | ||
| 444 | - <reg name="pmpaddr3" bitsize="64"/> | ||
| 445 | - <reg name="pmpaddr4" bitsize="64"/> | ||
| 446 | - <reg name="pmpaddr5" bitsize="64"/> | ||
| 447 | - <reg name="pmpaddr6" bitsize="64"/> | ||
| 448 | - <reg name="pmpaddr7" bitsize="64"/> | ||
| 449 | - <reg name="pmpaddr8" bitsize="64"/> | ||
| 450 | - <reg name="pmpaddr9" bitsize="64"/> | ||
| 451 | - <reg name="pmpaddr10" bitsize="64"/> | ||
| 452 | - <reg name="pmpaddr11" bitsize="64"/> | ||
| 453 | - <reg name="pmpaddr12" bitsize="64"/> | ||
| 454 | - <reg name="pmpaddr13" bitsize="64"/> | ||
| 455 | - <reg name="pmpaddr14" bitsize="64"/> | ||
| 456 | - <reg name="pmpaddr15" bitsize="64"/> | ||
| 457 | - <reg name="mcycle" bitsize="64"/> | ||
| 458 | - <reg name="minstret" bitsize="64"/> | ||
| 459 | - <reg name="mhpmcounter3" bitsize="64"/> | ||
| 460 | - <reg name="mhpmcounter4" bitsize="64"/> | ||
| 461 | - <reg name="mhpmcounter5" bitsize="64"/> | ||
| 462 | - <reg name="mhpmcounter6" bitsize="64"/> | ||
| 463 | - <reg name="mhpmcounter7" bitsize="64"/> | ||
| 464 | - <reg name="mhpmcounter8" bitsize="64"/> | ||
| 465 | - <reg name="mhpmcounter9" bitsize="64"/> | ||
| 466 | - <reg name="mhpmcounter10" bitsize="64"/> | ||
| 467 | - <reg name="mhpmcounter11" bitsize="64"/> | ||
| 468 | - <reg name="mhpmcounter12" bitsize="64"/> | ||
| 469 | - <reg name="mhpmcounter13" bitsize="64"/> | ||
| 470 | - <reg name="mhpmcounter14" bitsize="64"/> | ||
| 471 | - <reg name="mhpmcounter15" bitsize="64"/> | ||
| 472 | - <reg name="mhpmcounter16" bitsize="64"/> | ||
| 473 | - <reg name="mhpmcounter17" bitsize="64"/> | ||
| 474 | - <reg name="mhpmcounter18" bitsize="64"/> | ||
| 475 | - <reg name="mhpmcounter19" bitsize="64"/> | ||
| 476 | - <reg name="mhpmcounter20" bitsize="64"/> | ||
| 477 | - <reg name="mhpmcounter21" bitsize="64"/> | ||
| 478 | - <reg name="mhpmcounter22" bitsize="64"/> | ||
| 479 | - <reg name="mhpmcounter23" bitsize="64"/> | ||
| 480 | - <reg name="mhpmcounter24" bitsize="64"/> | ||
| 481 | - <reg name="mhpmcounter25" bitsize="64"/> | ||
| 482 | - <reg name="mhpmcounter26" bitsize="64"/> | ||
| 483 | - <reg name="mhpmcounter27" bitsize="64"/> | ||
| 484 | - <reg name="mhpmcounter28" bitsize="64"/> | ||
| 485 | - <reg name="mhpmcounter29" bitsize="64"/> | ||
| 486 | - <reg name="mhpmcounter30" bitsize="64"/> | ||
| 487 | - <reg name="mhpmcounter31" bitsize="64"/> | ||
| 488 | - <reg name="mcycleh" bitsize="64"/> | ||
| 489 | - <reg name="minstreth" bitsize="64"/> | ||
| 490 | - <reg name="mhpmcounter3h" bitsize="64"/> | ||
| 491 | - <reg name="mhpmcounter4h" bitsize="64"/> | ||
| 492 | - <reg name="mhpmcounter5h" bitsize="64"/> | ||
| 493 | - <reg name="mhpmcounter6h" bitsize="64"/> | ||
| 494 | - <reg name="mhpmcounter7h" bitsize="64"/> | ||
| 495 | - <reg name="mhpmcounter8h" bitsize="64"/> | ||
| 496 | - <reg name="mhpmcounter9h" bitsize="64"/> | ||
| 497 | - <reg name="mhpmcounter10h" bitsize="64"/> | ||
| 498 | - <reg name="mhpmcounter11h" bitsize="64"/> | ||
| 499 | - <reg name="mhpmcounter12h" bitsize="64"/> | ||
| 500 | - <reg name="mhpmcounter13h" bitsize="64"/> | ||
| 501 | - <reg name="mhpmcounter14h" bitsize="64"/> | ||
| 502 | - <reg name="mhpmcounter15h" bitsize="64"/> | ||
| 503 | - <reg name="mhpmcounter16h" bitsize="64"/> | ||
| 504 | - <reg name="mhpmcounter17h" bitsize="64"/> | ||
| 505 | - <reg name="mhpmcounter18h" bitsize="64"/> | ||
| 506 | - <reg name="mhpmcounter19h" bitsize="64"/> | ||
| 507 | - <reg name="mhpmcounter20h" bitsize="64"/> | ||
| 508 | - <reg name="mhpmcounter21h" bitsize="64"/> | ||
| 509 | - <reg name="mhpmcounter22h" bitsize="64"/> | ||
| 510 | - <reg name="mhpmcounter23h" bitsize="64"/> | ||
| 511 | - <reg name="mhpmcounter24h" bitsize="64"/> | ||
| 512 | - <reg name="mhpmcounter25h" bitsize="64"/> | ||
| 513 | - <reg name="mhpmcounter26h" bitsize="64"/> | ||
| 514 | - <reg name="mhpmcounter27h" bitsize="64"/> | ||
| 515 | - <reg name="mhpmcounter28h" bitsize="64"/> | ||
| 516 | - <reg name="mhpmcounter29h" bitsize="64"/> | ||
| 517 | - <reg name="mhpmcounter30h" bitsize="64"/> | ||
| 518 | - <reg name="mhpmcounter31h" bitsize="64"/> | ||
| 519 | - <reg name="mhpmevent3" bitsize="64"/> | ||
| 520 | - <reg name="mhpmevent4" bitsize="64"/> | ||
| 521 | - <reg name="mhpmevent5" bitsize="64"/> | ||
| 522 | - <reg name="mhpmevent6" bitsize="64"/> | ||
| 523 | - <reg name="mhpmevent7" bitsize="64"/> | ||
| 524 | - <reg name="mhpmevent8" bitsize="64"/> | ||
| 525 | - <reg name="mhpmevent9" bitsize="64"/> | ||
| 526 | - <reg name="mhpmevent10" bitsize="64"/> | ||
| 527 | - <reg name="mhpmevent11" bitsize="64"/> | ||
| 528 | - <reg name="mhpmevent12" bitsize="64"/> | ||
| 529 | - <reg name="mhpmevent13" bitsize="64"/> | ||
| 530 | - <reg name="mhpmevent14" bitsize="64"/> | ||
| 531 | - <reg name="mhpmevent15" bitsize="64"/> | ||
| 532 | - <reg name="mhpmevent16" bitsize="64"/> | ||
| 533 | - <reg name="mhpmevent17" bitsize="64"/> | ||
| 534 | - <reg name="mhpmevent18" bitsize="64"/> | ||
| 535 | - <reg name="mhpmevent19" bitsize="64"/> | ||
| 536 | - <reg name="mhpmevent20" bitsize="64"/> | ||
| 537 | - <reg name="mhpmevent21" bitsize="64"/> | ||
| 538 | - <reg name="mhpmevent22" bitsize="64"/> | ||
| 539 | - <reg name="mhpmevent23" bitsize="64"/> | ||
| 540 | - <reg name="mhpmevent24" bitsize="64"/> | ||
| 541 | - <reg name="mhpmevent25" bitsize="64"/> | ||
| 542 | - <reg name="mhpmevent26" bitsize="64"/> | ||
| 543 | - <reg name="mhpmevent27" bitsize="64"/> | ||
| 544 | - <reg name="mhpmevent28" bitsize="64"/> | ||
| 545 | - <reg name="mhpmevent29" bitsize="64"/> | ||
| 546 | - <reg name="mhpmevent30" bitsize="64"/> | ||
| 547 | - <reg name="mhpmevent31" bitsize="64"/> | ||
| 548 | - <reg name="tselect" bitsize="64"/> | ||
| 549 | - <reg name="tdata1" bitsize="64"/> | ||
| 550 | - <reg name="tdata2" bitsize="64"/> | ||
| 551 | - <reg name="tdata3" bitsize="64"/> | ||
| 552 | - <reg name="dcsr" bitsize="64"/> | ||
| 553 | - <reg name="dpc" bitsize="64"/> | ||
| 554 | - <reg name="dscratch" bitsize="64"/> | ||
| 555 | - <reg name="hstatus" bitsize="64"/> | ||
| 556 | - <reg name="hedeleg" bitsize="64"/> | ||
| 557 | - <reg name="hideleg" bitsize="64"/> | ||
| 558 | - <reg name="hie" bitsize="64"/> | ||
| 559 | - <reg name="htvec" bitsize="64"/> | ||
| 560 | - <reg name="hscratch" bitsize="64"/> | ||
| 561 | - <reg name="hepc" bitsize="64"/> | ||
| 562 | - <reg name="hcause" bitsize="64"/> | ||
| 563 | - <reg name="hbadaddr" bitsize="64"/> | ||
| 564 | - <reg name="hip" bitsize="64"/> | ||
| 565 | - <reg name="mbase" bitsize="64"/> | ||
| 566 | - <reg name="mbound" bitsize="64"/> | ||
| 567 | - <reg name="mibase" bitsize="64"/> | ||
| 568 | - <reg name="mibound" bitsize="64"/> | ||
| 569 | - <reg name="mdbase" bitsize="64"/> | ||
| 570 | - <reg name="mdbound" bitsize="64"/> | ||
| 571 | - <reg name="mucounteren" bitsize="64"/> | ||
| 572 | - <reg name="mscounteren" bitsize="64"/> | ||
| 573 | - <reg name="mhcounteren" bitsize="64"/> | ||
| 574 | -</feature> | ||
| 575 | -- | ||
| 576 | 2.29.2 | ||
| 577 | |||
| 578 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | We were accidently passing RISCVHartArrayState by value instead of | ||
| 2 | pointer. The type is 824 bytes long so let's correct that and pass it by | ||
| 3 | pointer instead. | ||
| 4 | 1 | ||
| 5 | Fixes: Coverity CID 1438099 | ||
| 6 | Fixes: Coverity CID 1438100 | ||
| 7 | Fixes: Coverity CID 1438101 | ||
| 8 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 9 | Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> | ||
| 10 | Reviewed-by: Bin Meng <bin.meng@windriver.com> | ||
| 11 | Message-id: f3e04424723e0e222769991896cc82308fd23f76.1610751609.git.alistair.francis@wdc.com | ||
| 12 | --- | ||
| 13 | include/hw/riscv/boot.h | 6 +++--- | ||
| 14 | hw/riscv/boot.c | 10 ++++------ | ||
| 15 | hw/riscv/sifive_u.c | 10 +++++----- | ||
| 16 | hw/riscv/spike.c | 8 ++++---- | ||
| 17 | hw/riscv/virt.c | 8 ++++---- | ||
| 18 | 5 files changed, 20 insertions(+), 22 deletions(-) | ||
| 19 | |||
| 20 | diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h | ||
| 21 | index XXXXXXX..XXXXXXX 100644 | ||
| 22 | --- a/include/hw/riscv/boot.h | ||
| 23 | +++ b/include/hw/riscv/boot.h | ||
| 24 | @@ -XXX,XX +XXX,XX @@ | ||
| 25 | #include "hw/loader.h" | ||
| 26 | #include "hw/riscv/riscv_hart.h" | ||
| 27 | |||
| 28 | -bool riscv_is_32bit(RISCVHartArrayState harts); | ||
| 29 | +bool riscv_is_32bit(RISCVHartArrayState *harts); | ||
| 30 | |||
| 31 | -target_ulong riscv_calc_kernel_start_addr(RISCVHartArrayState harts, | ||
| 32 | +target_ulong riscv_calc_kernel_start_addr(RISCVHartArrayState *harts, | ||
| 33 | target_ulong firmware_end_addr); | ||
| 34 | target_ulong riscv_find_and_load_firmware(MachineState *machine, | ||
| 35 | const char *default_machine_firmware, | ||
| 36 | @@ -XXX,XX +XXX,XX @@ target_ulong riscv_load_kernel(const char *kernel_filename, | ||
| 37 | hwaddr riscv_load_initrd(const char *filename, uint64_t mem_size, | ||
| 38 | uint64_t kernel_entry, hwaddr *start); | ||
| 39 | uint32_t riscv_load_fdt(hwaddr dram_start, uint64_t dram_size, void *fdt); | ||
| 40 | -void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState harts, | ||
| 41 | +void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState *harts, | ||
| 42 | hwaddr saddr, | ||
| 43 | hwaddr rom_base, hwaddr rom_size, | ||
| 44 | uint64_t kernel_entry, | ||
| 45 | diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c | ||
| 46 | index XXXXXXX..XXXXXXX 100644 | ||
| 47 | --- a/hw/riscv/boot.c | ||
| 48 | +++ b/hw/riscv/boot.c | ||
| 49 | @@ -XXX,XX +XXX,XX @@ | ||
| 50 | |||
| 51 | #include <libfdt.h> | ||
| 52 | |||
| 53 | -bool riscv_is_32bit(RISCVHartArrayState harts) | ||
| 54 | +bool riscv_is_32bit(RISCVHartArrayState *harts) | ||
| 55 | { | ||
| 56 | - RISCVCPU hart = harts.harts[0]; | ||
| 57 | - | ||
| 58 | - return riscv_cpu_is_32bit(&hart.env); | ||
| 59 | + return riscv_cpu_is_32bit(&harts->harts[0].env); | ||
| 60 | } | ||
| 61 | |||
| 62 | -target_ulong riscv_calc_kernel_start_addr(RISCVHartArrayState harts, | ||
| 63 | +target_ulong riscv_calc_kernel_start_addr(RISCVHartArrayState *harts, | ||
| 64 | target_ulong firmware_end_addr) { | ||
| 65 | if (riscv_is_32bit(harts)) { | ||
| 66 | return QEMU_ALIGN_UP(firmware_end_addr, 4 * MiB); | ||
| 67 | @@ -XXX,XX +XXX,XX @@ void riscv_rom_copy_firmware_info(MachineState *machine, hwaddr rom_base, | ||
| 68 | &address_space_memory); | ||
| 69 | } | ||
| 70 | |||
| 71 | -void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState harts, | ||
| 72 | +void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState *harts, | ||
| 73 | hwaddr start_addr, | ||
| 74 | hwaddr rom_base, hwaddr rom_size, | ||
| 75 | uint64_t kernel_entry, | ||
| 76 | diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c | ||
| 77 | index XXXXXXX..XXXXXXX 100644 | ||
| 78 | --- a/hw/riscv/sifive_u.c | ||
| 79 | +++ b/hw/riscv/sifive_u.c | ||
| 80 | @@ -XXX,XX +XXX,XX @@ static void sifive_u_machine_init(MachineState *machine) | ||
| 81 | |||
| 82 | /* create device tree */ | ||
| 83 | create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline, | ||
| 84 | - riscv_is_32bit(s->soc.u_cpus)); | ||
| 85 | + riscv_is_32bit(&s->soc.u_cpus)); | ||
| 86 | |||
| 87 | if (s->start_in_flash) { | ||
| 88 | /* | ||
| 89 | @@ -XXX,XX +XXX,XX @@ static void sifive_u_machine_init(MachineState *machine) | ||
| 90 | break; | ||
| 91 | } | ||
| 92 | |||
| 93 | - if (riscv_is_32bit(s->soc.u_cpus)) { | ||
| 94 | + if (riscv_is_32bit(&s->soc.u_cpus)) { | ||
| 95 | firmware_end_addr = riscv_find_and_load_firmware(machine, | ||
| 96 | "opensbi-riscv32-generic-fw_dynamic.bin", | ||
| 97 | start_addr, NULL); | ||
| 98 | @@ -XXX,XX +XXX,XX @@ static void sifive_u_machine_init(MachineState *machine) | ||
| 99 | } | ||
| 100 | |||
| 101 | if (machine->kernel_filename) { | ||
| 102 | - kernel_start_addr = riscv_calc_kernel_start_addr(s->soc.u_cpus, | ||
| 103 | + kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc.u_cpus, | ||
| 104 | firmware_end_addr); | ||
| 105 | |||
| 106 | kernel_entry = riscv_load_kernel(machine->kernel_filename, | ||
| 107 | @@ -XXX,XX +XXX,XX @@ static void sifive_u_machine_init(MachineState *machine) | ||
| 108 | /* Compute the fdt load address in dram */ | ||
| 109 | fdt_load_addr = riscv_load_fdt(memmap[SIFIVE_U_DEV_DRAM].base, | ||
| 110 | machine->ram_size, s->fdt); | ||
| 111 | - if (!riscv_is_32bit(s->soc.u_cpus)) { | ||
| 112 | + if (!riscv_is_32bit(&s->soc.u_cpus)) { | ||
| 113 | start_addr_hi32 = (uint64_t)start_addr >> 32; | ||
| 114 | } | ||
| 115 | |||
| 116 | @@ -XXX,XX +XXX,XX @@ static void sifive_u_machine_init(MachineState *machine) | ||
| 117 | 0x00000000, | ||
| 118 | /* fw_dyn: */ | ||
| 119 | }; | ||
| 120 | - if (riscv_is_32bit(s->soc.u_cpus)) { | ||
| 121 | + if (riscv_is_32bit(&s->soc.u_cpus)) { | ||
| 122 | reset_vec[4] = 0x0202a583; /* lw a1, 32(t0) */ | ||
| 123 | reset_vec[5] = 0x0182a283; /* lw t0, 24(t0) */ | ||
| 124 | } else { | ||
| 125 | diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c | ||
| 126 | index XXXXXXX..XXXXXXX 100644 | ||
| 127 | --- a/hw/riscv/spike.c | ||
| 128 | +++ b/hw/riscv/spike.c | ||
| 129 | @@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine) | ||
| 130 | |||
| 131 | /* create device tree */ | ||
| 132 | create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline, | ||
| 133 | - riscv_is_32bit(s->soc[0])); | ||
| 134 | + riscv_is_32bit(&s->soc[0])); | ||
| 135 | |||
| 136 | /* boot rom */ | ||
| 137 | memory_region_init_rom(mask_rom, NULL, "riscv.spike.mrom", | ||
| 138 | @@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine) | ||
| 139 | * keeping ELF files here was intentional because BIN files don't work | ||
| 140 | * for the Spike machine as HTIF emulation depends on ELF parsing. | ||
| 141 | */ | ||
| 142 | - if (riscv_is_32bit(s->soc[0])) { | ||
| 143 | + if (riscv_is_32bit(&s->soc[0])) { | ||
| 144 | firmware_end_addr = riscv_find_and_load_firmware(machine, | ||
| 145 | "opensbi-riscv32-generic-fw_dynamic.elf", | ||
| 146 | memmap[SPIKE_DRAM].base, | ||
| 147 | @@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine) | ||
| 148 | } | ||
| 149 | |||
| 150 | if (machine->kernel_filename) { | ||
| 151 | - kernel_start_addr = riscv_calc_kernel_start_addr(s->soc[0], | ||
| 152 | + kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc[0], | ||
| 153 | firmware_end_addr); | ||
| 154 | |||
| 155 | kernel_entry = riscv_load_kernel(machine->kernel_filename, | ||
| 156 | @@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine) | ||
| 157 | fdt_load_addr = riscv_load_fdt(memmap[SPIKE_DRAM].base, | ||
| 158 | machine->ram_size, s->fdt); | ||
| 159 | /* load the reset vector */ | ||
| 160 | - riscv_setup_rom_reset_vec(machine, s->soc[0], memmap[SPIKE_DRAM].base, | ||
| 161 | + riscv_setup_rom_reset_vec(machine, &s->soc[0], memmap[SPIKE_DRAM].base, | ||
| 162 | memmap[SPIKE_MROM].base, | ||
| 163 | memmap[SPIKE_MROM].size, kernel_entry, | ||
| 164 | fdt_load_addr, s->fdt); | ||
| 165 | diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c | ||
| 166 | index XXXXXXX..XXXXXXX 100644 | ||
| 167 | --- a/hw/riscv/virt.c | ||
| 168 | +++ b/hw/riscv/virt.c | ||
| 169 | @@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine) | ||
| 170 | |||
| 171 | /* create device tree */ | ||
| 172 | create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline, | ||
| 173 | - riscv_is_32bit(s->soc[0])); | ||
| 174 | + riscv_is_32bit(&s->soc[0])); | ||
| 175 | |||
| 176 | /* boot rom */ | ||
| 177 | memory_region_init_rom(mask_rom, NULL, "riscv_virt_board.mrom", | ||
| 178 | @@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine) | ||
| 179 | memory_region_add_subregion(system_memory, memmap[VIRT_MROM].base, | ||
| 180 | mask_rom); | ||
| 181 | |||
| 182 | - if (riscv_is_32bit(s->soc[0])) { | ||
| 183 | + if (riscv_is_32bit(&s->soc[0])) { | ||
| 184 | firmware_end_addr = riscv_find_and_load_firmware(machine, | ||
| 185 | "opensbi-riscv32-generic-fw_dynamic.bin", | ||
| 186 | start_addr, NULL); | ||
| 187 | @@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine) | ||
| 188 | } | ||
| 189 | |||
| 190 | if (machine->kernel_filename) { | ||
| 191 | - kernel_start_addr = riscv_calc_kernel_start_addr(s->soc[0], | ||
| 192 | + kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc[0], | ||
| 193 | firmware_end_addr); | ||
| 194 | |||
| 195 | kernel_entry = riscv_load_kernel(machine->kernel_filename, | ||
| 196 | @@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine) | ||
| 197 | fdt_load_addr = riscv_load_fdt(memmap[VIRT_DRAM].base, | ||
| 198 | machine->ram_size, s->fdt); | ||
| 199 | /* load the reset vector */ | ||
| 200 | - riscv_setup_rom_reset_vec(machine, s->soc[0], start_addr, | ||
| 201 | + riscv_setup_rom_reset_vec(machine, &s->soc[0], start_addr, | ||
| 202 | virt_memmap[VIRT_MROM].base, | ||
| 203 | virt_memmap[VIRT_MROM].size, kernel_entry, | ||
| 204 | fdt_load_addr, s->fdt); | ||
| 205 | -- | ||
| 206 | 2.29.2 | ||
| 207 | |||
| 208 | diff view generated by jsdifflib |