[PULL 00/12] riscv-to-apply queue
[PULL 00/16] riscv-to-apply queue
1
The following changes since commit 825a215c003cd028e26c7d19aa5049d957345f43:
1
The following changes since commit c95bd5ff1660883d15ad6e0005e4c8571604f51a:
2
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3
Merge remote-tracking branch 'remotes/kraxel/tags/audio-20210115-pull-request' into staging (2021-01-15 22:21:21 +0000)
3
Merge remote-tracking branch 'remotes/philmd/tags/mips-fixes-20210322' into staging (2021-03-22 14:26:13 +0000)
4
4
5
are available in the Git repository at:
5
are available in the Git repository at:
6
6
7
git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20210117-3
7
git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20210322-2
8
8
9
for you to fetch changes up to a8259b53230782f5e0a0d66013655c4ed5d71b7e:
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for you to fetch changes up to 9a27f69bd668d9d71674407badc412ce1231c7d5:
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11
riscv: Pass RISCVHartArrayState by pointer (2021-01-16 14:34:46 -0800)
11
target/riscv: Prevent lost illegal instruction exceptions (2021-03-22 21:54:40 -0400)
12
12
13
----------------------------------------------------------------
13
----------------------------------------------------------------
14
First RISC-V PR for 6.0
14
RISC-V PR for 6.0
15
15
16
This PR:
16
This PR includes:
17
- Fixes some issues with the m25p80
17
- Fix for vector CSR access
18
- Improves GDB support for RISC-V
18
- Improvements to the Ibex UART device
19
- Fixes some Linux boot issues, specifiaclly 32-bit boot failures
19
- PMP improvements and bug fixes
20
- Enforces PMP exceptions correctly
20
- Hypervisor extension bug fixes
21
- Fixes some Coverity issues
21
- ramfb support for the virt machine
22
- Fast read support for SST flash
23
- Improvements to the microchip_pfsoc machine
22
24
23
----------------------------------------------------------------
25
----------------------------------------------------------------
24
Alistair Francis (1):
26
Alexander Wagner (1):
25
riscv: Pass RISCVHartArrayState by pointer
27
hw/char: disable ibex uart receive if the buffer is full
26
28
27
Atish Patra (2):
29
Asherah Connor (2):
28
RISC-V: Place DTB at 3GB boundary instead of 4GB
30
hw/riscv: Add fw_cfg support to virt
29
target/riscv/pmp: Raise exception if no PMP entry is configured
31
hw/riscv: allow ramfb on virt
30
32
31
Bin Meng (6):
33
Bin Meng (3):
32
hw/block: m25p80: Don't write to flash if write is disabled
34
hw/block: m25p80: Support fast read for SST flashes
33
hw/riscv: sifive_u: Use SIFIVE_U_CPU for mc->default_cpu_type
35
hw/riscv: microchip_pfsoc: Map EMMC/SD mux register
34
target/riscv: Make csr_ops[CSR_TABLE_SIZE] external
36
docs/system: riscv: Add documentation for 'microchip-icicle-kit' machine
35
target/riscv: Add CSR name in the CSR function table
36
target/riscv: Generate the GDB XML file for CSR registers dynamically
37
target/riscv: Remove built-in GDB XML files for CSRs
38
37
39
Green Wan (1):
38
Frank Chang (1):
40
hw/misc/sifive_u_otp: handling the fails of blk_pread and blk_pwrite
39
target/riscv: fix vs() to return proper error code
41
40
42
Sylvain Pelissier (1):
41
Georg Kotheimer (6):
43
gdb: riscv: Add target description
42
target/riscv: Adjust privilege level for HLV(X)/HSV instructions
43
target/riscv: Make VSTIP and VSEIP read-only in hip
44
target/riscv: Use background registers also for MSTATUS_MPV
45
target/riscv: Fix read and write accesses to vsip and vsie
46
target/riscv: Add proper two-stage lookup exception detection
47
target/riscv: Prevent lost illegal instruction exceptions
44
48
45
Xuzhou Cheng (1):
49
Jim Shu (3):
46
hw/block: m25p80: Implement AAI-WP command support for SST flashes
50
target/riscv: propagate PMP permission to TLB page
51
target/riscv: add log of PMP permission checking
52
target/riscv: flush TLB pages if PMP permission has been changed
47
53
48
default-configs/targets/riscv32-linux-user.mak | 2 +-
54
docs/system/riscv/microchip-icicle-kit.rst | 89 ++++++++++++++
49
default-configs/targets/riscv32-softmmu.mak | 2 +-
55
docs/system/target-riscv.rst | 1 +
50
default-configs/targets/riscv64-linux-user.mak | 2 +-
56
include/hw/char/ibex_uart.h | 4 +
51
default-configs/targets/riscv64-softmmu.mak | 2 +-
57
include/hw/riscv/microchip_pfsoc.h | 1 +
52
include/hw/riscv/boot.h | 6 +-
58
include/hw/riscv/virt.h | 2 +
53
target/riscv/cpu.h | 11 +
59
target/riscv/cpu.h | 4 +
54
target/riscv/pmp.h | 1 +
60
target/riscv/pmp.h | 4 +-
55
hw/block/m25p80.c | 74 ++++++
61
hw/block/m25p80.c | 3 +
56
hw/misc/sifive_u_otp.c | 31 ++-
62
hw/char/ibex_uart.c | 23 +++-
57
hw/riscv/boot.c | 18 +-
63
hw/riscv/microchip_pfsoc.c | 6 +
58
hw/riscv/sifive_u.c | 16 +-
64
hw/riscv/virt.c | 33 ++++++
59
hw/riscv/spike.c | 8 +-
65
target/riscv/cpu.c | 1 +
60
hw/riscv/virt.c | 8 +-
66
target/riscv/cpu_helper.c | 144 +++++++++++++++--------
61
target/riscv/cpu.c | 25 ++
67
target/riscv/csr.c | 77 +++++++------
62
target/riscv/csr.c | 342 ++++++++++++++++++-------
68
target/riscv/pmp.c | 84 ++++++++++----
63
target/riscv/gdbstub.c | 308 ++++------------------
69
target/riscv/translate.c | 179 +----------------------------
64
target/riscv/op_helper.c | 5 +
70
hw/riscv/Kconfig | 1 +
65
target/riscv/pmp.c | 4 +-
71
17 files changed, 367 insertions(+), 289 deletions(-)
66
gdb-xml/riscv-32bit-csr.xml | 250 ------------------
72
create mode 100644 docs/system/riscv/microchip-icicle-kit.rst
67
gdb-xml/riscv-64bit-csr.xml | 250 ------------------
68
20 files changed, 463 insertions(+), 902 deletions(-)
69
delete mode 100644 gdb-xml/riscv-32bit-csr.xml
70
delete mode 100644 gdb-xml/riscv-64bit-csr.xml
71
73
diff view generated by jsdifflib
[PULL 08/12] target/riscv: Make csr_ops[CSR_TABLE_SIZE] external
[PULL 01/16] target/riscv: fix vs() to return proper error code
1
From: Bin Meng <bin.meng@windriver.com>
1
From: Frank Chang <frank.chang@sifive.com>
2
2
3
In preparation to generate the CSR register list for GDB stub
3
vs() should return -RISCV_EXCP_ILLEGAL_INST instead of -1 if rvv feature
4
dynamically, change csr_ops[] to non-static so that it can be
4
is not enabled.
5
referenced externally.
6
5
7
Signed-off-by: Bin Meng <bin.meng@windriver.com>
6
If -1 is returned, exception will be raised and cs->exception_index will
7
be set to the negative return value. The exception will then be treated
8
as an instruction access fault instead of illegal instruction fault.
9
10
Signed-off-by: Frank Chang <frank.chang@sifive.com>
11
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
12
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
9
Message-id: 1610427124-49887-2-git-send-email-bmeng.cn@gmail.com
13
Message-id: 20210223065935.20208-1-frank.chang@sifive.com
10
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
14
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
11
---
15
---
12
target/riscv/cpu.h | 8 ++++++++
16
target/riscv/csr.c | 2 +-
13
target/riscv/csr.c | 10 +---------
17
1 file changed, 1 insertion(+), 1 deletion(-)
14
2 files changed, 9 insertions(+), 9 deletions(-)
15
18
16
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/riscv/cpu.h
19
+++ b/target/riscv/cpu.h
20
@@ -XXX,XX +XXX,XX @@ typedef struct {
21
riscv_csr_op_fn op;
22
} riscv_csr_operations;
23
24
+/* CSR function table constants */
25
+enum {
26
+ CSR_TABLE_SIZE = 0x1000
27
+};
28
+
29
+/* CSR function table */
30
+extern riscv_csr_operations csr_ops[];
31
+
32
void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops);
33
void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops);
34
35
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
19
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
36
index XXXXXXX..XXXXXXX 100644
20
index XXXXXXX..XXXXXXX 100644
37
--- a/target/riscv/csr.c
21
--- a/target/riscv/csr.c
38
+++ b/target/riscv/csr.c
22
+++ b/target/riscv/csr.c
39
@@ -XXX,XX +XXX,XX @@
23
@@ -XXX,XX +XXX,XX @@ static int vs(CPURISCVState *env, int csrno)
40
#include "qemu/main-loop.h"
24
if (env->misa & RVV) {
41
#include "exec/exec-all.h"
25
return 0;
42
26
}
43
-/* CSR function table */
27
- return -1;
44
-static riscv_csr_operations csr_ops[];
28
+ return -RISCV_EXCP_ILLEGAL_INST;
45
-
46
-/* CSR function table constants */
47
-enum {
48
- CSR_TABLE_SIZE = 0x1000
49
-};
50
-
51
/* CSR function table public API */
52
void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops)
53
{
54
@@ -XXX,XX +XXX,XX @@ int riscv_csrrw_debug(CPURISCVState *env, int csrno, target_ulong *ret_value,
55
}
29
}
56
30
57
/* Control and Status Register function table */
31
static int ctr(CPURISCVState *env, int csrno)
58
-static riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
59
+riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
60
/* User Floating-Point CSRs */
61
[CSR_FFLAGS] = { fs, read_fflags, write_fflags },
62
[CSR_FRM] = { fs, read_frm, write_frm },
63
--
32
--
64
2.29.2
33
2.30.1
65
34
66
35
diff view generated by jsdifflib
New patch
[PULL 02/16] hw/char: disable ibex uart receive if the buffer is full
1
From: Alexander Wagner <alexander.wagner@ulal.de>
1
2
3
Not disabling the UART leads to QEMU overwriting the UART receive buffer with
4
the newest received byte. The rx_level variable is added to allow the use of
5
the existing OpenTitan driver libraries.
6
7
Signed-off-by: Alexander Wagner <alexander.wagner@ulal.de>
8
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
9
Message-id: 20210309152130.13038-1-alexander.wagner@ulal.de
10
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
11
---
12
include/hw/char/ibex_uart.h | 4 ++++
13
hw/char/ibex_uart.c | 23 ++++++++++++++++++-----
14
2 files changed, 22 insertions(+), 5 deletions(-)
15
16
diff --git a/include/hw/char/ibex_uart.h b/include/hw/char/ibex_uart.h
17
index XXXXXXX..XXXXXXX 100644
18
--- a/include/hw/char/ibex_uart.h
19
+++ b/include/hw/char/ibex_uart.h
20
@@ -XXX,XX +XXX,XX @@ REG32(FIFO_CTRL, 0x1c)
21
FIELD(FIFO_CTRL, RXILVL, 2, 3)
22
FIELD(FIFO_CTRL, TXILVL, 5, 2)
23
REG32(FIFO_STATUS, 0x20)
24
+ FIELD(FIFO_STATUS, TXLVL, 0, 5)
25
+ FIELD(FIFO_STATUS, RXLVL, 16, 5)
26
REG32(OVRD, 0x24)
27
REG32(VAL, 0x28)
28
REG32(TIMEOUT_CTRL, 0x2c)
29
@@ -XXX,XX +XXX,XX @@ struct IbexUartState {
30
uint8_t tx_fifo[IBEX_UART_TX_FIFO_SIZE];
31
uint32_t tx_level;
32
33
+ uint32_t rx_level;
34
+
35
QEMUTimer *fifo_trigger_handle;
36
uint64_t char_tx_time;
37
38
diff --git a/hw/char/ibex_uart.c b/hw/char/ibex_uart.c
39
index XXXXXXX..XXXXXXX 100644
40
--- a/hw/char/ibex_uart.c
41
+++ b/hw/char/ibex_uart.c
42
@@ -XXX,XX +XXX,XX @@ static int ibex_uart_can_receive(void *opaque)
43
{
44
IbexUartState *s = opaque;
45
46
- if (s->uart_ctrl & R_CTRL_RX_ENABLE_MASK) {
47
+ if ((s->uart_ctrl & R_CTRL_RX_ENABLE_MASK)
48
+ && !(s->uart_status & R_STATUS_RXFULL_MASK)) {
49
return 1;
50
}
51
52
@@ -XXX,XX +XXX,XX @@ static void ibex_uart_receive(void *opaque, const uint8_t *buf, int size)
53
54
s->uart_status &= ~R_STATUS_RXIDLE_MASK;
55
s->uart_status &= ~R_STATUS_RXEMPTY_MASK;
56
+ /* The RXFULL is set after receiving a single byte
57
+ * as the FIFO buffers are not yet implemented.
58
+ */
59
+ s->uart_status |= R_STATUS_RXFULL_MASK;
60
+ s->rx_level += 1;
61
62
if (size > rx_fifo_level) {
63
s->uart_intr_state |= R_INTR_STATE_RX_WATERMARK_MASK;
64
@@ -XXX,XX +XXX,XX @@ static void ibex_uart_reset(DeviceState *dev)
65
s->uart_timeout_ctrl = 0x00000000;
66
67
s->tx_level = 0;
68
+ s->rx_level = 0;
69
70
s->char_tx_time = (NANOSECONDS_PER_SECOND / 230400) * 10;
71
72
@@ -XXX,XX +XXX,XX @@ static uint64_t ibex_uart_read(void *opaque, hwaddr addr,
73
74
case R_RDATA:
75
retvalue = s->uart_rdata;
76
- if (s->uart_ctrl & R_CTRL_RX_ENABLE_MASK) {
77
+ if ((s->uart_ctrl & R_CTRL_RX_ENABLE_MASK) && (s->rx_level > 0)) {
78
qemu_chr_fe_accept_input(&s->chr);
79
80
- s->uart_status |= R_STATUS_RXIDLE_MASK;
81
- s->uart_status |= R_STATUS_RXEMPTY_MASK;
82
+ s->rx_level -= 1;
83
+ s->uart_status &= ~R_STATUS_RXFULL_MASK;
84
+ if (s->rx_level == 0) {
85
+ s->uart_status |= R_STATUS_RXIDLE_MASK;
86
+ s->uart_status |= R_STATUS_RXEMPTY_MASK;
87
+ }
88
}
89
break;
90
case R_WDATA:
91
@@ -XXX,XX +XXX,XX @@ static uint64_t ibex_uart_read(void *opaque, hwaddr addr,
92
case R_FIFO_STATUS:
93
retvalue = s->uart_fifo_status;
94
95
- retvalue |= s->tx_level & 0x1F;
96
+ retvalue |= (s->rx_level & 0x1F) << R_FIFO_STATUS_RXLVL_SHIFT;
97
+ retvalue |= (s->tx_level & 0x1F) << R_FIFO_STATUS_TXLVL_SHIFT;
98
99
qemu_log_mask(LOG_UNIMP,
100
"%s: RX fifos are not supported\n", __func__);
101
@@ -XXX,XX +XXX,XX @@ static void ibex_uart_write(void *opaque, hwaddr addr,
102
s->uart_fifo_ctrl = value;
103
104
if (value & R_FIFO_CTRL_RXRST_MASK) {
105
+ s->rx_level = 0;
106
qemu_log_mask(LOG_UNIMP,
107
"%s: RX fifos are not supported\n", __func__);
108
}
109
--
110
2.30.1
111
112
diff view generated by jsdifflib
[PULL 05/12] target/riscv/pmp: Raise exception if no PMP entry is configured
[PULL 03/16] target/riscv: propagate PMP permission to TLB page
1
From: Atish Patra <atish.patra@wdc.com>
1
From: Jim Shu <cwshu@andestech.com>
2
2
3
As per the privilege specification, any access from S/U mode should fail
3
Currently, PMP permission checking of TLB page is bypassed if TLB hits
4
if no pmp region is configured.
4
Fix it by propagating PMP permission to TLB page permission.
5
5
6
Signed-off-by: Atish Patra <atish.patra@wdc.com>
6
PMP permission checking also use MMU-style API to change TLB permission
7
and size.
8
9
Signed-off-by: Jim Shu <cwshu@andestech.com>
7
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
10
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
8
Message-id: 20201223192553.332508-1-atish.patra@wdc.com
11
Message-id: 1613916082-19528-2-git-send-email-cwshu@andestech.com
9
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
12
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
10
---
13
---
11
target/riscv/pmp.h | 1 +
14
target/riscv/pmp.h | 4 +-
12
target/riscv/op_helper.c | 5 +++++
15
target/riscv/cpu_helper.c | 84 +++++++++++++++++++++++++++++----------
13
target/riscv/pmp.c | 4 ++--
16
target/riscv/pmp.c | 80 +++++++++++++++++++++++++++----------
14
3 files changed, 8 insertions(+), 2 deletions(-)
17
3 files changed, 125 insertions(+), 43 deletions(-)
15
18
16
diff --git a/target/riscv/pmp.h b/target/riscv/pmp.h
19
diff --git a/target/riscv/pmp.h b/target/riscv/pmp.h
17
index XXXXXXX..XXXXXXX 100644
20
index XXXXXXX..XXXXXXX 100644
18
--- a/target/riscv/pmp.h
21
--- a/target/riscv/pmp.h
19
+++ b/target/riscv/pmp.h
22
+++ b/target/riscv/pmp.h
20
@@ -XXX,XX +XXX,XX @@ bool pmp_is_range_in_tlb(CPURISCVState *env, hwaddr tlb_sa,
23
@@ -XXX,XX +XXX,XX @@ void pmpaddr_csr_write(CPURISCVState *env, uint32_t addr_index,
24
target_ulong val);
25
target_ulong pmpaddr_csr_read(CPURISCVState *env, uint32_t addr_index);
26
bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
27
- target_ulong size, pmp_priv_t priv, target_ulong mode);
28
+ target_ulong size, pmp_priv_t privs, pmp_priv_t *allowed_privs,
29
+ target_ulong mode);
30
bool pmp_is_range_in_tlb(CPURISCVState *env, hwaddr tlb_sa,
21
target_ulong *tlb_size);
31
target_ulong *tlb_size);
22
void pmp_update_rule_addr(CPURISCVState *env, uint32_t pmp_index);
32
void pmp_update_rule_addr(CPURISCVState *env, uint32_t pmp_index);
23
void pmp_update_rule_nums(CPURISCVState *env);
33
void pmp_update_rule_nums(CPURISCVState *env);
24
+uint32_t pmp_get_num_rules(CPURISCVState *env);
34
uint32_t pmp_get_num_rules(CPURISCVState *env);
35
+int pmp_priv_to_page_prot(pmp_priv_t pmp_priv);
25
36
26
#endif
37
#endif
27
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
38
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
28
index XXXXXXX..XXXXXXX 100644
39
index XXXXXXX..XXXXXXX 100644
29
--- a/target/riscv/op_helper.c
40
--- a/target/riscv/cpu_helper.c
30
+++ b/target/riscv/op_helper.c
41
+++ b/target/riscv/cpu_helper.c
31
@@ -XXX,XX +XXX,XX @@ target_ulong helper_mret(CPURISCVState *env, target_ulong cpu_pc_deb)
42
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv)
32
43
env->load_res = -1;
33
uint64_t mstatus = env->mstatus;
44
}
34
target_ulong prev_priv = get_field(mstatus, MSTATUS_MPP);
45
35
+
46
+/*
36
+ if (!pmp_get_num_rules(env) && (prev_priv != PRV_M)) {
47
+ * get_physical_address_pmp - check PMP permission for this physical address
37
+ riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
48
+ *
38
+ }
49
+ * Match the PMP region and check permission for this physical address and it's
39
+
50
+ * TLB page. Returns 0 if the permission checking was successful
40
target_ulong prev_virt = get_field(env->mstatus, MSTATUS_MPV);
51
+ *
41
mstatus = set_field(mstatus, MSTATUS_MIE,
52
+ * @env: CPURISCVState
42
get_field(mstatus, MSTATUS_MPIE));
53
+ * @prot: The returned protection attributes
54
+ * @tlb_size: TLB page size containing addr. It could be modified after PMP
55
+ * permission checking. NULL if not set TLB page for addr.
56
+ * @addr: The physical address to be checked permission
57
+ * @access_type: The type of MMU access
58
+ * @mode: Indicates current privilege level.
59
+ */
60
+static int get_physical_address_pmp(CPURISCVState *env, int *prot,
61
+ target_ulong *tlb_size, hwaddr addr,
62
+ int size, MMUAccessType access_type,
63
+ int mode)
64
+{
65
+ pmp_priv_t pmp_priv;
66
+ target_ulong tlb_size_pmp = 0;
67
+
68
+ if (!riscv_feature(env, RISCV_FEATURE_PMP)) {
69
+ *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
70
+ return TRANSLATE_SUCCESS;
71
+ }
72
+
73
+ if (!pmp_hart_has_privs(env, addr, size, 1 << access_type, &pmp_priv,
74
+ mode)) {
75
+ *prot = 0;
76
+ return TRANSLATE_PMP_FAIL;
77
+ }
78
+
79
+ *prot = pmp_priv_to_page_prot(pmp_priv);
80
+ if (tlb_size != NULL) {
81
+ if (pmp_is_range_in_tlb(env, addr & ~(*tlb_size - 1), &tlb_size_pmp)) {
82
+ *tlb_size = tlb_size_pmp;
83
+ }
84
+ }
85
+
86
+ return TRANSLATE_SUCCESS;
87
+}
88
+
89
/* get_physical_address - get the physical address for this virtual address
90
*
91
* Do a page table walk to obtain the physical address corresponding to a
92
@@ -XXX,XX +XXX,XX @@ restart:
93
pte_addr = base + idx * ptesize;
94
}
95
96
- if (riscv_feature(env, RISCV_FEATURE_PMP) &&
97
- !pmp_hart_has_privs(env, pte_addr, sizeof(target_ulong),
98
- 1 << MMU_DATA_LOAD, PRV_S)) {
99
+ int pmp_prot;
100
+ int pmp_ret = get_physical_address_pmp(env, &pmp_prot, NULL, pte_addr,
101
+ sizeof(target_ulong),
102
+ MMU_DATA_LOAD, PRV_S);
103
+ if (pmp_ret != TRANSLATE_SUCCESS) {
104
return TRANSLATE_PMP_FAIL;
105
}
106
107
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
108
#ifndef CONFIG_USER_ONLY
109
vaddr im_address;
110
hwaddr pa = 0;
111
- int prot, prot2;
112
+ int prot, prot2, prot_pmp;
113
bool pmp_violation = false;
114
bool first_stage_error = true;
115
bool two_stage_lookup = false;
116
int ret = TRANSLATE_FAIL;
117
int mode = mmu_idx;
118
- target_ulong tlb_size = 0;
119
+ /* default TLB page size */
120
+ target_ulong tlb_size = TARGET_PAGE_SIZE;
121
122
env->guest_phys_fault_addr = 0;
123
124
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
125
126
prot &= prot2;
127
128
- if (riscv_feature(env, RISCV_FEATURE_PMP) &&
129
- (ret == TRANSLATE_SUCCESS) &&
130
- !pmp_hart_has_privs(env, pa, size, 1 << access_type, mode)) {
131
- ret = TRANSLATE_PMP_FAIL;
132
+ if (ret == TRANSLATE_SUCCESS) {
133
+ ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa,
134
+ size, access_type, mode);
135
+ prot &= prot_pmp;
136
}
137
138
if (ret != TRANSLATE_SUCCESS) {
139
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
140
"%s address=%" VADDR_PRIx " ret %d physical "
141
TARGET_FMT_plx " prot %d\n",
142
__func__, address, ret, pa, prot);
143
- }
144
145
- if (riscv_feature(env, RISCV_FEATURE_PMP) &&
146
- (ret == TRANSLATE_SUCCESS) &&
147
- !pmp_hart_has_privs(env, pa, size, 1 << access_type, mode)) {
148
- ret = TRANSLATE_PMP_FAIL;
149
+ if (ret == TRANSLATE_SUCCESS) {
150
+ ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa,
151
+ size, access_type, mode);
152
+ prot &= prot_pmp;
153
+ }
154
}
155
+
156
if (ret == TRANSLATE_PMP_FAIL) {
157
pmp_violation = true;
158
}
159
160
if (ret == TRANSLATE_SUCCESS) {
161
- if (pmp_is_range_in_tlb(env, pa & TARGET_PAGE_MASK, &tlb_size)) {
162
- tlb_set_page(cs, address & ~(tlb_size - 1), pa & ~(tlb_size - 1),
163
- prot, mmu_idx, tlb_size);
164
- } else {
165
- tlb_set_page(cs, address & TARGET_PAGE_MASK, pa & TARGET_PAGE_MASK,
166
- prot, mmu_idx, TARGET_PAGE_SIZE);
167
- }
168
+ tlb_set_page(cs, address & ~(tlb_size - 1), pa & ~(tlb_size - 1),
169
+ prot, mmu_idx, tlb_size);
170
return true;
171
} else if (probe) {
172
return false;
43
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
173
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
44
index XXXXXXX..XXXXXXX 100644
174
index XXXXXXX..XXXXXXX 100644
45
--- a/target/riscv/pmp.c
175
--- a/target/riscv/pmp.c
46
+++ b/target/riscv/pmp.c
176
+++ b/target/riscv/pmp.c
47
@@ -XXX,XX +XXX,XX @@ static inline int pmp_is_locked(CPURISCVState *env, uint32_t pmp_index)
177
@@ -XXX,XX +XXX,XX @@ static int pmp_is_in_range(CPURISCVState *env, int pmp_index, target_ulong addr)
178
return result;
179
}
180
181
+/*
182
+ * Check if the address has required RWX privs when no PMP entry is matched.
183
+ */
184
+static bool pmp_hart_has_privs_default(CPURISCVState *env, target_ulong addr,
185
+ target_ulong size, pmp_priv_t privs, pmp_priv_t *allowed_privs,
186
+ target_ulong mode)
187
+{
188
+ bool ret;
189
+
190
+ if ((!riscv_feature(env, RISCV_FEATURE_PMP)) || (mode == PRV_M)) {
191
+ /*
192
+ * Privileged spec v1.10 states if HW doesn't implement any PMP entry
193
+ * or no PMP entry matches an M-Mode access, the access succeeds.
194
+ */
195
+ ret = true;
196
+ *allowed_privs = PMP_READ | PMP_WRITE | PMP_EXEC;
197
+ } else {
198
+ /*
199
+ * Other modes are not allowed to succeed if they don't * match a rule,
200
+ * but there are rules. We've checked for no rule earlier in this
201
+ * function.
202
+ */
203
+ ret = false;
204
+ *allowed_privs = 0;
205
+ }
206
+
207
+ return ret;
208
+}
209
+
210
48
/*
211
/*
49
* Count the number of active rules.
212
* Public Interface
213
@@ -XXX,XX +XXX,XX @@ static int pmp_is_in_range(CPURISCVState *env, int pmp_index, target_ulong addr)
214
* Check if the address has required RWX privs to complete desired operation
50
*/
215
*/
51
-static inline uint32_t pmp_get_num_rules(CPURISCVState *env)
216
bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
52
+uint32_t pmp_get_num_rules(CPURISCVState *env)
217
- target_ulong size, pmp_priv_t privs, target_ulong mode)
218
+ target_ulong size, pmp_priv_t privs, pmp_priv_t *allowed_privs,
219
+ target_ulong mode)
53
{
220
{
54
return env->pmp_state.num_rules;
221
int i = 0;
55
}
222
int ret = -1;
56
@@ -XXX,XX +XXX,XX @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
223
int pmp_size = 0;
224
target_ulong s = 0;
225
target_ulong e = 0;
226
- pmp_priv_t allowed_privs = 0;
57
227
58
/* Short cut if no rules */
228
/* Short cut if no rules */
59
if (0 == pmp_get_num_rules(env)) {
229
if (0 == pmp_get_num_rules(env)) {
60
- return true;
230
- return (env->priv == PRV_M) ? true : false;
61
+ return (env->priv == PRV_M) ? true : false;
231
+ return pmp_hart_has_privs_default(env, addr, size, privs,
62
}
232
+ allowed_privs, mode);
233
}
63
234
64
if (size == 0) {
235
if (size == 0) {
236
@@ -XXX,XX +XXX,XX @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
237
* check
238
*/
239
if (((s + e) == 2) && (PMP_AMATCH_OFF != a_field)) {
240
- allowed_privs = PMP_READ | PMP_WRITE | PMP_EXEC;
241
+ *allowed_privs = PMP_READ | PMP_WRITE | PMP_EXEC;
242
if ((mode != PRV_M) || pmp_is_locked(env, i)) {
243
- allowed_privs &= env->pmp_state.pmp[i].cfg_reg;
244
+ *allowed_privs &= env->pmp_state.pmp[i].cfg_reg;
245
}
246
247
- if ((privs & allowed_privs) == privs) {
248
- ret = 1;
249
- break;
250
- } else {
251
- ret = 0;
252
- break;
253
- }
254
+ ret = ((privs & *allowed_privs) == privs);
255
+ break;
256
}
257
}
258
259
/* No rule matched */
260
if (ret == -1) {
261
- if (mode == PRV_M) {
262
- ret = 1; /* Privileged spec v1.10 states if no PMP entry matches an
263
- * M-Mode access, the access succeeds */
264
- } else {
265
- ret = 0; /* Other modes are not allowed to succeed if they don't
266
- * match a rule, but there are rules. We've checked for
267
- * no rule earlier in this function. */
268
- }
269
+ return pmp_hart_has_privs_default(env, addr, size, privs,
270
+ allowed_privs, mode);
271
}
272
273
return ret == 1 ? true : false;
274
}
275
276
-
277
/*
278
* Handle a write to a pmpcfg CSP
279
*/
280
@@ -XXX,XX +XXX,XX @@ bool pmp_is_range_in_tlb(CPURISCVState *env, hwaddr tlb_sa,
281
282
return false;
283
}
284
+
285
+/*
286
+ * Convert PMP privilege to TLB page privilege.
287
+ */
288
+int pmp_priv_to_page_prot(pmp_priv_t pmp_priv)
289
+{
290
+ int prot = 0;
291
+
292
+ if (pmp_priv & PMP_READ) {
293
+ prot |= PAGE_READ;
294
+ }
295
+ if (pmp_priv & PMP_WRITE) {
296
+ prot |= PAGE_WRITE;
297
+ }
298
+ if (pmp_priv & PMP_EXEC) {
299
+ prot |= PAGE_EXEC;
300
+ }
301
+
302
+ return prot;
303
+}
65
--
304
--
66
2.29.2
305
2.30.1
67
306
68
307
diff view generated by jsdifflib
New patch
[PULL 04/16] target/riscv: add log of PMP permission checking
1
From: Jim Shu <cwshu@andestech.com>
1
2
3
Like MMU translation, add qemu log of PMP permission checking for
4
debugging.
5
6
Signed-off-by: Jim Shu <cwshu@andestech.com>
7
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
8
Message-id: 1613916082-19528-3-git-send-email-cwshu@andestech.com
9
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
10
---
11
target/riscv/cpu_helper.c | 12 ++++++++++++
12
1 file changed, 12 insertions(+)
13
14
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/riscv/cpu_helper.c
17
+++ b/target/riscv/cpu_helper.c
18
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
19
if (ret == TRANSLATE_SUCCESS) {
20
ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa,
21
size, access_type, mode);
22
+
23
+ qemu_log_mask(CPU_LOG_MMU,
24
+ "%s PMP address=" TARGET_FMT_plx " ret %d prot"
25
+ " %d tlb_size " TARGET_FMT_lu "\n",
26
+ __func__, pa, ret, prot_pmp, tlb_size);
27
+
28
prot &= prot_pmp;
29
}
30
31
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
32
if (ret == TRANSLATE_SUCCESS) {
33
ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa,
34
size, access_type, mode);
35
+
36
+ qemu_log_mask(CPU_LOG_MMU,
37
+ "%s PMP address=" TARGET_FMT_plx " ret %d prot"
38
+ " %d tlb_size " TARGET_FMT_lu "\n",
39
+ __func__, pa, ret, prot_pmp, tlb_size);
40
+
41
prot &= prot_pmp;
42
}
43
}
44
--
45
2.30.1
46
47
diff view generated by jsdifflib
[PULL 04/12] RISC-V: Place DTB at 3GB boundary instead of 4GB
[PULL 05/16] target/riscv: flush TLB pages if PMP permission has been changed
1
From: Atish Patra <atish.patra@wdc.com>
1
From: Jim Shu <cwshu@andestech.com>
2
2
3
Currently, we place the DTB at 2MB from 4GB or end of DRAM which ever is
3
If PMP permission of any address has been changed by updating PMP entry,
4
lesser. However, Linux kernel can address only 1GB of memory for RV32.
4
flush all TLB pages to prevent from getting old permission.
5
Thus, it can not map anything beyond 3GB (assuming 2GB is the starting address).
6
As a result, it can not process DT and panic if opensbi dynamic firmware
7
is used. While at it, place the DTB further away to avoid in memory placement
8
issues in future.
9
5
10
Fix this by placing the DTB at 16MB from 3GB or end of DRAM whichever is lower.
6
Signed-off-by: Jim Shu <cwshu@andestech.com>
11
7
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
12
Fixes: 66b1205bc5ab ("RISC-V: Copy the fdt in dram instead of ROM")
8
Message-id: 1613916082-19528-4-git-send-email-cwshu@andestech.com
13
14
Reviewed-by: Bin Meng <bin.meng@windriver.com>
15
Tested-by: Bin Meng <bin.meng@windriver.com>
16
Signed-off-by: Atish Patra <atish.patra@wdc.com>
17
Message-id: 20210107091127.3407870-1-atish.patra@wdc.com
18
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
9
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
19
---
10
---
20
hw/riscv/boot.c | 8 ++++----
11
target/riscv/pmp.c | 4 ++++
21
1 file changed, 4 insertions(+), 4 deletions(-)
12
1 file changed, 4 insertions(+)
22
13
23
diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
14
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
24
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
25
--- a/hw/riscv/boot.c
16
--- a/target/riscv/pmp.c
26
+++ b/hw/riscv/boot.c
17
+++ b/target/riscv/pmp.c
27
@@ -XXX,XX +XXX,XX @@ uint32_t riscv_load_fdt(hwaddr dram_base, uint64_t mem_size, void *fdt)
18
@@ -XXX,XX +XXX,XX @@
28
/*
19
#include "qapi/error.h"
29
* We should put fdt as far as possible to avoid kernel/initrd overwriting
20
#include "cpu.h"
30
* its content. But it should be addressable by 32 bit system as well.
21
#include "trace.h"
31
- * Thus, put it at an aligned address that less than fdt size from end of
22
+#include "exec/exec-all.h"
32
- * dram or 4GB whichever is lesser.
23
33
+ * Thus, put it at an 16MB aligned address that less than fdt size from the
24
static void pmp_write_cfg(CPURISCVState *env, uint32_t addr_index,
34
+ * end of dram or 3GB whichever is lesser.
25
uint8_t val);
35
*/
26
@@ -XXX,XX +XXX,XX @@ void pmpcfg_csr_write(CPURISCVState *env, uint32_t reg_index,
36
- temp = MIN(dram_end, 4096 * MiB);
27
cfg_val = (val >> 8 * i) & 0xff;
37
- fdt_addr = QEMU_ALIGN_DOWN(temp - fdtsize, 2 * MiB);
28
pmp_write_cfg(env, (reg_index * 4) + i, cfg_val);
38
+ temp = MIN(dram_end, 3072 * MiB);
29
}
39
+ fdt_addr = QEMU_ALIGN_DOWN(temp - fdtsize, 16 * MiB);
30
+
40
31
+ /* If PMP permission of any addr has been changed, flush TLB pages. */
41
fdt_pack(fdt);
32
+ tlb_flush(env_cpu(env));
42
/* copy in the device tree */
33
}
34
35
43
--
36
--
44
2.29.2
37
2.30.1
45
38
46
39
diff view generated by jsdifflib
New patch
[PULL 06/16] target/riscv: Adjust privilege level for HLV(X)/HSV instructions
1
From: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
1
2
3
According to the specification the "field SPVP of hstatus controls the
4
privilege level of the access" for the hypervisor virtual-machine load
5
and store instructions HLV, HLVX and HSV.
6
7
Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
8
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
9
Message-id: 20210311103005.1400718-1-georg.kotheimer@kernkonzept.com
10
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
11
---
12
target/riscv/cpu_helper.c | 25 ++++++++++++++-----------
13
1 file changed, 14 insertions(+), 11 deletions(-)
14
15
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/target/riscv/cpu_helper.c
18
+++ b/target/riscv/cpu_helper.c
19
@@ -XXX,XX +XXX,XX @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
20
use_background = true;
21
}
22
23
- if (mode == PRV_M && access_type != MMU_INST_FETCH) {
24
+ /* MPRV does not affect the virtual-machine load/store
25
+ instructions, HLV, HLVX, and HSV. */
26
+ if (riscv_cpu_two_stage_lookup(mmu_idx)) {
27
+ mode = get_field(env->hstatus, HSTATUS_SPVP);
28
+ } else if (mode == PRV_M && access_type != MMU_INST_FETCH) {
29
if (get_field(env->mstatus, MSTATUS_MPRV)) {
30
mode = get_field(env->mstatus, MSTATUS_MPP);
31
}
32
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
33
qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d mmu_idx %d\n",
34
__func__, address, access_type, mmu_idx);
35
36
- if (mode == PRV_M && access_type != MMU_INST_FETCH) {
37
- if (get_field(env->mstatus, MSTATUS_MPRV)) {
38
- mode = get_field(env->mstatus, MSTATUS_MPP);
39
+ /* MPRV does not affect the virtual-machine load/store
40
+ instructions, HLV, HLVX, and HSV. */
41
+ if (riscv_cpu_two_stage_lookup(mmu_idx)) {
42
+ mode = get_field(env->hstatus, HSTATUS_SPVP);
43
+ } else if (mode == PRV_M && access_type != MMU_INST_FETCH &&
44
+ get_field(env->mstatus, MSTATUS_MPRV)) {
45
+ mode = get_field(env->mstatus, MSTATUS_MPP);
46
+ if (riscv_has_ext(env, RVH) && get_field(env->mstatus, MSTATUS_MPV)) {
47
+ two_stage_lookup = true;
48
}
49
}
50
51
- if (riscv_has_ext(env, RVH) && env->priv == PRV_M &&
52
- access_type != MMU_INST_FETCH &&
53
- get_field(env->mstatus, MSTATUS_MPRV) &&
54
- get_field(env->mstatus, MSTATUS_MPV)) {
55
- two_stage_lookup = true;
56
- }
57
-
58
if (riscv_cpu_virt_enabled(env) ||
59
((riscv_cpu_two_stage_lookup(mmu_idx) || two_stage_lookup) &&
60
access_type != MMU_INST_FETCH)) {
61
--
62
2.30.1
63
64
diff view generated by jsdifflib
[PULL 09/12] target/riscv: Add CSR name in the CSR function table
[PULL 07/16] target/riscv: Make VSTIP and VSEIP read-only in hip
1
From: Bin Meng <bin.meng@windriver.com>
1
From: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
2
2
3
In preparation to generate the CSR register list for GDB stub
3
Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
4
dynamically, let's add the CSR name in the CSR function table.
5
6
Signed-off-by: Bin Meng <bin.meng@windriver.com>
7
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
4
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
8
Message-id: 1610427124-49887-3-git-send-email-bmeng.cn@gmail.com
5
Message-id: 20210311094902.1377593-1-georg.kotheimer@kernkonzept.com
9
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
6
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
10
---
7
---
11
target/riscv/cpu.h | 1 +
8
target/riscv/csr.c | 7 ++++---
12
target/riscv/csr.c | 332 +++++++++++++++++++++++++++++++++------------
9
1 file changed, 4 insertions(+), 3 deletions(-)
13
2 files changed, 249 insertions(+), 84 deletions(-)
14
10
15
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
16
index XXXXXXX..XXXXXXX 100644
17
--- a/target/riscv/cpu.h
18
+++ b/target/riscv/cpu.h
19
@@ -XXX,XX +XXX,XX @@ typedef int (*riscv_csr_op_fn)(CPURISCVState *env, int csrno,
20
target_ulong *ret_value, target_ulong new_value, target_ulong write_mask);
21
22
typedef struct {
23
+ const char *name;
24
riscv_csr_predicate_fn predicate;
25
riscv_csr_read_fn read;
26
riscv_csr_write_fn write;
27
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
11
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
28
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
29
--- a/target/riscv/csr.c
13
--- a/target/riscv/csr.c
30
+++ b/target/riscv/csr.c
14
+++ b/target/riscv/csr.c
31
@@ -XXX,XX +XXX,XX @@ int riscv_csrrw_debug(CPURISCVState *env, int csrno, target_ulong *ret_value,
15
@@ -XXX,XX +XXX,XX @@ static const target_ulong sstatus_v1_10_mask = SSTATUS_SIE | SSTATUS_SPIE |
32
/* Control and Status Register function table */
16
SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS |
33
riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
17
SSTATUS_SUM | SSTATUS_MXR | SSTATUS_SD;
34
/* User Floating-Point CSRs */
18
static const target_ulong sip_writable_mask = SIP_SSIP | MIP_USIP | MIP_UEIP;
35
- [CSR_FFLAGS] = { fs, read_fflags, write_fflags },
19
-static const target_ulong hip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP;
36
- [CSR_FRM] = { fs, read_frm, write_frm },
20
+static const target_ulong hip_writable_mask = MIP_VSSIP;
37
- [CSR_FCSR] = { fs, read_fcsr, write_fcsr },
21
+static const target_ulong hvip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP;
38
+ [CSR_FFLAGS] = { "fflags", fs, read_fflags, write_fflags },
22
static const target_ulong vsip_writable_mask = MIP_VSSIP;
39
+ [CSR_FRM] = { "frm", fs, read_frm, write_frm },
23
40
+ [CSR_FCSR] = { "fcsr", fs, read_fcsr, write_fcsr },
24
static const char valid_vm_1_10_32[16] = {
41
/* Vector CSRs */
25
@@ -XXX,XX +XXX,XX @@ static int rmw_hvip(CPURISCVState *env, int csrno, target_ulong *ret_value,
42
- [CSR_VSTART] = { vs, read_vstart, write_vstart },
26
target_ulong new_value, target_ulong write_mask)
43
- [CSR_VXSAT] = { vs, read_vxsat, write_vxsat },
27
{
44
- [CSR_VXRM] = { vs, read_vxrm, write_vxrm },
28
int ret = rmw_mip(env, 0, ret_value, new_value,
45
- [CSR_VL] = { vs, read_vl },
29
- write_mask & hip_writable_mask);
46
- [CSR_VTYPE] = { vs, read_vtype },
30
+ write_mask & hvip_writable_mask);
47
+ [CSR_VSTART] = { "vstart", vs, read_vstart, write_vstart },
31
48
+ [CSR_VXSAT] = { "vxsat", vs, read_vxsat, write_vxsat },
32
- *ret_value &= hip_writable_mask;
49
+ [CSR_VXRM] = { "vxrm", vs, read_vxrm, write_vxrm },
33
+ *ret_value &= hvip_writable_mask;
50
+ [CSR_VL] = { "vl", vs, read_vl },
34
51
+ [CSR_VTYPE] = { "vtype", vs, read_vtype },
35
return ret;
52
/* User Timers and Counters */
36
}
53
- [CSR_CYCLE] = { ctr, read_instret },
54
- [CSR_INSTRET] = { ctr, read_instret },
55
- [CSR_CYCLEH] = { ctr32, read_instreth },
56
- [CSR_INSTRETH] = { ctr32, read_instreth },
57
-
58
- /* In privileged mode, the monitor will have to emulate TIME CSRs only if
59
- * rdtime callback is not provided by machine/platform emulation */
60
- [CSR_TIME] = { ctr, read_time },
61
- [CSR_TIMEH] = { ctr32, read_timeh },
62
+ [CSR_CYCLE] = { "cycle", ctr, read_instret },
63
+ [CSR_INSTRET] = { "instret", ctr, read_instret },
64
+ [CSR_CYCLEH] = { "cycleh", ctr32, read_instreth },
65
+ [CSR_INSTRETH] = { "instreth", ctr32, read_instreth },
66
+
67
+ /*
68
+ * In privileged mode, the monitor will have to emulate TIME CSRs only if
69
+ * rdtime callback is not provided by machine/platform emulation.
70
+ */
71
+ [CSR_TIME] = { "time", ctr, read_time },
72
+ [CSR_TIMEH] = { "timeh", ctr32, read_timeh },
73
74
#if !defined(CONFIG_USER_ONLY)
75
/* Machine Timers and Counters */
76
- [CSR_MCYCLE] = { any, read_instret },
77
- [CSR_MINSTRET] = { any, read_instret },
78
- [CSR_MCYCLEH] = { any32, read_instreth },
79
- [CSR_MINSTRETH] = { any32, read_instreth },
80
+ [CSR_MCYCLE] = { "mcycle", any, read_instret },
81
+ [CSR_MINSTRET] = { "minstret", any, read_instret },
82
+ [CSR_MCYCLEH] = { "mcycleh", any32, read_instreth },
83
+ [CSR_MINSTRETH] = { "minstreth", any32, read_instreth },
84
85
/* Machine Information Registers */
86
- [CSR_MVENDORID] = { any, read_zero },
87
- [CSR_MARCHID] = { any, read_zero },
88
- [CSR_MIMPID] = { any, read_zero },
89
- [CSR_MHARTID] = { any, read_mhartid },
90
+ [CSR_MVENDORID] = { "mvendorid", any, read_zero },
91
+ [CSR_MARCHID] = { "marchid", any, read_zero },
92
+ [CSR_MIMPID] = { "mimpid", any, read_zero },
93
+ [CSR_MHARTID] = { "mhartid", any, read_mhartid },
94
95
/* Machine Trap Setup */
96
- [CSR_MSTATUS] = { any, read_mstatus, write_mstatus },
97
- [CSR_MISA] = { any, read_misa, write_misa },
98
- [CSR_MIDELEG] = { any, read_mideleg, write_mideleg },
99
- [CSR_MEDELEG] = { any, read_medeleg, write_medeleg },
100
- [CSR_MIE] = { any, read_mie, write_mie },
101
- [CSR_MTVEC] = { any, read_mtvec, write_mtvec },
102
- [CSR_MCOUNTEREN] = { any, read_mcounteren, write_mcounteren },
103
+ [CSR_MSTATUS] = { "mstatus", any, read_mstatus, write_mstatus },
104
+ [CSR_MISA] = { "misa", any, read_misa, write_misa },
105
+ [CSR_MIDELEG] = { "mideleg", any, read_mideleg, write_mideleg },
106
+ [CSR_MEDELEG] = { "medeleg", any, read_medeleg, write_medeleg },
107
+ [CSR_MIE] = { "mie", any, read_mie, write_mie },
108
+ [CSR_MTVEC] = { "mtvec", any, read_mtvec, write_mtvec },
109
+ [CSR_MCOUNTEREN] = { "mcounteren", any, read_mcounteren, write_mcounteren },
110
111
- [CSR_MSTATUSH] = { any32, read_mstatush, write_mstatush },
112
+ [CSR_MSTATUSH] = { "mstatush", any32, read_mstatush, write_mstatush },
113
114
- [CSR_MSCOUNTEREN] = { any, read_mscounteren, write_mscounteren },
115
+ [CSR_MSCOUNTEREN] = { "msounteren", any, read_mscounteren, write_mscounteren },
116
117
/* Machine Trap Handling */
118
- [CSR_MSCRATCH] = { any, read_mscratch, write_mscratch },
119
- [CSR_MEPC] = { any, read_mepc, write_mepc },
120
- [CSR_MCAUSE] = { any, read_mcause, write_mcause },
121
- [CSR_MBADADDR] = { any, read_mbadaddr, write_mbadaddr },
122
- [CSR_MIP] = { any, NULL, NULL, rmw_mip },
123
+ [CSR_MSCRATCH] = { "mscratch", any, read_mscratch, write_mscratch },
124
+ [CSR_MEPC] = { "mepc", any, read_mepc, write_mepc },
125
+ [CSR_MCAUSE] = { "mcause", any, read_mcause, write_mcause },
126
+ [CSR_MBADADDR] = { "mbadaddr", any, read_mbadaddr, write_mbadaddr },
127
+ [CSR_MIP] = { "mip", any, NULL, NULL, rmw_mip },
128
129
/* Supervisor Trap Setup */
130
- [CSR_SSTATUS] = { smode, read_sstatus, write_sstatus },
131
- [CSR_SIE] = { smode, read_sie, write_sie },
132
- [CSR_STVEC] = { smode, read_stvec, write_stvec },
133
- [CSR_SCOUNTEREN] = { smode, read_scounteren, write_scounteren },
134
+ [CSR_SSTATUS] = { "sstatus", smode, read_sstatus, write_sstatus },
135
+ [CSR_SIE] = { "sie", smode, read_sie, write_sie },
136
+ [CSR_STVEC] = { "stvec", smode, read_stvec, write_stvec },
137
+ [CSR_SCOUNTEREN] = { "scounteren", smode, read_scounteren, write_scounteren },
138
139
/* Supervisor Trap Handling */
140
- [CSR_SSCRATCH] = { smode, read_sscratch, write_sscratch },
141
- [CSR_SEPC] = { smode, read_sepc, write_sepc },
142
- [CSR_SCAUSE] = { smode, read_scause, write_scause },
143
- [CSR_SBADADDR] = { smode, read_sbadaddr, write_sbadaddr },
144
- [CSR_SIP] = { smode, NULL, NULL, rmw_sip },
145
+ [CSR_SSCRATCH] = { "sscratch", smode, read_sscratch, write_sscratch },
146
+ [CSR_SEPC] = { "sepc", smode, read_sepc, write_sepc },
147
+ [CSR_SCAUSE] = { "scause", smode, read_scause, write_scause },
148
+ [CSR_SBADADDR] = { "sbadaddr", smode, read_sbadaddr, write_sbadaddr },
149
+ [CSR_SIP] = { "sip", smode, NULL, NULL, rmw_sip },
150
151
/* Supervisor Protection and Translation */
152
- [CSR_SATP] = { smode, read_satp, write_satp },
153
-
154
- [CSR_HSTATUS] = { hmode, read_hstatus, write_hstatus },
155
- [CSR_HEDELEG] = { hmode, read_hedeleg, write_hedeleg },
156
- [CSR_HIDELEG] = { hmode, read_hideleg, write_hideleg },
157
- [CSR_HVIP] = { hmode, NULL, NULL, rmw_hvip },
158
- [CSR_HIP] = { hmode, NULL, NULL, rmw_hip },
159
- [CSR_HIE] = { hmode, read_hie, write_hie },
160
- [CSR_HCOUNTEREN] = { hmode, read_hcounteren, write_hcounteren },
161
- [CSR_HGEIE] = { hmode, read_hgeie, write_hgeie },
162
- [CSR_HTVAL] = { hmode, read_htval, write_htval },
163
- [CSR_HTINST] = { hmode, read_htinst, write_htinst },
164
- [CSR_HGEIP] = { hmode, read_hgeip, write_hgeip },
165
- [CSR_HGATP] = { hmode, read_hgatp, write_hgatp },
166
- [CSR_HTIMEDELTA] = { hmode, read_htimedelta, write_htimedelta },
167
- [CSR_HTIMEDELTAH] = { hmode32, read_htimedeltah, write_htimedeltah},
168
-
169
- [CSR_VSSTATUS] = { hmode, read_vsstatus, write_vsstatus },
170
- [CSR_VSIP] = { hmode, NULL, NULL, rmw_vsip },
171
- [CSR_VSIE] = { hmode, read_vsie, write_vsie },
172
- [CSR_VSTVEC] = { hmode, read_vstvec, write_vstvec },
173
- [CSR_VSSCRATCH] = { hmode, read_vsscratch, write_vsscratch },
174
- [CSR_VSEPC] = { hmode, read_vsepc, write_vsepc },
175
- [CSR_VSCAUSE] = { hmode, read_vscause, write_vscause },
176
- [CSR_VSTVAL] = { hmode, read_vstval, write_vstval },
177
- [CSR_VSATP] = { hmode, read_vsatp, write_vsatp },
178
-
179
- [CSR_MTVAL2] = { hmode, read_mtval2, write_mtval2 },
180
- [CSR_MTINST] = { hmode, read_mtinst, write_mtinst },
181
+ [CSR_SATP] = { "satp", smode, read_satp, write_satp },
182
+
183
+ [CSR_HSTATUS] = { "hstatus", hmode, read_hstatus, write_hstatus },
184
+ [CSR_HEDELEG] = { "hedeleg", hmode, read_hedeleg, write_hedeleg },
185
+ [CSR_HIDELEG] = { "hideleg", hmode, read_hideleg, write_hideleg },
186
+ [CSR_HVIP] = { "hvip", hmode, NULL, NULL, rmw_hvip },
187
+ [CSR_HIP] = { "hip", hmode, NULL, NULL, rmw_hip },
188
+ [CSR_HIE] = { "hie", hmode, read_hie, write_hie },
189
+ [CSR_HCOUNTEREN] = { "hcounteren", hmode, read_hcounteren, write_hcounteren },
190
+ [CSR_HGEIE] = { "hgeie", hmode, read_hgeie, write_hgeie },
191
+ [CSR_HTVAL] = { "htval", hmode, read_htval, write_htval },
192
+ [CSR_HTINST] = { "htinst", hmode, read_htinst, write_htinst },
193
+ [CSR_HGEIP] = { "hgeip", hmode, read_hgeip, write_hgeip },
194
+ [CSR_HGATP] = { "hgatp", hmode, read_hgatp, write_hgatp },
195
+ [CSR_HTIMEDELTA] = { "htimedelta", hmode, read_htimedelta, write_htimedelta },
196
+ [CSR_HTIMEDELTAH] = { "htimedeltah", hmode32, read_htimedeltah, write_htimedeltah },
197
+
198
+ [CSR_VSSTATUS] = { "vsstatus", hmode, read_vsstatus, write_vsstatus },
199
+ [CSR_VSIP] = { "vsip", hmode, NULL, NULL, rmw_vsip },
200
+ [CSR_VSIE] = { "vsie", hmode, read_vsie, write_vsie },
201
+ [CSR_VSTVEC] = { "vstvec", hmode, read_vstvec, write_vstvec },
202
+ [CSR_VSSCRATCH] = { "vsscratch", hmode, read_vsscratch, write_vsscratch },
203
+ [CSR_VSEPC] = { "vsepc", hmode, read_vsepc, write_vsepc },
204
+ [CSR_VSCAUSE] = { "vscause", hmode, read_vscause, write_vscause },
205
+ [CSR_VSTVAL] = { "vstval", hmode, read_vstval, write_vstval },
206
+ [CSR_VSATP] = { "vsatp", hmode, read_vsatp, write_vsatp },
207
+
208
+ [CSR_MTVAL2] = { "mtval2", hmode, read_mtval2, write_mtval2 },
209
+ [CSR_MTINST] = { "mtinst", hmode, read_mtinst, write_mtinst },
210
211
/* Physical Memory Protection */
212
- [CSR_PMPCFG0 ... CSR_PMPCFG3] = { pmp, read_pmpcfg, write_pmpcfg },
213
- [CSR_PMPADDR0 ... CSR_PMPADDR15] = { pmp, read_pmpaddr, write_pmpaddr },
214
+ [CSR_PMPCFG0] = { "pmpcfg0", pmp, read_pmpcfg, write_pmpcfg },
215
+ [CSR_PMPCFG1] = { "pmpcfg1", pmp, read_pmpcfg, write_pmpcfg },
216
+ [CSR_PMPCFG2] = { "pmpcfg2", pmp, read_pmpcfg, write_pmpcfg },
217
+ [CSR_PMPCFG3] = { "pmpcfg3", pmp, read_pmpcfg, write_pmpcfg },
218
+ [CSR_PMPADDR0] = { "pmpaddr0", pmp, read_pmpaddr, write_pmpaddr },
219
+ [CSR_PMPADDR1] = { "pmpaddr1", pmp, read_pmpaddr, write_pmpaddr },
220
+ [CSR_PMPADDR2] = { "pmpaddr2", pmp, read_pmpaddr, write_pmpaddr },
221
+ [CSR_PMPADDR3] = { "pmpaddr3", pmp, read_pmpaddr, write_pmpaddr },
222
+ [CSR_PMPADDR4] = { "pmpaddr4", pmp, read_pmpaddr, write_pmpaddr },
223
+ [CSR_PMPADDR5] = { "pmpaddr5", pmp, read_pmpaddr, write_pmpaddr },
224
+ [CSR_PMPADDR6] = { "pmpaddr6", pmp, read_pmpaddr, write_pmpaddr },
225
+ [CSR_PMPADDR7] = { "pmpaddr7", pmp, read_pmpaddr, write_pmpaddr },
226
+ [CSR_PMPADDR8] = { "pmpaddr8", pmp, read_pmpaddr, write_pmpaddr },
227
+ [CSR_PMPADDR9] = { "pmpaddr9", pmp, read_pmpaddr, write_pmpaddr },
228
+ [CSR_PMPADDR10] = { "pmpaddr10", pmp, read_pmpaddr, write_pmpaddr },
229
+ [CSR_PMPADDR11] = { "pmpaddr11", pmp, read_pmpaddr, write_pmpaddr },
230
+ [CSR_PMPADDR12] = { "pmpaddr12", pmp, read_pmpaddr, write_pmpaddr },
231
+ [CSR_PMPADDR13] = { "pmpaddr13", pmp, read_pmpaddr, write_pmpaddr },
232
+ [CSR_PMPADDR14] = { "pmpaddr14", pmp, read_pmpaddr, write_pmpaddr },
233
+ [CSR_PMPADDR15] = { "pmpaddr15", pmp, read_pmpaddr, write_pmpaddr },
234
235
/* Performance Counters */
236
- [CSR_HPMCOUNTER3 ... CSR_HPMCOUNTER31] = { ctr, read_zero },
237
- [CSR_MHPMCOUNTER3 ... CSR_MHPMCOUNTER31] = { any, read_zero },
238
- [CSR_MHPMEVENT3 ... CSR_MHPMEVENT31] = { any, read_zero },
239
- [CSR_HPMCOUNTER3H ... CSR_HPMCOUNTER31H] = { ctr32, read_zero },
240
- [CSR_MHPMCOUNTER3H ... CSR_MHPMCOUNTER31H] = { any32, read_zero },
241
+ [CSR_HPMCOUNTER3] = { "hpmcounter3", ctr, read_zero },
242
+ [CSR_HPMCOUNTER4] = { "hpmcounter4", ctr, read_zero },
243
+ [CSR_HPMCOUNTER5] = { "hpmcounter5", ctr, read_zero },
244
+ [CSR_HPMCOUNTER6] = { "hpmcounter6", ctr, read_zero },
245
+ [CSR_HPMCOUNTER7] = { "hpmcounter7", ctr, read_zero },
246
+ [CSR_HPMCOUNTER8] = { "hpmcounter8", ctr, read_zero },
247
+ [CSR_HPMCOUNTER9] = { "hpmcounter9", ctr, read_zero },
248
+ [CSR_HPMCOUNTER10] = { "hpmcounter10", ctr, read_zero },
249
+ [CSR_HPMCOUNTER11] = { "hpmcounter11", ctr, read_zero },
250
+ [CSR_HPMCOUNTER12] = { "hpmcounter12", ctr, read_zero },
251
+ [CSR_HPMCOUNTER13] = { "hpmcounter13", ctr, read_zero },
252
+ [CSR_HPMCOUNTER14] = { "hpmcounter14", ctr, read_zero },
253
+ [CSR_HPMCOUNTER15] = { "hpmcounter15", ctr, read_zero },
254
+ [CSR_HPMCOUNTER16] = { "hpmcounter16", ctr, read_zero },
255
+ [CSR_HPMCOUNTER17] = { "hpmcounter17", ctr, read_zero },
256
+ [CSR_HPMCOUNTER18] = { "hpmcounter18", ctr, read_zero },
257
+ [CSR_HPMCOUNTER19] = { "hpmcounter19", ctr, read_zero },
258
+ [CSR_HPMCOUNTER20] = { "hpmcounter20", ctr, read_zero },
259
+ [CSR_HPMCOUNTER21] = { "hpmcounter21", ctr, read_zero },
260
+ [CSR_HPMCOUNTER22] = { "hpmcounter22", ctr, read_zero },
261
+ [CSR_HPMCOUNTER23] = { "hpmcounter23", ctr, read_zero },
262
+ [CSR_HPMCOUNTER24] = { "hpmcounter24", ctr, read_zero },
263
+ [CSR_HPMCOUNTER25] = { "hpmcounter25", ctr, read_zero },
264
+ [CSR_HPMCOUNTER26] = { "hpmcounter26", ctr, read_zero },
265
+ [CSR_HPMCOUNTER27] = { "hpmcounter27", ctr, read_zero },
266
+ [CSR_HPMCOUNTER28] = { "hpmcounter28", ctr, read_zero },
267
+ [CSR_HPMCOUNTER29] = { "hpmcounter29", ctr, read_zero },
268
+ [CSR_HPMCOUNTER30] = { "hpmcounter30", ctr, read_zero },
269
+ [CSR_HPMCOUNTER31] = { "hpmcounter31", ctr, read_zero },
270
+
271
+ [CSR_MHPMCOUNTER3] = { "mhpmcounter3", any, read_zero },
272
+ [CSR_MHPMCOUNTER4] = { "mhpmcounter4", any, read_zero },
273
+ [CSR_MHPMCOUNTER5] = { "mhpmcounter5", any, read_zero },
274
+ [CSR_MHPMCOUNTER6] = { "mhpmcounter6", any, read_zero },
275
+ [CSR_MHPMCOUNTER7] = { "mhpmcounter7", any, read_zero },
276
+ [CSR_MHPMCOUNTER8] = { "mhpmcounter8", any, read_zero },
277
+ [CSR_MHPMCOUNTER9] = { "mhpmcounter9", any, read_zero },
278
+ [CSR_MHPMCOUNTER10] = { "mhpmcounter10", any, read_zero },
279
+ [CSR_MHPMCOUNTER11] = { "mhpmcounter11", any, read_zero },
280
+ [CSR_MHPMCOUNTER12] = { "mhpmcounter12", any, read_zero },
281
+ [CSR_MHPMCOUNTER13] = { "mhpmcounter13", any, read_zero },
282
+ [CSR_MHPMCOUNTER14] = { "mhpmcounter14", any, read_zero },
283
+ [CSR_MHPMCOUNTER15] = { "mhpmcounter15", any, read_zero },
284
+ [CSR_MHPMCOUNTER16] = { "mhpmcounter16", any, read_zero },
285
+ [CSR_MHPMCOUNTER17] = { "mhpmcounter17", any, read_zero },
286
+ [CSR_MHPMCOUNTER18] = { "mhpmcounter18", any, read_zero },
287
+ [CSR_MHPMCOUNTER19] = { "mhpmcounter19", any, read_zero },
288
+ [CSR_MHPMCOUNTER20] = { "mhpmcounter20", any, read_zero },
289
+ [CSR_MHPMCOUNTER21] = { "mhpmcounter21", any, read_zero },
290
+ [CSR_MHPMCOUNTER22] = { "mhpmcounter22", any, read_zero },
291
+ [CSR_MHPMCOUNTER23] = { "mhpmcounter23", any, read_zero },
292
+ [CSR_MHPMCOUNTER24] = { "mhpmcounter24", any, read_zero },
293
+ [CSR_MHPMCOUNTER25] = { "mhpmcounter25", any, read_zero },
294
+ [CSR_MHPMCOUNTER26] = { "mhpmcounter26", any, read_zero },
295
+ [CSR_MHPMCOUNTER27] = { "mhpmcounter27", any, read_zero },
296
+ [CSR_MHPMCOUNTER28] = { "mhpmcounter28", any, read_zero },
297
+ [CSR_MHPMCOUNTER29] = { "mhpmcounter29", any, read_zero },
298
+ [CSR_MHPMCOUNTER30] = { "mhpmcounter30", any, read_zero },
299
+ [CSR_MHPMCOUNTER31] = { "mhpmcounter31", any, read_zero },
300
+
301
+ [CSR_MHPMEVENT3] = { "mhpmevent3", any, read_zero },
302
+ [CSR_MHPMEVENT4] = { "mhpmevent4", any, read_zero },
303
+ [CSR_MHPMEVENT5] = { "mhpmevent5", any, read_zero },
304
+ [CSR_MHPMEVENT6] = { "mhpmevent6", any, read_zero },
305
+ [CSR_MHPMEVENT7] = { "mhpmevent7", any, read_zero },
306
+ [CSR_MHPMEVENT8] = { "mhpmevent8", any, read_zero },
307
+ [CSR_MHPMEVENT9] = { "mhpmevent9", any, read_zero },
308
+ [CSR_MHPMEVENT10] = { "mhpmevent10", any, read_zero },
309
+ [CSR_MHPMEVENT11] = { "mhpmevent11", any, read_zero },
310
+ [CSR_MHPMEVENT12] = { "mhpmevent12", any, read_zero },
311
+ [CSR_MHPMEVENT13] = { "mhpmevent13", any, read_zero },
312
+ [CSR_MHPMEVENT14] = { "mhpmevent14", any, read_zero },
313
+ [CSR_MHPMEVENT15] = { "mhpmevent15", any, read_zero },
314
+ [CSR_MHPMEVENT16] = { "mhpmevent16", any, read_zero },
315
+ [CSR_MHPMEVENT17] = { "mhpmevent17", any, read_zero },
316
+ [CSR_MHPMEVENT18] = { "mhpmevent18", any, read_zero },
317
+ [CSR_MHPMEVENT19] = { "mhpmevent19", any, read_zero },
318
+ [CSR_MHPMEVENT20] = { "mhpmevent20", any, read_zero },
319
+ [CSR_MHPMEVENT21] = { "mhpmevent21", any, read_zero },
320
+ [CSR_MHPMEVENT22] = { "mhpmevent22", any, read_zero },
321
+ [CSR_MHPMEVENT23] = { "mhpmevent23", any, read_zero },
322
+ [CSR_MHPMEVENT24] = { "mhpmevent24", any, read_zero },
323
+ [CSR_MHPMEVENT25] = { "mhpmevent25", any, read_zero },
324
+ [CSR_MHPMEVENT26] = { "mhpmevent26", any, read_zero },
325
+ [CSR_MHPMEVENT27] = { "mhpmevent27", any, read_zero },
326
+ [CSR_MHPMEVENT28] = { "mhpmevent28", any, read_zero },
327
+ [CSR_MHPMEVENT29] = { "mhpmevent29", any, read_zero },
328
+ [CSR_MHPMEVENT30] = { "mhpmevent30", any, read_zero },
329
+ [CSR_MHPMEVENT31] = { "mhpmevent31", any, read_zero },
330
+
331
+ [CSR_HPMCOUNTER3H] = { "hpmcounter3h", ctr32, read_zero },
332
+ [CSR_HPMCOUNTER4H] = { "hpmcounter4h", ctr32, read_zero },
333
+ [CSR_HPMCOUNTER5H] = { "hpmcounter5h", ctr32, read_zero },
334
+ [CSR_HPMCOUNTER6H] = { "hpmcounter6h", ctr32, read_zero },
335
+ [CSR_HPMCOUNTER7H] = { "hpmcounter7h", ctr32, read_zero },
336
+ [CSR_HPMCOUNTER8H] = { "hpmcounter8h", ctr32, read_zero },
337
+ [CSR_HPMCOUNTER9H] = { "hpmcounter9h", ctr32, read_zero },
338
+ [CSR_HPMCOUNTER10H] = { "hpmcounter10h", ctr32, read_zero },
339
+ [CSR_HPMCOUNTER11H] = { "hpmcounter11h", ctr32, read_zero },
340
+ [CSR_HPMCOUNTER12H] = { "hpmcounter12h", ctr32, read_zero },
341
+ [CSR_HPMCOUNTER13H] = { "hpmcounter13h", ctr32, read_zero },
342
+ [CSR_HPMCOUNTER14H] = { "hpmcounter14h", ctr32, read_zero },
343
+ [CSR_HPMCOUNTER15H] = { "hpmcounter15h", ctr32, read_zero },
344
+ [CSR_HPMCOUNTER16H] = { "hpmcounter16h", ctr32, read_zero },
345
+ [CSR_HPMCOUNTER17H] = { "hpmcounter17h", ctr32, read_zero },
346
+ [CSR_HPMCOUNTER18H] = { "hpmcounter18h", ctr32, read_zero },
347
+ [CSR_HPMCOUNTER19H] = { "hpmcounter19h", ctr32, read_zero },
348
+ [CSR_HPMCOUNTER20H] = { "hpmcounter20h", ctr32, read_zero },
349
+ [CSR_HPMCOUNTER21H] = { "hpmcounter21h", ctr32, read_zero },
350
+ [CSR_HPMCOUNTER22H] = { "hpmcounter22h", ctr32, read_zero },
351
+ [CSR_HPMCOUNTER23H] = { "hpmcounter23h", ctr32, read_zero },
352
+ [CSR_HPMCOUNTER24H] = { "hpmcounter24h", ctr32, read_zero },
353
+ [CSR_HPMCOUNTER25H] = { "hpmcounter25h", ctr32, read_zero },
354
+ [CSR_HPMCOUNTER26H] = { "hpmcounter26h", ctr32, read_zero },
355
+ [CSR_HPMCOUNTER27H] = { "hpmcounter27h", ctr32, read_zero },
356
+ [CSR_HPMCOUNTER28H] = { "hpmcounter28h", ctr32, read_zero },
357
+ [CSR_HPMCOUNTER29H] = { "hpmcounter29h", ctr32, read_zero },
358
+ [CSR_HPMCOUNTER30H] = { "hpmcounter30h", ctr32, read_zero },
359
+ [CSR_HPMCOUNTER31H] = { "hpmcounter31h", ctr32, read_zero },
360
+
361
+ [CSR_MHPMCOUNTER3H] = { "mhpmcounter3h", any32, read_zero },
362
+ [CSR_MHPMCOUNTER4H] = { "mhpmcounter4h", any32, read_zero },
363
+ [CSR_MHPMCOUNTER5H] = { "mhpmcounter5h", any32, read_zero },
364
+ [CSR_MHPMCOUNTER6H] = { "mhpmcounter6h", any32, read_zero },
365
+ [CSR_MHPMCOUNTER7H] = { "mhpmcounter7h", any32, read_zero },
366
+ [CSR_MHPMCOUNTER8H] = { "mhpmcounter8h", any32, read_zero },
367
+ [CSR_MHPMCOUNTER9H] = { "mhpmcounter9h", any32, read_zero },
368
+ [CSR_MHPMCOUNTER10H] = { "mhpmcounter10h", any32, read_zero },
369
+ [CSR_MHPMCOUNTER11H] = { "mhpmcounter11h", any32, read_zero },
370
+ [CSR_MHPMCOUNTER12H] = { "mhpmcounter12h", any32, read_zero },
371
+ [CSR_MHPMCOUNTER13H] = { "mhpmcounter13h", any32, read_zero },
372
+ [CSR_MHPMCOUNTER14H] = { "mhpmcounter14h", any32, read_zero },
373
+ [CSR_MHPMCOUNTER15H] = { "mhpmcounter15h", any32, read_zero },
374
+ [CSR_MHPMCOUNTER16H] = { "mhpmcounter16h", any32, read_zero },
375
+ [CSR_MHPMCOUNTER17H] = { "mhpmcounter17h", any32, read_zero },
376
+ [CSR_MHPMCOUNTER18H] = { "mhpmcounter18h", any32, read_zero },
377
+ [CSR_MHPMCOUNTER19H] = { "mhpmcounter19h", any32, read_zero },
378
+ [CSR_MHPMCOUNTER20H] = { "mhpmcounter20h", any32, read_zero },
379
+ [CSR_MHPMCOUNTER21H] = { "mhpmcounter21h", any32, read_zero },
380
+ [CSR_MHPMCOUNTER22H] = { "mhpmcounter22h", any32, read_zero },
381
+ [CSR_MHPMCOUNTER23H] = { "mhpmcounter23h", any32, read_zero },
382
+ [CSR_MHPMCOUNTER24H] = { "mhpmcounter24h", any32, read_zero },
383
+ [CSR_MHPMCOUNTER25H] = { "mhpmcounter25h", any32, read_zero },
384
+ [CSR_MHPMCOUNTER26H] = { "mhpmcounter26h", any32, read_zero },
385
+ [CSR_MHPMCOUNTER27H] = { "mhpmcounter27h", any32, read_zero },
386
+ [CSR_MHPMCOUNTER28H] = { "mhpmcounter28h", any32, read_zero },
387
+ [CSR_MHPMCOUNTER29H] = { "mhpmcounter29h", any32, read_zero },
388
+ [CSR_MHPMCOUNTER30H] = { "mhpmcounter30h", any32, read_zero },
389
+ [CSR_MHPMCOUNTER31H] = { "mhpmcounter31h", any32, read_zero },
390
#endif /* !CONFIG_USER_ONLY */
391
};
392
--
37
--
393
2.29.2
38
2.30.1
394
39
395
40
diff view generated by jsdifflib
[PULL 07/12] hw/misc/sifive_u_otp: handling the fails of blk_pread and blk_pwrite
[PULL 08/16] target/riscv: Use background registers also for MSTATUS_MPV
1
From: Green Wan <green.wan@sifive.com>
1
From: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
2
2
3
Fix code coverage issues by checking return value and handling fail case
3
The current condition for the use of background registers only
4
of blk_pread() and blk_pwrite(). Return default value 0xff if read fails.
4
considers the hypervisor load and store instructions,
5
but not accesses from M mode via MSTATUS_MPRV+MPV.
5
6
6
Fixes: Coverity CID 1435959
7
Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
7
Fixes: Coverity CID 1435960
8
Fixes: Coverity CID 1435961
9
Signed-off-by: Green Wan <green.wan@sifive.com>
10
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
8
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
11
Message-id: 20201104092900.21214-1-green.wan@sifive.com
9
Message-id: 20210311103036.1401073-1-georg.kotheimer@kernkonzept.com
12
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
10
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
13
---
11
---
14
hw/misc/sifive_u_otp.c | 31 +++++++++++++++++++++++--------
12
target/riscv/cpu_helper.c | 2 +-
15
1 file changed, 23 insertions(+), 8 deletions(-)
13
1 file changed, 1 insertion(+), 1 deletion(-)
16
14
17
diff --git a/hw/misc/sifive_u_otp.c b/hw/misc/sifive_u_otp.c
15
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
18
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/misc/sifive_u_otp.c
17
--- a/target/riscv/cpu_helper.c
20
+++ b/hw/misc/sifive_u_otp.c
18
+++ b/target/riscv/cpu_helper.c
21
@@ -XXX,XX +XXX,XX @@ static uint64_t sifive_u_otp_read(void *opaque, hwaddr addr, unsigned int size)
19
@@ -XXX,XX +XXX,XX @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
22
if (s->blk) {
20
* was called. Background registers will be used if the guest has
23
int32_t buf;
21
* forced a two stage translation to be on (in HS or M mode).
24
22
*/
25
- blk_pread(s->blk, s->pa * SIFIVE_U_OTP_FUSE_WORD, &buf,
23
- if (!riscv_cpu_virt_enabled(env) && riscv_cpu_two_stage_lookup(mmu_idx)) {
26
- SIFIVE_U_OTP_FUSE_WORD);
24
+ if (!riscv_cpu_virt_enabled(env) && two_stage) {
27
+ if (blk_pread(s->blk, s->pa * SIFIVE_U_OTP_FUSE_WORD, &buf,
25
use_background = true;
28
+ SIFIVE_U_OTP_FUSE_WORD) < 0) {
29
+ qemu_log_mask(LOG_GUEST_ERROR,
30
+ "read error index<%d>\n", s->pa);
31
+ return 0xff;
32
+ }
33
+
34
return buf;
35
}
36
37
@@ -XXX,XX +XXX,XX @@ static void sifive_u_otp_write(void *opaque, hwaddr addr,
38
39
/* write to backend */
40
if (s->blk) {
41
- blk_pwrite(s->blk, s->pa * SIFIVE_U_OTP_FUSE_WORD,
42
- &s->fuse[s->pa], SIFIVE_U_OTP_FUSE_WORD, 0);
43
+ if (blk_pwrite(s->blk, s->pa * SIFIVE_U_OTP_FUSE_WORD,
44
+ &s->fuse[s->pa], SIFIVE_U_OTP_FUSE_WORD,
45
+ 0) < 0) {
46
+ qemu_log_mask(LOG_GUEST_ERROR,
47
+ "write error index<%d>\n", s->pa);
48
+ }
49
}
50
51
/* update written bit */
52
@@ -XXX,XX +XXX,XX @@ static void sifive_u_otp_reset(DeviceState *dev)
53
int index = SIFIVE_U_OTP_SERIAL_ADDR;
54
55
serial_data = s->serial;
56
- blk_pwrite(s->blk, index * SIFIVE_U_OTP_FUSE_WORD,
57
- &serial_data, SIFIVE_U_OTP_FUSE_WORD, 0);
58
+ if (blk_pwrite(s->blk, index * SIFIVE_U_OTP_FUSE_WORD,
59
+ &serial_data, SIFIVE_U_OTP_FUSE_WORD, 0) < 0) {
60
+ qemu_log_mask(LOG_GUEST_ERROR,
61
+ "write error index<%d>\n", index);
62
+ }
63
64
serial_data = ~(s->serial);
65
- blk_pwrite(s->blk, (index + 1) * SIFIVE_U_OTP_FUSE_WORD,
66
- &serial_data, SIFIVE_U_OTP_FUSE_WORD, 0);
67
+ if (blk_pwrite(s->blk, (index + 1) * SIFIVE_U_OTP_FUSE_WORD,
68
+ &serial_data, SIFIVE_U_OTP_FUSE_WORD, 0) < 0) {
69
+ qemu_log_mask(LOG_GUEST_ERROR,
70
+ "write error index<%d>\n", index + 1);
71
+ }
72
}
26
}
73
27
74
/* Initialize write-once map */
75
--
28
--
76
2.29.2
29
2.30.1
77
30
78
31
diff view generated by jsdifflib
[PULL 02/12] hw/block: m25p80: Implement AAI-WP command support for SST flashes
[PULL 09/16] hw/riscv: Add fw_cfg support to virt
1
From: Xuzhou Cheng <xuzhou.cheng@windriver.com>
1
From: Asherah Connor <ashe@kivikakk.ee>
2
2
3
Auto Address Increment (AAI) Word-Program is a special command of
3
Provides fw_cfg for the virt machine on riscv. This enables
4
SST flashes. AAI-WP allows multiple bytes of data to be programmed
4
using e.g. ramfb later.
5
without re-issuing the next sequential address location.
6
5
7
Signed-off-by: Xuzhou Cheng <xuzhou.cheng@windriver.com>
6
Signed-off-by: Asherah Connor <ashe@kivikakk.ee>
8
Signed-off-by: Bin Meng <bin.meng@windriver.com>
7
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
9
Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
8
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
10
Message-id: 1608688825-81519-2-git-send-email-bmeng.cn@gmail.com
9
Message-id: 20210318235041.17175-2-ashe@kivikakk.ee
11
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
10
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
12
---
11
---
13
hw/block/m25p80.c | 73 +++++++++++++++++++++++++++++++++++++++++++++++
12
include/hw/riscv/virt.h | 2 ++
14
1 file changed, 73 insertions(+)
13
hw/riscv/virt.c | 30 ++++++++++++++++++++++++++++++
14
hw/riscv/Kconfig | 1 +
15
3 files changed, 33 insertions(+)
15
16
16
diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
17
diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
17
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/block/m25p80.c
19
--- a/include/hw/riscv/virt.h
19
+++ b/hw/block/m25p80.c
20
+++ b/include/hw/riscv/virt.h
20
@@ -XXX,XX +XXX,XX @@ typedef enum {
21
@@ -XXX,XX +XXX,XX @@ struct RISCVVirtState {
21
QPP_4 = 0x34,
22
RISCVHartArrayState soc[VIRT_SOCKETS_MAX];
22
RDID_90 = 0x90,
23
DeviceState *plic[VIRT_SOCKETS_MAX];
23
RDID_AB = 0xab,
24
PFlashCFI01 *flash[2];
24
+ AAI_WP = 0xad,
25
+ FWCfgState *fw_cfg;
25
26
26
ERASE_4K = 0x20,
27
int fdt_size;
27
ERASE4_4K = 0x21,
28
};
28
@@ -XXX,XX +XXX,XX @@ struct Flash {
29
@@ -XXX,XX +XXX,XX @@ enum {
29
bool four_bytes_address_mode;
30
VIRT_PLIC,
30
bool reset_enable;
31
VIRT_UART0,
31
bool quad_enable;
32
VIRT_VIRTIO,
32
+ bool aai_enable;
33
+ VIRT_FW_CFG,
33
uint8_t ear;
34
VIRT_FLASH,
34
35
VIRT_DRAM,
35
int64_t dirty_page;
36
VIRT_PCIE_MMIO,
36
@@ -XXX,XX +XXX,XX @@ static void complete_collecting_data(Flash *s)
37
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
37
case PP4_4:
38
index XXXXXXX..XXXXXXX 100644
38
s->state = STATE_PAGE_PROGRAM;
39
--- a/hw/riscv/virt.c
39
break;
40
+++ b/hw/riscv/virt.c
40
+ case AAI_WP:
41
@@ -XXX,XX +XXX,XX @@ static const MemMapEntry virt_memmap[] = {
41
+ /* AAI programming starts from the even address */
42
[VIRT_PLIC] = { 0xc000000, VIRT_PLIC_SIZE(VIRT_CPUS_MAX * 2) },
42
+ s->cur_addr &= ~BIT(0);
43
[VIRT_UART0] = { 0x10000000, 0x100 },
43
+ s->state = STATE_PAGE_PROGRAM;
44
[VIRT_VIRTIO] = { 0x10001000, 0x1000 },
44
+ break;
45
+ [VIRT_FW_CFG] = { 0x10100000, 0x18 },
45
case READ:
46
[VIRT_FLASH] = { 0x20000000, 0x4000000 },
46
case READ4:
47
[VIRT_PCIE_ECAM] = { 0x30000000, 0x10000000 },
47
case FAST_READ:
48
[VIRT_PCIE_MMIO] = { 0x40000000, 0x40000000 },
48
@@ -XXX,XX +XXX,XX @@ static void reset_memory(Flash *s)
49
@@ -XXX,XX +XXX,XX @@ static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem,
49
s->write_enable = false;
50
return dev;
50
s->reset_enable = false;
51
s->quad_enable = false;
52
+ s->aai_enable = false;
53
54
switch (get_man(s)) {
55
case MAN_NUMONYX:
56
@@ -XXX,XX +XXX,XX @@ static void decode_qio_read_cmd(Flash *s)
57
s->state = STATE_COLLECTING_DATA;
58
}
51
}
59
52
60
+static bool is_valid_aai_cmd(uint32_t cmd)
53
+static FWCfgState *create_fw_cfg(const MachineState *mc)
61
+{
54
+{
62
+ return cmd == AAI_WP || cmd == WRDI || cmd == RDSR;
55
+ hwaddr base = virt_memmap[VIRT_FW_CFG].base;
56
+ hwaddr size = virt_memmap[VIRT_FW_CFG].size;
57
+ FWCfgState *fw_cfg;
58
+ char *nodename;
59
+
60
+ fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16,
61
+ &address_space_memory);
62
+ fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)mc->smp.cpus);
63
+
64
+ nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base);
65
+ qemu_fdt_add_subnode(mc->fdt, nodename);
66
+ qemu_fdt_setprop_string(mc->fdt, nodename,
67
+ "compatible", "qemu,fw-cfg-mmio");
68
+ qemu_fdt_setprop_sized_cells(mc->fdt, nodename, "reg",
69
+ 2, base, 2, size);
70
+ qemu_fdt_setprop(mc->fdt, nodename, "dma-coherent", NULL, 0);
71
+ g_free(nodename);
72
+ return fw_cfg;
63
+}
73
+}
64
+
74
+
65
static void decode_new_cmd(Flash *s, uint32_t value)
75
static void virt_machine_init(MachineState *machine)
66
{
76
{
67
int i;
77
const MemMapEntry *memmap = virt_memmap;
68
@@ -XXX,XX +XXX,XX @@ static void decode_new_cmd(Flash *s, uint32_t value)
78
@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
69
s->reset_enable = false;
79
start_addr = virt_memmap[VIRT_FLASH].base;
70
}
80
}
71
81
72
+ if (get_man(s) == MAN_SST && s->aai_enable && !is_valid_aai_cmd(value)) {
82
+ /*
73
+ qemu_log_mask(LOG_GUEST_ERROR,
83
+ * Init fw_cfg. Must be done before riscv_load_fdt, otherwise the device
74
+ "M25P80: Invalid cmd within AAI programming sequence");
84
+ * tree cannot be altered and we get FDT_ERR_NOSPACE.
75
+ }
85
+ */
86
+ s->fw_cfg = create_fw_cfg(machine);
87
+ rom_set_fw(s->fw_cfg);
76
+
88
+
77
switch (value) {
89
/* Compute the fdt load address in dram */
78
90
fdt_load_addr = riscv_load_fdt(memmap[VIRT_DRAM].base,
79
case ERASE_4K:
91
machine->ram_size, machine->fdt);
80
@@ -XXX,XX +XXX,XX @@ static void decode_new_cmd(Flash *s, uint32_t value)
92
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
81
93
index XXXXXXX..XXXXXXX 100644
82
case WRDI:
94
--- a/hw/riscv/Kconfig
83
s->write_enable = false;
95
+++ b/hw/riscv/Kconfig
84
+ if (get_man(s) == MAN_SST) {
96
@@ -XXX,XX +XXX,XX @@ config RISCV_VIRT
85
+ s->aai_enable = false;
97
select SIFIVE_PLIC
86
+ }
98
select SIFIVE_TEST
87
break;
99
select VIRTIO_MMIO
88
case WREN:
100
+ select FW_CFG_DMA
89
s->write_enable = true;
101
90
@@ -XXX,XX +XXX,XX @@ static void decode_new_cmd(Flash *s, uint32_t value)
102
config SIFIVE_E
91
if (get_man(s) == MAN_MACRONIX) {
103
bool
92
s->data[0] |= (!!s->quad_enable) << 6;
93
}
94
+ if (get_man(s) == MAN_SST) {
95
+ s->data[0] |= (!!s->aai_enable) << 6;
96
+ }
97
+
98
s->pos = 0;
99
s->len = 1;
100
s->data_read_loop = true;
101
@@ -XXX,XX +XXX,XX @@ static void decode_new_cmd(Flash *s, uint32_t value)
102
case RSTQIO:
103
s->quad_enable = false;
104
break;
105
+ case AAI_WP:
106
+ if (get_man(s) == MAN_SST) {
107
+ if (s->write_enable) {
108
+ if (s->aai_enable) {
109
+ s->state = STATE_PAGE_PROGRAM;
110
+ } else {
111
+ s->aai_enable = true;
112
+ s->needed_bytes = get_addr_length(s);
113
+ s->state = STATE_COLLECTING_DATA;
114
+ }
115
+ } else {
116
+ qemu_log_mask(LOG_GUEST_ERROR,
117
+ "M25P80: AAI_WP with write protect\n");
118
+ }
119
+ } else {
120
+ qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Unknown cmd %x\n", value);
121
+ }
122
+ break;
123
default:
124
s->pos = 0;
125
s->len = 1;
126
@@ -XXX,XX +XXX,XX @@ static uint32_t m25p80_transfer8(SSIPeripheral *ss, uint32_t tx)
127
trace_m25p80_page_program(s, s->cur_addr, (uint8_t)tx);
128
flash_write8(s, s->cur_addr, (uint8_t)tx);
129
s->cur_addr = (s->cur_addr + 1) & (s->size - 1);
130
+
131
+ if (get_man(s) == MAN_SST && s->aai_enable && s->cur_addr == 0) {
132
+ /*
133
+ * There is no wrap mode during AAI programming once the highest
134
+ * unprotected memory address is reached. The Write-Enable-Latch
135
+ * bit is automatically reset, and AAI programming mode aborts.
136
+ */
137
+ s->write_enable = false;
138
+ s->aai_enable = false;
139
+ }
140
+
141
break;
142
143
case STATE_READ:
144
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_m25p80_data_read_loop = {
145
}
146
};
147
148
+static bool m25p80_aai_enable_needed(void *opaque)
149
+{
150
+ Flash *s = (Flash *)opaque;
151
+
152
+ return s->aai_enable;
153
+}
154
+
155
+static const VMStateDescription vmstate_m25p80_aai_enable = {
156
+ .name = "m25p80/aai_enable",
157
+ .version_id = 1,
158
+ .minimum_version_id = 1,
159
+ .needed = m25p80_aai_enable_needed,
160
+ .fields = (VMStateField[]) {
161
+ VMSTATE_BOOL(aai_enable, Flash),
162
+ VMSTATE_END_OF_LIST()
163
+ }
164
+};
165
+
166
static const VMStateDescription vmstate_m25p80 = {
167
.name = "m25p80",
168
.version_id = 0,
169
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_m25p80 = {
170
},
171
.subsections = (const VMStateDescription * []) {
172
&vmstate_m25p80_data_read_loop,
173
+ &vmstate_m25p80_aai_enable,
174
NULL
175
}
176
};
177
--
104
--
178
2.29.2
105
2.30.1
179
106
180
107
diff view generated by jsdifflib
[PULL 12/12] riscv: Pass RISCVHartArrayState by pointer
[PULL 10/16] hw/riscv: allow ramfb on virt
1
We were accidently passing RISCVHartArrayState by value instead of
1
From: Asherah Connor <ashe@kivikakk.ee>
2
pointer. The type is 824 bytes long so let's correct that and pass it by
3
pointer instead.
4
2
5
Fixes: Coverity CID 1438099
3
Allow ramfb on virt. This lets `-device ramfb' work.
6
Fixes: Coverity CID 1438100
4
7
Fixes: Coverity CID 1438101
5
Signed-off-by: Asherah Connor <ashe@kivikakk.ee>
6
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
7
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
8
Message-id: 20210318235041.17175-3-ashe@kivikakk.ee
8
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
9
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
9
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
10
Reviewed-by: Bin Meng <bin.meng@windriver.com>
11
Message-id: f3e04424723e0e222769991896cc82308fd23f76.1610751609.git.alistair.francis@wdc.com
12
---
10
---
13
include/hw/riscv/boot.h | 6 +++---
11
hw/riscv/virt.c | 3 +++
14
hw/riscv/boot.c | 10 ++++------
12
1 file changed, 3 insertions(+)
15
hw/riscv/sifive_u.c | 10 +++++-----
16
hw/riscv/spike.c | 8 ++++----
17
hw/riscv/virt.c | 8 ++++----
18
5 files changed, 20 insertions(+), 22 deletions(-)
19
13
20
diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h
21
index XXXXXXX..XXXXXXX 100644
22
--- a/include/hw/riscv/boot.h
23
+++ b/include/hw/riscv/boot.h
24
@@ -XXX,XX +XXX,XX @@
25
#include "hw/loader.h"
26
#include "hw/riscv/riscv_hart.h"
27
28
-bool riscv_is_32bit(RISCVHartArrayState harts);
29
+bool riscv_is_32bit(RISCVHartArrayState *harts);
30
31
-target_ulong riscv_calc_kernel_start_addr(RISCVHartArrayState harts,
32
+target_ulong riscv_calc_kernel_start_addr(RISCVHartArrayState *harts,
33
target_ulong firmware_end_addr);
34
target_ulong riscv_find_and_load_firmware(MachineState *machine,
35
const char *default_machine_firmware,
36
@@ -XXX,XX +XXX,XX @@ target_ulong riscv_load_kernel(const char *kernel_filename,
37
hwaddr riscv_load_initrd(const char *filename, uint64_t mem_size,
38
uint64_t kernel_entry, hwaddr *start);
39
uint32_t riscv_load_fdt(hwaddr dram_start, uint64_t dram_size, void *fdt);
40
-void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState harts,
41
+void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState *harts,
42
hwaddr saddr,
43
hwaddr rom_base, hwaddr rom_size,
44
uint64_t kernel_entry,
45
diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
46
index XXXXXXX..XXXXXXX 100644
47
--- a/hw/riscv/boot.c
48
+++ b/hw/riscv/boot.c
49
@@ -XXX,XX +XXX,XX @@
50
51
#include <libfdt.h>
52
53
-bool riscv_is_32bit(RISCVHartArrayState harts)
54
+bool riscv_is_32bit(RISCVHartArrayState *harts)
55
{
56
- RISCVCPU hart = harts.harts[0];
57
-
58
- return riscv_cpu_is_32bit(&hart.env);
59
+ return riscv_cpu_is_32bit(&harts->harts[0].env);
60
}
61
62
-target_ulong riscv_calc_kernel_start_addr(RISCVHartArrayState harts,
63
+target_ulong riscv_calc_kernel_start_addr(RISCVHartArrayState *harts,
64
target_ulong firmware_end_addr) {
65
if (riscv_is_32bit(harts)) {
66
return QEMU_ALIGN_UP(firmware_end_addr, 4 * MiB);
67
@@ -XXX,XX +XXX,XX @@ void riscv_rom_copy_firmware_info(MachineState *machine, hwaddr rom_base,
68
&address_space_memory);
69
}
70
71
-void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState harts,
72
+void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState *harts,
73
hwaddr start_addr,
74
hwaddr rom_base, hwaddr rom_size,
75
uint64_t kernel_entry,
76
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
77
index XXXXXXX..XXXXXXX 100644
78
--- a/hw/riscv/sifive_u.c
79
+++ b/hw/riscv/sifive_u.c
80
@@ -XXX,XX +XXX,XX @@ static void sifive_u_machine_init(MachineState *machine)
81
82
/* create device tree */
83
create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline,
84
- riscv_is_32bit(s->soc.u_cpus));
85
+ riscv_is_32bit(&s->soc.u_cpus));
86
87
if (s->start_in_flash) {
88
/*
89
@@ -XXX,XX +XXX,XX @@ static void sifive_u_machine_init(MachineState *machine)
90
break;
91
}
92
93
- if (riscv_is_32bit(s->soc.u_cpus)) {
94
+ if (riscv_is_32bit(&s->soc.u_cpus)) {
95
firmware_end_addr = riscv_find_and_load_firmware(machine,
96
"opensbi-riscv32-generic-fw_dynamic.bin",
97
start_addr, NULL);
98
@@ -XXX,XX +XXX,XX @@ static void sifive_u_machine_init(MachineState *machine)
99
}
100
101
if (machine->kernel_filename) {
102
- kernel_start_addr = riscv_calc_kernel_start_addr(s->soc.u_cpus,
103
+ kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc.u_cpus,
104
firmware_end_addr);
105
106
kernel_entry = riscv_load_kernel(machine->kernel_filename,
107
@@ -XXX,XX +XXX,XX @@ static void sifive_u_machine_init(MachineState *machine)
108
/* Compute the fdt load address in dram */
109
fdt_load_addr = riscv_load_fdt(memmap[SIFIVE_U_DEV_DRAM].base,
110
machine->ram_size, s->fdt);
111
- if (!riscv_is_32bit(s->soc.u_cpus)) {
112
+ if (!riscv_is_32bit(&s->soc.u_cpus)) {
113
start_addr_hi32 = (uint64_t)start_addr >> 32;
114
}
115
116
@@ -XXX,XX +XXX,XX @@ static void sifive_u_machine_init(MachineState *machine)
117
0x00000000,
118
/* fw_dyn: */
119
};
120
- if (riscv_is_32bit(s->soc.u_cpus)) {
121
+ if (riscv_is_32bit(&s->soc.u_cpus)) {
122
reset_vec[4] = 0x0202a583; /* lw a1, 32(t0) */
123
reset_vec[5] = 0x0182a283; /* lw t0, 24(t0) */
124
} else {
125
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
126
index XXXXXXX..XXXXXXX 100644
127
--- a/hw/riscv/spike.c
128
+++ b/hw/riscv/spike.c
129
@@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine)
130
131
/* create device tree */
132
create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline,
133
- riscv_is_32bit(s->soc[0]));
134
+ riscv_is_32bit(&s->soc[0]));
135
136
/* boot rom */
137
memory_region_init_rom(mask_rom, NULL, "riscv.spike.mrom",
138
@@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine)
139
* keeping ELF files here was intentional because BIN files don't work
140
* for the Spike machine as HTIF emulation depends on ELF parsing.
141
*/
142
- if (riscv_is_32bit(s->soc[0])) {
143
+ if (riscv_is_32bit(&s->soc[0])) {
144
firmware_end_addr = riscv_find_and_load_firmware(machine,
145
"opensbi-riscv32-generic-fw_dynamic.elf",
146
memmap[SPIKE_DRAM].base,
147
@@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine)
148
}
149
150
if (machine->kernel_filename) {
151
- kernel_start_addr = riscv_calc_kernel_start_addr(s->soc[0],
152
+ kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc[0],
153
firmware_end_addr);
154
155
kernel_entry = riscv_load_kernel(machine->kernel_filename,
156
@@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine)
157
fdt_load_addr = riscv_load_fdt(memmap[SPIKE_DRAM].base,
158
machine->ram_size, s->fdt);
159
/* load the reset vector */
160
- riscv_setup_rom_reset_vec(machine, s->soc[0], memmap[SPIKE_DRAM].base,
161
+ riscv_setup_rom_reset_vec(machine, &s->soc[0], memmap[SPIKE_DRAM].base,
162
memmap[SPIKE_MROM].base,
163
memmap[SPIKE_MROM].size, kernel_entry,
164
fdt_load_addr, s->fdt);
165
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
14
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
166
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
167
--- a/hw/riscv/virt.c
16
--- a/hw/riscv/virt.c
168
+++ b/hw/riscv/virt.c
17
+++ b/hw/riscv/virt.c
169
@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
18
@@ -XXX,XX +XXX,XX @@
170
19
#include "sysemu/sysemu.h"
171
/* create device tree */
20
#include "hw/pci/pci.h"
172
create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline,
21
#include "hw/pci-host/gpex.h"
173
- riscv_is_32bit(s->soc[0]));
22
+#include "hw/display/ramfb.h"
174
+ riscv_is_32bit(&s->soc[0]));
23
175
24
static const MemMapEntry virt_memmap[] = {
176
/* boot rom */
25
[VIRT_DEBUG] = { 0x0, 0x100 },
177
memory_region_init_rom(mask_rom, NULL, "riscv_virt_board.mrom",
26
@@ -XXX,XX +XXX,XX @@ static void virt_machine_class_init(ObjectClass *oc, void *data)
178
@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
27
mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props;
179
memory_region_add_subregion(system_memory, memmap[VIRT_MROM].base,
28
mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id;
180
mask_rom);
29
mc->numa_mem_supported = true;
181
30
+
182
- if (riscv_is_32bit(s->soc[0])) {
31
+ machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE);
183
+ if (riscv_is_32bit(&s->soc[0])) {
32
}
184
firmware_end_addr = riscv_find_and_load_firmware(machine,
33
185
"opensbi-riscv32-generic-fw_dynamic.bin",
34
static const TypeInfo virt_machine_typeinfo = {
186
start_addr, NULL);
187
@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
188
}
189
190
if (machine->kernel_filename) {
191
- kernel_start_addr = riscv_calc_kernel_start_addr(s->soc[0],
192
+ kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc[0],
193
firmware_end_addr);
194
195
kernel_entry = riscv_load_kernel(machine->kernel_filename,
196
@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
197
fdt_load_addr = riscv_load_fdt(memmap[VIRT_DRAM].base,
198
machine->ram_size, s->fdt);
199
/* load the reset vector */
200
- riscv_setup_rom_reset_vec(machine, s->soc[0], start_addr,
201
+ riscv_setup_rom_reset_vec(machine, &s->soc[0], start_addr,
202
virt_memmap[VIRT_MROM].base,
203
virt_memmap[VIRT_MROM].size, kernel_entry,
204
fdt_load_addr, s->fdt);
205
--
35
--
206
2.29.2
36
2.30.1
207
37
208
38
diff view generated by jsdifflib
[PULL 03/12] gdb: riscv: Add target description
[PULL 11/16] target/riscv: Fix read and write accesses to vsip and vsie
1
From: Sylvain Pelissier <sylvain.pelissier@gmail.com>
1
From: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
2
2
3
Target description is not currently implemented in RISC-V
3
The previous implementation was broken in many ways:
4
architecture. Thus GDB won't set it properly when attached.
4
- Used mideleg instead of hideleg to mask accesses
5
The patch implements the target description response.
5
- Used MIP_VSSIP instead of VS_MODE_INTERRUPTS to mask writes to vsie
6
- Did not shift between S bits and VS bits (VSEIP <-> SEIP, ...)
6
7
7
Signed-off-by: Sylvain Pelissier <sylvain.pelissier@gmail.com>
8
Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
8
Reviewed-by: Bin Meng <bin.meng@windriver.com>
9
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
9
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
10
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
10
Message-id: 20210311094738.1376795-1-georg.kotheimer@kernkonzept.com
11
Message-id: 20210106204141.14027-1-sylvain.pelissier@gmail.com
12
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
11
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
13
---
12
---
14
target/riscv/cpu.c | 13 +++++++++++++
13
target/riscv/csr.c | 68 +++++++++++++++++++++++-----------------------
15
1 file changed, 13 insertions(+)
14
1 file changed, 34 insertions(+), 34 deletions(-)
16
15
17
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
16
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
18
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
19
--- a/target/riscv/cpu.c
18
--- a/target/riscv/csr.c
20
+++ b/target/riscv/cpu.c
19
+++ b/target/riscv/csr.c
21
@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_properties[] = {
20
@@ -XXX,XX +XXX,XX @@ static int write_sstatus(CPURISCVState *env, int csrno, target_ulong val)
22
DEFINE_PROP_END_OF_LIST(),
21
return write_mstatus(env, CSR_MSTATUS, newval);
23
};
22
}
24
23
25
+static gchar *riscv_gdb_arch_name(CPUState *cs)
24
+static int read_vsie(CPURISCVState *env, int csrno, target_ulong *val)
26
+{
25
+{
27
+ RISCVCPU *cpu = RISCV_CPU(cs);
26
+ /* Shift the VS bits to their S bit location in vsie */
28
+ CPURISCVState *env = &cpu->env;
27
+ *val = (env->mie & env->hideleg & VS_MODE_INTERRUPTS) >> 1;
29
+
28
+ return 0;
30
+ if (riscv_cpu_is_32bit(env)) {
31
+ return g_strdup("riscv:rv32");
32
+ } else {
33
+ return g_strdup("riscv:rv64");
34
+ }
35
+}
29
+}
36
+
30
+
37
static void riscv_cpu_class_init(ObjectClass *c, void *data)
31
static int read_sie(CPURISCVState *env, int csrno, target_ulong *val)
38
{
32
{
39
RISCVCPUClass *mcc = RISCV_CPU_CLASS(c);
33
if (riscv_cpu_virt_enabled(env)) {
40
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
34
- /* Tell the guest the VS bits, shifted to the S bit locations */
41
/* For now, mark unmigratable: */
35
- *val = (env->mie & env->mideleg & VS_MODE_INTERRUPTS) >> 1;
42
cc->vmsd = &vmstate_riscv_cpu;
36
+ read_vsie(env, CSR_VSIE, val);
43
#endif
37
} else {
44
+ cc->gdb_arch_name = riscv_gdb_arch_name;
38
*val = env->mie & env->mideleg;
45
#ifdef CONFIG_TCG
39
}
46
cc->tcg_initialize = riscv_translate_init;
40
return 0;
47
cc->tlb_fill = riscv_cpu_tlb_fill;
41
}
42
43
-static int write_sie(CPURISCVState *env, int csrno, target_ulong val)
44
+static int write_vsie(CPURISCVState *env, int csrno, target_ulong val)
45
{
46
- target_ulong newval;
47
+ /* Shift the S bits to their VS bit location in mie */
48
+ target_ulong newval = (env->mie & ~VS_MODE_INTERRUPTS) |
49
+ ((val << 1) & env->hideleg & VS_MODE_INTERRUPTS);
50
+ return write_mie(env, CSR_MIE, newval);
51
+}
52
53
+static int write_sie(CPURISCVState *env, int csrno, target_ulong val)
54
+{
55
if (riscv_cpu_virt_enabled(env)) {
56
- /* Shift the guests S bits to VS */
57
- newval = (env->mie & ~VS_MODE_INTERRUPTS) |
58
- ((val << 1) & VS_MODE_INTERRUPTS);
59
+ write_vsie(env, CSR_VSIE, val);
60
} else {
61
- newval = (env->mie & ~S_MODE_INTERRUPTS) | (val & S_MODE_INTERRUPTS);
62
+ target_ulong newval = (env->mie & ~S_MODE_INTERRUPTS) |
63
+ (val & S_MODE_INTERRUPTS);
64
+ write_mie(env, CSR_MIE, newval);
65
}
66
67
- return write_mie(env, CSR_MIE, newval);
68
+ return 0;
69
}
70
71
static int read_stvec(CPURISCVState *env, int csrno, target_ulong *val)
72
@@ -XXX,XX +XXX,XX @@ static int write_sbadaddr(CPURISCVState *env, int csrno, target_ulong val)
73
return 0;
74
}
75
76
+static int rmw_vsip(CPURISCVState *env, int csrno, target_ulong *ret_value,
77
+ target_ulong new_value, target_ulong write_mask)
78
+{
79
+ /* Shift the S bits to their VS bit location in mip */
80
+ int ret = rmw_mip(env, 0, ret_value, new_value << 1,
81
+ (write_mask << 1) & vsip_writable_mask & env->hideleg);
82
+ *ret_value &= VS_MODE_INTERRUPTS;
83
+ /* Shift the VS bits to their S bit location in vsip */
84
+ *ret_value >>= 1;
85
+ return ret;
86
+}
87
+
88
static int rmw_sip(CPURISCVState *env, int csrno, target_ulong *ret_value,
89
target_ulong new_value, target_ulong write_mask)
90
{
91
int ret;
92
93
if (riscv_cpu_virt_enabled(env)) {
94
- /* Shift the new values to line up with the VS bits */
95
- ret = rmw_mip(env, CSR_MSTATUS, ret_value, new_value << 1,
96
- (write_mask & sip_writable_mask) << 1 & env->mideleg);
97
- ret &= vsip_writable_mask;
98
- ret >>= 1;
99
+ ret = rmw_vsip(env, CSR_VSIP, ret_value, new_value, write_mask);
100
} else {
101
ret = rmw_mip(env, CSR_MSTATUS, ret_value, new_value,
102
write_mask & env->mideleg & sip_writable_mask);
103
@@ -XXX,XX +XXX,XX @@ static int write_vsstatus(CPURISCVState *env, int csrno, target_ulong val)
104
return 0;
105
}
106
107
-static int rmw_vsip(CPURISCVState *env, int csrno, target_ulong *ret_value,
108
- target_ulong new_value, target_ulong write_mask)
109
-{
110
- int ret = rmw_mip(env, 0, ret_value, new_value,
111
- write_mask & env->mideleg & vsip_writable_mask);
112
- return ret;
113
-}
114
-
115
-static int read_vsie(CPURISCVState *env, int csrno, target_ulong *val)
116
-{
117
- *val = env->mie & env->mideleg & VS_MODE_INTERRUPTS;
118
- return 0;
119
-}
120
-
121
-static int write_vsie(CPURISCVState *env, int csrno, target_ulong val)
122
-{
123
- target_ulong newval = (env->mie & ~env->mideleg) | (val & env->mideleg & MIP_VSSIP);
124
- return write_mie(env, CSR_MIE, newval);
125
-}
126
-
127
static int read_vstvec(CPURISCVState *env, int csrno, target_ulong *val)
128
{
129
*val = env->vstvec;
48
--
130
--
49
2.29.2
131
2.30.1
50
132
51
133
diff view generated by jsdifflib
[PULL 10/12] target/riscv: Generate the GDB XML file for CSR registers dynamically
[PULL 12/16] target/riscv: Add proper two-stage lookup exception detection
1
From: Bin Meng <bin.meng@windriver.com>
1
From: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
2
2
3
At present QEMU RISC-V uses a hardcoded XML to report the feature
3
The current two-stage lookup detection in riscv_cpu_do_interrupt falls
4
"org.gnu.gdb.riscv.csr" [1]. There are two major issues with the
4
short of its purpose, as all it checks is whether two-stage address
5
approach being used currently:
5
translation either via the hypervisor-load store instructions or the
6
MPRV feature would be allowed.
6
7
7
- The XML does not specify the "regnum" field of a CSR entry, hence
8
What we really need instead is whether two-stage address translation was
8
consecutive numbers are used by the remote GDB client to access
9
active when the exception was raised. However, in riscv_cpu_do_interrupt
9
CSRs. In QEMU we have to maintain a map table to convert the GDB
10
we do not have the information to reliably detect this. Therefore, when
10
number to the hardware number which is error prone.
11
we raise a memory fault exception we have to record whether two-stage
11
- The XML contains some CSRs that QEMU does not implement at all,
12
address translation is active.
12
which causes an "E14" response sent to remote GDB client.
13
13
14
Change to generate the CSR register list dynamically, based on the
14
Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
15
availability presented in the CSR function table. This new approach
16
will reflect a correct list of CSRs that QEMU actually implements.
17
18
[1] https://sourceware.org/gdb/current/onlinedocs/gdb/RISC_002dV-Features.html#RISC_002dV-Features
19
20
Signed-off-by: Bin Meng <bin.meng@windriver.com>
21
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
15
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
22
Message-id: 20210116054123.5457-2-bmeng.cn@gmail.com
16
Message-id: 20210319141459.1196741-1-georg.kotheimer@kernkonzept.com
23
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
17
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
24
---
18
---
25
target/riscv/cpu.h | 2 +
19
target/riscv/cpu.h | 4 ++++
26
target/riscv/cpu.c | 12 ++
20
target/riscv/cpu.c | 1 +
27
target/riscv/gdbstub.c | 308 ++++++-----------------------------------
21
target/riscv/cpu_helper.c | 21 ++++++++-------------
28
3 files changed, 58 insertions(+), 264 deletions(-)
22
3 files changed, 13 insertions(+), 13 deletions(-)
29
23
30
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
24
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
31
index XXXXXXX..XXXXXXX 100644
25
index XXXXXXX..XXXXXXX 100644
32
--- a/target/riscv/cpu.h
26
--- a/target/riscv/cpu.h
33
+++ b/target/riscv/cpu.h
27
+++ b/target/riscv/cpu.h
34
@@ -XXX,XX +XXX,XX @@ struct RISCVCPU {
28
@@ -XXX,XX +XXX,XX @@ struct CPURISCVState {
35
CPUNegativeOffsetState neg;
29
target_ulong satp_hs;
36
CPURISCVState env;
30
uint64_t mstatus_hs;
37
31
38
+ char *dyn_csr_xml;
32
+ /* Signals whether the current exception occurred with two-stage address
33
+ translation active. */
34
+ bool two_stage_lookup;
39
+
35
+
40
/* Configuration Settings */
36
target_ulong scounteren;
41
struct {
37
target_ulong mcounteren;
42
bool ext_i;
38
43
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
39
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
44
index XXXXXXX..XXXXXXX 100644
40
index XXXXXXX..XXXXXXX 100644
45
--- a/target/riscv/cpu.c
41
--- a/target/riscv/cpu.c
46
+++ b/target/riscv/cpu.c
42
+++ b/target/riscv/cpu.c
47
@@ -XXX,XX +XXX,XX @@ static gchar *riscv_gdb_arch_name(CPUState *cs)
43
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_reset(DeviceState *dev)
44
env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV);
45
env->mcause = 0;
46
env->pc = env->resetvec;
47
+ env->two_stage_lookup = false;
48
#endif
49
cs->exception_index = EXCP_NONE;
50
env->load_res = -1;
51
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
52
index XXXXXXX..XXXXXXX 100644
53
--- a/target/riscv/cpu_helper.c
54
+++ b/target/riscv/cpu_helper.c
55
@@ -XXX,XX +XXX,XX @@ static void raise_mmu_exception(CPURISCVState *env, target_ulong address,
56
g_assert_not_reached();
48
}
57
}
58
env->badaddr = address;
59
+ env->two_stage_lookup = two_stage;
49
}
60
}
50
61
51
+static const char *riscv_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname)
62
hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
52
+{
63
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
53
+ RISCVCPU *cpu = RISCV_CPU(cs);
64
}
54
+
65
55
+ if (strcmp(xmlname, "riscv-csr.xml") == 0) {
66
env->badaddr = addr;
56
+ return cpu->dyn_csr_xml;
67
+ env->two_stage_lookup = riscv_cpu_virt_enabled(env) ||
57
+ }
68
+ riscv_cpu_two_stage_lookup(mmu_idx);
58
+
69
riscv_raise_exception(&cpu->env, cs->exception_index, retaddr);
59
+ return NULL;
70
}
60
+}
71
61
+
72
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
62
static void riscv_cpu_class_init(ObjectClass *c, void *data)
73
g_assert_not_reached();
63
{
74
}
64
RISCVCPUClass *mcc = RISCV_CPU_CLASS(c);
75
env->badaddr = addr;
65
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
76
+ env->two_stage_lookup = riscv_cpu_virt_enabled(env) ||
66
cc->vmsd = &vmstate_riscv_cpu;
77
+ riscv_cpu_two_stage_lookup(mmu_idx);
78
riscv_raise_exception(env, cs->exception_index, retaddr);
79
}
80
#endif /* !CONFIG_USER_ONLY */
81
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
82
/* handle the trap in S-mode */
83
if (riscv_has_ext(env, RVH)) {
84
target_ulong hdeleg = async ? env->hideleg : env->hedeleg;
85
- bool two_stage_lookup = false;
86
87
- if (env->priv == PRV_M ||
88
- (env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) ||
89
- (env->priv == PRV_U && !riscv_cpu_virt_enabled(env) &&
90
- get_field(env->hstatus, HSTATUS_HU))) {
91
- two_stage_lookup = true;
92
- }
93
-
94
- if ((riscv_cpu_virt_enabled(env) || two_stage_lookup) && write_tval) {
95
+ if (env->two_stage_lookup && write_tval) {
96
/*
97
* If we are writing a guest virtual address to stval, set
98
* this to 1. If we are trapping to VS we will set this to 0
99
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
100
riscv_cpu_set_force_hs_excep(env, 0);
101
} else {
102
/* Trap into HS mode */
103
- if (!two_stage_lookup) {
104
- env->hstatus = set_field(env->hstatus, HSTATUS_SPV,
105
- riscv_cpu_virt_enabled(env));
106
- }
107
+ env->hstatus = set_field(env->hstatus, HSTATUS_SPV, false);
108
htval = env->guest_phys_fault_addr;
109
}
110
}
111
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
112
* RISC-V ISA Specification.
113
*/
114
115
+ env->two_stage_lookup = false;
67
#endif
116
#endif
68
cc->gdb_arch_name = riscv_gdb_arch_name;
117
cs->exception_index = EXCP_NONE; /* mark handled to qemu */
69
+ cc->gdb_get_dynamic_xml = riscv_gdb_get_dynamic_xml;
70
#ifdef CONFIG_TCG
71
cc->tcg_initialize = riscv_translate_init;
72
cc->tlb_fill = riscv_cpu_tlb_fill;
73
diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
74
index XXXXXXX..XXXXXXX 100644
75
--- a/target/riscv/gdbstub.c
76
+++ b/target/riscv/gdbstub.c
77
@@ -XXX,XX +XXX,XX @@
78
#include "exec/gdbstub.h"
79
#include "cpu.h"
80
81
-/*
82
- * The GDB CSR xml files list them in documentation order, not numerical order,
83
- * and are missing entries for unnamed CSRs. So we need to map the gdb numbers
84
- * to the hardware numbers.
85
- */
86
-
87
-static int csr_register_map[] = {
88
- CSR_USTATUS,
89
- CSR_UIE,
90
- CSR_UTVEC,
91
- CSR_USCRATCH,
92
- CSR_UEPC,
93
- CSR_UCAUSE,
94
- CSR_UTVAL,
95
- CSR_UIP,
96
- CSR_FFLAGS,
97
- CSR_FRM,
98
- CSR_FCSR,
99
- CSR_CYCLE,
100
- CSR_TIME,
101
- CSR_INSTRET,
102
- CSR_HPMCOUNTER3,
103
- CSR_HPMCOUNTER4,
104
- CSR_HPMCOUNTER5,
105
- CSR_HPMCOUNTER6,
106
- CSR_HPMCOUNTER7,
107
- CSR_HPMCOUNTER8,
108
- CSR_HPMCOUNTER9,
109
- CSR_HPMCOUNTER10,
110
- CSR_HPMCOUNTER11,
111
- CSR_HPMCOUNTER12,
112
- CSR_HPMCOUNTER13,
113
- CSR_HPMCOUNTER14,
114
- CSR_HPMCOUNTER15,
115
- CSR_HPMCOUNTER16,
116
- CSR_HPMCOUNTER17,
117
- CSR_HPMCOUNTER18,
118
- CSR_HPMCOUNTER19,
119
- CSR_HPMCOUNTER20,
120
- CSR_HPMCOUNTER21,
121
- CSR_HPMCOUNTER22,
122
- CSR_HPMCOUNTER23,
123
- CSR_HPMCOUNTER24,
124
- CSR_HPMCOUNTER25,
125
- CSR_HPMCOUNTER26,
126
- CSR_HPMCOUNTER27,
127
- CSR_HPMCOUNTER28,
128
- CSR_HPMCOUNTER29,
129
- CSR_HPMCOUNTER30,
130
- CSR_HPMCOUNTER31,
131
- CSR_CYCLEH,
132
- CSR_TIMEH,
133
- CSR_INSTRETH,
134
- CSR_HPMCOUNTER3H,
135
- CSR_HPMCOUNTER4H,
136
- CSR_HPMCOUNTER5H,
137
- CSR_HPMCOUNTER6H,
138
- CSR_HPMCOUNTER7H,
139
- CSR_HPMCOUNTER8H,
140
- CSR_HPMCOUNTER9H,
141
- CSR_HPMCOUNTER10H,
142
- CSR_HPMCOUNTER11H,
143
- CSR_HPMCOUNTER12H,
144
- CSR_HPMCOUNTER13H,
145
- CSR_HPMCOUNTER14H,
146
- CSR_HPMCOUNTER15H,
147
- CSR_HPMCOUNTER16H,
148
- CSR_HPMCOUNTER17H,
149
- CSR_HPMCOUNTER18H,
150
- CSR_HPMCOUNTER19H,
151
- CSR_HPMCOUNTER20H,
152
- CSR_HPMCOUNTER21H,
153
- CSR_HPMCOUNTER22H,
154
- CSR_HPMCOUNTER23H,
155
- CSR_HPMCOUNTER24H,
156
- CSR_HPMCOUNTER25H,
157
- CSR_HPMCOUNTER26H,
158
- CSR_HPMCOUNTER27H,
159
- CSR_HPMCOUNTER28H,
160
- CSR_HPMCOUNTER29H,
161
- CSR_HPMCOUNTER30H,
162
- CSR_HPMCOUNTER31H,
163
- CSR_SSTATUS,
164
- CSR_SEDELEG,
165
- CSR_SIDELEG,
166
- CSR_SIE,
167
- CSR_STVEC,
168
- CSR_SCOUNTEREN,
169
- CSR_SSCRATCH,
170
- CSR_SEPC,
171
- CSR_SCAUSE,
172
- CSR_STVAL,
173
- CSR_SIP,
174
- CSR_SATP,
175
- CSR_MVENDORID,
176
- CSR_MARCHID,
177
- CSR_MIMPID,
178
- CSR_MHARTID,
179
- CSR_MSTATUS,
180
- CSR_MISA,
181
- CSR_MEDELEG,
182
- CSR_MIDELEG,
183
- CSR_MIE,
184
- CSR_MTVEC,
185
- CSR_MCOUNTEREN,
186
- CSR_MSCRATCH,
187
- CSR_MEPC,
188
- CSR_MCAUSE,
189
- CSR_MTVAL,
190
- CSR_MIP,
191
- CSR_MTINST,
192
- CSR_MTVAL2,
193
- CSR_PMPCFG0,
194
- CSR_PMPCFG1,
195
- CSR_PMPCFG2,
196
- CSR_PMPCFG3,
197
- CSR_PMPADDR0,
198
- CSR_PMPADDR1,
199
- CSR_PMPADDR2,
200
- CSR_PMPADDR3,
201
- CSR_PMPADDR4,
202
- CSR_PMPADDR5,
203
- CSR_PMPADDR6,
204
- CSR_PMPADDR7,
205
- CSR_PMPADDR8,
206
- CSR_PMPADDR9,
207
- CSR_PMPADDR10,
208
- CSR_PMPADDR11,
209
- CSR_PMPADDR12,
210
- CSR_PMPADDR13,
211
- CSR_PMPADDR14,
212
- CSR_PMPADDR15,
213
- CSR_MCYCLE,
214
- CSR_MINSTRET,
215
- CSR_MHPMCOUNTER3,
216
- CSR_MHPMCOUNTER4,
217
- CSR_MHPMCOUNTER5,
218
- CSR_MHPMCOUNTER6,
219
- CSR_MHPMCOUNTER7,
220
- CSR_MHPMCOUNTER8,
221
- CSR_MHPMCOUNTER9,
222
- CSR_MHPMCOUNTER10,
223
- CSR_MHPMCOUNTER11,
224
- CSR_MHPMCOUNTER12,
225
- CSR_MHPMCOUNTER13,
226
- CSR_MHPMCOUNTER14,
227
- CSR_MHPMCOUNTER15,
228
- CSR_MHPMCOUNTER16,
229
- CSR_MHPMCOUNTER17,
230
- CSR_MHPMCOUNTER18,
231
- CSR_MHPMCOUNTER19,
232
- CSR_MHPMCOUNTER20,
233
- CSR_MHPMCOUNTER21,
234
- CSR_MHPMCOUNTER22,
235
- CSR_MHPMCOUNTER23,
236
- CSR_MHPMCOUNTER24,
237
- CSR_MHPMCOUNTER25,
238
- CSR_MHPMCOUNTER26,
239
- CSR_MHPMCOUNTER27,
240
- CSR_MHPMCOUNTER28,
241
- CSR_MHPMCOUNTER29,
242
- CSR_MHPMCOUNTER30,
243
- CSR_MHPMCOUNTER31,
244
- CSR_MCYCLEH,
245
- CSR_MINSTRETH,
246
- CSR_MHPMCOUNTER3H,
247
- CSR_MHPMCOUNTER4H,
248
- CSR_MHPMCOUNTER5H,
249
- CSR_MHPMCOUNTER6H,
250
- CSR_MHPMCOUNTER7H,
251
- CSR_MHPMCOUNTER8H,
252
- CSR_MHPMCOUNTER9H,
253
- CSR_MHPMCOUNTER10H,
254
- CSR_MHPMCOUNTER11H,
255
- CSR_MHPMCOUNTER12H,
256
- CSR_MHPMCOUNTER13H,
257
- CSR_MHPMCOUNTER14H,
258
- CSR_MHPMCOUNTER15H,
259
- CSR_MHPMCOUNTER16H,
260
- CSR_MHPMCOUNTER17H,
261
- CSR_MHPMCOUNTER18H,
262
- CSR_MHPMCOUNTER19H,
263
- CSR_MHPMCOUNTER20H,
264
- CSR_MHPMCOUNTER21H,
265
- CSR_MHPMCOUNTER22H,
266
- CSR_MHPMCOUNTER23H,
267
- CSR_MHPMCOUNTER24H,
268
- CSR_MHPMCOUNTER25H,
269
- CSR_MHPMCOUNTER26H,
270
- CSR_MHPMCOUNTER27H,
271
- CSR_MHPMCOUNTER28H,
272
- CSR_MHPMCOUNTER29H,
273
- CSR_MHPMCOUNTER30H,
274
- CSR_MHPMCOUNTER31H,
275
- CSR_MHPMEVENT3,
276
- CSR_MHPMEVENT4,
277
- CSR_MHPMEVENT5,
278
- CSR_MHPMEVENT6,
279
- CSR_MHPMEVENT7,
280
- CSR_MHPMEVENT8,
281
- CSR_MHPMEVENT9,
282
- CSR_MHPMEVENT10,
283
- CSR_MHPMEVENT11,
284
- CSR_MHPMEVENT12,
285
- CSR_MHPMEVENT13,
286
- CSR_MHPMEVENT14,
287
- CSR_MHPMEVENT15,
288
- CSR_MHPMEVENT16,
289
- CSR_MHPMEVENT17,
290
- CSR_MHPMEVENT18,
291
- CSR_MHPMEVENT19,
292
- CSR_MHPMEVENT20,
293
- CSR_MHPMEVENT21,
294
- CSR_MHPMEVENT22,
295
- CSR_MHPMEVENT23,
296
- CSR_MHPMEVENT24,
297
- CSR_MHPMEVENT25,
298
- CSR_MHPMEVENT26,
299
- CSR_MHPMEVENT27,
300
- CSR_MHPMEVENT28,
301
- CSR_MHPMEVENT29,
302
- CSR_MHPMEVENT30,
303
- CSR_MHPMEVENT31,
304
- CSR_TSELECT,
305
- CSR_TDATA1,
306
- CSR_TDATA2,
307
- CSR_TDATA3,
308
- CSR_DCSR,
309
- CSR_DPC,
310
- CSR_DSCRATCH,
311
- CSR_HSTATUS,
312
- CSR_HEDELEG,
313
- CSR_HIDELEG,
314
- CSR_HIE,
315
- CSR_HCOUNTEREN,
316
- CSR_HTVAL,
317
- CSR_HIP,
318
- CSR_HTINST,
319
- CSR_HGATP,
320
- CSR_MBASE,
321
- CSR_MBOUND,
322
- CSR_MIBASE,
323
- CSR_MIBOUND,
324
- CSR_MDBASE,
325
- CSR_MDBOUND,
326
- CSR_MUCOUNTEREN,
327
- CSR_MSCOUNTEREN,
328
- CSR_MHCOUNTEREN,
329
-};
330
-
331
int riscv_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
332
{
333
RISCVCPU *cpu = RISCV_CPU(cs);
334
@@ -XXX,XX +XXX,XX @@ static int riscv_gdb_get_fpu(CPURISCVState *env, GByteArray *buf, int n)
335
target_ulong val = 0;
336
int result;
337
/*
338
- * CSR_FFLAGS is at index 8 in csr_register, and gdb says it is FP
339
+ * CSR_FFLAGS is at index 1 in csr_register, and gdb says it is FP
340
* register 33, so we recalculate the map index.
341
* This also works for CSR_FRM and CSR_FCSR.
342
*/
343
- result = riscv_csrrw_debug(env, n - 33 + csr_register_map[8], &val,
344
+ result = riscv_csrrw_debug(env, n - 32, &val,
345
0, 0);
346
if (result == 0) {
347
return gdb_get_regl(buf, val);
348
@@ -XXX,XX +XXX,XX @@ static int riscv_gdb_set_fpu(CPURISCVState *env, uint8_t *mem_buf, int n)
349
target_ulong val = ldtul_p(mem_buf);
350
int result;
351
/*
352
- * CSR_FFLAGS is at index 8 in csr_register, and gdb says it is FP
353
+ * CSR_FFLAGS is at index 1 in csr_register, and gdb says it is FP
354
* register 33, so we recalculate the map index.
355
* This also works for CSR_FRM and CSR_FCSR.
356
*/
357
- result = riscv_csrrw_debug(env, n - 33 + csr_register_map[8], NULL,
358
+ result = riscv_csrrw_debug(env, n - 32, NULL,
359
val, -1);
360
if (result == 0) {
361
return sizeof(target_ulong);
362
@@ -XXX,XX +XXX,XX @@ static int riscv_gdb_set_fpu(CPURISCVState *env, uint8_t *mem_buf, int n)
363
364
static int riscv_gdb_get_csr(CPURISCVState *env, GByteArray *buf, int n)
365
{
366
- if (n < ARRAY_SIZE(csr_register_map)) {
367
+ if (n < CSR_TABLE_SIZE) {
368
target_ulong val = 0;
369
int result;
370
371
- result = riscv_csrrw_debug(env, csr_register_map[n], &val, 0, 0);
372
+ result = riscv_csrrw_debug(env, n, &val, 0, 0);
373
if (result == 0) {
374
return gdb_get_regl(buf, val);
375
}
376
@@ -XXX,XX +XXX,XX @@ static int riscv_gdb_get_csr(CPURISCVState *env, GByteArray *buf, int n)
377
378
static int riscv_gdb_set_csr(CPURISCVState *env, uint8_t *mem_buf, int n)
379
{
380
- if (n < ARRAY_SIZE(csr_register_map)) {
381
+ if (n < CSR_TABLE_SIZE) {
382
target_ulong val = ldtul_p(mem_buf);
383
int result;
384
385
- result = riscv_csrrw_debug(env, csr_register_map[n], NULL, val, -1);
386
+ result = riscv_csrrw_debug(env, n, NULL, val, -1);
387
if (result == 0) {
388
return sizeof(target_ulong);
389
}
390
@@ -XXX,XX +XXX,XX @@ static int riscv_gdb_set_virtual(CPURISCVState *cs, uint8_t *mem_buf, int n)
391
return 0;
392
}
393
394
+static int riscv_gen_dynamic_csr_xml(CPUState *cs, int base_reg)
395
+{
396
+ RISCVCPU *cpu = RISCV_CPU(cs);
397
+ CPURISCVState *env = &cpu->env;
398
+ GString *s = g_string_new(NULL);
399
+ riscv_csr_predicate_fn predicate;
400
+ int bitsize = riscv_cpu_is_32bit(env) ? 32 : 64;
401
+ int i;
402
+
403
+ g_string_printf(s, "<?xml version=\"1.0\"?>");
404
+ g_string_append_printf(s, "<!DOCTYPE feature SYSTEM \"gdb-target.dtd\">");
405
+ g_string_append_printf(s, "<feature name=\"org.gnu.gdb.riscv.csr\">");
406
+
407
+ for (i = 0; i < CSR_TABLE_SIZE; i++) {
408
+ predicate = csr_ops[i].predicate;
409
+ if (predicate && !predicate(env, i)) {
410
+ if (csr_ops[i].name) {
411
+ g_string_append_printf(s, "<reg name=\"%s\"", csr_ops[i].name);
412
+ } else {
413
+ g_string_append_printf(s, "<reg name=\"csr%03x\"", i);
414
+ }
415
+ g_string_append_printf(s, " bitsize=\"%d\"", bitsize);
416
+ g_string_append_printf(s, " regnum=\"%d\"/>", base_reg + i);
417
+ }
418
+ }
419
+
420
+ g_string_append_printf(s, "</feature>");
421
+
422
+ cpu->dyn_csr_xml = g_string_free(s, false);
423
+ return CSR_TABLE_SIZE;
424
+}
425
+
426
void riscv_cpu_register_gdb_regs_for_features(CPUState *cs)
427
{
428
RISCVCPU *cpu = RISCV_CPU(cs);
429
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs)
430
36, "riscv-32bit-fpu.xml", 0);
431
}
432
#if defined(TARGET_RISCV32)
433
- gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr,
434
- 240, "riscv-32bit-csr.xml", 0);
435
-
436
gdb_register_coprocessor(cs, riscv_gdb_get_virtual, riscv_gdb_set_virtual,
437
1, "riscv-32bit-virtual.xml", 0);
438
#elif defined(TARGET_RISCV64)
439
- gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr,
440
- 240, "riscv-64bit-csr.xml", 0);
441
-
442
gdb_register_coprocessor(cs, riscv_gdb_get_virtual, riscv_gdb_set_virtual,
443
1, "riscv-64bit-virtual.xml", 0);
444
#endif
445
+
446
+ gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr,
447
+ riscv_gen_dynamic_csr_xml(cs, cs->gdb_num_regs),
448
+ "riscv-csr.xml", 0);
449
}
118
}
450
--
119
--
451
2.29.2
120
2.30.1
452
121
453
122
diff view generated by jsdifflib
[PULL 01/12] hw/block: m25p80: Don't write to flash if write is disabled
[PULL 13/16] hw/block: m25p80: Support fast read for SST flashes
1
From: Bin Meng <bin.meng@windriver.com>
1
From: Bin Meng <bin.meng@windriver.com>
2
2
3
When write is disabled, the write to flash should be avoided
3
Per SST25VF016B datasheet [1], SST flash requires a dummy byte after
4
in flash_write8().
4
the address bytes. Note only SPI mode is supported by SST flashes.
5
5
6
Fixes: 82a2499011a7 ("m25p80: Initial implementation of SPI flash device")
6
[1] http://ww1.microchip.com/downloads/en/devicedoc/s71271_04.pdf
7
7
Signed-off-by: Bin Meng <bin.meng@windriver.com>
8
Signed-off-by: Bin Meng <bin.meng@windriver.com>
8
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
Acked-by: Alistair Francis <alistair.francis@wdc.com>
9
Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
10
Message-id: 20210306060152.7250-1-bmeng.cn@gmail.com
10
Message-id: 1608688825-81519-1-git-send-email-bmeng.cn@gmail.com
11
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
11
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
12
---
12
---
13
hw/block/m25p80.c | 1 +
13
hw/block/m25p80.c | 3 +++
14
1 file changed, 1 insertion(+)
14
1 file changed, 3 insertions(+)
15
15
16
diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
16
diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
17
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/block/m25p80.c
18
--- a/hw/block/m25p80.c
19
+++ b/hw/block/m25p80.c
19
+++ b/hw/block/m25p80.c
20
@@ -XXX,XX +XXX,XX @@ void flash_write8(Flash *s, uint32_t addr, uint8_t data)
20
@@ -XXX,XX +XXX,XX @@ static void decode_fast_read_cmd(Flash *s)
21
21
s->needed_bytes = get_addr_length(s);
22
if (!s->write_enable) {
22
switch (get_man(s)) {
23
qemu_log_mask(LOG_GUEST_ERROR, "M25P80: write with write protect!\n");
23
/* Dummy cycles - modeled with bytes writes instead of bits */
24
+ return;
24
+ case MAN_SST:
25
}
25
+ s->needed_bytes += 1;
26
26
+ break;
27
if ((prev ^ data) & data) {
27
case MAN_WINBOND:
28
s->needed_bytes += 8;
29
break;
28
--
30
--
29
2.29.2
31
2.30.1
30
32
31
33
diff view generated by jsdifflib
[PULL 06/12] hw/riscv: sifive_u: Use SIFIVE_U_CPU for mc->default_cpu_type
[PULL 14/16] hw/riscv: microchip_pfsoc: Map EMMC/SD mux register
1
From: Bin Meng <bin.meng@windriver.com>
1
From: Bin Meng <bin.meng@windriver.com>
2
2
3
SIFIVE_U_CPU is conditionally set to SIFIVE_U34 or SIFIVE_U54, hence
3
Since HSS commit c20a89f8dcac, the Icicle Kit reference design has
4
there is no need to use #idef to set the mc->default_cpu_type.
4
been updated to use a register mapped at 0x4f000000 instead of a
5
GPIO to control whether eMMC or SD card is to be used. With this
6
support the same HSS image can be used for both eMMC and SD card
7
boot flow, while previously two different board configurations were
8
used. This is undocumented but one can take a look at the HSS code
9
HSS_MMCInit() in services/mmc/mmc_api.c.
10
11
With this commit, HSS image built from 2020.12 release boots again.
5
12
6
Signed-off-by: Bin Meng <bin.meng@windriver.com>
13
Signed-off-by: Bin Meng <bin.meng@windriver.com>
7
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
14
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
9
Message-id: 20210109143637.29645-1-bmeng.cn@gmail.com
15
Message-id: 20210322075248.136255-1-bmeng.cn@gmail.com
10
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
16
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
11
---
17
---
12
hw/riscv/sifive_u.c | 6 +-----
18
include/hw/riscv/microchip_pfsoc.h | 1 +
13
1 file changed, 1 insertion(+), 5 deletions(-)
19
hw/riscv/microchip_pfsoc.c | 6 ++++++
20
2 files changed, 7 insertions(+)
14
21
15
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
22
diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h
16
index XXXXXXX..XXXXXXX 100644
23
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/riscv/sifive_u.c
24
--- a/include/hw/riscv/microchip_pfsoc.h
18
+++ b/hw/riscv/sifive_u.c
25
+++ b/include/hw/riscv/microchip_pfsoc.h
19
@@ -XXX,XX +XXX,XX @@ static void sifive_u_machine_class_init(ObjectClass *oc, void *data)
26
@@ -XXX,XX +XXX,XX @@ enum {
20
mc->init = sifive_u_machine_init;
27
MICROCHIP_PFSOC_ENVM_DATA,
21
mc->max_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + SIFIVE_U_COMPUTE_CPU_COUNT;
28
MICROCHIP_PFSOC_QSPI_XIP,
22
mc->min_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + 1;
29
MICROCHIP_PFSOC_IOSCB,
23
-#if defined(TARGET_RISCV32)
30
+ MICROCHIP_PFSOC_EMMC_SD_MUX,
24
- mc->default_cpu_type = TYPE_RISCV_CPU_SIFIVE_U34;
31
MICROCHIP_PFSOC_DRAM_LO,
25
-#elif defined(TARGET_RISCV64)
32
MICROCHIP_PFSOC_DRAM_LO_ALIAS,
26
- mc->default_cpu_type = TYPE_RISCV_CPU_SIFIVE_U54;
33
MICROCHIP_PFSOC_DRAM_HI,
27
-#endif
34
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
28
+ mc->default_cpu_type = SIFIVE_U_CPU;
35
index XXXXXXX..XXXXXXX 100644
29
mc->default_cpus = mc->min_cpus;
36
--- a/hw/riscv/microchip_pfsoc.c
30
37
+++ b/hw/riscv/microchip_pfsoc.c
31
object_class_property_add_bool(oc, "start-in-flash",
38
@@ -XXX,XX +XXX,XX @@ static const MemMapEntry microchip_pfsoc_memmap[] = {
39
[MICROCHIP_PFSOC_ENVM_DATA] = { 0x20220000, 0x20000 },
40
[MICROCHIP_PFSOC_QSPI_XIP] = { 0x21000000, 0x1000000 },
41
[MICROCHIP_PFSOC_IOSCB] = { 0x30000000, 0x10000000 },
42
+ [MICROCHIP_PFSOC_EMMC_SD_MUX] = { 0x4f000000, 0x4 },
43
[MICROCHIP_PFSOC_DRAM_LO] = { 0x80000000, 0x40000000 },
44
[MICROCHIP_PFSOC_DRAM_LO_ALIAS] = { 0xc0000000, 0x40000000 },
45
[MICROCHIP_PFSOC_DRAM_HI] = { 0x1000000000, 0x0 },
46
@@ -XXX,XX +XXX,XX @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
47
sysbus_mmio_map(SYS_BUS_DEVICE(&s->ioscb), 0,
48
memmap[MICROCHIP_PFSOC_IOSCB].base);
49
50
+ /* eMMC/SD mux */
51
+ create_unimplemented_device("microchip.pfsoc.emmc_sd_mux",
52
+ memmap[MICROCHIP_PFSOC_EMMC_SD_MUX].base,
53
+ memmap[MICROCHIP_PFSOC_EMMC_SD_MUX].size);
54
+
55
/* QSPI Flash */
56
memory_region_init_rom(qspi_xip_mem, OBJECT(dev),
57
"microchip.pfsoc.qspi_xip",
32
--
58
--
33
2.29.2
59
2.30.1
34
60
35
61
diff view generated by jsdifflib
[PULL 11/12] target/riscv: Remove built-in GDB XML files for CSRs
[PULL 15/16] docs/system: riscv: Add documentation for 'microchip-icicle-kit' machine
1
From: Bin Meng <bin.meng@windriver.com>
1
From: Bin Meng <bin.meng@windriver.com>
2
2
3
Now that we have switched to generate the RISC-V CSR XML dynamically,
3
This adds the documentation to describe what is supported for the
4
remove the built-in hardcoded XML files.
4
'microchip-icicle-kit' machine, and how to boot the machine in QEMU.
5
5
6
Signed-off-by: Bin Meng <bin.meng@windriver.com>
6
Signed-off-by: Bin Meng <bin.meng@windriver.com>
7
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
7
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
8
Message-id: 20210116054123.5457-3-bmeng.cn@gmail.com
8
Message-id: 20210322075248.136255-2-bmeng.cn@gmail.com
9
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
9
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
10
---
10
---
11
.../targets/riscv32-linux-user.mak | 2 +-
11
docs/system/riscv/microchip-icicle-kit.rst | 89 ++++++++++++++++++++++
12
default-configs/targets/riscv32-softmmu.mak | 2 +-
12
docs/system/target-riscv.rst | 1 +
13
.../targets/riscv64-linux-user.mak | 2 +-
13
2 files changed, 90 insertions(+)
14
default-configs/targets/riscv64-softmmu.mak | 2 +-
14
create mode 100644 docs/system/riscv/microchip-icicle-kit.rst
15
gdb-xml/riscv-32bit-csr.xml | 250 ------------------
16
gdb-xml/riscv-64bit-csr.xml | 250 ------------------
17
6 files changed, 4 insertions(+), 504 deletions(-)
18
delete mode 100644 gdb-xml/riscv-32bit-csr.xml
19
delete mode 100644 gdb-xml/riscv-64bit-csr.xml
20
15
21
diff --git a/default-configs/targets/riscv32-linux-user.mak b/default-configs/targets/riscv32-linux-user.mak
16
diff --git a/docs/system/riscv/microchip-icicle-kit.rst b/docs/system/riscv/microchip-icicle-kit.rst
17
new file mode 100644
18
index XXXXXXX..XXXXXXX
19
--- /dev/null
20
+++ b/docs/system/riscv/microchip-icicle-kit.rst
21
@@ -XXX,XX +XXX,XX @@
22
+Microchip PolarFire SoC Icicle Kit (``microchip-icicle-kit``)
23
+=============================================================
24
+
25
+Microchip PolarFire SoC Icicle Kit integrates a PolarFire SoC, with one
26
+SiFive's E51 plus four U54 cores and many on-chip peripherals and an FPGA.
27
+
28
+For more details about Microchip PolarFire SoC, please see:
29
+https://www.microsemi.com/product-directory/soc-fpgas/5498-polarfire-soc-fpga
30
+
31
+The Icicle Kit board information can be found here:
32
+https://www.microsemi.com/existing-parts/parts/152514
33
+
34
+Supported devices
35
+-----------------
36
+
37
+The ``microchip-icicle-kit`` machine supports the following devices:
38
+
39
+ * 1 E51 core
40
+ * 4 U54 cores
41
+ * Core Level Interruptor (CLINT)
42
+ * Platform-Level Interrupt Controller (PLIC)
43
+ * L2 Loosely Integrated Memory (L2-LIM)
44
+ * DDR memory controller
45
+ * 5 MMUARTs
46
+ * 1 DMA controller
47
+ * 2 GEM Ethernet controllers
48
+ * 1 SDHC storage controller
49
+
50
+Boot options
51
+------------
52
+
53
+The ``microchip-icicle-kit`` machine can start using the standard -bios
54
+functionality for loading its BIOS image, aka Hart Software Services (HSS_).
55
+HSS loads the second stage bootloader U-Boot from an SD card. It does not
56
+support direct kernel loading via the -kernel option. One has to load kernel
57
+from U-Boot.
58
+
59
+The memory is set to 1537 MiB by default which is the minimum required high
60
+memory size by HSS. A sanity check on ram size is performed in the machine
61
+init routine to prompt user to increase the RAM size to > 1537 MiB when less
62
+than 1537 MiB ram is detected.
63
+
64
+Boot the machine
65
+----------------
66
+
67
+HSS 2020.12 release is tested at the time of writing. To build an HSS image
68
+that can be booted by the ``microchip-icicle-kit`` machine, type the following
69
+in the HSS source tree:
70
+
71
+.. code-block:: bash
72
+
73
+ $ export CROSS_COMPILE=riscv64-linux-
74
+ $ cp boards/mpfs-icicle-kit-es/def_config .config
75
+ $ make BOARD=mpfs-icicle-kit-es
76
+
77
+Download the official SD card image released by Microchip and prepare it for
78
+QEMU usage:
79
+
80
+.. code-block:: bash
81
+
82
+ $ wget ftp://ftpsoc.microsemi.com/outgoing/core-image-minimal-dev-icicle-kit-es-sd-20201009141623.rootfs.wic.gz
83
+ $ gunzip core-image-minimal-dev-icicle-kit-es-sd-20201009141623.rootfs.wic.gz
84
+ $ qemu-img resize core-image-minimal-dev-icicle-kit-es-sd-20201009141623.rootfs.wic 4G
85
+
86
+Then we can boot the machine by:
87
+
88
+.. code-block:: bash
89
+
90
+ $ qemu-system-riscv64 -M microchip-icicle-kit -smp 5 \
91
+ -bios path/to/hss.bin -sd path/to/sdcard.img \
92
+ -nic user,model=cadence_gem \
93
+ -nic tap,ifname=tap,model=cadence_gem,script=no \
94
+ -display none -serial stdio \
95
+ -chardev socket,id=serial1,path=serial1.sock,server=on,wait=on \
96
+ -serial chardev:serial1
97
+
98
+With above command line, current terminal session will be used for the first
99
+serial port. Open another terminal window, and use `minicom` to connect the
100
+second serial port.
101
+
102
+.. code-block:: bash
103
+
104
+ $ minicom -D unix\#serial1.sock
105
+
106
+HSS output is on the first serial port (stdio) and U-Boot outputs on the
107
+second serial port. U-Boot will automatically load the Linux kernel from
108
+the SD card image.
109
+
110
+.. _HSS: https://github.com/polarfire-soc/hart-software-services
111
diff --git a/docs/system/target-riscv.rst b/docs/system/target-riscv.rst
22
index XXXXXXX..XXXXXXX 100644
112
index XXXXXXX..XXXXXXX 100644
23
--- a/default-configs/targets/riscv32-linux-user.mak
113
--- a/docs/system/target-riscv.rst
24
+++ b/default-configs/targets/riscv32-linux-user.mak
114
+++ b/docs/system/target-riscv.rst
25
@@ -XXX,XX +XXX,XX @@
115
@@ -XXX,XX +XXX,XX @@ undocumented; you can get a complete list by running
26
TARGET_ARCH=riscv32
116
.. toctree::
27
TARGET_BASE_ARCH=riscv
117
:maxdepth: 1
28
TARGET_ABI_DIR=riscv
118
29
-TARGET_XML_FILES= gdb-xml/riscv-32bit-cpu.xml gdb-xml/riscv-32bit-fpu.xml gdb-xml/riscv-64bit-fpu.xml gdb-xml/riscv-32bit-csr.xml gdb-xml/riscv-32bit-virtual.xml
119
+ riscv/microchip-icicle-kit
30
+TARGET_XML_FILES= gdb-xml/riscv-32bit-cpu.xml gdb-xml/riscv-32bit-fpu.xml gdb-xml/riscv-64bit-fpu.xml gdb-xml/riscv-32bit-virtual.xml
120
riscv/sifive_u
31
diff --git a/default-configs/targets/riscv32-softmmu.mak b/default-configs/targets/riscv32-softmmu.mak
121
32
index XXXXXXX..XXXXXXX 100644
122
RISC-V CPU features
33
--- a/default-configs/targets/riscv32-softmmu.mak
34
+++ b/default-configs/targets/riscv32-softmmu.mak
35
@@ -XXX,XX +XXX,XX @@
36
TARGET_ARCH=riscv32
37
TARGET_BASE_ARCH=riscv
38
TARGET_SUPPORTS_MTTCG=y
39
-TARGET_XML_FILES= gdb-xml/riscv-32bit-cpu.xml gdb-xml/riscv-32bit-fpu.xml gdb-xml/riscv-64bit-fpu.xml gdb-xml/riscv-32bit-csr.xml gdb-xml/riscv-32bit-virtual.xml
40
+TARGET_XML_FILES= gdb-xml/riscv-32bit-cpu.xml gdb-xml/riscv-32bit-fpu.xml gdb-xml/riscv-64bit-fpu.xml gdb-xml/riscv-32bit-virtual.xml
41
TARGET_NEED_FDT=y
42
diff --git a/default-configs/targets/riscv64-linux-user.mak b/default-configs/targets/riscv64-linux-user.mak
43
index XXXXXXX..XXXXXXX 100644
44
--- a/default-configs/targets/riscv64-linux-user.mak
45
+++ b/default-configs/targets/riscv64-linux-user.mak
46
@@ -XXX,XX +XXX,XX @@
47
TARGET_ARCH=riscv64
48
TARGET_BASE_ARCH=riscv
49
TARGET_ABI_DIR=riscv
50
-TARGET_XML_FILES= gdb-xml/riscv-64bit-cpu.xml gdb-xml/riscv-32bit-fpu.xml gdb-xml/riscv-64bit-fpu.xml gdb-xml/riscv-64bit-csr.xml gdb-xml/riscv-64bit-virtual.xml
51
+TARGET_XML_FILES= gdb-xml/riscv-64bit-cpu.xml gdb-xml/riscv-32bit-fpu.xml gdb-xml/riscv-64bit-fpu.xml gdb-xml/riscv-64bit-virtual.xml
52
diff --git a/default-configs/targets/riscv64-softmmu.mak b/default-configs/targets/riscv64-softmmu.mak
53
index XXXXXXX..XXXXXXX 100644
54
--- a/default-configs/targets/riscv64-softmmu.mak
55
+++ b/default-configs/targets/riscv64-softmmu.mak
56
@@ -XXX,XX +XXX,XX @@
57
TARGET_ARCH=riscv64
58
TARGET_BASE_ARCH=riscv
59
TARGET_SUPPORTS_MTTCG=y
60
-TARGET_XML_FILES= gdb-xml/riscv-64bit-cpu.xml gdb-xml/riscv-32bit-fpu.xml gdb-xml/riscv-64bit-fpu.xml gdb-xml/riscv-64bit-csr.xml gdb-xml/riscv-64bit-virtual.xml
61
+TARGET_XML_FILES= gdb-xml/riscv-64bit-cpu.xml gdb-xml/riscv-32bit-fpu.xml gdb-xml/riscv-64bit-fpu.xml gdb-xml/riscv-64bit-virtual.xml
62
TARGET_NEED_FDT=y
63
diff --git a/gdb-xml/riscv-32bit-csr.xml b/gdb-xml/riscv-32bit-csr.xml
64
deleted file mode 100644
65
index XXXXXXX..XXXXXXX
66
--- a/gdb-xml/riscv-32bit-csr.xml
67
+++ /dev/null
68
@@ -XXX,XX +XXX,XX @@
69
-<?xml version="1.0"?>
70
-<!-- Copyright (C) 2018-2019 Free Software Foundation, Inc.
71
-
72
- Copying and distribution of this file, with or without modification,
73
- are permitted in any medium without royalty provided the copyright
74
- notice and this notice are preserved. -->
75
-
76
-<!DOCTYPE feature SYSTEM "gdb-target.dtd">
77
-<feature name="org.gnu.gdb.riscv.csr">
78
- <reg name="ustatus" bitsize="32"/>
79
- <reg name="uie" bitsize="32"/>
80
- <reg name="utvec" bitsize="32"/>
81
- <reg name="uscratch" bitsize="32"/>
82
- <reg name="uepc" bitsize="32"/>
83
- <reg name="ucause" bitsize="32"/>
84
- <reg name="utval" bitsize="32"/>
85
- <reg name="uip" bitsize="32"/>
86
- <reg name="fflags" bitsize="32"/>
87
- <reg name="frm" bitsize="32"/>
88
- <reg name="fcsr" bitsize="32"/>
89
- <reg name="cycle" bitsize="32"/>
90
- <reg name="time" bitsize="32"/>
91
- <reg name="instret" bitsize="32"/>
92
- <reg name="hpmcounter3" bitsize="32"/>
93
- <reg name="hpmcounter4" bitsize="32"/>
94
- <reg name="hpmcounter5" bitsize="32"/>
95
- <reg name="hpmcounter6" bitsize="32"/>
96
- <reg name="hpmcounter7" bitsize="32"/>
97
- <reg name="hpmcounter8" bitsize="32"/>
98
- <reg name="hpmcounter9" bitsize="32"/>
99
- <reg name="hpmcounter10" bitsize="32"/>
100
- <reg name="hpmcounter11" bitsize="32"/>
101
- <reg name="hpmcounter12" bitsize="32"/>
102
- <reg name="hpmcounter13" bitsize="32"/>
103
- <reg name="hpmcounter14" bitsize="32"/>
104
- <reg name="hpmcounter15" bitsize="32"/>
105
- <reg name="hpmcounter16" bitsize="32"/>
106
- <reg name="hpmcounter17" bitsize="32"/>
107
- <reg name="hpmcounter18" bitsize="32"/>
108
- <reg name="hpmcounter19" bitsize="32"/>
109
- <reg name="hpmcounter20" bitsize="32"/>
110
- <reg name="hpmcounter21" bitsize="32"/>
111
- <reg name="hpmcounter22" bitsize="32"/>
112
- <reg name="hpmcounter23" bitsize="32"/>
113
- <reg name="hpmcounter24" bitsize="32"/>
114
- <reg name="hpmcounter25" bitsize="32"/>
115
- <reg name="hpmcounter26" bitsize="32"/>
116
- <reg name="hpmcounter27" bitsize="32"/>
117
- <reg name="hpmcounter28" bitsize="32"/>
118
- <reg name="hpmcounter29" bitsize="32"/>
119
- <reg name="hpmcounter30" bitsize="32"/>
120
- <reg name="hpmcounter31" bitsize="32"/>
121
- <reg name="cycleh" bitsize="32"/>
122
- <reg name="timeh" bitsize="32"/>
123
- <reg name="instreth" bitsize="32"/>
124
- <reg name="hpmcounter3h" bitsize="32"/>
125
- <reg name="hpmcounter4h" bitsize="32"/>
126
- <reg name="hpmcounter5h" bitsize="32"/>
127
- <reg name="hpmcounter6h" bitsize="32"/>
128
- <reg name="hpmcounter7h" bitsize="32"/>
129
- <reg name="hpmcounter8h" bitsize="32"/>
130
- <reg name="hpmcounter9h" bitsize="32"/>
131
- <reg name="hpmcounter10h" bitsize="32"/>
132
- <reg name="hpmcounter11h" bitsize="32"/>
133
- <reg name="hpmcounter12h" bitsize="32"/>
134
- <reg name="hpmcounter13h" bitsize="32"/>
135
- <reg name="hpmcounter14h" bitsize="32"/>
136
- <reg name="hpmcounter15h" bitsize="32"/>
137
- <reg name="hpmcounter16h" bitsize="32"/>
138
- <reg name="hpmcounter17h" bitsize="32"/>
139
- <reg name="hpmcounter18h" bitsize="32"/>
140
- <reg name="hpmcounter19h" bitsize="32"/>
141
- <reg name="hpmcounter20h" bitsize="32"/>
142
- <reg name="hpmcounter21h" bitsize="32"/>
143
- <reg name="hpmcounter22h" bitsize="32"/>
144
- <reg name="hpmcounter23h" bitsize="32"/>
145
- <reg name="hpmcounter24h" bitsize="32"/>
146
- <reg name="hpmcounter25h" bitsize="32"/>
147
- <reg name="hpmcounter26h" bitsize="32"/>
148
- <reg name="hpmcounter27h" bitsize="32"/>
149
- <reg name="hpmcounter28h" bitsize="32"/>
150
- <reg name="hpmcounter29h" bitsize="32"/>
151
- <reg name="hpmcounter30h" bitsize="32"/>
152
- <reg name="hpmcounter31h" bitsize="32"/>
153
- <reg name="sstatus" bitsize="32"/>
154
- <reg name="sedeleg" bitsize="32"/>
155
- <reg name="sideleg" bitsize="32"/>
156
- <reg name="sie" bitsize="32"/>
157
- <reg name="stvec" bitsize="32"/>
158
- <reg name="scounteren" bitsize="32"/>
159
- <reg name="sscratch" bitsize="32"/>
160
- <reg name="sepc" bitsize="32"/>
161
- <reg name="scause" bitsize="32"/>
162
- <reg name="stval" bitsize="32"/>
163
- <reg name="sip" bitsize="32"/>
164
- <reg name="satp" bitsize="32"/>
165
- <reg name="mvendorid" bitsize="32"/>
166
- <reg name="marchid" bitsize="32"/>
167
- <reg name="mimpid" bitsize="32"/>
168
- <reg name="mhartid" bitsize="32"/>
169
- <reg name="mstatus" bitsize="32"/>
170
- <reg name="misa" bitsize="32"/>
171
- <reg name="medeleg" bitsize="32"/>
172
- <reg name="mideleg" bitsize="32"/>
173
- <reg name="mie" bitsize="32"/>
174
- <reg name="mtvec" bitsize="32"/>
175
- <reg name="mcounteren" bitsize="32"/>
176
- <reg name="mscratch" bitsize="32"/>
177
- <reg name="mepc" bitsize="32"/>
178
- <reg name="mcause" bitsize="32"/>
179
- <reg name="mtval" bitsize="32"/>
180
- <reg name="mip" bitsize="32"/>
181
- <reg name="pmpcfg0" bitsize="32"/>
182
- <reg name="pmpcfg1" bitsize="32"/>
183
- <reg name="pmpcfg2" bitsize="32"/>
184
- <reg name="pmpcfg3" bitsize="32"/>
185
- <reg name="pmpaddr0" bitsize="32"/>
186
- <reg name="pmpaddr1" bitsize="32"/>
187
- <reg name="pmpaddr2" bitsize="32"/>
188
- <reg name="pmpaddr3" bitsize="32"/>
189
- <reg name="pmpaddr4" bitsize="32"/>
190
- <reg name="pmpaddr5" bitsize="32"/>
191
- <reg name="pmpaddr6" bitsize="32"/>
192
- <reg name="pmpaddr7" bitsize="32"/>
193
- <reg name="pmpaddr8" bitsize="32"/>
194
- <reg name="pmpaddr9" bitsize="32"/>
195
- <reg name="pmpaddr10" bitsize="32"/>
196
- <reg name="pmpaddr11" bitsize="32"/>
197
- <reg name="pmpaddr12" bitsize="32"/>
198
- <reg name="pmpaddr13" bitsize="32"/>
199
- <reg name="pmpaddr14" bitsize="32"/>
200
- <reg name="pmpaddr15" bitsize="32"/>
201
- <reg name="mcycle" bitsize="32"/>
202
- <reg name="minstret" bitsize="32"/>
203
- <reg name="mhpmcounter3" bitsize="32"/>
204
- <reg name="mhpmcounter4" bitsize="32"/>
205
- <reg name="mhpmcounter5" bitsize="32"/>
206
- <reg name="mhpmcounter6" bitsize="32"/>
207
- <reg name="mhpmcounter7" bitsize="32"/>
208
- <reg name="mhpmcounter8" bitsize="32"/>
209
- <reg name="mhpmcounter9" bitsize="32"/>
210
- <reg name="mhpmcounter10" bitsize="32"/>
211
- <reg name="mhpmcounter11" bitsize="32"/>
212
- <reg name="mhpmcounter12" bitsize="32"/>
213
- <reg name="mhpmcounter13" bitsize="32"/>
214
- <reg name="mhpmcounter14" bitsize="32"/>
215
- <reg name="mhpmcounter15" bitsize="32"/>
216
- <reg name="mhpmcounter16" bitsize="32"/>
217
- <reg name="mhpmcounter17" bitsize="32"/>
218
- <reg name="mhpmcounter18" bitsize="32"/>
219
- <reg name="mhpmcounter19" bitsize="32"/>
220
- <reg name="mhpmcounter20" bitsize="32"/>
221
- <reg name="mhpmcounter21" bitsize="32"/>
222
- <reg name="mhpmcounter22" bitsize="32"/>
223
- <reg name="mhpmcounter23" bitsize="32"/>
224
- <reg name="mhpmcounter24" bitsize="32"/>
225
- <reg name="mhpmcounter25" bitsize="32"/>
226
- <reg name="mhpmcounter26" bitsize="32"/>
227
- <reg name="mhpmcounter27" bitsize="32"/>
228
- <reg name="mhpmcounter28" bitsize="32"/>
229
- <reg name="mhpmcounter29" bitsize="32"/>
230
- <reg name="mhpmcounter30" bitsize="32"/>
231
- <reg name="mhpmcounter31" bitsize="32"/>
232
- <reg name="mcycleh" bitsize="32"/>
233
- <reg name="minstreth" bitsize="32"/>
234
- <reg name="mhpmcounter3h" bitsize="32"/>
235
- <reg name="mhpmcounter4h" bitsize="32"/>
236
- <reg name="mhpmcounter5h" bitsize="32"/>
237
- <reg name="mhpmcounter6h" bitsize="32"/>
238
- <reg name="mhpmcounter7h" bitsize="32"/>
239
- <reg name="mhpmcounter8h" bitsize="32"/>
240
- <reg name="mhpmcounter9h" bitsize="32"/>
241
- <reg name="mhpmcounter10h" bitsize="32"/>
242
- <reg name="mhpmcounter11h" bitsize="32"/>
243
- <reg name="mhpmcounter12h" bitsize="32"/>
244
- <reg name="mhpmcounter13h" bitsize="32"/>
245
- <reg name="mhpmcounter14h" bitsize="32"/>
246
- <reg name="mhpmcounter15h" bitsize="32"/>
247
- <reg name="mhpmcounter16h" bitsize="32"/>
248
- <reg name="mhpmcounter17h" bitsize="32"/>
249
- <reg name="mhpmcounter18h" bitsize="32"/>
250
- <reg name="mhpmcounter19h" bitsize="32"/>
251
- <reg name="mhpmcounter20h" bitsize="32"/>
252
- <reg name="mhpmcounter21h" bitsize="32"/>
253
- <reg name="mhpmcounter22h" bitsize="32"/>
254
- <reg name="mhpmcounter23h" bitsize="32"/>
255
- <reg name="mhpmcounter24h" bitsize="32"/>
256
- <reg name="mhpmcounter25h" bitsize="32"/>
257
- <reg name="mhpmcounter26h" bitsize="32"/>
258
- <reg name="mhpmcounter27h" bitsize="32"/>
259
- <reg name="mhpmcounter28h" bitsize="32"/>
260
- <reg name="mhpmcounter29h" bitsize="32"/>
261
- <reg name="mhpmcounter30h" bitsize="32"/>
262
- <reg name="mhpmcounter31h" bitsize="32"/>
263
- <reg name="mhpmevent3" bitsize="32"/>
264
- <reg name="mhpmevent4" bitsize="32"/>
265
- <reg name="mhpmevent5" bitsize="32"/>
266
- <reg name="mhpmevent6" bitsize="32"/>
267
- <reg name="mhpmevent7" bitsize="32"/>
268
- <reg name="mhpmevent8" bitsize="32"/>
269
- <reg name="mhpmevent9" bitsize="32"/>
270
- <reg name="mhpmevent10" bitsize="32"/>
271
- <reg name="mhpmevent11" bitsize="32"/>
272
- <reg name="mhpmevent12" bitsize="32"/>
273
- <reg name="mhpmevent13" bitsize="32"/>
274
- <reg name="mhpmevent14" bitsize="32"/>
275
- <reg name="mhpmevent15" bitsize="32"/>
276
- <reg name="mhpmevent16" bitsize="32"/>
277
- <reg name="mhpmevent17" bitsize="32"/>
278
- <reg name="mhpmevent18" bitsize="32"/>
279
- <reg name="mhpmevent19" bitsize="32"/>
280
- <reg name="mhpmevent20" bitsize="32"/>
281
- <reg name="mhpmevent21" bitsize="32"/>
282
- <reg name="mhpmevent22" bitsize="32"/>
283
- <reg name="mhpmevent23" bitsize="32"/>
284
- <reg name="mhpmevent24" bitsize="32"/>
285
- <reg name="mhpmevent25" bitsize="32"/>
286
- <reg name="mhpmevent26" bitsize="32"/>
287
- <reg name="mhpmevent27" bitsize="32"/>
288
- <reg name="mhpmevent28" bitsize="32"/>
289
- <reg name="mhpmevent29" bitsize="32"/>
290
- <reg name="mhpmevent30" bitsize="32"/>
291
- <reg name="mhpmevent31" bitsize="32"/>
292
- <reg name="tselect" bitsize="32"/>
293
- <reg name="tdata1" bitsize="32"/>
294
- <reg name="tdata2" bitsize="32"/>
295
- <reg name="tdata3" bitsize="32"/>
296
- <reg name="dcsr" bitsize="32"/>
297
- <reg name="dpc" bitsize="32"/>
298
- <reg name="dscratch" bitsize="32"/>
299
- <reg name="hstatus" bitsize="32"/>
300
- <reg name="hedeleg" bitsize="32"/>
301
- <reg name="hideleg" bitsize="32"/>
302
- <reg name="hie" bitsize="32"/>
303
- <reg name="htvec" bitsize="32"/>
304
- <reg name="hscratch" bitsize="32"/>
305
- <reg name="hepc" bitsize="32"/>
306
- <reg name="hcause" bitsize="32"/>
307
- <reg name="hbadaddr" bitsize="32"/>
308
- <reg name="hip" bitsize="32"/>
309
- <reg name="mbase" bitsize="32"/>
310
- <reg name="mbound" bitsize="32"/>
311
- <reg name="mibase" bitsize="32"/>
312
- <reg name="mibound" bitsize="32"/>
313
- <reg name="mdbase" bitsize="32"/>
314
- <reg name="mdbound" bitsize="32"/>
315
- <reg name="mucounteren" bitsize="32"/>
316
- <reg name="mscounteren" bitsize="32"/>
317
- <reg name="mhcounteren" bitsize="32"/>
318
-</feature>
319
diff --git a/gdb-xml/riscv-64bit-csr.xml b/gdb-xml/riscv-64bit-csr.xml
320
deleted file mode 100644
321
index XXXXXXX..XXXXXXX
322
--- a/gdb-xml/riscv-64bit-csr.xml
323
+++ /dev/null
324
@@ -XXX,XX +XXX,XX @@
325
-<?xml version="1.0"?>
326
-<!-- Copyright (C) 2018-2019 Free Software Foundation, Inc.
327
-
328
- Copying and distribution of this file, with or without modification,
329
- are permitted in any medium without royalty provided the copyright
330
- notice and this notice are preserved. -->
331
-
332
-<!DOCTYPE feature SYSTEM "gdb-target.dtd">
333
-<feature name="org.gnu.gdb.riscv.csr">
334
- <reg name="ustatus" bitsize="64"/>
335
- <reg name="uie" bitsize="64"/>
336
- <reg name="utvec" bitsize="64"/>
337
- <reg name="uscratch" bitsize="64"/>
338
- <reg name="uepc" bitsize="64"/>
339
- <reg name="ucause" bitsize="64"/>
340
- <reg name="utval" bitsize="64"/>
341
- <reg name="uip" bitsize="64"/>
342
- <reg name="fflags" bitsize="64"/>
343
- <reg name="frm" bitsize="64"/>
344
- <reg name="fcsr" bitsize="64"/>
345
- <reg name="cycle" bitsize="64"/>
346
- <reg name="time" bitsize="64"/>
347
- <reg name="instret" bitsize="64"/>
348
- <reg name="hpmcounter3" bitsize="64"/>
349
- <reg name="hpmcounter4" bitsize="64"/>
350
- <reg name="hpmcounter5" bitsize="64"/>
351
- <reg name="hpmcounter6" bitsize="64"/>
352
- <reg name="hpmcounter7" bitsize="64"/>
353
- <reg name="hpmcounter8" bitsize="64"/>
354
- <reg name="hpmcounter9" bitsize="64"/>
355
- <reg name="hpmcounter10" bitsize="64"/>
356
- <reg name="hpmcounter11" bitsize="64"/>
357
- <reg name="hpmcounter12" bitsize="64"/>
358
- <reg name="hpmcounter13" bitsize="64"/>
359
- <reg name="hpmcounter14" bitsize="64"/>
360
- <reg name="hpmcounter15" bitsize="64"/>
361
- <reg name="hpmcounter16" bitsize="64"/>
362
- <reg name="hpmcounter17" bitsize="64"/>
363
- <reg name="hpmcounter18" bitsize="64"/>
364
- <reg name="hpmcounter19" bitsize="64"/>
365
- <reg name="hpmcounter20" bitsize="64"/>
366
- <reg name="hpmcounter21" bitsize="64"/>
367
- <reg name="hpmcounter22" bitsize="64"/>
368
- <reg name="hpmcounter23" bitsize="64"/>
369
- <reg name="hpmcounter24" bitsize="64"/>
370
- <reg name="hpmcounter25" bitsize="64"/>
371
- <reg name="hpmcounter26" bitsize="64"/>
372
- <reg name="hpmcounter27" bitsize="64"/>
373
- <reg name="hpmcounter28" bitsize="64"/>
374
- <reg name="hpmcounter29" bitsize="64"/>
375
- <reg name="hpmcounter30" bitsize="64"/>
376
- <reg name="hpmcounter31" bitsize="64"/>
377
- <reg name="cycleh" bitsize="64"/>
378
- <reg name="timeh" bitsize="64"/>
379
- <reg name="instreth" bitsize="64"/>
380
- <reg name="hpmcounter3h" bitsize="64"/>
381
- <reg name="hpmcounter4h" bitsize="64"/>
382
- <reg name="hpmcounter5h" bitsize="64"/>
383
- <reg name="hpmcounter6h" bitsize="64"/>
384
- <reg name="hpmcounter7h" bitsize="64"/>
385
- <reg name="hpmcounter8h" bitsize="64"/>
386
- <reg name="hpmcounter9h" bitsize="64"/>
387
- <reg name="hpmcounter10h" bitsize="64"/>
388
- <reg name="hpmcounter11h" bitsize="64"/>
389
- <reg name="hpmcounter12h" bitsize="64"/>
390
- <reg name="hpmcounter13h" bitsize="64"/>
391
- <reg name="hpmcounter14h" bitsize="64"/>
392
- <reg name="hpmcounter15h" bitsize="64"/>
393
- <reg name="hpmcounter16h" bitsize="64"/>
394
- <reg name="hpmcounter17h" bitsize="64"/>
395
- <reg name="hpmcounter18h" bitsize="64"/>
396
- <reg name="hpmcounter19h" bitsize="64"/>
397
- <reg name="hpmcounter20h" bitsize="64"/>
398
- <reg name="hpmcounter21h" bitsize="64"/>
399
- <reg name="hpmcounter22h" bitsize="64"/>
400
- <reg name="hpmcounter23h" bitsize="64"/>
401
- <reg name="hpmcounter24h" bitsize="64"/>
402
- <reg name="hpmcounter25h" bitsize="64"/>
403
- <reg name="hpmcounter26h" bitsize="64"/>
404
- <reg name="hpmcounter27h" bitsize="64"/>
405
- <reg name="hpmcounter28h" bitsize="64"/>
406
- <reg name="hpmcounter29h" bitsize="64"/>
407
- <reg name="hpmcounter30h" bitsize="64"/>
408
- <reg name="hpmcounter31h" bitsize="64"/>
409
- <reg name="sstatus" bitsize="64"/>
410
- <reg name="sedeleg" bitsize="64"/>
411
- <reg name="sideleg" bitsize="64"/>
412
- <reg name="sie" bitsize="64"/>
413
- <reg name="stvec" bitsize="64"/>
414
- <reg name="scounteren" bitsize="64"/>
415
- <reg name="sscratch" bitsize="64"/>
416
- <reg name="sepc" bitsize="64"/>
417
- <reg name="scause" bitsize="64"/>
418
- <reg name="stval" bitsize="64"/>
419
- <reg name="sip" bitsize="64"/>
420
- <reg name="satp" bitsize="64"/>
421
- <reg name="mvendorid" bitsize="64"/>
422
- <reg name="marchid" bitsize="64"/>
423
- <reg name="mimpid" bitsize="64"/>
424
- <reg name="mhartid" bitsize="64"/>
425
- <reg name="mstatus" bitsize="64"/>
426
- <reg name="misa" bitsize="64"/>
427
- <reg name="medeleg" bitsize="64"/>
428
- <reg name="mideleg" bitsize="64"/>
429
- <reg name="mie" bitsize="64"/>
430
- <reg name="mtvec" bitsize="64"/>
431
- <reg name="mcounteren" bitsize="64"/>
432
- <reg name="mscratch" bitsize="64"/>
433
- <reg name="mepc" bitsize="64"/>
434
- <reg name="mcause" bitsize="64"/>
435
- <reg name="mtval" bitsize="64"/>
436
- <reg name="mip" bitsize="64"/>
437
- <reg name="pmpcfg0" bitsize="64"/>
438
- <reg name="pmpcfg1" bitsize="64"/>
439
- <reg name="pmpcfg2" bitsize="64"/>
440
- <reg name="pmpcfg3" bitsize="64"/>
441
- <reg name="pmpaddr0" bitsize="64"/>
442
- <reg name="pmpaddr1" bitsize="64"/>
443
- <reg name="pmpaddr2" bitsize="64"/>
444
- <reg name="pmpaddr3" bitsize="64"/>
445
- <reg name="pmpaddr4" bitsize="64"/>
446
- <reg name="pmpaddr5" bitsize="64"/>
447
- <reg name="pmpaddr6" bitsize="64"/>
448
- <reg name="pmpaddr7" bitsize="64"/>
449
- <reg name="pmpaddr8" bitsize="64"/>
450
- <reg name="pmpaddr9" bitsize="64"/>
451
- <reg name="pmpaddr10" bitsize="64"/>
452
- <reg name="pmpaddr11" bitsize="64"/>
453
- <reg name="pmpaddr12" bitsize="64"/>
454
- <reg name="pmpaddr13" bitsize="64"/>
455
- <reg name="pmpaddr14" bitsize="64"/>
456
- <reg name="pmpaddr15" bitsize="64"/>
457
- <reg name="mcycle" bitsize="64"/>
458
- <reg name="minstret" bitsize="64"/>
459
- <reg name="mhpmcounter3" bitsize="64"/>
460
- <reg name="mhpmcounter4" bitsize="64"/>
461
- <reg name="mhpmcounter5" bitsize="64"/>
462
- <reg name="mhpmcounter6" bitsize="64"/>
463
- <reg name="mhpmcounter7" bitsize="64"/>
464
- <reg name="mhpmcounter8" bitsize="64"/>
465
- <reg name="mhpmcounter9" bitsize="64"/>
466
- <reg name="mhpmcounter10" bitsize="64"/>
467
- <reg name="mhpmcounter11" bitsize="64"/>
468
- <reg name="mhpmcounter12" bitsize="64"/>
469
- <reg name="mhpmcounter13" bitsize="64"/>
470
- <reg name="mhpmcounter14" bitsize="64"/>
471
- <reg name="mhpmcounter15" bitsize="64"/>
472
- <reg name="mhpmcounter16" bitsize="64"/>
473
- <reg name="mhpmcounter17" bitsize="64"/>
474
- <reg name="mhpmcounter18" bitsize="64"/>
475
- <reg name="mhpmcounter19" bitsize="64"/>
476
- <reg name="mhpmcounter20" bitsize="64"/>
477
- <reg name="mhpmcounter21" bitsize="64"/>
478
- <reg name="mhpmcounter22" bitsize="64"/>
479
- <reg name="mhpmcounter23" bitsize="64"/>
480
- <reg name="mhpmcounter24" bitsize="64"/>
481
- <reg name="mhpmcounter25" bitsize="64"/>
482
- <reg name="mhpmcounter26" bitsize="64"/>
483
- <reg name="mhpmcounter27" bitsize="64"/>
484
- <reg name="mhpmcounter28" bitsize="64"/>
485
- <reg name="mhpmcounter29" bitsize="64"/>
486
- <reg name="mhpmcounter30" bitsize="64"/>
487
- <reg name="mhpmcounter31" bitsize="64"/>
488
- <reg name="mcycleh" bitsize="64"/>
489
- <reg name="minstreth" bitsize="64"/>
490
- <reg name="mhpmcounter3h" bitsize="64"/>
491
- <reg name="mhpmcounter4h" bitsize="64"/>
492
- <reg name="mhpmcounter5h" bitsize="64"/>
493
- <reg name="mhpmcounter6h" bitsize="64"/>
494
- <reg name="mhpmcounter7h" bitsize="64"/>
495
- <reg name="mhpmcounter8h" bitsize="64"/>
496
- <reg name="mhpmcounter9h" bitsize="64"/>
497
- <reg name="mhpmcounter10h" bitsize="64"/>
498
- <reg name="mhpmcounter11h" bitsize="64"/>
499
- <reg name="mhpmcounter12h" bitsize="64"/>
500
- <reg name="mhpmcounter13h" bitsize="64"/>
501
- <reg name="mhpmcounter14h" bitsize="64"/>
502
- <reg name="mhpmcounter15h" bitsize="64"/>
503
- <reg name="mhpmcounter16h" bitsize="64"/>
504
- <reg name="mhpmcounter17h" bitsize="64"/>
505
- <reg name="mhpmcounter18h" bitsize="64"/>
506
- <reg name="mhpmcounter19h" bitsize="64"/>
507
- <reg name="mhpmcounter20h" bitsize="64"/>
508
- <reg name="mhpmcounter21h" bitsize="64"/>
509
- <reg name="mhpmcounter22h" bitsize="64"/>
510
- <reg name="mhpmcounter23h" bitsize="64"/>
511
- <reg name="mhpmcounter24h" bitsize="64"/>
512
- <reg name="mhpmcounter25h" bitsize="64"/>
513
- <reg name="mhpmcounter26h" bitsize="64"/>
514
- <reg name="mhpmcounter27h" bitsize="64"/>
515
- <reg name="mhpmcounter28h" bitsize="64"/>
516
- <reg name="mhpmcounter29h" bitsize="64"/>
517
- <reg name="mhpmcounter30h" bitsize="64"/>
518
- <reg name="mhpmcounter31h" bitsize="64"/>
519
- <reg name="mhpmevent3" bitsize="64"/>
520
- <reg name="mhpmevent4" bitsize="64"/>
521
- <reg name="mhpmevent5" bitsize="64"/>
522
- <reg name="mhpmevent6" bitsize="64"/>
523
- <reg name="mhpmevent7" bitsize="64"/>
524
- <reg name="mhpmevent8" bitsize="64"/>
525
- <reg name="mhpmevent9" bitsize="64"/>
526
- <reg name="mhpmevent10" bitsize="64"/>
527
- <reg name="mhpmevent11" bitsize="64"/>
528
- <reg name="mhpmevent12" bitsize="64"/>
529
- <reg name="mhpmevent13" bitsize="64"/>
530
- <reg name="mhpmevent14" bitsize="64"/>
531
- <reg name="mhpmevent15" bitsize="64"/>
532
- <reg name="mhpmevent16" bitsize="64"/>
533
- <reg name="mhpmevent17" bitsize="64"/>
534
- <reg name="mhpmevent18" bitsize="64"/>
535
- <reg name="mhpmevent19" bitsize="64"/>
536
- <reg name="mhpmevent20" bitsize="64"/>
537
- <reg name="mhpmevent21" bitsize="64"/>
538
- <reg name="mhpmevent22" bitsize="64"/>
539
- <reg name="mhpmevent23" bitsize="64"/>
540
- <reg name="mhpmevent24" bitsize="64"/>
541
- <reg name="mhpmevent25" bitsize="64"/>
542
- <reg name="mhpmevent26" bitsize="64"/>
543
- <reg name="mhpmevent27" bitsize="64"/>
544
- <reg name="mhpmevent28" bitsize="64"/>
545
- <reg name="mhpmevent29" bitsize="64"/>
546
- <reg name="mhpmevent30" bitsize="64"/>
547
- <reg name="mhpmevent31" bitsize="64"/>
548
- <reg name="tselect" bitsize="64"/>
549
- <reg name="tdata1" bitsize="64"/>
550
- <reg name="tdata2" bitsize="64"/>
551
- <reg name="tdata3" bitsize="64"/>
552
- <reg name="dcsr" bitsize="64"/>
553
- <reg name="dpc" bitsize="64"/>
554
- <reg name="dscratch" bitsize="64"/>
555
- <reg name="hstatus" bitsize="64"/>
556
- <reg name="hedeleg" bitsize="64"/>
557
- <reg name="hideleg" bitsize="64"/>
558
- <reg name="hie" bitsize="64"/>
559
- <reg name="htvec" bitsize="64"/>
560
- <reg name="hscratch" bitsize="64"/>
561
- <reg name="hepc" bitsize="64"/>
562
- <reg name="hcause" bitsize="64"/>
563
- <reg name="hbadaddr" bitsize="64"/>
564
- <reg name="hip" bitsize="64"/>
565
- <reg name="mbase" bitsize="64"/>
566
- <reg name="mbound" bitsize="64"/>
567
- <reg name="mibase" bitsize="64"/>
568
- <reg name="mibound" bitsize="64"/>
569
- <reg name="mdbase" bitsize="64"/>
570
- <reg name="mdbound" bitsize="64"/>
571
- <reg name="mucounteren" bitsize="64"/>
572
- <reg name="mscounteren" bitsize="64"/>
573
- <reg name="mhcounteren" bitsize="64"/>
574
-</feature>
575
--
123
--
576
2.29.2
124
2.30.1
577
125
578
126
diff view generated by jsdifflib
New patch
[PULL 16/16] target/riscv: Prevent lost illegal instruction exceptions
1
1
From: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
2
3
When decode_insn16() fails, we fall back to decode_RV32_64C() for
4
further compressed instruction decoding. However, prior to this change,
5
we did not raise an illegal instruction exception, if decode_RV32_64C()
6
fails to decode the instruction. This means that we skipped illegal
7
compressed instructions instead of raising an illegal instruction
8
exception.
9
10
Instead of patching decode_RV32_64C(), we can just remove it,
11
as it is dead code since f330433b363 anyway.
12
13
Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
14
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
15
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
16
Message-id: 20210322121609.3097928-1-georg.kotheimer@kernkonzept.com
17
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
18
---
19
target/riscv/translate.c | 179 +--------------------------------------
20
1 file changed, 1 insertion(+), 178 deletions(-)
21
22
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
23
index XXXXXXX..XXXXXXX 100644
24
--- a/target/riscv/translate.c
25
+++ b/target/riscv/translate.c
26
@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
27
CPUState *cs;
28
} DisasContext;
29
30
-#ifdef TARGET_RISCV64
31
-/* convert riscv funct3 to qemu memop for load/store */
32
-static const int tcg_memop_lookup[8] = {
33
- [0 ... 7] = -1,
34
- [0] = MO_SB,
35
- [1] = MO_TESW,
36
- [2] = MO_TESL,
37
- [3] = MO_TEQ,
38
- [4] = MO_UB,
39
- [5] = MO_TEUW,
40
- [6] = MO_TEUL,
41
-};
42
-#endif
43
-
44
#ifdef TARGET_RISCV64
45
#define CASE_OP_32_64(X) case X: case glue(X, W)
46
#else
47
@@ -XXX,XX +XXX,XX @@ static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
48
ctx->base.is_jmp = DISAS_NORETURN;
49
}
50
51
-#ifdef TARGET_RISCV64
52
-static void gen_load_c(DisasContext *ctx, uint32_t opc, int rd, int rs1,
53
- target_long imm)
54
-{
55
- TCGv t0 = tcg_temp_new();
56
- TCGv t1 = tcg_temp_new();
57
- gen_get_gpr(t0, rs1);
58
- tcg_gen_addi_tl(t0, t0, imm);
59
- int memop = tcg_memop_lookup[(opc >> 12) & 0x7];
60
-
61
- if (memop < 0) {
62
- gen_exception_illegal(ctx);
63
- return;
64
- }
65
-
66
- tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, memop);
67
- gen_set_gpr(rd, t1);
68
- tcg_temp_free(t0);
69
- tcg_temp_free(t1);
70
-}
71
-
72
-static void gen_store_c(DisasContext *ctx, uint32_t opc, int rs1, int rs2,
73
- target_long imm)
74
-{
75
- TCGv t0 = tcg_temp_new();
76
- TCGv dat = tcg_temp_new();
77
- gen_get_gpr(t0, rs1);
78
- tcg_gen_addi_tl(t0, t0, imm);
79
- gen_get_gpr(dat, rs2);
80
- int memop = tcg_memop_lookup[(opc >> 12) & 0x7];
81
-
82
- if (memop < 0) {
83
- gen_exception_illegal(ctx);
84
- return;
85
- }
86
-
87
- tcg_gen_qemu_st_tl(dat, t0, ctx->mem_idx, memop);
88
- tcg_temp_free(t0);
89
- tcg_temp_free(dat);
90
-}
91
-#endif
92
-
93
#ifndef CONFIG_USER_ONLY
94
/* The states of mstatus_fs are:
95
* 0 = disabled, 1 = initial, 2 = clean, 3 = dirty
96
@@ -XXX,XX +XXX,XX @@ static void mark_fs_dirty(DisasContext *ctx)
97
static inline void mark_fs_dirty(DisasContext *ctx) { }
98
#endif
99
100
-#if !defined(TARGET_RISCV64)
101
-static void gen_fp_load(DisasContext *ctx, uint32_t opc, int rd,
102
- int rs1, target_long imm)
103
-{
104
- TCGv t0;
105
-
106
- if (ctx->mstatus_fs == 0) {
107
- gen_exception_illegal(ctx);
108
- return;
109
- }
110
-
111
- t0 = tcg_temp_new();
112
- gen_get_gpr(t0, rs1);
113
- tcg_gen_addi_tl(t0, t0, imm);
114
-
115
- switch (opc) {
116
- case OPC_RISC_FLW:
117
- if (!has_ext(ctx, RVF)) {
118
- goto do_illegal;
119
- }
120
- tcg_gen_qemu_ld_i64(cpu_fpr[rd], t0, ctx->mem_idx, MO_TEUL);
121
- /* RISC-V requires NaN-boxing of narrower width floating point values */
122
- tcg_gen_ori_i64(cpu_fpr[rd], cpu_fpr[rd], 0xffffffff00000000ULL);
123
- break;
124
- case OPC_RISC_FLD:
125
- if (!has_ext(ctx, RVD)) {
126
- goto do_illegal;
127
- }
128
- tcg_gen_qemu_ld_i64(cpu_fpr[rd], t0, ctx->mem_idx, MO_TEQ);
129
- break;
130
- do_illegal:
131
- default:
132
- gen_exception_illegal(ctx);
133
- break;
134
- }
135
- tcg_temp_free(t0);
136
-
137
- mark_fs_dirty(ctx);
138
-}
139
-
140
-static void gen_fp_store(DisasContext *ctx, uint32_t opc, int rs1,
141
- int rs2, target_long imm)
142
-{
143
- TCGv t0;
144
-
145
- if (ctx->mstatus_fs == 0) {
146
- gen_exception_illegal(ctx);
147
- return;
148
- }
149
-
150
- t0 = tcg_temp_new();
151
- gen_get_gpr(t0, rs1);
152
- tcg_gen_addi_tl(t0, t0, imm);
153
-
154
- switch (opc) {
155
- case OPC_RISC_FSW:
156
- if (!has_ext(ctx, RVF)) {
157
- goto do_illegal;
158
- }
159
- tcg_gen_qemu_st_i64(cpu_fpr[rs2], t0, ctx->mem_idx, MO_TEUL);
160
- break;
161
- case OPC_RISC_FSD:
162
- if (!has_ext(ctx, RVD)) {
163
- goto do_illegal;
164
- }
165
- tcg_gen_qemu_st_i64(cpu_fpr[rs2], t0, ctx->mem_idx, MO_TEQ);
166
- break;
167
- do_illegal:
168
- default:
169
- gen_exception_illegal(ctx);
170
- break;
171
- }
172
-
173
- tcg_temp_free(t0);
174
-}
175
-#endif
176
-
177
static void gen_set_rm(DisasContext *ctx, int rm)
178
{
179
TCGv_i32 t0;
180
@@ -XXX,XX +XXX,XX @@ static void gen_set_rm(DisasContext *ctx, int rm)
181
tcg_temp_free_i32(t0);
182
}
183
184
-static void decode_RV32_64C0(DisasContext *ctx, uint16_t opcode)
185
-{
186
- uint8_t funct3 = extract16(opcode, 13, 3);
187
- uint8_t rd_rs2 = GET_C_RS2S(opcode);
188
- uint8_t rs1s = GET_C_RS1S(opcode);
189
-
190
- switch (funct3) {
191
- case 3:
192
-#if defined(TARGET_RISCV64)
193
- /* C.LD(RV64/128) -> ld rd', offset[7:3](rs1')*/
194
- gen_load_c(ctx, OPC_RISC_LD, rd_rs2, rs1s,
195
- GET_C_LD_IMM(opcode));
196
-#else
197
- /* C.FLW (RV32) -> flw rd', offset[6:2](rs1')*/
198
- gen_fp_load(ctx, OPC_RISC_FLW, rd_rs2, rs1s,
199
- GET_C_LW_IMM(opcode));
200
-#endif
201
- break;
202
- case 7:
203
-#if defined(TARGET_RISCV64)
204
- /* C.SD (RV64/128) -> sd rs2', offset[7:3](rs1')*/
205
- gen_store_c(ctx, OPC_RISC_SD, rs1s, rd_rs2,
206
- GET_C_LD_IMM(opcode));
207
-#else
208
- /* C.FSW (RV32) -> fsw rs2', offset[6:2](rs1')*/
209
- gen_fp_store(ctx, OPC_RISC_FSW, rs1s, rd_rs2,
210
- GET_C_LW_IMM(opcode));
211
-#endif
212
- break;
213
- }
214
-}
215
-
216
-static void decode_RV32_64C(DisasContext *ctx, uint16_t opcode)
217
-{
218
- uint8_t op = extract16(opcode, 0, 2);
219
-
220
- switch (op) {
221
- case 0:
222
- decode_RV32_64C0(ctx, opcode);
223
- break;
224
- }
225
-}
226
-
227
static int ex_plus_1(DisasContext *ctx, int nf)
228
{
229
return nf + 1;
230
@@ -XXX,XX +XXX,XX @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
231
} else {
232
ctx->pc_succ_insn = ctx->base.pc_next + 2;
233
if (!decode_insn16(ctx, opcode)) {
234
- /* fall back to old decoder */
235
- decode_RV32_64C(ctx, opcode);
236
+ gen_exception_illegal(ctx);
237
}
238
}
239
} else {
240
--
241
2.30.1
242
243
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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