[PULL 00/12] riscv-to-apply queue
[PULL 00/30] riscv-to-apply queue
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The following changes since commit 825a215c003cd028e26c7d19aa5049d957345f43:
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The following changes since commit 9435a8b3dd35f1f926f1b9127e8a906217a5518a:
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Merge remote-tracking branch 'remotes/kraxel/tags/audio-20210115-pull-request' into staging (2021-01-15 22:21:21 +0000)
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Merge remote-tracking branch 'remotes/kraxel/tags/sirius/ipxe-20200908-pull-request' into staging (2020-09-08 21:21:13 +0100)
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are available in the Git repository at:
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are available in the Git repository at:
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git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20210117-3
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git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20200910
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for you to fetch changes up to a8259b53230782f5e0a0d66013655c4ed5d71b7e:
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for you to fetch changes up to 7595a65818ea9b49c36650a8c217a1ef9bd6e62a:
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riscv: Pass RISCVHartArrayState by pointer (2021-01-16 14:34:46 -0800)
11
hw/riscv: Sort the Kconfig options in alphabetical order (2020-09-09 15:54:19 -0700)
12
12
13
----------------------------------------------------------------
13
----------------------------------------------------------------
14
First RISC-V PR for 6.0
14
This PR includes multiple fixes and features for RISC-V:
15
15
- Fixes a bug in printing trap causes
16
This PR:
16
- Allows 16-bit writes to the SiFive test device. This fixes the
17
- Fixes some issues with the m25p80
17
failure to reboot the RISC-V virt machine
18
- Improves GDB support for RISC-V
18
- Support for the Microchip PolarFire SoC and Icicle Kit
19
- Fixes some Linux boot issues, specifiaclly 32-bit boot failures
19
- A reafactor of RISC-V code out of hw/riscv
20
- Enforces PMP exceptions correctly
21
- Fixes some Coverity issues
22
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23
----------------------------------------------------------------
21
----------------------------------------------------------------
24
Alistair Francis (1):
22
Bin Meng (28):
25
riscv: Pass RISCVHartArrayState by pointer
23
target/riscv: cpu: Add a new 'resetvec' property
24
hw/riscv: hart: Add a new 'resetvec' property
25
target/riscv: cpu: Set reset vector based on the configured property value
26
hw/riscv: Initial support for Microchip PolarFire SoC Icicle Kit board
27
hw/char: Add Microchip PolarFire SoC MMUART emulation
28
hw/riscv: microchip_pfsoc: Connect 5 MMUARTs
29
hw/sd: Add Cadence SDHCI emulation
30
hw/riscv: microchip_pfsoc: Connect a Cadence SDHCI controller and an SD card
31
hw/dma: Add SiFive platform DMA controller emulation
32
hw/riscv: microchip_pfsoc: Connect a DMA controller
33
hw/net: cadence_gem: Add a new 'phy-addr' property
34
hw/arm: xlnx: Set all boards' GEM 'phy-addr' property value to 23
35
hw/riscv: microchip_pfsoc: Connect 2 Cadence GEMs
36
hw/riscv: microchip_pfsoc: Hook GPIO controllers
37
hw/riscv: clint: Avoid using hard-coded timebase frequency
38
hw/riscv: sifive_u: Connect a DMA controller
39
hw/riscv: Move sifive_e_prci model to hw/misc
40
hw/riscv: Move sifive_u_prci model to hw/misc
41
hw/riscv: Move sifive_u_otp model to hw/misc
42
hw/riscv: Move sifive_gpio model to hw/gpio
43
hw/riscv: Move sifive_clint model to hw/intc
44
hw/riscv: Move sifive_plic model to hw/intc
45
hw/riscv: Move riscv_htif model to hw/char
46
hw/riscv: Move sifive_uart model to hw/char
47
hw/riscv: Move sifive_test model to hw/misc
48
hw/riscv: Always build riscv_hart.c
49
hw/riscv: Drop CONFIG_SIFIVE
50
hw/riscv: Sort the Kconfig options in alphabetical order
26
51
27
Atish Patra (2):
52
Nathan Chancellor (1):
28
RISC-V: Place DTB at 3GB boundary instead of 4GB
53
riscv: sifive_test: Allow 16-bit writes to memory region
29
target/riscv/pmp: Raise exception if no PMP entry is configured
30
54
31
Bin Meng (6):
55
Yifei Jiang (1):
32
hw/block: m25p80: Don't write to flash if write is disabled
56
target/riscv: Fix bug in getting trap cause name for trace_riscv_trap
33
hw/riscv: sifive_u: Use SIFIVE_U_CPU for mc->default_cpu_type
34
target/riscv: Make csr_ops[CSR_TABLE_SIZE] external
35
target/riscv: Add CSR name in the CSR function table
36
target/riscv: Generate the GDB XML file for CSR registers dynamically
37
target/riscv: Remove built-in GDB XML files for CSRs
38
57
39
Green Wan (1):
58
default-configs/riscv64-softmmu.mak | 1 +
40
hw/misc/sifive_u_otp: handling the fails of blk_pread and blk_pwrite
59
{include/hw/riscv => hw/intc}/sifive_plic.h | 0
60
hw/riscv/trace.h | 1 -
61
include/hw/char/mchp_pfsoc_mmuart.h | 61 ++++
62
include/hw/{riscv => char}/riscv_htif.h | 0
63
include/hw/{riscv => char}/sifive_uart.h | 0
64
include/hw/dma/sifive_pdma.h | 57 ++++
65
include/hw/{riscv => gpio}/sifive_gpio.h | 0
66
include/hw/{riscv => intc}/sifive_clint.h | 4 +-
67
include/hw/{riscv => misc}/sifive_e_prci.h | 0
68
include/hw/{riscv => misc}/sifive_test.h | 0
69
include/hw/{riscv => misc}/sifive_u_otp.h | 0
70
include/hw/{riscv => misc}/sifive_u_prci.h | 0
71
include/hw/net/cadence_gem.h | 2 +
72
include/hw/riscv/microchip_pfsoc.h | 133 +++++++++
73
include/hw/riscv/riscv_hart.h | 1 +
74
include/hw/riscv/sifive_e.h | 2 +-
75
include/hw/riscv/sifive_u.h | 17 +-
76
include/hw/sd/cadence_sdhci.h | 47 +++
77
target/riscv/cpu.h | 8 +-
78
hw/arm/xilinx_zynq.c | 1 +
79
hw/arm/xlnx-versal.c | 1 +
80
hw/arm/xlnx-zynqmp.c | 2 +
81
hw/char/mchp_pfsoc_mmuart.c | 86 ++++++
82
hw/{riscv => char}/riscv_htif.c | 2 +-
83
hw/{riscv => char}/sifive_uart.c | 2 +-
84
hw/dma/sifive_pdma.c | 313 ++++++++++++++++++++
85
hw/{riscv => gpio}/sifive_gpio.c | 2 +-
86
hw/{riscv => intc}/sifive_clint.c | 28 +-
87
hw/{riscv => intc}/sifive_plic.c | 2 +-
88
hw/{riscv => misc}/sifive_e_prci.c | 2 +-
89
hw/{riscv => misc}/sifive_test.c | 4 +-
90
hw/{riscv => misc}/sifive_u_otp.c | 2 +-
91
hw/{riscv => misc}/sifive_u_prci.c | 2 +-
92
hw/net/cadence_gem.c | 7 +-
93
hw/riscv/microchip_pfsoc.c | 437 ++++++++++++++++++++++++++++
94
hw/riscv/opentitan.c | 1 +
95
hw/riscv/riscv_hart.c | 3 +
96
hw/riscv/sifive_e.c | 12 +-
97
hw/riscv/sifive_u.c | 41 ++-
98
hw/riscv/spike.c | 7 +-
99
hw/riscv/virt.c | 9 +-
100
hw/sd/cadence_sdhci.c | 193 ++++++++++++
101
target/riscv/cpu.c | 19 +-
102
target/riscv/cpu_helper.c | 8 +-
103
target/riscv/csr.c | 4 +-
104
MAINTAINERS | 9 +
105
hw/char/Kconfig | 9 +
106
hw/char/meson.build | 3 +
107
hw/dma/Kconfig | 3 +
108
hw/dma/meson.build | 1 +
109
hw/gpio/Kconfig | 3 +
110
hw/gpio/meson.build | 1 +
111
hw/gpio/trace-events | 6 +
112
hw/intc/Kconfig | 6 +
113
hw/intc/meson.build | 2 +
114
hw/misc/Kconfig | 12 +
115
hw/misc/meson.build | 6 +
116
hw/riscv/Kconfig | 70 +++--
117
hw/riscv/meson.build | 12 +-
118
hw/riscv/trace-events | 7 -
119
hw/sd/Kconfig | 4 +
120
hw/sd/meson.build | 1 +
121
meson.build | 1 -
122
64 files changed, 1575 insertions(+), 105 deletions(-)
123
rename {include/hw/riscv => hw/intc}/sifive_plic.h (100%)
124
delete mode 100644 hw/riscv/trace.h
125
create mode 100644 include/hw/char/mchp_pfsoc_mmuart.h
126
rename include/hw/{riscv => char}/riscv_htif.h (100%)
127
rename include/hw/{riscv => char}/sifive_uart.h (100%)
128
create mode 100644 include/hw/dma/sifive_pdma.h
129
rename include/hw/{riscv => gpio}/sifive_gpio.h (100%)
130
rename include/hw/{riscv => intc}/sifive_clint.h (92%)
131
rename include/hw/{riscv => misc}/sifive_e_prci.h (100%)
132
rename include/hw/{riscv => misc}/sifive_test.h (100%)
133
rename include/hw/{riscv => misc}/sifive_u_otp.h (100%)
134
rename include/hw/{riscv => misc}/sifive_u_prci.h (100%)
135
create mode 100644 include/hw/riscv/microchip_pfsoc.h
136
create mode 100644 include/hw/sd/cadence_sdhci.h
137
create mode 100644 hw/char/mchp_pfsoc_mmuart.c
138
rename hw/{riscv => char}/riscv_htif.c (99%)
139
rename hw/{riscv => char}/sifive_uart.c (99%)
140
create mode 100644 hw/dma/sifive_pdma.c
141
rename hw/{riscv => gpio}/sifive_gpio.c (99%)
142
rename hw/{riscv => intc}/sifive_clint.c (90%)
143
rename hw/{riscv => intc}/sifive_plic.c (99%)
144
rename hw/{riscv => misc}/sifive_e_prci.c (99%)
145
rename hw/{riscv => misc}/sifive_test.c (97%)
146
rename hw/{riscv => misc}/sifive_u_otp.c (99%)
147
rename hw/{riscv => misc}/sifive_u_prci.c (99%)
148
create mode 100644 hw/riscv/microchip_pfsoc.c
149
create mode 100644 hw/sd/cadence_sdhci.c
150
delete mode 100644 hw/riscv/trace-events
41
151
42
Sylvain Pelissier (1):
43
gdb: riscv: Add target description
44
45
Xuzhou Cheng (1):
46
hw/block: m25p80: Implement AAI-WP command support for SST flashes
47
48
default-configs/targets/riscv32-linux-user.mak | 2 +-
49
default-configs/targets/riscv32-softmmu.mak | 2 +-
50
default-configs/targets/riscv64-linux-user.mak | 2 +-
51
default-configs/targets/riscv64-softmmu.mak | 2 +-
52
include/hw/riscv/boot.h | 6 +-
53
target/riscv/cpu.h | 11 +
54
target/riscv/pmp.h | 1 +
55
hw/block/m25p80.c | 74 ++++++
56
hw/misc/sifive_u_otp.c | 31 ++-
57
hw/riscv/boot.c | 18 +-
58
hw/riscv/sifive_u.c | 16 +-
59
hw/riscv/spike.c | 8 +-
60
hw/riscv/virt.c | 8 +-
61
target/riscv/cpu.c | 25 ++
62
target/riscv/csr.c | 342 ++++++++++++++++++-------
63
target/riscv/gdbstub.c | 308 ++++------------------
64
target/riscv/op_helper.c | 5 +
65
target/riscv/pmp.c | 4 +-
66
gdb-xml/riscv-32bit-csr.xml | 250 ------------------
67
gdb-xml/riscv-64bit-csr.xml | 250 ------------------
68
20 files changed, 463 insertions(+), 902 deletions(-)
69
delete mode 100644 gdb-xml/riscv-32bit-csr.xml
70
delete mode 100644 gdb-xml/riscv-64bit-csr.xml
71
diff view generated by jsdifflib
[PULL 03/12] gdb: riscv: Add target description
[PULL 01/30] target/riscv: Fix bug in getting trap cause name for trace_riscv_trap
1
From: Sylvain Pelissier <sylvain.pelissier@gmail.com>
1
From: Yifei Jiang <jiangyifei@huawei.com>
2
2
3
Target description is not currently implemented in RISC-V
3
When the cause number is equal to or greater than 23, print "(unknown)" in
4
architecture. Thus GDB won't set it properly when attached.
4
trace_riscv_trap. The max valid number of riscv_excp_names is 23, so the last
5
The patch implements the target description response.
5
excpetion "guest_store_page_fault" can not be printed.
6
6
7
Signed-off-by: Sylvain Pelissier <sylvain.pelissier@gmail.com>
7
In addition, the current check of cause is invalid for riscv_intr_names. So
8
Reviewed-by: Bin Meng <bin.meng@windriver.com>
8
introduce riscv_cpu_get_trap_name to get the trap cause name.
9
10
Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
11
Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com>
9
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
12
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
10
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
13
Message-Id: <20200814035819.1214-1-jiangyifei@huawei.com>
11
Message-id: 20210106204141.14027-1-sylvain.pelissier@gmail.com
12
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
14
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
13
---
15
---
14
target/riscv/cpu.c | 13 +++++++++++++
16
target/riscv/cpu.h | 1 +
15
1 file changed, 13 insertions(+)
17
target/riscv/cpu.c | 11 +++++++++++
18
target/riscv/cpu_helper.c | 4 ++--
19
3 files changed, 14 insertions(+), 2 deletions(-)
16
20
21
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
22
index XXXXXXX..XXXXXXX 100644
23
--- a/target/riscv/cpu.h
24
+++ b/target/riscv/cpu.h
25
@@ -XXX,XX +XXX,XX @@ extern const char * const riscv_fpr_regnames[];
26
extern const char * const riscv_excp_names[];
27
extern const char * const riscv_intr_names[];
28
29
+const char *riscv_cpu_get_trap_name(target_ulong cause, bool async);
30
void riscv_cpu_do_interrupt(CPUState *cpu);
31
int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
32
int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
17
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
33
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
18
index XXXXXXX..XXXXXXX 100644
34
index XXXXXXX..XXXXXXX 100644
19
--- a/target/riscv/cpu.c
35
--- a/target/riscv/cpu.c
20
+++ b/target/riscv/cpu.c
36
+++ b/target/riscv/cpu.c
21
@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_properties[] = {
37
@@ -XXX,XX +XXX,XX @@ const char * const riscv_intr_names[] = {
22
DEFINE_PROP_END_OF_LIST(),
38
"reserved"
23
};
39
};
24
40
25
+static gchar *riscv_gdb_arch_name(CPUState *cs)
41
+const char *riscv_cpu_get_trap_name(target_ulong cause, bool async)
26
+{
42
+{
27
+ RISCVCPU *cpu = RISCV_CPU(cs);
43
+ if (async) {
28
+ CPURISCVState *env = &cpu->env;
44
+ return (cause < ARRAY_SIZE(riscv_intr_names)) ?
29
+
45
+ riscv_intr_names[cause] : "(unknown)";
30
+ if (riscv_cpu_is_32bit(env)) {
31
+ return g_strdup("riscv:rv32");
32
+ } else {
46
+ } else {
33
+ return g_strdup("riscv:rv64");
47
+ return (cause < ARRAY_SIZE(riscv_excp_names)) ?
48
+ riscv_excp_names[cause] : "(unknown)";
34
+ }
49
+ }
35
+}
50
+}
36
+
51
+
37
static void riscv_cpu_class_init(ObjectClass *c, void *data)
52
static void set_misa(CPURISCVState *env, target_ulong misa)
38
{
53
{
39
RISCVCPUClass *mcc = RISCV_CPU_CLASS(c);
54
env->misa_mask = env->misa = misa;
40
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
55
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
41
/* For now, mark unmigratable: */
56
index XXXXXXX..XXXXXXX 100644
42
cc->vmsd = &vmstate_riscv_cpu;
57
--- a/target/riscv/cpu_helper.c
43
#endif
58
+++ b/target/riscv/cpu_helper.c
44
+ cc->gdb_arch_name = riscv_gdb_arch_name;
59
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
45
#ifdef CONFIG_TCG
60
}
46
cc->tcg_initialize = riscv_translate_init;
61
}
47
cc->tlb_fill = riscv_cpu_tlb_fill;
62
63
- trace_riscv_trap(env->mhartid, async, cause, env->pc, tval, cause < 23 ?
64
- (async ? riscv_intr_names : riscv_excp_names)[cause] : "(unknown)");
65
+ trace_riscv_trap(env->mhartid, async, cause, env->pc, tval,
66
+ riscv_cpu_get_trap_name(cause, async));
67
68
if (env->priv <= PRV_S &&
69
cause < TARGET_LONG_BITS && ((deleg >> cause) & 1)) {
48
--
70
--
49
2.29.2
71
2.28.0
50
72
51
73
diff view generated by jsdifflib
[PULL 02/12] hw/block: m25p80: Implement AAI-WP command support for SST flashes
[PULL 02/30] riscv: sifive_test: Allow 16-bit writes to memory region
1
From: Xuzhou Cheng <xuzhou.cheng@windriver.com>
1
From: Nathan Chancellor <natechancellor@gmail.com>
2
2
3
Auto Address Increment (AAI) Word-Program is a special command of
3
When shutting down the machine running a mainline Linux kernel, the
4
SST flashes. AAI-WP allows multiple bytes of data to be programmed
4
following error happens:
5
without re-issuing the next sequential address location.
6
5
7
Signed-off-by: Xuzhou Cheng <xuzhou.cheng@windriver.com>
6
$ build/riscv64-softmmu/qemu-system-riscv64 -bios default -M virt \
8
Signed-off-by: Bin Meng <bin.meng@windriver.com>
7
-display none -initrd rootfs.cpio -kernel Image -m 512m \
9
Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
8
-nodefaults -serial mon:stdio
10
Message-id: 1608688825-81519-2-git-send-email-bmeng.cn@gmail.com
9
...
10
Requesting system poweroff
11
[ 4.999630] reboot: Power down
12
sbi_trap_error: hart0: trap handler failed (error -2)
13
sbi_trap_error: hart0: mcause=0x0000000000000007 mtval=0x0000000000100000
14
sbi_trap_error: hart0: mepc=0x000000008000d4cc mstatus=0x0000000000001822
15
sbi_trap_error: hart0: ra=0x000000008000999e sp=0x0000000080015c78
16
sbi_trap_error: hart0: gp=0xffffffe000e76610 tp=0xffffffe0081b89c0
17
sbi_trap_error: hart0: s0=0x0000000080015c88 s1=0x0000000000000040
18
sbi_trap_error: hart0: a0=0x0000000000000000 a1=0x0000000080004024
19
sbi_trap_error: hart0: a2=0x0000000080004024 a3=0x0000000080004024
20
sbi_trap_error: hart0: a4=0x0000000000100000 a5=0x0000000000005555
21
sbi_trap_error: hart0: a6=0x0000000000004024 a7=0x0000000080011158
22
sbi_trap_error: hart0: s2=0x0000000000000000 s3=0x0000000080016000
23
sbi_trap_error: hart0: s4=0x0000000000000000 s5=0x0000000000000000
24
sbi_trap_error: hart0: s6=0x0000000000000001 s7=0x0000000000000000
25
sbi_trap_error: hart0: s8=0x0000000000000000 s9=0x0000000000000000
26
sbi_trap_error: hart0: s10=0x0000000000000000 s11=0x0000000000000008
27
sbi_trap_error: hart0: t0=0x0000000000000000 t1=0x0000000000000000
28
sbi_trap_error: hart0: t2=0x0000000000000000 t3=0x0000000000000000
29
sbi_trap_error: hart0: t4=0x0000000000000000 t5=0x0000000000000000
30
sbi_trap_error: hart0: t6=0x0000000000000000
31
32
The kernel does a 16-bit write when powering off the machine, which
33
was allowed before commit 5d971f9e67 ("memory: Revert "memory: accept
34
mismatching sizes in memory_region_access_valid""). Make min_access_size
35
match reality so that the machine can shut down properly now.
36
37
Cc: qemu-stable@nongnu.org
38
Fixes: 88a07990fa ("SiFive RISC-V Test Finisher")
39
Fixes: 5d971f9e67 ("memory: Revert "memory: accept mismatching sizes in memory_region_access_valid"")
40
Signed-off-by: Nathan Chancellor <natechancellor@gmail.com>
41
Acked-by: Michael S. Tsirkin <mst@redhat.com>
42
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
43
Message-Id: <20200901055822.2721209-1-natechancellor@gmail.com>
11
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
44
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
12
---
45
---
13
hw/block/m25p80.c | 73 +++++++++++++++++++++++++++++++++++++++++++++++
46
hw/riscv/sifive_test.c | 2 +-
14
1 file changed, 73 insertions(+)
47
1 file changed, 1 insertion(+), 1 deletion(-)
15
48
16
diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
49
diff --git a/hw/riscv/sifive_test.c b/hw/riscv/sifive_test.c
17
index XXXXXXX..XXXXXXX 100644
50
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/block/m25p80.c
51
--- a/hw/riscv/sifive_test.c
19
+++ b/hw/block/m25p80.c
52
+++ b/hw/riscv/sifive_test.c
20
@@ -XXX,XX +XXX,XX @@ typedef enum {
53
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps sifive_test_ops = {
21
QPP_4 = 0x34,
54
.write = sifive_test_write,
22
RDID_90 = 0x90,
55
.endianness = DEVICE_NATIVE_ENDIAN,
23
RDID_AB = 0xab,
56
.valid = {
24
+ AAI_WP = 0xad,
57
- .min_access_size = 4,
25
58
+ .min_access_size = 2,
26
ERASE_4K = 0x20,
59
.max_access_size = 4
27
ERASE4_4K = 0x21,
28
@@ -XXX,XX +XXX,XX @@ struct Flash {
29
bool four_bytes_address_mode;
30
bool reset_enable;
31
bool quad_enable;
32
+ bool aai_enable;
33
uint8_t ear;
34
35
int64_t dirty_page;
36
@@ -XXX,XX +XXX,XX @@ static void complete_collecting_data(Flash *s)
37
case PP4_4:
38
s->state = STATE_PAGE_PROGRAM;
39
break;
40
+ case AAI_WP:
41
+ /* AAI programming starts from the even address */
42
+ s->cur_addr &= ~BIT(0);
43
+ s->state = STATE_PAGE_PROGRAM;
44
+ break;
45
case READ:
46
case READ4:
47
case FAST_READ:
48
@@ -XXX,XX +XXX,XX @@ static void reset_memory(Flash *s)
49
s->write_enable = false;
50
s->reset_enable = false;
51
s->quad_enable = false;
52
+ s->aai_enable = false;
53
54
switch (get_man(s)) {
55
case MAN_NUMONYX:
56
@@ -XXX,XX +XXX,XX @@ static void decode_qio_read_cmd(Flash *s)
57
s->state = STATE_COLLECTING_DATA;
58
}
59
60
+static bool is_valid_aai_cmd(uint32_t cmd)
61
+{
62
+ return cmd == AAI_WP || cmd == WRDI || cmd == RDSR;
63
+}
64
+
65
static void decode_new_cmd(Flash *s, uint32_t value)
66
{
67
int i;
68
@@ -XXX,XX +XXX,XX @@ static void decode_new_cmd(Flash *s, uint32_t value)
69
s->reset_enable = false;
70
}
71
72
+ if (get_man(s) == MAN_SST && s->aai_enable && !is_valid_aai_cmd(value)) {
73
+ qemu_log_mask(LOG_GUEST_ERROR,
74
+ "M25P80: Invalid cmd within AAI programming sequence");
75
+ }
76
+
77
switch (value) {
78
79
case ERASE_4K:
80
@@ -XXX,XX +XXX,XX @@ static void decode_new_cmd(Flash *s, uint32_t value)
81
82
case WRDI:
83
s->write_enable = false;
84
+ if (get_man(s) == MAN_SST) {
85
+ s->aai_enable = false;
86
+ }
87
break;
88
case WREN:
89
s->write_enable = true;
90
@@ -XXX,XX +XXX,XX @@ static void decode_new_cmd(Flash *s, uint32_t value)
91
if (get_man(s) == MAN_MACRONIX) {
92
s->data[0] |= (!!s->quad_enable) << 6;
93
}
94
+ if (get_man(s) == MAN_SST) {
95
+ s->data[0] |= (!!s->aai_enable) << 6;
96
+ }
97
+
98
s->pos = 0;
99
s->len = 1;
100
s->data_read_loop = true;
101
@@ -XXX,XX +XXX,XX @@ static void decode_new_cmd(Flash *s, uint32_t value)
102
case RSTQIO:
103
s->quad_enable = false;
104
break;
105
+ case AAI_WP:
106
+ if (get_man(s) == MAN_SST) {
107
+ if (s->write_enable) {
108
+ if (s->aai_enable) {
109
+ s->state = STATE_PAGE_PROGRAM;
110
+ } else {
111
+ s->aai_enable = true;
112
+ s->needed_bytes = get_addr_length(s);
113
+ s->state = STATE_COLLECTING_DATA;
114
+ }
115
+ } else {
116
+ qemu_log_mask(LOG_GUEST_ERROR,
117
+ "M25P80: AAI_WP with write protect\n");
118
+ }
119
+ } else {
120
+ qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Unknown cmd %x\n", value);
121
+ }
122
+ break;
123
default:
124
s->pos = 0;
125
s->len = 1;
126
@@ -XXX,XX +XXX,XX @@ static uint32_t m25p80_transfer8(SSIPeripheral *ss, uint32_t tx)
127
trace_m25p80_page_program(s, s->cur_addr, (uint8_t)tx);
128
flash_write8(s, s->cur_addr, (uint8_t)tx);
129
s->cur_addr = (s->cur_addr + 1) & (s->size - 1);
130
+
131
+ if (get_man(s) == MAN_SST && s->aai_enable && s->cur_addr == 0) {
132
+ /*
133
+ * There is no wrap mode during AAI programming once the highest
134
+ * unprotected memory address is reached. The Write-Enable-Latch
135
+ * bit is automatically reset, and AAI programming mode aborts.
136
+ */
137
+ s->write_enable = false;
138
+ s->aai_enable = false;
139
+ }
140
+
141
break;
142
143
case STATE_READ:
144
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_m25p80_data_read_loop = {
145
}
146
};
147
148
+static bool m25p80_aai_enable_needed(void *opaque)
149
+{
150
+ Flash *s = (Flash *)opaque;
151
+
152
+ return s->aai_enable;
153
+}
154
+
155
+static const VMStateDescription vmstate_m25p80_aai_enable = {
156
+ .name = "m25p80/aai_enable",
157
+ .version_id = 1,
158
+ .minimum_version_id = 1,
159
+ .needed = m25p80_aai_enable_needed,
160
+ .fields = (VMStateField[]) {
161
+ VMSTATE_BOOL(aai_enable, Flash),
162
+ VMSTATE_END_OF_LIST()
163
+ }
164
+};
165
+
166
static const VMStateDescription vmstate_m25p80 = {
167
.name = "m25p80",
168
.version_id = 0,
169
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_m25p80 = {
170
},
171
.subsections = (const VMStateDescription * []) {
172
&vmstate_m25p80_data_read_loop,
173
+ &vmstate_m25p80_aai_enable,
174
NULL
175
}
60
}
176
};
61
};
177
--
62
--
178
2.29.2
63
2.28.0
179
64
180
65
diff view generated by jsdifflib
[PULL 10/12] target/riscv: Generate the GDB XML file for CSR registers dynamically
[PULL 03/30] target/riscv: cpu: Add a new 'resetvec' property
1
From: Bin Meng <bin.meng@windriver.com>
1
From: Bin Meng <bin.meng@windriver.com>
2
2
3
At present QEMU RISC-V uses a hardcoded XML to report the feature
3
Currently the reset vector address is hard-coded in a RISC-V CPU's
4
"org.gnu.gdb.riscv.csr" [1]. There are two major issues with the
4
instance_init() routine. In a real world we can have 2 exact same
5
approach being used currently:
5
CPUs except for the reset vector address, which is pretty common in
6
the RISC-V core IP licensing business.
6
7
7
- The XML does not specify the "regnum" field of a CSR entry, hence
8
Normally reset vector address is a configurable parameter. Let's
8
consecutive numbers are used by the remote GDB client to access
9
create a 64-bit property to store the reset vector address which
9
CSRs. In QEMU we have to maintain a map table to convert the GDB
10
covers both 32-bit and 64-bit CPUs.
10
number to the hardware number which is error prone.
11
- The XML contains some CSRs that QEMU does not implement at all,
12
which causes an "E14" response sent to remote GDB client.
13
14
Change to generate the CSR register list dynamically, based on the
15
availability presented in the CSR function table. This new approach
16
will reflect a correct list of CSRs that QEMU actually implements.
17
18
[1] https://sourceware.org/gdb/current/onlinedocs/gdb/RISC_002dV-Features.html#RISC_002dV-Features
19
11
20
Signed-off-by: Bin Meng <bin.meng@windriver.com>
12
Signed-off-by: Bin Meng <bin.meng@windriver.com>
21
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
13
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
22
Message-id: 20210116054123.5457-2-bmeng.cn@gmail.com
14
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
15
Message-Id: <1598924352-89526-2-git-send-email-bmeng.cn@gmail.com>
23
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
16
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
24
---
17
---
25
target/riscv/cpu.h | 2 +
18
target/riscv/cpu.h | 1 +
26
target/riscv/cpu.c | 12 ++
19
target/riscv/cpu.c | 1 +
27
target/riscv/gdbstub.c | 308 ++++++-----------------------------------
20
2 files changed, 2 insertions(+)
28
3 files changed, 58 insertions(+), 264 deletions(-)
29
21
30
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
22
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
31
index XXXXXXX..XXXXXXX 100644
23
index XXXXXXX..XXXXXXX 100644
32
--- a/target/riscv/cpu.h
24
--- a/target/riscv/cpu.h
33
+++ b/target/riscv/cpu.h
25
+++ b/target/riscv/cpu.h
34
@@ -XXX,XX +XXX,XX @@ struct RISCVCPU {
26
@@ -XXX,XX +XXX,XX @@ typedef struct RISCVCPU {
35
CPUNegativeOffsetState neg;
27
uint16_t elen;
36
CPURISCVState env;
28
bool mmu;
37
29
bool pmp;
38
+ char *dyn_csr_xml;
30
+ uint64_t resetvec;
39
+
31
} cfg;
40
/* Configuration Settings */
32
} RISCVCPU;
41
struct {
33
42
bool ext_i;
43
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
34
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
44
index XXXXXXX..XXXXXXX 100644
35
index XXXXXXX..XXXXXXX 100644
45
--- a/target/riscv/cpu.c
36
--- a/target/riscv/cpu.c
46
+++ b/target/riscv/cpu.c
37
+++ b/target/riscv/cpu.c
47
@@ -XXX,XX +XXX,XX @@ static gchar *riscv_gdb_arch_name(CPUState *cs)
38
@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_properties[] = {
48
}
39
DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
49
}
40
DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
50
41
DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
51
+static const char *riscv_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname)
42
+ DEFINE_PROP_UINT64("resetvec", RISCVCPU, cfg.resetvec, DEFAULT_RSTVEC),
52
+{
43
DEFINE_PROP_END_OF_LIST(),
53
+ RISCVCPU *cpu = RISCV_CPU(cs);
44
};
54
+
45
55
+ if (strcmp(xmlname, "riscv-csr.xml") == 0) {
56
+ return cpu->dyn_csr_xml;
57
+ }
58
+
59
+ return NULL;
60
+}
61
+
62
static void riscv_cpu_class_init(ObjectClass *c, void *data)
63
{
64
RISCVCPUClass *mcc = RISCV_CPU_CLASS(c);
65
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
66
cc->vmsd = &vmstate_riscv_cpu;
67
#endif
68
cc->gdb_arch_name = riscv_gdb_arch_name;
69
+ cc->gdb_get_dynamic_xml = riscv_gdb_get_dynamic_xml;
70
#ifdef CONFIG_TCG
71
cc->tcg_initialize = riscv_translate_init;
72
cc->tlb_fill = riscv_cpu_tlb_fill;
73
diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
74
index XXXXXXX..XXXXXXX 100644
75
--- a/target/riscv/gdbstub.c
76
+++ b/target/riscv/gdbstub.c
77
@@ -XXX,XX +XXX,XX @@
78
#include "exec/gdbstub.h"
79
#include "cpu.h"
80
81
-/*
82
- * The GDB CSR xml files list them in documentation order, not numerical order,
83
- * and are missing entries for unnamed CSRs. So we need to map the gdb numbers
84
- * to the hardware numbers.
85
- */
86
-
87
-static int csr_register_map[] = {
88
- CSR_USTATUS,
89
- CSR_UIE,
90
- CSR_UTVEC,
91
- CSR_USCRATCH,
92
- CSR_UEPC,
93
- CSR_UCAUSE,
94
- CSR_UTVAL,
95
- CSR_UIP,
96
- CSR_FFLAGS,
97
- CSR_FRM,
98
- CSR_FCSR,
99
- CSR_CYCLE,
100
- CSR_TIME,
101
- CSR_INSTRET,
102
- CSR_HPMCOUNTER3,
103
- CSR_HPMCOUNTER4,
104
- CSR_HPMCOUNTER5,
105
- CSR_HPMCOUNTER6,
106
- CSR_HPMCOUNTER7,
107
- CSR_HPMCOUNTER8,
108
- CSR_HPMCOUNTER9,
109
- CSR_HPMCOUNTER10,
110
- CSR_HPMCOUNTER11,
111
- CSR_HPMCOUNTER12,
112
- CSR_HPMCOUNTER13,
113
- CSR_HPMCOUNTER14,
114
- CSR_HPMCOUNTER15,
115
- CSR_HPMCOUNTER16,
116
- CSR_HPMCOUNTER17,
117
- CSR_HPMCOUNTER18,
118
- CSR_HPMCOUNTER19,
119
- CSR_HPMCOUNTER20,
120
- CSR_HPMCOUNTER21,
121
- CSR_HPMCOUNTER22,
122
- CSR_HPMCOUNTER23,
123
- CSR_HPMCOUNTER24,
124
- CSR_HPMCOUNTER25,
125
- CSR_HPMCOUNTER26,
126
- CSR_HPMCOUNTER27,
127
- CSR_HPMCOUNTER28,
128
- CSR_HPMCOUNTER29,
129
- CSR_HPMCOUNTER30,
130
- CSR_HPMCOUNTER31,
131
- CSR_CYCLEH,
132
- CSR_TIMEH,
133
- CSR_INSTRETH,
134
- CSR_HPMCOUNTER3H,
135
- CSR_HPMCOUNTER4H,
136
- CSR_HPMCOUNTER5H,
137
- CSR_HPMCOUNTER6H,
138
- CSR_HPMCOUNTER7H,
139
- CSR_HPMCOUNTER8H,
140
- CSR_HPMCOUNTER9H,
141
- CSR_HPMCOUNTER10H,
142
- CSR_HPMCOUNTER11H,
143
- CSR_HPMCOUNTER12H,
144
- CSR_HPMCOUNTER13H,
145
- CSR_HPMCOUNTER14H,
146
- CSR_HPMCOUNTER15H,
147
- CSR_HPMCOUNTER16H,
148
- CSR_HPMCOUNTER17H,
149
- CSR_HPMCOUNTER18H,
150
- CSR_HPMCOUNTER19H,
151
- CSR_HPMCOUNTER20H,
152
- CSR_HPMCOUNTER21H,
153
- CSR_HPMCOUNTER22H,
154
- CSR_HPMCOUNTER23H,
155
- CSR_HPMCOUNTER24H,
156
- CSR_HPMCOUNTER25H,
157
- CSR_HPMCOUNTER26H,
158
- CSR_HPMCOUNTER27H,
159
- CSR_HPMCOUNTER28H,
160
- CSR_HPMCOUNTER29H,
161
- CSR_HPMCOUNTER30H,
162
- CSR_HPMCOUNTER31H,
163
- CSR_SSTATUS,
164
- CSR_SEDELEG,
165
- CSR_SIDELEG,
166
- CSR_SIE,
167
- CSR_STVEC,
168
- CSR_SCOUNTEREN,
169
- CSR_SSCRATCH,
170
- CSR_SEPC,
171
- CSR_SCAUSE,
172
- CSR_STVAL,
173
- CSR_SIP,
174
- CSR_SATP,
175
- CSR_MVENDORID,
176
- CSR_MARCHID,
177
- CSR_MIMPID,
178
- CSR_MHARTID,
179
- CSR_MSTATUS,
180
- CSR_MISA,
181
- CSR_MEDELEG,
182
- CSR_MIDELEG,
183
- CSR_MIE,
184
- CSR_MTVEC,
185
- CSR_MCOUNTEREN,
186
- CSR_MSCRATCH,
187
- CSR_MEPC,
188
- CSR_MCAUSE,
189
- CSR_MTVAL,
190
- CSR_MIP,
191
- CSR_MTINST,
192
- CSR_MTVAL2,
193
- CSR_PMPCFG0,
194
- CSR_PMPCFG1,
195
- CSR_PMPCFG2,
196
- CSR_PMPCFG3,
197
- CSR_PMPADDR0,
198
- CSR_PMPADDR1,
199
- CSR_PMPADDR2,
200
- CSR_PMPADDR3,
201
- CSR_PMPADDR4,
202
- CSR_PMPADDR5,
203
- CSR_PMPADDR6,
204
- CSR_PMPADDR7,
205
- CSR_PMPADDR8,
206
- CSR_PMPADDR9,
207
- CSR_PMPADDR10,
208
- CSR_PMPADDR11,
209
- CSR_PMPADDR12,
210
- CSR_PMPADDR13,
211
- CSR_PMPADDR14,
212
- CSR_PMPADDR15,
213
- CSR_MCYCLE,
214
- CSR_MINSTRET,
215
- CSR_MHPMCOUNTER3,
216
- CSR_MHPMCOUNTER4,
217
- CSR_MHPMCOUNTER5,
218
- CSR_MHPMCOUNTER6,
219
- CSR_MHPMCOUNTER7,
220
- CSR_MHPMCOUNTER8,
221
- CSR_MHPMCOUNTER9,
222
- CSR_MHPMCOUNTER10,
223
- CSR_MHPMCOUNTER11,
224
- CSR_MHPMCOUNTER12,
225
- CSR_MHPMCOUNTER13,
226
- CSR_MHPMCOUNTER14,
227
- CSR_MHPMCOUNTER15,
228
- CSR_MHPMCOUNTER16,
229
- CSR_MHPMCOUNTER17,
230
- CSR_MHPMCOUNTER18,
231
- CSR_MHPMCOUNTER19,
232
- CSR_MHPMCOUNTER20,
233
- CSR_MHPMCOUNTER21,
234
- CSR_MHPMCOUNTER22,
235
- CSR_MHPMCOUNTER23,
236
- CSR_MHPMCOUNTER24,
237
- CSR_MHPMCOUNTER25,
238
- CSR_MHPMCOUNTER26,
239
- CSR_MHPMCOUNTER27,
240
- CSR_MHPMCOUNTER28,
241
- CSR_MHPMCOUNTER29,
242
- CSR_MHPMCOUNTER30,
243
- CSR_MHPMCOUNTER31,
244
- CSR_MCYCLEH,
245
- CSR_MINSTRETH,
246
- CSR_MHPMCOUNTER3H,
247
- CSR_MHPMCOUNTER4H,
248
- CSR_MHPMCOUNTER5H,
249
- CSR_MHPMCOUNTER6H,
250
- CSR_MHPMCOUNTER7H,
251
- CSR_MHPMCOUNTER8H,
252
- CSR_MHPMCOUNTER9H,
253
- CSR_MHPMCOUNTER10H,
254
- CSR_MHPMCOUNTER11H,
255
- CSR_MHPMCOUNTER12H,
256
- CSR_MHPMCOUNTER13H,
257
- CSR_MHPMCOUNTER14H,
258
- CSR_MHPMCOUNTER15H,
259
- CSR_MHPMCOUNTER16H,
260
- CSR_MHPMCOUNTER17H,
261
- CSR_MHPMCOUNTER18H,
262
- CSR_MHPMCOUNTER19H,
263
- CSR_MHPMCOUNTER20H,
264
- CSR_MHPMCOUNTER21H,
265
- CSR_MHPMCOUNTER22H,
266
- CSR_MHPMCOUNTER23H,
267
- CSR_MHPMCOUNTER24H,
268
- CSR_MHPMCOUNTER25H,
269
- CSR_MHPMCOUNTER26H,
270
- CSR_MHPMCOUNTER27H,
271
- CSR_MHPMCOUNTER28H,
272
- CSR_MHPMCOUNTER29H,
273
- CSR_MHPMCOUNTER30H,
274
- CSR_MHPMCOUNTER31H,
275
- CSR_MHPMEVENT3,
276
- CSR_MHPMEVENT4,
277
- CSR_MHPMEVENT5,
278
- CSR_MHPMEVENT6,
279
- CSR_MHPMEVENT7,
280
- CSR_MHPMEVENT8,
281
- CSR_MHPMEVENT9,
282
- CSR_MHPMEVENT10,
283
- CSR_MHPMEVENT11,
284
- CSR_MHPMEVENT12,
285
- CSR_MHPMEVENT13,
286
- CSR_MHPMEVENT14,
287
- CSR_MHPMEVENT15,
288
- CSR_MHPMEVENT16,
289
- CSR_MHPMEVENT17,
290
- CSR_MHPMEVENT18,
291
- CSR_MHPMEVENT19,
292
- CSR_MHPMEVENT20,
293
- CSR_MHPMEVENT21,
294
- CSR_MHPMEVENT22,
295
- CSR_MHPMEVENT23,
296
- CSR_MHPMEVENT24,
297
- CSR_MHPMEVENT25,
298
- CSR_MHPMEVENT26,
299
- CSR_MHPMEVENT27,
300
- CSR_MHPMEVENT28,
301
- CSR_MHPMEVENT29,
302
- CSR_MHPMEVENT30,
303
- CSR_MHPMEVENT31,
304
- CSR_TSELECT,
305
- CSR_TDATA1,
306
- CSR_TDATA2,
307
- CSR_TDATA3,
308
- CSR_DCSR,
309
- CSR_DPC,
310
- CSR_DSCRATCH,
311
- CSR_HSTATUS,
312
- CSR_HEDELEG,
313
- CSR_HIDELEG,
314
- CSR_HIE,
315
- CSR_HCOUNTEREN,
316
- CSR_HTVAL,
317
- CSR_HIP,
318
- CSR_HTINST,
319
- CSR_HGATP,
320
- CSR_MBASE,
321
- CSR_MBOUND,
322
- CSR_MIBASE,
323
- CSR_MIBOUND,
324
- CSR_MDBASE,
325
- CSR_MDBOUND,
326
- CSR_MUCOUNTEREN,
327
- CSR_MSCOUNTEREN,
328
- CSR_MHCOUNTEREN,
329
-};
330
-
331
int riscv_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
332
{
333
RISCVCPU *cpu = RISCV_CPU(cs);
334
@@ -XXX,XX +XXX,XX @@ static int riscv_gdb_get_fpu(CPURISCVState *env, GByteArray *buf, int n)
335
target_ulong val = 0;
336
int result;
337
/*
338
- * CSR_FFLAGS is at index 8 in csr_register, and gdb says it is FP
339
+ * CSR_FFLAGS is at index 1 in csr_register, and gdb says it is FP
340
* register 33, so we recalculate the map index.
341
* This also works for CSR_FRM and CSR_FCSR.
342
*/
343
- result = riscv_csrrw_debug(env, n - 33 + csr_register_map[8], &val,
344
+ result = riscv_csrrw_debug(env, n - 32, &val,
345
0, 0);
346
if (result == 0) {
347
return gdb_get_regl(buf, val);
348
@@ -XXX,XX +XXX,XX @@ static int riscv_gdb_set_fpu(CPURISCVState *env, uint8_t *mem_buf, int n)
349
target_ulong val = ldtul_p(mem_buf);
350
int result;
351
/*
352
- * CSR_FFLAGS is at index 8 in csr_register, and gdb says it is FP
353
+ * CSR_FFLAGS is at index 1 in csr_register, and gdb says it is FP
354
* register 33, so we recalculate the map index.
355
* This also works for CSR_FRM and CSR_FCSR.
356
*/
357
- result = riscv_csrrw_debug(env, n - 33 + csr_register_map[8], NULL,
358
+ result = riscv_csrrw_debug(env, n - 32, NULL,
359
val, -1);
360
if (result == 0) {
361
return sizeof(target_ulong);
362
@@ -XXX,XX +XXX,XX @@ static int riscv_gdb_set_fpu(CPURISCVState *env, uint8_t *mem_buf, int n)
363
364
static int riscv_gdb_get_csr(CPURISCVState *env, GByteArray *buf, int n)
365
{
366
- if (n < ARRAY_SIZE(csr_register_map)) {
367
+ if (n < CSR_TABLE_SIZE) {
368
target_ulong val = 0;
369
int result;
370
371
- result = riscv_csrrw_debug(env, csr_register_map[n], &val, 0, 0);
372
+ result = riscv_csrrw_debug(env, n, &val, 0, 0);
373
if (result == 0) {
374
return gdb_get_regl(buf, val);
375
}
376
@@ -XXX,XX +XXX,XX @@ static int riscv_gdb_get_csr(CPURISCVState *env, GByteArray *buf, int n)
377
378
static int riscv_gdb_set_csr(CPURISCVState *env, uint8_t *mem_buf, int n)
379
{
380
- if (n < ARRAY_SIZE(csr_register_map)) {
381
+ if (n < CSR_TABLE_SIZE) {
382
target_ulong val = ldtul_p(mem_buf);
383
int result;
384
385
- result = riscv_csrrw_debug(env, csr_register_map[n], NULL, val, -1);
386
+ result = riscv_csrrw_debug(env, n, NULL, val, -1);
387
if (result == 0) {
388
return sizeof(target_ulong);
389
}
390
@@ -XXX,XX +XXX,XX @@ static int riscv_gdb_set_virtual(CPURISCVState *cs, uint8_t *mem_buf, int n)
391
return 0;
392
}
393
394
+static int riscv_gen_dynamic_csr_xml(CPUState *cs, int base_reg)
395
+{
396
+ RISCVCPU *cpu = RISCV_CPU(cs);
397
+ CPURISCVState *env = &cpu->env;
398
+ GString *s = g_string_new(NULL);
399
+ riscv_csr_predicate_fn predicate;
400
+ int bitsize = riscv_cpu_is_32bit(env) ? 32 : 64;
401
+ int i;
402
+
403
+ g_string_printf(s, "<?xml version=\"1.0\"?>");
404
+ g_string_append_printf(s, "<!DOCTYPE feature SYSTEM \"gdb-target.dtd\">");
405
+ g_string_append_printf(s, "<feature name=\"org.gnu.gdb.riscv.csr\">");
406
+
407
+ for (i = 0; i < CSR_TABLE_SIZE; i++) {
408
+ predicate = csr_ops[i].predicate;
409
+ if (predicate && !predicate(env, i)) {
410
+ if (csr_ops[i].name) {
411
+ g_string_append_printf(s, "<reg name=\"%s\"", csr_ops[i].name);
412
+ } else {
413
+ g_string_append_printf(s, "<reg name=\"csr%03x\"", i);
414
+ }
415
+ g_string_append_printf(s, " bitsize=\"%d\"", bitsize);
416
+ g_string_append_printf(s, " regnum=\"%d\"/>", base_reg + i);
417
+ }
418
+ }
419
+
420
+ g_string_append_printf(s, "</feature>");
421
+
422
+ cpu->dyn_csr_xml = g_string_free(s, false);
423
+ return CSR_TABLE_SIZE;
424
+}
425
+
426
void riscv_cpu_register_gdb_regs_for_features(CPUState *cs)
427
{
428
RISCVCPU *cpu = RISCV_CPU(cs);
429
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs)
430
36, "riscv-32bit-fpu.xml", 0);
431
}
432
#if defined(TARGET_RISCV32)
433
- gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr,
434
- 240, "riscv-32bit-csr.xml", 0);
435
-
436
gdb_register_coprocessor(cs, riscv_gdb_get_virtual, riscv_gdb_set_virtual,
437
1, "riscv-32bit-virtual.xml", 0);
438
#elif defined(TARGET_RISCV64)
439
- gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr,
440
- 240, "riscv-64bit-csr.xml", 0);
441
-
442
gdb_register_coprocessor(cs, riscv_gdb_get_virtual, riscv_gdb_set_virtual,
443
1, "riscv-64bit-virtual.xml", 0);
444
#endif
445
+
446
+ gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr,
447
+ riscv_gen_dynamic_csr_xml(cs, cs->gdb_num_regs),
448
+ "riscv-csr.xml", 0);
449
}
450
--
46
--
451
2.29.2
47
2.28.0
452
48
453
49
diff view generated by jsdifflib
New patch
[PULL 04/30] hw/riscv: hart: Add a new 'resetvec' property
1
From: Bin Meng <bin.meng@windriver.com>
1
2
3
RISC-V machines do not instantiate RISC-V CPUs directly, instead
4
they do that via the hart array. Add a new property for the reset
5
vector address to allow the value to be passed to the CPU, before
6
CPU is realized.
7
8
Signed-off-by: Bin Meng <bin.meng@windriver.com>
9
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
10
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
11
Message-Id: <1598924352-89526-3-git-send-email-bmeng.cn@gmail.com>
12
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
13
---
14
include/hw/riscv/riscv_hart.h | 1 +
15
hw/riscv/riscv_hart.c | 3 +++
16
2 files changed, 4 insertions(+)
17
18
diff --git a/include/hw/riscv/riscv_hart.h b/include/hw/riscv/riscv_hart.h
19
index XXXXXXX..XXXXXXX 100644
20
--- a/include/hw/riscv/riscv_hart.h
21
+++ b/include/hw/riscv/riscv_hart.h
22
@@ -XXX,XX +XXX,XX @@ typedef struct RISCVHartArrayState {
23
uint32_t num_harts;
24
uint32_t hartid_base;
25
char *cpu_type;
26
+ uint64_t resetvec;
27
RISCVCPU *harts;
28
} RISCVHartArrayState;
29
30
diff --git a/hw/riscv/riscv_hart.c b/hw/riscv/riscv_hart.c
31
index XXXXXXX..XXXXXXX 100644
32
--- a/hw/riscv/riscv_hart.c
33
+++ b/hw/riscv/riscv_hart.c
34
@@ -XXX,XX +XXX,XX @@ static Property riscv_harts_props[] = {
35
DEFINE_PROP_UINT32("num-harts", RISCVHartArrayState, num_harts, 1),
36
DEFINE_PROP_UINT32("hartid-base", RISCVHartArrayState, hartid_base, 0),
37
DEFINE_PROP_STRING("cpu-type", RISCVHartArrayState, cpu_type),
38
+ DEFINE_PROP_UINT64("resetvec", RISCVHartArrayState, resetvec,
39
+ DEFAULT_RSTVEC),
40
DEFINE_PROP_END_OF_LIST(),
41
};
42
43
@@ -XXX,XX +XXX,XX @@ static bool riscv_hart_realize(RISCVHartArrayState *s, int idx,
44
char *cpu_type, Error **errp)
45
{
46
object_initialize_child(OBJECT(s), "harts[*]", &s->harts[idx], cpu_type);
47
+ qdev_prop_set_uint64(DEVICE(&s->harts[idx]), "resetvec", s->resetvec);
48
s->harts[idx].env.mhartid = s->hartid_base + idx;
49
qemu_register_reset(riscv_harts_cpu_reset, &s->harts[idx]);
50
return qdev_realize(DEVICE(&s->harts[idx]), NULL, errp);
51
--
52
2.28.0
53
54
diff view generated by jsdifflib
New patch
[PULL 05/30] target/riscv: cpu: Set reset vector based on the configured property value
1
From: Bin Meng <bin.meng@windriver.com>
1
2
3
Now that we have the newly introduced 'resetvec' property in the
4
RISC-V CPU and HART, instead of hard-coding the reset vector addr
5
in the CPU's instance_init(), move that to riscv_cpu_realize()
6
based on the configured property value from the RISC-V machines.
7
8
Signed-off-by: Bin Meng <bin.meng@windriver.com>
9
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
10
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
11
Message-Id: <1598924352-89526-4-git-send-email-bmeng.cn@gmail.com>
12
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
13
---
14
hw/riscv/opentitan.c | 1 +
15
hw/riscv/sifive_e.c | 1 +
16
hw/riscv/sifive_u.c | 2 ++
17
target/riscv/cpu.c | 7 ++-----
18
4 files changed, 6 insertions(+), 5 deletions(-)
19
20
diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
21
index XXXXXXX..XXXXXXX 100644
22
--- a/hw/riscv/opentitan.c
23
+++ b/hw/riscv/opentitan.c
24
@@ -XXX,XX +XXX,XX @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
25
&error_abort);
26
object_property_set_int(OBJECT(&s->cpus), "num-harts", ms->smp.cpus,
27
&error_abort);
28
+ object_property_set_int(OBJECT(&s->cpus), "resetvec", 0x8090, &error_abort);
29
sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_abort);
30
31
/* Boot ROM */
32
diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
33
index XXXXXXX..XXXXXXX 100644
34
--- a/hw/riscv/sifive_e.c
35
+++ b/hw/riscv/sifive_e.c
36
@@ -XXX,XX +XXX,XX @@ static void sifive_e_soc_init(Object *obj)
37
object_initialize_child(obj, "cpus", &s->cpus, TYPE_RISCV_HART_ARRAY);
38
object_property_set_int(OBJECT(&s->cpus), "num-harts", ms->smp.cpus,
39
&error_abort);
40
+ object_property_set_int(OBJECT(&s->cpus), "resetvec", 0x1004, &error_abort);
41
object_initialize_child(obj, "riscv.sifive.e.gpio0", &s->gpio,
42
TYPE_SIFIVE_GPIO);
43
}
44
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
45
index XXXXXXX..XXXXXXX 100644
46
--- a/hw/riscv/sifive_u.c
47
+++ b/hw/riscv/sifive_u.c
48
@@ -XXX,XX +XXX,XX @@ static void sifive_u_soc_instance_init(Object *obj)
49
qdev_prop_set_uint32(DEVICE(&s->e_cpus), "num-harts", 1);
50
qdev_prop_set_uint32(DEVICE(&s->e_cpus), "hartid-base", 0);
51
qdev_prop_set_string(DEVICE(&s->e_cpus), "cpu-type", SIFIVE_E_CPU);
52
+ qdev_prop_set_uint64(DEVICE(&s->e_cpus), "resetvec", 0x1004);
53
54
object_initialize_child(obj, "u-cluster", &s->u_cluster, TYPE_CPU_CLUSTER);
55
qdev_prop_set_uint32(DEVICE(&s->u_cluster), "cluster-id", 1);
56
@@ -XXX,XX +XXX,XX @@ static void sifive_u_soc_instance_init(Object *obj)
57
qdev_prop_set_uint32(DEVICE(&s->u_cpus), "num-harts", ms->smp.cpus - 1);
58
qdev_prop_set_uint32(DEVICE(&s->u_cpus), "hartid-base", 1);
59
qdev_prop_set_string(DEVICE(&s->u_cpus), "cpu-type", SIFIVE_U_CPU);
60
+ qdev_prop_set_uint64(DEVICE(&s->u_cpus), "resetvec", 0x1004);
61
62
object_initialize_child(obj, "prci", &s->prci, TYPE_SIFIVE_U_PRCI);
63
object_initialize_child(obj, "otp", &s->otp, TYPE_SIFIVE_U_OTP);
64
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
65
index XXXXXXX..XXXXXXX 100644
66
--- a/target/riscv/cpu.c
67
+++ b/target/riscv/cpu.c
68
@@ -XXX,XX +XXX,XX @@ static void riscv_any_cpu_init(Object *obj)
69
CPURISCVState *env = &RISCV_CPU(obj)->env;
70
set_misa(env, RVXLEN | RVI | RVM | RVA | RVF | RVD | RVC | RVU);
71
set_priv_version(env, PRIV_VERSION_1_11_0);
72
- set_resetvec(env, DEFAULT_RSTVEC);
73
}
74
75
static void riscv_base_cpu_init(Object *obj)
76
@@ -XXX,XX +XXX,XX @@ static void riscv_base_cpu_init(Object *obj)
77
CPURISCVState *env = &RISCV_CPU(obj)->env;
78
/* We set this in the realise function */
79
set_misa(env, 0);
80
- set_resetvec(env, DEFAULT_RSTVEC);
81
}
82
83
static void rvxx_sifive_u_cpu_init(Object *obj)
84
@@ -XXX,XX +XXX,XX @@ static void rvxx_sifive_u_cpu_init(Object *obj)
85
CPURISCVState *env = &RISCV_CPU(obj)->env;
86
set_misa(env, RVXLEN | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
87
set_priv_version(env, PRIV_VERSION_1_10_0);
88
- set_resetvec(env, 0x1004);
89
}
90
91
static void rvxx_sifive_e_cpu_init(Object *obj)
92
@@ -XXX,XX +XXX,XX @@ static void rvxx_sifive_e_cpu_init(Object *obj)
93
CPURISCVState *env = &RISCV_CPU(obj)->env;
94
set_misa(env, RVXLEN | RVI | RVM | RVA | RVC | RVU);
95
set_priv_version(env, PRIV_VERSION_1_10_0);
96
- set_resetvec(env, 0x1004);
97
qdev_prop_set_bit(DEVICE(obj), "mmu", false);
98
}
99
100
@@ -XXX,XX +XXX,XX @@ static void rv32_ibex_cpu_init(Object *obj)
101
CPURISCVState *env = &RISCV_CPU(obj)->env;
102
set_misa(env, RV32 | RVI | RVM | RVC | RVU);
103
set_priv_version(env, PRIV_VERSION_1_10_0);
104
- set_resetvec(env, 0x8090);
105
qdev_prop_set_bit(DEVICE(obj), "mmu", false);
106
}
107
108
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
109
set_feature(env, RISCV_FEATURE_PMP);
110
}
111
112
+ set_resetvec(env, cpu->cfg.resetvec);
113
+
114
/* If misa isn't set (rv32 and rv64 machines) set it here */
115
if (!env->misa) {
116
/* Do some ISA extension error checking */
117
--
118
2.28.0
119
120
diff view generated by jsdifflib
New patch
[PULL 06/30] hw/riscv: Initial support for Microchip PolarFire SoC Icicle Kit board
1
1
From: Bin Meng <bin.meng@windriver.com>
2
3
This is an initial support for Microchip PolarFire SoC Icicle Kit.
4
The Icicle Kit board integrates a PolarFire SoC, with one SiFive's
5
E51 plus four U54 cores and many on-chip peripherals and an FPGA.
6
7
For more details about Microchip PolarFire Soc, please see:
8
https://www.microsemi.com/product-directory/soc-fpgas/5498-polarfire-soc-fpga
9
10
Unlike SiFive FU540, the RISC-V core resect vector is at 0x20220000.
11
The following perepherals are created as an unimplemented device:
12
13
- Bus Error Uint 0/1/2/3/4
14
- L2 cache controller
15
- SYSREG
16
- MPUCFG
17
- IOSCBCFG
18
19
More devices will be added later.
20
21
The BIOS image used by this machine is hss.bin, aka Hart Software
22
Services, which can be built from:
23
https://github.com/polarfire-soc/hart-software-services
24
25
To launch this machine:
26
$ qemu-system-riscv64 -nographic -M microchip-icicle-kit
27
28
The memory is set to 1 GiB by default to match the hardware.
29
A sanity check on ram size is performed in the machine init routine
30
to prompt user to increase the RAM size to > 1 GiB when less than
31
1 GiB ram is detected.
32
33
Signed-off-by: Bin Meng <bin.meng@windriver.com>
34
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
35
Message-Id: <1598924352-89526-5-git-send-email-bmeng.cn@gmail.com>
36
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
37
---
38
default-configs/riscv64-softmmu.mak | 1 +
39
include/hw/riscv/microchip_pfsoc.h | 88 ++++++++
40
hw/riscv/microchip_pfsoc.c | 312 ++++++++++++++++++++++++++++
41
MAINTAINERS | 7 +
42
hw/riscv/Kconfig | 6 +
43
hw/riscv/meson.build | 1 +
44
6 files changed, 415 insertions(+)
45
create mode 100644 include/hw/riscv/microchip_pfsoc.h
46
create mode 100644 hw/riscv/microchip_pfsoc.c
47
48
diff --git a/default-configs/riscv64-softmmu.mak b/default-configs/riscv64-softmmu.mak
49
index XXXXXXX..XXXXXXX 100644
50
--- a/default-configs/riscv64-softmmu.mak
51
+++ b/default-configs/riscv64-softmmu.mak
52
@@ -XXX,XX +XXX,XX @@ CONFIG_SPIKE=y
53
CONFIG_SIFIVE_E=y
54
CONFIG_SIFIVE_U=y
55
CONFIG_RISCV_VIRT=y
56
+CONFIG_MICROCHIP_PFSOC=y
57
diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h
58
new file mode 100644
59
index XXXXXXX..XXXXXXX
60
--- /dev/null
61
+++ b/include/hw/riscv/microchip_pfsoc.h
62
@@ -XXX,XX +XXX,XX @@
63
+/*
64
+ * Microchip PolarFire SoC machine interface
65
+ *
66
+ * Copyright (c) 2020 Wind River Systems, Inc.
67
+ *
68
+ * Author:
69
+ * Bin Meng <bin.meng@windriver.com>
70
+ *
71
+ * This program is free software; you can redistribute it and/or modify it
72
+ * under the terms and conditions of the GNU General Public License,
73
+ * version 2 or later, as published by the Free Software Foundation.
74
+ *
75
+ * This program is distributed in the hope it will be useful, but WITHOUT
76
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
77
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
78
+ * more details.
79
+ *
80
+ * You should have received a copy of the GNU General Public License along with
81
+ * this program. If not, see <http://www.gnu.org/licenses/>.
82
+ */
83
+
84
+#ifndef HW_MICROCHIP_PFSOC_H
85
+#define HW_MICROCHIP_PFSOC_H
86
+
87
+typedef struct MicrochipPFSoCState {
88
+ /*< private >*/
89
+ DeviceState parent_obj;
90
+
91
+ /*< public >*/
92
+ CPUClusterState e_cluster;
93
+ CPUClusterState u_cluster;
94
+ RISCVHartArrayState e_cpus;
95
+ RISCVHartArrayState u_cpus;
96
+ DeviceState *plic;
97
+} MicrochipPFSoCState;
98
+
99
+#define TYPE_MICROCHIP_PFSOC "microchip.pfsoc"
100
+#define MICROCHIP_PFSOC(obj) \
101
+ OBJECT_CHECK(MicrochipPFSoCState, (obj), TYPE_MICROCHIP_PFSOC)
102
+
103
+typedef struct MicrochipIcicleKitState {
104
+ /*< private >*/
105
+ MachineState parent_obj;
106
+
107
+ /*< public >*/
108
+ MicrochipPFSoCState soc;
109
+} MicrochipIcicleKitState;
110
+
111
+#define TYPE_MICROCHIP_ICICLE_KIT_MACHINE \
112
+ MACHINE_TYPE_NAME("microchip-icicle-kit")
113
+#define MICROCHIP_ICICLE_KIT_MACHINE(obj) \
114
+ OBJECT_CHECK(MicrochipIcicleKitState, (obj), \
115
+ TYPE_MICROCHIP_ICICLE_KIT_MACHINE)
116
+
117
+enum {
118
+ MICROCHIP_PFSOC_DEBUG,
119
+ MICROCHIP_PFSOC_E51_DTIM,
120
+ MICROCHIP_PFSOC_BUSERR_UNIT0,
121
+ MICROCHIP_PFSOC_BUSERR_UNIT1,
122
+ MICROCHIP_PFSOC_BUSERR_UNIT2,
123
+ MICROCHIP_PFSOC_BUSERR_UNIT3,
124
+ MICROCHIP_PFSOC_BUSERR_UNIT4,
125
+ MICROCHIP_PFSOC_CLINT,
126
+ MICROCHIP_PFSOC_L2CC,
127
+ MICROCHIP_PFSOC_L2LIM,
128
+ MICROCHIP_PFSOC_PLIC,
129
+ MICROCHIP_PFSOC_SYSREG,
130
+ MICROCHIP_PFSOC_MPUCFG,
131
+ MICROCHIP_PFSOC_ENVM_CFG,
132
+ MICROCHIP_PFSOC_ENVM_DATA,
133
+ MICROCHIP_PFSOC_IOSCB_CFG,
134
+ MICROCHIP_PFSOC_DRAM,
135
+};
136
+
137
+#define MICROCHIP_PFSOC_MANAGEMENT_CPU_COUNT 1
138
+#define MICROCHIP_PFSOC_COMPUTE_CPU_COUNT 4
139
+
140
+#define MICROCHIP_PFSOC_PLIC_HART_CONFIG "MS"
141
+#define MICROCHIP_PFSOC_PLIC_NUM_SOURCES 185
142
+#define MICROCHIP_PFSOC_PLIC_NUM_PRIORITIES 7
143
+#define MICROCHIP_PFSOC_PLIC_PRIORITY_BASE 0x04
144
+#define MICROCHIP_PFSOC_PLIC_PENDING_BASE 0x1000
145
+#define MICROCHIP_PFSOC_PLIC_ENABLE_BASE 0x2000
146
+#define MICROCHIP_PFSOC_PLIC_ENABLE_STRIDE 0x80
147
+#define MICROCHIP_PFSOC_PLIC_CONTEXT_BASE 0x200000
148
+#define MICROCHIP_PFSOC_PLIC_CONTEXT_STRIDE 0x1000
149
+
150
+#endif /* HW_MICROCHIP_PFSOC_H */
151
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
152
new file mode 100644
153
index XXXXXXX..XXXXXXX
154
--- /dev/null
155
+++ b/hw/riscv/microchip_pfsoc.c
156
@@ -XXX,XX +XXX,XX @@
157
+/*
158
+ * QEMU RISC-V Board Compatible with Microchip PolarFire SoC Icicle Kit
159
+ *
160
+ * Copyright (c) 2020 Wind River Systems, Inc.
161
+ *
162
+ * Author:
163
+ * Bin Meng <bin.meng@windriver.com>
164
+ *
165
+ * Provides a board compatible with the Microchip PolarFire SoC Icicle Kit
166
+ *
167
+ * 0) CLINT (Core Level Interruptor)
168
+ * 1) PLIC (Platform Level Interrupt Controller)
169
+ * 2) eNVM (Embedded Non-Volatile Memory)
170
+ *
171
+ * This board currently generates devicetree dynamically that indicates at least
172
+ * two harts and up to five harts.
173
+ *
174
+ * This program is free software; you can redistribute it and/or modify it
175
+ * under the terms and conditions of the GNU General Public License,
176
+ * version 2 or later, as published by the Free Software Foundation.
177
+ *
178
+ * This program is distributed in the hope it will be useful, but WITHOUT
179
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
180
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
181
+ * more details.
182
+ *
183
+ * You should have received a copy of the GNU General Public License along with
184
+ * this program. If not, see <http://www.gnu.org/licenses/>.
185
+ */
186
+
187
+#include "qemu/osdep.h"
188
+#include "qemu/error-report.h"
189
+#include "qemu/log.h"
190
+#include "qemu/units.h"
191
+#include "qemu/cutils.h"
192
+#include "qapi/error.h"
193
+#include "hw/boards.h"
194
+#include "hw/irq.h"
195
+#include "hw/loader.h"
196
+#include "hw/sysbus.h"
197
+#include "hw/cpu/cluster.h"
198
+#include "target/riscv/cpu.h"
199
+#include "hw/misc/unimp.h"
200
+#include "hw/riscv/boot.h"
201
+#include "hw/riscv/riscv_hart.h"
202
+#include "hw/riscv/sifive_clint.h"
203
+#include "hw/riscv/sifive_plic.h"
204
+#include "hw/riscv/microchip_pfsoc.h"
205
+
206
+/*
207
+ * The BIOS image used by this machine is called Hart Software Services (HSS).
208
+ * See https://github.com/polarfire-soc/hart-software-services
209
+ */
210
+#define BIOS_FILENAME "hss.bin"
211
+#define RESET_VECTOR 0x20220000
212
+
213
+static const struct MemmapEntry {
214
+ hwaddr base;
215
+ hwaddr size;
216
+} microchip_pfsoc_memmap[] = {
217
+ [MICROCHIP_PFSOC_DEBUG] = { 0x0, 0x1000 },
218
+ [MICROCHIP_PFSOC_E51_DTIM] = { 0x1000000, 0x2000 },
219
+ [MICROCHIP_PFSOC_BUSERR_UNIT0] = { 0x1700000, 0x1000 },
220
+ [MICROCHIP_PFSOC_BUSERR_UNIT1] = { 0x1701000, 0x1000 },
221
+ [MICROCHIP_PFSOC_BUSERR_UNIT2] = { 0x1702000, 0x1000 },
222
+ [MICROCHIP_PFSOC_BUSERR_UNIT3] = { 0x1703000, 0x1000 },
223
+ [MICROCHIP_PFSOC_BUSERR_UNIT4] = { 0x1704000, 0x1000 },
224
+ [MICROCHIP_PFSOC_CLINT] = { 0x2000000, 0x10000 },
225
+ [MICROCHIP_PFSOC_L2CC] = { 0x2010000, 0x1000 },
226
+ [MICROCHIP_PFSOC_L2LIM] = { 0x8000000, 0x2000000 },
227
+ [MICROCHIP_PFSOC_PLIC] = { 0xc000000, 0x4000000 },
228
+ [MICROCHIP_PFSOC_SYSREG] = { 0x20002000, 0x2000 },
229
+ [MICROCHIP_PFSOC_MPUCFG] = { 0x20005000, 0x1000 },
230
+ [MICROCHIP_PFSOC_ENVM_CFG] = { 0x20200000, 0x1000 },
231
+ [MICROCHIP_PFSOC_ENVM_DATA] = { 0x20220000, 0x20000 },
232
+ [MICROCHIP_PFSOC_IOSCB_CFG] = { 0x37080000, 0x1000 },
233
+ [MICROCHIP_PFSOC_DRAM] = { 0x80000000, 0x0 },
234
+};
235
+
236
+static void microchip_pfsoc_soc_instance_init(Object *obj)
237
+{
238
+ MachineState *ms = MACHINE(qdev_get_machine());
239
+ MicrochipPFSoCState *s = MICROCHIP_PFSOC(obj);
240
+
241
+ object_initialize_child(obj, "e-cluster", &s->e_cluster, TYPE_CPU_CLUSTER);
242
+ qdev_prop_set_uint32(DEVICE(&s->e_cluster), "cluster-id", 0);
243
+
244
+ object_initialize_child(OBJECT(&s->e_cluster), "e-cpus", &s->e_cpus,
245
+ TYPE_RISCV_HART_ARRAY);
246
+ qdev_prop_set_uint32(DEVICE(&s->e_cpus), "num-harts", 1);
247
+ qdev_prop_set_uint32(DEVICE(&s->e_cpus), "hartid-base", 0);
248
+ qdev_prop_set_string(DEVICE(&s->e_cpus), "cpu-type",
249
+ TYPE_RISCV_CPU_SIFIVE_E51);
250
+ qdev_prop_set_uint64(DEVICE(&s->e_cpus), "resetvec", RESET_VECTOR);
251
+
252
+ object_initialize_child(obj, "u-cluster", &s->u_cluster, TYPE_CPU_CLUSTER);
253
+ qdev_prop_set_uint32(DEVICE(&s->u_cluster), "cluster-id", 1);
254
+
255
+ object_initialize_child(OBJECT(&s->u_cluster), "u-cpus", &s->u_cpus,
256
+ TYPE_RISCV_HART_ARRAY);
257
+ qdev_prop_set_uint32(DEVICE(&s->u_cpus), "num-harts", ms->smp.cpus - 1);
258
+ qdev_prop_set_uint32(DEVICE(&s->u_cpus), "hartid-base", 1);
259
+ qdev_prop_set_string(DEVICE(&s->u_cpus), "cpu-type",
260
+ TYPE_RISCV_CPU_SIFIVE_U54);
261
+ qdev_prop_set_uint64(DEVICE(&s->u_cpus), "resetvec", RESET_VECTOR);
262
+}
263
+
264
+static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
265
+{
266
+ MachineState *ms = MACHINE(qdev_get_machine());
267
+ MicrochipPFSoCState *s = MICROCHIP_PFSOC(dev);
268
+ const struct MemmapEntry *memmap = microchip_pfsoc_memmap;
269
+ MemoryRegion *system_memory = get_system_memory();
270
+ MemoryRegion *e51_dtim_mem = g_new(MemoryRegion, 1);
271
+ MemoryRegion *l2lim_mem = g_new(MemoryRegion, 1);
272
+ MemoryRegion *envm_data = g_new(MemoryRegion, 1);
273
+ char *plic_hart_config;
274
+ size_t plic_hart_config_len;
275
+ int i;
276
+
277
+ sysbus_realize(SYS_BUS_DEVICE(&s->e_cpus), &error_abort);
278
+ sysbus_realize(SYS_BUS_DEVICE(&s->u_cpus), &error_abort);
279
+ /*
280
+ * The cluster must be realized after the RISC-V hart array container,
281
+ * as the container's CPU object is only created on realize, and the
282
+ * CPU must exist and have been parented into the cluster before the
283
+ * cluster is realized.
284
+ */
285
+ qdev_realize(DEVICE(&s->e_cluster), NULL, &error_abort);
286
+ qdev_realize(DEVICE(&s->u_cluster), NULL, &error_abort);
287
+
288
+ /* E51 DTIM */
289
+ memory_region_init_ram(e51_dtim_mem, NULL, "microchip.pfsoc.e51_dtim_mem",
290
+ memmap[MICROCHIP_PFSOC_E51_DTIM].size, &error_fatal);
291
+ memory_region_add_subregion(system_memory,
292
+ memmap[MICROCHIP_PFSOC_E51_DTIM].base,
293
+ e51_dtim_mem);
294
+
295
+ /* Bus Error Units */
296
+ create_unimplemented_device("microchip.pfsoc.buserr_unit0_mem",
297
+ memmap[MICROCHIP_PFSOC_BUSERR_UNIT0].base,
298
+ memmap[MICROCHIP_PFSOC_BUSERR_UNIT0].size);
299
+ create_unimplemented_device("microchip.pfsoc.buserr_unit1_mem",
300
+ memmap[MICROCHIP_PFSOC_BUSERR_UNIT1].base,
301
+ memmap[MICROCHIP_PFSOC_BUSERR_UNIT1].size);
302
+ create_unimplemented_device("microchip.pfsoc.buserr_unit2_mem",
303
+ memmap[MICROCHIP_PFSOC_BUSERR_UNIT2].base,
304
+ memmap[MICROCHIP_PFSOC_BUSERR_UNIT2].size);
305
+ create_unimplemented_device("microchip.pfsoc.buserr_unit3_mem",
306
+ memmap[MICROCHIP_PFSOC_BUSERR_UNIT3].base,
307
+ memmap[MICROCHIP_PFSOC_BUSERR_UNIT3].size);
308
+ create_unimplemented_device("microchip.pfsoc.buserr_unit4_mem",
309
+ memmap[MICROCHIP_PFSOC_BUSERR_UNIT4].base,
310
+ memmap[MICROCHIP_PFSOC_BUSERR_UNIT4].size);
311
+
312
+ /* CLINT */
313
+ sifive_clint_create(memmap[MICROCHIP_PFSOC_CLINT].base,
314
+ memmap[MICROCHIP_PFSOC_CLINT].size, 0, ms->smp.cpus,
315
+ SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, false);
316
+
317
+ /* L2 cache controller */
318
+ create_unimplemented_device("microchip.pfsoc.l2cc",
319
+ memmap[MICROCHIP_PFSOC_L2CC].base, memmap[MICROCHIP_PFSOC_L2CC].size);
320
+
321
+ /*
322
+ * Add L2-LIM at reset size.
323
+ * This should be reduced in size as the L2 Cache Controller WayEnable
324
+ * register is incremented. Unfortunately I don't see a nice (or any) way
325
+ * to handle reducing or blocking out the L2 LIM while still allowing it
326
+ * be re returned to all enabled after a reset. For the time being, just
327
+ * leave it enabled all the time. This won't break anything, but will be
328
+ * too generous to misbehaving guests.
329
+ */
330
+ memory_region_init_ram(l2lim_mem, NULL, "microchip.pfsoc.l2lim",
331
+ memmap[MICROCHIP_PFSOC_L2LIM].size, &error_fatal);
332
+ memory_region_add_subregion(system_memory,
333
+ memmap[MICROCHIP_PFSOC_L2LIM].base,
334
+ l2lim_mem);
335
+
336
+ /* create PLIC hart topology configuration string */
337
+ plic_hart_config_len = (strlen(MICROCHIP_PFSOC_PLIC_HART_CONFIG) + 1) *
338
+ ms->smp.cpus;
339
+ plic_hart_config = g_malloc0(plic_hart_config_len);
340
+ for (i = 0; i < ms->smp.cpus; i++) {
341
+ if (i != 0) {
342
+ strncat(plic_hart_config, "," MICROCHIP_PFSOC_PLIC_HART_CONFIG,
343
+ plic_hart_config_len);
344
+ } else {
345
+ strncat(plic_hart_config, "M", plic_hart_config_len);
346
+ }
347
+ plic_hart_config_len -= (strlen(MICROCHIP_PFSOC_PLIC_HART_CONFIG) + 1);
348
+ }
349
+
350
+ /* PLIC */
351
+ s->plic = sifive_plic_create(memmap[MICROCHIP_PFSOC_PLIC].base,
352
+ plic_hart_config, 0,
353
+ MICROCHIP_PFSOC_PLIC_NUM_SOURCES,
354
+ MICROCHIP_PFSOC_PLIC_NUM_PRIORITIES,
355
+ MICROCHIP_PFSOC_PLIC_PRIORITY_BASE,
356
+ MICROCHIP_PFSOC_PLIC_PENDING_BASE,
357
+ MICROCHIP_PFSOC_PLIC_ENABLE_BASE,
358
+ MICROCHIP_PFSOC_PLIC_ENABLE_STRIDE,
359
+ MICROCHIP_PFSOC_PLIC_CONTEXT_BASE,
360
+ MICROCHIP_PFSOC_PLIC_CONTEXT_STRIDE,
361
+ memmap[MICROCHIP_PFSOC_PLIC].size);
362
+ g_free(plic_hart_config);
363
+
364
+ /* SYSREG */
365
+ create_unimplemented_device("microchip.pfsoc.sysreg",
366
+ memmap[MICROCHIP_PFSOC_SYSREG].base,
367
+ memmap[MICROCHIP_PFSOC_SYSREG].size);
368
+
369
+ /* MPUCFG */
370
+ create_unimplemented_device("microchip.pfsoc.mpucfg",
371
+ memmap[MICROCHIP_PFSOC_MPUCFG].base,
372
+ memmap[MICROCHIP_PFSOC_MPUCFG].size);
373
+
374
+ /* eNVM */
375
+ memory_region_init_rom(envm_data, OBJECT(dev), "microchip.pfsoc.envm.data",
376
+ memmap[MICROCHIP_PFSOC_ENVM_DATA].size,
377
+ &error_fatal);
378
+ memory_region_add_subregion(system_memory,
379
+ memmap[MICROCHIP_PFSOC_ENVM_DATA].base,
380
+ envm_data);
381
+
382
+ /* IOSCBCFG */
383
+ create_unimplemented_device("microchip.pfsoc.ioscb.cfg",
384
+ memmap[MICROCHIP_PFSOC_IOSCB_CFG].base,
385
+ memmap[MICROCHIP_PFSOC_IOSCB_CFG].size);
386
+}
387
+
388
+static void microchip_pfsoc_soc_class_init(ObjectClass *oc, void *data)
389
+{
390
+ DeviceClass *dc = DEVICE_CLASS(oc);
391
+
392
+ dc->realize = microchip_pfsoc_soc_realize;
393
+ /* Reason: Uses serial_hds in realize function, thus can't be used twice */
394
+ dc->user_creatable = false;
395
+}
396
+
397
+static const TypeInfo microchip_pfsoc_soc_type_info = {
398
+ .name = TYPE_MICROCHIP_PFSOC,
399
+ .parent = TYPE_DEVICE,
400
+ .instance_size = sizeof(MicrochipPFSoCState),
401
+ .instance_init = microchip_pfsoc_soc_instance_init,
402
+ .class_init = microchip_pfsoc_soc_class_init,
403
+};
404
+
405
+static void microchip_pfsoc_soc_register_types(void)
406
+{
407
+ type_register_static(&microchip_pfsoc_soc_type_info);
408
+}
409
+
410
+type_init(microchip_pfsoc_soc_register_types)
411
+
412
+static void microchip_icicle_kit_machine_init(MachineState *machine)
413
+{
414
+ MachineClass *mc = MACHINE_GET_CLASS(machine);
415
+ const struct MemmapEntry *memmap = microchip_pfsoc_memmap;
416
+ MicrochipIcicleKitState *s = MICROCHIP_ICICLE_KIT_MACHINE(machine);
417
+ MemoryRegion *system_memory = get_system_memory();
418
+ MemoryRegion *main_mem = g_new(MemoryRegion, 1);
419
+
420
+ /* Sanity check on RAM size */
421
+ if (machine->ram_size < mc->default_ram_size) {
422
+ char *sz = size_to_str(mc->default_ram_size);
423
+ error_report("Invalid RAM size, should be bigger than %s", sz);
424
+ g_free(sz);
425
+ exit(EXIT_FAILURE);
426
+ }
427
+
428
+ /* Initialize SoC */
429
+ object_initialize_child(OBJECT(machine), "soc", &s->soc,
430
+ TYPE_MICROCHIP_PFSOC);
431
+ qdev_realize(DEVICE(&s->soc), NULL, &error_abort);
432
+
433
+ /* Register RAM */
434
+ memory_region_init_ram(main_mem, NULL, "microchip.icicle.kit.ram",
435
+ machine->ram_size, &error_fatal);
436
+ memory_region_add_subregion(system_memory,
437
+ memmap[MICROCHIP_PFSOC_DRAM].base, main_mem);
438
+
439
+ /* Load the firmware */
440
+ riscv_find_and_load_firmware(machine, BIOS_FILENAME, RESET_VECTOR, NULL);
441
+}
442
+
443
+static void microchip_icicle_kit_machine_class_init(ObjectClass *oc, void *data)
444
+{
445
+ MachineClass *mc = MACHINE_CLASS(oc);
446
+
447
+ mc->desc = "Microchip PolarFire SoC Icicle Kit";
448
+ mc->init = microchip_icicle_kit_machine_init;
449
+ mc->max_cpus = MICROCHIP_PFSOC_MANAGEMENT_CPU_COUNT +
450
+ MICROCHIP_PFSOC_COMPUTE_CPU_COUNT;
451
+ mc->min_cpus = MICROCHIP_PFSOC_MANAGEMENT_CPU_COUNT + 1;
452
+ mc->default_cpus = mc->min_cpus;
453
+ mc->default_ram_size = 1 * GiB;
454
+}
455
+
456
+static const TypeInfo microchip_icicle_kit_machine_typeinfo = {
457
+ .name = MACHINE_TYPE_NAME("microchip-icicle-kit"),
458
+ .parent = TYPE_MACHINE,
459
+ .class_init = microchip_icicle_kit_machine_class_init,
460
+ .instance_size = sizeof(MicrochipIcicleKitState),
461
+};
462
+
463
+static void microchip_icicle_kit_machine_init_register_types(void)
464
+{
465
+ type_register_static(&microchip_icicle_kit_machine_typeinfo);
466
+}
467
+
468
+type_init(microchip_icicle_kit_machine_init_register_types)
469
diff --git a/MAINTAINERS b/MAINTAINERS
470
index XXXXXXX..XXXXXXX 100644
471
--- a/MAINTAINERS
472
+++ b/MAINTAINERS
473
@@ -XXX,XX +XXX,XX @@ F: include/hw/riscv/opentitan.h
474
F: include/hw/char/ibex_uart.h
475
F: include/hw/intc/ibex_plic.h
476
477
+Microchip PolarFire SoC Icicle Kit
478
+M: Bin Meng <bin.meng@windriver.com>
479
+L: qemu-riscv@nongnu.org
480
+S: Supported
481
+F: hw/riscv/microchip_pfsoc.c
482
+F: include/hw/riscv/microchip_pfsoc.h
483
+
484
RX Machines
485
-----------
486
rx-gdbsim
487
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
488
index XXXXXXX..XXXXXXX 100644
489
--- a/hw/riscv/Kconfig
490
+++ b/hw/riscv/Kconfig
491
@@ -XXX,XX +XXX,XX @@ config RISCV_VIRT
492
select PCI_EXPRESS_GENERIC_BRIDGE
493
select PFLASH_CFI01
494
select SIFIVE
495
+
496
+config MICROCHIP_PFSOC
497
+ bool
498
+ select HART
499
+ select SIFIVE
500
+ select UNIMP
501
diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
502
index XXXXXXX..XXXXXXX 100644
503
--- a/hw/riscv/meson.build
504
+++ b/hw/riscv/meson.build
505
@@ -XXX,XX +XXX,XX @@ riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u_otp.c'))
506
riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u_prci.c'))
507
riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('riscv_htif.c'))
508
riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c'))
509
+riscv_ss.add(when: 'CONFIG_MICROCHIP_PFSOC', if_true: files('microchip_pfsoc.c'))
510
511
hw_arch += {'riscv': riscv_ss}
512
--
513
2.28.0
514
515
diff view generated by jsdifflib
New patch
[PULL 07/30] hw/char: Add Microchip PolarFire SoC MMUART emulation
1
1
From: Bin Meng <bin.meng@windriver.com>
2
3
Microchip PolarFire SoC MMUART is ns16550 compatible, with some
4
additional registers. Create a simple MMUART model built on top
5
of the existing ns16550 model.
6
7
Signed-off-by: Bin Meng <bin.meng@windriver.com>
8
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
9
Message-Id: <1598924352-89526-6-git-send-email-bmeng.cn@gmail.com>
10
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
11
---
12
include/hw/char/mchp_pfsoc_mmuart.h | 61 ++++++++++++++++++++
13
hw/char/mchp_pfsoc_mmuart.c | 86 +++++++++++++++++++++++++++++
14
MAINTAINERS | 2 +
15
hw/char/Kconfig | 3 +
16
hw/char/meson.build | 1 +
17
5 files changed, 153 insertions(+)
18
create mode 100644 include/hw/char/mchp_pfsoc_mmuart.h
19
create mode 100644 hw/char/mchp_pfsoc_mmuart.c
20
21
diff --git a/include/hw/char/mchp_pfsoc_mmuart.h b/include/hw/char/mchp_pfsoc_mmuart.h
22
new file mode 100644
23
index XXXXXXX..XXXXXXX
24
--- /dev/null
25
+++ b/include/hw/char/mchp_pfsoc_mmuart.h
26
@@ -XXX,XX +XXX,XX @@
27
+/*
28
+ * Microchip PolarFire SoC MMUART emulation
29
+ *
30
+ * Copyright (c) 2020 Wind River Systems, Inc.
31
+ *
32
+ * Author:
33
+ * Bin Meng <bin.meng@windriver.com>
34
+ *
35
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
36
+ * of this software and associated documentation files (the "Software"), to deal
37
+ * in the Software without restriction, including without limitation the rights
38
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
39
+ * copies of the Software, and to permit persons to whom the Software is
40
+ * furnished to do so, subject to the following conditions:
41
+ *
42
+ * The above copyright notice and this permission notice shall be included in
43
+ * all copies or substantial portions of the Software.
44
+ *
45
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
46
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
47
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
48
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
49
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
50
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
51
+ * THE SOFTWARE.
52
+ */
53
+
54
+#ifndef HW_MCHP_PFSOC_MMUART_H
55
+#define HW_MCHP_PFSOC_MMUART_H
56
+
57
+#include "hw/char/serial.h"
58
+
59
+#define MCHP_PFSOC_MMUART_REG_SIZE 52
60
+
61
+typedef struct MchpPfSoCMMUartState {
62
+ MemoryRegion iomem;
63
+ hwaddr base;
64
+ qemu_irq irq;
65
+
66
+ SerialMM *serial;
67
+
68
+ uint32_t reg[MCHP_PFSOC_MMUART_REG_SIZE / sizeof(uint32_t)];
69
+} MchpPfSoCMMUartState;
70
+
71
+/**
72
+ * mchp_pfsoc_mmuart_create - Create a Microchip PolarFire SoC MMUART
73
+ *
74
+ * This is a helper routine for board to create a MMUART device that is
75
+ * compatible with Microchip PolarFire SoC.
76
+ *
77
+ * @sysmem: system memory region to map
78
+ * @base: base address of the MMUART registers
79
+ * @irq: IRQ number of the MMUART device
80
+ * @chr: character device to associate to
81
+ *
82
+ * @return: a pointer to the device specific control structure
83
+ */
84
+MchpPfSoCMMUartState *mchp_pfsoc_mmuart_create(MemoryRegion *sysmem,
85
+ hwaddr base, qemu_irq irq, Chardev *chr);
86
+
87
+#endif /* HW_MCHP_PFSOC_MMUART_H */
88
diff --git a/hw/char/mchp_pfsoc_mmuart.c b/hw/char/mchp_pfsoc_mmuart.c
89
new file mode 100644
90
index XXXXXXX..XXXXXXX
91
--- /dev/null
92
+++ b/hw/char/mchp_pfsoc_mmuart.c
93
@@ -XXX,XX +XXX,XX @@
94
+/*
95
+ * Microchip PolarFire SoC MMUART emulation
96
+ *
97
+ * Copyright (c) 2020 Wind River Systems, Inc.
98
+ *
99
+ * Author:
100
+ * Bin Meng <bin.meng@windriver.com>
101
+ *
102
+ * This program is free software; you can redistribute it and/or
103
+ * modify it under the terms of the GNU General Public License as
104
+ * published by the Free Software Foundation; either version 2 or
105
+ * (at your option) version 3 of the License.
106
+ *
107
+ * This program is distributed in the hope that it will be useful,
108
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
109
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
110
+ * GNU General Public License for more details.
111
+ *
112
+ * You should have received a copy of the GNU General Public License along
113
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
114
+ */
115
+
116
+#include "qemu/osdep.h"
117
+#include "qemu/log.h"
118
+#include "chardev/char.h"
119
+#include "exec/address-spaces.h"
120
+#include "hw/char/mchp_pfsoc_mmuart.h"
121
+
122
+static uint64_t mchp_pfsoc_mmuart_read(void *opaque, hwaddr addr, unsigned size)
123
+{
124
+ MchpPfSoCMMUartState *s = opaque;
125
+
126
+ if (addr >= MCHP_PFSOC_MMUART_REG_SIZE) {
127
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: read: addr=0x%" HWADDR_PRIx "\n",
128
+ __func__, addr);
129
+ return 0;
130
+ }
131
+
132
+ return s->reg[addr / sizeof(uint32_t)];
133
+}
134
+
135
+static void mchp_pfsoc_mmuart_write(void *opaque, hwaddr addr,
136
+ uint64_t value, unsigned size)
137
+{
138
+ MchpPfSoCMMUartState *s = opaque;
139
+ uint32_t val32 = (uint32_t)value;
140
+
141
+ if (addr >= MCHP_PFSOC_MMUART_REG_SIZE) {
142
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: bad write: addr=0x%" HWADDR_PRIx
143
+ " v=0x%x\n", __func__, addr, val32);
144
+ return;
145
+ }
146
+
147
+ s->reg[addr / sizeof(uint32_t)] = val32;
148
+}
149
+
150
+static const MemoryRegionOps mchp_pfsoc_mmuart_ops = {
151
+ .read = mchp_pfsoc_mmuart_read,
152
+ .write = mchp_pfsoc_mmuart_write,
153
+ .endianness = DEVICE_LITTLE_ENDIAN,
154
+ .impl = {
155
+ .min_access_size = 4,
156
+ .max_access_size = 4,
157
+ },
158
+};
159
+
160
+MchpPfSoCMMUartState *mchp_pfsoc_mmuart_create(MemoryRegion *sysmem,
161
+ hwaddr base, qemu_irq irq, Chardev *chr)
162
+{
163
+ MchpPfSoCMMUartState *s;
164
+
165
+ s = g_new0(MchpPfSoCMMUartState, 1);
166
+
167
+ memory_region_init_io(&s->iomem, NULL, &mchp_pfsoc_mmuart_ops, s,
168
+ "mchp.pfsoc.mmuart", 0x1000);
169
+
170
+ s->base = base;
171
+ s->irq = irq;
172
+
173
+ s->serial = serial_mm_init(sysmem, base, 2, irq, 399193, chr,
174
+ DEVICE_LITTLE_ENDIAN);
175
+
176
+ memory_region_add_subregion(sysmem, base + 0x20, &s->iomem);
177
+
178
+ return s;
179
+}
180
diff --git a/MAINTAINERS b/MAINTAINERS
181
index XXXXXXX..XXXXXXX 100644
182
--- a/MAINTAINERS
183
+++ b/MAINTAINERS
184
@@ -XXX,XX +XXX,XX @@ M: Bin Meng <bin.meng@windriver.com>
185
L: qemu-riscv@nongnu.org
186
S: Supported
187
F: hw/riscv/microchip_pfsoc.c
188
+F: hw/char/mchp_pfsoc_mmuart.c
189
F: include/hw/riscv/microchip_pfsoc.h
190
+F: include/hw/char/mchp_pfsoc_mmuart.h
191
192
RX Machines
193
-----------
194
diff --git a/hw/char/Kconfig b/hw/char/Kconfig
195
index XXXXXXX..XXXXXXX 100644
196
--- a/hw/char/Kconfig
197
+++ b/hw/char/Kconfig
198
@@ -XXX,XX +XXX,XX @@ config RENESAS_SCI
199
200
config AVR_USART
201
bool
202
+
203
+config MCHP_PFSOC_MMUART
204
+ bool
205
diff --git a/hw/char/meson.build b/hw/char/meson.build
206
index XXXXXXX..XXXXXXX 100644
207
--- a/hw/char/meson.build
208
+++ b/hw/char/meson.build
209
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_aux.c'))
210
softmmu_ss.add(when: 'CONFIG_RENESAS_SCI', if_true: files('renesas_sci.c'))
211
softmmu_ss.add(when: 'CONFIG_SH4', if_true: files('sh_serial.c'))
212
softmmu_ss.add(when: 'CONFIG_STM32F2XX_USART', if_true: files('stm32f2xx_usart.c'))
213
+softmmu_ss.add(when: 'CONFIG_MCHP_PFSOC_MMUART', if_true: files('mchp_pfsoc_mmuart.c'))
214
215
specific_ss.add(when: 'CONFIG_TERMINAL3270', if_true: files('terminal3270.c'))
216
specific_ss.add(when: 'CONFIG_VIRTIO', if_true: files('virtio-serial-bus.c'))
217
--
218
2.28.0
219
220
diff view generated by jsdifflib
[PULL 08/12] target/riscv: Make csr_ops[CSR_TABLE_SIZE] external
[PULL 08/30] hw/riscv: microchip_pfsoc: Connect 5 MMUARTs
1
From: Bin Meng <bin.meng@windriver.com>
1
From: Bin Meng <bin.meng@windriver.com>
2
2
3
In preparation to generate the CSR register list for GDB stub
3
Microchip PolarFire SoC has 5 MMUARTs, and the Icicle Kit board
4
dynamically, change csr_ops[] to non-static so that it can be
4
wires 4 of them out. Let's connect all 5 MMUARTs.
5
referenced externally.
6
5
7
Signed-off-by: Bin Meng <bin.meng@windriver.com>
6
Signed-off-by: Bin Meng <bin.meng@windriver.com>
8
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
7
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
9
Message-id: 1610427124-49887-2-git-send-email-bmeng.cn@gmail.com
8
Message-Id: <1598924352-89526-7-git-send-email-bmeng.cn@gmail.com>
10
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
9
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
11
---
10
---
12
target/riscv/cpu.h | 8 ++++++++
11
include/hw/riscv/microchip_pfsoc.h | 20 ++++++++++++++++++++
13
target/riscv/csr.c | 10 +---------
12
hw/riscv/microchip_pfsoc.c | 30 ++++++++++++++++++++++++++++++
14
2 files changed, 9 insertions(+), 9 deletions(-)
13
hw/riscv/Kconfig | 1 +
14
3 files changed, 51 insertions(+)
15
15
16
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
16
diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h
17
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/riscv/cpu.h
18
--- a/include/hw/riscv/microchip_pfsoc.h
19
+++ b/target/riscv/cpu.h
19
+++ b/include/hw/riscv/microchip_pfsoc.h
20
@@ -XXX,XX +XXX,XX @@ typedef struct {
20
@@ -XXX,XX +XXX,XX @@
21
riscv_csr_op_fn op;
21
#ifndef HW_MICROCHIP_PFSOC_H
22
} riscv_csr_operations;
22
#define HW_MICROCHIP_PFSOC_H
23
23
24
+/* CSR function table constants */
24
+#include "hw/char/mchp_pfsoc_mmuart.h"
25
+
26
typedef struct MicrochipPFSoCState {
27
/*< private >*/
28
DeviceState parent_obj;
29
@@ -XXX,XX +XXX,XX @@ typedef struct MicrochipPFSoCState {
30
RISCVHartArrayState e_cpus;
31
RISCVHartArrayState u_cpus;
32
DeviceState *plic;
33
+ MchpPfSoCMMUartState *serial0;
34
+ MchpPfSoCMMUartState *serial1;
35
+ MchpPfSoCMMUartState *serial2;
36
+ MchpPfSoCMMUartState *serial3;
37
+ MchpPfSoCMMUartState *serial4;
38
} MicrochipPFSoCState;
39
40
#define TYPE_MICROCHIP_PFSOC "microchip.pfsoc"
41
@@ -XXX,XX +XXX,XX @@ enum {
42
MICROCHIP_PFSOC_L2CC,
43
MICROCHIP_PFSOC_L2LIM,
44
MICROCHIP_PFSOC_PLIC,
45
+ MICROCHIP_PFSOC_MMUART0,
46
MICROCHIP_PFSOC_SYSREG,
47
MICROCHIP_PFSOC_MPUCFG,
48
+ MICROCHIP_PFSOC_MMUART1,
49
+ MICROCHIP_PFSOC_MMUART2,
50
+ MICROCHIP_PFSOC_MMUART3,
51
+ MICROCHIP_PFSOC_MMUART4,
52
MICROCHIP_PFSOC_ENVM_CFG,
53
MICROCHIP_PFSOC_ENVM_DATA,
54
MICROCHIP_PFSOC_IOSCB_CFG,
55
MICROCHIP_PFSOC_DRAM,
56
};
57
25
+enum {
58
+enum {
26
+ CSR_TABLE_SIZE = 0x1000
59
+ MICROCHIP_PFSOC_MMUART0_IRQ = 90,
60
+ MICROCHIP_PFSOC_MMUART1_IRQ = 91,
61
+ MICROCHIP_PFSOC_MMUART2_IRQ = 92,
62
+ MICROCHIP_PFSOC_MMUART3_IRQ = 93,
63
+ MICROCHIP_PFSOC_MMUART4_IRQ = 94,
27
+};
64
+};
28
+
65
+
29
+/* CSR function table */
66
#define MICROCHIP_PFSOC_MANAGEMENT_CPU_COUNT 1
30
+extern riscv_csr_operations csr_ops[];
67
#define MICROCHIP_PFSOC_COMPUTE_CPU_COUNT 4
68
69
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
70
index XXXXXXX..XXXXXXX 100644
71
--- a/hw/riscv/microchip_pfsoc.c
72
+++ b/hw/riscv/microchip_pfsoc.c
73
@@ -XXX,XX +XXX,XX @@
74
* 0) CLINT (Core Level Interruptor)
75
* 1) PLIC (Platform Level Interrupt Controller)
76
* 2) eNVM (Embedded Non-Volatile Memory)
77
+ * 3) MMUARTs (Multi-Mode UART)
78
*
79
* This board currently generates devicetree dynamically that indicates at least
80
* two harts and up to five harts.
81
@@ -XXX,XX +XXX,XX @@
82
#include "hw/irq.h"
83
#include "hw/loader.h"
84
#include "hw/sysbus.h"
85
+#include "chardev/char.h"
86
#include "hw/cpu/cluster.h"
87
#include "target/riscv/cpu.h"
88
#include "hw/misc/unimp.h"
89
@@ -XXX,XX +XXX,XX @@
90
#include "hw/riscv/sifive_clint.h"
91
#include "hw/riscv/sifive_plic.h"
92
#include "hw/riscv/microchip_pfsoc.h"
93
+#include "sysemu/sysemu.h"
94
95
/*
96
* The BIOS image used by this machine is called Hart Software Services (HSS).
97
@@ -XXX,XX +XXX,XX @@ static const struct MemmapEntry {
98
[MICROCHIP_PFSOC_L2CC] = { 0x2010000, 0x1000 },
99
[MICROCHIP_PFSOC_L2LIM] = { 0x8000000, 0x2000000 },
100
[MICROCHIP_PFSOC_PLIC] = { 0xc000000, 0x4000000 },
101
+ [MICROCHIP_PFSOC_MMUART0] = { 0x20000000, 0x1000 },
102
[MICROCHIP_PFSOC_SYSREG] = { 0x20002000, 0x2000 },
103
[MICROCHIP_PFSOC_MPUCFG] = { 0x20005000, 0x1000 },
104
+ [MICROCHIP_PFSOC_MMUART1] = { 0x20100000, 0x1000 },
105
+ [MICROCHIP_PFSOC_MMUART2] = { 0x20102000, 0x1000 },
106
+ [MICROCHIP_PFSOC_MMUART3] = { 0x20104000, 0x1000 },
107
+ [MICROCHIP_PFSOC_MMUART4] = { 0x20106000, 0x1000 },
108
[MICROCHIP_PFSOC_ENVM_CFG] = { 0x20200000, 0x1000 },
109
[MICROCHIP_PFSOC_ENVM_DATA] = { 0x20220000, 0x20000 },
110
[MICROCHIP_PFSOC_IOSCB_CFG] = { 0x37080000, 0x1000 },
111
@@ -XXX,XX +XXX,XX @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
112
memmap[MICROCHIP_PFSOC_MPUCFG].base,
113
memmap[MICROCHIP_PFSOC_MPUCFG].size);
114
115
+ /* MMUARTs */
116
+ s->serial0 = mchp_pfsoc_mmuart_create(system_memory,
117
+ memmap[MICROCHIP_PFSOC_MMUART0].base,
118
+ qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART0_IRQ),
119
+ serial_hd(0));
120
+ s->serial1 = mchp_pfsoc_mmuart_create(system_memory,
121
+ memmap[MICROCHIP_PFSOC_MMUART1].base,
122
+ qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART1_IRQ),
123
+ serial_hd(1));
124
+ s->serial2 = mchp_pfsoc_mmuart_create(system_memory,
125
+ memmap[MICROCHIP_PFSOC_MMUART2].base,
126
+ qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART2_IRQ),
127
+ serial_hd(2));
128
+ s->serial3 = mchp_pfsoc_mmuart_create(system_memory,
129
+ memmap[MICROCHIP_PFSOC_MMUART3].base,
130
+ qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART3_IRQ),
131
+ serial_hd(3));
132
+ s->serial4 = mchp_pfsoc_mmuart_create(system_memory,
133
+ memmap[MICROCHIP_PFSOC_MMUART4].base,
134
+ qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART4_IRQ),
135
+ serial_hd(4));
31
+
136
+
32
void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops);
137
/* eNVM */
33
void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops);
138
memory_region_init_rom(envm_data, OBJECT(dev), "microchip.pfsoc.envm.data",
34
139
memmap[MICROCHIP_PFSOC_ENVM_DATA].size,
35
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
140
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
36
index XXXXXXX..XXXXXXX 100644
141
index XXXXXXX..XXXXXXX 100644
37
--- a/target/riscv/csr.c
142
--- a/hw/riscv/Kconfig
38
+++ b/target/riscv/csr.c
143
+++ b/hw/riscv/Kconfig
39
@@ -XXX,XX +XXX,XX @@
144
@@ -XXX,XX +XXX,XX @@ config MICROCHIP_PFSOC
40
#include "qemu/main-loop.h"
145
select HART
41
#include "exec/exec-all.h"
146
select SIFIVE
42
147
select UNIMP
43
-/* CSR function table */
148
+ select MCHP_PFSOC_MMUART
44
-static riscv_csr_operations csr_ops[];
45
-
46
-/* CSR function table constants */
47
-enum {
48
- CSR_TABLE_SIZE = 0x1000
49
-};
50
-
51
/* CSR function table public API */
52
void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops)
53
{
54
@@ -XXX,XX +XXX,XX @@ int riscv_csrrw_debug(CPURISCVState *env, int csrno, target_ulong *ret_value,
55
}
56
57
/* Control and Status Register function table */
58
-static riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
59
+riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
60
/* User Floating-Point CSRs */
61
[CSR_FFLAGS] = { fs, read_fflags, write_fflags },
62
[CSR_FRM] = { fs, read_frm, write_frm },
63
--
149
--
64
2.29.2
150
2.28.0
65
151
66
152
diff view generated by jsdifflib
New patch
[PULL 09/30] hw/sd: Add Cadence SDHCI emulation
1
1
From: Bin Meng <bin.meng@windriver.com>
2
3
Cadence SD/SDIO/eMMC Host Controller (SD4HC) is an SDHCI compatible
4
controller. The SDHCI compatible registers start from offset 0x200,
5
which are called Slot Register Set (SRS) in its datasheet.
6
7
This creates a Cadence SDHCI model built on top of the existing
8
generic SDHCI model. Cadence specific Host Register Set (HRS) is
9
implemented to make guest software happy.
10
11
Signed-off-by: Bin Meng <bin.meng@windriver.com>
12
Acked-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
13
Acked-by: Alistair Francis <alistair.francis@wdc.com>
14
Message-Id: <1598924352-89526-8-git-send-email-bmeng.cn@gmail.com>
15
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
16
---
17
include/hw/sd/cadence_sdhci.h | 47 +++++++++
18
hw/sd/cadence_sdhci.c | 193 ++++++++++++++++++++++++++++++++++
19
hw/sd/Kconfig | 4 +
20
hw/sd/meson.build | 1 +
21
4 files changed, 245 insertions(+)
22
create mode 100644 include/hw/sd/cadence_sdhci.h
23
create mode 100644 hw/sd/cadence_sdhci.c
24
25
diff --git a/include/hw/sd/cadence_sdhci.h b/include/hw/sd/cadence_sdhci.h
26
new file mode 100644
27
index XXXXXXX..XXXXXXX
28
--- /dev/null
29
+++ b/include/hw/sd/cadence_sdhci.h
30
@@ -XXX,XX +XXX,XX @@
31
+/*
32
+ * Cadence SDHCI emulation
33
+ *
34
+ * Copyright (c) 2020 Wind River Systems, Inc.
35
+ *
36
+ * Author:
37
+ * Bin Meng <bin.meng@windriver.com>
38
+ *
39
+ * This program is free software; you can redistribute it and/or
40
+ * modify it under the terms of the GNU General Public License as
41
+ * published by the Free Software Foundation; either version 2 or
42
+ * (at your option) version 3 of the License.
43
+ *
44
+ * This program is distributed in the hope that it will be useful,
45
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
46
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
47
+ * GNU General Public License for more details.
48
+ *
49
+ * You should have received a copy of the GNU General Public License along
50
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
51
+ */
52
+
53
+#ifndef CADENCE_SDHCI_H
54
+#define CADENCE_SDHCI_H
55
+
56
+#include "hw/sd/sdhci.h"
57
+
58
+#define CADENCE_SDHCI_REG_SIZE 0x100
59
+#define CADENCE_SDHCI_NUM_REGS (CADENCE_SDHCI_REG_SIZE / sizeof(uint32_t))
60
+
61
+typedef struct CadenceSDHCIState {
62
+ SysBusDevice parent;
63
+
64
+ MemoryRegion container;
65
+ MemoryRegion iomem;
66
+ BusState *bus;
67
+
68
+ uint32_t regs[CADENCE_SDHCI_NUM_REGS];
69
+
70
+ SDHCIState sdhci;
71
+} CadenceSDHCIState;
72
+
73
+#define TYPE_CADENCE_SDHCI "cadence.sdhci"
74
+#define CADENCE_SDHCI(obj) OBJECT_CHECK(CadenceSDHCIState, (obj), \
75
+ TYPE_CADENCE_SDHCI)
76
+
77
+#endif /* CADENCE_SDHCI_H */
78
diff --git a/hw/sd/cadence_sdhci.c b/hw/sd/cadence_sdhci.c
79
new file mode 100644
80
index XXXXXXX..XXXXXXX
81
--- /dev/null
82
+++ b/hw/sd/cadence_sdhci.c
83
@@ -XXX,XX +XXX,XX @@
84
+/*
85
+ * Cadence SDHCI emulation
86
+ *
87
+ * Copyright (c) 2020 Wind River Systems, Inc.
88
+ *
89
+ * Author:
90
+ * Bin Meng <bin.meng@windriver.com>
91
+ *
92
+ * This program is free software; you can redistribute it and/or
93
+ * modify it under the terms of the GNU General Public License as
94
+ * published by the Free Software Foundation; either version 2 or
95
+ * (at your option) version 3 of the License.
96
+ *
97
+ * This program is distributed in the hope that it will be useful,
98
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
99
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
100
+ * GNU General Public License for more details.
101
+ *
102
+ * You should have received a copy of the GNU General Public License along
103
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
104
+ */
105
+
106
+#include "qemu/osdep.h"
107
+#include "qemu/bitops.h"
108
+#include "qemu/error-report.h"
109
+#include "qemu/log.h"
110
+#include "qapi/error.h"
111
+#include "migration/vmstate.h"
112
+#include "hw/irq.h"
113
+#include "hw/sd/cadence_sdhci.h"
114
+#include "sdhci-internal.h"
115
+
116
+/* HRS - Host Register Set (specific to Cadence) */
117
+
118
+#define CADENCE_SDHCI_HRS00 0x00 /* general information */
119
+#define CADENCE_SDHCI_HRS00_SWR BIT(0)
120
+#define CADENCE_SDHCI_HRS00_POR_VAL 0x00010000
121
+
122
+#define CADENCE_SDHCI_HRS04 0x10 /* PHY access port */
123
+#define CADENCE_SDHCI_HRS04_WR BIT(24)
124
+#define CADENCE_SDHCI_HRS04_RD BIT(25)
125
+#define CADENCE_SDHCI_HRS04_ACK BIT(26)
126
+
127
+#define CADENCE_SDHCI_HRS06 0x18 /* eMMC control */
128
+#define CADENCE_SDHCI_HRS06_TUNE_UP BIT(15)
129
+
130
+/* SRS - Slot Register Set (SDHCI-compatible) */
131
+
132
+#define CADENCE_SDHCI_SRS_BASE 0x200
133
+
134
+#define TO_REG(addr) ((addr) / sizeof(uint32_t))
135
+
136
+static void cadence_sdhci_instance_init(Object *obj)
137
+{
138
+ CadenceSDHCIState *s = CADENCE_SDHCI(obj);
139
+
140
+ object_initialize_child(OBJECT(s), "generic-sdhci",
141
+ &s->sdhci, TYPE_SYSBUS_SDHCI);
142
+}
143
+
144
+static void cadence_sdhci_reset(DeviceState *dev)
145
+{
146
+ CadenceSDHCIState *s = CADENCE_SDHCI(dev);
147
+
148
+ memset(s->regs, 0, CADENCE_SDHCI_REG_SIZE);
149
+ s->regs[TO_REG(CADENCE_SDHCI_HRS00)] = CADENCE_SDHCI_HRS00_POR_VAL;
150
+
151
+ device_cold_reset(DEVICE(&s->sdhci));
152
+}
153
+
154
+static uint64_t cadence_sdhci_read(void *opaque, hwaddr addr, unsigned int size)
155
+{
156
+ CadenceSDHCIState *s = opaque;
157
+ uint32_t val;
158
+
159
+ val = s->regs[TO_REG(addr)];
160
+
161
+ return (uint64_t)val;
162
+}
163
+
164
+static void cadence_sdhci_write(void *opaque, hwaddr addr, uint64_t val,
165
+ unsigned int size)
166
+{
167
+ CadenceSDHCIState *s = opaque;
168
+ uint32_t val32 = (uint32_t)val;
169
+
170
+ switch (addr) {
171
+ case CADENCE_SDHCI_HRS00:
172
+ /*
173
+ * The only writable bit is SWR (software reset) and it automatically
174
+ * clears to zero, so essentially this register remains unchanged.
175
+ */
176
+ if (val32 & CADENCE_SDHCI_HRS00_SWR) {
177
+ cadence_sdhci_reset(DEVICE(s));
178
+ }
179
+
180
+ break;
181
+ case CADENCE_SDHCI_HRS04:
182
+ /*
183
+ * Only emulate the ACK bit behavior when read or write transaction
184
+ * are requested.
185
+ */
186
+ if (val32 & (CADENCE_SDHCI_HRS04_WR | CADENCE_SDHCI_HRS04_RD)) {
187
+ val32 |= CADENCE_SDHCI_HRS04_ACK;
188
+ } else {
189
+ val32 &= ~CADENCE_SDHCI_HRS04_ACK;
190
+ }
191
+
192
+ s->regs[TO_REG(addr)] = val32;
193
+ break;
194
+ case CADENCE_SDHCI_HRS06:
195
+ if (val32 & CADENCE_SDHCI_HRS06_TUNE_UP) {
196
+ val32 &= ~CADENCE_SDHCI_HRS06_TUNE_UP;
197
+ }
198
+
199
+ s->regs[TO_REG(addr)] = val32;
200
+ break;
201
+ default:
202
+ s->regs[TO_REG(addr)] = val32;
203
+ break;
204
+ }
205
+}
206
+
207
+static const MemoryRegionOps cadence_sdhci_ops = {
208
+ .read = cadence_sdhci_read,
209
+ .write = cadence_sdhci_write,
210
+ .endianness = DEVICE_NATIVE_ENDIAN,
211
+ .impl = {
212
+ .min_access_size = 4,
213
+ .max_access_size = 4,
214
+ },
215
+ .valid = {
216
+ .min_access_size = 4,
217
+ .max_access_size = 4,
218
+ }
219
+};
220
+
221
+static void cadence_sdhci_realize(DeviceState *dev, Error **errp)
222
+{
223
+ CadenceSDHCIState *s = CADENCE_SDHCI(dev);
224
+ SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
225
+ SysBusDevice *sbd_sdhci = SYS_BUS_DEVICE(&s->sdhci);
226
+
227
+ memory_region_init(&s->container, OBJECT(s),
228
+ "cadence.sdhci-container", 0x1000);
229
+ sysbus_init_mmio(sbd, &s->container);
230
+
231
+ memory_region_init_io(&s->iomem, OBJECT(s), &cadence_sdhci_ops,
232
+ s, TYPE_CADENCE_SDHCI, CADENCE_SDHCI_REG_SIZE);
233
+ memory_region_add_subregion(&s->container, 0, &s->iomem);
234
+
235
+ sysbus_realize(sbd_sdhci, errp);
236
+ memory_region_add_subregion(&s->container, CADENCE_SDHCI_SRS_BASE,
237
+ sysbus_mmio_get_region(sbd_sdhci, 0));
238
+
239
+ /* propagate irq and "sd-bus" from generic-sdhci */
240
+ sysbus_pass_irq(sbd, sbd_sdhci);
241
+ s->bus = qdev_get_child_bus(DEVICE(sbd_sdhci), "sd-bus");
242
+}
243
+
244
+static const VMStateDescription vmstate_cadence_sdhci = {
245
+ .name = TYPE_CADENCE_SDHCI,
246
+ .version_id = 1,
247
+ .fields = (VMStateField[]) {
248
+ VMSTATE_UINT32_ARRAY(regs, CadenceSDHCIState, CADENCE_SDHCI_NUM_REGS),
249
+ VMSTATE_END_OF_LIST(),
250
+ },
251
+};
252
+
253
+static void cadence_sdhci_class_init(ObjectClass *classp, void *data)
254
+{
255
+ DeviceClass *dc = DEVICE_CLASS(classp);
256
+
257
+ dc->desc = "Cadence SD/SDIO/eMMC Host Controller (SD4HC)";
258
+ dc->realize = cadence_sdhci_realize;
259
+ dc->reset = cadence_sdhci_reset;
260
+ dc->vmsd = &vmstate_cadence_sdhci;
261
+}
262
+
263
+static TypeInfo cadence_sdhci_info = {
264
+ .name = TYPE_CADENCE_SDHCI,
265
+ .parent = TYPE_SYS_BUS_DEVICE,
266
+ .instance_size = sizeof(CadenceSDHCIState),
267
+ .instance_init = cadence_sdhci_instance_init,
268
+ .class_init = cadence_sdhci_class_init,
269
+};
270
+
271
+static void cadence_sdhci_register_types(void)
272
+{
273
+ type_register_static(&cadence_sdhci_info);
274
+}
275
+
276
+type_init(cadence_sdhci_register_types)
277
diff --git a/hw/sd/Kconfig b/hw/sd/Kconfig
278
index XXXXXXX..XXXXXXX 100644
279
--- a/hw/sd/Kconfig
280
+++ b/hw/sd/Kconfig
281
@@ -XXX,XX +XXX,XX @@ config SDHCI_PCI
282
default y if PCI_DEVICES
283
depends on PCI
284
select SDHCI
285
+
286
+config CADENCE_SDHCI
287
+ bool
288
+ select SDHCI
289
diff --git a/hw/sd/meson.build b/hw/sd/meson.build
290
index XXXXXXX..XXXXXXX 100644
291
--- a/hw/sd/meson.build
292
+++ b/hw/sd/meson.build
293
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_PXA2XX', if_true: files('pxa2xx_mmci.c'))
294
softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_sdhost.c'))
295
softmmu_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files('aspeed_sdhci.c'))
296
softmmu_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-sdhost.c'))
297
+softmmu_ss.add(when: 'CONFIG_CADENCE_SDHCI', if_true: files('cadence_sdhci.c'))
298
--
299
2.28.0
300
301
diff view generated by jsdifflib
New patch
[PULL 10/30] hw/riscv: microchip_pfsoc: Connect a Cadence SDHCI controller and an SD card
1
From: Bin Meng <bin.meng@windriver.com>
1
2
3
Microchip PolarFire SoC integrates one Cadence SDHCI controller.
4
On the Icicle Kit board, one eMMC chip and an external SD card
5
connect to this controller depending on different configuration.
6
7
As QEMU does not support eMMC yet, we just emulate the SD card
8
configuration. To test this, the Hart Software Services (HSS)
9
should choose the SD card configuration:
10
11
$ cp boards/icicle-kit-es/def_config.sdcard .config
12
$ make BOARD=icicle-kit-es
13
14
The SD card image can be built from the Yocto BSP at:
15
https://github.com/polarfire-soc/meta-polarfire-soc-yocto-bsp
16
17
Note the generated SD card image should be resized before use:
18
$ qemu-img resize /path/to/sdcard.img 4G
19
20
Launch QEMU with the following command:
21
$ qemu-system-riscv64 -nographic -M microchip-icicle-kit -sd sdcard.img
22
23
Signed-off-by: Bin Meng <bin.meng@windriver.com>
24
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
25
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
26
Message-Id: <1598924352-89526-9-git-send-email-bmeng.cn@gmail.com>
27
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
28
---
29
include/hw/riscv/microchip_pfsoc.h | 4 ++++
30
hw/riscv/microchip_pfsoc.c | 23 +++++++++++++++++++++++
31
hw/riscv/Kconfig | 1 +
32
3 files changed, 28 insertions(+)
33
34
diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h
35
index XXXXXXX..XXXXXXX 100644
36
--- a/include/hw/riscv/microchip_pfsoc.h
37
+++ b/include/hw/riscv/microchip_pfsoc.h
38
@@ -XXX,XX +XXX,XX @@
39
#define HW_MICROCHIP_PFSOC_H
40
41
#include "hw/char/mchp_pfsoc_mmuart.h"
42
+#include "hw/sd/cadence_sdhci.h"
43
44
typedef struct MicrochipPFSoCState {
45
/*< private >*/
46
@@ -XXX,XX +XXX,XX @@ typedef struct MicrochipPFSoCState {
47
MchpPfSoCMMUartState *serial2;
48
MchpPfSoCMMUartState *serial3;
49
MchpPfSoCMMUartState *serial4;
50
+ CadenceSDHCIState sdhci;
51
} MicrochipPFSoCState;
52
53
#define TYPE_MICROCHIP_PFSOC "microchip.pfsoc"
54
@@ -XXX,XX +XXX,XX @@ enum {
55
MICROCHIP_PFSOC_MMUART0,
56
MICROCHIP_PFSOC_SYSREG,
57
MICROCHIP_PFSOC_MPUCFG,
58
+ MICROCHIP_PFSOC_EMMC_SD,
59
MICROCHIP_PFSOC_MMUART1,
60
MICROCHIP_PFSOC_MMUART2,
61
MICROCHIP_PFSOC_MMUART3,
62
@@ -XXX,XX +XXX,XX @@ enum {
63
};
64
65
enum {
66
+ MICROCHIP_PFSOC_EMMC_SD_IRQ = 88,
67
MICROCHIP_PFSOC_MMUART0_IRQ = 90,
68
MICROCHIP_PFSOC_MMUART1_IRQ = 91,
69
MICROCHIP_PFSOC_MMUART2_IRQ = 92,
70
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
71
index XXXXXXX..XXXXXXX 100644
72
--- a/hw/riscv/microchip_pfsoc.c
73
+++ b/hw/riscv/microchip_pfsoc.c
74
@@ -XXX,XX +XXX,XX @@
75
* 1) PLIC (Platform Level Interrupt Controller)
76
* 2) eNVM (Embedded Non-Volatile Memory)
77
* 3) MMUARTs (Multi-Mode UART)
78
+ * 4) Cadence eMMC/SDHC controller and an SD card connected to it
79
*
80
* This board currently generates devicetree dynamically that indicates at least
81
* two harts and up to five harts.
82
@@ -XXX,XX +XXX,XX @@ static const struct MemmapEntry {
83
[MICROCHIP_PFSOC_MMUART0] = { 0x20000000, 0x1000 },
84
[MICROCHIP_PFSOC_SYSREG] = { 0x20002000, 0x2000 },
85
[MICROCHIP_PFSOC_MPUCFG] = { 0x20005000, 0x1000 },
86
+ [MICROCHIP_PFSOC_EMMC_SD] = { 0x20008000, 0x1000 },
87
[MICROCHIP_PFSOC_MMUART1] = { 0x20100000, 0x1000 },
88
[MICROCHIP_PFSOC_MMUART2] = { 0x20102000, 0x1000 },
89
[MICROCHIP_PFSOC_MMUART3] = { 0x20104000, 0x1000 },
90
@@ -XXX,XX +XXX,XX @@ static void microchip_pfsoc_soc_instance_init(Object *obj)
91
qdev_prop_set_string(DEVICE(&s->u_cpus), "cpu-type",
92
TYPE_RISCV_CPU_SIFIVE_U54);
93
qdev_prop_set_uint64(DEVICE(&s->u_cpus), "resetvec", RESET_VECTOR);
94
+
95
+ object_initialize_child(obj, "sd-controller", &s->sdhci,
96
+ TYPE_CADENCE_SDHCI);
97
}
98
99
static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
100
@@ -XXX,XX +XXX,XX @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
101
memmap[MICROCHIP_PFSOC_MPUCFG].base,
102
memmap[MICROCHIP_PFSOC_MPUCFG].size);
103
104
+ /* SDHCI */
105
+ sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), errp);
106
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdhci), 0,
107
+ memmap[MICROCHIP_PFSOC_EMMC_SD].base);
108
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0,
109
+ qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_EMMC_SD_IRQ));
110
+
111
/* MMUARTs */
112
s->serial0 = mchp_pfsoc_mmuart_create(system_memory,
113
memmap[MICROCHIP_PFSOC_MMUART0].base,
114
@@ -XXX,XX +XXX,XX @@ static void microchip_icicle_kit_machine_init(MachineState *machine)
115
MicrochipIcicleKitState *s = MICROCHIP_ICICLE_KIT_MACHINE(machine);
116
MemoryRegion *system_memory = get_system_memory();
117
MemoryRegion *main_mem = g_new(MemoryRegion, 1);
118
+ DriveInfo *dinfo = drive_get_next(IF_SD);
119
120
/* Sanity check on RAM size */
121
if (machine->ram_size < mc->default_ram_size) {
122
@@ -XXX,XX +XXX,XX @@ static void microchip_icicle_kit_machine_init(MachineState *machine)
123
124
/* Load the firmware */
125
riscv_find_and_load_firmware(machine, BIOS_FILENAME, RESET_VECTOR, NULL);
126
+
127
+ /* Attach an SD card */
128
+ if (dinfo) {
129
+ CadenceSDHCIState *sdhci = &(s->soc.sdhci);
130
+ DeviceState *card = qdev_new(TYPE_SD_CARD);
131
+
132
+ qdev_prop_set_drive_err(card, "drive", blk_by_legacy_dinfo(dinfo),
133
+ &error_fatal);
134
+ qdev_realize_and_unref(card, sdhci->bus, &error_fatal);
135
+ }
136
}
137
138
static void microchip_icicle_kit_machine_class_init(ObjectClass *oc, void *data)
139
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
140
index XXXXXXX..XXXXXXX 100644
141
--- a/hw/riscv/Kconfig
142
+++ b/hw/riscv/Kconfig
143
@@ -XXX,XX +XXX,XX @@ config MICROCHIP_PFSOC
144
select SIFIVE
145
select UNIMP
146
select MCHP_PFSOC_MMUART
147
+ select CADENCE_SDHCI
148
--
149
2.28.0
150
151
diff view generated by jsdifflib
New patch
[PULL 11/30] hw/dma: Add SiFive platform DMA controller emulation
1
1
From: Bin Meng <bin.meng@windriver.com>
2
3
Microchip PolarFire SoC integrates a DMA engine that supports:
4
* Independent concurrent DMA transfers using 4 DMA channels
5
* Generation of interrupts on various conditions during execution
6
which is actually an IP reused from the SiFive FU540 chip.
7
8
This creates a model to support both polling and interrupt modes.
9
10
Signed-off-by: Bin Meng <bin.meng@windriver.com>
11
Acked-by: Alistair Francis <alistair.francis@wdc.com>
12
Message-Id: <1598924352-89526-10-git-send-email-bmeng.cn@gmail.com>
13
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
14
---
15
include/hw/dma/sifive_pdma.h | 57 +++++++
16
hw/dma/sifive_pdma.c | 313 +++++++++++++++++++++++++++++++++++
17
hw/dma/Kconfig | 3 +
18
hw/dma/meson.build | 1 +
19
4 files changed, 374 insertions(+)
20
create mode 100644 include/hw/dma/sifive_pdma.h
21
create mode 100644 hw/dma/sifive_pdma.c
22
23
diff --git a/include/hw/dma/sifive_pdma.h b/include/hw/dma/sifive_pdma.h
24
new file mode 100644
25
index XXXXXXX..XXXXXXX
26
--- /dev/null
27
+++ b/include/hw/dma/sifive_pdma.h
28
@@ -XXX,XX +XXX,XX @@
29
+/*
30
+ * SiFive Platform DMA emulation
31
+ *
32
+ * Copyright (c) 2020 Wind River Systems, Inc.
33
+ *
34
+ * Author:
35
+ * Bin Meng <bin.meng@windriver.com>
36
+ *
37
+ * This program is free software; you can redistribute it and/or
38
+ * modify it under the terms of the GNU General Public License as
39
+ * published by the Free Software Foundation; either version 2 or
40
+ * (at your option) version 3 of the License.
41
+ *
42
+ * This program is distributed in the hope that it will be useful,
43
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
44
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
45
+ * GNU General Public License for more details.
46
+ *
47
+ * You should have received a copy of the GNU General Public License along
48
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
49
+ */
50
+
51
+#ifndef SIFIVE_PDMA_H
52
+#define SIFIVE_PDMA_H
53
+
54
+struct sifive_pdma_chan {
55
+ uint32_t control;
56
+ uint32_t next_config;
57
+ uint64_t next_bytes;
58
+ uint64_t next_dst;
59
+ uint64_t next_src;
60
+ uint32_t exec_config;
61
+ uint64_t exec_bytes;
62
+ uint64_t exec_dst;
63
+ uint64_t exec_src;
64
+ int state;
65
+};
66
+
67
+#define SIFIVE_PDMA_CHANS 4
68
+#define SIFIVE_PDMA_IRQS (SIFIVE_PDMA_CHANS * 2)
69
+#define SIFIVE_PDMA_REG_SIZE 0x100000
70
+#define SIFIVE_PDMA_CHAN_NO(reg) ((reg & (SIFIVE_PDMA_REG_SIZE - 1)) >> 12)
71
+
72
+typedef struct SiFivePDMAState {
73
+ SysBusDevice parent;
74
+ MemoryRegion iomem;
75
+ qemu_irq irq[SIFIVE_PDMA_IRQS];
76
+
77
+ struct sifive_pdma_chan chan[SIFIVE_PDMA_CHANS];
78
+} SiFivePDMAState;
79
+
80
+#define TYPE_SIFIVE_PDMA "sifive.pdma"
81
+
82
+#define SIFIVE_PDMA(obj) \
83
+ OBJECT_CHECK(SiFivePDMAState, (obj), TYPE_SIFIVE_PDMA)
84
+
85
+#endif /* SIFIVE_PDMA_H */
86
diff --git a/hw/dma/sifive_pdma.c b/hw/dma/sifive_pdma.c
87
new file mode 100644
88
index XXXXXXX..XXXXXXX
89
--- /dev/null
90
+++ b/hw/dma/sifive_pdma.c
91
@@ -XXX,XX +XXX,XX @@
92
+/*
93
+ * SiFive Platform DMA emulation
94
+ *
95
+ * Copyright (c) 2020 Wind River Systems, Inc.
96
+ *
97
+ * Author:
98
+ * Bin Meng <bin.meng@windriver.com>
99
+ *
100
+ * This program is free software; you can redistribute it and/or
101
+ * modify it under the terms of the GNU General Public License as
102
+ * published by the Free Software Foundation; either version 2 or
103
+ * (at your option) version 3 of the License.
104
+ *
105
+ * This program is distributed in the hope that it will be useful,
106
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
107
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
108
+ * GNU General Public License for more details.
109
+ *
110
+ * You should have received a copy of the GNU General Public License along
111
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
112
+ */
113
+
114
+#include "qemu/osdep.h"
115
+#include "qemu/bitops.h"
116
+#include "qemu/log.h"
117
+#include "qapi/error.h"
118
+#include "hw/hw.h"
119
+#include "hw/irq.h"
120
+#include "hw/qdev-properties.h"
121
+#include "hw/sysbus.h"
122
+#include "migration/vmstate.h"
123
+#include "sysemu/dma.h"
124
+#include "hw/dma/sifive_pdma.h"
125
+
126
+#define DMA_CONTROL 0x000
127
+#define CONTROL_CLAIM BIT(0)
128
+#define CONTROL_RUN BIT(1)
129
+#define CONTROL_DONE_IE BIT(14)
130
+#define CONTROL_ERR_IE BIT(15)
131
+#define CONTROL_DONE BIT(30)
132
+#define CONTROL_ERR BIT(31)
133
+
134
+#define DMA_NEXT_CONFIG 0x004
135
+#define CONFIG_REPEAT BIT(2)
136
+#define CONFIG_ORDER BIT(3)
137
+#define CONFIG_WRSZ_SHIFT 24
138
+#define CONFIG_RDSZ_SHIFT 28
139
+#define CONFIG_SZ_MASK 0xf
140
+
141
+#define DMA_NEXT_BYTES 0x008
142
+#define DMA_NEXT_DST 0x010
143
+#define DMA_NEXT_SRC 0x018
144
+#define DMA_EXEC_CONFIG 0x104
145
+#define DMA_EXEC_BYTES 0x108
146
+#define DMA_EXEC_DST 0x110
147
+#define DMA_EXEC_SRC 0x118
148
+
149
+enum dma_chan_state {
150
+ DMA_CHAN_STATE_IDLE,
151
+ DMA_CHAN_STATE_STARTED,
152
+ DMA_CHAN_STATE_ERROR,
153
+ DMA_CHAN_STATE_DONE
154
+};
155
+
156
+static void sifive_pdma_run(SiFivePDMAState *s, int ch)
157
+{
158
+ uint64_t bytes = s->chan[ch].next_bytes;
159
+ uint64_t dst = s->chan[ch].next_dst;
160
+ uint64_t src = s->chan[ch].next_src;
161
+ uint32_t config = s->chan[ch].next_config;
162
+ int wsize, rsize, size;
163
+ uint8_t buf[64];
164
+ int n;
165
+
166
+ /* do nothing if bytes to transfer is zero */
167
+ if (!bytes) {
168
+ goto error;
169
+ }
170
+
171
+ /*
172
+ * The manual does not describe how the hardware behaviors when
173
+ * config.wsize and config.rsize are given different values.
174
+ * A common case is memory to memory DMA, and in this case they
175
+ * are normally the same. Abort if this expectation fails.
176
+ */
177
+ wsize = (config >> CONFIG_WRSZ_SHIFT) & CONFIG_SZ_MASK;
178
+ rsize = (config >> CONFIG_RDSZ_SHIFT) & CONFIG_SZ_MASK;
179
+ if (wsize != rsize) {
180
+ goto error;
181
+ }
182
+
183
+ /*
184
+ * Calculate the transaction size
185
+ *
186
+ * size field is base 2 logarithm of DMA transaction size,
187
+ * but there is an upper limit of 64 bytes per transaction.
188
+ */
189
+ size = wsize;
190
+ if (size > 6) {
191
+ size = 6;
192
+ }
193
+ size = 1 << size;
194
+
195
+ /* the bytes to transfer should be multiple of transaction size */
196
+ if (bytes % size) {
197
+ goto error;
198
+ }
199
+
200
+ /* indicate a DMA transfer is started */
201
+ s->chan[ch].state = DMA_CHAN_STATE_STARTED;
202
+ s->chan[ch].control &= ~CONTROL_DONE;
203
+ s->chan[ch].control &= ~CONTROL_ERR;
204
+
205
+ /* load the next_ registers into their exec_ counterparts */
206
+ s->chan[ch].exec_config = config;
207
+ s->chan[ch].exec_bytes = bytes;
208
+ s->chan[ch].exec_dst = dst;
209
+ s->chan[ch].exec_src = src;
210
+
211
+ for (n = 0; n < bytes / size; n++) {
212
+ cpu_physical_memory_read(s->chan[ch].exec_src, buf, size);
213
+ cpu_physical_memory_write(s->chan[ch].exec_dst, buf, size);
214
+ s->chan[ch].exec_src += size;
215
+ s->chan[ch].exec_dst += size;
216
+ s->chan[ch].exec_bytes -= size;
217
+ }
218
+
219
+ /* indicate a DMA transfer is done */
220
+ s->chan[ch].state = DMA_CHAN_STATE_DONE;
221
+ s->chan[ch].control &= ~CONTROL_RUN;
222
+ s->chan[ch].control |= CONTROL_DONE;
223
+
224
+ /* reload exec_ registers if repeat is required */
225
+ if (s->chan[ch].next_config & CONFIG_REPEAT) {
226
+ s->chan[ch].exec_bytes = bytes;
227
+ s->chan[ch].exec_dst = dst;
228
+ s->chan[ch].exec_src = src;
229
+ }
230
+
231
+ return;
232
+
233
+error:
234
+ s->chan[ch].state = DMA_CHAN_STATE_ERROR;
235
+ s->chan[ch].control |= CONTROL_ERR;
236
+ return;
237
+}
238
+
239
+static inline void sifive_pdma_update_irq(SiFivePDMAState *s, int ch)
240
+{
241
+ bool done_ie, err_ie;
242
+
243
+ done_ie = !!(s->chan[ch].control & CONTROL_DONE_IE);
244
+ err_ie = !!(s->chan[ch].control & CONTROL_ERR_IE);
245
+
246
+ if (done_ie && (s->chan[ch].control & CONTROL_DONE)) {
247
+ qemu_irq_raise(s->irq[ch * 2]);
248
+ } else {
249
+ qemu_irq_lower(s->irq[ch * 2]);
250
+ }
251
+
252
+ if (err_ie && (s->chan[ch].control & CONTROL_ERR)) {
253
+ qemu_irq_raise(s->irq[ch * 2 + 1]);
254
+ } else {
255
+ qemu_irq_lower(s->irq[ch * 2 + 1]);
256
+ }
257
+
258
+ s->chan[ch].state = DMA_CHAN_STATE_IDLE;
259
+}
260
+
261
+static uint64_t sifive_pdma_read(void *opaque, hwaddr offset, unsigned size)
262
+{
263
+ SiFivePDMAState *s = opaque;
264
+ int ch = SIFIVE_PDMA_CHAN_NO(offset);
265
+ uint64_t val = 0;
266
+
267
+ if (ch >= SIFIVE_PDMA_CHANS) {
268
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid channel no %d\n",
269
+ __func__, ch);
270
+ return 0;
271
+ }
272
+
273
+ offset &= 0xfff;
274
+ switch (offset) {
275
+ case DMA_CONTROL:
276
+ val = s->chan[ch].control;
277
+ break;
278
+ case DMA_NEXT_CONFIG:
279
+ val = s->chan[ch].next_config;
280
+ break;
281
+ case DMA_NEXT_BYTES:
282
+ val = s->chan[ch].next_bytes;
283
+ break;
284
+ case DMA_NEXT_DST:
285
+ val = s->chan[ch].next_dst;
286
+ break;
287
+ case DMA_NEXT_SRC:
288
+ val = s->chan[ch].next_src;
289
+ break;
290
+ case DMA_EXEC_CONFIG:
291
+ val = s->chan[ch].exec_config;
292
+ break;
293
+ case DMA_EXEC_BYTES:
294
+ val = s->chan[ch].exec_bytes;
295
+ break;
296
+ case DMA_EXEC_DST:
297
+ val = s->chan[ch].exec_dst;
298
+ break;
299
+ case DMA_EXEC_SRC:
300
+ val = s->chan[ch].exec_src;
301
+ break;
302
+ default:
303
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n",
304
+ __func__, offset);
305
+ break;
306
+ }
307
+
308
+ return val;
309
+}
310
+
311
+static void sifive_pdma_write(void *opaque, hwaddr offset,
312
+ uint64_t value, unsigned size)
313
+{
314
+ SiFivePDMAState *s = opaque;
315
+ int ch = SIFIVE_PDMA_CHAN_NO(offset);
316
+
317
+ if (ch >= SIFIVE_PDMA_CHANS) {
318
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid channel no %d\n",
319
+ __func__, ch);
320
+ return;
321
+ }
322
+
323
+ offset &= 0xfff;
324
+ switch (offset) {
325
+ case DMA_CONTROL:
326
+ s->chan[ch].control = value;
327
+
328
+ if (value & CONTROL_RUN) {
329
+ sifive_pdma_run(s, ch);
330
+ }
331
+
332
+ sifive_pdma_update_irq(s, ch);
333
+ break;
334
+ case DMA_NEXT_CONFIG:
335
+ s->chan[ch].next_config = value;
336
+ break;
337
+ case DMA_NEXT_BYTES:
338
+ s->chan[ch].next_bytes = value;
339
+ break;
340
+ case DMA_NEXT_DST:
341
+ s->chan[ch].next_dst = value;
342
+ break;
343
+ case DMA_NEXT_SRC:
344
+ s->chan[ch].next_src = value;
345
+ break;
346
+ case DMA_EXEC_CONFIG:
347
+ case DMA_EXEC_BYTES:
348
+ case DMA_EXEC_DST:
349
+ case DMA_EXEC_SRC:
350
+ /* these are read-only registers */
351
+ break;
352
+ default:
353
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n",
354
+ __func__, offset);
355
+ break;
356
+ }
357
+}
358
+
359
+static const MemoryRegionOps sifive_pdma_ops = {
360
+ .read = sifive_pdma_read,
361
+ .write = sifive_pdma_write,
362
+ .endianness = DEVICE_LITTLE_ENDIAN,
363
+ /* there are 32-bit and 64-bit wide registers */
364
+ .impl = {
365
+ .min_access_size = 4,
366
+ .max_access_size = 8,
367
+ }
368
+};
369
+
370
+static void sifive_pdma_realize(DeviceState *dev, Error **errp)
371
+{
372
+ SiFivePDMAState *s = SIFIVE_PDMA(dev);
373
+ int i;
374
+
375
+ memory_region_init_io(&s->iomem, OBJECT(dev), &sifive_pdma_ops, s,
376
+ TYPE_SIFIVE_PDMA, SIFIVE_PDMA_REG_SIZE);
377
+ sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem);
378
+
379
+ for (i = 0; i < SIFIVE_PDMA_IRQS; i++) {
380
+ sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq[i]);
381
+ }
382
+}
383
+
384
+static void sifive_pdma_class_init(ObjectClass *klass, void *data)
385
+{
386
+ DeviceClass *dc = DEVICE_CLASS(klass);
387
+
388
+ dc->desc = "SiFive Platform DMA controller";
389
+ dc->realize = sifive_pdma_realize;
390
+}
391
+
392
+static const TypeInfo sifive_pdma_info = {
393
+ .name = TYPE_SIFIVE_PDMA,
394
+ .parent = TYPE_SYS_BUS_DEVICE,
395
+ .instance_size = sizeof(SiFivePDMAState),
396
+ .class_init = sifive_pdma_class_init,
397
+};
398
+
399
+static void sifive_pdma_register_types(void)
400
+{
401
+ type_register_static(&sifive_pdma_info);
402
+}
403
+
404
+type_init(sifive_pdma_register_types)
405
diff --git a/hw/dma/Kconfig b/hw/dma/Kconfig
406
index XXXXXXX..XXXXXXX 100644
407
--- a/hw/dma/Kconfig
408
+++ b/hw/dma/Kconfig
409
@@ -XXX,XX +XXX,XX @@ config ZYNQ_DEVCFG
410
411
config STP2000
412
bool
413
+
414
+config SIFIVE_PDMA
415
+ bool
416
diff --git a/hw/dma/meson.build b/hw/dma/meson.build
417
index XXXXXXX..XXXXXXX 100644
418
--- a/hw/dma/meson.build
419
+++ b/hw/dma/meson.build
420
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: files('xlnx-zdma.c'))
421
softmmu_ss.add(when: 'CONFIG_OMAP', if_true: files('omap_dma.c', 'soc_dma.c'))
422
softmmu_ss.add(when: 'CONFIG_PXA2XX', if_true: files('pxa2xx_dma.c'))
423
softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_dma.c'))
424
+softmmu_ss.add(when: 'CONFIG_SIFIVE_PDMA', if_true: files('sifive_pdma.c'))
425
--
426
2.28.0
427
428
diff view generated by jsdifflib
New patch
[PULL 12/30] hw/riscv: microchip_pfsoc: Connect a DMA controller
1
From: Bin Meng <bin.meng@windriver.com>
1
2
3
On the Icicle Kit board, the HSS firmware utilizes the on-chip DMA
4
controller to move the 2nd stage bootloader in the system memory.
5
Let's connect a DMA controller to Microchip PolarFire SoC.
6
7
Signed-off-by: Bin Meng <bin.meng@windriver.com>
8
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
9
Message-Id: <1598924352-89526-11-git-send-email-bmeng.cn@gmail.com>
10
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
11
---
12
include/hw/riscv/microchip_pfsoc.h | 11 +++++++++++
13
hw/riscv/microchip_pfsoc.c | 15 +++++++++++++++
14
hw/riscv/Kconfig | 1 +
15
3 files changed, 27 insertions(+)
16
17
diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h
18
index XXXXXXX..XXXXXXX 100644
19
--- a/include/hw/riscv/microchip_pfsoc.h
20
+++ b/include/hw/riscv/microchip_pfsoc.h
21
@@ -XXX,XX +XXX,XX @@
22
#define HW_MICROCHIP_PFSOC_H
23
24
#include "hw/char/mchp_pfsoc_mmuart.h"
25
+#include "hw/dma/sifive_pdma.h"
26
#include "hw/sd/cadence_sdhci.h"
27
28
typedef struct MicrochipPFSoCState {
29
@@ -XXX,XX +XXX,XX @@ typedef struct MicrochipPFSoCState {
30
MchpPfSoCMMUartState *serial2;
31
MchpPfSoCMMUartState *serial3;
32
MchpPfSoCMMUartState *serial4;
33
+ SiFivePDMAState dma;
34
CadenceSDHCIState sdhci;
35
} MicrochipPFSoCState;
36
37
@@ -XXX,XX +XXX,XX @@ enum {
38
MICROCHIP_PFSOC_BUSERR_UNIT4,
39
MICROCHIP_PFSOC_CLINT,
40
MICROCHIP_PFSOC_L2CC,
41
+ MICROCHIP_PFSOC_DMA,
42
MICROCHIP_PFSOC_L2LIM,
43
MICROCHIP_PFSOC_PLIC,
44
MICROCHIP_PFSOC_MMUART0,
45
@@ -XXX,XX +XXX,XX @@ enum {
46
};
47
48
enum {
49
+ MICROCHIP_PFSOC_DMA_IRQ0 = 5,
50
+ MICROCHIP_PFSOC_DMA_IRQ1 = 6,
51
+ MICROCHIP_PFSOC_DMA_IRQ2 = 7,
52
+ MICROCHIP_PFSOC_DMA_IRQ3 = 8,
53
+ MICROCHIP_PFSOC_DMA_IRQ4 = 9,
54
+ MICROCHIP_PFSOC_DMA_IRQ5 = 10,
55
+ MICROCHIP_PFSOC_DMA_IRQ6 = 11,
56
+ MICROCHIP_PFSOC_DMA_IRQ7 = 12,
57
MICROCHIP_PFSOC_EMMC_SD_IRQ = 88,
58
MICROCHIP_PFSOC_MMUART0_IRQ = 90,
59
MICROCHIP_PFSOC_MMUART1_IRQ = 91,
60
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
61
index XXXXXXX..XXXXXXX 100644
62
--- a/hw/riscv/microchip_pfsoc.c
63
+++ b/hw/riscv/microchip_pfsoc.c
64
@@ -XXX,XX +XXX,XX @@
65
* 2) eNVM (Embedded Non-Volatile Memory)
66
* 3) MMUARTs (Multi-Mode UART)
67
* 4) Cadence eMMC/SDHC controller and an SD card connected to it
68
+ * 5) SiFive Platform DMA (Direct Memory Access Controller)
69
*
70
* This board currently generates devicetree dynamically that indicates at least
71
* two harts and up to five harts.
72
@@ -XXX,XX +XXX,XX @@ static const struct MemmapEntry {
73
[MICROCHIP_PFSOC_BUSERR_UNIT4] = { 0x1704000, 0x1000 },
74
[MICROCHIP_PFSOC_CLINT] = { 0x2000000, 0x10000 },
75
[MICROCHIP_PFSOC_L2CC] = { 0x2010000, 0x1000 },
76
+ [MICROCHIP_PFSOC_DMA] = { 0x3000000, 0x100000 },
77
[MICROCHIP_PFSOC_L2LIM] = { 0x8000000, 0x2000000 },
78
[MICROCHIP_PFSOC_PLIC] = { 0xc000000, 0x4000000 },
79
[MICROCHIP_PFSOC_MMUART0] = { 0x20000000, 0x1000 },
80
@@ -XXX,XX +XXX,XX @@ static void microchip_pfsoc_soc_instance_init(Object *obj)
81
TYPE_RISCV_CPU_SIFIVE_U54);
82
qdev_prop_set_uint64(DEVICE(&s->u_cpus), "resetvec", RESET_VECTOR);
83
84
+ object_initialize_child(obj, "dma-controller", &s->dma,
85
+ TYPE_SIFIVE_PDMA);
86
+
87
object_initialize_child(obj, "sd-controller", &s->sdhci,
88
TYPE_CADENCE_SDHCI);
89
}
90
@@ -XXX,XX +XXX,XX @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
91
memmap[MICROCHIP_PFSOC_PLIC].size);
92
g_free(plic_hart_config);
93
94
+ /* DMA */
95
+ sysbus_realize(SYS_BUS_DEVICE(&s->dma), errp);
96
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->dma), 0,
97
+ memmap[MICROCHIP_PFSOC_DMA].base);
98
+ for (i = 0; i < SIFIVE_PDMA_IRQS; i++) {
99
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->dma), i,
100
+ qdev_get_gpio_in(DEVICE(s->plic),
101
+ MICROCHIP_PFSOC_DMA_IRQ0 + i));
102
+ }
103
+
104
/* SYSREG */
105
create_unimplemented_device("microchip.pfsoc.sysreg",
106
memmap[MICROCHIP_PFSOC_SYSREG].base,
107
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
108
index XXXXXXX..XXXXXXX 100644
109
--- a/hw/riscv/Kconfig
110
+++ b/hw/riscv/Kconfig
111
@@ -XXX,XX +XXX,XX @@ config MICROCHIP_PFSOC
112
select SIFIVE
113
select UNIMP
114
select MCHP_PFSOC_MMUART
115
+ select SIFIVE_PDMA
116
select CADENCE_SDHCI
117
--
118
2.28.0
119
120
diff view generated by jsdifflib
New patch
[PULL 13/30] hw/net: cadence_gem: Add a new 'phy-addr' property
1
From: Bin Meng <bin.meng@windriver.com>
1
2
3
At present the PHY address of the PHY connected to GEM is hard-coded
4
to either 23 (BOARD_PHY_ADDRESS) or 0. This might not be the case for
5
all boards. Add a new 'phy-addr' property so that board can specify
6
the PHY address for each GEM instance.
7
8
Signed-off-by: Bin Meng <bin.meng@windriver.com>
9
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
10
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
11
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
12
Message-Id: <1598924352-89526-12-git-send-email-bmeng.cn@gmail.com>
13
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
14
---
15
include/hw/net/cadence_gem.h | 2 ++
16
hw/net/cadence_gem.c | 5 +++--
17
2 files changed, 5 insertions(+), 2 deletions(-)
18
19
diff --git a/include/hw/net/cadence_gem.h b/include/hw/net/cadence_gem.h
20
index XXXXXXX..XXXXXXX 100644
21
--- a/include/hw/net/cadence_gem.h
22
+++ b/include/hw/net/cadence_gem.h
23
@@ -XXX,XX +XXX,XX @@ typedef struct CadenceGEMState {
24
/* Mask of register bits which are write 1 to clear */
25
uint32_t regs_w1c[CADENCE_GEM_MAXREG];
26
27
+ /* PHY address */
28
+ uint8_t phy_addr;
29
/* PHY registers backing store */
30
uint16_t phy_regs[32];
31
32
diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
33
index XXXXXXX..XXXXXXX 100644
34
--- a/hw/net/cadence_gem.c
35
+++ b/hw/net/cadence_gem.c
36
@@ -XXX,XX +XXX,XX @@ static uint64_t gem_read(void *opaque, hwaddr offset, unsigned size)
37
uint32_t phy_addr, reg_num;
38
39
phy_addr = (retval & GEM_PHYMNTNC_ADDR) >> GEM_PHYMNTNC_ADDR_SHFT;
40
- if (phy_addr == BOARD_PHY_ADDRESS || phy_addr == 0) {
41
+ if (phy_addr == s->phy_addr || phy_addr == 0) {
42
reg_num = (retval & GEM_PHYMNTNC_REG) >> GEM_PHYMNTNC_REG_SHIFT;
43
retval &= 0xFFFF0000;
44
retval |= gem_phy_read(s, reg_num);
45
@@ -XXX,XX +XXX,XX @@ static void gem_write(void *opaque, hwaddr offset, uint64_t val,
46
uint32_t phy_addr, reg_num;
47
48
phy_addr = (val & GEM_PHYMNTNC_ADDR) >> GEM_PHYMNTNC_ADDR_SHFT;
49
- if (phy_addr == BOARD_PHY_ADDRESS || phy_addr == 0) {
50
+ if (phy_addr == s->phy_addr || phy_addr == 0) {
51
reg_num = (val & GEM_PHYMNTNC_REG) >> GEM_PHYMNTNC_REG_SHIFT;
52
gem_phy_write(s, reg_num, val);
53
}
54
@@ -XXX,XX +XXX,XX @@ static Property gem_properties[] = {
55
DEFINE_NIC_PROPERTIES(CadenceGEMState, conf),
56
DEFINE_PROP_UINT32("revision", CadenceGEMState, revision,
57
GEM_MODID_VALUE),
58
+ DEFINE_PROP_UINT8("phy-addr", CadenceGEMState, phy_addr, BOARD_PHY_ADDRESS),
59
DEFINE_PROP_UINT8("num-priority-queues", CadenceGEMState,
60
num_priority_queues, 1),
61
DEFINE_PROP_UINT8("num-type1-screeners", CadenceGEMState,
62
--
63
2.28.0
64
65
diff view generated by jsdifflib
[PULL 01/12] hw/block: m25p80: Don't write to flash if write is disabled
[PULL 14/30] hw/arm: xlnx: Set all boards' GEM 'phy-addr' property value to 23
1
From: Bin Meng <bin.meng@windriver.com>
1
From: Bin Meng <bin.meng@windriver.com>
2
2
3
When write is disabled, the write to flash should be avoided
3
When cadence_gem model was created for Xilinx boards, the PHY address
4
in flash_write8().
4
was hard-coded to 23 in the GEM model. Now that we have introduced a
5
property we can use that to tell GEM model what our PHY address is.
6
Change all boards' GEM 'phy-addr' property value to 23, and set the
7
PHY address default value to 0 in the GEM model.
5
8
6
Fixes: 82a2499011a7 ("m25p80: Initial implementation of SPI flash device")
7
Signed-off-by: Bin Meng <bin.meng@windriver.com>
9
Signed-off-by: Bin Meng <bin.meng@windriver.com>
8
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
10
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
11
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
10
Message-id: 1608688825-81519-1-git-send-email-bmeng.cn@gmail.com
12
Message-Id: <1598924352-89526-13-git-send-email-bmeng.cn@gmail.com>
11
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
13
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
12
---
14
---
13
hw/block/m25p80.c | 1 +
15
hw/arm/xilinx_zynq.c | 1 +
14
1 file changed, 1 insertion(+)
16
hw/arm/xlnx-versal.c | 1 +
17
hw/arm/xlnx-zynqmp.c | 2 ++
18
hw/net/cadence_gem.c | 6 +++---
19
4 files changed, 7 insertions(+), 3 deletions(-)
15
20
16
diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
21
diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c
17
index XXXXXXX..XXXXXXX 100644
22
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/block/m25p80.c
23
--- a/hw/arm/xilinx_zynq.c
19
+++ b/hw/block/m25p80.c
24
+++ b/hw/arm/xilinx_zynq.c
20
@@ -XXX,XX +XXX,XX @@ void flash_write8(Flash *s, uint32_t addr, uint8_t data)
25
@@ -XXX,XX +XXX,XX @@ static void gem_init(NICInfo *nd, uint32_t base, qemu_irq irq)
21
26
qemu_check_nic_model(nd, TYPE_CADENCE_GEM);
22
if (!s->write_enable) {
27
qdev_set_nic_properties(dev, nd);
23
qemu_log_mask(LOG_GUEST_ERROR, "M25P80: write with write protect!\n");
24
+ return;
25
}
28
}
26
29
+ object_property_set_int(OBJECT(dev), "phy-addr", 23, &error_abort);
27
if ((prev ^ data) & data) {
30
s = SYS_BUS_DEVICE(dev);
31
sysbus_realize_and_unref(s, &error_fatal);
32
sysbus_mmio_map(s, 0, base);
33
diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c
34
index XXXXXXX..XXXXXXX 100644
35
--- a/hw/arm/xlnx-versal.c
36
+++ b/hw/arm/xlnx-versal.c
37
@@ -XXX,XX +XXX,XX @@ static void versal_create_gems(Versal *s, qemu_irq *pic)
38
qemu_check_nic_model(nd, "cadence_gem");
39
qdev_set_nic_properties(dev, nd);
40
}
41
+ object_property_set_int(OBJECT(dev), "phy-addr", 23, &error_abort);
42
object_property_set_int(OBJECT(dev), "num-priority-queues", 2,
43
&error_abort);
44
object_property_set_link(OBJECT(dev), "dma", OBJECT(&s->mr_ps),
45
diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
46
index XXXXXXX..XXXXXXX 100644
47
--- a/hw/arm/xlnx-zynqmp.c
48
+++ b/hw/arm/xlnx-zynqmp.c
49
@@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
50
}
51
object_property_set_int(OBJECT(&s->gem[i]), "revision", GEM_REVISION,
52
&error_abort);
53
+ object_property_set_int(OBJECT(&s->gem[i]), "phy-addr", 23,
54
+ &error_abort);
55
object_property_set_int(OBJECT(&s->gem[i]), "num-priority-queues", 2,
56
&error_abort);
57
if (!sysbus_realize(SYS_BUS_DEVICE(&s->gem[i]), errp)) {
58
diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
59
index XXXXXXX..XXXXXXX 100644
60
--- a/hw/net/cadence_gem.c
61
+++ b/hw/net/cadence_gem.c
62
@@ -XXX,XX +XXX,XX @@
63
#define GEM_PHYMNTNC_REG_SHIFT 18
64
65
/* Marvell PHY definitions */
66
-#define BOARD_PHY_ADDRESS 23 /* PHY address we will emulate a device at */
67
+#define BOARD_PHY_ADDRESS 0 /* PHY address we will emulate a device at */
68
69
#define PHY_REG_CONTROL 0
70
#define PHY_REG_STATUS 1
71
@@ -XXX,XX +XXX,XX @@ static uint64_t gem_read(void *opaque, hwaddr offset, unsigned size)
72
uint32_t phy_addr, reg_num;
73
74
phy_addr = (retval & GEM_PHYMNTNC_ADDR) >> GEM_PHYMNTNC_ADDR_SHFT;
75
- if (phy_addr == s->phy_addr || phy_addr == 0) {
76
+ if (phy_addr == s->phy_addr) {
77
reg_num = (retval & GEM_PHYMNTNC_REG) >> GEM_PHYMNTNC_REG_SHIFT;
78
retval &= 0xFFFF0000;
79
retval |= gem_phy_read(s, reg_num);
80
@@ -XXX,XX +XXX,XX @@ static void gem_write(void *opaque, hwaddr offset, uint64_t val,
81
uint32_t phy_addr, reg_num;
82
83
phy_addr = (val & GEM_PHYMNTNC_ADDR) >> GEM_PHYMNTNC_ADDR_SHFT;
84
- if (phy_addr == s->phy_addr || phy_addr == 0) {
85
+ if (phy_addr == s->phy_addr) {
86
reg_num = (val & GEM_PHYMNTNC_REG) >> GEM_PHYMNTNC_REG_SHIFT;
87
gem_phy_write(s, reg_num, val);
88
}
28
--
89
--
29
2.29.2
90
2.28.0
30
91
31
92
diff view generated by jsdifflib
[PULL 05/12] target/riscv/pmp: Raise exception if no PMP entry is configured
[PULL 15/30] hw/riscv: microchip_pfsoc: Connect 2 Cadence GEMs
1
From: Atish Patra <atish.patra@wdc.com>
1
From: Bin Meng <bin.meng@windriver.com>
2
2
3
As per the privilege specification, any access from S/U mode should fail
3
Microchip PolarFire SoC integrates 2 Candence GEMs to provide
4
if no pmp region is configured.
4
IEEE 802.3 standard-compliant 10/100/1000 Mbps ethernet interface.
5
5
6
Signed-off-by: Atish Patra <atish.patra@wdc.com>
6
On the Icicle Kit board, GEM0 connects to a PHY at address 8 while
7
GEM1 connects to a PHY at address 9.
8
9
The 2nd stage bootloader (U-Boot) is using GEM1 by default, so we
10
must specify 2 '-nic' options from the command line in order to get
11
a working ethernet.
12
13
Signed-off-by: Bin Meng <bin.meng@windriver.com>
7
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
14
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
8
Message-id: 20201223192553.332508-1-atish.patra@wdc.com
15
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
16
Message-Id: <1598924352-89526-14-git-send-email-bmeng.cn@gmail.com>
9
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
17
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
10
---
18
---
11
target/riscv/pmp.h | 1 +
19
include/hw/riscv/microchip_pfsoc.h | 7 ++++++
12
target/riscv/op_helper.c | 5 +++++
20
hw/riscv/microchip_pfsoc.c | 39 ++++++++++++++++++++++++++++++
13
target/riscv/pmp.c | 4 ++--
21
2 files changed, 46 insertions(+)
14
3 files changed, 8 insertions(+), 2 deletions(-)
15
22
16
diff --git a/target/riscv/pmp.h b/target/riscv/pmp.h
23
diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h
17
index XXXXXXX..XXXXXXX 100644
24
index XXXXXXX..XXXXXXX 100644
18
--- a/target/riscv/pmp.h
25
--- a/include/hw/riscv/microchip_pfsoc.h
19
+++ b/target/riscv/pmp.h
26
+++ b/include/hw/riscv/microchip_pfsoc.h
20
@@ -XXX,XX +XXX,XX @@ bool pmp_is_range_in_tlb(CPURISCVState *env, hwaddr tlb_sa,
27
@@ -XXX,XX +XXX,XX @@
21
target_ulong *tlb_size);
28
22
void pmp_update_rule_addr(CPURISCVState *env, uint32_t pmp_index);
29
#include "hw/char/mchp_pfsoc_mmuart.h"
23
void pmp_update_rule_nums(CPURISCVState *env);
30
#include "hw/dma/sifive_pdma.h"
24
+uint32_t pmp_get_num_rules(CPURISCVState *env);
31
+#include "hw/net/cadence_gem.h"
25
32
#include "hw/sd/cadence_sdhci.h"
26
#endif
33
27
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
34
typedef struct MicrochipPFSoCState {
35
@@ -XXX,XX +XXX,XX @@ typedef struct MicrochipPFSoCState {
36
MchpPfSoCMMUartState *serial3;
37
MchpPfSoCMMUartState *serial4;
38
SiFivePDMAState dma;
39
+ CadenceGEMState gem0;
40
+ CadenceGEMState gem1;
41
CadenceSDHCIState sdhci;
42
} MicrochipPFSoCState;
43
44
@@ -XXX,XX +XXX,XX @@ enum {
45
MICROCHIP_PFSOC_MMUART2,
46
MICROCHIP_PFSOC_MMUART3,
47
MICROCHIP_PFSOC_MMUART4,
48
+ MICROCHIP_PFSOC_GEM0,
49
+ MICROCHIP_PFSOC_GEM1,
50
MICROCHIP_PFSOC_ENVM_CFG,
51
MICROCHIP_PFSOC_ENVM_DATA,
52
MICROCHIP_PFSOC_IOSCB_CFG,
53
@@ -XXX,XX +XXX,XX @@ enum {
54
MICROCHIP_PFSOC_DMA_IRQ5 = 10,
55
MICROCHIP_PFSOC_DMA_IRQ6 = 11,
56
MICROCHIP_PFSOC_DMA_IRQ7 = 12,
57
+ MICROCHIP_PFSOC_GEM0_IRQ = 64,
58
+ MICROCHIP_PFSOC_GEM1_IRQ = 70,
59
MICROCHIP_PFSOC_EMMC_SD_IRQ = 88,
60
MICROCHIP_PFSOC_MMUART0_IRQ = 90,
61
MICROCHIP_PFSOC_MMUART1_IRQ = 91,
62
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
28
index XXXXXXX..XXXXXXX 100644
63
index XXXXXXX..XXXXXXX 100644
29
--- a/target/riscv/op_helper.c
64
--- a/hw/riscv/microchip_pfsoc.c
30
+++ b/target/riscv/op_helper.c
65
+++ b/hw/riscv/microchip_pfsoc.c
31
@@ -XXX,XX +XXX,XX @@ target_ulong helper_mret(CPURISCVState *env, target_ulong cpu_pc_deb)
66
@@ -XXX,XX +XXX,XX @@
32
67
* 3) MMUARTs (Multi-Mode UART)
33
uint64_t mstatus = env->mstatus;
68
* 4) Cadence eMMC/SDHC controller and an SD card connected to it
34
target_ulong prev_priv = get_field(mstatus, MSTATUS_MPP);
69
* 5) SiFive Platform DMA (Direct Memory Access Controller)
70
+ * 6) GEM (Gigabit Ethernet MAC Controller)
71
*
72
* This board currently generates devicetree dynamically that indicates at least
73
* two harts and up to five harts.
74
@@ -XXX,XX +XXX,XX @@
75
#define BIOS_FILENAME "hss.bin"
76
#define RESET_VECTOR 0x20220000
77
78
+/* GEM version */
79
+#define GEM_REVISION 0x0107010c
35
+
80
+
36
+ if (!pmp_get_num_rules(env) && (prev_priv != PRV_M)) {
81
static const struct MemmapEntry {
37
+ riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
82
hwaddr base;
83
hwaddr size;
84
@@ -XXX,XX +XXX,XX @@ static const struct MemmapEntry {
85
[MICROCHIP_PFSOC_MMUART2] = { 0x20102000, 0x1000 },
86
[MICROCHIP_PFSOC_MMUART3] = { 0x20104000, 0x1000 },
87
[MICROCHIP_PFSOC_MMUART4] = { 0x20106000, 0x1000 },
88
+ [MICROCHIP_PFSOC_GEM0] = { 0x20110000, 0x2000 },
89
+ [MICROCHIP_PFSOC_GEM1] = { 0x20112000, 0x2000 },
90
[MICROCHIP_PFSOC_ENVM_CFG] = { 0x20200000, 0x1000 },
91
[MICROCHIP_PFSOC_ENVM_DATA] = { 0x20220000, 0x20000 },
92
[MICROCHIP_PFSOC_IOSCB_CFG] = { 0x37080000, 0x1000 },
93
@@ -XXX,XX +XXX,XX @@ static void microchip_pfsoc_soc_instance_init(Object *obj)
94
object_initialize_child(obj, "dma-controller", &s->dma,
95
TYPE_SIFIVE_PDMA);
96
97
+ object_initialize_child(obj, "gem0", &s->gem0, TYPE_CADENCE_GEM);
98
+ object_initialize_child(obj, "gem1", &s->gem1, TYPE_CADENCE_GEM);
99
+
100
object_initialize_child(obj, "sd-controller", &s->sdhci,
101
TYPE_CADENCE_SDHCI);
102
}
103
@@ -XXX,XX +XXX,XX @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
104
MemoryRegion *envm_data = g_new(MemoryRegion, 1);
105
char *plic_hart_config;
106
size_t plic_hart_config_len;
107
+ NICInfo *nd;
108
int i;
109
110
sysbus_realize(SYS_BUS_DEVICE(&s->e_cpus), &error_abort);
111
@@ -XXX,XX +XXX,XX @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
112
qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART4_IRQ),
113
serial_hd(4));
114
115
+ /* GEMs */
116
+
117
+ nd = &nd_table[0];
118
+ if (nd->used) {
119
+ qemu_check_nic_model(nd, TYPE_CADENCE_GEM);
120
+ qdev_set_nic_properties(DEVICE(&s->gem0), nd);
121
+ }
122
+ nd = &nd_table[1];
123
+ if (nd->used) {
124
+ qemu_check_nic_model(nd, TYPE_CADENCE_GEM);
125
+ qdev_set_nic_properties(DEVICE(&s->gem1), nd);
38
+ }
126
+ }
39
+
127
+
40
target_ulong prev_virt = get_field(env->mstatus, MSTATUS_MPV);
128
+ object_property_set_int(OBJECT(&s->gem0), "revision", GEM_REVISION, errp);
41
mstatus = set_field(mstatus, MSTATUS_MIE,
129
+ object_property_set_int(OBJECT(&s->gem0), "phy-addr", 8, errp);
42
get_field(mstatus, MSTATUS_MPIE));
130
+ sysbus_realize(SYS_BUS_DEVICE(&s->gem0), errp);
43
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
131
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem0), 0,
44
index XXXXXXX..XXXXXXX 100644
132
+ memmap[MICROCHIP_PFSOC_GEM0].base);
45
--- a/target/riscv/pmp.c
133
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem0), 0,
46
+++ b/target/riscv/pmp.c
134
+ qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_GEM0_IRQ));
47
@@ -XXX,XX +XXX,XX @@ static inline int pmp_is_locked(CPURISCVState *env, uint32_t pmp_index)
135
+
48
/*
136
+ object_property_set_int(OBJECT(&s->gem1), "revision", GEM_REVISION, errp);
49
* Count the number of active rules.
137
+ object_property_set_int(OBJECT(&s->gem1), "phy-addr", 9, errp);
50
*/
138
+ sysbus_realize(SYS_BUS_DEVICE(&s->gem1), errp);
51
-static inline uint32_t pmp_get_num_rules(CPURISCVState *env)
139
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem1), 0,
52
+uint32_t pmp_get_num_rules(CPURISCVState *env)
140
+ memmap[MICROCHIP_PFSOC_GEM1].base);
53
{
141
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem1), 0,
54
return env->pmp_state.num_rules;
142
+ qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_GEM1_IRQ));
55
}
143
+
56
@@ -XXX,XX +XXX,XX @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
144
/* eNVM */
57
145
memory_region_init_rom(envm_data, OBJECT(dev), "microchip.pfsoc.envm.data",
58
/* Short cut if no rules */
146
memmap[MICROCHIP_PFSOC_ENVM_DATA].size,
59
if (0 == pmp_get_num_rules(env)) {
60
- return true;
61
+ return (env->priv == PRV_M) ? true : false;
62
}
63
64
if (size == 0) {
65
--
147
--
66
2.29.2
148
2.28.0
67
149
68
150
diff view generated by jsdifflib
New patch
[PULL 16/30] hw/riscv: microchip_pfsoc: Hook GPIO controllers
1
From: Bin Meng <bin.meng@windriver.com>
1
2
3
Microchip PolarFire SoC integrates 3 GPIOs controllers. It seems
4
enough to create unimplemented devices to cover their register
5
spaces at this point.
6
7
With this commit, QEMU can boot to U-Boot (2nd stage bootloader)
8
all the way to the Linux shell login prompt, with a modified HSS
9
(1st stage bootloader).
10
11
For detailed instructions on how to create images for the Icicle
12
Kit board, please check QEMU RISC-V WiKi page at:
13
https://wiki.qemu.org/Documentation/Platforms/RISCV
14
15
Signed-off-by: Bin Meng <bin.meng@windriver.com>
16
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
17
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
18
Message-Id: <1598924352-89526-15-git-send-email-bmeng.cn@gmail.com>
19
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
20
---
21
include/hw/riscv/microchip_pfsoc.h | 3 +++
22
hw/riscv/microchip_pfsoc.c | 14 ++++++++++++++
23
2 files changed, 17 insertions(+)
24
25
diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h
26
index XXXXXXX..XXXXXXX 100644
27
--- a/include/hw/riscv/microchip_pfsoc.h
28
+++ b/include/hw/riscv/microchip_pfsoc.h
29
@@ -XXX,XX +XXX,XX @@ enum {
30
MICROCHIP_PFSOC_MMUART4,
31
MICROCHIP_PFSOC_GEM0,
32
MICROCHIP_PFSOC_GEM1,
33
+ MICROCHIP_PFSOC_GPIO0,
34
+ MICROCHIP_PFSOC_GPIO1,
35
+ MICROCHIP_PFSOC_GPIO2,
36
MICROCHIP_PFSOC_ENVM_CFG,
37
MICROCHIP_PFSOC_ENVM_DATA,
38
MICROCHIP_PFSOC_IOSCB_CFG,
39
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
40
index XXXXXXX..XXXXXXX 100644
41
--- a/hw/riscv/microchip_pfsoc.c
42
+++ b/hw/riscv/microchip_pfsoc.c
43
@@ -XXX,XX +XXX,XX @@ static const struct MemmapEntry {
44
[MICROCHIP_PFSOC_MMUART4] = { 0x20106000, 0x1000 },
45
[MICROCHIP_PFSOC_GEM0] = { 0x20110000, 0x2000 },
46
[MICROCHIP_PFSOC_GEM1] = { 0x20112000, 0x2000 },
47
+ [MICROCHIP_PFSOC_GPIO0] = { 0x20120000, 0x1000 },
48
+ [MICROCHIP_PFSOC_GPIO1] = { 0x20121000, 0x1000 },
49
+ [MICROCHIP_PFSOC_GPIO2] = { 0x20122000, 0x1000 },
50
[MICROCHIP_PFSOC_ENVM_CFG] = { 0x20200000, 0x1000 },
51
[MICROCHIP_PFSOC_ENVM_DATA] = { 0x20220000, 0x20000 },
52
[MICROCHIP_PFSOC_IOSCB_CFG] = { 0x37080000, 0x1000 },
53
@@ -XXX,XX +XXX,XX @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
54
sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem1), 0,
55
qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_GEM1_IRQ));
56
57
+ /* GPIOs */
58
+ create_unimplemented_device("microchip.pfsoc.gpio0",
59
+ memmap[MICROCHIP_PFSOC_GPIO0].base,
60
+ memmap[MICROCHIP_PFSOC_GPIO0].size);
61
+ create_unimplemented_device("microchip.pfsoc.gpio1",
62
+ memmap[MICROCHIP_PFSOC_GPIO1].base,
63
+ memmap[MICROCHIP_PFSOC_GPIO1].size);
64
+ create_unimplemented_device("microchip.pfsoc.gpio2",
65
+ memmap[MICROCHIP_PFSOC_GPIO2].base,
66
+ memmap[MICROCHIP_PFSOC_GPIO2].size);
67
+
68
/* eNVM */
69
memory_region_init_rom(envm_data, OBJECT(dev), "microchip.pfsoc.envm.data",
70
memmap[MICROCHIP_PFSOC_ENVM_DATA].size,
71
--
72
2.28.0
73
74
diff view generated by jsdifflib
[PULL 09/12] target/riscv: Add CSR name in the CSR function table
[PULL 17/30] hw/riscv: clint: Avoid using hard-coded timebase frequency
1
From: Bin Meng <bin.meng@windriver.com>
1
From: Bin Meng <bin.meng@windriver.com>
2
2
3
In preparation to generate the CSR register list for GDB stub
3
At present the CLINT timestamp is using a hard-coded timebase
4
dynamically, let's add the CSR name in the CSR function table.
4
frequency value SIFIVE_CLINT_TIMEBASE_FREQ. This might not be
5
true for all boards.
6
7
Add a new 'timebase-freq' property to the CLINT device, and
8
update various functions to accept this as a parameter.
5
9
6
Signed-off-by: Bin Meng <bin.meng@windriver.com>
10
Signed-off-by: Bin Meng <bin.meng@windriver.com>
7
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
11
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
8
Message-id: 1610427124-49887-3-git-send-email-bmeng.cn@gmail.com
12
Message-Id: <1598924352-89526-16-git-send-email-bmeng.cn@gmail.com>
9
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
13
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
10
---
14
---
11
target/riscv/cpu.h | 1 +
15
include/hw/riscv/sifive_clint.h | 4 +++-
12
target/riscv/csr.c | 332 +++++++++++++++++++++++++++++++++------------
16
target/riscv/cpu.h | 6 ++++--
13
2 files changed, 249 insertions(+), 84 deletions(-)
17
hw/riscv/microchip_pfsoc.c | 6 +++++-
14
18
hw/riscv/sifive_clint.c | 26 +++++++++++++++-----------
19
hw/riscv/sifive_e.c | 3 ++-
20
hw/riscv/sifive_u.c | 3 ++-
21
hw/riscv/spike.c | 3 ++-
22
hw/riscv/virt.c | 3 ++-
23
target/riscv/cpu_helper.c | 4 +++-
24
target/riscv/csr.c | 4 ++--
25
10 files changed, 40 insertions(+), 22 deletions(-)
26
27
diff --git a/include/hw/riscv/sifive_clint.h b/include/hw/riscv/sifive_clint.h
28
index XXXXXXX..XXXXXXX 100644
29
--- a/include/hw/riscv/sifive_clint.h
30
+++ b/include/hw/riscv/sifive_clint.h
31
@@ -XXX,XX +XXX,XX @@ typedef struct SiFiveCLINTState {
32
uint32_t timecmp_base;
33
uint32_t time_base;
34
uint32_t aperture_size;
35
+ uint32_t timebase_freq;
36
} SiFiveCLINTState;
37
38
DeviceState *sifive_clint_create(hwaddr addr, hwaddr size,
39
uint32_t hartid_base, uint32_t num_harts, uint32_t sip_base,
40
- uint32_t timecmp_base, uint32_t time_base, bool provide_rdtime);
41
+ uint32_t timecmp_base, uint32_t time_base, uint32_t timebase_freq,
42
+ bool provide_rdtime);
43
44
enum {
45
SIFIVE_SIP_BASE = 0x0,
15
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
46
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
16
index XXXXXXX..XXXXXXX 100644
47
index XXXXXXX..XXXXXXX 100644
17
--- a/target/riscv/cpu.h
48
--- a/target/riscv/cpu.h
18
+++ b/target/riscv/cpu.h
49
+++ b/target/riscv/cpu.h
19
@@ -XXX,XX +XXX,XX @@ typedef int (*riscv_csr_op_fn)(CPURISCVState *env, int csrno,
50
@@ -XXX,XX +XXX,XX @@ struct CPURISCVState {
20
target_ulong *ret_value, target_ulong new_value, target_ulong write_mask);
51
pmp_table_t pmp_state;
21
52
22
typedef struct {
53
/* machine specific rdtime callback */
23
+ const char *name;
54
- uint64_t (*rdtime_fn)(void);
24
riscv_csr_predicate_fn predicate;
55
+ uint64_t (*rdtime_fn)(uint32_t);
25
riscv_csr_read_fn read;
56
+ uint32_t rdtime_fn_arg;
26
riscv_csr_write_fn write;
57
58
/* True if in debugger mode. */
59
bool debugger;
60
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env);
61
int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts);
62
uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value);
63
#define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */
64
-void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void));
65
+void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(uint32_t),
66
+ uint32_t arg);
67
#endif
68
void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv);
69
70
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
71
index XXXXXXX..XXXXXXX 100644
72
--- a/hw/riscv/microchip_pfsoc.c
73
+++ b/hw/riscv/microchip_pfsoc.c
74
@@ -XXX,XX +XXX,XX @@
75
#define BIOS_FILENAME "hss.bin"
76
#define RESET_VECTOR 0x20220000
77
78
+/* CLINT timebase frequency */
79
+#define CLINT_TIMEBASE_FREQ 1000000
80
+
81
/* GEM version */
82
#define GEM_REVISION 0x0107010c
83
84
@@ -XXX,XX +XXX,XX @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
85
/* CLINT */
86
sifive_clint_create(memmap[MICROCHIP_PFSOC_CLINT].base,
87
memmap[MICROCHIP_PFSOC_CLINT].size, 0, ms->smp.cpus,
88
- SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, false);
89
+ SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE,
90
+ CLINT_TIMEBASE_FREQ, false);
91
92
/* L2 cache controller */
93
create_unimplemented_device("microchip.pfsoc.l2cc",
94
diff --git a/hw/riscv/sifive_clint.c b/hw/riscv/sifive_clint.c
95
index XXXXXXX..XXXXXXX 100644
96
--- a/hw/riscv/sifive_clint.c
97
+++ b/hw/riscv/sifive_clint.c
98
@@ -XXX,XX +XXX,XX @@
99
#include "hw/riscv/sifive_clint.h"
100
#include "qemu/timer.h"
101
102
-static uint64_t cpu_riscv_read_rtc(void)
103
+static uint64_t cpu_riscv_read_rtc(uint32_t timebase_freq)
104
{
105
return muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
106
- SIFIVE_CLINT_TIMEBASE_FREQ, NANOSECONDS_PER_SECOND);
107
+ timebase_freq, NANOSECONDS_PER_SECOND);
108
}
109
110
/*
111
* Called when timecmp is written to update the QEMU timer or immediately
112
* trigger timer interrupt if mtimecmp <= current timer value.
113
*/
114
-static void sifive_clint_write_timecmp(RISCVCPU *cpu, uint64_t value)
115
+static void sifive_clint_write_timecmp(RISCVCPU *cpu, uint64_t value,
116
+ uint32_t timebase_freq)
117
{
118
uint64_t next;
119
uint64_t diff;
120
121
- uint64_t rtc_r = cpu_riscv_read_rtc();
122
+ uint64_t rtc_r = cpu_riscv_read_rtc(timebase_freq);
123
124
cpu->env.timecmp = value;
125
if (cpu->env.timecmp <= rtc_r) {
126
@@ -XXX,XX +XXX,XX @@ static void sifive_clint_write_timecmp(RISCVCPU *cpu, uint64_t value)
127
diff = cpu->env.timecmp - rtc_r;
128
/* back to ns (note args switched in muldiv64) */
129
next = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
130
- muldiv64(diff, NANOSECONDS_PER_SECOND, SIFIVE_CLINT_TIMEBASE_FREQ);
131
+ muldiv64(diff, NANOSECONDS_PER_SECOND, timebase_freq);
132
timer_mod(cpu->env.timer, next);
133
}
134
135
@@ -XXX,XX +XXX,XX @@ static uint64_t sifive_clint_read(void *opaque, hwaddr addr, unsigned size)
136
}
137
} else if (addr == clint->time_base) {
138
/* time_lo */
139
- return cpu_riscv_read_rtc() & 0xFFFFFFFF;
140
+ return cpu_riscv_read_rtc(clint->timebase_freq) & 0xFFFFFFFF;
141
} else if (addr == clint->time_base + 4) {
142
/* time_hi */
143
- return (cpu_riscv_read_rtc() >> 32) & 0xFFFFFFFF;
144
+ return (cpu_riscv_read_rtc(clint->timebase_freq) >> 32) & 0xFFFFFFFF;
145
}
146
147
error_report("clint: invalid read: %08x", (uint32_t)addr);
148
@@ -XXX,XX +XXX,XX @@ static void sifive_clint_write(void *opaque, hwaddr addr, uint64_t value,
149
/* timecmp_lo */
150
uint64_t timecmp_hi = env->timecmp >> 32;
151
sifive_clint_write_timecmp(RISCV_CPU(cpu),
152
- timecmp_hi << 32 | (value & 0xFFFFFFFF));
153
+ timecmp_hi << 32 | (value & 0xFFFFFFFF), clint->timebase_freq);
154
return;
155
} else if ((addr & 0x7) == 4) {
156
/* timecmp_hi */
157
uint64_t timecmp_lo = env->timecmp;
158
sifive_clint_write_timecmp(RISCV_CPU(cpu),
159
- value << 32 | (timecmp_lo & 0xFFFFFFFF));
160
+ value << 32 | (timecmp_lo & 0xFFFFFFFF), clint->timebase_freq);
161
} else {
162
error_report("clint: invalid timecmp write: %08x", (uint32_t)addr);
163
}
164
@@ -XXX,XX +XXX,XX @@ static Property sifive_clint_properties[] = {
165
DEFINE_PROP_UINT32("timecmp-base", SiFiveCLINTState, timecmp_base, 0),
166
DEFINE_PROP_UINT32("time-base", SiFiveCLINTState, time_base, 0),
167
DEFINE_PROP_UINT32("aperture-size", SiFiveCLINTState, aperture_size, 0),
168
+ DEFINE_PROP_UINT32("timebase-freq", SiFiveCLINTState, timebase_freq, 0),
169
DEFINE_PROP_END_OF_LIST(),
170
};
171
172
@@ -XXX,XX +XXX,XX @@ type_init(sifive_clint_register_types)
173
*/
174
DeviceState *sifive_clint_create(hwaddr addr, hwaddr size,
175
uint32_t hartid_base, uint32_t num_harts, uint32_t sip_base,
176
- uint32_t timecmp_base, uint32_t time_base, bool provide_rdtime)
177
+ uint32_t timecmp_base, uint32_t time_base, uint32_t timebase_freq,
178
+ bool provide_rdtime)
179
{
180
int i;
181
for (i = 0; i < num_harts; i++) {
182
@@ -XXX,XX +XXX,XX @@ DeviceState *sifive_clint_create(hwaddr addr, hwaddr size,
183
continue;
184
}
185
if (provide_rdtime) {
186
- riscv_cpu_set_rdtime_fn(env, cpu_riscv_read_rtc);
187
+ riscv_cpu_set_rdtime_fn(env, cpu_riscv_read_rtc, timebase_freq);
188
}
189
env->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
190
&sifive_clint_timer_cb, cpu);
191
@@ -XXX,XX +XXX,XX @@ DeviceState *sifive_clint_create(hwaddr addr, hwaddr size,
192
qdev_prop_set_uint32(dev, "timecmp-base", timecmp_base);
193
qdev_prop_set_uint32(dev, "time-base", time_base);
194
qdev_prop_set_uint32(dev, "aperture-size", size);
195
+ qdev_prop_set_uint32(dev, "timebase-freq", timebase_freq);
196
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
197
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
198
return dev;
199
diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
200
index XXXXXXX..XXXXXXX 100644
201
--- a/hw/riscv/sifive_e.c
202
+++ b/hw/riscv/sifive_e.c
203
@@ -XXX,XX +XXX,XX @@ static void sifive_e_soc_realize(DeviceState *dev, Error **errp)
204
memmap[SIFIVE_E_PLIC].size);
205
sifive_clint_create(memmap[SIFIVE_E_CLINT].base,
206
memmap[SIFIVE_E_CLINT].size, 0, ms->smp.cpus,
207
- SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, false);
208
+ SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE,
209
+ SIFIVE_CLINT_TIMEBASE_FREQ, false);
210
create_unimplemented_device("riscv.sifive.e.aon",
211
memmap[SIFIVE_E_AON].base, memmap[SIFIVE_E_AON].size);
212
sifive_e_prci_create(memmap[SIFIVE_E_PRCI].base);
213
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
214
index XXXXXXX..XXXXXXX 100644
215
--- a/hw/riscv/sifive_u.c
216
+++ b/hw/riscv/sifive_u.c
217
@@ -XXX,XX +XXX,XX @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
218
serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART1_IRQ));
219
sifive_clint_create(memmap[SIFIVE_U_CLINT].base,
220
memmap[SIFIVE_U_CLINT].size, 0, ms->smp.cpus,
221
- SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, false);
222
+ SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE,
223
+ SIFIVE_CLINT_TIMEBASE_FREQ, false);
224
225
if (!sysbus_realize(SYS_BUS_DEVICE(&s->prci), errp)) {
226
return;
227
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
228
index XXXXXXX..XXXXXXX 100644
229
--- a/hw/riscv/spike.c
230
+++ b/hw/riscv/spike.c
231
@@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine)
232
sifive_clint_create(
233
memmap[SPIKE_CLINT].base + i * memmap[SPIKE_CLINT].size,
234
memmap[SPIKE_CLINT].size, base_hartid, hart_count,
235
- SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, false);
236
+ SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE,
237
+ SIFIVE_CLINT_TIMEBASE_FREQ, false);
238
}
239
240
/* register system main memory (actual RAM) */
241
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
242
index XXXXXXX..XXXXXXX 100644
243
--- a/hw/riscv/virt.c
244
+++ b/hw/riscv/virt.c
245
@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
246
sifive_clint_create(
247
memmap[VIRT_CLINT].base + i * memmap[VIRT_CLINT].size,
248
memmap[VIRT_CLINT].size, base_hartid, hart_count,
249
- SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, true);
250
+ SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE,
251
+ SIFIVE_CLINT_TIMEBASE_FREQ, true);
252
253
/* Per-socket PLIC hart topology configuration string */
254
plic_hart_config_len =
255
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
256
index XXXXXXX..XXXXXXX 100644
257
--- a/target/riscv/cpu_helper.c
258
+++ b/target/riscv/cpu_helper.c
259
@@ -XXX,XX +XXX,XX @@ uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value)
260
return old;
261
}
262
263
-void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void))
264
+void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(uint32_t),
265
+ uint32_t arg)
266
{
267
env->rdtime_fn = fn;
268
+ env->rdtime_fn_arg = arg;
269
}
270
271
void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv)
27
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
272
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
28
index XXXXXXX..XXXXXXX 100644
273
index XXXXXXX..XXXXXXX 100644
29
--- a/target/riscv/csr.c
274
--- a/target/riscv/csr.c
30
+++ b/target/riscv/csr.c
275
+++ b/target/riscv/csr.c
31
@@ -XXX,XX +XXX,XX @@ int riscv_csrrw_debug(CPURISCVState *env, int csrno, target_ulong *ret_value,
276
@@ -XXX,XX +XXX,XX @@ static int read_time(CPURISCVState *env, int csrno, target_ulong *val)
32
/* Control and Status Register function table */
277
return -RISCV_EXCP_ILLEGAL_INST;
33
riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
278
}
34
/* User Floating-Point CSRs */
279
35
- [CSR_FFLAGS] = { fs, read_fflags, write_fflags },
280
- *val = env->rdtime_fn() + delta;
36
- [CSR_FRM] = { fs, read_frm, write_frm },
281
+ *val = env->rdtime_fn(env->rdtime_fn_arg) + delta;
37
- [CSR_FCSR] = { fs, read_fcsr, write_fcsr },
282
return 0;
38
+ [CSR_FFLAGS] = { "fflags", fs, read_fflags, write_fflags },
283
}
39
+ [CSR_FRM] = { "frm", fs, read_frm, write_frm },
284
40
+ [CSR_FCSR] = { "fcsr", fs, read_fcsr, write_fcsr },
285
@@ -XXX,XX +XXX,XX @@ static int read_timeh(CPURISCVState *env, int csrno, target_ulong *val)
41
/* Vector CSRs */
286
return -RISCV_EXCP_ILLEGAL_INST;
42
- [CSR_VSTART] = { vs, read_vstart, write_vstart },
287
}
43
- [CSR_VXSAT] = { vs, read_vxsat, write_vxsat },
288
44
- [CSR_VXRM] = { vs, read_vxrm, write_vxrm },
289
- *val = (env->rdtime_fn() + delta) >> 32;
45
- [CSR_VL] = { vs, read_vl },
290
+ *val = (env->rdtime_fn(env->rdtime_fn_arg) + delta) >> 32;
46
- [CSR_VTYPE] = { vs, read_vtype },
291
return 0;
47
+ [CSR_VSTART] = { "vstart", vs, read_vstart, write_vstart },
292
}
48
+ [CSR_VXSAT] = { "vxsat", vs, read_vxsat, write_vxsat },
293
#endif
49
+ [CSR_VXRM] = { "vxrm", vs, read_vxrm, write_vxrm },
50
+ [CSR_VL] = { "vl", vs, read_vl },
51
+ [CSR_VTYPE] = { "vtype", vs, read_vtype },
52
/* User Timers and Counters */
53
- [CSR_CYCLE] = { ctr, read_instret },
54
- [CSR_INSTRET] = { ctr, read_instret },
55
- [CSR_CYCLEH] = { ctr32, read_instreth },
56
- [CSR_INSTRETH] = { ctr32, read_instreth },
57
-
58
- /* In privileged mode, the monitor will have to emulate TIME CSRs only if
59
- * rdtime callback is not provided by machine/platform emulation */
60
- [CSR_TIME] = { ctr, read_time },
61
- [CSR_TIMEH] = { ctr32, read_timeh },
62
+ [CSR_CYCLE] = { "cycle", ctr, read_instret },
63
+ [CSR_INSTRET] = { "instret", ctr, read_instret },
64
+ [CSR_CYCLEH] = { "cycleh", ctr32, read_instreth },
65
+ [CSR_INSTRETH] = { "instreth", ctr32, read_instreth },
66
+
67
+ /*
68
+ * In privileged mode, the monitor will have to emulate TIME CSRs only if
69
+ * rdtime callback is not provided by machine/platform emulation.
70
+ */
71
+ [CSR_TIME] = { "time", ctr, read_time },
72
+ [CSR_TIMEH] = { "timeh", ctr32, read_timeh },
73
74
#if !defined(CONFIG_USER_ONLY)
75
/* Machine Timers and Counters */
76
- [CSR_MCYCLE] = { any, read_instret },
77
- [CSR_MINSTRET] = { any, read_instret },
78
- [CSR_MCYCLEH] = { any32, read_instreth },
79
- [CSR_MINSTRETH] = { any32, read_instreth },
80
+ [CSR_MCYCLE] = { "mcycle", any, read_instret },
81
+ [CSR_MINSTRET] = { "minstret", any, read_instret },
82
+ [CSR_MCYCLEH] = { "mcycleh", any32, read_instreth },
83
+ [CSR_MINSTRETH] = { "minstreth", any32, read_instreth },
84
85
/* Machine Information Registers */
86
- [CSR_MVENDORID] = { any, read_zero },
87
- [CSR_MARCHID] = { any, read_zero },
88
- [CSR_MIMPID] = { any, read_zero },
89
- [CSR_MHARTID] = { any, read_mhartid },
90
+ [CSR_MVENDORID] = { "mvendorid", any, read_zero },
91
+ [CSR_MARCHID] = { "marchid", any, read_zero },
92
+ [CSR_MIMPID] = { "mimpid", any, read_zero },
93
+ [CSR_MHARTID] = { "mhartid", any, read_mhartid },
94
95
/* Machine Trap Setup */
96
- [CSR_MSTATUS] = { any, read_mstatus, write_mstatus },
97
- [CSR_MISA] = { any, read_misa, write_misa },
98
- [CSR_MIDELEG] = { any, read_mideleg, write_mideleg },
99
- [CSR_MEDELEG] = { any, read_medeleg, write_medeleg },
100
- [CSR_MIE] = { any, read_mie, write_mie },
101
- [CSR_MTVEC] = { any, read_mtvec, write_mtvec },
102
- [CSR_MCOUNTEREN] = { any, read_mcounteren, write_mcounteren },
103
+ [CSR_MSTATUS] = { "mstatus", any, read_mstatus, write_mstatus },
104
+ [CSR_MISA] = { "misa", any, read_misa, write_misa },
105
+ [CSR_MIDELEG] = { "mideleg", any, read_mideleg, write_mideleg },
106
+ [CSR_MEDELEG] = { "medeleg", any, read_medeleg, write_medeleg },
107
+ [CSR_MIE] = { "mie", any, read_mie, write_mie },
108
+ [CSR_MTVEC] = { "mtvec", any, read_mtvec, write_mtvec },
109
+ [CSR_MCOUNTEREN] = { "mcounteren", any, read_mcounteren, write_mcounteren },
110
111
- [CSR_MSTATUSH] = { any32, read_mstatush, write_mstatush },
112
+ [CSR_MSTATUSH] = { "mstatush", any32, read_mstatush, write_mstatush },
113
114
- [CSR_MSCOUNTEREN] = { any, read_mscounteren, write_mscounteren },
115
+ [CSR_MSCOUNTEREN] = { "msounteren", any, read_mscounteren, write_mscounteren },
116
117
/* Machine Trap Handling */
118
- [CSR_MSCRATCH] = { any, read_mscratch, write_mscratch },
119
- [CSR_MEPC] = { any, read_mepc, write_mepc },
120
- [CSR_MCAUSE] = { any, read_mcause, write_mcause },
121
- [CSR_MBADADDR] = { any, read_mbadaddr, write_mbadaddr },
122
- [CSR_MIP] = { any, NULL, NULL, rmw_mip },
123
+ [CSR_MSCRATCH] = { "mscratch", any, read_mscratch, write_mscratch },
124
+ [CSR_MEPC] = { "mepc", any, read_mepc, write_mepc },
125
+ [CSR_MCAUSE] = { "mcause", any, read_mcause, write_mcause },
126
+ [CSR_MBADADDR] = { "mbadaddr", any, read_mbadaddr, write_mbadaddr },
127
+ [CSR_MIP] = { "mip", any, NULL, NULL, rmw_mip },
128
129
/* Supervisor Trap Setup */
130
- [CSR_SSTATUS] = { smode, read_sstatus, write_sstatus },
131
- [CSR_SIE] = { smode, read_sie, write_sie },
132
- [CSR_STVEC] = { smode, read_stvec, write_stvec },
133
- [CSR_SCOUNTEREN] = { smode, read_scounteren, write_scounteren },
134
+ [CSR_SSTATUS] = { "sstatus", smode, read_sstatus, write_sstatus },
135
+ [CSR_SIE] = { "sie", smode, read_sie, write_sie },
136
+ [CSR_STVEC] = { "stvec", smode, read_stvec, write_stvec },
137
+ [CSR_SCOUNTEREN] = { "scounteren", smode, read_scounteren, write_scounteren },
138
139
/* Supervisor Trap Handling */
140
- [CSR_SSCRATCH] = { smode, read_sscratch, write_sscratch },
141
- [CSR_SEPC] = { smode, read_sepc, write_sepc },
142
- [CSR_SCAUSE] = { smode, read_scause, write_scause },
143
- [CSR_SBADADDR] = { smode, read_sbadaddr, write_sbadaddr },
144
- [CSR_SIP] = { smode, NULL, NULL, rmw_sip },
145
+ [CSR_SSCRATCH] = { "sscratch", smode, read_sscratch, write_sscratch },
146
+ [CSR_SEPC] = { "sepc", smode, read_sepc, write_sepc },
147
+ [CSR_SCAUSE] = { "scause", smode, read_scause, write_scause },
148
+ [CSR_SBADADDR] = { "sbadaddr", smode, read_sbadaddr, write_sbadaddr },
149
+ [CSR_SIP] = { "sip", smode, NULL, NULL, rmw_sip },
150
151
/* Supervisor Protection and Translation */
152
- [CSR_SATP] = { smode, read_satp, write_satp },
153
-
154
- [CSR_HSTATUS] = { hmode, read_hstatus, write_hstatus },
155
- [CSR_HEDELEG] = { hmode, read_hedeleg, write_hedeleg },
156
- [CSR_HIDELEG] = { hmode, read_hideleg, write_hideleg },
157
- [CSR_HVIP] = { hmode, NULL, NULL, rmw_hvip },
158
- [CSR_HIP] = { hmode, NULL, NULL, rmw_hip },
159
- [CSR_HIE] = { hmode, read_hie, write_hie },
160
- [CSR_HCOUNTEREN] = { hmode, read_hcounteren, write_hcounteren },
161
- [CSR_HGEIE] = { hmode, read_hgeie, write_hgeie },
162
- [CSR_HTVAL] = { hmode, read_htval, write_htval },
163
- [CSR_HTINST] = { hmode, read_htinst, write_htinst },
164
- [CSR_HGEIP] = { hmode, read_hgeip, write_hgeip },
165
- [CSR_HGATP] = { hmode, read_hgatp, write_hgatp },
166
- [CSR_HTIMEDELTA] = { hmode, read_htimedelta, write_htimedelta },
167
- [CSR_HTIMEDELTAH] = { hmode32, read_htimedeltah, write_htimedeltah},
168
-
169
- [CSR_VSSTATUS] = { hmode, read_vsstatus, write_vsstatus },
170
- [CSR_VSIP] = { hmode, NULL, NULL, rmw_vsip },
171
- [CSR_VSIE] = { hmode, read_vsie, write_vsie },
172
- [CSR_VSTVEC] = { hmode, read_vstvec, write_vstvec },
173
- [CSR_VSSCRATCH] = { hmode, read_vsscratch, write_vsscratch },
174
- [CSR_VSEPC] = { hmode, read_vsepc, write_vsepc },
175
- [CSR_VSCAUSE] = { hmode, read_vscause, write_vscause },
176
- [CSR_VSTVAL] = { hmode, read_vstval, write_vstval },
177
- [CSR_VSATP] = { hmode, read_vsatp, write_vsatp },
178
-
179
- [CSR_MTVAL2] = { hmode, read_mtval2, write_mtval2 },
180
- [CSR_MTINST] = { hmode, read_mtinst, write_mtinst },
181
+ [CSR_SATP] = { "satp", smode, read_satp, write_satp },
182
+
183
+ [CSR_HSTATUS] = { "hstatus", hmode, read_hstatus, write_hstatus },
184
+ [CSR_HEDELEG] = { "hedeleg", hmode, read_hedeleg, write_hedeleg },
185
+ [CSR_HIDELEG] = { "hideleg", hmode, read_hideleg, write_hideleg },
186
+ [CSR_HVIP] = { "hvip", hmode, NULL, NULL, rmw_hvip },
187
+ [CSR_HIP] = { "hip", hmode, NULL, NULL, rmw_hip },
188
+ [CSR_HIE] = { "hie", hmode, read_hie, write_hie },
189
+ [CSR_HCOUNTEREN] = { "hcounteren", hmode, read_hcounteren, write_hcounteren },
190
+ [CSR_HGEIE] = { "hgeie", hmode, read_hgeie, write_hgeie },
191
+ [CSR_HTVAL] = { "htval", hmode, read_htval, write_htval },
192
+ [CSR_HTINST] = { "htinst", hmode, read_htinst, write_htinst },
193
+ [CSR_HGEIP] = { "hgeip", hmode, read_hgeip, write_hgeip },
194
+ [CSR_HGATP] = { "hgatp", hmode, read_hgatp, write_hgatp },
195
+ [CSR_HTIMEDELTA] = { "htimedelta", hmode, read_htimedelta, write_htimedelta },
196
+ [CSR_HTIMEDELTAH] = { "htimedeltah", hmode32, read_htimedeltah, write_htimedeltah },
197
+
198
+ [CSR_VSSTATUS] = { "vsstatus", hmode, read_vsstatus, write_vsstatus },
199
+ [CSR_VSIP] = { "vsip", hmode, NULL, NULL, rmw_vsip },
200
+ [CSR_VSIE] = { "vsie", hmode, read_vsie, write_vsie },
201
+ [CSR_VSTVEC] = { "vstvec", hmode, read_vstvec, write_vstvec },
202
+ [CSR_VSSCRATCH] = { "vsscratch", hmode, read_vsscratch, write_vsscratch },
203
+ [CSR_VSEPC] = { "vsepc", hmode, read_vsepc, write_vsepc },
204
+ [CSR_VSCAUSE] = { "vscause", hmode, read_vscause, write_vscause },
205
+ [CSR_VSTVAL] = { "vstval", hmode, read_vstval, write_vstval },
206
+ [CSR_VSATP] = { "vsatp", hmode, read_vsatp, write_vsatp },
207
+
208
+ [CSR_MTVAL2] = { "mtval2", hmode, read_mtval2, write_mtval2 },
209
+ [CSR_MTINST] = { "mtinst", hmode, read_mtinst, write_mtinst },
210
211
/* Physical Memory Protection */
212
- [CSR_PMPCFG0 ... CSR_PMPCFG3] = { pmp, read_pmpcfg, write_pmpcfg },
213
- [CSR_PMPADDR0 ... CSR_PMPADDR15] = { pmp, read_pmpaddr, write_pmpaddr },
214
+ [CSR_PMPCFG0] = { "pmpcfg0", pmp, read_pmpcfg, write_pmpcfg },
215
+ [CSR_PMPCFG1] = { "pmpcfg1", pmp, read_pmpcfg, write_pmpcfg },
216
+ [CSR_PMPCFG2] = { "pmpcfg2", pmp, read_pmpcfg, write_pmpcfg },
217
+ [CSR_PMPCFG3] = { "pmpcfg3", pmp, read_pmpcfg, write_pmpcfg },
218
+ [CSR_PMPADDR0] = { "pmpaddr0", pmp, read_pmpaddr, write_pmpaddr },
219
+ [CSR_PMPADDR1] = { "pmpaddr1", pmp, read_pmpaddr, write_pmpaddr },
220
+ [CSR_PMPADDR2] = { "pmpaddr2", pmp, read_pmpaddr, write_pmpaddr },
221
+ [CSR_PMPADDR3] = { "pmpaddr3", pmp, read_pmpaddr, write_pmpaddr },
222
+ [CSR_PMPADDR4] = { "pmpaddr4", pmp, read_pmpaddr, write_pmpaddr },
223
+ [CSR_PMPADDR5] = { "pmpaddr5", pmp, read_pmpaddr, write_pmpaddr },
224
+ [CSR_PMPADDR6] = { "pmpaddr6", pmp, read_pmpaddr, write_pmpaddr },
225
+ [CSR_PMPADDR7] = { "pmpaddr7", pmp, read_pmpaddr, write_pmpaddr },
226
+ [CSR_PMPADDR8] = { "pmpaddr8", pmp, read_pmpaddr, write_pmpaddr },
227
+ [CSR_PMPADDR9] = { "pmpaddr9", pmp, read_pmpaddr, write_pmpaddr },
228
+ [CSR_PMPADDR10] = { "pmpaddr10", pmp, read_pmpaddr, write_pmpaddr },
229
+ [CSR_PMPADDR11] = { "pmpaddr11", pmp, read_pmpaddr, write_pmpaddr },
230
+ [CSR_PMPADDR12] = { "pmpaddr12", pmp, read_pmpaddr, write_pmpaddr },
231
+ [CSR_PMPADDR13] = { "pmpaddr13", pmp, read_pmpaddr, write_pmpaddr },
232
+ [CSR_PMPADDR14] = { "pmpaddr14", pmp, read_pmpaddr, write_pmpaddr },
233
+ [CSR_PMPADDR15] = { "pmpaddr15", pmp, read_pmpaddr, write_pmpaddr },
234
235
/* Performance Counters */
236
- [CSR_HPMCOUNTER3 ... CSR_HPMCOUNTER31] = { ctr, read_zero },
237
- [CSR_MHPMCOUNTER3 ... CSR_MHPMCOUNTER31] = { any, read_zero },
238
- [CSR_MHPMEVENT3 ... CSR_MHPMEVENT31] = { any, read_zero },
239
- [CSR_HPMCOUNTER3H ... CSR_HPMCOUNTER31H] = { ctr32, read_zero },
240
- [CSR_MHPMCOUNTER3H ... CSR_MHPMCOUNTER31H] = { any32, read_zero },
241
+ [CSR_HPMCOUNTER3] = { "hpmcounter3", ctr, read_zero },
242
+ [CSR_HPMCOUNTER4] = { "hpmcounter4", ctr, read_zero },
243
+ [CSR_HPMCOUNTER5] = { "hpmcounter5", ctr, read_zero },
244
+ [CSR_HPMCOUNTER6] = { "hpmcounter6", ctr, read_zero },
245
+ [CSR_HPMCOUNTER7] = { "hpmcounter7", ctr, read_zero },
246
+ [CSR_HPMCOUNTER8] = { "hpmcounter8", ctr, read_zero },
247
+ [CSR_HPMCOUNTER9] = { "hpmcounter9", ctr, read_zero },
248
+ [CSR_HPMCOUNTER10] = { "hpmcounter10", ctr, read_zero },
249
+ [CSR_HPMCOUNTER11] = { "hpmcounter11", ctr, read_zero },
250
+ [CSR_HPMCOUNTER12] = { "hpmcounter12", ctr, read_zero },
251
+ [CSR_HPMCOUNTER13] = { "hpmcounter13", ctr, read_zero },
252
+ [CSR_HPMCOUNTER14] = { "hpmcounter14", ctr, read_zero },
253
+ [CSR_HPMCOUNTER15] = { "hpmcounter15", ctr, read_zero },
254
+ [CSR_HPMCOUNTER16] = { "hpmcounter16", ctr, read_zero },
255
+ [CSR_HPMCOUNTER17] = { "hpmcounter17", ctr, read_zero },
256
+ [CSR_HPMCOUNTER18] = { "hpmcounter18", ctr, read_zero },
257
+ [CSR_HPMCOUNTER19] = { "hpmcounter19", ctr, read_zero },
258
+ [CSR_HPMCOUNTER20] = { "hpmcounter20", ctr, read_zero },
259
+ [CSR_HPMCOUNTER21] = { "hpmcounter21", ctr, read_zero },
260
+ [CSR_HPMCOUNTER22] = { "hpmcounter22", ctr, read_zero },
261
+ [CSR_HPMCOUNTER23] = { "hpmcounter23", ctr, read_zero },
262
+ [CSR_HPMCOUNTER24] = { "hpmcounter24", ctr, read_zero },
263
+ [CSR_HPMCOUNTER25] = { "hpmcounter25", ctr, read_zero },
264
+ [CSR_HPMCOUNTER26] = { "hpmcounter26", ctr, read_zero },
265
+ [CSR_HPMCOUNTER27] = { "hpmcounter27", ctr, read_zero },
266
+ [CSR_HPMCOUNTER28] = { "hpmcounter28", ctr, read_zero },
267
+ [CSR_HPMCOUNTER29] = { "hpmcounter29", ctr, read_zero },
268
+ [CSR_HPMCOUNTER30] = { "hpmcounter30", ctr, read_zero },
269
+ [CSR_HPMCOUNTER31] = { "hpmcounter31", ctr, read_zero },
270
+
271
+ [CSR_MHPMCOUNTER3] = { "mhpmcounter3", any, read_zero },
272
+ [CSR_MHPMCOUNTER4] = { "mhpmcounter4", any, read_zero },
273
+ [CSR_MHPMCOUNTER5] = { "mhpmcounter5", any, read_zero },
274
+ [CSR_MHPMCOUNTER6] = { "mhpmcounter6", any, read_zero },
275
+ [CSR_MHPMCOUNTER7] = { "mhpmcounter7", any, read_zero },
276
+ [CSR_MHPMCOUNTER8] = { "mhpmcounter8", any, read_zero },
277
+ [CSR_MHPMCOUNTER9] = { "mhpmcounter9", any, read_zero },
278
+ [CSR_MHPMCOUNTER10] = { "mhpmcounter10", any, read_zero },
279
+ [CSR_MHPMCOUNTER11] = { "mhpmcounter11", any, read_zero },
280
+ [CSR_MHPMCOUNTER12] = { "mhpmcounter12", any, read_zero },
281
+ [CSR_MHPMCOUNTER13] = { "mhpmcounter13", any, read_zero },
282
+ [CSR_MHPMCOUNTER14] = { "mhpmcounter14", any, read_zero },
283
+ [CSR_MHPMCOUNTER15] = { "mhpmcounter15", any, read_zero },
284
+ [CSR_MHPMCOUNTER16] = { "mhpmcounter16", any, read_zero },
285
+ [CSR_MHPMCOUNTER17] = { "mhpmcounter17", any, read_zero },
286
+ [CSR_MHPMCOUNTER18] = { "mhpmcounter18", any, read_zero },
287
+ [CSR_MHPMCOUNTER19] = { "mhpmcounter19", any, read_zero },
288
+ [CSR_MHPMCOUNTER20] = { "mhpmcounter20", any, read_zero },
289
+ [CSR_MHPMCOUNTER21] = { "mhpmcounter21", any, read_zero },
290
+ [CSR_MHPMCOUNTER22] = { "mhpmcounter22", any, read_zero },
291
+ [CSR_MHPMCOUNTER23] = { "mhpmcounter23", any, read_zero },
292
+ [CSR_MHPMCOUNTER24] = { "mhpmcounter24", any, read_zero },
293
+ [CSR_MHPMCOUNTER25] = { "mhpmcounter25", any, read_zero },
294
+ [CSR_MHPMCOUNTER26] = { "mhpmcounter26", any, read_zero },
295
+ [CSR_MHPMCOUNTER27] = { "mhpmcounter27", any, read_zero },
296
+ [CSR_MHPMCOUNTER28] = { "mhpmcounter28", any, read_zero },
297
+ [CSR_MHPMCOUNTER29] = { "mhpmcounter29", any, read_zero },
298
+ [CSR_MHPMCOUNTER30] = { "mhpmcounter30", any, read_zero },
299
+ [CSR_MHPMCOUNTER31] = { "mhpmcounter31", any, read_zero },
300
+
301
+ [CSR_MHPMEVENT3] = { "mhpmevent3", any, read_zero },
302
+ [CSR_MHPMEVENT4] = { "mhpmevent4", any, read_zero },
303
+ [CSR_MHPMEVENT5] = { "mhpmevent5", any, read_zero },
304
+ [CSR_MHPMEVENT6] = { "mhpmevent6", any, read_zero },
305
+ [CSR_MHPMEVENT7] = { "mhpmevent7", any, read_zero },
306
+ [CSR_MHPMEVENT8] = { "mhpmevent8", any, read_zero },
307
+ [CSR_MHPMEVENT9] = { "mhpmevent9", any, read_zero },
308
+ [CSR_MHPMEVENT10] = { "mhpmevent10", any, read_zero },
309
+ [CSR_MHPMEVENT11] = { "mhpmevent11", any, read_zero },
310
+ [CSR_MHPMEVENT12] = { "mhpmevent12", any, read_zero },
311
+ [CSR_MHPMEVENT13] = { "mhpmevent13", any, read_zero },
312
+ [CSR_MHPMEVENT14] = { "mhpmevent14", any, read_zero },
313
+ [CSR_MHPMEVENT15] = { "mhpmevent15", any, read_zero },
314
+ [CSR_MHPMEVENT16] = { "mhpmevent16", any, read_zero },
315
+ [CSR_MHPMEVENT17] = { "mhpmevent17", any, read_zero },
316
+ [CSR_MHPMEVENT18] = { "mhpmevent18", any, read_zero },
317
+ [CSR_MHPMEVENT19] = { "mhpmevent19", any, read_zero },
318
+ [CSR_MHPMEVENT20] = { "mhpmevent20", any, read_zero },
319
+ [CSR_MHPMEVENT21] = { "mhpmevent21", any, read_zero },
320
+ [CSR_MHPMEVENT22] = { "mhpmevent22", any, read_zero },
321
+ [CSR_MHPMEVENT23] = { "mhpmevent23", any, read_zero },
322
+ [CSR_MHPMEVENT24] = { "mhpmevent24", any, read_zero },
323
+ [CSR_MHPMEVENT25] = { "mhpmevent25", any, read_zero },
324
+ [CSR_MHPMEVENT26] = { "mhpmevent26", any, read_zero },
325
+ [CSR_MHPMEVENT27] = { "mhpmevent27", any, read_zero },
326
+ [CSR_MHPMEVENT28] = { "mhpmevent28", any, read_zero },
327
+ [CSR_MHPMEVENT29] = { "mhpmevent29", any, read_zero },
328
+ [CSR_MHPMEVENT30] = { "mhpmevent30", any, read_zero },
329
+ [CSR_MHPMEVENT31] = { "mhpmevent31", any, read_zero },
330
+
331
+ [CSR_HPMCOUNTER3H] = { "hpmcounter3h", ctr32, read_zero },
332
+ [CSR_HPMCOUNTER4H] = { "hpmcounter4h", ctr32, read_zero },
333
+ [CSR_HPMCOUNTER5H] = { "hpmcounter5h", ctr32, read_zero },
334
+ [CSR_HPMCOUNTER6H] = { "hpmcounter6h", ctr32, read_zero },
335
+ [CSR_HPMCOUNTER7H] = { "hpmcounter7h", ctr32, read_zero },
336
+ [CSR_HPMCOUNTER8H] = { "hpmcounter8h", ctr32, read_zero },
337
+ [CSR_HPMCOUNTER9H] = { "hpmcounter9h", ctr32, read_zero },
338
+ [CSR_HPMCOUNTER10H] = { "hpmcounter10h", ctr32, read_zero },
339
+ [CSR_HPMCOUNTER11H] = { "hpmcounter11h", ctr32, read_zero },
340
+ [CSR_HPMCOUNTER12H] = { "hpmcounter12h", ctr32, read_zero },
341
+ [CSR_HPMCOUNTER13H] = { "hpmcounter13h", ctr32, read_zero },
342
+ [CSR_HPMCOUNTER14H] = { "hpmcounter14h", ctr32, read_zero },
343
+ [CSR_HPMCOUNTER15H] = { "hpmcounter15h", ctr32, read_zero },
344
+ [CSR_HPMCOUNTER16H] = { "hpmcounter16h", ctr32, read_zero },
345
+ [CSR_HPMCOUNTER17H] = { "hpmcounter17h", ctr32, read_zero },
346
+ [CSR_HPMCOUNTER18H] = { "hpmcounter18h", ctr32, read_zero },
347
+ [CSR_HPMCOUNTER19H] = { "hpmcounter19h", ctr32, read_zero },
348
+ [CSR_HPMCOUNTER20H] = { "hpmcounter20h", ctr32, read_zero },
349
+ [CSR_HPMCOUNTER21H] = { "hpmcounter21h", ctr32, read_zero },
350
+ [CSR_HPMCOUNTER22H] = { "hpmcounter22h", ctr32, read_zero },
351
+ [CSR_HPMCOUNTER23H] = { "hpmcounter23h", ctr32, read_zero },
352
+ [CSR_HPMCOUNTER24H] = { "hpmcounter24h", ctr32, read_zero },
353
+ [CSR_HPMCOUNTER25H] = { "hpmcounter25h", ctr32, read_zero },
354
+ [CSR_HPMCOUNTER26H] = { "hpmcounter26h", ctr32, read_zero },
355
+ [CSR_HPMCOUNTER27H] = { "hpmcounter27h", ctr32, read_zero },
356
+ [CSR_HPMCOUNTER28H] = { "hpmcounter28h", ctr32, read_zero },
357
+ [CSR_HPMCOUNTER29H] = { "hpmcounter29h", ctr32, read_zero },
358
+ [CSR_HPMCOUNTER30H] = { "hpmcounter30h", ctr32, read_zero },
359
+ [CSR_HPMCOUNTER31H] = { "hpmcounter31h", ctr32, read_zero },
360
+
361
+ [CSR_MHPMCOUNTER3H] = { "mhpmcounter3h", any32, read_zero },
362
+ [CSR_MHPMCOUNTER4H] = { "mhpmcounter4h", any32, read_zero },
363
+ [CSR_MHPMCOUNTER5H] = { "mhpmcounter5h", any32, read_zero },
364
+ [CSR_MHPMCOUNTER6H] = { "mhpmcounter6h", any32, read_zero },
365
+ [CSR_MHPMCOUNTER7H] = { "mhpmcounter7h", any32, read_zero },
366
+ [CSR_MHPMCOUNTER8H] = { "mhpmcounter8h", any32, read_zero },
367
+ [CSR_MHPMCOUNTER9H] = { "mhpmcounter9h", any32, read_zero },
368
+ [CSR_MHPMCOUNTER10H] = { "mhpmcounter10h", any32, read_zero },
369
+ [CSR_MHPMCOUNTER11H] = { "mhpmcounter11h", any32, read_zero },
370
+ [CSR_MHPMCOUNTER12H] = { "mhpmcounter12h", any32, read_zero },
371
+ [CSR_MHPMCOUNTER13H] = { "mhpmcounter13h", any32, read_zero },
372
+ [CSR_MHPMCOUNTER14H] = { "mhpmcounter14h", any32, read_zero },
373
+ [CSR_MHPMCOUNTER15H] = { "mhpmcounter15h", any32, read_zero },
374
+ [CSR_MHPMCOUNTER16H] = { "mhpmcounter16h", any32, read_zero },
375
+ [CSR_MHPMCOUNTER17H] = { "mhpmcounter17h", any32, read_zero },
376
+ [CSR_MHPMCOUNTER18H] = { "mhpmcounter18h", any32, read_zero },
377
+ [CSR_MHPMCOUNTER19H] = { "mhpmcounter19h", any32, read_zero },
378
+ [CSR_MHPMCOUNTER20H] = { "mhpmcounter20h", any32, read_zero },
379
+ [CSR_MHPMCOUNTER21H] = { "mhpmcounter21h", any32, read_zero },
380
+ [CSR_MHPMCOUNTER22H] = { "mhpmcounter22h", any32, read_zero },
381
+ [CSR_MHPMCOUNTER23H] = { "mhpmcounter23h", any32, read_zero },
382
+ [CSR_MHPMCOUNTER24H] = { "mhpmcounter24h", any32, read_zero },
383
+ [CSR_MHPMCOUNTER25H] = { "mhpmcounter25h", any32, read_zero },
384
+ [CSR_MHPMCOUNTER26H] = { "mhpmcounter26h", any32, read_zero },
385
+ [CSR_MHPMCOUNTER27H] = { "mhpmcounter27h", any32, read_zero },
386
+ [CSR_MHPMCOUNTER28H] = { "mhpmcounter28h", any32, read_zero },
387
+ [CSR_MHPMCOUNTER29H] = { "mhpmcounter29h", any32, read_zero },
388
+ [CSR_MHPMCOUNTER30H] = { "mhpmcounter30h", any32, read_zero },
389
+ [CSR_MHPMCOUNTER31H] = { "mhpmcounter31h", any32, read_zero },
390
#endif /* !CONFIG_USER_ONLY */
391
};
392
--
294
--
393
2.29.2
295
2.28.0
394
296
395
297
diff view generated by jsdifflib
[PULL 07/12] hw/misc/sifive_u_otp: handling the fails of blk_pread and blk_pwrite
[PULL 18/30] hw/riscv: sifive_u: Connect a DMA controller
1
From: Green Wan <green.wan@sifive.com>
1
From: Bin Meng <bin.meng@windriver.com>
2
2
3
Fix code coverage issues by checking return value and handling fail case
3
SiFive FU540 SoC integrates a platform DMA controller with 4 DMA
4
of blk_pread() and blk_pwrite(). Return default value 0xff if read fails.
4
channels. This connects the exsiting SiFive PDMA model to the SoC,
5
and adds its device tree data as well.
5
6
6
Fixes: Coverity CID 1435959
7
Signed-off-by: Bin Meng <bin.meng@windriver.com>
7
Fixes: Coverity CID 1435960
8
Fixes: Coverity CID 1435961
9
Signed-off-by: Green Wan <green.wan@sifive.com>
10
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
8
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
11
Message-id: 20201104092900.21214-1-green.wan@sifive.com
9
Message-Id: <1598924352-89526-17-git-send-email-bmeng.cn@gmail.com>
12
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
10
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
13
---
11
---
14
hw/misc/sifive_u_otp.c | 31 +++++++++++++++++++++++--------
12
include/hw/riscv/sifive_u.h | 11 +++++++++++
15
1 file changed, 23 insertions(+), 8 deletions(-)
13
hw/riscv/sifive_u.c | 30 ++++++++++++++++++++++++++++++
14
hw/riscv/Kconfig | 1 +
15
3 files changed, 42 insertions(+)
16
16
17
diff --git a/hw/misc/sifive_u_otp.c b/hw/misc/sifive_u_otp.c
17
diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
18
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/misc/sifive_u_otp.c
19
--- a/include/hw/riscv/sifive_u.h
20
+++ b/hw/misc/sifive_u_otp.c
20
+++ b/include/hw/riscv/sifive_u.h
21
@@ -XXX,XX +XXX,XX @@ static uint64_t sifive_u_otp_read(void *opaque, hwaddr addr, unsigned int size)
21
@@ -XXX,XX +XXX,XX @@
22
if (s->blk) {
22
#ifndef HW_SIFIVE_U_H
23
int32_t buf;
23
#define HW_SIFIVE_U_H
24
24
25
- blk_pread(s->blk, s->pa * SIFIVE_U_OTP_FUSE_WORD, &buf,
25
+#include "hw/dma/sifive_pdma.h"
26
- SIFIVE_U_OTP_FUSE_WORD);
26
#include "hw/net/cadence_gem.h"
27
+ if (blk_pread(s->blk, s->pa * SIFIVE_U_OTP_FUSE_WORD, &buf,
27
#include "hw/riscv/riscv_hart.h"
28
+ SIFIVE_U_OTP_FUSE_WORD) < 0) {
28
#include "hw/riscv/sifive_cpu.h"
29
+ qemu_log_mask(LOG_GUEST_ERROR,
29
@@ -XXX,XX +XXX,XX @@ typedef struct SiFiveUSoCState {
30
+ "read error index<%d>\n", s->pa);
30
SiFiveUPRCIState prci;
31
+ return 0xff;
31
SIFIVEGPIOState gpio;
32
+ }
32
SiFiveUOTPState otp;
33
+ SiFivePDMAState dma;
34
CadenceGEMState gem;
35
36
uint32_t serial;
37
@@ -XXX,XX +XXX,XX @@ enum {
38
SIFIVE_U_MROM,
39
SIFIVE_U_CLINT,
40
SIFIVE_U_L2CC,
41
+ SIFIVE_U_PDMA,
42
SIFIVE_U_L2LIM,
43
SIFIVE_U_PLIC,
44
SIFIVE_U_PRCI,
45
@@ -XXX,XX +XXX,XX @@ enum {
46
SIFIVE_U_GPIO_IRQ13 = 20,
47
SIFIVE_U_GPIO_IRQ14 = 21,
48
SIFIVE_U_GPIO_IRQ15 = 22,
49
+ SIFIVE_U_PDMA_IRQ0 = 23,
50
+ SIFIVE_U_PDMA_IRQ1 = 24,
51
+ SIFIVE_U_PDMA_IRQ2 = 25,
52
+ SIFIVE_U_PDMA_IRQ3 = 26,
53
+ SIFIVE_U_PDMA_IRQ4 = 27,
54
+ SIFIVE_U_PDMA_IRQ5 = 28,
55
+ SIFIVE_U_PDMA_IRQ6 = 29,
56
+ SIFIVE_U_PDMA_IRQ7 = 30,
57
SIFIVE_U_GEM_IRQ = 0x35
58
};
59
60
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
61
index XXXXXXX..XXXXXXX 100644
62
--- a/hw/riscv/sifive_u.c
63
+++ b/hw/riscv/sifive_u.c
64
@@ -XXX,XX +XXX,XX @@
65
* 4) GPIO (General Purpose Input/Output Controller)
66
* 5) OTP (One-Time Programmable) memory with stored serial number
67
* 6) GEM (Gigabit Ethernet Controller) and management block
68
+ * 7) DMA (Direct Memory Access Controller)
69
*
70
* This board currently generates devicetree dynamically that indicates at least
71
* two harts and up to five harts.
72
@@ -XXX,XX +XXX,XX @@ static const struct MemmapEntry {
73
[SIFIVE_U_MROM] = { 0x1000, 0xf000 },
74
[SIFIVE_U_CLINT] = { 0x2000000, 0x10000 },
75
[SIFIVE_U_L2CC] = { 0x2010000, 0x1000 },
76
+ [SIFIVE_U_PDMA] = { 0x3000000, 0x100000 },
77
[SIFIVE_U_L2LIM] = { 0x8000000, 0x2000000 },
78
[SIFIVE_U_PLIC] = { 0xc000000, 0x4000000 },
79
[SIFIVE_U_PRCI] = { 0x10000000, 0x1000 },
80
@@ -XXX,XX +XXX,XX @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
81
qemu_fdt_setprop_string(fdt, nodename, "compatible", "gpio-restart");
82
g_free(nodename);
83
84
+ nodename = g_strdup_printf("/soc/dma@%lx",
85
+ (long)memmap[SIFIVE_U_PDMA].base);
86
+ qemu_fdt_add_subnode(fdt, nodename);
87
+ qemu_fdt_setprop_cell(fdt, nodename, "#dma-cells", 1);
88
+ qemu_fdt_setprop_cells(fdt, nodename, "interrupts",
89
+ SIFIVE_U_PDMA_IRQ0, SIFIVE_U_PDMA_IRQ1, SIFIVE_U_PDMA_IRQ2,
90
+ SIFIVE_U_PDMA_IRQ3, SIFIVE_U_PDMA_IRQ4, SIFIVE_U_PDMA_IRQ5,
91
+ SIFIVE_U_PDMA_IRQ6, SIFIVE_U_PDMA_IRQ7);
92
+ qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
93
+ qemu_fdt_setprop_cells(fdt, nodename, "reg",
94
+ 0x0, memmap[SIFIVE_U_PDMA].base,
95
+ 0x0, memmap[SIFIVE_U_PDMA].size);
96
+ qemu_fdt_setprop_string(fdt, nodename, "compatible",
97
+ "sifive,fu540-c000-pdma");
98
+ g_free(nodename);
33
+
99
+
34
return buf;
100
nodename = g_strdup_printf("/soc/cache-controller@%lx",
35
}
101
(long)memmap[SIFIVE_U_L2CC].base);
36
102
qemu_fdt_add_subnode(fdt, nodename);
37
@@ -XXX,XX +XXX,XX @@ static void sifive_u_otp_write(void *opaque, hwaddr addr,
103
@@ -XXX,XX +XXX,XX @@ static void sifive_u_soc_instance_init(Object *obj)
38
104
object_initialize_child(obj, "otp", &s->otp, TYPE_SIFIVE_U_OTP);
39
/* write to backend */
105
object_initialize_child(obj, "gem", &s->gem, TYPE_CADENCE_GEM);
40
if (s->blk) {
106
object_initialize_child(obj, "gpio", &s->gpio, TYPE_SIFIVE_GPIO);
41
- blk_pwrite(s->blk, s->pa * SIFIVE_U_OTP_FUSE_WORD,
107
+ object_initialize_child(obj, "pdma", &s->dma, TYPE_SIFIVE_PDMA);
42
- &s->fuse[s->pa], SIFIVE_U_OTP_FUSE_WORD, 0);
108
}
43
+ if (blk_pwrite(s->blk, s->pa * SIFIVE_U_OTP_FUSE_WORD,
109
44
+ &s->fuse[s->pa], SIFIVE_U_OTP_FUSE_WORD,
110
static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
45
+ 0) < 0) {
111
@@ -XXX,XX +XXX,XX @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
46
+ qemu_log_mask(LOG_GUEST_ERROR,
112
SIFIVE_U_GPIO_IRQ0 + i));
47
+ "write error index<%d>\n", s->pa);
48
+ }
49
}
50
51
/* update written bit */
52
@@ -XXX,XX +XXX,XX @@ static void sifive_u_otp_reset(DeviceState *dev)
53
int index = SIFIVE_U_OTP_SERIAL_ADDR;
54
55
serial_data = s->serial;
56
- blk_pwrite(s->blk, index * SIFIVE_U_OTP_FUSE_WORD,
57
- &serial_data, SIFIVE_U_OTP_FUSE_WORD, 0);
58
+ if (blk_pwrite(s->blk, index * SIFIVE_U_OTP_FUSE_WORD,
59
+ &serial_data, SIFIVE_U_OTP_FUSE_WORD, 0) < 0) {
60
+ qemu_log_mask(LOG_GUEST_ERROR,
61
+ "write error index<%d>\n", index);
62
+ }
63
64
serial_data = ~(s->serial);
65
- blk_pwrite(s->blk, (index + 1) * SIFIVE_U_OTP_FUSE_WORD,
66
- &serial_data, SIFIVE_U_OTP_FUSE_WORD, 0);
67
+ if (blk_pwrite(s->blk, (index + 1) * SIFIVE_U_OTP_FUSE_WORD,
68
+ &serial_data, SIFIVE_U_OTP_FUSE_WORD, 0) < 0) {
69
+ qemu_log_mask(LOG_GUEST_ERROR,
70
+ "write error index<%d>\n", index + 1);
71
+ }
72
}
113
}
73
114
74
/* Initialize write-once map */
115
+ /* PDMA */
116
+ sysbus_realize(SYS_BUS_DEVICE(&s->dma), errp);
117
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->dma), 0, memmap[SIFIVE_U_PDMA].base);
118
+
119
+ /* Connect PDMA interrupts to the PLIC */
120
+ for (i = 0; i < SIFIVE_PDMA_IRQS; i++) {
121
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->dma), i,
122
+ qdev_get_gpio_in(DEVICE(s->plic),
123
+ SIFIVE_U_PDMA_IRQ0 + i));
124
+ }
125
+
126
qdev_prop_set_uint32(DEVICE(&s->otp), "serial", s->serial);
127
if (!sysbus_realize(SYS_BUS_DEVICE(&s->otp), errp)) {
128
return;
129
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
130
index XXXXXXX..XXXXXXX 100644
131
--- a/hw/riscv/Kconfig
132
+++ b/hw/riscv/Kconfig
133
@@ -XXX,XX +XXX,XX @@ config SIFIVE_U
134
select CADENCE
135
select HART
136
select SIFIVE
137
+ select SIFIVE_PDMA
138
select UNIMP
139
140
config SPIKE
75
--
141
--
76
2.29.2
142
2.28.0
77
143
78
144
diff view generated by jsdifflib
New patch
[PULL 19/30] hw/riscv: Move sifive_e_prci model to hw/misc
1
From: Bin Meng <bin.meng@windriver.com>
1
2
3
This is an effort to clean up the hw/riscv directory. Ideally it
4
should only contain the RISC-V SoC / machine codes plus generic
5
codes. Let's move sifive_e_prci model to hw/misc directory.
6
7
Signed-off-by: Bin Meng <bin.meng@windriver.com>
8
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
9
Message-Id: <1599129623-68957-2-git-send-email-bmeng.cn@gmail.com>
10
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
11
---
12
include/hw/{riscv => misc}/sifive_e_prci.h | 0
13
hw/{riscv => misc}/sifive_e_prci.c | 2 +-
14
hw/riscv/sifive_e.c | 2 +-
15
hw/misc/Kconfig | 3 +++
16
hw/misc/meson.build | 3 +++
17
hw/riscv/Kconfig | 1 +
18
hw/riscv/meson.build | 1 -
19
7 files changed, 9 insertions(+), 3 deletions(-)
20
rename include/hw/{riscv => misc}/sifive_e_prci.h (100%)
21
rename hw/{riscv => misc}/sifive_e_prci.c (99%)
22
23
diff --git a/include/hw/riscv/sifive_e_prci.h b/include/hw/misc/sifive_e_prci.h
24
similarity index 100%
25
rename from include/hw/riscv/sifive_e_prci.h
26
rename to include/hw/misc/sifive_e_prci.h
27
diff --git a/hw/riscv/sifive_e_prci.c b/hw/misc/sifive_e_prci.c
28
similarity index 99%
29
rename from hw/riscv/sifive_e_prci.c
30
rename to hw/misc/sifive_e_prci.c
31
index XXXXXXX..XXXXXXX 100644
32
--- a/hw/riscv/sifive_e_prci.c
33
+++ b/hw/misc/sifive_e_prci.c
34
@@ -XXX,XX +XXX,XX @@
35
#include "qemu/log.h"
36
#include "qemu/module.h"
37
#include "hw/hw.h"
38
-#include "hw/riscv/sifive_e_prci.h"
39
+#include "hw/misc/sifive_e_prci.h"
40
41
static uint64_t sifive_e_prci_read(void *opaque, hwaddr addr, unsigned int size)
42
{
43
diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
44
index XXXXXXX..XXXXXXX 100644
45
--- a/hw/riscv/sifive_e.c
46
+++ b/hw/riscv/sifive_e.c
47
@@ -XXX,XX +XXX,XX @@
48
#include "hw/riscv/sifive_clint.h"
49
#include "hw/riscv/sifive_uart.h"
50
#include "hw/riscv/sifive_e.h"
51
-#include "hw/riscv/sifive_e_prci.h"
52
#include "hw/riscv/boot.h"
53
+#include "hw/misc/sifive_e_prci.h"
54
#include "chardev/char.h"
55
#include "sysemu/arch_init.h"
56
#include "sysemu/sysemu.h"
57
diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig
58
index XXXXXXX..XXXXXXX 100644
59
--- a/hw/misc/Kconfig
60
+++ b/hw/misc/Kconfig
61
@@ -XXX,XX +XXX,XX @@ config MAC_VIA
62
config AVR_POWER
63
bool
64
65
+config SIFIVE_E_PRCI
66
+ bool
67
+
68
source macio/Kconfig
69
diff --git a/hw/misc/meson.build b/hw/misc/meson.build
70
index XXXXXXX..XXXXXXX 100644
71
--- a/hw/misc/meson.build
72
+++ b/hw/misc/meson.build
73
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_ARM11SCU', if_true: files('arm11scu.c'))
74
# Mac devices
75
softmmu_ss.add(when: 'CONFIG_MOS6522', if_true: files('mos6522.c'))
76
77
+# RISC-V devices
78
+softmmu_ss.add(when: 'CONFIG_SIFIVE_E_PRCI', if_true: files('sifive_e_prci.c'))
79
+
80
# PKUnity SoC devices
81
softmmu_ss.add(when: 'CONFIG_PUV3', if_true: files('puv3_pm.c'))
82
83
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
84
index XXXXXXX..XXXXXXX 100644
85
--- a/hw/riscv/Kconfig
86
+++ b/hw/riscv/Kconfig
87
@@ -XXX,XX +XXX,XX @@ config SIFIVE_E
88
bool
89
select HART
90
select SIFIVE
91
+ select SIFIVE_E_PRCI
92
select UNIMP
93
94
config SIFIVE_U
95
diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
96
index XXXXXXX..XXXXXXX 100644
97
--- a/hw/riscv/meson.build
98
+++ b/hw/riscv/meson.build
99
@@ -XXX,XX +XXX,XX @@ riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_plic.c'))
100
riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_test.c'))
101
riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_uart.c'))
102
riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c'))
103
-riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e_prci.c'))
104
riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c'))
105
riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u_otp.c'))
106
riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u_prci.c'))
107
--
108
2.28.0
109
110
diff view generated by jsdifflib
New patch
[PULL 20/30] hw/riscv: Move sifive_u_prci model to hw/misc
1
From: Bin Meng <bin.meng@windriver.com>
1
2
3
This is an effort to clean up the hw/riscv directory. Ideally it
4
should only contain the RISC-V SoC / machine codes plus generic
5
codes. Let's move sifive_u_prci model to hw/misc directory.
6
7
Signed-off-by: Bin Meng <bin.meng@windriver.com>
8
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
9
Message-Id: <1599129623-68957-3-git-send-email-bmeng.cn@gmail.com>
10
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
11
---
12
include/hw/{riscv => misc}/sifive_u_prci.h | 0
13
include/hw/riscv/sifive_u.h | 2 +-
14
hw/{riscv => misc}/sifive_u_prci.c | 2 +-
15
hw/misc/Kconfig | 3 +++
16
hw/misc/meson.build | 1 +
17
hw/riscv/Kconfig | 1 +
18
hw/riscv/meson.build | 1 -
19
7 files changed, 7 insertions(+), 3 deletions(-)
20
rename include/hw/{riscv => misc}/sifive_u_prci.h (100%)
21
rename hw/{riscv => misc}/sifive_u_prci.c (99%)
22
23
diff --git a/include/hw/riscv/sifive_u_prci.h b/include/hw/misc/sifive_u_prci.h
24
similarity index 100%
25
rename from include/hw/riscv/sifive_u_prci.h
26
rename to include/hw/misc/sifive_u_prci.h
27
diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
28
index XXXXXXX..XXXXXXX 100644
29
--- a/include/hw/riscv/sifive_u.h
30
+++ b/include/hw/riscv/sifive_u.h
31
@@ -XXX,XX +XXX,XX @@
32
#include "hw/riscv/riscv_hart.h"
33
#include "hw/riscv/sifive_cpu.h"
34
#include "hw/riscv/sifive_gpio.h"
35
-#include "hw/riscv/sifive_u_prci.h"
36
#include "hw/riscv/sifive_u_otp.h"
37
+#include "hw/misc/sifive_u_prci.h"
38
39
#define TYPE_RISCV_U_SOC "riscv.sifive.u.soc"
40
#define RISCV_U_SOC(obj) \
41
diff --git a/hw/riscv/sifive_u_prci.c b/hw/misc/sifive_u_prci.c
42
similarity index 99%
43
rename from hw/riscv/sifive_u_prci.c
44
rename to hw/misc/sifive_u_prci.c
45
index XXXXXXX..XXXXXXX 100644
46
--- a/hw/riscv/sifive_u_prci.c
47
+++ b/hw/misc/sifive_u_prci.c
48
@@ -XXX,XX +XXX,XX @@
49
#include "hw/sysbus.h"
50
#include "qemu/log.h"
51
#include "qemu/module.h"
52
-#include "hw/riscv/sifive_u_prci.h"
53
+#include "hw/misc/sifive_u_prci.h"
54
55
static uint64_t sifive_u_prci_read(void *opaque, hwaddr addr, unsigned int size)
56
{
57
diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig
58
index XXXXXXX..XXXXXXX 100644
59
--- a/hw/misc/Kconfig
60
+++ b/hw/misc/Kconfig
61
@@ -XXX,XX +XXX,XX @@ config AVR_POWER
62
config SIFIVE_E_PRCI
63
bool
64
65
+config SIFIVE_U_PRCI
66
+ bool
67
+
68
source macio/Kconfig
69
diff --git a/hw/misc/meson.build b/hw/misc/meson.build
70
index XXXXXXX..XXXXXXX 100644
71
--- a/hw/misc/meson.build
72
+++ b/hw/misc/meson.build
73
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_MOS6522', if_true: files('mos6522.c'))
74
75
# RISC-V devices
76
softmmu_ss.add(when: 'CONFIG_SIFIVE_E_PRCI', if_true: files('sifive_e_prci.c'))
77
+softmmu_ss.add(when: 'CONFIG_SIFIVE_U_PRCI', if_true: files('sifive_u_prci.c'))
78
79
# PKUnity SoC devices
80
softmmu_ss.add(when: 'CONFIG_PUV3', if_true: files('puv3_pm.c'))
81
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
82
index XXXXXXX..XXXXXXX 100644
83
--- a/hw/riscv/Kconfig
84
+++ b/hw/riscv/Kconfig
85
@@ -XXX,XX +XXX,XX @@ config SIFIVE_U
86
select HART
87
select SIFIVE
88
select SIFIVE_PDMA
89
+ select SIFIVE_U_PRCI
90
select UNIMP
91
92
config SPIKE
93
diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
94
index XXXXXXX..XXXXXXX 100644
95
--- a/hw/riscv/meson.build
96
+++ b/hw/riscv/meson.build
97
@@ -XXX,XX +XXX,XX @@ riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_uart.c'))
98
riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c'))
99
riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c'))
100
riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u_otp.c'))
101
-riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u_prci.c'))
102
riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('riscv_htif.c'))
103
riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c'))
104
riscv_ss.add(when: 'CONFIG_MICROCHIP_PFSOC', if_true: files('microchip_pfsoc.c'))
105
--
106
2.28.0
107
108
diff view generated by jsdifflib
New patch
[PULL 21/30] hw/riscv: Move sifive_u_otp model to hw/misc
1
From: Bin Meng <bin.meng@windriver.com>
1
2
3
This is an effort to clean up the hw/riscv directory. Ideally it
4
should only contain the RISC-V SoC / machine codes plus generic
5
codes. Let's move sifive_u_otp model to hw/misc directory.
6
7
Signed-off-by: Bin Meng <bin.meng@windriver.com>
8
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
9
Message-Id: <1599129623-68957-4-git-send-email-bmeng.cn@gmail.com>
10
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
11
---
12
include/hw/{riscv => misc}/sifive_u_otp.h | 0
13
include/hw/riscv/sifive_u.h | 2 +-
14
hw/{riscv => misc}/sifive_u_otp.c | 2 +-
15
hw/misc/Kconfig | 3 +++
16
hw/misc/meson.build | 1 +
17
hw/riscv/Kconfig | 1 +
18
hw/riscv/meson.build | 1 -
19
7 files changed, 7 insertions(+), 3 deletions(-)
20
rename include/hw/{riscv => misc}/sifive_u_otp.h (100%)
21
rename hw/{riscv => misc}/sifive_u_otp.c (99%)
22
23
diff --git a/include/hw/riscv/sifive_u_otp.h b/include/hw/misc/sifive_u_otp.h
24
similarity index 100%
25
rename from include/hw/riscv/sifive_u_otp.h
26
rename to include/hw/misc/sifive_u_otp.h
27
diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
28
index XXXXXXX..XXXXXXX 100644
29
--- a/include/hw/riscv/sifive_u.h
30
+++ b/include/hw/riscv/sifive_u.h
31
@@ -XXX,XX +XXX,XX @@
32
#include "hw/riscv/riscv_hart.h"
33
#include "hw/riscv/sifive_cpu.h"
34
#include "hw/riscv/sifive_gpio.h"
35
-#include "hw/riscv/sifive_u_otp.h"
36
+#include "hw/misc/sifive_u_otp.h"
37
#include "hw/misc/sifive_u_prci.h"
38
39
#define TYPE_RISCV_U_SOC "riscv.sifive.u.soc"
40
diff --git a/hw/riscv/sifive_u_otp.c b/hw/misc/sifive_u_otp.c
41
similarity index 99%
42
rename from hw/riscv/sifive_u_otp.c
43
rename to hw/misc/sifive_u_otp.c
44
index XXXXXXX..XXXXXXX 100644
45
--- a/hw/riscv/sifive_u_otp.c
46
+++ b/hw/misc/sifive_u_otp.c
47
@@ -XXX,XX +XXX,XX @@
48
#include "hw/sysbus.h"
49
#include "qemu/log.h"
50
#include "qemu/module.h"
51
-#include "hw/riscv/sifive_u_otp.h"
52
+#include "hw/misc/sifive_u_otp.h"
53
54
static uint64_t sifive_u_otp_read(void *opaque, hwaddr addr, unsigned int size)
55
{
56
diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig
57
index XXXXXXX..XXXXXXX 100644
58
--- a/hw/misc/Kconfig
59
+++ b/hw/misc/Kconfig
60
@@ -XXX,XX +XXX,XX @@ config AVR_POWER
61
config SIFIVE_E_PRCI
62
bool
63
64
+config SIFIVE_U_OTP
65
+ bool
66
+
67
config SIFIVE_U_PRCI
68
bool
69
70
diff --git a/hw/misc/meson.build b/hw/misc/meson.build
71
index XXXXXXX..XXXXXXX 100644
72
--- a/hw/misc/meson.build
73
+++ b/hw/misc/meson.build
74
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_MOS6522', if_true: files('mos6522.c'))
75
76
# RISC-V devices
77
softmmu_ss.add(when: 'CONFIG_SIFIVE_E_PRCI', if_true: files('sifive_e_prci.c'))
78
+softmmu_ss.add(when: 'CONFIG_SIFIVE_U_OTP', if_true: files('sifive_u_otp.c'))
79
softmmu_ss.add(when: 'CONFIG_SIFIVE_U_PRCI', if_true: files('sifive_u_prci.c'))
80
81
# PKUnity SoC devices
82
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
83
index XXXXXXX..XXXXXXX 100644
84
--- a/hw/riscv/Kconfig
85
+++ b/hw/riscv/Kconfig
86
@@ -XXX,XX +XXX,XX @@ config SIFIVE_U
87
select HART
88
select SIFIVE
89
select SIFIVE_PDMA
90
+ select SIFIVE_U_OTP
91
select SIFIVE_U_PRCI
92
select UNIMP
93
94
diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
95
index XXXXXXX..XXXXXXX 100644
96
--- a/hw/riscv/meson.build
97
+++ b/hw/riscv/meson.build
98
@@ -XXX,XX +XXX,XX @@ riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_test.c'))
99
riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_uart.c'))
100
riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c'))
101
riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c'))
102
-riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u_otp.c'))
103
riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('riscv_htif.c'))
104
riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c'))
105
riscv_ss.add(when: 'CONFIG_MICROCHIP_PFSOC', if_true: files('microchip_pfsoc.c'))
106
--
107
2.28.0
108
109
diff view generated by jsdifflib
[PULL 11/12] target/riscv: Remove built-in GDB XML files for CSRs
[PULL 22/30] hw/riscv: Move sifive_gpio model to hw/gpio
1
From: Bin Meng <bin.meng@windriver.com>
1
From: Bin Meng <bin.meng@windriver.com>
2
2
3
Now that we have switched to generate the RISC-V CSR XML dynamically,
3
This is an effort to clean up the hw/riscv directory. Ideally it
4
remove the built-in hardcoded XML files.
4
should only contain the RISC-V SoC / machine codes plus generic
5
codes. Let's move sifive_gpio model to hw/gpio directory.
6
7
Note this also removes the trace-events in the hw/riscv directory,
8
since gpio is the only supported trace target in that directory.
5
9
6
Signed-off-by: Bin Meng <bin.meng@windriver.com>
10
Signed-off-by: Bin Meng <bin.meng@windriver.com>
7
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
11
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
8
Message-id: 20210116054123.5457-3-bmeng.cn@gmail.com
12
Message-Id: <1599129623-68957-5-git-send-email-bmeng.cn@gmail.com>
9
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
13
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
10
---
14
---
11
.../targets/riscv32-linux-user.mak | 2 +-
15
hw/riscv/trace.h | 1 -
12
default-configs/targets/riscv32-softmmu.mak | 2 +-
16
include/hw/{riscv => gpio}/sifive_gpio.h | 0
13
.../targets/riscv64-linux-user.mak | 2 +-
17
include/hw/riscv/sifive_e.h | 2 +-
14
default-configs/targets/riscv64-softmmu.mak | 2 +-
18
include/hw/riscv/sifive_u.h | 2 +-
15
gdb-xml/riscv-32bit-csr.xml | 250 ------------------
19
hw/{riscv => gpio}/sifive_gpio.c | 2 +-
16
gdb-xml/riscv-64bit-csr.xml | 250 ------------------
20
hw/gpio/Kconfig | 3 +++
17
6 files changed, 4 insertions(+), 504 deletions(-)
21
hw/gpio/meson.build | 1 +
18
delete mode 100644 gdb-xml/riscv-32bit-csr.xml
22
hw/gpio/trace-events | 6 ++++++
19
delete mode 100644 gdb-xml/riscv-64bit-csr.xml
23
hw/riscv/Kconfig | 2 ++
24
hw/riscv/meson.build | 1 -
25
hw/riscv/trace-events | 7 -------
26
meson.build | 1 -
27
12 files changed, 15 insertions(+), 13 deletions(-)
28
delete mode 100644 hw/riscv/trace.h
29
rename include/hw/{riscv => gpio}/sifive_gpio.h (100%)
30
rename hw/{riscv => gpio}/sifive_gpio.c (99%)
31
delete mode 100644 hw/riscv/trace-events
20
32
21
diff --git a/default-configs/targets/riscv32-linux-user.mak b/default-configs/targets/riscv32-linux-user.mak
33
diff --git a/hw/riscv/trace.h b/hw/riscv/trace.h
22
index XXXXXXX..XXXXXXX 100644
23
--- a/default-configs/targets/riscv32-linux-user.mak
24
+++ b/default-configs/targets/riscv32-linux-user.mak
25
@@ -XXX,XX +XXX,XX @@
26
TARGET_ARCH=riscv32
27
TARGET_BASE_ARCH=riscv
28
TARGET_ABI_DIR=riscv
29
-TARGET_XML_FILES= gdb-xml/riscv-32bit-cpu.xml gdb-xml/riscv-32bit-fpu.xml gdb-xml/riscv-64bit-fpu.xml gdb-xml/riscv-32bit-csr.xml gdb-xml/riscv-32bit-virtual.xml
30
+TARGET_XML_FILES= gdb-xml/riscv-32bit-cpu.xml gdb-xml/riscv-32bit-fpu.xml gdb-xml/riscv-64bit-fpu.xml gdb-xml/riscv-32bit-virtual.xml
31
diff --git a/default-configs/targets/riscv32-softmmu.mak b/default-configs/targets/riscv32-softmmu.mak
32
index XXXXXXX..XXXXXXX 100644
33
--- a/default-configs/targets/riscv32-softmmu.mak
34
+++ b/default-configs/targets/riscv32-softmmu.mak
35
@@ -XXX,XX +XXX,XX @@
36
TARGET_ARCH=riscv32
37
TARGET_BASE_ARCH=riscv
38
TARGET_SUPPORTS_MTTCG=y
39
-TARGET_XML_FILES= gdb-xml/riscv-32bit-cpu.xml gdb-xml/riscv-32bit-fpu.xml gdb-xml/riscv-64bit-fpu.xml gdb-xml/riscv-32bit-csr.xml gdb-xml/riscv-32bit-virtual.xml
40
+TARGET_XML_FILES= gdb-xml/riscv-32bit-cpu.xml gdb-xml/riscv-32bit-fpu.xml gdb-xml/riscv-64bit-fpu.xml gdb-xml/riscv-32bit-virtual.xml
41
TARGET_NEED_FDT=y
42
diff --git a/default-configs/targets/riscv64-linux-user.mak b/default-configs/targets/riscv64-linux-user.mak
43
index XXXXXXX..XXXXXXX 100644
44
--- a/default-configs/targets/riscv64-linux-user.mak
45
+++ b/default-configs/targets/riscv64-linux-user.mak
46
@@ -XXX,XX +XXX,XX @@
47
TARGET_ARCH=riscv64
48
TARGET_BASE_ARCH=riscv
49
TARGET_ABI_DIR=riscv
50
-TARGET_XML_FILES= gdb-xml/riscv-64bit-cpu.xml gdb-xml/riscv-32bit-fpu.xml gdb-xml/riscv-64bit-fpu.xml gdb-xml/riscv-64bit-csr.xml gdb-xml/riscv-64bit-virtual.xml
51
+TARGET_XML_FILES= gdb-xml/riscv-64bit-cpu.xml gdb-xml/riscv-32bit-fpu.xml gdb-xml/riscv-64bit-fpu.xml gdb-xml/riscv-64bit-virtual.xml
52
diff --git a/default-configs/targets/riscv64-softmmu.mak b/default-configs/targets/riscv64-softmmu.mak
53
index XXXXXXX..XXXXXXX 100644
54
--- a/default-configs/targets/riscv64-softmmu.mak
55
+++ b/default-configs/targets/riscv64-softmmu.mak
56
@@ -XXX,XX +XXX,XX @@
57
TARGET_ARCH=riscv64
58
TARGET_BASE_ARCH=riscv
59
TARGET_SUPPORTS_MTTCG=y
60
-TARGET_XML_FILES= gdb-xml/riscv-64bit-cpu.xml gdb-xml/riscv-32bit-fpu.xml gdb-xml/riscv-64bit-fpu.xml gdb-xml/riscv-64bit-csr.xml gdb-xml/riscv-64bit-virtual.xml
61
+TARGET_XML_FILES= gdb-xml/riscv-64bit-cpu.xml gdb-xml/riscv-32bit-fpu.xml gdb-xml/riscv-64bit-fpu.xml gdb-xml/riscv-64bit-virtual.xml
62
TARGET_NEED_FDT=y
63
diff --git a/gdb-xml/riscv-32bit-csr.xml b/gdb-xml/riscv-32bit-csr.xml
64
deleted file mode 100644
34
deleted file mode 100644
65
index XXXXXXX..XXXXXXX
35
index XXXXXXX..XXXXXXX
66
--- a/gdb-xml/riscv-32bit-csr.xml
36
--- a/hw/riscv/trace.h
37
+++ /dev/null
38
@@ -1 +0,0 @@
39
-#include "trace/trace-hw_riscv.h"
40
diff --git a/include/hw/riscv/sifive_gpio.h b/include/hw/gpio/sifive_gpio.h
41
similarity index 100%
42
rename from include/hw/riscv/sifive_gpio.h
43
rename to include/hw/gpio/sifive_gpio.h
44
diff --git a/include/hw/riscv/sifive_e.h b/include/hw/riscv/sifive_e.h
45
index XXXXXXX..XXXXXXX 100644
46
--- a/include/hw/riscv/sifive_e.h
47
+++ b/include/hw/riscv/sifive_e.h
48
@@ -XXX,XX +XXX,XX @@
49
50
#include "hw/riscv/riscv_hart.h"
51
#include "hw/riscv/sifive_cpu.h"
52
-#include "hw/riscv/sifive_gpio.h"
53
+#include "hw/gpio/sifive_gpio.h"
54
55
#define TYPE_RISCV_E_SOC "riscv.sifive.e.soc"
56
#define RISCV_E_SOC(obj) \
57
diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
58
index XXXXXXX..XXXXXXX 100644
59
--- a/include/hw/riscv/sifive_u.h
60
+++ b/include/hw/riscv/sifive_u.h
61
@@ -XXX,XX +XXX,XX @@
62
#include "hw/net/cadence_gem.h"
63
#include "hw/riscv/riscv_hart.h"
64
#include "hw/riscv/sifive_cpu.h"
65
-#include "hw/riscv/sifive_gpio.h"
66
+#include "hw/gpio/sifive_gpio.h"
67
#include "hw/misc/sifive_u_otp.h"
68
#include "hw/misc/sifive_u_prci.h"
69
70
diff --git a/hw/riscv/sifive_gpio.c b/hw/gpio/sifive_gpio.c
71
similarity index 99%
72
rename from hw/riscv/sifive_gpio.c
73
rename to hw/gpio/sifive_gpio.c
74
index XXXXXXX..XXXXXXX 100644
75
--- a/hw/riscv/sifive_gpio.c
76
+++ b/hw/gpio/sifive_gpio.c
77
@@ -XXX,XX +XXX,XX @@
78
#include "qemu/log.h"
79
#include "hw/irq.h"
80
#include "hw/qdev-properties.h"
81
-#include "hw/riscv/sifive_gpio.h"
82
+#include "hw/gpio/sifive_gpio.h"
83
#include "migration/vmstate.h"
84
#include "trace.h"
85
86
diff --git a/hw/gpio/Kconfig b/hw/gpio/Kconfig
87
index XXXXXXX..XXXXXXX 100644
88
--- a/hw/gpio/Kconfig
89
+++ b/hw/gpio/Kconfig
90
@@ -XXX,XX +XXX,XX @@ config PL061
91
92
config GPIO_KEY
93
bool
94
+
95
+config SIFIVE_GPIO
96
+ bool
97
diff --git a/hw/gpio/meson.build b/hw/gpio/meson.build
98
index XXXXXXX..XXXXXXX 100644
99
--- a/hw/gpio/meson.build
100
+++ b/hw/gpio/meson.build
101
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_NRF51_SOC', if_true: files('nrf51_gpio.c'))
102
softmmu_ss.add(when: 'CONFIG_OMAP', if_true: files('omap_gpio.c'))
103
softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_gpio.c'))
104
softmmu_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files('aspeed_gpio.c'))
105
+softmmu_ss.add(when: 'CONFIG_SIFIVE_GPIO', if_true: files('sifive_gpio.c'))
106
diff --git a/hw/gpio/trace-events b/hw/gpio/trace-events
107
index XXXXXXX..XXXXXXX 100644
108
--- a/hw/gpio/trace-events
109
+++ b/hw/gpio/trace-events
110
@@ -XXX,XX +XXX,XX @@ nrf51_gpio_read(uint64_t offset, uint64_t r) "offset 0x%" PRIx64 " value 0x%" PR
111
nrf51_gpio_write(uint64_t offset, uint64_t value) "offset 0x%" PRIx64 " value 0x%" PRIx64
112
nrf51_gpio_set(int64_t line, int64_t value) "line %" PRIi64 " value %" PRIi64
113
nrf51_gpio_update_output_irq(int64_t line, int64_t value) "line %" PRIi64 " value %" PRIi64
114
+
115
+# sifive_gpio.c
116
+sifive_gpio_read(uint64_t offset, uint64_t r) "offset 0x%" PRIx64 " value 0x%" PRIx64
117
+sifive_gpio_write(uint64_t offset, uint64_t value) "offset 0x%" PRIx64 " value 0x%" PRIx64
118
+sifive_gpio_set(int64_t line, int64_t value) "line %" PRIi64 " value %" PRIi64
119
+sifive_gpio_update_output_irq(int64_t line, int64_t value) "line %" PRIi64 " value %" PRIi64
120
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
121
index XXXXXXX..XXXXXXX 100644
122
--- a/hw/riscv/Kconfig
123
+++ b/hw/riscv/Kconfig
124
@@ -XXX,XX +XXX,XX @@ config SIFIVE_E
125
bool
126
select HART
127
select SIFIVE
128
+ select SIFIVE_GPIO
129
select SIFIVE_E_PRCI
130
select UNIMP
131
132
@@ -XXX,XX +XXX,XX @@ config SIFIVE_U
133
select CADENCE
134
select HART
135
select SIFIVE
136
+ select SIFIVE_GPIO
137
select SIFIVE_PDMA
138
select SIFIVE_U_OTP
139
select SIFIVE_U_PRCI
140
diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
141
index XXXXXXX..XXXXXXX 100644
142
--- a/hw/riscv/meson.build
143
+++ b/hw/riscv/meson.build
144
@@ -XXX,XX +XXX,XX @@ riscv_ss.add(when: 'CONFIG_HART', if_true: files('riscv_hart.c'))
145
riscv_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c'))
146
riscv_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c'))
147
riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_clint.c'))
148
-riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_gpio.c'))
149
riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_plic.c'))
150
riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_test.c'))
151
riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_uart.c'))
152
diff --git a/hw/riscv/trace-events b/hw/riscv/trace-events
153
deleted file mode 100644
154
index XXXXXXX..XXXXXXX
155
--- a/hw/riscv/trace-events
67
+++ /dev/null
156
+++ /dev/null
68
@@ -XXX,XX +XXX,XX @@
157
@@ -XXX,XX +XXX,XX @@
69
-<?xml version="1.0"?>
158
-# See docs/devel/tracing.txt for syntax documentation.
70
-<!-- Copyright (C) 2018-2019 Free Software Foundation, Inc.
71
-
159
-
72
- Copying and distribution of this file, with or without modification,
160
-# hw/gpio/sifive_gpio.c
73
- are permitted in any medium without royalty provided the copyright
161
-sifive_gpio_read(uint64_t offset, uint64_t r) "offset 0x%" PRIx64 " value 0x%" PRIx64
74
- notice and this notice are preserved. -->
162
-sifive_gpio_write(uint64_t offset, uint64_t value) "offset 0x%" PRIx64 " value 0x%" PRIx64
75
-
163
-sifive_gpio_set(int64_t line, int64_t value) "line %" PRIi64 " value %" PRIi64
76
-<!DOCTYPE feature SYSTEM "gdb-target.dtd">
164
-sifive_gpio_update_output_irq(int64_t line, int64_t value) "line %" PRIi64 " value %" PRIi64
77
-<feature name="org.gnu.gdb.riscv.csr">
165
diff --git a/meson.build b/meson.build
78
- <reg name="ustatus" bitsize="32"/>
166
index XXXXXXX..XXXXXXX 100644
79
- <reg name="uie" bitsize="32"/>
167
--- a/meson.build
80
- <reg name="utvec" bitsize="32"/>
168
+++ b/meson.build
81
- <reg name="uscratch" bitsize="32"/>
169
@@ -XXX,XX +XXX,XX @@ if have_system
82
- <reg name="uepc" bitsize="32"/>
170
'hw/watchdog',
83
- <reg name="ucause" bitsize="32"/>
171
'hw/xen',
84
- <reg name="utval" bitsize="32"/>
172
'hw/gpio',
85
- <reg name="uip" bitsize="32"/>
173
- 'hw/riscv',
86
- <reg name="fflags" bitsize="32"/>
174
'migration',
87
- <reg name="frm" bitsize="32"/>
175
'net',
88
- <reg name="fcsr" bitsize="32"/>
176
'ui',
89
- <reg name="cycle" bitsize="32"/>
90
- <reg name="time" bitsize="32"/>
91
- <reg name="instret" bitsize="32"/>
92
- <reg name="hpmcounter3" bitsize="32"/>
93
- <reg name="hpmcounter4" bitsize="32"/>
94
- <reg name="hpmcounter5" bitsize="32"/>
95
- <reg name="hpmcounter6" bitsize="32"/>
96
- <reg name="hpmcounter7" bitsize="32"/>
97
- <reg name="hpmcounter8" bitsize="32"/>
98
- <reg name="hpmcounter9" bitsize="32"/>
99
- <reg name="hpmcounter10" bitsize="32"/>
100
- <reg name="hpmcounter11" bitsize="32"/>
101
- <reg name="hpmcounter12" bitsize="32"/>
102
- <reg name="hpmcounter13" bitsize="32"/>
103
- <reg name="hpmcounter14" bitsize="32"/>
104
- <reg name="hpmcounter15" bitsize="32"/>
105
- <reg name="hpmcounter16" bitsize="32"/>
106
- <reg name="hpmcounter17" bitsize="32"/>
107
- <reg name="hpmcounter18" bitsize="32"/>
108
- <reg name="hpmcounter19" bitsize="32"/>
109
- <reg name="hpmcounter20" bitsize="32"/>
110
- <reg name="hpmcounter21" bitsize="32"/>
111
- <reg name="hpmcounter22" bitsize="32"/>
112
- <reg name="hpmcounter23" bitsize="32"/>
113
- <reg name="hpmcounter24" bitsize="32"/>
114
- <reg name="hpmcounter25" bitsize="32"/>
115
- <reg name="hpmcounter26" bitsize="32"/>
116
- <reg name="hpmcounter27" bitsize="32"/>
117
- <reg name="hpmcounter28" bitsize="32"/>
118
- <reg name="hpmcounter29" bitsize="32"/>
119
- <reg name="hpmcounter30" bitsize="32"/>
120
- <reg name="hpmcounter31" bitsize="32"/>
121
- <reg name="cycleh" bitsize="32"/>
122
- <reg name="timeh" bitsize="32"/>
123
- <reg name="instreth" bitsize="32"/>
124
- <reg name="hpmcounter3h" bitsize="32"/>
125
- <reg name="hpmcounter4h" bitsize="32"/>
126
- <reg name="hpmcounter5h" bitsize="32"/>
127
- <reg name="hpmcounter6h" bitsize="32"/>
128
- <reg name="hpmcounter7h" bitsize="32"/>
129
- <reg name="hpmcounter8h" bitsize="32"/>
130
- <reg name="hpmcounter9h" bitsize="32"/>
131
- <reg name="hpmcounter10h" bitsize="32"/>
132
- <reg name="hpmcounter11h" bitsize="32"/>
133
- <reg name="hpmcounter12h" bitsize="32"/>
134
- <reg name="hpmcounter13h" bitsize="32"/>
135
- <reg name="hpmcounter14h" bitsize="32"/>
136
- <reg name="hpmcounter15h" bitsize="32"/>
137
- <reg name="hpmcounter16h" bitsize="32"/>
138
- <reg name="hpmcounter17h" bitsize="32"/>
139
- <reg name="hpmcounter18h" bitsize="32"/>
140
- <reg name="hpmcounter19h" bitsize="32"/>
141
- <reg name="hpmcounter20h" bitsize="32"/>
142
- <reg name="hpmcounter21h" bitsize="32"/>
143
- <reg name="hpmcounter22h" bitsize="32"/>
144
- <reg name="hpmcounter23h" bitsize="32"/>
145
- <reg name="hpmcounter24h" bitsize="32"/>
146
- <reg name="hpmcounter25h" bitsize="32"/>
147
- <reg name="hpmcounter26h" bitsize="32"/>
148
- <reg name="hpmcounter27h" bitsize="32"/>
149
- <reg name="hpmcounter28h" bitsize="32"/>
150
- <reg name="hpmcounter29h" bitsize="32"/>
151
- <reg name="hpmcounter30h" bitsize="32"/>
152
- <reg name="hpmcounter31h" bitsize="32"/>
153
- <reg name="sstatus" bitsize="32"/>
154
- <reg name="sedeleg" bitsize="32"/>
155
- <reg name="sideleg" bitsize="32"/>
156
- <reg name="sie" bitsize="32"/>
157
- <reg name="stvec" bitsize="32"/>
158
- <reg name="scounteren" bitsize="32"/>
159
- <reg name="sscratch" bitsize="32"/>
160
- <reg name="sepc" bitsize="32"/>
161
- <reg name="scause" bitsize="32"/>
162
- <reg name="stval" bitsize="32"/>
163
- <reg name="sip" bitsize="32"/>
164
- <reg name="satp" bitsize="32"/>
165
- <reg name="mvendorid" bitsize="32"/>
166
- <reg name="marchid" bitsize="32"/>
167
- <reg name="mimpid" bitsize="32"/>
168
- <reg name="mhartid" bitsize="32"/>
169
- <reg name="mstatus" bitsize="32"/>
170
- <reg name="misa" bitsize="32"/>
171
- <reg name="medeleg" bitsize="32"/>
172
- <reg name="mideleg" bitsize="32"/>
173
- <reg name="mie" bitsize="32"/>
174
- <reg name="mtvec" bitsize="32"/>
175
- <reg name="mcounteren" bitsize="32"/>
176
- <reg name="mscratch" bitsize="32"/>
177
- <reg name="mepc" bitsize="32"/>
178
- <reg name="mcause" bitsize="32"/>
179
- <reg name="mtval" bitsize="32"/>
180
- <reg name="mip" bitsize="32"/>
181
- <reg name="pmpcfg0" bitsize="32"/>
182
- <reg name="pmpcfg1" bitsize="32"/>
183
- <reg name="pmpcfg2" bitsize="32"/>
184
- <reg name="pmpcfg3" bitsize="32"/>
185
- <reg name="pmpaddr0" bitsize="32"/>
186
- <reg name="pmpaddr1" bitsize="32"/>
187
- <reg name="pmpaddr2" bitsize="32"/>
188
- <reg name="pmpaddr3" bitsize="32"/>
189
- <reg name="pmpaddr4" bitsize="32"/>
190
- <reg name="pmpaddr5" bitsize="32"/>
191
- <reg name="pmpaddr6" bitsize="32"/>
192
- <reg name="pmpaddr7" bitsize="32"/>
193
- <reg name="pmpaddr8" bitsize="32"/>
194
- <reg name="pmpaddr9" bitsize="32"/>
195
- <reg name="pmpaddr10" bitsize="32"/>
196
- <reg name="pmpaddr11" bitsize="32"/>
197
- <reg name="pmpaddr12" bitsize="32"/>
198
- <reg name="pmpaddr13" bitsize="32"/>
199
- <reg name="pmpaddr14" bitsize="32"/>
200
- <reg name="pmpaddr15" bitsize="32"/>
201
- <reg name="mcycle" bitsize="32"/>
202
- <reg name="minstret" bitsize="32"/>
203
- <reg name="mhpmcounter3" bitsize="32"/>
204
- <reg name="mhpmcounter4" bitsize="32"/>
205
- <reg name="mhpmcounter5" bitsize="32"/>
206
- <reg name="mhpmcounter6" bitsize="32"/>
207
- <reg name="mhpmcounter7" bitsize="32"/>
208
- <reg name="mhpmcounter8" bitsize="32"/>
209
- <reg name="mhpmcounter9" bitsize="32"/>
210
- <reg name="mhpmcounter10" bitsize="32"/>
211
- <reg name="mhpmcounter11" bitsize="32"/>
212
- <reg name="mhpmcounter12" bitsize="32"/>
213
- <reg name="mhpmcounter13" bitsize="32"/>
214
- <reg name="mhpmcounter14" bitsize="32"/>
215
- <reg name="mhpmcounter15" bitsize="32"/>
216
- <reg name="mhpmcounter16" bitsize="32"/>
217
- <reg name="mhpmcounter17" bitsize="32"/>
218
- <reg name="mhpmcounter18" bitsize="32"/>
219
- <reg name="mhpmcounter19" bitsize="32"/>
220
- <reg name="mhpmcounter20" bitsize="32"/>
221
- <reg name="mhpmcounter21" bitsize="32"/>
222
- <reg name="mhpmcounter22" bitsize="32"/>
223
- <reg name="mhpmcounter23" bitsize="32"/>
224
- <reg name="mhpmcounter24" bitsize="32"/>
225
- <reg name="mhpmcounter25" bitsize="32"/>
226
- <reg name="mhpmcounter26" bitsize="32"/>
227
- <reg name="mhpmcounter27" bitsize="32"/>
228
- <reg name="mhpmcounter28" bitsize="32"/>
229
- <reg name="mhpmcounter29" bitsize="32"/>
230
- <reg name="mhpmcounter30" bitsize="32"/>
231
- <reg name="mhpmcounter31" bitsize="32"/>
232
- <reg name="mcycleh" bitsize="32"/>
233
- <reg name="minstreth" bitsize="32"/>
234
- <reg name="mhpmcounter3h" bitsize="32"/>
235
- <reg name="mhpmcounter4h" bitsize="32"/>
236
- <reg name="mhpmcounter5h" bitsize="32"/>
237
- <reg name="mhpmcounter6h" bitsize="32"/>
238
- <reg name="mhpmcounter7h" bitsize="32"/>
239
- <reg name="mhpmcounter8h" bitsize="32"/>
240
- <reg name="mhpmcounter9h" bitsize="32"/>
241
- <reg name="mhpmcounter10h" bitsize="32"/>
242
- <reg name="mhpmcounter11h" bitsize="32"/>
243
- <reg name="mhpmcounter12h" bitsize="32"/>
244
- <reg name="mhpmcounter13h" bitsize="32"/>
245
- <reg name="mhpmcounter14h" bitsize="32"/>
246
- <reg name="mhpmcounter15h" bitsize="32"/>
247
- <reg name="mhpmcounter16h" bitsize="32"/>
248
- <reg name="mhpmcounter17h" bitsize="32"/>
249
- <reg name="mhpmcounter18h" bitsize="32"/>
250
- <reg name="mhpmcounter19h" bitsize="32"/>
251
- <reg name="mhpmcounter20h" bitsize="32"/>
252
- <reg name="mhpmcounter21h" bitsize="32"/>
253
- <reg name="mhpmcounter22h" bitsize="32"/>
254
- <reg name="mhpmcounter23h" bitsize="32"/>
255
- <reg name="mhpmcounter24h" bitsize="32"/>
256
- <reg name="mhpmcounter25h" bitsize="32"/>
257
- <reg name="mhpmcounter26h" bitsize="32"/>
258
- <reg name="mhpmcounter27h" bitsize="32"/>
259
- <reg name="mhpmcounter28h" bitsize="32"/>
260
- <reg name="mhpmcounter29h" bitsize="32"/>
261
- <reg name="mhpmcounter30h" bitsize="32"/>
262
- <reg name="mhpmcounter31h" bitsize="32"/>
263
- <reg name="mhpmevent3" bitsize="32"/>
264
- <reg name="mhpmevent4" bitsize="32"/>
265
- <reg name="mhpmevent5" bitsize="32"/>
266
- <reg name="mhpmevent6" bitsize="32"/>
267
- <reg name="mhpmevent7" bitsize="32"/>
268
- <reg name="mhpmevent8" bitsize="32"/>
269
- <reg name="mhpmevent9" bitsize="32"/>
270
- <reg name="mhpmevent10" bitsize="32"/>
271
- <reg name="mhpmevent11" bitsize="32"/>
272
- <reg name="mhpmevent12" bitsize="32"/>
273
- <reg name="mhpmevent13" bitsize="32"/>
274
- <reg name="mhpmevent14" bitsize="32"/>
275
- <reg name="mhpmevent15" bitsize="32"/>
276
- <reg name="mhpmevent16" bitsize="32"/>
277
- <reg name="mhpmevent17" bitsize="32"/>
278
- <reg name="mhpmevent18" bitsize="32"/>
279
- <reg name="mhpmevent19" bitsize="32"/>
280
- <reg name="mhpmevent20" bitsize="32"/>
281
- <reg name="mhpmevent21" bitsize="32"/>
282
- <reg name="mhpmevent22" bitsize="32"/>
283
- <reg name="mhpmevent23" bitsize="32"/>
284
- <reg name="mhpmevent24" bitsize="32"/>
285
- <reg name="mhpmevent25" bitsize="32"/>
286
- <reg name="mhpmevent26" bitsize="32"/>
287
- <reg name="mhpmevent27" bitsize="32"/>
288
- <reg name="mhpmevent28" bitsize="32"/>
289
- <reg name="mhpmevent29" bitsize="32"/>
290
- <reg name="mhpmevent30" bitsize="32"/>
291
- <reg name="mhpmevent31" bitsize="32"/>
292
- <reg name="tselect" bitsize="32"/>
293
- <reg name="tdata1" bitsize="32"/>
294
- <reg name="tdata2" bitsize="32"/>
295
- <reg name="tdata3" bitsize="32"/>
296
- <reg name="dcsr" bitsize="32"/>
297
- <reg name="dpc" bitsize="32"/>
298
- <reg name="dscratch" bitsize="32"/>
299
- <reg name="hstatus" bitsize="32"/>
300
- <reg name="hedeleg" bitsize="32"/>
301
- <reg name="hideleg" bitsize="32"/>
302
- <reg name="hie" bitsize="32"/>
303
- <reg name="htvec" bitsize="32"/>
304
- <reg name="hscratch" bitsize="32"/>
305
- <reg name="hepc" bitsize="32"/>
306
- <reg name="hcause" bitsize="32"/>
307
- <reg name="hbadaddr" bitsize="32"/>
308
- <reg name="hip" bitsize="32"/>
309
- <reg name="mbase" bitsize="32"/>
310
- <reg name="mbound" bitsize="32"/>
311
- <reg name="mibase" bitsize="32"/>
312
- <reg name="mibound" bitsize="32"/>
313
- <reg name="mdbase" bitsize="32"/>
314
- <reg name="mdbound" bitsize="32"/>
315
- <reg name="mucounteren" bitsize="32"/>
316
- <reg name="mscounteren" bitsize="32"/>
317
- <reg name="mhcounteren" bitsize="32"/>
318
-</feature>
319
diff --git a/gdb-xml/riscv-64bit-csr.xml b/gdb-xml/riscv-64bit-csr.xml
320
deleted file mode 100644
321
index XXXXXXX..XXXXXXX
322
--- a/gdb-xml/riscv-64bit-csr.xml
323
+++ /dev/null
324
@@ -XXX,XX +XXX,XX @@
325
-<?xml version="1.0"?>
326
-<!-- Copyright (C) 2018-2019 Free Software Foundation, Inc.
327
-
328
- Copying and distribution of this file, with or without modification,
329
- are permitted in any medium without royalty provided the copyright
330
- notice and this notice are preserved. -->
331
-
332
-<!DOCTYPE feature SYSTEM "gdb-target.dtd">
333
-<feature name="org.gnu.gdb.riscv.csr">
334
- <reg name="ustatus" bitsize="64"/>
335
- <reg name="uie" bitsize="64"/>
336
- <reg name="utvec" bitsize="64"/>
337
- <reg name="uscratch" bitsize="64"/>
338
- <reg name="uepc" bitsize="64"/>
339
- <reg name="ucause" bitsize="64"/>
340
- <reg name="utval" bitsize="64"/>
341
- <reg name="uip" bitsize="64"/>
342
- <reg name="fflags" bitsize="64"/>
343
- <reg name="frm" bitsize="64"/>
344
- <reg name="fcsr" bitsize="64"/>
345
- <reg name="cycle" bitsize="64"/>
346
- <reg name="time" bitsize="64"/>
347
- <reg name="instret" bitsize="64"/>
348
- <reg name="hpmcounter3" bitsize="64"/>
349
- <reg name="hpmcounter4" bitsize="64"/>
350
- <reg name="hpmcounter5" bitsize="64"/>
351
- <reg name="hpmcounter6" bitsize="64"/>
352
- <reg name="hpmcounter7" bitsize="64"/>
353
- <reg name="hpmcounter8" bitsize="64"/>
354
- <reg name="hpmcounter9" bitsize="64"/>
355
- <reg name="hpmcounter10" bitsize="64"/>
356
- <reg name="hpmcounter11" bitsize="64"/>
357
- <reg name="hpmcounter12" bitsize="64"/>
358
- <reg name="hpmcounter13" bitsize="64"/>
359
- <reg name="hpmcounter14" bitsize="64"/>
360
- <reg name="hpmcounter15" bitsize="64"/>
361
- <reg name="hpmcounter16" bitsize="64"/>
362
- <reg name="hpmcounter17" bitsize="64"/>
363
- <reg name="hpmcounter18" bitsize="64"/>
364
- <reg name="hpmcounter19" bitsize="64"/>
365
- <reg name="hpmcounter20" bitsize="64"/>
366
- <reg name="hpmcounter21" bitsize="64"/>
367
- <reg name="hpmcounter22" bitsize="64"/>
368
- <reg name="hpmcounter23" bitsize="64"/>
369
- <reg name="hpmcounter24" bitsize="64"/>
370
- <reg name="hpmcounter25" bitsize="64"/>
371
- <reg name="hpmcounter26" bitsize="64"/>
372
- <reg name="hpmcounter27" bitsize="64"/>
373
- <reg name="hpmcounter28" bitsize="64"/>
374
- <reg name="hpmcounter29" bitsize="64"/>
375
- <reg name="hpmcounter30" bitsize="64"/>
376
- <reg name="hpmcounter31" bitsize="64"/>
377
- <reg name="cycleh" bitsize="64"/>
378
- <reg name="timeh" bitsize="64"/>
379
- <reg name="instreth" bitsize="64"/>
380
- <reg name="hpmcounter3h" bitsize="64"/>
381
- <reg name="hpmcounter4h" bitsize="64"/>
382
- <reg name="hpmcounter5h" bitsize="64"/>
383
- <reg name="hpmcounter6h" bitsize="64"/>
384
- <reg name="hpmcounter7h" bitsize="64"/>
385
- <reg name="hpmcounter8h" bitsize="64"/>
386
- <reg name="hpmcounter9h" bitsize="64"/>
387
- <reg name="hpmcounter10h" bitsize="64"/>
388
- <reg name="hpmcounter11h" bitsize="64"/>
389
- <reg name="hpmcounter12h" bitsize="64"/>
390
- <reg name="hpmcounter13h" bitsize="64"/>
391
- <reg name="hpmcounter14h" bitsize="64"/>
392
- <reg name="hpmcounter15h" bitsize="64"/>
393
- <reg name="hpmcounter16h" bitsize="64"/>
394
- <reg name="hpmcounter17h" bitsize="64"/>
395
- <reg name="hpmcounter18h" bitsize="64"/>
396
- <reg name="hpmcounter19h" bitsize="64"/>
397
- <reg name="hpmcounter20h" bitsize="64"/>
398
- <reg name="hpmcounter21h" bitsize="64"/>
399
- <reg name="hpmcounter22h" bitsize="64"/>
400
- <reg name="hpmcounter23h" bitsize="64"/>
401
- <reg name="hpmcounter24h" bitsize="64"/>
402
- <reg name="hpmcounter25h" bitsize="64"/>
403
- <reg name="hpmcounter26h" bitsize="64"/>
404
- <reg name="hpmcounter27h" bitsize="64"/>
405
- <reg name="hpmcounter28h" bitsize="64"/>
406
- <reg name="hpmcounter29h" bitsize="64"/>
407
- <reg name="hpmcounter30h" bitsize="64"/>
408
- <reg name="hpmcounter31h" bitsize="64"/>
409
- <reg name="sstatus" bitsize="64"/>
410
- <reg name="sedeleg" bitsize="64"/>
411
- <reg name="sideleg" bitsize="64"/>
412
- <reg name="sie" bitsize="64"/>
413
- <reg name="stvec" bitsize="64"/>
414
- <reg name="scounteren" bitsize="64"/>
415
- <reg name="sscratch" bitsize="64"/>
416
- <reg name="sepc" bitsize="64"/>
417
- <reg name="scause" bitsize="64"/>
418
- <reg name="stval" bitsize="64"/>
419
- <reg name="sip" bitsize="64"/>
420
- <reg name="satp" bitsize="64"/>
421
- <reg name="mvendorid" bitsize="64"/>
422
- <reg name="marchid" bitsize="64"/>
423
- <reg name="mimpid" bitsize="64"/>
424
- <reg name="mhartid" bitsize="64"/>
425
- <reg name="mstatus" bitsize="64"/>
426
- <reg name="misa" bitsize="64"/>
427
- <reg name="medeleg" bitsize="64"/>
428
- <reg name="mideleg" bitsize="64"/>
429
- <reg name="mie" bitsize="64"/>
430
- <reg name="mtvec" bitsize="64"/>
431
- <reg name="mcounteren" bitsize="64"/>
432
- <reg name="mscratch" bitsize="64"/>
433
- <reg name="mepc" bitsize="64"/>
434
- <reg name="mcause" bitsize="64"/>
435
- <reg name="mtval" bitsize="64"/>
436
- <reg name="mip" bitsize="64"/>
437
- <reg name="pmpcfg0" bitsize="64"/>
438
- <reg name="pmpcfg1" bitsize="64"/>
439
- <reg name="pmpcfg2" bitsize="64"/>
440
- <reg name="pmpcfg3" bitsize="64"/>
441
- <reg name="pmpaddr0" bitsize="64"/>
442
- <reg name="pmpaddr1" bitsize="64"/>
443
- <reg name="pmpaddr2" bitsize="64"/>
444
- <reg name="pmpaddr3" bitsize="64"/>
445
- <reg name="pmpaddr4" bitsize="64"/>
446
- <reg name="pmpaddr5" bitsize="64"/>
447
- <reg name="pmpaddr6" bitsize="64"/>
448
- <reg name="pmpaddr7" bitsize="64"/>
449
- <reg name="pmpaddr8" bitsize="64"/>
450
- <reg name="pmpaddr9" bitsize="64"/>
451
- <reg name="pmpaddr10" bitsize="64"/>
452
- <reg name="pmpaddr11" bitsize="64"/>
453
- <reg name="pmpaddr12" bitsize="64"/>
454
- <reg name="pmpaddr13" bitsize="64"/>
455
- <reg name="pmpaddr14" bitsize="64"/>
456
- <reg name="pmpaddr15" bitsize="64"/>
457
- <reg name="mcycle" bitsize="64"/>
458
- <reg name="minstret" bitsize="64"/>
459
- <reg name="mhpmcounter3" bitsize="64"/>
460
- <reg name="mhpmcounter4" bitsize="64"/>
461
- <reg name="mhpmcounter5" bitsize="64"/>
462
- <reg name="mhpmcounter6" bitsize="64"/>
463
- <reg name="mhpmcounter7" bitsize="64"/>
464
- <reg name="mhpmcounter8" bitsize="64"/>
465
- <reg name="mhpmcounter9" bitsize="64"/>
466
- <reg name="mhpmcounter10" bitsize="64"/>
467
- <reg name="mhpmcounter11" bitsize="64"/>
468
- <reg name="mhpmcounter12" bitsize="64"/>
469
- <reg name="mhpmcounter13" bitsize="64"/>
470
- <reg name="mhpmcounter14" bitsize="64"/>
471
- <reg name="mhpmcounter15" bitsize="64"/>
472
- <reg name="mhpmcounter16" bitsize="64"/>
473
- <reg name="mhpmcounter17" bitsize="64"/>
474
- <reg name="mhpmcounter18" bitsize="64"/>
475
- <reg name="mhpmcounter19" bitsize="64"/>
476
- <reg name="mhpmcounter20" bitsize="64"/>
477
- <reg name="mhpmcounter21" bitsize="64"/>
478
- <reg name="mhpmcounter22" bitsize="64"/>
479
- <reg name="mhpmcounter23" bitsize="64"/>
480
- <reg name="mhpmcounter24" bitsize="64"/>
481
- <reg name="mhpmcounter25" bitsize="64"/>
482
- <reg name="mhpmcounter26" bitsize="64"/>
483
- <reg name="mhpmcounter27" bitsize="64"/>
484
- <reg name="mhpmcounter28" bitsize="64"/>
485
- <reg name="mhpmcounter29" bitsize="64"/>
486
- <reg name="mhpmcounter30" bitsize="64"/>
487
- <reg name="mhpmcounter31" bitsize="64"/>
488
- <reg name="mcycleh" bitsize="64"/>
489
- <reg name="minstreth" bitsize="64"/>
490
- <reg name="mhpmcounter3h" bitsize="64"/>
491
- <reg name="mhpmcounter4h" bitsize="64"/>
492
- <reg name="mhpmcounter5h" bitsize="64"/>
493
- <reg name="mhpmcounter6h" bitsize="64"/>
494
- <reg name="mhpmcounter7h" bitsize="64"/>
495
- <reg name="mhpmcounter8h" bitsize="64"/>
496
- <reg name="mhpmcounter9h" bitsize="64"/>
497
- <reg name="mhpmcounter10h" bitsize="64"/>
498
- <reg name="mhpmcounter11h" bitsize="64"/>
499
- <reg name="mhpmcounter12h" bitsize="64"/>
500
- <reg name="mhpmcounter13h" bitsize="64"/>
501
- <reg name="mhpmcounter14h" bitsize="64"/>
502
- <reg name="mhpmcounter15h" bitsize="64"/>
503
- <reg name="mhpmcounter16h" bitsize="64"/>
504
- <reg name="mhpmcounter17h" bitsize="64"/>
505
- <reg name="mhpmcounter18h" bitsize="64"/>
506
- <reg name="mhpmcounter19h" bitsize="64"/>
507
- <reg name="mhpmcounter20h" bitsize="64"/>
508
- <reg name="mhpmcounter21h" bitsize="64"/>
509
- <reg name="mhpmcounter22h" bitsize="64"/>
510
- <reg name="mhpmcounter23h" bitsize="64"/>
511
- <reg name="mhpmcounter24h" bitsize="64"/>
512
- <reg name="mhpmcounter25h" bitsize="64"/>
513
- <reg name="mhpmcounter26h" bitsize="64"/>
514
- <reg name="mhpmcounter27h" bitsize="64"/>
515
- <reg name="mhpmcounter28h" bitsize="64"/>
516
- <reg name="mhpmcounter29h" bitsize="64"/>
517
- <reg name="mhpmcounter30h" bitsize="64"/>
518
- <reg name="mhpmcounter31h" bitsize="64"/>
519
- <reg name="mhpmevent3" bitsize="64"/>
520
- <reg name="mhpmevent4" bitsize="64"/>
521
- <reg name="mhpmevent5" bitsize="64"/>
522
- <reg name="mhpmevent6" bitsize="64"/>
523
- <reg name="mhpmevent7" bitsize="64"/>
524
- <reg name="mhpmevent8" bitsize="64"/>
525
- <reg name="mhpmevent9" bitsize="64"/>
526
- <reg name="mhpmevent10" bitsize="64"/>
527
- <reg name="mhpmevent11" bitsize="64"/>
528
- <reg name="mhpmevent12" bitsize="64"/>
529
- <reg name="mhpmevent13" bitsize="64"/>
530
- <reg name="mhpmevent14" bitsize="64"/>
531
- <reg name="mhpmevent15" bitsize="64"/>
532
- <reg name="mhpmevent16" bitsize="64"/>
533
- <reg name="mhpmevent17" bitsize="64"/>
534
- <reg name="mhpmevent18" bitsize="64"/>
535
- <reg name="mhpmevent19" bitsize="64"/>
536
- <reg name="mhpmevent20" bitsize="64"/>
537
- <reg name="mhpmevent21" bitsize="64"/>
538
- <reg name="mhpmevent22" bitsize="64"/>
539
- <reg name="mhpmevent23" bitsize="64"/>
540
- <reg name="mhpmevent24" bitsize="64"/>
541
- <reg name="mhpmevent25" bitsize="64"/>
542
- <reg name="mhpmevent26" bitsize="64"/>
543
- <reg name="mhpmevent27" bitsize="64"/>
544
- <reg name="mhpmevent28" bitsize="64"/>
545
- <reg name="mhpmevent29" bitsize="64"/>
546
- <reg name="mhpmevent30" bitsize="64"/>
547
- <reg name="mhpmevent31" bitsize="64"/>
548
- <reg name="tselect" bitsize="64"/>
549
- <reg name="tdata1" bitsize="64"/>
550
- <reg name="tdata2" bitsize="64"/>
551
- <reg name="tdata3" bitsize="64"/>
552
- <reg name="dcsr" bitsize="64"/>
553
- <reg name="dpc" bitsize="64"/>
554
- <reg name="dscratch" bitsize="64"/>
555
- <reg name="hstatus" bitsize="64"/>
556
- <reg name="hedeleg" bitsize="64"/>
557
- <reg name="hideleg" bitsize="64"/>
558
- <reg name="hie" bitsize="64"/>
559
- <reg name="htvec" bitsize="64"/>
560
- <reg name="hscratch" bitsize="64"/>
561
- <reg name="hepc" bitsize="64"/>
562
- <reg name="hcause" bitsize="64"/>
563
- <reg name="hbadaddr" bitsize="64"/>
564
- <reg name="hip" bitsize="64"/>
565
- <reg name="mbase" bitsize="64"/>
566
- <reg name="mbound" bitsize="64"/>
567
- <reg name="mibase" bitsize="64"/>
568
- <reg name="mibound" bitsize="64"/>
569
- <reg name="mdbase" bitsize="64"/>
570
- <reg name="mdbound" bitsize="64"/>
571
- <reg name="mucounteren" bitsize="64"/>
572
- <reg name="mscounteren" bitsize="64"/>
573
- <reg name="mhcounteren" bitsize="64"/>
574
-</feature>
575
--
177
--
576
2.29.2
178
2.28.0
577
179
578
180
diff view generated by jsdifflib
[PULL 12/12] riscv: Pass RISCVHartArrayState by pointer
[PULL 23/30] hw/riscv: Move sifive_clint model to hw/intc
1
We were accidently passing RISCVHartArrayState by value instead of
1
From: Bin Meng <bin.meng@windriver.com>
2
pointer. The type is 824 bytes long so let's correct that and pass it by
2
3
pointer instead.
3
This is an effort to clean up the hw/riscv directory. Ideally it
4
4
should only contain the RISC-V SoC / machine codes plus generic
5
Fixes: Coverity CID 1438099
5
codes. Let's move sifive_clint model to hw/intc directory.
6
Fixes: Coverity CID 1438100
6
7
Fixes: Coverity CID 1438101
7
Signed-off-by: Bin Meng <bin.meng@windriver.com>
8
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
9
Message-Id: <1599129623-68957-6-git-send-email-bmeng.cn@gmail.com>
8
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
10
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
9
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
10
Reviewed-by: Bin Meng <bin.meng@windriver.com>
11
Message-id: f3e04424723e0e222769991896cc82308fd23f76.1610751609.git.alistair.francis@wdc.com
12
---
11
---
13
include/hw/riscv/boot.h | 6 +++---
12
include/hw/{riscv => intc}/sifive_clint.h | 0
14
hw/riscv/boot.c | 10 ++++------
13
hw/{riscv => intc}/sifive_clint.c | 2 +-
15
hw/riscv/sifive_u.c | 10 +++++-----
14
hw/riscv/microchip_pfsoc.c | 2 +-
16
hw/riscv/spike.c | 8 ++++----
15
hw/riscv/sifive_e.c | 2 +-
17
hw/riscv/virt.c | 8 ++++----
16
hw/riscv/sifive_u.c | 2 +-
18
5 files changed, 20 insertions(+), 22 deletions(-)
17
hw/riscv/spike.c | 2 +-
19
18
hw/riscv/virt.c | 2 +-
20
diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h
19
hw/intc/Kconfig | 3 +++
21
index XXXXXXX..XXXXXXX 100644
20
hw/intc/meson.build | 1 +
22
--- a/include/hw/riscv/boot.h
21
hw/riscv/Kconfig | 5 +++++
23
+++ b/include/hw/riscv/boot.h
22
hw/riscv/meson.build | 1 -
24
@@ -XXX,XX +XXX,XX @@
23
11 files changed, 15 insertions(+), 7 deletions(-)
25
#include "hw/loader.h"
24
rename include/hw/{riscv => intc}/sifive_clint.h (100%)
26
#include "hw/riscv/riscv_hart.h"
25
rename hw/{riscv => intc}/sifive_clint.c (99%)
27
26
28
-bool riscv_is_32bit(RISCVHartArrayState harts);
27
diff --git a/include/hw/riscv/sifive_clint.h b/include/hw/intc/sifive_clint.h
29
+bool riscv_is_32bit(RISCVHartArrayState *harts);
28
similarity index 100%
30
29
rename from include/hw/riscv/sifive_clint.h
31
-target_ulong riscv_calc_kernel_start_addr(RISCVHartArrayState harts,
30
rename to include/hw/intc/sifive_clint.h
32
+target_ulong riscv_calc_kernel_start_addr(RISCVHartArrayState *harts,
31
diff --git a/hw/riscv/sifive_clint.c b/hw/intc/sifive_clint.c
33
target_ulong firmware_end_addr);
32
similarity index 99%
34
target_ulong riscv_find_and_load_firmware(MachineState *machine,
33
rename from hw/riscv/sifive_clint.c
35
const char *default_machine_firmware,
34
rename to hw/intc/sifive_clint.c
36
@@ -XXX,XX +XXX,XX @@ target_ulong riscv_load_kernel(const char *kernel_filename,
35
index XXXXXXX..XXXXXXX 100644
37
hwaddr riscv_load_initrd(const char *filename, uint64_t mem_size,
36
--- a/hw/riscv/sifive_clint.c
38
uint64_t kernel_entry, hwaddr *start);
37
+++ b/hw/intc/sifive_clint.c
39
uint32_t riscv_load_fdt(hwaddr dram_start, uint64_t dram_size, void *fdt);
38
@@ -XXX,XX +XXX,XX @@
40
-void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState harts,
39
#include "hw/sysbus.h"
41
+void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState *harts,
40
#include "target/riscv/cpu.h"
42
hwaddr saddr,
41
#include "hw/qdev-properties.h"
43
hwaddr rom_base, hwaddr rom_size,
42
-#include "hw/riscv/sifive_clint.h"
44
uint64_t kernel_entry,
43
+#include "hw/intc/sifive_clint.h"
45
diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
44
#include "qemu/timer.h"
46
index XXXXXXX..XXXXXXX 100644
45
47
--- a/hw/riscv/boot.c
46
static uint64_t cpu_riscv_read_rtc(uint32_t timebase_freq)
48
+++ b/hw/riscv/boot.c
47
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
49
@@ -XXX,XX +XXX,XX @@
48
index XXXXXXX..XXXXXXX 100644
50
49
--- a/hw/riscv/microchip_pfsoc.c
51
#include <libfdt.h>
50
+++ b/hw/riscv/microchip_pfsoc.c
52
51
@@ -XXX,XX +XXX,XX @@
53
-bool riscv_is_32bit(RISCVHartArrayState harts)
52
#include "hw/misc/unimp.h"
54
+bool riscv_is_32bit(RISCVHartArrayState *harts)
53
#include "hw/riscv/boot.h"
55
{
54
#include "hw/riscv/riscv_hart.h"
56
- RISCVCPU hart = harts.harts[0];
55
-#include "hw/riscv/sifive_clint.h"
57
-
56
#include "hw/riscv/sifive_plic.h"
58
- return riscv_cpu_is_32bit(&hart.env);
57
#include "hw/riscv/microchip_pfsoc.h"
59
+ return riscv_cpu_is_32bit(&harts->harts[0].env);
58
+#include "hw/intc/sifive_clint.h"
60
}
59
#include "sysemu/sysemu.h"
61
60
62
-target_ulong riscv_calc_kernel_start_addr(RISCVHartArrayState harts,
61
/*
63
+target_ulong riscv_calc_kernel_start_addr(RISCVHartArrayState *harts,
62
diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
64
target_ulong firmware_end_addr) {
63
index XXXXXXX..XXXXXXX 100644
65
if (riscv_is_32bit(harts)) {
64
--- a/hw/riscv/sifive_e.c
66
return QEMU_ALIGN_UP(firmware_end_addr, 4 * MiB);
65
+++ b/hw/riscv/sifive_e.c
67
@@ -XXX,XX +XXX,XX @@ void riscv_rom_copy_firmware_info(MachineState *machine, hwaddr rom_base,
66
@@ -XXX,XX +XXX,XX @@
68
&address_space_memory);
67
#include "target/riscv/cpu.h"
69
}
68
#include "hw/riscv/riscv_hart.h"
70
69
#include "hw/riscv/sifive_plic.h"
71
-void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState harts,
70
-#include "hw/riscv/sifive_clint.h"
72
+void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState *harts,
71
#include "hw/riscv/sifive_uart.h"
73
hwaddr start_addr,
72
#include "hw/riscv/sifive_e.h"
74
hwaddr rom_base, hwaddr rom_size,
73
#include "hw/riscv/boot.h"
75
uint64_t kernel_entry,
74
+#include "hw/intc/sifive_clint.h"
75
#include "hw/misc/sifive_e_prci.h"
76
#include "chardev/char.h"
77
#include "sysemu/arch_init.h"
76
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
78
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
77
index XXXXXXX..XXXXXXX 100644
79
index XXXXXXX..XXXXXXX 100644
78
--- a/hw/riscv/sifive_u.c
80
--- a/hw/riscv/sifive_u.c
79
+++ b/hw/riscv/sifive_u.c
81
+++ b/hw/riscv/sifive_u.c
80
@@ -XXX,XX +XXX,XX @@ static void sifive_u_machine_init(MachineState *machine)
82
@@ -XXX,XX +XXX,XX @@
81
83
#include "target/riscv/cpu.h"
82
/* create device tree */
84
#include "hw/riscv/riscv_hart.h"
83
create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline,
85
#include "hw/riscv/sifive_plic.h"
84
- riscv_is_32bit(s->soc.u_cpus));
86
-#include "hw/riscv/sifive_clint.h"
85
+ riscv_is_32bit(&s->soc.u_cpus));
87
#include "hw/riscv/sifive_uart.h"
86
88
#include "hw/riscv/sifive_u.h"
87
if (s->start_in_flash) {
89
#include "hw/riscv/boot.h"
88
/*
90
+#include "hw/intc/sifive_clint.h"
89
@@ -XXX,XX +XXX,XX @@ static void sifive_u_machine_init(MachineState *machine)
91
#include "chardev/char.h"
90
break;
92
#include "net/eth.h"
91
}
93
#include "sysemu/arch_init.h"
92
93
- if (riscv_is_32bit(s->soc.u_cpus)) {
94
+ if (riscv_is_32bit(&s->soc.u_cpus)) {
95
firmware_end_addr = riscv_find_and_load_firmware(machine,
96
"opensbi-riscv32-generic-fw_dynamic.bin",
97
start_addr, NULL);
98
@@ -XXX,XX +XXX,XX @@ static void sifive_u_machine_init(MachineState *machine)
99
}
100
101
if (machine->kernel_filename) {
102
- kernel_start_addr = riscv_calc_kernel_start_addr(s->soc.u_cpus,
103
+ kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc.u_cpus,
104
firmware_end_addr);
105
106
kernel_entry = riscv_load_kernel(machine->kernel_filename,
107
@@ -XXX,XX +XXX,XX @@ static void sifive_u_machine_init(MachineState *machine)
108
/* Compute the fdt load address in dram */
109
fdt_load_addr = riscv_load_fdt(memmap[SIFIVE_U_DEV_DRAM].base,
110
machine->ram_size, s->fdt);
111
- if (!riscv_is_32bit(s->soc.u_cpus)) {
112
+ if (!riscv_is_32bit(&s->soc.u_cpus)) {
113
start_addr_hi32 = (uint64_t)start_addr >> 32;
114
}
115
116
@@ -XXX,XX +XXX,XX @@ static void sifive_u_machine_init(MachineState *machine)
117
0x00000000,
118
/* fw_dyn: */
119
};
120
- if (riscv_is_32bit(s->soc.u_cpus)) {
121
+ if (riscv_is_32bit(&s->soc.u_cpus)) {
122
reset_vec[4] = 0x0202a583; /* lw a1, 32(t0) */
123
reset_vec[5] = 0x0182a283; /* lw t0, 24(t0) */
124
} else {
125
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
94
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
126
index XXXXXXX..XXXXXXX 100644
95
index XXXXXXX..XXXXXXX 100644
127
--- a/hw/riscv/spike.c
96
--- a/hw/riscv/spike.c
128
+++ b/hw/riscv/spike.c
97
+++ b/hw/riscv/spike.c
129
@@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine)
98
@@ -XXX,XX +XXX,XX @@
130
99
#include "target/riscv/cpu.h"
131
/* create device tree */
100
#include "hw/riscv/riscv_htif.h"
132
create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline,
101
#include "hw/riscv/riscv_hart.h"
133
- riscv_is_32bit(s->soc[0]));
102
-#include "hw/riscv/sifive_clint.h"
134
+ riscv_is_32bit(&s->soc[0]));
103
#include "hw/riscv/spike.h"
135
104
#include "hw/riscv/boot.h"
136
/* boot rom */
105
#include "hw/riscv/numa.h"
137
memory_region_init_rom(mask_rom, NULL, "riscv.spike.mrom",
106
+#include "hw/intc/sifive_clint.h"
138
@@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine)
107
#include "chardev/char.h"
139
* keeping ELF files here was intentional because BIN files don't work
108
#include "sysemu/arch_init.h"
140
* for the Spike machine as HTIF emulation depends on ELF parsing.
109
#include "sysemu/device_tree.h"
141
*/
142
- if (riscv_is_32bit(s->soc[0])) {
143
+ if (riscv_is_32bit(&s->soc[0])) {
144
firmware_end_addr = riscv_find_and_load_firmware(machine,
145
"opensbi-riscv32-generic-fw_dynamic.elf",
146
memmap[SPIKE_DRAM].base,
147
@@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine)
148
}
149
150
if (machine->kernel_filename) {
151
- kernel_start_addr = riscv_calc_kernel_start_addr(s->soc[0],
152
+ kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc[0],
153
firmware_end_addr);
154
155
kernel_entry = riscv_load_kernel(machine->kernel_filename,
156
@@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine)
157
fdt_load_addr = riscv_load_fdt(memmap[SPIKE_DRAM].base,
158
machine->ram_size, s->fdt);
159
/* load the reset vector */
160
- riscv_setup_rom_reset_vec(machine, s->soc[0], memmap[SPIKE_DRAM].base,
161
+ riscv_setup_rom_reset_vec(machine, &s->soc[0], memmap[SPIKE_DRAM].base,
162
memmap[SPIKE_MROM].base,
163
memmap[SPIKE_MROM].size, kernel_entry,
164
fdt_load_addr, s->fdt);
165
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
110
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
166
index XXXXXXX..XXXXXXX 100644
111
index XXXXXXX..XXXXXXX 100644
167
--- a/hw/riscv/virt.c
112
--- a/hw/riscv/virt.c
168
+++ b/hw/riscv/virt.c
113
+++ b/hw/riscv/virt.c
169
@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
114
@@ -XXX,XX +XXX,XX @@
170
115
#include "target/riscv/cpu.h"
171
/* create device tree */
116
#include "hw/riscv/riscv_hart.h"
172
create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline,
117
#include "hw/riscv/sifive_plic.h"
173
- riscv_is_32bit(s->soc[0]));
118
-#include "hw/riscv/sifive_clint.h"
174
+ riscv_is_32bit(&s->soc[0]));
119
#include "hw/riscv/sifive_test.h"
175
120
#include "hw/riscv/virt.h"
176
/* boot rom */
121
#include "hw/riscv/boot.h"
177
memory_region_init_rom(mask_rom, NULL, "riscv_virt_board.mrom",
122
#include "hw/riscv/numa.h"
178
@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
123
+#include "hw/intc/sifive_clint.h"
179
memory_region_add_subregion(system_memory, memmap[VIRT_MROM].base,
124
#include "chardev/char.h"
180
mask_rom);
125
#include "sysemu/arch_init.h"
181
126
#include "sysemu/device_tree.h"
182
- if (riscv_is_32bit(s->soc[0])) {
127
diff --git a/hw/intc/Kconfig b/hw/intc/Kconfig
183
+ if (riscv_is_32bit(&s->soc[0])) {
128
index XXXXXXX..XXXXXXX 100644
184
firmware_end_addr = riscv_find_and_load_firmware(machine,
129
--- a/hw/intc/Kconfig
185
"opensbi-riscv32-generic-fw_dynamic.bin",
130
+++ b/hw/intc/Kconfig
186
start_addr, NULL);
131
@@ -XXX,XX +XXX,XX @@ config RX_ICU
187
@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
132
188
}
133
config LOONGSON_LIOINTC
189
134
bool
190
if (machine->kernel_filename) {
135
+
191
- kernel_start_addr = riscv_calc_kernel_start_addr(s->soc[0],
136
+config SIFIVE_CLINT
192
+ kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc[0],
137
+ bool
193
firmware_end_addr);
138
diff --git a/hw/intc/meson.build b/hw/intc/meson.build
194
139
index XXXXXXX..XXXXXXX 100644
195
kernel_entry = riscv_load_kernel(machine->kernel_filename,
140
--- a/hw/intc/meson.build
196
@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
141
+++ b/hw/intc/meson.build
197
fdt_load_addr = riscv_load_fdt(memmap[VIRT_DRAM].base,
142
@@ -XXX,XX +XXX,XX @@ specific_ss.add(when: 'CONFIG_RX_ICU', if_true: files('rx_icu.c'))
198
machine->ram_size, s->fdt);
143
specific_ss.add(when: 'CONFIG_S390_FLIC', if_true: files('s390_flic.c'))
199
/* load the reset vector */
144
specific_ss.add(when: 'CONFIG_S390_FLIC_KVM', if_true: files('s390_flic_kvm.c'))
200
- riscv_setup_rom_reset_vec(machine, s->soc[0], start_addr,
145
specific_ss.add(when: 'CONFIG_SH4', if_true: files('sh_intc.c'))
201
+ riscv_setup_rom_reset_vec(machine, &s->soc[0], start_addr,
146
+specific_ss.add(when: 'CONFIG_SIFIVE_CLINT', if_true: files('sifive_clint.c'))
202
virt_memmap[VIRT_MROM].base,
147
specific_ss.add(when: 'CONFIG_XICS', if_true: files('xics.c'))
203
virt_memmap[VIRT_MROM].size, kernel_entry,
148
specific_ss.add(when: 'CONFIG_XICS_KVM', if_true: files('xics_kvm.c'))
204
fdt_load_addr, s->fdt);
149
specific_ss.add(when: 'CONFIG_XICS_SPAPR', if_true: files('xics_spapr.c'))
150
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
151
index XXXXXXX..XXXXXXX 100644
152
--- a/hw/riscv/Kconfig
153
+++ b/hw/riscv/Kconfig
154
@@ -XXX,XX +XXX,XX @@ config SIFIVE_E
155
bool
156
select HART
157
select SIFIVE
158
+ select SIFIVE_CLINT
159
select SIFIVE_GPIO
160
select SIFIVE_E_PRCI
161
select UNIMP
162
@@ -XXX,XX +XXX,XX @@ config SIFIVE_U
163
select CADENCE
164
select HART
165
select SIFIVE
166
+ select SIFIVE_CLINT
167
select SIFIVE_GPIO
168
select SIFIVE_PDMA
169
select SIFIVE_U_OTP
170
@@ -XXX,XX +XXX,XX @@ config SPIKE
171
select HART
172
select HTIF
173
select SIFIVE
174
+ select SIFIVE_CLINT
175
176
config OPENTITAN
177
bool
178
@@ -XXX,XX +XXX,XX @@ config RISCV_VIRT
179
select PCI_EXPRESS_GENERIC_BRIDGE
180
select PFLASH_CFI01
181
select SIFIVE
182
+ select SIFIVE_CLINT
183
184
config MICROCHIP_PFSOC
185
bool
186
select HART
187
select SIFIVE
188
+ select SIFIVE_CLINT
189
select UNIMP
190
select MCHP_PFSOC_MMUART
191
select SIFIVE_PDMA
192
diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
193
index XXXXXXX..XXXXXXX 100644
194
--- a/hw/riscv/meson.build
195
+++ b/hw/riscv/meson.build
196
@@ -XXX,XX +XXX,XX @@ riscv_ss.add(files('numa.c'))
197
riscv_ss.add(when: 'CONFIG_HART', if_true: files('riscv_hart.c'))
198
riscv_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c'))
199
riscv_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c'))
200
-riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_clint.c'))
201
riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_plic.c'))
202
riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_test.c'))
203
riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_uart.c'))
205
--
204
--
206
2.29.2
205
2.28.0
207
206
208
207
diff view generated by jsdifflib
New patch
[PULL 24/30] hw/riscv: Move sifive_plic model to hw/intc
1
From: Bin Meng <bin.meng@windriver.com>
1
2
3
This is an effort to clean up the hw/riscv directory. Ideally it
4
should only contain the RISC-V SoC / machine codes plus generic
5
codes. Let's move sifive_plic model to hw/intc directory.
6
7
Signed-off-by: Bin Meng <bin.meng@windriver.com>
8
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
9
Message-Id: <1599129623-68957-7-git-send-email-bmeng.cn@gmail.com>
10
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
11
---
12
{include/hw/riscv => hw/intc}/sifive_plic.h | 0
13
hw/{riscv => intc}/sifive_plic.c | 2 +-
14
hw/riscv/microchip_pfsoc.c | 2 +-
15
hw/riscv/sifive_e.c | 2 +-
16
hw/riscv/sifive_u.c | 2 +-
17
hw/riscv/virt.c | 2 +-
18
hw/intc/Kconfig | 3 +++
19
hw/intc/meson.build | 1 +
20
hw/riscv/Kconfig | 5 +++++
21
hw/riscv/meson.build | 1 -
22
10 files changed, 14 insertions(+), 6 deletions(-)
23
rename {include/hw/riscv => hw/intc}/sifive_plic.h (100%)
24
rename hw/{riscv => intc}/sifive_plic.c (99%)
25
26
diff --git a/include/hw/riscv/sifive_plic.h b/hw/intc/sifive_plic.h
27
similarity index 100%
28
rename from include/hw/riscv/sifive_plic.h
29
rename to hw/intc/sifive_plic.h
30
diff --git a/hw/riscv/sifive_plic.c b/hw/intc/sifive_plic.c
31
similarity index 99%
32
rename from hw/riscv/sifive_plic.c
33
rename to hw/intc/sifive_plic.c
34
index XXXXXXX..XXXXXXX 100644
35
--- a/hw/riscv/sifive_plic.c
36
+++ b/hw/intc/sifive_plic.c
37
@@ -XXX,XX +XXX,XX @@
38
#include "hw/pci/msi.h"
39
#include "hw/boards.h"
40
#include "hw/qdev-properties.h"
41
+#include "hw/intc/sifive_plic.h"
42
#include "target/riscv/cpu.h"
43
#include "sysemu/sysemu.h"
44
-#include "hw/riscv/sifive_plic.h"
45
46
#define RISCV_DEBUG_PLIC 0
47
48
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
49
index XXXXXXX..XXXXXXX 100644
50
--- a/hw/riscv/microchip_pfsoc.c
51
+++ b/hw/riscv/microchip_pfsoc.c
52
@@ -XXX,XX +XXX,XX @@
53
#include "hw/misc/unimp.h"
54
#include "hw/riscv/boot.h"
55
#include "hw/riscv/riscv_hart.h"
56
-#include "hw/riscv/sifive_plic.h"
57
#include "hw/riscv/microchip_pfsoc.h"
58
#include "hw/intc/sifive_clint.h"
59
+#include "hw/intc/sifive_plic.h"
60
#include "sysemu/sysemu.h"
61
62
/*
63
diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
64
index XXXXXXX..XXXXXXX 100644
65
--- a/hw/riscv/sifive_e.c
66
+++ b/hw/riscv/sifive_e.c
67
@@ -XXX,XX +XXX,XX @@
68
#include "hw/misc/unimp.h"
69
#include "target/riscv/cpu.h"
70
#include "hw/riscv/riscv_hart.h"
71
-#include "hw/riscv/sifive_plic.h"
72
#include "hw/riscv/sifive_uart.h"
73
#include "hw/riscv/sifive_e.h"
74
#include "hw/riscv/boot.h"
75
#include "hw/intc/sifive_clint.h"
76
+#include "hw/intc/sifive_plic.h"
77
#include "hw/misc/sifive_e_prci.h"
78
#include "chardev/char.h"
79
#include "sysemu/arch_init.h"
80
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
81
index XXXXXXX..XXXXXXX 100644
82
--- a/hw/riscv/sifive_u.c
83
+++ b/hw/riscv/sifive_u.c
84
@@ -XXX,XX +XXX,XX @@
85
#include "hw/misc/unimp.h"
86
#include "target/riscv/cpu.h"
87
#include "hw/riscv/riscv_hart.h"
88
-#include "hw/riscv/sifive_plic.h"
89
#include "hw/riscv/sifive_uart.h"
90
#include "hw/riscv/sifive_u.h"
91
#include "hw/riscv/boot.h"
92
#include "hw/intc/sifive_clint.h"
93
+#include "hw/intc/sifive_plic.h"
94
#include "chardev/char.h"
95
#include "net/eth.h"
96
#include "sysemu/arch_init.h"
97
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
98
index XXXXXXX..XXXXXXX 100644
99
--- a/hw/riscv/virt.c
100
+++ b/hw/riscv/virt.c
101
@@ -XXX,XX +XXX,XX @@
102
#include "hw/char/serial.h"
103
#include "target/riscv/cpu.h"
104
#include "hw/riscv/riscv_hart.h"
105
-#include "hw/riscv/sifive_plic.h"
106
#include "hw/riscv/sifive_test.h"
107
#include "hw/riscv/virt.h"
108
#include "hw/riscv/boot.h"
109
#include "hw/riscv/numa.h"
110
#include "hw/intc/sifive_clint.h"
111
+#include "hw/intc/sifive_plic.h"
112
#include "chardev/char.h"
113
#include "sysemu/arch_init.h"
114
#include "sysemu/device_tree.h"
115
diff --git a/hw/intc/Kconfig b/hw/intc/Kconfig
116
index XXXXXXX..XXXXXXX 100644
117
--- a/hw/intc/Kconfig
118
+++ b/hw/intc/Kconfig
119
@@ -XXX,XX +XXX,XX @@ config LOONGSON_LIOINTC
120
121
config SIFIVE_CLINT
122
bool
123
+
124
+config SIFIVE_PLIC
125
+ bool
126
diff --git a/hw/intc/meson.build b/hw/intc/meson.build
127
index XXXXXXX..XXXXXXX 100644
128
--- a/hw/intc/meson.build
129
+++ b/hw/intc/meson.build
130
@@ -XXX,XX +XXX,XX @@ specific_ss.add(when: 'CONFIG_S390_FLIC', if_true: files('s390_flic.c'))
131
specific_ss.add(when: 'CONFIG_S390_FLIC_KVM', if_true: files('s390_flic_kvm.c'))
132
specific_ss.add(when: 'CONFIG_SH4', if_true: files('sh_intc.c'))
133
specific_ss.add(when: 'CONFIG_SIFIVE_CLINT', if_true: files('sifive_clint.c'))
134
+specific_ss.add(when: 'CONFIG_SIFIVE_PLIC', if_true: files('sifive_plic.c'))
135
specific_ss.add(when: 'CONFIG_XICS', if_true: files('xics.c'))
136
specific_ss.add(when: 'CONFIG_XICS_KVM', if_true: files('xics_kvm.c'))
137
specific_ss.add(when: 'CONFIG_XICS_SPAPR', if_true: files('xics_spapr.c'))
138
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
139
index XXXXXXX..XXXXXXX 100644
140
--- a/hw/riscv/Kconfig
141
+++ b/hw/riscv/Kconfig
142
@@ -XXX,XX +XXX,XX @@ config SIFIVE_E
143
select SIFIVE
144
select SIFIVE_CLINT
145
select SIFIVE_GPIO
146
+ select SIFIVE_PLIC
147
select SIFIVE_E_PRCI
148
select UNIMP
149
150
@@ -XXX,XX +XXX,XX @@ config SIFIVE_U
151
select SIFIVE_CLINT
152
select SIFIVE_GPIO
153
select SIFIVE_PDMA
154
+ select SIFIVE_PLIC
155
select SIFIVE_U_OTP
156
select SIFIVE_U_PRCI
157
select UNIMP
158
@@ -XXX,XX +XXX,XX @@ config SPIKE
159
select HTIF
160
select SIFIVE
161
select SIFIVE_CLINT
162
+ select SIFIVE_PLIC
163
164
config OPENTITAN
165
bool
166
@@ -XXX,XX +XXX,XX @@ config RISCV_VIRT
167
select PFLASH_CFI01
168
select SIFIVE
169
select SIFIVE_CLINT
170
+ select SIFIVE_PLIC
171
172
config MICROCHIP_PFSOC
173
bool
174
@@ -XXX,XX +XXX,XX @@ config MICROCHIP_PFSOC
175
select UNIMP
176
select MCHP_PFSOC_MMUART
177
select SIFIVE_PDMA
178
+ select SIFIVE_PLIC
179
select CADENCE_SDHCI
180
diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
181
index XXXXXXX..XXXXXXX 100644
182
--- a/hw/riscv/meson.build
183
+++ b/hw/riscv/meson.build
184
@@ -XXX,XX +XXX,XX @@ riscv_ss.add(files('numa.c'))
185
riscv_ss.add(when: 'CONFIG_HART', if_true: files('riscv_hart.c'))
186
riscv_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c'))
187
riscv_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c'))
188
-riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_plic.c'))
189
riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_test.c'))
190
riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_uart.c'))
191
riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c'))
192
--
193
2.28.0
194
195
diff view generated by jsdifflib
New patch
[PULL 25/30] hw/riscv: Move riscv_htif model to hw/char
1
From: Bin Meng <bin.meng@windriver.com>
1
2
3
This is an effort to clean up the hw/riscv directory. Ideally it
4
should only contain the RISC-V SoC / machine codes plus generic
5
codes. Let's move riscv_htif model to hw/char directory.
6
7
Signed-off-by: Bin Meng <bin.meng@windriver.com>
8
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
9
Message-Id: <1599129623-68957-8-git-send-email-bmeng.cn@gmail.com>
10
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
11
---
12
include/hw/{riscv => char}/riscv_htif.h | 0
13
hw/{riscv => char}/riscv_htif.c | 2 +-
14
hw/riscv/spike.c | 2 +-
15
hw/char/Kconfig | 3 +++
16
hw/char/meson.build | 1 +
17
hw/riscv/Kconfig | 3 ---
18
hw/riscv/meson.build | 1 -
19
7 files changed, 6 insertions(+), 6 deletions(-)
20
rename include/hw/{riscv => char}/riscv_htif.h (100%)
21
rename hw/{riscv => char}/riscv_htif.c (99%)
22
23
diff --git a/include/hw/riscv/riscv_htif.h b/include/hw/char/riscv_htif.h
24
similarity index 100%
25
rename from include/hw/riscv/riscv_htif.h
26
rename to include/hw/char/riscv_htif.h
27
diff --git a/hw/riscv/riscv_htif.c b/hw/char/riscv_htif.c
28
similarity index 99%
29
rename from hw/riscv/riscv_htif.c
30
rename to hw/char/riscv_htif.c
31
index XXXXXXX..XXXXXXX 100644
32
--- a/hw/riscv/riscv_htif.c
33
+++ b/hw/char/riscv_htif.c
34
@@ -XXX,XX +XXX,XX @@
35
#include "qapi/error.h"
36
#include "qemu/log.h"
37
#include "hw/sysbus.h"
38
+#include "hw/char/riscv_htif.h"
39
#include "hw/char/serial.h"
40
#include "chardev/char.h"
41
#include "chardev/char-fe.h"
42
-#include "hw/riscv/riscv_htif.h"
43
#include "qemu/timer.h"
44
#include "qemu/error-report.h"
45
46
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
47
index XXXXXXX..XXXXXXX 100644
48
--- a/hw/riscv/spike.c
49
+++ b/hw/riscv/spike.c
50
@@ -XXX,XX +XXX,XX @@
51
#include "hw/loader.h"
52
#include "hw/sysbus.h"
53
#include "target/riscv/cpu.h"
54
-#include "hw/riscv/riscv_htif.h"
55
#include "hw/riscv/riscv_hart.h"
56
#include "hw/riscv/spike.h"
57
#include "hw/riscv/boot.h"
58
#include "hw/riscv/numa.h"
59
+#include "hw/char/riscv_htif.h"
60
#include "hw/intc/sifive_clint.h"
61
#include "chardev/char.h"
62
#include "sysemu/arch_init.h"
63
diff --git a/hw/char/Kconfig b/hw/char/Kconfig
64
index XXXXXXX..XXXXXXX 100644
65
--- a/hw/char/Kconfig
66
+++ b/hw/char/Kconfig
67
@@ -XXX,XX +XXX,XX @@
68
config ESCC
69
bool
70
71
+config HTIF
72
+ bool
73
+
74
config PARALLEL
75
bool
76
default y
77
diff --git a/hw/char/meson.build b/hw/char/meson.build
78
index XXXXXXX..XXXXXXX 100644
79
--- a/hw/char/meson.build
80
+++ b/hw/char/meson.build
81
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_SH4', if_true: files('sh_serial.c'))
82
softmmu_ss.add(when: 'CONFIG_STM32F2XX_USART', if_true: files('stm32f2xx_usart.c'))
83
softmmu_ss.add(when: 'CONFIG_MCHP_PFSOC_MMUART', if_true: files('mchp_pfsoc_mmuart.c'))
84
85
+specific_ss.add(when: 'CONFIG_HTIF', if_true: files('riscv_htif.c'))
86
specific_ss.add(when: 'CONFIG_TERMINAL3270', if_true: files('terminal3270.c'))
87
specific_ss.add(when: 'CONFIG_VIRTIO', if_true: files('virtio-serial-bus.c'))
88
specific_ss.add(when: 'CONFIG_PSERIES', if_true: files('spapr_vty.c'))
89
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
90
index XXXXXXX..XXXXXXX 100644
91
--- a/hw/riscv/Kconfig
92
+++ b/hw/riscv/Kconfig
93
@@ -XXX,XX +XXX,XX @@
94
-config HTIF
95
- bool
96
-
97
config HART
98
bool
99
100
diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
101
index XXXXXXX..XXXXXXX 100644
102
--- a/hw/riscv/meson.build
103
+++ b/hw/riscv/meson.build
104
@@ -XXX,XX +XXX,XX @@ riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_test.c'))
105
riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_uart.c'))
106
riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c'))
107
riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c'))
108
-riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('riscv_htif.c'))
109
riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c'))
110
riscv_ss.add(when: 'CONFIG_MICROCHIP_PFSOC', if_true: files('microchip_pfsoc.c'))
111
112
--
113
2.28.0
114
115
diff view generated by jsdifflib
[PULL 06/12] hw/riscv: sifive_u: Use SIFIVE_U_CPU for mc->default_cpu_type
[PULL 26/30] hw/riscv: Move sifive_uart model to hw/char
1
From: Bin Meng <bin.meng@windriver.com>
1
From: Bin Meng <bin.meng@windriver.com>
2
2
3
SIFIVE_U_CPU is conditionally set to SIFIVE_U34 or SIFIVE_U54, hence
3
This is an effort to clean up the hw/riscv directory. Ideally it
4
there is no need to use #idef to set the mc->default_cpu_type.
4
should only contain the RISC-V SoC / machine codes plus generic
5
codes. Let's move sifive_uart model to hw/char directory.
5
6
6
Signed-off-by: Bin Meng <bin.meng@windriver.com>
7
Signed-off-by: Bin Meng <bin.meng@windriver.com>
7
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
8
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
9
Message-id: 20210109143637.29645-1-bmeng.cn@gmail.com
9
Message-Id: <1599129623-68957-9-git-send-email-bmeng.cn@gmail.com>
10
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
10
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
11
---
11
---
12
hw/riscv/sifive_u.c | 6 +-----
12
include/hw/{riscv => char}/sifive_uart.h | 0
13
1 file changed, 1 insertion(+), 5 deletions(-)
13
hw/{riscv => char}/sifive_uart.c | 2 +-
14
hw/riscv/sifive_e.c | 2 +-
15
hw/riscv/sifive_u.c | 2 +-
16
hw/char/Kconfig | 3 +++
17
hw/char/meson.build | 1 +
18
hw/riscv/Kconfig | 2 ++
19
hw/riscv/meson.build | 1 -
20
8 files changed, 9 insertions(+), 4 deletions(-)
21
rename include/hw/{riscv => char}/sifive_uart.h (100%)
22
rename hw/{riscv => char}/sifive_uart.c (99%)
14
23
24
diff --git a/include/hw/riscv/sifive_uart.h b/include/hw/char/sifive_uart.h
25
similarity index 100%
26
rename from include/hw/riscv/sifive_uart.h
27
rename to include/hw/char/sifive_uart.h
28
diff --git a/hw/riscv/sifive_uart.c b/hw/char/sifive_uart.c
29
similarity index 99%
30
rename from hw/riscv/sifive_uart.c
31
rename to hw/char/sifive_uart.c
32
index XXXXXXX..XXXXXXX 100644
33
--- a/hw/riscv/sifive_uart.c
34
+++ b/hw/char/sifive_uart.c
35
@@ -XXX,XX +XXX,XX @@
36
#include "chardev/char-fe.h"
37
#include "hw/hw.h"
38
#include "hw/irq.h"
39
-#include "hw/riscv/sifive_uart.h"
40
+#include "hw/char/sifive_uart.h"
41
42
/*
43
* Not yet implemented:
44
diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
45
index XXXXXXX..XXXXXXX 100644
46
--- a/hw/riscv/sifive_e.c
47
+++ b/hw/riscv/sifive_e.c
48
@@ -XXX,XX +XXX,XX @@
49
#include "hw/misc/unimp.h"
50
#include "target/riscv/cpu.h"
51
#include "hw/riscv/riscv_hart.h"
52
-#include "hw/riscv/sifive_uart.h"
53
#include "hw/riscv/sifive_e.h"
54
#include "hw/riscv/boot.h"
55
+#include "hw/char/sifive_uart.h"
56
#include "hw/intc/sifive_clint.h"
57
#include "hw/intc/sifive_plic.h"
58
#include "hw/misc/sifive_e_prci.h"
15
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
59
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
16
index XXXXXXX..XXXXXXX 100644
60
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/riscv/sifive_u.c
61
--- a/hw/riscv/sifive_u.c
18
+++ b/hw/riscv/sifive_u.c
62
+++ b/hw/riscv/sifive_u.c
19
@@ -XXX,XX +XXX,XX @@ static void sifive_u_machine_class_init(ObjectClass *oc, void *data)
63
@@ -XXX,XX +XXX,XX @@
20
mc->init = sifive_u_machine_init;
64
#include "hw/misc/unimp.h"
21
mc->max_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + SIFIVE_U_COMPUTE_CPU_COUNT;
65
#include "target/riscv/cpu.h"
22
mc->min_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + 1;
66
#include "hw/riscv/riscv_hart.h"
23
-#if defined(TARGET_RISCV32)
67
-#include "hw/riscv/sifive_uart.h"
24
- mc->default_cpu_type = TYPE_RISCV_CPU_SIFIVE_U34;
68
#include "hw/riscv/sifive_u.h"
25
-#elif defined(TARGET_RISCV64)
69
#include "hw/riscv/boot.h"
26
- mc->default_cpu_type = TYPE_RISCV_CPU_SIFIVE_U54;
70
+#include "hw/char/sifive_uart.h"
27
-#endif
71
#include "hw/intc/sifive_clint.h"
28
+ mc->default_cpu_type = SIFIVE_U_CPU;
72
#include "hw/intc/sifive_plic.h"
29
mc->default_cpus = mc->min_cpus;
73
#include "chardev/char.h"
30
74
diff --git a/hw/char/Kconfig b/hw/char/Kconfig
31
object_class_property_add_bool(oc, "start-in-flash",
75
index XXXXXXX..XXXXXXX 100644
76
--- a/hw/char/Kconfig
77
+++ b/hw/char/Kconfig
78
@@ -XXX,XX +XXX,XX @@ config AVR_USART
79
80
config MCHP_PFSOC_MMUART
81
bool
82
+
83
+config SIFIVE_UART
84
+ bool
85
diff --git a/hw/char/meson.build b/hw/char/meson.build
86
index XXXXXXX..XXXXXXX 100644
87
--- a/hw/char/meson.build
88
+++ b/hw/char/meson.build
89
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_EXYNOS4', if_true: files('exynos4210_uart.c'))
90
softmmu_ss.add(when: 'CONFIG_OMAP', if_true: files('omap_uart.c'))
91
softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_aux.c'))
92
softmmu_ss.add(when: 'CONFIG_RENESAS_SCI', if_true: files('renesas_sci.c'))
93
+softmmu_ss.add(when: 'CONFIG_SIFIVE_UART', if_true: files('sifive_uart.c'))
94
softmmu_ss.add(when: 'CONFIG_SH4', if_true: files('sh_serial.c'))
95
softmmu_ss.add(when: 'CONFIG_STM32F2XX_USART', if_true: files('stm32f2xx_usart.c'))
96
softmmu_ss.add(when: 'CONFIG_MCHP_PFSOC_MMUART', if_true: files('mchp_pfsoc_mmuart.c'))
97
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
98
index XXXXXXX..XXXXXXX 100644
99
--- a/hw/riscv/Kconfig
100
+++ b/hw/riscv/Kconfig
101
@@ -XXX,XX +XXX,XX @@ config SIFIVE_E
102
select SIFIVE_CLINT
103
select SIFIVE_GPIO
104
select SIFIVE_PLIC
105
+ select SIFIVE_UART
106
select SIFIVE_E_PRCI
107
select UNIMP
108
109
@@ -XXX,XX +XXX,XX @@ config SIFIVE_U
110
select SIFIVE_GPIO
111
select SIFIVE_PDMA
112
select SIFIVE_PLIC
113
+ select SIFIVE_UART
114
select SIFIVE_U_OTP
115
select SIFIVE_U_PRCI
116
select UNIMP
117
diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
118
index XXXXXXX..XXXXXXX 100644
119
--- a/hw/riscv/meson.build
120
+++ b/hw/riscv/meson.build
121
@@ -XXX,XX +XXX,XX @@ riscv_ss.add(when: 'CONFIG_HART', if_true: files('riscv_hart.c'))
122
riscv_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c'))
123
riscv_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c'))
124
riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_test.c'))
125
-riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_uart.c'))
126
riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c'))
127
riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c'))
128
riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c'))
32
--
129
--
33
2.29.2
130
2.28.0
34
131
35
132
diff view generated by jsdifflib
New patch
[PULL 27/30] hw/riscv: Move sifive_test model to hw/misc
1
From: Bin Meng <bin.meng@windriver.com>
1
2
3
This is an effort to clean up the hw/riscv directory. Ideally it
4
should only contain the RISC-V SoC / machine codes plus generic
5
codes. Let's move sifive_test model to hw/misc directory.
6
7
Signed-off-by: Bin Meng <bin.meng@windriver.com>
8
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
9
Message-Id: <1599129623-68957-10-git-send-email-bmeng.cn@gmail.com>
10
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
11
---
12
include/hw/{riscv => misc}/sifive_test.h | 0
13
hw/{riscv => misc}/sifive_test.c | 2 +-
14
hw/riscv/virt.c | 2 +-
15
hw/misc/Kconfig | 3 +++
16
hw/misc/meson.build | 1 +
17
hw/riscv/Kconfig | 1 +
18
hw/riscv/meson.build | 1 -
19
7 files changed, 7 insertions(+), 3 deletions(-)
20
rename include/hw/{riscv => misc}/sifive_test.h (100%)
21
rename hw/{riscv => misc}/sifive_test.c (98%)
22
23
diff --git a/include/hw/riscv/sifive_test.h b/include/hw/misc/sifive_test.h
24
similarity index 100%
25
rename from include/hw/riscv/sifive_test.h
26
rename to include/hw/misc/sifive_test.h
27
diff --git a/hw/riscv/sifive_test.c b/hw/misc/sifive_test.c
28
similarity index 98%
29
rename from hw/riscv/sifive_test.c
30
rename to hw/misc/sifive_test.c
31
index XXXXXXX..XXXXXXX 100644
32
--- a/hw/riscv/sifive_test.c
33
+++ b/hw/misc/sifive_test.c
34
@@ -XXX,XX +XXX,XX @@
35
#include "qemu/module.h"
36
#include "sysemu/runstate.h"
37
#include "hw/hw.h"
38
-#include "hw/riscv/sifive_test.h"
39
+#include "hw/misc/sifive_test.h"
40
41
static uint64_t sifive_test_read(void *opaque, hwaddr addr, unsigned int size)
42
{
43
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
44
index XXXXXXX..XXXXXXX 100644
45
--- a/hw/riscv/virt.c
46
+++ b/hw/riscv/virt.c
47
@@ -XXX,XX +XXX,XX @@
48
#include "hw/char/serial.h"
49
#include "target/riscv/cpu.h"
50
#include "hw/riscv/riscv_hart.h"
51
-#include "hw/riscv/sifive_test.h"
52
#include "hw/riscv/virt.h"
53
#include "hw/riscv/boot.h"
54
#include "hw/riscv/numa.h"
55
#include "hw/intc/sifive_clint.h"
56
#include "hw/intc/sifive_plic.h"
57
+#include "hw/misc/sifive_test.h"
58
#include "chardev/char.h"
59
#include "sysemu/arch_init.h"
60
#include "sysemu/device_tree.h"
61
diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig
62
index XXXXXXX..XXXXXXX 100644
63
--- a/hw/misc/Kconfig
64
+++ b/hw/misc/Kconfig
65
@@ -XXX,XX +XXX,XX @@ config MAC_VIA
66
config AVR_POWER
67
bool
68
69
+config SIFIVE_TEST
70
+ bool
71
+
72
config SIFIVE_E_PRCI
73
bool
74
75
diff --git a/hw/misc/meson.build b/hw/misc/meson.build
76
index XXXXXXX..XXXXXXX 100644
77
--- a/hw/misc/meson.build
78
+++ b/hw/misc/meson.build
79
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_ARM11SCU', if_true: files('arm11scu.c'))
80
softmmu_ss.add(when: 'CONFIG_MOS6522', if_true: files('mos6522.c'))
81
82
# RISC-V devices
83
+softmmu_ss.add(when: 'CONFIG_SIFIVE_TEST', if_true: files('sifive_test.c'))
84
softmmu_ss.add(when: 'CONFIG_SIFIVE_E_PRCI', if_true: files('sifive_e_prci.c'))
85
softmmu_ss.add(when: 'CONFIG_SIFIVE_U_OTP', if_true: files('sifive_u_otp.c'))
86
softmmu_ss.add(when: 'CONFIG_SIFIVE_U_PRCI', if_true: files('sifive_u_prci.c'))
87
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
88
index XXXXXXX..XXXXXXX 100644
89
--- a/hw/riscv/Kconfig
90
+++ b/hw/riscv/Kconfig
91
@@ -XXX,XX +XXX,XX @@ config RISCV_VIRT
92
select SIFIVE
93
select SIFIVE_CLINT
94
select SIFIVE_PLIC
95
+ select SIFIVE_TEST
96
97
config MICROCHIP_PFSOC
98
bool
99
diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
100
index XXXXXXX..XXXXXXX 100644
101
--- a/hw/riscv/meson.build
102
+++ b/hw/riscv/meson.build
103
@@ -XXX,XX +XXX,XX @@ riscv_ss.add(files('numa.c'))
104
riscv_ss.add(when: 'CONFIG_HART', if_true: files('riscv_hart.c'))
105
riscv_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c'))
106
riscv_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c'))
107
-riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_test.c'))
108
riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c'))
109
riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c'))
110
riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c'))
111
--
112
2.28.0
113
114
diff view generated by jsdifflib
New patch
[PULL 28/30] hw/riscv: Always build riscv_hart.c
1
From: Bin Meng <bin.meng@windriver.com>
1
2
3
Every RISC-V machine needs riscv_hart hence there is no need to
4
have a dedicated Kconfig option for it. Drop the Kconfig option
5
and always build riscv_hart.c.
6
7
Signed-off-by: Bin Meng <bin.meng@windriver.com>
8
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
9
Message-Id: <1599129623-68957-11-git-send-email-bmeng.cn@gmail.com>
10
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
11
---
12
hw/riscv/Kconfig | 9 ---------
13
hw/riscv/meson.build | 2 +-
14
2 files changed, 1 insertion(+), 10 deletions(-)
15
16
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
17
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/riscv/Kconfig
19
+++ b/hw/riscv/Kconfig
20
@@ -XXX,XX +XXX,XX @@
21
-config HART
22
- bool
23
-
24
config IBEX
25
bool
26
27
@@ -XXX,XX +XXX,XX @@ config SIFIVE
28
29
config SIFIVE_E
30
bool
31
- select HART
32
select SIFIVE
33
select SIFIVE_CLINT
34
select SIFIVE_GPIO
35
@@ -XXX,XX +XXX,XX @@ config SIFIVE_E
36
config SIFIVE_U
37
bool
38
select CADENCE
39
- select HART
40
select SIFIVE
41
select SIFIVE_CLINT
42
select SIFIVE_GPIO
43
@@ -XXX,XX +XXX,XX @@ config SIFIVE_U
44
45
config SPIKE
46
bool
47
- select HART
48
select HTIF
49
select SIFIVE
50
select SIFIVE_CLINT
51
@@ -XXX,XX +XXX,XX @@ config SPIKE
52
config OPENTITAN
53
bool
54
select IBEX
55
- select HART
56
select UNIMP
57
58
config RISCV_VIRT
59
@@ -XXX,XX +XXX,XX @@ config RISCV_VIRT
60
imply PCI_DEVICES
61
imply TEST_DEVICES
62
select PCI
63
- select HART
64
select SERIAL
65
select GOLDFISH_RTC
66
select VIRTIO_MMIO
67
@@ -XXX,XX +XXX,XX @@ config RISCV_VIRT
68
69
config MICROCHIP_PFSOC
70
bool
71
- select HART
72
select SIFIVE
73
select SIFIVE_CLINT
74
select UNIMP
75
diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
76
index XXXXXXX..XXXXXXX 100644
77
--- a/hw/riscv/meson.build
78
+++ b/hw/riscv/meson.build
79
@@ -XXX,XX +XXX,XX @@
80
riscv_ss = ss.source_set()
81
riscv_ss.add(files('boot.c'), fdt)
82
riscv_ss.add(files('numa.c'))
83
-riscv_ss.add(when: 'CONFIG_HART', if_true: files('riscv_hart.c'))
84
+riscv_ss.add(files('riscv_hart.c'))
85
riscv_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c'))
86
riscv_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c'))
87
riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c'))
88
--
89
2.28.0
90
91
diff view generated by jsdifflib
New patch
[PULL 29/30] hw/riscv: Drop CONFIG_SIFIVE
1
From: Bin Meng <bin.meng@windriver.com>
1
2
3
The name SIFIVE is too vague to convey the required component of
4
MSI_NONBROKEN. Let's drop the option, and select MSI_NONBROKEN in
5
each machine instead.
6
7
Signed-off-by: Bin Meng <bin.meng@windriver.com>
8
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
9
Message-Id: <1599129623-68957-12-git-send-email-bmeng.cn@gmail.com>
10
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
11
---
12
hw/riscv/Kconfig | 14 +++++---------
13
1 file changed, 5 insertions(+), 9 deletions(-)
14
15
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
16
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/riscv/Kconfig
18
+++ b/hw/riscv/Kconfig
19
@@ -XXX,XX +XXX,XX @@
20
config IBEX
21
bool
22
23
-config SIFIVE
24
- bool
25
- select MSI_NONBROKEN
26
-
27
config SIFIVE_E
28
bool
29
- select SIFIVE
30
+ select MSI_NONBROKEN
31
select SIFIVE_CLINT
32
select SIFIVE_GPIO
33
select SIFIVE_PLIC
34
@@ -XXX,XX +XXX,XX @@ config SIFIVE_E
35
config SIFIVE_U
36
bool
37
select CADENCE
38
- select SIFIVE
39
+ select MSI_NONBROKEN
40
select SIFIVE_CLINT
41
select SIFIVE_GPIO
42
select SIFIVE_PDMA
43
@@ -XXX,XX +XXX,XX @@ config SIFIVE_U
44
config SPIKE
45
bool
46
select HTIF
47
- select SIFIVE
48
+ select MSI_NONBROKEN
49
select SIFIVE_CLINT
50
select SIFIVE_PLIC
51
52
@@ -XXX,XX +XXX,XX @@ config RISCV_VIRT
53
bool
54
imply PCI_DEVICES
55
imply TEST_DEVICES
56
+ select MSI_NONBROKEN
57
select PCI
58
select SERIAL
59
select GOLDFISH_RTC
60
select VIRTIO_MMIO
61
select PCI_EXPRESS_GENERIC_BRIDGE
62
select PFLASH_CFI01
63
- select SIFIVE
64
select SIFIVE_CLINT
65
select SIFIVE_PLIC
66
select SIFIVE_TEST
67
68
config MICROCHIP_PFSOC
69
bool
70
- select SIFIVE
71
+ select MSI_NONBROKEN
72
select SIFIVE_CLINT
73
select UNIMP
74
select MCHP_PFSOC_MMUART
75
--
76
2.28.0
77
78
diff view generated by jsdifflib
[PULL 04/12] RISC-V: Place DTB at 3GB boundary instead of 4GB
[PULL 30/30] hw/riscv: Sort the Kconfig options in alphabetical order
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From: Atish Patra <atish.patra@wdc.com>
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From: Bin Meng <bin.meng@windriver.com>
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2
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Currently, we place the DTB at 2MB from 4GB or end of DRAM which ever is
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At present the Kconfig file is in disorder. Let's sort the options.
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lesser. However, Linux kernel can address only 1GB of memory for RV32.
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Thus, it can not map anything beyond 3GB (assuming 2GB is the starting address).
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As a result, it can not process DT and panic if opensbi dynamic firmware
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is used. While at it, place the DTB further away to avoid in memory placement
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issues in future.
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4
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Fix this by placing the DTB at 16MB from 3GB or end of DRAM whichever is lower.
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Signed-off-by: Bin Meng <bin.meng@windriver.com>
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Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
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Fixes: 66b1205bc5ab ("RISC-V: Copy the fdt in dram instead of ROM")
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Message-Id: <1599129623-68957-13-git-send-email-bmeng.cn@gmail.com>
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Reviewed-by: Bin Meng <bin.meng@windriver.com>
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Tested-by: Bin Meng <bin.meng@windriver.com>
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Signed-off-by: Atish Patra <atish.patra@wdc.com>
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Message-id: 20210107091127.3407870-1-atish.patra@wdc.com
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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---
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---
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hw/riscv/boot.c | 8 ++++----
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hw/riscv/Kconfig | 58 ++++++++++++++++++++++++------------------------
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1 file changed, 4 insertions(+), 4 deletions(-)
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1 file changed, 29 insertions(+), 29 deletions(-)
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12
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diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
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diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
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index XXXXXXX..XXXXXXX 100644
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index XXXXXXX..XXXXXXX 100644
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--- a/hw/riscv/boot.c
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--- a/hw/riscv/Kconfig
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+++ b/hw/riscv/boot.c
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+++ b/hw/riscv/Kconfig
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@@ -XXX,XX +XXX,XX @@ uint32_t riscv_load_fdt(hwaddr dram_base, uint64_t mem_size, void *fdt)
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@@ -XXX,XX +XXX,XX @@
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/*
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config IBEX
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* We should put fdt as far as possible to avoid kernel/initrd overwriting
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bool
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* its content. But it should be addressable by 32 bit system as well.
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- * Thus, put it at an aligned address that less than fdt size from end of
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-config SIFIVE_E
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- * dram or 4GB whichever is lesser.
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- bool
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+ * Thus, put it at an 16MB aligned address that less than fdt size from the
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- select MSI_NONBROKEN
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+ * end of dram or 3GB whichever is lesser.
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- select SIFIVE_CLINT
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*/
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- select SIFIVE_GPIO
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- temp = MIN(dram_end, 4096 * MiB);
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- select SIFIVE_PLIC
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- fdt_addr = QEMU_ALIGN_DOWN(temp - fdtsize, 2 * MiB);
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- select SIFIVE_UART
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+ temp = MIN(dram_end, 3072 * MiB);
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- select SIFIVE_E_PRCI
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+ fdt_addr = QEMU_ALIGN_DOWN(temp - fdtsize, 16 * MiB);
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- select UNIMP
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-
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fdt_pack(fdt);
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-config SIFIVE_U
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/* copy in the device tree */
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+config MICROCHIP_PFSOC
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bool
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- select CADENCE
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+ select CADENCE_SDHCI
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+ select MCHP_PFSOC_MMUART
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select MSI_NONBROKEN
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select SIFIVE_CLINT
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- select SIFIVE_GPIO
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select SIFIVE_PDMA
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select SIFIVE_PLIC
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- select SIFIVE_UART
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- select SIFIVE_U_OTP
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- select SIFIVE_U_PRCI
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select UNIMP
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-config SPIKE
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- bool
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- select HTIF
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- select MSI_NONBROKEN
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- select SIFIVE_CLINT
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- select SIFIVE_PLIC
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-
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config OPENTITAN
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bool
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select IBEX
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@@ -XXX,XX +XXX,XX @@ config RISCV_VIRT
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bool
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imply PCI_DEVICES
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imply TEST_DEVICES
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+ select GOLDFISH_RTC
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select MSI_NONBROKEN
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select PCI
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- select SERIAL
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- select GOLDFISH_RTC
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- select VIRTIO_MMIO
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select PCI_EXPRESS_GENERIC_BRIDGE
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select PFLASH_CFI01
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+ select SERIAL
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select SIFIVE_CLINT
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select SIFIVE_PLIC
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select SIFIVE_TEST
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+ select VIRTIO_MMIO
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-config MICROCHIP_PFSOC
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+config SIFIVE_E
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bool
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select MSI_NONBROKEN
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select SIFIVE_CLINT
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+ select SIFIVE_GPIO
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+ select SIFIVE_PLIC
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+ select SIFIVE_UART
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+ select SIFIVE_E_PRCI
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select UNIMP
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- select MCHP_PFSOC_MMUART
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+
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+config SIFIVE_U
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+ bool
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+ select CADENCE
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+ select MSI_NONBROKEN
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+ select SIFIVE_CLINT
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+ select SIFIVE_GPIO
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select SIFIVE_PDMA
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select SIFIVE_PLIC
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- select CADENCE_SDHCI
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+ select SIFIVE_UART
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+ select SIFIVE_U_OTP
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+ select SIFIVE_U_PRCI
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+ select UNIMP
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+
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+config SPIKE
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+ bool
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+ select HTIF
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+ select MSI_NONBROKEN
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+ select SIFIVE_CLINT
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+ select SIFIVE_PLIC
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--
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--
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2.29.2
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2.28.0
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109
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