1 | The following changes since commit 45240eed4f064576d589ea60ebadf3c11d7ab891: | 1 | The following changes since commit aa3a285b5bc56a4208b3b57d4a55291e9c260107: |
---|---|---|---|
2 | 2 | ||
3 | Merge remote-tracking branch 'remotes/armbru/tags/pull-yank-2021-01-13' into staging (2021-01-13 14:19:24 +0000) | 3 | Merge tag 'mem-2024-12-21' of https://github.com/davidhildenbrand/qemu into staging (2024-12-22 14:33:27 -0500) |
4 | 4 | ||
5 | are available in the Git repository at: | 5 | are available in the Git repository at: |
6 | 6 | ||
7 | https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20210113 | 7 | https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20241224 |
8 | 8 | ||
9 | for you to fetch changes up to 4cacecaaa2bbf8af0967bd3eee43297fada475a9: | 9 | for you to fetch changes up to e4a8e093dc74be049f4829831dce76e5edab0003: |
10 | 10 | ||
11 | decodetree: Open files with encoding='utf-8' (2021-01-13 08:39:08 -1000) | 11 | accel/tcg: Move gen_intermediate_code to TCGCPUOps.translate_core (2024-12-24 08:32:15 -0800) |
12 | 12 | ||
13 | ---------------------------------------------------------------- | 13 | ---------------------------------------------------------------- |
14 | Improvements to tcg constant handling. | 14 | tcg/optimize: Remove in-flight mask data from OptContext |
15 | Force utf8 for decodetree. | 15 | fpu: Add float*_muladd_scalbn |
16 | fpu: Remove float_muladd_halve_result | ||
17 | fpu: Add float_round_nearest_even_max | ||
18 | fpu: Add float_muladd_suppress_add_product_zero | ||
19 | target/hexagon: Use float32_muladd | ||
20 | accel/tcg: Move gen_intermediate_code to TCGCPUOps.translate_core | ||
16 | 21 | ||
17 | ---------------------------------------------------------------- | 22 | ---------------------------------------------------------------- |
18 | Philippe Mathieu-Daudé (1): | 23 | Ilya Leoshkevich (1): |
19 | decodetree: Open files with encoding='utf-8' | 24 | tests/tcg: Do not use inttypes.h in multiarch/system/memory.c |
20 | 25 | ||
21 | Richard Henderson (23): | 26 | Pierrick Bouvier (1): |
22 | tcg: Use tcg_out_dupi_vec from temp_load | 27 | plugins: optimize cpu_index code generation |
23 | tcg: Increase tcg_out_dupi_vec immediate to int64_t | ||
24 | tcg: Consolidate 3 bits into enum TCGTempKind | ||
25 | tcg: Add temp_readonly | ||
26 | tcg: Expand TCGTemp.val to 64-bits | ||
27 | tcg: Rename struct tcg_temp_info to TempOptInfo | ||
28 | tcg: Expand TempOptInfo to 64-bits | ||
29 | tcg: Introduce TYPE_CONST temporaries | ||
30 | tcg/optimize: Improve find_better_copy | ||
31 | tcg/optimize: Adjust TempOptInfo allocation | ||
32 | tcg/optimize: Use tcg_constant_internal with constant folding | ||
33 | tcg: Convert tcg_gen_dupi_vec to TCG_CONST | ||
34 | tcg: Use tcg_constant_i32 with icount expander | ||
35 | tcg: Use tcg_constant_{i32,i64} with tcg int expanders | ||
36 | tcg: Use tcg_constant_{i32,i64} with tcg plugins | ||
37 | tcg: Use tcg_constant_{i32,i64,vec} with gvec expanders | ||
38 | tcg/tci: Add special tci_movi_{i32,i64} opcodes | ||
39 | tcg: Remove movi and dupi opcodes | ||
40 | tcg: Add tcg_reg_alloc_dup2 | ||
41 | tcg/i386: Use tcg_constant_vec with tcg vec expanders | ||
42 | tcg: Remove tcg_gen_dup{8,16,32,64}i_vec | ||
43 | tcg/ppc: Use tcg_constant_vec with tcg vec expanders | ||
44 | tcg/aarch64: Use tcg_constant_vec with tcg vec expanders | ||
45 | 28 | ||
46 | include/exec/gen-icount.h | 25 +-- | 29 | Richard Henderson (70): |
47 | include/tcg/tcg-op.h | 17 +- | 30 | tcg/optimize: Split out finish_bb, finish_ebb |
48 | include/tcg/tcg-opc.h | 11 +- | 31 | tcg/optimize: Split out fold_affected_mask |
49 | include/tcg/tcg.h | 50 ++++- | 32 | tcg/optimize: Copy mask writeback to fold_masks |
50 | accel/tcg/plugin-gen.c | 49 ++--- | 33 | tcg/optimize: Split out fold_masks_zs |
51 | tcg/optimize.c | 249 +++++++++++----------- | 34 | tcg/optimize: Augment s_mask from z_mask in fold_masks_zs |
52 | tcg/tcg-op-gvec.c | 129 +++++------- | 35 | tcg/optimize: Change representation of s_mask |
53 | tcg/tcg-op-vec.c | 52 +---- | 36 | tcg/optimize: Use finish_folding in fold_add, fold_add_vec, fold_addsub2 |
54 | tcg/tcg-op.c | 227 ++++++++++---------- | 37 | tcg/optimize: Introduce const value accessors for TempOptInfo |
55 | tcg/tcg.c | 488 +++++++++++++++++++++++++++++++++---------- | 38 | tcg/optimize: Use fold_masks_zs in fold_and |
56 | tcg/tci.c | 4 +- | 39 | tcg/optimize: Use fold_masks_zs in fold_andc |
57 | tcg/aarch64/tcg-target.c.inc | 32 +-- | 40 | tcg/optimize: Use fold_masks_zs in fold_bswap |
58 | tcg/arm/tcg-target.c.inc | 1 - | 41 | tcg/optimize: Use fold_masks_zs in fold_count_zeros |
59 | tcg/i386/tcg-target.c.inc | 112 ++++++---- | 42 | tcg/optimize: Use fold_masks_z in fold_ctpop |
60 | tcg/mips/tcg-target.c.inc | 2 - | 43 | tcg/optimize: Use fold_and and fold_masks_z in fold_deposit |
61 | tcg/ppc/tcg-target.c.inc | 90 ++++---- | 44 | tcg/optimize: Compute sign mask in fold_deposit |
62 | tcg/riscv/tcg-target.c.inc | 2 - | 45 | tcg/optimize: Use finish_folding in fold_divide |
63 | tcg/s390/tcg-target.c.inc | 2 - | 46 | tcg/optimize: Use finish_folding in fold_dup, fold_dup2 |
64 | tcg/sparc/tcg-target.c.inc | 2 - | 47 | tcg/optimize: Use fold_masks_s in fold_eqv |
65 | tcg/tci/tcg-target.c.inc | 6 +- | 48 | tcg/optimize: Use fold_masks_z in fold_extract |
66 | scripts/decodetree.py | 9 +- | 49 | tcg/optimize: Use finish_folding in fold_extract2 |
67 | 21 files changed, 890 insertions(+), 669 deletions(-) | 50 | tcg/optimize: Use fold_masks_zs in fold_exts |
51 | tcg/optimize: Use fold_masks_z in fold_extu | ||
52 | tcg/optimize: Use fold_masks_zs in fold_movcond | ||
53 | tcg/optimize: Use finish_folding in fold_mul* | ||
54 | tcg/optimize: Use fold_masks_s in fold_nand | ||
55 | tcg/optimize: Use fold_masks_z in fold_neg_no_const | ||
56 | tcg/optimize: Use fold_masks_s in fold_nor | ||
57 | tcg/optimize: Use fold_masks_s in fold_not | ||
58 | tcg/optimize: Use fold_masks_zs in fold_or | ||
59 | tcg/optimize: Use fold_masks_zs in fold_orc | ||
60 | tcg/optimize: Use fold_masks_zs in fold_qemu_ld | ||
61 | tcg/optimize: Return true from fold_qemu_st, fold_tcg_st | ||
62 | tcg/optimize: Use finish_folding in fold_remainder | ||
63 | tcg/optimize: Distinguish simplification in fold_setcond_zmask | ||
64 | tcg/optimize: Use fold_masks_z in fold_setcond | ||
65 | tcg/optimize: Use fold_masks_s in fold_negsetcond | ||
66 | tcg/optimize: Use fold_masks_z in fold_setcond2 | ||
67 | tcg/optimize: Use finish_folding in fold_cmp_vec | ||
68 | tcg/optimize: Use finish_folding in fold_cmpsel_vec | ||
69 | tcg/optimize: Use fold_masks_zs in fold_sextract | ||
70 | tcg/optimize: Use fold_masks_zs, fold_masks_s in fold_shift | ||
71 | tcg/optimize: Simplify sign bit test in fold_shift | ||
72 | tcg/optimize: Use finish_folding in fold_sub, fold_sub_vec | ||
73 | tcg/optimize: Use fold_masks_zs in fold_tcg_ld | ||
74 | tcg/optimize: Use finish_folding in fold_tcg_ld_memcopy | ||
75 | tcg/optimize: Use fold_masks_zs in fold_xor | ||
76 | tcg/optimize: Use finish_folding in fold_bitsel_vec | ||
77 | tcg/optimize: Use finish_folding as default in tcg_optimize | ||
78 | tcg/optimize: Remove z_mask, s_mask from OptContext | ||
79 | tcg/optimize: Re-enable sign-mask optimizations | ||
80 | tcg/optimize: Move fold_bitsel_vec into alphabetic sort | ||
81 | tcg/optimize: Move fold_cmp_vec, fold_cmpsel_vec into alphabetic sort | ||
82 | softfloat: Add float{16,32,64}_muladd_scalbn | ||
83 | target/arm: Use float*_muladd_scalbn | ||
84 | target/sparc: Use float*_muladd_scalbn | ||
85 | softfloat: Remove float_muladd_halve_result | ||
86 | softfloat: Add float_round_nearest_even_max | ||
87 | softfloat: Add float_muladd_suppress_add_product_zero | ||
88 | target/hexagon: Use float32_mul in helper_sfmpy | ||
89 | target/hexagon: Use float32_muladd for helper_sffma | ||
90 | target/hexagon: Use float32_muladd for helper_sffms | ||
91 | target/hexagon: Use float32_muladd_scalbn for helper_sffma_sc | ||
92 | target/hexagon: Use float32_muladd for helper_sffm[as]_lib | ||
93 | target/hexagon: Remove internal_fmafx | ||
94 | target/hexagon: Expand GEN_XF_ROUND | ||
95 | target/hexagon: Remove Float | ||
96 | target/hexagon: Remove Double | ||
97 | target/hexagon: Use mulu64 for int128_mul_6464 | ||
98 | target/hexagon: Simplify internal_mpyhh setup | ||
99 | accel/tcg: Move gen_intermediate_code to TCGCPUOps.translate_core | ||
68 | 100 | ||
101 | include/exec/translator.h | 14 - | ||
102 | include/fpu/softfloat-types.h | 2 + | ||
103 | include/fpu/softfloat.h | 14 +- | ||
104 | include/hw/core/tcg-cpu-ops.h | 13 + | ||
105 | target/alpha/cpu.h | 2 + | ||
106 | target/arm/internals.h | 2 + | ||
107 | target/avr/cpu.h | 2 + | ||
108 | target/hexagon/cpu.h | 2 + | ||
109 | target/hexagon/fma_emu.h | 3 - | ||
110 | target/hppa/cpu.h | 2 + | ||
111 | target/i386/tcg/helper-tcg.h | 2 + | ||
112 | target/loongarch/internals.h | 2 + | ||
113 | target/m68k/cpu.h | 2 + | ||
114 | target/microblaze/cpu.h | 2 + | ||
115 | target/mips/tcg/tcg-internal.h | 2 + | ||
116 | target/openrisc/cpu.h | 2 + | ||
117 | target/ppc/cpu.h | 2 + | ||
118 | target/riscv/cpu.h | 3 + | ||
119 | target/rx/cpu.h | 2 + | ||
120 | target/s390x/s390x-internal.h | 2 + | ||
121 | target/sh4/cpu.h | 2 + | ||
122 | target/sparc/cpu.h | 2 + | ||
123 | target/sparc/helper.h | 4 +- | ||
124 | target/tricore/cpu.h | 2 + | ||
125 | target/xtensa/cpu.h | 2 + | ||
126 | accel/tcg/cpu-exec.c | 8 +- | ||
127 | accel/tcg/plugin-gen.c | 9 + | ||
128 | accel/tcg/translate-all.c | 8 +- | ||
129 | fpu/softfloat.c | 63 +-- | ||
130 | target/alpha/cpu.c | 1 + | ||
131 | target/alpha/translate.c | 4 +- | ||
132 | target/arm/cpu.c | 1 + | ||
133 | target/arm/tcg/cpu-v7m.c | 1 + | ||
134 | target/arm/tcg/helper-a64.c | 6 +- | ||
135 | target/arm/tcg/translate.c | 5 +- | ||
136 | target/avr/cpu.c | 1 + | ||
137 | target/avr/translate.c | 6 +- | ||
138 | target/hexagon/cpu.c | 1 + | ||
139 | target/hexagon/fma_emu.c | 496 ++++++--------------- | ||
140 | target/hexagon/op_helper.c | 125 ++---- | ||
141 | target/hexagon/translate.c | 4 +- | ||
142 | target/hppa/cpu.c | 1 + | ||
143 | target/hppa/translate.c | 4 +- | ||
144 | target/i386/tcg/tcg-cpu.c | 1 + | ||
145 | target/i386/tcg/translate.c | 5 +- | ||
146 | target/loongarch/cpu.c | 1 + | ||
147 | target/loongarch/tcg/translate.c | 4 +- | ||
148 | target/m68k/cpu.c | 1 + | ||
149 | target/m68k/translate.c | 4 +- | ||
150 | target/microblaze/cpu.c | 1 + | ||
151 | target/microblaze/translate.c | 4 +- | ||
152 | target/mips/cpu.c | 1 + | ||
153 | target/mips/tcg/translate.c | 4 +- | ||
154 | target/openrisc/cpu.c | 1 + | ||
155 | target/openrisc/translate.c | 4 +- | ||
156 | target/ppc/cpu_init.c | 1 + | ||
157 | target/ppc/translate.c | 4 +- | ||
158 | target/riscv/tcg/tcg-cpu.c | 1 + | ||
159 | target/riscv/translate.c | 4 +- | ||
160 | target/rx/cpu.c | 1 + | ||
161 | target/rx/translate.c | 4 +- | ||
162 | target/s390x/cpu.c | 1 + | ||
163 | target/s390x/tcg/translate.c | 4 +- | ||
164 | target/sh4/cpu.c | 1 + | ||
165 | target/sh4/translate.c | 4 +- | ||
166 | target/sparc/cpu.c | 1 + | ||
167 | target/sparc/fop_helper.c | 8 +- | ||
168 | target/sparc/translate.c | 84 ++-- | ||
169 | target/tricore/cpu.c | 1 + | ||
170 | target/tricore/translate.c | 5 +- | ||
171 | target/xtensa/cpu.c | 1 + | ||
172 | target/xtensa/translate.c | 4 +- | ||
173 | tcg/optimize.c | 857 +++++++++++++++++++----------------- | ||
174 | tests/tcg/multiarch/system/memory.c | 9 +- | ||
175 | fpu/softfloat-parts.c.inc | 16 +- | ||
176 | 75 files changed, 866 insertions(+), 1009 deletions(-) | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Ilya Leoshkevich <iii@linux.ibm.com> | ||
1 | 2 | ||
3 | make check-tcg fails on Fedora with the following error message: | ||
4 | |||
5 | alpha-linux-gnu-gcc [...] qemu/tests/tcg/multiarch/system/memory.c -o memory [...] | ||
6 | qemu/tests/tcg/multiarch/system/memory.c:17:10: fatal error: inttypes.h: No such file or directory | ||
7 | 17 | #include <inttypes.h> | ||
8 | | ^~~~~~~~~~~~ | ||
9 | compilation terminated. | ||
10 | |||
11 | The reason is that Fedora has cross-compilers, but no cross-glibc | ||
12 | headers. Fix by hardcoding the format specifiers and dropping the | ||
13 | include. | ||
14 | |||
15 | An alternative fix would be to introduce a configure check for | ||
16 | inttypes.h. But this would make it impossible to use Fedora | ||
17 | cross-compilers for softmmu tests, which used to work so far. | ||
18 | |||
19 | Fixes: ecbcc9ead2f8 ("tests/tcg: add a system test to check memory instrumentation") | ||
20 | Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> | ||
21 | Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> | ||
22 | Message-ID: <20241010085906.226249-1-iii@linux.ibm.com> | ||
23 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
24 | --- | ||
25 | tests/tcg/multiarch/system/memory.c | 9 ++++----- | ||
26 | 1 file changed, 4 insertions(+), 5 deletions(-) | ||
27 | |||
28 | diff --git a/tests/tcg/multiarch/system/memory.c b/tests/tcg/multiarch/system/memory.c | ||
29 | index XXXXXXX..XXXXXXX 100644 | ||
30 | --- a/tests/tcg/multiarch/system/memory.c | ||
31 | +++ b/tests/tcg/multiarch/system/memory.c | ||
32 | @@ -XXX,XX +XXX,XX @@ | ||
33 | |||
34 | #include <stdint.h> | ||
35 | #include <stdbool.h> | ||
36 | -#include <inttypes.h> | ||
37 | #include <minilib.h> | ||
38 | |||
39 | #ifndef CHECK_UNALIGNED | ||
40 | @@ -XXX,XX +XXX,XX @@ int main(void) | ||
41 | int i; | ||
42 | bool ok = true; | ||
43 | |||
44 | - ml_printf("Test data start: 0x%"PRIxPTR"\n", &test_data[0]); | ||
45 | - ml_printf("Test data end: 0x%"PRIxPTR"\n", &test_data[TEST_SIZE]); | ||
46 | + ml_printf("Test data start: 0x%lx\n", (unsigned long)&test_data[0]); | ||
47 | + ml_printf("Test data end: 0x%lx\n", (unsigned long)&test_data[TEST_SIZE]); | ||
48 | |||
49 | /* Run through the unsigned tests first */ | ||
50 | for (i = 0; i < ARRAY_SIZE(init_ufns) && ok; i++) { | ||
51 | @@ -XXX,XX +XXX,XX @@ int main(void) | ||
52 | ok = do_signed_reads(true); | ||
53 | } | ||
54 | |||
55 | - ml_printf("Test data read: %"PRId32"\n", test_read_count); | ||
56 | - ml_printf("Test data write: %"PRId32"\n", test_write_count); | ||
57 | + ml_printf("Test data read: %lu\n", (unsigned long)test_read_count); | ||
58 | + ml_printf("Test data write: %lu\n", (unsigned long)test_write_count); | ||
59 | ml_printf("Test complete: %s\n", ok ? "PASSED" : "FAILED"); | ||
60 | return ok ? 0 : -1; | ||
61 | } | ||
62 | -- | ||
63 | 2.43.0 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Pierrick Bouvier <pierrick.bouvier@linaro.org> | ||
1 | 2 | ||
3 | When running with a single vcpu, we can return a constant instead of a | ||
4 | load when accessing cpu_index. | ||
5 | A side effect is that all tcg operations using it are optimized, most | ||
6 | notably scoreboard access. | ||
7 | When running a simple loop in user-mode, the speedup is around 20%. | ||
8 | |||
9 | Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> | ||
10 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
11 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
12 | Message-ID: <20241128213843.1023080-1-pierrick.bouvier@linaro.org> | ||
13 | --- | ||
14 | accel/tcg/plugin-gen.c | 9 +++++++++ | ||
15 | 1 file changed, 9 insertions(+) | ||
16 | |||
17 | diff --git a/accel/tcg/plugin-gen.c b/accel/tcg/plugin-gen.c | ||
18 | index XXXXXXX..XXXXXXX 100644 | ||
19 | --- a/accel/tcg/plugin-gen.c | ||
20 | +++ b/accel/tcg/plugin-gen.c | ||
21 | @@ -XXX,XX +XXX,XX @@ static void gen_disable_mem_helper(void) | ||
22 | |||
23 | static TCGv_i32 gen_cpu_index(void) | ||
24 | { | ||
25 | + /* | ||
26 | + * Optimize when we run with a single vcpu. All values using cpu_index, | ||
27 | + * including scoreboard index, will be optimized out. | ||
28 | + * User-mode calls tb_flush when setting this flag. In system-mode, all | ||
29 | + * vcpus are created before generating code. | ||
30 | + */ | ||
31 | + if (!tcg_cflags_has(current_cpu, CF_PARALLEL)) { | ||
32 | + return tcg_constant_i32(current_cpu->cpu_index); | ||
33 | + } | ||
34 | TCGv_i32 cpu_index = tcg_temp_ebb_new_i32(); | ||
35 | tcg_gen_ld_i32(cpu_index, tcg_env, | ||
36 | -offsetof(ArchCPU, env) + offsetof(CPUState, cpu_index)); | ||
37 | -- | ||
38 | 2.43.0 | diff view generated by jsdifflib |
1 | Having dupi pass though movi is confusing and arguably wrong. | 1 | Call them directly from the opcode switch statement in tcg_optimize, |
---|---|---|---|
2 | rather than in finish_folding based on opcode flags. Adjust folding | ||
3 | of conditional branches to match. | ||
2 | 4 | ||
3 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | 5 | Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> |
4 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
5 | --- | 7 | --- |
6 | tcg/tcg.c | 6 +++- | 8 | tcg/optimize.c | 47 +++++++++++++++++++++++++++++++---------------- |
7 | tcg/aarch64/tcg-target.c.inc | 7 ---- | 9 | 1 file changed, 31 insertions(+), 16 deletions(-) |
8 | tcg/i386/tcg-target.c.inc | 63 ++++++++++++++++++++++++------------ | ||
9 | tcg/ppc/tcg-target.c.inc | 6 ---- | ||
10 | 4 files changed, 47 insertions(+), 35 deletions(-) | ||
11 | 10 | ||
12 | diff --git a/tcg/tcg.c b/tcg/tcg.c | 11 | diff --git a/tcg/optimize.c b/tcg/optimize.c |
13 | index XXXXXXX..XXXXXXX 100644 | 12 | index XXXXXXX..XXXXXXX 100644 |
14 | --- a/tcg/tcg.c | 13 | --- a/tcg/optimize.c |
15 | +++ b/tcg/tcg.c | 14 | +++ b/tcg/optimize.c |
16 | @@ -XXX,XX +XXX,XX @@ static void temp_load(TCGContext *s, TCGTemp *ts, TCGRegSet desired_regs, | 15 | @@ -XXX,XX +XXX,XX @@ static void copy_propagate(OptContext *ctx, TCGOp *op, |
17 | case TEMP_VAL_CONST: | ||
18 | reg = tcg_reg_alloc(s, desired_regs, allocated_regs, | ||
19 | preferred_regs, ts->indirect_base); | ||
20 | - tcg_out_movi(s, ts->type, reg, ts->val); | ||
21 | + if (ts->type <= TCG_TYPE_I64) { | ||
22 | + tcg_out_movi(s, ts->type, reg, ts->val); | ||
23 | + } else { | ||
24 | + tcg_out_dupi_vec(s, ts->type, reg, ts->val); | ||
25 | + } | ||
26 | ts->mem_coherent = 0; | ||
27 | break; | ||
28 | case TEMP_VAL_MEM: | ||
29 | diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc | ||
30 | index XXXXXXX..XXXXXXX 100644 | ||
31 | --- a/tcg/aarch64/tcg-target.c.inc | ||
32 | +++ b/tcg/aarch64/tcg-target.c.inc | ||
33 | @@ -XXX,XX +XXX,XX @@ static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg rd, | ||
34 | case TCG_TYPE_I64: | ||
35 | tcg_debug_assert(rd < 32); | ||
36 | break; | ||
37 | - | ||
38 | - case TCG_TYPE_V64: | ||
39 | - case TCG_TYPE_V128: | ||
40 | - tcg_debug_assert(rd >= 32); | ||
41 | - tcg_out_dupi_vec(s, type, rd, value); | ||
42 | - return; | ||
43 | - | ||
44 | default: | ||
45 | g_assert_not_reached(); | ||
46 | } | ||
47 | diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc | ||
48 | index XXXXXXX..XXXXXXX 100644 | ||
49 | --- a/tcg/i386/tcg-target.c.inc | ||
50 | +++ b/tcg/i386/tcg-target.c.inc | ||
51 | @@ -XXX,XX +XXX,XX @@ static void tcg_out_dupi_vec(TCGContext *s, TCGType type, | ||
52 | } | 16 | } |
53 | } | 17 | } |
54 | 18 | ||
55 | -static void tcg_out_movi(TCGContext *s, TCGType type, | 19 | +static void finish_bb(OptContext *ctx) |
56 | - TCGReg ret, tcg_target_long arg) | ||
57 | +static void tcg_out_movi_vec(TCGContext *s, TCGType type, | ||
58 | + TCGReg ret, tcg_target_long arg) | ||
59 | +{ | 20 | +{ |
60 | + if (arg == 0) { | 21 | + /* We only optimize memory barriers across basic blocks. */ |
61 | + tcg_out_vex_modrm(s, OPC_PXOR, ret, ret, ret); | 22 | + ctx->prev_mb = NULL; |
62 | + return; | ||
63 | + } | ||
64 | + if (arg == -1) { | ||
65 | + tcg_out_vex_modrm(s, OPC_PCMPEQB, ret, ret, ret); | ||
66 | + return; | ||
67 | + } | ||
68 | + | ||
69 | + int rexw = (type == TCG_TYPE_I32 ? 0 : P_REXW); | ||
70 | + tcg_out_vex_modrm_pool(s, OPC_MOVD_VyEy + rexw, ret); | ||
71 | + if (TCG_TARGET_REG_BITS == 64) { | ||
72 | + new_pool_label(s, arg, R_386_PC32, s->code_ptr - 4, -4); | ||
73 | + } else { | ||
74 | + new_pool_label(s, arg, R_386_32, s->code_ptr - 4, 0); | ||
75 | + } | ||
76 | +} | 23 | +} |
77 | + | 24 | + |
78 | +static void tcg_out_movi_int(TCGContext *s, TCGType type, | 25 | +static void finish_ebb(OptContext *ctx) |
79 | + TCGReg ret, tcg_target_long arg) | 26 | +{ |
27 | + finish_bb(ctx); | ||
28 | + /* We only optimize across extended basic blocks. */ | ||
29 | + memset(&ctx->temps_used, 0, sizeof(ctx->temps_used)); | ||
30 | + remove_mem_copy_all(ctx); | ||
31 | +} | ||
32 | + | ||
33 | static void finish_folding(OptContext *ctx, TCGOp *op) | ||
80 | { | 34 | { |
81 | tcg_target_long diff; | 35 | const TCGOpDef *def = &tcg_op_defs[op->opc]; |
82 | 36 | int i, nb_oargs; | |
83 | - switch (type) { | 37 | |
84 | - case TCG_TYPE_I32: | 38 | - /* |
85 | -#if TCG_TARGET_REG_BITS == 64 | 39 | - * We only optimize extended basic blocks. If the opcode ends a BB |
86 | - case TCG_TYPE_I64: | 40 | - * and is not a conditional branch, reset all temp data. |
87 | -#endif | 41 | - */ |
88 | - if (ret < 16) { | 42 | - if (def->flags & TCG_OPF_BB_END) { |
89 | - break; | 43 | - ctx->prev_mb = NULL; |
44 | - if (!(def->flags & TCG_OPF_COND_BRANCH)) { | ||
45 | - memset(&ctx->temps_used, 0, sizeof(ctx->temps_used)); | ||
46 | - remove_mem_copy_all(ctx); | ||
90 | - } | 47 | - } |
91 | - /* fallthru */ | ||
92 | - case TCG_TYPE_V64: | ||
93 | - case TCG_TYPE_V128: | ||
94 | - case TCG_TYPE_V256: | ||
95 | - tcg_debug_assert(ret >= 16); | ||
96 | - tcg_out_dupi_vec(s, type, ret, arg); | ||
97 | - return; | 48 | - return; |
98 | - default: | ||
99 | - g_assert_not_reached(); | ||
100 | - } | 49 | - } |
101 | - | 50 | - |
102 | if (arg == 0) { | 51 | nb_oargs = def->nb_oargs; |
103 | tgen_arithr(s, ARITH_XOR, ret, ret); | 52 | for (i = 0; i < nb_oargs; i++) { |
104 | return; | 53 | TCGTemp *ts = arg_temp(op->args[i]); |
105 | @@ -XXX,XX +XXX,XX @@ static void tcg_out_movi(TCGContext *s, TCGType type, | 54 | @@ -XXX,XX +XXX,XX @@ static bool fold_brcond(OptContext *ctx, TCGOp *op) |
106 | tcg_out64(s, arg); | 55 | if (i > 0) { |
56 | op->opc = INDEX_op_br; | ||
57 | op->args[0] = op->args[3]; | ||
58 | + finish_ebb(ctx); | ||
59 | + } else { | ||
60 | + finish_bb(ctx); | ||
61 | } | ||
62 | - return false; | ||
63 | + return true; | ||
107 | } | 64 | } |
108 | 65 | ||
109 | +static void tcg_out_movi(TCGContext *s, TCGType type, | 66 | static bool fold_brcond2(OptContext *ctx, TCGOp *op) |
110 | + TCGReg ret, tcg_target_long arg) | 67 | @@ -XXX,XX +XXX,XX @@ static bool fold_brcond2(OptContext *ctx, TCGOp *op) |
111 | +{ | 68 | } |
112 | + switch (type) { | 69 | op->opc = INDEX_op_br; |
113 | + case TCG_TYPE_I32: | 70 | op->args[0] = label; |
114 | +#if TCG_TARGET_REG_BITS == 64 | 71 | - break; |
115 | + case TCG_TYPE_I64: | 72 | + finish_ebb(ctx); |
116 | +#endif | 73 | + return true; |
117 | + if (ret < 16) { | 74 | } |
118 | + tcg_out_movi_int(s, type, ret, arg); | 75 | - return false; |
119 | + } else { | ||
120 | + tcg_out_movi_vec(s, type, ret, arg); | ||
121 | + } | ||
122 | + break; | ||
123 | + default: | ||
124 | + g_assert_not_reached(); | ||
125 | + } | ||
126 | +} | ||
127 | + | 76 | + |
128 | static inline void tcg_out_pushi(TCGContext *s, tcg_target_long val) | 77 | + finish_bb(ctx); |
129 | { | 78 | + return true; |
130 | if (val == (int8_t)val) { | 79 | } |
131 | diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc | 80 | |
132 | index XXXXXXX..XXXXXXX 100644 | 81 | static bool fold_bswap(OptContext *ctx, TCGOp *op) |
133 | --- a/tcg/ppc/tcg-target.c.inc | 82 | @@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s) |
134 | +++ b/tcg/ppc/tcg-target.c.inc | 83 | CASE_OP_32_64_VEC(xor): |
135 | @@ -XXX,XX +XXX,XX @@ static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg ret, | 84 | done = fold_xor(&ctx, op); |
136 | tcg_out_movi_int(s, type, ret, arg, false); | 85 | break; |
137 | break; | 86 | + case INDEX_op_set_label: |
138 | 87 | + case INDEX_op_br: | |
139 | - case TCG_TYPE_V64: | 88 | + case INDEX_op_exit_tb: |
140 | - case TCG_TYPE_V128: | 89 | + case INDEX_op_goto_tb: |
141 | - tcg_debug_assert(ret >= TCG_REG_V0); | 90 | + case INDEX_op_goto_ptr: |
142 | - tcg_out_dupi_vec(s, type, ret, arg); | 91 | + finish_ebb(&ctx); |
143 | - break; | 92 | + done = true; |
144 | - | 93 | + break; |
145 | default: | 94 | default: |
146 | g_assert_not_reached(); | 95 | break; |
147 | } | 96 | } |
148 | -- | 97 | -- |
149 | 2.25.1 | 98 | 2.43.0 |
150 | |||
151 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | There are only a few logical operations which can compute | ||
2 | an "affected" mask. Split out handling of this optimization | ||
3 | to a separate function, only to be called when applicable. | ||
1 | 4 | ||
5 | Remove the a_mask field from OptContext, as the mask is | ||
6 | no longer stored anywhere. | ||
7 | |||
8 | Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> | ||
9 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
10 | --- | ||
11 | tcg/optimize.c | 42 +++++++++++++++++++++++++++--------------- | ||
12 | 1 file changed, 27 insertions(+), 15 deletions(-) | ||
13 | |||
14 | diff --git a/tcg/optimize.c b/tcg/optimize.c | ||
15 | index XXXXXXX..XXXXXXX 100644 | ||
16 | --- a/tcg/optimize.c | ||
17 | +++ b/tcg/optimize.c | ||
18 | @@ -XXX,XX +XXX,XX @@ typedef struct OptContext { | ||
19 | QSIMPLEQ_HEAD(, MemCopyInfo) mem_free; | ||
20 | |||
21 | /* In flight values from optimization. */ | ||
22 | - uint64_t a_mask; /* mask bit is 0 iff value identical to first input */ | ||
23 | uint64_t z_mask; /* mask bit is 0 iff value bit is 0 */ | ||
24 | uint64_t s_mask; /* mask of clrsb(value) bits */ | ||
25 | TCGType type; | ||
26 | @@ -XXX,XX +XXX,XX @@ static bool fold_const2_commutative(OptContext *ctx, TCGOp *op) | ||
27 | |||
28 | static bool fold_masks(OptContext *ctx, TCGOp *op) | ||
29 | { | ||
30 | - uint64_t a_mask = ctx->a_mask; | ||
31 | uint64_t z_mask = ctx->z_mask; | ||
32 | uint64_t s_mask = ctx->s_mask; | ||
33 | |||
34 | @@ -XXX,XX +XXX,XX @@ static bool fold_masks(OptContext *ctx, TCGOp *op) | ||
35 | * type changing opcodes. | ||
36 | */ | ||
37 | if (ctx->type == TCG_TYPE_I32) { | ||
38 | - a_mask = (int32_t)a_mask; | ||
39 | z_mask = (int32_t)z_mask; | ||
40 | s_mask |= MAKE_64BIT_MASK(32, 32); | ||
41 | ctx->z_mask = z_mask; | ||
42 | @@ -XXX,XX +XXX,XX @@ static bool fold_masks(OptContext *ctx, TCGOp *op) | ||
43 | if (z_mask == 0) { | ||
44 | return tcg_opt_gen_movi(ctx, op, op->args[0], 0); | ||
45 | } | ||
46 | + return false; | ||
47 | +} | ||
48 | + | ||
49 | +/* | ||
50 | + * An "affected" mask bit is 0 if and only if the result is identical | ||
51 | + * to the first input. Thus if the entire mask is 0, the operation | ||
52 | + * is equivalent to a copy. | ||
53 | + */ | ||
54 | +static bool fold_affected_mask(OptContext *ctx, TCGOp *op, uint64_t a_mask) | ||
55 | +{ | ||
56 | + if (ctx->type == TCG_TYPE_I32) { | ||
57 | + a_mask = (uint32_t)a_mask; | ||
58 | + } | ||
59 | if (a_mask == 0) { | ||
60 | return tcg_opt_gen_mov(ctx, op, op->args[0], op->args[1]); | ||
61 | } | ||
62 | @@ -XXX,XX +XXX,XX @@ static bool fold_and(OptContext *ctx, TCGOp *op) | ||
63 | * Known-zeros does not imply known-ones. Therefore unless | ||
64 | * arg2 is constant, we can't infer affected bits from it. | ||
65 | */ | ||
66 | - if (arg_is_const(op->args[2])) { | ||
67 | - ctx->a_mask = z1 & ~z2; | ||
68 | + if (arg_is_const(op->args[2]) && | ||
69 | + fold_affected_mask(ctx, op, z1 & ~z2)) { | ||
70 | + return true; | ||
71 | } | ||
72 | |||
73 | return fold_masks(ctx, op); | ||
74 | @@ -XXX,XX +XXX,XX @@ static bool fold_andc(OptContext *ctx, TCGOp *op) | ||
75 | */ | ||
76 | if (arg_is_const(op->args[2])) { | ||
77 | uint64_t z2 = ~arg_info(op->args[2])->z_mask; | ||
78 | - ctx->a_mask = z1 & ~z2; | ||
79 | + if (fold_affected_mask(ctx, op, z1 & ~z2)) { | ||
80 | + return true; | ||
81 | + } | ||
82 | z1 &= z2; | ||
83 | } | ||
84 | ctx->z_mask = z1; | ||
85 | @@ -XXX,XX +XXX,XX @@ static bool fold_extract(OptContext *ctx, TCGOp *op) | ||
86 | |||
87 | z_mask_old = arg_info(op->args[1])->z_mask; | ||
88 | z_mask = extract64(z_mask_old, pos, len); | ||
89 | - if (pos == 0) { | ||
90 | - ctx->a_mask = z_mask_old ^ z_mask; | ||
91 | + if (pos == 0 && fold_affected_mask(ctx, op, z_mask_old ^ z_mask)) { | ||
92 | + return true; | ||
93 | } | ||
94 | ctx->z_mask = z_mask; | ||
95 | ctx->s_mask = smask_from_zmask(z_mask); | ||
96 | @@ -XXX,XX +XXX,XX @@ static bool fold_exts(OptContext *ctx, TCGOp *op) | ||
97 | |||
98 | ctx->z_mask = z_mask; | ||
99 | ctx->s_mask = s_mask; | ||
100 | - if (!type_change) { | ||
101 | - ctx->a_mask = s_mask & ~s_mask_old; | ||
102 | + if (!type_change && fold_affected_mask(ctx, op, s_mask & ~s_mask_old)) { | ||
103 | + return true; | ||
104 | } | ||
105 | |||
106 | return fold_masks(ctx, op); | ||
107 | @@ -XXX,XX +XXX,XX @@ static bool fold_extu(OptContext *ctx, TCGOp *op) | ||
108 | |||
109 | ctx->z_mask = z_mask; | ||
110 | ctx->s_mask = smask_from_zmask(z_mask); | ||
111 | - if (!type_change) { | ||
112 | - ctx->a_mask = z_mask_old ^ z_mask; | ||
113 | + if (!type_change && fold_affected_mask(ctx, op, z_mask_old ^ z_mask)) { | ||
114 | + return true; | ||
115 | } | ||
116 | return fold_masks(ctx, op); | ||
117 | } | ||
118 | @@ -XXX,XX +XXX,XX @@ static bool fold_sextract(OptContext *ctx, TCGOp *op) | ||
119 | s_mask |= MAKE_64BIT_MASK(len, 64 - len); | ||
120 | ctx->s_mask = s_mask; | ||
121 | |||
122 | - if (pos == 0) { | ||
123 | - ctx->a_mask = s_mask & ~s_mask_old; | ||
124 | + if (pos == 0 && fold_affected_mask(ctx, op, s_mask & ~s_mask_old)) { | ||
125 | + return true; | ||
126 | } | ||
127 | |||
128 | return fold_masks(ctx, op); | ||
129 | @@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s) | ||
130 | } | ||
131 | |||
132 | /* Assume all bits affected, no bits known zero, no sign reps. */ | ||
133 | - ctx.a_mask = -1; | ||
134 | ctx.z_mask = -1; | ||
135 | ctx.s_mask = 0; | ||
136 | |||
137 | -- | ||
138 | 2.43.0 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Use of fold_masks should be restricted to those opcodes that | ||
2 | can reliably make use of it -- those with a single output, | ||
3 | and from higher-level folders that set up the masks. | ||
4 | Prepare for conversion of each folder in turn. | ||
1 | 5 | ||
6 | Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> | ||
7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | --- | ||
9 | tcg/optimize.c | 17 ++++++++++++++--- | ||
10 | 1 file changed, 14 insertions(+), 3 deletions(-) | ||
11 | |||
12 | diff --git a/tcg/optimize.c b/tcg/optimize.c | ||
13 | index XXXXXXX..XXXXXXX 100644 | ||
14 | --- a/tcg/optimize.c | ||
15 | +++ b/tcg/optimize.c | ||
16 | @@ -XXX,XX +XXX,XX @@ static bool fold_masks(OptContext *ctx, TCGOp *op) | ||
17 | { | ||
18 | uint64_t z_mask = ctx->z_mask; | ||
19 | uint64_t s_mask = ctx->s_mask; | ||
20 | + const TCGOpDef *def = &tcg_op_defs[op->opc]; | ||
21 | + TCGTemp *ts; | ||
22 | + TempOptInfo *ti; | ||
23 | + | ||
24 | + /* Only single-output opcodes are supported here. */ | ||
25 | + tcg_debug_assert(def->nb_oargs == 1); | ||
26 | |||
27 | /* | ||
28 | * 32-bit ops generate 32-bit results, which for the purpose of | ||
29 | @@ -XXX,XX +XXX,XX @@ static bool fold_masks(OptContext *ctx, TCGOp *op) | ||
30 | if (ctx->type == TCG_TYPE_I32) { | ||
31 | z_mask = (int32_t)z_mask; | ||
32 | s_mask |= MAKE_64BIT_MASK(32, 32); | ||
33 | - ctx->z_mask = z_mask; | ||
34 | - ctx->s_mask = s_mask; | ||
35 | } | ||
36 | |||
37 | if (z_mask == 0) { | ||
38 | return tcg_opt_gen_movi(ctx, op, op->args[0], 0); | ||
39 | } | ||
40 | - return false; | ||
41 | + | ||
42 | + ts = arg_temp(op->args[0]); | ||
43 | + reset_ts(ctx, ts); | ||
44 | + | ||
45 | + ti = ts_info(ts); | ||
46 | + ti->z_mask = z_mask; | ||
47 | + ti->s_mask = s_mask; | ||
48 | + return true; | ||
49 | } | ||
50 | |||
51 | /* | ||
52 | -- | ||
53 | 2.43.0 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Add a routine to which masks can be passed directly, rather than | ||
2 | storing them into OptContext. To be used in upcoming patches. | ||
1 | 3 | ||
4 | Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> | ||
5 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
6 | --- | ||
7 | tcg/optimize.c | 15 ++++++++++++--- | ||
8 | 1 file changed, 12 insertions(+), 3 deletions(-) | ||
9 | |||
10 | diff --git a/tcg/optimize.c b/tcg/optimize.c | ||
11 | index XXXXXXX..XXXXXXX 100644 | ||
12 | --- a/tcg/optimize.c | ||
13 | +++ b/tcg/optimize.c | ||
14 | @@ -XXX,XX +XXX,XX @@ static bool fold_const2_commutative(OptContext *ctx, TCGOp *op) | ||
15 | return fold_const2(ctx, op); | ||
16 | } | ||
17 | |||
18 | -static bool fold_masks(OptContext *ctx, TCGOp *op) | ||
19 | +/* | ||
20 | + * Record "zero" and "sign" masks for the single output of @op. | ||
21 | + * See TempOptInfo definition of z_mask and s_mask. | ||
22 | + * If z_mask allows, fold the output to constant zero. | ||
23 | + */ | ||
24 | +static bool fold_masks_zs(OptContext *ctx, TCGOp *op, | ||
25 | + uint64_t z_mask, uint64_t s_mask) | ||
26 | { | ||
27 | - uint64_t z_mask = ctx->z_mask; | ||
28 | - uint64_t s_mask = ctx->s_mask; | ||
29 | const TCGOpDef *def = &tcg_op_defs[op->opc]; | ||
30 | TCGTemp *ts; | ||
31 | TempOptInfo *ti; | ||
32 | @@ -XXX,XX +XXX,XX @@ static bool fold_masks(OptContext *ctx, TCGOp *op) | ||
33 | return true; | ||
34 | } | ||
35 | |||
36 | +static bool fold_masks(OptContext *ctx, TCGOp *op) | ||
37 | +{ | ||
38 | + return fold_masks_zs(ctx, op, ctx->z_mask, ctx->s_mask); | ||
39 | +} | ||
40 | + | ||
41 | /* | ||
42 | * An "affected" mask bit is 0 if and only if the result is identical | ||
43 | * to the first input. Thus if the entire mask is 0, the operation | ||
44 | -- | ||
45 | 2.43.0 | diff view generated by jsdifflib |
1 | Consider the passed s_mask to be a minimum deduced from | ||
---|---|---|---|
2 | either existing s_mask or from a sign-extension operation. | ||
3 | We may be able to deduce more from the set of known zeros. | ||
4 | Remove identical logic from several opcode folders. | ||
5 | |||
6 | Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> | ||
1 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
2 | --- | 8 | --- |
3 | include/tcg/tcg.h | 1 + | 9 | tcg/optimize.c | 21 ++++++--------------- |
4 | tcg/tcg-op-gvec.c | 129 ++++++++++++++++++---------------------------- | 10 | 1 file changed, 6 insertions(+), 15 deletions(-) |
5 | tcg/tcg.c | 8 +++ | ||
6 | 3 files changed, 60 insertions(+), 78 deletions(-) | ||
7 | 11 | ||
8 | diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h | 12 | diff --git a/tcg/optimize.c b/tcg/optimize.c |
9 | index XXXXXXX..XXXXXXX 100644 | 13 | index XXXXXXX..XXXXXXX 100644 |
10 | --- a/include/tcg/tcg.h | 14 | --- a/tcg/optimize.c |
11 | +++ b/include/tcg/tcg.h | 15 | +++ b/tcg/optimize.c |
12 | @@ -XXX,XX +XXX,XX @@ static inline TCGv_i64 tcg_constant_i64(int64_t val) | 16 | @@ -XXX,XX +XXX,XX @@ static bool fold_const2_commutative(OptContext *ctx, TCGOp *op) |
17 | * Record "zero" and "sign" masks for the single output of @op. | ||
18 | * See TempOptInfo definition of z_mask and s_mask. | ||
19 | * If z_mask allows, fold the output to constant zero. | ||
20 | + * The passed s_mask may be augmented by z_mask. | ||
21 | */ | ||
22 | static bool fold_masks_zs(OptContext *ctx, TCGOp *op, | ||
23 | uint64_t z_mask, uint64_t s_mask) | ||
24 | @@ -XXX,XX +XXX,XX @@ static bool fold_masks_zs(OptContext *ctx, TCGOp *op, | ||
25 | |||
26 | ti = ts_info(ts); | ||
27 | ti->z_mask = z_mask; | ||
28 | - ti->s_mask = s_mask; | ||
29 | + ti->s_mask = s_mask | smask_from_zmask(z_mask); | ||
30 | return true; | ||
13 | } | 31 | } |
14 | 32 | ||
15 | TCGv_vec tcg_constant_vec(TCGType type, unsigned vece, int64_t val); | 33 | @@ -XXX,XX +XXX,XX @@ static bool fold_bswap(OptContext *ctx, TCGOp *op) |
16 | +TCGv_vec tcg_constant_vec_matching(TCGv_vec match, unsigned vece, int64_t val); | 34 | default: |
17 | 35 | g_assert_not_reached(); | |
18 | #if UINTPTR_MAX == UINT32_MAX | 36 | } |
19 | # define tcg_const_ptr(x) ((TCGv_ptr)tcg_const_i32((intptr_t)(x))) | 37 | - s_mask = smask_from_zmask(z_mask); |
20 | diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c | 38 | |
21 | index XXXXXXX..XXXXXXX 100644 | 39 | + s_mask = 0; |
22 | --- a/tcg/tcg-op-gvec.c | 40 | switch (op->args[2] & (TCG_BSWAP_OZ | TCG_BSWAP_OS)) { |
23 | +++ b/tcg/tcg-op-gvec.c | 41 | case TCG_BSWAP_OZ: |
24 | @@ -XXX,XX +XXX,XX @@ void tcg_gen_gvec_2_ool(uint32_t dofs, uint32_t aofs, | 42 | break; |
25 | gen_helper_gvec_2 *fn) | 43 | @@ -XXX,XX +XXX,XX @@ static bool fold_bswap(OptContext *ctx, TCGOp *op) |
26 | { | 44 | default: |
27 | TCGv_ptr a0, a1; | 45 | /* The high bits are undefined: force all bits above the sign to 1. */ |
28 | - TCGv_i32 desc = tcg_const_i32(simd_desc(oprsz, maxsz, data)); | 46 | z_mask |= sign << 1; |
29 | + TCGv_i32 desc = tcg_constant_i32(simd_desc(oprsz, maxsz, data)); | 47 | - s_mask = 0; |
30 | 48 | break; | |
31 | a0 = tcg_temp_new_ptr(); | 49 | } |
32 | a1 = tcg_temp_new_ptr(); | 50 | ctx->z_mask = z_mask; |
33 | @@ -XXX,XX +XXX,XX @@ void tcg_gen_gvec_2_ool(uint32_t dofs, uint32_t aofs, | 51 | @@ -XXX,XX +XXX,XX @@ static bool fold_count_zeros(OptContext *ctx, TCGOp *op) |
34 | 52 | g_assert_not_reached(); | |
35 | tcg_temp_free_ptr(a0); | 53 | } |
36 | tcg_temp_free_ptr(a1); | 54 | ctx->z_mask = arg_info(op->args[2])->z_mask | z_mask; |
37 | - tcg_temp_free_i32(desc); | 55 | - ctx->s_mask = smask_from_zmask(ctx->z_mask); |
56 | return false; | ||
38 | } | 57 | } |
39 | 58 | ||
40 | /* Generate a call to a gvec-style helper with two vector operands | 59 | @@ -XXX,XX +XXX,XX @@ static bool fold_ctpop(OptContext *ctx, TCGOp *op) |
41 | @@ -XXX,XX +XXX,XX @@ void tcg_gen_gvec_2i_ool(uint32_t dofs, uint32_t aofs, TCGv_i64 c, | 60 | default: |
42 | gen_helper_gvec_2i *fn) | 61 | g_assert_not_reached(); |
43 | { | 62 | } |
44 | TCGv_ptr a0, a1; | 63 | - ctx->s_mask = smask_from_zmask(ctx->z_mask); |
45 | - TCGv_i32 desc = tcg_const_i32(simd_desc(oprsz, maxsz, data)); | 64 | return false; |
46 | + TCGv_i32 desc = tcg_constant_i32(simd_desc(oprsz, maxsz, data)); | ||
47 | |||
48 | a0 = tcg_temp_new_ptr(); | ||
49 | a1 = tcg_temp_new_ptr(); | ||
50 | @@ -XXX,XX +XXX,XX @@ void tcg_gen_gvec_2i_ool(uint32_t dofs, uint32_t aofs, TCGv_i64 c, | ||
51 | |||
52 | tcg_temp_free_ptr(a0); | ||
53 | tcg_temp_free_ptr(a1); | ||
54 | - tcg_temp_free_i32(desc); | ||
55 | } | 65 | } |
56 | 66 | ||
57 | /* Generate a call to a gvec-style helper with three vector operands. */ | 67 | @@ -XXX,XX +XXX,XX @@ static bool fold_extract(OptContext *ctx, TCGOp *op) |
58 | @@ -XXX,XX +XXX,XX @@ void tcg_gen_gvec_3_ool(uint32_t dofs, uint32_t aofs, uint32_t bofs, | 68 | return true; |
59 | gen_helper_gvec_3 *fn) | 69 | } |
60 | { | 70 | ctx->z_mask = z_mask; |
61 | TCGv_ptr a0, a1, a2; | 71 | - ctx->s_mask = smask_from_zmask(z_mask); |
62 | - TCGv_i32 desc = tcg_const_i32(simd_desc(oprsz, maxsz, data)); | 72 | |
63 | + TCGv_i32 desc = tcg_constant_i32(simd_desc(oprsz, maxsz, data)); | 73 | return fold_masks(ctx, op); |
64 | |||
65 | a0 = tcg_temp_new_ptr(); | ||
66 | a1 = tcg_temp_new_ptr(); | ||
67 | @@ -XXX,XX +XXX,XX @@ void tcg_gen_gvec_3_ool(uint32_t dofs, uint32_t aofs, uint32_t bofs, | ||
68 | tcg_temp_free_ptr(a0); | ||
69 | tcg_temp_free_ptr(a1); | ||
70 | tcg_temp_free_ptr(a2); | ||
71 | - tcg_temp_free_i32(desc); | ||
72 | } | 74 | } |
73 | 75 | @@ -XXX,XX +XXX,XX @@ static bool fold_extu(OptContext *ctx, TCGOp *op) | |
74 | /* Generate a call to a gvec-style helper with four vector operands. */ | ||
75 | @@ -XXX,XX +XXX,XX @@ void tcg_gen_gvec_4_ool(uint32_t dofs, uint32_t aofs, uint32_t bofs, | ||
76 | int32_t data, gen_helper_gvec_4 *fn) | ||
77 | { | ||
78 | TCGv_ptr a0, a1, a2, a3; | ||
79 | - TCGv_i32 desc = tcg_const_i32(simd_desc(oprsz, maxsz, data)); | ||
80 | + TCGv_i32 desc = tcg_constant_i32(simd_desc(oprsz, maxsz, data)); | ||
81 | |||
82 | a0 = tcg_temp_new_ptr(); | ||
83 | a1 = tcg_temp_new_ptr(); | ||
84 | @@ -XXX,XX +XXX,XX @@ void tcg_gen_gvec_4_ool(uint32_t dofs, uint32_t aofs, uint32_t bofs, | ||
85 | tcg_temp_free_ptr(a1); | ||
86 | tcg_temp_free_ptr(a2); | ||
87 | tcg_temp_free_ptr(a3); | ||
88 | - tcg_temp_free_i32(desc); | ||
89 | } | ||
90 | |||
91 | /* Generate a call to a gvec-style helper with five vector operands. */ | ||
92 | @@ -XXX,XX +XXX,XX @@ void tcg_gen_gvec_5_ool(uint32_t dofs, uint32_t aofs, uint32_t bofs, | ||
93 | uint32_t maxsz, int32_t data, gen_helper_gvec_5 *fn) | ||
94 | { | ||
95 | TCGv_ptr a0, a1, a2, a3, a4; | ||
96 | - TCGv_i32 desc = tcg_const_i32(simd_desc(oprsz, maxsz, data)); | ||
97 | + TCGv_i32 desc = tcg_constant_i32(simd_desc(oprsz, maxsz, data)); | ||
98 | |||
99 | a0 = tcg_temp_new_ptr(); | ||
100 | a1 = tcg_temp_new_ptr(); | ||
101 | @@ -XXX,XX +XXX,XX @@ void tcg_gen_gvec_5_ool(uint32_t dofs, uint32_t aofs, uint32_t bofs, | ||
102 | tcg_temp_free_ptr(a2); | ||
103 | tcg_temp_free_ptr(a3); | ||
104 | tcg_temp_free_ptr(a4); | ||
105 | - tcg_temp_free_i32(desc); | ||
106 | } | ||
107 | |||
108 | /* Generate a call to a gvec-style helper with three vector operands | ||
109 | @@ -XXX,XX +XXX,XX @@ void tcg_gen_gvec_2_ptr(uint32_t dofs, uint32_t aofs, | ||
110 | int32_t data, gen_helper_gvec_2_ptr *fn) | ||
111 | { | ||
112 | TCGv_ptr a0, a1; | ||
113 | - TCGv_i32 desc = tcg_const_i32(simd_desc(oprsz, maxsz, data)); | ||
114 | + TCGv_i32 desc = tcg_constant_i32(simd_desc(oprsz, maxsz, data)); | ||
115 | |||
116 | a0 = tcg_temp_new_ptr(); | ||
117 | a1 = tcg_temp_new_ptr(); | ||
118 | @@ -XXX,XX +XXX,XX @@ void tcg_gen_gvec_2_ptr(uint32_t dofs, uint32_t aofs, | ||
119 | |||
120 | tcg_temp_free_ptr(a0); | ||
121 | tcg_temp_free_ptr(a1); | ||
122 | - tcg_temp_free_i32(desc); | ||
123 | } | ||
124 | |||
125 | /* Generate a call to a gvec-style helper with three vector operands | ||
126 | @@ -XXX,XX +XXX,XX @@ void tcg_gen_gvec_3_ptr(uint32_t dofs, uint32_t aofs, uint32_t bofs, | ||
127 | int32_t data, gen_helper_gvec_3_ptr *fn) | ||
128 | { | ||
129 | TCGv_ptr a0, a1, a2; | ||
130 | - TCGv_i32 desc = tcg_const_i32(simd_desc(oprsz, maxsz, data)); | ||
131 | + TCGv_i32 desc = tcg_constant_i32(simd_desc(oprsz, maxsz, data)); | ||
132 | |||
133 | a0 = tcg_temp_new_ptr(); | ||
134 | a1 = tcg_temp_new_ptr(); | ||
135 | @@ -XXX,XX +XXX,XX @@ void tcg_gen_gvec_3_ptr(uint32_t dofs, uint32_t aofs, uint32_t bofs, | ||
136 | tcg_temp_free_ptr(a0); | ||
137 | tcg_temp_free_ptr(a1); | ||
138 | tcg_temp_free_ptr(a2); | ||
139 | - tcg_temp_free_i32(desc); | ||
140 | } | ||
141 | |||
142 | /* Generate a call to a gvec-style helper with four vector operands | ||
143 | @@ -XXX,XX +XXX,XX @@ void tcg_gen_gvec_4_ptr(uint32_t dofs, uint32_t aofs, uint32_t bofs, | ||
144 | gen_helper_gvec_4_ptr *fn) | ||
145 | { | ||
146 | TCGv_ptr a0, a1, a2, a3; | ||
147 | - TCGv_i32 desc = tcg_const_i32(simd_desc(oprsz, maxsz, data)); | ||
148 | + TCGv_i32 desc = tcg_constant_i32(simd_desc(oprsz, maxsz, data)); | ||
149 | |||
150 | a0 = tcg_temp_new_ptr(); | ||
151 | a1 = tcg_temp_new_ptr(); | ||
152 | @@ -XXX,XX +XXX,XX @@ void tcg_gen_gvec_4_ptr(uint32_t dofs, uint32_t aofs, uint32_t bofs, | ||
153 | tcg_temp_free_ptr(a1); | ||
154 | tcg_temp_free_ptr(a2); | ||
155 | tcg_temp_free_ptr(a3); | ||
156 | - tcg_temp_free_i32(desc); | ||
157 | } | ||
158 | |||
159 | /* Generate a call to a gvec-style helper with five vector operands | ||
160 | @@ -XXX,XX +XXX,XX @@ void tcg_gen_gvec_5_ptr(uint32_t dofs, uint32_t aofs, uint32_t bofs, | ||
161 | gen_helper_gvec_5_ptr *fn) | ||
162 | { | ||
163 | TCGv_ptr a0, a1, a2, a3, a4; | ||
164 | - TCGv_i32 desc = tcg_const_i32(simd_desc(oprsz, maxsz, data)); | ||
165 | + TCGv_i32 desc = tcg_constant_i32(simd_desc(oprsz, maxsz, data)); | ||
166 | |||
167 | a0 = tcg_temp_new_ptr(); | ||
168 | a1 = tcg_temp_new_ptr(); | ||
169 | @@ -XXX,XX +XXX,XX @@ void tcg_gen_gvec_5_ptr(uint32_t dofs, uint32_t aofs, uint32_t bofs, | ||
170 | tcg_temp_free_ptr(a2); | ||
171 | tcg_temp_free_ptr(a3); | ||
172 | tcg_temp_free_ptr(a4); | ||
173 | - tcg_temp_free_i32(desc); | ||
174 | } | ||
175 | |||
176 | /* Return true if we want to implement something of OPRSZ bytes | ||
177 | @@ -XXX,XX +XXX,XX @@ static void do_dup(unsigned vece, uint32_t dofs, uint32_t oprsz, | ||
178 | || (TCG_TARGET_REG_BITS == 64 | ||
179 | && (in_c == 0 || in_c == -1 | ||
180 | || !check_size_impl(oprsz, 4)))) { | ||
181 | - t_64 = tcg_const_i64(in_c); | ||
182 | + t_64 = tcg_constant_i64(in_c); | ||
183 | } else { | ||
184 | - t_32 = tcg_const_i32(in_c); | ||
185 | + t_32 = tcg_constant_i32(in_c); | ||
186 | } | ||
187 | } | ||
188 | |||
189 | @@ -XXX,XX +XXX,XX @@ static void do_dup(unsigned vece, uint32_t dofs, uint32_t oprsz, | ||
190 | t_val = tcg_temp_new_i32(); | ||
191 | tcg_gen_extrl_i64_i32(t_val, in_64); | ||
192 | } else { | ||
193 | - t_val = tcg_const_i32(in_c); | ||
194 | + t_val = tcg_constant_i32(in_c); | ||
195 | } | ||
196 | gen_helper_memset(t_ptr, t_ptr, t_val, t_size); | ||
197 | |||
198 | - if (!in_32) { | ||
199 | + if (in_64) { | ||
200 | tcg_temp_free_i32(t_val); | ||
201 | } | ||
202 | tcg_temp_free_ptr(t_size); | ||
203 | @@ -XXX,XX +XXX,XX @@ static void do_dup(unsigned vece, uint32_t dofs, uint32_t oprsz, | ||
204 | return; | ||
205 | } | 76 | } |
206 | 77 | ||
207 | - t_desc = tcg_const_i32(simd_desc(oprsz, maxsz, 0)); | 78 | ctx->z_mask = z_mask; |
208 | + t_desc = tcg_constant_i32(simd_desc(oprsz, maxsz, 0)); | 79 | - ctx->s_mask = smask_from_zmask(z_mask); |
209 | 80 | if (!type_change && fold_affected_mask(ctx, op, z_mask_old ^ z_mask)) { | |
210 | if (vece == MO_64) { | 81 | return true; |
211 | if (in_64) { | 82 | } |
212 | gen_helper_gvec_dup64(t_ptr, t_desc, in_64); | 83 | @@ -XXX,XX +XXX,XX @@ static bool fold_qemu_ld(OptContext *ctx, TCGOp *op) |
213 | } else { | 84 | int width = 8 * memop_size(mop); |
214 | - t_64 = tcg_const_i64(in_c); | 85 | |
215 | + t_64 = tcg_constant_i64(in_c); | 86 | if (width < 64) { |
216 | gen_helper_gvec_dup64(t_ptr, t_desc, t_64); | 87 | - ctx->s_mask = MAKE_64BIT_MASK(width, 64 - width); |
217 | - tcg_temp_free_i64(t_64); | 88 | - if (!(mop & MO_SIGN)) { |
218 | } | 89 | + if (mop & MO_SIGN) { |
219 | } else { | 90 | + ctx->s_mask = MAKE_64BIT_MASK(width, 64 - width); |
220 | typedef void dup_fn(TCGv_ptr, TCGv_i32, TCGv_i32); | ||
221 | @@ -XXX,XX +XXX,XX @@ static void do_dup(unsigned vece, uint32_t dofs, uint32_t oprsz, | ||
222 | |||
223 | if (in_32) { | ||
224 | fns[vece](t_ptr, t_desc, in_32); | ||
225 | - } else { | ||
226 | + } else if (in_64) { | ||
227 | t_32 = tcg_temp_new_i32(); | ||
228 | - if (in_64) { | ||
229 | - tcg_gen_extrl_i64_i32(t_32, in_64); | ||
230 | - } else if (vece == MO_8) { | ||
231 | - tcg_gen_movi_i32(t_32, in_c & 0xff); | ||
232 | - } else if (vece == MO_16) { | ||
233 | - tcg_gen_movi_i32(t_32, in_c & 0xffff); | ||
234 | - } else { | ||
235 | - tcg_gen_movi_i32(t_32, in_c); | ||
236 | - } | ||
237 | + tcg_gen_extrl_i64_i32(t_32, in_64); | ||
238 | fns[vece](t_ptr, t_desc, t_32); | ||
239 | tcg_temp_free_i32(t_32); | ||
240 | + } else { | 91 | + } else { |
241 | + if (vece == MO_8) { | 92 | ctx->z_mask = MAKE_64BIT_MASK(0, width); |
242 | + in_c &= 0xff; | 93 | - ctx->s_mask <<= 1; |
243 | + } else if (vece == MO_16) { | ||
244 | + in_c &= 0xffff; | ||
245 | + } | ||
246 | + t_32 = tcg_constant_i32(in_c); | ||
247 | + fns[vece](t_ptr, t_desc, t_32); | ||
248 | } | 94 | } |
249 | } | 95 | } |
250 | 96 | ||
251 | tcg_temp_free_ptr(t_ptr); | 97 | @@ -XXX,XX +XXX,XX @@ static bool fold_setcond(OptContext *ctx, TCGOp *op) |
252 | - tcg_temp_free_i32(t_desc); | 98 | fold_setcond_tst_pow2(ctx, op, false); |
253 | return; | 99 | |
254 | 100 | ctx->z_mask = 1; | |
255 | done: | 101 | - ctx->s_mask = smask_from_zmask(1); |
256 | @@ -XXX,XX +XXX,XX @@ void tcg_gen_gvec_2i(uint32_t dofs, uint32_t aofs, uint32_t oprsz, | 102 | return false; |
257 | if (g->fno) { | ||
258 | tcg_gen_gvec_2_ool(dofs, aofs, oprsz, maxsz, c, g->fno); | ||
259 | } else { | ||
260 | - TCGv_i64 tcg_c = tcg_const_i64(c); | ||
261 | + TCGv_i64 tcg_c = tcg_constant_i64(c); | ||
262 | tcg_gen_gvec_2i_ool(dofs, aofs, tcg_c, oprsz, | ||
263 | maxsz, c, g->fnoi); | ||
264 | - tcg_temp_free_i64(tcg_c); | ||
265 | } | ||
266 | oprsz = maxsz; | ||
267 | } | ||
268 | @@ -XXX,XX +XXX,XX @@ static void gen_addv_mask(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b, TCGv_i64 m) | ||
269 | |||
270 | void tcg_gen_vec_add8_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) | ||
271 | { | ||
272 | - TCGv_i64 m = tcg_const_i64(dup_const(MO_8, 0x80)); | ||
273 | + TCGv_i64 m = tcg_constant_i64(dup_const(MO_8, 0x80)); | ||
274 | gen_addv_mask(d, a, b, m); | ||
275 | - tcg_temp_free_i64(m); | ||
276 | } | 103 | } |
277 | 104 | ||
278 | void tcg_gen_vec_add16_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) | 105 | @@ -XXX,XX +XXX,XX @@ static bool fold_setcond2(OptContext *ctx, TCGOp *op) |
279 | { | 106 | } |
280 | - TCGv_i64 m = tcg_const_i64(dup_const(MO_16, 0x8000)); | 107 | |
281 | + TCGv_i64 m = tcg_constant_i64(dup_const(MO_16, 0x8000)); | 108 | ctx->z_mask = 1; |
282 | gen_addv_mask(d, a, b, m); | 109 | - ctx->s_mask = smask_from_zmask(1); |
283 | - tcg_temp_free_i64(m); | 110 | return false; |
284 | } | 111 | |
285 | 112 | do_setcond_const: | |
286 | void tcg_gen_vec_add32_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) | 113 | @@ -XXX,XX +XXX,XX @@ static bool fold_tcg_ld(OptContext *ctx, TCGOp *op) |
287 | @@ -XXX,XX +XXX,XX @@ void tcg_gen_gvec_adds(unsigned vece, uint32_t dofs, uint32_t aofs, | 114 | break; |
288 | void tcg_gen_gvec_addi(unsigned vece, uint32_t dofs, uint32_t aofs, | 115 | CASE_OP_32_64(ld8u): |
289 | int64_t c, uint32_t oprsz, uint32_t maxsz) | 116 | ctx->z_mask = MAKE_64BIT_MASK(0, 8); |
290 | { | 117 | - ctx->s_mask = MAKE_64BIT_MASK(9, 55); |
291 | - TCGv_i64 tmp = tcg_const_i64(c); | 118 | break; |
292 | + TCGv_i64 tmp = tcg_constant_i64(c); | 119 | CASE_OP_32_64(ld16s): |
293 | tcg_gen_gvec_adds(vece, dofs, aofs, tmp, oprsz, maxsz); | 120 | ctx->s_mask = MAKE_64BIT_MASK(16, 48); |
294 | - tcg_temp_free_i64(tmp); | 121 | break; |
295 | } | 122 | CASE_OP_32_64(ld16u): |
296 | 123 | ctx->z_mask = MAKE_64BIT_MASK(0, 16); | |
297 | static const TCGOpcode vecop_list_sub[] = { INDEX_op_sub_vec, 0 }; | 124 | - ctx->s_mask = MAKE_64BIT_MASK(17, 47); |
298 | @@ -XXX,XX +XXX,XX @@ static void gen_subv_mask(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b, TCGv_i64 m) | 125 | break; |
299 | 126 | case INDEX_op_ld32s_i64: | |
300 | void tcg_gen_vec_sub8_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) | 127 | ctx->s_mask = MAKE_64BIT_MASK(32, 32); |
301 | { | 128 | break; |
302 | - TCGv_i64 m = tcg_const_i64(dup_const(MO_8, 0x80)); | 129 | case INDEX_op_ld32u_i64: |
303 | + TCGv_i64 m = tcg_constant_i64(dup_const(MO_8, 0x80)); | 130 | ctx->z_mask = MAKE_64BIT_MASK(0, 32); |
304 | gen_subv_mask(d, a, b, m); | 131 | - ctx->s_mask = MAKE_64BIT_MASK(33, 31); |
305 | - tcg_temp_free_i64(m); | 132 | break; |
306 | } | 133 | default: |
307 | 134 | g_assert_not_reached(); | |
308 | void tcg_gen_vec_sub16_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) | ||
309 | { | ||
310 | - TCGv_i64 m = tcg_const_i64(dup_const(MO_16, 0x8000)); | ||
311 | + TCGv_i64 m = tcg_constant_i64(dup_const(MO_16, 0x8000)); | ||
312 | gen_subv_mask(d, a, b, m); | ||
313 | - tcg_temp_free_i64(m); | ||
314 | } | ||
315 | |||
316 | void tcg_gen_vec_sub32_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) | ||
317 | @@ -XXX,XX +XXX,XX @@ void tcg_gen_gvec_muls(unsigned vece, uint32_t dofs, uint32_t aofs, | ||
318 | void tcg_gen_gvec_muli(unsigned vece, uint32_t dofs, uint32_t aofs, | ||
319 | int64_t c, uint32_t oprsz, uint32_t maxsz) | ||
320 | { | ||
321 | - TCGv_i64 tmp = tcg_const_i64(c); | ||
322 | + TCGv_i64 tmp = tcg_constant_i64(c); | ||
323 | tcg_gen_gvec_muls(vece, dofs, aofs, tmp, oprsz, maxsz); | ||
324 | - tcg_temp_free_i64(tmp); | ||
325 | } | ||
326 | |||
327 | void tcg_gen_gvec_ssadd(unsigned vece, uint32_t dofs, uint32_t aofs, | ||
328 | @@ -XXX,XX +XXX,XX @@ void tcg_gen_gvec_sssub(unsigned vece, uint32_t dofs, uint32_t aofs, | ||
329 | |||
330 | static void tcg_gen_usadd_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b) | ||
331 | { | ||
332 | - TCGv_i32 max = tcg_const_i32(-1); | ||
333 | + TCGv_i32 max = tcg_constant_i32(-1); | ||
334 | tcg_gen_add_i32(d, a, b); | ||
335 | tcg_gen_movcond_i32(TCG_COND_LTU, d, d, a, max, d); | ||
336 | - tcg_temp_free_i32(max); | ||
337 | } | ||
338 | |||
339 | static void tcg_gen_usadd_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) | ||
340 | { | ||
341 | - TCGv_i64 max = tcg_const_i64(-1); | ||
342 | + TCGv_i64 max = tcg_constant_i64(-1); | ||
343 | tcg_gen_add_i64(d, a, b); | ||
344 | tcg_gen_movcond_i64(TCG_COND_LTU, d, d, a, max, d); | ||
345 | - tcg_temp_free_i64(max); | ||
346 | } | ||
347 | |||
348 | void tcg_gen_gvec_usadd(unsigned vece, uint32_t dofs, uint32_t aofs, | ||
349 | @@ -XXX,XX +XXX,XX @@ void tcg_gen_gvec_usadd(unsigned vece, uint32_t dofs, uint32_t aofs, | ||
350 | |||
351 | static void tcg_gen_ussub_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b) | ||
352 | { | ||
353 | - TCGv_i32 min = tcg_const_i32(0); | ||
354 | + TCGv_i32 min = tcg_constant_i32(0); | ||
355 | tcg_gen_sub_i32(d, a, b); | ||
356 | tcg_gen_movcond_i32(TCG_COND_LTU, d, a, b, min, d); | ||
357 | - tcg_temp_free_i32(min); | ||
358 | } | ||
359 | |||
360 | static void tcg_gen_ussub_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) | ||
361 | { | ||
362 | - TCGv_i64 min = tcg_const_i64(0); | ||
363 | + TCGv_i64 min = tcg_constant_i64(0); | ||
364 | tcg_gen_sub_i64(d, a, b); | ||
365 | tcg_gen_movcond_i64(TCG_COND_LTU, d, a, b, min, d); | ||
366 | - tcg_temp_free_i64(min); | ||
367 | } | ||
368 | |||
369 | void tcg_gen_gvec_ussub(unsigned vece, uint32_t dofs, uint32_t aofs, | ||
370 | @@ -XXX,XX +XXX,XX @@ static void gen_negv_mask(TCGv_i64 d, TCGv_i64 b, TCGv_i64 m) | ||
371 | |||
372 | void tcg_gen_vec_neg8_i64(TCGv_i64 d, TCGv_i64 b) | ||
373 | { | ||
374 | - TCGv_i64 m = tcg_const_i64(dup_const(MO_8, 0x80)); | ||
375 | + TCGv_i64 m = tcg_constant_i64(dup_const(MO_8, 0x80)); | ||
376 | gen_negv_mask(d, b, m); | ||
377 | - tcg_temp_free_i64(m); | ||
378 | } | ||
379 | |||
380 | void tcg_gen_vec_neg16_i64(TCGv_i64 d, TCGv_i64 b) | ||
381 | { | ||
382 | - TCGv_i64 m = tcg_const_i64(dup_const(MO_16, 0x8000)); | ||
383 | + TCGv_i64 m = tcg_constant_i64(dup_const(MO_16, 0x8000)); | ||
384 | gen_negv_mask(d, b, m); | ||
385 | - tcg_temp_free_i64(m); | ||
386 | } | ||
387 | |||
388 | void tcg_gen_vec_neg32_i64(TCGv_i64 d, TCGv_i64 b) | ||
389 | @@ -XXX,XX +XXX,XX @@ void tcg_gen_gvec_ands(unsigned vece, uint32_t dofs, uint32_t aofs, | ||
390 | void tcg_gen_gvec_andi(unsigned vece, uint32_t dofs, uint32_t aofs, | ||
391 | int64_t c, uint32_t oprsz, uint32_t maxsz) | ||
392 | { | ||
393 | - TCGv_i64 tmp = tcg_const_i64(dup_const(vece, c)); | ||
394 | + TCGv_i64 tmp = tcg_constant_i64(dup_const(vece, c)); | ||
395 | tcg_gen_gvec_2s(dofs, aofs, oprsz, maxsz, tmp, &gop_ands); | ||
396 | - tcg_temp_free_i64(tmp); | ||
397 | } | ||
398 | |||
399 | static const GVecGen2s gop_xors = { | ||
400 | @@ -XXX,XX +XXX,XX @@ void tcg_gen_gvec_xors(unsigned vece, uint32_t dofs, uint32_t aofs, | ||
401 | void tcg_gen_gvec_xori(unsigned vece, uint32_t dofs, uint32_t aofs, | ||
402 | int64_t c, uint32_t oprsz, uint32_t maxsz) | ||
403 | { | ||
404 | - TCGv_i64 tmp = tcg_const_i64(dup_const(vece, c)); | ||
405 | + TCGv_i64 tmp = tcg_constant_i64(dup_const(vece, c)); | ||
406 | tcg_gen_gvec_2s(dofs, aofs, oprsz, maxsz, tmp, &gop_xors); | ||
407 | - tcg_temp_free_i64(tmp); | ||
408 | } | ||
409 | |||
410 | static const GVecGen2s gop_ors = { | ||
411 | @@ -XXX,XX +XXX,XX @@ void tcg_gen_gvec_ors(unsigned vece, uint32_t dofs, uint32_t aofs, | ||
412 | void tcg_gen_gvec_ori(unsigned vece, uint32_t dofs, uint32_t aofs, | ||
413 | int64_t c, uint32_t oprsz, uint32_t maxsz) | ||
414 | { | ||
415 | - TCGv_i64 tmp = tcg_const_i64(dup_const(vece, c)); | ||
416 | + TCGv_i64 tmp = tcg_constant_i64(dup_const(vece, c)); | ||
417 | tcg_gen_gvec_2s(dofs, aofs, oprsz, maxsz, tmp, &gop_ors); | ||
418 | - tcg_temp_free_i64(tmp); | ||
419 | } | ||
420 | |||
421 | void tcg_gen_vec_shl8i_i64(TCGv_i64 d, TCGv_i64 a, int64_t c) | ||
422 | @@ -XXX,XX +XXX,XX @@ static void tcg_gen_shlv_mod_vec(unsigned vece, TCGv_vec d, | ||
423 | TCGv_vec a, TCGv_vec b) | ||
424 | { | ||
425 | TCGv_vec t = tcg_temp_new_vec_matching(d); | ||
426 | + TCGv_vec m = tcg_constant_vec_matching(d, vece, (8 << vece) - 1); | ||
427 | |||
428 | - tcg_gen_dupi_vec(vece, t, (8 << vece) - 1); | ||
429 | - tcg_gen_and_vec(vece, t, t, b); | ||
430 | + tcg_gen_and_vec(vece, t, b, m); | ||
431 | tcg_gen_shlv_vec(vece, d, a, t); | ||
432 | tcg_temp_free_vec(t); | ||
433 | } | ||
434 | @@ -XXX,XX +XXX,XX @@ static void tcg_gen_shrv_mod_vec(unsigned vece, TCGv_vec d, | ||
435 | TCGv_vec a, TCGv_vec b) | ||
436 | { | ||
437 | TCGv_vec t = tcg_temp_new_vec_matching(d); | ||
438 | + TCGv_vec m = tcg_constant_vec_matching(d, vece, (8 << vece) - 1); | ||
439 | |||
440 | - tcg_gen_dupi_vec(vece, t, (8 << vece) - 1); | ||
441 | - tcg_gen_and_vec(vece, t, t, b); | ||
442 | + tcg_gen_and_vec(vece, t, b, m); | ||
443 | tcg_gen_shrv_vec(vece, d, a, t); | ||
444 | tcg_temp_free_vec(t); | ||
445 | } | ||
446 | @@ -XXX,XX +XXX,XX @@ static void tcg_gen_sarv_mod_vec(unsigned vece, TCGv_vec d, | ||
447 | TCGv_vec a, TCGv_vec b) | ||
448 | { | ||
449 | TCGv_vec t = tcg_temp_new_vec_matching(d); | ||
450 | + TCGv_vec m = tcg_constant_vec_matching(d, vece, (8 << vece) - 1); | ||
451 | |||
452 | - tcg_gen_dupi_vec(vece, t, (8 << vece) - 1); | ||
453 | - tcg_gen_and_vec(vece, t, t, b); | ||
454 | + tcg_gen_and_vec(vece, t, b, m); | ||
455 | tcg_gen_sarv_vec(vece, d, a, t); | ||
456 | tcg_temp_free_vec(t); | ||
457 | } | ||
458 | @@ -XXX,XX +XXX,XX @@ static void tcg_gen_rotlv_mod_vec(unsigned vece, TCGv_vec d, | ||
459 | TCGv_vec a, TCGv_vec b) | ||
460 | { | ||
461 | TCGv_vec t = tcg_temp_new_vec_matching(d); | ||
462 | + TCGv_vec m = tcg_constant_vec_matching(d, vece, (8 << vece) - 1); | ||
463 | |||
464 | - tcg_gen_dupi_vec(vece, t, (8 << vece) - 1); | ||
465 | - tcg_gen_and_vec(vece, t, t, b); | ||
466 | + tcg_gen_and_vec(vece, t, b, m); | ||
467 | tcg_gen_rotlv_vec(vece, d, a, t); | ||
468 | tcg_temp_free_vec(t); | ||
469 | } | ||
470 | @@ -XXX,XX +XXX,XX @@ static void tcg_gen_rotrv_mod_vec(unsigned vece, TCGv_vec d, | ||
471 | TCGv_vec a, TCGv_vec b) | ||
472 | { | ||
473 | TCGv_vec t = tcg_temp_new_vec_matching(d); | ||
474 | + TCGv_vec m = tcg_constant_vec_matching(d, vece, (8 << vece) - 1); | ||
475 | |||
476 | - tcg_gen_dupi_vec(vece, t, (8 << vece) - 1); | ||
477 | - tcg_gen_and_vec(vece, t, t, b); | ||
478 | + tcg_gen_and_vec(vece, t, b, m); | ||
479 | tcg_gen_rotrv_vec(vece, d, a, t); | ||
480 | tcg_temp_free_vec(t); | ||
481 | } | ||
482 | diff --git a/tcg/tcg.c b/tcg/tcg.c | ||
483 | index XXXXXXX..XXXXXXX 100644 | ||
484 | --- a/tcg/tcg.c | ||
485 | +++ b/tcg/tcg.c | ||
486 | @@ -XXX,XX +XXX,XX @@ TCGv_vec tcg_constant_vec(TCGType type, unsigned vece, int64_t val) | ||
487 | return temp_tcgv_vec(tcg_constant_internal(type, val)); | ||
488 | } | ||
489 | |||
490 | +TCGv_vec tcg_constant_vec_matching(TCGv_vec match, unsigned vece, int64_t val) | ||
491 | +{ | ||
492 | + TCGTemp *t = tcgv_vec_temp(match); | ||
493 | + | ||
494 | + tcg_debug_assert(t->temp_allocated != 0); | ||
495 | + return tcg_constant_vec(t->base_type, vece, val); | ||
496 | +} | ||
497 | + | ||
498 | TCGv_i32 tcg_const_i32(int32_t val) | ||
499 | { | ||
500 | TCGv_i32 t0; | ||
501 | -- | 135 | -- |
502 | 2.25.1 | 136 | 2.43.0 |
503 | |||
504 | diff view generated by jsdifflib |
1 | This propagates the extended value of TCGTemp.val that we did before. | 1 | Change the representation from sign bit repetitions to all bits equal |
---|---|---|---|
2 | In addition, it will be required for vector constants. | 2 | to the sign bit, including the sign bit itself. |
3 | 3 | ||
4 | The previous format has a problem in that it is difficult to recreate | ||
5 | a valid sign mask after a shift operation: the "repetitions" part of | ||
6 | the previous format meant that applying the same shift as for the value | ||
7 | lead to an off-by-one value. | ||
8 | |||
9 | The new format, including the sign bit itself, means that the sign mask | ||
10 | can be manipulated in exactly the same way as the value, canonicalization | ||
11 | is easier. | ||
12 | |||
13 | Canonicalize the s_mask in fold_masks_zs, rather than requiring callers | ||
14 | to do so. Treat 0 as a non-canonical but typeless input for no sign | ||
15 | information, which will be reset as appropriate for the data type. | ||
16 | We can easily fold in the data from z_mask while canonicalizing. | ||
17 | |||
18 | Temporarily disable optimizations using s_mask while each operation is | ||
19 | converted to use fold_masks_zs and to the new form. | ||
20 | |||
21 | Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> | ||
4 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 22 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
5 | --- | 23 | --- |
6 | tcg/optimize.c | 40 +++++++++++++++++++++------------------- | 24 | tcg/optimize.c | 64 ++++++++++++-------------------------------------- |
7 | 1 file changed, 21 insertions(+), 19 deletions(-) | 25 | 1 file changed, 15 insertions(+), 49 deletions(-) |
8 | 26 | ||
9 | diff --git a/tcg/optimize.c b/tcg/optimize.c | 27 | diff --git a/tcg/optimize.c b/tcg/optimize.c |
10 | index XXXXXXX..XXXXXXX 100644 | 28 | index XXXXXXX..XXXXXXX 100644 |
11 | --- a/tcg/optimize.c | 29 | --- a/tcg/optimize.c |
12 | +++ b/tcg/optimize.c | 30 | +++ b/tcg/optimize.c |
13 | @@ -XXX,XX +XXX,XX @@ typedef struct TempOptInfo { | 31 | @@ -XXX,XX +XXX,XX @@ typedef struct TempOptInfo { |
14 | bool is_const; | 32 | QSIMPLEQ_HEAD(, MemCopyInfo) mem_copy; |
15 | TCGTemp *prev_copy; | 33 | uint64_t val; |
16 | TCGTemp *next_copy; | 34 | uint64_t z_mask; /* mask bit is 0 if and only if value bit is 0 */ |
17 | - tcg_target_ulong val; | 35 | - uint64_t s_mask; /* a left-aligned mask of clrsb(value) bits. */ |
18 | - tcg_target_ulong mask; | 36 | + uint64_t s_mask; /* mask bit is 1 if value bit matches msb */ |
19 | + uint64_t val; | ||
20 | + uint64_t mask; | ||
21 | } TempOptInfo; | 37 | } TempOptInfo; |
22 | 38 | ||
39 | typedef struct OptContext { | ||
40 | @@ -XXX,XX +XXX,XX @@ typedef struct OptContext { | ||
41 | |||
42 | /* In flight values from optimization. */ | ||
43 | uint64_t z_mask; /* mask bit is 0 iff value bit is 0 */ | ||
44 | - uint64_t s_mask; /* mask of clrsb(value) bits */ | ||
45 | + uint64_t s_mask; /* mask bit is 1 if value bit matches msb */ | ||
46 | TCGType type; | ||
47 | } OptContext; | ||
48 | |||
49 | -/* Calculate the smask for a specific value. */ | ||
50 | -static uint64_t smask_from_value(uint64_t value) | ||
51 | -{ | ||
52 | - int rep = clrsb64(value); | ||
53 | - return ~(~0ull >> rep); | ||
54 | -} | ||
55 | - | ||
56 | -/* | ||
57 | - * Calculate the smask for a given set of known-zeros. | ||
58 | - * If there are lots of zeros on the left, we can consider the remainder | ||
59 | - * an unsigned field, and thus the corresponding signed field is one bit | ||
60 | - * larger. | ||
61 | - */ | ||
62 | -static uint64_t smask_from_zmask(uint64_t zmask) | ||
63 | -{ | ||
64 | - /* | ||
65 | - * Only the 0 bits are significant for zmask, thus the msb itself | ||
66 | - * must be zero, else we have no sign information. | ||
67 | - */ | ||
68 | - int rep = clz64(zmask); | ||
69 | - if (rep == 0) { | ||
70 | - return 0; | ||
71 | - } | ||
72 | - rep -= 1; | ||
73 | - return ~(~0ull >> rep); | ||
74 | -} | ||
75 | - | ||
76 | -/* | ||
77 | - * Recreate a properly left-aligned smask after manipulation. | ||
78 | - * Some bit-shuffling, particularly shifts and rotates, may | ||
79 | - * retain sign bits on the left, but may scatter disconnected | ||
80 | - * sign bits on the right. Retain only what remains to the left. | ||
81 | - */ | ||
82 | -static uint64_t smask_from_smask(int64_t smask) | ||
83 | -{ | ||
84 | - /* Only the 1 bits are significant for smask */ | ||
85 | - return smask_from_zmask(~smask); | ||
86 | -} | ||
87 | - | ||
23 | static inline TempOptInfo *ts_info(TCGTemp *ts) | 88 | static inline TempOptInfo *ts_info(TCGTemp *ts) |
24 | @@ -XXX,XX +XXX,XX @@ static bool args_are_copies(TCGArg arg1, TCGArg arg2) | ||
25 | return ts_are_copies(arg_temp(arg1), arg_temp(arg2)); | ||
26 | } | ||
27 | |||
28 | -static void tcg_opt_gen_movi(TCGContext *s, TCGOp *op, TCGArg dst, TCGArg val) | ||
29 | +static void tcg_opt_gen_movi(TCGContext *s, TCGOp *op, TCGArg dst, uint64_t val) | ||
30 | { | 89 | { |
31 | const TCGOpDef *def; | 90 | return ts->state_ptr; |
32 | TCGOpcode new_op; | 91 | @@ -XXX,XX +XXX,XX @@ static void init_ts_info(OptContext *ctx, TCGTemp *ts) |
33 | - tcg_target_ulong mask; | 92 | ti->is_const = true; |
34 | + uint64_t mask; | 93 | ti->val = ts->val; |
35 | TempOptInfo *di = arg_info(dst); | 94 | ti->z_mask = ts->val; |
36 | 95 | - ti->s_mask = smask_from_value(ts->val); | |
37 | def = &tcg_op_defs[op->opc]; | 96 | + ti->s_mask = INT64_MIN >> clrsb64(ts->val); |
38 | @@ -XXX,XX +XXX,XX @@ static void tcg_opt_gen_mov(TCGContext *s, TCGOp *op, TCGArg dst, TCGArg src) | 97 | } else { |
39 | const TCGOpDef *def; | 98 | ti->is_const = false; |
40 | TempOptInfo *di; | 99 | ti->z_mask = -1; |
41 | TempOptInfo *si; | 100 | @@ -XXX,XX +XXX,XX @@ static void finish_folding(OptContext *ctx, TCGOp *op) |
42 | - tcg_target_ulong mask; | 101 | */ |
43 | + uint64_t mask; | 102 | if (i == 0) { |
44 | TCGOpcode new_op; | 103 | ts_info(ts)->z_mask = ctx->z_mask; |
45 | 104 | - ts_info(ts)->s_mask = ctx->s_mask; | |
46 | if (ts_are_copies(dst_ts, src_ts)) { | 105 | } |
47 | @@ -XXX,XX +XXX,XX @@ static void tcg_opt_gen_mov(TCGContext *s, TCGOp *op, TCGArg dst, TCGArg src) | ||
48 | } | 106 | } |
49 | } | 107 | } |
50 | 108 | @@ -XXX,XX +XXX,XX @@ static bool fold_const2_commutative(OptContext *ctx, TCGOp *op) | |
51 | -static TCGArg do_constant_folding_2(TCGOpcode op, TCGArg x, TCGArg y) | 109 | * The passed s_mask may be augmented by z_mask. |
52 | +static uint64_t do_constant_folding_2(TCGOpcode op, uint64_t x, uint64_t y) | 110 | */ |
111 | static bool fold_masks_zs(OptContext *ctx, TCGOp *op, | ||
112 | - uint64_t z_mask, uint64_t s_mask) | ||
113 | + uint64_t z_mask, int64_t s_mask) | ||
53 | { | 114 | { |
54 | uint64_t l64, h64; | 115 | const TCGOpDef *def = &tcg_op_defs[op->opc]; |
55 | 116 | TCGTemp *ts; | |
56 | @@ -XXX,XX +XXX,XX @@ static TCGArg do_constant_folding_2(TCGOpcode op, TCGArg x, TCGArg y) | 117 | TempOptInfo *ti; |
118 | + int rep; | ||
119 | |||
120 | /* Only single-output opcodes are supported here. */ | ||
121 | tcg_debug_assert(def->nb_oargs == 1); | ||
122 | @@ -XXX,XX +XXX,XX @@ static bool fold_masks_zs(OptContext *ctx, TCGOp *op, | ||
123 | */ | ||
124 | if (ctx->type == TCG_TYPE_I32) { | ||
125 | z_mask = (int32_t)z_mask; | ||
126 | - s_mask |= MAKE_64BIT_MASK(32, 32); | ||
127 | + s_mask |= INT32_MIN; | ||
57 | } | 128 | } |
129 | |||
130 | if (z_mask == 0) { | ||
131 | @@ -XXX,XX +XXX,XX @@ static bool fold_masks_zs(OptContext *ctx, TCGOp *op, | ||
132 | |||
133 | ti = ts_info(ts); | ||
134 | ti->z_mask = z_mask; | ||
135 | - ti->s_mask = s_mask | smask_from_zmask(z_mask); | ||
136 | + | ||
137 | + /* Canonicalize s_mask and incorporate data from z_mask. */ | ||
138 | + rep = clz64(~s_mask); | ||
139 | + rep = MAX(rep, clz64(z_mask)); | ||
140 | + rep = MAX(rep - 1, 0); | ||
141 | + ti->s_mask = INT64_MIN >> rep; | ||
142 | + | ||
143 | return true; | ||
58 | } | 144 | } |
59 | 145 | ||
60 | -static TCGArg do_constant_folding(TCGOpcode op, TCGArg x, TCGArg y) | 146 | @@ -XXX,XX +XXX,XX @@ static bool fold_exts(OptContext *ctx, TCGOp *op) |
61 | +static uint64_t do_constant_folding(TCGOpcode op, uint64_t x, uint64_t y) | 147 | |
62 | { | 148 | ctx->z_mask = z_mask; |
63 | const TCGOpDef *def = &tcg_op_defs[op]; | 149 | ctx->s_mask = s_mask; |
64 | - TCGArg res = do_constant_folding_2(op, x, y); | 150 | - if (!type_change && fold_affected_mask(ctx, op, s_mask & ~s_mask_old)) { |
65 | + uint64_t res = do_constant_folding_2(op, x, y); | 151 | + if (0 && !type_change && fold_affected_mask(ctx, op, s_mask & ~s_mask_old)) { |
66 | if (!(def->flags & TCG_OPF_64BIT)) { | 152 | return true; |
67 | res = (int32_t)res; | ||
68 | } | 153 | } |
69 | @@ -XXX,XX +XXX,XX @@ static bool do_constant_folding_cond_eq(TCGCond c) | 154 | |
70 | static TCGArg do_constant_folding_cond(TCGOpcode op, TCGArg x, | 155 | @@ -XXX,XX +XXX,XX @@ static bool fold_sextract(OptContext *ctx, TCGOp *op) |
71 | TCGArg y, TCGCond c) | 156 | s_mask |= MAKE_64BIT_MASK(len, 64 - len); |
72 | { | 157 | ctx->s_mask = s_mask; |
73 | - tcg_target_ulong xv = arg_info(x)->val; | 158 | |
74 | - tcg_target_ulong yv = arg_info(y)->val; | 159 | - if (pos == 0 && fold_affected_mask(ctx, op, s_mask & ~s_mask_old)) { |
75 | + uint64_t xv = arg_info(x)->val; | 160 | + if (0 && pos == 0 && fold_affected_mask(ctx, op, s_mask & ~s_mask_old)) { |
76 | + uint64_t yv = arg_info(y)->val; | 161 | return true; |
77 | + | 162 | } |
78 | if (arg_is_const(x) && arg_is_const(y)) { | 163 | |
79 | const TCGOpDef *def = &tcg_op_defs[op]; | 164 | @@ -XXX,XX +XXX,XX @@ static bool fold_shift(OptContext *ctx, TCGOp *op) |
80 | tcg_debug_assert(!(def->flags & TCG_OPF_VECTOR)); | 165 | ctx->z_mask = do_constant_folding(op->opc, ctx->type, z_mask, sh); |
81 | @@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s) | 166 | |
82 | infos = tcg_malloc(sizeof(TempOptInfo) * nb_temps); | 167 | s_mask = do_constant_folding(op->opc, ctx->type, s_mask, sh); |
83 | 168 | - ctx->s_mask = smask_from_smask(s_mask); | |
84 | QTAILQ_FOREACH_SAFE(op, &s->ops, link, op_next) { | 169 | |
85 | - tcg_target_ulong mask, partmask, affected; | 170 | return fold_masks(ctx, op); |
86 | + uint64_t mask, partmask, affected, tmp; | 171 | } |
87 | int nb_oargs, nb_iargs, i; | ||
88 | - TCGArg tmp; | ||
89 | TCGOpcode opc = op->opc; | ||
90 | const TCGOpDef *def = &tcg_op_defs[opc]; | ||
91 | |||
92 | @@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s) | ||
93 | |||
94 | CASE_OP_32_64(extract2): | ||
95 | if (arg_is_const(op->args[1]) && arg_is_const(op->args[2])) { | ||
96 | - TCGArg v1 = arg_info(op->args[1])->val; | ||
97 | - TCGArg v2 = arg_info(op->args[2])->val; | ||
98 | + uint64_t v1 = arg_info(op->args[1])->val; | ||
99 | + uint64_t v2 = arg_info(op->args[2])->val; | ||
100 | + int shr = op->args[3]; | ||
101 | |||
102 | if (opc == INDEX_op_extract2_i64) { | ||
103 | - tmp = (v1 >> op->args[3]) | (v2 << (64 - op->args[3])); | ||
104 | + tmp = (v1 >> shr) | (v2 << (64 - shr)); | ||
105 | } else { | ||
106 | - tmp = (int32_t)(((uint32_t)v1 >> op->args[3]) | | ||
107 | - ((uint32_t)v2 << (32 - op->args[3]))); | ||
108 | + tmp = (int32_t)(((uint32_t)v1 >> shr) | | ||
109 | + ((uint32_t)v2 << (32 - shr))); | ||
110 | } | ||
111 | tcg_opt_gen_movi(s, op, op->args[0], tmp); | ||
112 | break; | ||
113 | @@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s) | ||
114 | break; | ||
115 | } | ||
116 | if (arg_is_const(op->args[3]) && arg_is_const(op->args[4])) { | ||
117 | - tcg_target_ulong tv = arg_info(op->args[3])->val; | ||
118 | - tcg_target_ulong fv = arg_info(op->args[4])->val; | ||
119 | + uint64_t tv = arg_info(op->args[3])->val; | ||
120 | + uint64_t fv = arg_info(op->args[4])->val; | ||
121 | TCGCond cond = op->args[5]; | ||
122 | + | ||
123 | if (fv == 1 && tv == 0) { | ||
124 | cond = tcg_invert_cond(cond); | ||
125 | } else if (!(tv == 1 && fv == 0)) { | ||
126 | -- | 172 | -- |
127 | 2.25.1 | 173 | 2.43.0 |
128 | |||
129 | diff view generated by jsdifflib |
1 | Because we now store uint64_t in TCGTemp, we can now always | 1 | Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> |
---|---|---|---|
2 | store the full 64-bit duplicate immediate. So remove the | ||
3 | difference between 32- and 64-bit hosts. | ||
4 | |||
5 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 2 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
6 | --- | 3 | --- |
7 | tcg/optimize.c | 9 ++++----- | 4 | tcg/optimize.c | 9 +++++---- |
8 | tcg/tcg-op-vec.c | 39 ++++++++++----------------------------- | 5 | 1 file changed, 5 insertions(+), 4 deletions(-) |
9 | tcg/tcg.c | 7 +------ | ||
10 | 3 files changed, 15 insertions(+), 40 deletions(-) | ||
11 | 6 | ||
12 | diff --git a/tcg/optimize.c b/tcg/optimize.c | 7 | diff --git a/tcg/optimize.c b/tcg/optimize.c |
13 | index XXXXXXX..XXXXXXX 100644 | 8 | index XXXXXXX..XXXXXXX 100644 |
14 | --- a/tcg/optimize.c | 9 | --- a/tcg/optimize.c |
15 | +++ b/tcg/optimize.c | 10 | +++ b/tcg/optimize.c |
16 | @@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s) | 11 | @@ -XXX,XX +XXX,XX @@ static void finish_ebb(OptContext *ctx) |
17 | case INDEX_op_dup2_vec: | 12 | remove_mem_copy_all(ctx); |
18 | assert(TCG_TARGET_REG_BITS == 32); | 13 | } |
19 | if (arg_is_const(op->args[1]) && arg_is_const(op->args[2])) { | 14 | |
20 | - tmp = arg_info(op->args[1])->val; | 15 | -static void finish_folding(OptContext *ctx, TCGOp *op) |
21 | - if (tmp == arg_info(op->args[2])->val) { | 16 | +static bool finish_folding(OptContext *ctx, TCGOp *op) |
22 | - tcg_opt_gen_movi(s, &temps_used, op, op->args[0], tmp); | 17 | { |
23 | - break; | 18 | const TCGOpDef *def = &tcg_op_defs[op->opc]; |
24 | - } | 19 | int i, nb_oargs; |
25 | + tcg_opt_gen_movi(s, &temps_used, op, op->args[0], | 20 | @@ -XXX,XX +XXX,XX @@ static void finish_folding(OptContext *ctx, TCGOp *op) |
26 | + deposit64(arg_info(op->args[1])->val, 32, 32, | 21 | ts_info(ts)->z_mask = ctx->z_mask; |
27 | + arg_info(op->args[2])->val)); | 22 | } |
28 | + break; | ||
29 | } else if (args_are_copies(op->args[1], op->args[2])) { | ||
30 | op->opc = INDEX_op_dup_vec; | ||
31 | TCGOP_VECE(op) = MO_32; | ||
32 | diff --git a/tcg/tcg-op-vec.c b/tcg/tcg-op-vec.c | ||
33 | index XXXXXXX..XXXXXXX 100644 | ||
34 | --- a/tcg/tcg-op-vec.c | ||
35 | +++ b/tcg/tcg-op-vec.c | ||
36 | @@ -XXX,XX +XXX,XX @@ void tcg_gen_mov_vec(TCGv_vec r, TCGv_vec a) | ||
37 | } | 23 | } |
24 | + return true; | ||
38 | } | 25 | } |
39 | 26 | ||
40 | -#define MO_REG (TCG_TARGET_REG_BITS == 64 ? MO_64 : MO_32) | 27 | /* |
41 | - | 28 | @@ -XXX,XX +XXX,XX @@ static bool fold_add(OptContext *ctx, TCGOp *op) |
42 | -static void do_dupi_vec(TCGv_vec r, unsigned vece, TCGArg a) | 29 | fold_xi_to_x(ctx, op, 0)) { |
43 | -{ | 30 | return true; |
44 | - TCGTemp *rt = tcgv_vec_temp(r); | 31 | } |
45 | - vec_gen_2(INDEX_op_dupi_vec, rt->base_type, vece, temp_arg(rt), a); | 32 | - return false; |
46 | -} | 33 | + return finish_folding(ctx, op); |
47 | - | ||
48 | TCGv_vec tcg_const_zeros_vec(TCGType type) | ||
49 | { | ||
50 | TCGv_vec ret = tcg_temp_new_vec(type); | ||
51 | - do_dupi_vec(ret, MO_REG, 0); | ||
52 | + tcg_gen_dupi_vec(MO_64, ret, 0); | ||
53 | return ret; | ||
54 | } | 34 | } |
55 | 35 | ||
56 | TCGv_vec tcg_const_ones_vec(TCGType type) | 36 | /* We cannot as yet do_constant_folding with vectors. */ |
57 | { | 37 | @@ -XXX,XX +XXX,XX @@ static bool fold_add_vec(OptContext *ctx, TCGOp *op) |
58 | TCGv_vec ret = tcg_temp_new_vec(type); | 38 | fold_xi_to_x(ctx, op, 0)) { |
59 | - do_dupi_vec(ret, MO_REG, -1); | 39 | return true; |
60 | + tcg_gen_dupi_vec(MO_64, ret, -1); | 40 | } |
61 | return ret; | 41 | - return false; |
42 | + return finish_folding(ctx, op); | ||
62 | } | 43 | } |
63 | 44 | ||
64 | @@ -XXX,XX +XXX,XX @@ TCGv_vec tcg_const_ones_vec_matching(TCGv_vec m) | 45 | static bool fold_addsub2(OptContext *ctx, TCGOp *op, bool add) |
65 | 46 | @@ -XXX,XX +XXX,XX @@ static bool fold_addsub2(OptContext *ctx, TCGOp *op, bool add) | |
66 | void tcg_gen_dup64i_vec(TCGv_vec r, uint64_t a) | 47 | op->args[4] = arg_new_constant(ctx, bl); |
67 | { | 48 | op->args[5] = arg_new_constant(ctx, bh); |
68 | - if (TCG_TARGET_REG_BITS == 64) { | 49 | } |
69 | - do_dupi_vec(r, MO_64, a); | 50 | - return false; |
70 | - } else if (a == dup_const(MO_32, a)) { | 51 | + return finish_folding(ctx, op); |
71 | - do_dupi_vec(r, MO_32, a); | ||
72 | - } else { | ||
73 | - TCGv_i64 c = tcg_const_i64(a); | ||
74 | - tcg_gen_dup_i64_vec(MO_64, r, c); | ||
75 | - tcg_temp_free_i64(c); | ||
76 | - } | ||
77 | + tcg_gen_dupi_vec(MO_64, r, a); | ||
78 | } | 52 | } |
79 | 53 | ||
80 | void tcg_gen_dup32i_vec(TCGv_vec r, uint32_t a) | 54 | static bool fold_add2(OptContext *ctx, TCGOp *op) |
81 | { | ||
82 | - do_dupi_vec(r, MO_REG, dup_const(MO_32, a)); | ||
83 | + tcg_gen_dupi_vec(MO_32, r, a); | ||
84 | } | ||
85 | |||
86 | void tcg_gen_dup16i_vec(TCGv_vec r, uint32_t a) | ||
87 | { | ||
88 | - do_dupi_vec(r, MO_REG, dup_const(MO_16, a)); | ||
89 | + tcg_gen_dupi_vec(MO_16, r, a); | ||
90 | } | ||
91 | |||
92 | void tcg_gen_dup8i_vec(TCGv_vec r, uint32_t a) | ||
93 | { | ||
94 | - do_dupi_vec(r, MO_REG, dup_const(MO_8, a)); | ||
95 | + tcg_gen_dupi_vec(MO_8, r, a); | ||
96 | } | ||
97 | |||
98 | void tcg_gen_dupi_vec(unsigned vece, TCGv_vec r, uint64_t a) | ||
99 | { | ||
100 | - if (vece == MO_64) { | ||
101 | - tcg_gen_dup64i_vec(r, a); | ||
102 | - } else { | ||
103 | - do_dupi_vec(r, MO_REG, dup_const(vece, a)); | ||
104 | - } | ||
105 | + TCGTemp *rt = tcgv_vec_temp(r); | ||
106 | + tcg_gen_mov_vec(r, tcg_constant_vec(rt->base_type, vece, a)); | ||
107 | } | ||
108 | |||
109 | void tcg_gen_dup_i64_vec(unsigned vece, TCGv_vec r, TCGv_i64 a) | ||
110 | @@ -XXX,XX +XXX,XX @@ void tcg_gen_abs_vec(unsigned vece, TCGv_vec r, TCGv_vec a) | ||
111 | if (tcg_can_emit_vec_op(INDEX_op_sari_vec, type, vece) > 0) { | ||
112 | tcg_gen_sari_vec(vece, t, a, (8 << vece) - 1); | ||
113 | } else { | ||
114 | - do_dupi_vec(t, MO_REG, 0); | ||
115 | - tcg_gen_cmp_vec(TCG_COND_LT, vece, t, a, t); | ||
116 | + tcg_gen_cmp_vec(TCG_COND_LT, vece, t, a, | ||
117 | + tcg_constant_vec(type, vece, 0)); | ||
118 | } | ||
119 | tcg_gen_xor_vec(vece, r, a, t); | ||
120 | tcg_gen_sub_vec(vece, r, r, t); | ||
121 | diff --git a/tcg/tcg.c b/tcg/tcg.c | ||
122 | index XXXXXXX..XXXXXXX 100644 | ||
123 | --- a/tcg/tcg.c | ||
124 | +++ b/tcg/tcg.c | ||
125 | @@ -XXX,XX +XXX,XX @@ static void temp_load(TCGContext *s, TCGTemp *ts, TCGRegSet desired_regs, | ||
126 | * The targets will, in general, have to do this search anyway, | ||
127 | * do this generically. | ||
128 | */ | ||
129 | - if (TCG_TARGET_REG_BITS == 32) { | ||
130 | - val = dup_const(MO_32, val); | ||
131 | - vece = MO_32; | ||
132 | - } | ||
133 | if (val == dup_const(MO_8, val)) { | ||
134 | vece = MO_8; | ||
135 | } else if (val == dup_const(MO_16, val)) { | ||
136 | vece = MO_16; | ||
137 | - } else if (TCG_TARGET_REG_BITS == 64 && | ||
138 | - val == dup_const(MO_32, val)) { | ||
139 | + } else if (val == dup_const(MO_32, val)) { | ||
140 | vece = MO_32; | ||
141 | } | ||
142 | |||
143 | -- | 55 | -- |
144 | 2.25.1 | 56 | 2.43.0 |
145 | |||
146 | diff view generated by jsdifflib |
1 | These will hold a single constant for the duration of the TB. | 1 | Introduce ti_is_const, ti_const_val, ti_is_const_val. |
---|---|---|---|
2 | They are hashed, so that each value has one temp across the TB. | ||
3 | |||
4 | Not used yet, this is all infrastructure. | ||
5 | 2 | ||
6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 3 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
7 | --- | 4 | --- |
8 | include/tcg/tcg.h | 24 ++++- | 5 | tcg/optimize.c | 20 +++++++++++++++++--- |
9 | tcg/optimize.c | 13 ++- | 6 | 1 file changed, 17 insertions(+), 3 deletions(-) |
10 | tcg/tcg.c | 224 ++++++++++++++++++++++++++++++++++++---------- | ||
11 | 3 files changed, 211 insertions(+), 50 deletions(-) | ||
12 | 7 | ||
13 | diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h | ||
14 | index XXXXXXX..XXXXXXX 100644 | ||
15 | --- a/include/tcg/tcg.h | ||
16 | +++ b/include/tcg/tcg.h | ||
17 | @@ -XXX,XX +XXX,XX @@ typedef enum TCGTempKind { | ||
18 | TEMP_GLOBAL, | ||
19 | /* Temp is in a fixed register. */ | ||
20 | TEMP_FIXED, | ||
21 | + /* Temp is a fixed constant. */ | ||
22 | + TEMP_CONST, | ||
23 | } TCGTempKind; | ||
24 | |||
25 | typedef struct TCGTemp { | ||
26 | @@ -XXX,XX +XXX,XX @@ struct TCGContext { | ||
27 | QSIMPLEQ_HEAD(, TCGOp) plugin_ops; | ||
28 | #endif | ||
29 | |||
30 | + GHashTable *const_table[TCG_TYPE_COUNT]; | ||
31 | TCGTempSet free_temps[TCG_TYPE_COUNT * 2]; | ||
32 | TCGTemp temps[TCG_MAX_TEMPS]; /* globals first, temps after */ | ||
33 | |||
34 | @@ -XXX,XX +XXX,XX @@ struct TCGContext { | ||
35 | |||
36 | static inline bool temp_readonly(TCGTemp *ts) | ||
37 | { | ||
38 | - return ts->kind == TEMP_FIXED; | ||
39 | + return ts->kind >= TEMP_FIXED; | ||
40 | } | ||
41 | |||
42 | extern TCGContext tcg_init_ctx; | ||
43 | @@ -XXX,XX +XXX,XX @@ TCGOp *tcg_op_insert_after(TCGContext *s, TCGOp *op, TCGOpcode opc); | ||
44 | |||
45 | void tcg_optimize(TCGContext *s); | ||
46 | |||
47 | +/* Allocate a new temporary and initialize it with a constant. */ | ||
48 | TCGv_i32 tcg_const_i32(int32_t val); | ||
49 | TCGv_i64 tcg_const_i64(int64_t val); | ||
50 | TCGv_i32 tcg_const_local_i32(int32_t val); | ||
51 | @@ -XXX,XX +XXX,XX @@ TCGv_vec tcg_const_ones_vec(TCGType); | ||
52 | TCGv_vec tcg_const_zeros_vec_matching(TCGv_vec); | ||
53 | TCGv_vec tcg_const_ones_vec_matching(TCGv_vec); | ||
54 | |||
55 | +/* | ||
56 | + * Locate or create a read-only temporary that is a constant. | ||
57 | + * This kind of temporary need not and should not be freed. | ||
58 | + */ | ||
59 | +TCGTemp *tcg_constant_internal(TCGType type, int64_t val); | ||
60 | + | ||
61 | +static inline TCGv_i32 tcg_constant_i32(int32_t val) | ||
62 | +{ | ||
63 | + return temp_tcgv_i32(tcg_constant_internal(TCG_TYPE_I32, val)); | ||
64 | +} | ||
65 | + | ||
66 | +static inline TCGv_i64 tcg_constant_i64(int64_t val) | ||
67 | +{ | ||
68 | + return temp_tcgv_i64(tcg_constant_internal(TCG_TYPE_I64, val)); | ||
69 | +} | ||
70 | + | ||
71 | +TCGv_vec tcg_constant_vec(TCGType type, unsigned vece, int64_t val); | ||
72 | + | ||
73 | #if UINTPTR_MAX == UINT32_MAX | ||
74 | # define tcg_const_ptr(x) ((TCGv_ptr)tcg_const_i32((intptr_t)(x))) | ||
75 | # define tcg_const_local_ptr(x) ((TCGv_ptr)tcg_const_local_i32((intptr_t)(x))) | ||
76 | diff --git a/tcg/optimize.c b/tcg/optimize.c | 8 | diff --git a/tcg/optimize.c b/tcg/optimize.c |
77 | index XXXXXXX..XXXXXXX 100644 | 9 | index XXXXXXX..XXXXXXX 100644 |
78 | --- a/tcg/optimize.c | 10 | --- a/tcg/optimize.c |
79 | +++ b/tcg/optimize.c | 11 | +++ b/tcg/optimize.c |
80 | @@ -XXX,XX +XXX,XX @@ static void init_ts_info(TempOptInfo *infos, | 12 | @@ -XXX,XX +XXX,XX @@ static inline TempOptInfo *arg_info(TCGArg arg) |
81 | ts->state_ptr = ti; | 13 | return ts_info(arg_temp(arg)); |
82 | ti->next_copy = ts; | ||
83 | ti->prev_copy = ts; | ||
84 | - ti->is_const = false; | ||
85 | - ti->mask = -1; | ||
86 | + if (ts->kind == TEMP_CONST) { | ||
87 | + ti->is_const = true; | ||
88 | + ti->val = ti->mask = ts->val; | ||
89 | + if (TCG_TARGET_REG_BITS > 32 && ts->type == TCG_TYPE_I32) { | ||
90 | + /* High bits of a 32-bit quantity are garbage. */ | ||
91 | + ti->mask |= ~0xffffffffull; | ||
92 | + } | ||
93 | + } else { | ||
94 | + ti->is_const = false; | ||
95 | + ti->mask = -1; | ||
96 | + } | ||
97 | set_bit(idx, temps_used->l); | ||
98 | } | ||
99 | } | 14 | } |
100 | diff --git a/tcg/tcg.c b/tcg/tcg.c | 15 | |
101 | index XXXXXXX..XXXXXXX 100644 | 16 | +static inline bool ti_is_const(TempOptInfo *ti) |
102 | --- a/tcg/tcg.c | ||
103 | +++ b/tcg/tcg.c | ||
104 | @@ -XXX,XX +XXX,XX @@ void tcg_func_start(TCGContext *s) | ||
105 | /* No temps have been previously allocated for size or locality. */ | ||
106 | memset(s->free_temps, 0, sizeof(s->free_temps)); | ||
107 | |||
108 | + /* No constant temps have been previously allocated. */ | ||
109 | + for (int i = 0; i < TCG_TYPE_COUNT; ++i) { | ||
110 | + if (s->const_table[i]) { | ||
111 | + g_hash_table_remove_all(s->const_table[i]); | ||
112 | + } | ||
113 | + } | ||
114 | + | ||
115 | s->nb_ops = 0; | ||
116 | s->nb_labels = 0; | ||
117 | s->current_frame_offset = s->frame_start; | ||
118 | @@ -XXX,XX +XXX,XX @@ TCGTemp *tcg_global_mem_new_internal(TCGType type, TCGv_ptr base, | ||
119 | bigendian = 1; | ||
120 | #endif | ||
121 | |||
122 | - if (base_ts->kind != TEMP_FIXED) { | ||
123 | + switch (base_ts->kind) { | ||
124 | + case TEMP_FIXED: | ||
125 | + break; | ||
126 | + case TEMP_GLOBAL: | ||
127 | /* We do not support double-indirect registers. */ | ||
128 | tcg_debug_assert(!base_ts->indirect_reg); | ||
129 | base_ts->indirect_base = 1; | ||
130 | s->nb_indirects += (TCG_TARGET_REG_BITS == 32 && type == TCG_TYPE_I64 | ||
131 | ? 2 : 1); | ||
132 | indirect_reg = 1; | ||
133 | + break; | ||
134 | + default: | ||
135 | + g_assert_not_reached(); | ||
136 | } | ||
137 | |||
138 | if (TCG_TARGET_REG_BITS == 32 && type == TCG_TYPE_I64) { | ||
139 | @@ -XXX,XX +XXX,XX @@ void tcg_temp_free_internal(TCGTemp *ts) | ||
140 | TCGContext *s = tcg_ctx; | ||
141 | int k, idx; | ||
142 | |||
143 | + /* In order to simplify users of tcg_constant_*, silently ignore free. */ | ||
144 | + if (ts->kind == TEMP_CONST) { | ||
145 | + return; | ||
146 | + } | ||
147 | + | ||
148 | #if defined(CONFIG_DEBUG_TCG) | ||
149 | s->temps_in_use--; | ||
150 | if (s->temps_in_use < 0) { | ||
151 | @@ -XXX,XX +XXX,XX @@ void tcg_temp_free_internal(TCGTemp *ts) | ||
152 | set_bit(idx, s->free_temps[k].l); | ||
153 | } | ||
154 | |||
155 | +TCGTemp *tcg_constant_internal(TCGType type, int64_t val) | ||
156 | +{ | 17 | +{ |
157 | + TCGContext *s = tcg_ctx; | 18 | + return ti->is_const; |
158 | + GHashTable *h = s->const_table[type]; | ||
159 | + TCGTemp *ts; | ||
160 | + | ||
161 | + if (h == NULL) { | ||
162 | + h = g_hash_table_new(g_int64_hash, g_int64_equal); | ||
163 | + s->const_table[type] = h; | ||
164 | + } | ||
165 | + | ||
166 | + ts = g_hash_table_lookup(h, &val); | ||
167 | + if (ts == NULL) { | ||
168 | + ts = tcg_temp_alloc(s); | ||
169 | + | ||
170 | + if (TCG_TARGET_REG_BITS == 32 && type == TCG_TYPE_I64) { | ||
171 | + TCGTemp *ts2 = tcg_temp_alloc(s); | ||
172 | + | ||
173 | + ts->base_type = TCG_TYPE_I64; | ||
174 | + ts->type = TCG_TYPE_I32; | ||
175 | + ts->kind = TEMP_CONST; | ||
176 | + ts->temp_allocated = 1; | ||
177 | + /* | ||
178 | + * Retain the full value of the 64-bit constant in the low | ||
179 | + * part, so that the hash table works. Actual uses will | ||
180 | + * truncate the value to the low part. | ||
181 | + */ | ||
182 | + ts->val = val; | ||
183 | + | ||
184 | + tcg_debug_assert(ts2 == ts + 1); | ||
185 | + ts2->base_type = TCG_TYPE_I64; | ||
186 | + ts2->type = TCG_TYPE_I32; | ||
187 | + ts2->kind = TEMP_CONST; | ||
188 | + ts2->temp_allocated = 1; | ||
189 | + ts2->val = val >> 32; | ||
190 | + } else { | ||
191 | + ts->base_type = type; | ||
192 | + ts->type = type; | ||
193 | + ts->kind = TEMP_CONST; | ||
194 | + ts->temp_allocated = 1; | ||
195 | + ts->val = val; | ||
196 | + } | ||
197 | + g_hash_table_insert(h, &ts->val, ts); | ||
198 | + } | ||
199 | + | ||
200 | + return ts; | ||
201 | +} | 19 | +} |
202 | + | 20 | + |
203 | +TCGv_vec tcg_constant_vec(TCGType type, unsigned vece, int64_t val) | 21 | +static inline uint64_t ti_const_val(TempOptInfo *ti) |
204 | +{ | 22 | +{ |
205 | + val = dup_const(vece, val); | 23 | + return ti->val; |
206 | + return temp_tcgv_vec(tcg_constant_internal(type, val)); | ||
207 | +} | 24 | +} |
208 | + | 25 | + |
209 | TCGv_i32 tcg_const_i32(int32_t val) | 26 | +static inline bool ti_is_const_val(TempOptInfo *ti, uint64_t val) |
27 | +{ | ||
28 | + return ti_is_const(ti) && ti_const_val(ti) == val; | ||
29 | +} | ||
30 | + | ||
31 | static inline bool ts_is_const(TCGTemp *ts) | ||
210 | { | 32 | { |
211 | TCGv_i32 t0; | 33 | - return ts_info(ts)->is_const; |
212 | @@ -XXX,XX +XXX,XX @@ static void tcg_reg_alloc_start(TCGContext *s) | 34 | + return ti_is_const(ts_info(ts)); |
213 | TCGTempVal val = TEMP_VAL_MEM; | ||
214 | |||
215 | switch (ts->kind) { | ||
216 | + case TEMP_CONST: | ||
217 | + val = TEMP_VAL_CONST; | ||
218 | + break; | ||
219 | case TEMP_FIXED: | ||
220 | val = TEMP_VAL_REG; | ||
221 | break; | ||
222 | @@ -XXX,XX +XXX,XX @@ static char *tcg_get_arg_str_ptr(TCGContext *s, char *buf, int buf_size, | ||
223 | case TEMP_NORMAL: | ||
224 | snprintf(buf, buf_size, "tmp%d", idx - s->nb_globals); | ||
225 | break; | ||
226 | + case TEMP_CONST: | ||
227 | + switch (ts->type) { | ||
228 | + case TCG_TYPE_I32: | ||
229 | + snprintf(buf, buf_size, "$0x%x", (int32_t)ts->val); | ||
230 | + break; | ||
231 | +#if TCG_TARGET_REG_BITS > 32 | ||
232 | + case TCG_TYPE_I64: | ||
233 | + snprintf(buf, buf_size, "$0x%" PRIx64, ts->val); | ||
234 | + break; | ||
235 | +#endif | ||
236 | + case TCG_TYPE_V64: | ||
237 | + case TCG_TYPE_V128: | ||
238 | + case TCG_TYPE_V256: | ||
239 | + snprintf(buf, buf_size, "v%d$0x%" PRIx64, | ||
240 | + 64 << (ts->type - TCG_TYPE_V64), ts->val); | ||
241 | + break; | ||
242 | + default: | ||
243 | + g_assert_not_reached(); | ||
244 | + } | ||
245 | + break; | ||
246 | } | ||
247 | return buf; | ||
248 | } | 35 | } |
249 | @@ -XXX,XX +XXX,XX @@ static void la_bb_end(TCGContext *s, int ng, int nt) | 36 | |
250 | state = TS_DEAD | TS_MEM; | 37 | static inline bool ts_is_const_val(TCGTemp *ts, uint64_t val) |
251 | break; | ||
252 | case TEMP_NORMAL: | ||
253 | + case TEMP_CONST: | ||
254 | state = TS_DEAD; | ||
255 | break; | ||
256 | default: | ||
257 | @@ -XXX,XX +XXX,XX @@ static void la_bb_sync(TCGContext *s, int ng, int nt) | ||
258 | la_global_sync(s, ng); | ||
259 | |||
260 | for (int i = ng; i < nt; ++i) { | ||
261 | - if (s->temps[i].kind == TEMP_LOCAL) { | ||
262 | - int state = s->temps[i].state; | ||
263 | - s->temps[i].state = state | TS_MEM; | ||
264 | + TCGTemp *ts = &s->temps[i]; | ||
265 | + int state; | ||
266 | + | ||
267 | + switch (ts->kind) { | ||
268 | + case TEMP_LOCAL: | ||
269 | + state = ts->state; | ||
270 | + ts->state = state | TS_MEM; | ||
271 | if (state != TS_DEAD) { | ||
272 | continue; | ||
273 | } | ||
274 | - } else { | ||
275 | + break; | ||
276 | + case TEMP_NORMAL: | ||
277 | s->temps[i].state = TS_DEAD; | ||
278 | + break; | ||
279 | + case TEMP_CONST: | ||
280 | + continue; | ||
281 | + default: | ||
282 | + g_assert_not_reached(); | ||
283 | } | ||
284 | la_reset_pref(&s->temps[i]); | ||
285 | } | ||
286 | @@ -XXX,XX +XXX,XX @@ static void temp_load(TCGContext *, TCGTemp *, TCGRegSet, TCGRegSet, TCGRegSet); | ||
287 | mark it free; otherwise mark it dead. */ | ||
288 | static void temp_free_or_dead(TCGContext *s, TCGTemp *ts, int free_or_dead) | ||
289 | { | 38 | { |
290 | - if (temp_readonly(ts)) { | 39 | - TempOptInfo *ti = ts_info(ts); |
291 | + TCGTempVal new_type; | 40 | - return ti->is_const && ti->val == val; |
292 | + | 41 | + return ti_is_const_val(ts_info(ts), val); |
293 | + switch (ts->kind) { | ||
294 | + case TEMP_FIXED: | ||
295 | return; | ||
296 | + case TEMP_GLOBAL: | ||
297 | + case TEMP_LOCAL: | ||
298 | + new_type = TEMP_VAL_MEM; | ||
299 | + break; | ||
300 | + case TEMP_NORMAL: | ||
301 | + new_type = free_or_dead < 0 ? TEMP_VAL_MEM : TEMP_VAL_DEAD; | ||
302 | + break; | ||
303 | + case TEMP_CONST: | ||
304 | + new_type = TEMP_VAL_CONST; | ||
305 | + break; | ||
306 | + default: | ||
307 | + g_assert_not_reached(); | ||
308 | } | ||
309 | if (ts->val_type == TEMP_VAL_REG) { | ||
310 | s->reg_to_temp[ts->reg] = NULL; | ||
311 | } | ||
312 | - ts->val_type = (free_or_dead < 0 | ||
313 | - || ts->kind != TEMP_NORMAL | ||
314 | - ? TEMP_VAL_MEM : TEMP_VAL_DEAD); | ||
315 | + ts->val_type = new_type; | ||
316 | } | 42 | } |
317 | 43 | ||
318 | /* Mark a temporary as dead. */ | 44 | static inline bool arg_is_const(TCGArg arg) |
319 | @@ -XXX,XX +XXX,XX @@ static inline void temp_dead(TCGContext *s, TCGTemp *ts) | ||
320 | static void temp_sync(TCGContext *s, TCGTemp *ts, TCGRegSet allocated_regs, | ||
321 | TCGRegSet preferred_regs, int free_or_dead) | ||
322 | { | ||
323 | - if (temp_readonly(ts)) { | ||
324 | - return; | ||
325 | - } | ||
326 | - if (!ts->mem_coherent) { | ||
327 | + if (!temp_readonly(ts) && !ts->mem_coherent) { | ||
328 | if (!ts->mem_allocated) { | ||
329 | temp_allocate_frame(s, ts); | ||
330 | } | ||
331 | @@ -XXX,XX +XXX,XX @@ static void tcg_reg_alloc_bb_end(TCGContext *s, TCGRegSet allocated_regs) | ||
332 | |||
333 | for (i = s->nb_globals; i < s->nb_temps; i++) { | ||
334 | TCGTemp *ts = &s->temps[i]; | ||
335 | - if (ts->kind == TEMP_LOCAL) { | ||
336 | + | ||
337 | + switch (ts->kind) { | ||
338 | + case TEMP_LOCAL: | ||
339 | temp_save(s, ts, allocated_regs); | ||
340 | - } else { | ||
341 | + break; | ||
342 | + case TEMP_NORMAL: | ||
343 | /* The liveness analysis already ensures that temps are dead. | ||
344 | Keep an tcg_debug_assert for safety. */ | ||
345 | tcg_debug_assert(ts->val_type == TEMP_VAL_DEAD); | ||
346 | + break; | ||
347 | + case TEMP_CONST: | ||
348 | + /* Similarly, we should have freed any allocated register. */ | ||
349 | + tcg_debug_assert(ts->val_type == TEMP_VAL_CONST); | ||
350 | + break; | ||
351 | + default: | ||
352 | + g_assert_not_reached(); | ||
353 | } | ||
354 | } | ||
355 | |||
356 | @@ -XXX,XX +XXX,XX @@ static void tcg_reg_alloc_cbranch(TCGContext *s, TCGRegSet allocated_regs) | ||
357 | * The liveness analysis already ensures that temps are dead. | ||
358 | * Keep tcg_debug_asserts for safety. | ||
359 | */ | ||
360 | - if (ts->kind == TEMP_LOCAL) { | ||
361 | + switch (ts->kind) { | ||
362 | + case TEMP_LOCAL: | ||
363 | tcg_debug_assert(ts->val_type != TEMP_VAL_REG || ts->mem_coherent); | ||
364 | - } else { | ||
365 | + break; | ||
366 | + case TEMP_NORMAL: | ||
367 | tcg_debug_assert(ts->val_type == TEMP_VAL_DEAD); | ||
368 | + break; | ||
369 | + case TEMP_CONST: | ||
370 | + break; | ||
371 | + default: | ||
372 | + g_assert_not_reached(); | ||
373 | } | ||
374 | } | ||
375 | } | ||
376 | @@ -XXX,XX +XXX,XX @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op) | ||
377 | i_preferred_regs = o_preferred_regs = 0; | ||
378 | if (arg_ct->ialias) { | ||
379 | o_preferred_regs = op->output_pref[arg_ct->alias_index]; | ||
380 | - if (ts->kind == TEMP_FIXED) { | ||
381 | - /* if fixed register, we must allocate a new register | ||
382 | - if the alias is not the same register */ | ||
383 | - if (arg != op->args[arg_ct->alias_index]) { | ||
384 | - goto allocate_in_reg; | ||
385 | - } | ||
386 | - } else { | ||
387 | - /* if the input is aliased to an output and if it is | ||
388 | - not dead after the instruction, we must allocate | ||
389 | - a new register and move it */ | ||
390 | - if (!IS_DEAD_ARG(i)) { | ||
391 | - goto allocate_in_reg; | ||
392 | - } | ||
393 | |||
394 | - /* check if the current register has already been allocated | ||
395 | - for another input aliased to an output */ | ||
396 | - if (ts->val_type == TEMP_VAL_REG) { | ||
397 | - int k2, i2; | ||
398 | - reg = ts->reg; | ||
399 | - for (k2 = 0 ; k2 < k ; k2++) { | ||
400 | - i2 = def->args_ct[nb_oargs + k2].sort_index; | ||
401 | - if (def->args_ct[i2].ialias && reg == new_args[i2]) { | ||
402 | - goto allocate_in_reg; | ||
403 | - } | ||
404 | + /* | ||
405 | + * If the input is readonly, then it cannot also be an | ||
406 | + * output and aliased to itself. If the input is not | ||
407 | + * dead after the instruction, we must allocate a new | ||
408 | + * register and move it. | ||
409 | + */ | ||
410 | + if (temp_readonly(ts) || !IS_DEAD_ARG(i)) { | ||
411 | + goto allocate_in_reg; | ||
412 | + } | ||
413 | + | ||
414 | + /* | ||
415 | + * Check if the current register has already been allocated | ||
416 | + * for another input aliased to an output. | ||
417 | + */ | ||
418 | + if (ts->val_type == TEMP_VAL_REG) { | ||
419 | + reg = ts->reg; | ||
420 | + for (int k2 = 0; k2 < k; k2++) { | ||
421 | + int i2 = def->args_ct[nb_oargs + k2].sort_index; | ||
422 | + if (def->args_ct[i2].ialias && reg == new_args[i2]) { | ||
423 | + goto allocate_in_reg; | ||
424 | } | ||
425 | } | ||
426 | - i_preferred_regs = o_preferred_regs; | ||
427 | } | ||
428 | + i_preferred_regs = o_preferred_regs; | ||
429 | } | ||
430 | |||
431 | temp_load(s, ts, arg_ct->regs, i_allocated_regs, i_preferred_regs); | ||
432 | reg = ts->reg; | ||
433 | |||
434 | - if (tcg_regset_test_reg(arg_ct->regs, reg)) { | ||
435 | - /* nothing to do : the constraint is satisfied */ | ||
436 | - } else { | ||
437 | - allocate_in_reg: | ||
438 | - /* allocate a new register matching the constraint | ||
439 | - and move the temporary register into it */ | ||
440 | + if (!tcg_regset_test_reg(arg_ct->regs, reg)) { | ||
441 | + allocate_in_reg: | ||
442 | + /* | ||
443 | + * Allocate a new register matching the constraint | ||
444 | + * and move the temporary register into it. | ||
445 | + */ | ||
446 | temp_load(s, ts, tcg_target_available_regs[ts->type], | ||
447 | i_allocated_regs, 0); | ||
448 | reg = tcg_reg_alloc(s, arg_ct->regs, i_allocated_regs, | ||
449 | -- | 45 | -- |
450 | 2.25.1 | 46 | 2.43.0 |
451 | |||
452 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Avoid the use of the OptContext slots. Find TempOptInfo once. | ||
2 | Sink mask computation below fold_affected_mask early exit. | ||
1 | 3 | ||
4 | Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> | ||
5 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
6 | --- | ||
7 | tcg/optimize.c | 30 ++++++++++++++++-------------- | ||
8 | 1 file changed, 16 insertions(+), 14 deletions(-) | ||
9 | |||
10 | diff --git a/tcg/optimize.c b/tcg/optimize.c | ||
11 | index XXXXXXX..XXXXXXX 100644 | ||
12 | --- a/tcg/optimize.c | ||
13 | +++ b/tcg/optimize.c | ||
14 | @@ -XXX,XX +XXX,XX @@ static bool fold_add2(OptContext *ctx, TCGOp *op) | ||
15 | |||
16 | static bool fold_and(OptContext *ctx, TCGOp *op) | ||
17 | { | ||
18 | - uint64_t z1, z2; | ||
19 | + uint64_t z1, z2, z_mask, s_mask; | ||
20 | + TempOptInfo *t1, *t2; | ||
21 | |||
22 | if (fold_const2_commutative(ctx, op) || | ||
23 | fold_xi_to_i(ctx, op, 0) || | ||
24 | @@ -XXX,XX +XXX,XX @@ static bool fold_and(OptContext *ctx, TCGOp *op) | ||
25 | return true; | ||
26 | } | ||
27 | |||
28 | - z1 = arg_info(op->args[1])->z_mask; | ||
29 | - z2 = arg_info(op->args[2])->z_mask; | ||
30 | - ctx->z_mask = z1 & z2; | ||
31 | - | ||
32 | - /* | ||
33 | - * Sign repetitions are perforce all identical, whether they are 1 or 0. | ||
34 | - * Bitwise operations preserve the relative quantity of the repetitions. | ||
35 | - */ | ||
36 | - ctx->s_mask = arg_info(op->args[1])->s_mask | ||
37 | - & arg_info(op->args[2])->s_mask; | ||
38 | + t1 = arg_info(op->args[1]); | ||
39 | + t2 = arg_info(op->args[2]); | ||
40 | + z1 = t1->z_mask; | ||
41 | + z2 = t2->z_mask; | ||
42 | |||
43 | /* | ||
44 | * Known-zeros does not imply known-ones. Therefore unless | ||
45 | * arg2 is constant, we can't infer affected bits from it. | ||
46 | */ | ||
47 | - if (arg_is_const(op->args[2]) && | ||
48 | - fold_affected_mask(ctx, op, z1 & ~z2)) { | ||
49 | + if (ti_is_const(t2) && fold_affected_mask(ctx, op, z1 & ~z2)) { | ||
50 | return true; | ||
51 | } | ||
52 | |||
53 | - return fold_masks(ctx, op); | ||
54 | + z_mask = z1 & z2; | ||
55 | + | ||
56 | + /* | ||
57 | + * Sign repetitions are perforce all identical, whether they are 1 or 0. | ||
58 | + * Bitwise operations preserve the relative quantity of the repetitions. | ||
59 | + */ | ||
60 | + s_mask = t1->s_mask & t2->s_mask; | ||
61 | + | ||
62 | + return fold_masks_zs(ctx, op, z_mask, s_mask); | ||
63 | } | ||
64 | |||
65 | static bool fold_andc(OptContext *ctx, TCGOp *op) | ||
66 | -- | ||
67 | 2.43.0 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Avoid the use of the OptContext slots. Find TempOptInfo once. | ||
2 | Avoid double inversion of the value of second const operand. | ||
1 | 3 | ||
4 | Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> | ||
5 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
6 | --- | ||
7 | tcg/optimize.c | 21 +++++++++++---------- | ||
8 | 1 file changed, 11 insertions(+), 10 deletions(-) | ||
9 | |||
10 | diff --git a/tcg/optimize.c b/tcg/optimize.c | ||
11 | index XXXXXXX..XXXXXXX 100644 | ||
12 | --- a/tcg/optimize.c | ||
13 | +++ b/tcg/optimize.c | ||
14 | @@ -XXX,XX +XXX,XX @@ static bool fold_and(OptContext *ctx, TCGOp *op) | ||
15 | |||
16 | static bool fold_andc(OptContext *ctx, TCGOp *op) | ||
17 | { | ||
18 | - uint64_t z1; | ||
19 | + uint64_t z_mask, s_mask; | ||
20 | + TempOptInfo *t1, *t2; | ||
21 | |||
22 | if (fold_const2(ctx, op) || | ||
23 | fold_xx_to_i(ctx, op, 0) || | ||
24 | @@ -XXX,XX +XXX,XX @@ static bool fold_andc(OptContext *ctx, TCGOp *op) | ||
25 | return true; | ||
26 | } | ||
27 | |||
28 | - z1 = arg_info(op->args[1])->z_mask; | ||
29 | + t1 = arg_info(op->args[1]); | ||
30 | + t2 = arg_info(op->args[2]); | ||
31 | + z_mask = t1->z_mask; | ||
32 | |||
33 | /* | ||
34 | * Known-zeros does not imply known-ones. Therefore unless | ||
35 | * arg2 is constant, we can't infer anything from it. | ||
36 | */ | ||
37 | - if (arg_is_const(op->args[2])) { | ||
38 | - uint64_t z2 = ~arg_info(op->args[2])->z_mask; | ||
39 | - if (fold_affected_mask(ctx, op, z1 & ~z2)) { | ||
40 | + if (ti_is_const(t2)) { | ||
41 | + uint64_t v2 = ti_const_val(t2); | ||
42 | + if (fold_affected_mask(ctx, op, z_mask & v2)) { | ||
43 | return true; | ||
44 | } | ||
45 | - z1 &= z2; | ||
46 | + z_mask &= ~v2; | ||
47 | } | ||
48 | - ctx->z_mask = z1; | ||
49 | |||
50 | - ctx->s_mask = arg_info(op->args[1])->s_mask | ||
51 | - & arg_info(op->args[2])->s_mask; | ||
52 | - return fold_masks(ctx, op); | ||
53 | + s_mask = t1->s_mask & t2->s_mask; | ||
54 | + return fold_masks_zs(ctx, op, z_mask, s_mask); | ||
55 | } | ||
56 | |||
57 | static bool fold_brcond(OptContext *ctx, TCGOp *op) | ||
58 | -- | ||
59 | 2.43.0 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Avoid the use of the OptContext slots. Find TempOptInfo once. | ||
2 | Always set s_mask along the BSWAP_OS path, since the result is | ||
3 | being explicitly sign-extended. | ||
1 | 4 | ||
5 | Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> | ||
6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | --- | ||
8 | tcg/optimize.c | 21 ++++++++++----------- | ||
9 | 1 file changed, 10 insertions(+), 11 deletions(-) | ||
10 | |||
11 | diff --git a/tcg/optimize.c b/tcg/optimize.c | ||
12 | index XXXXXXX..XXXXXXX 100644 | ||
13 | --- a/tcg/optimize.c | ||
14 | +++ b/tcg/optimize.c | ||
15 | @@ -XXX,XX +XXX,XX @@ static bool fold_brcond2(OptContext *ctx, TCGOp *op) | ||
16 | static bool fold_bswap(OptContext *ctx, TCGOp *op) | ||
17 | { | ||
18 | uint64_t z_mask, s_mask, sign; | ||
19 | + TempOptInfo *t1 = arg_info(op->args[1]); | ||
20 | |||
21 | - if (arg_is_const(op->args[1])) { | ||
22 | - uint64_t t = arg_info(op->args[1])->val; | ||
23 | - | ||
24 | - t = do_constant_folding(op->opc, ctx->type, t, op->args[2]); | ||
25 | - return tcg_opt_gen_movi(ctx, op, op->args[0], t); | ||
26 | + if (ti_is_const(t1)) { | ||
27 | + return tcg_opt_gen_movi(ctx, op, op->args[0], | ||
28 | + do_constant_folding(op->opc, ctx->type, | ||
29 | + ti_const_val(t1), | ||
30 | + op->args[2])); | ||
31 | } | ||
32 | |||
33 | - z_mask = arg_info(op->args[1])->z_mask; | ||
34 | - | ||
35 | + z_mask = t1->z_mask; | ||
36 | switch (op->opc) { | ||
37 | case INDEX_op_bswap16_i32: | ||
38 | case INDEX_op_bswap16_i64: | ||
39 | @@ -XXX,XX +XXX,XX @@ static bool fold_bswap(OptContext *ctx, TCGOp *op) | ||
40 | /* If the sign bit may be 1, force all the bits above to 1. */ | ||
41 | if (z_mask & sign) { | ||
42 | z_mask |= sign; | ||
43 | - s_mask = sign << 1; | ||
44 | } | ||
45 | + /* The value and therefore s_mask is explicitly sign-extended. */ | ||
46 | + s_mask = sign; | ||
47 | break; | ||
48 | default: | ||
49 | /* The high bits are undefined: force all bits above the sign to 1. */ | ||
50 | z_mask |= sign << 1; | ||
51 | break; | ||
52 | } | ||
53 | - ctx->z_mask = z_mask; | ||
54 | - ctx->s_mask = s_mask; | ||
55 | |||
56 | - return fold_masks(ctx, op); | ||
57 | + return fold_masks_zs(ctx, op, z_mask, s_mask); | ||
58 | } | ||
59 | |||
60 | static bool fold_call(OptContext *ctx, TCGOp *op) | ||
61 | -- | ||
62 | 2.43.0 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Avoid the use of the OptContext slots. Find TempOptInfo once. | ||
2 | Compute s_mask from the union of the maximum count and the | ||
3 | op2 fallback for op1 being zero. | ||
1 | 4 | ||
5 | Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> | ||
6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | --- | ||
8 | tcg/optimize.c | 15 ++++++++++----- | ||
9 | 1 file changed, 10 insertions(+), 5 deletions(-) | ||
10 | |||
11 | diff --git a/tcg/optimize.c b/tcg/optimize.c | ||
12 | index XXXXXXX..XXXXXXX 100644 | ||
13 | --- a/tcg/optimize.c | ||
14 | +++ b/tcg/optimize.c | ||
15 | @@ -XXX,XX +XXX,XX @@ static bool fold_call(OptContext *ctx, TCGOp *op) | ||
16 | |||
17 | static bool fold_count_zeros(OptContext *ctx, TCGOp *op) | ||
18 | { | ||
19 | - uint64_t z_mask; | ||
20 | + uint64_t z_mask, s_mask; | ||
21 | + TempOptInfo *t1 = arg_info(op->args[1]); | ||
22 | + TempOptInfo *t2 = arg_info(op->args[2]); | ||
23 | |||
24 | - if (arg_is_const(op->args[1])) { | ||
25 | - uint64_t t = arg_info(op->args[1])->val; | ||
26 | + if (ti_is_const(t1)) { | ||
27 | + uint64_t t = ti_const_val(t1); | ||
28 | |||
29 | if (t != 0) { | ||
30 | t = do_constant_folding(op->opc, ctx->type, t, 0); | ||
31 | @@ -XXX,XX +XXX,XX @@ static bool fold_count_zeros(OptContext *ctx, TCGOp *op) | ||
32 | default: | ||
33 | g_assert_not_reached(); | ||
34 | } | ||
35 | - ctx->z_mask = arg_info(op->args[2])->z_mask | z_mask; | ||
36 | - return false; | ||
37 | + s_mask = ~z_mask; | ||
38 | + z_mask |= t2->z_mask; | ||
39 | + s_mask &= t2->s_mask; | ||
40 | + | ||
41 | + return fold_masks_zs(ctx, op, z_mask, s_mask); | ||
42 | } | ||
43 | |||
44 | static bool fold_ctpop(OptContext *ctx, TCGOp *op) | ||
45 | -- | ||
46 | 2.43.0 | diff view generated by jsdifflib |
1 | While we don't store more than tcg_target_long in TCGTemp, | 1 | Add fold_masks_z as a trivial wrapper around fold_masks_zs. |
---|---|---|---|
2 | we shouldn't be limited to that for code generation. We will | 2 | Avoid the use of the OptContext slots. |
3 | be able to use this for INDEX_op_dup2_vec with 2 constants. | ||
4 | 3 | ||
5 | Also pass along the minimal vece that may be said to apply | 4 | Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> |
6 | to the constant. This allows some simplification in the | ||
7 | various backends. | ||
8 | |||
9 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 5 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
10 | --- | 6 | --- |
11 | tcg/tcg.c | 31 +++++++++++++++++++++++++----- | 7 | tcg/optimize.c | 13 ++++++++++--- |
12 | tcg/aarch64/tcg-target.c.inc | 12 ++++++------ | 8 | 1 file changed, 10 insertions(+), 3 deletions(-) |
13 | tcg/i386/tcg-target.c.inc | 22 ++++++++++++--------- | ||
14 | tcg/ppc/tcg-target.c.inc | 37 +++++++++++++++++++++++------------- | ||
15 | 4 files changed, 69 insertions(+), 33 deletions(-) | ||
16 | 9 | ||
17 | diff --git a/tcg/tcg.c b/tcg/tcg.c | 10 | diff --git a/tcg/optimize.c b/tcg/optimize.c |
18 | index XXXXXXX..XXXXXXX 100644 | 11 | index XXXXXXX..XXXXXXX 100644 |
19 | --- a/tcg/tcg.c | 12 | --- a/tcg/optimize.c |
20 | +++ b/tcg/tcg.c | 13 | +++ b/tcg/optimize.c |
21 | @@ -XXX,XX +XXX,XX @@ static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece, | 14 | @@ -XXX,XX +XXX,XX @@ static bool fold_masks_zs(OptContext *ctx, TCGOp *op, |
22 | TCGReg dst, TCGReg src); | ||
23 | static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece, | ||
24 | TCGReg dst, TCGReg base, intptr_t offset); | ||
25 | -static void tcg_out_dupi_vec(TCGContext *s, TCGType type, | ||
26 | - TCGReg dst, tcg_target_long arg); | ||
27 | +static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece, | ||
28 | + TCGReg dst, int64_t arg); | ||
29 | static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, unsigned vecl, | ||
30 | unsigned vece, const TCGArg *args, | ||
31 | const int *const_args); | ||
32 | @@ -XXX,XX +XXX,XX @@ static inline bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece, | ||
33 | { | ||
34 | g_assert_not_reached(); | ||
35 | } | ||
36 | -static inline void tcg_out_dupi_vec(TCGContext *s, TCGType type, | ||
37 | - TCGReg dst, tcg_target_long arg) | ||
38 | +static inline void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece, | ||
39 | + TCGReg dst, int64_t arg) | ||
40 | { | ||
41 | g_assert_not_reached(); | ||
42 | } | ||
43 | @@ -XXX,XX +XXX,XX @@ static void temp_load(TCGContext *s, TCGTemp *ts, TCGRegSet desired_regs, | ||
44 | if (ts->type <= TCG_TYPE_I64) { | ||
45 | tcg_out_movi(s, ts->type, reg, ts->val); | ||
46 | } else { | ||
47 | - tcg_out_dupi_vec(s, ts->type, reg, ts->val); | ||
48 | + uint64_t val = ts->val; | ||
49 | + MemOp vece = MO_64; | ||
50 | + | ||
51 | + /* | ||
52 | + * Find the minimal vector element that matches the constant. | ||
53 | + * The targets will, in general, have to do this search anyway, | ||
54 | + * do this generically. | ||
55 | + */ | ||
56 | + if (TCG_TARGET_REG_BITS == 32) { | ||
57 | + val = dup_const(MO_32, val); | ||
58 | + vece = MO_32; | ||
59 | + } | ||
60 | + if (val == dup_const(MO_8, val)) { | ||
61 | + vece = MO_8; | ||
62 | + } else if (val == dup_const(MO_16, val)) { | ||
63 | + vece = MO_16; | ||
64 | + } else if (TCG_TARGET_REG_BITS == 64 && | ||
65 | + val == dup_const(MO_32, val)) { | ||
66 | + vece = MO_32; | ||
67 | + } | ||
68 | + | ||
69 | + tcg_out_dupi_vec(s, ts->type, vece, reg, ts->val); | ||
70 | } | ||
71 | ts->mem_coherent = 0; | ||
72 | break; | ||
73 | diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc | ||
74 | index XXXXXXX..XXXXXXX 100644 | ||
75 | --- a/tcg/aarch64/tcg-target.c.inc | ||
76 | +++ b/tcg/aarch64/tcg-target.c.inc | ||
77 | @@ -XXX,XX +XXX,XX @@ static void tcg_out_logicali(TCGContext *s, AArch64Insn insn, TCGType ext, | ||
78 | tcg_out_insn_3404(s, insn, ext, rd, rn, ext, r, c); | ||
79 | } | ||
80 | |||
81 | -static void tcg_out_dupi_vec(TCGContext *s, TCGType type, | ||
82 | - TCGReg rd, tcg_target_long v64) | ||
83 | +static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece, | ||
84 | + TCGReg rd, int64_t v64) | ||
85 | { | ||
86 | bool q = type == TCG_TYPE_V128; | ||
87 | int cmode, imm8, i; | ||
88 | |||
89 | /* Test all bytes equal first. */ | ||
90 | - if (v64 == dup_const(MO_8, v64)) { | ||
91 | + if (vece == MO_8) { | ||
92 | imm8 = (uint8_t)v64; | ||
93 | tcg_out_insn(s, 3606, MOVI, q, rd, 0, 0xe, imm8); | ||
94 | return; | ||
95 | @@ -XXX,XX +XXX,XX @@ static void tcg_out_dupi_vec(TCGContext *s, TCGType type, | ||
96 | * cannot find an expansion there's no point checking a larger | ||
97 | * width because we already know by replication it cannot match. | ||
98 | */ | ||
99 | - if (v64 == dup_const(MO_16, v64)) { | ||
100 | + if (vece == MO_16) { | ||
101 | uint16_t v16 = v64; | ||
102 | |||
103 | if (is_shimm16(v16, &cmode, &imm8)) { | ||
104 | @@ -XXX,XX +XXX,XX @@ static void tcg_out_dupi_vec(TCGContext *s, TCGType type, | ||
105 | tcg_out_insn(s, 3606, MOVI, q, rd, 0, 0x8, v16 & 0xff); | ||
106 | tcg_out_insn(s, 3606, ORR, q, rd, 0, 0xa, v16 >> 8); | ||
107 | return; | ||
108 | - } else if (v64 == dup_const(MO_32, v64)) { | ||
109 | + } else if (vece == MO_32) { | ||
110 | uint32_t v32 = v64; | ||
111 | uint32_t n32 = ~v32; | ||
112 | |||
113 | @@ -XXX,XX +XXX,XX @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, | ||
114 | tcg_out_insn_3617(s, insn, is_q, vece, a0, a1); | ||
115 | break; | ||
116 | } | ||
117 | - tcg_out_dupi_vec(s, type, TCG_VEC_TMP, 0); | ||
118 | + tcg_out_dupi_vec(s, type, MO_8, TCG_VEC_TMP, 0); | ||
119 | a2 = TCG_VEC_TMP; | ||
120 | } | ||
121 | insn = cmp_insn[cond]; | ||
122 | diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc | ||
123 | index XXXXXXX..XXXXXXX 100644 | ||
124 | --- a/tcg/i386/tcg-target.c.inc | ||
125 | +++ b/tcg/i386/tcg-target.c.inc | ||
126 | @@ -XXX,XX +XXX,XX @@ static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece, | ||
127 | return true; | 15 | return true; |
128 | } | 16 | } |
129 | 17 | ||
130 | -static void tcg_out_dupi_vec(TCGContext *s, TCGType type, | 18 | +static bool fold_masks_z(OptContext *ctx, TCGOp *op, uint64_t z_mask) |
131 | - TCGReg ret, tcg_target_long arg) | 19 | +{ |
132 | +static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece, | 20 | + return fold_masks_zs(ctx, op, z_mask, 0); |
133 | + TCGReg ret, int64_t arg) | 21 | +} |
22 | + | ||
23 | static bool fold_masks(OptContext *ctx, TCGOp *op) | ||
134 | { | 24 | { |
135 | int vex_l = (type == TCG_TYPE_V256 ? P_VEXL : 0); | 25 | return fold_masks_zs(ctx, op, ctx->z_mask, ctx->s_mask); |
136 | 26 | @@ -XXX,XX +XXX,XX @@ static bool fold_count_zeros(OptContext *ctx, TCGOp *op) | |
137 | @@ -XXX,XX +XXX,XX @@ static void tcg_out_dupi_vec(TCGContext *s, TCGType type, | 27 | |
138 | return; | 28 | static bool fold_ctpop(OptContext *ctx, TCGOp *op) |
29 | { | ||
30 | + uint64_t z_mask; | ||
31 | + | ||
32 | if (fold_const1(ctx, op)) { | ||
33 | return true; | ||
139 | } | 34 | } |
140 | 35 | ||
141 | - if (TCG_TARGET_REG_BITS == 64) { | 36 | switch (ctx->type) { |
142 | + if (TCG_TARGET_REG_BITS == 32 && vece < MO_64) { | 37 | case TCG_TYPE_I32: |
143 | + if (have_avx2) { | 38 | - ctx->z_mask = 32 | 31; |
144 | + tcg_out_vex_modrm_pool(s, OPC_VPBROADCASTD + vex_l, ret); | 39 | + z_mask = 32 | 31; |
145 | + } else { | 40 | break; |
146 | + tcg_out_vex_modrm_pool(s, OPC_VBROADCASTSS, ret); | 41 | case TCG_TYPE_I64: |
147 | + } | 42 | - ctx->z_mask = 64 | 63; |
148 | + new_pool_label(s, arg, R_386_32, s->code_ptr - 4, 0); | 43 | + z_mask = 64 | 63; |
149 | + } else { | 44 | break; |
150 | if (type == TCG_TYPE_V64) { | 45 | default: |
151 | tcg_out_vex_modrm_pool(s, OPC_MOVQ_VqWq, ret); | 46 | g_assert_not_reached(); |
152 | } else if (have_avx2) { | ||
153 | @@ -XXX,XX +XXX,XX @@ static void tcg_out_dupi_vec(TCGContext *s, TCGType type, | ||
154 | } else { | ||
155 | tcg_out_vex_modrm_pool(s, OPC_MOVDDUP, ret); | ||
156 | } | ||
157 | - new_pool_label(s, arg, R_386_PC32, s->code_ptr - 4, -4); | ||
158 | - } else { | ||
159 | - if (have_avx2) { | ||
160 | - tcg_out_vex_modrm_pool(s, OPC_VPBROADCASTD + vex_l, ret); | ||
161 | + if (TCG_TARGET_REG_BITS == 64) { | ||
162 | + new_pool_label(s, arg, R_386_PC32, s->code_ptr - 4, -4); | ||
163 | } else { | ||
164 | - tcg_out_vex_modrm_pool(s, OPC_VBROADCASTSS, ret); | ||
165 | + new_pool_l2(s, R_386_32, s->code_ptr - 4, 0, arg, arg >> 32); | ||
166 | } | ||
167 | - new_pool_label(s, arg, R_386_32, s->code_ptr - 4, 0); | ||
168 | } | 47 | } |
48 | - return false; | ||
49 | + return fold_masks_z(ctx, op, z_mask); | ||
169 | } | 50 | } |
170 | 51 | ||
171 | diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc | 52 | static bool fold_deposit(OptContext *ctx, TCGOp *op) |
172 | index XXXXXXX..XXXXXXX 100644 | ||
173 | --- a/tcg/ppc/tcg-target.c.inc | ||
174 | +++ b/tcg/ppc/tcg-target.c.inc | ||
175 | @@ -XXX,XX +XXX,XX @@ static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret, | ||
176 | } | ||
177 | } | ||
178 | |||
179 | -static void tcg_out_dupi_vec(TCGContext *s, TCGType type, TCGReg ret, | ||
180 | - tcg_target_long val) | ||
181 | +static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece, | ||
182 | + TCGReg ret, int64_t val) | ||
183 | { | ||
184 | uint32_t load_insn; | ||
185 | int rel, low; | ||
186 | intptr_t add; | ||
187 | |||
188 | - low = (int8_t)val; | ||
189 | - if (low >= -16 && low < 16) { | ||
190 | - if (val == (tcg_target_long)dup_const(MO_8, low)) { | ||
191 | + switch (vece) { | ||
192 | + case MO_8: | ||
193 | + low = (int8_t)val; | ||
194 | + if (low >= -16 && low < 16) { | ||
195 | tcg_out32(s, VSPLTISB | VRT(ret) | ((val & 31) << 16)); | ||
196 | return; | ||
197 | } | ||
198 | - if (val == (tcg_target_long)dup_const(MO_16, low)) { | ||
199 | + if (have_isa_3_00) { | ||
200 | + tcg_out32(s, XXSPLTIB | VRT(ret) | ((val & 0xff) << 11)); | ||
201 | + return; | ||
202 | + } | ||
203 | + break; | ||
204 | + | ||
205 | + case MO_16: | ||
206 | + low = (int16_t)val; | ||
207 | + if (low >= -16 && low < 16) { | ||
208 | tcg_out32(s, VSPLTISH | VRT(ret) | ((val & 31) << 16)); | ||
209 | return; | ||
210 | } | ||
211 | - if (val == (tcg_target_long)dup_const(MO_32, low)) { | ||
212 | + break; | ||
213 | + | ||
214 | + case MO_32: | ||
215 | + low = (int32_t)val; | ||
216 | + if (low >= -16 && low < 16) { | ||
217 | tcg_out32(s, VSPLTISW | VRT(ret) | ((val & 31) << 16)); | ||
218 | return; | ||
219 | } | ||
220 | - } | ||
221 | - if (have_isa_3_00 && val == (tcg_target_long)dup_const(MO_8, val)) { | ||
222 | - tcg_out32(s, XXSPLTIB | VRT(ret) | ((val & 0xff) << 11)); | ||
223 | - return; | ||
224 | + break; | ||
225 | } | ||
226 | |||
227 | /* | ||
228 | @@ -XXX,XX +XXX,XX @@ static void tcg_out_dupi_vec(TCGContext *s, TCGType type, TCGReg ret, | ||
229 | if (TCG_TARGET_REG_BITS == 64) { | ||
230 | new_pool_label(s, val, rel, s->code_ptr, add); | ||
231 | } else { | ||
232 | - new_pool_l2(s, rel, s->code_ptr, add, val, val); | ||
233 | + new_pool_l2(s, rel, s->code_ptr, add, val >> 32, val); | ||
234 | } | ||
235 | } else { | ||
236 | load_insn = LVX | VRT(ret) | RB(TCG_REG_TMP1); | ||
237 | if (TCG_TARGET_REG_BITS == 64) { | ||
238 | new_pool_l2(s, rel, s->code_ptr, add, val, val); | ||
239 | } else { | ||
240 | - new_pool_l4(s, rel, s->code_ptr, add, val, val, val, val); | ||
241 | + new_pool_l4(s, rel, s->code_ptr, add, | ||
242 | + val >> 32, val, val >> 32, val); | ||
243 | } | ||
244 | } | ||
245 | |||
246 | -- | 53 | -- |
247 | 2.25.1 | 54 | 2.43.0 |
248 | |||
249 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Avoid the use of the OptContext slots. Find TempOptInfo once. | ||
2 | When we fold to and, use fold_and. | ||
1 | 3 | ||
4 | Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> | ||
5 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
6 | --- | ||
7 | tcg/optimize.c | 35 +++++++++++++++++------------------ | ||
8 | 1 file changed, 17 insertions(+), 18 deletions(-) | ||
9 | |||
10 | diff --git a/tcg/optimize.c b/tcg/optimize.c | ||
11 | index XXXXXXX..XXXXXXX 100644 | ||
12 | --- a/tcg/optimize.c | ||
13 | +++ b/tcg/optimize.c | ||
14 | @@ -XXX,XX +XXX,XX @@ static bool fold_ctpop(OptContext *ctx, TCGOp *op) | ||
15 | |||
16 | static bool fold_deposit(OptContext *ctx, TCGOp *op) | ||
17 | { | ||
18 | + TempOptInfo *t1 = arg_info(op->args[1]); | ||
19 | + TempOptInfo *t2 = arg_info(op->args[2]); | ||
20 | + int ofs = op->args[3]; | ||
21 | + int len = op->args[4]; | ||
22 | TCGOpcode and_opc; | ||
23 | + uint64_t z_mask; | ||
24 | |||
25 | - if (arg_is_const(op->args[1]) && arg_is_const(op->args[2])) { | ||
26 | - uint64_t t1 = arg_info(op->args[1])->val; | ||
27 | - uint64_t t2 = arg_info(op->args[2])->val; | ||
28 | - | ||
29 | - t1 = deposit64(t1, op->args[3], op->args[4], t2); | ||
30 | - return tcg_opt_gen_movi(ctx, op, op->args[0], t1); | ||
31 | + if (ti_is_const(t1) && ti_is_const(t2)) { | ||
32 | + return tcg_opt_gen_movi(ctx, op, op->args[0], | ||
33 | + deposit64(ti_const_val(t1), ofs, len, | ||
34 | + ti_const_val(t2))); | ||
35 | } | ||
36 | |||
37 | switch (ctx->type) { | ||
38 | @@ -XXX,XX +XXX,XX @@ static bool fold_deposit(OptContext *ctx, TCGOp *op) | ||
39 | } | ||
40 | |||
41 | /* Inserting a value into zero at offset 0. */ | ||
42 | - if (arg_is_const_val(op->args[1], 0) && op->args[3] == 0) { | ||
43 | - uint64_t mask = MAKE_64BIT_MASK(0, op->args[4]); | ||
44 | + if (ti_is_const_val(t1, 0) && ofs == 0) { | ||
45 | + uint64_t mask = MAKE_64BIT_MASK(0, len); | ||
46 | |||
47 | op->opc = and_opc; | ||
48 | op->args[1] = op->args[2]; | ||
49 | op->args[2] = arg_new_constant(ctx, mask); | ||
50 | - ctx->z_mask = mask & arg_info(op->args[1])->z_mask; | ||
51 | - return false; | ||
52 | + return fold_and(ctx, op); | ||
53 | } | ||
54 | |||
55 | /* Inserting zero into a value. */ | ||
56 | - if (arg_is_const_val(op->args[2], 0)) { | ||
57 | - uint64_t mask = deposit64(-1, op->args[3], op->args[4], 0); | ||
58 | + if (ti_is_const_val(t2, 0)) { | ||
59 | + uint64_t mask = deposit64(-1, ofs, len, 0); | ||
60 | |||
61 | op->opc = and_opc; | ||
62 | op->args[2] = arg_new_constant(ctx, mask); | ||
63 | - ctx->z_mask = mask & arg_info(op->args[1])->z_mask; | ||
64 | - return false; | ||
65 | + return fold_and(ctx, op); | ||
66 | } | ||
67 | |||
68 | - ctx->z_mask = deposit64(arg_info(op->args[1])->z_mask, | ||
69 | - op->args[3], op->args[4], | ||
70 | - arg_info(op->args[2])->z_mask); | ||
71 | - return false; | ||
72 | + z_mask = deposit64(t1->z_mask, ofs, len, t2->z_mask); | ||
73 | + return fold_masks_z(ctx, op, z_mask); | ||
74 | } | ||
75 | |||
76 | static bool fold_divide(OptContext *ctx, TCGOp *op) | ||
77 | -- | ||
78 | 2.43.0 | diff view generated by jsdifflib |
1 | Improve expand_vec_shi to use sign-extraction for MO_32. | 1 | The input which overlaps the sign bit of the output can |
---|---|---|---|
2 | This allows a single VSPLTISB instruction to load all of | 2 | have its input s_mask propagated to the output s_mask. |
3 | the valid shift constants. | ||
4 | 3 | ||
4 | Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> | ||
5 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 5 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
6 | --- | 6 | --- |
7 | tcg/ppc/tcg-target.c.inc | 44 ++++++++++++++++++++++++---------------- | 7 | tcg/optimize.c | 14 ++++++++++++-- |
8 | 1 file changed, 27 insertions(+), 17 deletions(-) | 8 | 1 file changed, 12 insertions(+), 2 deletions(-) |
9 | 9 | ||
10 | diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc | 10 | diff --git a/tcg/optimize.c b/tcg/optimize.c |
11 | index XXXXXXX..XXXXXXX 100644 | 11 | index XXXXXXX..XXXXXXX 100644 |
12 | --- a/tcg/ppc/tcg-target.c.inc | 12 | --- a/tcg/optimize.c |
13 | +++ b/tcg/ppc/tcg-target.c.inc | 13 | +++ b/tcg/optimize.c |
14 | @@ -XXX,XX +XXX,XX @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, | 14 | @@ -XXX,XX +XXX,XX @@ static bool fold_deposit(OptContext *ctx, TCGOp *op) |
15 | static void expand_vec_shi(TCGType type, unsigned vece, TCGv_vec v0, | 15 | TempOptInfo *t2 = arg_info(op->args[2]); |
16 | TCGv_vec v1, TCGArg imm, TCGOpcode opci) | 16 | int ofs = op->args[3]; |
17 | { | 17 | int len = op->args[4]; |
18 | - TCGv_vec t1 = tcg_temp_new_vec(type); | 18 | + int width; |
19 | + TCGv_vec t1; | 19 | TCGOpcode and_opc; |
20 | 20 | - uint64_t z_mask; | |
21 | - /* Splat w/bytes for xxspltib. */ | 21 | + uint64_t z_mask, s_mask; |
22 | - tcg_gen_dupi_vec(MO_8, t1, imm & ((8 << vece) - 1)); | 22 | |
23 | + if (vece == MO_32) { | 23 | if (ti_is_const(t1) && ti_is_const(t2)) { |
24 | + /* | 24 | return tcg_opt_gen_movi(ctx, op, op->args[0], |
25 | + * Only 5 bits are significant, and VSPLTISB can represent -16..15. | 25 | @@ -XXX,XX +XXX,XX @@ static bool fold_deposit(OptContext *ctx, TCGOp *op) |
26 | + * So using negative numbers gets us the 4th bit easily. | 26 | switch (ctx->type) { |
27 | + */ | 27 | case TCG_TYPE_I32: |
28 | + imm = sextract32(imm, 0, 5); | 28 | and_opc = INDEX_op_and_i32; |
29 | + width = 32; | ||
30 | break; | ||
31 | case TCG_TYPE_I64: | ||
32 | and_opc = INDEX_op_and_i64; | ||
33 | + width = 64; | ||
34 | break; | ||
35 | default: | ||
36 | g_assert_not_reached(); | ||
37 | @@ -XXX,XX +XXX,XX @@ static bool fold_deposit(OptContext *ctx, TCGOp *op) | ||
38 | return fold_and(ctx, op); | ||
39 | } | ||
40 | |||
41 | + /* The s_mask from the top portion of the deposit is still valid. */ | ||
42 | + if (ofs + len == width) { | ||
43 | + s_mask = t2->s_mask << ofs; | ||
29 | + } else { | 44 | + } else { |
30 | + imm &= (8 << vece) - 1; | 45 | + s_mask = t1->s_mask & ~MAKE_64BIT_MASK(0, ofs + len); |
31 | + } | 46 | + } |
32 | + | 47 | + |
33 | + /* Splat w/bytes for xxspltib when 2.07 allows MO_64. */ | 48 | z_mask = deposit64(t1->z_mask, ofs, len, t2->z_mask); |
34 | + t1 = tcg_constant_vec(type, MO_8, imm); | 49 | - return fold_masks_z(ctx, op, z_mask); |
35 | vec_gen_3(opci, type, vece, tcgv_vec_arg(v0), | 50 | + return fold_masks_zs(ctx, op, z_mask, s_mask); |
36 | tcgv_vec_arg(v1), tcgv_vec_arg(t1)); | ||
37 | - tcg_temp_free_vec(t1); | ||
38 | } | 51 | } |
39 | 52 | ||
40 | static void expand_vec_cmp(TCGType type, unsigned vece, TCGv_vec v0, | 53 | static bool fold_divide(OptContext *ctx, TCGOp *op) |
41 | @@ -XXX,XX +XXX,XX @@ static void expand_vec_mul(TCGType type, unsigned vece, TCGv_vec v0, | ||
42 | { | ||
43 | TCGv_vec t1 = tcg_temp_new_vec(type); | ||
44 | TCGv_vec t2 = tcg_temp_new_vec(type); | ||
45 | - TCGv_vec t3, t4; | ||
46 | + TCGv_vec c0, c16; | ||
47 | |||
48 | switch (vece) { | ||
49 | case MO_8: | ||
50 | @@ -XXX,XX +XXX,XX @@ static void expand_vec_mul(TCGType type, unsigned vece, TCGv_vec v0, | ||
51 | |||
52 | case MO_32: | ||
53 | tcg_debug_assert(!have_isa_2_07); | ||
54 | - t3 = tcg_temp_new_vec(type); | ||
55 | - t4 = tcg_temp_new_vec(type); | ||
56 | - tcg_gen_dupi_vec(MO_8, t4, -16); | ||
57 | + /* | ||
58 | + * Only 5 bits are significant, and VSPLTISB can represent -16..15. | ||
59 | + * So using -16 is a quick way to represent 16. | ||
60 | + */ | ||
61 | + c16 = tcg_constant_vec(type, MO_8, -16); | ||
62 | + c0 = tcg_constant_vec(type, MO_8, 0); | ||
63 | + | ||
64 | vec_gen_3(INDEX_op_rotlv_vec, type, MO_32, tcgv_vec_arg(t1), | ||
65 | - tcgv_vec_arg(v2), tcgv_vec_arg(t4)); | ||
66 | + tcgv_vec_arg(v2), tcgv_vec_arg(c16)); | ||
67 | vec_gen_3(INDEX_op_ppc_mulou_vec, type, MO_16, tcgv_vec_arg(t2), | ||
68 | tcgv_vec_arg(v1), tcgv_vec_arg(v2)); | ||
69 | - tcg_gen_dupi_vec(MO_8, t3, 0); | ||
70 | - vec_gen_4(INDEX_op_ppc_msum_vec, type, MO_16, tcgv_vec_arg(t3), | ||
71 | - tcgv_vec_arg(v1), tcgv_vec_arg(t1), tcgv_vec_arg(t3)); | ||
72 | - vec_gen_3(INDEX_op_shlv_vec, type, MO_32, tcgv_vec_arg(t3), | ||
73 | - tcgv_vec_arg(t3), tcgv_vec_arg(t4)); | ||
74 | - tcg_gen_add_vec(MO_32, v0, t2, t3); | ||
75 | - tcg_temp_free_vec(t3); | ||
76 | - tcg_temp_free_vec(t4); | ||
77 | + vec_gen_4(INDEX_op_ppc_msum_vec, type, MO_16, tcgv_vec_arg(t1), | ||
78 | + tcgv_vec_arg(v1), tcgv_vec_arg(t1), tcgv_vec_arg(c0)); | ||
79 | + vec_gen_3(INDEX_op_shlv_vec, type, MO_32, tcgv_vec_arg(t1), | ||
80 | + tcgv_vec_arg(t1), tcgv_vec_arg(c16)); | ||
81 | + tcg_gen_add_vec(MO_32, v0, t1, t2); | ||
82 | break; | ||
83 | |||
84 | default: | ||
85 | -- | 54 | -- |
86 | 2.25.1 | 55 | 2.43.0 |
87 | |||
88 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> | ||
2 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
3 | --- | ||
4 | tcg/optimize.c | 2 +- | ||
5 | 1 file changed, 1 insertion(+), 1 deletion(-) | ||
1 | 6 | ||
7 | diff --git a/tcg/optimize.c b/tcg/optimize.c | ||
8 | index XXXXXXX..XXXXXXX 100644 | ||
9 | --- a/tcg/optimize.c | ||
10 | +++ b/tcg/optimize.c | ||
11 | @@ -XXX,XX +XXX,XX @@ static bool fold_divide(OptContext *ctx, TCGOp *op) | ||
12 | fold_xi_to_x(ctx, op, 1)) { | ||
13 | return true; | ||
14 | } | ||
15 | - return false; | ||
16 | + return finish_folding(ctx, op); | ||
17 | } | ||
18 | |||
19 | static bool fold_dup(OptContext *ctx, TCGOp *op) | ||
20 | -- | ||
21 | 2.43.0 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> | ||
2 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
3 | --- | ||
4 | tcg/optimize.c | 4 ++-- | ||
5 | 1 file changed, 2 insertions(+), 2 deletions(-) | ||
1 | 6 | ||
7 | diff --git a/tcg/optimize.c b/tcg/optimize.c | ||
8 | index XXXXXXX..XXXXXXX 100644 | ||
9 | --- a/tcg/optimize.c | ||
10 | +++ b/tcg/optimize.c | ||
11 | @@ -XXX,XX +XXX,XX @@ static bool fold_dup(OptContext *ctx, TCGOp *op) | ||
12 | t = dup_const(TCGOP_VECE(op), t); | ||
13 | return tcg_opt_gen_movi(ctx, op, op->args[0], t); | ||
14 | } | ||
15 | - return false; | ||
16 | + return finish_folding(ctx, op); | ||
17 | } | ||
18 | |||
19 | static bool fold_dup2(OptContext *ctx, TCGOp *op) | ||
20 | @@ -XXX,XX +XXX,XX @@ static bool fold_dup2(OptContext *ctx, TCGOp *op) | ||
21 | op->opc = INDEX_op_dup_vec; | ||
22 | TCGOP_VECE(op) = MO_32; | ||
23 | } | ||
24 | - return false; | ||
25 | + return finish_folding(ctx, op); | ||
26 | } | ||
27 | |||
28 | static bool fold_eqv(OptContext *ctx, TCGOp *op) | ||
29 | -- | ||
30 | 2.43.0 | diff view generated by jsdifflib |
1 | In most, but not all, places that we check for TEMP_FIXED, | 1 | Add fold_masks_s as a trivial wrapper around fold_masks_zs. |
---|---|---|---|
2 | we are really testing that we do not modify the temporary. | 2 | Avoid the use of the OptContext slots. |
3 | 3 | ||
4 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | 4 | Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> |
5 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 5 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
7 | --- | 6 | --- |
8 | include/tcg/tcg.h | 5 +++++ | 7 | tcg/optimize.c | 13 ++++++++++--- |
9 | tcg/tcg.c | 21 ++++++++++----------- | 8 | 1 file changed, 10 insertions(+), 3 deletions(-) |
10 | 2 files changed, 15 insertions(+), 11 deletions(-) | ||
11 | 9 | ||
12 | diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h | 10 | diff --git a/tcg/optimize.c b/tcg/optimize.c |
13 | index XXXXXXX..XXXXXXX 100644 | 11 | index XXXXXXX..XXXXXXX 100644 |
14 | --- a/include/tcg/tcg.h | 12 | --- a/tcg/optimize.c |
15 | +++ b/include/tcg/tcg.h | 13 | +++ b/tcg/optimize.c |
16 | @@ -XXX,XX +XXX,XX @@ struct TCGContext { | 14 | @@ -XXX,XX +XXX,XX @@ static bool fold_masks_z(OptContext *ctx, TCGOp *op, uint64_t z_mask) |
17 | target_ulong gen_insn_data[TCG_MAX_INSNS][TARGET_INSN_START_WORDS]; | 15 | return fold_masks_zs(ctx, op, z_mask, 0); |
18 | }; | 16 | } |
19 | 17 | ||
20 | +static inline bool temp_readonly(TCGTemp *ts) | 18 | +static bool fold_masks_s(OptContext *ctx, TCGOp *op, uint64_t s_mask) |
21 | +{ | 19 | +{ |
22 | + return ts->kind == TEMP_FIXED; | 20 | + return fold_masks_zs(ctx, op, -1, s_mask); |
23 | +} | 21 | +} |
24 | + | 22 | + |
25 | extern TCGContext tcg_init_ctx; | 23 | static bool fold_masks(OptContext *ctx, TCGOp *op) |
26 | extern __thread TCGContext *tcg_ctx; | ||
27 | extern const void *tcg_code_gen_epilogue; | ||
28 | diff --git a/tcg/tcg.c b/tcg/tcg.c | ||
29 | index XXXXXXX..XXXXXXX 100644 | ||
30 | --- a/tcg/tcg.c | ||
31 | +++ b/tcg/tcg.c | ||
32 | @@ -XXX,XX +XXX,XX @@ static void temp_load(TCGContext *, TCGTemp *, TCGRegSet, TCGRegSet, TCGRegSet); | ||
33 | mark it free; otherwise mark it dead. */ | ||
34 | static void temp_free_or_dead(TCGContext *s, TCGTemp *ts, int free_or_dead) | ||
35 | { | 24 | { |
36 | - if (ts->kind == TEMP_FIXED) { | 25 | return fold_masks_zs(ctx, op, ctx->z_mask, ctx->s_mask); |
37 | + if (temp_readonly(ts)) { | 26 | @@ -XXX,XX +XXX,XX @@ static bool fold_dup2(OptContext *ctx, TCGOp *op) |
38 | return; | 27 | |
28 | static bool fold_eqv(OptContext *ctx, TCGOp *op) | ||
29 | { | ||
30 | + uint64_t s_mask; | ||
31 | + | ||
32 | if (fold_const2_commutative(ctx, op) || | ||
33 | fold_xi_to_x(ctx, op, -1) || | ||
34 | fold_xi_to_not(ctx, op, 0)) { | ||
35 | return true; | ||
39 | } | 36 | } |
40 | if (ts->val_type == TEMP_VAL_REG) { | 37 | |
41 | @@ -XXX,XX +XXX,XX @@ static inline void temp_dead(TCGContext *s, TCGTemp *ts) | 38 | - ctx->s_mask = arg_info(op->args[1])->s_mask |
42 | static void temp_sync(TCGContext *s, TCGTemp *ts, TCGRegSet allocated_regs, | 39 | - & arg_info(op->args[2])->s_mask; |
43 | TCGRegSet preferred_regs, int free_or_dead) | 40 | - return false; |
44 | { | 41 | + s_mask = arg_info(op->args[1])->s_mask |
45 | - if (ts->kind == TEMP_FIXED) { | 42 | + & arg_info(op->args[2])->s_mask; |
46 | + if (temp_readonly(ts)) { | 43 | + return fold_masks_s(ctx, op, s_mask); |
47 | return; | ||
48 | } | ||
49 | if (!ts->mem_coherent) { | ||
50 | @@ -XXX,XX +XXX,XX @@ static void temp_save(TCGContext *s, TCGTemp *ts, TCGRegSet allocated_regs) | ||
51 | { | ||
52 | /* The liveness analysis already ensures that globals are back | ||
53 | in memory. Keep an tcg_debug_assert for safety. */ | ||
54 | - tcg_debug_assert(ts->val_type == TEMP_VAL_MEM | ||
55 | - || ts->kind == TEMP_FIXED); | ||
56 | + tcg_debug_assert(ts->val_type == TEMP_VAL_MEM || temp_readonly(ts)); | ||
57 | } | 44 | } |
58 | 45 | ||
59 | /* save globals to their canonical location and assume they can be | 46 | static bool fold_extract(OptContext *ctx, TCGOp *op) |
60 | @@ -XXX,XX +XXX,XX @@ static void tcg_reg_alloc_do_movi(TCGContext *s, TCGTemp *ots, | ||
61 | TCGRegSet preferred_regs) | ||
62 | { | ||
63 | /* ENV should not be modified. */ | ||
64 | - tcg_debug_assert(ots->kind != TEMP_FIXED); | ||
65 | + tcg_debug_assert(!temp_readonly(ots)); | ||
66 | |||
67 | /* The movi is not explicitly generated here. */ | ||
68 | if (ots->val_type == TEMP_VAL_REG) { | ||
69 | @@ -XXX,XX +XXX,XX @@ static void tcg_reg_alloc_mov(TCGContext *s, const TCGOp *op) | ||
70 | ts = arg_temp(op->args[1]); | ||
71 | |||
72 | /* ENV should not be modified. */ | ||
73 | - tcg_debug_assert(ots->kind != TEMP_FIXED); | ||
74 | + tcg_debug_assert(!temp_readonly(ots)); | ||
75 | |||
76 | /* Note that otype != itype for no-op truncation. */ | ||
77 | otype = ots->type; | ||
78 | @@ -XXX,XX +XXX,XX @@ static void tcg_reg_alloc_mov(TCGContext *s, const TCGOp *op) | ||
79 | * Store the source register into the destination slot | ||
80 | * and leave the destination temp as TEMP_VAL_MEM. | ||
81 | */ | ||
82 | - assert(ots->kind != TEMP_FIXED); | ||
83 | + assert(!temp_readonly(ots)); | ||
84 | if (!ts->mem_allocated) { | ||
85 | temp_allocate_frame(s, ots); | ||
86 | } | ||
87 | @@ -XXX,XX +XXX,XX @@ static void tcg_reg_alloc_dup(TCGContext *s, const TCGOp *op) | ||
88 | its = arg_temp(op->args[1]); | ||
89 | |||
90 | /* ENV should not be modified. */ | ||
91 | - tcg_debug_assert(ots->kind != TEMP_FIXED); | ||
92 | + tcg_debug_assert(!temp_readonly(ots)); | ||
93 | |||
94 | itype = its->type; | ||
95 | vece = TCGOP_VECE(op); | ||
96 | @@ -XXX,XX +XXX,XX @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op) | ||
97 | ts = arg_temp(arg); | ||
98 | |||
99 | /* ENV should not be modified. */ | ||
100 | - tcg_debug_assert(ts->kind != TEMP_FIXED); | ||
101 | + tcg_debug_assert(!temp_readonly(ts)); | ||
102 | |||
103 | if (arg_ct->oalias && !const_args[arg_ct->alias_index]) { | ||
104 | reg = new_args[arg_ct->alias_index]; | ||
105 | @@ -XXX,XX +XXX,XX @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op) | ||
106 | ts = arg_temp(op->args[i]); | ||
107 | |||
108 | /* ENV should not be modified. */ | ||
109 | - tcg_debug_assert(ts->kind != TEMP_FIXED); | ||
110 | + tcg_debug_assert(!temp_readonly(ts)); | ||
111 | |||
112 | if (NEED_SYNC_ARG(i)) { | ||
113 | temp_sync(s, ts, o_allocated_regs, 0, IS_DEAD_ARG(i)); | ||
114 | @@ -XXX,XX +XXX,XX @@ static void tcg_reg_alloc_call(TCGContext *s, TCGOp *op) | ||
115 | ts = arg_temp(arg); | ||
116 | |||
117 | /* ENV should not be modified. */ | ||
118 | - tcg_debug_assert(ts->kind != TEMP_FIXED); | ||
119 | + tcg_debug_assert(!temp_readonly(ts)); | ||
120 | |||
121 | reg = tcg_target_call_oarg_regs[i]; | ||
122 | tcg_debug_assert(s->reg_to_temp[reg] == NULL); | ||
123 | -- | 47 | -- |
124 | 2.25.1 | 48 | 2.43.0 |
125 | |||
126 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Avoid the use of the OptContext slots. Find TempOptInfo once. | ||
1 | 2 | ||
3 | Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> | ||
4 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
5 | --- | ||
6 | tcg/optimize.c | 15 ++++++--------- | ||
7 | 1 file changed, 6 insertions(+), 9 deletions(-) | ||
8 | |||
9 | diff --git a/tcg/optimize.c b/tcg/optimize.c | ||
10 | index XXXXXXX..XXXXXXX 100644 | ||
11 | --- a/tcg/optimize.c | ||
12 | +++ b/tcg/optimize.c | ||
13 | @@ -XXX,XX +XXX,XX @@ static bool fold_eqv(OptContext *ctx, TCGOp *op) | ||
14 | static bool fold_extract(OptContext *ctx, TCGOp *op) | ||
15 | { | ||
16 | uint64_t z_mask_old, z_mask; | ||
17 | + TempOptInfo *t1 = arg_info(op->args[1]); | ||
18 | int pos = op->args[2]; | ||
19 | int len = op->args[3]; | ||
20 | |||
21 | - if (arg_is_const(op->args[1])) { | ||
22 | - uint64_t t; | ||
23 | - | ||
24 | - t = arg_info(op->args[1])->val; | ||
25 | - t = extract64(t, pos, len); | ||
26 | - return tcg_opt_gen_movi(ctx, op, op->args[0], t); | ||
27 | + if (ti_is_const(t1)) { | ||
28 | + return tcg_opt_gen_movi(ctx, op, op->args[0], | ||
29 | + extract64(ti_const_val(t1), pos, len)); | ||
30 | } | ||
31 | |||
32 | - z_mask_old = arg_info(op->args[1])->z_mask; | ||
33 | + z_mask_old = t1->z_mask; | ||
34 | z_mask = extract64(z_mask_old, pos, len); | ||
35 | if (pos == 0 && fold_affected_mask(ctx, op, z_mask_old ^ z_mask)) { | ||
36 | return true; | ||
37 | } | ||
38 | - ctx->z_mask = z_mask; | ||
39 | |||
40 | - return fold_masks(ctx, op); | ||
41 | + return fold_masks_z(ctx, op, z_mask); | ||
42 | } | ||
43 | |||
44 | static bool fold_extract2(OptContext *ctx, TCGOp *op) | ||
45 | -- | ||
46 | 2.43.0 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> | ||
2 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
3 | --- | ||
4 | tcg/optimize.c | 2 +- | ||
5 | 1 file changed, 1 insertion(+), 1 deletion(-) | ||
1 | 6 | ||
7 | diff --git a/tcg/optimize.c b/tcg/optimize.c | ||
8 | index XXXXXXX..XXXXXXX 100644 | ||
9 | --- a/tcg/optimize.c | ||
10 | +++ b/tcg/optimize.c | ||
11 | @@ -XXX,XX +XXX,XX @@ static bool fold_extract2(OptContext *ctx, TCGOp *op) | ||
12 | } | ||
13 | return tcg_opt_gen_movi(ctx, op, op->args[0], v1 | v2); | ||
14 | } | ||
15 | - return false; | ||
16 | + return finish_folding(ctx, op); | ||
17 | } | ||
18 | |||
19 | static bool fold_exts(OptContext *ctx, TCGOp *op) | ||
20 | -- | ||
21 | 2.43.0 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Avoid the use of the OptContext slots. Find TempOptInfo once. | ||
2 | Explicitly sign-extend z_mask instead of doing that manually. | ||
1 | 3 | ||
4 | Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> | ||
5 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
6 | --- | ||
7 | tcg/optimize.c | 29 ++++++++++++----------------- | ||
8 | 1 file changed, 12 insertions(+), 17 deletions(-) | ||
9 | |||
10 | diff --git a/tcg/optimize.c b/tcg/optimize.c | ||
11 | index XXXXXXX..XXXXXXX 100644 | ||
12 | --- a/tcg/optimize.c | ||
13 | +++ b/tcg/optimize.c | ||
14 | @@ -XXX,XX +XXX,XX @@ static bool fold_extract2(OptContext *ctx, TCGOp *op) | ||
15 | |||
16 | static bool fold_exts(OptContext *ctx, TCGOp *op) | ||
17 | { | ||
18 | - uint64_t s_mask_old, s_mask, z_mask, sign; | ||
19 | + uint64_t s_mask_old, s_mask, z_mask; | ||
20 | bool type_change = false; | ||
21 | + TempOptInfo *t1; | ||
22 | |||
23 | if (fold_const1(ctx, op)) { | ||
24 | return true; | ||
25 | } | ||
26 | |||
27 | - z_mask = arg_info(op->args[1])->z_mask; | ||
28 | - s_mask = arg_info(op->args[1])->s_mask; | ||
29 | + t1 = arg_info(op->args[1]); | ||
30 | + z_mask = t1->z_mask; | ||
31 | + s_mask = t1->s_mask; | ||
32 | s_mask_old = s_mask; | ||
33 | |||
34 | switch (op->opc) { | ||
35 | CASE_OP_32_64(ext8s): | ||
36 | - sign = INT8_MIN; | ||
37 | - z_mask = (uint8_t)z_mask; | ||
38 | + s_mask |= INT8_MIN; | ||
39 | + z_mask = (int8_t)z_mask; | ||
40 | break; | ||
41 | CASE_OP_32_64(ext16s): | ||
42 | - sign = INT16_MIN; | ||
43 | - z_mask = (uint16_t)z_mask; | ||
44 | + s_mask |= INT16_MIN; | ||
45 | + z_mask = (int16_t)z_mask; | ||
46 | break; | ||
47 | case INDEX_op_ext_i32_i64: | ||
48 | type_change = true; | ||
49 | QEMU_FALLTHROUGH; | ||
50 | case INDEX_op_ext32s_i64: | ||
51 | - sign = INT32_MIN; | ||
52 | - z_mask = (uint32_t)z_mask; | ||
53 | + s_mask |= INT32_MIN; | ||
54 | + z_mask = (int32_t)z_mask; | ||
55 | break; | ||
56 | default: | ||
57 | g_assert_not_reached(); | ||
58 | } | ||
59 | |||
60 | - if (z_mask & sign) { | ||
61 | - z_mask |= sign; | ||
62 | - } | ||
63 | - s_mask |= sign << 1; | ||
64 | - | ||
65 | - ctx->z_mask = z_mask; | ||
66 | - ctx->s_mask = s_mask; | ||
67 | if (0 && !type_change && fold_affected_mask(ctx, op, s_mask & ~s_mask_old)) { | ||
68 | return true; | ||
69 | } | ||
70 | |||
71 | - return fold_masks(ctx, op); | ||
72 | + return fold_masks_zs(ctx, op, z_mask, s_mask); | ||
73 | } | ||
74 | |||
75 | static bool fold_extu(OptContext *ctx, TCGOp *op) | ||
76 | -- | ||
77 | 2.43.0 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Avoid the use of the OptContext slots. | ||
1 | 2 | ||
3 | Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> | ||
4 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
5 | --- | ||
6 | tcg/optimize.c | 4 ++-- | ||
7 | 1 file changed, 2 insertions(+), 2 deletions(-) | ||
8 | |||
9 | diff --git a/tcg/optimize.c b/tcg/optimize.c | ||
10 | index XXXXXXX..XXXXXXX 100644 | ||
11 | --- a/tcg/optimize.c | ||
12 | +++ b/tcg/optimize.c | ||
13 | @@ -XXX,XX +XXX,XX @@ static bool fold_extu(OptContext *ctx, TCGOp *op) | ||
14 | g_assert_not_reached(); | ||
15 | } | ||
16 | |||
17 | - ctx->z_mask = z_mask; | ||
18 | if (!type_change && fold_affected_mask(ctx, op, z_mask_old ^ z_mask)) { | ||
19 | return true; | ||
20 | } | ||
21 | - return fold_masks(ctx, op); | ||
22 | + | ||
23 | + return fold_masks_z(ctx, op, z_mask); | ||
24 | } | ||
25 | |||
26 | static bool fold_mb(OptContext *ctx, TCGOp *op) | ||
27 | -- | ||
28 | 2.43.0 | diff view generated by jsdifflib |
1 | Prefer TEMP_CONST over anything else. | 1 | Avoid the use of the OptContext slots. Find TempOptInfo once. |
---|---|---|---|
2 | 2 | ||
3 | Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> | ||
3 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 4 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
4 | --- | 5 | --- |
5 | tcg/optimize.c | 27 ++++++++++++--------------- | 6 | tcg/optimize.c | 19 +++++++++++-------- |
6 | 1 file changed, 12 insertions(+), 15 deletions(-) | 7 | 1 file changed, 11 insertions(+), 8 deletions(-) |
7 | 8 | ||
8 | diff --git a/tcg/optimize.c b/tcg/optimize.c | 9 | diff --git a/tcg/optimize.c b/tcg/optimize.c |
9 | index XXXXXXX..XXXXXXX 100644 | 10 | index XXXXXXX..XXXXXXX 100644 |
10 | --- a/tcg/optimize.c | 11 | --- a/tcg/optimize.c |
11 | +++ b/tcg/optimize.c | 12 | +++ b/tcg/optimize.c |
12 | @@ -XXX,XX +XXX,XX @@ static void init_arg_info(TempOptInfo *infos, | 13 | @@ -XXX,XX +XXX,XX @@ static bool fold_mov(OptContext *ctx, TCGOp *op) |
13 | 14 | ||
14 | static TCGTemp *find_better_copy(TCGContext *s, TCGTemp *ts) | 15 | static bool fold_movcond(OptContext *ctx, TCGOp *op) |
15 | { | 16 | { |
16 | - TCGTemp *i; | 17 | + uint64_t z_mask, s_mask; |
17 | + TCGTemp *i, *g, *l; | 18 | + TempOptInfo *tt, *ft; |
18 | 19 | int i; | |
19 | - /* If this is already a global, we can't do better. */ | 20 | |
20 | - if (ts->kind >= TEMP_GLOBAL) { | 21 | /* If true and false values are the same, eliminate the cmp. */ |
21 | + /* If this is already readonly, we can't do better. */ | 22 | @@ -XXX,XX +XXX,XX @@ static bool fold_movcond(OptContext *ctx, TCGOp *op) |
22 | + if (temp_readonly(ts)) { | 23 | return tcg_opt_gen_mov(ctx, op, op->args[0], op->args[4 - i]); |
23 | return ts; | ||
24 | } | 24 | } |
25 | 25 | ||
26 | - /* Search for a global first. */ | 26 | - ctx->z_mask = arg_info(op->args[3])->z_mask |
27 | + g = l = NULL; | 27 | - | arg_info(op->args[4])->z_mask; |
28 | for (i = ts_info(ts)->next_copy; i != ts; i = ts_info(i)->next_copy) { | 28 | - ctx->s_mask = arg_info(op->args[3])->s_mask |
29 | - if (i->kind >= TEMP_GLOBAL) { | 29 | - & arg_info(op->args[4])->s_mask; |
30 | + if (temp_readonly(i)) { | 30 | + tt = arg_info(op->args[3]); |
31 | return i; | 31 | + ft = arg_info(op->args[4]); |
32 | - } | 32 | + z_mask = tt->z_mask | ft->z_mask; |
33 | - } | 33 | + s_mask = tt->s_mask & ft->s_mask; |
34 | - | 34 | |
35 | - /* If it is a temp, search for a temp local. */ | 35 | - if (arg_is_const(op->args[3]) && arg_is_const(op->args[4])) { |
36 | - if (ts->kind == TEMP_NORMAL) { | 36 | - uint64_t tv = arg_info(op->args[3])->val; |
37 | - for (i = ts_info(ts)->next_copy; i != ts; i = ts_info(i)->next_copy) { | 37 | - uint64_t fv = arg_info(op->args[4])->val; |
38 | - if (i->kind >= TEMP_LOCAL) { | 38 | + if (ti_is_const(tt) && ti_is_const(ft)) { |
39 | - return i; | 39 | + uint64_t tv = ti_const_val(tt); |
40 | + } else if (i->kind > ts->kind) { | 40 | + uint64_t fv = ti_const_val(ft); |
41 | + if (i->kind == TEMP_GLOBAL) { | 41 | TCGOpcode opc, negopc = 0; |
42 | + g = i; | 42 | TCGCond cond = op->args[5]; |
43 | + } else if (i->kind == TEMP_LOCAL) { | 43 | |
44 | + l = i; | 44 | @@ -XXX,XX +XXX,XX @@ static bool fold_movcond(OptContext *ctx, TCGOp *op) |
45 | } | 45 | } |
46 | } | 46 | } |
47 | } | 47 | } |
48 | 48 | - return false; | |
49 | - /* Failure to find a better representation, return the same temp. */ | 49 | + |
50 | - return ts; | 50 | + return fold_masks_zs(ctx, op, z_mask, s_mask); |
51 | + /* If we didn't find a better representation, return the same temp. */ | ||
52 | + return g ? g : l ? l : ts; | ||
53 | } | 51 | } |
54 | 52 | ||
55 | static bool ts_are_copies(TCGTemp *ts1, TCGTemp *ts2) | 53 | static bool fold_mul(OptContext *ctx, TCGOp *op) |
56 | -- | 54 | -- |
57 | 2.25.1 | 55 | 2.43.0 |
58 | |||
59 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> | ||
2 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
3 | --- | ||
4 | tcg/optimize.c | 6 +++--- | ||
5 | 1 file changed, 3 insertions(+), 3 deletions(-) | ||
1 | 6 | ||
7 | diff --git a/tcg/optimize.c b/tcg/optimize.c | ||
8 | index XXXXXXX..XXXXXXX 100644 | ||
9 | --- a/tcg/optimize.c | ||
10 | +++ b/tcg/optimize.c | ||
11 | @@ -XXX,XX +XXX,XX @@ static bool fold_mul(OptContext *ctx, TCGOp *op) | ||
12 | fold_xi_to_x(ctx, op, 1)) { | ||
13 | return true; | ||
14 | } | ||
15 | - return false; | ||
16 | + return finish_folding(ctx, op); | ||
17 | } | ||
18 | |||
19 | static bool fold_mul_highpart(OptContext *ctx, TCGOp *op) | ||
20 | @@ -XXX,XX +XXX,XX @@ static bool fold_mul_highpart(OptContext *ctx, TCGOp *op) | ||
21 | fold_xi_to_i(ctx, op, 0)) { | ||
22 | return true; | ||
23 | } | ||
24 | - return false; | ||
25 | + return finish_folding(ctx, op); | ||
26 | } | ||
27 | |||
28 | static bool fold_multiply2(OptContext *ctx, TCGOp *op) | ||
29 | @@ -XXX,XX +XXX,XX @@ static bool fold_multiply2(OptContext *ctx, TCGOp *op) | ||
30 | tcg_opt_gen_movi(ctx, op2, rh, h); | ||
31 | return true; | ||
32 | } | ||
33 | - return false; | ||
34 | + return finish_folding(ctx, op); | ||
35 | } | ||
36 | |||
37 | static bool fold_nand(OptContext *ctx, TCGOp *op) | ||
38 | -- | ||
39 | 2.43.0 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Avoid the use of the OptContext slots. | ||
1 | 2 | ||
3 | Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> | ||
4 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
5 | --- | ||
6 | tcg/optimize.c | 8 +++++--- | ||
7 | 1 file changed, 5 insertions(+), 3 deletions(-) | ||
8 | |||
9 | diff --git a/tcg/optimize.c b/tcg/optimize.c | ||
10 | index XXXXXXX..XXXXXXX 100644 | ||
11 | --- a/tcg/optimize.c | ||
12 | +++ b/tcg/optimize.c | ||
13 | @@ -XXX,XX +XXX,XX @@ static bool fold_multiply2(OptContext *ctx, TCGOp *op) | ||
14 | |||
15 | static bool fold_nand(OptContext *ctx, TCGOp *op) | ||
16 | { | ||
17 | + uint64_t s_mask; | ||
18 | + | ||
19 | if (fold_const2_commutative(ctx, op) || | ||
20 | fold_xi_to_not(ctx, op, -1)) { | ||
21 | return true; | ||
22 | } | ||
23 | |||
24 | - ctx->s_mask = arg_info(op->args[1])->s_mask | ||
25 | - & arg_info(op->args[2])->s_mask; | ||
26 | - return false; | ||
27 | + s_mask = arg_info(op->args[1])->s_mask | ||
28 | + & arg_info(op->args[2])->s_mask; | ||
29 | + return fold_masks_s(ctx, op, s_mask); | ||
30 | } | ||
31 | |||
32 | static bool fold_neg_no_const(OptContext *ctx, TCGOp *op) | ||
33 | -- | ||
34 | 2.43.0 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Avoid the use of the OptContext slots. | ||
1 | 2 | ||
3 | Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> | ||
4 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
5 | --- | ||
6 | tcg/optimize.c | 9 ++------- | ||
7 | 1 file changed, 2 insertions(+), 7 deletions(-) | ||
8 | |||
9 | diff --git a/tcg/optimize.c b/tcg/optimize.c | ||
10 | index XXXXXXX..XXXXXXX 100644 | ||
11 | --- a/tcg/optimize.c | ||
12 | +++ b/tcg/optimize.c | ||
13 | @@ -XXX,XX +XXX,XX @@ static bool fold_neg_no_const(OptContext *ctx, TCGOp *op) | ||
14 | { | ||
15 | /* Set to 1 all bits to the left of the rightmost. */ | ||
16 | uint64_t z_mask = arg_info(op->args[1])->z_mask; | ||
17 | - ctx->z_mask = -(z_mask & -z_mask); | ||
18 | + z_mask = -(z_mask & -z_mask); | ||
19 | |||
20 | - /* | ||
21 | - * Because of fold_sub_to_neg, we want to always return true, | ||
22 | - * via finish_folding. | ||
23 | - */ | ||
24 | - finish_folding(ctx, op); | ||
25 | - return true; | ||
26 | + return fold_masks_z(ctx, op, z_mask); | ||
27 | } | ||
28 | |||
29 | static bool fold_neg(OptContext *ctx, TCGOp *op) | ||
30 | -- | ||
31 | 2.43.0 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Avoid the use of the OptContext slots. | ||
1 | 2 | ||
3 | Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> | ||
4 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
5 | --- | ||
6 | tcg/optimize.c | 8 +++++--- | ||
7 | 1 file changed, 5 insertions(+), 3 deletions(-) | ||
8 | |||
9 | diff --git a/tcg/optimize.c b/tcg/optimize.c | ||
10 | index XXXXXXX..XXXXXXX 100644 | ||
11 | --- a/tcg/optimize.c | ||
12 | +++ b/tcg/optimize.c | ||
13 | @@ -XXX,XX +XXX,XX @@ static bool fold_neg(OptContext *ctx, TCGOp *op) | ||
14 | |||
15 | static bool fold_nor(OptContext *ctx, TCGOp *op) | ||
16 | { | ||
17 | + uint64_t s_mask; | ||
18 | + | ||
19 | if (fold_const2_commutative(ctx, op) || | ||
20 | fold_xi_to_not(ctx, op, 0)) { | ||
21 | return true; | ||
22 | } | ||
23 | |||
24 | - ctx->s_mask = arg_info(op->args[1])->s_mask | ||
25 | - & arg_info(op->args[2])->s_mask; | ||
26 | - return false; | ||
27 | + s_mask = arg_info(op->args[1])->s_mask | ||
28 | + & arg_info(op->args[2])->s_mask; | ||
29 | + return fold_masks_s(ctx, op, s_mask); | ||
30 | } | ||
31 | |||
32 | static bool fold_not(OptContext *ctx, TCGOp *op) | ||
33 | -- | ||
34 | 2.43.0 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Avoid the use of the OptContext slots. | ||
1 | 2 | ||
3 | Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> | ||
4 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
5 | --- | ||
6 | tcg/optimize.c | 7 +------ | ||
7 | 1 file changed, 1 insertion(+), 6 deletions(-) | ||
8 | |||
9 | diff --git a/tcg/optimize.c b/tcg/optimize.c | ||
10 | index XXXXXXX..XXXXXXX 100644 | ||
11 | --- a/tcg/optimize.c | ||
12 | +++ b/tcg/optimize.c | ||
13 | @@ -XXX,XX +XXX,XX @@ static bool fold_not(OptContext *ctx, TCGOp *op) | ||
14 | if (fold_const1(ctx, op)) { | ||
15 | return true; | ||
16 | } | ||
17 | - | ||
18 | - ctx->s_mask = arg_info(op->args[1])->s_mask; | ||
19 | - | ||
20 | - /* Because of fold_to_not, we want to always return true, via finish. */ | ||
21 | - finish_folding(ctx, op); | ||
22 | - return true; | ||
23 | + return fold_masks_s(ctx, op, arg_info(op->args[1])->s_mask); | ||
24 | } | ||
25 | |||
26 | static bool fold_or(OptContext *ctx, TCGOp *op) | ||
27 | -- | ||
28 | 2.43.0 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Avoid the use of the OptContext slots. Find TempOptInfo once. | ||
1 | 2 | ||
3 | Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> | ||
4 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
5 | --- | ||
6 | tcg/optimize.c | 13 ++++++++----- | ||
7 | 1 file changed, 8 insertions(+), 5 deletions(-) | ||
8 | |||
9 | diff --git a/tcg/optimize.c b/tcg/optimize.c | ||
10 | index XXXXXXX..XXXXXXX 100644 | ||
11 | --- a/tcg/optimize.c | ||
12 | +++ b/tcg/optimize.c | ||
13 | @@ -XXX,XX +XXX,XX @@ static bool fold_not(OptContext *ctx, TCGOp *op) | ||
14 | |||
15 | static bool fold_or(OptContext *ctx, TCGOp *op) | ||
16 | { | ||
17 | + uint64_t z_mask, s_mask; | ||
18 | + TempOptInfo *t1, *t2; | ||
19 | + | ||
20 | if (fold_const2_commutative(ctx, op) || | ||
21 | fold_xi_to_x(ctx, op, 0) || | ||
22 | fold_xx_to_x(ctx, op)) { | ||
23 | return true; | ||
24 | } | ||
25 | |||
26 | - ctx->z_mask = arg_info(op->args[1])->z_mask | ||
27 | - | arg_info(op->args[2])->z_mask; | ||
28 | - ctx->s_mask = arg_info(op->args[1])->s_mask | ||
29 | - & arg_info(op->args[2])->s_mask; | ||
30 | - return fold_masks(ctx, op); | ||
31 | + t1 = arg_info(op->args[1]); | ||
32 | + t2 = arg_info(op->args[2]); | ||
33 | + z_mask = t1->z_mask | t2->z_mask; | ||
34 | + s_mask = t1->s_mask & t2->s_mask; | ||
35 | + return fold_masks_zs(ctx, op, z_mask, s_mask); | ||
36 | } | ||
37 | |||
38 | static bool fold_orc(OptContext *ctx, TCGOp *op) | ||
39 | -- | ||
40 | 2.43.0 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Avoid the use of the OptContext slots. | ||
1 | 2 | ||
3 | Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> | ||
4 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
5 | --- | ||
6 | tcg/optimize.c | 8 +++++--- | ||
7 | 1 file changed, 5 insertions(+), 3 deletions(-) | ||
8 | |||
9 | diff --git a/tcg/optimize.c b/tcg/optimize.c | ||
10 | index XXXXXXX..XXXXXXX 100644 | ||
11 | --- a/tcg/optimize.c | ||
12 | +++ b/tcg/optimize.c | ||
13 | @@ -XXX,XX +XXX,XX @@ static bool fold_or(OptContext *ctx, TCGOp *op) | ||
14 | |||
15 | static bool fold_orc(OptContext *ctx, TCGOp *op) | ||
16 | { | ||
17 | + uint64_t s_mask; | ||
18 | + | ||
19 | if (fold_const2(ctx, op) || | ||
20 | fold_xx_to_i(ctx, op, -1) || | ||
21 | fold_xi_to_x(ctx, op, -1) || | ||
22 | @@ -XXX,XX +XXX,XX @@ static bool fold_orc(OptContext *ctx, TCGOp *op) | ||
23 | return true; | ||
24 | } | ||
25 | |||
26 | - ctx->s_mask = arg_info(op->args[1])->s_mask | ||
27 | - & arg_info(op->args[2])->s_mask; | ||
28 | - return false; | ||
29 | + s_mask = arg_info(op->args[1])->s_mask | ||
30 | + & arg_info(op->args[2])->s_mask; | ||
31 | + return fold_masks_s(ctx, op, s_mask); | ||
32 | } | ||
33 | |||
34 | static bool fold_qemu_ld(OptContext *ctx, TCGOp *op) | ||
35 | -- | ||
36 | 2.43.0 | diff view generated by jsdifflib |
1 | Avoid the use of the OptContext slots. | ||
---|---|---|---|
2 | |||
3 | Be careful not to call fold_masks_zs when the memory operation | ||
4 | is wide enough to require multiple outputs, so split into two | ||
5 | functions: fold_qemu_ld_1reg and fold_qemu_ld_2reg. | ||
6 | |||
7 | Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> | ||
1 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 8 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
2 | --- | 9 | --- |
3 | tcg/optimize.c | 108 ++++++++++++++++++++++--------------------------- | 10 | tcg/optimize.c | 26 +++++++++++++++++++++----- |
4 | 1 file changed, 49 insertions(+), 59 deletions(-) | 11 | 1 file changed, 21 insertions(+), 5 deletions(-) |
5 | 12 | ||
6 | diff --git a/tcg/optimize.c b/tcg/optimize.c | 13 | diff --git a/tcg/optimize.c b/tcg/optimize.c |
7 | index XXXXXXX..XXXXXXX 100644 | 14 | index XXXXXXX..XXXXXXX 100644 |
8 | --- a/tcg/optimize.c | 15 | --- a/tcg/optimize.c |
9 | +++ b/tcg/optimize.c | 16 | +++ b/tcg/optimize.c |
10 | @@ -XXX,XX +XXX,XX @@ static bool args_are_copies(TCGArg arg1, TCGArg arg2) | 17 | @@ -XXX,XX +XXX,XX @@ static bool fold_orc(OptContext *ctx, TCGOp *op) |
11 | return ts_are_copies(arg_temp(arg1), arg_temp(arg2)); | 18 | return fold_masks_s(ctx, op, s_mask); |
12 | } | 19 | } |
13 | 20 | ||
14 | -static void tcg_opt_gen_movi(TCGContext *s, TCGOp *op, TCGArg dst, uint64_t val) | 21 | -static bool fold_qemu_ld(OptContext *ctx, TCGOp *op) |
15 | -{ | 22 | +static bool fold_qemu_ld_1reg(OptContext *ctx, TCGOp *op) |
16 | - const TCGOpDef *def; | ||
17 | - TCGOpcode new_op; | ||
18 | - uint64_t mask; | ||
19 | - TempOptInfo *di = arg_info(dst); | ||
20 | - | ||
21 | - def = &tcg_op_defs[op->opc]; | ||
22 | - if (def->flags & TCG_OPF_VECTOR) { | ||
23 | - new_op = INDEX_op_dupi_vec; | ||
24 | - } else if (def->flags & TCG_OPF_64BIT) { | ||
25 | - new_op = INDEX_op_movi_i64; | ||
26 | - } else { | ||
27 | - new_op = INDEX_op_movi_i32; | ||
28 | - } | ||
29 | - op->opc = new_op; | ||
30 | - /* TCGOP_VECL and TCGOP_VECE remain unchanged. */ | ||
31 | - op->args[0] = dst; | ||
32 | - op->args[1] = val; | ||
33 | - | ||
34 | - reset_temp(dst); | ||
35 | - di->is_const = true; | ||
36 | - di->val = val; | ||
37 | - mask = val; | ||
38 | - if (TCG_TARGET_REG_BITS > 32 && new_op == INDEX_op_movi_i32) { | ||
39 | - /* High bits of the destination are now garbage. */ | ||
40 | - mask |= ~0xffffffffull; | ||
41 | - } | ||
42 | - di->mask = mask; | ||
43 | -} | ||
44 | - | ||
45 | static void tcg_opt_gen_mov(TCGContext *s, TCGOp *op, TCGArg dst, TCGArg src) | ||
46 | { | 23 | { |
47 | TCGTemp *dst_ts = arg_temp(dst); | 24 | const TCGOpDef *def = &tcg_op_defs[op->opc]; |
48 | @@ -XXX,XX +XXX,XX @@ static void tcg_opt_gen_mov(TCGContext *s, TCGOp *op, TCGArg dst, TCGArg src) | 25 | MemOpIdx oi = op->args[def->nb_oargs + def->nb_iargs]; |
26 | MemOp mop = get_memop(oi); | ||
27 | int width = 8 * memop_size(mop); | ||
28 | + uint64_t z_mask = -1, s_mask = 0; | ||
29 | |||
30 | if (width < 64) { | ||
31 | if (mop & MO_SIGN) { | ||
32 | - ctx->s_mask = MAKE_64BIT_MASK(width, 64 - width); | ||
33 | + s_mask = MAKE_64BIT_MASK(width - 1, 64 - (width - 1)); | ||
34 | } else { | ||
35 | - ctx->z_mask = MAKE_64BIT_MASK(0, width); | ||
36 | + z_mask = MAKE_64BIT_MASK(0, width); | ||
37 | } | ||
49 | } | 38 | } |
50 | } | 39 | |
51 | 40 | /* Opcodes that touch guest memory stop the mb optimization. */ | |
52 | +static void tcg_opt_gen_movi(TCGContext *s, TCGTempSet *temps_used, | 41 | ctx->prev_mb = NULL; |
53 | + TCGOp *op, TCGArg dst, uint64_t val) | 42 | - return false; |
54 | +{ | ||
55 | + const TCGOpDef *def = &tcg_op_defs[op->opc]; | ||
56 | + TCGType type; | ||
57 | + TCGTemp *tv; | ||
58 | + | 43 | + |
59 | + if (def->flags & TCG_OPF_VECTOR) { | 44 | + return fold_masks_zs(ctx, op, z_mask, s_mask); |
60 | + type = TCGOP_VECL(op) + TCG_TYPE_V64; | ||
61 | + } else if (def->flags & TCG_OPF_64BIT) { | ||
62 | + type = TCG_TYPE_I64; | ||
63 | + } else { | ||
64 | + type = TCG_TYPE_I32; | ||
65 | + } | ||
66 | + | ||
67 | + /* Convert movi to mov with constant temp. */ | ||
68 | + tv = tcg_constant_internal(type, val); | ||
69 | + init_ts_info(temps_used, tv); | ||
70 | + tcg_opt_gen_mov(s, op, dst, temp_arg(tv)); | ||
71 | +} | 45 | +} |
72 | + | 46 | + |
73 | static uint64_t do_constant_folding_2(TCGOpcode op, uint64_t x, uint64_t y) | 47 | +static bool fold_qemu_ld_2reg(OptContext *ctx, TCGOp *op) |
74 | { | 48 | +{ |
75 | uint64_t l64, h64; | 49 | + /* Opcodes that touch guest memory stop the mb optimization. */ |
76 | @@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s) | 50 | + ctx->prev_mb = NULL; |
77 | nb_temps = s->nb_temps; | 51 | + return finish_folding(ctx, op); |
78 | nb_globals = s->nb_globals; | 52 | } |
79 | 53 | ||
80 | - bitmap_zero(temps_used.l, nb_temps); | 54 | static bool fold_qemu_st(OptContext *ctx, TCGOp *op) |
81 | + memset(&temps_used, 0, sizeof(temps_used)); | ||
82 | for (i = 0; i < nb_temps; ++i) { | ||
83 | s->temps[i].state_ptr = NULL; | ||
84 | } | ||
85 | @@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s) | ||
86 | CASE_OP_32_64(rotr): | ||
87 | if (arg_is_const(op->args[1]) | ||
88 | && arg_info(op->args[1])->val == 0) { | ||
89 | - tcg_opt_gen_movi(s, op, op->args[0], 0); | ||
90 | + tcg_opt_gen_movi(s, &temps_used, op, op->args[0], 0); | ||
91 | continue; | ||
92 | } | ||
93 | break; | ||
94 | @@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s) | ||
95 | |||
96 | if (partmask == 0) { | ||
97 | tcg_debug_assert(nb_oargs == 1); | ||
98 | - tcg_opt_gen_movi(s, op, op->args[0], 0); | ||
99 | + tcg_opt_gen_movi(s, &temps_used, op, op->args[0], 0); | ||
100 | continue; | ||
101 | } | ||
102 | if (affected == 0) { | ||
103 | @@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s) | ||
104 | CASE_OP_32_64(mulsh): | ||
105 | if (arg_is_const(op->args[2]) | ||
106 | && arg_info(op->args[2])->val == 0) { | ||
107 | - tcg_opt_gen_movi(s, op, op->args[0], 0); | ||
108 | + tcg_opt_gen_movi(s, &temps_used, op, op->args[0], 0); | ||
109 | continue; | ||
110 | } | ||
111 | break; | ||
112 | @@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s) | ||
113 | CASE_OP_32_64_VEC(sub): | ||
114 | CASE_OP_32_64_VEC(xor): | ||
115 | if (args_are_copies(op->args[1], op->args[2])) { | ||
116 | - tcg_opt_gen_movi(s, op, op->args[0], 0); | ||
117 | + tcg_opt_gen_movi(s, &temps_used, op, op->args[0], 0); | ||
118 | continue; | ||
119 | } | ||
120 | break; | ||
121 | @@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s) | 55 | @@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s) |
122 | break; | 56 | break; |
123 | CASE_OP_32_64(movi): | 57 | case INDEX_op_qemu_ld_a32_i32: |
124 | case INDEX_op_dupi_vec: | 58 | case INDEX_op_qemu_ld_a64_i32: |
125 | - tcg_opt_gen_movi(s, op, op->args[0], op->args[1]); | 59 | + done = fold_qemu_ld_1reg(&ctx, op); |
126 | + tcg_opt_gen_movi(s, &temps_used, op, op->args[0], op->args[1]); | 60 | + break; |
61 | case INDEX_op_qemu_ld_a32_i64: | ||
62 | case INDEX_op_qemu_ld_a64_i64: | ||
63 | + if (TCG_TARGET_REG_BITS == 64) { | ||
64 | + done = fold_qemu_ld_1reg(&ctx, op); | ||
65 | + break; | ||
66 | + } | ||
67 | + QEMU_FALLTHROUGH; | ||
68 | case INDEX_op_qemu_ld_a32_i128: | ||
69 | case INDEX_op_qemu_ld_a64_i128: | ||
70 | - done = fold_qemu_ld(&ctx, op); | ||
71 | + done = fold_qemu_ld_2reg(&ctx, op); | ||
127 | break; | 72 | break; |
128 | 73 | case INDEX_op_qemu_st8_a32_i32: | |
129 | case INDEX_op_dup_vec: | 74 | case INDEX_op_qemu_st8_a64_i32: |
130 | if (arg_is_const(op->args[1])) { | ||
131 | tmp = arg_info(op->args[1])->val; | ||
132 | tmp = dup_const(TCGOP_VECE(op), tmp); | ||
133 | - tcg_opt_gen_movi(s, op, op->args[0], tmp); | ||
134 | + tcg_opt_gen_movi(s, &temps_used, op, op->args[0], tmp); | ||
135 | break; | ||
136 | } | ||
137 | goto do_default; | ||
138 | @@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s) | ||
139 | if (arg_is_const(op->args[1]) && arg_is_const(op->args[2])) { | ||
140 | tmp = arg_info(op->args[1])->val; | ||
141 | if (tmp == arg_info(op->args[2])->val) { | ||
142 | - tcg_opt_gen_movi(s, op, op->args[0], tmp); | ||
143 | + tcg_opt_gen_movi(s, &temps_used, op, op->args[0], tmp); | ||
144 | break; | ||
145 | } | ||
146 | } else if (args_are_copies(op->args[1], op->args[2])) { | ||
147 | @@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s) | ||
148 | case INDEX_op_extrh_i64_i32: | ||
149 | if (arg_is_const(op->args[1])) { | ||
150 | tmp = do_constant_folding(opc, arg_info(op->args[1])->val, 0); | ||
151 | - tcg_opt_gen_movi(s, op, op->args[0], tmp); | ||
152 | + tcg_opt_gen_movi(s, &temps_used, op, op->args[0], tmp); | ||
153 | break; | ||
154 | } | ||
155 | goto do_default; | ||
156 | @@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s) | ||
157 | if (arg_is_const(op->args[1]) && arg_is_const(op->args[2])) { | ||
158 | tmp = do_constant_folding(opc, arg_info(op->args[1])->val, | ||
159 | arg_info(op->args[2])->val); | ||
160 | - tcg_opt_gen_movi(s, op, op->args[0], tmp); | ||
161 | + tcg_opt_gen_movi(s, &temps_used, op, op->args[0], tmp); | ||
162 | break; | ||
163 | } | ||
164 | goto do_default; | ||
165 | @@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s) | ||
166 | TCGArg v = arg_info(op->args[1])->val; | ||
167 | if (v != 0) { | ||
168 | tmp = do_constant_folding(opc, v, 0); | ||
169 | - tcg_opt_gen_movi(s, op, op->args[0], tmp); | ||
170 | + tcg_opt_gen_movi(s, &temps_used, op, op->args[0], tmp); | ||
171 | } else { | ||
172 | tcg_opt_gen_mov(s, op, op->args[0], op->args[2]); | ||
173 | } | ||
174 | @@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s) | ||
175 | tmp = deposit64(arg_info(op->args[1])->val, | ||
176 | op->args[3], op->args[4], | ||
177 | arg_info(op->args[2])->val); | ||
178 | - tcg_opt_gen_movi(s, op, op->args[0], tmp); | ||
179 | + tcg_opt_gen_movi(s, &temps_used, op, op->args[0], tmp); | ||
180 | break; | ||
181 | } | ||
182 | goto do_default; | ||
183 | @@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s) | ||
184 | if (arg_is_const(op->args[1])) { | ||
185 | tmp = extract64(arg_info(op->args[1])->val, | ||
186 | op->args[2], op->args[3]); | ||
187 | - tcg_opt_gen_movi(s, op, op->args[0], tmp); | ||
188 | + tcg_opt_gen_movi(s, &temps_used, op, op->args[0], tmp); | ||
189 | break; | ||
190 | } | ||
191 | goto do_default; | ||
192 | @@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s) | ||
193 | if (arg_is_const(op->args[1])) { | ||
194 | tmp = sextract64(arg_info(op->args[1])->val, | ||
195 | op->args[2], op->args[3]); | ||
196 | - tcg_opt_gen_movi(s, op, op->args[0], tmp); | ||
197 | + tcg_opt_gen_movi(s, &temps_used, op, op->args[0], tmp); | ||
198 | break; | ||
199 | } | ||
200 | goto do_default; | ||
201 | @@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s) | ||
202 | tmp = (int32_t)(((uint32_t)v1 >> shr) | | ||
203 | ((uint32_t)v2 << (32 - shr))); | ||
204 | } | ||
205 | - tcg_opt_gen_movi(s, op, op->args[0], tmp); | ||
206 | + tcg_opt_gen_movi(s, &temps_used, op, op->args[0], tmp); | ||
207 | break; | ||
208 | } | ||
209 | goto do_default; | ||
210 | @@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s) | ||
211 | tmp = do_constant_folding_cond(opc, op->args[1], | ||
212 | op->args[2], op->args[3]); | ||
213 | if (tmp != 2) { | ||
214 | - tcg_opt_gen_movi(s, op, op->args[0], tmp); | ||
215 | + tcg_opt_gen_movi(s, &temps_used, op, op->args[0], tmp); | ||
216 | break; | ||
217 | } | ||
218 | goto do_default; | ||
219 | @@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s) | ||
220 | op->args[1], op->args[2]); | ||
221 | if (tmp != 2) { | ||
222 | if (tmp) { | ||
223 | - bitmap_zero(temps_used.l, nb_temps); | ||
224 | + memset(&temps_used, 0, sizeof(temps_used)); | ||
225 | op->opc = INDEX_op_br; | ||
226 | op->args[0] = op->args[3]; | ||
227 | } else { | ||
228 | @@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s) | ||
229 | uint64_t a = ((uint64_t)ah << 32) | al; | ||
230 | uint64_t b = ((uint64_t)bh << 32) | bl; | ||
231 | TCGArg rl, rh; | ||
232 | - TCGOp *op2 = tcg_op_insert_before(s, op, INDEX_op_movi_i32); | ||
233 | + TCGOp *op2 = tcg_op_insert_before(s, op, INDEX_op_mov_i32); | ||
234 | |||
235 | if (opc == INDEX_op_add2_i32) { | ||
236 | a += b; | ||
237 | @@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s) | ||
238 | |||
239 | rl = op->args[0]; | ||
240 | rh = op->args[1]; | ||
241 | - tcg_opt_gen_movi(s, op, rl, (int32_t)a); | ||
242 | - tcg_opt_gen_movi(s, op2, rh, (int32_t)(a >> 32)); | ||
243 | + tcg_opt_gen_movi(s, &temps_used, op, rl, (int32_t)a); | ||
244 | + tcg_opt_gen_movi(s, &temps_used, op2, rh, (int32_t)(a >> 32)); | ||
245 | break; | ||
246 | } | ||
247 | goto do_default; | ||
248 | @@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s) | ||
249 | uint32_t b = arg_info(op->args[3])->val; | ||
250 | uint64_t r = (uint64_t)a * b; | ||
251 | TCGArg rl, rh; | ||
252 | - TCGOp *op2 = tcg_op_insert_before(s, op, INDEX_op_movi_i32); | ||
253 | + TCGOp *op2 = tcg_op_insert_before(s, op, INDEX_op_mov_i32); | ||
254 | |||
255 | rl = op->args[0]; | ||
256 | rh = op->args[1]; | ||
257 | - tcg_opt_gen_movi(s, op, rl, (int32_t)r); | ||
258 | - tcg_opt_gen_movi(s, op2, rh, (int32_t)(r >> 32)); | ||
259 | + tcg_opt_gen_movi(s, &temps_used, op, rl, (int32_t)r); | ||
260 | + tcg_opt_gen_movi(s, &temps_used, op2, rh, (int32_t)(r >> 32)); | ||
261 | break; | ||
262 | } | ||
263 | goto do_default; | ||
264 | @@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s) | ||
265 | if (tmp != 2) { | ||
266 | if (tmp) { | ||
267 | do_brcond_true: | ||
268 | - bitmap_zero(temps_used.l, nb_temps); | ||
269 | + memset(&temps_used, 0, sizeof(temps_used)); | ||
270 | op->opc = INDEX_op_br; | ||
271 | op->args[0] = op->args[5]; | ||
272 | } else { | ||
273 | @@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s) | ||
274 | /* Simplify LT/GE comparisons vs zero to a single compare | ||
275 | vs the high word of the input. */ | ||
276 | do_brcond_high: | ||
277 | - bitmap_zero(temps_used.l, nb_temps); | ||
278 | + memset(&temps_used, 0, sizeof(temps_used)); | ||
279 | op->opc = INDEX_op_brcond_i32; | ||
280 | op->args[0] = op->args[1]; | ||
281 | op->args[1] = op->args[3]; | ||
282 | @@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s) | ||
283 | goto do_default; | ||
284 | } | ||
285 | do_brcond_low: | ||
286 | - bitmap_zero(temps_used.l, nb_temps); | ||
287 | + memset(&temps_used, 0, sizeof(temps_used)); | ||
288 | op->opc = INDEX_op_brcond_i32; | ||
289 | op->args[1] = op->args[2]; | ||
290 | op->args[2] = op->args[4]; | ||
291 | @@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s) | ||
292 | op->args[5]); | ||
293 | if (tmp != 2) { | ||
294 | do_setcond_const: | ||
295 | - tcg_opt_gen_movi(s, op, op->args[0], tmp); | ||
296 | + tcg_opt_gen_movi(s, &temps_used, op, op->args[0], tmp); | ||
297 | } else if ((op->args[5] == TCG_COND_LT | ||
298 | || op->args[5] == TCG_COND_GE) | ||
299 | && arg_is_const(op->args[3]) | ||
300 | @@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s) | ||
301 | block, otherwise we only trash the output args. "mask" is | ||
302 | the non-zero bits mask for the first output arg. */ | ||
303 | if (def->flags & TCG_OPF_BB_END) { | ||
304 | - bitmap_zero(temps_used.l, nb_temps); | ||
305 | + memset(&temps_used, 0, sizeof(temps_used)); | ||
306 | } else { | ||
307 | do_reset_output: | ||
308 | for (i = 0; i < nb_oargs; i++) { | ||
309 | -- | 75 | -- |
310 | 2.25.1 | 76 | 2.43.0 |
311 | |||
312 | diff view generated by jsdifflib |
1 | Fix this name vs our coding style. | 1 | Stores have no output operands, and so need no further work. |
---|---|---|---|
2 | 2 | ||
3 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | 3 | Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> |
4 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
5 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 4 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
6 | --- | 5 | --- |
7 | tcg/optimize.c | 32 ++++++++++++++++---------------- | 6 | tcg/optimize.c | 11 +++++------ |
8 | 1 file changed, 16 insertions(+), 16 deletions(-) | 7 | 1 file changed, 5 insertions(+), 6 deletions(-) |
9 | 8 | ||
10 | diff --git a/tcg/optimize.c b/tcg/optimize.c | 9 | diff --git a/tcg/optimize.c b/tcg/optimize.c |
11 | index XXXXXXX..XXXXXXX 100644 | 10 | index XXXXXXX..XXXXXXX 100644 |
12 | --- a/tcg/optimize.c | 11 | --- a/tcg/optimize.c |
13 | +++ b/tcg/optimize.c | 12 | +++ b/tcg/optimize.c |
14 | @@ -XXX,XX +XXX,XX @@ | 13 | @@ -XXX,XX +XXX,XX @@ static bool fold_qemu_st(OptContext *ctx, TCGOp *op) |
15 | glue(glue(case INDEX_op_, x), _i64): \ | ||
16 | glue(glue(case INDEX_op_, x), _vec) | ||
17 | |||
18 | -struct tcg_temp_info { | ||
19 | +typedef struct TempOptInfo { | ||
20 | bool is_const; | ||
21 | TCGTemp *prev_copy; | ||
22 | TCGTemp *next_copy; | ||
23 | tcg_target_ulong val; | ||
24 | tcg_target_ulong mask; | ||
25 | -}; | ||
26 | +} TempOptInfo; | ||
27 | |||
28 | -static inline struct tcg_temp_info *ts_info(TCGTemp *ts) | ||
29 | +static inline TempOptInfo *ts_info(TCGTemp *ts) | ||
30 | { | 14 | { |
31 | return ts->state_ptr; | 15 | /* Opcodes that touch guest memory stop the mb optimization. */ |
16 | ctx->prev_mb = NULL; | ||
17 | - return false; | ||
18 | + return true; | ||
32 | } | 19 | } |
33 | 20 | ||
34 | -static inline struct tcg_temp_info *arg_info(TCGArg arg) | 21 | static bool fold_remainder(OptContext *ctx, TCGOp *op) |
35 | +static inline TempOptInfo *arg_info(TCGArg arg) | 22 | @@ -XXX,XX +XXX,XX @@ static bool fold_tcg_st(OptContext *ctx, TCGOp *op) |
36 | { | 23 | |
37 | return ts_info(arg_temp(arg)); | 24 | if (op->args[1] != tcgv_ptr_arg(tcg_env)) { |
25 | remove_mem_copy_all(ctx); | ||
26 | - return false; | ||
27 | + return true; | ||
28 | } | ||
29 | |||
30 | switch (op->opc) { | ||
31 | @@ -XXX,XX +XXX,XX @@ static bool fold_tcg_st(OptContext *ctx, TCGOp *op) | ||
32 | g_assert_not_reached(); | ||
33 | } | ||
34 | remove_mem_copy_in(ctx, ofs, ofs + lm1); | ||
35 | - return false; | ||
36 | + return true; | ||
38 | } | 37 | } |
39 | @@ -XXX,XX +XXX,XX @@ static inline bool ts_is_copy(TCGTemp *ts) | 38 | |
40 | /* Reset TEMP's state, possibly removing the temp for the list of copies. */ | 39 | static bool fold_tcg_st_memcopy(OptContext *ctx, TCGOp *op) |
41 | static void reset_ts(TCGTemp *ts) | 40 | @@ -XXX,XX +XXX,XX @@ static bool fold_tcg_st_memcopy(OptContext *ctx, TCGOp *op) |
42 | { | 41 | TCGType type; |
43 | - struct tcg_temp_info *ti = ts_info(ts); | 42 | |
44 | - struct tcg_temp_info *pi = ts_info(ti->prev_copy); | 43 | if (op->args[1] != tcgv_ptr_arg(tcg_env)) { |
45 | - struct tcg_temp_info *ni = ts_info(ti->next_copy); | 44 | - fold_tcg_st(ctx, op); |
46 | + TempOptInfo *ti = ts_info(ts); | 45 | - return false; |
47 | + TempOptInfo *pi = ts_info(ti->prev_copy); | 46 | + return fold_tcg_st(ctx, op); |
48 | + TempOptInfo *ni = ts_info(ti->next_copy); | 47 | } |
49 | 48 | ||
50 | ni->prev_copy = ti->prev_copy; | 49 | src = arg_temp(op->args[0]); |
51 | pi->next_copy = ti->next_copy; | 50 | @@ -XXX,XX +XXX,XX @@ static bool fold_tcg_st_memcopy(OptContext *ctx, TCGOp *op) |
52 | @@ -XXX,XX +XXX,XX @@ static void reset_temp(TCGArg arg) | 51 | last = ofs + tcg_type_size(type) - 1; |
52 | remove_mem_copy_in(ctx, ofs, last); | ||
53 | record_mem_copy(ctx, type, src, ofs, last); | ||
54 | - return false; | ||
55 | + return true; | ||
53 | } | 56 | } |
54 | 57 | ||
55 | /* Initialize and activate a temporary. */ | 58 | static bool fold_xor(OptContext *ctx, TCGOp *op) |
56 | -static void init_ts_info(struct tcg_temp_info *infos, | ||
57 | +static void init_ts_info(TempOptInfo *infos, | ||
58 | TCGTempSet *temps_used, TCGTemp *ts) | ||
59 | { | ||
60 | size_t idx = temp_idx(ts); | ||
61 | if (!test_bit(idx, temps_used->l)) { | ||
62 | - struct tcg_temp_info *ti = &infos[idx]; | ||
63 | + TempOptInfo *ti = &infos[idx]; | ||
64 | |||
65 | ts->state_ptr = ti; | ||
66 | ti->next_copy = ts; | ||
67 | @@ -XXX,XX +XXX,XX @@ static void init_ts_info(struct tcg_temp_info *infos, | ||
68 | } | ||
69 | } | ||
70 | |||
71 | -static void init_arg_info(struct tcg_temp_info *infos, | ||
72 | +static void init_arg_info(TempOptInfo *infos, | ||
73 | TCGTempSet *temps_used, TCGArg arg) | ||
74 | { | ||
75 | init_ts_info(infos, temps_used, arg_temp(arg)); | ||
76 | @@ -XXX,XX +XXX,XX @@ static void tcg_opt_gen_movi(TCGContext *s, TCGOp *op, TCGArg dst, TCGArg val) | ||
77 | const TCGOpDef *def; | ||
78 | TCGOpcode new_op; | ||
79 | tcg_target_ulong mask; | ||
80 | - struct tcg_temp_info *di = arg_info(dst); | ||
81 | + TempOptInfo *di = arg_info(dst); | ||
82 | |||
83 | def = &tcg_op_defs[op->opc]; | ||
84 | if (def->flags & TCG_OPF_VECTOR) { | ||
85 | @@ -XXX,XX +XXX,XX @@ static void tcg_opt_gen_mov(TCGContext *s, TCGOp *op, TCGArg dst, TCGArg src) | ||
86 | TCGTemp *dst_ts = arg_temp(dst); | ||
87 | TCGTemp *src_ts = arg_temp(src); | ||
88 | const TCGOpDef *def; | ||
89 | - struct tcg_temp_info *di; | ||
90 | - struct tcg_temp_info *si; | ||
91 | + TempOptInfo *di; | ||
92 | + TempOptInfo *si; | ||
93 | tcg_target_ulong mask; | ||
94 | TCGOpcode new_op; | ||
95 | |||
96 | @@ -XXX,XX +XXX,XX @@ static void tcg_opt_gen_mov(TCGContext *s, TCGOp *op, TCGArg dst, TCGArg src) | ||
97 | di->mask = mask; | ||
98 | |||
99 | if (src_ts->type == dst_ts->type) { | ||
100 | - struct tcg_temp_info *ni = ts_info(si->next_copy); | ||
101 | + TempOptInfo *ni = ts_info(si->next_copy); | ||
102 | |||
103 | di->next_copy = si->next_copy; | ||
104 | di->prev_copy = src_ts; | ||
105 | @@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s) | ||
106 | { | ||
107 | int nb_temps, nb_globals; | ||
108 | TCGOp *op, *op_next, *prev_mb = NULL; | ||
109 | - struct tcg_temp_info *infos; | ||
110 | + TempOptInfo *infos; | ||
111 | TCGTempSet temps_used; | ||
112 | |||
113 | /* Array VALS has an element for each temp. | ||
114 | @@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s) | ||
115 | nb_temps = s->nb_temps; | ||
116 | nb_globals = s->nb_globals; | ||
117 | bitmap_zero(temps_used.l, nb_temps); | ||
118 | - infos = tcg_malloc(sizeof(struct tcg_temp_info) * nb_temps); | ||
119 | + infos = tcg_malloc(sizeof(TempOptInfo) * nb_temps); | ||
120 | |||
121 | QTAILQ_FOREACH_SAFE(op, &s->ops, link, op_next) { | ||
122 | tcg_target_ulong mask, partmask, affected; | ||
123 | -- | 59 | -- |
124 | 2.25.1 | 60 | 2.43.0 |
125 | |||
126 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> | ||
2 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
3 | --- | ||
4 | tcg/optimize.c | 2 +- | ||
5 | 1 file changed, 1 insertion(+), 1 deletion(-) | ||
1 | 6 | ||
7 | diff --git a/tcg/optimize.c b/tcg/optimize.c | ||
8 | index XXXXXXX..XXXXXXX 100644 | ||
9 | --- a/tcg/optimize.c | ||
10 | +++ b/tcg/optimize.c | ||
11 | @@ -XXX,XX +XXX,XX @@ static bool fold_remainder(OptContext *ctx, TCGOp *op) | ||
12 | fold_xx_to_i(ctx, op, 0)) { | ||
13 | return true; | ||
14 | } | ||
15 | - return false; | ||
16 | + return finish_folding(ctx, op); | ||
17 | } | ||
18 | |||
19 | static bool fold_setcond_zmask(OptContext *ctx, TCGOp *op, bool neg) | ||
20 | -- | ||
21 | 2.43.0 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Change return from bool to int; distinguish between | ||
2 | complete folding, simplification, and no change. | ||
1 | 3 | ||
4 | Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> | ||
5 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
6 | --- | ||
7 | tcg/optimize.c | 22 ++++++++++++++-------- | ||
8 | 1 file changed, 14 insertions(+), 8 deletions(-) | ||
9 | |||
10 | diff --git a/tcg/optimize.c b/tcg/optimize.c | ||
11 | index XXXXXXX..XXXXXXX 100644 | ||
12 | --- a/tcg/optimize.c | ||
13 | +++ b/tcg/optimize.c | ||
14 | @@ -XXX,XX +XXX,XX @@ static bool fold_remainder(OptContext *ctx, TCGOp *op) | ||
15 | return finish_folding(ctx, op); | ||
16 | } | ||
17 | |||
18 | -static bool fold_setcond_zmask(OptContext *ctx, TCGOp *op, bool neg) | ||
19 | +/* Return 1 if finished, -1 if simplified, 0 if unchanged. */ | ||
20 | +static int fold_setcond_zmask(OptContext *ctx, TCGOp *op, bool neg) | ||
21 | { | ||
22 | uint64_t a_zmask, b_val; | ||
23 | TCGCond cond; | ||
24 | @@ -XXX,XX +XXX,XX @@ static bool fold_setcond_zmask(OptContext *ctx, TCGOp *op, bool neg) | ||
25 | op->opc = xor_opc; | ||
26 | op->args[2] = arg_new_constant(ctx, 1); | ||
27 | } | ||
28 | - return false; | ||
29 | + return -1; | ||
30 | } | ||
31 | } | ||
32 | - | ||
33 | - return false; | ||
34 | + return 0; | ||
35 | } | ||
36 | |||
37 | static void fold_setcond_tst_pow2(OptContext *ctx, TCGOp *op, bool neg) | ||
38 | @@ -XXX,XX +XXX,XX @@ static bool fold_setcond(OptContext *ctx, TCGOp *op) | ||
39 | return tcg_opt_gen_movi(ctx, op, op->args[0], i); | ||
40 | } | ||
41 | |||
42 | - if (fold_setcond_zmask(ctx, op, false)) { | ||
43 | + i = fold_setcond_zmask(ctx, op, false); | ||
44 | + if (i > 0) { | ||
45 | return true; | ||
46 | } | ||
47 | - fold_setcond_tst_pow2(ctx, op, false); | ||
48 | + if (i == 0) { | ||
49 | + fold_setcond_tst_pow2(ctx, op, false); | ||
50 | + } | ||
51 | |||
52 | ctx->z_mask = 1; | ||
53 | return false; | ||
54 | @@ -XXX,XX +XXX,XX @@ static bool fold_negsetcond(OptContext *ctx, TCGOp *op) | ||
55 | return tcg_opt_gen_movi(ctx, op, op->args[0], -i); | ||
56 | } | ||
57 | |||
58 | - if (fold_setcond_zmask(ctx, op, true)) { | ||
59 | + i = fold_setcond_zmask(ctx, op, true); | ||
60 | + if (i > 0) { | ||
61 | return true; | ||
62 | } | ||
63 | - fold_setcond_tst_pow2(ctx, op, true); | ||
64 | + if (i == 0) { | ||
65 | + fold_setcond_tst_pow2(ctx, op, true); | ||
66 | + } | ||
67 | |||
68 | /* Value is {0,-1} so all bits are repetitions of the sign. */ | ||
69 | ctx->s_mask = -1; | ||
70 | -- | ||
71 | 2.43.0 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Avoid the use of the OptContext slots. | ||
1 | 2 | ||
3 | Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> | ||
4 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
5 | --- | ||
6 | tcg/optimize.c | 3 +-- | ||
7 | 1 file changed, 1 insertion(+), 2 deletions(-) | ||
8 | |||
9 | diff --git a/tcg/optimize.c b/tcg/optimize.c | ||
10 | index XXXXXXX..XXXXXXX 100644 | ||
11 | --- a/tcg/optimize.c | ||
12 | +++ b/tcg/optimize.c | ||
13 | @@ -XXX,XX +XXX,XX @@ static bool fold_setcond(OptContext *ctx, TCGOp *op) | ||
14 | fold_setcond_tst_pow2(ctx, op, false); | ||
15 | } | ||
16 | |||
17 | - ctx->z_mask = 1; | ||
18 | - return false; | ||
19 | + return fold_masks_z(ctx, op, 1); | ||
20 | } | ||
21 | |||
22 | static bool fold_negsetcond(OptContext *ctx, TCGOp *op) | ||
23 | -- | ||
24 | 2.43.0 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Avoid the use of the OptContext slots. | ||
1 | 2 | ||
3 | Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> | ||
4 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
5 | --- | ||
6 | tcg/optimize.c | 3 +-- | ||
7 | 1 file changed, 1 insertion(+), 2 deletions(-) | ||
8 | |||
9 | diff --git a/tcg/optimize.c b/tcg/optimize.c | ||
10 | index XXXXXXX..XXXXXXX 100644 | ||
11 | --- a/tcg/optimize.c | ||
12 | +++ b/tcg/optimize.c | ||
13 | @@ -XXX,XX +XXX,XX @@ static bool fold_negsetcond(OptContext *ctx, TCGOp *op) | ||
14 | } | ||
15 | |||
16 | /* Value is {0,-1} so all bits are repetitions of the sign. */ | ||
17 | - ctx->s_mask = -1; | ||
18 | - return false; | ||
19 | + return fold_masks_s(ctx, op, -1); | ||
20 | } | ||
21 | |||
22 | static bool fold_setcond2(OptContext *ctx, TCGOp *op) | ||
23 | -- | ||
24 | 2.43.0 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Avoid the use of the OptContext slots. | ||
1 | 2 | ||
3 | Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> | ||
4 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
5 | --- | ||
6 | tcg/optimize.c | 3 +-- | ||
7 | 1 file changed, 1 insertion(+), 2 deletions(-) | ||
8 | |||
9 | diff --git a/tcg/optimize.c b/tcg/optimize.c | ||
10 | index XXXXXXX..XXXXXXX 100644 | ||
11 | --- a/tcg/optimize.c | ||
12 | +++ b/tcg/optimize.c | ||
13 | @@ -XXX,XX +XXX,XX @@ static bool fold_setcond2(OptContext *ctx, TCGOp *op) | ||
14 | return fold_setcond(ctx, op); | ||
15 | } | ||
16 | |||
17 | - ctx->z_mask = 1; | ||
18 | - return false; | ||
19 | + return fold_masks_z(ctx, op, 1); | ||
20 | |||
21 | do_setcond_const: | ||
22 | return tcg_opt_gen_movi(ctx, op, op->args[0], i); | ||
23 | -- | ||
24 | 2.43.0 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> | ||
2 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
3 | --- | ||
4 | tcg/optimize.c | 2 +- | ||
5 | 1 file changed, 1 insertion(+), 1 deletion(-) | ||
1 | 6 | ||
7 | diff --git a/tcg/optimize.c b/tcg/optimize.c | ||
8 | index XXXXXXX..XXXXXXX 100644 | ||
9 | --- a/tcg/optimize.c | ||
10 | +++ b/tcg/optimize.c | ||
11 | @@ -XXX,XX +XXX,XX @@ static bool fold_cmp_vec(OptContext *ctx, TCGOp *op) | ||
12 | if (swap_commutative(NO_DEST, &op->args[1], &op->args[2])) { | ||
13 | op->args[3] = tcg_swap_cond(op->args[3]); | ||
14 | } | ||
15 | - return false; | ||
16 | + return finish_folding(ctx, op); | ||
17 | } | ||
18 | |||
19 | static bool fold_cmpsel_vec(OptContext *ctx, TCGOp *op) | ||
20 | -- | ||
21 | 2.43.0 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> | ||
2 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
3 | --- | ||
4 | tcg/optimize.c | 2 +- | ||
5 | 1 file changed, 1 insertion(+), 1 deletion(-) | ||
1 | 6 | ||
7 | diff --git a/tcg/optimize.c b/tcg/optimize.c | ||
8 | index XXXXXXX..XXXXXXX 100644 | ||
9 | --- a/tcg/optimize.c | ||
10 | +++ b/tcg/optimize.c | ||
11 | @@ -XXX,XX +XXX,XX @@ static bool fold_cmpsel_vec(OptContext *ctx, TCGOp *op) | ||
12 | if (swap_commutative(op->args[0], &op->args[4], &op->args[3])) { | ||
13 | op->args[5] = tcg_invert_cond(op->args[5]); | ||
14 | } | ||
15 | - return false; | ||
16 | + return finish_folding(ctx, op); | ||
17 | } | ||
18 | |||
19 | static bool fold_sextract(OptContext *ctx, TCGOp *op) | ||
20 | -- | ||
21 | 2.43.0 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Avoid the use of the OptContext slots. Find TempOptInfo once. | ||
1 | 2 | ||
3 | Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> | ||
4 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
5 | --- | ||
6 | tcg/optimize.c | 24 +++++++++--------------- | ||
7 | 1 file changed, 9 insertions(+), 15 deletions(-) | ||
8 | |||
9 | diff --git a/tcg/optimize.c b/tcg/optimize.c | ||
10 | index XXXXXXX..XXXXXXX 100644 | ||
11 | --- a/tcg/optimize.c | ||
12 | +++ b/tcg/optimize.c | ||
13 | @@ -XXX,XX +XXX,XX @@ static bool fold_cmpsel_vec(OptContext *ctx, TCGOp *op) | ||
14 | static bool fold_sextract(OptContext *ctx, TCGOp *op) | ||
15 | { | ||
16 | uint64_t z_mask, s_mask, s_mask_old; | ||
17 | + TempOptInfo *t1 = arg_info(op->args[1]); | ||
18 | int pos = op->args[2]; | ||
19 | int len = op->args[3]; | ||
20 | |||
21 | - if (arg_is_const(op->args[1])) { | ||
22 | - uint64_t t; | ||
23 | - | ||
24 | - t = arg_info(op->args[1])->val; | ||
25 | - t = sextract64(t, pos, len); | ||
26 | - return tcg_opt_gen_movi(ctx, op, op->args[0], t); | ||
27 | + if (ti_is_const(t1)) { | ||
28 | + return tcg_opt_gen_movi(ctx, op, op->args[0], | ||
29 | + sextract64(ti_const_val(t1), pos, len)); | ||
30 | } | ||
31 | |||
32 | - z_mask = arg_info(op->args[1])->z_mask; | ||
33 | - z_mask = sextract64(z_mask, pos, len); | ||
34 | - ctx->z_mask = z_mask; | ||
35 | - | ||
36 | - s_mask_old = arg_info(op->args[1])->s_mask; | ||
37 | - s_mask = sextract64(s_mask_old, pos, len); | ||
38 | - s_mask |= MAKE_64BIT_MASK(len, 64 - len); | ||
39 | - ctx->s_mask = s_mask; | ||
40 | + s_mask_old = t1->s_mask; | ||
41 | + s_mask = s_mask_old >> pos; | ||
42 | + s_mask |= -1ull << (len - 1); | ||
43 | |||
44 | if (0 && pos == 0 && fold_affected_mask(ctx, op, s_mask & ~s_mask_old)) { | ||
45 | return true; | ||
46 | } | ||
47 | |||
48 | - return fold_masks(ctx, op); | ||
49 | + z_mask = sextract64(t1->z_mask, pos, len); | ||
50 | + return fold_masks_zs(ctx, op, z_mask, s_mask); | ||
51 | } | ||
52 | |||
53 | static bool fold_shift(OptContext *ctx, TCGOp *op) | ||
54 | -- | ||
55 | 2.43.0 | diff view generated by jsdifflib |
1 | We must do this before we adjust tcg_out_movi_i32, lest the | 1 | Avoid the use of the OptContext slots. Find TempOptInfo once. |
---|---|---|---|
2 | under-the-hood poking that we do for icount be broken. | ||
3 | 2 | ||
4 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | 3 | Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> |
5 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 4 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
6 | --- | 5 | --- |
7 | include/exec/gen-icount.h | 25 +++++++++++++------------ | 6 | tcg/optimize.c | 27 ++++++++++++++------------- |
8 | 1 file changed, 13 insertions(+), 12 deletions(-) | 7 | 1 file changed, 14 insertions(+), 13 deletions(-) |
9 | 8 | ||
10 | diff --git a/include/exec/gen-icount.h b/include/exec/gen-icount.h | 9 | diff --git a/tcg/optimize.c b/tcg/optimize.c |
11 | index XXXXXXX..XXXXXXX 100644 | 10 | index XXXXXXX..XXXXXXX 100644 |
12 | --- a/include/exec/gen-icount.h | 11 | --- a/tcg/optimize.c |
13 | +++ b/include/exec/gen-icount.h | 12 | +++ b/tcg/optimize.c |
14 | @@ -XXX,XX +XXX,XX @@ static inline void gen_io_end(void) | 13 | @@ -XXX,XX +XXX,XX @@ static bool fold_sextract(OptContext *ctx, TCGOp *op) |
15 | 14 | static bool fold_shift(OptContext *ctx, TCGOp *op) | |
16 | static inline void gen_tb_start(const TranslationBlock *tb) | ||
17 | { | 15 | { |
18 | - TCGv_i32 count, imm; | 16 | uint64_t s_mask, z_mask, sign; |
19 | + TCGv_i32 count; | 17 | + TempOptInfo *t1, *t2; |
20 | 18 | ||
21 | tcg_ctx->exitreq_label = gen_new_label(); | 19 | if (fold_const2(ctx, op) || |
22 | if (tb_cflags(tb) & CF_USE_ICOUNT) { | 20 | fold_ix_to_i(ctx, op, 0) || |
23 | @@ -XXX,XX +XXX,XX @@ static inline void gen_tb_start(const TranslationBlock *tb) | 21 | @@ -XXX,XX +XXX,XX @@ static bool fold_shift(OptContext *ctx, TCGOp *op) |
24 | offsetof(ArchCPU, env)); | 22 | return true; |
25 | 23 | } | |
26 | if (tb_cflags(tb) & CF_USE_ICOUNT) { | 24 | |
27 | - imm = tcg_temp_new_i32(); | 25 | - s_mask = arg_info(op->args[1])->s_mask; |
28 | - /* We emit a movi with a dummy immediate argument. Keep the insn index | 26 | - z_mask = arg_info(op->args[1])->z_mask; |
29 | - * of the movi so that we later (when we know the actual insn count) | 27 | + t1 = arg_info(op->args[1]); |
30 | - * can update the immediate argument with the actual insn count. */ | 28 | + t2 = arg_info(op->args[2]); |
31 | - tcg_gen_movi_i32(imm, 0xdeadbeef); | 29 | + s_mask = t1->s_mask; |
32 | + /* | 30 | + z_mask = t1->z_mask; |
33 | + * We emit a sub with a dummy immediate argument. Keep the insn index | 31 | |
34 | + * of the sub so that we later (when we know the actual insn count) | 32 | - if (arg_is_const(op->args[2])) { |
35 | + * can update the argument with the actual insn count. | 33 | - int sh = arg_info(op->args[2])->val; |
36 | + */ | ||
37 | + tcg_gen_sub_i32(count, count, tcg_constant_i32(0)); | ||
38 | icount_start_insn = tcg_last_op(); | ||
39 | - | 34 | - |
40 | - tcg_gen_sub_i32(count, count, imm); | 35 | - ctx->z_mask = do_constant_folding(op->opc, ctx->type, z_mask, sh); |
41 | - tcg_temp_free_i32(imm); | 36 | + if (ti_is_const(t2)) { |
37 | + int sh = ti_const_val(t2); | ||
38 | |||
39 | + z_mask = do_constant_folding(op->opc, ctx->type, z_mask, sh); | ||
40 | s_mask = do_constant_folding(op->opc, ctx->type, s_mask, sh); | ||
41 | |||
42 | - return fold_masks(ctx, op); | ||
43 | + return fold_masks_zs(ctx, op, z_mask, s_mask); | ||
42 | } | 44 | } |
43 | 45 | ||
44 | tcg_gen_brcondi_i32(TCG_COND_LT, count, 0, tcg_ctx->exitreq_label); | 46 | switch (op->opc) { |
45 | @@ -XXX,XX +XXX,XX @@ static inline void gen_tb_start(const TranslationBlock *tb) | 47 | @@ -XXX,XX +XXX,XX @@ static bool fold_shift(OptContext *ctx, TCGOp *op) |
46 | static inline void gen_tb_end(const TranslationBlock *tb, int num_insns) | 48 | * Arithmetic right shift will not reduce the number of |
47 | { | 49 | * input sign repetitions. |
48 | if (tb_cflags(tb) & CF_USE_ICOUNT) { | 50 | */ |
49 | - /* Update the num_insn immediate parameter now that we know | 51 | - ctx->s_mask = s_mask; |
50 | - * the actual insn count. */ | 52 | - break; |
51 | - tcg_set_insn_param(icount_start_insn, 1, num_insns); | 53 | + return fold_masks_s(ctx, op, s_mask); |
52 | + /* | 54 | CASE_OP_32_64(shr): |
53 | + * Update the num_insn immediate parameter now that we know | 55 | /* |
54 | + * the actual insn count. | 56 | * If the sign bit is known zero, then logical right shift |
55 | + */ | 57 | - * will not reduced the number of input sign repetitions. |
56 | + tcg_set_insn_param(icount_start_insn, 2, | 58 | + * will not reduce the number of input sign repetitions. |
57 | + tcgv_i32_arg(tcg_constant_i32(num_insns))); | 59 | */ |
60 | - sign = (s_mask & -s_mask) >> 1; | ||
61 | + sign = -s_mask; | ||
62 | if (sign && !(z_mask & sign)) { | ||
63 | - ctx->s_mask = s_mask; | ||
64 | + return fold_masks_s(ctx, op, s_mask); | ||
65 | } | ||
66 | break; | ||
67 | default: | ||
68 | break; | ||
58 | } | 69 | } |
59 | 70 | ||
60 | gen_set_label(tcg_ctx->exitreq_label); | 71 | - return false; |
72 | + return finish_folding(ctx, op); | ||
73 | } | ||
74 | |||
75 | static bool fold_sub_to_neg(OptContext *ctx, TCGOp *op) | ||
61 | -- | 76 | -- |
62 | 2.25.1 | 77 | 2.43.0 |
63 | |||
64 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Merge the two conditions, sign != 0 && !(z_mask & sign), | ||
2 | by testing ~z_mask & sign. If sign == 0, the logical and | ||
3 | will produce false. | ||
1 | 4 | ||
5 | Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> | ||
6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | --- | ||
8 | tcg/optimize.c | 5 ++--- | ||
9 | 1 file changed, 2 insertions(+), 3 deletions(-) | ||
10 | |||
11 | diff --git a/tcg/optimize.c b/tcg/optimize.c | ||
12 | index XXXXXXX..XXXXXXX 100644 | ||
13 | --- a/tcg/optimize.c | ||
14 | +++ b/tcg/optimize.c | ||
15 | @@ -XXX,XX +XXX,XX @@ static bool fold_sextract(OptContext *ctx, TCGOp *op) | ||
16 | |||
17 | static bool fold_shift(OptContext *ctx, TCGOp *op) | ||
18 | { | ||
19 | - uint64_t s_mask, z_mask, sign; | ||
20 | + uint64_t s_mask, z_mask; | ||
21 | TempOptInfo *t1, *t2; | ||
22 | |||
23 | if (fold_const2(ctx, op) || | ||
24 | @@ -XXX,XX +XXX,XX @@ static bool fold_shift(OptContext *ctx, TCGOp *op) | ||
25 | * If the sign bit is known zero, then logical right shift | ||
26 | * will not reduce the number of input sign repetitions. | ||
27 | */ | ||
28 | - sign = -s_mask; | ||
29 | - if (sign && !(z_mask & sign)) { | ||
30 | + if (~z_mask & -s_mask) { | ||
31 | return fold_masks_s(ctx, op, s_mask); | ||
32 | } | ||
33 | break; | ||
34 | -- | ||
35 | 2.43.0 | diff view generated by jsdifflib |
1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> | 1 | Duplicate fold_sub_vec into fold_sub instead of calling it, |
---|---|---|---|
2 | now that fold_sub_vec always returns true. | ||
2 | 3 | ||
3 | When decodetree.py was added in commit 568ae7efae7, QEMU was | 4 | Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> |
4 | using Python 2 which happily reads UTF-8 files in text mode. | ||
5 | Python 3 requires either UTF-8 locale or an explicit encoding | ||
6 | passed to open(). Now that Python 3 is required, explicit | ||
7 | UTF-8 encoding for decodetree source files. | ||
8 | |||
9 | To avoid further problems with the user locale, also explicit | ||
10 | UTF-8 encoding for the generated C files. | ||
11 | |||
12 | Explicit both input/output are plain text by using the 't' mode. | ||
13 | |||
14 | This fixes: | ||
15 | |||
16 | $ /usr/bin/python3 scripts/decodetree.py test.decode | ||
17 | Traceback (most recent call last): | ||
18 | File "scripts/decodetree.py", line 1397, in <module> | ||
19 | main() | ||
20 | File "scripts/decodetree.py", line 1308, in main | ||
21 | parse_file(f, toppat) | ||
22 | File "scripts/decodetree.py", line 994, in parse_file | ||
23 | for line in f: | ||
24 | File "/usr/lib/python3.6/encodings/ascii.py", line 26, in decode | ||
25 | return codecs.ascii_decode(input, self.errors)[0] | ||
26 | UnicodeDecodeError: 'ascii' codec can't decode byte 0xc3 in position 80: | ||
27 | ordinal not in range(128) | ||
28 | |||
29 | Reported-by: Peter Maydell <peter.maydell@linaro.org> | ||
30 | Suggested-by: Yonggang Luo <luoyonggang@gmail.com> | ||
31 | Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> | ||
32 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
33 | Message-Id: <20210110000240.761122-1-f4bug@amsat.org> | ||
34 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 5 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
35 | --- | 6 | --- |
36 | scripts/decodetree.py | 9 ++++++--- | 7 | tcg/optimize.c | 9 ++++++--- |
37 | 1 file changed, 6 insertions(+), 3 deletions(-) | 8 | 1 file changed, 6 insertions(+), 3 deletions(-) |
38 | 9 | ||
39 | diff --git a/scripts/decodetree.py b/scripts/decodetree.py | 10 | diff --git a/tcg/optimize.c b/tcg/optimize.c |
40 | index XXXXXXX..XXXXXXX 100644 | 11 | index XXXXXXX..XXXXXXX 100644 |
41 | --- a/scripts/decodetree.py | 12 | --- a/tcg/optimize.c |
42 | +++ b/scripts/decodetree.py | 13 | +++ b/tcg/optimize.c |
43 | @@ -XXX,XX +XXX,XX @@ | 14 | @@ -XXX,XX +XXX,XX @@ static bool fold_sub_vec(OptContext *ctx, TCGOp *op) |
44 | # See the syntax and semantics in docs/devel/decodetree.rst. | 15 | fold_sub_to_neg(ctx, op)) { |
45 | # | 16 | return true; |
46 | 17 | } | |
47 | +import io | 18 | - return false; |
48 | import os | 19 | + return finish_folding(ctx, op); |
49 | import re | 20 | } |
50 | import sys | 21 | |
51 | @@ -XXX,XX +XXX,XX @@ def main(): | 22 | static bool fold_sub(OptContext *ctx, TCGOp *op) |
52 | 23 | { | |
53 | for filename in args: | 24 | - if (fold_const2(ctx, op) || fold_sub_vec(ctx, op)) { |
54 | input_file = filename | 25 | + if (fold_const2(ctx, op) || |
55 | - f = open(filename, 'r') | 26 | + fold_xx_to_i(ctx, op, 0) || |
56 | + f = open(filename, 'rt', encoding='utf-8') | 27 | + fold_xi_to_x(ctx, op, 0) || |
57 | parse_file(f, toppat) | 28 | + fold_sub_to_neg(ctx, op)) { |
58 | f.close() | 29 | return true; |
59 | 30 | } | |
60 | @@ -XXX,XX +XXX,XX @@ def main(): | 31 | |
61 | prop_size(stree) | 32 | @@ -XXX,XX +XXX,XX @@ static bool fold_sub(OptContext *ctx, TCGOp *op) |
62 | 33 | ? INDEX_op_add_i32 : INDEX_op_add_i64); | |
63 | if output_file: | 34 | op->args[2] = arg_new_constant(ctx, -val); |
64 | - output_fd = open(output_file, 'w') | 35 | } |
65 | + output_fd = open(output_file, 'wt', encoding='utf-8') | 36 | - return false; |
66 | else: | 37 | + return finish_folding(ctx, op); |
67 | - output_fd = sys.stdout | 38 | } |
68 | + output_fd = io.TextIOWrapper(sys.stdout.buffer, | 39 | |
69 | + encoding=sys.stdout.encoding, | 40 | static bool fold_sub2(OptContext *ctx, TCGOp *op) |
70 | + errors="ignore") | ||
71 | |||
72 | output_autogen() | ||
73 | for n in sorted(arguments.keys()): | ||
74 | -- | 41 | -- |
75 | 2.25.1 | 42 | 2.43.0 |
76 | |||
77 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Avoid the use of the OptContext slots. | ||
1 | 2 | ||
3 | Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> | ||
4 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
5 | --- | ||
6 | tcg/optimize.c | 16 +++++++++------- | ||
7 | 1 file changed, 9 insertions(+), 7 deletions(-) | ||
8 | |||
9 | diff --git a/tcg/optimize.c b/tcg/optimize.c | ||
10 | index XXXXXXX..XXXXXXX 100644 | ||
11 | --- a/tcg/optimize.c | ||
12 | +++ b/tcg/optimize.c | ||
13 | @@ -XXX,XX +XXX,XX @@ static bool fold_sub2(OptContext *ctx, TCGOp *op) | ||
14 | |||
15 | static bool fold_tcg_ld(OptContext *ctx, TCGOp *op) | ||
16 | { | ||
17 | + uint64_t z_mask = -1, s_mask = 0; | ||
18 | + | ||
19 | /* We can't do any folding with a load, but we can record bits. */ | ||
20 | switch (op->opc) { | ||
21 | CASE_OP_32_64(ld8s): | ||
22 | - ctx->s_mask = MAKE_64BIT_MASK(8, 56); | ||
23 | + s_mask = INT8_MIN; | ||
24 | break; | ||
25 | CASE_OP_32_64(ld8u): | ||
26 | - ctx->z_mask = MAKE_64BIT_MASK(0, 8); | ||
27 | + z_mask = MAKE_64BIT_MASK(0, 8); | ||
28 | break; | ||
29 | CASE_OP_32_64(ld16s): | ||
30 | - ctx->s_mask = MAKE_64BIT_MASK(16, 48); | ||
31 | + s_mask = INT16_MIN; | ||
32 | break; | ||
33 | CASE_OP_32_64(ld16u): | ||
34 | - ctx->z_mask = MAKE_64BIT_MASK(0, 16); | ||
35 | + z_mask = MAKE_64BIT_MASK(0, 16); | ||
36 | break; | ||
37 | case INDEX_op_ld32s_i64: | ||
38 | - ctx->s_mask = MAKE_64BIT_MASK(32, 32); | ||
39 | + s_mask = INT32_MIN; | ||
40 | break; | ||
41 | case INDEX_op_ld32u_i64: | ||
42 | - ctx->z_mask = MAKE_64BIT_MASK(0, 32); | ||
43 | + z_mask = MAKE_64BIT_MASK(0, 32); | ||
44 | break; | ||
45 | default: | ||
46 | g_assert_not_reached(); | ||
47 | } | ||
48 | - return false; | ||
49 | + return fold_masks_zs(ctx, op, z_mask, s_mask); | ||
50 | } | ||
51 | |||
52 | static bool fold_tcg_ld_memcopy(OptContext *ctx, TCGOp *op) | ||
53 | -- | ||
54 | 2.43.0 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> | ||
2 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
3 | --- | ||
4 | tcg/optimize.c | 2 +- | ||
5 | 1 file changed, 1 insertion(+), 1 deletion(-) | ||
1 | 6 | ||
7 | diff --git a/tcg/optimize.c b/tcg/optimize.c | ||
8 | index XXXXXXX..XXXXXXX 100644 | ||
9 | --- a/tcg/optimize.c | ||
10 | +++ b/tcg/optimize.c | ||
11 | @@ -XXX,XX +XXX,XX @@ static bool fold_tcg_ld_memcopy(OptContext *ctx, TCGOp *op) | ||
12 | TCGType type; | ||
13 | |||
14 | if (op->args[1] != tcgv_ptr_arg(tcg_env)) { | ||
15 | - return false; | ||
16 | + return finish_folding(ctx, op); | ||
17 | } | ||
18 | |||
19 | type = ctx->type; | ||
20 | -- | ||
21 | 2.43.0 | diff view generated by jsdifflib |
1 | These are now completely covered by mov from a | 1 | Avoid the use of the OptContext slots. Find TempOptInfo once. |
---|---|---|---|
2 | TYPE_CONST temporary. | 2 | Remove fold_masks as the function becomes unused. |
3 | 3 | ||
4 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | 4 | Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> |
5 | Reviewed-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com> | ||
6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 5 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
7 | --- | 6 | --- |
8 | include/tcg/tcg-opc.h | 3 --- | 7 | tcg/optimize.c | 18 ++++++++---------- |
9 | tcg/optimize.c | 4 ---- | 8 | 1 file changed, 8 insertions(+), 10 deletions(-) |
10 | tcg/tcg-op-vec.c | 1 - | ||
11 | tcg/tcg.c | 18 +----------------- | ||
12 | tcg/aarch64/tcg-target.c.inc | 3 --- | ||
13 | tcg/arm/tcg-target.c.inc | 1 - | ||
14 | tcg/i386/tcg-target.c.inc | 3 --- | ||
15 | tcg/mips/tcg-target.c.inc | 2 -- | ||
16 | tcg/ppc/tcg-target.c.inc | 3 --- | ||
17 | tcg/riscv/tcg-target.c.inc | 2 -- | ||
18 | tcg/s390/tcg-target.c.inc | 2 -- | ||
19 | tcg/sparc/tcg-target.c.inc | 2 -- | ||
20 | tcg/tci/tcg-target.c.inc | 2 -- | ||
21 | 13 files changed, 1 insertion(+), 45 deletions(-) | ||
22 | 9 | ||
23 | diff --git a/include/tcg/tcg-opc.h b/include/tcg/tcg-opc.h | ||
24 | index XXXXXXX..XXXXXXX 100644 | ||
25 | --- a/include/tcg/tcg-opc.h | ||
26 | +++ b/include/tcg/tcg-opc.h | ||
27 | @@ -XXX,XX +XXX,XX @@ DEF(br, 0, 0, 1, TCG_OPF_BB_END) | ||
28 | DEF(mb, 0, 0, 1, 0) | ||
29 | |||
30 | DEF(mov_i32, 1, 1, 0, TCG_OPF_NOT_PRESENT) | ||
31 | -DEF(movi_i32, 1, 0, 1, TCG_OPF_NOT_PRESENT) | ||
32 | DEF(setcond_i32, 1, 2, 1, 0) | ||
33 | DEF(movcond_i32, 1, 4, 1, IMPL(TCG_TARGET_HAS_movcond_i32)) | ||
34 | /* load/store */ | ||
35 | @@ -XXX,XX +XXX,XX @@ DEF(ctz_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_ctz_i32)) | ||
36 | DEF(ctpop_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_ctpop_i32)) | ||
37 | |||
38 | DEF(mov_i64, 1, 1, 0, TCG_OPF_64BIT | TCG_OPF_NOT_PRESENT) | ||
39 | -DEF(movi_i64, 1, 0, 1, TCG_OPF_64BIT | TCG_OPF_NOT_PRESENT) | ||
40 | DEF(setcond_i64, 1, 2, 1, IMPL64) | ||
41 | DEF(movcond_i64, 1, 4, 1, IMPL64 | IMPL(TCG_TARGET_HAS_movcond_i64)) | ||
42 | /* load/store */ | ||
43 | @@ -XXX,XX +XXX,XX @@ DEF(qemu_st8_i32, 0, TLADDR_ARGS + 1, 1, | ||
44 | #define IMPLVEC TCG_OPF_VECTOR | IMPL(TCG_TARGET_MAYBE_vec) | ||
45 | |||
46 | DEF(mov_vec, 1, 1, 0, TCG_OPF_VECTOR | TCG_OPF_NOT_PRESENT) | ||
47 | -DEF(dupi_vec, 1, 0, 1, TCG_OPF_VECTOR | TCG_OPF_NOT_PRESENT) | ||
48 | |||
49 | DEF(dup_vec, 1, 1, 0, IMPLVEC) | ||
50 | DEF(dup2_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_REG_BITS == 32)) | ||
51 | diff --git a/tcg/optimize.c b/tcg/optimize.c | 10 | diff --git a/tcg/optimize.c b/tcg/optimize.c |
52 | index XXXXXXX..XXXXXXX 100644 | 11 | index XXXXXXX..XXXXXXX 100644 |
53 | --- a/tcg/optimize.c | 12 | --- a/tcg/optimize.c |
54 | +++ b/tcg/optimize.c | 13 | +++ b/tcg/optimize.c |
55 | @@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s) | 14 | @@ -XXX,XX +XXX,XX @@ static bool fold_masks_s(OptContext *ctx, TCGOp *op, uint64_t s_mask) |
56 | CASE_OP_32_64_VEC(mov): | 15 | return fold_masks_zs(ctx, op, -1, s_mask); |
57 | tcg_opt_gen_mov(s, op, op->args[0], op->args[1]); | ||
58 | break; | ||
59 | - CASE_OP_32_64(movi): | ||
60 | - case INDEX_op_dupi_vec: | ||
61 | - tcg_opt_gen_movi(s, &temps_used, op, op->args[0], op->args[1]); | ||
62 | - break; | ||
63 | |||
64 | case INDEX_op_dup_vec: | ||
65 | if (arg_is_const(op->args[1])) { | ||
66 | diff --git a/tcg/tcg-op-vec.c b/tcg/tcg-op-vec.c | ||
67 | index XXXXXXX..XXXXXXX 100644 | ||
68 | --- a/tcg/tcg-op-vec.c | ||
69 | +++ b/tcg/tcg-op-vec.c | ||
70 | @@ -XXX,XX +XXX,XX @@ bool tcg_can_emit_vecop_list(const TCGOpcode *list, | ||
71 | case INDEX_op_xor_vec: | ||
72 | case INDEX_op_mov_vec: | ||
73 | case INDEX_op_dup_vec: | ||
74 | - case INDEX_op_dupi_vec: | ||
75 | case INDEX_op_dup2_vec: | ||
76 | case INDEX_op_ld_vec: | ||
77 | case INDEX_op_st_vec: | ||
78 | diff --git a/tcg/tcg.c b/tcg/tcg.c | ||
79 | index XXXXXXX..XXXXXXX 100644 | ||
80 | --- a/tcg/tcg.c | ||
81 | +++ b/tcg/tcg.c | ||
82 | @@ -XXX,XX +XXX,XX @@ bool tcg_op_supported(TCGOpcode op) | ||
83 | return TCG_TARGET_HAS_goto_ptr; | ||
84 | |||
85 | case INDEX_op_mov_i32: | ||
86 | - case INDEX_op_movi_i32: | ||
87 | case INDEX_op_setcond_i32: | ||
88 | case INDEX_op_brcond_i32: | ||
89 | case INDEX_op_ld8u_i32: | ||
90 | @@ -XXX,XX +XXX,XX @@ bool tcg_op_supported(TCGOpcode op) | ||
91 | return TCG_TARGET_REG_BITS == 32; | ||
92 | |||
93 | case INDEX_op_mov_i64: | ||
94 | - case INDEX_op_movi_i64: | ||
95 | case INDEX_op_setcond_i64: | ||
96 | case INDEX_op_brcond_i64: | ||
97 | case INDEX_op_ld8u_i64: | ||
98 | @@ -XXX,XX +XXX,XX @@ bool tcg_op_supported(TCGOpcode op) | ||
99 | |||
100 | case INDEX_op_mov_vec: | ||
101 | case INDEX_op_dup_vec: | ||
102 | - case INDEX_op_dupi_vec: | ||
103 | case INDEX_op_dupm_vec: | ||
104 | case INDEX_op_ld_vec: | ||
105 | case INDEX_op_st_vec: | ||
106 | @@ -XXX,XX +XXX,XX @@ static void tcg_reg_alloc_cbranch(TCGContext *s, TCGRegSet allocated_regs) | ||
107 | } | 16 | } |
108 | 17 | ||
109 | /* | 18 | -static bool fold_masks(OptContext *ctx, TCGOp *op) |
110 | - * Specialized code generation for INDEX_op_movi_*. | ||
111 | + * Specialized code generation for INDEX_op_mov_* with a constant. | ||
112 | */ | ||
113 | static void tcg_reg_alloc_do_movi(TCGContext *s, TCGTemp *ots, | ||
114 | tcg_target_ulong val, TCGLifeData arg_life, | ||
115 | @@ -XXX,XX +XXX,XX @@ static void tcg_reg_alloc_do_movi(TCGContext *s, TCGTemp *ots, | ||
116 | } | ||
117 | } | ||
118 | |||
119 | -static void tcg_reg_alloc_movi(TCGContext *s, const TCGOp *op) | ||
120 | -{ | 19 | -{ |
121 | - TCGTemp *ots = arg_temp(op->args[0]); | 20 | - return fold_masks_zs(ctx, op, ctx->z_mask, ctx->s_mask); |
122 | - tcg_target_ulong val = op->args[1]; | ||
123 | - | ||
124 | - tcg_reg_alloc_do_movi(s, ots, val, op->life, op->output_pref[0]); | ||
125 | -} | 21 | -} |
126 | - | 22 | - |
127 | /* | 23 | /* |
128 | * Specialized code generation for INDEX_op_mov_*. | 24 | * An "affected" mask bit is 0 if and only if the result is identical |
129 | */ | 25 | * to the first input. Thus if the entire mask is 0, the operation |
130 | @@ -XXX,XX +XXX,XX @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb) | 26 | @@ -XXX,XX +XXX,XX @@ static bool fold_tcg_st_memcopy(OptContext *ctx, TCGOp *op) |
131 | case INDEX_op_mov_vec: | 27 | |
132 | tcg_reg_alloc_mov(s, op); | 28 | static bool fold_xor(OptContext *ctx, TCGOp *op) |
133 | break; | 29 | { |
134 | - case INDEX_op_movi_i32: | 30 | + uint64_t z_mask, s_mask; |
135 | - case INDEX_op_movi_i64: | 31 | + TempOptInfo *t1, *t2; |
136 | - case INDEX_op_dupi_vec: | 32 | + |
137 | - tcg_reg_alloc_movi(s, op); | 33 | if (fold_const2_commutative(ctx, op) || |
138 | - break; | 34 | fold_xx_to_i(ctx, op, 0) || |
139 | case INDEX_op_dup_vec: | 35 | fold_xi_to_x(ctx, op, 0) || |
140 | tcg_reg_alloc_dup(s, op); | 36 | @@ -XXX,XX +XXX,XX @@ static bool fold_xor(OptContext *ctx, TCGOp *op) |
141 | break; | 37 | return true; |
142 | diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc | 38 | } |
143 | index XXXXXXX..XXXXXXX 100644 | 39 | |
144 | --- a/tcg/aarch64/tcg-target.c.inc | 40 | - ctx->z_mask = arg_info(op->args[1])->z_mask |
145 | +++ b/tcg/aarch64/tcg-target.c.inc | 41 | - | arg_info(op->args[2])->z_mask; |
146 | @@ -XXX,XX +XXX,XX @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, | 42 | - ctx->s_mask = arg_info(op->args[1])->s_mask |
147 | 43 | - & arg_info(op->args[2])->s_mask; | |
148 | case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ | 44 | - return fold_masks(ctx, op); |
149 | case INDEX_op_mov_i64: | 45 | + t1 = arg_info(op->args[1]); |
150 | - case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */ | 46 | + t2 = arg_info(op->args[2]); |
151 | - case INDEX_op_movi_i64: | 47 | + z_mask = t1->z_mask | t2->z_mask; |
152 | case INDEX_op_call: /* Always emitted via tcg_out_call. */ | 48 | + s_mask = t1->s_mask & t2->s_mask; |
153 | default: | 49 | + return fold_masks_zs(ctx, op, z_mask, s_mask); |
154 | g_assert_not_reached(); | 50 | } |
155 | @@ -XXX,XX +XXX,XX @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, | 51 | |
156 | break; | 52 | static bool fold_bitsel_vec(OptContext *ctx, TCGOp *op) |
157 | |||
158 | case INDEX_op_mov_vec: /* Always emitted via tcg_out_mov. */ | ||
159 | - case INDEX_op_dupi_vec: /* Always emitted via tcg_out_movi. */ | ||
160 | case INDEX_op_dup_vec: /* Always emitted via tcg_out_dup_vec. */ | ||
161 | default: | ||
162 | g_assert_not_reached(); | ||
163 | diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc | ||
164 | index XXXXXXX..XXXXXXX 100644 | ||
165 | --- a/tcg/arm/tcg-target.c.inc | ||
166 | +++ b/tcg/arm/tcg-target.c.inc | ||
167 | @@ -XXX,XX +XXX,XX @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, | ||
168 | break; | ||
169 | |||
170 | case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ | ||
171 | - case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */ | ||
172 | case INDEX_op_call: /* Always emitted via tcg_out_call. */ | ||
173 | default: | ||
174 | tcg_abort(); | ||
175 | diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc | ||
176 | index XXXXXXX..XXXXXXX 100644 | ||
177 | --- a/tcg/i386/tcg-target.c.inc | ||
178 | +++ b/tcg/i386/tcg-target.c.inc | ||
179 | @@ -XXX,XX +XXX,XX @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, | ||
180 | break; | ||
181 | case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ | ||
182 | case INDEX_op_mov_i64: | ||
183 | - case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */ | ||
184 | - case INDEX_op_movi_i64: | ||
185 | case INDEX_op_call: /* Always emitted via tcg_out_call. */ | ||
186 | default: | ||
187 | tcg_abort(); | ||
188 | @@ -XXX,XX +XXX,XX @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, | ||
189 | break; | ||
190 | |||
191 | case INDEX_op_mov_vec: /* Always emitted via tcg_out_mov. */ | ||
192 | - case INDEX_op_dupi_vec: /* Always emitted via tcg_out_movi. */ | ||
193 | case INDEX_op_dup_vec: /* Always emitted via tcg_out_dup_vec. */ | ||
194 | default: | ||
195 | g_assert_not_reached(); | ||
196 | diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc | ||
197 | index XXXXXXX..XXXXXXX 100644 | ||
198 | --- a/tcg/mips/tcg-target.c.inc | ||
199 | +++ b/tcg/mips/tcg-target.c.inc | ||
200 | @@ -XXX,XX +XXX,XX @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, | ||
201 | break; | ||
202 | case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ | ||
203 | case INDEX_op_mov_i64: | ||
204 | - case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */ | ||
205 | - case INDEX_op_movi_i64: | ||
206 | case INDEX_op_call: /* Always emitted via tcg_out_call. */ | ||
207 | default: | ||
208 | tcg_abort(); | ||
209 | diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc | ||
210 | index XXXXXXX..XXXXXXX 100644 | ||
211 | --- a/tcg/ppc/tcg-target.c.inc | ||
212 | +++ b/tcg/ppc/tcg-target.c.inc | ||
213 | @@ -XXX,XX +XXX,XX @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, | ||
214 | |||
215 | case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ | ||
216 | case INDEX_op_mov_i64: | ||
217 | - case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */ | ||
218 | - case INDEX_op_movi_i64: | ||
219 | case INDEX_op_call: /* Always emitted via tcg_out_call. */ | ||
220 | default: | ||
221 | tcg_abort(); | ||
222 | @@ -XXX,XX +XXX,XX @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, | ||
223 | return; | ||
224 | |||
225 | case INDEX_op_mov_vec: /* Always emitted via tcg_out_mov. */ | ||
226 | - case INDEX_op_dupi_vec: /* Always emitted via tcg_out_movi. */ | ||
227 | case INDEX_op_dup_vec: /* Always emitted via tcg_out_dup_vec. */ | ||
228 | default: | ||
229 | g_assert_not_reached(); | ||
230 | diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc | ||
231 | index XXXXXXX..XXXXXXX 100644 | ||
232 | --- a/tcg/riscv/tcg-target.c.inc | ||
233 | +++ b/tcg/riscv/tcg-target.c.inc | ||
234 | @@ -XXX,XX +XXX,XX @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, | ||
235 | |||
236 | case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ | ||
237 | case INDEX_op_mov_i64: | ||
238 | - case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */ | ||
239 | - case INDEX_op_movi_i64: | ||
240 | case INDEX_op_call: /* Always emitted via tcg_out_call. */ | ||
241 | default: | ||
242 | g_assert_not_reached(); | ||
243 | diff --git a/tcg/s390/tcg-target.c.inc b/tcg/s390/tcg-target.c.inc | ||
244 | index XXXXXXX..XXXXXXX 100644 | ||
245 | --- a/tcg/s390/tcg-target.c.inc | ||
246 | +++ b/tcg/s390/tcg-target.c.inc | ||
247 | @@ -XXX,XX +XXX,XX @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, | ||
248 | |||
249 | case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ | ||
250 | case INDEX_op_mov_i64: | ||
251 | - case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */ | ||
252 | - case INDEX_op_movi_i64: | ||
253 | case INDEX_op_call: /* Always emitted via tcg_out_call. */ | ||
254 | default: | ||
255 | tcg_abort(); | ||
256 | diff --git a/tcg/sparc/tcg-target.c.inc b/tcg/sparc/tcg-target.c.inc | ||
257 | index XXXXXXX..XXXXXXX 100644 | ||
258 | --- a/tcg/sparc/tcg-target.c.inc | ||
259 | +++ b/tcg/sparc/tcg-target.c.inc | ||
260 | @@ -XXX,XX +XXX,XX @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, | ||
261 | |||
262 | case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ | ||
263 | case INDEX_op_mov_i64: | ||
264 | - case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */ | ||
265 | - case INDEX_op_movi_i64: | ||
266 | case INDEX_op_call: /* Always emitted via tcg_out_call. */ | ||
267 | default: | ||
268 | tcg_abort(); | ||
269 | diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc | ||
270 | index XXXXXXX..XXXXXXX 100644 | ||
271 | --- a/tcg/tci/tcg-target.c.inc | ||
272 | +++ b/tcg/tci/tcg-target.c.inc | ||
273 | @@ -XXX,XX +XXX,XX @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, | ||
274 | break; | ||
275 | case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ | ||
276 | case INDEX_op_mov_i64: | ||
277 | - case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */ | ||
278 | - case INDEX_op_movi_i64: | ||
279 | case INDEX_op_call: /* Always emitted via tcg_out_call. */ | ||
280 | default: | ||
281 | tcg_abort(); | ||
282 | -- | 53 | -- |
283 | 2.25.1 | 54 | 2.43.0 |
284 | |||
285 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> | ||
2 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
3 | --- | ||
4 | tcg/optimize.c | 2 +- | ||
5 | 1 file changed, 1 insertion(+), 1 deletion(-) | ||
1 | 6 | ||
7 | diff --git a/tcg/optimize.c b/tcg/optimize.c | ||
8 | index XXXXXXX..XXXXXXX 100644 | ||
9 | --- a/tcg/optimize.c | ||
10 | +++ b/tcg/optimize.c | ||
11 | @@ -XXX,XX +XXX,XX @@ static bool fold_bitsel_vec(OptContext *ctx, TCGOp *op) | ||
12 | return fold_orc(ctx, op); | ||
13 | } | ||
14 | } | ||
15 | - return false; | ||
16 | + return finish_folding(ctx, op); | ||
17 | } | ||
18 | |||
19 | /* Propagate constants and copies, fold constant expressions. */ | ||
20 | -- | ||
21 | 2.43.0 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | All non-default cases now finish folding within each function. | ||
2 | Do the same with the default case and assert it is done after. | ||
1 | 3 | ||
4 | Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> | ||
5 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
6 | --- | ||
7 | tcg/optimize.c | 6 ++---- | ||
8 | 1 file changed, 2 insertions(+), 4 deletions(-) | ||
9 | |||
10 | diff --git a/tcg/optimize.c b/tcg/optimize.c | ||
11 | index XXXXXXX..XXXXXXX 100644 | ||
12 | --- a/tcg/optimize.c | ||
13 | +++ b/tcg/optimize.c | ||
14 | @@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s) | ||
15 | done = true; | ||
16 | break; | ||
17 | default: | ||
18 | + done = finish_folding(&ctx, op); | ||
19 | break; | ||
20 | } | ||
21 | - | ||
22 | - if (!done) { | ||
23 | - finish_folding(&ctx, op); | ||
24 | - } | ||
25 | + tcg_debug_assert(done); | ||
26 | } | ||
27 | } | ||
28 | -- | ||
29 | 2.43.0 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | All mask setting is now done with parameters via fold_masks_*. | ||
1 | 2 | ||
3 | Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> | ||
4 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
5 | --- | ||
6 | tcg/optimize.c | 13 ------------- | ||
7 | 1 file changed, 13 deletions(-) | ||
8 | |||
9 | diff --git a/tcg/optimize.c b/tcg/optimize.c | ||
10 | index XXXXXXX..XXXXXXX 100644 | ||
11 | --- a/tcg/optimize.c | ||
12 | +++ b/tcg/optimize.c | ||
13 | @@ -XXX,XX +XXX,XX @@ typedef struct OptContext { | ||
14 | QSIMPLEQ_HEAD(, MemCopyInfo) mem_free; | ||
15 | |||
16 | /* In flight values from optimization. */ | ||
17 | - uint64_t z_mask; /* mask bit is 0 iff value bit is 0 */ | ||
18 | - uint64_t s_mask; /* mask bit is 1 if value bit matches msb */ | ||
19 | TCGType type; | ||
20 | } OptContext; | ||
21 | |||
22 | @@ -XXX,XX +XXX,XX @@ static bool finish_folding(OptContext *ctx, TCGOp *op) | ||
23 | for (i = 0; i < nb_oargs; i++) { | ||
24 | TCGTemp *ts = arg_temp(op->args[i]); | ||
25 | reset_ts(ctx, ts); | ||
26 | - /* | ||
27 | - * Save the corresponding known-zero/sign bits mask for the | ||
28 | - * first output argument (only one supported so far). | ||
29 | - */ | ||
30 | - if (i == 0) { | ||
31 | - ts_info(ts)->z_mask = ctx->z_mask; | ||
32 | - } | ||
33 | } | ||
34 | return true; | ||
35 | } | ||
36 | @@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s) | ||
37 | ctx.type = TCG_TYPE_I32; | ||
38 | } | ||
39 | |||
40 | - /* Assume all bits affected, no bits known zero, no sign reps. */ | ||
41 | - ctx.z_mask = -1; | ||
42 | - ctx.s_mask = 0; | ||
43 | - | ||
44 | /* | ||
45 | * Process each opcode. | ||
46 | * Sorted alphabetically by opcode as much as possible. | ||
47 | -- | ||
48 | 2.43.0 | diff view generated by jsdifflib |
1 | The temp_fixed, temp_global, temp_local bits are all related. | 1 | All instances of s_mask have been converted to the new |
---|---|---|---|
2 | Combine them into a single enumeration. | 2 | representation. We can now re-enable usage. |
3 | 3 | ||
4 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | 4 | Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> |
5 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 5 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
7 | --- | 6 | --- |
8 | include/tcg/tcg.h | 20 +++++--- | 7 | tcg/optimize.c | 4 ++-- |
9 | tcg/optimize.c | 8 +-- | 8 | 1 file changed, 2 insertions(+), 2 deletions(-) |
10 | tcg/tcg.c | 126 ++++++++++++++++++++++++++++------------------ | ||
11 | 3 files changed, 92 insertions(+), 62 deletions(-) | ||
12 | 9 | ||
13 | diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h | ||
14 | index XXXXXXX..XXXXXXX 100644 | ||
15 | --- a/include/tcg/tcg.h | ||
16 | +++ b/include/tcg/tcg.h | ||
17 | @@ -XXX,XX +XXX,XX @@ typedef enum TCGTempVal { | ||
18 | TEMP_VAL_CONST, | ||
19 | } TCGTempVal; | ||
20 | |||
21 | +typedef enum TCGTempKind { | ||
22 | + /* Temp is dead at the end of all basic blocks. */ | ||
23 | + TEMP_NORMAL, | ||
24 | + /* Temp is saved across basic blocks but dead at the end of TBs. */ | ||
25 | + TEMP_LOCAL, | ||
26 | + /* Temp is saved across both basic blocks and translation blocks. */ | ||
27 | + TEMP_GLOBAL, | ||
28 | + /* Temp is in a fixed register. */ | ||
29 | + TEMP_FIXED, | ||
30 | +} TCGTempKind; | ||
31 | + | ||
32 | typedef struct TCGTemp { | ||
33 | TCGReg reg:8; | ||
34 | TCGTempVal val_type:8; | ||
35 | TCGType base_type:8; | ||
36 | TCGType type:8; | ||
37 | - unsigned int fixed_reg:1; | ||
38 | + TCGTempKind kind:3; | ||
39 | unsigned int indirect_reg:1; | ||
40 | unsigned int indirect_base:1; | ||
41 | unsigned int mem_coherent:1; | ||
42 | unsigned int mem_allocated:1; | ||
43 | - /* If true, the temp is saved across both basic blocks and | ||
44 | - translation blocks. */ | ||
45 | - unsigned int temp_global:1; | ||
46 | - /* If true, the temp is saved across basic blocks but dead | ||
47 | - at the end of translation blocks. If false, the temp is | ||
48 | - dead at the end of basic blocks. */ | ||
49 | - unsigned int temp_local:1; | ||
50 | unsigned int temp_allocated:1; | ||
51 | |||
52 | tcg_target_long val; | ||
53 | diff --git a/tcg/optimize.c b/tcg/optimize.c | 10 | diff --git a/tcg/optimize.c b/tcg/optimize.c |
54 | index XXXXXXX..XXXXXXX 100644 | 11 | index XXXXXXX..XXXXXXX 100644 |
55 | --- a/tcg/optimize.c | 12 | --- a/tcg/optimize.c |
56 | +++ b/tcg/optimize.c | 13 | +++ b/tcg/optimize.c |
57 | @@ -XXX,XX +XXX,XX @@ static TCGTemp *find_better_copy(TCGContext *s, TCGTemp *ts) | 14 | @@ -XXX,XX +XXX,XX @@ static bool fold_exts(OptContext *ctx, TCGOp *op) |
58 | TCGTemp *i; | 15 | g_assert_not_reached(); |
59 | |||
60 | /* If this is already a global, we can't do better. */ | ||
61 | - if (ts->temp_global) { | ||
62 | + if (ts->kind >= TEMP_GLOBAL) { | ||
63 | return ts; | ||
64 | } | 16 | } |
65 | 17 | ||
66 | /* Search for a global first. */ | 18 | - if (0 && !type_change && fold_affected_mask(ctx, op, s_mask & ~s_mask_old)) { |
67 | for (i = ts_info(ts)->next_copy; i != ts; i = ts_info(i)->next_copy) { | 19 | + if (!type_change && fold_affected_mask(ctx, op, s_mask & ~s_mask_old)) { |
68 | - if (i->temp_global) { | 20 | return true; |
69 | + if (i->kind >= TEMP_GLOBAL) { | ||
70 | return i; | ||
71 | } | ||
72 | } | 21 | } |
73 | 22 | ||
74 | /* If it is a temp, search for a temp local. */ | 23 | @@ -XXX,XX +XXX,XX @@ static bool fold_sextract(OptContext *ctx, TCGOp *op) |
75 | - if (!ts->temp_local) { | 24 | s_mask = s_mask_old >> pos; |
76 | + if (ts->kind == TEMP_NORMAL) { | 25 | s_mask |= -1ull << (len - 1); |
77 | for (i = ts_info(ts)->next_copy; i != ts; i = ts_info(i)->next_copy) { | 26 | |
78 | - if (ts->temp_local) { | 27 | - if (0 && pos == 0 && fold_affected_mask(ctx, op, s_mask & ~s_mask_old)) { |
79 | + if (i->kind >= TEMP_LOCAL) { | 28 | + if (pos == 0 && fold_affected_mask(ctx, op, s_mask & ~s_mask_old)) { |
80 | return i; | 29 | return true; |
81 | } | ||
82 | } | ||
83 | diff --git a/tcg/tcg.c b/tcg/tcg.c | ||
84 | index XXXXXXX..XXXXXXX 100644 | ||
85 | --- a/tcg/tcg.c | ||
86 | +++ b/tcg/tcg.c | ||
87 | @@ -XXX,XX +XXX,XX @@ static inline TCGTemp *tcg_global_alloc(TCGContext *s) | ||
88 | tcg_debug_assert(s->nb_globals == s->nb_temps); | ||
89 | s->nb_globals++; | ||
90 | ts = tcg_temp_alloc(s); | ||
91 | - ts->temp_global = 1; | ||
92 | + ts->kind = TEMP_GLOBAL; | ||
93 | |||
94 | return ts; | ||
95 | } | ||
96 | @@ -XXX,XX +XXX,XX @@ static TCGTemp *tcg_global_reg_new_internal(TCGContext *s, TCGType type, | ||
97 | ts = tcg_global_alloc(s); | ||
98 | ts->base_type = type; | ||
99 | ts->type = type; | ||
100 | - ts->fixed_reg = 1; | ||
101 | + ts->kind = TEMP_FIXED; | ||
102 | ts->reg = reg; | ||
103 | ts->name = name; | ||
104 | tcg_regset_set_reg(s->reserved_regs, reg); | ||
105 | @@ -XXX,XX +XXX,XX @@ TCGTemp *tcg_global_mem_new_internal(TCGType type, TCGv_ptr base, | ||
106 | bigendian = 1; | ||
107 | #endif | ||
108 | |||
109 | - if (!base_ts->fixed_reg) { | ||
110 | + if (base_ts->kind != TEMP_FIXED) { | ||
111 | /* We do not support double-indirect registers. */ | ||
112 | tcg_debug_assert(!base_ts->indirect_reg); | ||
113 | base_ts->indirect_base = 1; | ||
114 | @@ -XXX,XX +XXX,XX @@ TCGTemp *tcg_global_mem_new_internal(TCGType type, TCGv_ptr base, | ||
115 | TCGTemp *tcg_temp_new_internal(TCGType type, bool temp_local) | ||
116 | { | ||
117 | TCGContext *s = tcg_ctx; | ||
118 | + TCGTempKind kind = temp_local ? TEMP_LOCAL : TEMP_NORMAL; | ||
119 | TCGTemp *ts; | ||
120 | int idx, k; | ||
121 | |||
122 | @@ -XXX,XX +XXX,XX @@ TCGTemp *tcg_temp_new_internal(TCGType type, bool temp_local) | ||
123 | ts = &s->temps[idx]; | ||
124 | ts->temp_allocated = 1; | ||
125 | tcg_debug_assert(ts->base_type == type); | ||
126 | - tcg_debug_assert(ts->temp_local == temp_local); | ||
127 | + tcg_debug_assert(ts->kind == kind); | ||
128 | } else { | ||
129 | ts = tcg_temp_alloc(s); | ||
130 | if (TCG_TARGET_REG_BITS == 32 && type == TCG_TYPE_I64) { | ||
131 | @@ -XXX,XX +XXX,XX @@ TCGTemp *tcg_temp_new_internal(TCGType type, bool temp_local) | ||
132 | ts->base_type = type; | ||
133 | ts->type = TCG_TYPE_I32; | ||
134 | ts->temp_allocated = 1; | ||
135 | - ts->temp_local = temp_local; | ||
136 | + ts->kind = kind; | ||
137 | |||
138 | tcg_debug_assert(ts2 == ts + 1); | ||
139 | ts2->base_type = TCG_TYPE_I64; | ||
140 | ts2->type = TCG_TYPE_I32; | ||
141 | ts2->temp_allocated = 1; | ||
142 | - ts2->temp_local = temp_local; | ||
143 | + ts2->kind = kind; | ||
144 | } else { | ||
145 | ts->base_type = type; | ||
146 | ts->type = type; | ||
147 | ts->temp_allocated = 1; | ||
148 | - ts->temp_local = temp_local; | ||
149 | + ts->kind = kind; | ||
150 | } | ||
151 | } | 30 | } |
152 | 31 | ||
153 | @@ -XXX,XX +XXX,XX @@ void tcg_temp_free_internal(TCGTemp *ts) | ||
154 | } | ||
155 | #endif | ||
156 | |||
157 | - tcg_debug_assert(ts->temp_global == 0); | ||
158 | + tcg_debug_assert(ts->kind < TEMP_GLOBAL); | ||
159 | tcg_debug_assert(ts->temp_allocated != 0); | ||
160 | ts->temp_allocated = 0; | ||
161 | |||
162 | idx = temp_idx(ts); | ||
163 | - k = ts->base_type + (ts->temp_local ? TCG_TYPE_COUNT : 0); | ||
164 | + k = ts->base_type + (ts->kind == TEMP_NORMAL ? 0 : TCG_TYPE_COUNT); | ||
165 | set_bit(idx, s->free_temps[k].l); | ||
166 | } | ||
167 | |||
168 | @@ -XXX,XX +XXX,XX @@ void tcg_gen_callN(void *func, TCGTemp *ret, int nargs, TCGTemp **args) | ||
169 | static void tcg_reg_alloc_start(TCGContext *s) | ||
170 | { | ||
171 | int i, n; | ||
172 | - TCGTemp *ts; | ||
173 | |||
174 | - for (i = 0, n = s->nb_globals; i < n; i++) { | ||
175 | - ts = &s->temps[i]; | ||
176 | - ts->val_type = (ts->fixed_reg ? TEMP_VAL_REG : TEMP_VAL_MEM); | ||
177 | - } | ||
178 | - for (n = s->nb_temps; i < n; i++) { | ||
179 | - ts = &s->temps[i]; | ||
180 | - ts->val_type = (ts->temp_local ? TEMP_VAL_MEM : TEMP_VAL_DEAD); | ||
181 | - ts->mem_allocated = 0; | ||
182 | - ts->fixed_reg = 0; | ||
183 | + for (i = 0, n = s->nb_temps; i < n; i++) { | ||
184 | + TCGTemp *ts = &s->temps[i]; | ||
185 | + TCGTempVal val = TEMP_VAL_MEM; | ||
186 | + | ||
187 | + switch (ts->kind) { | ||
188 | + case TEMP_FIXED: | ||
189 | + val = TEMP_VAL_REG; | ||
190 | + break; | ||
191 | + case TEMP_GLOBAL: | ||
192 | + break; | ||
193 | + case TEMP_NORMAL: | ||
194 | + val = TEMP_VAL_DEAD; | ||
195 | + /* fall through */ | ||
196 | + case TEMP_LOCAL: | ||
197 | + ts->mem_allocated = 0; | ||
198 | + break; | ||
199 | + default: | ||
200 | + g_assert_not_reached(); | ||
201 | + } | ||
202 | + ts->val_type = val; | ||
203 | } | ||
204 | |||
205 | memset(s->reg_to_temp, 0, sizeof(s->reg_to_temp)); | ||
206 | @@ -XXX,XX +XXX,XX @@ static char *tcg_get_arg_str_ptr(TCGContext *s, char *buf, int buf_size, | ||
207 | { | ||
208 | int idx = temp_idx(ts); | ||
209 | |||
210 | - if (ts->temp_global) { | ||
211 | + switch (ts->kind) { | ||
212 | + case TEMP_FIXED: | ||
213 | + case TEMP_GLOBAL: | ||
214 | pstrcpy(buf, buf_size, ts->name); | ||
215 | - } else if (ts->temp_local) { | ||
216 | + break; | ||
217 | + case TEMP_LOCAL: | ||
218 | snprintf(buf, buf_size, "loc%d", idx - s->nb_globals); | ||
219 | - } else { | ||
220 | + break; | ||
221 | + case TEMP_NORMAL: | ||
222 | snprintf(buf, buf_size, "tmp%d", idx - s->nb_globals); | ||
223 | + break; | ||
224 | } | ||
225 | return buf; | ||
226 | } | ||
227 | @@ -XXX,XX +XXX,XX @@ static void la_bb_end(TCGContext *s, int ng, int nt) | ||
228 | { | ||
229 | int i; | ||
230 | |||
231 | - for (i = 0; i < ng; ++i) { | ||
232 | - s->temps[i].state = TS_DEAD | TS_MEM; | ||
233 | - la_reset_pref(&s->temps[i]); | ||
234 | - } | ||
235 | - for (i = ng; i < nt; ++i) { | ||
236 | - s->temps[i].state = (s->temps[i].temp_local | ||
237 | - ? TS_DEAD | TS_MEM | ||
238 | - : TS_DEAD); | ||
239 | - la_reset_pref(&s->temps[i]); | ||
240 | + for (i = 0; i < nt; ++i) { | ||
241 | + TCGTemp *ts = &s->temps[i]; | ||
242 | + int state; | ||
243 | + | ||
244 | + switch (ts->kind) { | ||
245 | + case TEMP_FIXED: | ||
246 | + case TEMP_GLOBAL: | ||
247 | + case TEMP_LOCAL: | ||
248 | + state = TS_DEAD | TS_MEM; | ||
249 | + break; | ||
250 | + case TEMP_NORMAL: | ||
251 | + state = TS_DEAD; | ||
252 | + break; | ||
253 | + default: | ||
254 | + g_assert_not_reached(); | ||
255 | + } | ||
256 | + ts->state = state; | ||
257 | + la_reset_pref(ts); | ||
258 | } | ||
259 | } | ||
260 | |||
261 | @@ -XXX,XX +XXX,XX @@ static void la_bb_sync(TCGContext *s, int ng, int nt) | ||
262 | la_global_sync(s, ng); | ||
263 | |||
264 | for (int i = ng; i < nt; ++i) { | ||
265 | - if (s->temps[i].temp_local) { | ||
266 | + if (s->temps[i].kind == TEMP_LOCAL) { | ||
267 | int state = s->temps[i].state; | ||
268 | s->temps[i].state = state | TS_MEM; | ||
269 | if (state != TS_DEAD) { | ||
270 | @@ -XXX,XX +XXX,XX @@ static void check_regs(TCGContext *s) | ||
271 | } | ||
272 | for (k = 0; k < s->nb_temps; k++) { | ||
273 | ts = &s->temps[k]; | ||
274 | - if (ts->val_type == TEMP_VAL_REG && !ts->fixed_reg | ||
275 | + if (ts->val_type == TEMP_VAL_REG | ||
276 | + && ts->kind != TEMP_FIXED | ||
277 | && s->reg_to_temp[ts->reg] != ts) { | ||
278 | printf("Inconsistency for temp %s:\n", | ||
279 | tcg_get_arg_str_ptr(s, buf, sizeof(buf), ts)); | ||
280 | @@ -XXX,XX +XXX,XX @@ static void temp_load(TCGContext *, TCGTemp *, TCGRegSet, TCGRegSet, TCGRegSet); | ||
281 | mark it free; otherwise mark it dead. */ | ||
282 | static void temp_free_or_dead(TCGContext *s, TCGTemp *ts, int free_or_dead) | ||
283 | { | ||
284 | - if (ts->fixed_reg) { | ||
285 | + if (ts->kind == TEMP_FIXED) { | ||
286 | return; | ||
287 | } | ||
288 | if (ts->val_type == TEMP_VAL_REG) { | ||
289 | s->reg_to_temp[ts->reg] = NULL; | ||
290 | } | ||
291 | ts->val_type = (free_or_dead < 0 | ||
292 | - || ts->temp_local | ||
293 | - || ts->temp_global | ||
294 | + || ts->kind != TEMP_NORMAL | ||
295 | ? TEMP_VAL_MEM : TEMP_VAL_DEAD); | ||
296 | } | ||
297 | |||
298 | @@ -XXX,XX +XXX,XX @@ static inline void temp_dead(TCGContext *s, TCGTemp *ts) | ||
299 | static void temp_sync(TCGContext *s, TCGTemp *ts, TCGRegSet allocated_regs, | ||
300 | TCGRegSet preferred_regs, int free_or_dead) | ||
301 | { | ||
302 | - if (ts->fixed_reg) { | ||
303 | + if (ts->kind == TEMP_FIXED) { | ||
304 | return; | ||
305 | } | ||
306 | if (!ts->mem_coherent) { | ||
307 | @@ -XXX,XX +XXX,XX @@ static void temp_save(TCGContext *s, TCGTemp *ts, TCGRegSet allocated_regs) | ||
308 | { | ||
309 | /* The liveness analysis already ensures that globals are back | ||
310 | in memory. Keep an tcg_debug_assert for safety. */ | ||
311 | - tcg_debug_assert(ts->val_type == TEMP_VAL_MEM || ts->fixed_reg); | ||
312 | + tcg_debug_assert(ts->val_type == TEMP_VAL_MEM | ||
313 | + || ts->kind == TEMP_FIXED); | ||
314 | } | ||
315 | |||
316 | /* save globals to their canonical location and assume they can be | ||
317 | @@ -XXX,XX +XXX,XX @@ static void sync_globals(TCGContext *s, TCGRegSet allocated_regs) | ||
318 | for (i = 0, n = s->nb_globals; i < n; i++) { | ||
319 | TCGTemp *ts = &s->temps[i]; | ||
320 | tcg_debug_assert(ts->val_type != TEMP_VAL_REG | ||
321 | - || ts->fixed_reg | ||
322 | + || ts->kind == TEMP_FIXED | ||
323 | || ts->mem_coherent); | ||
324 | } | ||
325 | } | ||
326 | @@ -XXX,XX +XXX,XX @@ static void tcg_reg_alloc_bb_end(TCGContext *s, TCGRegSet allocated_regs) | ||
327 | |||
328 | for (i = s->nb_globals; i < s->nb_temps; i++) { | ||
329 | TCGTemp *ts = &s->temps[i]; | ||
330 | - if (ts->temp_local) { | ||
331 | + if (ts->kind == TEMP_LOCAL) { | ||
332 | temp_save(s, ts, allocated_regs); | ||
333 | } else { | ||
334 | /* The liveness analysis already ensures that temps are dead. | ||
335 | @@ -XXX,XX +XXX,XX @@ static void tcg_reg_alloc_cbranch(TCGContext *s, TCGRegSet allocated_regs) | ||
336 | * The liveness analysis already ensures that temps are dead. | ||
337 | * Keep tcg_debug_asserts for safety. | ||
338 | */ | ||
339 | - if (ts->temp_local) { | ||
340 | + if (ts->kind == TEMP_LOCAL) { | ||
341 | tcg_debug_assert(ts->val_type != TEMP_VAL_REG || ts->mem_coherent); | ||
342 | } else { | ||
343 | tcg_debug_assert(ts->val_type == TEMP_VAL_DEAD); | ||
344 | @@ -XXX,XX +XXX,XX @@ static void tcg_reg_alloc_do_movi(TCGContext *s, TCGTemp *ots, | ||
345 | TCGRegSet preferred_regs) | ||
346 | { | ||
347 | /* ENV should not be modified. */ | ||
348 | - tcg_debug_assert(!ots->fixed_reg); | ||
349 | + tcg_debug_assert(ots->kind != TEMP_FIXED); | ||
350 | |||
351 | /* The movi is not explicitly generated here. */ | ||
352 | if (ots->val_type == TEMP_VAL_REG) { | ||
353 | @@ -XXX,XX +XXX,XX @@ static void tcg_reg_alloc_mov(TCGContext *s, const TCGOp *op) | ||
354 | ts = arg_temp(op->args[1]); | ||
355 | |||
356 | /* ENV should not be modified. */ | ||
357 | - tcg_debug_assert(!ots->fixed_reg); | ||
358 | + tcg_debug_assert(ots->kind != TEMP_FIXED); | ||
359 | |||
360 | /* Note that otype != itype for no-op truncation. */ | ||
361 | otype = ots->type; | ||
362 | @@ -XXX,XX +XXX,XX @@ static void tcg_reg_alloc_mov(TCGContext *s, const TCGOp *op) | ||
363 | } | ||
364 | temp_dead(s, ots); | ||
365 | } else { | ||
366 | - if (IS_DEAD_ARG(1) && !ts->fixed_reg) { | ||
367 | + if (IS_DEAD_ARG(1) && ts->kind != TEMP_FIXED) { | ||
368 | /* the mov can be suppressed */ | ||
369 | if (ots->val_type == TEMP_VAL_REG) { | ||
370 | s->reg_to_temp[ots->reg] = NULL; | ||
371 | @@ -XXX,XX +XXX,XX @@ static void tcg_reg_alloc_mov(TCGContext *s, const TCGOp *op) | ||
372 | * Store the source register into the destination slot | ||
373 | * and leave the destination temp as TEMP_VAL_MEM. | ||
374 | */ | ||
375 | - assert(!ots->fixed_reg); | ||
376 | + assert(ots->kind != TEMP_FIXED); | ||
377 | if (!ts->mem_allocated) { | ||
378 | temp_allocate_frame(s, ots); | ||
379 | } | ||
380 | @@ -XXX,XX +XXX,XX @@ static void tcg_reg_alloc_dup(TCGContext *s, const TCGOp *op) | ||
381 | its = arg_temp(op->args[1]); | ||
382 | |||
383 | /* ENV should not be modified. */ | ||
384 | - tcg_debug_assert(!ots->fixed_reg); | ||
385 | + tcg_debug_assert(ots->kind != TEMP_FIXED); | ||
386 | |||
387 | itype = its->type; | ||
388 | vece = TCGOP_VECE(op); | ||
389 | @@ -XXX,XX +XXX,XX @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op) | ||
390 | i_preferred_regs = o_preferred_regs = 0; | ||
391 | if (arg_ct->ialias) { | ||
392 | o_preferred_regs = op->output_pref[arg_ct->alias_index]; | ||
393 | - if (ts->fixed_reg) { | ||
394 | + if (ts->kind == TEMP_FIXED) { | ||
395 | /* if fixed register, we must allocate a new register | ||
396 | if the alias is not the same register */ | ||
397 | if (arg != op->args[arg_ct->alias_index]) { | ||
398 | @@ -XXX,XX +XXX,XX @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op) | ||
399 | ts = arg_temp(arg); | ||
400 | |||
401 | /* ENV should not be modified. */ | ||
402 | - tcg_debug_assert(!ts->fixed_reg); | ||
403 | + tcg_debug_assert(ts->kind != TEMP_FIXED); | ||
404 | |||
405 | if (arg_ct->oalias && !const_args[arg_ct->alias_index]) { | ||
406 | reg = new_args[arg_ct->alias_index]; | ||
407 | @@ -XXX,XX +XXX,XX @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op) | ||
408 | ts = arg_temp(op->args[i]); | ||
409 | |||
410 | /* ENV should not be modified. */ | ||
411 | - tcg_debug_assert(!ts->fixed_reg); | ||
412 | + tcg_debug_assert(ts->kind != TEMP_FIXED); | ||
413 | |||
414 | if (NEED_SYNC_ARG(i)) { | ||
415 | temp_sync(s, ts, o_allocated_regs, 0, IS_DEAD_ARG(i)); | ||
416 | @@ -XXX,XX +XXX,XX @@ static void tcg_reg_alloc_call(TCGContext *s, TCGOp *op) | ||
417 | ts = arg_temp(arg); | ||
418 | |||
419 | /* ENV should not be modified. */ | ||
420 | - tcg_debug_assert(!ts->fixed_reg); | ||
421 | + tcg_debug_assert(ts->kind != TEMP_FIXED); | ||
422 | |||
423 | reg = tcg_target_call_oarg_regs[i]; | ||
424 | tcg_debug_assert(s->reg_to_temp[reg] == NULL); | ||
425 | -- | 32 | -- |
426 | 2.25.1 | 33 | 2.43.0 |
427 | |||
428 | diff view generated by jsdifflib |
1 | Do not allocate a large block for indexing. Instead, allocate | 1 | The big comment just above says functions should be sorted. |
---|---|---|---|
2 | for each temporary as they are seen. | 2 | Add forward declarations as needed. |
3 | 3 | ||
4 | In general, this will use less memory, if we consider that most | 4 | Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> |
5 | TBs do not touch every target register. This also allows us to | ||
6 | allocate TempOptInfo for new temps created during optimization. | ||
7 | |||
8 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | ||
9 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 5 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
10 | --- | 6 | --- |
11 | tcg/optimize.c | 60 ++++++++++++++++++++++++++++---------------------- | 7 | tcg/optimize.c | 114 +++++++++++++++++++++++++------------------------ |
12 | 1 file changed, 34 insertions(+), 26 deletions(-) | 8 | 1 file changed, 59 insertions(+), 55 deletions(-) |
13 | 9 | ||
14 | diff --git a/tcg/optimize.c b/tcg/optimize.c | 10 | diff --git a/tcg/optimize.c b/tcg/optimize.c |
15 | index XXXXXXX..XXXXXXX 100644 | 11 | index XXXXXXX..XXXXXXX 100644 |
16 | --- a/tcg/optimize.c | 12 | --- a/tcg/optimize.c |
17 | +++ b/tcg/optimize.c | 13 | +++ b/tcg/optimize.c |
18 | @@ -XXX,XX +XXX,XX @@ static void reset_temp(TCGArg arg) | 14 | @@ -XXX,XX +XXX,XX @@ static bool fold_xx_to_x(OptContext *ctx, TCGOp *op) |
15 | * 3) those that produce information about the result value. | ||
16 | */ | ||
17 | |||
18 | +static bool fold_or(OptContext *ctx, TCGOp *op); | ||
19 | +static bool fold_orc(OptContext *ctx, TCGOp *op); | ||
20 | +static bool fold_xor(OptContext *ctx, TCGOp *op); | ||
21 | + | ||
22 | static bool fold_add(OptContext *ctx, TCGOp *op) | ||
23 | { | ||
24 | if (fold_const2_commutative(ctx, op) || | ||
25 | @@ -XXX,XX +XXX,XX @@ static bool fold_andc(OptContext *ctx, TCGOp *op) | ||
26 | return fold_masks_zs(ctx, op, z_mask, s_mask); | ||
19 | } | 27 | } |
20 | 28 | ||
21 | /* Initialize and activate a temporary. */ | 29 | +static bool fold_bitsel_vec(OptContext *ctx, TCGOp *op) |
22 | -static void init_ts_info(TempOptInfo *infos, | 30 | +{ |
23 | - TCGTempSet *temps_used, TCGTemp *ts) | 31 | + /* If true and false values are the same, eliminate the cmp. */ |
24 | +static void init_ts_info(TCGTempSet *temps_used, TCGTemp *ts) | 32 | + if (args_are_copies(op->args[2], op->args[3])) { |
25 | { | 33 | + return tcg_opt_gen_mov(ctx, op, op->args[0], op->args[2]); |
26 | size_t idx = temp_idx(ts); | ||
27 | - if (!test_bit(idx, temps_used->l)) { | ||
28 | - TempOptInfo *ti = &infos[idx]; | ||
29 | + TempOptInfo *ti; | ||
30 | |||
31 | + if (test_bit(idx, temps_used->l)) { | ||
32 | + return; | ||
33 | + } | ||
34 | + set_bit(idx, temps_used->l); | ||
35 | + | ||
36 | + ti = ts->state_ptr; | ||
37 | + if (ti == NULL) { | ||
38 | + ti = tcg_malloc(sizeof(TempOptInfo)); | ||
39 | ts->state_ptr = ti; | ||
40 | - ti->next_copy = ts; | ||
41 | - ti->prev_copy = ts; | ||
42 | - if (ts->kind == TEMP_CONST) { | ||
43 | - ti->is_const = true; | ||
44 | - ti->val = ti->mask = ts->val; | ||
45 | - if (TCG_TARGET_REG_BITS > 32 && ts->type == TCG_TYPE_I32) { | ||
46 | - /* High bits of a 32-bit quantity are garbage. */ | ||
47 | - ti->mask |= ~0xffffffffull; | ||
48 | - } | ||
49 | - } else { | ||
50 | - ti->is_const = false; | ||
51 | - ti->mask = -1; | ||
52 | + } | 34 | + } |
53 | + | 35 | + |
54 | + ti->next_copy = ts; | 36 | + if (arg_is_const(op->args[2]) && arg_is_const(op->args[3])) { |
55 | + ti->prev_copy = ts; | 37 | + uint64_t tv = arg_info(op->args[2])->val; |
56 | + if (ts->kind == TEMP_CONST) { | 38 | + uint64_t fv = arg_info(op->args[3])->val; |
57 | + ti->is_const = true; | 39 | + |
58 | + ti->val = ts->val; | 40 | + if (tv == -1 && fv == 0) { |
59 | + ti->mask = ts->val; | 41 | + return tcg_opt_gen_mov(ctx, op, op->args[0], op->args[1]); |
60 | + if (TCG_TARGET_REG_BITS > 32 && ts->type == TCG_TYPE_I32) { | 42 | + } |
61 | + /* High bits of a 32-bit quantity are garbage. */ | 43 | + if (tv == 0 && fv == -1) { |
62 | + ti->mask |= ~0xffffffffull; | 44 | + if (TCG_TARGET_HAS_not_vec) { |
63 | } | 45 | + op->opc = INDEX_op_not_vec; |
64 | - set_bit(idx, temps_used->l); | 46 | + return fold_not(ctx, op); |
65 | + } else { | 47 | + } else { |
66 | + ti->is_const = false; | 48 | + op->opc = INDEX_op_xor_vec; |
67 | + ti->mask = -1; | 49 | + op->args[2] = arg_new_constant(ctx, -1); |
68 | } | 50 | + return fold_xor(ctx, op); |
51 | + } | ||
52 | + } | ||
53 | + } | ||
54 | + if (arg_is_const(op->args[2])) { | ||
55 | + uint64_t tv = arg_info(op->args[2])->val; | ||
56 | + if (tv == -1) { | ||
57 | + op->opc = INDEX_op_or_vec; | ||
58 | + op->args[2] = op->args[3]; | ||
59 | + return fold_or(ctx, op); | ||
60 | + } | ||
61 | + if (tv == 0 && TCG_TARGET_HAS_andc_vec) { | ||
62 | + op->opc = INDEX_op_andc_vec; | ||
63 | + op->args[2] = op->args[1]; | ||
64 | + op->args[1] = op->args[3]; | ||
65 | + return fold_andc(ctx, op); | ||
66 | + } | ||
67 | + } | ||
68 | + if (arg_is_const(op->args[3])) { | ||
69 | + uint64_t fv = arg_info(op->args[3])->val; | ||
70 | + if (fv == 0) { | ||
71 | + op->opc = INDEX_op_and_vec; | ||
72 | + return fold_and(ctx, op); | ||
73 | + } | ||
74 | + if (fv == -1 && TCG_TARGET_HAS_orc_vec) { | ||
75 | + op->opc = INDEX_op_orc_vec; | ||
76 | + op->args[2] = op->args[1]; | ||
77 | + op->args[1] = op->args[3]; | ||
78 | + return fold_orc(ctx, op); | ||
79 | + } | ||
80 | + } | ||
81 | + return finish_folding(ctx, op); | ||
82 | +} | ||
83 | + | ||
84 | static bool fold_brcond(OptContext *ctx, TCGOp *op) | ||
85 | { | ||
86 | int i = do_constant_folding_cond1(ctx, op, NO_DEST, &op->args[0], | ||
87 | @@ -XXX,XX +XXX,XX @@ static bool fold_xor(OptContext *ctx, TCGOp *op) | ||
88 | return fold_masks_zs(ctx, op, z_mask, s_mask); | ||
69 | } | 89 | } |
70 | 90 | ||
71 | -static void init_arg_info(TempOptInfo *infos, | 91 | -static bool fold_bitsel_vec(OptContext *ctx, TCGOp *op) |
72 | - TCGTempSet *temps_used, TCGArg arg) | 92 | -{ |
73 | +static void init_arg_info(TCGTempSet *temps_used, TCGArg arg) | 93 | - /* If true and false values are the same, eliminate the cmp. */ |
74 | { | 94 | - if (args_are_copies(op->args[2], op->args[3])) { |
75 | - init_ts_info(infos, temps_used, arg_temp(arg)); | 95 | - return tcg_opt_gen_mov(ctx, op, op->args[0], op->args[2]); |
76 | + init_ts_info(temps_used, arg_temp(arg)); | 96 | - } |
77 | } | 97 | - |
78 | 98 | - if (arg_is_const(op->args[2]) && arg_is_const(op->args[3])) { | |
79 | static TCGTemp *find_better_copy(TCGContext *s, TCGTemp *ts) | 99 | - uint64_t tv = arg_info(op->args[2])->val; |
80 | @@ -XXX,XX +XXX,XX @@ static bool swap_commutative2(TCGArg *p1, TCGArg *p2) | 100 | - uint64_t fv = arg_info(op->args[3])->val; |
101 | - | ||
102 | - if (tv == -1 && fv == 0) { | ||
103 | - return tcg_opt_gen_mov(ctx, op, op->args[0], op->args[1]); | ||
104 | - } | ||
105 | - if (tv == 0 && fv == -1) { | ||
106 | - if (TCG_TARGET_HAS_not_vec) { | ||
107 | - op->opc = INDEX_op_not_vec; | ||
108 | - return fold_not(ctx, op); | ||
109 | - } else { | ||
110 | - op->opc = INDEX_op_xor_vec; | ||
111 | - op->args[2] = arg_new_constant(ctx, -1); | ||
112 | - return fold_xor(ctx, op); | ||
113 | - } | ||
114 | - } | ||
115 | - } | ||
116 | - if (arg_is_const(op->args[2])) { | ||
117 | - uint64_t tv = arg_info(op->args[2])->val; | ||
118 | - if (tv == -1) { | ||
119 | - op->opc = INDEX_op_or_vec; | ||
120 | - op->args[2] = op->args[3]; | ||
121 | - return fold_or(ctx, op); | ||
122 | - } | ||
123 | - if (tv == 0 && TCG_TARGET_HAS_andc_vec) { | ||
124 | - op->opc = INDEX_op_andc_vec; | ||
125 | - op->args[2] = op->args[1]; | ||
126 | - op->args[1] = op->args[3]; | ||
127 | - return fold_andc(ctx, op); | ||
128 | - } | ||
129 | - } | ||
130 | - if (arg_is_const(op->args[3])) { | ||
131 | - uint64_t fv = arg_info(op->args[3])->val; | ||
132 | - if (fv == 0) { | ||
133 | - op->opc = INDEX_op_and_vec; | ||
134 | - return fold_and(ctx, op); | ||
135 | - } | ||
136 | - if (fv == -1 && TCG_TARGET_HAS_orc_vec) { | ||
137 | - op->opc = INDEX_op_orc_vec; | ||
138 | - op->args[2] = op->args[1]; | ||
139 | - op->args[1] = op->args[3]; | ||
140 | - return fold_orc(ctx, op); | ||
141 | - } | ||
142 | - } | ||
143 | - return finish_folding(ctx, op); | ||
144 | -} | ||
145 | - | ||
81 | /* Propagate constants and copies, fold constant expressions. */ | 146 | /* Propagate constants and copies, fold constant expressions. */ |
82 | void tcg_optimize(TCGContext *s) | 147 | void tcg_optimize(TCGContext *s) |
83 | { | 148 | { |
84 | - int nb_temps, nb_globals; | ||
85 | + int nb_temps, nb_globals, i; | ||
86 | TCGOp *op, *op_next, *prev_mb = NULL; | ||
87 | - TempOptInfo *infos; | ||
88 | TCGTempSet temps_used; | ||
89 | |||
90 | /* Array VALS has an element for each temp. | ||
91 | @@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s) | ||
92 | |||
93 | nb_temps = s->nb_temps; | ||
94 | nb_globals = s->nb_globals; | ||
95 | + | ||
96 | bitmap_zero(temps_used.l, nb_temps); | ||
97 | - infos = tcg_malloc(sizeof(TempOptInfo) * nb_temps); | ||
98 | + for (i = 0; i < nb_temps; ++i) { | ||
99 | + s->temps[i].state_ptr = NULL; | ||
100 | + } | ||
101 | |||
102 | QTAILQ_FOREACH_SAFE(op, &s->ops, link, op_next) { | ||
103 | uint64_t mask, partmask, affected, tmp; | ||
104 | - int nb_oargs, nb_iargs, i; | ||
105 | + int nb_oargs, nb_iargs; | ||
106 | TCGOpcode opc = op->opc; | ||
107 | const TCGOpDef *def = &tcg_op_defs[opc]; | ||
108 | |||
109 | @@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s) | ||
110 | for (i = 0; i < nb_oargs + nb_iargs; i++) { | ||
111 | TCGTemp *ts = arg_temp(op->args[i]); | ||
112 | if (ts) { | ||
113 | - init_ts_info(infos, &temps_used, ts); | ||
114 | + init_ts_info(&temps_used, ts); | ||
115 | } | ||
116 | } | ||
117 | } else { | ||
118 | nb_oargs = def->nb_oargs; | ||
119 | nb_iargs = def->nb_iargs; | ||
120 | for (i = 0; i < nb_oargs + nb_iargs; i++) { | ||
121 | - init_arg_info(infos, &temps_used, op->args[i]); | ||
122 | + init_arg_info(&temps_used, op->args[i]); | ||
123 | } | ||
124 | } | ||
125 | |||
126 | -- | 149 | -- |
127 | 2.25.1 | 150 | 2.43.0 |
128 | |||
129 | diff view generated by jsdifflib |
1 | There are several ways we can expand a vector dup of a 64-bit | 1 | The big comment just above says functions should be sorted. |
---|---|---|---|
2 | element on a 32-bit host. | ||
3 | 2 | ||
3 | Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> | ||
4 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 4 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
5 | --- | 5 | --- |
6 | tcg/tcg.c | 97 +++++++++++++++++++++++++++++++++++++++++++++++++++++++ | 6 | tcg/optimize.c | 60 +++++++++++++++++++++++++------------------------- |
7 | 1 file changed, 97 insertions(+) | 7 | 1 file changed, 30 insertions(+), 30 deletions(-) |
8 | 8 | ||
9 | diff --git a/tcg/tcg.c b/tcg/tcg.c | 9 | diff --git a/tcg/optimize.c b/tcg/optimize.c |
10 | index XXXXXXX..XXXXXXX 100644 | 10 | index XXXXXXX..XXXXXXX 100644 |
11 | --- a/tcg/tcg.c | 11 | --- a/tcg/optimize.c |
12 | +++ b/tcg/tcg.c | 12 | +++ b/tcg/optimize.c |
13 | @@ -XXX,XX +XXX,XX @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op) | 13 | @@ -XXX,XX +XXX,XX @@ static bool fold_call(OptContext *ctx, TCGOp *op) |
14 | } | 14 | return true; |
15 | } | 15 | } |
16 | 16 | ||
17 | +static bool tcg_reg_alloc_dup2(TCGContext *s, const TCGOp *op) | 17 | +static bool fold_cmp_vec(OptContext *ctx, TCGOp *op) |
18 | +{ | 18 | +{ |
19 | + const TCGLifeData arg_life = op->life; | 19 | + /* Canonicalize the comparison to put immediate second. */ |
20 | + TCGTemp *ots, *itsl, *itsh; | 20 | + if (swap_commutative(NO_DEST, &op->args[1], &op->args[2])) { |
21 | + TCGType vtype = TCGOP_VECL(op) + TCG_TYPE_V64; | 21 | + op->args[3] = tcg_swap_cond(op->args[3]); |
22 | + } | ||
23 | + return finish_folding(ctx, op); | ||
24 | +} | ||
22 | + | 25 | + |
23 | + /* This opcode is only valid for 32-bit hosts, for 64-bit elements. */ | 26 | +static bool fold_cmpsel_vec(OptContext *ctx, TCGOp *op) |
24 | + tcg_debug_assert(TCG_TARGET_REG_BITS == 32); | 27 | +{ |
25 | + tcg_debug_assert(TCGOP_VECE(op) == MO_64); | 28 | + /* If true and false values are the same, eliminate the cmp. */ |
26 | + | 29 | + if (args_are_copies(op->args[3], op->args[4])) { |
27 | + ots = arg_temp(op->args[0]); | 30 | + return tcg_opt_gen_mov(ctx, op, op->args[0], op->args[3]); |
28 | + itsl = arg_temp(op->args[1]); | ||
29 | + itsh = arg_temp(op->args[2]); | ||
30 | + | ||
31 | + /* ENV should not be modified. */ | ||
32 | + tcg_debug_assert(!temp_readonly(ots)); | ||
33 | + | ||
34 | + /* Allocate the output register now. */ | ||
35 | + if (ots->val_type != TEMP_VAL_REG) { | ||
36 | + TCGRegSet allocated_regs = s->reserved_regs; | ||
37 | + TCGRegSet dup_out_regs = | ||
38 | + tcg_op_defs[INDEX_op_dup_vec].args_ct[0].regs; | ||
39 | + | ||
40 | + /* Make sure to not spill the input registers. */ | ||
41 | + if (!IS_DEAD_ARG(1) && itsl->val_type == TEMP_VAL_REG) { | ||
42 | + tcg_regset_set_reg(allocated_regs, itsl->reg); | ||
43 | + } | ||
44 | + if (!IS_DEAD_ARG(2) && itsh->val_type == TEMP_VAL_REG) { | ||
45 | + tcg_regset_set_reg(allocated_regs, itsh->reg); | ||
46 | + } | ||
47 | + | ||
48 | + ots->reg = tcg_reg_alloc(s, dup_out_regs, allocated_regs, | ||
49 | + op->output_pref[0], ots->indirect_base); | ||
50 | + ots->val_type = TEMP_VAL_REG; | ||
51 | + ots->mem_coherent = 0; | ||
52 | + s->reg_to_temp[ots->reg] = ots; | ||
53 | + } | 31 | + } |
54 | + | 32 | + |
55 | + /* Promote dup2 of immediates to dupi_vec. */ | 33 | + /* Canonicalize the comparison to put immediate second. */ |
56 | + if (itsl->val_type == TEMP_VAL_CONST && itsh->val_type == TEMP_VAL_CONST) { | 34 | + if (swap_commutative(NO_DEST, &op->args[1], &op->args[2])) { |
57 | + uint64_t val = deposit64(itsl->val, 32, 32, itsh->val); | 35 | + op->args[5] = tcg_swap_cond(op->args[5]); |
58 | + MemOp vece = MO_64; | ||
59 | + | ||
60 | + if (val == dup_const(MO_8, val)) { | ||
61 | + vece = MO_8; | ||
62 | + } else if (val == dup_const(MO_16, val)) { | ||
63 | + vece = MO_16; | ||
64 | + } else if (val == dup_const(MO_32, val)) { | ||
65 | + vece = MO_32; | ||
66 | + } | ||
67 | + | ||
68 | + tcg_out_dupi_vec(s, vtype, vece, ots->reg, val); | ||
69 | + goto done; | ||
70 | + } | 36 | + } |
71 | + | 37 | + /* |
72 | + /* If the two inputs form one 64-bit value, try dupm_vec. */ | 38 | + * Canonicalize the "false" input reg to match the destination, |
73 | + if (itsl + 1 == itsh && itsl->base_type == TCG_TYPE_I64) { | 39 | + * so that the tcg backend can implement "move if true". |
74 | + if (!itsl->mem_coherent) { | 40 | + */ |
75 | + temp_sync(s, itsl, s->reserved_regs, 0, 0); | 41 | + if (swap_commutative(op->args[0], &op->args[4], &op->args[3])) { |
76 | + } | 42 | + op->args[5] = tcg_invert_cond(op->args[5]); |
77 | + if (!itsh->mem_coherent) { | ||
78 | + temp_sync(s, itsh, s->reserved_regs, 0, 0); | ||
79 | + } | ||
80 | +#ifdef HOST_WORDS_BIGENDIAN | ||
81 | + TCGTemp *its = itsh; | ||
82 | +#else | ||
83 | + TCGTemp *its = itsl; | ||
84 | +#endif | ||
85 | + if (tcg_out_dupm_vec(s, vtype, MO_64, ots->reg, | ||
86 | + its->mem_base->reg, its->mem_offset)) { | ||
87 | + goto done; | ||
88 | + } | ||
89 | + } | 43 | + } |
90 | + | 44 | + return finish_folding(ctx, op); |
91 | + /* Fall back to generic expansion. */ | ||
92 | + return false; | ||
93 | + | ||
94 | + done: | ||
95 | + if (IS_DEAD_ARG(1)) { | ||
96 | + temp_dead(s, itsl); | ||
97 | + } | ||
98 | + if (IS_DEAD_ARG(2)) { | ||
99 | + temp_dead(s, itsh); | ||
100 | + } | ||
101 | + if (NEED_SYNC_ARG(0)) { | ||
102 | + temp_sync(s, ots, s->reserved_regs, 0, IS_DEAD_ARG(0)); | ||
103 | + } else if (IS_DEAD_ARG(0)) { | ||
104 | + temp_dead(s, ots); | ||
105 | + } | ||
106 | + return true; | ||
107 | +} | 45 | +} |
108 | + | 46 | + |
109 | #ifdef TCG_TARGET_STACK_GROWSUP | 47 | static bool fold_count_zeros(OptContext *ctx, TCGOp *op) |
110 | #define STACK_DIR(x) (-(x)) | 48 | { |
111 | #else | 49 | uint64_t z_mask, s_mask; |
112 | @@ -XXX,XX +XXX,XX @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb) | 50 | @@ -XXX,XX +XXX,XX @@ static bool fold_setcond2(OptContext *ctx, TCGOp *op) |
113 | case INDEX_op_call: | 51 | return tcg_opt_gen_movi(ctx, op, op->args[0], i); |
114 | tcg_reg_alloc_call(s, op); | 52 | } |
115 | break; | 53 | |
116 | + case INDEX_op_dup2_vec: | 54 | -static bool fold_cmp_vec(OptContext *ctx, TCGOp *op) |
117 | + if (tcg_reg_alloc_dup2(s, op)) { | 55 | -{ |
118 | + break; | 56 | - /* Canonicalize the comparison to put immediate second. */ |
119 | + } | 57 | - if (swap_commutative(NO_DEST, &op->args[1], &op->args[2])) { |
120 | + /* fall through */ | 58 | - op->args[3] = tcg_swap_cond(op->args[3]); |
121 | default: | 59 | - } |
122 | /* Sanity check that we've not introduced any unhandled opcodes. */ | 60 | - return finish_folding(ctx, op); |
123 | tcg_debug_assert(tcg_op_supported(opc)); | 61 | -} |
62 | - | ||
63 | -static bool fold_cmpsel_vec(OptContext *ctx, TCGOp *op) | ||
64 | -{ | ||
65 | - /* If true and false values are the same, eliminate the cmp. */ | ||
66 | - if (args_are_copies(op->args[3], op->args[4])) { | ||
67 | - return tcg_opt_gen_mov(ctx, op, op->args[0], op->args[3]); | ||
68 | - } | ||
69 | - | ||
70 | - /* Canonicalize the comparison to put immediate second. */ | ||
71 | - if (swap_commutative(NO_DEST, &op->args[1], &op->args[2])) { | ||
72 | - op->args[5] = tcg_swap_cond(op->args[5]); | ||
73 | - } | ||
74 | - /* | ||
75 | - * Canonicalize the "false" input reg to match the destination, | ||
76 | - * so that the tcg backend can implement "move if true". | ||
77 | - */ | ||
78 | - if (swap_commutative(op->args[0], &op->args[4], &op->args[3])) { | ||
79 | - op->args[5] = tcg_invert_cond(op->args[5]); | ||
80 | - } | ||
81 | - return finish_folding(ctx, op); | ||
82 | -} | ||
83 | - | ||
84 | static bool fold_sextract(OptContext *ctx, TCGOp *op) | ||
85 | { | ||
86 | uint64_t z_mask, s_mask, s_mask_old; | ||
124 | -- | 87 | -- |
125 | 2.25.1 | 88 | 2.43.0 |
126 | |||
127 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | 1 | We currently have a flag, float_muladd_halve_result, to scale | |
2 | the result by 2**-1. Extend this to handle arbitrary scaling. | ||
3 | |||
4 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
5 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
6 | --- | ||
7 | include/fpu/softfloat.h | 6 ++++ | ||
8 | fpu/softfloat.c | 58 ++++++++++++++++++++++----------------- | ||
9 | fpu/softfloat-parts.c.inc | 7 +++-- | ||
10 | 3 files changed, 44 insertions(+), 27 deletions(-) | ||
11 | |||
12 | diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h | ||
13 | index XXXXXXX..XXXXXXX 100644 | ||
14 | --- a/include/fpu/softfloat.h | ||
15 | +++ b/include/fpu/softfloat.h | ||
16 | @@ -XXX,XX +XXX,XX @@ float16 float16_add(float16, float16, float_status *status); | ||
17 | float16 float16_sub(float16, float16, float_status *status); | ||
18 | float16 float16_mul(float16, float16, float_status *status); | ||
19 | float16 float16_muladd(float16, float16, float16, int, float_status *status); | ||
20 | +float16 float16_muladd_scalbn(float16, float16, float16, | ||
21 | + int, int, float_status *status); | ||
22 | float16 float16_div(float16, float16, float_status *status); | ||
23 | float16 float16_scalbn(float16, int, float_status *status); | ||
24 | float16 float16_min(float16, float16, float_status *status); | ||
25 | @@ -XXX,XX +XXX,XX @@ float32 float32_mul(float32, float32, float_status *status); | ||
26 | float32 float32_div(float32, float32, float_status *status); | ||
27 | float32 float32_rem(float32, float32, float_status *status); | ||
28 | float32 float32_muladd(float32, float32, float32, int, float_status *status); | ||
29 | +float32 float32_muladd_scalbn(float32, float32, float32, | ||
30 | + int, int, float_status *status); | ||
31 | float32 float32_sqrt(float32, float_status *status); | ||
32 | float32 float32_exp2(float32, float_status *status); | ||
33 | float32 float32_log2(float32, float_status *status); | ||
34 | @@ -XXX,XX +XXX,XX @@ float64 float64_mul(float64, float64, float_status *status); | ||
35 | float64 float64_div(float64, float64, float_status *status); | ||
36 | float64 float64_rem(float64, float64, float_status *status); | ||
37 | float64 float64_muladd(float64, float64, float64, int, float_status *status); | ||
38 | +float64 float64_muladd_scalbn(float64, float64, float64, | ||
39 | + int, int, float_status *status); | ||
40 | float64 float64_sqrt(float64, float_status *status); | ||
41 | float64 float64_log2(float64, float_status *status); | ||
42 | FloatRelation float64_compare(float64, float64, float_status *status); | ||
43 | diff --git a/fpu/softfloat.c b/fpu/softfloat.c | ||
44 | index XXXXXXX..XXXXXXX 100644 | ||
45 | --- a/fpu/softfloat.c | ||
46 | +++ b/fpu/softfloat.c | ||
47 | @@ -XXX,XX +XXX,XX @@ static FloatParts128 *parts128_mul(FloatParts128 *a, FloatParts128 *b, | ||
48 | #define parts_mul(A, B, S) \ | ||
49 | PARTS_GENERIC_64_128(mul, A)(A, B, S) | ||
50 | |||
51 | -static FloatParts64 *parts64_muladd(FloatParts64 *a, FloatParts64 *b, | ||
52 | - FloatParts64 *c, int flags, | ||
53 | - float_status *s); | ||
54 | -static FloatParts128 *parts128_muladd(FloatParts128 *a, FloatParts128 *b, | ||
55 | - FloatParts128 *c, int flags, | ||
56 | - float_status *s); | ||
57 | +static FloatParts64 *parts64_muladd_scalbn(FloatParts64 *a, FloatParts64 *b, | ||
58 | + FloatParts64 *c, int scale, | ||
59 | + int flags, float_status *s); | ||
60 | +static FloatParts128 *parts128_muladd_scalbn(FloatParts128 *a, FloatParts128 *b, | ||
61 | + FloatParts128 *c, int scale, | ||
62 | + int flags, float_status *s); | ||
63 | |||
64 | -#define parts_muladd(A, B, C, Z, S) \ | ||
65 | - PARTS_GENERIC_64_128(muladd, A)(A, B, C, Z, S) | ||
66 | +#define parts_muladd_scalbn(A, B, C, Z, Y, S) \ | ||
67 | + PARTS_GENERIC_64_128(muladd_scalbn, A)(A, B, C, Z, Y, S) | ||
68 | |||
69 | static FloatParts64 *parts64_div(FloatParts64 *a, FloatParts64 *b, | ||
70 | float_status *s); | ||
71 | @@ -XXX,XX +XXX,XX @@ floatx80_mul(floatx80 a, floatx80 b, float_status *status) | ||
72 | * Fused multiply-add | ||
73 | */ | ||
74 | |||
75 | -float16 QEMU_FLATTEN float16_muladd(float16 a, float16 b, float16 c, | ||
76 | - int flags, float_status *status) | ||
77 | +float16 QEMU_FLATTEN | ||
78 | +float16_muladd_scalbn(float16 a, float16 b, float16 c, | ||
79 | + int scale, int flags, float_status *status) | ||
80 | { | ||
81 | FloatParts64 pa, pb, pc, *pr; | ||
82 | |||
83 | float16_unpack_canonical(&pa, a, status); | ||
84 | float16_unpack_canonical(&pb, b, status); | ||
85 | float16_unpack_canonical(&pc, c, status); | ||
86 | - pr = parts_muladd(&pa, &pb, &pc, flags, status); | ||
87 | + pr = parts_muladd_scalbn(&pa, &pb, &pc, scale, flags, status); | ||
88 | |||
89 | return float16_round_pack_canonical(pr, status); | ||
90 | } | ||
91 | |||
92 | -static float32 QEMU_SOFTFLOAT_ATTR | ||
93 | -soft_f32_muladd(float32 a, float32 b, float32 c, int flags, | ||
94 | - float_status *status) | ||
95 | +float16 float16_muladd(float16 a, float16 b, float16 c, | ||
96 | + int flags, float_status *status) | ||
97 | +{ | ||
98 | + return float16_muladd_scalbn(a, b, c, 0, flags, status); | ||
99 | +} | ||
100 | + | ||
101 | +float32 QEMU_SOFTFLOAT_ATTR | ||
102 | +float32_muladd_scalbn(float32 a, float32 b, float32 c, | ||
103 | + int scale, int flags, float_status *status) | ||
104 | { | ||
105 | FloatParts64 pa, pb, pc, *pr; | ||
106 | |||
107 | float32_unpack_canonical(&pa, a, status); | ||
108 | float32_unpack_canonical(&pb, b, status); | ||
109 | float32_unpack_canonical(&pc, c, status); | ||
110 | - pr = parts_muladd(&pa, &pb, &pc, flags, status); | ||
111 | + pr = parts_muladd_scalbn(&pa, &pb, &pc, scale, flags, status); | ||
112 | |||
113 | return float32_round_pack_canonical(pr, status); | ||
114 | } | ||
115 | |||
116 | -static float64 QEMU_SOFTFLOAT_ATTR | ||
117 | -soft_f64_muladd(float64 a, float64 b, float64 c, int flags, | ||
118 | - float_status *status) | ||
119 | +float64 QEMU_SOFTFLOAT_ATTR | ||
120 | +float64_muladd_scalbn(float64 a, float64 b, float64 c, | ||
121 | + int scale, int flags, float_status *status) | ||
122 | { | ||
123 | FloatParts64 pa, pb, pc, *pr; | ||
124 | |||
125 | float64_unpack_canonical(&pa, a, status); | ||
126 | float64_unpack_canonical(&pb, b, status); | ||
127 | float64_unpack_canonical(&pc, c, status); | ||
128 | - pr = parts_muladd(&pa, &pb, &pc, flags, status); | ||
129 | + pr = parts_muladd_scalbn(&pa, &pb, &pc, scale, flags, status); | ||
130 | |||
131 | return float64_round_pack_canonical(pr, status); | ||
132 | } | ||
133 | @@ -XXX,XX +XXX,XX @@ float32_muladd(float32 xa, float32 xb, float32 xc, int flags, float_status *s) | ||
134 | return ur.s; | ||
135 | |||
136 | soft: | ||
137 | - return soft_f32_muladd(ua.s, ub.s, uc.s, flags, s); | ||
138 | + return float32_muladd_scalbn(ua.s, ub.s, uc.s, 0, flags, s); | ||
139 | } | ||
140 | |||
141 | float64 QEMU_FLATTEN | ||
142 | @@ -XXX,XX +XXX,XX @@ float64_muladd(float64 xa, float64 xb, float64 xc, int flags, float_status *s) | ||
143 | return ur.s; | ||
144 | |||
145 | soft: | ||
146 | - return soft_f64_muladd(ua.s, ub.s, uc.s, flags, s); | ||
147 | + return float64_muladd_scalbn(ua.s, ub.s, uc.s, 0, flags, s); | ||
148 | } | ||
149 | |||
150 | float64 float64r32_muladd(float64 a, float64 b, float64 c, | ||
151 | @@ -XXX,XX +XXX,XX @@ float64 float64r32_muladd(float64 a, float64 b, float64 c, | ||
152 | float64_unpack_canonical(&pa, a, status); | ||
153 | float64_unpack_canonical(&pb, b, status); | ||
154 | float64_unpack_canonical(&pc, c, status); | ||
155 | - pr = parts_muladd(&pa, &pb, &pc, flags, status); | ||
156 | + pr = parts_muladd_scalbn(&pa, &pb, &pc, 0, flags, status); | ||
157 | |||
158 | return float64r32_round_pack_canonical(pr, status); | ||
159 | } | ||
160 | @@ -XXX,XX +XXX,XX @@ bfloat16 QEMU_FLATTEN bfloat16_muladd(bfloat16 a, bfloat16 b, bfloat16 c, | ||
161 | bfloat16_unpack_canonical(&pa, a, status); | ||
162 | bfloat16_unpack_canonical(&pb, b, status); | ||
163 | bfloat16_unpack_canonical(&pc, c, status); | ||
164 | - pr = parts_muladd(&pa, &pb, &pc, flags, status); | ||
165 | + pr = parts_muladd_scalbn(&pa, &pb, &pc, 0, flags, status); | ||
166 | |||
167 | return bfloat16_round_pack_canonical(pr, status); | ||
168 | } | ||
169 | @@ -XXX,XX +XXX,XX @@ float128 QEMU_FLATTEN float128_muladd(float128 a, float128 b, float128 c, | ||
170 | float128_unpack_canonical(&pa, a, status); | ||
171 | float128_unpack_canonical(&pb, b, status); | ||
172 | float128_unpack_canonical(&pc, c, status); | ||
173 | - pr = parts_muladd(&pa, &pb, &pc, flags, status); | ||
174 | + pr = parts_muladd_scalbn(&pa, &pb, &pc, 0, flags, status); | ||
175 | |||
176 | return float128_round_pack_canonical(pr, status); | ||
177 | } | ||
178 | @@ -XXX,XX +XXX,XX @@ float32 float32_exp2(float32 a, float_status *status) | ||
179 | |||
180 | float64_unpack_canonical(&rp, float64_one, status); | ||
181 | for (i = 0 ; i < 15 ; i++) { | ||
182 | + | ||
183 | float64_unpack_canonical(&tp, float32_exp2_coefficients[i], status); | ||
184 | - rp = *parts_muladd(&tp, &xnp, &rp, 0, status); | ||
185 | + rp = *parts_muladd_scalbn(&tp, &xnp, &rp, 0, 0, status); | ||
186 | xnp = *parts_mul(&xnp, &xp, status); | ||
187 | } | ||
188 | |||
189 | diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc | ||
190 | index XXXXXXX..XXXXXXX 100644 | ||
191 | --- a/fpu/softfloat-parts.c.inc | ||
192 | +++ b/fpu/softfloat-parts.c.inc | ||
193 | @@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(mul)(FloatPartsN *a, FloatPartsN *b, | ||
194 | * Requires A and C extracted into a double-sized structure to provide the | ||
195 | * extra space for the widening multiply. | ||
196 | */ | ||
197 | -static FloatPartsN *partsN(muladd)(FloatPartsN *a, FloatPartsN *b, | ||
198 | - FloatPartsN *c, int flags, float_status *s) | ||
199 | +static FloatPartsN *partsN(muladd_scalbn)(FloatPartsN *a, FloatPartsN *b, | ||
200 | + FloatPartsN *c, int scale, | ||
201 | + int flags, float_status *s) | ||
202 | { | ||
203 | int ab_mask, abc_mask; | ||
204 | FloatPartsW p_widen, c_widen; | ||
205 | @@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(muladd)(FloatPartsN *a, FloatPartsN *b, | ||
206 | a->exp = p_widen.exp; | ||
207 | |||
208 | return_normal: | ||
209 | + /* TODO: Replace all use of float_muladd_halve_result with scale. */ | ||
210 | if (flags & float_muladd_halve_result) { | ||
211 | a->exp -= 1; | ||
212 | } | ||
213 | + a->exp += scale; | ||
214 | finish_sign: | ||
215 | if (flags & float_muladd_negate_result) { | ||
216 | a->sign ^= 1; | ||
217 | -- | ||
218 | 2.43.0 | ||
219 | |||
220 | diff view generated by jsdifflib |
1 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | 1 | Use the scalbn interface instead of float_muladd_halve_result. |
---|---|---|---|
2 | |||
3 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
2 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 4 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
3 | --- | 5 | --- |
4 | accel/tcg/plugin-gen.c | 49 +++++++++++++++++++----------------------- | 6 | target/arm/tcg/helper-a64.c | 6 +++--- |
5 | 1 file changed, 22 insertions(+), 27 deletions(-) | 7 | 1 file changed, 3 insertions(+), 3 deletions(-) |
6 | 8 | ||
7 | diff --git a/accel/tcg/plugin-gen.c b/accel/tcg/plugin-gen.c | 9 | diff --git a/target/arm/tcg/helper-a64.c b/target/arm/tcg/helper-a64.c |
8 | index XXXXXXX..XXXXXXX 100644 | 10 | index XXXXXXX..XXXXXXX 100644 |
9 | --- a/accel/tcg/plugin-gen.c | 11 | --- a/target/arm/tcg/helper-a64.c |
10 | +++ b/accel/tcg/plugin-gen.c | 12 | +++ b/target/arm/tcg/helper-a64.c |
11 | @@ -XXX,XX +XXX,XX @@ static TCGOp *copy_extu_i32_i64(TCGOp **begin_op, TCGOp *op) | 13 | @@ -XXX,XX +XXX,XX @@ uint32_t HELPER(rsqrtsf_f16)(uint32_t a, uint32_t b, float_status *fpst) |
12 | if (TCG_TARGET_REG_BITS == 32) { | 14 | (float16_is_infinity(b) && float16_is_zero(a))) { |
13 | /* mov_i32 */ | 15 | return float16_one_point_five; |
14 | op = copy_op(begin_op, op, INDEX_op_mov_i32); | 16 | } |
15 | - /* movi_i32 */ | 17 | - return float16_muladd(a, b, float16_three, float_muladd_halve_result, fpst); |
16 | - op = copy_op(begin_op, op, INDEX_op_movi_i32); | 18 | + return float16_muladd_scalbn(a, b, float16_three, -1, 0, fpst); |
17 | + /* mov_i32 w/ $0 */ | ||
18 | + op = copy_op(begin_op, op, INDEX_op_mov_i32); | ||
19 | } else { | ||
20 | /* extu_i32_i64 */ | ||
21 | op = copy_op(begin_op, op, INDEX_op_extu_i32_i64); | ||
22 | @@ -XXX,XX +XXX,XX @@ static TCGOp *copy_mov_i64(TCGOp **begin_op, TCGOp *op) | ||
23 | return op; | ||
24 | } | 19 | } |
25 | 20 | ||
26 | -static TCGOp *copy_movi_i64(TCGOp **begin_op, TCGOp *op, uint64_t v) | 21 | float32 HELPER(rsqrtsf_f32)(float32 a, float32 b, float_status *fpst) |
27 | -{ | 22 | @@ -XXX,XX +XXX,XX @@ float32 HELPER(rsqrtsf_f32)(float32 a, float32 b, float_status *fpst) |
28 | - if (TCG_TARGET_REG_BITS == 32) { | 23 | (float32_is_infinity(b) && float32_is_zero(a))) { |
29 | - /* 2x movi_i32 */ | 24 | return float32_one_point_five; |
30 | - op = copy_op(begin_op, op, INDEX_op_movi_i32); | ||
31 | - op->args[1] = v; | ||
32 | - | ||
33 | - op = copy_op(begin_op, op, INDEX_op_movi_i32); | ||
34 | - op->args[1] = v >> 32; | ||
35 | - } else { | ||
36 | - /* movi_i64 */ | ||
37 | - op = copy_op(begin_op, op, INDEX_op_movi_i64); | ||
38 | - op->args[1] = v; | ||
39 | - } | ||
40 | - return op; | ||
41 | -} | ||
42 | - | ||
43 | static TCGOp *copy_const_ptr(TCGOp **begin_op, TCGOp *op, void *ptr) | ||
44 | { | ||
45 | if (UINTPTR_MAX == UINT32_MAX) { | ||
46 | - /* movi_i32 */ | ||
47 | - op = copy_op(begin_op, op, INDEX_op_movi_i32); | ||
48 | - op->args[1] = (uintptr_t)ptr; | ||
49 | + /* mov_i32 */ | ||
50 | + op = copy_op(begin_op, op, INDEX_op_mov_i32); | ||
51 | + op->args[1] = tcgv_i32_arg(tcg_constant_i32((uintptr_t)ptr)); | ||
52 | } else { | ||
53 | - /* movi_i64 */ | ||
54 | - op = copy_movi_i64(begin_op, op, (uint64_t)(uintptr_t)ptr); | ||
55 | + /* mov_i64 */ | ||
56 | + op = copy_op(begin_op, op, INDEX_op_mov_i64); | ||
57 | + op->args[1] = tcgv_i64_arg(tcg_constant_i64((uintptr_t)ptr)); | ||
58 | } | 25 | } |
59 | return op; | 26 | - return float32_muladd(a, b, float32_three, float_muladd_halve_result, fpst); |
27 | + return float32_muladd_scalbn(a, b, float32_three, -1, 0, fpst); | ||
60 | } | 28 | } |
61 | 29 | ||
62 | static TCGOp *copy_const_i64(TCGOp **begin_op, TCGOp *op, uint64_t v) | 30 | float64 HELPER(rsqrtsf_f64)(float64 a, float64 b, float_status *fpst) |
63 | { | 31 | @@ -XXX,XX +XXX,XX @@ float64 HELPER(rsqrtsf_f64)(float64 a, float64 b, float_status *fpst) |
64 | - return copy_movi_i64(begin_op, op, v); | 32 | (float64_is_infinity(b) && float64_is_zero(a))) { |
65 | + if (TCG_TARGET_REG_BITS == 32) { | 33 | return float64_one_point_five; |
66 | + /* 2x mov_i32 */ | 34 | } |
67 | + op = copy_op(begin_op, op, INDEX_op_mov_i32); | 35 | - return float64_muladd(a, b, float64_three, float_muladd_halve_result, fpst); |
68 | + op->args[1] = tcgv_i32_arg(tcg_constant_i32(v)); | 36 | + return float64_muladd_scalbn(a, b, float64_three, -1, 0, fpst); |
69 | + op = copy_op(begin_op, op, INDEX_op_mov_i32); | ||
70 | + op->args[1] = tcgv_i32_arg(tcg_constant_i32(v >> 32)); | ||
71 | + } else { | ||
72 | + /* mov_i64 */ | ||
73 | + op = copy_op(begin_op, op, INDEX_op_mov_i64); | ||
74 | + op->args[1] = tcgv_i64_arg(tcg_constant_i64(v)); | ||
75 | + } | ||
76 | + return op; | ||
77 | } | 37 | } |
78 | 38 | ||
79 | static TCGOp *copy_extu_tl_i64(TCGOp **begin_op, TCGOp *op) | 39 | /* Floating-point reciprocal exponent - see FPRecpX in ARM ARM */ |
80 | @@ -XXX,XX +XXX,XX @@ static TCGOp *append_mem_cb(const struct qemu_plugin_dyn_cb *cb, | ||
81 | |||
82 | tcg_debug_assert(type == PLUGIN_GEN_CB_MEM); | ||
83 | |||
84 | - /* const_i32 == movi_i32 ("info", so it remains as is) */ | ||
85 | - op = copy_op(&begin_op, op, INDEX_op_movi_i32); | ||
86 | + /* const_i32 == mov_i32 ("info", so it remains as is) */ | ||
87 | + op = copy_op(&begin_op, op, INDEX_op_mov_i32); | ||
88 | |||
89 | /* const_ptr */ | ||
90 | op = copy_const_ptr(&begin_op, op, cb->userp); | ||
91 | -- | 40 | -- |
92 | 2.25.1 | 41 | 2.43.0 |
93 | 42 | ||
94 | 43 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | 1 | Use the scalbn interface instead of float_muladd_halve_result. | |
2 | |||
3 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
4 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
5 | --- | ||
6 | target/sparc/helper.h | 4 +- | ||
7 | target/sparc/fop_helper.c | 8 ++-- | ||
8 | target/sparc/translate.c | 80 +++++++++++++++++++++++---------------- | ||
9 | 3 files changed, 54 insertions(+), 38 deletions(-) | ||
10 | |||
11 | diff --git a/target/sparc/helper.h b/target/sparc/helper.h | ||
12 | index XXXXXXX..XXXXXXX 100644 | ||
13 | --- a/target/sparc/helper.h | ||
14 | +++ b/target/sparc/helper.h | ||
15 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(faddd, TCG_CALL_NO_WG, f64, env, f64, f64) | ||
16 | DEF_HELPER_FLAGS_3(fsubd, TCG_CALL_NO_WG, f64, env, f64, f64) | ||
17 | DEF_HELPER_FLAGS_3(fmuld, TCG_CALL_NO_WG, f64, env, f64, f64) | ||
18 | DEF_HELPER_FLAGS_3(fdivd, TCG_CALL_NO_WG, f64, env, f64, f64) | ||
19 | -DEF_HELPER_FLAGS_5(fmaddd, TCG_CALL_NO_WG, f64, env, f64, f64, f64, i32) | ||
20 | +DEF_HELPER_FLAGS_6(fmaddd, TCG_CALL_NO_WG, f64, env, f64, f64, f64, s32, i32) | ||
21 | DEF_HELPER_FLAGS_3(fnaddd, TCG_CALL_NO_WG, f64, env, f64, f64) | ||
22 | DEF_HELPER_FLAGS_3(fnmuld, TCG_CALL_NO_WG, f64, env, f64, f64) | ||
23 | |||
24 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(fadds, TCG_CALL_NO_WG, f32, env, f32, f32) | ||
25 | DEF_HELPER_FLAGS_3(fsubs, TCG_CALL_NO_WG, f32, env, f32, f32) | ||
26 | DEF_HELPER_FLAGS_3(fmuls, TCG_CALL_NO_WG, f32, env, f32, f32) | ||
27 | DEF_HELPER_FLAGS_3(fdivs, TCG_CALL_NO_WG, f32, env, f32, f32) | ||
28 | -DEF_HELPER_FLAGS_5(fmadds, TCG_CALL_NO_WG, f32, env, f32, f32, f32, i32) | ||
29 | +DEF_HELPER_FLAGS_6(fmadds, TCG_CALL_NO_WG, f32, env, f32, f32, f32, s32, i32) | ||
30 | DEF_HELPER_FLAGS_3(fnadds, TCG_CALL_NO_WG, f32, env, f32, f32) | ||
31 | DEF_HELPER_FLAGS_3(fnmuls, TCG_CALL_NO_WG, f32, env, f32, f32) | ||
32 | |||
33 | diff --git a/target/sparc/fop_helper.c b/target/sparc/fop_helper.c | ||
34 | index XXXXXXX..XXXXXXX 100644 | ||
35 | --- a/target/sparc/fop_helper.c | ||
36 | +++ b/target/sparc/fop_helper.c | ||
37 | @@ -XXX,XX +XXX,XX @@ Int128 helper_fsqrtq(CPUSPARCState *env, Int128 src) | ||
38 | } | ||
39 | |||
40 | float32 helper_fmadds(CPUSPARCState *env, float32 s1, | ||
41 | - float32 s2, float32 s3, uint32_t op) | ||
42 | + float32 s2, float32 s3, int32_t sc, uint32_t op) | ||
43 | { | ||
44 | - float32 ret = float32_muladd(s1, s2, s3, op, &env->fp_status); | ||
45 | + float32 ret = float32_muladd_scalbn(s1, s2, s3, sc, op, &env->fp_status); | ||
46 | check_ieee_exceptions(env, GETPC()); | ||
47 | return ret; | ||
48 | } | ||
49 | |||
50 | float64 helper_fmaddd(CPUSPARCState *env, float64 s1, | ||
51 | - float64 s2, float64 s3, uint32_t op) | ||
52 | + float64 s2, float64 s3, int32_t sc, uint32_t op) | ||
53 | { | ||
54 | - float64 ret = float64_muladd(s1, s2, s3, op, &env->fp_status); | ||
55 | + float64 ret = float64_muladd_scalbn(s1, s2, s3, sc, op, &env->fp_status); | ||
56 | check_ieee_exceptions(env, GETPC()); | ||
57 | return ret; | ||
58 | } | ||
59 | diff --git a/target/sparc/translate.c b/target/sparc/translate.c | ||
60 | index XXXXXXX..XXXXXXX 100644 | ||
61 | --- a/target/sparc/translate.c | ||
62 | +++ b/target/sparc/translate.c | ||
63 | @@ -XXX,XX +XXX,XX @@ static void gen_op_fabsq(TCGv_i128 dst, TCGv_i128 src) | ||
64 | |||
65 | static void gen_op_fmadds(TCGv_i32 d, TCGv_i32 s1, TCGv_i32 s2, TCGv_i32 s3) | ||
66 | { | ||
67 | - gen_helper_fmadds(d, tcg_env, s1, s2, s3, tcg_constant_i32(0)); | ||
68 | + TCGv_i32 z = tcg_constant_i32(0); | ||
69 | + gen_helper_fmadds(d, tcg_env, s1, s2, s3, z, z); | ||
70 | } | ||
71 | |||
72 | static void gen_op_fmaddd(TCGv_i64 d, TCGv_i64 s1, TCGv_i64 s2, TCGv_i64 s3) | ||
73 | { | ||
74 | - gen_helper_fmaddd(d, tcg_env, s1, s2, s3, tcg_constant_i32(0)); | ||
75 | + TCGv_i32 z = tcg_constant_i32(0); | ||
76 | + gen_helper_fmaddd(d, tcg_env, s1, s2, s3, z, z); | ||
77 | } | ||
78 | |||
79 | static void gen_op_fmsubs(TCGv_i32 d, TCGv_i32 s1, TCGv_i32 s2, TCGv_i32 s3) | ||
80 | { | ||
81 | - int op = float_muladd_negate_c; | ||
82 | - gen_helper_fmadds(d, tcg_env, s1, s2, s3, tcg_constant_i32(op)); | ||
83 | + TCGv_i32 z = tcg_constant_i32(0); | ||
84 | + TCGv_i32 op = tcg_constant_i32(float_muladd_negate_c); | ||
85 | + gen_helper_fmadds(d, tcg_env, s1, s2, s3, z, op); | ||
86 | } | ||
87 | |||
88 | static void gen_op_fmsubd(TCGv_i64 d, TCGv_i64 s1, TCGv_i64 s2, TCGv_i64 s3) | ||
89 | { | ||
90 | - int op = float_muladd_negate_c; | ||
91 | - gen_helper_fmaddd(d, tcg_env, s1, s2, s3, tcg_constant_i32(op)); | ||
92 | + TCGv_i32 z = tcg_constant_i32(0); | ||
93 | + TCGv_i32 op = tcg_constant_i32(float_muladd_negate_c); | ||
94 | + gen_helper_fmaddd(d, tcg_env, s1, s2, s3, z, op); | ||
95 | } | ||
96 | |||
97 | static void gen_op_fnmsubs(TCGv_i32 d, TCGv_i32 s1, TCGv_i32 s2, TCGv_i32 s3) | ||
98 | { | ||
99 | - int op = float_muladd_negate_c | float_muladd_negate_result; | ||
100 | - gen_helper_fmadds(d, tcg_env, s1, s2, s3, tcg_constant_i32(op)); | ||
101 | + TCGv_i32 z = tcg_constant_i32(0); | ||
102 | + TCGv_i32 op = tcg_constant_i32(float_muladd_negate_c | | ||
103 | + float_muladd_negate_result); | ||
104 | + gen_helper_fmadds(d, tcg_env, s1, s2, s3, z, op); | ||
105 | } | ||
106 | |||
107 | static void gen_op_fnmsubd(TCGv_i64 d, TCGv_i64 s1, TCGv_i64 s2, TCGv_i64 s3) | ||
108 | { | ||
109 | - int op = float_muladd_negate_c | float_muladd_negate_result; | ||
110 | - gen_helper_fmaddd(d, tcg_env, s1, s2, s3, tcg_constant_i32(op)); | ||
111 | + TCGv_i32 z = tcg_constant_i32(0); | ||
112 | + TCGv_i32 op = tcg_constant_i32(float_muladd_negate_c | | ||
113 | + float_muladd_negate_result); | ||
114 | + gen_helper_fmaddd(d, tcg_env, s1, s2, s3, z, op); | ||
115 | } | ||
116 | |||
117 | static void gen_op_fnmadds(TCGv_i32 d, TCGv_i32 s1, TCGv_i32 s2, TCGv_i32 s3) | ||
118 | { | ||
119 | - int op = float_muladd_negate_result; | ||
120 | - gen_helper_fmadds(d, tcg_env, s1, s2, s3, tcg_constant_i32(op)); | ||
121 | + TCGv_i32 z = tcg_constant_i32(0); | ||
122 | + TCGv_i32 op = tcg_constant_i32(float_muladd_negate_result); | ||
123 | + gen_helper_fmadds(d, tcg_env, s1, s2, s3, z, op); | ||
124 | } | ||
125 | |||
126 | static void gen_op_fnmaddd(TCGv_i64 d, TCGv_i64 s1, TCGv_i64 s2, TCGv_i64 s3) | ||
127 | { | ||
128 | - int op = float_muladd_negate_result; | ||
129 | - gen_helper_fmaddd(d, tcg_env, s1, s2, s3, tcg_constant_i32(op)); | ||
130 | + TCGv_i32 z = tcg_constant_i32(0); | ||
131 | + TCGv_i32 op = tcg_constant_i32(float_muladd_negate_result); | ||
132 | + gen_helper_fmaddd(d, tcg_env, s1, s2, s3, z, op); | ||
133 | } | ||
134 | |||
135 | /* Use muladd to compute (1 * src1) + src2 / 2 with one rounding. */ | ||
136 | static void gen_op_fhadds(TCGv_i32 d, TCGv_i32 s1, TCGv_i32 s2) | ||
137 | { | ||
138 | - TCGv_i32 one = tcg_constant_i32(float32_one); | ||
139 | - int op = float_muladd_halve_result; | ||
140 | - gen_helper_fmadds(d, tcg_env, one, s1, s2, tcg_constant_i32(op)); | ||
141 | + TCGv_i32 fone = tcg_constant_i32(float32_one); | ||
142 | + TCGv_i32 mone = tcg_constant_i32(-1); | ||
143 | + TCGv_i32 op = tcg_constant_i32(0); | ||
144 | + gen_helper_fmadds(d, tcg_env, fone, s1, s2, mone, op); | ||
145 | } | ||
146 | |||
147 | static void gen_op_fhaddd(TCGv_i64 d, TCGv_i64 s1, TCGv_i64 s2) | ||
148 | { | ||
149 | - TCGv_i64 one = tcg_constant_i64(float64_one); | ||
150 | - int op = float_muladd_halve_result; | ||
151 | - gen_helper_fmaddd(d, tcg_env, one, s1, s2, tcg_constant_i32(op)); | ||
152 | + TCGv_i64 fone = tcg_constant_i64(float64_one); | ||
153 | + TCGv_i32 mone = tcg_constant_i32(-1); | ||
154 | + TCGv_i32 op = tcg_constant_i32(0); | ||
155 | + gen_helper_fmaddd(d, tcg_env, fone, s1, s2, mone, op); | ||
156 | } | ||
157 | |||
158 | /* Use muladd to compute (1 * src1) - src2 / 2 with one rounding. */ | ||
159 | static void gen_op_fhsubs(TCGv_i32 d, TCGv_i32 s1, TCGv_i32 s2) | ||
160 | { | ||
161 | - TCGv_i32 one = tcg_constant_i32(float32_one); | ||
162 | - int op = float_muladd_negate_c | float_muladd_halve_result; | ||
163 | - gen_helper_fmadds(d, tcg_env, one, s1, s2, tcg_constant_i32(op)); | ||
164 | + TCGv_i32 fone = tcg_constant_i32(float32_one); | ||
165 | + TCGv_i32 mone = tcg_constant_i32(-1); | ||
166 | + TCGv_i32 op = tcg_constant_i32(float_muladd_negate_c); | ||
167 | + gen_helper_fmadds(d, tcg_env, fone, s1, s2, mone, op); | ||
168 | } | ||
169 | |||
170 | static void gen_op_fhsubd(TCGv_i64 d, TCGv_i64 s1, TCGv_i64 s2) | ||
171 | { | ||
172 | - TCGv_i64 one = tcg_constant_i64(float64_one); | ||
173 | - int op = float_muladd_negate_c | float_muladd_halve_result; | ||
174 | - gen_helper_fmaddd(d, tcg_env, one, s1, s2, tcg_constant_i32(op)); | ||
175 | + TCGv_i64 fone = tcg_constant_i64(float64_one); | ||
176 | + TCGv_i32 mone = tcg_constant_i32(-1); | ||
177 | + TCGv_i32 op = tcg_constant_i32(float_muladd_negate_c); | ||
178 | + gen_helper_fmaddd(d, tcg_env, fone, s1, s2, mone, op); | ||
179 | } | ||
180 | |||
181 | /* Use muladd to compute -((1 * src1) + src2 / 2) with one rounding. */ | ||
182 | static void gen_op_fnhadds(TCGv_i32 d, TCGv_i32 s1, TCGv_i32 s2) | ||
183 | { | ||
184 | - TCGv_i32 one = tcg_constant_i32(float32_one); | ||
185 | - int op = float_muladd_negate_result | float_muladd_halve_result; | ||
186 | - gen_helper_fmadds(d, tcg_env, one, s1, s2, tcg_constant_i32(op)); | ||
187 | + TCGv_i32 fone = tcg_constant_i32(float32_one); | ||
188 | + TCGv_i32 mone = tcg_constant_i32(-1); | ||
189 | + TCGv_i32 op = tcg_constant_i32(float_muladd_negate_result); | ||
190 | + gen_helper_fmadds(d, tcg_env, fone, s1, s2, mone, op); | ||
191 | } | ||
192 | |||
193 | static void gen_op_fnhaddd(TCGv_i64 d, TCGv_i64 s1, TCGv_i64 s2) | ||
194 | { | ||
195 | - TCGv_i64 one = tcg_constant_i64(float64_one); | ||
196 | - int op = float_muladd_negate_result | float_muladd_halve_result; | ||
197 | - gen_helper_fmaddd(d, tcg_env, one, s1, s2, tcg_constant_i32(op)); | ||
198 | + TCGv_i64 fone = tcg_constant_i64(float64_one); | ||
199 | + TCGv_i32 mone = tcg_constant_i32(-1); | ||
200 | + TCGv_i32 op = tcg_constant_i32(float_muladd_negate_result); | ||
201 | + gen_helper_fmaddd(d, tcg_env, fone, s1, s2, mone, op); | ||
202 | } | ||
203 | |||
204 | static void gen_op_fpexception_im(DisasContext *dc, int ftt) | ||
205 | -- | ||
206 | 2.43.0 | ||
207 | |||
208 | diff view generated by jsdifflib |
1 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | 1 | All uses have been convered to float*_muladd_scalbn. |
---|---|---|---|
2 | |||
3 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
2 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 4 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
3 | --- | 5 | --- |
4 | tcg/i386/tcg-target.c.inc | 26 +++++++++++++------------- | 6 | include/fpu/softfloat.h | 3 --- |
5 | 1 file changed, 13 insertions(+), 13 deletions(-) | 7 | fpu/softfloat.c | 6 ------ |
8 | fpu/softfloat-parts.c.inc | 4 ---- | ||
9 | 3 files changed, 13 deletions(-) | ||
6 | 10 | ||
7 | diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc | 11 | diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h |
8 | index XXXXXXX..XXXXXXX 100644 | 12 | index XXXXXXX..XXXXXXX 100644 |
9 | --- a/tcg/i386/tcg-target.c.inc | 13 | --- a/include/fpu/softfloat.h |
10 | +++ b/tcg/i386/tcg-target.c.inc | 14 | +++ b/include/fpu/softfloat.h |
11 | @@ -XXX,XX +XXX,XX @@ static void expand_vec_rotv(TCGType type, unsigned vece, TCGv_vec v0, | 15 | @@ -XXX,XX +XXX,XX @@ bfloat16 bfloat16_squash_input_denormal(bfloat16 a, float_status *status); |
12 | static void expand_vec_mul(TCGType type, unsigned vece, | 16 | | Using these differs from negating an input or output before calling |
13 | TCGv_vec v0, TCGv_vec v1, TCGv_vec v2) | 17 | | the muladd function in that this means that a NaN doesn't have its |
14 | { | 18 | | sign bit inverted before it is propagated. |
15 | - TCGv_vec t1, t2, t3, t4; | 19 | -| We also support halving the result before rounding, as a special |
16 | + TCGv_vec t1, t2, t3, t4, zero; | 20 | -| case to support the ARM fused-sqrt-step instruction FRSQRTS. |
17 | 21 | *----------------------------------------------------------------------------*/ | |
18 | tcg_debug_assert(vece == MO_8); | 22 | enum { |
19 | 23 | float_muladd_negate_c = 1, | |
20 | @@ -XXX,XX +XXX,XX @@ static void expand_vec_mul(TCGType type, unsigned vece, | 24 | float_muladd_negate_product = 2, |
21 | case TCG_TYPE_V64: | 25 | float_muladd_negate_result = 4, |
22 | t1 = tcg_temp_new_vec(TCG_TYPE_V128); | 26 | - float_muladd_halve_result = 8, |
23 | t2 = tcg_temp_new_vec(TCG_TYPE_V128); | 27 | }; |
24 | - tcg_gen_dup16i_vec(t2, 0); | 28 | |
25 | + zero = tcg_constant_vec(TCG_TYPE_V128, MO_8, 0); | 29 | /*---------------------------------------------------------------------------- |
26 | vec_gen_3(INDEX_op_x86_punpckl_vec, TCG_TYPE_V128, MO_8, | 30 | diff --git a/fpu/softfloat.c b/fpu/softfloat.c |
27 | - tcgv_vec_arg(t1), tcgv_vec_arg(v1), tcgv_vec_arg(t2)); | 31 | index XXXXXXX..XXXXXXX 100644 |
28 | + tcgv_vec_arg(t1), tcgv_vec_arg(v1), tcgv_vec_arg(zero)); | 32 | --- a/fpu/softfloat.c |
29 | vec_gen_3(INDEX_op_x86_punpckl_vec, TCG_TYPE_V128, MO_8, | 33 | +++ b/fpu/softfloat.c |
30 | - tcgv_vec_arg(t2), tcgv_vec_arg(t2), tcgv_vec_arg(v2)); | 34 | @@ -XXX,XX +XXX,XX @@ float32_muladd(float32 xa, float32 xb, float32 xc, int flags, float_status *s) |
31 | + tcgv_vec_arg(t2), tcgv_vec_arg(zero), tcgv_vec_arg(v2)); | 35 | if (unlikely(!can_use_fpu(s))) { |
32 | tcg_gen_mul_vec(MO_16, t1, t1, t2); | 36 | goto soft; |
33 | tcg_gen_shri_vec(MO_16, t1, t1, 8); | 37 | } |
34 | vec_gen_3(INDEX_op_x86_packus_vec, TCG_TYPE_V128, MO_8, | 38 | - if (unlikely(flags & float_muladd_halve_result)) { |
35 | @@ -XXX,XX +XXX,XX @@ static void expand_vec_mul(TCGType type, unsigned vece, | 39 | - goto soft; |
36 | t2 = tcg_temp_new_vec(type); | 40 | - } |
37 | t3 = tcg_temp_new_vec(type); | 41 | |
38 | t4 = tcg_temp_new_vec(type); | 42 | float32_input_flush3(&ua.s, &ub.s, &uc.s, s); |
39 | - tcg_gen_dup16i_vec(t4, 0); | 43 | if (unlikely(!f32_is_zon3(ua, ub, uc))) { |
40 | + zero = tcg_constant_vec(TCG_TYPE_V128, MO_8, 0); | 44 | @@ -XXX,XX +XXX,XX @@ float64_muladd(float64 xa, float64 xb, float64 xc, int flags, float_status *s) |
41 | vec_gen_3(INDEX_op_x86_punpckl_vec, type, MO_8, | 45 | if (unlikely(!can_use_fpu(s))) { |
42 | - tcgv_vec_arg(t1), tcgv_vec_arg(v1), tcgv_vec_arg(t4)); | 46 | goto soft; |
43 | + tcgv_vec_arg(t1), tcgv_vec_arg(v1), tcgv_vec_arg(zero)); | 47 | } |
44 | vec_gen_3(INDEX_op_x86_punpckl_vec, type, MO_8, | 48 | - if (unlikely(flags & float_muladd_halve_result)) { |
45 | - tcgv_vec_arg(t2), tcgv_vec_arg(t4), tcgv_vec_arg(v2)); | 49 | - goto soft; |
46 | + tcgv_vec_arg(t2), tcgv_vec_arg(zero), tcgv_vec_arg(v2)); | 50 | - } |
47 | vec_gen_3(INDEX_op_x86_punpckh_vec, type, MO_8, | 51 | |
48 | - tcgv_vec_arg(t3), tcgv_vec_arg(v1), tcgv_vec_arg(t4)); | 52 | float64_input_flush3(&ua.s, &ub.s, &uc.s, s); |
49 | + tcgv_vec_arg(t3), tcgv_vec_arg(v1), tcgv_vec_arg(zero)); | 53 | if (unlikely(!f64_is_zon3(ua, ub, uc))) { |
50 | vec_gen_3(INDEX_op_x86_punpckh_vec, type, MO_8, | 54 | diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc |
51 | - tcgv_vec_arg(t4), tcgv_vec_arg(t4), tcgv_vec_arg(v2)); | 55 | index XXXXXXX..XXXXXXX 100644 |
52 | + tcgv_vec_arg(t4), tcgv_vec_arg(zero), tcgv_vec_arg(v2)); | 56 | --- a/fpu/softfloat-parts.c.inc |
53 | tcg_gen_mul_vec(MO_16, t1, t1, t2); | 57 | +++ b/fpu/softfloat-parts.c.inc |
54 | tcg_gen_mul_vec(MO_16, t3, t3, t4); | 58 | @@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(muladd_scalbn)(FloatPartsN *a, FloatPartsN *b, |
55 | tcg_gen_shri_vec(MO_16, t1, t1, 8); | 59 | a->exp = p_widen.exp; |
56 | @@ -XXX,XX +XXX,XX @@ static bool expand_vec_cmp_noinv(TCGType type, unsigned vece, TCGv_vec v0, | 60 | |
57 | NEED_UMIN = 8, | 61 | return_normal: |
58 | NEED_UMAX = 16, | 62 | - /* TODO: Replace all use of float_muladd_halve_result with scale. */ |
59 | }; | 63 | - if (flags & float_muladd_halve_result) { |
60 | - TCGv_vec t1, t2; | 64 | - a->exp -= 1; |
61 | + TCGv_vec t1, t2, t3; | 65 | - } |
62 | uint8_t fixup; | 66 | a->exp += scale; |
63 | 67 | finish_sign: | |
64 | switch (cond) { | 68 | if (flags & float_muladd_negate_result) { |
65 | @@ -XXX,XX +XXX,XX @@ static bool expand_vec_cmp_noinv(TCGType type, unsigned vece, TCGv_vec v0, | ||
66 | } else if (fixup & NEED_BIAS) { | ||
67 | t1 = tcg_temp_new_vec(type); | ||
68 | t2 = tcg_temp_new_vec(type); | ||
69 | - tcg_gen_dupi_vec(vece, t2, 1ull << ((8 << vece) - 1)); | ||
70 | - tcg_gen_sub_vec(vece, t1, v1, t2); | ||
71 | - tcg_gen_sub_vec(vece, t2, v2, t2); | ||
72 | + t3 = tcg_constant_vec(type, vece, 1ull << ((8 << vece) - 1)); | ||
73 | + tcg_gen_sub_vec(vece, t1, v1, t3); | ||
74 | + tcg_gen_sub_vec(vece, t2, v2, t3); | ||
75 | v1 = t1; | ||
76 | v2 = t2; | ||
77 | cond = tcg_signed_cond(cond); | ||
78 | -- | 69 | -- |
79 | 2.25.1 | 70 | 2.43.0 |
80 | 71 | ||
81 | 72 | diff view generated by jsdifflib |
1 | Improve rotrv_vec to reduce "t1 = -v2, t2 = t1 + c" to | 1 | This rounding mode is used by Hexagon. |
---|---|---|---|
2 | "t1 = -v2, t2 = c - v2". This avoids a serial dependency | ||
3 | between t1 and t2. | ||
4 | 2 | ||
5 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 3 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
6 | --- | 4 | --- |
7 | tcg/aarch64/tcg-target.c.inc | 10 +++++----- | 5 | include/fpu/softfloat-types.h | 2 ++ |
8 | 1 file changed, 5 insertions(+), 5 deletions(-) | 6 | fpu/softfloat-parts.c.inc | 3 +++ |
7 | 2 files changed, 5 insertions(+) | ||
9 | 8 | ||
10 | diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc | 9 | diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h |
11 | index XXXXXXX..XXXXXXX 100644 | 10 | index XXXXXXX..XXXXXXX 100644 |
12 | --- a/tcg/aarch64/tcg-target.c.inc | 11 | --- a/include/fpu/softfloat-types.h |
13 | +++ b/tcg/aarch64/tcg-target.c.inc | 12 | +++ b/include/fpu/softfloat-types.h |
14 | @@ -XXX,XX +XXX,XX @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece, | 13 | @@ -XXX,XX +XXX,XX @@ typedef enum __attribute__((__packed__)) { |
15 | TCGArg a0, ...) | 14 | float_round_to_odd = 5, |
16 | { | 15 | /* Not an IEEE rounding mode: round to closest odd, overflow to inf */ |
17 | va_list va; | 16 | float_round_to_odd_inf = 6, |
18 | - TCGv_vec v0, v1, v2, t1, t2; | 17 | + /* Not an IEEE rounding mode: round to nearest even, overflow to max */ |
19 | + TCGv_vec v0, v1, v2, t1, t2, c1; | 18 | + float_round_nearest_even_max = 7, |
20 | TCGArg a2; | 19 | } FloatRoundMode; |
21 | 20 | ||
22 | va_start(va, a0); | 21 | /* |
23 | @@ -XXX,XX +XXX,XX @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece, | 22 | diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc |
24 | 23 | index XXXXXXX..XXXXXXX 100644 | |
25 | case INDEX_op_rotlv_vec: | 24 | --- a/fpu/softfloat-parts.c.inc |
26 | t1 = tcg_temp_new_vec(type); | 25 | +++ b/fpu/softfloat-parts.c.inc |
27 | - tcg_gen_dupi_vec(vece, t1, 8 << vece); | 26 | @@ -XXX,XX +XXX,XX @@ static void partsN(uncanon_normal)(FloatPartsN *p, float_status *s, |
28 | - tcg_gen_sub_vec(vece, t1, v2, t1); | 27 | int exp, flags = 0; |
29 | + c1 = tcg_constant_vec(type, vece, 8 << vece); | 28 | |
30 | + tcg_gen_sub_vec(vece, t1, v2, c1); | 29 | switch (s->float_rounding_mode) { |
31 | /* Right shifts are negative left shifts for AArch64. */ | 30 | + case float_round_nearest_even_max: |
32 | vec_gen_3(INDEX_op_shlv_vec, type, vece, tcgv_vec_arg(t1), | 31 | + overflow_norm = true; |
33 | tcgv_vec_arg(v1), tcgv_vec_arg(t1)); | 32 | + /* fall through */ |
34 | @@ -XXX,XX +XXX,XX @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece, | 33 | case float_round_nearest_even: |
35 | case INDEX_op_rotrv_vec: | 34 | if (N > 64 && frac_lsb == 0) { |
36 | t1 = tcg_temp_new_vec(type); | 35 | inc = ((p->frac_hi & 1) || (p->frac_lo & round_mask) != frac_lsbm1 |
37 | t2 = tcg_temp_new_vec(type); | ||
38 | + c1 = tcg_constant_vec(type, vece, 8 << vece); | ||
39 | tcg_gen_neg_vec(vece, t1, v2); | ||
40 | - tcg_gen_dupi_vec(vece, t2, 8 << vece); | ||
41 | - tcg_gen_add_vec(vece, t2, t1, t2); | ||
42 | + tcg_gen_sub_vec(vece, t2, c1, v2); | ||
43 | /* Right shifts are negative left shifts for AArch64. */ | ||
44 | vec_gen_3(INDEX_op_shlv_vec, type, vece, tcgv_vec_arg(t1), | ||
45 | tcgv_vec_arg(v1), tcgv_vec_arg(t1)); | ||
46 | -- | 36 | -- |
47 | 2.25.1 | 37 | 2.43.0 |
48 | |||
49 | diff view generated by jsdifflib |
1 | This will reduce the differences between 32-bit and 64-bit hosts, | 1 | Certain Hexagon instructions suppress changes to the result |
---|---|---|---|
2 | allowing full 64-bit constants to be created with the same interface. | 2 | when the product of fma() is a true zero. |
3 | 3 | ||
4 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 4 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
5 | --- | 5 | --- |
6 | include/tcg/tcg.h | 2 +- | 6 | include/fpu/softfloat.h | 5 +++++ |
7 | tcg/tcg.c | 2 +- | 7 | fpu/softfloat.c | 3 +++ |
8 | 2 files changed, 2 insertions(+), 2 deletions(-) | 8 | fpu/softfloat-parts.c.inc | 4 +++- |
9 | 3 files changed, 11 insertions(+), 1 deletion(-) | ||
9 | 10 | ||
10 | diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h | 11 | diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h |
11 | index XXXXXXX..XXXXXXX 100644 | 12 | index XXXXXXX..XXXXXXX 100644 |
12 | --- a/include/tcg/tcg.h | 13 | --- a/include/fpu/softfloat.h |
13 | +++ b/include/tcg/tcg.h | 14 | +++ b/include/fpu/softfloat.h |
14 | @@ -XXX,XX +XXX,XX @@ typedef struct TCGTemp { | 15 | @@ -XXX,XX +XXX,XX @@ bfloat16 bfloat16_squash_input_denormal(bfloat16 a, float_status *status); |
15 | unsigned int mem_allocated:1; | 16 | | Using these differs from negating an input or output before calling |
16 | unsigned int temp_allocated:1; | 17 | | the muladd function in that this means that a NaN doesn't have its |
17 | 18 | | sign bit inverted before it is propagated. | |
18 | - tcg_target_long val; | 19 | +| |
19 | + int64_t val; | 20 | +| With float_muladd_suppress_add_product_zero, if A or B is zero |
20 | struct TCGTemp *mem_base; | 21 | +| such that the product is a true zero, then return C without addition. |
21 | intptr_t mem_offset; | 22 | +| This preserves the sign of C when C is +/- 0. Used for Hexagon. |
22 | const char *name; | 23 | *----------------------------------------------------------------------------*/ |
23 | diff --git a/tcg/tcg.c b/tcg/tcg.c | 24 | enum { |
25 | float_muladd_negate_c = 1, | ||
26 | float_muladd_negate_product = 2, | ||
27 | float_muladd_negate_result = 4, | ||
28 | + float_muladd_suppress_add_product_zero = 8, | ||
29 | }; | ||
30 | |||
31 | /*---------------------------------------------------------------------------- | ||
32 | diff --git a/fpu/softfloat.c b/fpu/softfloat.c | ||
24 | index XXXXXXX..XXXXXXX 100644 | 33 | index XXXXXXX..XXXXXXX 100644 |
25 | --- a/tcg/tcg.c | 34 | --- a/fpu/softfloat.c |
26 | +++ b/tcg/tcg.c | 35 | +++ b/fpu/softfloat.c |
27 | @@ -XXX,XX +XXX,XX @@ static void dump_regs(TCGContext *s) | 36 | @@ -XXX,XX +XXX,XX @@ float32_muladd(float32 xa, float32 xb, float32 xc, int flags, float_status *s) |
28 | tcg_target_reg_names[ts->mem_base->reg]); | 37 | if (unlikely(!can_use_fpu(s))) { |
29 | break; | 38 | goto soft; |
30 | case TEMP_VAL_CONST: | 39 | } |
31 | - printf("$0x%" TCG_PRIlx, ts->val); | 40 | + if (unlikely(flags & float_muladd_suppress_add_product_zero)) { |
32 | + printf("$0x%" PRIx64, ts->val); | 41 | + goto soft; |
33 | break; | 42 | + } |
34 | case TEMP_VAL_DEAD: | 43 | |
35 | printf("D"); | 44 | float32_input_flush3(&ua.s, &ub.s, &uc.s, s); |
45 | if (unlikely(!f32_is_zon3(ua, ub, uc))) { | ||
46 | diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc | ||
47 | index XXXXXXX..XXXXXXX 100644 | ||
48 | --- a/fpu/softfloat-parts.c.inc | ||
49 | +++ b/fpu/softfloat-parts.c.inc | ||
50 | @@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(muladd_scalbn)(FloatPartsN *a, FloatPartsN *b, | ||
51 | goto return_normal; | ||
52 | } | ||
53 | if (c->cls == float_class_zero) { | ||
54 | - if (a->sign != c->sign) { | ||
55 | + if (flags & float_muladd_suppress_add_product_zero) { | ||
56 | + a->sign = c->sign; | ||
57 | + } else if (a->sign != c->sign) { | ||
58 | goto return_sub_zero; | ||
59 | } | ||
60 | goto return_zero; | ||
36 | -- | 61 | -- |
37 | 2.25.1 | 62 | 2.43.0 |
38 | |||
39 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | There are no special cases for this instruction. | ||
2 | Remove internal_mpyf as unused. | ||
1 | 3 | ||
4 | Reviewed-by: Brian Cain <brian.cain@oss.qualcomm.com> | ||
5 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
6 | --- | ||
7 | target/hexagon/fma_emu.h | 1 - | ||
8 | target/hexagon/fma_emu.c | 8 -------- | ||
9 | target/hexagon/op_helper.c | 2 +- | ||
10 | 3 files changed, 1 insertion(+), 10 deletions(-) | ||
11 | |||
12 | diff --git a/target/hexagon/fma_emu.h b/target/hexagon/fma_emu.h | ||
13 | index XXXXXXX..XXXXXXX 100644 | ||
14 | --- a/target/hexagon/fma_emu.h | ||
15 | +++ b/target/hexagon/fma_emu.h | ||
16 | @@ -XXX,XX +XXX,XX @@ int32_t float32_getexp(float32 f32); | ||
17 | float32 infinite_float32(uint8_t sign); | ||
18 | float32 internal_fmafx(float32 a, float32 b, float32 c, | ||
19 | int scale, float_status *fp_status); | ||
20 | -float32 internal_mpyf(float32 a, float32 b, float_status *fp_status); | ||
21 | float64 internal_mpyhh(float64 a, float64 b, | ||
22 | unsigned long long int accumulated, | ||
23 | float_status *fp_status); | ||
24 | diff --git a/target/hexagon/fma_emu.c b/target/hexagon/fma_emu.c | ||
25 | index XXXXXXX..XXXXXXX 100644 | ||
26 | --- a/target/hexagon/fma_emu.c | ||
27 | +++ b/target/hexagon/fma_emu.c | ||
28 | @@ -XXX,XX +XXX,XX @@ float32 internal_fmafx(float32 a, float32 b, float32 c, int scale, | ||
29 | return accum_round_float32(result, fp_status); | ||
30 | } | ||
31 | |||
32 | -float32 internal_mpyf(float32 a, float32 b, float_status *fp_status) | ||
33 | -{ | ||
34 | - if (float32_is_zero(a) || float32_is_zero(b)) { | ||
35 | - return float32_mul(a, b, fp_status); | ||
36 | - } | ||
37 | - return internal_fmafx(a, b, float32_zero, 0, fp_status); | ||
38 | -} | ||
39 | - | ||
40 | float64 internal_mpyhh(float64 a, float64 b, | ||
41 | unsigned long long int accumulated, | ||
42 | float_status *fp_status) | ||
43 | diff --git a/target/hexagon/op_helper.c b/target/hexagon/op_helper.c | ||
44 | index XXXXXXX..XXXXXXX 100644 | ||
45 | --- a/target/hexagon/op_helper.c | ||
46 | +++ b/target/hexagon/op_helper.c | ||
47 | @@ -XXX,XX +XXX,XX @@ float32 HELPER(sfmpy)(CPUHexagonState *env, float32 RsV, float32 RtV) | ||
48 | { | ||
49 | float32 RdV; | ||
50 | arch_fpop_start(env); | ||
51 | - RdV = internal_mpyf(RsV, RtV, &env->fp_status); | ||
52 | + RdV = float32_mul(RsV, RtV, &env->fp_status); | ||
53 | arch_fpop_end(env); | ||
54 | return RdV; | ||
55 | } | ||
56 | -- | ||
57 | 2.43.0 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | There are no special cases for this instruction. | ||
1 | 2 | ||
3 | Reviewed-by: Brian Cain <brian.cain@oss.qualcomm.com> | ||
4 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
5 | --- | ||
6 | target/hexagon/op_helper.c | 2 +- | ||
7 | 1 file changed, 1 insertion(+), 1 deletion(-) | ||
8 | |||
9 | diff --git a/target/hexagon/op_helper.c b/target/hexagon/op_helper.c | ||
10 | index XXXXXXX..XXXXXXX 100644 | ||
11 | --- a/target/hexagon/op_helper.c | ||
12 | +++ b/target/hexagon/op_helper.c | ||
13 | @@ -XXX,XX +XXX,XX @@ float32 HELPER(sffma)(CPUHexagonState *env, float32 RxV, | ||
14 | float32 RsV, float32 RtV) | ||
15 | { | ||
16 | arch_fpop_start(env); | ||
17 | - RxV = internal_fmafx(RsV, RtV, RxV, 0, &env->fp_status); | ||
18 | + RxV = float32_muladd(RsV, RtV, RxV, 0, &env->fp_status); | ||
19 | arch_fpop_end(env); | ||
20 | return RxV; | ||
21 | } | ||
22 | -- | ||
23 | 2.43.0 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | There are no special cases for this instruction. Since hexagon | ||
2 | always uses default-nan mode, explicitly negating the first | ||
3 | input is unnecessary. Use float_muladd_negate_product instead. | ||
1 | 4 | ||
5 | Reviewed-by: Brian Cain <brian.cain@oss.qualcomm.com> | ||
6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | --- | ||
8 | target/hexagon/op_helper.c | 5 ++--- | ||
9 | 1 file changed, 2 insertions(+), 3 deletions(-) | ||
10 | |||
11 | diff --git a/target/hexagon/op_helper.c b/target/hexagon/op_helper.c | ||
12 | index XXXXXXX..XXXXXXX 100644 | ||
13 | --- a/target/hexagon/op_helper.c | ||
14 | +++ b/target/hexagon/op_helper.c | ||
15 | @@ -XXX,XX +XXX,XX @@ float32 HELPER(sffma_sc)(CPUHexagonState *env, float32 RxV, | ||
16 | float32 HELPER(sffms)(CPUHexagonState *env, float32 RxV, | ||
17 | float32 RsV, float32 RtV) | ||
18 | { | ||
19 | - float32 neg_RsV; | ||
20 | arch_fpop_start(env); | ||
21 | - neg_RsV = float32_set_sign(RsV, float32_is_neg(RsV) ? 0 : 1); | ||
22 | - RxV = internal_fmafx(neg_RsV, RtV, RxV, 0, &env->fp_status); | ||
23 | + RxV = float32_muladd(RsV, RtV, RxV, float_muladd_negate_product, | ||
24 | + &env->fp_status); | ||
25 | arch_fpop_end(env); | ||
26 | return RxV; | ||
27 | } | ||
28 | -- | ||
29 | 2.43.0 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | This instruction has a special case that 0 * x + c returns c | ||
2 | without the normal sign folding that comes with 0 + -0. | ||
3 | Use the new float_muladd_suppress_add_product_zero to | ||
4 | describe this. | ||
1 | 5 | ||
6 | Reviewed-by: Brian Cain <brian.cain@oss.qualcomm.com> | ||
7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | --- | ||
9 | target/hexagon/op_helper.c | 11 +++-------- | ||
10 | 1 file changed, 3 insertions(+), 8 deletions(-) | ||
11 | |||
12 | diff --git a/target/hexagon/op_helper.c b/target/hexagon/op_helper.c | ||
13 | index XXXXXXX..XXXXXXX 100644 | ||
14 | --- a/target/hexagon/op_helper.c | ||
15 | +++ b/target/hexagon/op_helper.c | ||
16 | @@ -XXX,XX +XXX,XX @@ static float32 check_nan(float32 dst, float32 x, float_status *fp_status) | ||
17 | float32 HELPER(sffma_sc)(CPUHexagonState *env, float32 RxV, | ||
18 | float32 RsV, float32 RtV, float32 PuV) | ||
19 | { | ||
20 | - size4s_t tmp; | ||
21 | arch_fpop_start(env); | ||
22 | - RxV = check_nan(RxV, RxV, &env->fp_status); | ||
23 | - RxV = check_nan(RxV, RsV, &env->fp_status); | ||
24 | - RxV = check_nan(RxV, RtV, &env->fp_status); | ||
25 | - tmp = internal_fmafx(RsV, RtV, RxV, fSXTN(8, 64, PuV), &env->fp_status); | ||
26 | - if (!(float32_is_zero(RxV) && is_zero_prod(RsV, RtV))) { | ||
27 | - RxV = tmp; | ||
28 | - } | ||
29 | + RxV = float32_muladd_scalbn(RsV, RtV, RxV, fSXTN(8, 64, PuV), | ||
30 | + float_muladd_suppress_add_product_zero, | ||
31 | + &env->fp_status); | ||
32 | arch_fpop_end(env); | ||
33 | return RxV; | ||
34 | } | ||
35 | -- | ||
36 | 2.43.0 | diff view generated by jsdifflib |
1 | There are multiple special cases for this instruction. | ||
---|---|---|---|
2 | (1) The saturate to normal maximum instead of overflow to infinity is | ||
3 | handled by the new float_round_nearest_even_max rounding mode. | ||
4 | (2) The 0 * n + c special case is handled by the new | ||
5 | float_muladd_suppress_add_product_zero flag. | ||
6 | (3) The Inf - Inf -> 0 special case can be detected after the fact | ||
7 | by examining float_flag_invalid_isi. | ||
8 | |||
9 | Reviewed-by: Brian Cain <brian.cain@oss.qualcomm.com> | ||
1 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 10 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
2 | --- | 11 | --- |
3 | include/tcg/tcg-op.h | 13 +-- | 12 | target/hexagon/op_helper.c | 105 +++++++++---------------------------- |
4 | tcg/tcg-op.c | 227 ++++++++++++++++++++----------------------- | 13 | 1 file changed, 26 insertions(+), 79 deletions(-) |
5 | 2 files changed, 109 insertions(+), 131 deletions(-) | ||
6 | 14 | ||
7 | diff --git a/include/tcg/tcg-op.h b/include/tcg/tcg-op.h | 15 | diff --git a/target/hexagon/op_helper.c b/target/hexagon/op_helper.c |
8 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
9 | --- a/include/tcg/tcg-op.h | 17 | --- a/target/hexagon/op_helper.c |
10 | +++ b/include/tcg/tcg-op.h | 18 | +++ b/target/hexagon/op_helper.c |
11 | @@ -XXX,XX +XXX,XX @@ void tcg_gen_mb(TCGBar); | 19 | @@ -XXX,XX +XXX,XX @@ float32 HELPER(sffma)(CPUHexagonState *env, float32 RxV, |
12 | 20 | return RxV; | |
13 | /* 32 bit ops */ | ||
14 | |||
15 | +void tcg_gen_movi_i32(TCGv_i32 ret, int32_t arg); | ||
16 | void tcg_gen_addi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); | ||
17 | void tcg_gen_subfi_i32(TCGv_i32 ret, int32_t arg1, TCGv_i32 arg2); | ||
18 | void tcg_gen_subi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); | ||
19 | @@ -XXX,XX +XXX,XX @@ static inline void tcg_gen_mov_i32(TCGv_i32 ret, TCGv_i32 arg) | ||
20 | } | ||
21 | } | 21 | } |
22 | 22 | ||
23 | -static inline void tcg_gen_movi_i32(TCGv_i32 ret, int32_t arg) | 23 | -static bool is_zero_prod(float32 a, float32 b) |
24 | -{ | 24 | -{ |
25 | - tcg_gen_op2i_i32(INDEX_op_movi_i32, ret, arg); | 25 | - return ((float32_is_zero(a) && is_finite(b)) || |
26 | - (float32_is_zero(b) && is_finite(a))); | ||
26 | -} | 27 | -} |
27 | - | 28 | - |
28 | static inline void tcg_gen_ld8u_i32(TCGv_i32 ret, TCGv_ptr arg2, | 29 | -static float32 check_nan(float32 dst, float32 x, float_status *fp_status) |
29 | tcg_target_long offset) | ||
30 | { | ||
31 | @@ -XXX,XX +XXX,XX @@ static inline void tcg_gen_not_i32(TCGv_i32 ret, TCGv_i32 arg) | ||
32 | |||
33 | /* 64 bit ops */ | ||
34 | |||
35 | +void tcg_gen_movi_i64(TCGv_i64 ret, int64_t arg); | ||
36 | void tcg_gen_addi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); | ||
37 | void tcg_gen_subfi_i64(TCGv_i64 ret, int64_t arg1, TCGv_i64 arg2); | ||
38 | void tcg_gen_subi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); | ||
39 | @@ -XXX,XX +XXX,XX @@ static inline void tcg_gen_mov_i64(TCGv_i64 ret, TCGv_i64 arg) | ||
40 | } | ||
41 | } | ||
42 | |||
43 | -static inline void tcg_gen_movi_i64(TCGv_i64 ret, int64_t arg) | ||
44 | -{ | 30 | -{ |
45 | - tcg_gen_op2i_i64(INDEX_op_movi_i64, ret, arg); | 31 | - float32 ret = dst; |
32 | - if (float32_is_any_nan(x)) { | ||
33 | - if (extract32(x, 22, 1) == 0) { | ||
34 | - float_raise(float_flag_invalid, fp_status); | ||
35 | - } | ||
36 | - ret = make_float32(0xffffffff); /* nan */ | ||
37 | - } | ||
38 | - return ret; | ||
46 | -} | 39 | -} |
47 | - | 40 | - |
48 | static inline void tcg_gen_ld8u_i64(TCGv_i64 ret, TCGv_ptr arg2, | 41 | float32 HELPER(sffma_sc)(CPUHexagonState *env, float32 RxV, |
49 | tcg_target_long offset) | 42 | float32 RsV, float32 RtV, float32 PuV) |
50 | { | 43 | { |
51 | @@ -XXX,XX +XXX,XX @@ static inline void tcg_gen_sub_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) | 44 | @@ -XXX,XX +XXX,XX @@ float32 HELPER(sffms)(CPUHexagonState *env, float32 RxV, |
52 | 45 | return RxV; | |
53 | void tcg_gen_discard_i64(TCGv_i64 arg); | 46 | } |
54 | void tcg_gen_mov_i64(TCGv_i64 ret, TCGv_i64 arg); | 47 | |
55 | -void tcg_gen_movi_i64(TCGv_i64 ret, int64_t arg); | 48 | -static bool is_inf_prod(int32_t a, int32_t b) |
56 | void tcg_gen_ld8u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset); | 49 | +static float32 do_sffma_lib(CPUHexagonState *env, float32 RxV, |
57 | void tcg_gen_ld8s_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset); | 50 | + float32 RsV, float32 RtV, int negate) |
58 | void tcg_gen_ld16u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset); | 51 | { |
59 | diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c | 52 | - return (float32_is_infinity(a) && float32_is_infinity(b)) || |
60 | index XXXXXXX..XXXXXXX 100644 | 53 | - (float32_is_infinity(a) && is_finite(b) && !float32_is_zero(b)) || |
61 | --- a/tcg/tcg-op.c | 54 | - (float32_is_infinity(b) && is_finite(a) && !float32_is_zero(a)); |
62 | +++ b/tcg/tcg-op.c | 55 | + int flags; |
63 | @@ -XXX,XX +XXX,XX @@ void tcg_gen_mb(TCGBar mb_type) | ||
64 | |||
65 | /* 32 bit ops */ | ||
66 | |||
67 | +void tcg_gen_movi_i32(TCGv_i32 ret, int32_t arg) | ||
68 | +{ | ||
69 | + tcg_gen_mov_i32(ret, tcg_constant_i32(arg)); | ||
70 | +} | ||
71 | + | 56 | + |
72 | void tcg_gen_addi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) | 57 | + arch_fpop_start(env); |
58 | + | ||
59 | + set_float_rounding_mode(float_round_nearest_even_max, &env->fp_status); | ||
60 | + RxV = float32_muladd(RsV, RtV, RxV, | ||
61 | + negate | float_muladd_suppress_add_product_zero, | ||
62 | + &env->fp_status); | ||
63 | + | ||
64 | + flags = get_float_exception_flags(&env->fp_status); | ||
65 | + if (flags) { | ||
66 | + /* Flags are suppressed by this instruction. */ | ||
67 | + set_float_exception_flags(0, &env->fp_status); | ||
68 | + | ||
69 | + /* Return 0 for Inf - Inf. */ | ||
70 | + if (flags & float_flag_invalid_isi) { | ||
71 | + RxV = 0; | ||
72 | + } | ||
73 | + } | ||
74 | + | ||
75 | + arch_fpop_end(env); | ||
76 | + return RxV; | ||
77 | } | ||
78 | |||
79 | float32 HELPER(sffma_lib)(CPUHexagonState *env, float32 RxV, | ||
80 | float32 RsV, float32 RtV) | ||
73 | { | 81 | { |
74 | /* some cases can be optimized here */ | 82 | - bool infinp; |
75 | if (arg2 == 0) { | 83 | - bool infminusinf; |
76 | tcg_gen_mov_i32(ret, arg1); | 84 | - float32 tmp; |
77 | } else { | 85 | - |
78 | - TCGv_i32 t0 = tcg_const_i32(arg2); | 86 | - arch_fpop_start(env); |
79 | - tcg_gen_add_i32(ret, arg1, t0); | 87 | - set_float_rounding_mode(float_round_nearest_even, &env->fp_status); |
80 | - tcg_temp_free_i32(t0); | 88 | - infminusinf = float32_is_infinity(RxV) && |
81 | + tcg_gen_add_i32(ret, arg1, tcg_constant_i32(arg2)); | 89 | - is_inf_prod(RsV, RtV) && |
82 | } | 90 | - (fGETBIT(31, RsV ^ RxV ^ RtV) != 0); |
91 | - infinp = float32_is_infinity(RxV) || | ||
92 | - float32_is_infinity(RtV) || | ||
93 | - float32_is_infinity(RsV); | ||
94 | - RxV = check_nan(RxV, RxV, &env->fp_status); | ||
95 | - RxV = check_nan(RxV, RsV, &env->fp_status); | ||
96 | - RxV = check_nan(RxV, RtV, &env->fp_status); | ||
97 | - tmp = internal_fmafx(RsV, RtV, RxV, 0, &env->fp_status); | ||
98 | - if (!(float32_is_zero(RxV) && is_zero_prod(RsV, RtV))) { | ||
99 | - RxV = tmp; | ||
100 | - } | ||
101 | - set_float_exception_flags(0, &env->fp_status); | ||
102 | - if (float32_is_infinity(RxV) && !infinp) { | ||
103 | - RxV = RxV - 1; | ||
104 | - } | ||
105 | - if (infminusinf) { | ||
106 | - RxV = 0; | ||
107 | - } | ||
108 | - arch_fpop_end(env); | ||
109 | - return RxV; | ||
110 | + return do_sffma_lib(env, RxV, RsV, RtV, 0); | ||
83 | } | 111 | } |
84 | 112 | ||
85 | @@ -XXX,XX +XXX,XX @@ void tcg_gen_subfi_i32(TCGv_i32 ret, int32_t arg1, TCGv_i32 arg2) | 113 | float32 HELPER(sffms_lib)(CPUHexagonState *env, float32 RxV, |
86 | /* Don't recurse with tcg_gen_neg_i32. */ | 114 | float32 RsV, float32 RtV) |
87 | tcg_gen_op2_i32(INDEX_op_neg_i32, ret, arg2); | 115 | { |
88 | } else { | 116 | - bool infinp; |
89 | - TCGv_i32 t0 = tcg_const_i32(arg1); | 117 | - bool infminusinf; |
90 | - tcg_gen_sub_i32(ret, t0, arg2); | 118 | - float32 tmp; |
91 | - tcg_temp_free_i32(t0); | 119 | - |
92 | + tcg_gen_sub_i32(ret, tcg_constant_i32(arg1), arg2); | 120 | - arch_fpop_start(env); |
93 | } | 121 | - set_float_rounding_mode(float_round_nearest_even, &env->fp_status); |
122 | - infminusinf = float32_is_infinity(RxV) && | ||
123 | - is_inf_prod(RsV, RtV) && | ||
124 | - (fGETBIT(31, RsV ^ RxV ^ RtV) == 0); | ||
125 | - infinp = float32_is_infinity(RxV) || | ||
126 | - float32_is_infinity(RtV) || | ||
127 | - float32_is_infinity(RsV); | ||
128 | - RxV = check_nan(RxV, RxV, &env->fp_status); | ||
129 | - RxV = check_nan(RxV, RsV, &env->fp_status); | ||
130 | - RxV = check_nan(RxV, RtV, &env->fp_status); | ||
131 | - float32 minus_RsV = float32_sub(float32_zero, RsV, &env->fp_status); | ||
132 | - tmp = internal_fmafx(minus_RsV, RtV, RxV, 0, &env->fp_status); | ||
133 | - if (!(float32_is_zero(RxV) && is_zero_prod(RsV, RtV))) { | ||
134 | - RxV = tmp; | ||
135 | - } | ||
136 | - set_float_exception_flags(0, &env->fp_status); | ||
137 | - if (float32_is_infinity(RxV) && !infinp) { | ||
138 | - RxV = RxV - 1; | ||
139 | - } | ||
140 | - if (infminusinf) { | ||
141 | - RxV = 0; | ||
142 | - } | ||
143 | - arch_fpop_end(env); | ||
144 | - return RxV; | ||
145 | + return do_sffma_lib(env, RxV, RsV, RtV, float_muladd_negate_product); | ||
94 | } | 146 | } |
95 | 147 | ||
96 | @@ -XXX,XX +XXX,XX @@ void tcg_gen_subi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) | 148 | float64 HELPER(dfmpyfix)(CPUHexagonState *env, float64 RssV, float64 RttV) |
97 | if (arg2 == 0) { | ||
98 | tcg_gen_mov_i32(ret, arg1); | ||
99 | } else { | ||
100 | - TCGv_i32 t0 = tcg_const_i32(arg2); | ||
101 | - tcg_gen_sub_i32(ret, arg1, t0); | ||
102 | - tcg_temp_free_i32(t0); | ||
103 | + tcg_gen_sub_i32(ret, arg1, tcg_constant_i32(arg2)); | ||
104 | } | ||
105 | } | ||
106 | |||
107 | void tcg_gen_andi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) | ||
108 | { | ||
109 | - TCGv_i32 t0; | ||
110 | /* Some cases can be optimized here. */ | ||
111 | switch (arg2) { | ||
112 | case 0: | ||
113 | @@ -XXX,XX +XXX,XX @@ void tcg_gen_andi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) | ||
114 | } | ||
115 | break; | ||
116 | } | ||
117 | - t0 = tcg_const_i32(arg2); | ||
118 | - tcg_gen_and_i32(ret, arg1, t0); | ||
119 | - tcg_temp_free_i32(t0); | ||
120 | + | ||
121 | + tcg_gen_and_i32(ret, arg1, tcg_constant_i32(arg2)); | ||
122 | } | ||
123 | |||
124 | void tcg_gen_ori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) | ||
125 | @@ -XXX,XX +XXX,XX @@ void tcg_gen_ori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) | ||
126 | } else if (arg2 == 0) { | ||
127 | tcg_gen_mov_i32(ret, arg1); | ||
128 | } else { | ||
129 | - TCGv_i32 t0 = tcg_const_i32(arg2); | ||
130 | - tcg_gen_or_i32(ret, arg1, t0); | ||
131 | - tcg_temp_free_i32(t0); | ||
132 | + tcg_gen_or_i32(ret, arg1, tcg_constant_i32(arg2)); | ||
133 | } | ||
134 | } | ||
135 | |||
136 | @@ -XXX,XX +XXX,XX @@ void tcg_gen_xori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) | ||
137 | /* Don't recurse with tcg_gen_not_i32. */ | ||
138 | tcg_gen_op2_i32(INDEX_op_not_i32, ret, arg1); | ||
139 | } else { | ||
140 | - TCGv_i32 t0 = tcg_const_i32(arg2); | ||
141 | - tcg_gen_xor_i32(ret, arg1, t0); | ||
142 | - tcg_temp_free_i32(t0); | ||
143 | + tcg_gen_xor_i32(ret, arg1, tcg_constant_i32(arg2)); | ||
144 | } | ||
145 | } | ||
146 | |||
147 | @@ -XXX,XX +XXX,XX @@ void tcg_gen_shli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) | ||
148 | if (arg2 == 0) { | ||
149 | tcg_gen_mov_i32(ret, arg1); | ||
150 | } else { | ||
151 | - TCGv_i32 t0 = tcg_const_i32(arg2); | ||
152 | - tcg_gen_shl_i32(ret, arg1, t0); | ||
153 | - tcg_temp_free_i32(t0); | ||
154 | + tcg_gen_shl_i32(ret, arg1, tcg_constant_i32(arg2)); | ||
155 | } | ||
156 | } | ||
157 | |||
158 | @@ -XXX,XX +XXX,XX @@ void tcg_gen_shri_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) | ||
159 | if (arg2 == 0) { | ||
160 | tcg_gen_mov_i32(ret, arg1); | ||
161 | } else { | ||
162 | - TCGv_i32 t0 = tcg_const_i32(arg2); | ||
163 | - tcg_gen_shr_i32(ret, arg1, t0); | ||
164 | - tcg_temp_free_i32(t0); | ||
165 | + tcg_gen_shr_i32(ret, arg1, tcg_constant_i32(arg2)); | ||
166 | } | ||
167 | } | ||
168 | |||
169 | @@ -XXX,XX +XXX,XX @@ void tcg_gen_sari_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) | ||
170 | if (arg2 == 0) { | ||
171 | tcg_gen_mov_i32(ret, arg1); | ||
172 | } else { | ||
173 | - TCGv_i32 t0 = tcg_const_i32(arg2); | ||
174 | - tcg_gen_sar_i32(ret, arg1, t0); | ||
175 | - tcg_temp_free_i32(t0); | ||
176 | + tcg_gen_sar_i32(ret, arg1, tcg_constant_i32(arg2)); | ||
177 | } | ||
178 | } | ||
179 | |||
180 | @@ -XXX,XX +XXX,XX @@ void tcg_gen_brcondi_i32(TCGCond cond, TCGv_i32 arg1, int32_t arg2, TCGLabel *l) | ||
181 | if (cond == TCG_COND_ALWAYS) { | ||
182 | tcg_gen_br(l); | ||
183 | } else if (cond != TCG_COND_NEVER) { | ||
184 | - TCGv_i32 t0 = tcg_const_i32(arg2); | ||
185 | - tcg_gen_brcond_i32(cond, arg1, t0, l); | ||
186 | - tcg_temp_free_i32(t0); | ||
187 | + tcg_gen_brcond_i32(cond, arg1, tcg_constant_i32(arg2), l); | ||
188 | } | ||
189 | } | ||
190 | |||
191 | @@ -XXX,XX +XXX,XX @@ void tcg_gen_setcond_i32(TCGCond cond, TCGv_i32 ret, | ||
192 | void tcg_gen_setcondi_i32(TCGCond cond, TCGv_i32 ret, | ||
193 | TCGv_i32 arg1, int32_t arg2) | ||
194 | { | ||
195 | - TCGv_i32 t0 = tcg_const_i32(arg2); | ||
196 | - tcg_gen_setcond_i32(cond, ret, arg1, t0); | ||
197 | - tcg_temp_free_i32(t0); | ||
198 | + tcg_gen_setcond_i32(cond, ret, arg1, tcg_constant_i32(arg2)); | ||
199 | } | ||
200 | |||
201 | void tcg_gen_muli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) | ||
202 | @@ -XXX,XX +XXX,XX @@ void tcg_gen_muli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) | ||
203 | } else if (is_power_of_2(arg2)) { | ||
204 | tcg_gen_shli_i32(ret, arg1, ctz32(arg2)); | ||
205 | } else { | ||
206 | - TCGv_i32 t0 = tcg_const_i32(arg2); | ||
207 | - tcg_gen_mul_i32(ret, arg1, t0); | ||
208 | - tcg_temp_free_i32(t0); | ||
209 | + tcg_gen_mul_i32(ret, arg1, tcg_constant_i32(arg2)); | ||
210 | } | ||
211 | } | ||
212 | |||
213 | @@ -XXX,XX +XXX,XX @@ void tcg_gen_clz_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) | ||
214 | |||
215 | void tcg_gen_clzi_i32(TCGv_i32 ret, TCGv_i32 arg1, uint32_t arg2) | ||
216 | { | ||
217 | - TCGv_i32 t = tcg_const_i32(arg2); | ||
218 | - tcg_gen_clz_i32(ret, arg1, t); | ||
219 | - tcg_temp_free_i32(t); | ||
220 | + tcg_gen_clz_i32(ret, arg1, tcg_constant_i32(arg2)); | ||
221 | } | ||
222 | |||
223 | void tcg_gen_ctz_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) | ||
224 | @@ -XXX,XX +XXX,XX @@ void tcg_gen_ctz_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) | ||
225 | tcg_gen_clzi_i32(t, t, 32); | ||
226 | tcg_gen_xori_i32(t, t, 31); | ||
227 | } | ||
228 | - z = tcg_const_i32(0); | ||
229 | + z = tcg_constant_i32(0); | ||
230 | tcg_gen_movcond_i32(TCG_COND_EQ, ret, arg1, z, arg2, t); | ||
231 | tcg_temp_free_i32(t); | ||
232 | - tcg_temp_free_i32(z); | ||
233 | } else { | ||
234 | gen_helper_ctz_i32(ret, arg1, arg2); | ||
235 | } | ||
236 | @@ -XXX,XX +XXX,XX @@ void tcg_gen_ctzi_i32(TCGv_i32 ret, TCGv_i32 arg1, uint32_t arg2) | ||
237 | tcg_gen_ctpop_i32(ret, t); | ||
238 | tcg_temp_free_i32(t); | ||
239 | } else { | ||
240 | - TCGv_i32 t = tcg_const_i32(arg2); | ||
241 | - tcg_gen_ctz_i32(ret, arg1, t); | ||
242 | - tcg_temp_free_i32(t); | ||
243 | + tcg_gen_ctz_i32(ret, arg1, tcg_constant_i32(arg2)); | ||
244 | } | ||
245 | } | ||
246 | |||
247 | @@ -XXX,XX +XXX,XX @@ void tcg_gen_rotli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) | ||
248 | if (arg2 == 0) { | ||
249 | tcg_gen_mov_i32(ret, arg1); | ||
250 | } else if (TCG_TARGET_HAS_rot_i32) { | ||
251 | - TCGv_i32 t0 = tcg_const_i32(arg2); | ||
252 | - tcg_gen_rotl_i32(ret, arg1, t0); | ||
253 | - tcg_temp_free_i32(t0); | ||
254 | + tcg_gen_rotl_i32(ret, arg1, tcg_constant_i32(arg2)); | ||
255 | } else { | ||
256 | TCGv_i32 t0, t1; | ||
257 | t0 = tcg_temp_new_i32(); | ||
258 | @@ -XXX,XX +XXX,XX @@ void tcg_gen_deposit_z_i32(TCGv_i32 ret, TCGv_i32 arg, | ||
259 | tcg_gen_andi_i32(ret, arg, (1u << len) - 1); | ||
260 | } else if (TCG_TARGET_HAS_deposit_i32 | ||
261 | && TCG_TARGET_deposit_i32_valid(ofs, len)) { | ||
262 | - TCGv_i32 zero = tcg_const_i32(0); | ||
263 | + TCGv_i32 zero = tcg_constant_i32(0); | ||
264 | tcg_gen_op5ii_i32(INDEX_op_deposit_i32, ret, zero, arg, ofs, len); | ||
265 | - tcg_temp_free_i32(zero); | ||
266 | } else { | ||
267 | /* To help two-operand hosts we prefer to zero-extend first, | ||
268 | which allows ARG to stay live. */ | ||
269 | @@ -XXX,XX +XXX,XX @@ void tcg_gen_bswap32_i32(TCGv_i32 ret, TCGv_i32 arg) | ||
270 | } else { | ||
271 | TCGv_i32 t0 = tcg_temp_new_i32(); | ||
272 | TCGv_i32 t1 = tcg_temp_new_i32(); | ||
273 | - TCGv_i32 t2 = tcg_const_i32(0x00ff00ff); | ||
274 | + TCGv_i32 t2 = tcg_constant_i32(0x00ff00ff); | ||
275 | |||
276 | /* arg = abcd */ | ||
277 | tcg_gen_shri_i32(t0, arg, 8); /* t0 = .abc */ | ||
278 | @@ -XXX,XX +XXX,XX @@ void tcg_gen_bswap32_i32(TCGv_i32 ret, TCGv_i32 arg) | ||
279 | |||
280 | tcg_temp_free_i32(t0); | ||
281 | tcg_temp_free_i32(t1); | ||
282 | - tcg_temp_free_i32(t2); | ||
283 | } | ||
284 | } | ||
285 | |||
286 | @@ -XXX,XX +XXX,XX @@ void tcg_gen_discard_i64(TCGv_i64 arg) | ||
287 | |||
288 | void tcg_gen_mov_i64(TCGv_i64 ret, TCGv_i64 arg) | ||
289 | { | ||
290 | - tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg)); | ||
291 | - tcg_gen_mov_i32(TCGV_HIGH(ret), TCGV_HIGH(arg)); | ||
292 | + TCGTemp *ts = tcgv_i64_temp(arg); | ||
293 | + | ||
294 | + /* Canonicalize TCGv_i64 TEMP_CONST into TCGv_i32 TEMP_CONST. */ | ||
295 | + if (ts->kind == TEMP_CONST) { | ||
296 | + tcg_gen_movi_i64(ret, ts->val); | ||
297 | + } else { | ||
298 | + tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg)); | ||
299 | + tcg_gen_mov_i32(TCGV_HIGH(ret), TCGV_HIGH(arg)); | ||
300 | + } | ||
301 | } | ||
302 | |||
303 | void tcg_gen_movi_i64(TCGv_i64 ret, int64_t arg) | ||
304 | @@ -XXX,XX +XXX,XX @@ void tcg_gen_mul_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) | ||
305 | tcg_temp_free_i64(t0); | ||
306 | tcg_temp_free_i32(t1); | ||
307 | } | ||
308 | + | ||
309 | +#else | ||
310 | + | ||
311 | +void tcg_gen_movi_i64(TCGv_i64 ret, int64_t arg) | ||
312 | +{ | ||
313 | + tcg_gen_mov_i64(ret, tcg_constant_i64(arg)); | ||
314 | +} | ||
315 | + | ||
316 | #endif /* TCG_TARGET_REG_SIZE == 32 */ | ||
317 | |||
318 | void tcg_gen_addi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) | ||
319 | @@ -XXX,XX +XXX,XX @@ void tcg_gen_addi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) | ||
320 | /* some cases can be optimized here */ | ||
321 | if (arg2 == 0) { | ||
322 | tcg_gen_mov_i64(ret, arg1); | ||
323 | + } else if (TCG_TARGET_REG_BITS == 64) { | ||
324 | + tcg_gen_add_i64(ret, arg1, tcg_constant_i64(arg2)); | ||
325 | } else { | ||
326 | - TCGv_i64 t0 = tcg_const_i64(arg2); | ||
327 | - tcg_gen_add_i64(ret, arg1, t0); | ||
328 | - tcg_temp_free_i64(t0); | ||
329 | + tcg_gen_add2_i32(TCGV_LOW(ret), TCGV_HIGH(ret), | ||
330 | + TCGV_LOW(arg1), TCGV_HIGH(arg1), | ||
331 | + tcg_constant_i32(arg2), tcg_constant_i32(arg2 >> 32)); | ||
332 | } | ||
333 | } | ||
334 | |||
335 | @@ -XXX,XX +XXX,XX @@ void tcg_gen_subfi_i64(TCGv_i64 ret, int64_t arg1, TCGv_i64 arg2) | ||
336 | if (arg1 == 0 && TCG_TARGET_HAS_neg_i64) { | ||
337 | /* Don't recurse with tcg_gen_neg_i64. */ | ||
338 | tcg_gen_op2_i64(INDEX_op_neg_i64, ret, arg2); | ||
339 | + } else if (TCG_TARGET_REG_BITS == 64) { | ||
340 | + tcg_gen_sub_i64(ret, tcg_constant_i64(arg1), arg2); | ||
341 | } else { | ||
342 | - TCGv_i64 t0 = tcg_const_i64(arg1); | ||
343 | - tcg_gen_sub_i64(ret, t0, arg2); | ||
344 | - tcg_temp_free_i64(t0); | ||
345 | + tcg_gen_sub2_i32(TCGV_LOW(ret), TCGV_HIGH(ret), | ||
346 | + tcg_constant_i32(arg1), tcg_constant_i32(arg1 >> 32), | ||
347 | + TCGV_LOW(arg2), TCGV_HIGH(arg2)); | ||
348 | } | ||
349 | } | ||
350 | |||
351 | @@ -XXX,XX +XXX,XX @@ void tcg_gen_subi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) | ||
352 | /* some cases can be optimized here */ | ||
353 | if (arg2 == 0) { | ||
354 | tcg_gen_mov_i64(ret, arg1); | ||
355 | + } else if (TCG_TARGET_REG_BITS == 64) { | ||
356 | + tcg_gen_sub_i64(ret, arg1, tcg_constant_i64(arg2)); | ||
357 | } else { | ||
358 | - TCGv_i64 t0 = tcg_const_i64(arg2); | ||
359 | - tcg_gen_sub_i64(ret, arg1, t0); | ||
360 | - tcg_temp_free_i64(t0); | ||
361 | + tcg_gen_sub2_i32(TCGV_LOW(ret), TCGV_HIGH(ret), | ||
362 | + TCGV_LOW(arg1), TCGV_HIGH(arg1), | ||
363 | + tcg_constant_i32(arg2), tcg_constant_i32(arg2 >> 32)); | ||
364 | } | ||
365 | } | ||
366 | |||
367 | void tcg_gen_andi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) | ||
368 | { | ||
369 | - TCGv_i64 t0; | ||
370 | - | ||
371 | if (TCG_TARGET_REG_BITS == 32) { | ||
372 | tcg_gen_andi_i32(TCGV_LOW(ret), TCGV_LOW(arg1), arg2); | ||
373 | tcg_gen_andi_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32); | ||
374 | @@ -XXX,XX +XXX,XX @@ void tcg_gen_andi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) | ||
375 | } | ||
376 | break; | ||
377 | } | ||
378 | - t0 = tcg_const_i64(arg2); | ||
379 | - tcg_gen_and_i64(ret, arg1, t0); | ||
380 | - tcg_temp_free_i64(t0); | ||
381 | + | ||
382 | + tcg_gen_and_i64(ret, arg1, tcg_constant_i64(arg2)); | ||
383 | } | ||
384 | |||
385 | void tcg_gen_ori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) | ||
386 | @@ -XXX,XX +XXX,XX @@ void tcg_gen_ori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) | ||
387 | } else if (arg2 == 0) { | ||
388 | tcg_gen_mov_i64(ret, arg1); | ||
389 | } else { | ||
390 | - TCGv_i64 t0 = tcg_const_i64(arg2); | ||
391 | - tcg_gen_or_i64(ret, arg1, t0); | ||
392 | - tcg_temp_free_i64(t0); | ||
393 | + tcg_gen_or_i64(ret, arg1, tcg_constant_i64(arg2)); | ||
394 | } | ||
395 | } | ||
396 | |||
397 | @@ -XXX,XX +XXX,XX @@ void tcg_gen_xori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) | ||
398 | /* Don't recurse with tcg_gen_not_i64. */ | ||
399 | tcg_gen_op2_i64(INDEX_op_not_i64, ret, arg1); | ||
400 | } else { | ||
401 | - TCGv_i64 t0 = tcg_const_i64(arg2); | ||
402 | - tcg_gen_xor_i64(ret, arg1, t0); | ||
403 | - tcg_temp_free_i64(t0); | ||
404 | + tcg_gen_xor_i64(ret, arg1, tcg_constant_i64(arg2)); | ||
405 | } | ||
406 | } | ||
407 | |||
408 | @@ -XXX,XX +XXX,XX @@ void tcg_gen_shli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) | ||
409 | } else if (arg2 == 0) { | ||
410 | tcg_gen_mov_i64(ret, arg1); | ||
411 | } else { | ||
412 | - TCGv_i64 t0 = tcg_const_i64(arg2); | ||
413 | - tcg_gen_shl_i64(ret, arg1, t0); | ||
414 | - tcg_temp_free_i64(t0); | ||
415 | + tcg_gen_shl_i64(ret, arg1, tcg_constant_i64(arg2)); | ||
416 | } | ||
417 | } | ||
418 | |||
419 | @@ -XXX,XX +XXX,XX @@ void tcg_gen_shri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) | ||
420 | } else if (arg2 == 0) { | ||
421 | tcg_gen_mov_i64(ret, arg1); | ||
422 | } else { | ||
423 | - TCGv_i64 t0 = tcg_const_i64(arg2); | ||
424 | - tcg_gen_shr_i64(ret, arg1, t0); | ||
425 | - tcg_temp_free_i64(t0); | ||
426 | + tcg_gen_shr_i64(ret, arg1, tcg_constant_i64(arg2)); | ||
427 | } | ||
428 | } | ||
429 | |||
430 | @@ -XXX,XX +XXX,XX @@ void tcg_gen_sari_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) | ||
431 | } else if (arg2 == 0) { | ||
432 | tcg_gen_mov_i64(ret, arg1); | ||
433 | } else { | ||
434 | - TCGv_i64 t0 = tcg_const_i64(arg2); | ||
435 | - tcg_gen_sar_i64(ret, arg1, t0); | ||
436 | - tcg_temp_free_i64(t0); | ||
437 | + tcg_gen_sar_i64(ret, arg1, tcg_constant_i64(arg2)); | ||
438 | } | ||
439 | } | ||
440 | |||
441 | @@ -XXX,XX +XXX,XX @@ void tcg_gen_brcond_i64(TCGCond cond, TCGv_i64 arg1, TCGv_i64 arg2, TCGLabel *l) | ||
442 | |||
443 | void tcg_gen_brcondi_i64(TCGCond cond, TCGv_i64 arg1, int64_t arg2, TCGLabel *l) | ||
444 | { | ||
445 | - if (cond == TCG_COND_ALWAYS) { | ||
446 | + if (TCG_TARGET_REG_BITS == 64) { | ||
447 | + tcg_gen_brcond_i64(cond, arg1, tcg_constant_i64(arg2), l); | ||
448 | + } else if (cond == TCG_COND_ALWAYS) { | ||
449 | tcg_gen_br(l); | ||
450 | } else if (cond != TCG_COND_NEVER) { | ||
451 | - TCGv_i64 t0 = tcg_const_i64(arg2); | ||
452 | - tcg_gen_brcond_i64(cond, arg1, t0, l); | ||
453 | - tcg_temp_free_i64(t0); | ||
454 | + l->refs++; | ||
455 | + tcg_gen_op6ii_i32(INDEX_op_brcond2_i32, | ||
456 | + TCGV_LOW(arg1), TCGV_HIGH(arg1), | ||
457 | + tcg_constant_i32(arg2), | ||
458 | + tcg_constant_i32(arg2 >> 32), | ||
459 | + cond, label_arg(l)); | ||
460 | } | ||
461 | } | ||
462 | |||
463 | @@ -XXX,XX +XXX,XX @@ void tcg_gen_setcond_i64(TCGCond cond, TCGv_i64 ret, | ||
464 | void tcg_gen_setcondi_i64(TCGCond cond, TCGv_i64 ret, | ||
465 | TCGv_i64 arg1, int64_t arg2) | ||
466 | { | ||
467 | - TCGv_i64 t0 = tcg_const_i64(arg2); | ||
468 | - tcg_gen_setcond_i64(cond, ret, arg1, t0); | ||
469 | - tcg_temp_free_i64(t0); | ||
470 | + if (TCG_TARGET_REG_BITS == 64) { | ||
471 | + tcg_gen_setcond_i64(cond, ret, arg1, tcg_constant_i64(arg2)); | ||
472 | + } else if (cond == TCG_COND_ALWAYS) { | ||
473 | + tcg_gen_movi_i64(ret, 1); | ||
474 | + } else if (cond == TCG_COND_NEVER) { | ||
475 | + tcg_gen_movi_i64(ret, 0); | ||
476 | + } else { | ||
477 | + tcg_gen_op6i_i32(INDEX_op_setcond2_i32, TCGV_LOW(ret), | ||
478 | + TCGV_LOW(arg1), TCGV_HIGH(arg1), | ||
479 | + tcg_constant_i32(arg2), | ||
480 | + tcg_constant_i32(arg2 >> 32), cond); | ||
481 | + tcg_gen_movi_i32(TCGV_HIGH(ret), 0); | ||
482 | + } | ||
483 | } | ||
484 | |||
485 | void tcg_gen_muli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) | ||
486 | @@ -XXX,XX +XXX,XX @@ void tcg_gen_bswap32_i64(TCGv_i64 ret, TCGv_i64 arg) | ||
487 | } else { | ||
488 | TCGv_i64 t0 = tcg_temp_new_i64(); | ||
489 | TCGv_i64 t1 = tcg_temp_new_i64(); | ||
490 | - TCGv_i64 t2 = tcg_const_i64(0x00ff00ff); | ||
491 | + TCGv_i64 t2 = tcg_constant_i64(0x00ff00ff); | ||
492 | |||
493 | /* arg = ....abcd */ | ||
494 | tcg_gen_shri_i64(t0, arg, 8); /* t0 = .....abc */ | ||
495 | @@ -XXX,XX +XXX,XX @@ void tcg_gen_bswap32_i64(TCGv_i64 ret, TCGv_i64 arg) | ||
496 | |||
497 | tcg_temp_free_i64(t0); | ||
498 | tcg_temp_free_i64(t1); | ||
499 | - tcg_temp_free_i64(t2); | ||
500 | } | ||
501 | } | ||
502 | |||
503 | @@ -XXX,XX +XXX,XX @@ void tcg_gen_clzi_i64(TCGv_i64 ret, TCGv_i64 arg1, uint64_t arg2) | ||
504 | if (TCG_TARGET_REG_BITS == 32 | ||
505 | && TCG_TARGET_HAS_clz_i32 | ||
506 | && arg2 <= 0xffffffffu) { | ||
507 | - TCGv_i32 t = tcg_const_i32((uint32_t)arg2 - 32); | ||
508 | - tcg_gen_clz_i32(t, TCGV_LOW(arg1), t); | ||
509 | + TCGv_i32 t = tcg_temp_new_i32(); | ||
510 | + tcg_gen_clzi_i32(t, TCGV_LOW(arg1), arg2 - 32); | ||
511 | tcg_gen_addi_i32(t, t, 32); | ||
512 | tcg_gen_clz_i32(TCGV_LOW(ret), TCGV_HIGH(arg1), t); | ||
513 | tcg_gen_movi_i32(TCGV_HIGH(ret), 0); | ||
514 | tcg_temp_free_i32(t); | ||
515 | } else { | ||
516 | - TCGv_i64 t = tcg_const_i64(arg2); | ||
517 | - tcg_gen_clz_i64(ret, arg1, t); | ||
518 | - tcg_temp_free_i64(t); | ||
519 | + TCGv_i64 t0 = tcg_const_i64(arg2); | ||
520 | + tcg_gen_clz_i64(ret, arg1, t0); | ||
521 | + tcg_temp_free_i64(t0); | ||
522 | } | ||
523 | } | ||
524 | |||
525 | @@ -XXX,XX +XXX,XX @@ void tcg_gen_ctz_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) | ||
526 | tcg_gen_clzi_i64(t, t, 64); | ||
527 | tcg_gen_xori_i64(t, t, 63); | ||
528 | } | ||
529 | - z = tcg_const_i64(0); | ||
530 | + z = tcg_constant_i64(0); | ||
531 | tcg_gen_movcond_i64(TCG_COND_EQ, ret, arg1, z, arg2, t); | ||
532 | tcg_temp_free_i64(t); | ||
533 | tcg_temp_free_i64(z); | ||
534 | @@ -XXX,XX +XXX,XX @@ void tcg_gen_ctzi_i64(TCGv_i64 ret, TCGv_i64 arg1, uint64_t arg2) | ||
535 | if (TCG_TARGET_REG_BITS == 32 | ||
536 | && TCG_TARGET_HAS_ctz_i32 | ||
537 | && arg2 <= 0xffffffffu) { | ||
538 | - TCGv_i32 t32 = tcg_const_i32((uint32_t)arg2 - 32); | ||
539 | - tcg_gen_ctz_i32(t32, TCGV_HIGH(arg1), t32); | ||
540 | + TCGv_i32 t32 = tcg_temp_new_i32(); | ||
541 | + tcg_gen_ctzi_i32(t32, TCGV_HIGH(arg1), arg2 - 32); | ||
542 | tcg_gen_addi_i32(t32, t32, 32); | ||
543 | tcg_gen_ctz_i32(TCGV_LOW(ret), TCGV_LOW(arg1), t32); | ||
544 | tcg_gen_movi_i32(TCGV_HIGH(ret), 0); | ||
545 | @@ -XXX,XX +XXX,XX @@ void tcg_gen_ctzi_i64(TCGv_i64 ret, TCGv_i64 arg1, uint64_t arg2) | ||
546 | tcg_gen_ctpop_i64(ret, t); | ||
547 | tcg_temp_free_i64(t); | ||
548 | } else { | ||
549 | - TCGv_i64 t64 = tcg_const_i64(arg2); | ||
550 | - tcg_gen_ctz_i64(ret, arg1, t64); | ||
551 | - tcg_temp_free_i64(t64); | ||
552 | + TCGv_i64 t0 = tcg_const_i64(arg2); | ||
553 | + tcg_gen_ctz_i64(ret, arg1, t0); | ||
554 | + tcg_temp_free_i64(t0); | ||
555 | } | ||
556 | } | ||
557 | |||
558 | @@ -XXX,XX +XXX,XX @@ void tcg_gen_rotli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) | ||
559 | if (arg2 == 0) { | ||
560 | tcg_gen_mov_i64(ret, arg1); | ||
561 | } else if (TCG_TARGET_HAS_rot_i64) { | ||
562 | - TCGv_i64 t0 = tcg_const_i64(arg2); | ||
563 | - tcg_gen_rotl_i64(ret, arg1, t0); | ||
564 | - tcg_temp_free_i64(t0); | ||
565 | + tcg_gen_rotl_i64(ret, arg1, tcg_constant_i64(arg2)); | ||
566 | } else { | ||
567 | TCGv_i64 t0, t1; | ||
568 | t0 = tcg_temp_new_i64(); | ||
569 | @@ -XXX,XX +XXX,XX @@ void tcg_gen_deposit_z_i64(TCGv_i64 ret, TCGv_i64 arg, | ||
570 | tcg_gen_andi_i64(ret, arg, (1ull << len) - 1); | ||
571 | } else if (TCG_TARGET_HAS_deposit_i64 | ||
572 | && TCG_TARGET_deposit_i64_valid(ofs, len)) { | ||
573 | - TCGv_i64 zero = tcg_const_i64(0); | ||
574 | + TCGv_i64 zero = tcg_constant_i64(0); | ||
575 | tcg_gen_op5ii_i64(INDEX_op_deposit_i64, ret, zero, arg, ofs, len); | ||
576 | - tcg_temp_free_i64(zero); | ||
577 | } else { | ||
578 | if (TCG_TARGET_REG_BITS == 32) { | ||
579 | if (ofs >= 32) { | ||
580 | @@ -XXX,XX +XXX,XX @@ void tcg_gen_atomic_cmpxchg_i32(TCGv_i32 retv, TCGv addr, TCGv_i32 cmpv, | ||
581 | |||
582 | #ifdef CONFIG_SOFTMMU | ||
583 | { | ||
584 | - TCGv_i32 oi = tcg_const_i32(make_memop_idx(memop & ~MO_SIGN, idx)); | ||
585 | - gen(retv, cpu_env, addr, cmpv, newv, oi); | ||
586 | - tcg_temp_free_i32(oi); | ||
587 | + TCGMemOpIdx oi = make_memop_idx(memop & ~MO_SIGN, idx); | ||
588 | + gen(retv, cpu_env, addr, cmpv, newv, tcg_constant_i32(oi)); | ||
589 | } | ||
590 | #else | ||
591 | gen(retv, cpu_env, addr, cmpv, newv); | ||
592 | @@ -XXX,XX +XXX,XX @@ void tcg_gen_atomic_cmpxchg_i64(TCGv_i64 retv, TCGv addr, TCGv_i64 cmpv, | ||
593 | |||
594 | #ifdef CONFIG_SOFTMMU | ||
595 | { | ||
596 | - TCGv_i32 oi = tcg_const_i32(make_memop_idx(memop, idx)); | ||
597 | - gen(retv, cpu_env, addr, cmpv, newv, oi); | ||
598 | - tcg_temp_free_i32(oi); | ||
599 | + TCGMemOpIdx oi = make_memop_idx(memop, idx); | ||
600 | + gen(retv, cpu_env, addr, cmpv, newv, tcg_constant_i32(oi)); | ||
601 | } | ||
602 | #else | ||
603 | gen(retv, cpu_env, addr, cmpv, newv); | ||
604 | @@ -XXX,XX +XXX,XX @@ static void do_atomic_op_i32(TCGv_i32 ret, TCGv addr, TCGv_i32 val, | ||
605 | |||
606 | #ifdef CONFIG_SOFTMMU | ||
607 | { | ||
608 | - TCGv_i32 oi = tcg_const_i32(make_memop_idx(memop & ~MO_SIGN, idx)); | ||
609 | - gen(ret, cpu_env, addr, val, oi); | ||
610 | - tcg_temp_free_i32(oi); | ||
611 | + TCGMemOpIdx oi = make_memop_idx(memop & ~MO_SIGN, idx); | ||
612 | + gen(ret, cpu_env, addr, val, tcg_constant_i32(oi)); | ||
613 | } | ||
614 | #else | ||
615 | gen(ret, cpu_env, addr, val); | ||
616 | @@ -XXX,XX +XXX,XX @@ static void do_atomic_op_i64(TCGv_i64 ret, TCGv addr, TCGv_i64 val, | ||
617 | |||
618 | #ifdef CONFIG_SOFTMMU | ||
619 | { | ||
620 | - TCGv_i32 oi = tcg_const_i32(make_memop_idx(memop & ~MO_SIGN, idx)); | ||
621 | - gen(ret, cpu_env, addr, val, oi); | ||
622 | - tcg_temp_free_i32(oi); | ||
623 | + TCGMemOpIdx oi = make_memop_idx(memop & ~MO_SIGN, idx); | ||
624 | + gen(ret, cpu_env, addr, val, tcg_constant_i32(oi)); | ||
625 | } | ||
626 | #else | ||
627 | gen(ret, cpu_env, addr, val); | ||
628 | -- | 149 | -- |
629 | 2.25.1 | 150 | 2.43.0 |
630 | |||
631 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | The function is now unused. | ||
1 | 2 | ||
3 | Reviewed-by: Brian Cain <brian.cain@oss.qualcomm.com> | ||
4 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
5 | --- | ||
6 | target/hexagon/fma_emu.h | 2 - | ||
7 | target/hexagon/fma_emu.c | 171 --------------------------------------- | ||
8 | 2 files changed, 173 deletions(-) | ||
9 | |||
10 | diff --git a/target/hexagon/fma_emu.h b/target/hexagon/fma_emu.h | ||
11 | index XXXXXXX..XXXXXXX 100644 | ||
12 | --- a/target/hexagon/fma_emu.h | ||
13 | +++ b/target/hexagon/fma_emu.h | ||
14 | @@ -XXX,XX +XXX,XX @@ static inline uint32_t float32_getexp_raw(float32 f32) | ||
15 | } | ||
16 | int32_t float32_getexp(float32 f32); | ||
17 | float32 infinite_float32(uint8_t sign); | ||
18 | -float32 internal_fmafx(float32 a, float32 b, float32 c, | ||
19 | - int scale, float_status *fp_status); | ||
20 | float64 internal_mpyhh(float64 a, float64 b, | ||
21 | unsigned long long int accumulated, | ||
22 | float_status *fp_status); | ||
23 | diff --git a/target/hexagon/fma_emu.c b/target/hexagon/fma_emu.c | ||
24 | index XXXXXXX..XXXXXXX 100644 | ||
25 | --- a/target/hexagon/fma_emu.c | ||
26 | +++ b/target/hexagon/fma_emu.c | ||
27 | @@ -XXX,XX +XXX,XX @@ int32_t float64_getexp(float64 f64) | ||
28 | return -1; | ||
29 | } | ||
30 | |||
31 | -static uint64_t float32_getmant(float32 f32) | ||
32 | -{ | ||
33 | - Float a = { .i = f32 }; | ||
34 | - if (float32_is_normal(f32)) { | ||
35 | - return a.mant | 1ULL << 23; | ||
36 | - } | ||
37 | - if (float32_is_zero(f32)) { | ||
38 | - return 0; | ||
39 | - } | ||
40 | - if (float32_is_denormal(f32)) { | ||
41 | - return a.mant; | ||
42 | - } | ||
43 | - return ~0ULL; | ||
44 | -} | ||
45 | - | ||
46 | int32_t float32_getexp(float32 f32) | ||
47 | { | ||
48 | Float a = { .i = f32 }; | ||
49 | @@ -XXX,XX +XXX,XX @@ float32 infinite_float32(uint8_t sign) | ||
50 | } | ||
51 | |||
52 | /* Return a maximum finite value with the requested sign */ | ||
53 | -static float32 maxfinite_float32(uint8_t sign) | ||
54 | -{ | ||
55 | - if (sign) { | ||
56 | - return make_float32(SF_MINUS_MAXF); | ||
57 | - } else { | ||
58 | - return make_float32(SF_MAXF); | ||
59 | - } | ||
60 | -} | ||
61 | - | ||
62 | -/* Return a zero value with requested sign */ | ||
63 | -static float32 zero_float32(uint8_t sign) | ||
64 | -{ | ||
65 | - if (sign) { | ||
66 | - return make_float32(0x80000000); | ||
67 | - } else { | ||
68 | - return float32_zero; | ||
69 | - } | ||
70 | -} | ||
71 | - | ||
72 | #define GEN_XF_ROUND(SUFFIX, MANTBITS, INF_EXP, INTERNAL_TYPE) \ | ||
73 | static SUFFIX accum_round_##SUFFIX(Accum a, float_status * fp_status) \ | ||
74 | { \ | ||
75 | @@ -XXX,XX +XXX,XX @@ static SUFFIX accum_round_##SUFFIX(Accum a, float_status * fp_status) \ | ||
76 | } | ||
77 | |||
78 | GEN_XF_ROUND(float64, DF_MANTBITS, DF_INF_EXP, Double) | ||
79 | -GEN_XF_ROUND(float32, SF_MANTBITS, SF_INF_EXP, Float) | ||
80 | - | ||
81 | -static bool is_inf_prod(float64 a, float64 b) | ||
82 | -{ | ||
83 | - return ((float64_is_infinity(a) && float64_is_infinity(b)) || | ||
84 | - (float64_is_infinity(a) && is_finite(b) && (!float64_is_zero(b))) || | ||
85 | - (float64_is_infinity(b) && is_finite(a) && (!float64_is_zero(a)))); | ||
86 | -} | ||
87 | - | ||
88 | -static float64 special_fma(float64 a, float64 b, float64 c, | ||
89 | - float_status *fp_status) | ||
90 | -{ | ||
91 | - float64 ret = make_float64(0); | ||
92 | - | ||
93 | - /* | ||
94 | - * If A multiplied by B is an exact infinity and C is also an infinity | ||
95 | - * but with the opposite sign, FMA returns NaN and raises invalid. | ||
96 | - */ | ||
97 | - uint8_t a_sign = float64_is_neg(a); | ||
98 | - uint8_t b_sign = float64_is_neg(b); | ||
99 | - uint8_t c_sign = float64_is_neg(c); | ||
100 | - if (is_inf_prod(a, b) && float64_is_infinity(c)) { | ||
101 | - if ((a_sign ^ b_sign) != c_sign) { | ||
102 | - ret = make_float64(DF_NAN); | ||
103 | - float_raise(float_flag_invalid, fp_status); | ||
104 | - return ret; | ||
105 | - } | ||
106 | - } | ||
107 | - if ((float64_is_infinity(a) && float64_is_zero(b)) || | ||
108 | - (float64_is_zero(a) && float64_is_infinity(b))) { | ||
109 | - ret = make_float64(DF_NAN); | ||
110 | - float_raise(float_flag_invalid, fp_status); | ||
111 | - return ret; | ||
112 | - } | ||
113 | - /* | ||
114 | - * If none of the above checks are true and C is a NaN, | ||
115 | - * a NaN shall be returned | ||
116 | - * If A or B are NaN, a NAN shall be returned. | ||
117 | - */ | ||
118 | - if (float64_is_any_nan(a) || | ||
119 | - float64_is_any_nan(b) || | ||
120 | - float64_is_any_nan(c)) { | ||
121 | - if (float64_is_any_nan(a) && (fGETBIT(51, a) == 0)) { | ||
122 | - float_raise(float_flag_invalid, fp_status); | ||
123 | - } | ||
124 | - if (float64_is_any_nan(b) && (fGETBIT(51, b) == 0)) { | ||
125 | - float_raise(float_flag_invalid, fp_status); | ||
126 | - } | ||
127 | - if (float64_is_any_nan(c) && (fGETBIT(51, c) == 0)) { | ||
128 | - float_raise(float_flag_invalid, fp_status); | ||
129 | - } | ||
130 | - ret = make_float64(DF_NAN); | ||
131 | - return ret; | ||
132 | - } | ||
133 | - /* | ||
134 | - * We have checked for adding opposite-signed infinities. | ||
135 | - * Other infinities return infinity with the correct sign | ||
136 | - */ | ||
137 | - if (float64_is_infinity(c)) { | ||
138 | - ret = infinite_float64(c_sign); | ||
139 | - return ret; | ||
140 | - } | ||
141 | - if (float64_is_infinity(a) || float64_is_infinity(b)) { | ||
142 | - ret = infinite_float64(a_sign ^ b_sign); | ||
143 | - return ret; | ||
144 | - } | ||
145 | - g_assert_not_reached(); | ||
146 | -} | ||
147 | - | ||
148 | -static float32 special_fmaf(float32 a, float32 b, float32 c, | ||
149 | - float_status *fp_status) | ||
150 | -{ | ||
151 | - float64 aa, bb, cc; | ||
152 | - aa = float32_to_float64(a, fp_status); | ||
153 | - bb = float32_to_float64(b, fp_status); | ||
154 | - cc = float32_to_float64(c, fp_status); | ||
155 | - return float64_to_float32(special_fma(aa, bb, cc, fp_status), fp_status); | ||
156 | -} | ||
157 | - | ||
158 | -float32 internal_fmafx(float32 a, float32 b, float32 c, int scale, | ||
159 | - float_status *fp_status) | ||
160 | -{ | ||
161 | - Accum prod; | ||
162 | - Accum acc; | ||
163 | - Accum result; | ||
164 | - accum_init(&prod); | ||
165 | - accum_init(&acc); | ||
166 | - accum_init(&result); | ||
167 | - | ||
168 | - uint8_t a_sign = float32_is_neg(a); | ||
169 | - uint8_t b_sign = float32_is_neg(b); | ||
170 | - uint8_t c_sign = float32_is_neg(c); | ||
171 | - if (float32_is_infinity(a) || | ||
172 | - float32_is_infinity(b) || | ||
173 | - float32_is_infinity(c)) { | ||
174 | - return special_fmaf(a, b, c, fp_status); | ||
175 | - } | ||
176 | - if (float32_is_any_nan(a) || | ||
177 | - float32_is_any_nan(b) || | ||
178 | - float32_is_any_nan(c)) { | ||
179 | - return special_fmaf(a, b, c, fp_status); | ||
180 | - } | ||
181 | - if ((scale == 0) && (float32_is_zero(a) || float32_is_zero(b))) { | ||
182 | - float32 tmp = float32_mul(a, b, fp_status); | ||
183 | - tmp = float32_add(tmp, c, fp_status); | ||
184 | - return tmp; | ||
185 | - } | ||
186 | - | ||
187 | - /* (a * 2**b) * (c * 2**d) == a*c * 2**(b+d) */ | ||
188 | - prod.mant = int128_mul_6464(float32_getmant(a), float32_getmant(b)); | ||
189 | - | ||
190 | - /* | ||
191 | - * Note: extracting the mantissa into an int is multiplying by | ||
192 | - * 2**23, so adjust here | ||
193 | - */ | ||
194 | - prod.exp = float32_getexp(a) + float32_getexp(b) - SF_BIAS - 23; | ||
195 | - prod.sign = a_sign ^ b_sign; | ||
196 | - if (float32_is_zero(a) || float32_is_zero(b)) { | ||
197 | - prod.exp = -2 * WAY_BIG_EXP; | ||
198 | - } | ||
199 | - if ((scale > 0) && float32_is_denormal(c)) { | ||
200 | - acc.mant = int128_mul_6464(0, 0); | ||
201 | - acc.exp = -WAY_BIG_EXP; | ||
202 | - acc.sign = c_sign; | ||
203 | - acc.sticky = 1; | ||
204 | - result = accum_add(prod, acc); | ||
205 | - } else if (!float32_is_zero(c)) { | ||
206 | - acc.mant = int128_mul_6464(float32_getmant(c), 1); | ||
207 | - acc.exp = float32_getexp(c); | ||
208 | - acc.sign = c_sign; | ||
209 | - result = accum_add(prod, acc); | ||
210 | - } else { | ||
211 | - result = prod; | ||
212 | - } | ||
213 | - result.exp += scale; | ||
214 | - return accum_round_float32(result, fp_status); | ||
215 | -} | ||
216 | |||
217 | float64 internal_mpyhh(float64 a, float64 b, | ||
218 | unsigned long long int accumulated, | ||
219 | -- | ||
220 | 2.43.0 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | This massive macro is now only used once. | ||
2 | Expand it for use only by float64. | ||
1 | 3 | ||
4 | Reviewed-by: Brian Cain <brian.cain@oss.qualcomm.com> | ||
5 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
6 | --- | ||
7 | target/hexagon/fma_emu.c | 255 +++++++++++++++++++-------------------- | ||
8 | 1 file changed, 127 insertions(+), 128 deletions(-) | ||
9 | |||
10 | diff --git a/target/hexagon/fma_emu.c b/target/hexagon/fma_emu.c | ||
11 | index XXXXXXX..XXXXXXX 100644 | ||
12 | --- a/target/hexagon/fma_emu.c | ||
13 | +++ b/target/hexagon/fma_emu.c | ||
14 | @@ -XXX,XX +XXX,XX @@ float32 infinite_float32(uint8_t sign) | ||
15 | } | ||
16 | |||
17 | /* Return a maximum finite value with the requested sign */ | ||
18 | -#define GEN_XF_ROUND(SUFFIX, MANTBITS, INF_EXP, INTERNAL_TYPE) \ | ||
19 | -static SUFFIX accum_round_##SUFFIX(Accum a, float_status * fp_status) \ | ||
20 | -{ \ | ||
21 | - if ((int128_gethi(a.mant) == 0) && (int128_getlo(a.mant) == 0) \ | ||
22 | - && ((a.guard | a.round | a.sticky) == 0)) { \ | ||
23 | - /* result zero */ \ | ||
24 | - switch (fp_status->float_rounding_mode) { \ | ||
25 | - case float_round_down: \ | ||
26 | - return zero_##SUFFIX(1); \ | ||
27 | - default: \ | ||
28 | - return zero_##SUFFIX(0); \ | ||
29 | - } \ | ||
30 | - } \ | ||
31 | - /* Normalize right */ \ | ||
32 | - /* We want MANTBITS bits of mantissa plus the leading one. */ \ | ||
33 | - /* That means that we want MANTBITS+1 bits, or 0x000000000000FF_FFFF */ \ | ||
34 | - /* So we need to normalize right while the high word is non-zero and \ | ||
35 | - * while the low word is nonzero when masked with 0xffe0_0000_0000_0000 */ \ | ||
36 | - while ((int128_gethi(a.mant) != 0) || \ | ||
37 | - ((int128_getlo(a.mant) >> (MANTBITS + 1)) != 0)) { \ | ||
38 | - a = accum_norm_right(a, 1); \ | ||
39 | - } \ | ||
40 | - /* \ | ||
41 | - * OK, now normalize left \ | ||
42 | - * We want to normalize left until we have a leading one in bit 24 \ | ||
43 | - * Theoretically, we only need to shift a maximum of one to the left if we \ | ||
44 | - * shifted out lots of bits from B, or if we had no shift / 1 shift sticky \ | ||
45 | - * should be 0 \ | ||
46 | - */ \ | ||
47 | - while ((int128_getlo(a.mant) & (1ULL << MANTBITS)) == 0) { \ | ||
48 | - a = accum_norm_left(a); \ | ||
49 | - } \ | ||
50 | - /* \ | ||
51 | - * OK, now we might need to denormalize because of potential underflow. \ | ||
52 | - * We need to do this before rounding, and rounding might make us normal \ | ||
53 | - * again \ | ||
54 | - */ \ | ||
55 | - while (a.exp <= 0) { \ | ||
56 | - a = accum_norm_right(a, 1 - a.exp); \ | ||
57 | - /* \ | ||
58 | - * Do we have underflow? \ | ||
59 | - * That's when we get an inexact answer because we ran out of bits \ | ||
60 | - * in a denormal. \ | ||
61 | - */ \ | ||
62 | - if (a.guard || a.round || a.sticky) { \ | ||
63 | - float_raise(float_flag_underflow, fp_status); \ | ||
64 | - } \ | ||
65 | - } \ | ||
66 | - /* OK, we're relatively canonical... now we need to round */ \ | ||
67 | - if (a.guard || a.round || a.sticky) { \ | ||
68 | - float_raise(float_flag_inexact, fp_status); \ | ||
69 | - switch (fp_status->float_rounding_mode) { \ | ||
70 | - case float_round_to_zero: \ | ||
71 | - /* Chop and we're done */ \ | ||
72 | - break; \ | ||
73 | - case float_round_up: \ | ||
74 | - if (a.sign == 0) { \ | ||
75 | - a.mant = int128_add(a.mant, int128_one()); \ | ||
76 | - } \ | ||
77 | - break; \ | ||
78 | - case float_round_down: \ | ||
79 | - if (a.sign != 0) { \ | ||
80 | - a.mant = int128_add(a.mant, int128_one()); \ | ||
81 | - } \ | ||
82 | - break; \ | ||
83 | - default: \ | ||
84 | - if (a.round || a.sticky) { \ | ||
85 | - /* round up if guard is 1, down if guard is zero */ \ | ||
86 | - a.mant = int128_add(a.mant, int128_make64(a.guard)); \ | ||
87 | - } else if (a.guard) { \ | ||
88 | - /* exactly .5, round up if odd */ \ | ||
89 | - a.mant = int128_add(a.mant, int128_and(a.mant, int128_one())); \ | ||
90 | - } \ | ||
91 | - break; \ | ||
92 | - } \ | ||
93 | - } \ | ||
94 | - /* \ | ||
95 | - * OK, now we might have carried all the way up. \ | ||
96 | - * So we might need to shr once \ | ||
97 | - * at least we know that the lsb should be zero if we rounded and \ | ||
98 | - * got a carry out... \ | ||
99 | - */ \ | ||
100 | - if ((int128_getlo(a.mant) >> (MANTBITS + 1)) != 0) { \ | ||
101 | - a = accum_norm_right(a, 1); \ | ||
102 | - } \ | ||
103 | - /* Overflow? */ \ | ||
104 | - if (a.exp >= INF_EXP) { \ | ||
105 | - /* Yep, inf result */ \ | ||
106 | - float_raise(float_flag_overflow, fp_status); \ | ||
107 | - float_raise(float_flag_inexact, fp_status); \ | ||
108 | - switch (fp_status->float_rounding_mode) { \ | ||
109 | - case float_round_to_zero: \ | ||
110 | - return maxfinite_##SUFFIX(a.sign); \ | ||
111 | - case float_round_up: \ | ||
112 | - if (a.sign == 0) { \ | ||
113 | - return infinite_##SUFFIX(a.sign); \ | ||
114 | - } else { \ | ||
115 | - return maxfinite_##SUFFIX(a.sign); \ | ||
116 | - } \ | ||
117 | - case float_round_down: \ | ||
118 | - if (a.sign != 0) { \ | ||
119 | - return infinite_##SUFFIX(a.sign); \ | ||
120 | - } else { \ | ||
121 | - return maxfinite_##SUFFIX(a.sign); \ | ||
122 | - } \ | ||
123 | - default: \ | ||
124 | - return infinite_##SUFFIX(a.sign); \ | ||
125 | - } \ | ||
126 | - } \ | ||
127 | - /* Underflow? */ \ | ||
128 | - if (int128_getlo(a.mant) & (1ULL << MANTBITS)) { \ | ||
129 | - /* Leading one means: No, we're normal. So, we should be done... */ \ | ||
130 | - INTERNAL_TYPE ret; \ | ||
131 | - ret.i = 0; \ | ||
132 | - ret.sign = a.sign; \ | ||
133 | - ret.exp = a.exp; \ | ||
134 | - ret.mant = int128_getlo(a.mant); \ | ||
135 | - return ret.i; \ | ||
136 | - } \ | ||
137 | - assert(a.exp == 1); \ | ||
138 | - INTERNAL_TYPE ret; \ | ||
139 | - ret.i = 0; \ | ||
140 | - ret.sign = a.sign; \ | ||
141 | - ret.exp = 0; \ | ||
142 | - ret.mant = int128_getlo(a.mant); \ | ||
143 | - return ret.i; \ | ||
144 | +static float64 accum_round_float64(Accum a, float_status *fp_status) | ||
145 | +{ | ||
146 | + if ((int128_gethi(a.mant) == 0) && (int128_getlo(a.mant) == 0) | ||
147 | + && ((a.guard | a.round | a.sticky) == 0)) { | ||
148 | + /* result zero */ | ||
149 | + switch (fp_status->float_rounding_mode) { | ||
150 | + case float_round_down: | ||
151 | + return zero_float64(1); | ||
152 | + default: | ||
153 | + return zero_float64(0); | ||
154 | + } | ||
155 | + } | ||
156 | + /* | ||
157 | + * Normalize right | ||
158 | + * We want DF_MANTBITS bits of mantissa plus the leading one. | ||
159 | + * That means that we want DF_MANTBITS+1 bits, or 0x000000000000FF_FFFF | ||
160 | + * So we need to normalize right while the high word is non-zero and | ||
161 | + * while the low word is nonzero when masked with 0xffe0_0000_0000_0000 | ||
162 | + */ | ||
163 | + while ((int128_gethi(a.mant) != 0) || | ||
164 | + ((int128_getlo(a.mant) >> (DF_MANTBITS + 1)) != 0)) { | ||
165 | + a = accum_norm_right(a, 1); | ||
166 | + } | ||
167 | + /* | ||
168 | + * OK, now normalize left | ||
169 | + * We want to normalize left until we have a leading one in bit 24 | ||
170 | + * Theoretically, we only need to shift a maximum of one to the left if we | ||
171 | + * shifted out lots of bits from B, or if we had no shift / 1 shift sticky | ||
172 | + * should be 0 | ||
173 | + */ | ||
174 | + while ((int128_getlo(a.mant) & (1ULL << DF_MANTBITS)) == 0) { | ||
175 | + a = accum_norm_left(a); | ||
176 | + } | ||
177 | + /* | ||
178 | + * OK, now we might need to denormalize because of potential underflow. | ||
179 | + * We need to do this before rounding, and rounding might make us normal | ||
180 | + * again | ||
181 | + */ | ||
182 | + while (a.exp <= 0) { | ||
183 | + a = accum_norm_right(a, 1 - a.exp); | ||
184 | + /* | ||
185 | + * Do we have underflow? | ||
186 | + * That's when we get an inexact answer because we ran out of bits | ||
187 | + * in a denormal. | ||
188 | + */ | ||
189 | + if (a.guard || a.round || a.sticky) { | ||
190 | + float_raise(float_flag_underflow, fp_status); | ||
191 | + } | ||
192 | + } | ||
193 | + /* OK, we're relatively canonical... now we need to round */ | ||
194 | + if (a.guard || a.round || a.sticky) { | ||
195 | + float_raise(float_flag_inexact, fp_status); | ||
196 | + switch (fp_status->float_rounding_mode) { | ||
197 | + case float_round_to_zero: | ||
198 | + /* Chop and we're done */ | ||
199 | + break; | ||
200 | + case float_round_up: | ||
201 | + if (a.sign == 0) { | ||
202 | + a.mant = int128_add(a.mant, int128_one()); | ||
203 | + } | ||
204 | + break; | ||
205 | + case float_round_down: | ||
206 | + if (a.sign != 0) { | ||
207 | + a.mant = int128_add(a.mant, int128_one()); | ||
208 | + } | ||
209 | + break; | ||
210 | + default: | ||
211 | + if (a.round || a.sticky) { | ||
212 | + /* round up if guard is 1, down if guard is zero */ | ||
213 | + a.mant = int128_add(a.mant, int128_make64(a.guard)); | ||
214 | + } else if (a.guard) { | ||
215 | + /* exactly .5, round up if odd */ | ||
216 | + a.mant = int128_add(a.mant, int128_and(a.mant, int128_one())); | ||
217 | + } | ||
218 | + break; | ||
219 | + } | ||
220 | + } | ||
221 | + /* | ||
222 | + * OK, now we might have carried all the way up. | ||
223 | + * So we might need to shr once | ||
224 | + * at least we know that the lsb should be zero if we rounded and | ||
225 | + * got a carry out... | ||
226 | + */ | ||
227 | + if ((int128_getlo(a.mant) >> (DF_MANTBITS + 1)) != 0) { | ||
228 | + a = accum_norm_right(a, 1); | ||
229 | + } | ||
230 | + /* Overflow? */ | ||
231 | + if (a.exp >= DF_INF_EXP) { | ||
232 | + /* Yep, inf result */ | ||
233 | + float_raise(float_flag_overflow, fp_status); | ||
234 | + float_raise(float_flag_inexact, fp_status); | ||
235 | + switch (fp_status->float_rounding_mode) { | ||
236 | + case float_round_to_zero: | ||
237 | + return maxfinite_float64(a.sign); | ||
238 | + case float_round_up: | ||
239 | + if (a.sign == 0) { | ||
240 | + return infinite_float64(a.sign); | ||
241 | + } else { | ||
242 | + return maxfinite_float64(a.sign); | ||
243 | + } | ||
244 | + case float_round_down: | ||
245 | + if (a.sign != 0) { | ||
246 | + return infinite_float64(a.sign); | ||
247 | + } else { | ||
248 | + return maxfinite_float64(a.sign); | ||
249 | + } | ||
250 | + default: | ||
251 | + return infinite_float64(a.sign); | ||
252 | + } | ||
253 | + } | ||
254 | + /* Underflow? */ | ||
255 | + if (int128_getlo(a.mant) & (1ULL << DF_MANTBITS)) { | ||
256 | + /* Leading one means: No, we're normal. So, we should be done... */ | ||
257 | + Double ret; | ||
258 | + ret.i = 0; | ||
259 | + ret.sign = a.sign; | ||
260 | + ret.exp = a.exp; | ||
261 | + ret.mant = int128_getlo(a.mant); | ||
262 | + return ret.i; | ||
263 | + } | ||
264 | + assert(a.exp == 1); | ||
265 | + Double ret; | ||
266 | + ret.i = 0; | ||
267 | + ret.sign = a.sign; | ||
268 | + ret.exp = 0; | ||
269 | + ret.mant = int128_getlo(a.mant); | ||
270 | + return ret.i; | ||
271 | } | ||
272 | |||
273 | -GEN_XF_ROUND(float64, DF_MANTBITS, DF_INF_EXP, Double) | ||
274 | - | ||
275 | float64 internal_mpyhh(float64 a, float64 b, | ||
276 | unsigned long long int accumulated, | ||
277 | float_status *fp_status) | ||
278 | -- | ||
279 | 2.43.0 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | This structure, with bitfields, is incorrect for big-endian. | ||
2 | Use the existing float32_getexp_raw which uses extract32. | ||
1 | 3 | ||
4 | Reviewed-by: Brian Cain <brian.cain@oss.qualcomm.com> | ||
5 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
6 | --- | ||
7 | target/hexagon/fma_emu.c | 16 +++------------- | ||
8 | 1 file changed, 3 insertions(+), 13 deletions(-) | ||
9 | |||
10 | diff --git a/target/hexagon/fma_emu.c b/target/hexagon/fma_emu.c | ||
11 | index XXXXXXX..XXXXXXX 100644 | ||
12 | --- a/target/hexagon/fma_emu.c | ||
13 | +++ b/target/hexagon/fma_emu.c | ||
14 | @@ -XXX,XX +XXX,XX @@ typedef union { | ||
15 | }; | ||
16 | } Double; | ||
17 | |||
18 | -typedef union { | ||
19 | - float f; | ||
20 | - uint32_t i; | ||
21 | - struct { | ||
22 | - uint32_t mant:23; | ||
23 | - uint32_t exp:8; | ||
24 | - uint32_t sign:1; | ||
25 | - }; | ||
26 | -} Float; | ||
27 | - | ||
28 | static uint64_t float64_getmant(float64 f64) | ||
29 | { | ||
30 | Double a = { .i = f64 }; | ||
31 | @@ -XXX,XX +XXX,XX @@ int32_t float64_getexp(float64 f64) | ||
32 | |||
33 | int32_t float32_getexp(float32 f32) | ||
34 | { | ||
35 | - Float a = { .i = f32 }; | ||
36 | + int exp = float32_getexp_raw(f32); | ||
37 | if (float32_is_normal(f32)) { | ||
38 | - return a.exp; | ||
39 | + return exp; | ||
40 | } | ||
41 | if (float32_is_denormal(f32)) { | ||
42 | - return a.exp + 1; | ||
43 | + return exp + 1; | ||
44 | } | ||
45 | return -1; | ||
46 | } | ||
47 | -- | ||
48 | 2.43.0 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | This structure, with bitfields, is incorrect for big-endian. | ||
2 | Use extract64 and deposit64 instead. | ||
1 | 3 | ||
4 | Reviewed-by: Brian Cain <brian.cain@oss.qualcomm.com> | ||
5 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
6 | --- | ||
7 | target/hexagon/fma_emu.c | 46 ++++++++++++++-------------------------- | ||
8 | 1 file changed, 16 insertions(+), 30 deletions(-) | ||
9 | |||
10 | diff --git a/target/hexagon/fma_emu.c b/target/hexagon/fma_emu.c | ||
11 | index XXXXXXX..XXXXXXX 100644 | ||
12 | --- a/target/hexagon/fma_emu.c | ||
13 | +++ b/target/hexagon/fma_emu.c | ||
14 | @@ -XXX,XX +XXX,XX @@ | ||
15 | |||
16 | #define WAY_BIG_EXP 4096 | ||
17 | |||
18 | -typedef union { | ||
19 | - double f; | ||
20 | - uint64_t i; | ||
21 | - struct { | ||
22 | - uint64_t mant:52; | ||
23 | - uint64_t exp:11; | ||
24 | - uint64_t sign:1; | ||
25 | - }; | ||
26 | -} Double; | ||
27 | - | ||
28 | static uint64_t float64_getmant(float64 f64) | ||
29 | { | ||
30 | - Double a = { .i = f64 }; | ||
31 | + uint64_t mant = extract64(f64, 0, 52); | ||
32 | if (float64_is_normal(f64)) { | ||
33 | - return a.mant | 1ULL << 52; | ||
34 | + return mant | 1ULL << 52; | ||
35 | } | ||
36 | if (float64_is_zero(f64)) { | ||
37 | return 0; | ||
38 | } | ||
39 | if (float64_is_denormal(f64)) { | ||
40 | - return a.mant; | ||
41 | + return mant; | ||
42 | } | ||
43 | return ~0ULL; | ||
44 | } | ||
45 | |||
46 | int32_t float64_getexp(float64 f64) | ||
47 | { | ||
48 | - Double a = { .i = f64 }; | ||
49 | + int exp = extract64(f64, 52, 11); | ||
50 | if (float64_is_normal(f64)) { | ||
51 | - return a.exp; | ||
52 | + return exp; | ||
53 | } | ||
54 | if (float64_is_denormal(f64)) { | ||
55 | - return a.exp + 1; | ||
56 | + return exp + 1; | ||
57 | } | ||
58 | return -1; | ||
59 | } | ||
60 | @@ -XXX,XX +XXX,XX @@ float32 infinite_float32(uint8_t sign) | ||
61 | /* Return a maximum finite value with the requested sign */ | ||
62 | static float64 accum_round_float64(Accum a, float_status *fp_status) | ||
63 | { | ||
64 | + uint64_t ret; | ||
65 | + | ||
66 | if ((int128_gethi(a.mant) == 0) && (int128_getlo(a.mant) == 0) | ||
67 | && ((a.guard | a.round | a.sticky) == 0)) { | ||
68 | /* result zero */ | ||
69 | @@ -XXX,XX +XXX,XX @@ static float64 accum_round_float64(Accum a, float_status *fp_status) | ||
70 | } | ||
71 | } | ||
72 | /* Underflow? */ | ||
73 | - if (int128_getlo(a.mant) & (1ULL << DF_MANTBITS)) { | ||
74 | + ret = int128_getlo(a.mant); | ||
75 | + if (ret & (1ULL << DF_MANTBITS)) { | ||
76 | /* Leading one means: No, we're normal. So, we should be done... */ | ||
77 | - Double ret; | ||
78 | - ret.i = 0; | ||
79 | - ret.sign = a.sign; | ||
80 | - ret.exp = a.exp; | ||
81 | - ret.mant = int128_getlo(a.mant); | ||
82 | - return ret.i; | ||
83 | + ret = deposit64(ret, 52, 11, a.exp); | ||
84 | + } else { | ||
85 | + assert(a.exp == 1); | ||
86 | + ret = deposit64(ret, 52, 11, 0); | ||
87 | } | ||
88 | - assert(a.exp == 1); | ||
89 | - Double ret; | ||
90 | - ret.i = 0; | ||
91 | - ret.sign = a.sign; | ||
92 | - ret.exp = 0; | ||
93 | - ret.mant = int128_getlo(a.mant); | ||
94 | - return ret.i; | ||
95 | + ret = deposit64(ret, 63, 1, a.sign); | ||
96 | + return ret; | ||
97 | } | ||
98 | |||
99 | float64 internal_mpyhh(float64 a, float64 b, | ||
100 | -- | ||
101 | 2.43.0 | diff view generated by jsdifflib |
1 | These interfaces have been replaced by tcg_gen_dupi_vec | 1 | No need to open-code 64x64->128-bit multiplication. |
---|---|---|---|
2 | and tcg_constant_vec. | ||
3 | 2 | ||
4 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | 3 | Reviewed-by: Brian Cain <brian.cain@oss.qualcomm.com> |
5 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 4 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
6 | --- | 5 | --- |
7 | include/tcg/tcg-op.h | 4 ---- | 6 | target/hexagon/fma_emu.c | 32 +++----------------------------- |
8 | tcg/tcg-op-vec.c | 20 -------------------- | 7 | 1 file changed, 3 insertions(+), 29 deletions(-) |
9 | 2 files changed, 24 deletions(-) | ||
10 | 8 | ||
11 | diff --git a/include/tcg/tcg-op.h b/include/tcg/tcg-op.h | 9 | diff --git a/target/hexagon/fma_emu.c b/target/hexagon/fma_emu.c |
12 | index XXXXXXX..XXXXXXX 100644 | 10 | index XXXXXXX..XXXXXXX 100644 |
13 | --- a/include/tcg/tcg-op.h | 11 | --- a/target/hexagon/fma_emu.c |
14 | +++ b/include/tcg/tcg-op.h | 12 | +++ b/target/hexagon/fma_emu.c |
15 | @@ -XXX,XX +XXX,XX @@ void tcg_gen_mov_vec(TCGv_vec, TCGv_vec); | 13 | @@ -XXX,XX +XXX,XX @@ int32_t float32_getexp(float32 f32) |
16 | void tcg_gen_dup_i32_vec(unsigned vece, TCGv_vec, TCGv_i32); | 14 | return -1; |
17 | void tcg_gen_dup_i64_vec(unsigned vece, TCGv_vec, TCGv_i64); | ||
18 | void tcg_gen_dup_mem_vec(unsigned vece, TCGv_vec, TCGv_ptr, tcg_target_long); | ||
19 | -void tcg_gen_dup8i_vec(TCGv_vec, uint32_t); | ||
20 | -void tcg_gen_dup16i_vec(TCGv_vec, uint32_t); | ||
21 | -void tcg_gen_dup32i_vec(TCGv_vec, uint32_t); | ||
22 | -void tcg_gen_dup64i_vec(TCGv_vec, uint64_t); | ||
23 | void tcg_gen_dupi_vec(unsigned vece, TCGv_vec, uint64_t); | ||
24 | void tcg_gen_add_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); | ||
25 | void tcg_gen_sub_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); | ||
26 | diff --git a/tcg/tcg-op-vec.c b/tcg/tcg-op-vec.c | ||
27 | index XXXXXXX..XXXXXXX 100644 | ||
28 | --- a/tcg/tcg-op-vec.c | ||
29 | +++ b/tcg/tcg-op-vec.c | ||
30 | @@ -XXX,XX +XXX,XX @@ TCGv_vec tcg_const_ones_vec_matching(TCGv_vec m) | ||
31 | return tcg_const_ones_vec(t->base_type); | ||
32 | } | 15 | } |
33 | 16 | ||
34 | -void tcg_gen_dup64i_vec(TCGv_vec r, uint64_t a) | 17 | -static uint32_t int128_getw0(Int128 x) |
35 | -{ | 18 | -{ |
36 | - tcg_gen_dupi_vec(MO_64, r, a); | 19 | - return int128_getlo(x); |
37 | -} | 20 | -} |
38 | - | 21 | - |
39 | -void tcg_gen_dup32i_vec(TCGv_vec r, uint32_t a) | 22 | -static uint32_t int128_getw1(Int128 x) |
40 | -{ | 23 | -{ |
41 | - tcg_gen_dupi_vec(MO_32, r, a); | 24 | - return int128_getlo(x) >> 32; |
42 | -} | 25 | -} |
43 | - | 26 | - |
44 | -void tcg_gen_dup16i_vec(TCGv_vec r, uint32_t a) | 27 | static Int128 int128_mul_6464(uint64_t ai, uint64_t bi) |
45 | -{ | 28 | { |
46 | - tcg_gen_dupi_vec(MO_16, r, a); | 29 | - Int128 a, b; |
47 | -} | 30 | - uint64_t pp0, pp1a, pp1b, pp1s, pp2; |
31 | + uint64_t l, h; | ||
32 | |||
33 | - a = int128_make64(ai); | ||
34 | - b = int128_make64(bi); | ||
35 | - pp0 = (uint64_t)int128_getw0(a) * (uint64_t)int128_getw0(b); | ||
36 | - pp1a = (uint64_t)int128_getw1(a) * (uint64_t)int128_getw0(b); | ||
37 | - pp1b = (uint64_t)int128_getw1(b) * (uint64_t)int128_getw0(a); | ||
38 | - pp2 = (uint64_t)int128_getw1(a) * (uint64_t)int128_getw1(b); | ||
48 | - | 39 | - |
49 | -void tcg_gen_dup8i_vec(TCGv_vec r, uint32_t a) | 40 | - pp1s = pp1a + pp1b; |
50 | -{ | 41 | - if ((pp1s < pp1a) || (pp1s < pp1b)) { |
51 | - tcg_gen_dupi_vec(MO_8, r, a); | 42 | - pp2 += (1ULL << 32); |
52 | -} | 43 | - } |
44 | - uint64_t ret_low = pp0 + (pp1s << 32); | ||
45 | - if ((ret_low < pp0) || (ret_low < (pp1s << 32))) { | ||
46 | - pp2 += 1; | ||
47 | - } | ||
53 | - | 48 | - |
54 | void tcg_gen_dupi_vec(unsigned vece, TCGv_vec r, uint64_t a) | 49 | - return int128_make128(ret_low, pp2 + (pp1s >> 32)); |
55 | { | 50 | + mulu64(&l, &h, ai, bi); |
56 | TCGTemp *rt = tcgv_vec_temp(r); | 51 | + return int128_make128(l, h); |
52 | } | ||
53 | |||
54 | static Int128 int128_sub_borrow(Int128 a, Int128 b, int borrow) | ||
57 | -- | 55 | -- |
58 | 2.25.1 | 56 | 2.43.0 |
59 | |||
60 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Initialize x with accumulated via direct assignment, | ||
2 | rather than multiplying by 1. | ||
1 | 3 | ||
4 | Reviewed-by: Brian Cain <brian.cain@oss.qualcomm.com> | ||
5 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
6 | --- | ||
7 | target/hexagon/fma_emu.c | 2 +- | ||
8 | 1 file changed, 1 insertion(+), 1 deletion(-) | ||
9 | |||
10 | diff --git a/target/hexagon/fma_emu.c b/target/hexagon/fma_emu.c | ||
11 | index XXXXXXX..XXXXXXX 100644 | ||
12 | --- a/target/hexagon/fma_emu.c | ||
13 | +++ b/target/hexagon/fma_emu.c | ||
14 | @@ -XXX,XX +XXX,XX @@ float64 internal_mpyhh(float64 a, float64 b, | ||
15 | float64_is_infinity(b)) { | ||
16 | return float64_mul(a, b, fp_status); | ||
17 | } | ||
18 | - x.mant = int128_mul_6464(accumulated, 1); | ||
19 | + x.mant = int128_make64(accumulated); | ||
20 | x.sticky = sticky; | ||
21 | prod = fGETUWORD(1, float64_getmant(a)) * fGETUWORD(1, float64_getmant(b)); | ||
22 | x.mant = int128_add(x.mant, int128_mul_6464(prod, 0x100000000ULL)); | ||
23 | -- | ||
24 | 2.43.0 | diff view generated by jsdifflib |
1 | The normal movi opcodes are going away. We need something | 1 | Convert all targets simultaneously, as the gen_intermediate_code |
---|---|---|---|
2 | for TCI to use internally. | 2 | function disappears from the target. While there are possible |
3 | workarounds, they're larger than simply performing the conversion. | ||
3 | 4 | ||
4 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | 5 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
5 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
6 | --- | 7 | --- |
7 | include/tcg/tcg-opc.h | 8 ++++++++ | 8 | include/exec/translator.h | 14 -------------- |
8 | tcg/tci.c | 4 ++-- | 9 | include/hw/core/tcg-cpu-ops.h | 13 +++++++++++++ |
9 | tcg/tci/tcg-target.c.inc | 4 ++-- | 10 | target/alpha/cpu.h | 2 ++ |
10 | 3 files changed, 12 insertions(+), 4 deletions(-) | 11 | target/arm/internals.h | 2 ++ |
12 | target/avr/cpu.h | 2 ++ | ||
13 | target/hexagon/cpu.h | 2 ++ | ||
14 | target/hppa/cpu.h | 2 ++ | ||
15 | target/i386/tcg/helper-tcg.h | 2 ++ | ||
16 | target/loongarch/internals.h | 2 ++ | ||
17 | target/m68k/cpu.h | 2 ++ | ||
18 | target/microblaze/cpu.h | 2 ++ | ||
19 | target/mips/tcg/tcg-internal.h | 2 ++ | ||
20 | target/openrisc/cpu.h | 2 ++ | ||
21 | target/ppc/cpu.h | 2 ++ | ||
22 | target/riscv/cpu.h | 3 +++ | ||
23 | target/rx/cpu.h | 2 ++ | ||
24 | target/s390x/s390x-internal.h | 2 ++ | ||
25 | target/sh4/cpu.h | 2 ++ | ||
26 | target/sparc/cpu.h | 2 ++ | ||
27 | target/tricore/cpu.h | 2 ++ | ||
28 | target/xtensa/cpu.h | 2 ++ | ||
29 | accel/tcg/cpu-exec.c | 8 +++++--- | ||
30 | accel/tcg/translate-all.c | 8 +++++--- | ||
31 | target/alpha/cpu.c | 1 + | ||
32 | target/alpha/translate.c | 4 ++-- | ||
33 | target/arm/cpu.c | 1 + | ||
34 | target/arm/tcg/cpu-v7m.c | 1 + | ||
35 | target/arm/tcg/translate.c | 5 ++--- | ||
36 | target/avr/cpu.c | 1 + | ||
37 | target/avr/translate.c | 6 +++--- | ||
38 | target/hexagon/cpu.c | 1 + | ||
39 | target/hexagon/translate.c | 4 ++-- | ||
40 | target/hppa/cpu.c | 1 + | ||
41 | target/hppa/translate.c | 4 ++-- | ||
42 | target/i386/tcg/tcg-cpu.c | 1 + | ||
43 | target/i386/tcg/translate.c | 5 ++--- | ||
44 | target/loongarch/cpu.c | 1 + | ||
45 | target/loongarch/tcg/translate.c | 4 ++-- | ||
46 | target/m68k/cpu.c | 1 + | ||
47 | target/m68k/translate.c | 4 ++-- | ||
48 | target/microblaze/cpu.c | 1 + | ||
49 | target/microblaze/translate.c | 4 ++-- | ||
50 | target/mips/cpu.c | 1 + | ||
51 | target/mips/tcg/translate.c | 4 ++-- | ||
52 | target/openrisc/cpu.c | 1 + | ||
53 | target/openrisc/translate.c | 4 ++-- | ||
54 | target/ppc/cpu_init.c | 1 + | ||
55 | target/ppc/translate.c | 4 ++-- | ||
56 | target/riscv/tcg/tcg-cpu.c | 1 + | ||
57 | target/riscv/translate.c | 4 ++-- | ||
58 | target/rx/cpu.c | 1 + | ||
59 | target/rx/translate.c | 4 ++-- | ||
60 | target/s390x/cpu.c | 1 + | ||
61 | target/s390x/tcg/translate.c | 4 ++-- | ||
62 | target/sh4/cpu.c | 1 + | ||
63 | target/sh4/translate.c | 4 ++-- | ||
64 | target/sparc/cpu.c | 1 + | ||
65 | target/sparc/translate.c | 4 ++-- | ||
66 | target/tricore/cpu.c | 1 + | ||
67 | target/tricore/translate.c | 5 ++--- | ||
68 | target/xtensa/cpu.c | 1 + | ||
69 | target/xtensa/translate.c | 4 ++-- | ||
70 | 62 files changed, 121 insertions(+), 62 deletions(-) | ||
11 | 71 | ||
12 | diff --git a/include/tcg/tcg-opc.h b/include/tcg/tcg-opc.h | 72 | diff --git a/include/exec/translator.h b/include/exec/translator.h |
13 | index XXXXXXX..XXXXXXX 100644 | 73 | index XXXXXXX..XXXXXXX 100644 |
14 | --- a/include/tcg/tcg-opc.h | 74 | --- a/include/exec/translator.h |
15 | +++ b/include/tcg/tcg-opc.h | 75 | +++ b/include/exec/translator.h |
16 | @@ -XXX,XX +XXX,XX @@ DEF(last_generic, 0, 0, 0, TCG_OPF_NOT_PRESENT) | 76 | @@ -XXX,XX +XXX,XX @@ |
17 | #include "tcg-target.opc.h" | 77 | #include "qemu/bswap.h" |
78 | #include "exec/vaddr.h" | ||
79 | |||
80 | -/** | ||
81 | - * gen_intermediate_code | ||
82 | - * @cpu: cpu context | ||
83 | - * @tb: translation block | ||
84 | - * @max_insns: max number of instructions to translate | ||
85 | - * @pc: guest virtual program counter address | ||
86 | - * @host_pc: host physical program counter address | ||
87 | - * | ||
88 | - * This function must be provided by the target, which should create | ||
89 | - * the target-specific DisasContext, and then invoke translator_loop. | ||
90 | - */ | ||
91 | -void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int *max_insns, | ||
92 | - vaddr pc, void *host_pc); | ||
93 | - | ||
94 | /** | ||
95 | * DisasJumpType: | ||
96 | * @DISAS_NEXT: Next instruction in program order. | ||
97 | diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h | ||
98 | index XXXXXXX..XXXXXXX 100644 | ||
99 | --- a/include/hw/core/tcg-cpu-ops.h | ||
100 | +++ b/include/hw/core/tcg-cpu-ops.h | ||
101 | @@ -XXX,XX +XXX,XX @@ struct TCGCPUOps { | ||
102 | * Called when the first CPU is realized. | ||
103 | */ | ||
104 | void (*initialize)(void); | ||
105 | + /** | ||
106 | + * @translate_code: Translate guest instructions to TCGOps | ||
107 | + * @cpu: cpu context | ||
108 | + * @tb: translation block | ||
109 | + * @max_insns: max number of instructions to translate | ||
110 | + * @pc: guest virtual program counter address | ||
111 | + * @host_pc: host physical program counter address | ||
112 | + * | ||
113 | + * This function must be provided by the target, which should create | ||
114 | + * the target-specific DisasContext, and then invoke translator_loop. | ||
115 | + */ | ||
116 | + void (*translate_code)(CPUState *cpu, TranslationBlock *tb, | ||
117 | + int *max_insns, vaddr pc, void *host_pc); | ||
118 | /** | ||
119 | * @synchronize_from_tb: Synchronize state from a TCG #TranslationBlock | ||
120 | * | ||
121 | diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h | ||
122 | index XXXXXXX..XXXXXXX 100644 | ||
123 | --- a/target/alpha/cpu.h | ||
124 | +++ b/target/alpha/cpu.h | ||
125 | @@ -XXX,XX +XXX,XX @@ enum { | ||
126 | }; | ||
127 | |||
128 | void alpha_translate_init(void); | ||
129 | +void alpha_translate_code(CPUState *cs, TranslationBlock *tb, | ||
130 | + int *max_insns, vaddr pc, void *host_pc); | ||
131 | |||
132 | #define CPU_RESOLVING_TYPE TYPE_ALPHA_CPU | ||
133 | |||
134 | diff --git a/target/arm/internals.h b/target/arm/internals.h | ||
135 | index XXXXXXX..XXXXXXX 100644 | ||
136 | --- a/target/arm/internals.h | ||
137 | +++ b/target/arm/internals.h | ||
138 | @@ -XXX,XX +XXX,XX @@ void init_cpreg_list(ARMCPU *cpu); | ||
139 | |||
140 | void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu); | ||
141 | void arm_translate_init(void); | ||
142 | +void arm_translate_code(CPUState *cs, TranslationBlock *tb, | ||
143 | + int *max_insns, vaddr pc, void *host_pc); | ||
144 | |||
145 | void arm_cpu_register_gdb_commands(ARMCPU *cpu); | ||
146 | void aarch64_cpu_register_gdb_commands(ARMCPU *cpu, GString *, | ||
147 | diff --git a/target/avr/cpu.h b/target/avr/cpu.h | ||
148 | index XXXXXXX..XXXXXXX 100644 | ||
149 | --- a/target/avr/cpu.h | ||
150 | +++ b/target/avr/cpu.h | ||
151 | @@ -XXX,XX +XXX,XX @@ static inline void set_avr_feature(CPUAVRState *env, int feature) | ||
152 | } | ||
153 | |||
154 | void avr_cpu_tcg_init(void); | ||
155 | +void avr_cpu_translate_code(CPUState *cs, TranslationBlock *tb, | ||
156 | + int *max_insns, vaddr pc, void *host_pc); | ||
157 | |||
158 | int cpu_avr_exec(CPUState *cpu); | ||
159 | |||
160 | diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h | ||
161 | index XXXXXXX..XXXXXXX 100644 | ||
162 | --- a/target/hexagon/cpu.h | ||
163 | +++ b/target/hexagon/cpu.h | ||
164 | @@ -XXX,XX +XXX,XX @@ static inline void cpu_get_tb_cpu_state(CPUHexagonState *env, vaddr *pc, | ||
165 | typedef HexagonCPU ArchCPU; | ||
166 | |||
167 | void hexagon_translate_init(void); | ||
168 | +void hexagon_translate_code(CPUState *cs, TranslationBlock *tb, | ||
169 | + int *max_insns, vaddr pc, void *host_pc); | ||
170 | |||
171 | #include "exec/cpu-all.h" | ||
172 | |||
173 | diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h | ||
174 | index XXXXXXX..XXXXXXX 100644 | ||
175 | --- a/target/hppa/cpu.h | ||
176 | +++ b/target/hppa/cpu.h | ||
177 | @@ -XXX,XX +XXX,XX @@ static inline int HPPA_BTLB_ENTRIES(CPUHPPAState *env) | ||
178 | } | ||
179 | |||
180 | void hppa_translate_init(void); | ||
181 | +void hppa_translate_code(CPUState *cs, TranslationBlock *tb, | ||
182 | + int *max_insns, vaddr pc, void *host_pc); | ||
183 | |||
184 | #define CPU_RESOLVING_TYPE TYPE_HPPA_CPU | ||
185 | |||
186 | diff --git a/target/i386/tcg/helper-tcg.h b/target/i386/tcg/helper-tcg.h | ||
187 | index XXXXXXX..XXXXXXX 100644 | ||
188 | --- a/target/i386/tcg/helper-tcg.h | ||
189 | +++ b/target/i386/tcg/helper-tcg.h | ||
190 | @@ -XXX,XX +XXX,XX @@ static inline target_long lshift(target_long x, int n) | ||
191 | |||
192 | /* translate.c */ | ||
193 | void tcg_x86_init(void); | ||
194 | +void x86_translate_code(CPUState *cs, TranslationBlock *tb, | ||
195 | + int *max_insns, vaddr pc, void *host_pc); | ||
196 | |||
197 | /* excp_helper.c */ | ||
198 | G_NORETURN void raise_exception(CPUX86State *env, int exception_index); | ||
199 | diff --git a/target/loongarch/internals.h b/target/loongarch/internals.h | ||
200 | index XXXXXXX..XXXXXXX 100644 | ||
201 | --- a/target/loongarch/internals.h | ||
202 | +++ b/target/loongarch/internals.h | ||
203 | @@ -XXX,XX +XXX,XX @@ | ||
204 | #define TARGET_VIRT_MASK MAKE_64BIT_MASK(0, TARGET_VIRT_ADDR_SPACE_BITS) | ||
205 | |||
206 | void loongarch_translate_init(void); | ||
207 | +void loongarch_translate_code(CPUState *cs, TranslationBlock *tb, | ||
208 | + int *max_insns, vaddr pc, void *host_pc); | ||
209 | |||
210 | void G_NORETURN do_raise_exception(CPULoongArchState *env, | ||
211 | uint32_t exception, | ||
212 | diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h | ||
213 | index XXXXXXX..XXXXXXX 100644 | ||
214 | --- a/target/m68k/cpu.h | ||
215 | +++ b/target/m68k/cpu.h | ||
216 | @@ -XXX,XX +XXX,XX @@ int m68k_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); | ||
217 | int m68k_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); | ||
218 | |||
219 | void m68k_tcg_init(void); | ||
220 | +void m68k_translate_code(CPUState *cs, TranslationBlock *tb, | ||
221 | + int *max_insns, vaddr pc, void *host_pc); | ||
222 | void m68k_cpu_init_gdb(M68kCPU *cpu); | ||
223 | uint32_t cpu_m68k_get_ccr(CPUM68KState *env); | ||
224 | void cpu_m68k_set_ccr(CPUM68KState *env, uint32_t); | ||
225 | diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h | ||
226 | index XXXXXXX..XXXXXXX 100644 | ||
227 | --- a/target/microblaze/cpu.h | ||
228 | +++ b/target/microblaze/cpu.h | ||
229 | @@ -XXX,XX +XXX,XX @@ static inline void mb_cpu_write_msr(CPUMBState *env, uint32_t val) | ||
230 | } | ||
231 | |||
232 | void mb_tcg_init(void); | ||
233 | +void mb_translate_code(CPUState *cs, TranslationBlock *tb, | ||
234 | + int *max_insns, vaddr pc, void *host_pc); | ||
235 | |||
236 | #define CPU_RESOLVING_TYPE TYPE_MICROBLAZE_CPU | ||
237 | |||
238 | diff --git a/target/mips/tcg/tcg-internal.h b/target/mips/tcg/tcg-internal.h | ||
239 | index XXXXXXX..XXXXXXX 100644 | ||
240 | --- a/target/mips/tcg/tcg-internal.h | ||
241 | +++ b/target/mips/tcg/tcg-internal.h | ||
242 | @@ -XXX,XX +XXX,XX @@ | ||
243 | #include "cpu.h" | ||
244 | |||
245 | void mips_tcg_init(void); | ||
246 | +void mips_translate_code(CPUState *cs, TranslationBlock *tb, | ||
247 | + int *max_insns, vaddr pc, void *host_pc); | ||
248 | |||
249 | void mips_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb); | ||
250 | G_NORETURN void mips_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, | ||
251 | diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h | ||
252 | index XXXXXXX..XXXXXXX 100644 | ||
253 | --- a/target/openrisc/cpu.h | ||
254 | +++ b/target/openrisc/cpu.h | ||
255 | @@ -XXX,XX +XXX,XX @@ void openrisc_cpu_dump_state(CPUState *cpu, FILE *f, int flags); | ||
256 | int openrisc_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); | ||
257 | int openrisc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); | ||
258 | void openrisc_translate_init(void); | ||
259 | +void openrisc_translate_code(CPUState *cs, TranslationBlock *tb, | ||
260 | + int *max_insns, vaddr pc, void *host_pc); | ||
261 | int print_insn_or1k(bfd_vma addr, disassemble_info *info); | ||
262 | |||
263 | #ifndef CONFIG_USER_ONLY | ||
264 | diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h | ||
265 | index XXXXXXX..XXXXXXX 100644 | ||
266 | --- a/target/ppc/cpu.h | ||
267 | +++ b/target/ppc/cpu.h | ||
268 | @@ -XXX,XX +XXX,XX @@ extern const VMStateDescription vmstate_ppc_cpu; | ||
269 | |||
270 | /*****************************************************************************/ | ||
271 | void ppc_translate_init(void); | ||
272 | +void ppc_translate_code(CPUState *cs, TranslationBlock *tb, | ||
273 | + int *max_insns, vaddr pc, void *host_pc); | ||
274 | |||
275 | #if !defined(CONFIG_USER_ONLY) | ||
276 | void ppc_store_sdr1(CPUPPCState *env, target_ulong value); | ||
277 | diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h | ||
278 | index XXXXXXX..XXXXXXX 100644 | ||
279 | --- a/target/riscv/cpu.h | ||
280 | +++ b/target/riscv/cpu.h | ||
281 | @@ -XXX,XX +XXX,XX @@ RISCVException smstateen_acc_ok(CPURISCVState *env, int index, uint64_t bit); | ||
282 | void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv, bool virt_en); | ||
283 | |||
284 | void riscv_translate_init(void); | ||
285 | +void riscv_translate_code(CPUState *cs, TranslationBlock *tb, | ||
286 | + int *max_insns, vaddr pc, void *host_pc); | ||
287 | + | ||
288 | G_NORETURN void riscv_raise_exception(CPURISCVState *env, | ||
289 | uint32_t exception, uintptr_t pc); | ||
290 | |||
291 | diff --git a/target/rx/cpu.h b/target/rx/cpu.h | ||
292 | index XXXXXXX..XXXXXXX 100644 | ||
293 | --- a/target/rx/cpu.h | ||
294 | +++ b/target/rx/cpu.h | ||
295 | @@ -XXX,XX +XXX,XX @@ int rx_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); | ||
296 | int rx_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); | ||
297 | |||
298 | void rx_translate_init(void); | ||
299 | +void rx_translate_code(CPUState *cs, TranslationBlock *tb, | ||
300 | + int *max_insns, vaddr pc, void *host_pc); | ||
301 | void rx_cpu_unpack_psw(CPURXState *env, uint32_t psw, int rte); | ||
302 | |||
303 | #include "exec/cpu-all.h" | ||
304 | diff --git a/target/s390x/s390x-internal.h b/target/s390x/s390x-internal.h | ||
305 | index XXXXXXX..XXXXXXX 100644 | ||
306 | --- a/target/s390x/s390x-internal.h | ||
307 | +++ b/target/s390x/s390x-internal.h | ||
308 | @@ -XXX,XX +XXX,XX @@ void handle_diag_308(CPUS390XState *env, uint64_t r1, uint64_t r3, | ||
309 | |||
310 | /* translate.c */ | ||
311 | void s390x_translate_init(void); | ||
312 | +void s390x_translate_code(CPUState *cs, TranslationBlock *tb, | ||
313 | + int *max_insns, vaddr pc, void *host_pc); | ||
314 | void s390x_restore_state_to_opc(CPUState *cs, | ||
315 | const TranslationBlock *tb, | ||
316 | const uint64_t *data); | ||
317 | diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h | ||
318 | index XXXXXXX..XXXXXXX 100644 | ||
319 | --- a/target/sh4/cpu.h | ||
320 | +++ b/target/sh4/cpu.h | ||
321 | @@ -XXX,XX +XXX,XX @@ G_NORETURN void superh_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, | ||
322 | uintptr_t retaddr); | ||
323 | |||
324 | void sh4_translate_init(void); | ||
325 | +void sh4_translate_code(CPUState *cs, TranslationBlock *tb, | ||
326 | + int *max_insns, vaddr pc, void *host_pc); | ||
327 | |||
328 | #if !defined(CONFIG_USER_ONLY) | ||
329 | hwaddr superh_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); | ||
330 | diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h | ||
331 | index XXXXXXX..XXXXXXX 100644 | ||
332 | --- a/target/sparc/cpu.h | ||
333 | +++ b/target/sparc/cpu.h | ||
334 | @@ -XXX,XX +XXX,XX @@ int sparc_cpu_memory_rw_debug(CPUState *cpu, vaddr addr, | ||
335 | |||
336 | /* translate.c */ | ||
337 | void sparc_tcg_init(void); | ||
338 | +void sparc_translate_code(CPUState *cs, TranslationBlock *tb, | ||
339 | + int *max_insns, vaddr pc, void *host_pc); | ||
340 | |||
341 | /* fop_helper.c */ | ||
342 | target_ulong cpu_get_fsr(CPUSPARCState *); | ||
343 | diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h | ||
344 | index XXXXXXX..XXXXXXX 100644 | ||
345 | --- a/target/tricore/cpu.h | ||
346 | +++ b/target/tricore/cpu.h | ||
347 | @@ -XXX,XX +XXX,XX @@ FIELD(TB_FLAGS, PRIV, 0, 2) | ||
348 | |||
349 | void cpu_state_reset(CPUTriCoreState *s); | ||
350 | void tricore_tcg_init(void); | ||
351 | +void tricore_translate_code(CPUState *cs, TranslationBlock *tb, | ||
352 | + int *max_insns, vaddr pc, void *host_pc); | ||
353 | |||
354 | static inline void cpu_get_tb_cpu_state(CPUTriCoreState *env, vaddr *pc, | ||
355 | uint64_t *cs_base, uint32_t *flags) | ||
356 | diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h | ||
357 | index XXXXXXX..XXXXXXX 100644 | ||
358 | --- a/target/xtensa/cpu.h | ||
359 | +++ b/target/xtensa/cpu.h | ||
360 | @@ -XXX,XX +XXX,XX @@ G_NORETURN void xtensa_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, | ||
361 | |||
362 | void xtensa_collect_sr_names(const XtensaConfig *config); | ||
363 | void xtensa_translate_init(void); | ||
364 | +void xtensa_translate_code(CPUState *cs, TranslationBlock *tb, | ||
365 | + int *max_insns, vaddr pc, void *host_pc); | ||
366 | void **xtensa_get_regfile_by_name(const char *name, int entries, int bits); | ||
367 | void xtensa_breakpoint_handler(CPUState *cs); | ||
368 | void xtensa_register_core(XtensaConfigList *node); | ||
369 | diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c | ||
370 | index XXXXXXX..XXXXXXX 100644 | ||
371 | --- a/accel/tcg/cpu-exec.c | ||
372 | +++ b/accel/tcg/cpu-exec.c | ||
373 | @@ -XXX,XX +XXX,XX @@ bool tcg_exec_realizefn(CPUState *cpu, Error **errp) | ||
374 | |||
375 | if (!tcg_target_initialized) { | ||
376 | /* Check mandatory TCGCPUOps handlers */ | ||
377 | + const TCGCPUOps *tcg_ops = cpu->cc->tcg_ops; | ||
378 | #ifndef CONFIG_USER_ONLY | ||
379 | - assert(cpu->cc->tcg_ops->cpu_exec_halt); | ||
380 | - assert(cpu->cc->tcg_ops->cpu_exec_interrupt); | ||
381 | + assert(tcg_ops->cpu_exec_halt); | ||
382 | + assert(tcg_ops->cpu_exec_interrupt); | ||
383 | #endif /* !CONFIG_USER_ONLY */ | ||
384 | - cpu->cc->tcg_ops->initialize(); | ||
385 | + assert(tcg_ops->translate_code); | ||
386 | + tcg_ops->initialize(); | ||
387 | tcg_target_initialized = true; | ||
388 | } | ||
389 | |||
390 | diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c | ||
391 | index XXXXXXX..XXXXXXX 100644 | ||
392 | --- a/accel/tcg/translate-all.c | ||
393 | +++ b/accel/tcg/translate-all.c | ||
394 | @@ -XXX,XX +XXX,XX @@ static int setjmp_gen_code(CPUArchState *env, TranslationBlock *tb, | ||
395 | |||
396 | tcg_func_start(tcg_ctx); | ||
397 | |||
398 | - tcg_ctx->cpu = env_cpu(env); | ||
399 | - gen_intermediate_code(env_cpu(env), tb, max_insns, pc, host_pc); | ||
400 | + CPUState *cs = env_cpu(env); | ||
401 | + tcg_ctx->cpu = cs; | ||
402 | + cs->cc->tcg_ops->translate_code(cs, tb, max_insns, pc, host_pc); | ||
403 | + | ||
404 | assert(tb->size != 0); | ||
405 | tcg_ctx->cpu = NULL; | ||
406 | *max_insns = tb->icount; | ||
407 | @@ -XXX,XX +XXX,XX @@ TranslationBlock *tb_gen_code(CPUState *cpu, | ||
408 | /* | ||
409 | * Overflow of code_gen_buffer, or the current slice of it. | ||
410 | * | ||
411 | - * TODO: We don't need to re-do gen_intermediate_code, nor | ||
412 | + * TODO: We don't need to re-do tcg_ops->translate_code, nor | ||
413 | * should we re-do the tcg optimization currently hidden | ||
414 | * inside tcg_gen_code. All that should be required is to | ||
415 | * flush the TBs, allocate a new TB, re-initialize it per | ||
416 | diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c | ||
417 | index XXXXXXX..XXXXXXX 100644 | ||
418 | --- a/target/alpha/cpu.c | ||
419 | +++ b/target/alpha/cpu.c | ||
420 | @@ -XXX,XX +XXX,XX @@ static const struct SysemuCPUOps alpha_sysemu_ops = { | ||
421 | |||
422 | static const TCGCPUOps alpha_tcg_ops = { | ||
423 | .initialize = alpha_translate_init, | ||
424 | + .translate_code = alpha_translate_code, | ||
425 | .synchronize_from_tb = alpha_cpu_synchronize_from_tb, | ||
426 | .restore_state_to_opc = alpha_restore_state_to_opc, | ||
427 | |||
428 | diff --git a/target/alpha/translate.c b/target/alpha/translate.c | ||
429 | index XXXXXXX..XXXXXXX 100644 | ||
430 | --- a/target/alpha/translate.c | ||
431 | +++ b/target/alpha/translate.c | ||
432 | @@ -XXX,XX +XXX,XX @@ static const TranslatorOps alpha_tr_ops = { | ||
433 | .tb_stop = alpha_tr_tb_stop, | ||
434 | }; | ||
435 | |||
436 | -void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int *max_insns, | ||
437 | - vaddr pc, void *host_pc) | ||
438 | +void alpha_translate_code(CPUState *cpu, TranslationBlock *tb, | ||
439 | + int *max_insns, vaddr pc, void *host_pc) | ||
440 | { | ||
441 | DisasContext dc; | ||
442 | translator_loop(cpu, tb, max_insns, pc, host_pc, &alpha_tr_ops, &dc.base); | ||
443 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c | ||
444 | index XXXXXXX..XXXXXXX 100644 | ||
445 | --- a/target/arm/cpu.c | ||
446 | +++ b/target/arm/cpu.c | ||
447 | @@ -XXX,XX +XXX,XX @@ static const struct SysemuCPUOps arm_sysemu_ops = { | ||
448 | #ifdef CONFIG_TCG | ||
449 | static const TCGCPUOps arm_tcg_ops = { | ||
450 | .initialize = arm_translate_init, | ||
451 | + .translate_code = arm_translate_code, | ||
452 | .synchronize_from_tb = arm_cpu_synchronize_from_tb, | ||
453 | .debug_excp_handler = arm_debug_excp_handler, | ||
454 | .restore_state_to_opc = arm_restore_state_to_opc, | ||
455 | diff --git a/target/arm/tcg/cpu-v7m.c b/target/arm/tcg/cpu-v7m.c | ||
456 | index XXXXXXX..XXXXXXX 100644 | ||
457 | --- a/target/arm/tcg/cpu-v7m.c | ||
458 | +++ b/target/arm/tcg/cpu-v7m.c | ||
459 | @@ -XXX,XX +XXX,XX @@ static void cortex_m55_initfn(Object *obj) | ||
460 | |||
461 | static const TCGCPUOps arm_v7m_tcg_ops = { | ||
462 | .initialize = arm_translate_init, | ||
463 | + .translate_code = arm_translate_code, | ||
464 | .synchronize_from_tb = arm_cpu_synchronize_from_tb, | ||
465 | .debug_excp_handler = arm_debug_excp_handler, | ||
466 | .restore_state_to_opc = arm_restore_state_to_opc, | ||
467 | diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c | ||
468 | index XXXXXXX..XXXXXXX 100644 | ||
469 | --- a/target/arm/tcg/translate.c | ||
470 | +++ b/target/arm/tcg/translate.c | ||
471 | @@ -XXX,XX +XXX,XX @@ static const TranslatorOps thumb_translator_ops = { | ||
472 | .tb_stop = arm_tr_tb_stop, | ||
473 | }; | ||
474 | |||
475 | -/* generate intermediate code for basic block 'tb'. */ | ||
476 | -void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int *max_insns, | ||
477 | - vaddr pc, void *host_pc) | ||
478 | +void arm_translate_code(CPUState *cpu, TranslationBlock *tb, | ||
479 | + int *max_insns, vaddr pc, void *host_pc) | ||
480 | { | ||
481 | DisasContext dc = { }; | ||
482 | const TranslatorOps *ops = &arm_translator_ops; | ||
483 | diff --git a/target/avr/cpu.c b/target/avr/cpu.c | ||
484 | index XXXXXXX..XXXXXXX 100644 | ||
485 | --- a/target/avr/cpu.c | ||
486 | +++ b/target/avr/cpu.c | ||
487 | @@ -XXX,XX +XXX,XX @@ static const struct SysemuCPUOps avr_sysemu_ops = { | ||
488 | |||
489 | static const TCGCPUOps avr_tcg_ops = { | ||
490 | .initialize = avr_cpu_tcg_init, | ||
491 | + .translate_code = avr_cpu_translate_code, | ||
492 | .synchronize_from_tb = avr_cpu_synchronize_from_tb, | ||
493 | .restore_state_to_opc = avr_restore_state_to_opc, | ||
494 | .cpu_exec_interrupt = avr_cpu_exec_interrupt, | ||
495 | diff --git a/target/avr/translate.c b/target/avr/translate.c | ||
496 | index XXXXXXX..XXXXXXX 100644 | ||
497 | --- a/target/avr/translate.c | ||
498 | +++ b/target/avr/translate.c | ||
499 | @@ -XXX,XX +XXX,XX @@ static bool trans_WDR(DisasContext *ctx, arg_WDR *a) | ||
500 | * | ||
501 | * - translate() | ||
502 | * - canonicalize_skip() | ||
503 | - * - gen_intermediate_code() | ||
504 | + * - translate_code() | ||
505 | * - restore_state_to_opc() | ||
506 | * | ||
507 | */ | ||
508 | @@ -XXX,XX +XXX,XX @@ static const TranslatorOps avr_tr_ops = { | ||
509 | .tb_stop = avr_tr_tb_stop, | ||
510 | }; | ||
511 | |||
512 | -void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns, | ||
513 | - vaddr pc, void *host_pc) | ||
514 | +void avr_cpu_translate_code(CPUState *cs, TranslationBlock *tb, | ||
515 | + int *max_insns, vaddr pc, void *host_pc) | ||
516 | { | ||
517 | DisasContext dc = { }; | ||
518 | translator_loop(cs, tb, max_insns, pc, host_pc, &avr_tr_ops, &dc.base); | ||
519 | diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c | ||
520 | index XXXXXXX..XXXXXXX 100644 | ||
521 | --- a/target/hexagon/cpu.c | ||
522 | +++ b/target/hexagon/cpu.c | ||
523 | @@ -XXX,XX +XXX,XX @@ static void hexagon_cpu_init(Object *obj) | ||
524 | |||
525 | static const TCGCPUOps hexagon_tcg_ops = { | ||
526 | .initialize = hexagon_translate_init, | ||
527 | + .translate_code = hexagon_translate_code, | ||
528 | .synchronize_from_tb = hexagon_cpu_synchronize_from_tb, | ||
529 | .restore_state_to_opc = hexagon_restore_state_to_opc, | ||
530 | }; | ||
531 | diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c | ||
532 | index XXXXXXX..XXXXXXX 100644 | ||
533 | --- a/target/hexagon/translate.c | ||
534 | +++ b/target/hexagon/translate.c | ||
535 | @@ -XXX,XX +XXX,XX @@ static const TranslatorOps hexagon_tr_ops = { | ||
536 | .tb_stop = hexagon_tr_tb_stop, | ||
537 | }; | ||
538 | |||
539 | -void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns, | ||
540 | - vaddr pc, void *host_pc) | ||
541 | +void hexagon_translate_code(CPUState *cs, TranslationBlock *tb, | ||
542 | + int *max_insns, vaddr pc, void *host_pc) | ||
543 | { | ||
544 | DisasContext ctx; | ||
545 | |||
546 | diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c | ||
547 | index XXXXXXX..XXXXXXX 100644 | ||
548 | --- a/target/hppa/cpu.c | ||
549 | +++ b/target/hppa/cpu.c | ||
550 | @@ -XXX,XX +XXX,XX @@ static const struct SysemuCPUOps hppa_sysemu_ops = { | ||
551 | |||
552 | static const TCGCPUOps hppa_tcg_ops = { | ||
553 | .initialize = hppa_translate_init, | ||
554 | + .translate_code = hppa_translate_code, | ||
555 | .synchronize_from_tb = hppa_cpu_synchronize_from_tb, | ||
556 | .restore_state_to_opc = hppa_restore_state_to_opc, | ||
557 | |||
558 | diff --git a/target/hppa/translate.c b/target/hppa/translate.c | ||
559 | index XXXXXXX..XXXXXXX 100644 | ||
560 | --- a/target/hppa/translate.c | ||
561 | +++ b/target/hppa/translate.c | ||
562 | @@ -XXX,XX +XXX,XX @@ static const TranslatorOps hppa_tr_ops = { | ||
18 | #endif | 563 | #endif |
19 | 564 | }; | |
20 | +#ifdef TCG_TARGET_INTERPRETER | 565 | |
21 | +/* These opcodes are only for use between the tci generator and interpreter. */ | 566 | -void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns, |
22 | +DEF(tci_movi_i32, 1, 0, 1, TCG_OPF_NOT_PRESENT) | 567 | - vaddr pc, void *host_pc) |
23 | +#if TCG_TARGET_REG_BITS == 64 | 568 | +void hppa_translate_code(CPUState *cs, TranslationBlock *tb, |
24 | +DEF(tci_movi_i64, 1, 0, 1, TCG_OPF_64BIT | TCG_OPF_NOT_PRESENT) | 569 | + int *max_insns, vaddr pc, void *host_pc) |
25 | +#endif | 570 | { |
26 | +#endif | 571 | DisasContext ctx = { }; |
27 | + | 572 | translator_loop(cs, tb, max_insns, pc, host_pc, &hppa_tr_ops, &ctx.base); |
28 | #undef TLADDR_ARGS | 573 | diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c |
29 | #undef DATA64_ARGS | 574 | index XXXXXXX..XXXXXXX 100644 |
30 | #undef IMPL | 575 | --- a/target/i386/tcg/tcg-cpu.c |
31 | diff --git a/tcg/tci.c b/tcg/tci.c | 576 | +++ b/target/i386/tcg/tcg-cpu.c |
32 | index XXXXXXX..XXXXXXX 100644 | 577 | @@ -XXX,XX +XXX,XX @@ static bool x86_debug_check_breakpoint(CPUState *cs) |
33 | --- a/tcg/tci.c | 578 | |
34 | +++ b/tcg/tci.c | 579 | static const TCGCPUOps x86_tcg_ops = { |
35 | @@ -XXX,XX +XXX,XX @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, | 580 | .initialize = tcg_x86_init, |
36 | t1 = tci_read_r32(regs, &tb_ptr); | 581 | + .translate_code = x86_translate_code, |
37 | tci_write_reg32(regs, t0, t1); | 582 | .synchronize_from_tb = x86_cpu_synchronize_from_tb, |
38 | break; | 583 | .restore_state_to_opc = x86_restore_state_to_opc, |
39 | - case INDEX_op_movi_i32: | 584 | .cpu_exec_enter = x86_cpu_exec_enter, |
40 | + case INDEX_op_tci_movi_i32: | 585 | diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c |
41 | t0 = *tb_ptr++; | 586 | index XXXXXXX..XXXXXXX 100644 |
42 | t1 = tci_read_i32(&tb_ptr); | 587 | --- a/target/i386/tcg/translate.c |
43 | tci_write_reg32(regs, t0, t1); | 588 | +++ b/target/i386/tcg/translate.c |
44 | @@ -XXX,XX +XXX,XX @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, | 589 | @@ -XXX,XX +XXX,XX @@ static const TranslatorOps i386_tr_ops = { |
45 | t1 = tci_read_r64(regs, &tb_ptr); | 590 | .tb_stop = i386_tr_tb_stop, |
46 | tci_write_reg64(regs, t0, t1); | 591 | }; |
47 | break; | 592 | |
48 | - case INDEX_op_movi_i64: | 593 | -/* generate intermediate code for basic block 'tb'. */ |
49 | + case INDEX_op_tci_movi_i64: | 594 | -void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int *max_insns, |
50 | t0 = *tb_ptr++; | 595 | - vaddr pc, void *host_pc) |
51 | t1 = tci_read_i64(&tb_ptr); | 596 | +void x86_translate_code(CPUState *cpu, TranslationBlock *tb, |
52 | tci_write_reg64(regs, t0, t1); | 597 | + int *max_insns, vaddr pc, void *host_pc) |
53 | diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc | 598 | { |
54 | index XXXXXXX..XXXXXXX 100644 | 599 | DisasContext dc; |
55 | --- a/tcg/tci/tcg-target.c.inc | 600 | |
56 | +++ b/tcg/tci/tcg-target.c.inc | 601 | diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c |
57 | @@ -XXX,XX +XXX,XX @@ static void tcg_out_movi(TCGContext *s, TCGType type, | 602 | index XXXXXXX..XXXXXXX 100644 |
58 | uint8_t *old_code_ptr = s->code_ptr; | 603 | --- a/target/loongarch/cpu.c |
59 | uint32_t arg32 = arg; | 604 | +++ b/target/loongarch/cpu.c |
60 | if (type == TCG_TYPE_I32 || arg == arg32) { | 605 | @@ -XXX,XX +XXX,XX @@ static void loongarch_cpu_dump_state(CPUState *cs, FILE *f, int flags) |
61 | - tcg_out_op_t(s, INDEX_op_movi_i32); | 606 | |
62 | + tcg_out_op_t(s, INDEX_op_tci_movi_i32); | 607 | static const TCGCPUOps loongarch_tcg_ops = { |
63 | tcg_out_r(s, t0); | 608 | .initialize = loongarch_translate_init, |
64 | tcg_out32(s, arg32); | 609 | + .translate_code = loongarch_translate_code, |
65 | } else { | 610 | .synchronize_from_tb = loongarch_cpu_synchronize_from_tb, |
66 | tcg_debug_assert(type == TCG_TYPE_I64); | 611 | .restore_state_to_opc = loongarch_restore_state_to_opc, |
67 | #if TCG_TARGET_REG_BITS == 64 | 612 | |
68 | - tcg_out_op_t(s, INDEX_op_movi_i64); | 613 | diff --git a/target/loongarch/tcg/translate.c b/target/loongarch/tcg/translate.c |
69 | + tcg_out_op_t(s, INDEX_op_tci_movi_i64); | 614 | index XXXXXXX..XXXXXXX 100644 |
70 | tcg_out_r(s, t0); | 615 | --- a/target/loongarch/tcg/translate.c |
71 | tcg_out64(s, arg); | 616 | +++ b/target/loongarch/tcg/translate.c |
72 | #else | 617 | @@ -XXX,XX +XXX,XX @@ static const TranslatorOps loongarch_tr_ops = { |
618 | .tb_stop = loongarch_tr_tb_stop, | ||
619 | }; | ||
620 | |||
621 | -void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns, | ||
622 | - vaddr pc, void *host_pc) | ||
623 | +void loongarch_translate_code(CPUState *cs, TranslationBlock *tb, | ||
624 | + int *max_insns, vaddr pc, void *host_pc) | ||
625 | { | ||
626 | DisasContext ctx; | ||
627 | |||
628 | diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c | ||
629 | index XXXXXXX..XXXXXXX 100644 | ||
630 | --- a/target/m68k/cpu.c | ||
631 | +++ b/target/m68k/cpu.c | ||
632 | @@ -XXX,XX +XXX,XX @@ static const struct SysemuCPUOps m68k_sysemu_ops = { | ||
633 | |||
634 | static const TCGCPUOps m68k_tcg_ops = { | ||
635 | .initialize = m68k_tcg_init, | ||
636 | + .translate_code = m68k_translate_code, | ||
637 | .restore_state_to_opc = m68k_restore_state_to_opc, | ||
638 | |||
639 | #ifndef CONFIG_USER_ONLY | ||
640 | diff --git a/target/m68k/translate.c b/target/m68k/translate.c | ||
641 | index XXXXXXX..XXXXXXX 100644 | ||
642 | --- a/target/m68k/translate.c | ||
643 | +++ b/target/m68k/translate.c | ||
644 | @@ -XXX,XX +XXX,XX @@ static const TranslatorOps m68k_tr_ops = { | ||
645 | .tb_stop = m68k_tr_tb_stop, | ||
646 | }; | ||
647 | |||
648 | -void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int *max_insns, | ||
649 | - vaddr pc, void *host_pc) | ||
650 | +void m68k_translate_code(CPUState *cpu, TranslationBlock *tb, | ||
651 | + int *max_insns, vaddr pc, void *host_pc) | ||
652 | { | ||
653 | DisasContext dc; | ||
654 | translator_loop(cpu, tb, max_insns, pc, host_pc, &m68k_tr_ops, &dc.base); | ||
655 | diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c | ||
656 | index XXXXXXX..XXXXXXX 100644 | ||
657 | --- a/target/microblaze/cpu.c | ||
658 | +++ b/target/microblaze/cpu.c | ||
659 | @@ -XXX,XX +XXX,XX @@ static const struct SysemuCPUOps mb_sysemu_ops = { | ||
660 | |||
661 | static const TCGCPUOps mb_tcg_ops = { | ||
662 | .initialize = mb_tcg_init, | ||
663 | + .translate_code = mb_translate_code, | ||
664 | .synchronize_from_tb = mb_cpu_synchronize_from_tb, | ||
665 | .restore_state_to_opc = mb_restore_state_to_opc, | ||
666 | |||
667 | diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c | ||
668 | index XXXXXXX..XXXXXXX 100644 | ||
669 | --- a/target/microblaze/translate.c | ||
670 | +++ b/target/microblaze/translate.c | ||
671 | @@ -XXX,XX +XXX,XX @@ static const TranslatorOps mb_tr_ops = { | ||
672 | .tb_stop = mb_tr_tb_stop, | ||
673 | }; | ||
674 | |||
675 | -void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int *max_insns, | ||
676 | - vaddr pc, void *host_pc) | ||
677 | +void mb_translate_code(CPUState *cpu, TranslationBlock *tb, | ||
678 | + int *max_insns, vaddr pc, void *host_pc) | ||
679 | { | ||
680 | DisasContext dc; | ||
681 | translator_loop(cpu, tb, max_insns, pc, host_pc, &mb_tr_ops, &dc.base); | ||
682 | diff --git a/target/mips/cpu.c b/target/mips/cpu.c | ||
683 | index XXXXXXX..XXXXXXX 100644 | ||
684 | --- a/target/mips/cpu.c | ||
685 | +++ b/target/mips/cpu.c | ||
686 | @@ -XXX,XX +XXX,XX @@ static const Property mips_cpu_properties[] = { | ||
687 | #include "hw/core/tcg-cpu-ops.h" | ||
688 | static const TCGCPUOps mips_tcg_ops = { | ||
689 | .initialize = mips_tcg_init, | ||
690 | + .translate_code = mips_translate_code, | ||
691 | .synchronize_from_tb = mips_cpu_synchronize_from_tb, | ||
692 | .restore_state_to_opc = mips_restore_state_to_opc, | ||
693 | |||
694 | diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c | ||
695 | index XXXXXXX..XXXXXXX 100644 | ||
696 | --- a/target/mips/tcg/translate.c | ||
697 | +++ b/target/mips/tcg/translate.c | ||
698 | @@ -XXX,XX +XXX,XX @@ static const TranslatorOps mips_tr_ops = { | ||
699 | .tb_stop = mips_tr_tb_stop, | ||
700 | }; | ||
701 | |||
702 | -void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns, | ||
703 | - vaddr pc, void *host_pc) | ||
704 | +void mips_translate_code(CPUState *cs, TranslationBlock *tb, | ||
705 | + int *max_insns, vaddr pc, void *host_pc) | ||
706 | { | ||
707 | DisasContext ctx; | ||
708 | |||
709 | diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c | ||
710 | index XXXXXXX..XXXXXXX 100644 | ||
711 | --- a/target/openrisc/cpu.c | ||
712 | +++ b/target/openrisc/cpu.c | ||
713 | @@ -XXX,XX +XXX,XX @@ static const struct SysemuCPUOps openrisc_sysemu_ops = { | ||
714 | |||
715 | static const TCGCPUOps openrisc_tcg_ops = { | ||
716 | .initialize = openrisc_translate_init, | ||
717 | + .translate_code = openrisc_translate_code, | ||
718 | .synchronize_from_tb = openrisc_cpu_synchronize_from_tb, | ||
719 | .restore_state_to_opc = openrisc_restore_state_to_opc, | ||
720 | |||
721 | diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c | ||
722 | index XXXXXXX..XXXXXXX 100644 | ||
723 | --- a/target/openrisc/translate.c | ||
724 | +++ b/target/openrisc/translate.c | ||
725 | @@ -XXX,XX +XXX,XX @@ static const TranslatorOps openrisc_tr_ops = { | ||
726 | .tb_stop = openrisc_tr_tb_stop, | ||
727 | }; | ||
728 | |||
729 | -void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns, | ||
730 | - vaddr pc, void *host_pc) | ||
731 | +void openrisc_translate_code(CPUState *cs, TranslationBlock *tb, | ||
732 | + int *max_insns, vaddr pc, void *host_pc) | ||
733 | { | ||
734 | DisasContext ctx; | ||
735 | |||
736 | diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c | ||
737 | index XXXXXXX..XXXXXXX 100644 | ||
738 | --- a/target/ppc/cpu_init.c | ||
739 | +++ b/target/ppc/cpu_init.c | ||
740 | @@ -XXX,XX +XXX,XX @@ static const struct SysemuCPUOps ppc_sysemu_ops = { | ||
741 | |||
742 | static const TCGCPUOps ppc_tcg_ops = { | ||
743 | .initialize = ppc_translate_init, | ||
744 | + .translate_code = ppc_translate_code, | ||
745 | .restore_state_to_opc = ppc_restore_state_to_opc, | ||
746 | |||
747 | #ifdef CONFIG_USER_ONLY | ||
748 | diff --git a/target/ppc/translate.c b/target/ppc/translate.c | ||
749 | index XXXXXXX..XXXXXXX 100644 | ||
750 | --- a/target/ppc/translate.c | ||
751 | +++ b/target/ppc/translate.c | ||
752 | @@ -XXX,XX +XXX,XX @@ static const TranslatorOps ppc_tr_ops = { | ||
753 | .tb_stop = ppc_tr_tb_stop, | ||
754 | }; | ||
755 | |||
756 | -void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns, | ||
757 | - vaddr pc, void *host_pc) | ||
758 | +void ppc_translate_code(CPUState *cs, TranslationBlock *tb, | ||
759 | + int *max_insns, vaddr pc, void *host_pc) | ||
760 | { | ||
761 | DisasContext ctx; | ||
762 | |||
763 | diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c | ||
764 | index XXXXXXX..XXXXXXX 100644 | ||
765 | --- a/target/riscv/tcg/tcg-cpu.c | ||
766 | +++ b/target/riscv/tcg/tcg-cpu.c | ||
767 | @@ -XXX,XX +XXX,XX @@ static void riscv_restore_state_to_opc(CPUState *cs, | ||
768 | |||
769 | static const TCGCPUOps riscv_tcg_ops = { | ||
770 | .initialize = riscv_translate_init, | ||
771 | + .translate_code = riscv_translate_code, | ||
772 | .synchronize_from_tb = riscv_cpu_synchronize_from_tb, | ||
773 | .restore_state_to_opc = riscv_restore_state_to_opc, | ||
774 | |||
775 | diff --git a/target/riscv/translate.c b/target/riscv/translate.c | ||
776 | index XXXXXXX..XXXXXXX 100644 | ||
777 | --- a/target/riscv/translate.c | ||
778 | +++ b/target/riscv/translate.c | ||
779 | @@ -XXX,XX +XXX,XX @@ static const TranslatorOps riscv_tr_ops = { | ||
780 | .tb_stop = riscv_tr_tb_stop, | ||
781 | }; | ||
782 | |||
783 | -void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns, | ||
784 | - vaddr pc, void *host_pc) | ||
785 | +void riscv_translate_code(CPUState *cs, TranslationBlock *tb, | ||
786 | + int *max_insns, vaddr pc, void *host_pc) | ||
787 | { | ||
788 | DisasContext ctx; | ||
789 | |||
790 | diff --git a/target/rx/cpu.c b/target/rx/cpu.c | ||
791 | index XXXXXXX..XXXXXXX 100644 | ||
792 | --- a/target/rx/cpu.c | ||
793 | +++ b/target/rx/cpu.c | ||
794 | @@ -XXX,XX +XXX,XX @@ static const struct SysemuCPUOps rx_sysemu_ops = { | ||
795 | |||
796 | static const TCGCPUOps rx_tcg_ops = { | ||
797 | .initialize = rx_translate_init, | ||
798 | + .translate_code = rx_translate_code, | ||
799 | .synchronize_from_tb = rx_cpu_synchronize_from_tb, | ||
800 | .restore_state_to_opc = rx_restore_state_to_opc, | ||
801 | .tlb_fill = rx_cpu_tlb_fill, | ||
802 | diff --git a/target/rx/translate.c b/target/rx/translate.c | ||
803 | index XXXXXXX..XXXXXXX 100644 | ||
804 | --- a/target/rx/translate.c | ||
805 | +++ b/target/rx/translate.c | ||
806 | @@ -XXX,XX +XXX,XX @@ static const TranslatorOps rx_tr_ops = { | ||
807 | .tb_stop = rx_tr_tb_stop, | ||
808 | }; | ||
809 | |||
810 | -void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns, | ||
811 | - vaddr pc, void *host_pc) | ||
812 | +void rx_translate_code(CPUState *cs, TranslationBlock *tb, | ||
813 | + int *max_insns, vaddr pc, void *host_pc) | ||
814 | { | ||
815 | DisasContext dc; | ||
816 | |||
817 | diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c | ||
818 | index XXXXXXX..XXXXXXX 100644 | ||
819 | --- a/target/s390x/cpu.c | ||
820 | +++ b/target/s390x/cpu.c | ||
821 | @@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPUS390XState *env, vaddr *pc, | ||
822 | |||
823 | static const TCGCPUOps s390_tcg_ops = { | ||
824 | .initialize = s390x_translate_init, | ||
825 | + .translate_code = s390x_translate_code, | ||
826 | .restore_state_to_opc = s390x_restore_state_to_opc, | ||
827 | |||
828 | #ifdef CONFIG_USER_ONLY | ||
829 | diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c | ||
830 | index XXXXXXX..XXXXXXX 100644 | ||
831 | --- a/target/s390x/tcg/translate.c | ||
832 | +++ b/target/s390x/tcg/translate.c | ||
833 | @@ -XXX,XX +XXX,XX @@ static const TranslatorOps s390x_tr_ops = { | ||
834 | .disas_log = s390x_tr_disas_log, | ||
835 | }; | ||
836 | |||
837 | -void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns, | ||
838 | - vaddr pc, void *host_pc) | ||
839 | +void s390x_translate_code(CPUState *cs, TranslationBlock *tb, | ||
840 | + int *max_insns, vaddr pc, void *host_pc) | ||
841 | { | ||
842 | DisasContext dc; | ||
843 | |||
844 | diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c | ||
845 | index XXXXXXX..XXXXXXX 100644 | ||
846 | --- a/target/sh4/cpu.c | ||
847 | +++ b/target/sh4/cpu.c | ||
848 | @@ -XXX,XX +XXX,XX @@ static const struct SysemuCPUOps sh4_sysemu_ops = { | ||
849 | |||
850 | static const TCGCPUOps superh_tcg_ops = { | ||
851 | .initialize = sh4_translate_init, | ||
852 | + .translate_code = sh4_translate_code, | ||
853 | .synchronize_from_tb = superh_cpu_synchronize_from_tb, | ||
854 | .restore_state_to_opc = superh_restore_state_to_opc, | ||
855 | |||
856 | diff --git a/target/sh4/translate.c b/target/sh4/translate.c | ||
857 | index XXXXXXX..XXXXXXX 100644 | ||
858 | --- a/target/sh4/translate.c | ||
859 | +++ b/target/sh4/translate.c | ||
860 | @@ -XXX,XX +XXX,XX @@ static const TranslatorOps sh4_tr_ops = { | ||
861 | .tb_stop = sh4_tr_tb_stop, | ||
862 | }; | ||
863 | |||
864 | -void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns, | ||
865 | - vaddr pc, void *host_pc) | ||
866 | +void sh4_translate_code(CPUState *cs, TranslationBlock *tb, | ||
867 | + int *max_insns, vaddr pc, void *host_pc) | ||
868 | { | ||
869 | DisasContext ctx; | ||
870 | |||
871 | diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c | ||
872 | index XXXXXXX..XXXXXXX 100644 | ||
873 | --- a/target/sparc/cpu.c | ||
874 | +++ b/target/sparc/cpu.c | ||
875 | @@ -XXX,XX +XXX,XX @@ static const struct SysemuCPUOps sparc_sysemu_ops = { | ||
876 | |||
877 | static const TCGCPUOps sparc_tcg_ops = { | ||
878 | .initialize = sparc_tcg_init, | ||
879 | + .translate_code = sparc_translate_code, | ||
880 | .synchronize_from_tb = sparc_cpu_synchronize_from_tb, | ||
881 | .restore_state_to_opc = sparc_restore_state_to_opc, | ||
882 | |||
883 | diff --git a/target/sparc/translate.c b/target/sparc/translate.c | ||
884 | index XXXXXXX..XXXXXXX 100644 | ||
885 | --- a/target/sparc/translate.c | ||
886 | +++ b/target/sparc/translate.c | ||
887 | @@ -XXX,XX +XXX,XX @@ static const TranslatorOps sparc_tr_ops = { | ||
888 | .tb_stop = sparc_tr_tb_stop, | ||
889 | }; | ||
890 | |||
891 | -void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns, | ||
892 | - vaddr pc, void *host_pc) | ||
893 | +void sparc_translate_code(CPUState *cs, TranslationBlock *tb, | ||
894 | + int *max_insns, vaddr pc, void *host_pc) | ||
895 | { | ||
896 | DisasContext dc = {}; | ||
897 | |||
898 | diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c | ||
899 | index XXXXXXX..XXXXXXX 100644 | ||
900 | --- a/target/tricore/cpu.c | ||
901 | +++ b/target/tricore/cpu.c | ||
902 | @@ -XXX,XX +XXX,XX @@ static const struct SysemuCPUOps tricore_sysemu_ops = { | ||
903 | |||
904 | static const TCGCPUOps tricore_tcg_ops = { | ||
905 | .initialize = tricore_tcg_init, | ||
906 | + .translate_code = tricore_translate_code, | ||
907 | .synchronize_from_tb = tricore_cpu_synchronize_from_tb, | ||
908 | .restore_state_to_opc = tricore_restore_state_to_opc, | ||
909 | .tlb_fill = tricore_cpu_tlb_fill, | ||
910 | diff --git a/target/tricore/translate.c b/target/tricore/translate.c | ||
911 | index XXXXXXX..XXXXXXX 100644 | ||
912 | --- a/target/tricore/translate.c | ||
913 | +++ b/target/tricore/translate.c | ||
914 | @@ -XXX,XX +XXX,XX @@ static const TranslatorOps tricore_tr_ops = { | ||
915 | .tb_stop = tricore_tr_tb_stop, | ||
916 | }; | ||
917 | |||
918 | - | ||
919 | -void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns, | ||
920 | - vaddr pc, void *host_pc) | ||
921 | +void tricore_translate_code(CPUState *cs, TranslationBlock *tb, | ||
922 | + int *max_insns, vaddr pc, void *host_pc) | ||
923 | { | ||
924 | DisasContext ctx; | ||
925 | translator_loop(cs, tb, max_insns, pc, host_pc, | ||
926 | diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c | ||
927 | index XXXXXXX..XXXXXXX 100644 | ||
928 | --- a/target/xtensa/cpu.c | ||
929 | +++ b/target/xtensa/cpu.c | ||
930 | @@ -XXX,XX +XXX,XX @@ static const struct SysemuCPUOps xtensa_sysemu_ops = { | ||
931 | |||
932 | static const TCGCPUOps xtensa_tcg_ops = { | ||
933 | .initialize = xtensa_translate_init, | ||
934 | + .translate_code = xtensa_translate_code, | ||
935 | .debug_excp_handler = xtensa_breakpoint_handler, | ||
936 | .restore_state_to_opc = xtensa_restore_state_to_opc, | ||
937 | |||
938 | diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c | ||
939 | index XXXXXXX..XXXXXXX 100644 | ||
940 | --- a/target/xtensa/translate.c | ||
941 | +++ b/target/xtensa/translate.c | ||
942 | @@ -XXX,XX +XXX,XX @@ static const TranslatorOps xtensa_translator_ops = { | ||
943 | .tb_stop = xtensa_tr_tb_stop, | ||
944 | }; | ||
945 | |||
946 | -void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int *max_insns, | ||
947 | - vaddr pc, void *host_pc) | ||
948 | +void xtensa_translate_code(CPUState *cpu, TranslationBlock *tb, | ||
949 | + int *max_insns, vaddr pc, void *host_pc) | ||
950 | { | ||
951 | DisasContext dc = {}; | ||
952 | translator_loop(cpu, tb, max_insns, pc, host_pc, | ||
73 | -- | 953 | -- |
74 | 2.25.1 | 954 | 2.43.0 |
75 | 955 | ||
76 | 956 | diff view generated by jsdifflib |