1 | Arm queue; not huge but I figured I might as well send it out since | 1 | Hi; here's a target-arm pullreq to go in before softfreeze. |
---|---|---|---|
2 | I've been doing code review today and there's no queue of unprocessed | 2 | This is actually pretty much entirely bugfixes (since the |
3 | pullreqs... | 3 | SEL2 timers we implement here are a missing part of a feature |
4 | we claim to already implement). | ||
4 | 5 | ||
5 | thanks | 6 | thanks |
6 | -- PMM | 7 | -- PMM |
7 | 8 | ||
8 | The following changes since commit b3f846c59d8405bb87c551187721fc92ff2f1b92: | 9 | The following changes since commit 98c7362b1efe651327385a25874a73e008c6549e: |
9 | 10 | ||
10 | Merge remote-tracking branch 'remotes/huth-gitlab/tags/pull-request-2021-01-11v2' into staging (2021-01-11 15:15:35 +0000) | 11 | Merge tag 'accel-cpus-20250306' of https://github.com/philmd/qemu into staging (2025-03-07 07:39:49 +0800) |
11 | 12 | ||
12 | are available in the Git repository at: | 13 | are available in the Git repository at: |
13 | 14 | ||
14 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210112 | 15 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20250307 |
15 | 16 | ||
16 | for you to fetch changes up to 19d131395ccaf503db21dadd8257e6dc9fc1d7de: | 17 | for you to fetch changes up to 0ce0739d46983e5e88fa9c149cb305689c9d8c6f: |
17 | 18 | ||
18 | ui/cocoa: Fix openFile: deprecation on Big Sur (2021-01-12 11:38:37 +0000) | 19 | target/rx: Remove TCG_CALL_NO_WG from helpers which write env (2025-03-07 15:03:20 +0000) |
19 | 20 | ||
20 | ---------------------------------------------------------------- | 21 | ---------------------------------------------------------------- |
21 | target-arm queue: | 22 | target-arm queue: |
22 | * arm: Support emulation of ARMv8.4-TTST extension | 23 | * hw/arm/smmu-common: Remove the repeated ttb field |
23 | * arm: Update cpu.h ID register field definitions | 24 | * hw/gpio: npcm7xx: fixup out-of-bounds access |
24 | * arm: Fix breakage of XScale instruction emulation | 25 | * tests/functional/test_arm_sx1: Check whether the serial console is working |
25 | * hw/net/lan9118: Fix RX Status FIFO PEEK value | 26 | * target/arm: Fix minor bugs in generic timer register handling |
26 | * npcm7xx: Add ADC and PWM emulation | 27 | * target/arm: Implement SEL2 physical and virtual timers |
27 | * ui/cocoa: Make "open docs" help menu entry work again when binary | 28 | * target/arm: Correct STRD, LDRD atomicity and fault behaviour |
28 | is run from the build tree | 29 | * target/arm: Make dummy debug registers RAZ, not NOP |
29 | * ui/cocoa: Fix openFile: deprecation on Big Sur | 30 | * util/qemu-timer.c: Don't warp timer from timerlist_rearm() |
30 | * docs: Add qemu-storage-daemon(1) manpage to meson.build | 31 | * include/exec/memop.h: Expand comment for MO_ATOM_SUBALIGN |
31 | * docs: Build and install all the docs in a single manual | 32 | * hw/arm/smmu: Introduce smmu_configs_inv_sid_range() helper |
33 | * target/rx: Set exception vector base to 0xffffff80 | ||
34 | * target/rx: Remove TCG_CALL_NO_WG from helpers which write env | ||
32 | 35 | ||
33 | ---------------------------------------------------------------- | 36 | ---------------------------------------------------------------- |
34 | Hao Wu (6): | 37 | Alex Bennée (4): |
35 | hw/misc: Add clock converter in NPCM7XX CLK module | 38 | target/arm: Implement SEL2 physical and virtual timers |
36 | hw/timer: Refactor NPCM7XX Timer to use CLK clock | 39 | target/arm: Document the architectural names of our GTIMERs |
37 | hw/adc: Add an ADC module for NPCM7XX | 40 | hw/arm: enable secure EL2 timers for virt machine |
38 | hw/misc: Add a PWM module for NPCM7XX | 41 | hw/arm: enable secure EL2 timers for sbsa machine |
39 | hw/misc: Add QTest for NPCM7XX PWM Module | ||
40 | hw/*: Use type casting for SysBusDevice in NPCM7XX | ||
41 | 42 | ||
42 | Leif Lindholm (6): | 43 | JianChunfu (2): |
43 | target/arm: fix typo in cpu.h ID_AA64PFR1 field name | 44 | hw/arm/smmu-common: Remove the repeated ttb field |
44 | target/arm: make ARMCPU.clidr 64-bit | 45 | hw/arm/smmu: Introduce smmu_configs_inv_sid_range() helper |
45 | target/arm: make ARMCPU.ctr 64-bit | ||
46 | target/arm: add descriptions of CLIDR_EL1, CCSIDR_EL1, CTR_EL0 to cpu.h | ||
47 | target/arm: add aarch64 ID register fields to cpu.h | ||
48 | target/arm: add aarch32 ID register fields to cpu.h | ||
49 | 46 | ||
50 | Peter Maydell (5): | 47 | Keith Packard (2): |
51 | docs: Add qemu-storage-daemon(1) manpage to meson.build | 48 | target/rx: Set exception vector base to 0xffffff80 |
52 | docs: Build and install all the docs in a single manual | 49 | target/rx: Remove TCG_CALL_NO_WG from helpers which write env |
53 | target/arm: Don't decode insns in the XScale/iWMMXt space as cp insns | ||
54 | hw/net/lan9118: Fix RX Status FIFO PEEK value | ||
55 | hw/net/lan9118: Add symbolic constants for register offsets | ||
56 | 50 | ||
57 | Roman Bolshakov (2): | 51 | Patrick Venture (1): |
58 | ui/cocoa: Update path to docs in build tree | 52 | hw/gpio: npcm7xx: fixup out-of-bounds access |
59 | ui/cocoa: Fix openFile: deprecation on Big Sur | ||
60 | 53 | ||
61 | Rémi Denis-Courmont (2): | 54 | Peter Maydell (11): |
62 | target/arm: ARMv8.4-TTST extension | 55 | target/arm: Apply correct timer offset when calculating deadlines |
63 | target/arm: enable Small Translation tables in max CPU | 56 | target/arm: Don't apply CNTVOFF_EL2 for EL2_VIRT timer |
57 | target/arm: Make CNTPS_* UNDEF from Secure EL1 when Secure EL2 is enabled | ||
58 | target/arm: Always apply CNTVOFF_EL2 for CNTV_TVAL_EL02 accesses | ||
59 | target/arm: Refactor handling of timer offset for direct register accesses | ||
60 | target/arm: Correct LDRD atomicity and fault behaviour | ||
61 | target/arm: Correct STRD atomicity | ||
62 | target/arm: Drop unused address_offset from op_addr_{rr, ri}_post() | ||
63 | target/arm: Make dummy debug registers RAZ, not NOP | ||
64 | util/qemu-timer.c: Don't warp timer from timerlist_rearm() | ||
65 | include/exec/memop.h: Expand comment for MO_ATOM_SUBALIGN | ||
64 | 66 | ||
65 | docs/conf.py | 46 ++- | 67 | Thomas Huth (1): |
66 | docs/devel/conf.py | 15 - | 68 | tests/functional/test_arm_sx1: Check whether the serial console is working |
67 | docs/index.html.in | 17 - | ||
68 | docs/interop/conf.py | 28 -- | ||
69 | docs/meson.build | 65 ++-- | ||
70 | docs/specs/conf.py | 16 - | ||
71 | docs/system/arm/nuvoton.rst | 4 +- | ||
72 | docs/system/conf.py | 28 -- | ||
73 | docs/tools/conf.py | 37 -- | ||
74 | docs/user/conf.py | 15 - | ||
75 | meson.build | 1 + | ||
76 | hw/adc/trace.h | 1 + | ||
77 | include/hw/adc/npcm7xx_adc.h | 69 ++++ | ||
78 | include/hw/arm/npcm7xx.h | 4 + | ||
79 | include/hw/misc/npcm7xx_clk.h | 146 ++++++- | ||
80 | include/hw/misc/npcm7xx_pwm.h | 105 +++++ | ||
81 | include/hw/timer/npcm7xx_timer.h | 1 + | ||
82 | target/arm/cpu.h | 85 ++++- | ||
83 | hw/adc/npcm7xx_adc.c | 301 +++++++++++++++ | ||
84 | hw/arm/npcm7xx.c | 55 ++- | ||
85 | hw/arm/npcm7xx_boards.c | 2 +- | ||
86 | hw/mem/npcm7xx_mc.c | 2 +- | ||
87 | hw/misc/npcm7xx_clk.c | 807 ++++++++++++++++++++++++++++++++++++++- | ||
88 | hw/misc/npcm7xx_gcr.c | 2 +- | ||
89 | hw/misc/npcm7xx_pwm.c | 550 ++++++++++++++++++++++++++ | ||
90 | hw/misc/npcm7xx_rng.c | 2 +- | ||
91 | hw/net/lan9118.c | 26 +- | ||
92 | hw/nvram/npcm7xx_otp.c | 2 +- | ||
93 | hw/ssi/npcm7xx_fiu.c | 2 +- | ||
94 | hw/timer/npcm7xx_timer.c | 39 +- | ||
95 | target/arm/cpu64.c | 1 + | ||
96 | target/arm/helper.c | 15 +- | ||
97 | target/arm/translate.c | 7 + | ||
98 | tests/qtest/npcm7xx_adc-test.c | 377 ++++++++++++++++++ | ||
99 | tests/qtest/npcm7xx_pwm-test.c | 490 ++++++++++++++++++++++++ | ||
100 | hw/adc/meson.build | 1 + | ||
101 | hw/adc/trace-events | 5 + | ||
102 | hw/misc/meson.build | 1 + | ||
103 | hw/misc/trace-events | 6 + | ||
104 | tests/qtest/meson.build | 4 +- | ||
105 | ui/cocoa.m | 7 +- | ||
106 | 41 files changed, 3124 insertions(+), 263 deletions(-) | ||
107 | delete mode 100644 docs/devel/conf.py | ||
108 | delete mode 100644 docs/index.html.in | ||
109 | delete mode 100644 docs/interop/conf.py | ||
110 | delete mode 100644 docs/specs/conf.py | ||
111 | delete mode 100644 docs/system/conf.py | ||
112 | delete mode 100644 docs/tools/conf.py | ||
113 | delete mode 100644 docs/user/conf.py | ||
114 | create mode 100644 hw/adc/trace.h | ||
115 | create mode 100644 include/hw/adc/npcm7xx_adc.h | ||
116 | create mode 100644 include/hw/misc/npcm7xx_pwm.h | ||
117 | create mode 100644 hw/adc/npcm7xx_adc.c | ||
118 | create mode 100644 hw/misc/npcm7xx_pwm.c | ||
119 | create mode 100644 tests/qtest/npcm7xx_adc-test.c | ||
120 | create mode 100644 tests/qtest/npcm7xx_pwm-test.c | ||
121 | create mode 100644 hw/adc/trace-events | ||
122 | 69 | ||
70 | MAINTAINERS | 1 + | ||
71 | hw/arm/smmu-internal.h | 5 - | ||
72 | include/exec/memop.h | 8 +- | ||
73 | include/hw/arm/bsa.h | 2 + | ||
74 | include/hw/arm/smmu-common.h | 7 +- | ||
75 | target/arm/cpu.h | 2 + | ||
76 | target/arm/gtimer.h | 14 +- | ||
77 | target/arm/internals.h | 5 +- | ||
78 | target/rx/helper.h | 34 ++-- | ||
79 | hw/arm/sbsa-ref.c | 2 + | ||
80 | hw/arm/smmu-common.c | 21 +++ | ||
81 | hw/arm/smmuv3.c | 19 +-- | ||
82 | hw/arm/virt.c | 2 + | ||
83 | hw/gpio/npcm7xx_gpio.c | 3 +- | ||
84 | target/arm/cpu.c | 4 + | ||
85 | target/arm/debug_helper.c | 7 +- | ||
86 | target/arm/helper.c | 324 ++++++++++++++++++++++++++++++++------- | ||
87 | target/arm/tcg/op_helper.c | 8 +- | ||
88 | target/arm/tcg/translate.c | 147 +++++++++++------- | ||
89 | target/rx/helper.c | 2 +- | ||
90 | util/qemu-timer.c | 4 - | ||
91 | hw/arm/trace-events | 3 +- | ||
92 | tests/functional/test_arm_sx1.py | 7 +- | ||
93 | 23 files changed, 455 insertions(+), 176 deletions(-) | ||
94 | diff view generated by jsdifflib |
1 | From: Roman Bolshakov <r.bolshakov@yadro.com> | 1 | From: JianChunfu <jansef.jian@hj-micro.com> |
---|---|---|---|
2 | 2 | ||
3 | ui/cocoa.m:1188:44: warning: 'openFile:' is deprecated: first deprecated in macOS 11.0 - Use -[NSWorkspace openURL:] instead. | 3 | SMMUTransCfg->ttb is never used in QEMU, TT base address |
4 | [-Wdeprecated-declarations] | 4 | can be accessed by SMMUTransCfg->tt[i]->ttb. |
5 | if ([[NSWorkspace sharedWorkspace] openFile: full_file_path] == YES) { | ||
6 | ^ | ||
7 | /Library/Developer/CommandLineTools/SDKs/MacOSX.sdk/System/Library/Frameworks/AppKit.framework/Headers/NSWorkspace.h:350:1: note: | ||
8 | 'openFile:' has been explicitly marked deprecated here | ||
9 | - (BOOL)openFile:(NSString *)fullPath API_DEPRECATED("Use -[NSWorkspace openURL:] instead.", macos(10.0, 11.0)); | ||
10 | ^ | ||
11 | 5 | ||
12 | Signed-off-by: Roman Bolshakov <r.bolshakov@yadro.com> | 6 | Signed-off-by: JianChunfu <jansef.jian@hj-micro.com> |
13 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 7 | Reviewed-by: Eric Auger <eric.auger@redhat.com> |
14 | Message-id: 20210102150718.47618-1-r.bolshakov@yadro.com | 8 | Message-id: 20250221031034.69822-1-jansef.jian@hj-micro.com |
15 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
16 | --- | 10 | --- |
17 | ui/cocoa.m | 5 ++++- | 11 | include/hw/arm/smmu-common.h | 1 - |
18 | 1 file changed, 4 insertions(+), 1 deletion(-) | 12 | 1 file changed, 1 deletion(-) |
19 | 13 | ||
20 | diff --git a/ui/cocoa.m b/ui/cocoa.m | 14 | diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h |
21 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
22 | --- a/ui/cocoa.m | 16 | --- a/include/hw/arm/smmu-common.h |
23 | +++ b/ui/cocoa.m | 17 | +++ b/include/hw/arm/smmu-common.h |
24 | @@ -XXX,XX +XXX,XX @@ QemuCocoaView *cocoaView; | 18 | @@ -XXX,XX +XXX,XX @@ typedef struct SMMUTransCfg { |
25 | /* Where to look for local files */ | 19 | /* Used by stage-1 only. */ |
26 | NSString *path_array[] = {@"../share/doc/qemu/", @"../doc/qemu/", @"docs/"}; | 20 | bool aa64; /* arch64 or aarch32 translation table */ |
27 | NSString *full_file_path; | 21 | bool record_faults; /* record fault events */ |
28 | + NSURL *full_file_url; | 22 | - uint64_t ttb; /* TT base address */ |
29 | 23 | uint8_t oas; /* output address width */ | |
30 | /* iterate thru the possible paths until the file is found */ | 24 | uint8_t tbi; /* Top Byte Ignore */ |
31 | int index; | 25 | int asid; |
32 | @@ -XXX,XX +XXX,XX @@ QemuCocoaView *cocoaView; | ||
33 | full_file_path = [full_file_path stringByDeletingLastPathComponent]; | ||
34 | full_file_path = [NSString stringWithFormat: @"%@/%@%@", full_file_path, | ||
35 | path_array[index], filename]; | ||
36 | - if ([[NSWorkspace sharedWorkspace] openFile: full_file_path] == YES) { | ||
37 | + full_file_url = [NSURL fileURLWithPath: full_file_path | ||
38 | + isDirectory: false]; | ||
39 | + if ([[NSWorkspace sharedWorkspace] openURL: full_file_url] == YES) { | ||
40 | return; | ||
41 | } | ||
42 | } | ||
43 | -- | 26 | -- |
44 | 2.20.1 | 27 | 2.43.0 |
45 | |||
46 | diff view generated by jsdifflib |
1 | From: Leif Lindholm <leif@nuviainc.com> | 1 | From: Patrick Venture <venture@google.com> |
---|---|---|---|
2 | 2 | ||
3 | Add entries present in ARM DDI 0487F.c (August 2020). | 3 | The reg isn't validated to be a possible register before |
4 | it's dereferenced for one case. The mmio space registered | ||
5 | for the gpio device is 4KiB but there aren't that many | ||
6 | registers in the struct. | ||
4 | 7 | ||
5 | Signed-off-by: Leif Lindholm <leif@nuviainc.com> | 8 | Cc: qemu-stable@nongnu.org |
6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Fixes: 526dbbe0874 ("hw/gpio: Add GPIO model for Nuvoton NPCM7xx") |
7 | Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com> | 10 | Signed-off-by: Patrick Venture <venture@google.com> |
8 | Message-id: 20210108185154.8108-7-leif@nuviainc.com | 11 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
12 | Message-id: 20250226024603.493148-1-venture@google.com | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
10 | --- | 14 | --- |
11 | target/arm/cpu.h | 28 ++++++++++++++++++++++++++++ | 15 | hw/gpio/npcm7xx_gpio.c | 3 +-- |
12 | 1 file changed, 28 insertions(+) | 16 | 1 file changed, 1 insertion(+), 2 deletions(-) |
13 | 17 | ||
14 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | 18 | diff --git a/hw/gpio/npcm7xx_gpio.c b/hw/gpio/npcm7xx_gpio.c |
15 | index XXXXXXX..XXXXXXX 100644 | 19 | index XXXXXXX..XXXXXXX 100644 |
16 | --- a/target/arm/cpu.h | 20 | --- a/hw/gpio/npcm7xx_gpio.c |
17 | +++ b/target/arm/cpu.h | 21 | +++ b/hw/gpio/npcm7xx_gpio.c |
18 | @@ -XXX,XX +XXX,XX @@ FIELD(ID_ISAR6, DP, 4, 4) | 22 | @@ -XXX,XX +XXX,XX @@ static void npcm7xx_gpio_regs_write(void *opaque, hwaddr addr, uint64_t v, |
19 | FIELD(ID_ISAR6, FHM, 8, 4) | 23 | return; |
20 | FIELD(ID_ISAR6, SB, 12, 4) | 24 | } |
21 | FIELD(ID_ISAR6, SPECRES, 16, 4) | 25 | |
22 | +FIELD(ID_ISAR6, BF16, 20, 4) | 26 | - diff = s->regs[reg] ^ value; |
23 | +FIELD(ID_ISAR6, I8MM, 24, 4) | 27 | - |
24 | 28 | switch (reg) { | |
25 | FIELD(ID_MMFR0, VMSA, 0, 4) | 29 | case NPCM7XX_GPIO_TLOCK1: |
26 | FIELD(ID_MMFR0, PMSA, 4, 4) | 30 | case NPCM7XX_GPIO_TLOCK2: |
27 | @@ -XXX,XX +XXX,XX @@ FIELD(ID_MMFR0, AUXREG, 20, 4) | 31 | @@ -XXX,XX +XXX,XX @@ static void npcm7xx_gpio_regs_write(void *opaque, hwaddr addr, uint64_t v, |
28 | FIELD(ID_MMFR0, FCSE, 24, 4) | 32 | case NPCM7XX_GPIO_PU: |
29 | FIELD(ID_MMFR0, INNERSHR, 28, 4) | 33 | case NPCM7XX_GPIO_PD: |
30 | 34 | case NPCM7XX_GPIO_IEM: | |
31 | +FIELD(ID_MMFR1, L1HVDVA, 0, 4) | 35 | + diff = s->regs[reg] ^ value; |
32 | +FIELD(ID_MMFR1, L1UNIVA, 4, 4) | 36 | s->regs[reg] = value; |
33 | +FIELD(ID_MMFR1, L1HVDSW, 8, 4) | 37 | npcm7xx_gpio_update_pins(s, diff); |
34 | +FIELD(ID_MMFR1, L1UNISW, 12, 4) | 38 | break; |
35 | +FIELD(ID_MMFR1, L1HVD, 16, 4) | ||
36 | +FIELD(ID_MMFR1, L1UNI, 20, 4) | ||
37 | +FIELD(ID_MMFR1, L1TSTCLN, 24, 4) | ||
38 | +FIELD(ID_MMFR1, BPRED, 28, 4) | ||
39 | + | ||
40 | +FIELD(ID_MMFR2, L1HVDFG, 0, 4) | ||
41 | +FIELD(ID_MMFR2, L1HVDBG, 4, 4) | ||
42 | +FIELD(ID_MMFR2, L1HVDRNG, 8, 4) | ||
43 | +FIELD(ID_MMFR2, HVDTLB, 12, 4) | ||
44 | +FIELD(ID_MMFR2, UNITLB, 16, 4) | ||
45 | +FIELD(ID_MMFR2, MEMBARR, 20, 4) | ||
46 | +FIELD(ID_MMFR2, WFISTALL, 24, 4) | ||
47 | +FIELD(ID_MMFR2, HWACCFLG, 28, 4) | ||
48 | + | ||
49 | FIELD(ID_MMFR3, CMAINTVA, 0, 4) | ||
50 | FIELD(ID_MMFR3, CMAINTSW, 4, 4) | ||
51 | FIELD(ID_MMFR3, BPMAINT, 8, 4) | ||
52 | @@ -XXX,XX +XXX,XX @@ FIELD(ID_MMFR4, LSM, 20, 4) | ||
53 | FIELD(ID_MMFR4, CCIDX, 24, 4) | ||
54 | FIELD(ID_MMFR4, EVT, 28, 4) | ||
55 | |||
56 | +FIELD(ID_MMFR5, ETS, 0, 4) | ||
57 | + | ||
58 | FIELD(ID_PFR0, STATE0, 0, 4) | ||
59 | FIELD(ID_PFR0, STATE1, 4, 4) | ||
60 | FIELD(ID_PFR0, STATE2, 8, 4) | ||
61 | @@ -XXX,XX +XXX,XX @@ FIELD(ID_PFR1, SEC_FRAC, 20, 4) | ||
62 | FIELD(ID_PFR1, VIRT_FRAC, 24, 4) | ||
63 | FIELD(ID_PFR1, GIC, 28, 4) | ||
64 | |||
65 | +FIELD(ID_PFR2, CSV3, 0, 4) | ||
66 | +FIELD(ID_PFR2, SSBS, 4, 4) | ||
67 | +FIELD(ID_PFR2, RAS_FRAC, 8, 4) | ||
68 | + | ||
69 | FIELD(ID_AA64ISAR0, AES, 4, 4) | ||
70 | FIELD(ID_AA64ISAR0, SHA1, 8, 4) | ||
71 | FIELD(ID_AA64ISAR0, SHA2, 12, 4) | ||
72 | @@ -XXX,XX +XXX,XX @@ FIELD(ID_DFR0, MPROFDBG, 20, 4) | ||
73 | FIELD(ID_DFR0, PERFMON, 24, 4) | ||
74 | FIELD(ID_DFR0, TRACEFILT, 28, 4) | ||
75 | |||
76 | +FIELD(ID_DFR1, MTPMU, 0, 4) | ||
77 | + | ||
78 | FIELD(DBGDIDR, SE_IMP, 12, 1) | ||
79 | FIELD(DBGDIDR, NSUHD_IMP, 14, 1) | ||
80 | FIELD(DBGDIDR, VERSION, 16, 4) | ||
81 | -- | 39 | -- |
82 | 2.20.1 | 40 | 2.43.0 |
83 | 41 | ||
84 | 42 | diff view generated by jsdifflib |
1 | From: Leif Lindholm <leif@nuviainc.com> | 1 | From: Thomas Huth <thuth@redhat.com> |
---|---|---|---|
2 | 2 | ||
3 | Add entries present in ARM DDI 0487F.c (August 2020). | 3 | The kernel that is used in the sx1 test prints the usual Linux log |
4 | onto the serial console, but this test currently ignores it. To | ||
5 | make sure that the serial device is working properly, let's check | ||
6 | for some strings in the output here. | ||
4 | 7 | ||
5 | Signed-off-by: Leif Lindholm <leif@nuviainc.com> | 8 | While we're at it, also add the test to the corresponding section |
6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 9 | in the MAINTAINERS file. |
7 | Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com> | 10 | |
8 | Message-id: 20210108185154.8108-6-leif@nuviainc.com | 11 | Signed-off-by: Thomas Huth <thuth@redhat.com> |
12 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
13 | Message-id: 20250226104833.1176253-1-thuth@redhat.com | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 14 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
10 | --- | 15 | --- |
11 | target/arm/cpu.h | 15 +++++++++++++++ | 16 | MAINTAINERS | 1 + |
12 | 1 file changed, 15 insertions(+) | 17 | tests/functional/test_arm_sx1.py | 7 ++++--- |
18 | 2 files changed, 5 insertions(+), 3 deletions(-) | ||
13 | 19 | ||
14 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | 20 | diff --git a/MAINTAINERS b/MAINTAINERS |
15 | index XXXXXXX..XXXXXXX 100644 | 21 | index XXXXXXX..XXXXXXX 100644 |
16 | --- a/target/arm/cpu.h | 22 | --- a/MAINTAINERS |
17 | +++ b/target/arm/cpu.h | 23 | +++ b/MAINTAINERS |
18 | @@ -XXX,XX +XXX,XX @@ FIELD(ID_AA64ISAR1, GPI, 28, 4) | 24 | @@ -XXX,XX +XXX,XX @@ S: Maintained |
19 | FIELD(ID_AA64ISAR1, FRINTTS, 32, 4) | 25 | F: hw/*/omap* |
20 | FIELD(ID_AA64ISAR1, SB, 36, 4) | 26 | F: include/hw/arm/omap.h |
21 | FIELD(ID_AA64ISAR1, SPECRES, 40, 4) | 27 | F: docs/system/arm/sx1.rst |
22 | +FIELD(ID_AA64ISAR1, BF16, 44, 4) | 28 | +F: tests/functional/test_arm_sx1.py |
23 | +FIELD(ID_AA64ISAR1, DGH, 48, 4) | 29 | |
24 | +FIELD(ID_AA64ISAR1, I8MM, 52, 4) | 30 | IPack |
25 | 31 | M: Alberto Garcia <berto@igalia.com> | |
26 | FIELD(ID_AA64PFR0, EL0, 0, 4) | 32 | diff --git a/tests/functional/test_arm_sx1.py b/tests/functional/test_arm_sx1.py |
27 | FIELD(ID_AA64PFR0, EL1, 4, 4) | 33 | index XXXXXXX..XXXXXXX 100755 |
28 | @@ -XXX,XX +XXX,XX @@ FIELD(ID_AA64PFR0, ADVSIMD, 20, 4) | 34 | --- a/tests/functional/test_arm_sx1.py |
29 | FIELD(ID_AA64PFR0, GIC, 24, 4) | 35 | +++ b/tests/functional/test_arm_sx1.py |
30 | FIELD(ID_AA64PFR0, RAS, 28, 4) | 36 | @@ -XXX,XX +XXX,XX @@ def test_arm_sx1_initrd(self): |
31 | FIELD(ID_AA64PFR0, SVE, 32, 4) | 37 | self.vm.add_args('-append', f'kunit.enable=0 rdinit=/sbin/init {self.CONSOLE_ARGS}') |
32 | +FIELD(ID_AA64PFR0, SEL2, 36, 4) | 38 | self.vm.add_args('-no-reboot') |
33 | +FIELD(ID_AA64PFR0, MPAM, 40, 4) | 39 | self.launch_kernel(zimage_path, |
34 | +FIELD(ID_AA64PFR0, AMU, 44, 4) | 40 | - initrd=initrd_path) |
35 | +FIELD(ID_AA64PFR0, DIT, 48, 4) | 41 | + initrd=initrd_path, |
36 | +FIELD(ID_AA64PFR0, CSV2, 56, 4) | 42 | + wait_for='Boot successful') |
37 | +FIELD(ID_AA64PFR0, CSV3, 60, 4) | 43 | self.vm.wait(timeout=120) |
38 | 44 | ||
39 | FIELD(ID_AA64PFR1, BT, 0, 4) | 45 | def test_arm_sx1_sd(self): |
40 | FIELD(ID_AA64PFR1, SSBS, 4, 4) | 46 | @@ -XXX,XX +XXX,XX @@ def test_arm_sx1_sd(self): |
41 | FIELD(ID_AA64PFR1, MTE, 8, 4) | 47 | self.vm.add_args('-no-reboot') |
42 | FIELD(ID_AA64PFR1, RAS_FRAC, 12, 4) | 48 | self.vm.add_args('-snapshot') |
43 | +FIELD(ID_AA64PFR1, MPAM_FRAC, 16, 4) | 49 | self.vm.add_args('-drive', f'format=raw,if=sd,file={sd_fs_path}') |
44 | 50 | - self.launch_kernel(zimage_path) | |
45 | FIELD(ID_AA64MMFR0, PARANGE, 0, 4) | 51 | + self.launch_kernel(zimage_path, wait_for='Boot successful') |
46 | FIELD(ID_AA64MMFR0, ASIDBITS, 4, 4) | 52 | self.vm.wait(timeout=120) |
47 | @@ -XXX,XX +XXX,XX @@ FIELD(ID_AA64MMFR0, TGRAN16_2, 32, 4) | 53 | |
48 | FIELD(ID_AA64MMFR0, TGRAN64_2, 36, 4) | 54 | def test_arm_sx1_flash(self): |
49 | FIELD(ID_AA64MMFR0, TGRAN4_2, 40, 4) | 55 | @@ -XXX,XX +XXX,XX @@ def test_arm_sx1_flash(self): |
50 | FIELD(ID_AA64MMFR0, EXS, 44, 4) | 56 | self.vm.add_args('-no-reboot') |
51 | +FIELD(ID_AA64MMFR0, FGT, 56, 4) | 57 | self.vm.add_args('-snapshot') |
52 | +FIELD(ID_AA64MMFR0, ECV, 60, 4) | 58 | self.vm.add_args('-drive', f'format=raw,if=pflash,file={flash_path}') |
53 | 59 | - self.launch_kernel(zimage_path) | |
54 | FIELD(ID_AA64MMFR1, HAFDBS, 0, 4) | 60 | + self.launch_kernel(zimage_path, wait_for='Boot successful') |
55 | FIELD(ID_AA64MMFR1, VMIDBITS, 4, 4) | 61 | self.vm.wait(timeout=120) |
56 | @@ -XXX,XX +XXX,XX @@ FIELD(ID_AA64MMFR1, LO, 16, 4) | 62 | |
57 | FIELD(ID_AA64MMFR1, PAN, 20, 4) | 63 | if __name__ == '__main__': |
58 | FIELD(ID_AA64MMFR1, SPECSEI, 24, 4) | ||
59 | FIELD(ID_AA64MMFR1, XNX, 28, 4) | ||
60 | +FIELD(ID_AA64MMFR1, TWED, 32, 4) | ||
61 | +FIELD(ID_AA64MMFR1, ETS, 36, 4) | ||
62 | |||
63 | FIELD(ID_AA64MMFR2, CNP, 0, 4) | ||
64 | FIELD(ID_AA64MMFR2, UAO, 4, 4) | ||
65 | @@ -XXX,XX +XXX,XX @@ FIELD(ID_AA64DFR0, CTX_CMPS, 28, 4) | ||
66 | FIELD(ID_AA64DFR0, PMSVER, 32, 4) | ||
67 | FIELD(ID_AA64DFR0, DOUBLELOCK, 36, 4) | ||
68 | FIELD(ID_AA64DFR0, TRACEFILT, 40, 4) | ||
69 | +FIELD(ID_AA64DFR0, MTPMU, 48, 4) | ||
70 | |||
71 | FIELD(ID_DFR0, COPDBG, 0, 4) | ||
72 | FIELD(ID_DFR0, COPSDBG, 4, 4) | ||
73 | -- | 64 | -- |
74 | 2.20.1 | 65 | 2.43.0 |
75 | 66 | ||
76 | 67 | diff view generated by jsdifflib |
1 | From: Hao Wu <wuhaotsh@google.com> | 1 | When we are calculating timer deadlines, the correct definition of |
---|---|---|---|
2 | whether or not to apply an offset to the physical count is described | ||
3 | in the Arm ARM DDI4087 rev L.a section D12.2.4.1. This is different | ||
4 | from when the offset should be applied for a direct read of the | ||
5 | counter sysreg. | ||
2 | 6 | ||
3 | The PWM module is part of NPCM7XX module. Each NPCM7XX module has two | 7 | We got this right for the EL1 physical timer and for the EL1 virtual |
4 | identical PWM modules. Each module contains 4 PWM entries. Each PWM has | 8 | timer, but got all the rest wrong: they should be using a zero offset |
5 | two outputs: frequency and duty_cycle. Both are computed using inputs | 9 | always. |
6 | from software side. | ||
7 | 10 | ||
8 | This module does not model detail pulse signals since it is expensive. | 11 | Factor the offset calculation out into a function that has a comment |
9 | It also does not model interrupts and watchdogs that are dependant on | 12 | documenting exactly which offset it is calculating and which gets the |
10 | the detail models. The interfaces for these are left in the module so | 13 | HYP, SEC, and HYPVIRT cases right. |
11 | that anyone in need for these functionalities can implement on their | ||
12 | own. | ||
13 | 14 | ||
14 | The user can read the duty cycle and frequency using qom-get command. | 15 | Cc: qemu-stable@nongnu.org |
16 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
17 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | ||
18 | Message-id: 20250204125009.2281315-2-peter.maydell@linaro.org | ||
19 | --- | ||
20 | target/arm/helper.c | 29 +++++++++++++++++++++++++++-- | ||
21 | 1 file changed, 27 insertions(+), 2 deletions(-) | ||
15 | 22 | ||
16 | Reviewed-by: Havard Skinnemoen <hskinnemoen@google.com> | 23 | diff --git a/target/arm/helper.c b/target/arm/helper.c |
17 | Reviewed-by: Tyrone Ting <kfting@nuvoton.com> | ||
18 | Signed-off-by: Hao Wu <wuhaotsh@google.com> | ||
19 | Message-id: 20210108190945.949196-5-wuhaotsh@google.com | ||
20 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
21 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
22 | --- | ||
23 | docs/system/arm/nuvoton.rst | 2 +- | ||
24 | include/hw/arm/npcm7xx.h | 2 + | ||
25 | include/hw/misc/npcm7xx_pwm.h | 105 +++++++ | ||
26 | hw/arm/npcm7xx.c | 26 +- | ||
27 | hw/misc/npcm7xx_pwm.c | 550 ++++++++++++++++++++++++++++++++++ | ||
28 | hw/misc/meson.build | 1 + | ||
29 | hw/misc/trace-events | 6 + | ||
30 | 7 files changed, 689 insertions(+), 3 deletions(-) | ||
31 | create mode 100644 include/hw/misc/npcm7xx_pwm.h | ||
32 | create mode 100644 hw/misc/npcm7xx_pwm.c | ||
33 | |||
34 | diff --git a/docs/system/arm/nuvoton.rst b/docs/system/arm/nuvoton.rst | ||
35 | index XXXXXXX..XXXXXXX 100644 | 24 | index XXXXXXX..XXXXXXX 100644 |
36 | --- a/docs/system/arm/nuvoton.rst | 25 | --- a/target/arm/helper.c |
37 | +++ b/docs/system/arm/nuvoton.rst | 26 | +++ b/target/arm/helper.c |
38 | @@ -XXX,XX +XXX,XX @@ Supported devices | 27 | @@ -XXX,XX +XXX,XX @@ static uint64_t gt_phys_cnt_offset(CPUARMState *env) |
39 | * USB host (USBH) | 28 | return gt_phys_raw_cnt_offset(env); |
40 | * GPIO controller | ||
41 | * Analog to Digital Converter (ADC) | ||
42 | + * Pulse Width Modulation (PWM) | ||
43 | |||
44 | Missing devices | ||
45 | --------------- | ||
46 | @@ -XXX,XX +XXX,XX @@ Missing devices | ||
47 | * Peripheral SPI controller (PSPI) | ||
48 | * SD/MMC host | ||
49 | * PECI interface | ||
50 | - * Pulse Width Modulation (PWM) | ||
51 | * Tachometer | ||
52 | * PCI and PCIe root complex and bridges | ||
53 | * VDM and MCTP support | ||
54 | diff --git a/include/hw/arm/npcm7xx.h b/include/hw/arm/npcm7xx.h | ||
55 | index XXXXXXX..XXXXXXX 100644 | ||
56 | --- a/include/hw/arm/npcm7xx.h | ||
57 | +++ b/include/hw/arm/npcm7xx.h | ||
58 | @@ -XXX,XX +XXX,XX @@ | ||
59 | #include "hw/mem/npcm7xx_mc.h" | ||
60 | #include "hw/misc/npcm7xx_clk.h" | ||
61 | #include "hw/misc/npcm7xx_gcr.h" | ||
62 | +#include "hw/misc/npcm7xx_pwm.h" | ||
63 | #include "hw/misc/npcm7xx_rng.h" | ||
64 | #include "hw/nvram/npcm7xx_otp.h" | ||
65 | #include "hw/timer/npcm7xx_timer.h" | ||
66 | @@ -XXX,XX +XXX,XX @@ typedef struct NPCM7xxState { | ||
67 | NPCM7xxCLKState clk; | ||
68 | NPCM7xxTimerCtrlState tim[3]; | ||
69 | NPCM7xxADCState adc; | ||
70 | + NPCM7xxPWMState pwm[2]; | ||
71 | NPCM7xxOTPState key_storage; | ||
72 | NPCM7xxOTPState fuse_array; | ||
73 | NPCM7xxMCState mc; | ||
74 | diff --git a/include/hw/misc/npcm7xx_pwm.h b/include/hw/misc/npcm7xx_pwm.h | ||
75 | new file mode 100644 | ||
76 | index XXXXXXX..XXXXXXX | ||
77 | --- /dev/null | ||
78 | +++ b/include/hw/misc/npcm7xx_pwm.h | ||
79 | @@ -XXX,XX +XXX,XX @@ | ||
80 | +/* | ||
81 | + * Nuvoton NPCM7xx PWM Module | ||
82 | + * | ||
83 | + * Copyright 2020 Google LLC | ||
84 | + * | ||
85 | + * This program is free software; you can redistribute it and/or modify it | ||
86 | + * under the terms of the GNU General Public License as published by the | ||
87 | + * Free Software Foundation; either version 2 of the License, or | ||
88 | + * (at your option) any later version. | ||
89 | + * | ||
90 | + * This program is distributed in the hope that it will be useful, but WITHOUT | ||
91 | + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
92 | + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | ||
93 | + * for more details. | ||
94 | + */ | ||
95 | +#ifndef NPCM7XX_PWM_H | ||
96 | +#define NPCM7XX_PWM_H | ||
97 | + | ||
98 | +#include "hw/clock.h" | ||
99 | +#include "hw/sysbus.h" | ||
100 | +#include "hw/irq.h" | ||
101 | + | ||
102 | +/* Each PWM module holds 4 PWM channels. */ | ||
103 | +#define NPCM7XX_PWM_PER_MODULE 4 | ||
104 | + | ||
105 | +/* | ||
106 | + * Number of registers in one pwm module. Don't change this without increasing | ||
107 | + * the version_id in vmstate. | ||
108 | + */ | ||
109 | +#define NPCM7XX_PWM_NR_REGS (0x54 / sizeof(uint32_t)) | ||
110 | + | ||
111 | +/* | ||
112 | + * The maximum duty values. Each duty unit represents 1/NPCM7XX_PWM_MAX_DUTY | ||
113 | + * cycles. For example, if NPCM7XX_PWM_MAX_DUTY=1,000,000 and a PWM has a duty | ||
114 | + * value of 100,000 the duty cycle for that PWM is 10%. | ||
115 | + */ | ||
116 | +#define NPCM7XX_PWM_MAX_DUTY 1000000 | ||
117 | + | ||
118 | +typedef struct NPCM7xxPWMState NPCM7xxPWMState; | ||
119 | + | ||
120 | +/** | ||
121 | + * struct NPCM7xxPWM - The state of a single PWM channel. | ||
122 | + * @module: The PWM module that contains this channel. | ||
123 | + * @irq: GIC interrupt line to fire on expiration if enabled. | ||
124 | + * @running: Whether this PWM channel is generating output. | ||
125 | + * @inverted: Whether this PWM channel is inverted. | ||
126 | + * @index: The index of this PWM channel. | ||
127 | + * @cnr: The counter register. | ||
128 | + * @cmr: The comparator register. | ||
129 | + * @pdr: The data register. | ||
130 | + * @pwdr: The watchdog register. | ||
131 | + * @freq: The frequency of this PWM channel. | ||
132 | + * @duty: The duty cycle of this PWM channel. One unit represents | ||
133 | + * 1/NPCM7XX_MAX_DUTY cycles. | ||
134 | + */ | ||
135 | +typedef struct NPCM7xxPWM { | ||
136 | + NPCM7xxPWMState *module; | ||
137 | + | ||
138 | + qemu_irq irq; | ||
139 | + | ||
140 | + bool running; | ||
141 | + bool inverted; | ||
142 | + | ||
143 | + uint8_t index; | ||
144 | + uint32_t cnr; | ||
145 | + uint32_t cmr; | ||
146 | + uint32_t pdr; | ||
147 | + uint32_t pwdr; | ||
148 | + | ||
149 | + uint32_t freq; | ||
150 | + uint32_t duty; | ||
151 | +} NPCM7xxPWM; | ||
152 | + | ||
153 | +/** | ||
154 | + * struct NPCM7xxPWMState - Pulse Width Modulation device state. | ||
155 | + * @parent: System bus device. | ||
156 | + * @iomem: Memory region through which registers are accessed. | ||
157 | + * @clock: The PWM clock. | ||
158 | + * @pwm: The PWM channels owned by this module. | ||
159 | + * @ppr: The prescaler register. | ||
160 | + * @csr: The clock selector register. | ||
161 | + * @pcr: The control register. | ||
162 | + * @pier: The interrupt enable register. | ||
163 | + * @piir: The interrupt indication register. | ||
164 | + */ | ||
165 | +struct NPCM7xxPWMState { | ||
166 | + SysBusDevice parent; | ||
167 | + | ||
168 | + MemoryRegion iomem; | ||
169 | + | ||
170 | + Clock *clock; | ||
171 | + NPCM7xxPWM pwm[NPCM7XX_PWM_PER_MODULE]; | ||
172 | + | ||
173 | + uint32_t ppr; | ||
174 | + uint32_t csr; | ||
175 | + uint32_t pcr; | ||
176 | + uint32_t pier; | ||
177 | + uint32_t piir; | ||
178 | +}; | ||
179 | + | ||
180 | +#define TYPE_NPCM7XX_PWM "npcm7xx-pwm" | ||
181 | +#define NPCM7XX_PWM(obj) \ | ||
182 | + OBJECT_CHECK(NPCM7xxPWMState, (obj), TYPE_NPCM7XX_PWM) | ||
183 | + | ||
184 | +#endif /* NPCM7XX_PWM_H */ | ||
185 | diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c | ||
186 | index XXXXXXX..XXXXXXX 100644 | ||
187 | --- a/hw/arm/npcm7xx.c | ||
188 | +++ b/hw/arm/npcm7xx.c | ||
189 | @@ -XXX,XX +XXX,XX @@ enum NPCM7xxInterrupt { | ||
190 | NPCM7XX_WDG2_IRQ, /* Timer Module 2 Watchdog */ | ||
191 | NPCM7XX_EHCI_IRQ = 61, | ||
192 | NPCM7XX_OHCI_IRQ = 62, | ||
193 | + NPCM7XX_PWM0_IRQ = 93, /* PWM module 0 */ | ||
194 | + NPCM7XX_PWM1_IRQ, /* PWM module 1 */ | ||
195 | NPCM7XX_GPIO0_IRQ = 116, | ||
196 | NPCM7XX_GPIO1_IRQ, | ||
197 | NPCM7XX_GPIO2_IRQ, | ||
198 | @@ -XXX,XX +XXX,XX @@ static const hwaddr npcm7xx_fiu3_flash_addr[] = { | ||
199 | 0xb8000000, /* CS3 */ | ||
200 | }; | ||
201 | |||
202 | +/* Register base address for each PWM Module */ | ||
203 | +static const hwaddr npcm7xx_pwm_addr[] = { | ||
204 | + 0xf0103000, | ||
205 | + 0xf0104000, | ||
206 | +}; | ||
207 | + | ||
208 | static const struct { | ||
209 | hwaddr regs_addr; | ||
210 | uint32_t unconnected_pins; | ||
211 | @@ -XXX,XX +XXX,XX @@ static void npcm7xx_init(Object *obj) | ||
212 | object_initialize_child(obj, npcm7xx_fiu[i].name, &s->fiu[i], | ||
213 | TYPE_NPCM7XX_FIU); | ||
214 | } | ||
215 | + | ||
216 | + for (i = 0; i < ARRAY_SIZE(s->pwm); i++) { | ||
217 | + object_initialize_child(obj, "pwm[*]", &s->pwm[i], TYPE_NPCM7XX_PWM); | ||
218 | + } | ||
219 | } | 29 | } |
220 | 30 | ||
221 | static void npcm7xx_realize(DeviceState *dev, Error **errp) | 31 | +static uint64_t gt_indirect_access_timer_offset(CPUARMState *env, int timeridx) |
222 | @@ -XXX,XX +XXX,XX @@ static void npcm7xx_realize(DeviceState *dev, Error **errp) | ||
223 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->ohci), 0, | ||
224 | npcm7xx_irq(s, NPCM7XX_OHCI_IRQ)); | ||
225 | |||
226 | + /* PWM Modules. Cannot fail. */ | ||
227 | + QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_pwm_addr) != ARRAY_SIZE(s->pwm)); | ||
228 | + for (i = 0; i < ARRAY_SIZE(s->pwm); i++) { | ||
229 | + SysBusDevice *sbd = SYS_BUS_DEVICE(&s->pwm[i]); | ||
230 | + | ||
231 | + qdev_connect_clock_in(DEVICE(&s->pwm[i]), "clock", qdev_get_clock_out( | ||
232 | + DEVICE(&s->clk), "apb3-clock")); | ||
233 | + sysbus_realize(sbd, &error_abort); | ||
234 | + sysbus_mmio_map(sbd, 0, npcm7xx_pwm_addr[i]); | ||
235 | + sysbus_connect_irq(sbd, i, npcm7xx_irq(s, NPCM7XX_PWM0_IRQ + i)); | ||
236 | + } | ||
237 | + | ||
238 | /* | ||
239 | * Flash Interface Unit (FIU). Can fail if incorrect number of chip selects | ||
240 | * specified, but this is a programming error. | ||
241 | @@ -XXX,XX +XXX,XX @@ static void npcm7xx_realize(DeviceState *dev, Error **errp) | ||
242 | create_unimplemented_device("npcm7xx.peci", 0xf0100000, 4 * KiB); | ||
243 | create_unimplemented_device("npcm7xx.siox[1]", 0xf0101000, 4 * KiB); | ||
244 | create_unimplemented_device("npcm7xx.siox[2]", 0xf0102000, 4 * KiB); | ||
245 | - create_unimplemented_device("npcm7xx.pwm[0]", 0xf0103000, 4 * KiB); | ||
246 | - create_unimplemented_device("npcm7xx.pwm[1]", 0xf0104000, 4 * KiB); | ||
247 | create_unimplemented_device("npcm7xx.mft[0]", 0xf0180000, 4 * KiB); | ||
248 | create_unimplemented_device("npcm7xx.mft[1]", 0xf0181000, 4 * KiB); | ||
249 | create_unimplemented_device("npcm7xx.mft[2]", 0xf0182000, 4 * KiB); | ||
250 | diff --git a/hw/misc/npcm7xx_pwm.c b/hw/misc/npcm7xx_pwm.c | ||
251 | new file mode 100644 | ||
252 | index XXXXXXX..XXXXXXX | ||
253 | --- /dev/null | ||
254 | +++ b/hw/misc/npcm7xx_pwm.c | ||
255 | @@ -XXX,XX +XXX,XX @@ | ||
256 | +/* | ||
257 | + * Nuvoton NPCM7xx PWM Module | ||
258 | + * | ||
259 | + * Copyright 2020 Google LLC | ||
260 | + * | ||
261 | + * This program is free software; you can redistribute it and/or modify it | ||
262 | + * under the terms of the GNU General Public License as published by the | ||
263 | + * Free Software Foundation; either version 2 of the License, or | ||
264 | + * (at your option) any later version. | ||
265 | + * | ||
266 | + * This program is distributed in the hope that it will be useful, but WITHOUT | ||
267 | + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
268 | + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | ||
269 | + * for more details. | ||
270 | + */ | ||
271 | + | ||
272 | +#include "qemu/osdep.h" | ||
273 | +#include "hw/irq.h" | ||
274 | +#include "hw/qdev-clock.h" | ||
275 | +#include "hw/qdev-properties.h" | ||
276 | +#include "hw/misc/npcm7xx_pwm.h" | ||
277 | +#include "hw/registerfields.h" | ||
278 | +#include "migration/vmstate.h" | ||
279 | +#include "qemu/bitops.h" | ||
280 | +#include "qemu/error-report.h" | ||
281 | +#include "qemu/log.h" | ||
282 | +#include "qemu/module.h" | ||
283 | +#include "qemu/units.h" | ||
284 | +#include "trace.h" | ||
285 | + | ||
286 | +REG32(NPCM7XX_PWM_PPR, 0x00); | ||
287 | +REG32(NPCM7XX_PWM_CSR, 0x04); | ||
288 | +REG32(NPCM7XX_PWM_PCR, 0x08); | ||
289 | +REG32(NPCM7XX_PWM_CNR0, 0x0c); | ||
290 | +REG32(NPCM7XX_PWM_CMR0, 0x10); | ||
291 | +REG32(NPCM7XX_PWM_PDR0, 0x14); | ||
292 | +REG32(NPCM7XX_PWM_CNR1, 0x18); | ||
293 | +REG32(NPCM7XX_PWM_CMR1, 0x1c); | ||
294 | +REG32(NPCM7XX_PWM_PDR1, 0x20); | ||
295 | +REG32(NPCM7XX_PWM_CNR2, 0x24); | ||
296 | +REG32(NPCM7XX_PWM_CMR2, 0x28); | ||
297 | +REG32(NPCM7XX_PWM_PDR2, 0x2c); | ||
298 | +REG32(NPCM7XX_PWM_CNR3, 0x30); | ||
299 | +REG32(NPCM7XX_PWM_CMR3, 0x34); | ||
300 | +REG32(NPCM7XX_PWM_PDR3, 0x38); | ||
301 | +REG32(NPCM7XX_PWM_PIER, 0x3c); | ||
302 | +REG32(NPCM7XX_PWM_PIIR, 0x40); | ||
303 | +REG32(NPCM7XX_PWM_PWDR0, 0x44); | ||
304 | +REG32(NPCM7XX_PWM_PWDR1, 0x48); | ||
305 | +REG32(NPCM7XX_PWM_PWDR2, 0x4c); | ||
306 | +REG32(NPCM7XX_PWM_PWDR3, 0x50); | ||
307 | + | ||
308 | +/* Register field definitions. */ | ||
309 | +#define NPCM7XX_PPR(rv, index) extract32((rv), npcm7xx_ppr_base[index], 8) | ||
310 | +#define NPCM7XX_CSR(rv, index) extract32((rv), npcm7xx_csr_base[index], 3) | ||
311 | +#define NPCM7XX_CH(rv, index) extract32((rv), npcm7xx_ch_base[index], 4) | ||
312 | +#define NPCM7XX_CH_EN BIT(0) | ||
313 | +#define NPCM7XX_CH_INV BIT(2) | ||
314 | +#define NPCM7XX_CH_MOD BIT(3) | ||
315 | + | ||
316 | +/* Offset of each PWM channel's prescaler in the PPR register. */ | ||
317 | +static const int npcm7xx_ppr_base[] = { 0, 0, 8, 8 }; | ||
318 | +/* Offset of each PWM channel's clock selector in the CSR register. */ | ||
319 | +static const int npcm7xx_csr_base[] = { 0, 4, 8, 12 }; | ||
320 | +/* Offset of each PWM channel's control variable in the PCR register. */ | ||
321 | +static const int npcm7xx_ch_base[] = { 0, 8, 12, 16 }; | ||
322 | + | ||
323 | +static uint32_t npcm7xx_pwm_calculate_freq(NPCM7xxPWM *p) | ||
324 | +{ | 32 | +{ |
325 | + uint32_t ppr; | 33 | + /* |
326 | + uint32_t csr; | 34 | + * Return the timer offset to use for indirect accesses to the timer. |
327 | + uint32_t freq; | 35 | + * This is the Offset value as defined in D12.2.4.1 "Operation of the |
328 | + | 36 | + * CompareValue views of the timers". |
329 | + if (!p->running) { | 37 | + * |
38 | + * The condition here is not always the same as the condition for | ||
39 | + * whether to apply an offset register when doing a direct read of | ||
40 | + * the counter sysreg; those conditions are described in the | ||
41 | + * access pseudocode for each counter register. | ||
42 | + */ | ||
43 | + switch (timeridx) { | ||
44 | + case GTIMER_PHYS: | ||
45 | + return gt_phys_raw_cnt_offset(env); | ||
46 | + case GTIMER_VIRT: | ||
47 | + return env->cp15.cntvoff_el2; | ||
48 | + case GTIMER_HYP: | ||
49 | + case GTIMER_SEC: | ||
50 | + case GTIMER_HYPVIRT: | ||
330 | + return 0; | 51 | + return 0; |
331 | + } | ||
332 | + | ||
333 | + csr = NPCM7XX_CSR(p->module->csr, p->index); | ||
334 | + ppr = NPCM7XX_PPR(p->module->ppr, p->index); | ||
335 | + freq = clock_get_hz(p->module->clock); | ||
336 | + freq /= ppr + 1; | ||
337 | + /* csr can only be 0~4 */ | ||
338 | + if (csr > 4) { | ||
339 | + qemu_log_mask(LOG_GUEST_ERROR, | ||
340 | + "%s: invalid csr value %u\n", | ||
341 | + __func__, csr); | ||
342 | + csr = 4; | ||
343 | + } | ||
344 | + /* freq won't be changed if csr == 4. */ | ||
345 | + if (csr < 4) { | ||
346 | + freq >>= csr + 1; | ||
347 | + } | ||
348 | + | ||
349 | + return freq / (p->cnr + 1); | ||
350 | +} | ||
351 | + | ||
352 | +static uint32_t npcm7xx_pwm_calculate_duty(NPCM7xxPWM *p) | ||
353 | +{ | ||
354 | + uint64_t duty; | ||
355 | + | ||
356 | + if (p->running) { | ||
357 | + if (p->cnr == 0) { | ||
358 | + duty = 0; | ||
359 | + } else if (p->cmr >= p->cnr) { | ||
360 | + duty = NPCM7XX_PWM_MAX_DUTY; | ||
361 | + } else { | ||
362 | + duty = NPCM7XX_PWM_MAX_DUTY * (p->cmr + 1) / (p->cnr + 1); | ||
363 | + } | ||
364 | + } else { | ||
365 | + duty = 0; | ||
366 | + } | ||
367 | + | ||
368 | + if (p->inverted) { | ||
369 | + duty = NPCM7XX_PWM_MAX_DUTY - duty; | ||
370 | + } | ||
371 | + | ||
372 | + return duty; | ||
373 | +} | ||
374 | + | ||
375 | +static void npcm7xx_pwm_update_freq(NPCM7xxPWM *p) | ||
376 | +{ | ||
377 | + uint32_t freq = npcm7xx_pwm_calculate_freq(p); | ||
378 | + | ||
379 | + if (freq != p->freq) { | ||
380 | + trace_npcm7xx_pwm_update_freq(DEVICE(p->module)->canonical_path, | ||
381 | + p->index, p->freq, freq); | ||
382 | + p->freq = freq; | ||
383 | + } | ||
384 | +} | ||
385 | + | ||
386 | +static void npcm7xx_pwm_update_duty(NPCM7xxPWM *p) | ||
387 | +{ | ||
388 | + uint32_t duty = npcm7xx_pwm_calculate_duty(p); | ||
389 | + | ||
390 | + if (duty != p->duty) { | ||
391 | + trace_npcm7xx_pwm_update_duty(DEVICE(p->module)->canonical_path, | ||
392 | + p->index, p->duty, duty); | ||
393 | + p->duty = duty; | ||
394 | + } | ||
395 | +} | ||
396 | + | ||
397 | +static void npcm7xx_pwm_update_output(NPCM7xxPWM *p) | ||
398 | +{ | ||
399 | + npcm7xx_pwm_update_freq(p); | ||
400 | + npcm7xx_pwm_update_duty(p); | ||
401 | +} | ||
402 | + | ||
403 | +static void npcm7xx_pwm_write_ppr(NPCM7xxPWMState *s, uint32_t new_ppr) | ||
404 | +{ | ||
405 | + int i; | ||
406 | + uint32_t old_ppr = s->ppr; | ||
407 | + | ||
408 | + QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_ppr_base) != NPCM7XX_PWM_PER_MODULE); | ||
409 | + s->ppr = new_ppr; | ||
410 | + for (i = 0; i < NPCM7XX_PWM_PER_MODULE; ++i) { | ||
411 | + if (NPCM7XX_PPR(old_ppr, i) != NPCM7XX_PPR(new_ppr, i)) { | ||
412 | + npcm7xx_pwm_update_freq(&s->pwm[i]); | ||
413 | + } | ||
414 | + } | ||
415 | +} | ||
416 | + | ||
417 | +static void npcm7xx_pwm_write_csr(NPCM7xxPWMState *s, uint32_t new_csr) | ||
418 | +{ | ||
419 | + int i; | ||
420 | + uint32_t old_csr = s->csr; | ||
421 | + | ||
422 | + QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_csr_base) != NPCM7XX_PWM_PER_MODULE); | ||
423 | + s->csr = new_csr; | ||
424 | + for (i = 0; i < NPCM7XX_PWM_PER_MODULE; ++i) { | ||
425 | + if (NPCM7XX_CSR(old_csr, i) != NPCM7XX_CSR(new_csr, i)) { | ||
426 | + npcm7xx_pwm_update_freq(&s->pwm[i]); | ||
427 | + } | ||
428 | + } | ||
429 | +} | ||
430 | + | ||
431 | +static void npcm7xx_pwm_write_pcr(NPCM7xxPWMState *s, uint32_t new_pcr) | ||
432 | +{ | ||
433 | + int i; | ||
434 | + bool inverted; | ||
435 | + uint32_t pcr; | ||
436 | + NPCM7xxPWM *p; | ||
437 | + | ||
438 | + s->pcr = new_pcr; | ||
439 | + QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_ch_base) != NPCM7XX_PWM_PER_MODULE); | ||
440 | + for (i = 0; i < NPCM7XX_PWM_PER_MODULE; ++i) { | ||
441 | + p = &s->pwm[i]; | ||
442 | + pcr = NPCM7XX_CH(new_pcr, i); | ||
443 | + inverted = pcr & NPCM7XX_CH_INV; | ||
444 | + | ||
445 | + /* | ||
446 | + * We only run a PWM channel with toggle mode. Single-shot mode does not | ||
447 | + * generate frequency and duty-cycle values. | ||
448 | + */ | ||
449 | + if ((pcr & NPCM7XX_CH_EN) && (pcr & NPCM7XX_CH_MOD)) { | ||
450 | + if (p->running) { | ||
451 | + /* Re-run this PWM channel if inverted changed. */ | ||
452 | + if (p->inverted ^ inverted) { | ||
453 | + p->inverted = inverted; | ||
454 | + npcm7xx_pwm_update_duty(p); | ||
455 | + } | ||
456 | + } else { | ||
457 | + /* Run this PWM channel. */ | ||
458 | + p->running = true; | ||
459 | + p->inverted = inverted; | ||
460 | + npcm7xx_pwm_update_output(p); | ||
461 | + } | ||
462 | + } else { | ||
463 | + /* Clear this PWM channel. */ | ||
464 | + p->running = false; | ||
465 | + p->inverted = inverted; | ||
466 | + npcm7xx_pwm_update_output(p); | ||
467 | + } | ||
468 | + } | ||
469 | + | ||
470 | +} | ||
471 | + | ||
472 | +static hwaddr npcm7xx_cnr_index(hwaddr offset) | ||
473 | +{ | ||
474 | + switch (offset) { | ||
475 | + case A_NPCM7XX_PWM_CNR0: | ||
476 | + return 0; | ||
477 | + case A_NPCM7XX_PWM_CNR1: | ||
478 | + return 1; | ||
479 | + case A_NPCM7XX_PWM_CNR2: | ||
480 | + return 2; | ||
481 | + case A_NPCM7XX_PWM_CNR3: | ||
482 | + return 3; | ||
483 | + default: | 52 | + default: |
484 | + g_assert_not_reached(); | 53 | + g_assert_not_reached(); |
485 | + } | 54 | + } |
486 | +} | 55 | +} |
487 | + | 56 | + |
488 | +static hwaddr npcm7xx_cmr_index(hwaddr offset) | 57 | static void gt_recalc_timer(ARMCPU *cpu, int timeridx) |
489 | +{ | 58 | { |
490 | + switch (offset) { | 59 | ARMGenericTimer *gt = &cpu->env.cp15.c14_timer[timeridx]; |
491 | + case A_NPCM7XX_PWM_CMR0: | 60 | @@ -XXX,XX +XXX,XX @@ static void gt_recalc_timer(ARMCPU *cpu, int timeridx) |
492 | + return 0; | 61 | * Timer enabled: calculate and set current ISTATUS, irq, and |
493 | + case A_NPCM7XX_PWM_CMR1: | 62 | * reset timer to when ISTATUS next has to change |
494 | + return 1; | 63 | */ |
495 | + case A_NPCM7XX_PWM_CMR2: | 64 | - uint64_t offset = timeridx == GTIMER_VIRT ? |
496 | + return 2; | 65 | - cpu->env.cp15.cntvoff_el2 : gt_phys_raw_cnt_offset(&cpu->env); |
497 | + case A_NPCM7XX_PWM_CMR3: | 66 | + uint64_t offset = gt_indirect_access_timer_offset(&cpu->env, timeridx); |
498 | + return 3; | 67 | uint64_t count = gt_get_countervalue(&cpu->env); |
499 | + default: | 68 | /* Note that this must be unsigned 64 bit arithmetic: */ |
500 | + g_assert_not_reached(); | 69 | int istatus = count - offset >= gt->cval; |
501 | + } | ||
502 | +} | ||
503 | + | ||
504 | +static hwaddr npcm7xx_pdr_index(hwaddr offset) | ||
505 | +{ | ||
506 | + switch (offset) { | ||
507 | + case A_NPCM7XX_PWM_PDR0: | ||
508 | + return 0; | ||
509 | + case A_NPCM7XX_PWM_PDR1: | ||
510 | + return 1; | ||
511 | + case A_NPCM7XX_PWM_PDR2: | ||
512 | + return 2; | ||
513 | + case A_NPCM7XX_PWM_PDR3: | ||
514 | + return 3; | ||
515 | + default: | ||
516 | + g_assert_not_reached(); | ||
517 | + } | ||
518 | +} | ||
519 | + | ||
520 | +static hwaddr npcm7xx_pwdr_index(hwaddr offset) | ||
521 | +{ | ||
522 | + switch (offset) { | ||
523 | + case A_NPCM7XX_PWM_PWDR0: | ||
524 | + return 0; | ||
525 | + case A_NPCM7XX_PWM_PWDR1: | ||
526 | + return 1; | ||
527 | + case A_NPCM7XX_PWM_PWDR2: | ||
528 | + return 2; | ||
529 | + case A_NPCM7XX_PWM_PWDR3: | ||
530 | + return 3; | ||
531 | + default: | ||
532 | + g_assert_not_reached(); | ||
533 | + } | ||
534 | +} | ||
535 | + | ||
536 | +static uint64_t npcm7xx_pwm_read(void *opaque, hwaddr offset, unsigned size) | ||
537 | +{ | ||
538 | + NPCM7xxPWMState *s = opaque; | ||
539 | + uint64_t value = 0; | ||
540 | + | ||
541 | + switch (offset) { | ||
542 | + case A_NPCM7XX_PWM_CNR0: | ||
543 | + case A_NPCM7XX_PWM_CNR1: | ||
544 | + case A_NPCM7XX_PWM_CNR2: | ||
545 | + case A_NPCM7XX_PWM_CNR3: | ||
546 | + value = s->pwm[npcm7xx_cnr_index(offset)].cnr; | ||
547 | + break; | ||
548 | + | ||
549 | + case A_NPCM7XX_PWM_CMR0: | ||
550 | + case A_NPCM7XX_PWM_CMR1: | ||
551 | + case A_NPCM7XX_PWM_CMR2: | ||
552 | + case A_NPCM7XX_PWM_CMR3: | ||
553 | + value = s->pwm[npcm7xx_cmr_index(offset)].cmr; | ||
554 | + break; | ||
555 | + | ||
556 | + case A_NPCM7XX_PWM_PDR0: | ||
557 | + case A_NPCM7XX_PWM_PDR1: | ||
558 | + case A_NPCM7XX_PWM_PDR2: | ||
559 | + case A_NPCM7XX_PWM_PDR3: | ||
560 | + value = s->pwm[npcm7xx_pdr_index(offset)].pdr; | ||
561 | + break; | ||
562 | + | ||
563 | + case A_NPCM7XX_PWM_PWDR0: | ||
564 | + case A_NPCM7XX_PWM_PWDR1: | ||
565 | + case A_NPCM7XX_PWM_PWDR2: | ||
566 | + case A_NPCM7XX_PWM_PWDR3: | ||
567 | + value = s->pwm[npcm7xx_pwdr_index(offset)].pwdr; | ||
568 | + break; | ||
569 | + | ||
570 | + case A_NPCM7XX_PWM_PPR: | ||
571 | + value = s->ppr; | ||
572 | + break; | ||
573 | + | ||
574 | + case A_NPCM7XX_PWM_CSR: | ||
575 | + value = s->csr; | ||
576 | + break; | ||
577 | + | ||
578 | + case A_NPCM7XX_PWM_PCR: | ||
579 | + value = s->pcr; | ||
580 | + break; | ||
581 | + | ||
582 | + case A_NPCM7XX_PWM_PIER: | ||
583 | + value = s->pier; | ||
584 | + break; | ||
585 | + | ||
586 | + case A_NPCM7XX_PWM_PIIR: | ||
587 | + value = s->piir; | ||
588 | + break; | ||
589 | + | ||
590 | + default: | ||
591 | + qemu_log_mask(LOG_GUEST_ERROR, | ||
592 | + "%s: invalid offset 0x%04" HWADDR_PRIx "\n", | ||
593 | + __func__, offset); | ||
594 | + break; | ||
595 | + } | ||
596 | + | ||
597 | + trace_npcm7xx_pwm_read(DEVICE(s)->canonical_path, offset, value); | ||
598 | + return value; | ||
599 | +} | ||
600 | + | ||
601 | +static void npcm7xx_pwm_write(void *opaque, hwaddr offset, | ||
602 | + uint64_t v, unsigned size) | ||
603 | +{ | ||
604 | + NPCM7xxPWMState *s = opaque; | ||
605 | + NPCM7xxPWM *p; | ||
606 | + uint32_t value = v; | ||
607 | + | ||
608 | + trace_npcm7xx_pwm_write(DEVICE(s)->canonical_path, offset, value); | ||
609 | + switch (offset) { | ||
610 | + case A_NPCM7XX_PWM_CNR0: | ||
611 | + case A_NPCM7XX_PWM_CNR1: | ||
612 | + case A_NPCM7XX_PWM_CNR2: | ||
613 | + case A_NPCM7XX_PWM_CNR3: | ||
614 | + p = &s->pwm[npcm7xx_cnr_index(offset)]; | ||
615 | + p->cnr = value; | ||
616 | + npcm7xx_pwm_update_output(p); | ||
617 | + break; | ||
618 | + | ||
619 | + case A_NPCM7XX_PWM_CMR0: | ||
620 | + case A_NPCM7XX_PWM_CMR1: | ||
621 | + case A_NPCM7XX_PWM_CMR2: | ||
622 | + case A_NPCM7XX_PWM_CMR3: | ||
623 | + p = &s->pwm[npcm7xx_cmr_index(offset)]; | ||
624 | + p->cmr = value; | ||
625 | + npcm7xx_pwm_update_output(p); | ||
626 | + break; | ||
627 | + | ||
628 | + case A_NPCM7XX_PWM_PDR0: | ||
629 | + case A_NPCM7XX_PWM_PDR1: | ||
630 | + case A_NPCM7XX_PWM_PDR2: | ||
631 | + case A_NPCM7XX_PWM_PDR3: | ||
632 | + qemu_log_mask(LOG_GUEST_ERROR, | ||
633 | + "%s: register @ 0x%04" HWADDR_PRIx " is read-only\n", | ||
634 | + __func__, offset); | ||
635 | + break; | ||
636 | + | ||
637 | + case A_NPCM7XX_PWM_PWDR0: | ||
638 | + case A_NPCM7XX_PWM_PWDR1: | ||
639 | + case A_NPCM7XX_PWM_PWDR2: | ||
640 | + case A_NPCM7XX_PWM_PWDR3: | ||
641 | + qemu_log_mask(LOG_UNIMP, | ||
642 | + "%s: register @ 0x%04" HWADDR_PRIx " is not implemented\n", | ||
643 | + __func__, offset); | ||
644 | + break; | ||
645 | + | ||
646 | + case A_NPCM7XX_PWM_PPR: | ||
647 | + npcm7xx_pwm_write_ppr(s, value); | ||
648 | + break; | ||
649 | + | ||
650 | + case A_NPCM7XX_PWM_CSR: | ||
651 | + npcm7xx_pwm_write_csr(s, value); | ||
652 | + break; | ||
653 | + | ||
654 | + case A_NPCM7XX_PWM_PCR: | ||
655 | + npcm7xx_pwm_write_pcr(s, value); | ||
656 | + break; | ||
657 | + | ||
658 | + case A_NPCM7XX_PWM_PIER: | ||
659 | + qemu_log_mask(LOG_UNIMP, | ||
660 | + "%s: register @ 0x%04" HWADDR_PRIx " is not implemented\n", | ||
661 | + __func__, offset); | ||
662 | + break; | ||
663 | + | ||
664 | + case A_NPCM7XX_PWM_PIIR: | ||
665 | + qemu_log_mask(LOG_UNIMP, | ||
666 | + "%s: register @ 0x%04" HWADDR_PRIx " is not implemented\n", | ||
667 | + __func__, offset); | ||
668 | + break; | ||
669 | + | ||
670 | + default: | ||
671 | + qemu_log_mask(LOG_GUEST_ERROR, | ||
672 | + "%s: invalid offset 0x%04" HWADDR_PRIx "\n", | ||
673 | + __func__, offset); | ||
674 | + break; | ||
675 | + } | ||
676 | +} | ||
677 | + | ||
678 | +static const struct MemoryRegionOps npcm7xx_pwm_ops = { | ||
679 | + .read = npcm7xx_pwm_read, | ||
680 | + .write = npcm7xx_pwm_write, | ||
681 | + .endianness = DEVICE_LITTLE_ENDIAN, | ||
682 | + .valid = { | ||
683 | + .min_access_size = 4, | ||
684 | + .max_access_size = 4, | ||
685 | + .unaligned = false, | ||
686 | + }, | ||
687 | +}; | ||
688 | + | ||
689 | +static void npcm7xx_pwm_enter_reset(Object *obj, ResetType type) | ||
690 | +{ | ||
691 | + NPCM7xxPWMState *s = NPCM7XX_PWM(obj); | ||
692 | + int i; | ||
693 | + | ||
694 | + for (i = 0; i < NPCM7XX_PWM_PER_MODULE; i++) { | ||
695 | + NPCM7xxPWM *p = &s->pwm[i]; | ||
696 | + | ||
697 | + p->cnr = 0x00000000; | ||
698 | + p->cmr = 0x00000000; | ||
699 | + p->pdr = 0x00000000; | ||
700 | + p->pwdr = 0x00000000; | ||
701 | + } | ||
702 | + | ||
703 | + s->ppr = 0x00000000; | ||
704 | + s->csr = 0x00000000; | ||
705 | + s->pcr = 0x00000000; | ||
706 | + s->pier = 0x00000000; | ||
707 | + s->piir = 0x00000000; | ||
708 | +} | ||
709 | + | ||
710 | +static void npcm7xx_pwm_hold_reset(Object *obj) | ||
711 | +{ | ||
712 | + NPCM7xxPWMState *s = NPCM7XX_PWM(obj); | ||
713 | + int i; | ||
714 | + | ||
715 | + for (i = 0; i < NPCM7XX_PWM_PER_MODULE; i++) { | ||
716 | + qemu_irq_lower(s->pwm[i].irq); | ||
717 | + } | ||
718 | +} | ||
719 | + | ||
720 | +static void npcm7xx_pwm_init(Object *obj) | ||
721 | +{ | ||
722 | + NPCM7xxPWMState *s = NPCM7XX_PWM(obj); | ||
723 | + SysBusDevice *sbd = SYS_BUS_DEVICE(obj); | ||
724 | + int i; | ||
725 | + | ||
726 | + for (i = 0; i < NPCM7XX_PWM_PER_MODULE; i++) { | ||
727 | + NPCM7xxPWM *p = &s->pwm[i]; | ||
728 | + p->module = s; | ||
729 | + p->index = i; | ||
730 | + sysbus_init_irq(sbd, &p->irq); | ||
731 | + } | ||
732 | + | ||
733 | + memory_region_init_io(&s->iomem, obj, &npcm7xx_pwm_ops, s, | ||
734 | + TYPE_NPCM7XX_PWM, 4 * KiB); | ||
735 | + sysbus_init_mmio(sbd, &s->iomem); | ||
736 | + s->clock = qdev_init_clock_in(DEVICE(s), "clock", NULL, NULL); | ||
737 | + | ||
738 | + for (i = 0; i < NPCM7XX_PWM_PER_MODULE; ++i) { | ||
739 | + object_property_add_uint32_ptr(obj, "freq[*]", | ||
740 | + &s->pwm[i].freq, OBJ_PROP_FLAG_READ); | ||
741 | + object_property_add_uint32_ptr(obj, "duty[*]", | ||
742 | + &s->pwm[i].duty, OBJ_PROP_FLAG_READ); | ||
743 | + } | ||
744 | +} | ||
745 | + | ||
746 | +static const VMStateDescription vmstate_npcm7xx_pwm = { | ||
747 | + .name = "npcm7xx-pwm", | ||
748 | + .version_id = 0, | ||
749 | + .minimum_version_id = 0, | ||
750 | + .fields = (VMStateField[]) { | ||
751 | + VMSTATE_BOOL(running, NPCM7xxPWM), | ||
752 | + VMSTATE_BOOL(inverted, NPCM7xxPWM), | ||
753 | + VMSTATE_UINT8(index, NPCM7xxPWM), | ||
754 | + VMSTATE_UINT32(cnr, NPCM7xxPWM), | ||
755 | + VMSTATE_UINT32(cmr, NPCM7xxPWM), | ||
756 | + VMSTATE_UINT32(pdr, NPCM7xxPWM), | ||
757 | + VMSTATE_UINT32(pwdr, NPCM7xxPWM), | ||
758 | + VMSTATE_UINT32(freq, NPCM7xxPWM), | ||
759 | + VMSTATE_UINT32(duty, NPCM7xxPWM), | ||
760 | + VMSTATE_END_OF_LIST(), | ||
761 | + }, | ||
762 | +}; | ||
763 | + | ||
764 | +static const VMStateDescription vmstate_npcm7xx_pwm_module = { | ||
765 | + .name = "npcm7xx-pwm-module", | ||
766 | + .version_id = 0, | ||
767 | + .minimum_version_id = 0, | ||
768 | + .fields = (VMStateField[]) { | ||
769 | + VMSTATE_CLOCK(clock, NPCM7xxPWMState), | ||
770 | + VMSTATE_STRUCT_ARRAY(pwm, NPCM7xxPWMState, | ||
771 | + NPCM7XX_PWM_PER_MODULE, 0, vmstate_npcm7xx_pwm, | ||
772 | + NPCM7xxPWM), | ||
773 | + VMSTATE_UINT32(ppr, NPCM7xxPWMState), | ||
774 | + VMSTATE_UINT32(csr, NPCM7xxPWMState), | ||
775 | + VMSTATE_UINT32(pcr, NPCM7xxPWMState), | ||
776 | + VMSTATE_UINT32(pier, NPCM7xxPWMState), | ||
777 | + VMSTATE_UINT32(piir, NPCM7xxPWMState), | ||
778 | + VMSTATE_END_OF_LIST(), | ||
779 | + }, | ||
780 | +}; | ||
781 | + | ||
782 | +static void npcm7xx_pwm_class_init(ObjectClass *klass, void *data) | ||
783 | +{ | ||
784 | + ResettableClass *rc = RESETTABLE_CLASS(klass); | ||
785 | + DeviceClass *dc = DEVICE_CLASS(klass); | ||
786 | + | ||
787 | + dc->desc = "NPCM7xx PWM Controller"; | ||
788 | + dc->vmsd = &vmstate_npcm7xx_pwm_module; | ||
789 | + rc->phases.enter = npcm7xx_pwm_enter_reset; | ||
790 | + rc->phases.hold = npcm7xx_pwm_hold_reset; | ||
791 | +} | ||
792 | + | ||
793 | +static const TypeInfo npcm7xx_pwm_info = { | ||
794 | + .name = TYPE_NPCM7XX_PWM, | ||
795 | + .parent = TYPE_SYS_BUS_DEVICE, | ||
796 | + .instance_size = sizeof(NPCM7xxPWMState), | ||
797 | + .class_init = npcm7xx_pwm_class_init, | ||
798 | + .instance_init = npcm7xx_pwm_init, | ||
799 | +}; | ||
800 | + | ||
801 | +static void npcm7xx_pwm_register_type(void) | ||
802 | +{ | ||
803 | + type_register_static(&npcm7xx_pwm_info); | ||
804 | +} | ||
805 | +type_init(npcm7xx_pwm_register_type); | ||
806 | diff --git a/hw/misc/meson.build b/hw/misc/meson.build | ||
807 | index XXXXXXX..XXXXXXX 100644 | ||
808 | --- a/hw/misc/meson.build | ||
809 | +++ b/hw/misc/meson.build | ||
810 | @@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_MAINSTONE', if_true: files('mst_fpga.c')) | ||
811 | softmmu_ss.add(when: 'CONFIG_NPCM7XX', if_true: files( | ||
812 | 'npcm7xx_clk.c', | ||
813 | 'npcm7xx_gcr.c', | ||
814 | + 'npcm7xx_pwm.c', | ||
815 | 'npcm7xx_rng.c', | ||
816 | )) | ||
817 | softmmu_ss.add(when: 'CONFIG_OMAP', if_true: files( | ||
818 | diff --git a/hw/misc/trace-events b/hw/misc/trace-events | ||
819 | index XXXXXXX..XXXXXXX 100644 | ||
820 | --- a/hw/misc/trace-events | ||
821 | +++ b/hw/misc/trace-events | ||
822 | @@ -XXX,XX +XXX,XX @@ npcm7xx_gcr_write(uint64_t offset, uint32_t value) "offset: 0x%04" PRIx64 " valu | ||
823 | npcm7xx_rng_read(uint64_t offset, uint64_t value, unsigned size) "offset: 0x%04" PRIx64 " value: 0x%02" PRIx64 " size: %u" | ||
824 | npcm7xx_rng_write(uint64_t offset, uint64_t value, unsigned size) "offset: 0x%04" PRIx64 " value: 0x%02" PRIx64 " size: %u" | ||
825 | |||
826 | +# npcm7xx_pwm.c | ||
827 | +npcm7xx_pwm_read(const char *id, uint64_t offset, uint32_t value) "%s offset: 0x%04" PRIx64 " value: 0x%08" PRIx32 | ||
828 | +npcm7xx_pwm_write(const char *id, uint64_t offset, uint32_t value) "%s offset: 0x%04" PRIx64 " value: 0x%08" PRIx32 | ||
829 | +npcm7xx_pwm_update_freq(const char *id, uint8_t index, uint32_t old_value, uint32_t new_value) "%s pwm[%u] Update Freq: old_freq: %u, new_freq: %u" | ||
830 | +npcm7xx_pwm_update_duty(const char *id, uint8_t index, uint32_t old_value, uint32_t new_value) "%s pwm[%u] Update Duty: old_duty: %u, new_duty: %u" | ||
831 | + | ||
832 | # stm32f4xx_syscfg.c | ||
833 | stm32f4xx_syscfg_set_irq(int gpio, int line, int level) "Interupt: GPIO: %d, Line: %d; Level: %d" | ||
834 | stm32f4xx_pulse_exti(int irq) "Pulse EXTI: %d" | ||
835 | -- | 70 | -- |
836 | 2.20.1 | 71 | 2.43.0 |
837 | 72 | ||
838 | 73 | diff view generated by jsdifflib |
1 | The lan9118 code mostly uses symbolic constants for register offsets; | 1 | The CNTVOFF_EL2 offset register should only be applied for accessses |
---|---|---|---|
2 | the exceptions are those which the datasheet doesn't give an official | 2 | to CNTVCT_EL0 and for the EL1 virtual timer (CNTV_*). We were |
3 | symbolic name to. | 3 | incorrectly applying it for the EL2 virtual timer (CNTHV_*). |
4 | 4 | ||
5 | Add some names for the registers which don't already have them, based | 5 | Cc: qemu-stable@nongnu.org |
6 | on the longer names they are given in the memory map. | 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | ||
8 | Message-id: 20250204125009.2281315-3-peter.maydell@linaro.org | ||
9 | --- | ||
10 | target/arm/helper.c | 2 -- | ||
11 | 1 file changed, 2 deletions(-) | ||
7 | 12 | ||
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 13 | diff --git a/target/arm/helper.c b/target/arm/helper.c |
9 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
10 | Message-id: 20210108180401.2263-3-peter.maydell@linaro.org | ||
11 | --- | ||
12 | hw/net/lan9118.c | 24 ++++++++++++++++++------ | ||
13 | 1 file changed, 18 insertions(+), 6 deletions(-) | ||
14 | |||
15 | diff --git a/hw/net/lan9118.c b/hw/net/lan9118.c | ||
16 | index XXXXXXX..XXXXXXX 100644 | 14 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/hw/net/lan9118.c | 15 | --- a/target/arm/helper.c |
18 | +++ b/hw/net/lan9118.c | 16 | +++ b/target/arm/helper.c |
19 | @@ -XXX,XX +XXX,XX @@ do { hw_error("lan9118: error: " fmt , ## __VA_ARGS__);} while (0) | 17 | @@ -XXX,XX +XXX,XX @@ static uint64_t gt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri, |
20 | do { fprintf(stderr, "lan9118: error: " fmt , ## __VA_ARGS__);} while (0) | 18 | |
21 | #endif | 19 | switch (timeridx) { |
22 | 20 | case GTIMER_VIRT: | |
23 | +/* The tx and rx fifo ports are a range of aliased 32-bit registers */ | 21 | - case GTIMER_HYPVIRT: |
24 | +#define RX_DATA_FIFO_PORT_FIRST 0x00 | 22 | offset = gt_virt_cnt_offset(env); |
25 | +#define RX_DATA_FIFO_PORT_LAST 0x1f | 23 | break; |
26 | +#define TX_DATA_FIFO_PORT_FIRST 0x20 | 24 | case GTIMER_PHYS: |
27 | +#define TX_DATA_FIFO_PORT_LAST 0x3f | 25 | @@ -XXX,XX +XXX,XX @@ static void gt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, |
28 | + | 26 | |
29 | +#define RX_STATUS_FIFO_PORT 0x40 | 27 | switch (timeridx) { |
30 | +#define RX_STATUS_FIFO_PEEK 0x44 | 28 | case GTIMER_VIRT: |
31 | +#define TX_STATUS_FIFO_PORT 0x48 | 29 | - case GTIMER_HYPVIRT: |
32 | +#define TX_STATUS_FIFO_PEEK 0x4c | 30 | offset = gt_virt_cnt_offset(env); |
33 | + | 31 | break; |
34 | #define CSR_ID_REV 0x50 | 32 | case GTIMER_PHYS: |
35 | #define CSR_IRQ_CFG 0x54 | ||
36 | #define CSR_INT_STS 0x58 | ||
37 | @@ -XXX,XX +XXX,XX @@ static void lan9118_writel(void *opaque, hwaddr offset, | ||
38 | offset &= 0xff; | ||
39 | |||
40 | //DPRINTF("Write reg 0x%02x = 0x%08x\n", (int)offset, val); | ||
41 | - if (offset >= 0x20 && offset < 0x40) { | ||
42 | + if (offset >= TX_DATA_FIFO_PORT_FIRST && | ||
43 | + offset <= TX_DATA_FIFO_PORT_LAST) { | ||
44 | /* TX FIFO */ | ||
45 | tx_fifo_push(s, val); | ||
46 | return; | ||
47 | @@ -XXX,XX +XXX,XX @@ static uint64_t lan9118_readl(void *opaque, hwaddr offset, | ||
48 | lan9118_state *s = (lan9118_state *)opaque; | ||
49 | |||
50 | //DPRINTF("Read reg 0x%02x\n", (int)offset); | ||
51 | - if (offset < 0x20) { | ||
52 | + if (offset <= RX_DATA_FIFO_PORT_LAST) { | ||
53 | /* RX FIFO */ | ||
54 | return rx_fifo_pop(s); | ||
55 | } | ||
56 | switch (offset) { | ||
57 | - case 0x40: | ||
58 | + case RX_STATUS_FIFO_PORT: | ||
59 | return rx_status_fifo_pop(s); | ||
60 | - case 0x44: | ||
61 | + case RX_STATUS_FIFO_PEEK: | ||
62 | return s->rx_status_fifo[s->rx_status_fifo_head]; | ||
63 | - case 0x48: | ||
64 | + case TX_STATUS_FIFO_PORT: | ||
65 | return tx_status_fifo_pop(s); | ||
66 | - case 0x4c: | ||
67 | + case TX_STATUS_FIFO_PEEK: | ||
68 | return s->tx_status_fifo[s->tx_status_fifo_head]; | ||
69 | case CSR_ID_REV: | ||
70 | return 0x01180001; | ||
71 | -- | 33 | -- |
72 | 2.20.1 | 34 | 2.43.0 |
73 | 35 | ||
74 | 36 | diff view generated by jsdifflib |
1 | From: Rémi Denis-Courmont <remi.denis.courmont@huawei.com> | 1 | When we added Secure EL2 support, we missed that this needs an update |
---|---|---|---|
2 | to the access code for the EL3 physical timer registers. These are | ||
3 | supposed to UNDEF from Secure EL1 when Secure EL2 is enabled. | ||
2 | 4 | ||
3 | This adds for the Small Translation tables extension in AArch64 state. | 5 | (Note for stable backporting: for backports to branches where |
6 | CP_ACCESS_UNDEFINED is not defined, the old name to use instead | ||
7 | is CP_ACCESS_TRAP_UNCATEGORIZED.) | ||
4 | 8 | ||
5 | Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com> | 9 | Cc: qemu-stable@nongnu.org |
6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
11 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | ||
12 | Message-id: 20250204125009.2281315-4-peter.maydell@linaro.org | ||
8 | --- | 13 | --- |
9 | target/arm/cpu.h | 5 +++++ | 14 | target/arm/helper.c | 3 +++ |
10 | target/arm/helper.c | 15 +++++++++++++-- | 15 | 1 file changed, 3 insertions(+) |
11 | 2 files changed, 18 insertions(+), 2 deletions(-) | ||
12 | 16 | ||
13 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | ||
14 | index XXXXXXX..XXXXXXX 100644 | ||
15 | --- a/target/arm/cpu.h | ||
16 | +++ b/target/arm/cpu.h | ||
17 | @@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_uao(const ARMISARegisters *id) | ||
18 | return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, UAO) != 0; | ||
19 | } | ||
20 | |||
21 | +static inline bool isar_feature_aa64_st(const ARMISARegisters *id) | ||
22 | +{ | ||
23 | + return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, ST) != 0; | ||
24 | +} | ||
25 | + | ||
26 | static inline bool isar_feature_aa64_bti(const ARMISARegisters *id) | ||
27 | { | ||
28 | return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) != 0; | ||
29 | diff --git a/target/arm/helper.c b/target/arm/helper.c | 17 | diff --git a/target/arm/helper.c b/target/arm/helper.c |
30 | index XXXXXXX..XXXXXXX 100644 | 18 | index XXXXXXX..XXXXXXX 100644 |
31 | --- a/target/arm/helper.c | 19 | --- a/target/arm/helper.c |
32 | +++ b/target/arm/helper.c | 20 | +++ b/target/arm/helper.c |
33 | @@ -XXX,XX +XXX,XX @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, | 21 | @@ -XXX,XX +XXX,XX @@ static CPAccessResult gt_stimer_access(CPUARMState *env, |
34 | { | 22 | if (!arm_is_secure(env)) { |
35 | uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr; | 23 | return CP_ACCESS_UNDEFINED; |
36 | bool epd, hpd, using16k, using64k; | ||
37 | - int select, tsz, tbi; | ||
38 | + int select, tsz, tbi, max_tsz; | ||
39 | |||
40 | if (!regime_has_2_ranges(mmu_idx)) { | ||
41 | select = 0; | ||
42 | @@ -XXX,XX +XXX,XX @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, | ||
43 | hpd = extract64(tcr, 42, 1); | ||
44 | } | 24 | } |
45 | } | 25 | + if (arm_is_el2_enabled(env)) { |
46 | - tsz = MIN(tsz, 39); /* TODO: ARMv8.4-TTST */ | 26 | + return CP_ACCESS_UNDEFINED; |
47 | + | 27 | + } |
48 | + if (cpu_isar_feature(aa64_st, env_archcpu(env))) { | 28 | if (!(env->cp15.scr_el3 & SCR_ST)) { |
49 | + max_tsz = 48 - using64k; | 29 | return CP_ACCESS_TRAP_EL3; |
50 | + } else { | 30 | } |
51 | + max_tsz = 39; | ||
52 | + } | ||
53 | + | ||
54 | + tsz = MIN(tsz, max_tsz); | ||
55 | tsz = MAX(tsz, 16); /* TODO: ARMv8.2-LVA */ | ||
56 | |||
57 | /* Present TBI as a composite with TBID. */ | ||
58 | @@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, | ||
59 | if (!aarch64 || stride == 9) { | ||
60 | /* AArch32 or 4KB pages */ | ||
61 | startlevel = 2 - sl0; | ||
62 | + | ||
63 | + if (cpu_isar_feature(aa64_st, cpu)) { | ||
64 | + startlevel &= 3; | ||
65 | + } | ||
66 | } else { | ||
67 | /* 16KB or 64KB pages */ | ||
68 | startlevel = 3 - sl0; | ||
69 | -- | 31 | -- |
70 | 2.20.1 | 32 | 2.43.0 |
71 | 33 | ||
72 | 34 | diff view generated by jsdifflib |
1 | From: Hao Wu <wuhaotsh@google.com> | 1 | Currently we handle CNTV_TVAL_EL02 by calling gt_tval_read() for the |
---|---|---|---|
2 | EL1 virt timer. This is almost correct, but the underlying | ||
3 | CNTV_TVAL_EL0 register behaves slightly differently. CNTV_TVAL_EL02 | ||
4 | always applies the CNTVOFF_EL2 offset; CNTV_TVAL_EL0 doesn't do so if | ||
5 | we're at EL2 and HCR_EL2.E2H is 1. | ||
2 | 6 | ||
3 | A device shouldn't access its parent object which is QOM internal. | 7 | We were getting this wrong, because we ended up in |
4 | Instead it should use type cast for this purporse. This patch fixes this | 8 | gt_virt_cnt_offset() and did the E2H check. |
5 | issue for all NPCM7XX Devices. | ||
6 | 9 | ||
7 | Signed-off-by: Hao Wu <wuhaotsh@google.com> | 10 | Factor out the tval read/write calculation from the selection of the |
8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 11 | offset, so that we can special case gt_virt_tval_read() and |
9 | Message-id: 20210108190945.949196-7-wuhaotsh@google.com | 12 | gt_virt_tval_write() to unconditionally pass CNTVOFF_EL2. |
13 | |||
14 | Cc: qemu-stable@nongnu.org | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 15 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
16 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | ||
17 | Message-id: 20250204125009.2281315-5-peter.maydell@linaro.org | ||
11 | --- | 18 | --- |
12 | hw/arm/npcm7xx_boards.c | 2 +- | 19 | target/arm/helper.c | 36 +++++++++++++++++++++++++++--------- |
13 | hw/mem/npcm7xx_mc.c | 2 +- | 20 | 1 file changed, 27 insertions(+), 9 deletions(-) |
14 | hw/misc/npcm7xx_clk.c | 2 +- | ||
15 | hw/misc/npcm7xx_gcr.c | 2 +- | ||
16 | hw/misc/npcm7xx_rng.c | 2 +- | ||
17 | hw/nvram/npcm7xx_otp.c | 2 +- | ||
18 | hw/ssi/npcm7xx_fiu.c | 2 +- | ||
19 | 7 files changed, 7 insertions(+), 7 deletions(-) | ||
20 | 21 | ||
21 | diff --git a/hw/arm/npcm7xx_boards.c b/hw/arm/npcm7xx_boards.c | 22 | diff --git a/target/arm/helper.c b/target/arm/helper.c |
22 | index XXXXXXX..XXXXXXX 100644 | 23 | index XXXXXXX..XXXXXXX 100644 |
23 | --- a/hw/arm/npcm7xx_boards.c | 24 | --- a/target/arm/helper.c |
24 | +++ b/hw/arm/npcm7xx_boards.c | 25 | +++ b/target/arm/helper.c |
25 | @@ -XXX,XX +XXX,XX @@ static NPCM7xxState *npcm7xx_create_soc(MachineState *machine, | 26 | @@ -XXX,XX +XXX,XX @@ static void gt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, |
26 | uint32_t hw_straps) | 27 | gt_recalc_timer(env_archcpu(env), timeridx); |
28 | } | ||
29 | |||
30 | +static uint64_t do_tval_read(CPUARMState *env, int timeridx, uint64_t offset) | ||
31 | +{ | ||
32 | + return (uint32_t)(env->cp15.c14_timer[timeridx].cval - | ||
33 | + (gt_get_countervalue(env) - offset)); | ||
34 | +} | ||
35 | + | ||
36 | static uint64_t gt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri, | ||
37 | int timeridx) | ||
27 | { | 38 | { |
28 | NPCM7xxMachineClass *nmc = NPCM7XX_MACHINE_GET_CLASS(machine); | 39 | @@ -XXX,XX +XXX,XX @@ static uint64_t gt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri, |
29 | - MachineClass *mc = &nmc->parent; | 40 | break; |
30 | + MachineClass *mc = MACHINE_CLASS(nmc); | 41 | } |
31 | Object *obj; | 42 | |
32 | 43 | - return (uint32_t)(env->cp15.c14_timer[timeridx].cval - | |
33 | if (strcmp(machine->cpu_type, mc->default_cpu_type) != 0) { | 44 | - (gt_get_countervalue(env) - offset)); |
34 | diff --git a/hw/mem/npcm7xx_mc.c b/hw/mem/npcm7xx_mc.c | 45 | + return do_tval_read(env, timeridx, offset); |
35 | index XXXXXXX..XXXXXXX 100644 | 46 | +} |
36 | --- a/hw/mem/npcm7xx_mc.c | 47 | + |
37 | +++ b/hw/mem/npcm7xx_mc.c | 48 | +static void do_tval_write(CPUARMState *env, int timeridx, uint64_t value, |
38 | @@ -XXX,XX +XXX,XX @@ static void npcm7xx_mc_realize(DeviceState *dev, Error **errp) | 49 | + uint64_t offset) |
39 | 50 | +{ | |
40 | memory_region_init_io(&s->mmio, OBJECT(s), &npcm7xx_mc_ops, s, "regs", | 51 | + trace_arm_gt_tval_write(timeridx, value); |
41 | NPCM7XX_MC_REGS_SIZE); | 52 | + env->cp15.c14_timer[timeridx].cval = gt_get_countervalue(env) - offset + |
42 | - sysbus_init_mmio(&s->parent, &s->mmio); | 53 | + sextract64(value, 0, 32); |
43 | + sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->mmio); | 54 | + gt_recalc_timer(env_archcpu(env), timeridx); |
44 | } | 55 | } |
45 | 56 | ||
46 | static void npcm7xx_mc_class_init(ObjectClass *klass, void *data) | 57 | static void gt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, |
47 | diff --git a/hw/misc/npcm7xx_clk.c b/hw/misc/npcm7xx_clk.c | 58 | @@ -XXX,XX +XXX,XX @@ static void gt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, |
48 | index XXXXXXX..XXXXXXX 100644 | 59 | offset = gt_phys_cnt_offset(env); |
49 | --- a/hw/misc/npcm7xx_clk.c | 60 | break; |
50 | +++ b/hw/misc/npcm7xx_clk.c | 61 | } |
51 | @@ -XXX,XX +XXX,XX @@ static void npcm7xx_clk_init(Object *obj) | 62 | - |
52 | 63 | - trace_arm_gt_tval_write(timeridx, value); | |
53 | memory_region_init_io(&s->iomem, obj, &npcm7xx_clk_ops, s, | 64 | - env->cp15.c14_timer[timeridx].cval = gt_get_countervalue(env) - offset + |
54 | TYPE_NPCM7XX_CLK, 4 * KiB); | 65 | - sextract64(value, 0, 32); |
55 | - sysbus_init_mmio(&s->parent, &s->iomem); | 66 | - gt_recalc_timer(env_archcpu(env), timeridx); |
56 | + sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem); | 67 | + do_tval_write(env, timeridx, value, offset); |
57 | } | 68 | } |
58 | 69 | ||
59 | static int npcm7xx_clk_post_load(void *opaque, int version_id) | 70 | static void gt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, |
60 | diff --git a/hw/misc/npcm7xx_gcr.c b/hw/misc/npcm7xx_gcr.c | 71 | @@ -XXX,XX +XXX,XX @@ static void gt_virt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, |
61 | index XXXXXXX..XXXXXXX 100644 | 72 | |
62 | --- a/hw/misc/npcm7xx_gcr.c | 73 | static uint64_t gt_virt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri) |
63 | +++ b/hw/misc/npcm7xx_gcr.c | 74 | { |
64 | @@ -XXX,XX +XXX,XX @@ static void npcm7xx_gcr_init(Object *obj) | 75 | - return gt_tval_read(env, ri, GTIMER_VIRT); |
65 | 76 | + /* | |
66 | memory_region_init_io(&s->iomem, obj, &npcm7xx_gcr_ops, s, | 77 | + * This is CNTV_TVAL_EL02; unlike the underlying CNTV_TVAL_EL0 |
67 | TYPE_NPCM7XX_GCR, 4 * KiB); | 78 | + * we always apply CNTVOFF_EL2. Special case that here rather |
68 | - sysbus_init_mmio(&s->parent, &s->iomem); | 79 | + * than going into the generic gt_tval_read() and then having |
69 | + sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem); | 80 | + * to re-detect that it's this register. |
81 | + * Note that the accessfn/perms mean we know we're at EL2 or EL3 here. | ||
82 | + */ | ||
83 | + return do_tval_read(env, GTIMER_VIRT, env->cp15.cntvoff_el2); | ||
70 | } | 84 | } |
71 | 85 | ||
72 | static const VMStateDescription vmstate_npcm7xx_gcr = { | 86 | static void gt_virt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, |
73 | diff --git a/hw/misc/npcm7xx_rng.c b/hw/misc/npcm7xx_rng.c | 87 | uint64_t value) |
74 | index XXXXXXX..XXXXXXX 100644 | 88 | { |
75 | --- a/hw/misc/npcm7xx_rng.c | 89 | - gt_tval_write(env, ri, GTIMER_VIRT, value); |
76 | +++ b/hw/misc/npcm7xx_rng.c | 90 | + /* Similarly for writes to CNTV_TVAL_EL02 */ |
77 | @@ -XXX,XX +XXX,XX @@ static void npcm7xx_rng_init(Object *obj) | 91 | + do_tval_write(env, GTIMER_VIRT, value, env->cp15.cntvoff_el2); |
78 | |||
79 | memory_region_init_io(&s->iomem, obj, &npcm7xx_rng_ops, s, "regs", | ||
80 | NPCM7XX_RNG_REGS_SIZE); | ||
81 | - sysbus_init_mmio(&s->parent, &s->iomem); | ||
82 | + sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem); | ||
83 | } | 92 | } |
84 | 93 | ||
85 | static const VMStateDescription vmstate_npcm7xx_rng = { | 94 | static void gt_virt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, |
86 | diff --git a/hw/nvram/npcm7xx_otp.c b/hw/nvram/npcm7xx_otp.c | ||
87 | index XXXXXXX..XXXXXXX 100644 | ||
88 | --- a/hw/nvram/npcm7xx_otp.c | ||
89 | +++ b/hw/nvram/npcm7xx_otp.c | ||
90 | @@ -XXX,XX +XXX,XX @@ static void npcm7xx_otp_realize(DeviceState *dev, Error **errp) | ||
91 | { | ||
92 | NPCM7xxOTPClass *oc = NPCM7XX_OTP_GET_CLASS(dev); | ||
93 | NPCM7xxOTPState *s = NPCM7XX_OTP(dev); | ||
94 | - SysBusDevice *sbd = &s->parent; | ||
95 | + SysBusDevice *sbd = SYS_BUS_DEVICE(dev); | ||
96 | |||
97 | memset(s->array, 0, sizeof(s->array)); | ||
98 | |||
99 | diff --git a/hw/ssi/npcm7xx_fiu.c b/hw/ssi/npcm7xx_fiu.c | ||
100 | index XXXXXXX..XXXXXXX 100644 | ||
101 | --- a/hw/ssi/npcm7xx_fiu.c | ||
102 | +++ b/hw/ssi/npcm7xx_fiu.c | ||
103 | @@ -XXX,XX +XXX,XX @@ static void npcm7xx_fiu_hold_reset(Object *obj) | ||
104 | static void npcm7xx_fiu_realize(DeviceState *dev, Error **errp) | ||
105 | { | ||
106 | NPCM7xxFIUState *s = NPCM7XX_FIU(dev); | ||
107 | - SysBusDevice *sbd = &s->parent; | ||
108 | + SysBusDevice *sbd = SYS_BUS_DEVICE(dev); | ||
109 | int i; | ||
110 | |||
111 | if (s->cs_count <= 0) { | ||
112 | -- | 95 | -- |
113 | 2.20.1 | 96 | 2.43.0 |
114 | 97 | ||
115 | 98 | diff view generated by jsdifflib |
1 | From: Hao Wu <wuhaotsh@google.com> | 1 | When reading or writing the timer registers, sometimes we need to |
---|---|---|---|
2 | 2 | apply one of the timer offsets. Specifically, this happens for | |
3 | We add a qtest for the PWM in the previous patch. It proves it works as | 3 | direct reads of the counter registers CNTPCT_EL0 and CNTVCT_EL0 (and |
4 | expected. | 4 | their self-synchronized variants CNTVCTSS_EL0 and CNTPCTSS_EL0). It |
5 | 5 | also applies for direct reads and writes of the CNT*_TVAL_EL* | |
6 | Reviewed-by: Havard Skinnemoen <hskinnemoen@google.com> | 6 | registers that provide the 32-bit downcounting view of each timer. |
7 | Reviewed-by: Tyrone Ting <kfting@nuvoton.com> | 7 | |
8 | Signed-off-by: Hao Wu <wuhaotsh@google.com> | 8 | We currently do this with duplicated code in gt_tval_read() and |
9 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 9 | gt_tval_write() and a special-case in gt_virt_cnt_read() and |
10 | Message-id: 20210108190945.949196-6-wuhaotsh@google.com | 10 | gt_cnt_read(). Refactor this so that we handle it all in a single |
11 | function gt_direct_access_timer_offset(), to parallel how we handle | ||
12 | the offset for indirect accesses. | ||
13 | |||
14 | The call in the WFIT helper previously to gt_virt_cnt_offset() is | ||
15 | now to gt_direct_access_timer_offset(); this is the correct | ||
16 | behaviour, but it's not immediately obvious that it shouldn't be | ||
17 | considered an indirect access, so we add an explanatory comment. | ||
18 | |||
19 | This commit should make no behavioural changes. | ||
20 | |||
21 | (Cc to stable because the following bugfix commit will | ||
22 | depend on this one.) | ||
23 | |||
24 | Cc: qemu-stable@nongnu.org | ||
11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 25 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
26 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | ||
27 | Message-id: 20250204125009.2281315-6-peter.maydell@linaro.org | ||
12 | --- | 28 | --- |
13 | tests/qtest/npcm7xx_pwm-test.c | 490 +++++++++++++++++++++++++++++++++ | 29 | target/arm/internals.h | 5 +- |
14 | tests/qtest/meson.build | 1 + | 30 | target/arm/helper.c | 103 +++++++++++++++++++------------------ |
15 | 2 files changed, 491 insertions(+) | 31 | target/arm/tcg/op_helper.c | 8 ++- |
16 | create mode 100644 tests/qtest/npcm7xx_pwm-test.c | 32 | 3 files changed, 62 insertions(+), 54 deletions(-) |
17 | 33 | ||
18 | diff --git a/tests/qtest/npcm7xx_pwm-test.c b/tests/qtest/npcm7xx_pwm-test.c | 34 | diff --git a/target/arm/internals.h b/target/arm/internals.h |
19 | new file mode 100644 | 35 | index XXXXXXX..XXXXXXX 100644 |
20 | index XXXXXXX..XXXXXXX | 36 | --- a/target/arm/internals.h |
21 | --- /dev/null | 37 | +++ b/target/arm/internals.h |
22 | +++ b/tests/qtest/npcm7xx_pwm-test.c | 38 | @@ -XXX,XX +XXX,XX @@ int delete_hw_watchpoint(target_ulong addr, target_ulong len, int type); |
23 | @@ -XXX,XX +XXX,XX @@ | 39 | uint64_t gt_get_countervalue(CPUARMState *env); |
24 | +/* | 40 | /* |
25 | + * QTests for Nuvoton NPCM7xx PWM Modules. | 41 | * Return the currently applicable offset between the system counter |
26 | + * | 42 | - * and CNTVCT_EL0 (this will be either 0 or the value of CNTVOFF_EL2). |
27 | + * Copyright 2020 Google LLC | 43 | + * and the counter for the specified timer, as used for direct register |
28 | + * | 44 | + * accesses. |
29 | + * This program is free software; you can redistribute it and/or modify it | 45 | */ |
30 | + * under the terms of the GNU General Public License as published by the | 46 | -uint64_t gt_virt_cnt_offset(CPUARMState *env); |
31 | + * Free Software Foundation; either version 2 of the License, or | 47 | +uint64_t gt_direct_access_timer_offset(CPUARMState *env, int timeridx); |
32 | + * (at your option) any later version. | 48 | |
33 | + * | 49 | /* |
34 | + * This program is distributed in the hope that it will be useful, but WITHOUT | 50 | * Return mask of ARMMMUIdxBit values corresponding to an "invalidate |
35 | + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | 51 | diff --git a/target/arm/helper.c b/target/arm/helper.c |
36 | + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | 52 | index XXXXXXX..XXXXXXX 100644 |
37 | + * for more details. | 53 | --- a/target/arm/helper.c |
38 | + */ | 54 | +++ b/target/arm/helper.c |
55 | @@ -XXX,XX +XXX,XX @@ static uint64_t gt_phys_raw_cnt_offset(CPUARMState *env) | ||
56 | return 0; | ||
57 | } | ||
58 | |||
59 | -static uint64_t gt_phys_cnt_offset(CPUARMState *env) | ||
60 | -{ | ||
61 | - if (arm_current_el(env) >= 2) { | ||
62 | - return 0; | ||
63 | - } | ||
64 | - return gt_phys_raw_cnt_offset(env); | ||
65 | -} | ||
66 | - | ||
67 | static uint64_t gt_indirect_access_timer_offset(CPUARMState *env, int timeridx) | ||
68 | { | ||
69 | /* | ||
70 | @@ -XXX,XX +XXX,XX @@ static uint64_t gt_indirect_access_timer_offset(CPUARMState *env, int timeridx) | ||
71 | } | ||
72 | } | ||
73 | |||
74 | +uint64_t gt_direct_access_timer_offset(CPUARMState *env, int timeridx) | ||
75 | +{ | ||
76 | + /* | ||
77 | + * Return the timer offset to use for direct accesses to the | ||
78 | + * counter registers CNTPCT and CNTVCT, and for direct accesses | ||
79 | + * to the CNT*_TVAL registers. | ||
80 | + * | ||
81 | + * This isn't exactly the same as the indirect-access offset, | ||
82 | + * because here we also care about what EL the register access | ||
83 | + * is being made from. | ||
84 | + * | ||
85 | + * This corresponds to the access pseudocode for the registers. | ||
86 | + */ | ||
87 | + uint64_t hcr; | ||
39 | + | 88 | + |
40 | +#include "qemu/osdep.h" | 89 | + switch (timeridx) { |
41 | +#include "qemu/bitops.h" | 90 | + case GTIMER_PHYS: |
42 | +#include "libqos/libqtest.h" | 91 | + if (arm_current_el(env) >= 2) { |
43 | +#include "qapi/qmp/qdict.h" | 92 | + return 0; |
44 | +#include "qapi/qmp/qnum.h" | 93 | + } |
45 | + | 94 | + return gt_phys_raw_cnt_offset(env); |
46 | +#define REF_HZ 25000000 | 95 | + case GTIMER_VIRT: |
47 | + | 96 | + switch (arm_current_el(env)) { |
48 | +/* Register field definitions. */ | 97 | + case 2: |
49 | +#define CH_EN BIT(0) | 98 | + hcr = arm_hcr_el2_eff(env); |
50 | +#define CH_INV BIT(2) | 99 | + if (hcr & HCR_E2H) { |
51 | +#define CH_MOD BIT(3) | 100 | + return 0; |
52 | + | 101 | + } |
53 | +/* Registers shared between all PWMs in a module */ | 102 | + break; |
54 | +#define PPR 0x00 | 103 | + case 0: |
55 | +#define CSR 0x04 | 104 | + hcr = arm_hcr_el2_eff(env); |
56 | +#define PCR 0x08 | 105 | + if ((hcr & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) { |
57 | +#define PIER 0x3c | 106 | + return 0; |
58 | +#define PIIR 0x40 | 107 | + } |
59 | + | 108 | + break; |
60 | +/* CLK module related */ | 109 | + } |
61 | +#define CLK_BA 0xf0801000 | 110 | + return env->cp15.cntvoff_el2; |
62 | +#define CLKSEL 0x04 | 111 | + case GTIMER_HYP: |
63 | +#define CLKDIV1 0x08 | 112 | + case GTIMER_SEC: |
64 | +#define CLKDIV2 0x2c | 113 | + case GTIMER_HYPVIRT: |
65 | +#define PLLCON0 0x0c | 114 | + return 0; |
66 | +#define PLLCON1 0x10 | ||
67 | +#define PLL_INDV(rv) extract32((rv), 0, 6) | ||
68 | +#define PLL_FBDV(rv) extract32((rv), 16, 12) | ||
69 | +#define PLL_OTDV1(rv) extract32((rv), 8, 3) | ||
70 | +#define PLL_OTDV2(rv) extract32((rv), 13, 3) | ||
71 | +#define APB3CKDIV(rv) extract32((rv), 28, 2) | ||
72 | +#define CLK2CKDIV(rv) extract32((rv), 0, 1) | ||
73 | +#define CLK4CKDIV(rv) extract32((rv), 26, 2) | ||
74 | +#define CPUCKSEL(rv) extract32((rv), 0, 2) | ||
75 | + | ||
76 | +#define MAX_DUTY 1000000 | ||
77 | + | ||
78 | +typedef struct PWMModule { | ||
79 | + int irq; | ||
80 | + uint64_t base_addr; | ||
81 | +} PWMModule; | ||
82 | + | ||
83 | +typedef struct PWM { | ||
84 | + uint32_t cnr_offset; | ||
85 | + uint32_t cmr_offset; | ||
86 | + uint32_t pdr_offset; | ||
87 | + uint32_t pwdr_offset; | ||
88 | +} PWM; | ||
89 | + | ||
90 | +typedef struct TestData { | ||
91 | + const PWMModule *module; | ||
92 | + const PWM *pwm; | ||
93 | +} TestData; | ||
94 | + | ||
95 | +static const PWMModule pwm_module_list[] = { | ||
96 | + { | ||
97 | + .irq = 93, | ||
98 | + .base_addr = 0xf0103000 | ||
99 | + }, | ||
100 | + { | ||
101 | + .irq = 94, | ||
102 | + .base_addr = 0xf0104000 | ||
103 | + } | ||
104 | +}; | ||
105 | + | ||
106 | +static const PWM pwm_list[] = { | ||
107 | + { | ||
108 | + .cnr_offset = 0x0c, | ||
109 | + .cmr_offset = 0x10, | ||
110 | + .pdr_offset = 0x14, | ||
111 | + .pwdr_offset = 0x44, | ||
112 | + }, | ||
113 | + { | ||
114 | + .cnr_offset = 0x18, | ||
115 | + .cmr_offset = 0x1c, | ||
116 | + .pdr_offset = 0x20, | ||
117 | + .pwdr_offset = 0x48, | ||
118 | + }, | ||
119 | + { | ||
120 | + .cnr_offset = 0x24, | ||
121 | + .cmr_offset = 0x28, | ||
122 | + .pdr_offset = 0x2c, | ||
123 | + .pwdr_offset = 0x4c, | ||
124 | + }, | ||
125 | + { | ||
126 | + .cnr_offset = 0x30, | ||
127 | + .cmr_offset = 0x34, | ||
128 | + .pdr_offset = 0x38, | ||
129 | + .pwdr_offset = 0x50, | ||
130 | + }, | ||
131 | +}; | ||
132 | + | ||
133 | +static const int ppr_base[] = { 0, 0, 8, 8 }; | ||
134 | +static const int csr_base[] = { 0, 4, 8, 12 }; | ||
135 | +static const int pcr_base[] = { 0, 8, 12, 16 }; | ||
136 | + | ||
137 | +static const uint32_t ppr_list[] = { | ||
138 | + 0, | ||
139 | + 1, | ||
140 | + 10, | ||
141 | + 100, | ||
142 | + 255, /* Max possible value. */ | ||
143 | +}; | ||
144 | + | ||
145 | +static const uint32_t csr_list[] = { | ||
146 | + 0, | ||
147 | + 1, | ||
148 | + 2, | ||
149 | + 3, | ||
150 | + 4, /* Max possible value. */ | ||
151 | +}; | ||
152 | + | ||
153 | +static const uint32_t cnr_list[] = { | ||
154 | + 0, | ||
155 | + 1, | ||
156 | + 50, | ||
157 | + 100, | ||
158 | + 150, | ||
159 | + 200, | ||
160 | + 1000, | ||
161 | + 10000, | ||
162 | + 65535, /* Max possible value. */ | ||
163 | +}; | ||
164 | + | ||
165 | +static const uint32_t cmr_list[] = { | ||
166 | + 0, | ||
167 | + 1, | ||
168 | + 10, | ||
169 | + 50, | ||
170 | + 100, | ||
171 | + 150, | ||
172 | + 200, | ||
173 | + 1000, | ||
174 | + 10000, | ||
175 | + 65535, /* Max possible value. */ | ||
176 | +}; | ||
177 | + | ||
178 | +/* Returns the index of the PWM module. */ | ||
179 | +static int pwm_module_index(const PWMModule *module) | ||
180 | +{ | ||
181 | + ptrdiff_t diff = module - pwm_module_list; | ||
182 | + | ||
183 | + g_assert_true(diff >= 0 && diff < ARRAY_SIZE(pwm_module_list)); | ||
184 | + | ||
185 | + return diff; | ||
186 | +} | ||
187 | + | ||
188 | +/* Returns the index of the PWM entry. */ | ||
189 | +static int pwm_index(const PWM *pwm) | ||
190 | +{ | ||
191 | + ptrdiff_t diff = pwm - pwm_list; | ||
192 | + | ||
193 | + g_assert_true(diff >= 0 && diff < ARRAY_SIZE(pwm_list)); | ||
194 | + | ||
195 | + return diff; | ||
196 | +} | ||
197 | + | ||
198 | +static uint64_t pwm_qom_get(QTestState *qts, const char *path, const char *name) | ||
199 | +{ | ||
200 | + QDict *response; | ||
201 | + | ||
202 | + g_test_message("Getting properties %s from %s", name, path); | ||
203 | + response = qtest_qmp(qts, "{ 'execute': 'qom-get'," | ||
204 | + " 'arguments': { 'path': %s, 'property': %s}}", | ||
205 | + path, name); | ||
206 | + /* The qom set message returns successfully. */ | ||
207 | + g_assert_true(qdict_haskey(response, "return")); | ||
208 | + return qnum_get_uint(qobject_to(QNum, qdict_get(response, "return"))); | ||
209 | +} | ||
210 | + | ||
211 | +static uint64_t pwm_get_freq(QTestState *qts, int module_index, int pwm_index) | ||
212 | +{ | ||
213 | + char path[100]; | ||
214 | + char name[100]; | ||
215 | + | ||
216 | + sprintf(path, "/machine/soc/pwm[%d]", module_index); | ||
217 | + sprintf(name, "freq[%d]", pwm_index); | ||
218 | + | ||
219 | + return pwm_qom_get(qts, path, name); | ||
220 | +} | ||
221 | + | ||
222 | +static uint64_t pwm_get_duty(QTestState *qts, int module_index, int pwm_index) | ||
223 | +{ | ||
224 | + char path[100]; | ||
225 | + char name[100]; | ||
226 | + | ||
227 | + sprintf(path, "/machine/soc/pwm[%d]", module_index); | ||
228 | + sprintf(name, "duty[%d]", pwm_index); | ||
229 | + | ||
230 | + return pwm_qom_get(qts, path, name); | ||
231 | +} | ||
232 | + | ||
233 | +static uint32_t get_pll(uint32_t con) | ||
234 | +{ | ||
235 | + return REF_HZ * PLL_FBDV(con) / (PLL_INDV(con) * PLL_OTDV1(con) | ||
236 | + * PLL_OTDV2(con)); | ||
237 | +} | ||
238 | + | ||
239 | +static uint64_t read_pclk(QTestState *qts) | ||
240 | +{ | ||
241 | + uint64_t freq = REF_HZ; | ||
242 | + uint32_t clksel = qtest_readl(qts, CLK_BA + CLKSEL); | ||
243 | + uint32_t pllcon; | ||
244 | + uint32_t clkdiv1 = qtest_readl(qts, CLK_BA + CLKDIV1); | ||
245 | + uint32_t clkdiv2 = qtest_readl(qts, CLK_BA + CLKDIV2); | ||
246 | + | ||
247 | + switch (CPUCKSEL(clksel)) { | ||
248 | + case 0: | ||
249 | + pllcon = qtest_readl(qts, CLK_BA + PLLCON0); | ||
250 | + freq = get_pll(pllcon); | ||
251 | + break; | ||
252 | + case 1: | ||
253 | + pllcon = qtest_readl(qts, CLK_BA + PLLCON1); | ||
254 | + freq = get_pll(pllcon); | ||
255 | + break; | ||
256 | + case 2: | ||
257 | + break; | ||
258 | + case 3: | ||
259 | + break; | ||
260 | + default: | ||
261 | + g_assert_not_reached(); | ||
262 | + } | ||
263 | + | ||
264 | + freq >>= (CLK2CKDIV(clkdiv1) + CLK4CKDIV(clkdiv1) + APB3CKDIV(clkdiv2)); | ||
265 | + | ||
266 | + return freq; | ||
267 | +} | ||
268 | + | ||
269 | +static uint32_t pwm_selector(uint32_t csr) | ||
270 | +{ | ||
271 | + switch (csr) { | ||
272 | + case 0: | ||
273 | + return 2; | ||
274 | + case 1: | ||
275 | + return 4; | ||
276 | + case 2: | ||
277 | + return 8; | ||
278 | + case 3: | ||
279 | + return 16; | ||
280 | + case 4: | ||
281 | + return 1; | ||
282 | + default: | 115 | + default: |
283 | + g_assert_not_reached(); | 116 | + g_assert_not_reached(); |
284 | + } | 117 | + } |
285 | +} | 118 | +} |
286 | + | 119 | + |
287 | +static uint64_t pwm_compute_freq(QTestState *qts, uint32_t ppr, uint32_t csr, | 120 | static void gt_recalc_timer(ARMCPU *cpu, int timeridx) |
288 | + uint32_t cnr) | 121 | { |
289 | +{ | 122 | ARMGenericTimer *gt = &cpu->env.cp15.c14_timer[timeridx]; |
290 | + return read_pclk(qts) / ((ppr + 1) * pwm_selector(csr) * (cnr + 1)); | 123 | @@ -XXX,XX +XXX,XX @@ static void gt_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri, |
291 | +} | 124 | |
292 | + | 125 | static uint64_t gt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri) |
293 | +static uint64_t pwm_compute_duty(uint32_t cnr, uint32_t cmr, bool inverted) | 126 | { |
294 | +{ | 127 | - return gt_get_countervalue(env) - gt_phys_cnt_offset(env); |
295 | + uint64_t duty; | 128 | -} |
296 | + | 129 | - |
297 | + if (cnr == 0) { | 130 | -uint64_t gt_virt_cnt_offset(CPUARMState *env) |
298 | + /* PWM is stopped. */ | 131 | -{ |
299 | + duty = 0; | 132 | - uint64_t hcr; |
300 | + } else if (cmr >= cnr) { | 133 | - |
301 | + duty = MAX_DUTY; | 134 | - switch (arm_current_el(env)) { |
302 | + } else { | 135 | - case 2: |
303 | + duty = MAX_DUTY * (cmr + 1) / (cnr + 1); | 136 | - hcr = arm_hcr_el2_eff(env); |
304 | + } | 137 | - if (hcr & HCR_E2H) { |
305 | + | 138 | - return 0; |
306 | + if (inverted) { | 139 | - } |
307 | + duty = MAX_DUTY - duty; | 140 | - break; |
308 | + } | 141 | - case 0: |
309 | + | 142 | - hcr = arm_hcr_el2_eff(env); |
310 | + return duty; | 143 | - if ((hcr & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) { |
311 | +} | 144 | - return 0; |
312 | + | 145 | - } |
313 | +static uint32_t pwm_read(QTestState *qts, const TestData *td, unsigned offset) | 146 | - break; |
314 | +{ | 147 | - } |
315 | + return qtest_readl(qts, td->module->base_addr + offset); | 148 | - |
316 | +} | 149 | - return env->cp15.cntvoff_el2; |
317 | + | 150 | + uint64_t offset = gt_direct_access_timer_offset(env, GTIMER_PHYS); |
318 | +static void pwm_write(QTestState *qts, const TestData *td, unsigned offset, | 151 | + return gt_get_countervalue(env) - offset; |
319 | + uint32_t value) | 152 | } |
320 | +{ | 153 | |
321 | + qtest_writel(qts, td->module->base_addr + offset, value); | 154 | static uint64_t gt_virt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri) |
322 | +} | 155 | { |
323 | + | 156 | - return gt_get_countervalue(env) - gt_virt_cnt_offset(env); |
324 | +static uint32_t pwm_read_ppr(QTestState *qts, const TestData *td) | 157 | + uint64_t offset = gt_direct_access_timer_offset(env, GTIMER_VIRT); |
325 | +{ | 158 | + return gt_get_countervalue(env) - offset; |
326 | + return extract32(pwm_read(qts, td, PPR), ppr_base[pwm_index(td->pwm)], 8); | 159 | } |
327 | +} | 160 | |
328 | + | 161 | static void gt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, |
329 | +static void pwm_write_ppr(QTestState *qts, const TestData *td, uint32_t value) | 162 | @@ -XXX,XX +XXX,XX @@ static uint64_t do_tval_read(CPUARMState *env, int timeridx, uint64_t offset) |
330 | +{ | 163 | static uint64_t gt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri, |
331 | + pwm_write(qts, td, PPR, value << ppr_base[pwm_index(td->pwm)]); | 164 | int timeridx) |
332 | +} | 165 | { |
333 | + | 166 | - uint64_t offset = 0; |
334 | +static uint32_t pwm_read_csr(QTestState *qts, const TestData *td) | 167 | - |
335 | +{ | 168 | - switch (timeridx) { |
336 | + return extract32(pwm_read(qts, td, CSR), csr_base[pwm_index(td->pwm)], 3); | 169 | - case GTIMER_VIRT: |
337 | +} | 170 | - offset = gt_virt_cnt_offset(env); |
338 | + | 171 | - break; |
339 | +static void pwm_write_csr(QTestState *qts, const TestData *td, uint32_t value) | 172 | - case GTIMER_PHYS: |
340 | +{ | 173 | - offset = gt_phys_cnt_offset(env); |
341 | + pwm_write(qts, td, CSR, value << csr_base[pwm_index(td->pwm)]); | 174 | - break; |
342 | +} | 175 | - } |
343 | + | 176 | + uint64_t offset = gt_direct_access_timer_offset(env, timeridx); |
344 | +static uint32_t pwm_read_pcr(QTestState *qts, const TestData *td) | 177 | |
345 | +{ | 178 | return do_tval_read(env, timeridx, offset); |
346 | + return extract32(pwm_read(qts, td, PCR), pcr_base[pwm_index(td->pwm)], 4); | 179 | } |
347 | +} | 180 | @@ -XXX,XX +XXX,XX @@ static void gt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, |
348 | + | 181 | int timeridx, |
349 | +static void pwm_write_pcr(QTestState *qts, const TestData *td, uint32_t value) | 182 | uint64_t value) |
350 | +{ | 183 | { |
351 | + pwm_write(qts, td, PCR, value << pcr_base[pwm_index(td->pwm)]); | 184 | - uint64_t offset = 0; |
352 | +} | 185 | + uint64_t offset = gt_direct_access_timer_offset(env, timeridx); |
353 | + | 186 | |
354 | +static uint32_t pwm_read_cnr(QTestState *qts, const TestData *td) | 187 | - switch (timeridx) { |
355 | +{ | 188 | - case GTIMER_VIRT: |
356 | + return pwm_read(qts, td, td->pwm->cnr_offset); | 189 | - offset = gt_virt_cnt_offset(env); |
357 | +} | 190 | - break; |
358 | + | 191 | - case GTIMER_PHYS: |
359 | +static void pwm_write_cnr(QTestState *qts, const TestData *td, uint32_t value) | 192 | - offset = gt_phys_cnt_offset(env); |
360 | +{ | 193 | - break; |
361 | + pwm_write(qts, td, td->pwm->cnr_offset, value); | 194 | - } |
362 | +} | 195 | do_tval_write(env, timeridx, value, offset); |
363 | + | 196 | } |
364 | +static uint32_t pwm_read_cmr(QTestState *qts, const TestData *td) | 197 | |
365 | +{ | 198 | diff --git a/target/arm/tcg/op_helper.c b/target/arm/tcg/op_helper.c |
366 | + return pwm_read(qts, td, td->pwm->cmr_offset); | ||
367 | +} | ||
368 | + | ||
369 | +static void pwm_write_cmr(QTestState *qts, const TestData *td, uint32_t value) | ||
370 | +{ | ||
371 | + pwm_write(qts, td, td->pwm->cmr_offset, value); | ||
372 | +} | ||
373 | + | ||
374 | +/* Check pwm registers can be reset to default value */ | ||
375 | +static void test_init(gconstpointer test_data) | ||
376 | +{ | ||
377 | + const TestData *td = test_data; | ||
378 | + QTestState *qts = qtest_init("-machine quanta-gsj"); | ||
379 | + int module = pwm_module_index(td->module); | ||
380 | + int pwm = pwm_index(td->pwm); | ||
381 | + | ||
382 | + g_assert_cmpuint(pwm_get_freq(qts, module, pwm), ==, 0); | ||
383 | + g_assert_cmpuint(pwm_get_duty(qts, module, pwm), ==, 0); | ||
384 | + | ||
385 | + qtest_quit(qts); | ||
386 | +} | ||
387 | + | ||
388 | +/* One-shot mode should not change frequency and duty cycle. */ | ||
389 | +static void test_oneshot(gconstpointer test_data) | ||
390 | +{ | ||
391 | + const TestData *td = test_data; | ||
392 | + QTestState *qts = qtest_init("-machine quanta-gsj"); | ||
393 | + int module = pwm_module_index(td->module); | ||
394 | + int pwm = pwm_index(td->pwm); | ||
395 | + uint32_t ppr, csr, pcr; | ||
396 | + int i, j; | ||
397 | + | ||
398 | + pcr = CH_EN; | ||
399 | + for (i = 0; i < ARRAY_SIZE(ppr_list); ++i) { | ||
400 | + ppr = ppr_list[i]; | ||
401 | + pwm_write_ppr(qts, td, ppr); | ||
402 | + | ||
403 | + for (j = 0; j < ARRAY_SIZE(csr_list); ++j) { | ||
404 | + csr = csr_list[j]; | ||
405 | + pwm_write_csr(qts, td, csr); | ||
406 | + pwm_write_pcr(qts, td, pcr); | ||
407 | + | ||
408 | + g_assert_cmpuint(pwm_read_ppr(qts, td), ==, ppr); | ||
409 | + g_assert_cmpuint(pwm_read_csr(qts, td), ==, csr); | ||
410 | + g_assert_cmpuint(pwm_read_pcr(qts, td), ==, pcr); | ||
411 | + g_assert_cmpuint(pwm_get_freq(qts, module, pwm), ==, 0); | ||
412 | + g_assert_cmpuint(pwm_get_duty(qts, module, pwm), ==, 0); | ||
413 | + } | ||
414 | + } | ||
415 | + | ||
416 | + qtest_quit(qts); | ||
417 | +} | ||
418 | + | ||
419 | +/* In toggle mode, the PWM generates correct outputs. */ | ||
420 | +static void test_toggle(gconstpointer test_data) | ||
421 | +{ | ||
422 | + const TestData *td = test_data; | ||
423 | + QTestState *qts = qtest_init("-machine quanta-gsj"); | ||
424 | + int module = pwm_module_index(td->module); | ||
425 | + int pwm = pwm_index(td->pwm); | ||
426 | + uint32_t ppr, csr, pcr, cnr, cmr; | ||
427 | + int i, j, k, l; | ||
428 | + uint64_t expected_freq, expected_duty; | ||
429 | + | ||
430 | + pcr = CH_EN | CH_MOD; | ||
431 | + for (i = 0; i < ARRAY_SIZE(ppr_list); ++i) { | ||
432 | + ppr = ppr_list[i]; | ||
433 | + pwm_write_ppr(qts, td, ppr); | ||
434 | + | ||
435 | + for (j = 0; j < ARRAY_SIZE(csr_list); ++j) { | ||
436 | + csr = csr_list[j]; | ||
437 | + pwm_write_csr(qts, td, csr); | ||
438 | + | ||
439 | + for (k = 0; k < ARRAY_SIZE(cnr_list); ++k) { | ||
440 | + cnr = cnr_list[k]; | ||
441 | + pwm_write_cnr(qts, td, cnr); | ||
442 | + | ||
443 | + for (l = 0; l < ARRAY_SIZE(cmr_list); ++l) { | ||
444 | + cmr = cmr_list[l]; | ||
445 | + pwm_write_cmr(qts, td, cmr); | ||
446 | + expected_freq = pwm_compute_freq(qts, ppr, csr, cnr); | ||
447 | + expected_duty = pwm_compute_duty(cnr, cmr, false); | ||
448 | + | ||
449 | + pwm_write_pcr(qts, td, pcr); | ||
450 | + g_assert_cmpuint(pwm_read_ppr(qts, td), ==, ppr); | ||
451 | + g_assert_cmpuint(pwm_read_csr(qts, td), ==, csr); | ||
452 | + g_assert_cmpuint(pwm_read_pcr(qts, td), ==, pcr); | ||
453 | + g_assert_cmpuint(pwm_read_cnr(qts, td), ==, cnr); | ||
454 | + g_assert_cmpuint(pwm_read_cmr(qts, td), ==, cmr); | ||
455 | + g_assert_cmpuint(pwm_get_duty(qts, module, pwm), | ||
456 | + ==, expected_duty); | ||
457 | + if (expected_duty != 0 && expected_duty != 100) { | ||
458 | + /* Duty cycle with 0 or 100 doesn't need frequency. */ | ||
459 | + g_assert_cmpuint(pwm_get_freq(qts, module, pwm), | ||
460 | + ==, expected_freq); | ||
461 | + } | ||
462 | + | ||
463 | + /* Test inverted mode */ | ||
464 | + expected_duty = pwm_compute_duty(cnr, cmr, true); | ||
465 | + pwm_write_pcr(qts, td, pcr | CH_INV); | ||
466 | + g_assert_cmpuint(pwm_read_pcr(qts, td), ==, pcr | CH_INV); | ||
467 | + g_assert_cmpuint(pwm_get_duty(qts, module, pwm), | ||
468 | + ==, expected_duty); | ||
469 | + if (expected_duty != 0 && expected_duty != 100) { | ||
470 | + /* Duty cycle with 0 or 100 doesn't need frequency. */ | ||
471 | + g_assert_cmpuint(pwm_get_freq(qts, module, pwm), | ||
472 | + ==, expected_freq); | ||
473 | + } | ||
474 | + | ||
475 | + } | ||
476 | + } | ||
477 | + } | ||
478 | + } | ||
479 | + | ||
480 | + qtest_quit(qts); | ||
481 | +} | ||
482 | + | ||
483 | +static void pwm_add_test(const char *name, const TestData* td, | ||
484 | + GTestDataFunc fn) | ||
485 | +{ | ||
486 | + g_autofree char *full_name = g_strdup_printf( | ||
487 | + "npcm7xx_pwm/module[%d]/pwm[%d]/%s", pwm_module_index(td->module), | ||
488 | + pwm_index(td->pwm), name); | ||
489 | + qtest_add_data_func(full_name, td, fn); | ||
490 | +} | ||
491 | +#define add_test(name, td) pwm_add_test(#name, td, test_##name) | ||
492 | + | ||
493 | +int main(int argc, char **argv) | ||
494 | +{ | ||
495 | + TestData test_data_list[ARRAY_SIZE(pwm_module_list) * ARRAY_SIZE(pwm_list)]; | ||
496 | + | ||
497 | + g_test_init(&argc, &argv, NULL); | ||
498 | + | ||
499 | + for (int i = 0; i < ARRAY_SIZE(pwm_module_list); ++i) { | ||
500 | + for (int j = 0; j < ARRAY_SIZE(pwm_list); ++j) { | ||
501 | + TestData *td = &test_data_list[i * ARRAY_SIZE(pwm_list) + j]; | ||
502 | + | ||
503 | + td->module = &pwm_module_list[i]; | ||
504 | + td->pwm = &pwm_list[j]; | ||
505 | + | ||
506 | + add_test(init, td); | ||
507 | + add_test(oneshot, td); | ||
508 | + add_test(toggle, td); | ||
509 | + } | ||
510 | + } | ||
511 | + | ||
512 | + return g_test_run(); | ||
513 | +} | ||
514 | diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build | ||
515 | index XXXXXXX..XXXXXXX 100644 | 199 | index XXXXXXX..XXXXXXX 100644 |
516 | --- a/tests/qtest/meson.build | 200 | --- a/target/arm/tcg/op_helper.c |
517 | +++ b/tests/qtest/meson.build | 201 | +++ b/target/arm/tcg/op_helper.c |
518 | @@ -XXX,XX +XXX,XX @@ qtests_sparc64 = \ | 202 | @@ -XXX,XX +XXX,XX @@ void HELPER(wfit)(CPUARMState *env, uint64_t timeout) |
519 | qtests_npcm7xx = \ | 203 | int target_el = check_wfx_trap(env, false, &excp); |
520 | ['npcm7xx_adc-test', | 204 | /* The WFIT should time out when CNTVCT_EL0 >= the specified value. */ |
521 | 'npcm7xx_gpio-test', | 205 | uint64_t cntval = gt_get_countervalue(env); |
522 | + 'npcm7xx_pwm-test', | 206 | - uint64_t offset = gt_virt_cnt_offset(env); |
523 | 'npcm7xx_rng-test', | 207 | + /* |
524 | 'npcm7xx_timer-test', | 208 | + * We want the value that we would get if we read CNTVCT_EL0 from |
525 | 'npcm7xx_watchdog_timer-test'] | 209 | + * the current exception level, so the direct_access offset, not |
210 | + * the indirect_access one. Compare the pseudocode LocalTimeoutEvent(), | ||
211 | + * which calls VirtualCounterTimer(). | ||
212 | + */ | ||
213 | + uint64_t offset = gt_direct_access_timer_offset(env, GTIMER_VIRT); | ||
214 | uint64_t cntvct = cntval - offset; | ||
215 | uint64_t nexttick; | ||
216 | |||
526 | -- | 217 | -- |
527 | 2.20.1 | 218 | 2.43.0 |
528 | 219 | ||
529 | 220 | diff view generated by jsdifflib |
1 | From: Hao Wu <wuhaotsh@google.com> | 1 | From: Alex Bennée <alex.bennee@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | This patch allows NPCM7XX CLK module to compute clocks that are used by | 3 | When FEAT_SEL2 was implemented the SEL2 timers were missed. This |
4 | other NPCM7XX modules. | 4 | shows up when building the latest Hafnium with SPMC_AT_EL=2. The |
5 | 5 | actual implementation utilises the same logic as the rest of the | |
6 | Add a new struct NPCM7xxClockConverterState which represents a | 6 | timers so all we need to do is: |
7 | single converter. Each clock converter in CLK module represents one | 7 | |
8 | converter in NPCM7XX CLK Module(PLL, SEL or Divider). Each converter | 8 | - define the timers and their access functions |
9 | takes one or more input clocks and converts them into one output clock. | 9 | - conditionally add the correct system registers |
10 | They form a clock hierarchy in the CLK module and are responsible for | 10 | - create a new accessfn as the rules are subtly different to the |
11 | outputing clocks for various other modules in an NPCM7XX SoC. | 11 | existing secure timer |
12 | 12 | ||
13 | Each converter has a function pointer called "convert" which represents | 13 | Fixes: e9152ee91c (target/arm: add ARMv8.4-SEL2 system registers) |
14 | the unique logic for that converter. | 14 | Signed-off-by: Alex Bennée <alex.bennee@linaro.org> |
15 | 15 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | |
16 | The clock contains two initialization information: ConverterInitInfo and | ||
17 | ConverterConnectionInfo. They represent the vertices and edges in the | ||
18 | clock diagram respectively. | ||
19 | |||
20 | Reviewed-by: Havard Skinnemoen <hskinnemoen@google.com> | ||
21 | Reviewed-by: Tyrone Ting <kfting@nuvoton.com> | ||
22 | Signed-off-by: Hao Wu <wuhaotsh@google.com> | ||
23 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 16 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
24 | Message-id: 20210108190945.949196-2-wuhaotsh@google.com | 17 | Message-id: 20250204125009.2281315-7-peter.maydell@linaro.org |
18 | Cc: qemu-stable@nongnu.org | ||
19 | Cc: Andrei Homescu <ahomescu@google.com> | ||
20 | Cc: Arve Hjønnevåg <arve@google.com> | ||
21 | Cc: Rémi Denis-Courmont <remi.denis.courmont@huawei.com> | ||
22 | [PMM: CP_ACCESS_TRAP_UNCATEGORIZED -> CP_ACCESS_UNDEFINED; | ||
23 | offset logic now in gt_{indirect,direct}_access_timer_offset() ] | ||
24 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
25 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 25 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
26 | --- | 26 | --- |
27 | include/hw/misc/npcm7xx_clk.h | 140 +++++- | 27 | include/hw/arm/bsa.h | 2 + |
28 | hw/misc/npcm7xx_clk.c | 805 +++++++++++++++++++++++++++++++++- | 28 | target/arm/cpu.h | 2 + |
29 | 2 files changed, 932 insertions(+), 13 deletions(-) | 29 | target/arm/gtimer.h | 4 +- |
30 | 30 | target/arm/cpu.c | 4 ++ | |
31 | diff --git a/include/hw/misc/npcm7xx_clk.h b/include/hw/misc/npcm7xx_clk.h | 31 | target/arm/helper.c | 163 +++++++++++++++++++++++++++++++++++++++++++ |
32 | index XXXXXXX..XXXXXXX 100644 | 32 | 5 files changed, 174 insertions(+), 1 deletion(-) |
33 | --- a/include/hw/misc/npcm7xx_clk.h | 33 | |
34 | +++ b/include/hw/misc/npcm7xx_clk.h | 34 | diff --git a/include/hw/arm/bsa.h b/include/hw/arm/bsa.h |
35 | index XXXXXXX..XXXXXXX 100644 | ||
36 | --- a/include/hw/arm/bsa.h | ||
37 | +++ b/include/hw/arm/bsa.h | ||
35 | @@ -XXX,XX +XXX,XX @@ | 38 | @@ -XXX,XX +XXX,XX @@ |
36 | #define NPCM7XX_CLK_H | 39 | #define QEMU_ARM_BSA_H |
37 | 40 | ||
38 | #include "exec/memory.h" | 41 | /* These are architectural INTID values */ |
39 | +#include "hw/clock.h" | 42 | +#define ARCH_TIMER_S_EL2_VIRT_IRQ 19 |
40 | #include "hw/sysbus.h" | 43 | +#define ARCH_TIMER_S_EL2_IRQ 20 |
41 | 44 | #define VIRTUAL_PMU_IRQ 23 | |
42 | /* | 45 | #define ARCH_GIC_MAINT_IRQ 25 |
43 | @@ -XXX,XX +XXX,XX @@ | 46 | #define ARCH_TIMER_NS_EL2_IRQ 26 |
44 | 47 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | |
45 | #define NPCM7XX_WATCHDOG_RESET_GPIO_IN "npcm7xx-clk-watchdog-reset-gpio-in" | 48 | index XXXXXXX..XXXXXXX 100644 |
46 | 49 | --- a/target/arm/cpu.h | |
47 | -typedef struct NPCM7xxCLKState { | 50 | +++ b/target/arm/cpu.h |
48 | +/* Maximum amount of clock inputs in a SEL module. */ | 51 | @@ -XXX,XX +XXX,XX @@ void arm_gt_vtimer_cb(void *opaque); |
49 | +#define NPCM7XX_CLK_SEL_MAX_INPUT 5 | 52 | void arm_gt_htimer_cb(void *opaque); |
50 | + | 53 | void arm_gt_stimer_cb(void *opaque); |
51 | +/* PLLs in CLK module. */ | 54 | void arm_gt_hvtimer_cb(void *opaque); |
52 | +typedef enum NPCM7xxClockPLL { | 55 | +void arm_gt_sel2timer_cb(void *opaque); |
53 | + NPCM7XX_CLOCK_PLL0, | 56 | +void arm_gt_sel2vtimer_cb(void *opaque); |
54 | + NPCM7XX_CLOCK_PLL1, | 57 | |
55 | + NPCM7XX_CLOCK_PLL2, | 58 | unsigned int gt_cntfrq_period_ns(ARMCPU *cpu); |
56 | + NPCM7XX_CLOCK_PLLG, | 59 | void gt_rme_post_el_change(ARMCPU *cpu, void *opaque); |
57 | + NPCM7XX_CLOCK_NR_PLLS, | 60 | diff --git a/target/arm/gtimer.h b/target/arm/gtimer.h |
58 | +} NPCM7xxClockPLL; | 61 | index XXXXXXX..XXXXXXX 100644 |
59 | + | 62 | --- a/target/arm/gtimer.h |
60 | +/* SEL/MUX in CLK module. */ | 63 | +++ b/target/arm/gtimer.h |
61 | +typedef enum NPCM7xxClockSEL { | 64 | @@ -XXX,XX +XXX,XX @@ enum { |
62 | + NPCM7XX_CLOCK_PIXCKSEL, | 65 | GTIMER_HYP = 2, |
63 | + NPCM7XX_CLOCK_MCCKSEL, | 66 | GTIMER_SEC = 3, |
64 | + NPCM7XX_CLOCK_CPUCKSEL, | 67 | GTIMER_HYPVIRT = 4, |
65 | + NPCM7XX_CLOCK_CLKOUTSEL, | 68 | -#define NUM_GTIMERS 5 |
66 | + NPCM7XX_CLOCK_UARTCKSEL, | 69 | + GTIMER_S_EL2_PHYS = 5, /* CNTHPS_* ; only if FEAT_SEL2 */ |
67 | + NPCM7XX_CLOCK_TIMCKSEL, | 70 | + GTIMER_S_EL2_VIRT = 6, /* CNTHVS_* ; only if FEAT_SEL2 */ |
68 | + NPCM7XX_CLOCK_SDCKSEL, | 71 | +#define NUM_GTIMERS 7 |
69 | + NPCM7XX_CLOCK_GFXMSEL, | ||
70 | + NPCM7XX_CLOCK_SUCKSEL, | ||
71 | + NPCM7XX_CLOCK_NR_SELS, | ||
72 | +} NPCM7xxClockSEL; | ||
73 | + | ||
74 | +/* Dividers in CLK module. */ | ||
75 | +typedef enum NPCM7xxClockDivider { | ||
76 | + NPCM7XX_CLOCK_PLL1D2, /* PLL1/2 */ | ||
77 | + NPCM7XX_CLOCK_PLL2D2, /* PLL2/2 */ | ||
78 | + NPCM7XX_CLOCK_MC_DIVIDER, | ||
79 | + NPCM7XX_CLOCK_AXI_DIVIDER, | ||
80 | + NPCM7XX_CLOCK_AHB_DIVIDER, | ||
81 | + NPCM7XX_CLOCK_AHB3_DIVIDER, | ||
82 | + NPCM7XX_CLOCK_SPI0_DIVIDER, | ||
83 | + NPCM7XX_CLOCK_SPIX_DIVIDER, | ||
84 | + NPCM7XX_CLOCK_APB1_DIVIDER, | ||
85 | + NPCM7XX_CLOCK_APB2_DIVIDER, | ||
86 | + NPCM7XX_CLOCK_APB3_DIVIDER, | ||
87 | + NPCM7XX_CLOCK_APB4_DIVIDER, | ||
88 | + NPCM7XX_CLOCK_APB5_DIVIDER, | ||
89 | + NPCM7XX_CLOCK_CLKOUT_DIVIDER, | ||
90 | + NPCM7XX_CLOCK_UART_DIVIDER, | ||
91 | + NPCM7XX_CLOCK_TIMER_DIVIDER, | ||
92 | + NPCM7XX_CLOCK_ADC_DIVIDER, | ||
93 | + NPCM7XX_CLOCK_MMC_DIVIDER, | ||
94 | + NPCM7XX_CLOCK_SDHC_DIVIDER, | ||
95 | + NPCM7XX_CLOCK_GFXM_DIVIDER, /* divide by 3 */ | ||
96 | + NPCM7XX_CLOCK_UTMI_DIVIDER, | ||
97 | + NPCM7XX_CLOCK_NR_DIVIDERS, | ||
98 | +} NPCM7xxClockConverter; | ||
99 | + | ||
100 | +typedef struct NPCM7xxCLKState NPCM7xxCLKState; | ||
101 | + | ||
102 | +/** | ||
103 | + * struct NPCM7xxClockPLLState - A PLL module in CLK module. | ||
104 | + * @name: The name of the module. | ||
105 | + * @clk: The CLK module that owns this module. | ||
106 | + * @clock_in: The input clock of this module. | ||
107 | + * @clock_out: The output clock of this module. | ||
108 | + * @reg: The control registers for this PLL module. | ||
109 | + */ | ||
110 | +typedef struct NPCM7xxClockPLLState { | ||
111 | + DeviceState parent; | ||
112 | + | ||
113 | + const char *name; | ||
114 | + NPCM7xxCLKState *clk; | ||
115 | + Clock *clock_in; | ||
116 | + Clock *clock_out; | ||
117 | + | ||
118 | + int reg; | ||
119 | +} NPCM7xxClockPLLState; | ||
120 | + | ||
121 | +/** | ||
122 | + * struct NPCM7xxClockSELState - A SEL module in CLK module. | ||
123 | + * @name: The name of the module. | ||
124 | + * @clk: The CLK module that owns this module. | ||
125 | + * @input_size: The size of inputs of this module. | ||
126 | + * @clock_in: The input clocks of this module. | ||
127 | + * @clock_out: The output clocks of this module. | ||
128 | + * @offset: The offset of this module in the control register. | ||
129 | + * @len: The length of this module in the control register. | ||
130 | + */ | ||
131 | +typedef struct NPCM7xxClockSELState { | ||
132 | + DeviceState parent; | ||
133 | + | ||
134 | + const char *name; | ||
135 | + NPCM7xxCLKState *clk; | ||
136 | + uint8_t input_size; | ||
137 | + Clock *clock_in[NPCM7XX_CLK_SEL_MAX_INPUT]; | ||
138 | + Clock *clock_out; | ||
139 | + | ||
140 | + int offset; | ||
141 | + int len; | ||
142 | +} NPCM7xxClockSELState; | ||
143 | + | ||
144 | +/** | ||
145 | + * struct NPCM7xxClockDividerState - A Divider module in CLK module. | ||
146 | + * @name: The name of the module. | ||
147 | + * @clk: The CLK module that owns this module. | ||
148 | + * @clock_in: The input clock of this module. | ||
149 | + * @clock_out: The output clock of this module. | ||
150 | + * @divide: The function the divider uses to divide the input. | ||
151 | + * @reg: The index of the control register that contains the divisor. | ||
152 | + * @offset: The offset of the divisor in the control register. | ||
153 | + * @len: The length of the divisor in the control register. | ||
154 | + * @divisor: The divisor for a constant divisor | ||
155 | + */ | ||
156 | +typedef struct NPCM7xxClockDividerState { | ||
157 | + DeviceState parent; | ||
158 | + | ||
159 | + const char *name; | ||
160 | + NPCM7xxCLKState *clk; | ||
161 | + Clock *clock_in; | ||
162 | + Clock *clock_out; | ||
163 | + | ||
164 | + uint32_t (*divide)(struct NPCM7xxClockDividerState *s); | ||
165 | + union { | ||
166 | + struct { | ||
167 | + int reg; | ||
168 | + int offset; | ||
169 | + int len; | ||
170 | + }; | ||
171 | + int divisor; | ||
172 | + }; | ||
173 | +} NPCM7xxClockDividerState; | ||
174 | + | ||
175 | +struct NPCM7xxCLKState { | ||
176 | SysBusDevice parent; | ||
177 | |||
178 | MemoryRegion iomem; | ||
179 | |||
180 | + /* Clock converters */ | ||
181 | + NPCM7xxClockPLLState plls[NPCM7XX_CLOCK_NR_PLLS]; | ||
182 | + NPCM7xxClockSELState sels[NPCM7XX_CLOCK_NR_SELS]; | ||
183 | + NPCM7xxClockDividerState dividers[NPCM7XX_CLOCK_NR_DIVIDERS]; | ||
184 | + | ||
185 | uint32_t regs[NPCM7XX_CLK_NR_REGS]; | ||
186 | |||
187 | /* Time reference for SECCNT and CNTR25M, initialized by power on reset */ | ||
188 | int64_t ref_ns; | ||
189 | -} NPCM7xxCLKState; | ||
190 | + | ||
191 | + /* The incoming reference clock. */ | ||
192 | + Clock *clkref; | ||
193 | +}; | ||
194 | |||
195 | #define TYPE_NPCM7XX_CLK "npcm7xx-clk" | ||
196 | #define NPCM7XX_CLK(obj) OBJECT_CHECK(NPCM7xxCLKState, (obj), TYPE_NPCM7XX_CLK) | ||
197 | diff --git a/hw/misc/npcm7xx_clk.c b/hw/misc/npcm7xx_clk.c | ||
198 | index XXXXXXX..XXXXXXX 100644 | ||
199 | --- a/hw/misc/npcm7xx_clk.c | ||
200 | +++ b/hw/misc/npcm7xx_clk.c | ||
201 | @@ -XXX,XX +XXX,XX @@ | ||
202 | |||
203 | #include "hw/misc/npcm7xx_clk.h" | ||
204 | #include "hw/timer/npcm7xx_timer.h" | ||
205 | +#include "hw/qdev-clock.h" | ||
206 | #include "migration/vmstate.h" | ||
207 | #include "qemu/error-report.h" | ||
208 | #include "qemu/log.h" | ||
209 | @@ -XXX,XX +XXX,XX @@ | ||
210 | #include "trace.h" | ||
211 | #include "sysemu/watchdog.h" | ||
212 | |||
213 | +/* | ||
214 | + * The reference clock hz, and the SECCNT and CNTR25M registers in this module, | ||
215 | + * is always 25 MHz. | ||
216 | + */ | ||
217 | +#define NPCM7XX_CLOCK_REF_HZ (25000000) | ||
218 | + | ||
219 | +/* Register Field Definitions */ | ||
220 | +#define NPCM7XX_CLK_WDRCR_CA9C BIT(0) /* Cortex A9 Cores */ | ||
221 | + | ||
222 | #define PLLCON_LOKI BIT(31) | ||
223 | #define PLLCON_LOKS BIT(30) | ||
224 | #define PLLCON_PWDEN BIT(12) | ||
225 | +#define PLLCON_FBDV(con) extract32((con), 16, 12) | ||
226 | +#define PLLCON_OTDV2(con) extract32((con), 13, 3) | ||
227 | +#define PLLCON_OTDV1(con) extract32((con), 8, 3) | ||
228 | +#define PLLCON_INDV(con) extract32((con), 0, 6) | ||
229 | |||
230 | enum NPCM7xxCLKRegisters { | ||
231 | NPCM7XX_CLK_CLKEN1, | ||
232 | @@ -XXX,XX +XXX,XX @@ static const uint32_t cold_reset_values[NPCM7XX_CLK_NR_REGS] = { | ||
233 | [NPCM7XX_CLK_AHBCKFI] = 0x000000c8, | ||
234 | }; | 72 | }; |
235 | 73 | ||
236 | -/* Register Field Definitions */ | 74 | #endif |
237 | -#define NPCM7XX_CLK_WDRCR_CA9C BIT(0) /* Cortex A9 Cores */ | 75 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c |
238 | - | 76 | index XXXXXXX..XXXXXXX 100644 |
239 | /* The number of watchdogs that can trigger a reset. */ | 77 | --- a/target/arm/cpu.c |
240 | #define NPCM7XX_NR_WATCHDOGS (3) | 78 | +++ b/target/arm/cpu.c |
241 | 79 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) | |
242 | +/* Clock converter functions */ | 80 | arm_gt_stimer_cb, cpu); |
243 | + | 81 | cpu->gt_timer[GTIMER_HYPVIRT] = timer_new(QEMU_CLOCK_VIRTUAL, scale, |
244 | +#define TYPE_NPCM7XX_CLOCK_PLL "npcm7xx-clock-pll" | 82 | arm_gt_hvtimer_cb, cpu); |
245 | +#define NPCM7XX_CLOCK_PLL(obj) OBJECT_CHECK(NPCM7xxClockPLLState, \ | 83 | + cpu->gt_timer[GTIMER_S_EL2_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, scale, |
246 | + (obj), TYPE_NPCM7XX_CLOCK_PLL) | 84 | + arm_gt_sel2timer_cb, cpu); |
247 | +#define TYPE_NPCM7XX_CLOCK_SEL "npcm7xx-clock-sel" | 85 | + cpu->gt_timer[GTIMER_S_EL2_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, scale, |
248 | +#define NPCM7XX_CLOCK_SEL(obj) OBJECT_CHECK(NPCM7xxClockSELState, \ | 86 | + arm_gt_sel2vtimer_cb, cpu); |
249 | + (obj), TYPE_NPCM7XX_CLOCK_SEL) | 87 | } |
250 | +#define TYPE_NPCM7XX_CLOCK_DIVIDER "npcm7xx-clock-divider" | 88 | #endif |
251 | +#define NPCM7XX_CLOCK_DIVIDER(obj) OBJECT_CHECK(NPCM7xxClockDividerState, \ | 89 | |
252 | + (obj), TYPE_NPCM7XX_CLOCK_DIVIDER) | 90 | diff --git a/target/arm/helper.c b/target/arm/helper.c |
253 | + | 91 | index XXXXXXX..XXXXXXX 100644 |
254 | +static void npcm7xx_clk_update_pll(void *opaque) | 92 | --- a/target/arm/helper.c |
255 | +{ | 93 | +++ b/target/arm/helper.c |
256 | + NPCM7xxClockPLLState *s = opaque; | 94 | @@ -XXX,XX +XXX,XX @@ static CPAccessResult gt_stimer_access(CPUARMState *env, |
257 | + uint32_t con = s->clk->regs[s->reg]; | 95 | } |
258 | + uint64_t freq; | 96 | } |
259 | + | 97 | |
260 | + /* The PLL is grounded if it is not locked yet. */ | 98 | +static CPAccessResult gt_sel2timer_access(CPUARMState *env, |
261 | + if (con & PLLCON_LOKI) { | 99 | + const ARMCPRegInfo *ri, |
262 | + freq = clock_get_hz(s->clock_in); | 100 | + bool isread) |
263 | + freq *= PLLCON_FBDV(con); | 101 | +{ |
264 | + freq /= PLLCON_INDV(con) * PLLCON_OTDV1(con) * PLLCON_OTDV2(con); | 102 | + /* |
265 | + } else { | 103 | + * The AArch64 register view of the secure EL2 timers are mostly |
266 | + freq = 0; | 104 | + * accessible from EL3 and EL2 although can also be trapped to EL2 |
267 | + } | 105 | + * from EL1 depending on nested virt config. |
268 | + | 106 | + */ |
269 | + clock_update_hz(s->clock_out, freq); | 107 | + switch (arm_current_el(env)) { |
270 | +} | 108 | + case 0: /* UNDEFINED */ |
271 | + | 109 | + return CP_ACCESS_UNDEFINED; |
272 | +static void npcm7xx_clk_update_sel(void *opaque) | 110 | + case 1: |
273 | +{ | 111 | + if (!arm_is_secure(env)) { |
274 | + NPCM7xxClockSELState *s = opaque; | 112 | + /* UNDEFINED */ |
275 | + uint32_t index = extract32(s->clk->regs[NPCM7XX_CLK_CLKSEL], s->offset, | 113 | + return CP_ACCESS_UNDEFINED; |
276 | + s->len); | 114 | + } else if (arm_hcr_el2_eff(env) & HCR_NV) { |
277 | + | 115 | + /* Aarch64.SystemAccessTrap(EL2, 0x18) */ |
278 | + if (index >= s->input_size) { | 116 | + return CP_ACCESS_TRAP_EL2; |
279 | + qemu_log_mask(LOG_GUEST_ERROR, | 117 | + } |
280 | + "%s: SEL index: %u out of range\n", | 118 | + /* UNDEFINED */ |
281 | + __func__, index); | 119 | + return CP_ACCESS_UNDEFINED; |
282 | + index = 0; | 120 | + case 2: |
283 | + } | 121 | + if (!arm_is_secure(env)) { |
284 | + clock_update_hz(s->clock_out, clock_get_hz(s->clock_in[index])); | 122 | + /* UNDEFINED */ |
285 | +} | 123 | + return CP_ACCESS_UNDEFINED; |
286 | + | 124 | + } |
287 | +static void npcm7xx_clk_update_divider(void *opaque) | 125 | + return CP_ACCESS_OK; |
288 | +{ | 126 | + case 3: |
289 | + NPCM7xxClockDividerState *s = opaque; | 127 | + if (env->cp15.scr_el3 & SCR_EEL2) { |
290 | + uint32_t freq; | 128 | + return CP_ACCESS_OK; |
291 | + | 129 | + } else { |
292 | + freq = s->divide(s); | 130 | + return CP_ACCESS_UNDEFINED; |
293 | + clock_update_hz(s->clock_out, freq); | 131 | + } |
294 | +} | ||
295 | + | ||
296 | +static uint32_t divide_by_constant(NPCM7xxClockDividerState *s) | ||
297 | +{ | ||
298 | + return clock_get_hz(s->clock_in) / s->divisor; | ||
299 | +} | ||
300 | + | ||
301 | +static uint32_t divide_by_reg_divisor(NPCM7xxClockDividerState *s) | ||
302 | +{ | ||
303 | + return clock_get_hz(s->clock_in) / | ||
304 | + (extract32(s->clk->regs[s->reg], s->offset, s->len) + 1); | ||
305 | +} | ||
306 | + | ||
307 | +static uint32_t divide_by_reg_divisor_times_2(NPCM7xxClockDividerState *s) | ||
308 | +{ | ||
309 | + return divide_by_reg_divisor(s) / 2; | ||
310 | +} | ||
311 | + | ||
312 | +static uint32_t shift_by_reg_divisor(NPCM7xxClockDividerState *s) | ||
313 | +{ | ||
314 | + return clock_get_hz(s->clock_in) >> | ||
315 | + extract32(s->clk->regs[s->reg], s->offset, s->len); | ||
316 | +} | ||
317 | + | ||
318 | +static NPCM7xxClockPLL find_pll_by_reg(enum NPCM7xxCLKRegisters reg) | ||
319 | +{ | ||
320 | + switch (reg) { | ||
321 | + case NPCM7XX_CLK_PLLCON0: | ||
322 | + return NPCM7XX_CLOCK_PLL0; | ||
323 | + case NPCM7XX_CLK_PLLCON1: | ||
324 | + return NPCM7XX_CLOCK_PLL1; | ||
325 | + case NPCM7XX_CLK_PLLCON2: | ||
326 | + return NPCM7XX_CLOCK_PLL2; | ||
327 | + case NPCM7XX_CLK_PLLCONG: | ||
328 | + return NPCM7XX_CLOCK_PLLG; | ||
329 | + default: | 132 | + default: |
330 | + g_assert_not_reached(); | 133 | + g_assert_not_reached(); |
331 | + } | 134 | + } |
332 | +} | 135 | +} |
333 | + | 136 | + |
334 | +static void npcm7xx_clk_update_all_plls(NPCM7xxCLKState *clk) | 137 | uint64_t gt_get_countervalue(CPUARMState *env) |
335 | +{ | ||
336 | + int i; | ||
337 | + | ||
338 | + for (i = 0; i < NPCM7XX_CLOCK_NR_PLLS; ++i) { | ||
339 | + npcm7xx_clk_update_pll(&clk->plls[i]); | ||
340 | + } | ||
341 | +} | ||
342 | + | ||
343 | +static void npcm7xx_clk_update_all_sels(NPCM7xxCLKState *clk) | ||
344 | +{ | ||
345 | + int i; | ||
346 | + | ||
347 | + for (i = 0; i < NPCM7XX_CLOCK_NR_SELS; ++i) { | ||
348 | + npcm7xx_clk_update_sel(&clk->sels[i]); | ||
349 | + } | ||
350 | +} | ||
351 | + | ||
352 | +static void npcm7xx_clk_update_all_dividers(NPCM7xxCLKState *clk) | ||
353 | +{ | ||
354 | + int i; | ||
355 | + | ||
356 | + for (i = 0; i < NPCM7XX_CLOCK_NR_DIVIDERS; ++i) { | ||
357 | + npcm7xx_clk_update_divider(&clk->dividers[i]); | ||
358 | + } | ||
359 | +} | ||
360 | + | ||
361 | +static void npcm7xx_clk_update_all_clocks(NPCM7xxCLKState *clk) | ||
362 | +{ | ||
363 | + clock_update_hz(clk->clkref, NPCM7XX_CLOCK_REF_HZ); | ||
364 | + npcm7xx_clk_update_all_plls(clk); | ||
365 | + npcm7xx_clk_update_all_sels(clk); | ||
366 | + npcm7xx_clk_update_all_dividers(clk); | ||
367 | +} | ||
368 | + | ||
369 | +/* Types of clock sources. */ | ||
370 | +typedef enum ClockSrcType { | ||
371 | + CLKSRC_REF, | ||
372 | + CLKSRC_PLL, | ||
373 | + CLKSRC_SEL, | ||
374 | + CLKSRC_DIV, | ||
375 | +} ClockSrcType; | ||
376 | + | ||
377 | +typedef struct PLLInitInfo { | ||
378 | + const char *name; | ||
379 | + ClockSrcType src_type; | ||
380 | + int src_index; | ||
381 | + int reg; | ||
382 | + const char *public_name; | ||
383 | +} PLLInitInfo; | ||
384 | + | ||
385 | +typedef struct SELInitInfo { | ||
386 | + const char *name; | ||
387 | + uint8_t input_size; | ||
388 | + ClockSrcType src_type[NPCM7XX_CLK_SEL_MAX_INPUT]; | ||
389 | + int src_index[NPCM7XX_CLK_SEL_MAX_INPUT]; | ||
390 | + int offset; | ||
391 | + int len; | ||
392 | + const char *public_name; | ||
393 | +} SELInitInfo; | ||
394 | + | ||
395 | +typedef struct DividerInitInfo { | ||
396 | + const char *name; | ||
397 | + ClockSrcType src_type; | ||
398 | + int src_index; | ||
399 | + uint32_t (*divide)(NPCM7xxClockDividerState *s); | ||
400 | + int reg; /* not used when type == CONSTANT */ | ||
401 | + int offset; /* not used when type == CONSTANT */ | ||
402 | + int len; /* not used when type == CONSTANT */ | ||
403 | + int divisor; /* used only when type == CONSTANT */ | ||
404 | + const char *public_name; | ||
405 | +} DividerInitInfo; | ||
406 | + | ||
407 | +static const PLLInitInfo pll_init_info_list[] = { | ||
408 | + [NPCM7XX_CLOCK_PLL0] = { | ||
409 | + .name = "pll0", | ||
410 | + .src_type = CLKSRC_REF, | ||
411 | + .reg = NPCM7XX_CLK_PLLCON0, | ||
412 | + }, | ||
413 | + [NPCM7XX_CLOCK_PLL1] = { | ||
414 | + .name = "pll1", | ||
415 | + .src_type = CLKSRC_REF, | ||
416 | + .reg = NPCM7XX_CLK_PLLCON1, | ||
417 | + }, | ||
418 | + [NPCM7XX_CLOCK_PLL2] = { | ||
419 | + .name = "pll2", | ||
420 | + .src_type = CLKSRC_REF, | ||
421 | + .reg = NPCM7XX_CLK_PLLCON2, | ||
422 | + }, | ||
423 | + [NPCM7XX_CLOCK_PLLG] = { | ||
424 | + .name = "pllg", | ||
425 | + .src_type = CLKSRC_REF, | ||
426 | + .reg = NPCM7XX_CLK_PLLCONG, | ||
427 | + }, | ||
428 | +}; | ||
429 | + | ||
430 | +static const SELInitInfo sel_init_info_list[] = { | ||
431 | + [NPCM7XX_CLOCK_PIXCKSEL] = { | ||
432 | + .name = "pixcksel", | ||
433 | + .input_size = 2, | ||
434 | + .src_type = {CLKSRC_PLL, CLKSRC_REF}, | ||
435 | + .src_index = {NPCM7XX_CLOCK_PLLG, 0}, | ||
436 | + .offset = 5, | ||
437 | + .len = 1, | ||
438 | + .public_name = "pixel-clock", | ||
439 | + }, | ||
440 | + [NPCM7XX_CLOCK_MCCKSEL] = { | ||
441 | + .name = "mccksel", | ||
442 | + .input_size = 4, | ||
443 | + .src_type = {CLKSRC_DIV, CLKSRC_REF, CLKSRC_REF, | ||
444 | + /*MCBPCK, shouldn't be used in normal operation*/ | ||
445 | + CLKSRC_REF}, | ||
446 | + .src_index = {NPCM7XX_CLOCK_PLL1D2, 0, 0, 0}, | ||
447 | + .offset = 12, | ||
448 | + .len = 2, | ||
449 | + .public_name = "mc-phy-clock", | ||
450 | + }, | ||
451 | + [NPCM7XX_CLOCK_CPUCKSEL] = { | ||
452 | + .name = "cpucksel", | ||
453 | + .input_size = 4, | ||
454 | + .src_type = {CLKSRC_PLL, CLKSRC_DIV, CLKSRC_REF, | ||
455 | + /*SYSBPCK, shouldn't be used in normal operation*/ | ||
456 | + CLKSRC_REF}, | ||
457 | + .src_index = {NPCM7XX_CLOCK_PLL0, NPCM7XX_CLOCK_PLL1D2, 0, 0}, | ||
458 | + .offset = 0, | ||
459 | + .len = 2, | ||
460 | + .public_name = "system-clock", | ||
461 | + }, | ||
462 | + [NPCM7XX_CLOCK_CLKOUTSEL] = { | ||
463 | + .name = "clkoutsel", | ||
464 | + .input_size = 5, | ||
465 | + .src_type = {CLKSRC_PLL, CLKSRC_DIV, CLKSRC_REF, | ||
466 | + CLKSRC_PLL, CLKSRC_DIV}, | ||
467 | + .src_index = {NPCM7XX_CLOCK_PLL0, NPCM7XX_CLOCK_PLL1D2, 0, | ||
468 | + NPCM7XX_CLOCK_PLLG, NPCM7XX_CLOCK_PLL2D2}, | ||
469 | + .offset = 18, | ||
470 | + .len = 3, | ||
471 | + .public_name = "tock", | ||
472 | + }, | ||
473 | + [NPCM7XX_CLOCK_UARTCKSEL] = { | ||
474 | + .name = "uartcksel", | ||
475 | + .input_size = 4, | ||
476 | + .src_type = {CLKSRC_PLL, CLKSRC_DIV, CLKSRC_REF, CLKSRC_DIV}, | ||
477 | + .src_index = {NPCM7XX_CLOCK_PLL0, NPCM7XX_CLOCK_PLL1D2, 0, | ||
478 | + NPCM7XX_CLOCK_PLL2D2}, | ||
479 | + .offset = 8, | ||
480 | + .len = 2, | ||
481 | + }, | ||
482 | + [NPCM7XX_CLOCK_TIMCKSEL] = { | ||
483 | + .name = "timcksel", | ||
484 | + .input_size = 4, | ||
485 | + .src_type = {CLKSRC_PLL, CLKSRC_DIV, CLKSRC_REF, CLKSRC_DIV}, | ||
486 | + .src_index = {NPCM7XX_CLOCK_PLL0, NPCM7XX_CLOCK_PLL1D2, 0, | ||
487 | + NPCM7XX_CLOCK_PLL2D2}, | ||
488 | + .offset = 14, | ||
489 | + .len = 2, | ||
490 | + }, | ||
491 | + [NPCM7XX_CLOCK_SDCKSEL] = { | ||
492 | + .name = "sdcksel", | ||
493 | + .input_size = 4, | ||
494 | + .src_type = {CLKSRC_PLL, CLKSRC_DIV, CLKSRC_REF, CLKSRC_DIV}, | ||
495 | + .src_index = {NPCM7XX_CLOCK_PLL0, NPCM7XX_CLOCK_PLL1D2, 0, | ||
496 | + NPCM7XX_CLOCK_PLL2D2}, | ||
497 | + .offset = 6, | ||
498 | + .len = 2, | ||
499 | + }, | ||
500 | + [NPCM7XX_CLOCK_GFXMSEL] = { | ||
501 | + .name = "gfxmksel", | ||
502 | + .input_size = 2, | ||
503 | + .src_type = {CLKSRC_REF, CLKSRC_PLL}, | ||
504 | + .src_index = {0, NPCM7XX_CLOCK_PLL2}, | ||
505 | + .offset = 21, | ||
506 | + .len = 1, | ||
507 | + }, | ||
508 | + [NPCM7XX_CLOCK_SUCKSEL] = { | ||
509 | + .name = "sucksel", | ||
510 | + .input_size = 4, | ||
511 | + .src_type = {CLKSRC_PLL, CLKSRC_DIV, CLKSRC_REF, CLKSRC_DIV}, | ||
512 | + .src_index = {NPCM7XX_CLOCK_PLL0, NPCM7XX_CLOCK_PLL1D2, 0, | ||
513 | + NPCM7XX_CLOCK_PLL2D2}, | ||
514 | + .offset = 10, | ||
515 | + .len = 2, | ||
516 | + }, | ||
517 | +}; | ||
518 | + | ||
519 | +static const DividerInitInfo divider_init_info_list[] = { | ||
520 | + [NPCM7XX_CLOCK_PLL1D2] = { | ||
521 | + .name = "pll1d2", | ||
522 | + .src_type = CLKSRC_PLL, | ||
523 | + .src_index = NPCM7XX_CLOCK_PLL1, | ||
524 | + .divide = divide_by_constant, | ||
525 | + .divisor = 2, | ||
526 | + }, | ||
527 | + [NPCM7XX_CLOCK_PLL2D2] = { | ||
528 | + .name = "pll2d2", | ||
529 | + .src_type = CLKSRC_PLL, | ||
530 | + .src_index = NPCM7XX_CLOCK_PLL2, | ||
531 | + .divide = divide_by_constant, | ||
532 | + .divisor = 2, | ||
533 | + }, | ||
534 | + [NPCM7XX_CLOCK_MC_DIVIDER] = { | ||
535 | + .name = "mc-divider", | ||
536 | + .src_type = CLKSRC_SEL, | ||
537 | + .src_index = NPCM7XX_CLOCK_MCCKSEL, | ||
538 | + .divide = divide_by_constant, | ||
539 | + .divisor = 2, | ||
540 | + .public_name = "mc-clock" | ||
541 | + }, | ||
542 | + [NPCM7XX_CLOCK_AXI_DIVIDER] = { | ||
543 | + .name = "axi-divider", | ||
544 | + .src_type = CLKSRC_SEL, | ||
545 | + .src_index = NPCM7XX_CLOCK_CPUCKSEL, | ||
546 | + .divide = shift_by_reg_divisor, | ||
547 | + .reg = NPCM7XX_CLK_CLKDIV1, | ||
548 | + .offset = 0, | ||
549 | + .len = 1, | ||
550 | + .public_name = "clk2" | ||
551 | + }, | ||
552 | + [NPCM7XX_CLOCK_AHB_DIVIDER] = { | ||
553 | + .name = "ahb-divider", | ||
554 | + .src_type = CLKSRC_DIV, | ||
555 | + .src_index = NPCM7XX_CLOCK_AXI_DIVIDER, | ||
556 | + .divide = divide_by_reg_divisor, | ||
557 | + .reg = NPCM7XX_CLK_CLKDIV1, | ||
558 | + .offset = 26, | ||
559 | + .len = 2, | ||
560 | + .public_name = "clk4" | ||
561 | + }, | ||
562 | + [NPCM7XX_CLOCK_AHB3_DIVIDER] = { | ||
563 | + .name = "ahb3-divider", | ||
564 | + .src_type = CLKSRC_DIV, | ||
565 | + .src_index = NPCM7XX_CLOCK_AHB_DIVIDER, | ||
566 | + .divide = divide_by_reg_divisor, | ||
567 | + .reg = NPCM7XX_CLK_CLKDIV1, | ||
568 | + .offset = 6, | ||
569 | + .len = 5, | ||
570 | + .public_name = "ahb3-spi3-clock" | ||
571 | + }, | ||
572 | + [NPCM7XX_CLOCK_SPI0_DIVIDER] = { | ||
573 | + .name = "spi0-divider", | ||
574 | + .src_type = CLKSRC_DIV, | ||
575 | + .src_index = NPCM7XX_CLOCK_AHB_DIVIDER, | ||
576 | + .divide = divide_by_reg_divisor, | ||
577 | + .reg = NPCM7XX_CLK_CLKDIV3, | ||
578 | + .offset = 6, | ||
579 | + .len = 5, | ||
580 | + .public_name = "spi0-clock", | ||
581 | + }, | ||
582 | + [NPCM7XX_CLOCK_SPIX_DIVIDER] = { | ||
583 | + .name = "spix-divider", | ||
584 | + .src_type = CLKSRC_DIV, | ||
585 | + .src_index = NPCM7XX_CLOCK_AHB_DIVIDER, | ||
586 | + .divide = divide_by_reg_divisor, | ||
587 | + .reg = NPCM7XX_CLK_CLKDIV3, | ||
588 | + .offset = 1, | ||
589 | + .len = 5, | ||
590 | + .public_name = "spix-clock", | ||
591 | + }, | ||
592 | + [NPCM7XX_CLOCK_APB1_DIVIDER] = { | ||
593 | + .name = "apb1-divider", | ||
594 | + .src_type = CLKSRC_DIV, | ||
595 | + .src_index = NPCM7XX_CLOCK_AHB_DIVIDER, | ||
596 | + .divide = shift_by_reg_divisor, | ||
597 | + .reg = NPCM7XX_CLK_CLKDIV2, | ||
598 | + .offset = 24, | ||
599 | + .len = 2, | ||
600 | + .public_name = "apb1-clock", | ||
601 | + }, | ||
602 | + [NPCM7XX_CLOCK_APB2_DIVIDER] = { | ||
603 | + .name = "apb2-divider", | ||
604 | + .src_type = CLKSRC_DIV, | ||
605 | + .src_index = NPCM7XX_CLOCK_AHB_DIVIDER, | ||
606 | + .divide = shift_by_reg_divisor, | ||
607 | + .reg = NPCM7XX_CLK_CLKDIV2, | ||
608 | + .offset = 26, | ||
609 | + .len = 2, | ||
610 | + .public_name = "apb2-clock", | ||
611 | + }, | ||
612 | + [NPCM7XX_CLOCK_APB3_DIVIDER] = { | ||
613 | + .name = "apb3-divider", | ||
614 | + .src_type = CLKSRC_DIV, | ||
615 | + .src_index = NPCM7XX_CLOCK_AHB_DIVIDER, | ||
616 | + .divide = shift_by_reg_divisor, | ||
617 | + .reg = NPCM7XX_CLK_CLKDIV2, | ||
618 | + .offset = 28, | ||
619 | + .len = 2, | ||
620 | + .public_name = "apb3-clock", | ||
621 | + }, | ||
622 | + [NPCM7XX_CLOCK_APB4_DIVIDER] = { | ||
623 | + .name = "apb4-divider", | ||
624 | + .src_type = CLKSRC_DIV, | ||
625 | + .src_index = NPCM7XX_CLOCK_AHB_DIVIDER, | ||
626 | + .divide = shift_by_reg_divisor, | ||
627 | + .reg = NPCM7XX_CLK_CLKDIV2, | ||
628 | + .offset = 30, | ||
629 | + .len = 2, | ||
630 | + .public_name = "apb4-clock", | ||
631 | + }, | ||
632 | + [NPCM7XX_CLOCK_APB5_DIVIDER] = { | ||
633 | + .name = "apb5-divider", | ||
634 | + .src_type = CLKSRC_DIV, | ||
635 | + .src_index = NPCM7XX_CLOCK_AHB_DIVIDER, | ||
636 | + .divide = shift_by_reg_divisor, | ||
637 | + .reg = NPCM7XX_CLK_CLKDIV2, | ||
638 | + .offset = 22, | ||
639 | + .len = 2, | ||
640 | + .public_name = "apb5-clock", | ||
641 | + }, | ||
642 | + [NPCM7XX_CLOCK_CLKOUT_DIVIDER] = { | ||
643 | + .name = "clkout-divider", | ||
644 | + .src_type = CLKSRC_SEL, | ||
645 | + .src_index = NPCM7XX_CLOCK_CLKOUTSEL, | ||
646 | + .divide = divide_by_reg_divisor, | ||
647 | + .reg = NPCM7XX_CLK_CLKDIV2, | ||
648 | + .offset = 16, | ||
649 | + .len = 5, | ||
650 | + .public_name = "clkout", | ||
651 | + }, | ||
652 | + [NPCM7XX_CLOCK_UART_DIVIDER] = { | ||
653 | + .name = "uart-divider", | ||
654 | + .src_type = CLKSRC_SEL, | ||
655 | + .src_index = NPCM7XX_CLOCK_UARTCKSEL, | ||
656 | + .divide = divide_by_reg_divisor, | ||
657 | + .reg = NPCM7XX_CLK_CLKDIV1, | ||
658 | + .offset = 16, | ||
659 | + .len = 5, | ||
660 | + .public_name = "uart-clock", | ||
661 | + }, | ||
662 | + [NPCM7XX_CLOCK_TIMER_DIVIDER] = { | ||
663 | + .name = "timer-divider", | ||
664 | + .src_type = CLKSRC_SEL, | ||
665 | + .src_index = NPCM7XX_CLOCK_TIMCKSEL, | ||
666 | + .divide = divide_by_reg_divisor, | ||
667 | + .reg = NPCM7XX_CLK_CLKDIV1, | ||
668 | + .offset = 21, | ||
669 | + .len = 5, | ||
670 | + .public_name = "timer-clock", | ||
671 | + }, | ||
672 | + [NPCM7XX_CLOCK_ADC_DIVIDER] = { | ||
673 | + .name = "adc-divider", | ||
674 | + .src_type = CLKSRC_DIV, | ||
675 | + .src_index = NPCM7XX_CLOCK_TIMER_DIVIDER, | ||
676 | + .divide = shift_by_reg_divisor, | ||
677 | + .reg = NPCM7XX_CLK_CLKDIV1, | ||
678 | + .offset = 28, | ||
679 | + .len = 3, | ||
680 | + .public_name = "adc-clock", | ||
681 | + }, | ||
682 | + [NPCM7XX_CLOCK_MMC_DIVIDER] = { | ||
683 | + .name = "mmc-divider", | ||
684 | + .src_type = CLKSRC_SEL, | ||
685 | + .src_index = NPCM7XX_CLOCK_SDCKSEL, | ||
686 | + .divide = divide_by_reg_divisor, | ||
687 | + .reg = NPCM7XX_CLK_CLKDIV1, | ||
688 | + .offset = 11, | ||
689 | + .len = 5, | ||
690 | + .public_name = "mmc-clock", | ||
691 | + }, | ||
692 | + [NPCM7XX_CLOCK_SDHC_DIVIDER] = { | ||
693 | + .name = "sdhc-divider", | ||
694 | + .src_type = CLKSRC_SEL, | ||
695 | + .src_index = NPCM7XX_CLOCK_SDCKSEL, | ||
696 | + .divide = divide_by_reg_divisor_times_2, | ||
697 | + .reg = NPCM7XX_CLK_CLKDIV2, | ||
698 | + .offset = 0, | ||
699 | + .len = 4, | ||
700 | + .public_name = "sdhc-clock", | ||
701 | + }, | ||
702 | + [NPCM7XX_CLOCK_GFXM_DIVIDER] = { | ||
703 | + .name = "gfxm-divider", | ||
704 | + .src_type = CLKSRC_SEL, | ||
705 | + .src_index = NPCM7XX_CLOCK_GFXMSEL, | ||
706 | + .divide = divide_by_constant, | ||
707 | + .divisor = 3, | ||
708 | + .public_name = "gfxm-clock", | ||
709 | + }, | ||
710 | + [NPCM7XX_CLOCK_UTMI_DIVIDER] = { | ||
711 | + .name = "utmi-divider", | ||
712 | + .src_type = CLKSRC_SEL, | ||
713 | + .src_index = NPCM7XX_CLOCK_SUCKSEL, | ||
714 | + .divide = divide_by_reg_divisor, | ||
715 | + .reg = NPCM7XX_CLK_CLKDIV2, | ||
716 | + .offset = 8, | ||
717 | + .len = 5, | ||
718 | + .public_name = "utmi-clock", | ||
719 | + }, | ||
720 | +}; | ||
721 | + | ||
722 | +static void npcm7xx_clk_pll_init(Object *obj) | ||
723 | +{ | ||
724 | + NPCM7xxClockPLLState *pll = NPCM7XX_CLOCK_PLL(obj); | ||
725 | + | ||
726 | + pll->clock_in = qdev_init_clock_in(DEVICE(pll), "clock-in", | ||
727 | + npcm7xx_clk_update_pll, pll); | ||
728 | + pll->clock_out = qdev_init_clock_out(DEVICE(pll), "clock-out"); | ||
729 | +} | ||
730 | + | ||
731 | +static void npcm7xx_clk_sel_init(Object *obj) | ||
732 | +{ | ||
733 | + int i; | ||
734 | + NPCM7xxClockSELState *sel = NPCM7XX_CLOCK_SEL(obj); | ||
735 | + | ||
736 | + for (i = 0; i < NPCM7XX_CLK_SEL_MAX_INPUT; ++i) { | ||
737 | + sel->clock_in[i] = qdev_init_clock_in(DEVICE(sel), | ||
738 | + g_strdup_printf("clock-in[%d]", i), | ||
739 | + npcm7xx_clk_update_sel, sel); | ||
740 | + } | ||
741 | + sel->clock_out = qdev_init_clock_out(DEVICE(sel), "clock-out"); | ||
742 | +} | ||
743 | +static void npcm7xx_clk_divider_init(Object *obj) | ||
744 | +{ | ||
745 | + NPCM7xxClockDividerState *div = NPCM7XX_CLOCK_DIVIDER(obj); | ||
746 | + | ||
747 | + div->clock_in = qdev_init_clock_in(DEVICE(div), "clock-in", | ||
748 | + npcm7xx_clk_update_divider, div); | ||
749 | + div->clock_out = qdev_init_clock_out(DEVICE(div), "clock-out"); | ||
750 | +} | ||
751 | + | ||
752 | +static void npcm7xx_init_clock_pll(NPCM7xxClockPLLState *pll, | ||
753 | + NPCM7xxCLKState *clk, const PLLInitInfo *init_info) | ||
754 | +{ | ||
755 | + pll->name = init_info->name; | ||
756 | + pll->clk = clk; | ||
757 | + pll->reg = init_info->reg; | ||
758 | + if (init_info->public_name != NULL) { | ||
759 | + qdev_alias_clock(DEVICE(pll), "clock-out", DEVICE(clk), | ||
760 | + init_info->public_name); | ||
761 | + } | ||
762 | +} | ||
763 | + | ||
764 | +static void npcm7xx_init_clock_sel(NPCM7xxClockSELState *sel, | ||
765 | + NPCM7xxCLKState *clk, const SELInitInfo *init_info) | ||
766 | +{ | ||
767 | + int input_size = init_info->input_size; | ||
768 | + | ||
769 | + sel->name = init_info->name; | ||
770 | + sel->clk = clk; | ||
771 | + sel->input_size = init_info->input_size; | ||
772 | + g_assert(input_size <= NPCM7XX_CLK_SEL_MAX_INPUT); | ||
773 | + sel->offset = init_info->offset; | ||
774 | + sel->len = init_info->len; | ||
775 | + if (init_info->public_name != NULL) { | ||
776 | + qdev_alias_clock(DEVICE(sel), "clock-out", DEVICE(clk), | ||
777 | + init_info->public_name); | ||
778 | + } | ||
779 | +} | ||
780 | + | ||
781 | +static void npcm7xx_init_clock_divider(NPCM7xxClockDividerState *div, | ||
782 | + NPCM7xxCLKState *clk, const DividerInitInfo *init_info) | ||
783 | +{ | ||
784 | + div->name = init_info->name; | ||
785 | + div->clk = clk; | ||
786 | + | ||
787 | + div->divide = init_info->divide; | ||
788 | + if (div->divide == divide_by_constant) { | ||
789 | + div->divisor = init_info->divisor; | ||
790 | + } else { | ||
791 | + div->reg = init_info->reg; | ||
792 | + div->offset = init_info->offset; | ||
793 | + div->len = init_info->len; | ||
794 | + } | ||
795 | + if (init_info->public_name != NULL) { | ||
796 | + qdev_alias_clock(DEVICE(div), "clock-out", DEVICE(clk), | ||
797 | + init_info->public_name); | ||
798 | + } | ||
799 | +} | ||
800 | + | ||
801 | +static Clock *npcm7xx_get_clock(NPCM7xxCLKState *clk, ClockSrcType type, | ||
802 | + int index) | ||
803 | +{ | ||
804 | + switch (type) { | ||
805 | + case CLKSRC_REF: | ||
806 | + return clk->clkref; | ||
807 | + case CLKSRC_PLL: | ||
808 | + return clk->plls[index].clock_out; | ||
809 | + case CLKSRC_SEL: | ||
810 | + return clk->sels[index].clock_out; | ||
811 | + case CLKSRC_DIV: | ||
812 | + return clk->dividers[index].clock_out; | ||
813 | + default: | ||
814 | + g_assert_not_reached(); | ||
815 | + } | ||
816 | +} | ||
817 | + | ||
818 | +static void npcm7xx_connect_clocks(NPCM7xxCLKState *clk) | ||
819 | +{ | ||
820 | + int i, j; | ||
821 | + Clock *src; | ||
822 | + | ||
823 | + for (i = 0; i < NPCM7XX_CLOCK_NR_PLLS; ++i) { | ||
824 | + src = npcm7xx_get_clock(clk, pll_init_info_list[i].src_type, | ||
825 | + pll_init_info_list[i].src_index); | ||
826 | + clock_set_source(clk->plls[i].clock_in, src); | ||
827 | + } | ||
828 | + for (i = 0; i < NPCM7XX_CLOCK_NR_SELS; ++i) { | ||
829 | + for (j = 0; j < sel_init_info_list[i].input_size; ++j) { | ||
830 | + src = npcm7xx_get_clock(clk, sel_init_info_list[i].src_type[j], | ||
831 | + sel_init_info_list[i].src_index[j]); | ||
832 | + clock_set_source(clk->sels[i].clock_in[j], src); | ||
833 | + } | ||
834 | + } | ||
835 | + for (i = 0; i < NPCM7XX_CLOCK_NR_DIVIDERS; ++i) { | ||
836 | + src = npcm7xx_get_clock(clk, divider_init_info_list[i].src_type, | ||
837 | + divider_init_info_list[i].src_index); | ||
838 | + clock_set_source(clk->dividers[i].clock_in, src); | ||
839 | + } | ||
840 | +} | ||
841 | + | ||
842 | static uint64_t npcm7xx_clk_read(void *opaque, hwaddr offset, unsigned size) | ||
843 | { | 138 | { |
844 | uint32_t reg = offset / sizeof(uint32_t); | 139 | ARMCPU *cpu = env_archcpu(env); |
845 | @@ -XXX,XX +XXX,XX @@ static uint64_t npcm7xx_clk_read(void *opaque, hwaddr offset, unsigned size) | 140 | @@ -XXX,XX +XXX,XX @@ static uint64_t gt_indirect_access_timer_offset(CPUARMState *env, int timeridx) |
846 | * | 141 | case GTIMER_HYP: |
847 | * The 4 LSBs are always zero: (1e9 / 640) << 4 = 25000000. | 142 | case GTIMER_SEC: |
848 | */ | 143 | case GTIMER_HYPVIRT: |
849 | - value = (((now_ns - s->ref_ns) / 640) << 4) % NPCM7XX_TIMER_REF_HZ; | 144 | + case GTIMER_S_EL2_PHYS: |
850 | + value = (((now_ns - s->ref_ns) / 640) << 4) % NPCM7XX_CLOCK_REF_HZ; | 145 | + case GTIMER_S_EL2_VIRT: |
851 | break; | 146 | return 0; |
852 | |||
853 | default: | 147 | default: |
854 | @@ -XXX,XX +XXX,XX @@ static void npcm7xx_clk_write(void *opaque, hwaddr offset, | 148 | g_assert_not_reached(); |
855 | value |= (value & PLLCON_LOKS); | 149 | @@ -XXX,XX +XXX,XX @@ uint64_t gt_direct_access_timer_offset(CPUARMState *env, int timeridx) |
856 | } | 150 | case GTIMER_HYP: |
857 | } | 151 | case GTIMER_SEC: |
858 | + /* Only update PLL when it is locked. */ | 152 | case GTIMER_HYPVIRT: |
859 | + if (value & PLLCON_LOKI) { | 153 | + case GTIMER_S_EL2_PHYS: |
860 | + npcm7xx_clk_update_pll(&s->plls[find_pll_by_reg(reg)]); | 154 | + case GTIMER_S_EL2_VIRT: |
861 | + } | 155 | return 0; |
862 | + break; | 156 | default: |
863 | + | 157 | g_assert_not_reached(); |
864 | + case NPCM7XX_CLK_CLKSEL: | 158 | @@ -XXX,XX +XXX,XX @@ static void gt_sec_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, |
865 | + npcm7xx_clk_update_all_sels(s); | 159 | gt_ctl_write(env, ri, GTIMER_SEC, value); |
866 | + break; | ||
867 | + | ||
868 | + case NPCM7XX_CLK_CLKDIV1: | ||
869 | + case NPCM7XX_CLK_CLKDIV2: | ||
870 | + case NPCM7XX_CLK_CLKDIV3: | ||
871 | + npcm7xx_clk_update_all_dividers(s); | ||
872 | break; | ||
873 | |||
874 | case NPCM7XX_CLK_CNTR25M: | ||
875 | @@ -XXX,XX +XXX,XX @@ static void npcm7xx_clk_enter_reset(Object *obj, ResetType type) | ||
876 | case RESET_TYPE_COLD: | ||
877 | memcpy(s->regs, cold_reset_values, sizeof(cold_reset_values)); | ||
878 | s->ref_ns = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); | ||
879 | + npcm7xx_clk_update_all_clocks(s); | ||
880 | return; | ||
881 | } | ||
882 | |||
883 | @@ -XXX,XX +XXX,XX @@ static void npcm7xx_clk_enter_reset(Object *obj, ResetType type) | ||
884 | __func__, type); | ||
885 | } | 160 | } |
886 | 161 | ||
887 | +static void npcm7xx_clk_init_clock_hierarchy(NPCM7xxCLKState *s) | 162 | +static void gt_sec_pel2_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri) |
888 | +{ | 163 | +{ |
889 | + int i; | 164 | + gt_timer_reset(env, ri, GTIMER_S_EL2_PHYS); |
890 | + | 165 | +} |
891 | + s->clkref = qdev_init_clock_in(DEVICE(s), "clkref", NULL, NULL); | 166 | + |
892 | + | 167 | +static void gt_sec_pel2_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, |
893 | + /* First pass: init all converter modules */ | 168 | + uint64_t value) |
894 | + QEMU_BUILD_BUG_ON(ARRAY_SIZE(pll_init_info_list) != NPCM7XX_CLOCK_NR_PLLS); | 169 | +{ |
895 | + QEMU_BUILD_BUG_ON(ARRAY_SIZE(sel_init_info_list) != NPCM7XX_CLOCK_NR_SELS); | 170 | + gt_cval_write(env, ri, GTIMER_S_EL2_PHYS, value); |
896 | + QEMU_BUILD_BUG_ON(ARRAY_SIZE(divider_init_info_list) | 171 | +} |
897 | + != NPCM7XX_CLOCK_NR_DIVIDERS); | 172 | + |
898 | + for (i = 0; i < NPCM7XX_CLOCK_NR_PLLS; ++i) { | 173 | +static uint64_t gt_sec_pel2_tval_read(CPUARMState *env, const ARMCPRegInfo *ri) |
899 | + object_initialize_child(OBJECT(s), pll_init_info_list[i].name, | 174 | +{ |
900 | + &s->plls[i], TYPE_NPCM7XX_CLOCK_PLL); | 175 | + return gt_tval_read(env, ri, GTIMER_S_EL2_PHYS); |
901 | + npcm7xx_init_clock_pll(&s->plls[i], s, | 176 | +} |
902 | + &pll_init_info_list[i]); | 177 | + |
903 | + } | 178 | +static void gt_sec_pel2_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, |
904 | + for (i = 0; i < NPCM7XX_CLOCK_NR_SELS; ++i) { | 179 | + uint64_t value) |
905 | + object_initialize_child(OBJECT(s), sel_init_info_list[i].name, | 180 | +{ |
906 | + &s->sels[i], TYPE_NPCM7XX_CLOCK_SEL); | 181 | + gt_tval_write(env, ri, GTIMER_S_EL2_PHYS, value); |
907 | + npcm7xx_init_clock_sel(&s->sels[i], s, | 182 | +} |
908 | + &sel_init_info_list[i]); | 183 | + |
909 | + } | 184 | +static void gt_sec_pel2_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, |
910 | + for (i = 0; i < NPCM7XX_CLOCK_NR_DIVIDERS; ++i) { | 185 | + uint64_t value) |
911 | + object_initialize_child(OBJECT(s), divider_init_info_list[i].name, | 186 | +{ |
912 | + &s->dividers[i], TYPE_NPCM7XX_CLOCK_DIVIDER); | 187 | + gt_ctl_write(env, ri, GTIMER_S_EL2_PHYS, value); |
913 | + npcm7xx_init_clock_divider(&s->dividers[i], s, | 188 | +} |
914 | + ÷r_init_info_list[i]); | 189 | + |
915 | + } | 190 | +static void gt_sec_vel2_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri) |
916 | + | 191 | +{ |
917 | + /* Second pass: connect converter modules */ | 192 | + gt_timer_reset(env, ri, GTIMER_S_EL2_VIRT); |
918 | + npcm7xx_connect_clocks(s); | 193 | +} |
919 | + | 194 | + |
920 | + clock_update_hz(s->clkref, NPCM7XX_CLOCK_REF_HZ); | 195 | +static void gt_sec_vel2_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, |
921 | +} | 196 | + uint64_t value) |
922 | + | 197 | +{ |
923 | static void npcm7xx_clk_init(Object *obj) | 198 | + gt_cval_write(env, ri, GTIMER_S_EL2_VIRT, value); |
199 | +} | ||
200 | + | ||
201 | +static uint64_t gt_sec_vel2_tval_read(CPUARMState *env, const ARMCPRegInfo *ri) | ||
202 | +{ | ||
203 | + return gt_tval_read(env, ri, GTIMER_S_EL2_VIRT); | ||
204 | +} | ||
205 | + | ||
206 | +static void gt_sec_vel2_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, | ||
207 | + uint64_t value) | ||
208 | +{ | ||
209 | + gt_tval_write(env, ri, GTIMER_S_EL2_VIRT, value); | ||
210 | +} | ||
211 | + | ||
212 | +static void gt_sec_vel2_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, | ||
213 | + uint64_t value) | ||
214 | +{ | ||
215 | + gt_ctl_write(env, ri, GTIMER_S_EL2_VIRT, value); | ||
216 | +} | ||
217 | + | ||
218 | static void gt_hv_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri) | ||
924 | { | 219 | { |
925 | NPCM7xxCLKState *s = NPCM7XX_CLK(obj); | 220 | gt_timer_reset(env, ri, GTIMER_HYPVIRT); |
926 | @@ -XXX,XX +XXX,XX @@ static void npcm7xx_clk_init(Object *obj) | 221 | @@ -XXX,XX +XXX,XX @@ void arm_gt_stimer_cb(void *opaque) |
927 | memory_region_init_io(&s->iomem, obj, &npcm7xx_clk_ops, s, | 222 | gt_recalc_timer(cpu, GTIMER_SEC); |
928 | TYPE_NPCM7XX_CLK, 4 * KiB); | ||
929 | sysbus_init_mmio(&s->parent, &s->iomem); | ||
930 | - qdev_init_gpio_in_named(DEVICE(s), npcm7xx_clk_perform_watchdog_reset, | ||
931 | - NPCM7XX_WATCHDOG_RESET_GPIO_IN, NPCM7XX_NR_WATCHDOGS); | ||
932 | } | 223 | } |
933 | 224 | ||
934 | -static const VMStateDescription vmstate_npcm7xx_clk = { | 225 | +void arm_gt_sel2timer_cb(void *opaque) |
935 | - .name = "npcm7xx-clk", | 226 | +{ |
936 | +static int npcm7xx_clk_post_load(void *opaque, int version_id) | 227 | + ARMCPU *cpu = opaque; |
937 | +{ | 228 | + |
938 | + if (version_id >= 1) { | 229 | + gt_recalc_timer(cpu, GTIMER_S_EL2_PHYS); |
939 | + NPCM7xxCLKState *clk = opaque; | 230 | +} |
940 | + | 231 | + |
941 | + npcm7xx_clk_update_all_clocks(clk); | 232 | +void arm_gt_sel2vtimer_cb(void *opaque) |
942 | + } | 233 | +{ |
943 | + | 234 | + ARMCPU *cpu = opaque; |
944 | + return 0; | 235 | + |
945 | +} | 236 | + gt_recalc_timer(cpu, GTIMER_S_EL2_VIRT); |
946 | + | 237 | +} |
947 | +static void npcm7xx_clk_realize(DeviceState *dev, Error **errp) | 238 | + |
948 | +{ | 239 | void arm_gt_hvtimer_cb(void *opaque) |
949 | + int i; | 240 | { |
950 | + NPCM7xxCLKState *s = NPCM7XX_CLK(dev); | 241 | ARMCPU *cpu = opaque; |
951 | + | 242 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el2_sec_cp_reginfo[] = { |
952 | + qdev_init_gpio_in_named(DEVICE(s), npcm7xx_clk_perform_watchdog_reset, | 243 | .access = PL2_RW, .accessfn = sel2_access, |
953 | + NPCM7XX_WATCHDOG_RESET_GPIO_IN, NPCM7XX_NR_WATCHDOGS); | 244 | .nv2_redirect_offset = 0x48, |
954 | + npcm7xx_clk_init_clock_hierarchy(s); | 245 | .fieldoffset = offsetof(CPUARMState, cp15.vstcr_el2) }, |
955 | + | 246 | +#ifndef CONFIG_USER_ONLY |
956 | + /* Realize child devices */ | 247 | + /* Secure EL2 Physical Timer */ |
957 | + for (i = 0; i < NPCM7XX_CLOCK_NR_PLLS; ++i) { | 248 | + { .name = "CNTHPS_TVAL_EL2", .state = ARM_CP_STATE_AA64, |
958 | + if (!qdev_realize(DEVICE(&s->plls[i]), NULL, errp)) { | 249 | + .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 5, .opc2 = 0, |
959 | + return; | 250 | + .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL2_RW, |
960 | + } | 251 | + .accessfn = gt_sel2timer_access, |
961 | + } | 252 | + .readfn = gt_sec_pel2_tval_read, |
962 | + for (i = 0; i < NPCM7XX_CLOCK_NR_SELS; ++i) { | 253 | + .writefn = gt_sec_pel2_tval_write, |
963 | + if (!qdev_realize(DEVICE(&s->sels[i]), NULL, errp)) { | 254 | + .resetfn = gt_sec_pel2_timer_reset, |
964 | + return; | 255 | + }, |
965 | + } | 256 | + { .name = "CNTHPS_CTL_EL2", .state = ARM_CP_STATE_AA64, |
966 | + } | 257 | + .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 5, .opc2 = 1, |
967 | + for (i = 0; i < NPCM7XX_CLOCK_NR_DIVIDERS; ++i) { | 258 | + .type = ARM_CP_IO, .access = PL2_RW, |
968 | + if (!qdev_realize(DEVICE(&s->dividers[i]), NULL, errp)) { | 259 | + .accessfn = gt_sel2timer_access, |
969 | + return; | 260 | + .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_S_EL2_PHYS].ctl), |
970 | + } | 261 | + .resetvalue = 0, |
971 | + } | 262 | + .writefn = gt_sec_pel2_ctl_write, .raw_writefn = raw_write, |
972 | +} | 263 | + }, |
973 | + | 264 | + { .name = "CNTHPS_CVAL_EL2", .state = ARM_CP_STATE_AA64, |
974 | +static const VMStateDescription vmstate_npcm7xx_clk_pll = { | 265 | + .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 5, .opc2 = 2, |
975 | + .name = "npcm7xx-clock-pll", | 266 | + .type = ARM_CP_IO, .access = PL2_RW, |
976 | .version_id = 0, | 267 | + .accessfn = gt_sel2timer_access, |
977 | .minimum_version_id = 0, | 268 | + .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_S_EL2_PHYS].cval), |
978 | - .fields = (VMStateField[]) { | 269 | + .writefn = gt_sec_pel2_cval_write, .raw_writefn = raw_write, |
979 | - VMSTATE_UINT32_ARRAY(regs, NPCM7xxCLKState, NPCM7XX_CLK_NR_REGS), | 270 | + }, |
980 | - VMSTATE_INT64(ref_ns, NPCM7xxCLKState), | 271 | + /* Secure EL2 Virtual Timer */ |
981 | + .fields = (VMStateField[]) { | 272 | + { .name = "CNTHVS_TVAL_EL2", .state = ARM_CP_STATE_AA64, |
982 | + VMSTATE_CLOCK(clock_in, NPCM7xxClockPLLState), | 273 | + .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 4, .opc2 = 0, |
983 | VMSTATE_END_OF_LIST(), | 274 | + .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL2_RW, |
984 | }, | 275 | + .accessfn = gt_sel2timer_access, |
276 | + .readfn = gt_sec_vel2_tval_read, | ||
277 | + .writefn = gt_sec_vel2_tval_write, | ||
278 | + .resetfn = gt_sec_vel2_timer_reset, | ||
279 | + }, | ||
280 | + { .name = "CNTHVS_CTL_EL2", .state = ARM_CP_STATE_AA64, | ||
281 | + .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 4, .opc2 = 1, | ||
282 | + .type = ARM_CP_IO, .access = PL2_RW, | ||
283 | + .accessfn = gt_sel2timer_access, | ||
284 | + .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_S_EL2_VIRT].ctl), | ||
285 | + .resetvalue = 0, | ||
286 | + .writefn = gt_sec_vel2_ctl_write, .raw_writefn = raw_write, | ||
287 | + }, | ||
288 | + { .name = "CNTHVS_CVAL_EL2", .state = ARM_CP_STATE_AA64, | ||
289 | + .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 4, .opc2 = 2, | ||
290 | + .type = ARM_CP_IO, .access = PL2_RW, | ||
291 | + .accessfn = gt_sel2timer_access, | ||
292 | + .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_S_EL2_VIRT].cval), | ||
293 | + .writefn = gt_sec_vel2_cval_write, .raw_writefn = raw_write, | ||
294 | + }, | ||
295 | +#endif | ||
985 | }; | 296 | }; |
986 | 297 | ||
987 | +static const VMStateDescription vmstate_npcm7xx_clk_sel = { | 298 | static CPAccessResult nsacr_access(CPUARMState *env, const ARMCPRegInfo *ri, |
988 | + .name = "npcm7xx-clock-sel", | ||
989 | + .version_id = 0, | ||
990 | + .minimum_version_id = 0, | ||
991 | + .fields = (VMStateField[]) { | ||
992 | + VMSTATE_ARRAY_OF_POINTER_TO_STRUCT(clock_in, NPCM7xxClockSELState, | ||
993 | + NPCM7XX_CLK_SEL_MAX_INPUT, 0, vmstate_clock, Clock), | ||
994 | + VMSTATE_END_OF_LIST(), | ||
995 | + }, | ||
996 | +}; | ||
997 | + | ||
998 | +static const VMStateDescription vmstate_npcm7xx_clk_divider = { | ||
999 | + .name = "npcm7xx-clock-divider", | ||
1000 | + .version_id = 0, | ||
1001 | + .minimum_version_id = 0, | ||
1002 | + .fields = (VMStateField[]) { | ||
1003 | + VMSTATE_CLOCK(clock_in, NPCM7xxClockDividerState), | ||
1004 | + VMSTATE_END_OF_LIST(), | ||
1005 | + }, | ||
1006 | +}; | ||
1007 | + | ||
1008 | +static const VMStateDescription vmstate_npcm7xx_clk = { | ||
1009 | + .name = "npcm7xx-clk", | ||
1010 | + .version_id = 1, | ||
1011 | + .minimum_version_id = 1, | ||
1012 | + .post_load = npcm7xx_clk_post_load, | ||
1013 | + .fields = (VMStateField[]) { | ||
1014 | + VMSTATE_UINT32_ARRAY(regs, NPCM7xxCLKState, NPCM7XX_CLK_NR_REGS), | ||
1015 | + VMSTATE_INT64(ref_ns, NPCM7xxCLKState), | ||
1016 | + VMSTATE_CLOCK(clkref, NPCM7xxCLKState), | ||
1017 | + VMSTATE_END_OF_LIST(), | ||
1018 | + }, | ||
1019 | +}; | ||
1020 | + | ||
1021 | +static void npcm7xx_clk_pll_class_init(ObjectClass *klass, void *data) | ||
1022 | +{ | ||
1023 | + DeviceClass *dc = DEVICE_CLASS(klass); | ||
1024 | + | ||
1025 | + dc->desc = "NPCM7xx Clock PLL Module"; | ||
1026 | + dc->vmsd = &vmstate_npcm7xx_clk_pll; | ||
1027 | +} | ||
1028 | + | ||
1029 | +static void npcm7xx_clk_sel_class_init(ObjectClass *klass, void *data) | ||
1030 | +{ | ||
1031 | + DeviceClass *dc = DEVICE_CLASS(klass); | ||
1032 | + | ||
1033 | + dc->desc = "NPCM7xx Clock SEL Module"; | ||
1034 | + dc->vmsd = &vmstate_npcm7xx_clk_sel; | ||
1035 | +} | ||
1036 | + | ||
1037 | +static void npcm7xx_clk_divider_class_init(ObjectClass *klass, void *data) | ||
1038 | +{ | ||
1039 | + DeviceClass *dc = DEVICE_CLASS(klass); | ||
1040 | + | ||
1041 | + dc->desc = "NPCM7xx Clock Divider Module"; | ||
1042 | + dc->vmsd = &vmstate_npcm7xx_clk_divider; | ||
1043 | +} | ||
1044 | + | ||
1045 | static void npcm7xx_clk_class_init(ObjectClass *klass, void *data) | ||
1046 | { | ||
1047 | ResettableClass *rc = RESETTABLE_CLASS(klass); | ||
1048 | @@ -XXX,XX +XXX,XX @@ static void npcm7xx_clk_class_init(ObjectClass *klass, void *data) | ||
1049 | |||
1050 | dc->desc = "NPCM7xx Clock Control Registers"; | ||
1051 | dc->vmsd = &vmstate_npcm7xx_clk; | ||
1052 | + dc->realize = npcm7xx_clk_realize; | ||
1053 | rc->phases.enter = npcm7xx_clk_enter_reset; | ||
1054 | } | ||
1055 | |||
1056 | +static const TypeInfo npcm7xx_clk_pll_info = { | ||
1057 | + .name = TYPE_NPCM7XX_CLOCK_PLL, | ||
1058 | + .parent = TYPE_DEVICE, | ||
1059 | + .instance_size = sizeof(NPCM7xxClockPLLState), | ||
1060 | + .instance_init = npcm7xx_clk_pll_init, | ||
1061 | + .class_init = npcm7xx_clk_pll_class_init, | ||
1062 | +}; | ||
1063 | + | ||
1064 | +static const TypeInfo npcm7xx_clk_sel_info = { | ||
1065 | + .name = TYPE_NPCM7XX_CLOCK_SEL, | ||
1066 | + .parent = TYPE_DEVICE, | ||
1067 | + .instance_size = sizeof(NPCM7xxClockSELState), | ||
1068 | + .instance_init = npcm7xx_clk_sel_init, | ||
1069 | + .class_init = npcm7xx_clk_sel_class_init, | ||
1070 | +}; | ||
1071 | + | ||
1072 | +static const TypeInfo npcm7xx_clk_divider_info = { | ||
1073 | + .name = TYPE_NPCM7XX_CLOCK_DIVIDER, | ||
1074 | + .parent = TYPE_DEVICE, | ||
1075 | + .instance_size = sizeof(NPCM7xxClockDividerState), | ||
1076 | + .instance_init = npcm7xx_clk_divider_init, | ||
1077 | + .class_init = npcm7xx_clk_divider_class_init, | ||
1078 | +}; | ||
1079 | + | ||
1080 | static const TypeInfo npcm7xx_clk_info = { | ||
1081 | .name = TYPE_NPCM7XX_CLK, | ||
1082 | .parent = TYPE_SYS_BUS_DEVICE, | ||
1083 | @@ -XXX,XX +XXX,XX @@ static const TypeInfo npcm7xx_clk_info = { | ||
1084 | |||
1085 | static void npcm7xx_clk_register_type(void) | ||
1086 | { | ||
1087 | + type_register_static(&npcm7xx_clk_pll_info); | ||
1088 | + type_register_static(&npcm7xx_clk_sel_info); | ||
1089 | + type_register_static(&npcm7xx_clk_divider_info); | ||
1090 | type_register_static(&npcm7xx_clk_info); | ||
1091 | } | ||
1092 | type_init(npcm7xx_clk_register_type); | ||
1093 | -- | 299 | -- |
1094 | 2.20.1 | 300 | 2.43.0 |
1095 | 301 | ||
1096 | 302 | diff view generated by jsdifflib |
1 | From: Leif Lindholm <leif@nuviainc.com> | 1 | From: Alex Bennée <alex.bennee@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Signed-off-by: Leif Lindholm <leif@nuviainc.com> | 3 | As we are about to add more physical and virtual timers let's make it |
4 | Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com> | 4 | clear what each timer does. |
5 | Message-id: 20210108185154.8108-5-leif@nuviainc.com | 5 | |
6 | Signed-off-by: Alex Bennée <alex.bennee@linaro.org> | ||
7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
9 | Message-id: 20250204125009.2281315-8-peter.maydell@linaro.org | ||
10 | [PMM: Add timer register name prefix to each comment] | ||
11 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | --- | 13 | --- |
8 | target/arm/cpu.h | 31 +++++++++++++++++++++++++++++++ | 14 | target/arm/gtimer.h | 10 +++++----- |
9 | 1 file changed, 31 insertions(+) | 15 | 1 file changed, 5 insertions(+), 5 deletions(-) |
10 | 16 | ||
11 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | 17 | diff --git a/target/arm/gtimer.h b/target/arm/gtimer.h |
12 | index XXXXXXX..XXXXXXX 100644 | 18 | index XXXXXXX..XXXXXXX 100644 |
13 | --- a/target/arm/cpu.h | 19 | --- a/target/arm/gtimer.h |
14 | +++ b/target/arm/cpu.h | 20 | +++ b/target/arm/gtimer.h |
15 | @@ -XXX,XX +XXX,XX @@ FIELD(V7M_FPCCR, ASPEN, 31, 1) | 21 | @@ -XXX,XX +XXX,XX @@ |
16 | /* | 22 | #define TARGET_ARM_GTIMER_H |
17 | * System register ID fields. | 23 | |
18 | */ | 24 | enum { |
19 | +FIELD(CLIDR_EL1, CTYPE1, 0, 3) | 25 | - GTIMER_PHYS = 0, |
20 | +FIELD(CLIDR_EL1, CTYPE2, 3, 3) | 26 | - GTIMER_VIRT = 1, |
21 | +FIELD(CLIDR_EL1, CTYPE3, 6, 3) | 27 | - GTIMER_HYP = 2, |
22 | +FIELD(CLIDR_EL1, CTYPE4, 9, 3) | 28 | - GTIMER_SEC = 3, |
23 | +FIELD(CLIDR_EL1, CTYPE5, 12, 3) | 29 | - GTIMER_HYPVIRT = 4, |
24 | +FIELD(CLIDR_EL1, CTYPE6, 15, 3) | 30 | + GTIMER_PHYS = 0, /* CNTP_* ; EL1 physical timer */ |
25 | +FIELD(CLIDR_EL1, CTYPE7, 18, 3) | 31 | + GTIMER_VIRT = 1, /* CNTV_* ; EL1 virtual timer */ |
26 | +FIELD(CLIDR_EL1, LOUIS, 21, 3) | 32 | + GTIMER_HYP = 2, /* CNTHP_* ; EL2 physical timer */ |
27 | +FIELD(CLIDR_EL1, LOC, 24, 3) | 33 | + GTIMER_SEC = 3, /* CNTPS_* ; EL3 physical timer */ |
28 | +FIELD(CLIDR_EL1, LOUU, 27, 3) | 34 | + GTIMER_HYPVIRT = 4, /* CNTHV_* ; EL2 virtual timer ; only if FEAT_VHE */ |
29 | +FIELD(CLIDR_EL1, ICB, 30, 3) | 35 | GTIMER_S_EL2_PHYS = 5, /* CNTHPS_* ; only if FEAT_SEL2 */ |
30 | + | 36 | GTIMER_S_EL2_VIRT = 6, /* CNTHVS_* ; only if FEAT_SEL2 */ |
31 | +/* When FEAT_CCIDX is implemented */ | 37 | #define NUM_GTIMERS 7 |
32 | +FIELD(CCSIDR_EL1, CCIDX_LINESIZE, 0, 3) | ||
33 | +FIELD(CCSIDR_EL1, CCIDX_ASSOCIATIVITY, 3, 21) | ||
34 | +FIELD(CCSIDR_EL1, CCIDX_NUMSETS, 32, 24) | ||
35 | + | ||
36 | +/* When FEAT_CCIDX is not implemented */ | ||
37 | +FIELD(CCSIDR_EL1, LINESIZE, 0, 3) | ||
38 | +FIELD(CCSIDR_EL1, ASSOCIATIVITY, 3, 10) | ||
39 | +FIELD(CCSIDR_EL1, NUMSETS, 13, 15) | ||
40 | + | ||
41 | +FIELD(CTR_EL0, IMINLINE, 0, 4) | ||
42 | +FIELD(CTR_EL0, L1IP, 14, 2) | ||
43 | +FIELD(CTR_EL0, DMINLINE, 16, 4) | ||
44 | +FIELD(CTR_EL0, ERG, 20, 4) | ||
45 | +FIELD(CTR_EL0, CWG, 24, 4) | ||
46 | +FIELD(CTR_EL0, IDC, 28, 1) | ||
47 | +FIELD(CTR_EL0, DIC, 29, 1) | ||
48 | +FIELD(CTR_EL0, TMINLINE, 32, 6) | ||
49 | + | ||
50 | FIELD(MIDR_EL1, REVISION, 0, 4) | ||
51 | FIELD(MIDR_EL1, PARTNUM, 4, 12) | ||
52 | FIELD(MIDR_EL1, ARCHITECTURE, 16, 4) | ||
53 | -- | 38 | -- |
54 | 2.20.1 | 39 | 2.43.0 |
55 | 40 | ||
56 | 41 | diff view generated by jsdifflib |
1 | From: Leif Lindholm <leif@nuviainc.com> | 1 | From: Alex Bennée <alex.bennee@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | When FEAT_MTE is implemented, the AArch64 view of CTR_EL0 adds the | 3 | Signed-off-by: Alex Bennée <alex.bennee@linaro.org> |
4 | TminLine field in bits [37:32]. | 4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
5 | Extend the ctr field to be able to hold this context. | 5 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
6 | 6 | Message-id: 20250204125009.2281315-9-peter.maydell@linaro.org | |
7 | Signed-off-by: Leif Lindholm <leif@nuviainc.com> | 7 | Cc: qemu-stable@nongnu.org |
8 | Reviewed-by: Hao Wu <wuhaotsh@google.com> | 8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
9 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
10 | Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com> | ||
11 | Message-id: 20210108185154.8108-4-leif@nuviainc.com | ||
12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
13 | --- | 10 | --- |
14 | target/arm/cpu.h | 2 +- | 11 | hw/arm/virt.c | 2 ++ |
15 | 1 file changed, 1 insertion(+), 1 deletion(-) | 12 | 1 file changed, 2 insertions(+) |
16 | 13 | ||
17 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | 14 | diff --git a/hw/arm/virt.c b/hw/arm/virt.c |
18 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
19 | --- a/target/arm/cpu.h | 16 | --- a/hw/arm/virt.c |
20 | +++ b/target/arm/cpu.h | 17 | +++ b/hw/arm/virt.c |
21 | @@ -XXX,XX +XXX,XX @@ struct ARMCPU { | 18 | @@ -XXX,XX +XXX,XX @@ static void create_gic(VirtMachineState *vms, MemoryRegion *mem) |
22 | uint64_t midr; | 19 | [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ, |
23 | uint32_t revidr; | 20 | [GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ, |
24 | uint32_t reset_fpsid; | 21 | [GTIMER_HYPVIRT] = ARCH_TIMER_NS_EL2_VIRT_IRQ, |
25 | - uint32_t ctr; | 22 | + [GTIMER_S_EL2_PHYS] = ARCH_TIMER_S_EL2_IRQ, |
26 | + uint64_t ctr; | 23 | + [GTIMER_S_EL2_VIRT] = ARCH_TIMER_S_EL2_VIRT_IRQ, |
27 | uint32_t reset_sctlr; | 24 | }; |
28 | uint64_t pmceid0; | 25 | |
29 | uint64_t pmceid1; | 26 | for (unsigned irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) { |
30 | -- | 27 | -- |
31 | 2.20.1 | 28 | 2.43.0 |
32 | 29 | ||
33 | 30 | diff view generated by jsdifflib |
1 | From: Leif Lindholm <leif@nuviainc.com> | 1 | From: Alex Bennée <alex.bennee@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | The AArch64 view of CLIDR_EL1 extends the ICB field to include also bit | 3 | Signed-off-by: Alex Bennée <alex.bennee@linaro.org> |
4 | 32, as well as adding a Ttype<n> field when FEAT_MTE is implemented. | ||
5 | Extend the clidr field to be able to hold this context. | ||
6 | |||
7 | Signed-off-by: Leif Lindholm <leif@nuviainc.com> | ||
8 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
9 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 4 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
10 | Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com> | 5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
11 | Message-id: 20210108185154.8108-3-leif@nuviainc.com | 6 | Message-id: 20250204125009.2281315-10-peter.maydell@linaro.org |
7 | Cc: qemu-stable@nongnu.org | ||
12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
13 | --- | 9 | --- |
14 | target/arm/cpu.h | 2 +- | 10 | hw/arm/sbsa-ref.c | 2 ++ |
15 | 1 file changed, 1 insertion(+), 1 deletion(-) | 11 | 1 file changed, 2 insertions(+) |
16 | 12 | ||
17 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | 13 | diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c |
18 | index XXXXXXX..XXXXXXX 100644 | 14 | index XXXXXXX..XXXXXXX 100644 |
19 | --- a/target/arm/cpu.h | 15 | --- a/hw/arm/sbsa-ref.c |
20 | +++ b/target/arm/cpu.h | 16 | +++ b/hw/arm/sbsa-ref.c |
21 | @@ -XXX,XX +XXX,XX @@ struct ARMCPU { | 17 | @@ -XXX,XX +XXX,XX @@ static void create_gic(SBSAMachineState *sms, MemoryRegion *mem) |
22 | uint32_t id_afr0; | 18 | [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ, |
23 | uint64_t id_aa64afr0; | 19 | [GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ, |
24 | uint64_t id_aa64afr1; | 20 | [GTIMER_HYPVIRT] = ARCH_TIMER_NS_EL2_VIRT_IRQ, |
25 | - uint32_t clidr; | 21 | + [GTIMER_S_EL2_PHYS] = ARCH_TIMER_S_EL2_IRQ, |
26 | + uint64_t clidr; | 22 | + [GTIMER_S_EL2_VIRT] = ARCH_TIMER_S_EL2_VIRT_IRQ, |
27 | uint64_t mp_affinity; /* MP ID without feature bits */ | 23 | }; |
28 | /* The elements of this array are the CCSIDR values for each cache, | 24 | |
29 | * in the order L1DCache, L1ICache, L2DCache, L2ICache, etc. | 25 | for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) { |
30 | -- | 26 | -- |
31 | 2.20.1 | 27 | 2.43.0 |
32 | 28 | ||
33 | 29 | diff view generated by jsdifflib |
1 | A copy-and-paste error meant that the return value for register offset 0x44 | 1 | Our LDRD implementation is wrong in two respects: |
---|---|---|---|
2 | (the RX Status FIFO PEEK register) returned a byte from a bogus offset in | 2 | |
3 | the rx status FIFO. Fix the typo. | 3 | * if the address is 4-aligned and the load crosses a page boundary |
4 | and the second load faults and the first load was to the | ||
5 | base register (as in cases like "ldrd r2, r3, [r2]", then we | ||
6 | must not update the base register before taking the fault | ||
7 | * if the address is 8-aligned the access must be a 64-bit | ||
8 | single-copy atomic access, not two 32-bit accesses | ||
9 | |||
10 | Rewrite the handling of the loads in LDRD to use a single | ||
11 | tcg_gen_qemu_ld_i64() and split the result into the destination | ||
12 | registers. This allows us to get the atomicity requirements | ||
13 | right, and also implicitly means that we won't update the | ||
14 | base register too early for the page-crossing case. | ||
15 | |||
16 | Note that because we no longer increment 'addr' by 4 in the course of | ||
17 | performing the LDRD we must change the adjustment value we pass to | ||
18 | op_addr_ri_post() and op_addr_rr_post(): it no longer needs to | ||
19 | subtract 4 to get the correct value to use if doing base register | ||
20 | writeback. | ||
21 | |||
22 | STRD has the same problem with not getting the atomicity right; | ||
23 | we will deal with that in the following commit. | ||
4 | 24 | ||
5 | Cc: qemu-stable@nongnu.org | 25 | Cc: qemu-stable@nongnu.org |
6 | Fixes: https://bugs.launchpad.net/qemu/+bug/1904954 | 26 | Reported-by: Stu Grossman <stu.grossman@gmail.com> |
7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 27 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
8 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 28 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
9 | Message-id: 20210108180401.2263-2-peter.maydell@linaro.org | 29 | Message-id: 20250227142746.1698904-2-peter.maydell@linaro.org |
10 | --- | 30 | --- |
11 | hw/net/lan9118.c | 2 +- | 31 | target/arm/tcg/translate.c | 70 +++++++++++++++++++++++++------------- |
12 | 1 file changed, 1 insertion(+), 1 deletion(-) | 32 | 1 file changed, 46 insertions(+), 24 deletions(-) |
13 | 33 | ||
14 | diff --git a/hw/net/lan9118.c b/hw/net/lan9118.c | 34 | diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c |
15 | index XXXXXXX..XXXXXXX 100644 | 35 | index XXXXXXX..XXXXXXX 100644 |
16 | --- a/hw/net/lan9118.c | 36 | --- a/target/arm/tcg/translate.c |
17 | +++ b/hw/net/lan9118.c | 37 | +++ b/target/arm/tcg/translate.c |
18 | @@ -XXX,XX +XXX,XX @@ static uint64_t lan9118_readl(void *opaque, hwaddr offset, | 38 | @@ -XXX,XX +XXX,XX @@ static bool op_store_rr(DisasContext *s, arg_ldst_rr *a, |
19 | case 0x40: | 39 | return true; |
20 | return rx_status_fifo_pop(s); | 40 | } |
21 | case 0x44: | 41 | |
22 | - return s->rx_status_fifo[s->tx_status_fifo_head]; | 42 | +static void do_ldrd_load(DisasContext *s, TCGv_i32 addr, int rt, int rt2) |
23 | + return s->rx_status_fifo[s->rx_status_fifo_head]; | 43 | +{ |
24 | case 0x48: | 44 | + /* |
25 | return tx_status_fifo_pop(s); | 45 | + * LDRD is required to be an atomic 64-bit access if the |
26 | case 0x4c: | 46 | + * address is 8-aligned, two atomic 32-bit accesses if |
47 | + * it's only 4-aligned, and to give an alignment fault | ||
48 | + * if it's not 4-aligned. This is MO_ALIGN_4 | MO_ATOM_SUBALIGN. | ||
49 | + * Rt is always the word from the lower address, and Rt2 the | ||
50 | + * data from the higher address, regardless of endianness. | ||
51 | + * So (like gen_load_exclusive) we avoid gen_aa32_ld_i64() | ||
52 | + * so we don't get its SCTLR_B check, and instead do a 64-bit access | ||
53 | + * using MO_BE if appropriate and then split the two halves. | ||
54 | + * | ||
55 | + * For M-profile, and for A-profile before LPAE, the 64-bit | ||
56 | + * atomicity is not required. We could model that using | ||
57 | + * the looser MO_ATOM_IFALIGN_PAIR, but providing a higher | ||
58 | + * level of atomicity than required is harmless (we would not | ||
59 | + * currently generate better code for IFALIGN_PAIR here). | ||
60 | + * | ||
61 | + * This also gives us the correct behaviour of not updating | ||
62 | + * rt if the load of rt2 faults; this is required for cases | ||
63 | + * like "ldrd r2, r3, [r2]" where rt is also the base register. | ||
64 | + */ | ||
65 | + int mem_idx = get_mem_index(s); | ||
66 | + MemOp opc = MO_64 | MO_ALIGN_4 | MO_ATOM_SUBALIGN | s->be_data; | ||
67 | + TCGv taddr = gen_aa32_addr(s, addr, opc); | ||
68 | + TCGv_i64 t64 = tcg_temp_new_i64(); | ||
69 | + TCGv_i32 tmp = tcg_temp_new_i32(); | ||
70 | + TCGv_i32 tmp2 = tcg_temp_new_i32(); | ||
71 | + | ||
72 | + tcg_gen_qemu_ld_i64(t64, taddr, mem_idx, opc); | ||
73 | + if (s->be_data == MO_BE) { | ||
74 | + tcg_gen_extr_i64_i32(tmp2, tmp, t64); | ||
75 | + } else { | ||
76 | + tcg_gen_extr_i64_i32(tmp, tmp2, t64); | ||
77 | + } | ||
78 | + store_reg(s, rt, tmp); | ||
79 | + store_reg(s, rt2, tmp2); | ||
80 | +} | ||
81 | + | ||
82 | static bool trans_LDRD_rr(DisasContext *s, arg_ldst_rr *a) | ||
83 | { | ||
84 | - int mem_idx = get_mem_index(s); | ||
85 | - TCGv_i32 addr, tmp; | ||
86 | + TCGv_i32 addr; | ||
87 | |||
88 | if (!ENABLE_ARCH_5TE) { | ||
89 | return false; | ||
90 | @@ -XXX,XX +XXX,XX @@ static bool trans_LDRD_rr(DisasContext *s, arg_ldst_rr *a) | ||
91 | } | ||
92 | addr = op_addr_rr_pre(s, a); | ||
93 | |||
94 | - tmp = tcg_temp_new_i32(); | ||
95 | - gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN); | ||
96 | - store_reg(s, a->rt, tmp); | ||
97 | - | ||
98 | - tcg_gen_addi_i32(addr, addr, 4); | ||
99 | - | ||
100 | - tmp = tcg_temp_new_i32(); | ||
101 | - gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN); | ||
102 | - store_reg(s, a->rt + 1, tmp); | ||
103 | + do_ldrd_load(s, addr, a->rt, a->rt + 1); | ||
104 | |||
105 | /* LDRD w/ base writeback is undefined if the registers overlap. */ | ||
106 | - op_addr_rr_post(s, a, addr, -4); | ||
107 | + op_addr_rr_post(s, a, addr, 0); | ||
108 | return true; | ||
109 | } | ||
110 | |||
111 | @@ -XXX,XX +XXX,XX @@ static bool op_store_ri(DisasContext *s, arg_ldst_ri *a, | ||
112 | |||
113 | static bool op_ldrd_ri(DisasContext *s, arg_ldst_ri *a, int rt2) | ||
114 | { | ||
115 | - int mem_idx = get_mem_index(s); | ||
116 | - TCGv_i32 addr, tmp; | ||
117 | + TCGv_i32 addr; | ||
118 | |||
119 | addr = op_addr_ri_pre(s, a); | ||
120 | |||
121 | - tmp = tcg_temp_new_i32(); | ||
122 | - gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN); | ||
123 | - store_reg(s, a->rt, tmp); | ||
124 | - | ||
125 | - tcg_gen_addi_i32(addr, addr, 4); | ||
126 | - | ||
127 | - tmp = tcg_temp_new_i32(); | ||
128 | - gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN); | ||
129 | - store_reg(s, rt2, tmp); | ||
130 | + do_ldrd_load(s, addr, a->rt, rt2); | ||
131 | |||
132 | /* LDRD w/ base writeback is undefined if the registers overlap. */ | ||
133 | - op_addr_ri_post(s, a, addr, -4); | ||
134 | + op_addr_ri_post(s, a, addr, 0); | ||
135 | return true; | ||
136 | } | ||
137 | |||
27 | -- | 138 | -- |
28 | 2.20.1 | 139 | 2.43.0 |
29 | |||
30 | diff view generated by jsdifflib |
1 | From: Leif Lindholm <leif@nuviainc.com> | 1 | Our STRD implementation doesn't correctly implement the requirement: |
---|---|---|---|
2 | * if the address is 8-aligned the access must be a 64-bit | ||
3 | single-copy atomic access, not two 32-bit accesses | ||
2 | 4 | ||
3 | SBSS -> SSBS | 5 | Rewrite the handling of STRD to use a single tcg_gen_qemu_st_i64() |
6 | of a value produced by concatenating the two 32 bit source registers. | ||
7 | This allows us to get the atomicity right. | ||
4 | 8 | ||
5 | Signed-off-by: Leif Lindholm <leif@nuviainc.com> | 9 | As with the LDRD change, now that we don't update 'addr' in the |
6 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 10 | course of performing the store we need to adjust the offset |
7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 11 | we pass to op_addr_ri_post() and op_addr_rr_post(). |
8 | Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com> | 12 | |
9 | Message-id: 20210108185154.8108-2-leif@nuviainc.com | 13 | Cc: qemu-stable@nongnu.org |
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 14 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
15 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
16 | Message-id: 20250227142746.1698904-3-peter.maydell@linaro.org | ||
11 | --- | 17 | --- |
12 | target/arm/cpu.h | 2 +- | 18 | target/arm/tcg/translate.c | 59 +++++++++++++++++++++++++------------- |
13 | 1 file changed, 1 insertion(+), 1 deletion(-) | 19 | 1 file changed, 39 insertions(+), 20 deletions(-) |
14 | 20 | ||
15 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | 21 | diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c |
16 | index XXXXXXX..XXXXXXX 100644 | 22 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/target/arm/cpu.h | 23 | --- a/target/arm/tcg/translate.c |
18 | +++ b/target/arm/cpu.h | 24 | +++ b/target/arm/tcg/translate.c |
19 | @@ -XXX,XX +XXX,XX @@ FIELD(ID_AA64PFR0, RAS, 28, 4) | 25 | @@ -XXX,XX +XXX,XX @@ static bool trans_LDRD_rr(DisasContext *s, arg_ldst_rr *a) |
20 | FIELD(ID_AA64PFR0, SVE, 32, 4) | 26 | return true; |
21 | 27 | } | |
22 | FIELD(ID_AA64PFR1, BT, 0, 4) | 28 | |
23 | -FIELD(ID_AA64PFR1, SBSS, 4, 4) | 29 | +static void do_strd_store(DisasContext *s, TCGv_i32 addr, int rt, int rt2) |
24 | +FIELD(ID_AA64PFR1, SSBS, 4, 4) | 30 | +{ |
25 | FIELD(ID_AA64PFR1, MTE, 8, 4) | 31 | + /* |
26 | FIELD(ID_AA64PFR1, RAS_FRAC, 12, 4) | 32 | + * STRD is required to be an atomic 64-bit access if the |
33 | + * address is 8-aligned, two atomic 32-bit accesses if | ||
34 | + * it's only 4-aligned, and to give an alignment fault | ||
35 | + * if it's not 4-aligned. | ||
36 | + * Rt is always the word from the lower address, and Rt2 the | ||
37 | + * data from the higher address, regardless of endianness. | ||
38 | + * So (like gen_store_exclusive) we avoid gen_aa32_ld_i64() | ||
39 | + * so we don't get its SCTLR_B check, and instead do a 64-bit access | ||
40 | + * using MO_BE if appropriate, using a value constructed | ||
41 | + * by putting the two halves together in the right order. | ||
42 | + * | ||
43 | + * As with LDRD, the 64-bit atomicity is not required for | ||
44 | + * M-profile, or for A-profile before LPAE, and we provide | ||
45 | + * the higher guarantee always for simplicity. | ||
46 | + */ | ||
47 | + int mem_idx = get_mem_index(s); | ||
48 | + MemOp opc = MO_64 | MO_ALIGN_4 | MO_ATOM_SUBALIGN | s->be_data; | ||
49 | + TCGv taddr = gen_aa32_addr(s, addr, opc); | ||
50 | + TCGv_i32 t1 = load_reg(s, rt); | ||
51 | + TCGv_i32 t2 = load_reg(s, rt2); | ||
52 | + TCGv_i64 t64 = tcg_temp_new_i64(); | ||
53 | + | ||
54 | + if (s->be_data == MO_BE) { | ||
55 | + tcg_gen_concat_i32_i64(t64, t2, t1); | ||
56 | + } else { | ||
57 | + tcg_gen_concat_i32_i64(t64, t1, t2); | ||
58 | + } | ||
59 | + tcg_gen_qemu_st_i64(t64, taddr, mem_idx, opc); | ||
60 | +} | ||
61 | + | ||
62 | static bool trans_STRD_rr(DisasContext *s, arg_ldst_rr *a) | ||
63 | { | ||
64 | - int mem_idx = get_mem_index(s); | ||
65 | - TCGv_i32 addr, tmp; | ||
66 | + TCGv_i32 addr; | ||
67 | |||
68 | if (!ENABLE_ARCH_5TE) { | ||
69 | return false; | ||
70 | @@ -XXX,XX +XXX,XX @@ static bool trans_STRD_rr(DisasContext *s, arg_ldst_rr *a) | ||
71 | } | ||
72 | addr = op_addr_rr_pre(s, a); | ||
73 | |||
74 | - tmp = load_reg(s, a->rt); | ||
75 | - gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN); | ||
76 | + do_strd_store(s, addr, a->rt, a->rt + 1); | ||
77 | |||
78 | - tcg_gen_addi_i32(addr, addr, 4); | ||
79 | - | ||
80 | - tmp = load_reg(s, a->rt + 1); | ||
81 | - gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN); | ||
82 | - | ||
83 | - op_addr_rr_post(s, a, addr, -4); | ||
84 | + op_addr_rr_post(s, a, addr, 0); | ||
85 | return true; | ||
86 | } | ||
87 | |||
88 | @@ -XXX,XX +XXX,XX @@ static bool trans_LDRD_ri_t32(DisasContext *s, arg_ldst_ri2 *a) | ||
89 | |||
90 | static bool op_strd_ri(DisasContext *s, arg_ldst_ri *a, int rt2) | ||
91 | { | ||
92 | - int mem_idx = get_mem_index(s); | ||
93 | - TCGv_i32 addr, tmp; | ||
94 | + TCGv_i32 addr; | ||
95 | |||
96 | addr = op_addr_ri_pre(s, a); | ||
97 | |||
98 | - tmp = load_reg(s, a->rt); | ||
99 | - gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN); | ||
100 | + do_strd_store(s, addr, a->rt, rt2); | ||
101 | |||
102 | - tcg_gen_addi_i32(addr, addr, 4); | ||
103 | - | ||
104 | - tmp = load_reg(s, rt2); | ||
105 | - gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN); | ||
106 | - | ||
107 | - op_addr_ri_post(s, a, addr, -4); | ||
108 | + op_addr_ri_post(s, a, addr, 0); | ||
109 | return true; | ||
110 | } | ||
27 | 111 | ||
28 | -- | 112 | -- |
29 | 2.20.1 | 113 | 2.43.0 |
30 | |||
31 | diff view generated by jsdifflib |
1 | From: Hao Wu <wuhaotsh@google.com> | 1 | All the callers of op_addr_rr_post() and op_addr_ri_post() now pass in |
---|---|---|---|
2 | zero for the address_offset, so we can remove that argument. | ||
2 | 3 | ||
3 | This patch makes NPCM7XX Timer to use a the timer clock generated by the | 4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
4 | CLK module instead of the magic number TIMER_REF_HZ. | 5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
6 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
7 | Message-id: 20250227142746.1698904-4-peter.maydell@linaro.org | ||
8 | --- | ||
9 | target/arm/tcg/translate.c | 26 +++++++++++++------------- | ||
10 | 1 file changed, 13 insertions(+), 13 deletions(-) | ||
5 | 11 | ||
6 | Reviewed-by: Havard Skinnemoen <hskinnemoen@google.com> | 12 | diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c |
7 | Reviewed-by: Tyrone Ting <kfting@nuvoton.com> | ||
8 | Signed-off-by: Hao Wu <wuhaotsh@google.com> | ||
9 | Message-id: 20210108190945.949196-3-wuhaotsh@google.com | ||
10 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
12 | --- | ||
13 | include/hw/misc/npcm7xx_clk.h | 6 ----- | ||
14 | include/hw/timer/npcm7xx_timer.h | 1 + | ||
15 | hw/arm/npcm7xx.c | 5 ++++ | ||
16 | hw/timer/npcm7xx_timer.c | 39 +++++++++++++++----------------- | ||
17 | 4 files changed, 24 insertions(+), 27 deletions(-) | ||
18 | |||
19 | diff --git a/include/hw/misc/npcm7xx_clk.h b/include/hw/misc/npcm7xx_clk.h | ||
20 | index XXXXXXX..XXXXXXX 100644 | 13 | index XXXXXXX..XXXXXXX 100644 |
21 | --- a/include/hw/misc/npcm7xx_clk.h | 14 | --- a/target/arm/tcg/translate.c |
22 | +++ b/include/hw/misc/npcm7xx_clk.h | 15 | +++ b/target/arm/tcg/translate.c |
23 | @@ -XXX,XX +XXX,XX @@ | 16 | @@ -XXX,XX +XXX,XX @@ static TCGv_i32 op_addr_rr_pre(DisasContext *s, arg_ldst_rr *a) |
24 | #include "hw/clock.h" | 17 | } |
25 | #include "hw/sysbus.h" | 18 | |
26 | 19 | static void op_addr_rr_post(DisasContext *s, arg_ldst_rr *a, | |
27 | -/* | 20 | - TCGv_i32 addr, int address_offset) |
28 | - * The reference clock frequency for the timer modules, and the SECCNT and | 21 | + TCGv_i32 addr) |
29 | - * CNTR25M registers in this module, is always 25 MHz. | ||
30 | - */ | ||
31 | -#define NPCM7XX_TIMER_REF_HZ (25000000) | ||
32 | - | ||
33 | /* | ||
34 | * Number of registers in our device state structure. Don't change this without | ||
35 | * incrementing the version_id in the vmstate. | ||
36 | diff --git a/include/hw/timer/npcm7xx_timer.h b/include/hw/timer/npcm7xx_timer.h | ||
37 | index XXXXXXX..XXXXXXX 100644 | ||
38 | --- a/include/hw/timer/npcm7xx_timer.h | ||
39 | +++ b/include/hw/timer/npcm7xx_timer.h | ||
40 | @@ -XXX,XX +XXX,XX @@ struct NPCM7xxTimerCtrlState { | ||
41 | |||
42 | uint32_t tisr; | ||
43 | |||
44 | + Clock *clock; | ||
45 | NPCM7xxTimer timer[NPCM7XX_TIMERS_PER_CTRL]; | ||
46 | NPCM7xxWatchdogTimer watchdog_timer; | ||
47 | }; | ||
48 | diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c | ||
49 | index XXXXXXX..XXXXXXX 100644 | ||
50 | --- a/hw/arm/npcm7xx.c | ||
51 | +++ b/hw/arm/npcm7xx.c | ||
52 | @@ -XXX,XX +XXX,XX @@ | ||
53 | #include "hw/char/serial.h" | ||
54 | #include "hw/loader.h" | ||
55 | #include "hw/misc/unimp.h" | ||
56 | +#include "hw/qdev-clock.h" | ||
57 | #include "hw/qdev-properties.h" | ||
58 | #include "qapi/error.h" | ||
59 | #include "qemu/units.h" | ||
60 | @@ -XXX,XX +XXX,XX @@ static void npcm7xx_realize(DeviceState *dev, Error **errp) | ||
61 | int first_irq; | ||
62 | int j; | ||
63 | |||
64 | + /* Connect the timer clock. */ | ||
65 | + qdev_connect_clock_in(DEVICE(&s->tim[i]), "clock", qdev_get_clock_out( | ||
66 | + DEVICE(&s->clk), "timer-clock")); | ||
67 | + | ||
68 | sysbus_realize(sbd, &error_abort); | ||
69 | sysbus_mmio_map(sbd, 0, npcm7xx_tim_addr[i]); | ||
70 | |||
71 | diff --git a/hw/timer/npcm7xx_timer.c b/hw/timer/npcm7xx_timer.c | ||
72 | index XXXXXXX..XXXXXXX 100644 | ||
73 | --- a/hw/timer/npcm7xx_timer.c | ||
74 | +++ b/hw/timer/npcm7xx_timer.c | ||
75 | @@ -XXX,XX +XXX,XX @@ | ||
76 | #include "qemu/osdep.h" | ||
77 | |||
78 | #include "hw/irq.h" | ||
79 | +#include "hw/qdev-clock.h" | ||
80 | #include "hw/qdev-properties.h" | ||
81 | -#include "hw/misc/npcm7xx_clk.h" | ||
82 | #include "hw/timer/npcm7xx_timer.h" | ||
83 | #include "migration/vmstate.h" | ||
84 | #include "qemu/bitops.h" | ||
85 | @@ -XXX,XX +XXX,XX @@ static uint32_t npcm7xx_tcsr_prescaler(uint32_t tcsr) | ||
86 | /* Convert a timer cycle count to a time interval in nanoseconds. */ | ||
87 | static int64_t npcm7xx_timer_count_to_ns(NPCM7xxTimer *t, uint32_t count) | ||
88 | { | 22 | { |
89 | - int64_t ns = count; | 23 | if (!a->p) { |
90 | + int64_t ticks = count; | 24 | TCGv_i32 ofs = load_reg(s, a->rm); |
91 | 25 | @@ -XXX,XX +XXX,XX @@ static void op_addr_rr_post(DisasContext *s, arg_ldst_rr *a, | |
92 | - ns *= NANOSECONDS_PER_SECOND / NPCM7XX_TIMER_REF_HZ; | 26 | } else if (!a->w) { |
93 | - ns *= npcm7xx_tcsr_prescaler(t->tcsr); | 27 | return; |
94 | + ticks *= npcm7xx_tcsr_prescaler(t->tcsr); | 28 | } |
95 | 29 | - tcg_gen_addi_i32(addr, addr, address_offset); | |
96 | - return ns; | 30 | store_reg(s, a->rn, addr); |
97 | + return clock_ticks_to_ns(t->ctrl->clock, ticks); | ||
98 | } | 31 | } |
99 | 32 | ||
100 | /* Convert a time interval in nanoseconds to a timer cycle count. */ | 33 | @@ -XXX,XX +XXX,XX @@ static bool op_load_rr(DisasContext *s, arg_ldst_rr *a, |
101 | static uint32_t npcm7xx_timer_ns_to_count(NPCM7xxTimer *t, int64_t ns) | 34 | * Perform base writeback before the loaded value to |
35 | * ensure correct behavior with overlapping index registers. | ||
36 | */ | ||
37 | - op_addr_rr_post(s, a, addr, 0); | ||
38 | + op_addr_rr_post(s, a, addr); | ||
39 | store_reg_from_load(s, a->rt, tmp); | ||
40 | return true; | ||
41 | } | ||
42 | @@ -XXX,XX +XXX,XX @@ static bool op_store_rr(DisasContext *s, arg_ldst_rr *a, | ||
43 | gen_aa32_st_i32(s, tmp, addr, mem_idx, mop); | ||
44 | disas_set_da_iss(s, mop, issinfo); | ||
45 | |||
46 | - op_addr_rr_post(s, a, addr, 0); | ||
47 | + op_addr_rr_post(s, a, addr); | ||
48 | return true; | ||
49 | } | ||
50 | |||
51 | @@ -XXX,XX +XXX,XX @@ static bool trans_LDRD_rr(DisasContext *s, arg_ldst_rr *a) | ||
52 | do_ldrd_load(s, addr, a->rt, a->rt + 1); | ||
53 | |||
54 | /* LDRD w/ base writeback is undefined if the registers overlap. */ | ||
55 | - op_addr_rr_post(s, a, addr, 0); | ||
56 | + op_addr_rr_post(s, a, addr); | ||
57 | return true; | ||
58 | } | ||
59 | |||
60 | @@ -XXX,XX +XXX,XX @@ static bool trans_STRD_rr(DisasContext *s, arg_ldst_rr *a) | ||
61 | |||
62 | do_strd_store(s, addr, a->rt, a->rt + 1); | ||
63 | |||
64 | - op_addr_rr_post(s, a, addr, 0); | ||
65 | + op_addr_rr_post(s, a, addr); | ||
66 | return true; | ||
67 | } | ||
68 | |||
69 | @@ -XXX,XX +XXX,XX @@ static TCGv_i32 op_addr_ri_pre(DisasContext *s, arg_ldst_ri *a) | ||
70 | } | ||
71 | |||
72 | static void op_addr_ri_post(DisasContext *s, arg_ldst_ri *a, | ||
73 | - TCGv_i32 addr, int address_offset) | ||
74 | + TCGv_i32 addr) | ||
102 | { | 75 | { |
103 | - int64_t count; | 76 | + int address_offset = 0; |
104 | - | 77 | if (!a->p) { |
105 | - count = ns / (NANOSECONDS_PER_SECOND / NPCM7XX_TIMER_REF_HZ); | 78 | if (a->u) { |
106 | - count /= npcm7xx_tcsr_prescaler(t->tcsr); | 79 | - address_offset += a->imm; |
107 | - | 80 | + address_offset = a->imm; |
108 | - return count; | 81 | } else { |
109 | + return ns / clock_ticks_to_ns(t->ctrl->clock, | 82 | - address_offset -= a->imm; |
110 | + npcm7xx_tcsr_prescaler(t->tcsr)); | 83 | + address_offset = -a->imm; |
84 | } | ||
85 | } else if (!a->w) { | ||
86 | return; | ||
87 | @@ -XXX,XX +XXX,XX @@ static bool op_load_ri(DisasContext *s, arg_ldst_ri *a, | ||
88 | * Perform base writeback before the loaded value to | ||
89 | * ensure correct behavior with overlapping index registers. | ||
90 | */ | ||
91 | - op_addr_ri_post(s, a, addr, 0); | ||
92 | + op_addr_ri_post(s, a, addr); | ||
93 | store_reg_from_load(s, a->rt, tmp); | ||
94 | return true; | ||
111 | } | 95 | } |
112 | 96 | @@ -XXX,XX +XXX,XX @@ static bool op_store_ri(DisasContext *s, arg_ldst_ri *a, | |
113 | static uint32_t npcm7xx_watchdog_timer_prescaler(const NPCM7xxWatchdogTimer *t) | 97 | gen_aa32_st_i32(s, tmp, addr, mem_idx, mop); |
114 | @@ -XXX,XX +XXX,XX @@ static uint32_t npcm7xx_watchdog_timer_prescaler(const NPCM7xxWatchdogTimer *t) | 98 | disas_set_da_iss(s, mop, issinfo); |
115 | static void npcm7xx_watchdog_timer_reset_cycles(NPCM7xxWatchdogTimer *t, | 99 | |
116 | int64_t cycles) | 100 | - op_addr_ri_post(s, a, addr, 0); |
117 | { | 101 | + op_addr_ri_post(s, a, addr); |
118 | - uint32_t prescaler = npcm7xx_watchdog_timer_prescaler(t); | 102 | return true; |
119 | - int64_t ns = (NANOSECONDS_PER_SECOND / NPCM7XX_TIMER_REF_HZ) * cycles; | ||
120 | + int64_t ticks = cycles * npcm7xx_watchdog_timer_prescaler(t); | ||
121 | + int64_t ns = clock_ticks_to_ns(t->ctrl->clock, ticks); | ||
122 | |||
123 | /* | ||
124 | * The reset function always clears the current timer. The caller of the | ||
125 | @@ -XXX,XX +XXX,XX @@ static void npcm7xx_watchdog_timer_reset_cycles(NPCM7xxWatchdogTimer *t, | ||
126 | */ | ||
127 | npcm7xx_timer_clear(&t->base_timer); | ||
128 | |||
129 | - ns *= prescaler; | ||
130 | t->base_timer.remaining_ns = ns; | ||
131 | } | 103 | } |
132 | 104 | ||
133 | @@ -XXX,XX +XXX,XX @@ static void npcm7xx_timer_hold_reset(Object *obj) | 105 | @@ -XXX,XX +XXX,XX @@ static bool op_ldrd_ri(DisasContext *s, arg_ldst_ri *a, int rt2) |
134 | qemu_irq_lower(s->watchdog_timer.irq); | 106 | do_ldrd_load(s, addr, a->rt, rt2); |
107 | |||
108 | /* LDRD w/ base writeback is undefined if the registers overlap. */ | ||
109 | - op_addr_ri_post(s, a, addr, 0); | ||
110 | + op_addr_ri_post(s, a, addr); | ||
111 | return true; | ||
135 | } | 112 | } |
136 | 113 | ||
137 | -static void npcm7xx_timer_realize(DeviceState *dev, Error **errp) | 114 | @@ -XXX,XX +XXX,XX @@ static bool op_strd_ri(DisasContext *s, arg_ldst_ri *a, int rt2) |
138 | +static void npcm7xx_timer_init(Object *obj) | 115 | |
139 | { | 116 | do_strd_store(s, addr, a->rt, rt2); |
140 | - NPCM7xxTimerCtrlState *s = NPCM7XX_TIMER(dev); | 117 | |
141 | - SysBusDevice *sbd = &s->parent; | 118 | - op_addr_ri_post(s, a, addr, 0); |
142 | + NPCM7xxTimerCtrlState *s = NPCM7XX_TIMER(obj); | 119 | + op_addr_ri_post(s, a, addr); |
143 | + DeviceState *dev = DEVICE(obj); | 120 | return true; |
144 | + SysBusDevice *sbd = SYS_BUS_DEVICE(obj); | ||
145 | int i; | ||
146 | NPCM7xxWatchdogTimer *w; | ||
147 | |||
148 | @@ -XXX,XX +XXX,XX @@ static void npcm7xx_timer_realize(DeviceState *dev, Error **errp) | ||
149 | npcm7xx_watchdog_timer_expired, w); | ||
150 | sysbus_init_irq(sbd, &w->irq); | ||
151 | |||
152 | - memory_region_init_io(&s->iomem, OBJECT(s), &npcm7xx_timer_ops, s, | ||
153 | + memory_region_init_io(&s->iomem, obj, &npcm7xx_timer_ops, s, | ||
154 | TYPE_NPCM7XX_TIMER, 4 * KiB); | ||
155 | sysbus_init_mmio(sbd, &s->iomem); | ||
156 | qdev_init_gpio_out_named(dev, &w->reset_signal, | ||
157 | NPCM7XX_WATCHDOG_RESET_GPIO_OUT, 1); | ||
158 | + s->clock = qdev_init_clock_in(dev, "clock", NULL, NULL); | ||
159 | } | 121 | } |
160 | 122 | ||
161 | static const VMStateDescription vmstate_npcm7xx_base_timer = { | ||
162 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_npcm7xx_watchdog_timer = { | ||
163 | |||
164 | static const VMStateDescription vmstate_npcm7xx_timer_ctrl = { | ||
165 | .name = "npcm7xx-timer-ctrl", | ||
166 | - .version_id = 1, | ||
167 | - .minimum_version_id = 1, | ||
168 | + .version_id = 2, | ||
169 | + .minimum_version_id = 2, | ||
170 | .fields = (VMStateField[]) { | ||
171 | VMSTATE_UINT32(tisr, NPCM7xxTimerCtrlState), | ||
172 | + VMSTATE_CLOCK(clock, NPCM7xxTimerCtrlState), | ||
173 | VMSTATE_STRUCT_ARRAY(timer, NPCM7xxTimerCtrlState, | ||
174 | NPCM7XX_TIMERS_PER_CTRL, 0, vmstate_npcm7xx_timer, | ||
175 | NPCM7xxTimer), | ||
176 | @@ -XXX,XX +XXX,XX @@ static void npcm7xx_timer_class_init(ObjectClass *klass, void *data) | ||
177 | QEMU_BUILD_BUG_ON(NPCM7XX_TIMER_REGS_END > NPCM7XX_TIMER_NR_REGS); | ||
178 | |||
179 | dc->desc = "NPCM7xx Timer Controller"; | ||
180 | - dc->realize = npcm7xx_timer_realize; | ||
181 | dc->vmsd = &vmstate_npcm7xx_timer_ctrl; | ||
182 | rc->phases.enter = npcm7xx_timer_enter_reset; | ||
183 | rc->phases.hold = npcm7xx_timer_hold_reset; | ||
184 | @@ -XXX,XX +XXX,XX @@ static const TypeInfo npcm7xx_timer_info = { | ||
185 | .parent = TYPE_SYS_BUS_DEVICE, | ||
186 | .instance_size = sizeof(NPCM7xxTimerCtrlState), | ||
187 | .class_init = npcm7xx_timer_class_init, | ||
188 | + .instance_init = npcm7xx_timer_init, | ||
189 | }; | ||
190 | |||
191 | static void npcm7xx_timer_register_type(void) | ||
192 | -- | 123 | -- |
193 | 2.20.1 | 124 | 2.43.0 |
194 | 125 | ||
195 | 126 | diff view generated by jsdifflib |
1 | When we first converted our documentation to Sphinx, we split it into | 1 | In debug_helper.c we provide a few dummy versions of |
---|---|---|---|
2 | multiple manuals (system, interop, tools, etc), which are all built | 2 | debug registers: |
3 | separately. The primary driver for this was wanting to be able to | 3 | * DBGVCR (AArch32 only): enable bits for vector-catch |
4 | avoid shipping the 'devel' manual to end-users. However, this is | 4 | debug events |
5 | working against the grain of the way Sphinx wants to be used and | 5 | * MDCCINT_EL1: interrupt enable bits for the DCC |
6 | causes some annoyances: | 6 | debug communications channel |
7 | * Cross-references between documents become much harder or | 7 | * DBGVCR32_EL2: the AArch64 accessor for the state in |
8 | possibly impossible | 8 | DBGVCR |
9 | * There is no single index to the whole documentation | ||
10 | * Within one manual there's no links or table-of-contents info | ||
11 | that lets you easily navigate to the others | ||
12 | * The devel manual doesn't get published on the QEMU website | ||
13 | (it would be nice to able to refer to it there) | ||
14 | 9 | ||
15 | Merely hiding our developer documentation from end users seems like | 10 | We implemented these only to stop Linux crashing on startup, |
16 | it's not enough benefit for these costs. Combine all the | 11 | but we chose to implement them as ARM_CP_NOP. This worked |
17 | documentation into a single manual (the same way that the readthedocs | 12 | for Linux where it only cares about trying to write to these |
18 | site builds it) and install the whole thing. The previous manual | 13 | registers, but is very confusing behaviour for anything that |
19 | divisions remain as the new top level sections in the manual. | 14 | wants to read the registers (perhaps for context state switches), |
15 | because the destination register will be left with whatever | ||
16 | random value it happened to have before the read. | ||
20 | 17 | ||
21 | * The per-manual conf.py files are no longer needed | 18 | Model these registers instead as RAZ. |
22 | * The man_pages[] specifications previously in each per-manual | ||
23 | conf.py move to the top level conf.py | ||
24 | * docs/meson.build logic is simplified as we now only need to run | ||
25 | Sphinx once for the HTML and then once for the manpages5B | ||
26 | * The old index.html.in that produced the top-level page with | ||
27 | links to each manual is no longer needed | ||
28 | 19 | ||
29 | Unfortunately this means that we now have to build the HTML | 20 | Fixes: 5e8b12ffbb8c68 ("target-arm: Implement minimal DBGVCR, OSDLR_EL1, MDCCSR_EL0") |
30 | documentation into docs/manual in the build tree rather than directly | 21 | Fixes: 5dbdc4342f479d ("target-arm: Implement dummy MDCCINT_EL1") |
31 | into docs/; otherwise it is too awkward to ensure we install only the | 22 | Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2708 |
32 | built manual and not also the dependency info, stamp file, etc. The | 23 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
33 | manual still ends up in the same place in the final installed | 24 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
34 | directory, but anybody who was consulting documentation from within | 25 | Message-id: 20250228162424.1917269-1-peter.maydell@linaro.org |
35 | the build tree will have to adjust where they're looking. | 26 | --- |
27 | target/arm/debug_helper.c | 7 ++++--- | ||
28 | 1 file changed, 4 insertions(+), 3 deletions(-) | ||
36 | 29 | ||
37 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 30 | diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c |
38 | Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> | ||
39 | Message-id: 20210108161416.21129-3-peter.maydell@linaro.org | ||
40 | --- | ||
41 | docs/conf.py | 46 ++++++++++++++++++++++++++++++- | ||
42 | docs/devel/conf.py | 15 ----------- | ||
43 | docs/index.html.in | 17 ------------ | ||
44 | docs/interop/conf.py | 28 ------------------- | ||
45 | docs/meson.build | 64 +++++++++++++++++--------------------------- | ||
46 | docs/specs/conf.py | 16 ----------- | ||
47 | docs/system/conf.py | 28 ------------------- | ||
48 | docs/tools/conf.py | 37 ------------------------- | ||
49 | docs/user/conf.py | 15 ----------- | ||
50 | 9 files changed, 70 insertions(+), 196 deletions(-) | ||
51 | delete mode 100644 docs/devel/conf.py | ||
52 | delete mode 100644 docs/index.html.in | ||
53 | delete mode 100644 docs/interop/conf.py | ||
54 | delete mode 100644 docs/specs/conf.py | ||
55 | delete mode 100644 docs/system/conf.py | ||
56 | delete mode 100644 docs/tools/conf.py | ||
57 | delete mode 100644 docs/user/conf.py | ||
58 | |||
59 | diff --git a/docs/conf.py b/docs/conf.py | ||
60 | index XXXXXXX..XXXXXXX 100644 | 31 | index XXXXXXX..XXXXXXX 100644 |
61 | --- a/docs/conf.py | 32 | --- a/target/arm/debug_helper.c |
62 | +++ b/docs/conf.py | 33 | +++ b/target/arm/debug_helper.c |
63 | @@ -XXX,XX +XXX,XX @@ latex_documents = [ | 34 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo debug_cp_reginfo[] = { |
64 | 35 | { .name = "DBGVCR", | |
65 | # -- Options for manual page output --------------------------------------- | 36 | .cp = 14, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0, |
66 | # Individual manual/conf.py can override this to create man pages | 37 | .access = PL1_RW, .accessfn = access_tda, |
67 | -man_pages = [] | 38 | - .type = ARM_CP_NOP }, |
68 | +man_pages = [ | 39 | + .type = ARM_CP_CONST, .resetvalue = 0 }, |
69 | + ('interop/qemu-ga', 'qemu-ga', | 40 | /* |
70 | + 'QEMU Guest Agent', | 41 | * Dummy MDCCINT_EL1, since we don't implement the Debug Communications |
71 | + ['Michael Roth <mdroth@linux.vnet.ibm.com>'], 8), | 42 | * Channel but Linux may try to access this register. The 32-bit |
72 | + ('interop/qemu-ga-ref', 'qemu-ga-ref', | 43 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo debug_cp_reginfo[] = { |
73 | + 'QEMU Guest Agent Protocol Reference', | 44 | { .name = "MDCCINT_EL1", .state = ARM_CP_STATE_BOTH, |
74 | + [], 7), | 45 | .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0, |
75 | + ('interop/qemu-qmp-ref', 'qemu-qmp-ref', | 46 | .access = PL1_RW, .accessfn = access_tdcc, |
76 | + 'QEMU QMP Reference Manual', | 47 | - .type = ARM_CP_NOP }, |
77 | + [], 7), | 48 | + .type = ARM_CP_CONST, .resetvalue = 0 }, |
78 | + ('interop/qemu-storage-daemon-qmp-ref', 'qemu-storage-daemon-qmp-ref', | 49 | /* |
79 | + 'QEMU Storage Daemon QMP Reference Manual', | 50 | * Dummy DBGCLAIM registers. |
80 | + [], 7), | 51 | * "The architecture does not define any functionality for the CLAIM tag bits.", |
81 | + ('system/qemu-manpage', 'qemu', | 52 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo debug_aa32_el1_reginfo[] = { |
82 | + 'QEMU User Documentation', | 53 | { .name = "DBGVCR32_EL2", .state = ARM_CP_STATE_AA64, |
83 | + ['Fabrice Bellard'], 1), | 54 | .opc0 = 2, .opc1 = 4, .crn = 0, .crm = 7, .opc2 = 0, |
84 | + ('system/qemu-block-drivers', 'qemu-block-drivers', | 55 | .access = PL2_RW, .accessfn = access_dbgvcr32, |
85 | + 'QEMU block drivers reference', | 56 | - .type = ARM_CP_NOP | ARM_CP_EL3_NO_EL2_KEEP }, |
86 | + ['Fabrice Bellard and the QEMU Project developers'], 7), | 57 | + .type = ARM_CP_CONST | ARM_CP_EL3_NO_EL2_KEEP, |
87 | + ('system/qemu-cpu-models', 'qemu-cpu-models', | 58 | + .resetvalue = 0 }, |
88 | + 'QEMU CPU Models', | 59 | }; |
89 | + ['The QEMU Project developers'], 7), | 60 | |
90 | + ('tools/qemu-img', 'qemu-img', | 61 | static const ARMCPRegInfo debug_lpae_cp_reginfo[] = { |
91 | + 'QEMU disk image utility', | ||
92 | + ['Fabrice Bellard'], 1), | ||
93 | + ('tools/qemu-nbd', 'qemu-nbd', | ||
94 | + 'QEMU Disk Network Block Device Server', | ||
95 | + ['Anthony Liguori <anthony@codemonkey.ws>'], 8), | ||
96 | + ('tools/qemu-pr-helper', 'qemu-pr-helper', | ||
97 | + 'QEMU persistent reservation helper', | ||
98 | + [], 8), | ||
99 | + ('tools/qemu-storage-daemon', 'qemu-storage-daemon', | ||
100 | + 'QEMU storage daemon', | ||
101 | + [], 1), | ||
102 | + ('tools/qemu-trace-stap', 'qemu-trace-stap', | ||
103 | + 'QEMU SystemTap trace tool', | ||
104 | + [], 1), | ||
105 | + ('tools/virtfs-proxy-helper', 'virtfs-proxy-helper', | ||
106 | + 'QEMU 9p virtfs proxy filesystem helper', | ||
107 | + ['M. Mohan Kumar'], 1), | ||
108 | + ('tools/virtiofsd', 'virtiofsd', | ||
109 | + 'QEMU virtio-fs shared file system daemon', | ||
110 | + ['Stefan Hajnoczi <stefanha@redhat.com>', | ||
111 | + 'Masayoshi Mizuma <m.mizuma@jp.fujitsu.com>'], 1), | ||
112 | +] | ||
113 | |||
114 | # -- Options for Texinfo output ------------------------------------------- | ||
115 | |||
116 | diff --git a/docs/devel/conf.py b/docs/devel/conf.py | ||
117 | deleted file mode 100644 | ||
118 | index XXXXXXX..XXXXXXX | ||
119 | --- a/docs/devel/conf.py | ||
120 | +++ /dev/null | ||
121 | @@ -XXX,XX +XXX,XX @@ | ||
122 | -# -*- coding: utf-8 -*- | ||
123 | -# | ||
124 | -# QEMU documentation build configuration file for the 'devel' manual. | ||
125 | -# | ||
126 | -# This includes the top level conf file and then makes any necessary tweaks. | ||
127 | -import sys | ||
128 | -import os | ||
129 | - | ||
130 | -qemu_docdir = os.path.abspath("..") | ||
131 | -parent_config = os.path.join(qemu_docdir, "conf.py") | ||
132 | -exec(compile(open(parent_config, "rb").read(), parent_config, 'exec')) | ||
133 | - | ||
134 | -# This slightly misuses the 'description', but is the best way to get | ||
135 | -# the manual title to appear in the sidebar. | ||
136 | -html_theme_options['description'] = u'Developer''s Guide' | ||
137 | diff --git a/docs/index.html.in b/docs/index.html.in | ||
138 | deleted file mode 100644 | ||
139 | index XXXXXXX..XXXXXXX | ||
140 | --- a/docs/index.html.in | ||
141 | +++ /dev/null | ||
142 | @@ -XXX,XX +XXX,XX @@ | ||
143 | -<!DOCTYPE html> | ||
144 | -<html lang="en"> | ||
145 | - <head> | ||
146 | - <meta charset="UTF-8"> | ||
147 | - <title>QEMU @VERSION@ Documentation</title> | ||
148 | - </head> | ||
149 | - <body> | ||
150 | - <h1>QEMU @VERSION@ Documentation</h1> | ||
151 | - <ul> | ||
152 | - <li><a href="system/index.html">System Emulation User's Guide</a></li> | ||
153 | - <li><a href="user/index.html">User Mode Emulation User's Guide</a></li> | ||
154 | - <li><a href="tools/index.html">Tools Guide</a></li> | ||
155 | - <li><a href="interop/index.html">System Emulation Management and Interoperability Guide</a></li> | ||
156 | - <li><a href="specs/index.html">System Emulation Guest Hardware Specifications</a></li> | ||
157 | - </ul> | ||
158 | - </body> | ||
159 | -</html> | ||
160 | diff --git a/docs/interop/conf.py b/docs/interop/conf.py | ||
161 | deleted file mode 100644 | ||
162 | index XXXXXXX..XXXXXXX | ||
163 | --- a/docs/interop/conf.py | ||
164 | +++ /dev/null | ||
165 | @@ -XXX,XX +XXX,XX @@ | ||
166 | -# -*- coding: utf-8 -*- | ||
167 | -# | ||
168 | -# QEMU documentation build configuration file for the 'interop' manual. | ||
169 | -# | ||
170 | -# This includes the top level conf file and then makes any necessary tweaks. | ||
171 | -import sys | ||
172 | -import os | ||
173 | - | ||
174 | -qemu_docdir = os.path.abspath("..") | ||
175 | -parent_config = os.path.join(qemu_docdir, "conf.py") | ||
176 | -exec(compile(open(parent_config, "rb").read(), parent_config, 'exec')) | ||
177 | - | ||
178 | -# This slightly misuses the 'description', but is the best way to get | ||
179 | -# the manual title to appear in the sidebar. | ||
180 | -html_theme_options['description'] = u'System Emulation Management and Interoperability Guide' | ||
181 | - | ||
182 | -# One entry per manual page. List of tuples | ||
183 | -# (source start file, name, description, authors, manual section). | ||
184 | -man_pages = [ | ||
185 | - ('qemu-ga', 'qemu-ga', u'QEMU Guest Agent', | ||
186 | - ['Michael Roth <mdroth@linux.vnet.ibm.com>'], 8), | ||
187 | - ('qemu-ga-ref', 'qemu-ga-ref', 'QEMU Guest Agent Protocol Reference', | ||
188 | - [], 7), | ||
189 | - ('qemu-qmp-ref', 'qemu-qmp-ref', 'QEMU QMP Reference Manual', | ||
190 | - [], 7), | ||
191 | - ('qemu-storage-daemon-qmp-ref', 'qemu-storage-daemon-qmp-ref', | ||
192 | - 'QEMU Storage Daemon QMP Reference Manual', [], 7), | ||
193 | -] | ||
194 | diff --git a/docs/meson.build b/docs/meson.build | ||
195 | index XXXXXXX..XXXXXXX 100644 | ||
196 | --- a/docs/meson.build | ||
197 | +++ b/docs/meson.build | ||
198 | @@ -XXX,XX +XXX,XX @@ if build_docs | ||
199 | meson.source_root() / 'docs/sphinx/qmp_lexer.py', | ||
200 | qapi_gen_depends ] | ||
201 | |||
202 | - configure_file(output: 'index.html', | ||
203 | - input: files('index.html.in'), | ||
204 | - configuration: {'VERSION': meson.project_version()}, | ||
205 | - install_dir: qemu_docdir) | ||
206 | - manuals = [ 'devel', 'interop', 'tools', 'specs', 'system', 'user' ] | ||
207 | man_pages = { | ||
208 | - 'interop' : { | ||
209 | 'qemu-ga.8': (have_tools ? 'man8' : ''), | ||
210 | 'qemu-ga-ref.7': 'man7', | ||
211 | 'qemu-qmp-ref.7': 'man7', | ||
212 | 'qemu-storage-daemon-qmp-ref.7': (have_tools ? 'man7' : ''), | ||
213 | - }, | ||
214 | - 'tools': { | ||
215 | 'qemu-img.1': (have_tools ? 'man1' : ''), | ||
216 | 'qemu-nbd.8': (have_tools ? 'man8' : ''), | ||
217 | 'qemu-pr-helper.8': (have_tools ? 'man8' : ''), | ||
218 | @@ -XXX,XX +XXX,XX @@ if build_docs | ||
219 | 'qemu-trace-stap.1': (config_host.has_key('CONFIG_TRACE_SYSTEMTAP') ? 'man1' : ''), | ||
220 | 'virtfs-proxy-helper.1': (have_virtfs_proxy_helper ? 'man1' : ''), | ||
221 | 'virtiofsd.1': (have_virtiofsd ? 'man1' : ''), | ||
222 | - }, | ||
223 | - 'system': { | ||
224 | 'qemu.1': 'man1', | ||
225 | 'qemu-block-drivers.7': 'man7', | ||
226 | 'qemu-cpu-models.7': 'man7' | ||
227 | - }, | ||
228 | } | ||
229 | |||
230 | sphinxdocs = [] | ||
231 | sphinxmans = [] | ||
232 | - foreach manual : manuals | ||
233 | - private_dir = meson.current_build_dir() / (manual + '.p') | ||
234 | - output_dir = meson.current_build_dir() / manual | ||
235 | - input_dir = meson.current_source_dir() / manual | ||
236 | |||
237 | - this_manual = custom_target(manual + ' manual', | ||
238 | + private_dir = meson.current_build_dir() / 'manual.p' | ||
239 | + output_dir = meson.current_build_dir() / 'manual' | ||
240 | + input_dir = meson.current_source_dir() | ||
241 | + | ||
242 | + this_manual = custom_target('QEMU manual', | ||
243 | build_by_default: build_docs, | ||
244 | - output: [manual + '.stamp'], | ||
245 | - input: [files('conf.py'), files(manual / 'conf.py')], | ||
246 | - depfile: manual + '.d', | ||
247 | + output: 'docs.stamp', | ||
248 | + input: files('conf.py'), | ||
249 | + depfile: 'docs.d', | ||
250 | depend_files: sphinx_extn_depends, | ||
251 | command: [SPHINX_ARGS, '-Ddepfile=@DEPFILE@', | ||
252 | '-Ddepfile_stamp=@OUTPUT0@', | ||
253 | '-b', 'html', '-d', private_dir, | ||
254 | input_dir, output_dir]) | ||
255 | - sphinxdocs += this_manual | ||
256 | - if build_docs and manual != 'devel' | ||
257 | - install_subdir(output_dir, install_dir: qemu_docdir) | ||
258 | - endif | ||
259 | + sphinxdocs += this_manual | ||
260 | + install_subdir(output_dir, install_dir: qemu_docdir, strip_directory: true) | ||
261 | |||
262 | - these_man_pages = [] | ||
263 | - install_dirs = [] | ||
264 | - foreach page, section : man_pages.get(manual, {}) | ||
265 | - these_man_pages += page | ||
266 | - install_dirs += section == '' ? false : get_option('mandir') / section | ||
267 | - endforeach | ||
268 | - if these_man_pages.length() > 0 | ||
269 | - sphinxmans += custom_target(manual + ' man pages', | ||
270 | - build_by_default: build_docs, | ||
271 | - output: these_man_pages, | ||
272 | - input: this_manual, | ||
273 | - install: build_docs, | ||
274 | - install_dir: install_dirs, | ||
275 | - command: [SPHINX_ARGS, '-b', 'man', '-d', private_dir, | ||
276 | - input_dir, meson.current_build_dir()]) | ||
277 | - endif | ||
278 | + these_man_pages = [] | ||
279 | + install_dirs = [] | ||
280 | + foreach page, section : man_pages | ||
281 | + these_man_pages += page | ||
282 | + install_dirs += section == '' ? false : get_option('mandir') / section | ||
283 | endforeach | ||
284 | + | ||
285 | + sphinxmans += custom_target('QEMU man pages', | ||
286 | + build_by_default: build_docs, | ||
287 | + output: these_man_pages, | ||
288 | + input: this_manual, | ||
289 | + install: build_docs, | ||
290 | + install_dir: install_dirs, | ||
291 | + command: [SPHINX_ARGS, '-b', 'man', '-d', private_dir, | ||
292 | + input_dir, meson.current_build_dir()]) | ||
293 | + | ||
294 | alias_target('sphinxdocs', sphinxdocs) | ||
295 | alias_target('html', sphinxdocs) | ||
296 | alias_target('man', sphinxmans) | ||
297 | diff --git a/docs/specs/conf.py b/docs/specs/conf.py | ||
298 | deleted file mode 100644 | ||
299 | index XXXXXXX..XXXXXXX | ||
300 | --- a/docs/specs/conf.py | ||
301 | +++ /dev/null | ||
302 | @@ -XXX,XX +XXX,XX @@ | ||
303 | -# -*- coding: utf-8 -*- | ||
304 | -# | ||
305 | -# QEMU documentation build configuration file for the 'specs' manual. | ||
306 | -# | ||
307 | -# This includes the top level conf file and then makes any necessary tweaks. | ||
308 | -import sys | ||
309 | -import os | ||
310 | - | ||
311 | -qemu_docdir = os.path.abspath("..") | ||
312 | -parent_config = os.path.join(qemu_docdir, "conf.py") | ||
313 | -exec(compile(open(parent_config, "rb").read(), parent_config, 'exec')) | ||
314 | - | ||
315 | -# This slightly misuses the 'description', but is the best way to get | ||
316 | -# the manual title to appear in the sidebar. | ||
317 | -html_theme_options['description'] = \ | ||
318 | - u'System Emulation Guest Hardware Specifications' | ||
319 | diff --git a/docs/system/conf.py b/docs/system/conf.py | ||
320 | deleted file mode 100644 | ||
321 | index XXXXXXX..XXXXXXX | ||
322 | --- a/docs/system/conf.py | ||
323 | +++ /dev/null | ||
324 | @@ -XXX,XX +XXX,XX @@ | ||
325 | -# -*- coding: utf-8 -*- | ||
326 | -# | ||
327 | -# QEMU documentation build configuration file for the 'system' manual. | ||
328 | -# | ||
329 | -# This includes the top level conf file and then makes any necessary tweaks. | ||
330 | -import sys | ||
331 | -import os | ||
332 | - | ||
333 | -qemu_docdir = os.path.abspath("..") | ||
334 | -parent_config = os.path.join(qemu_docdir, "conf.py") | ||
335 | -exec(compile(open(parent_config, "rb").read(), parent_config, 'exec')) | ||
336 | - | ||
337 | -# This slightly misuses the 'description', but is the best way to get | ||
338 | -# the manual title to appear in the sidebar. | ||
339 | -html_theme_options['description'] = u'System Emulation User''s Guide' | ||
340 | - | ||
341 | -# One entry per manual page. List of tuples | ||
342 | -# (source start file, name, description, authors, manual section). | ||
343 | -man_pages = [ | ||
344 | - ('qemu-manpage', 'qemu', u'QEMU User Documentation', | ||
345 | - ['Fabrice Bellard'], 1), | ||
346 | - ('qemu-block-drivers', 'qemu-block-drivers', | ||
347 | - u'QEMU block drivers reference', | ||
348 | - ['Fabrice Bellard and the QEMU Project developers'], 7), | ||
349 | - ('qemu-cpu-models', 'qemu-cpu-models', | ||
350 | - u'QEMU CPU Models', | ||
351 | - ['The QEMU Project developers'], 7) | ||
352 | -] | ||
353 | diff --git a/docs/tools/conf.py b/docs/tools/conf.py | ||
354 | deleted file mode 100644 | ||
355 | index XXXXXXX..XXXXXXX | ||
356 | --- a/docs/tools/conf.py | ||
357 | +++ /dev/null | ||
358 | @@ -XXX,XX +XXX,XX @@ | ||
359 | -# -*- coding: utf-8 -*- | ||
360 | -# | ||
361 | -# QEMU documentation build configuration file for the 'tools' manual. | ||
362 | -# | ||
363 | -# This includes the top level conf file and then makes any necessary tweaks. | ||
364 | -import sys | ||
365 | -import os | ||
366 | - | ||
367 | -qemu_docdir = os.path.abspath("..") | ||
368 | -parent_config = os.path.join(qemu_docdir, "conf.py") | ||
369 | -exec(compile(open(parent_config, "rb").read(), parent_config, 'exec')) | ||
370 | - | ||
371 | -# This slightly misuses the 'description', but is the best way to get | ||
372 | -# the manual title to appear in the sidebar. | ||
373 | -html_theme_options['description'] = \ | ||
374 | - u'Tools Guide' | ||
375 | - | ||
376 | -# One entry per manual page. List of tuples | ||
377 | -# (source start file, name, description, authors, manual section). | ||
378 | -man_pages = [ | ||
379 | - ('qemu-img', 'qemu-img', u'QEMU disk image utility', | ||
380 | - ['Fabrice Bellard'], 1), | ||
381 | - ('qemu-storage-daemon', 'qemu-storage-daemon', u'QEMU storage daemon', | ||
382 | - [], 1), | ||
383 | - ('qemu-nbd', 'qemu-nbd', u'QEMU Disk Network Block Device Server', | ||
384 | - ['Anthony Liguori <anthony@codemonkey.ws>'], 8), | ||
385 | - ('qemu-pr-helper', 'qemu-pr-helper', 'QEMU persistent reservation helper', | ||
386 | - [], 8), | ||
387 | - ('qemu-trace-stap', 'qemu-trace-stap', u'QEMU SystemTap trace tool', | ||
388 | - [], 1), | ||
389 | - ('virtfs-proxy-helper', 'virtfs-proxy-helper', | ||
390 | - u'QEMU 9p virtfs proxy filesystem helper', | ||
391 | - ['M. Mohan Kumar'], 1), | ||
392 | - ('virtiofsd', 'virtiofsd', u'QEMU virtio-fs shared file system daemon', | ||
393 | - ['Stefan Hajnoczi <stefanha@redhat.com>', | ||
394 | - 'Masayoshi Mizuma <m.mizuma@jp.fujitsu.com>'], 1), | ||
395 | -] | ||
396 | diff --git a/docs/user/conf.py b/docs/user/conf.py | ||
397 | deleted file mode 100644 | ||
398 | index XXXXXXX..XXXXXXX | ||
399 | --- a/docs/user/conf.py | ||
400 | +++ /dev/null | ||
401 | @@ -XXX,XX +XXX,XX @@ | ||
402 | -# -*- coding: utf-8 -*- | ||
403 | -# | ||
404 | -# QEMU documentation build configuration file for the 'user' manual. | ||
405 | -# | ||
406 | -# This includes the top level conf file and then makes any necessary tweaks. | ||
407 | -import sys | ||
408 | -import os | ||
409 | - | ||
410 | -qemu_docdir = os.path.abspath("..") | ||
411 | -parent_config = os.path.join(qemu_docdir, "conf.py") | ||
412 | -exec(compile(open(parent_config, "rb").read(), parent_config, 'exec')) | ||
413 | - | ||
414 | -# This slightly misuses the 'description', but is the best way to get | ||
415 | -# the manual title to appear in the sidebar. | ||
416 | -html_theme_options['description'] = u'User Mode Emulation User''s Guide' | ||
417 | -- | 62 | -- |
418 | 2.20.1 | 63 | 2.43.0 |
419 | |||
420 | diff view generated by jsdifflib |
1 | In commit cd8be50e58f63413c0 we converted the A32 coprocessor | 1 | Currently we call icount_start_warp_timer() from timerlist_rearm(). |
---|---|---|---|
2 | insns to decodetree. This accidentally broke XScale/iWMMXt insns, | 2 | This produces incorrect behaviour, because timerlist_rearm() is |
3 | because it moved the handling of "cp insns which are handled | 3 | called, for instance, when a timer callback modifies its timer. We |
4 | by looking up the cp register in the hashtable" from after the | 4 | cannot decide here to warp the timer forwards to the next timer |
5 | call to the legacy disas_xscale_insn() decode to before it, | 5 | deadline merely because all_cpu_threads_idle() is true, because the |
6 | with the result that all XScale/iWMMXt insns now UNDEF. | 6 | timer callback we were called from (or some other callback later in |
7 | the list of callbacks being invoked) may be about to raise a CPU | ||
8 | interrupt and move a CPU from idle to ready. | ||
7 | 9 | ||
8 | Update valid_cp() so that it knows that on XScale cp 0 and 1 | 10 | The only valid place to choose to warp the timer forward is from the |
9 | are not standard coprocessor instructions; this will cause | 11 | main loop, when we know we have no outstanding IO or timer callbacks |
10 | the decodetree trans_ functions to ignore them, so that | 12 | that might be about to wake up a CPU. |
11 | execution will correctly get through to the legacy decode again. | 13 | |
14 | For Arm guests, this bug was mostly latent until the refactoring | ||
15 | commit f6fc36deef6abc ("target/arm/helper: Implement | ||
16 | CNTHCTL_EL2.CNT[VP]MASK"), which exposed it because it refactored a | ||
17 | timer callback so that it happened to call timer_mod() first and | ||
18 | raise the interrupt second, when it had previously raised the | ||
19 | interrupt first and called timer_mod() afterwards. | ||
20 | |||
21 | This call seems to have originally derived from the | ||
22 | pre-record-and-replay icount code, which (as of e.g. commit | ||
23 | db1a49726c3c in 2010) in this location did a call to | ||
24 | qemu_notify_event(), necessary to get the icount code in the vCPU | ||
25 | round-robin thread to stop and recalculate the icount deadline when a | ||
26 | timer was reprogrammed from the IO thread. In current QEMU, | ||
27 | everything is done on the vCPU thread when we are in icount mode, so | ||
28 | there's no need to try to notify another thread here. | ||
29 | |||
30 | I suspect that the other reason why this call was doing icount timer | ||
31 | warping is that it pre-dates commit efab87cf79077a from 2015, which | ||
32 | added a call to icount_start_warp_timer() to main_loop_wait(). Once | ||
33 | the call in timerlist_rearm() has been removed, if the timer | ||
34 | callbacks don't cause any CPU to be woken up then we will end up | ||
35 | calling icount_start_warp_timer() from main_loop_wait() when the rr | ||
36 | main loop code calls rr_wait_io_event(). | ||
37 | |||
38 | Remove the incorrect call from timerlist_rearm(). | ||
12 | 39 | ||
13 | Cc: qemu-stable@nongnu.org | 40 | Cc: qemu-stable@nongnu.org |
14 | Reported-by: Guenter Roeck <linux@roeck-us.net> | 41 | Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2703 |
15 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 42 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
16 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 43 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
17 | Tested-by: Guenter Roeck <linux@roeck-us.net> | 44 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> |
18 | Message-id: 20210108195157.32067-1-peter.maydell@linaro.org | 45 | Tested-by: Alex Bennée <alex.bennee@linaro.org> |
46 | Message-id: 20250210135804.3526943-1-peter.maydell@linaro.org | ||
19 | --- | 47 | --- |
20 | target/arm/translate.c | 7 +++++++ | 48 | util/qemu-timer.c | 4 ---- |
21 | 1 file changed, 7 insertions(+) | 49 | 1 file changed, 4 deletions(-) |
22 | 50 | ||
23 | diff --git a/target/arm/translate.c b/target/arm/translate.c | 51 | diff --git a/util/qemu-timer.c b/util/qemu-timer.c |
24 | index XXXXXXX..XXXXXXX 100644 | 52 | index XXXXXXX..XXXXXXX 100644 |
25 | --- a/target/arm/translate.c | 53 | --- a/util/qemu-timer.c |
26 | +++ b/target/arm/translate.c | 54 | +++ b/util/qemu-timer.c |
27 | @@ -XXX,XX +XXX,XX @@ static bool valid_cp(DisasContext *s, int cp) | 55 | @@ -XXX,XX +XXX,XX @@ static bool timer_mod_ns_locked(QEMUTimerList *timer_list, |
28 | * only cp14 and cp15 are valid, and other values aren't considered | 56 | |
29 | * to be in the coprocessor-instruction space at all. v8M still | 57 | static void timerlist_rearm(QEMUTimerList *timer_list) |
30 | * permits coprocessors 0..7. | 58 | { |
31 | + * For XScale, we must not decode the XScale cp0, cp1 space as | 59 | - /* Interrupt execution to force deadline recalculation. */ |
32 | + * a standard coprocessor insn, because we want to fall through to | 60 | - if (icount_enabled() && timer_list->clock->type == QEMU_CLOCK_VIRTUAL) { |
33 | + * the legacy disas_xscale_insn() decoder after decodetree is done. | 61 | - icount_start_warp_timer(); |
34 | */ | 62 | - } |
35 | + if (arm_dc_feature(s, ARM_FEATURE_XSCALE) && (cp == 0 || cp == 1)) { | 63 | timerlist_notify(timer_list); |
36 | + return false; | 64 | } |
37 | + } | 65 | |
38 | + | ||
39 | if (arm_dc_feature(s, ARM_FEATURE_V8) && | ||
40 | !arm_dc_feature(s, ARM_FEATURE_M)) { | ||
41 | return cp >= 14; | ||
42 | -- | 66 | -- |
43 | 2.20.1 | 67 | 2.43.0 |
44 | 68 | ||
45 | 69 | diff view generated by jsdifflib |
1 | In commit 1982e1602d15 we added a new qemu-storage-daemon(1) manpage. | 1 | Expand the example in the comment documenting MO_ATOM_SUBALIGN, |
---|---|---|---|
2 | At the moment new manpages have to be listed both in the conf.py for | 2 | to be clearer about the atomicity guarantees it represents. |
3 | Sphinx and also in docs/meson.build for Meson. We forgot the second | ||
4 | of those -- correct the omission. | ||
5 | 3 | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> | 5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
8 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | 6 | Message-id: 20250228103222.1838913-1-peter.maydell@linaro.org |
9 | Message-id: 20210108161416.21129-2-peter.maydell@linaro.org | ||
10 | --- | 7 | --- |
11 | docs/meson.build | 1 + | 8 | include/exec/memop.h | 8 ++++++-- |
12 | 1 file changed, 1 insertion(+) | 9 | 1 file changed, 6 insertions(+), 2 deletions(-) |
13 | 10 | ||
14 | diff --git a/docs/meson.build b/docs/meson.build | 11 | diff --git a/include/exec/memop.h b/include/exec/memop.h |
15 | index XXXXXXX..XXXXXXX 100644 | 12 | index XXXXXXX..XXXXXXX 100644 |
16 | --- a/docs/meson.build | 13 | --- a/include/exec/memop.h |
17 | +++ b/docs/meson.build | 14 | +++ b/include/exec/memop.h |
18 | @@ -XXX,XX +XXX,XX @@ if build_docs | 15 | @@ -XXX,XX +XXX,XX @@ typedef enum MemOp { |
19 | 'qemu-img.1': (have_tools ? 'man1' : ''), | 16 | * Depending on alignment, one or both will be single-copy atomic. |
20 | 'qemu-nbd.8': (have_tools ? 'man8' : ''), | 17 | * This is the atomicity e.g. of Arm FEAT_LSE2 LDP. |
21 | 'qemu-pr-helper.8': (have_tools ? 'man8' : ''), | 18 | * MO_ATOM_SUBALIGN: the operation is single-copy atomic by parts |
22 | + 'qemu-storage-daemon.1': (have_tools ? 'man1' : ''), | 19 | - * by the alignment. E.g. if the address is 0 mod 4, then each |
23 | 'qemu-trace-stap.1': (config_host.has_key('CONFIG_TRACE_SYSTEMTAP') ? 'man1' : ''), | 20 | - * 4-byte subobject is single-copy atomic. |
24 | 'virtfs-proxy-helper.1': (have_virtfs_proxy_helper ? 'man1' : ''), | 21 | + * by the alignment. E.g. if an 8-byte value is accessed at an |
25 | 'virtiofsd.1': (have_virtiofsd ? 'man1' : ''), | 22 | + * address which is 0 mod 8, then the whole 8-byte access is |
23 | + * single-copy atomic; otherwise, if it is accessed at 0 mod 4 | ||
24 | + * then each 4-byte subobject is single-copy atomic; otherwise | ||
25 | + * if it is accessed at 0 mod 2 then the four 2-byte subobjects | ||
26 | + * are single-copy atomic. | ||
27 | * This is the atomicity e.g. of IBM Power. | ||
28 | * MO_ATOM_NONE: the operation has no atomicity requirements. | ||
29 | * | ||
26 | -- | 30 | -- |
27 | 2.20.1 | 31 | 2.43.0 |
28 | |||
29 | diff view generated by jsdifflib |
1 | From: Hao Wu <wuhaotsh@google.com> | 1 | From: JianChunfu <jansef.jian@hj-micro.com> |
---|---|---|---|
2 | 2 | ||
3 | The ADC is part of NPCM7XX Module. Its behavior is controled by the | 3 | Use a similar terminology smmu_hash_remove_by_sid_range() as the one |
4 | ADC_CON register. It converts one of the eight analog inputs into a | 4 | being used for other hash table matching functions since |
5 | digital input and stores it in the ADC_DATA register when enabled. | 5 | smmuv3_invalidate_ste() name is not self explanatory, and introduce a |
6 | helper that invokes the g_hash_table_foreach_remove. | ||
6 | 7 | ||
7 | Users can alter input value by using qom-set QMP command. | 8 | No functional change intended. |
8 | 9 | ||
9 | Reviewed-by: Havard Skinnemoen <hskinnemoen@google.com> | 10 | Signed-off-by: JianChunfu <jansef.jian@hj-micro.com> |
10 | Reviewed-by: Tyrone Ting <kfting@nuvoton.com> | 11 | Reviewed-by: Eric Auger <eric.auger@redhat.com> |
11 | Signed-off-by: Hao Wu <wuhaotsh@google.com> | 12 | Message-id: 20250228031438.3916-1-jansef.jian@hj-micro.com |
12 | Message-id: 20210108190945.949196-4-wuhaotsh@google.com | ||
13 | [PMM: Added missing hw/adc/trace.h file] | ||
14 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
15 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
16 | --- | 14 | --- |
17 | docs/system/arm/nuvoton.rst | 2 +- | 15 | hw/arm/smmu-internal.h | 5 ----- |
18 | meson.build | 1 + | 16 | include/hw/arm/smmu-common.h | 6 ++++++ |
19 | hw/adc/trace.h | 1 + | 17 | hw/arm/smmu-common.c | 21 +++++++++++++++++++++ |
20 | include/hw/adc/npcm7xx_adc.h | 69 ++++++ | 18 | hw/arm/smmuv3.c | 19 ++----------------- |
21 | include/hw/arm/npcm7xx.h | 2 + | 19 | hw/arm/trace-events | 3 ++- |
22 | hw/adc/npcm7xx_adc.c | 301 ++++++++++++++++++++++++++ | 20 | 5 files changed, 31 insertions(+), 23 deletions(-) |
23 | hw/arm/npcm7xx.c | 24 ++- | ||
24 | tests/qtest/npcm7xx_adc-test.c | 377 +++++++++++++++++++++++++++++++++ | ||
25 | hw/adc/meson.build | 1 + | ||
26 | hw/adc/trace-events | 5 + | ||
27 | tests/qtest/meson.build | 3 +- | ||
28 | 11 files changed, 783 insertions(+), 3 deletions(-) | ||
29 | create mode 100644 hw/adc/trace.h | ||
30 | create mode 100644 include/hw/adc/npcm7xx_adc.h | ||
31 | create mode 100644 hw/adc/npcm7xx_adc.c | ||
32 | create mode 100644 tests/qtest/npcm7xx_adc-test.c | ||
33 | create mode 100644 hw/adc/trace-events | ||
34 | 21 | ||
35 | diff --git a/docs/system/arm/nuvoton.rst b/docs/system/arm/nuvoton.rst | 22 | diff --git a/hw/arm/smmu-internal.h b/hw/arm/smmu-internal.h |
36 | index XXXXXXX..XXXXXXX 100644 | 23 | index XXXXXXX..XXXXXXX 100644 |
37 | --- a/docs/system/arm/nuvoton.rst | 24 | --- a/hw/arm/smmu-internal.h |
38 | +++ b/docs/system/arm/nuvoton.rst | 25 | +++ b/hw/arm/smmu-internal.h |
39 | @@ -XXX,XX +XXX,XX @@ Supported devices | 26 | @@ -XXX,XX +XXX,XX @@ typedef struct SMMUIOTLBPageInvInfo { |
40 | * Random Number Generator (RNG) | 27 | uint64_t mask; |
41 | * USB host (USBH) | 28 | } SMMUIOTLBPageInvInfo; |
42 | * GPIO controller | 29 | |
43 | + * Analog to Digital Converter (ADC) | 30 | -typedef struct SMMUSIDRange { |
44 | 31 | - uint32_t start; | |
45 | Missing devices | 32 | - uint32_t end; |
46 | --------------- | 33 | -} SMMUSIDRange; |
47 | @@ -XXX,XX +XXX,XX @@ Missing devices | 34 | - |
48 | * USB device (USBD) | 35 | #endif |
49 | * SMBus controller (SMBF) | 36 | diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h |
50 | * Peripheral SPI controller (PSPI) | ||
51 | - * Analog to Digital Converter (ADC) | ||
52 | * SD/MMC host | ||
53 | * PECI interface | ||
54 | * Pulse Width Modulation (PWM) | ||
55 | diff --git a/meson.build b/meson.build | ||
56 | index XXXXXXX..XXXXXXX 100644 | 37 | index XXXXXXX..XXXXXXX 100644 |
57 | --- a/meson.build | 38 | --- a/include/hw/arm/smmu-common.h |
58 | +++ b/meson.build | 39 | +++ b/include/hw/arm/smmu-common.h |
59 | @@ -XXX,XX +XXX,XX @@ if have_system | 40 | @@ -XXX,XX +XXX,XX @@ typedef struct SMMUIOTLBKey { |
60 | 'chardev', | 41 | uint8_t level; |
61 | 'hw/9pfs', | 42 | } SMMUIOTLBKey; |
62 | 'hw/acpi', | 43 | |
63 | + 'hw/adc', | 44 | +typedef struct SMMUSIDRange { |
64 | 'hw/alpha', | 45 | + uint32_t start; |
65 | 'hw/arm', | 46 | + uint32_t end; |
66 | 'hw/audio', | 47 | +} SMMUSIDRange; |
67 | diff --git a/hw/adc/trace.h b/hw/adc/trace.h | ||
68 | new file mode 100644 | ||
69 | index XXXXXXX..XXXXXXX | ||
70 | --- /dev/null | ||
71 | +++ b/hw/adc/trace.h | ||
72 | @@ -0,0 +1 @@ | ||
73 | +#include "trace/trace-hw_adc.h" | ||
74 | diff --git a/include/hw/adc/npcm7xx_adc.h b/include/hw/adc/npcm7xx_adc.h | ||
75 | new file mode 100644 | ||
76 | index XXXXXXX..XXXXXXX | ||
77 | --- /dev/null | ||
78 | +++ b/include/hw/adc/npcm7xx_adc.h | ||
79 | @@ -XXX,XX +XXX,XX @@ | ||
80 | +/* | ||
81 | + * Nuvoton NPCM7xx ADC Module | ||
82 | + * | ||
83 | + * Copyright 2020 Google LLC | ||
84 | + * | ||
85 | + * This program is free software; you can redistribute it and/or modify it | ||
86 | + * under the terms of the GNU General Public License as published by the | ||
87 | + * Free Software Foundation; either version 2 of the License, or | ||
88 | + * (at your option) any later version. | ||
89 | + * | ||
90 | + * This program is distributed in the hope that it will be useful, but WITHOUT | ||
91 | + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
92 | + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | ||
93 | + * for more details. | ||
94 | + */ | ||
95 | +#ifndef NPCM7XX_ADC_H | ||
96 | +#define NPCM7XX_ADC_H | ||
97 | + | 48 | + |
98 | +#include "hw/clock.h" | 49 | struct SMMUState { |
99 | +#include "hw/irq.h" | 50 | /* <private> */ |
100 | +#include "hw/sysbus.h" | 51 | SysBusDevice dev; |
101 | +#include "qemu/timer.h" | 52 | @@ -XXX,XX +XXX,XX @@ void smmu_iotlb_inv_iova(SMMUState *s, int asid, int vmid, dma_addr_t iova, |
53 | uint8_t tg, uint64_t num_pages, uint8_t ttl); | ||
54 | void smmu_iotlb_inv_ipa(SMMUState *s, int vmid, dma_addr_t ipa, uint8_t tg, | ||
55 | uint64_t num_pages, uint8_t ttl); | ||
56 | +void smmu_configs_inv_sid_range(SMMUState *s, SMMUSIDRange sid_range); | ||
57 | /* Unmap the range of all the notifiers registered to any IOMMU mr */ | ||
58 | void smmu_inv_notifiers_all(SMMUState *s); | ||
59 | |||
60 | diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c | ||
61 | index XXXXXXX..XXXXXXX 100644 | ||
62 | --- a/hw/arm/smmu-common.c | ||
63 | +++ b/hw/arm/smmu-common.c | ||
64 | @@ -XXX,XX +XXX,XX @@ static gboolean smmu_hash_remove_by_vmid_ipa(gpointer key, gpointer value, | ||
65 | ((entry->iova & ~info->mask) == info->iova); | ||
66 | } | ||
67 | |||
68 | +static gboolean | ||
69 | +smmu_hash_remove_by_sid_range(gpointer key, gpointer value, gpointer user_data) | ||
70 | +{ | ||
71 | + SMMUDevice *sdev = (SMMUDevice *)key; | ||
72 | + uint32_t sid = smmu_get_sid(sdev); | ||
73 | + SMMUSIDRange *sid_range = (SMMUSIDRange *)user_data; | ||
102 | + | 74 | + |
103 | +#define NPCM7XX_ADC_NUM_INPUTS 8 | 75 | + if (sid < sid_range->start || sid > sid_range->end) { |
104 | +/** | 76 | + return false; |
105 | + * This value should not be changed unless write_adc_calibration function in | 77 | + } |
106 | + * hw/arm/npcm7xx.c is also changed. | 78 | + trace_smmu_config_cache_inv(sid); |
107 | + */ | 79 | + return true; |
108 | +#define NPCM7XX_ADC_NUM_CALIB 2 | ||
109 | + | ||
110 | +/** | ||
111 | + * struct NPCM7xxADCState - Analog to Digital Converter Module device state. | ||
112 | + * @parent: System bus device. | ||
113 | + * @iomem: Memory region through which registers are accessed. | ||
114 | + * @conv_timer: The timer counts down remaining cycles for the conversion. | ||
115 | + * @irq: GIC interrupt line to fire on expiration (if enabled). | ||
116 | + * @con: The Control Register. | ||
117 | + * @data: The Data Buffer. | ||
118 | + * @clock: The ADC Clock. | ||
119 | + * @adci: The input voltage in units of uV. 1uv = 1e-6V. | ||
120 | + * @vref: The external reference voltage. | ||
121 | + * @iref: The internal reference voltage, initialized at launch time. | ||
122 | + * @rv: The calibrated output values of 0.5V and 1.5V for the ADC. | ||
123 | + */ | ||
124 | +typedef struct { | ||
125 | + SysBusDevice parent; | ||
126 | + | ||
127 | + MemoryRegion iomem; | ||
128 | + | ||
129 | + QEMUTimer conv_timer; | ||
130 | + | ||
131 | + qemu_irq irq; | ||
132 | + uint32_t con; | ||
133 | + uint32_t data; | ||
134 | + Clock *clock; | ||
135 | + | ||
136 | + /* Voltages are in unit of uV. 1V = 1000000uV. */ | ||
137 | + uint32_t adci[NPCM7XX_ADC_NUM_INPUTS]; | ||
138 | + uint32_t vref; | ||
139 | + uint32_t iref; | ||
140 | + | ||
141 | + uint16_t calibration_r_values[NPCM7XX_ADC_NUM_CALIB]; | ||
142 | +} NPCM7xxADCState; | ||
143 | + | ||
144 | +#define TYPE_NPCM7XX_ADC "npcm7xx-adc" | ||
145 | +#define NPCM7XX_ADC(obj) \ | ||
146 | + OBJECT_CHECK(NPCM7xxADCState, (obj), TYPE_NPCM7XX_ADC) | ||
147 | + | ||
148 | +#endif /* NPCM7XX_ADC_H */ | ||
149 | diff --git a/include/hw/arm/npcm7xx.h b/include/hw/arm/npcm7xx.h | ||
150 | index XXXXXXX..XXXXXXX 100644 | ||
151 | --- a/include/hw/arm/npcm7xx.h | ||
152 | +++ b/include/hw/arm/npcm7xx.h | ||
153 | @@ -XXX,XX +XXX,XX @@ | ||
154 | #define NPCM7XX_H | ||
155 | |||
156 | #include "hw/boards.h" | ||
157 | +#include "hw/adc/npcm7xx_adc.h" | ||
158 | #include "hw/cpu/a9mpcore.h" | ||
159 | #include "hw/gpio/npcm7xx_gpio.h" | ||
160 | #include "hw/mem/npcm7xx_mc.h" | ||
161 | @@ -XXX,XX +XXX,XX @@ typedef struct NPCM7xxState { | ||
162 | NPCM7xxGCRState gcr; | ||
163 | NPCM7xxCLKState clk; | ||
164 | NPCM7xxTimerCtrlState tim[3]; | ||
165 | + NPCM7xxADCState adc; | ||
166 | NPCM7xxOTPState key_storage; | ||
167 | NPCM7xxOTPState fuse_array; | ||
168 | NPCM7xxMCState mc; | ||
169 | diff --git a/hw/adc/npcm7xx_adc.c b/hw/adc/npcm7xx_adc.c | ||
170 | new file mode 100644 | ||
171 | index XXXXXXX..XXXXXXX | ||
172 | --- /dev/null | ||
173 | +++ b/hw/adc/npcm7xx_adc.c | ||
174 | @@ -XXX,XX +XXX,XX @@ | ||
175 | +/* | ||
176 | + * Nuvoton NPCM7xx ADC Module | ||
177 | + * | ||
178 | + * Copyright 2020 Google LLC | ||
179 | + * | ||
180 | + * This program is free software; you can redistribute it and/or modify it | ||
181 | + * under the terms of the GNU General Public License as published by the | ||
182 | + * Free Software Foundation; either version 2 of the License, or | ||
183 | + * (at your option) any later version. | ||
184 | + * | ||
185 | + * This program is distributed in the hope that it will be useful, but WITHOUT | ||
186 | + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
187 | + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | ||
188 | + * for more details. | ||
189 | + */ | ||
190 | + | ||
191 | +#include "qemu/osdep.h" | ||
192 | +#include "hw/adc/npcm7xx_adc.h" | ||
193 | +#include "hw/qdev-clock.h" | ||
194 | +#include "hw/qdev-properties.h" | ||
195 | +#include "hw/registerfields.h" | ||
196 | +#include "migration/vmstate.h" | ||
197 | +#include "qemu/log.h" | ||
198 | +#include "qemu/module.h" | ||
199 | +#include "qemu/timer.h" | ||
200 | +#include "qemu/units.h" | ||
201 | +#include "trace.h" | ||
202 | + | ||
203 | +REG32(NPCM7XX_ADC_CON, 0x0) | ||
204 | +REG32(NPCM7XX_ADC_DATA, 0x4) | ||
205 | + | ||
206 | +/* Register field definitions. */ | ||
207 | +#define NPCM7XX_ADC_CON_MUX(rv) extract32(rv, 24, 4) | ||
208 | +#define NPCM7XX_ADC_CON_INT_EN BIT(21) | ||
209 | +#define NPCM7XX_ADC_CON_REFSEL BIT(19) | ||
210 | +#define NPCM7XX_ADC_CON_INT BIT(18) | ||
211 | +#define NPCM7XX_ADC_CON_EN BIT(17) | ||
212 | +#define NPCM7XX_ADC_CON_RST BIT(16) | ||
213 | +#define NPCM7XX_ADC_CON_CONV BIT(14) | ||
214 | +#define NPCM7XX_ADC_CON_DIV(rv) extract32(rv, 1, 8) | ||
215 | + | ||
216 | +#define NPCM7XX_ADC_MAX_RESULT 1023 | ||
217 | +#define NPCM7XX_ADC_DEFAULT_IREF 2000000 | ||
218 | +#define NPCM7XX_ADC_CONV_CYCLES 20 | ||
219 | +#define NPCM7XX_ADC_RESET_CYCLES 10 | ||
220 | +#define NPCM7XX_ADC_R0_INPUT 500000 | ||
221 | +#define NPCM7XX_ADC_R1_INPUT 1500000 | ||
222 | + | ||
223 | +static void npcm7xx_adc_reset(NPCM7xxADCState *s) | ||
224 | +{ | ||
225 | + timer_del(&s->conv_timer); | ||
226 | + s->con = 0x000c0001; | ||
227 | + s->data = 0x00000000; | ||
228 | +} | 80 | +} |
229 | + | 81 | + |
230 | +static uint32_t npcm7xx_adc_convert(uint32_t input, uint32_t ref) | 82 | +void smmu_configs_inv_sid_range(SMMUState *s, SMMUSIDRange sid_range) |
231 | +{ | 83 | +{ |
232 | + uint32_t result; | 84 | + trace_smmu_configs_inv_sid_range(sid_range.start, sid_range.end); |
233 | + | 85 | + g_hash_table_foreach_remove(s->configs, smmu_hash_remove_by_sid_range, |
234 | + result = input * (NPCM7XX_ADC_MAX_RESULT + 1) / ref; | 86 | + &sid_range); |
235 | + if (result > NPCM7XX_ADC_MAX_RESULT) { | ||
236 | + result = NPCM7XX_ADC_MAX_RESULT; | ||
237 | + } | ||
238 | + | ||
239 | + return result; | ||
240 | +} | 87 | +} |
241 | + | 88 | + |
242 | +static uint32_t npcm7xx_adc_prescaler(NPCM7xxADCState *s) | 89 | void smmu_iotlb_inv_iova(SMMUState *s, int asid, int vmid, dma_addr_t iova, |
243 | +{ | 90 | uint8_t tg, uint64_t num_pages, uint8_t ttl) |
244 | + return 2 * (NPCM7XX_ADC_CON_DIV(s->con) + 1); | 91 | { |
245 | +} | 92 | diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c |
246 | + | ||
247 | +static void npcm7xx_adc_start_timer(Clock *clk, QEMUTimer *timer, | ||
248 | + uint32_t cycles, uint32_t prescaler) | ||
249 | +{ | ||
250 | + int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); | ||
251 | + int64_t ticks = cycles; | ||
252 | + int64_t ns; | ||
253 | + | ||
254 | + ticks *= prescaler; | ||
255 | + ns = clock_ticks_to_ns(clk, ticks); | ||
256 | + ns += now; | ||
257 | + timer_mod(timer, ns); | ||
258 | +} | ||
259 | + | ||
260 | +static void npcm7xx_adc_start_convert(NPCM7xxADCState *s) | ||
261 | +{ | ||
262 | + uint32_t prescaler = npcm7xx_adc_prescaler(s); | ||
263 | + | ||
264 | + npcm7xx_adc_start_timer(s->clock, &s->conv_timer, NPCM7XX_ADC_CONV_CYCLES, | ||
265 | + prescaler); | ||
266 | +} | ||
267 | + | ||
268 | +static void npcm7xx_adc_convert_done(void *opaque) | ||
269 | +{ | ||
270 | + NPCM7xxADCState *s = opaque; | ||
271 | + uint32_t input = NPCM7XX_ADC_CON_MUX(s->con); | ||
272 | + uint32_t ref = (s->con & NPCM7XX_ADC_CON_REFSEL) | ||
273 | + ? s->iref : s->vref; | ||
274 | + | ||
275 | + if (input >= NPCM7XX_ADC_NUM_INPUTS) { | ||
276 | + qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid input: %u\n", | ||
277 | + __func__, input); | ||
278 | + return; | ||
279 | + } | ||
280 | + s->data = npcm7xx_adc_convert(s->adci[input], ref); | ||
281 | + if (s->con & NPCM7XX_ADC_CON_INT_EN) { | ||
282 | + s->con |= NPCM7XX_ADC_CON_INT; | ||
283 | + qemu_irq_raise(s->irq); | ||
284 | + } | ||
285 | + s->con &= ~NPCM7XX_ADC_CON_CONV; | ||
286 | +} | ||
287 | + | ||
288 | +static void npcm7xx_adc_calibrate(NPCM7xxADCState *adc) | ||
289 | +{ | ||
290 | + adc->calibration_r_values[0] = npcm7xx_adc_convert(NPCM7XX_ADC_R0_INPUT, | ||
291 | + adc->iref); | ||
292 | + adc->calibration_r_values[1] = npcm7xx_adc_convert(NPCM7XX_ADC_R1_INPUT, | ||
293 | + adc->iref); | ||
294 | +} | ||
295 | + | ||
296 | +static void npcm7xx_adc_write_con(NPCM7xxADCState *s, uint32_t new_con) | ||
297 | +{ | ||
298 | + uint32_t old_con = s->con; | ||
299 | + | ||
300 | + /* Write ADC_INT to 1 to clear it */ | ||
301 | + if (new_con & NPCM7XX_ADC_CON_INT) { | ||
302 | + new_con &= ~NPCM7XX_ADC_CON_INT; | ||
303 | + qemu_irq_lower(s->irq); | ||
304 | + } else if (old_con & NPCM7XX_ADC_CON_INT) { | ||
305 | + new_con |= NPCM7XX_ADC_CON_INT; | ||
306 | + } | ||
307 | + | ||
308 | + s->con = new_con; | ||
309 | + | ||
310 | + if (s->con & NPCM7XX_ADC_CON_RST) { | ||
311 | + npcm7xx_adc_reset(s); | ||
312 | + return; | ||
313 | + } | ||
314 | + | ||
315 | + if ((s->con & NPCM7XX_ADC_CON_EN)) { | ||
316 | + if (s->con & NPCM7XX_ADC_CON_CONV) { | ||
317 | + if (!(old_con & NPCM7XX_ADC_CON_CONV)) { | ||
318 | + npcm7xx_adc_start_convert(s); | ||
319 | + } | ||
320 | + } else { | ||
321 | + timer_del(&s->conv_timer); | ||
322 | + } | ||
323 | + } | ||
324 | +} | ||
325 | + | ||
326 | +static uint64_t npcm7xx_adc_read(void *opaque, hwaddr offset, unsigned size) | ||
327 | +{ | ||
328 | + uint64_t value = 0; | ||
329 | + NPCM7xxADCState *s = opaque; | ||
330 | + | ||
331 | + switch (offset) { | ||
332 | + case A_NPCM7XX_ADC_CON: | ||
333 | + value = s->con; | ||
334 | + break; | ||
335 | + | ||
336 | + case A_NPCM7XX_ADC_DATA: | ||
337 | + value = s->data; | ||
338 | + break; | ||
339 | + | ||
340 | + default: | ||
341 | + qemu_log_mask(LOG_GUEST_ERROR, | ||
342 | + "%s: invalid offset 0x%04" HWADDR_PRIx "\n", | ||
343 | + __func__, offset); | ||
344 | + break; | ||
345 | + } | ||
346 | + | ||
347 | + trace_npcm7xx_adc_read(DEVICE(s)->canonical_path, offset, value); | ||
348 | + return value; | ||
349 | +} | ||
350 | + | ||
351 | +static void npcm7xx_adc_write(void *opaque, hwaddr offset, uint64_t v, | ||
352 | + unsigned size) | ||
353 | +{ | ||
354 | + NPCM7xxADCState *s = opaque; | ||
355 | + | ||
356 | + trace_npcm7xx_adc_write(DEVICE(s)->canonical_path, offset, v); | ||
357 | + switch (offset) { | ||
358 | + case A_NPCM7XX_ADC_CON: | ||
359 | + npcm7xx_adc_write_con(s, v); | ||
360 | + break; | ||
361 | + | ||
362 | + case A_NPCM7XX_ADC_DATA: | ||
363 | + qemu_log_mask(LOG_GUEST_ERROR, | ||
364 | + "%s: register @ 0x%04" HWADDR_PRIx " is read-only\n", | ||
365 | + __func__, offset); | ||
366 | + break; | ||
367 | + | ||
368 | + default: | ||
369 | + qemu_log_mask(LOG_GUEST_ERROR, | ||
370 | + "%s: invalid offset 0x%04" HWADDR_PRIx "\n", | ||
371 | + __func__, offset); | ||
372 | + break; | ||
373 | + } | ||
374 | + | ||
375 | +} | ||
376 | + | ||
377 | +static const struct MemoryRegionOps npcm7xx_adc_ops = { | ||
378 | + .read = npcm7xx_adc_read, | ||
379 | + .write = npcm7xx_adc_write, | ||
380 | + .endianness = DEVICE_LITTLE_ENDIAN, | ||
381 | + .valid = { | ||
382 | + .min_access_size = 4, | ||
383 | + .max_access_size = 4, | ||
384 | + .unaligned = false, | ||
385 | + }, | ||
386 | +}; | ||
387 | + | ||
388 | +static void npcm7xx_adc_enter_reset(Object *obj, ResetType type) | ||
389 | +{ | ||
390 | + NPCM7xxADCState *s = NPCM7XX_ADC(obj); | ||
391 | + | ||
392 | + npcm7xx_adc_reset(s); | ||
393 | +} | ||
394 | + | ||
395 | +static void npcm7xx_adc_hold_reset(Object *obj) | ||
396 | +{ | ||
397 | + NPCM7xxADCState *s = NPCM7XX_ADC(obj); | ||
398 | + | ||
399 | + qemu_irq_lower(s->irq); | ||
400 | +} | ||
401 | + | ||
402 | +static void npcm7xx_adc_init(Object *obj) | ||
403 | +{ | ||
404 | + NPCM7xxADCState *s = NPCM7XX_ADC(obj); | ||
405 | + SysBusDevice *sbd = SYS_BUS_DEVICE(obj); | ||
406 | + int i; | ||
407 | + | ||
408 | + sysbus_init_irq(sbd, &s->irq); | ||
409 | + | ||
410 | + timer_init_ns(&s->conv_timer, QEMU_CLOCK_VIRTUAL, | ||
411 | + npcm7xx_adc_convert_done, s); | ||
412 | + memory_region_init_io(&s->iomem, obj, &npcm7xx_adc_ops, s, | ||
413 | + TYPE_NPCM7XX_ADC, 4 * KiB); | ||
414 | + sysbus_init_mmio(sbd, &s->iomem); | ||
415 | + s->clock = qdev_init_clock_in(DEVICE(s), "clock", NULL, NULL); | ||
416 | + | ||
417 | + for (i = 0; i < NPCM7XX_ADC_NUM_INPUTS; ++i) { | ||
418 | + object_property_add_uint32_ptr(obj, "adci[*]", | ||
419 | + &s->adci[i], OBJ_PROP_FLAG_WRITE); | ||
420 | + } | ||
421 | + object_property_add_uint32_ptr(obj, "vref", | ||
422 | + &s->vref, OBJ_PROP_FLAG_WRITE); | ||
423 | + npcm7xx_adc_calibrate(s); | ||
424 | +} | ||
425 | + | ||
426 | +static const VMStateDescription vmstate_npcm7xx_adc = { | ||
427 | + .name = "npcm7xx-adc", | ||
428 | + .version_id = 0, | ||
429 | + .minimum_version_id = 0, | ||
430 | + .fields = (VMStateField[]) { | ||
431 | + VMSTATE_TIMER(conv_timer, NPCM7xxADCState), | ||
432 | + VMSTATE_UINT32(con, NPCM7xxADCState), | ||
433 | + VMSTATE_UINT32(data, NPCM7xxADCState), | ||
434 | + VMSTATE_CLOCK(clock, NPCM7xxADCState), | ||
435 | + VMSTATE_UINT32_ARRAY(adci, NPCM7xxADCState, NPCM7XX_ADC_NUM_INPUTS), | ||
436 | + VMSTATE_UINT32(vref, NPCM7xxADCState), | ||
437 | + VMSTATE_UINT32(iref, NPCM7xxADCState), | ||
438 | + VMSTATE_UINT16_ARRAY(calibration_r_values, NPCM7xxADCState, | ||
439 | + NPCM7XX_ADC_NUM_CALIB), | ||
440 | + VMSTATE_END_OF_LIST(), | ||
441 | + }, | ||
442 | +}; | ||
443 | + | ||
444 | +static Property npcm7xx_timer_properties[] = { | ||
445 | + DEFINE_PROP_UINT32("iref", NPCM7xxADCState, iref, NPCM7XX_ADC_DEFAULT_IREF), | ||
446 | + DEFINE_PROP_END_OF_LIST(), | ||
447 | +}; | ||
448 | + | ||
449 | +static void npcm7xx_adc_class_init(ObjectClass *klass, void *data) | ||
450 | +{ | ||
451 | + ResettableClass *rc = RESETTABLE_CLASS(klass); | ||
452 | + DeviceClass *dc = DEVICE_CLASS(klass); | ||
453 | + | ||
454 | + dc->desc = "NPCM7xx ADC Module"; | ||
455 | + dc->vmsd = &vmstate_npcm7xx_adc; | ||
456 | + rc->phases.enter = npcm7xx_adc_enter_reset; | ||
457 | + rc->phases.hold = npcm7xx_adc_hold_reset; | ||
458 | + | ||
459 | + device_class_set_props(dc, npcm7xx_timer_properties); | ||
460 | +} | ||
461 | + | ||
462 | +static const TypeInfo npcm7xx_adc_info = { | ||
463 | + .name = TYPE_NPCM7XX_ADC, | ||
464 | + .parent = TYPE_SYS_BUS_DEVICE, | ||
465 | + .instance_size = sizeof(NPCM7xxADCState), | ||
466 | + .class_init = npcm7xx_adc_class_init, | ||
467 | + .instance_init = npcm7xx_adc_init, | ||
468 | +}; | ||
469 | + | ||
470 | +static void npcm7xx_adc_register_types(void) | ||
471 | +{ | ||
472 | + type_register_static(&npcm7xx_adc_info); | ||
473 | +} | ||
474 | + | ||
475 | +type_init(npcm7xx_adc_register_types); | ||
476 | diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c | ||
477 | index XXXXXXX..XXXXXXX 100644 | 93 | index XXXXXXX..XXXXXXX 100644 |
478 | --- a/hw/arm/npcm7xx.c | 94 | --- a/hw/arm/smmuv3.c |
479 | +++ b/hw/arm/npcm7xx.c | 95 | +++ b/hw/arm/smmuv3.c |
480 | @@ -XXX,XX +XXX,XX @@ | 96 | @@ -XXX,XX +XXX,XX @@ static void smmuv3_flush_config(SMMUDevice *sdev) |
481 | #define NPCM7XX_EHCI_BA (0xf0806000) | 97 | SMMUv3State *s = sdev->smmu; |
482 | #define NPCM7XX_OHCI_BA (0xf0807000) | 98 | SMMUState *bc = &s->smmu_state; |
483 | 99 | ||
484 | +/* ADC Module */ | 100 | - trace_smmuv3_config_cache_inv(smmu_get_sid(sdev)); |
485 | +#define NPCM7XX_ADC_BA (0xf000c000) | 101 | + trace_smmu_config_cache_inv(smmu_get_sid(sdev)); |
486 | + | 102 | g_hash_table_remove(bc->configs, sdev); |
487 | /* Internal AHB SRAM */ | ||
488 | #define NPCM7XX_RAM3_BA (0xc0008000) | ||
489 | #define NPCM7XX_RAM3_SZ (4 * KiB) | ||
490 | @@ -XXX,XX +XXX,XX @@ | ||
491 | #define NPCM7XX_ROM_BA (0xffff0000) | ||
492 | #define NPCM7XX_ROM_SZ (64 * KiB) | ||
493 | |||
494 | + | ||
495 | /* Clock configuration values to be fixed up when bypassing bootloader */ | ||
496 | |||
497 | /* Run PLL1 at 1600 MHz */ | ||
498 | @@ -XXX,XX +XXX,XX @@ | ||
499 | * interrupts. | ||
500 | */ | ||
501 | enum NPCM7xxInterrupt { | ||
502 | + NPCM7XX_ADC_IRQ = 0, | ||
503 | NPCM7XX_UART0_IRQ = 2, | ||
504 | NPCM7XX_UART1_IRQ, | ||
505 | NPCM7XX_UART2_IRQ, | ||
506 | @@ -XXX,XX +XXX,XX @@ static void npcm7xx_init_fuses(NPCM7xxState *s) | ||
507 | sizeof(value)); | ||
508 | } | 103 | } |
509 | 104 | ||
510 | +static void npcm7xx_write_adc_calibration(NPCM7xxState *s) | 105 | @@ -XXX,XX +XXX,XX @@ static void smmuv3_range_inval(SMMUState *s, Cmd *cmd, SMMUStage stage) |
511 | +{ | 106 | } |
512 | + /* Both ADC and the fuse array must have realized. */ | 107 | } |
513 | + QEMU_BUILD_BUG_ON(sizeof(s->adc.calibration_r_values) != 4); | 108 | |
514 | + npcm7xx_otp_array_write(&s->fuse_array, s->adc.calibration_r_values, | 109 | -static gboolean |
515 | + NPCM7XX_FUSE_ADC_CALIB, sizeof(s->adc.calibration_r_values)); | 110 | -smmuv3_invalidate_ste(gpointer key, gpointer value, gpointer user_data) |
516 | +} | 111 | -{ |
517 | + | 112 | - SMMUDevice *sdev = (SMMUDevice *)key; |
518 | static qemu_irq npcm7xx_irq(NPCM7xxState *s, int n) | 113 | - uint32_t sid = smmu_get_sid(sdev); |
114 | - SMMUSIDRange *sid_range = (SMMUSIDRange *)user_data; | ||
115 | - | ||
116 | - if (sid < sid_range->start || sid > sid_range->end) { | ||
117 | - return false; | ||
118 | - } | ||
119 | - trace_smmuv3_config_cache_inv(sid); | ||
120 | - return true; | ||
121 | -} | ||
122 | - | ||
123 | static int smmuv3_cmdq_consume(SMMUv3State *s) | ||
519 | { | 124 | { |
520 | return qdev_get_gpio_in(DEVICE(&s->a9mpcore), n); | 125 | SMMUState *bs = ARM_SMMU(s); |
521 | @@ -XXX,XX +XXX,XX @@ static void npcm7xx_init(Object *obj) | 126 | @@ -XXX,XX +XXX,XX @@ static int smmuv3_cmdq_consume(SMMUv3State *s) |
522 | TYPE_NPCM7XX_FUSE_ARRAY); | 127 | sid_range.end = sid_range.start + mask; |
523 | object_initialize_child(obj, "mc", &s->mc, TYPE_NPCM7XX_MC); | 128 | |
524 | object_initialize_child(obj, "rng", &s->rng, TYPE_NPCM7XX_RNG); | 129 | trace_smmuv3_cmdq_cfgi_ste_range(sid_range.start, sid_range.end); |
525 | + object_initialize_child(obj, "adc", &s->adc, TYPE_NPCM7XX_ADC); | 130 | - g_hash_table_foreach_remove(bs->configs, smmuv3_invalidate_ste, |
526 | 131 | - &sid_range); | |
527 | for (i = 0; i < ARRAY_SIZE(s->tim); i++) { | 132 | + smmu_configs_inv_sid_range(bs, sid_range); |
528 | object_initialize_child(obj, "tim[*]", &s->tim[i], TYPE_NPCM7XX_TIMER); | 133 | break; |
529 | @@ -XXX,XX +XXX,XX @@ static void npcm7xx_realize(DeviceState *dev, Error **errp) | 134 | } |
530 | sysbus_realize(SYS_BUS_DEVICE(&s->mc), &error_abort); | 135 | case SMMU_CMD_CFGI_CD: |
531 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->mc), 0, NPCM7XX_MC_BA); | 136 | diff --git a/hw/arm/trace-events b/hw/arm/trace-events |
532 | |||
533 | + /* ADC Modules. Cannot fail. */ | ||
534 | + qdev_connect_clock_in(DEVICE(&s->adc), "clock", qdev_get_clock_out( | ||
535 | + DEVICE(&s->clk), "adc-clock")); | ||
536 | + sysbus_realize(SYS_BUS_DEVICE(&s->adc), &error_abort); | ||
537 | + sysbus_mmio_map(SYS_BUS_DEVICE(&s->adc), 0, NPCM7XX_ADC_BA); | ||
538 | + sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0, | ||
539 | + npcm7xx_irq(s, NPCM7XX_ADC_IRQ)); | ||
540 | + npcm7xx_write_adc_calibration(s); | ||
541 | + | ||
542 | /* Timer Modules (TIM). Cannot fail. */ | ||
543 | QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_tim_addr) != ARRAY_SIZE(s->tim)); | ||
544 | for (i = 0; i < ARRAY_SIZE(s->tim); i++) { | ||
545 | @@ -XXX,XX +XXX,XX @@ static void npcm7xx_realize(DeviceState *dev, Error **errp) | ||
546 | create_unimplemented_device("npcm7xx.vdmx", 0xe0800000, 4 * KiB); | ||
547 | create_unimplemented_device("npcm7xx.pcierc", 0xe1000000, 64 * KiB); | ||
548 | create_unimplemented_device("npcm7xx.kcs", 0xf0007000, 4 * KiB); | ||
549 | - create_unimplemented_device("npcm7xx.adc", 0xf000c000, 4 * KiB); | ||
550 | create_unimplemented_device("npcm7xx.gfxi", 0xf000e000, 4 * KiB); | ||
551 | create_unimplemented_device("npcm7xx.gpio[0]", 0xf0010000, 4 * KiB); | ||
552 | create_unimplemented_device("npcm7xx.gpio[1]", 0xf0011000, 4 * KiB); | ||
553 | diff --git a/tests/qtest/npcm7xx_adc-test.c b/tests/qtest/npcm7xx_adc-test.c | ||
554 | new file mode 100644 | ||
555 | index XXXXXXX..XXXXXXX | ||
556 | --- /dev/null | ||
557 | +++ b/tests/qtest/npcm7xx_adc-test.c | ||
558 | @@ -XXX,XX +XXX,XX @@ | ||
559 | +/* | ||
560 | + * QTests for Nuvoton NPCM7xx ADCModules. | ||
561 | + * | ||
562 | + * Copyright 2020 Google LLC | ||
563 | + * | ||
564 | + * This program is free software; you can redistribute it and/or modify it | ||
565 | + * under the terms of the GNU General Public License as published by the | ||
566 | + * Free Software Foundation; either version 2 of the License, or | ||
567 | + * (at your option) any later version. | ||
568 | + * | ||
569 | + * This program is distributed in the hope that it will be useful, but WITHOUT | ||
570 | + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
571 | + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | ||
572 | + * for more details. | ||
573 | + */ | ||
574 | + | ||
575 | +#include "qemu/osdep.h" | ||
576 | +#include "qemu/bitops.h" | ||
577 | +#include "qemu/timer.h" | ||
578 | +#include "libqos/libqtest.h" | ||
579 | +#include "qapi/qmp/qdict.h" | ||
580 | + | ||
581 | +#define REF_HZ (25000000) | ||
582 | + | ||
583 | +#define CON_OFFSET 0x0 | ||
584 | +#define DATA_OFFSET 0x4 | ||
585 | + | ||
586 | +#define NUM_INPUTS 8 | ||
587 | +#define DEFAULT_IREF 2000000 | ||
588 | +#define CONV_CYCLES 20 | ||
589 | +#define RESET_CYCLES 10 | ||
590 | +#define R0_INPUT 500000 | ||
591 | +#define R1_INPUT 1500000 | ||
592 | +#define MAX_RESULT 1023 | ||
593 | + | ||
594 | +#define DEFAULT_CLKDIV 5 | ||
595 | + | ||
596 | +#define FUSE_ARRAY_BA 0xf018a000 | ||
597 | +#define FCTL_OFFSET 0x14 | ||
598 | +#define FST_OFFSET 0x0 | ||
599 | +#define FADDR_OFFSET 0x4 | ||
600 | +#define FDATA_OFFSET 0x8 | ||
601 | +#define ADC_CALIB_ADDR 24 | ||
602 | +#define FUSE_READ 0x2 | ||
603 | + | ||
604 | +/* Register field definitions. */ | ||
605 | +#define CON_MUX(rv) ((rv) << 24) | ||
606 | +#define CON_INT_EN BIT(21) | ||
607 | +#define CON_REFSEL BIT(19) | ||
608 | +#define CON_INT BIT(18) | ||
609 | +#define CON_EN BIT(17) | ||
610 | +#define CON_RST BIT(16) | ||
611 | +#define CON_CONV BIT(14) | ||
612 | +#define CON_DIV(rv) extract32(rv, 1, 8) | ||
613 | + | ||
614 | +#define FST_RDST BIT(1) | ||
615 | +#define FDATA_MASK 0xff | ||
616 | + | ||
617 | +#define MAX_ERROR 10000 | ||
618 | +#define MIN_CALIB_INPUT 100000 | ||
619 | +#define MAX_CALIB_INPUT 1800000 | ||
620 | + | ||
621 | +static const uint32_t input_list[] = { | ||
622 | + 100000, | ||
623 | + 500000, | ||
624 | + 1000000, | ||
625 | + 1500000, | ||
626 | + 1800000, | ||
627 | + 2000000, | ||
628 | +}; | ||
629 | + | ||
630 | +static const uint32_t vref_list[] = { | ||
631 | + 2000000, | ||
632 | + 2200000, | ||
633 | + 2500000, | ||
634 | +}; | ||
635 | + | ||
636 | +static const uint32_t iref_list[] = { | ||
637 | + 1800000, | ||
638 | + 1900000, | ||
639 | + 2000000, | ||
640 | + 2100000, | ||
641 | + 2200000, | ||
642 | +}; | ||
643 | + | ||
644 | +static const uint32_t div_list[] = {0, 1, 3, 7, 15}; | ||
645 | + | ||
646 | +typedef struct ADC { | ||
647 | + int irq; | ||
648 | + uint64_t base_addr; | ||
649 | +} ADC; | ||
650 | + | ||
651 | +ADC adc = { | ||
652 | + .irq = 0, | ||
653 | + .base_addr = 0xf000c000 | ||
654 | +}; | ||
655 | + | ||
656 | +static uint32_t adc_read_con(QTestState *qts, const ADC *adc) | ||
657 | +{ | ||
658 | + return qtest_readl(qts, adc->base_addr + CON_OFFSET); | ||
659 | +} | ||
660 | + | ||
661 | +static void adc_write_con(QTestState *qts, const ADC *adc, uint32_t value) | ||
662 | +{ | ||
663 | + qtest_writel(qts, adc->base_addr + CON_OFFSET, value); | ||
664 | +} | ||
665 | + | ||
666 | +static uint32_t adc_read_data(QTestState *qts, const ADC *adc) | ||
667 | +{ | ||
668 | + return qtest_readl(qts, adc->base_addr + DATA_OFFSET); | ||
669 | +} | ||
670 | + | ||
671 | +static uint32_t adc_calibrate(uint32_t measured, uint32_t *rv) | ||
672 | +{ | ||
673 | + return R0_INPUT + (R1_INPUT - R0_INPUT) * (int32_t)(measured - rv[0]) | ||
674 | + / (int32_t)(rv[1] - rv[0]); | ||
675 | +} | ||
676 | + | ||
677 | +static void adc_qom_set(QTestState *qts, const ADC *adc, | ||
678 | + const char *name, uint32_t value) | ||
679 | +{ | ||
680 | + QDict *response; | ||
681 | + const char *path = "/machine/soc/adc"; | ||
682 | + | ||
683 | + g_test_message("Setting properties %s of %s with value %u", | ||
684 | + name, path, value); | ||
685 | + response = qtest_qmp(qts, "{ 'execute': 'qom-set'," | ||
686 | + " 'arguments': { 'path': %s, 'property': %s, 'value': %u}}", | ||
687 | + path, name, value); | ||
688 | + /* The qom set message returns successfully. */ | ||
689 | + g_assert_true(qdict_haskey(response, "return")); | ||
690 | +} | ||
691 | + | ||
692 | +static void adc_write_input(QTestState *qts, const ADC *adc, | ||
693 | + uint32_t index, uint32_t value) | ||
694 | +{ | ||
695 | + char name[100]; | ||
696 | + | ||
697 | + sprintf(name, "adci[%u]", index); | ||
698 | + adc_qom_set(qts, adc, name, value); | ||
699 | +} | ||
700 | + | ||
701 | +static void adc_write_vref(QTestState *qts, const ADC *adc, uint32_t value) | ||
702 | +{ | ||
703 | + adc_qom_set(qts, adc, "vref", value); | ||
704 | +} | ||
705 | + | ||
706 | +static uint32_t adc_calculate_output(uint32_t input, uint32_t ref) | ||
707 | +{ | ||
708 | + uint32_t output; | ||
709 | + | ||
710 | + g_assert_cmpuint(input, <=, ref); | ||
711 | + output = (input * (MAX_RESULT + 1)) / ref; | ||
712 | + if (output > MAX_RESULT) { | ||
713 | + output = MAX_RESULT; | ||
714 | + } | ||
715 | + | ||
716 | + return output; | ||
717 | +} | ||
718 | + | ||
719 | +static uint32_t adc_prescaler(QTestState *qts, const ADC *adc) | ||
720 | +{ | ||
721 | + uint32_t div = extract32(adc_read_con(qts, adc), 1, 8); | ||
722 | + | ||
723 | + return 2 * (div + 1); | ||
724 | +} | ||
725 | + | ||
726 | +static int64_t adc_calculate_steps(uint32_t cycles, uint32_t prescale, | ||
727 | + uint32_t clkdiv) | ||
728 | +{ | ||
729 | + return (NANOSECONDS_PER_SECOND / (REF_HZ >> clkdiv)) * cycles * prescale; | ||
730 | +} | ||
731 | + | ||
732 | +static void adc_wait_conv_finished(QTestState *qts, const ADC *adc, | ||
733 | + uint32_t clkdiv) | ||
734 | +{ | ||
735 | + uint32_t prescaler = adc_prescaler(qts, adc); | ||
736 | + | ||
737 | + /* | ||
738 | + * ADC should takes roughly 20 cycles to convert one sample. So we assert it | ||
739 | + * should take 10~30 cycles here. | ||
740 | + */ | ||
741 | + qtest_clock_step(qts, adc_calculate_steps(CONV_CYCLES / 2, prescaler, | ||
742 | + clkdiv)); | ||
743 | + /* ADC is still converting. */ | ||
744 | + g_assert_true(adc_read_con(qts, adc) & CON_CONV); | ||
745 | + qtest_clock_step(qts, adc_calculate_steps(CONV_CYCLES, prescaler, clkdiv)); | ||
746 | + /* ADC has finished conversion. */ | ||
747 | + g_assert_false(adc_read_con(qts, adc) & CON_CONV); | ||
748 | +} | ||
749 | + | ||
750 | +/* Check ADC can be reset to default value. */ | ||
751 | +static void test_init(gconstpointer adc_p) | ||
752 | +{ | ||
753 | + const ADC *adc = adc_p; | ||
754 | + | ||
755 | + QTestState *qts = qtest_init("-machine quanta-gsj"); | ||
756 | + adc_write_con(qts, adc, CON_REFSEL | CON_INT); | ||
757 | + g_assert_cmphex(adc_read_con(qts, adc), ==, CON_REFSEL); | ||
758 | + qtest_quit(qts); | ||
759 | +} | ||
760 | + | ||
761 | +/* Check ADC can convert from an internal reference. */ | ||
762 | +static void test_convert_internal(gconstpointer adc_p) | ||
763 | +{ | ||
764 | + const ADC *adc = adc_p; | ||
765 | + uint32_t index, input, output, expected_output; | ||
766 | + QTestState *qts = qtest_init("-machine quanta-gsj"); | ||
767 | + qtest_irq_intercept_in(qts, "/machine/soc/a9mpcore/gic"); | ||
768 | + | ||
769 | + for (index = 0; index < NUM_INPUTS; ++index) { | ||
770 | + for (size_t i = 0; i < ARRAY_SIZE(input_list); ++i) { | ||
771 | + input = input_list[i]; | ||
772 | + expected_output = adc_calculate_output(input, DEFAULT_IREF); | ||
773 | + | ||
774 | + adc_write_input(qts, adc, index, input); | ||
775 | + adc_write_con(qts, adc, CON_MUX(index) | CON_REFSEL | CON_INT | | ||
776 | + CON_EN | CON_CONV); | ||
777 | + adc_wait_conv_finished(qts, adc, DEFAULT_CLKDIV); | ||
778 | + g_assert_cmphex(adc_read_con(qts, adc), ==, CON_MUX(index) | | ||
779 | + CON_REFSEL | CON_EN); | ||
780 | + g_assert_false(qtest_get_irq(qts, adc->irq)); | ||
781 | + output = adc_read_data(qts, adc); | ||
782 | + g_assert_cmpuint(output, ==, expected_output); | ||
783 | + } | ||
784 | + } | ||
785 | + | ||
786 | + qtest_quit(qts); | ||
787 | +} | ||
788 | + | ||
789 | +/* Check ADC can convert from an external reference. */ | ||
790 | +static void test_convert_external(gconstpointer adc_p) | ||
791 | +{ | ||
792 | + const ADC *adc = adc_p; | ||
793 | + uint32_t index, input, vref, output, expected_output; | ||
794 | + QTestState *qts = qtest_init("-machine quanta-gsj"); | ||
795 | + qtest_irq_intercept_in(qts, "/machine/soc/a9mpcore/gic"); | ||
796 | + | ||
797 | + for (index = 0; index < NUM_INPUTS; ++index) { | ||
798 | + for (size_t i = 0; i < ARRAY_SIZE(input_list); ++i) { | ||
799 | + for (size_t j = 0; j < ARRAY_SIZE(vref_list); ++j) { | ||
800 | + input = input_list[i]; | ||
801 | + vref = vref_list[j]; | ||
802 | + expected_output = adc_calculate_output(input, vref); | ||
803 | + | ||
804 | + adc_write_input(qts, adc, index, input); | ||
805 | + adc_write_vref(qts, adc, vref); | ||
806 | + adc_write_con(qts, adc, CON_MUX(index) | CON_INT | CON_EN | | ||
807 | + CON_CONV); | ||
808 | + adc_wait_conv_finished(qts, adc, DEFAULT_CLKDIV); | ||
809 | + g_assert_cmphex(adc_read_con(qts, adc), ==, | ||
810 | + CON_MUX(index) | CON_EN); | ||
811 | + g_assert_false(qtest_get_irq(qts, adc->irq)); | ||
812 | + output = adc_read_data(qts, adc); | ||
813 | + g_assert_cmpuint(output, ==, expected_output); | ||
814 | + } | ||
815 | + } | ||
816 | + } | ||
817 | + | ||
818 | + qtest_quit(qts); | ||
819 | +} | ||
820 | + | ||
821 | +/* Check ADC interrupt files if and only if CON_INT_EN is set. */ | ||
822 | +static void test_interrupt(gconstpointer adc_p) | ||
823 | +{ | ||
824 | + const ADC *adc = adc_p; | ||
825 | + uint32_t index, input, output, expected_output; | ||
826 | + QTestState *qts = qtest_init("-machine quanta-gsj"); | ||
827 | + | ||
828 | + index = 1; | ||
829 | + input = input_list[1]; | ||
830 | + expected_output = adc_calculate_output(input, DEFAULT_IREF); | ||
831 | + | ||
832 | + qtest_irq_intercept_in(qts, "/machine/soc/a9mpcore/gic"); | ||
833 | + adc_write_input(qts, adc, index, input); | ||
834 | + g_assert_false(qtest_get_irq(qts, adc->irq)); | ||
835 | + adc_write_con(qts, adc, CON_MUX(index) | CON_INT_EN | CON_REFSEL | CON_INT | ||
836 | + | CON_EN | CON_CONV); | ||
837 | + adc_wait_conv_finished(qts, adc, DEFAULT_CLKDIV); | ||
838 | + g_assert_cmphex(adc_read_con(qts, adc), ==, CON_MUX(index) | CON_INT_EN | ||
839 | + | CON_REFSEL | CON_INT | CON_EN); | ||
840 | + g_assert_true(qtest_get_irq(qts, adc->irq)); | ||
841 | + output = adc_read_data(qts, adc); | ||
842 | + g_assert_cmpuint(output, ==, expected_output); | ||
843 | + | ||
844 | + qtest_quit(qts); | ||
845 | +} | ||
846 | + | ||
847 | +/* Check ADC is reset after setting ADC_RST for 10 ADC cycles. */ | ||
848 | +static void test_reset(gconstpointer adc_p) | ||
849 | +{ | ||
850 | + const ADC *adc = adc_p; | ||
851 | + QTestState *qts = qtest_init("-machine quanta-gsj"); | ||
852 | + | ||
853 | + for (size_t i = 0; i < ARRAY_SIZE(div_list); ++i) { | ||
854 | + uint32_t div = div_list[i]; | ||
855 | + | ||
856 | + adc_write_con(qts, adc, CON_INT | CON_EN | CON_RST | CON_DIV(div)); | ||
857 | + qtest_clock_step(qts, adc_calculate_steps(RESET_CYCLES, | ||
858 | + adc_prescaler(qts, adc), DEFAULT_CLKDIV)); | ||
859 | + g_assert_false(adc_read_con(qts, adc) & CON_EN); | ||
860 | + } | ||
861 | + qtest_quit(qts); | ||
862 | +} | ||
863 | + | ||
864 | +/* Check ADC Calibration works as desired. */ | ||
865 | +static void test_calibrate(gconstpointer adc_p) | ||
866 | +{ | ||
867 | + int i, j; | ||
868 | + const ADC *adc = adc_p; | ||
869 | + | ||
870 | + for (j = 0; j < ARRAY_SIZE(iref_list); ++j) { | ||
871 | + uint32_t iref = iref_list[j]; | ||
872 | + uint32_t expected_rv[] = { | ||
873 | + adc_calculate_output(R0_INPUT, iref), | ||
874 | + adc_calculate_output(R1_INPUT, iref), | ||
875 | + }; | ||
876 | + char buf[100]; | ||
877 | + QTestState *qts; | ||
878 | + | ||
879 | + sprintf(buf, "-machine quanta-gsj -global npcm7xx-adc.iref=%u", iref); | ||
880 | + qts = qtest_init(buf); | ||
881 | + | ||
882 | + /* Check the converted value is correct using the calibration value. */ | ||
883 | + for (i = 0; i < ARRAY_SIZE(input_list); ++i) { | ||
884 | + uint32_t input; | ||
885 | + uint32_t output; | ||
886 | + uint32_t expected_output; | ||
887 | + uint32_t calibrated_voltage; | ||
888 | + uint32_t index = 0; | ||
889 | + | ||
890 | + input = input_list[i]; | ||
891 | + /* Calibration only works for input range 0.1V ~ 1.8V. */ | ||
892 | + if (input < MIN_CALIB_INPUT || input > MAX_CALIB_INPUT) { | ||
893 | + continue; | ||
894 | + } | ||
895 | + expected_output = adc_calculate_output(input, iref); | ||
896 | + | ||
897 | + adc_write_input(qts, adc, index, input); | ||
898 | + adc_write_con(qts, adc, CON_MUX(index) | CON_REFSEL | CON_INT | | ||
899 | + CON_EN | CON_CONV); | ||
900 | + adc_wait_conv_finished(qts, adc, DEFAULT_CLKDIV); | ||
901 | + g_assert_cmphex(adc_read_con(qts, adc), ==, | ||
902 | + CON_REFSEL | CON_MUX(index) | CON_EN); | ||
903 | + output = adc_read_data(qts, adc); | ||
904 | + g_assert_cmpuint(output, ==, expected_output); | ||
905 | + | ||
906 | + calibrated_voltage = adc_calibrate(output, expected_rv); | ||
907 | + g_assert_cmpuint(calibrated_voltage, >, input - MAX_ERROR); | ||
908 | + g_assert_cmpuint(calibrated_voltage, <, input + MAX_ERROR); | ||
909 | + } | ||
910 | + | ||
911 | + qtest_quit(qts); | ||
912 | + } | ||
913 | +} | ||
914 | + | ||
915 | +static void adc_add_test(const char *name, const ADC* wd, | ||
916 | + GTestDataFunc fn) | ||
917 | +{ | ||
918 | + g_autofree char *full_name = g_strdup_printf("npcm7xx_adc/%s", name); | ||
919 | + qtest_add_data_func(full_name, wd, fn); | ||
920 | +} | ||
921 | +#define add_test(name, td) adc_add_test(#name, td, test_##name) | ||
922 | + | ||
923 | +int main(int argc, char **argv) | ||
924 | +{ | ||
925 | + g_test_init(&argc, &argv, NULL); | ||
926 | + | ||
927 | + add_test(init, &adc); | ||
928 | + add_test(convert_internal, &adc); | ||
929 | + add_test(convert_external, &adc); | ||
930 | + add_test(interrupt, &adc); | ||
931 | + add_test(reset, &adc); | ||
932 | + add_test(calibrate, &adc); | ||
933 | + | ||
934 | + return g_test_run(); | ||
935 | +} | ||
936 | diff --git a/hw/adc/meson.build b/hw/adc/meson.build | ||
937 | index XXXXXXX..XXXXXXX 100644 | 137 | index XXXXXXX..XXXXXXX 100644 |
938 | --- a/hw/adc/meson.build | 138 | --- a/hw/arm/trace-events |
939 | +++ b/hw/adc/meson.build | 139 | +++ b/hw/arm/trace-events |
940 | @@ -1 +1,2 @@ | 140 | @@ -XXX,XX +XXX,XX @@ smmu_iotlb_inv_asid_vmid(int asid, int vmid) "IOTLB invalidate asid=%d vmid=%d" |
941 | softmmu_ss.add(when: 'CONFIG_STM32F2XX_ADC', if_true: files('stm32f2xx_adc.c')) | 141 | smmu_iotlb_inv_vmid(int vmid) "IOTLB invalidate vmid=%d" |
942 | +softmmu_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx_adc.c')) | 142 | smmu_iotlb_inv_vmid_s1(int vmid) "IOTLB invalidate vmid=%d" |
943 | diff --git a/hw/adc/trace-events b/hw/adc/trace-events | 143 | smmu_iotlb_inv_iova(int asid, uint64_t addr) "IOTLB invalidate asid=%d addr=0x%"PRIx64 |
944 | new file mode 100644 | 144 | +smmu_configs_inv_sid_range(uint32_t start, uint32_t end) "Config cache INV SID range from 0x%x to 0x%x" |
945 | index XXXXXXX..XXXXXXX | 145 | +smmu_config_cache_inv(uint32_t sid) "Config cache INV for sid=0x%x" |
946 | --- /dev/null | 146 | smmu_inv_notifiers_mr(const char *name) "iommu mr=%s" |
947 | +++ b/hw/adc/trace-events | 147 | smmu_iotlb_lookup_hit(int asid, int vmid, uint64_t addr, uint32_t hit, uint32_t miss, uint32_t p) "IOTLB cache HIT asid=%d vmid=%d addr=0x%"PRIx64" hit=%d miss=%d hit rate=%d" |
948 | @@ -XXX,XX +XXX,XX @@ | 148 | smmu_iotlb_lookup_miss(int asid, int vmid, uint64_t addr, uint32_t hit, uint32_t miss, uint32_t p) "IOTLB cache MISS asid=%d vmid=%d addr=0x%"PRIx64" hit=%d miss=%d hit rate=%d" |
949 | +# See docs/devel/tracing.txt for syntax documentation. | 149 | @@ -XXX,XX +XXX,XX @@ smmuv3_cmdq_tlbi_nh(int vmid) "vmid=%d" |
950 | + | 150 | smmuv3_cmdq_tlbi_nsnh(void) "" |
951 | +# npcm7xx_adc.c | 151 | smmuv3_cmdq_tlbi_nh_asid(int asid) "asid=%d" |
952 | +npcm7xx_adc_read(const char *id, uint64_t offset, uint32_t value) " %s offset: 0x%04" PRIx64 " value 0x%04" PRIx32 | 152 | smmuv3_cmdq_tlbi_s12_vmid(int vmid) "vmid=%d" |
953 | +npcm7xx_adc_write(const char *id, uint64_t offset, uint32_t value) "%s offset: 0x%04" PRIx64 " value 0x%04" PRIx32 | 153 | -smmuv3_config_cache_inv(uint32_t sid) "Config cache INV for sid=0x%x" |
954 | diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build | 154 | smmuv3_notify_flag_add(const char *iommu) "ADD SMMUNotifier node for iommu mr=%s" |
955 | index XXXXXXX..XXXXXXX 100644 | 155 | smmuv3_notify_flag_del(const char *iommu) "DEL SMMUNotifier node for iommu mr=%s" |
956 | --- a/tests/qtest/meson.build | 156 | smmuv3_inv_notifiers_iova(const char *name, int asid, int vmid, uint64_t iova, uint8_t tg, uint64_t num_pages, int stage) "iommu mr=%s asid=%d vmid=%d iova=0x%"PRIx64" tg=%d num_pages=0x%"PRIx64" stage=%d" |
957 | +++ b/tests/qtest/meson.build | ||
958 | @@ -XXX,XX +XXX,XX @@ qtests_sparc64 = \ | ||
959 | ['prom-env-test', 'boot-serial-test'] | ||
960 | |||
961 | qtests_npcm7xx = \ | ||
962 | - ['npcm7xx_gpio-test', | ||
963 | + ['npcm7xx_adc-test', | ||
964 | + 'npcm7xx_gpio-test', | ||
965 | 'npcm7xx_rng-test', | ||
966 | 'npcm7xx_timer-test', | ||
967 | 'npcm7xx_watchdog_timer-test'] | ||
968 | -- | 157 | -- |
969 | 2.20.1 | 158 | 2.43.0 |
970 | |||
971 | diff view generated by jsdifflib |
1 | From: Roman Bolshakov <r.bolshakov@yadro.com> | 1 | From: Keith Packard <keithp@keithp.com> |
---|---|---|---|
2 | 2 | ||
3 | QEMU documentation can't be opened if QEMU is run from build tree | 3 | The documentation says the vector is at 0xffffff80, instead of the |
4 | because executables are placed in the top of build tree after conversion | 4 | previous value of 0xffffffc0. That value must have been a bug because |
5 | to meson. | 5 | the standard vector values (20, 21, 23, 25, 30) were all |
6 | past the end of the array. | ||
6 | 7 | ||
7 | Signed-off-by: Roman Bolshakov <r.bolshakov@yadro.com> | 8 | Signed-off-by: Keith Packard <keithp@keithp.com> |
8 | Reported-by: Peter Maydell <peter.maydell@linaro.org> | ||
9 | Message-id: 20210108213815.64678-1-r.bolshakov@yadro.com | ||
10 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
12 | --- | 11 | --- |
13 | ui/cocoa.m | 2 +- | 12 | target/rx/helper.c | 2 +- |
14 | 1 file changed, 1 insertion(+), 1 deletion(-) | 13 | 1 file changed, 1 insertion(+), 1 deletion(-) |
15 | 14 | ||
16 | diff --git a/ui/cocoa.m b/ui/cocoa.m | 15 | diff --git a/target/rx/helper.c b/target/rx/helper.c |
17 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
18 | --- a/ui/cocoa.m | 17 | --- a/target/rx/helper.c |
19 | +++ b/ui/cocoa.m | 18 | +++ b/target/rx/helper.c |
20 | @@ -XXX,XX +XXX,XX @@ QemuCocoaView *cocoaView; | 19 | @@ -XXX,XX +XXX,XX @@ void rx_cpu_do_interrupt(CPUState *cs) |
21 | - (void) openDocumentation: (NSString *) filename | 20 | cpu_stl_data(env, env->isp, env->pc); |
22 | { | 21 | |
23 | /* Where to look for local files */ | 22 | if (vec < 0x100) { |
24 | - NSString *path_array[] = {@"../share/doc/qemu/", @"../doc/qemu/", @"../docs/"}; | 23 | - env->pc = cpu_ldl_data(env, 0xffffffc0 + vec * 4); |
25 | + NSString *path_array[] = {@"../share/doc/qemu/", @"../doc/qemu/", @"docs/"}; | 24 | + env->pc = cpu_ldl_data(env, 0xffffff80 + vec * 4); |
26 | NSString *full_file_path; | 25 | } else { |
27 | 26 | env->pc = cpu_ldl_data(env, env->intb + (vec & 0xff) * 4); | |
28 | /* iterate thru the possible paths until the file is found */ | 27 | } |
29 | -- | 28 | -- |
30 | 2.20.1 | 29 | 2.43.0 |
31 | |||
32 | diff view generated by jsdifflib |
1 | From: Rémi Denis-Courmont <remi.denis.courmont@huawei.com> | 1 | From: Keith Packard <keithp@keithp.com> |
---|---|---|---|
2 | 2 | ||
3 | Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com> | 3 | Functions which modify TCG globals must not be marked TCG_CALL_NO_WG, |
4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 4 | as that tells the optimizer that TCG global values already loaded in |
5 | machine registers are still valid, and so any changes which these | ||
6 | helpers make to the CPU state may be ignored. | ||
7 | |||
8 | The target/rx code chooses to put (among other things) all the PSW | ||
9 | bits and also ACC into globals, so the NO_WG flag on various | ||
10 | functions that touch the PSW or ACC is incorrect and must be removed. | ||
11 | This includes all the floating point helper functions, because | ||
12 | update_fpsw() will update PSW Z and S. | ||
13 | |||
14 | Signed-off-by: Keith Packard <keithp@keithp.com> | ||
15 | [PMM: Clarified commit message] | ||
16 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 17 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
6 | --- | 18 | --- |
7 | target/arm/cpu64.c | 1 + | 19 | target/rx/helper.h | 34 +++++++++++++++++----------------- |
8 | 1 file changed, 1 insertion(+) | 20 | 1 file changed, 17 insertions(+), 17 deletions(-) |
9 | 21 | ||
10 | diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c | 22 | diff --git a/target/rx/helper.h b/target/rx/helper.h |
11 | index XXXXXXX..XXXXXXX 100644 | 23 | index XXXXXXX..XXXXXXX 100644 |
12 | --- a/target/arm/cpu64.c | 24 | --- a/target/rx/helper.h |
13 | +++ b/target/arm/cpu64.c | 25 | +++ b/target/rx/helper.h |
14 | @@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj) | 26 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_1(raise_privilege_violation, noreturn, env) |
15 | t = cpu->isar.id_aa64mmfr2; | 27 | DEF_HELPER_1(wait, noreturn, env) |
16 | t = FIELD_DP64(t, ID_AA64MMFR2, UAO, 1); | 28 | DEF_HELPER_2(rxint, noreturn, env, i32) |
17 | t = FIELD_DP64(t, ID_AA64MMFR2, CNP, 1); /* TTCNP */ | 29 | DEF_HELPER_1(rxbrk, noreturn, env) |
18 | + t = FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* TTST */ | 30 | -DEF_HELPER_FLAGS_3(fadd, TCG_CALL_NO_WG, f32, env, f32, f32) |
19 | cpu->isar.id_aa64mmfr2 = t; | 31 | -DEF_HELPER_FLAGS_3(fsub, TCG_CALL_NO_WG, f32, env, f32, f32) |
20 | 32 | -DEF_HELPER_FLAGS_3(fmul, TCG_CALL_NO_WG, f32, env, f32, f32) | |
21 | /* Replicate the same data to the 32-bit id registers. */ | 33 | -DEF_HELPER_FLAGS_3(fdiv, TCG_CALL_NO_WG, f32, env, f32, f32) |
34 | -DEF_HELPER_FLAGS_3(fcmp, TCG_CALL_NO_WG, void, env, f32, f32) | ||
35 | -DEF_HELPER_FLAGS_2(ftoi, TCG_CALL_NO_WG, i32, env, f32) | ||
36 | -DEF_HELPER_FLAGS_2(round, TCG_CALL_NO_WG, i32, env, f32) | ||
37 | -DEF_HELPER_FLAGS_2(itof, TCG_CALL_NO_WG, f32, env, i32) | ||
38 | +DEF_HELPER_3(fadd, f32, env, f32, f32) | ||
39 | +DEF_HELPER_3(fsub, f32, env, f32, f32) | ||
40 | +DEF_HELPER_3(fmul, f32, env, f32, f32) | ||
41 | +DEF_HELPER_3(fdiv, f32, env, f32, f32) | ||
42 | +DEF_HELPER_3(fcmp, void, env, f32, f32) | ||
43 | +DEF_HELPER_2(ftoi, i32, env, f32) | ||
44 | +DEF_HELPER_2(round, i32, env, f32) | ||
45 | +DEF_HELPER_2(itof, f32, env, i32) | ||
46 | DEF_HELPER_2(set_fpsw, void, env, i32) | ||
47 | -DEF_HELPER_FLAGS_2(racw, TCG_CALL_NO_WG, void, env, i32) | ||
48 | -DEF_HELPER_FLAGS_2(set_psw_rte, TCG_CALL_NO_WG, void, env, i32) | ||
49 | -DEF_HELPER_FLAGS_2(set_psw, TCG_CALL_NO_WG, void, env, i32) | ||
50 | +DEF_HELPER_2(racw, void, env, i32) | ||
51 | +DEF_HELPER_2(set_psw_rte, void, env, i32) | ||
52 | +DEF_HELPER_2(set_psw, void, env, i32) | ||
53 | DEF_HELPER_1(pack_psw, i32, env) | ||
54 | -DEF_HELPER_FLAGS_3(div, TCG_CALL_NO_WG, i32, env, i32, i32) | ||
55 | -DEF_HELPER_FLAGS_3(divu, TCG_CALL_NO_WG, i32, env, i32, i32) | ||
56 | -DEF_HELPER_FLAGS_1(scmpu, TCG_CALL_NO_WG, void, env) | ||
57 | +DEF_HELPER_3(div, i32, env, i32, i32) | ||
58 | +DEF_HELPER_3(divu, i32, env, i32, i32) | ||
59 | +DEF_HELPER_1(scmpu, void, env) | ||
60 | DEF_HELPER_1(smovu, void, env) | ||
61 | DEF_HELPER_1(smovf, void, env) | ||
62 | DEF_HELPER_1(smovb, void, env) | ||
63 | DEF_HELPER_2(sstr, void, env, i32) | ||
64 | -DEF_HELPER_FLAGS_2(swhile, TCG_CALL_NO_WG, void, env, i32) | ||
65 | -DEF_HELPER_FLAGS_2(suntil, TCG_CALL_NO_WG, void, env, i32) | ||
66 | -DEF_HELPER_FLAGS_2(rmpa, TCG_CALL_NO_WG, void, env, i32) | ||
67 | +DEF_HELPER_2(swhile, void, env, i32) | ||
68 | +DEF_HELPER_2(suntil, void, env, i32) | ||
69 | +DEF_HELPER_2(rmpa, void, env, i32) | ||
70 | DEF_HELPER_1(satr, void, env) | ||
22 | -- | 71 | -- |
23 | 2.20.1 | 72 | 2.43.0 |
24 | |||
25 | diff view generated by jsdifflib |