1 | Arm queue; not huge but I figured I might as well send it out since | 1 | Hi; here's the first arm pullreq for 9.1. |
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2 | I've been doing code review today and there's no queue of unprocessed | 2 | |
3 | pullreqs... | 3 | This includes the reset method function signature change, so it has |
4 | some chance of compile failures due to merge conflicts if some other | ||
5 | pullreq added a device reset method and that pullreq got applied | ||
6 | before this one. If so, the changes needed to fix those up can be | ||
7 | created by running the spatch rune described in the commit message of | ||
8 | the "hw, target: Add ResetType argument to hold and exit phase | ||
9 | methods" commit. | ||
4 | 10 | ||
5 | thanks | 11 | thanks |
6 | -- PMM | 12 | -- PMM |
7 | 13 | ||
8 | The following changes since commit b3f846c59d8405bb87c551187721fc92ff2f1b92: | 14 | The following changes since commit 5da72194df36535d773c8bdc951529ecd5e31707: |
9 | 15 | ||
10 | Merge remote-tracking branch 'remotes/huth-gitlab/tags/pull-request-2021-01-11v2' into staging (2021-01-11 15:15:35 +0000) | 16 | Merge tag 'pull-tcg-20240424' of https://gitlab.com/rth7680/qemu into staging (2024-04-24 15:51:49 -0700) |
11 | 17 | ||
12 | are available in the Git repository at: | 18 | are available in the Git repository at: |
13 | 19 | ||
14 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210112 | 20 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20240425 |
15 | 21 | ||
16 | for you to fetch changes up to 19d131395ccaf503db21dadd8257e6dc9fc1d7de: | 22 | for you to fetch changes up to 214652da123e3821657a64691ee556281e9f6238: |
17 | 23 | ||
18 | ui/cocoa: Fix openFile: deprecation on Big Sur (2021-01-12 11:38:37 +0000) | 24 | tests/qtest: Add tests for the STM32L4x5 USART (2024-04-25 10:21:59 +0100) |
19 | 25 | ||
20 | ---------------------------------------------------------------- | 26 | ---------------------------------------------------------------- |
21 | target-arm queue: | 27 | target-arm queue: |
22 | * arm: Support emulation of ARMv8.4-TTST extension | 28 | * Implement FEAT_NMI and NMI support in the GICv3 |
23 | * arm: Update cpu.h ID register field definitions | 29 | * hw/dma: avoid apparent overflow in soc_dma_set_request |
24 | * arm: Fix breakage of XScale instruction emulation | 30 | * linux-user/flatload.c: Remove unused bFLT shared-library and ZFLAT code |
25 | * hw/net/lan9118: Fix RX Status FIFO PEEK value | 31 | * Add ResetType argument to Resettable hold and exit phase methods |
26 | * npcm7xx: Add ADC and PWM emulation | 32 | * Add RESET_TYPE_SNAPSHOT_LOAD ResetType |
27 | * ui/cocoa: Make "open docs" help menu entry work again when binary | 33 | * Implement STM32L4x5 USART |
28 | is run from the build tree | ||
29 | * ui/cocoa: Fix openFile: deprecation on Big Sur | ||
30 | * docs: Add qemu-storage-daemon(1) manpage to meson.build | ||
31 | * docs: Build and install all the docs in a single manual | ||
32 | 34 | ||
33 | ---------------------------------------------------------------- | 35 | ---------------------------------------------------------------- |
34 | Hao Wu (6): | 36 | Anastasia Belova (1): |
35 | hw/misc: Add clock converter in NPCM7XX CLK module | 37 | hw/dma: avoid apparent overflow in soc_dma_set_request |
36 | hw/timer: Refactor NPCM7XX Timer to use CLK clock | 38 | |
37 | hw/adc: Add an ADC module for NPCM7XX | 39 | Arnaud Minier (5): |
38 | hw/misc: Add a PWM module for NPCM7XX | 40 | hw/char: Implement STM32L4x5 USART skeleton |
39 | hw/misc: Add QTest for NPCM7XX PWM Module | 41 | hw/char/stm32l4x5_usart: Enable serial read and write |
40 | hw/*: Use type casting for SysBusDevice in NPCM7XX | 42 | hw/char/stm32l4x5_usart: Add options for serial parameters setting |
41 | 43 | hw/arm: Add the USART to the stm32l4x5 SoC | |
42 | Leif Lindholm (6): | 44 | tests/qtest: Add tests for the STM32L4x5 USART |
43 | target/arm: fix typo in cpu.h ID_AA64PFR1 field name | 45 | |
44 | target/arm: make ARMCPU.clidr 64-bit | 46 | Jinjie Ruan (22): |
45 | target/arm: make ARMCPU.ctr 64-bit | 47 | target/arm: Handle HCR_EL2 accesses for bits introduced with FEAT_NMI |
46 | target/arm: add descriptions of CLIDR_EL1, CCSIDR_EL1, CTR_EL0 to cpu.h | 48 | target/arm: Add PSTATE.ALLINT |
47 | target/arm: add aarch64 ID register fields to cpu.h | 49 | target/arm: Add support for FEAT_NMI, Non-maskable Interrupt |
48 | target/arm: add aarch32 ID register fields to cpu.h | 50 | target/arm: Implement ALLINT MSR (immediate) |
49 | 51 | target/arm: Support MSR access to ALLINT | |
50 | Peter Maydell (5): | 52 | target/arm: Add support for Non-maskable Interrupt |
51 | docs: Add qemu-storage-daemon(1) manpage to meson.build | 53 | target/arm: Add support for NMI in arm_phys_excp_target_el() |
52 | docs: Build and install all the docs in a single manual | 54 | target/arm: Handle IS/FS in ISR_EL1 for NMI, VINMI and VFNMI |
53 | target/arm: Don't decode insns in the XScale/iWMMXt space as cp insns | 55 | target/arm: Handle PSTATE.ALLINT on taking an exception |
54 | hw/net/lan9118: Fix RX Status FIFO PEEK value | 56 | hw/intc/arm_gicv3: Add external IRQ lines for NMI |
55 | hw/net/lan9118: Add symbolic constants for register offsets | 57 | hw/arm/virt: Wire NMI and VINMI irq lines from GIC to CPU |
56 | 58 | target/arm: Handle NMI in arm_cpu_do_interrupt_aarch64() | |
57 | Roman Bolshakov (2): | 59 | hw/intc/arm_gicv3: Add has-nmi property to GICv3 device |
58 | ui/cocoa: Update path to docs in build tree | 60 | hw/intc/arm_gicv3_kvm: Not set has-nmi=true for the KVM GICv3 |
59 | ui/cocoa: Fix openFile: deprecation on Big Sur | 61 | hw/intc/arm_gicv3: Add irq non-maskable property |
60 | 62 | hw/intc/arm_gicv3_redist: Implement GICR_INMIR0 | |
61 | Rémi Denis-Courmont (2): | 63 | hw/intc/arm_gicv3: Implement GICD_INMIR |
62 | target/arm: ARMv8.4-TTST extension | 64 | hw/intc/arm_gicv3: Implement NMI interrupt priority |
63 | target/arm: enable Small Translation tables in max CPU | 65 | hw/intc/arm_gicv3: Report the NMI interrupt in gicv3_cpuif_update() |
64 | 66 | hw/intc/arm_gicv3: Report the VINMI interrupt | |
65 | docs/conf.py | 46 ++- | 67 | target/arm: Add FEAT_NMI to max |
66 | docs/devel/conf.py | 15 - | 68 | hw/arm/virt: Enable NMI support in the GIC if the CPU has FEAT_NMI |
67 | docs/index.html.in | 17 - | 69 | |
68 | docs/interop/conf.py | 28 -- | 70 | Peter Maydell (9): |
69 | docs/meson.build | 65 ++-- | 71 | hw/intc/arm_gicv3: Add NMI handling CPU interface registers |
70 | docs/specs/conf.py | 16 - | 72 | hw/intc/arm_gicv3: Handle icv_nmiar1_read() for icc_nmiar1_read() |
71 | docs/system/arm/nuvoton.rst | 4 +- | 73 | linux-user/flatload.c: Remove unused bFLT shared-library and ZFLAT code |
72 | docs/system/conf.py | 28 -- | 74 | hw/misc: Don't special case RESET_TYPE_COLD in npcm7xx_clk, gcr |
73 | docs/tools/conf.py | 37 -- | 75 | allwinner-i2c, adm1272: Use device_cold_reset() for software-triggered reset |
74 | docs/user/conf.py | 15 - | 76 | scripts/coccinelle: New script to add ResetType to hold and exit phases |
75 | meson.build | 1 + | 77 | hw, target: Add ResetType argument to hold and exit phase methods |
76 | hw/adc/trace.h | 1 + | 78 | docs/devel/reset: Update to new API for hold and exit phase methods |
77 | include/hw/adc/npcm7xx_adc.h | 69 ++++ | 79 | reset: Add RESET_TYPE_SNAPSHOT_LOAD |
78 | include/hw/arm/npcm7xx.h | 4 + | 80 | |
79 | include/hw/misc/npcm7xx_clk.h | 146 ++++++- | 81 | MAINTAINERS | 1 + |
80 | include/hw/misc/npcm7xx_pwm.h | 105 +++++ | 82 | docs/devel/reset.rst | 25 +- |
81 | include/hw/timer/npcm7xx_timer.h | 1 + | 83 | docs/system/arm/b-l475e-iot01a.rst | 2 +- |
82 | target/arm/cpu.h | 85 ++++- | 84 | docs/system/arm/emulation.rst | 1 + |
83 | hw/adc/npcm7xx_adc.c | 301 +++++++++++++++ | 85 | scripts/coccinelle/reset-type.cocci | 133 ++++++++ |
84 | hw/arm/npcm7xx.c | 55 ++- | 86 | hw/intc/gicv3_internal.h | 13 + |
85 | hw/arm/npcm7xx_boards.c | 2 +- | 87 | include/hw/arm/stm32l4x5_soc.h | 7 + |
86 | hw/mem/npcm7xx_mc.c | 2 +- | 88 | include/hw/char/stm32l4x5_usart.h | 67 ++++ |
87 | hw/misc/npcm7xx_clk.c | 807 ++++++++++++++++++++++++++++++++++++++- | 89 | include/hw/intc/arm_gic_common.h | 2 + |
88 | hw/misc/npcm7xx_gcr.c | 2 +- | 90 | include/hw/intc/arm_gicv3_common.h | 14 + |
89 | hw/misc/npcm7xx_pwm.c | 550 ++++++++++++++++++++++++++ | 91 | include/hw/resettable.h | 5 +- |
90 | hw/misc/npcm7xx_rng.c | 2 +- | 92 | linux-user/flat.h | 5 +- |
91 | hw/net/lan9118.c | 26 +- | 93 | target/arm/cpu-features.h | 5 + |
92 | hw/nvram/npcm7xx_otp.c | 2 +- | 94 | target/arm/cpu-qom.h | 5 +- |
93 | hw/ssi/npcm7xx_fiu.c | 2 +- | 95 | target/arm/cpu.h | 9 + |
94 | hw/timer/npcm7xx_timer.c | 39 +- | 96 | target/arm/internals.h | 21 ++ |
95 | target/arm/cpu64.c | 1 + | 97 | target/arm/tcg/helper-a64.h | 1 + |
96 | target/arm/helper.c | 15 +- | 98 | target/arm/tcg/a64.decode | 1 + |
97 | target/arm/translate.c | 7 + | 99 | hw/adc/npcm7xx_adc.c | 2 +- |
98 | tests/qtest/npcm7xx_adc-test.c | 377 ++++++++++++++++++ | 100 | hw/arm/pxa2xx_pic.c | 2 +- |
99 | tests/qtest/npcm7xx_pwm-test.c | 490 ++++++++++++++++++++++++ | 101 | hw/arm/smmu-common.c | 2 +- |
100 | hw/adc/meson.build | 1 + | 102 | hw/arm/smmuv3.c | 4 +- |
101 | hw/adc/trace-events | 5 + | 103 | hw/arm/stellaris.c | 10 +- |
102 | hw/misc/meson.build | 1 + | 104 | hw/arm/stm32l4x5_soc.c | 83 ++++- |
103 | hw/misc/trace-events | 6 + | 105 | hw/arm/virt.c | 29 +- |
104 | tests/qtest/meson.build | 4 +- | 106 | hw/audio/asc.c | 2 +- |
105 | ui/cocoa.m | 7 +- | 107 | hw/char/cadence_uart.c | 2 +- |
106 | 41 files changed, 3124 insertions(+), 263 deletions(-) | 108 | hw/char/sifive_uart.c | 2 +- |
107 | delete mode 100644 docs/devel/conf.py | 109 | hw/char/stm32l4x5_usart.c | 637 ++++++++++++++++++++++++++++++++++++ |
108 | delete mode 100644 docs/index.html.in | 110 | hw/core/cpu-common.c | 2 +- |
109 | delete mode 100644 docs/interop/conf.py | 111 | hw/core/qdev.c | 4 +- |
110 | delete mode 100644 docs/specs/conf.py | 112 | hw/core/reset.c | 17 +- |
111 | delete mode 100644 docs/system/conf.py | 113 | hw/core/resettable.c | 8 +- |
112 | delete mode 100644 docs/tools/conf.py | 114 | hw/display/virtio-vga.c | 4 +- |
113 | delete mode 100644 docs/user/conf.py | 115 | hw/dma/soc_dma.c | 4 +- |
114 | create mode 100644 hw/adc/trace.h | 116 | hw/gpio/npcm7xx_gpio.c | 2 +- |
115 | create mode 100644 include/hw/adc/npcm7xx_adc.h | 117 | hw/gpio/pl061.c | 2 +- |
116 | create mode 100644 include/hw/misc/npcm7xx_pwm.h | 118 | hw/gpio/stm32l4x5_gpio.c | 2 +- |
117 | create mode 100644 hw/adc/npcm7xx_adc.c | 119 | hw/hyperv/vmbus.c | 2 +- |
118 | create mode 100644 hw/misc/npcm7xx_pwm.c | 120 | hw/i2c/allwinner-i2c.c | 5 +- |
119 | create mode 100644 tests/qtest/npcm7xx_adc-test.c | 121 | hw/i2c/npcm7xx_smbus.c | 2 +- |
120 | create mode 100644 tests/qtest/npcm7xx_pwm-test.c | 122 | hw/input/adb.c | 2 +- |
121 | create mode 100644 hw/adc/trace-events | 123 | hw/input/ps2.c | 12 +- |
122 | 124 | hw/intc/arm_gic_common.c | 2 +- | |
125 | hw/intc/arm_gic_kvm.c | 4 +- | ||
126 | hw/intc/arm_gicv3.c | 67 +++- | ||
127 | hw/intc/arm_gicv3_common.c | 50 ++- | ||
128 | hw/intc/arm_gicv3_cpuif.c | 268 ++++++++++++++- | ||
129 | hw/intc/arm_gicv3_dist.c | 36 ++ | ||
130 | hw/intc/arm_gicv3_its.c | 4 +- | ||
131 | hw/intc/arm_gicv3_its_common.c | 2 +- | ||
132 | hw/intc/arm_gicv3_its_kvm.c | 4 +- | ||
133 | hw/intc/arm_gicv3_kvm.c | 9 +- | ||
134 | hw/intc/arm_gicv3_redist.c | 22 ++ | ||
135 | hw/intc/xics.c | 2 +- | ||
136 | hw/m68k/q800-glue.c | 2 +- | ||
137 | hw/misc/djmemc.c | 2 +- | ||
138 | hw/misc/iosb.c | 2 +- | ||
139 | hw/misc/mac_via.c | 8 +- | ||
140 | hw/misc/macio/cuda.c | 4 +- | ||
141 | hw/misc/macio/pmu.c | 4 +- | ||
142 | hw/misc/mos6522.c | 2 +- | ||
143 | hw/misc/npcm7xx_clk.c | 13 +- | ||
144 | hw/misc/npcm7xx_gcr.c | 12 +- | ||
145 | hw/misc/npcm7xx_mft.c | 2 +- | ||
146 | hw/misc/npcm7xx_pwm.c | 2 +- | ||
147 | hw/misc/stm32l4x5_exti.c | 2 +- | ||
148 | hw/misc/stm32l4x5_rcc.c | 10 +- | ||
149 | hw/misc/stm32l4x5_syscfg.c | 2 +- | ||
150 | hw/misc/xlnx-versal-cframe-reg.c | 2 +- | ||
151 | hw/misc/xlnx-versal-crl.c | 2 +- | ||
152 | hw/misc/xlnx-versal-pmc-iou-slcr.c | 2 +- | ||
153 | hw/misc/xlnx-versal-trng.c | 2 +- | ||
154 | hw/misc/xlnx-versal-xramc.c | 2 +- | ||
155 | hw/misc/xlnx-zynqmp-apu-ctrl.c | 2 +- | ||
156 | hw/misc/xlnx-zynqmp-crf.c | 2 +- | ||
157 | hw/misc/zynq_slcr.c | 4 +- | ||
158 | hw/net/can/xlnx-zynqmp-can.c | 2 +- | ||
159 | hw/net/e1000.c | 2 +- | ||
160 | hw/net/e1000e.c | 2 +- | ||
161 | hw/net/igb.c | 2 +- | ||
162 | hw/net/igbvf.c | 2 +- | ||
163 | hw/nvram/xlnx-bbram.c | 2 +- | ||
164 | hw/nvram/xlnx-versal-efuse-ctrl.c | 2 +- | ||
165 | hw/nvram/xlnx-zynqmp-efuse.c | 2 +- | ||
166 | hw/pci-bridge/cxl_root_port.c | 4 +- | ||
167 | hw/pci-bridge/pcie_root_port.c | 2 +- | ||
168 | hw/pci-host/bonito.c | 2 +- | ||
169 | hw/pci-host/pnv_phb.c | 4 +- | ||
170 | hw/pci-host/pnv_phb3_msi.c | 4 +- | ||
171 | hw/pci/pci.c | 4 +- | ||
172 | hw/rtc/mc146818rtc.c | 2 +- | ||
173 | hw/s390x/css-bridge.c | 2 +- | ||
174 | hw/sensor/adm1266.c | 2 +- | ||
175 | hw/sensor/adm1272.c | 4 +- | ||
176 | hw/sensor/isl_pmbus_vr.c | 10 +- | ||
177 | hw/sensor/max31785.c | 2 +- | ||
178 | hw/sensor/max34451.c | 2 +- | ||
179 | hw/ssi/npcm7xx_fiu.c | 2 +- | ||
180 | hw/timer/etraxfs_timer.c | 2 +- | ||
181 | hw/timer/npcm7xx_timer.c | 2 +- | ||
182 | hw/usb/hcd-dwc2.c | 8 +- | ||
183 | hw/usb/xlnx-versal-usb2-ctrl-regs.c | 2 +- | ||
184 | hw/virtio/virtio-pci.c | 2 +- | ||
185 | linux-user/flatload.c | 293 +---------------- | ||
186 | target/arm/cpu.c | 151 ++++++++- | ||
187 | target/arm/helper.c | 101 +++++- | ||
188 | target/arm/tcg/cpu64.c | 1 + | ||
189 | target/arm/tcg/helper-a64.c | 16 +- | ||
190 | target/arm/tcg/translate-a64.c | 19 ++ | ||
191 | target/avr/cpu.c | 4 +- | ||
192 | target/cris/cpu.c | 4 +- | ||
193 | target/hexagon/cpu.c | 4 +- | ||
194 | target/i386/cpu.c | 4 +- | ||
195 | target/loongarch/cpu.c | 4 +- | ||
196 | target/m68k/cpu.c | 4 +- | ||
197 | target/microblaze/cpu.c | 4 +- | ||
198 | target/mips/cpu.c | 4 +- | ||
199 | target/openrisc/cpu.c | 4 +- | ||
200 | target/ppc/cpu_init.c | 4 +- | ||
201 | target/riscv/cpu.c | 4 +- | ||
202 | target/rx/cpu.c | 4 +- | ||
203 | target/sh4/cpu.c | 4 +- | ||
204 | target/sparc/cpu.c | 4 +- | ||
205 | target/tricore/cpu.c | 4 +- | ||
206 | target/xtensa/cpu.c | 4 +- | ||
207 | tests/qtest/stm32l4x5_usart-test.c | 315 ++++++++++++++++++ | ||
208 | hw/arm/Kconfig | 1 + | ||
209 | hw/char/Kconfig | 3 + | ||
210 | hw/char/meson.build | 1 + | ||
211 | hw/char/trace-events | 12 + | ||
212 | hw/intc/trace-events | 2 + | ||
213 | tests/qtest/meson.build | 4 +- | ||
214 | 133 files changed, 2239 insertions(+), 537 deletions(-) | ||
215 | create mode 100644 scripts/coccinelle/reset-type.cocci | ||
216 | create mode 100644 include/hw/char/stm32l4x5_usart.h | ||
217 | create mode 100644 hw/char/stm32l4x5_usart.c | ||
218 | create mode 100644 tests/qtest/stm32l4x5_usart-test.c | diff view generated by jsdifflib |
1 | From: Rémi Denis-Courmont <remi.denis.courmont@huawei.com> | 1 | From: Jinjie Ruan <ruanjinjie@huawei.com> |
---|---|---|---|
2 | 2 | ||
3 | This adds for the Small Translation tables extension in AArch64 state. | 3 | FEAT_NMI defines another three new bits in HCRX_EL2: TALLINT, HCRX_VINMI and |
4 | HCRX_VFNMI. When the feature is enabled, allow these bits to be written in | ||
5 | HCRX_EL2. | ||
4 | 6 | ||
5 | Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com> | 7 | Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com> |
6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
9 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
10 | Message-id: 20240407081733.3231820-2-ruanjinjie@huawei.com | ||
7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
8 | --- | 12 | --- |
9 | target/arm/cpu.h | 5 +++++ | 13 | target/arm/cpu-features.h | 5 +++++ |
10 | target/arm/helper.c | 15 +++++++++++++-- | 14 | target/arm/helper.c | 8 +++++++- |
11 | 2 files changed, 18 insertions(+), 2 deletions(-) | 15 | 2 files changed, 12 insertions(+), 1 deletion(-) |
12 | 16 | ||
13 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | 17 | diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h |
14 | index XXXXXXX..XXXXXXX 100644 | 18 | index XXXXXXX..XXXXXXX 100644 |
15 | --- a/target/arm/cpu.h | 19 | --- a/target/arm/cpu-features.h |
16 | +++ b/target/arm/cpu.h | 20 | +++ b/target/arm/cpu-features.h |
17 | @@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_uao(const ARMISARegisters *id) | 21 | @@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_sme(const ARMISARegisters *id) |
18 | return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, UAO) != 0; | 22 | return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, SME) != 0; |
19 | } | 23 | } |
20 | 24 | ||
21 | +static inline bool isar_feature_aa64_st(const ARMISARegisters *id) | 25 | +static inline bool isar_feature_aa64_nmi(const ARMISARegisters *id) |
22 | +{ | 26 | +{ |
23 | + return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, ST) != 0; | 27 | + return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, NMI) != 0; |
24 | +} | 28 | +} |
25 | + | 29 | + |
26 | static inline bool isar_feature_aa64_bti(const ARMISARegisters *id) | 30 | static inline bool isar_feature_aa64_tgran4_lpa2(const ARMISARegisters *id) |
27 | { | 31 | { |
28 | return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) != 0; | 32 | return FIELD_SEX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4) >= 1; |
29 | diff --git a/target/arm/helper.c b/target/arm/helper.c | 33 | diff --git a/target/arm/helper.c b/target/arm/helper.c |
30 | index XXXXXXX..XXXXXXX 100644 | 34 | index XXXXXXX..XXXXXXX 100644 |
31 | --- a/target/arm/helper.c | 35 | --- a/target/arm/helper.c |
32 | +++ b/target/arm/helper.c | 36 | +++ b/target/arm/helper.c |
33 | @@ -XXX,XX +XXX,XX @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, | 37 | @@ -XXX,XX +XXX,XX @@ bool el_is_in_host(CPUARMState *env, int el) |
38 | static void hcrx_write(CPUARMState *env, const ARMCPRegInfo *ri, | ||
39 | uint64_t value) | ||
34 | { | 40 | { |
35 | uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr; | 41 | + ARMCPU *cpu = env_archcpu(env); |
36 | bool epd, hpd, using16k, using64k; | 42 | uint64_t valid_mask = 0; |
37 | - int select, tsz, tbi; | 43 | |
38 | + int select, tsz, tbi, max_tsz; | 44 | /* FEAT_MOPS adds MSCEn and MCE2 */ |
39 | 45 | - if (cpu_isar_feature(aa64_mops, env_archcpu(env))) { | |
40 | if (!regime_has_2_ranges(mmu_idx)) { | 46 | + if (cpu_isar_feature(aa64_mops, cpu)) { |
41 | select = 0; | 47 | valid_mask |= HCRX_MSCEN | HCRX_MCE2; |
42 | @@ -XXX,XX +XXX,XX @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, | ||
43 | hpd = extract64(tcr, 42, 1); | ||
44 | } | ||
45 | } | 48 | } |
46 | - tsz = MIN(tsz, 39); /* TODO: ARMv8.4-TTST */ | 49 | |
47 | + | 50 | + /* FEAT_NMI adds TALLINT, VINMI and VFNMI */ |
48 | + if (cpu_isar_feature(aa64_st, env_archcpu(env))) { | 51 | + if (cpu_isar_feature(aa64_nmi, cpu)) { |
49 | + max_tsz = 48 - using64k; | 52 | + valid_mask |= HCRX_TALLINT | HCRX_VINMI | HCRX_VFNMI; |
50 | + } else { | ||
51 | + max_tsz = 39; | ||
52 | + } | 53 | + } |
53 | + | 54 | + |
54 | + tsz = MIN(tsz, max_tsz); | 55 | /* Clear RES0 bits. */ |
55 | tsz = MAX(tsz, 16); /* TODO: ARMv8.2-LVA */ | 56 | env->cp15.hcrx_el2 = value & valid_mask; |
56 | 57 | } | |
57 | /* Present TBI as a composite with TBID. */ | ||
58 | @@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, | ||
59 | if (!aarch64 || stride == 9) { | ||
60 | /* AArch32 or 4KB pages */ | ||
61 | startlevel = 2 - sl0; | ||
62 | + | ||
63 | + if (cpu_isar_feature(aa64_st, cpu)) { | ||
64 | + startlevel &= 3; | ||
65 | + } | ||
66 | } else { | ||
67 | /* 16KB or 64KB pages */ | ||
68 | startlevel = 3 - sl0; | ||
69 | -- | 58 | -- |
70 | 2.20.1 | 59 | 2.34.1 |
71 | |||
72 | diff view generated by jsdifflib |
1 | From: Leif Lindholm <leif@nuviainc.com> | 1 | From: Jinjie Ruan <ruanjinjie@huawei.com> |
---|---|---|---|
2 | 2 | ||
3 | Add entries present in ARM DDI 0487F.c (August 2020). | 3 | When PSTATE.ALLINT is set, an IRQ or FIQ interrupt that is targeted to |
4 | ELx, with or without superpriority is masked. As Richard suggested, place | ||
5 | ALLINT bit in PSTATE in env->pstate. | ||
4 | 6 | ||
5 | Signed-off-by: Leif Lindholm <leif@nuviainc.com> | 7 | In the pseudocode, AArch64.ExceptionReturn() calls SetPSTATEFromPSR(), which |
8 | treats PSTATE.ALLINT as one of the bits which are reinstated from SPSR to | ||
9 | PSTATE regardless of whether this is an illegal exception return or not. So | ||
10 | handle PSTATE.ALLINT the same way as PSTATE.DAIF in the illegal_return exit | ||
11 | path of the exception_return helper. With the change, exception entry and | ||
12 | return are automatically handled. | ||
13 | |||
14 | Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com> | ||
15 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 16 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
7 | Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com> | 17 | Message-id: 20240407081733.3231820-3-ruanjinjie@huawei.com |
8 | Message-id: 20210108185154.8108-7-leif@nuviainc.com | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 18 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
10 | --- | 19 | --- |
11 | target/arm/cpu.h | 28 ++++++++++++++++++++++++++++ | 20 | target/arm/cpu.h | 1 + |
12 | 1 file changed, 28 insertions(+) | 21 | target/arm/tcg/helper-a64.c | 4 ++-- |
22 | 2 files changed, 3 insertions(+), 2 deletions(-) | ||
13 | 23 | ||
14 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | 24 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h |
15 | index XXXXXXX..XXXXXXX 100644 | 25 | index XXXXXXX..XXXXXXX 100644 |
16 | --- a/target/arm/cpu.h | 26 | --- a/target/arm/cpu.h |
17 | +++ b/target/arm/cpu.h | 27 | +++ b/target/arm/cpu.h |
18 | @@ -XXX,XX +XXX,XX @@ FIELD(ID_ISAR6, DP, 4, 4) | 28 | @@ -XXX,XX +XXX,XX @@ void pmu_init(ARMCPU *cpu); |
19 | FIELD(ID_ISAR6, FHM, 8, 4) | 29 | #define PSTATE_D (1U << 9) |
20 | FIELD(ID_ISAR6, SB, 12, 4) | 30 | #define PSTATE_BTYPE (3U << 10) |
21 | FIELD(ID_ISAR6, SPECRES, 16, 4) | 31 | #define PSTATE_SSBS (1U << 12) |
22 | +FIELD(ID_ISAR6, BF16, 20, 4) | 32 | +#define PSTATE_ALLINT (1U << 13) |
23 | +FIELD(ID_ISAR6, I8MM, 24, 4) | 33 | #define PSTATE_IL (1U << 20) |
24 | 34 | #define PSTATE_SS (1U << 21) | |
25 | FIELD(ID_MMFR0, VMSA, 0, 4) | 35 | #define PSTATE_PAN (1U << 22) |
26 | FIELD(ID_MMFR0, PMSA, 4, 4) | 36 | diff --git a/target/arm/tcg/helper-a64.c b/target/arm/tcg/helper-a64.c |
27 | @@ -XXX,XX +XXX,XX @@ FIELD(ID_MMFR0, AUXREG, 20, 4) | 37 | index XXXXXXX..XXXXXXX 100644 |
28 | FIELD(ID_MMFR0, FCSE, 24, 4) | 38 | --- a/target/arm/tcg/helper-a64.c |
29 | FIELD(ID_MMFR0, INNERSHR, 28, 4) | 39 | +++ b/target/arm/tcg/helper-a64.c |
30 | 40 | @@ -XXX,XX +XXX,XX @@ illegal_return: | |
31 | +FIELD(ID_MMFR1, L1HVDVA, 0, 4) | 41 | */ |
32 | +FIELD(ID_MMFR1, L1UNIVA, 4, 4) | 42 | env->pstate |= PSTATE_IL; |
33 | +FIELD(ID_MMFR1, L1HVDSW, 8, 4) | 43 | env->pc = new_pc; |
34 | +FIELD(ID_MMFR1, L1UNISW, 12, 4) | 44 | - spsr &= PSTATE_NZCV | PSTATE_DAIF; |
35 | +FIELD(ID_MMFR1, L1HVD, 16, 4) | 45 | - spsr |= pstate_read(env) & ~(PSTATE_NZCV | PSTATE_DAIF); |
36 | +FIELD(ID_MMFR1, L1UNI, 20, 4) | 46 | + spsr &= PSTATE_NZCV | PSTATE_DAIF | PSTATE_ALLINT; |
37 | +FIELD(ID_MMFR1, L1TSTCLN, 24, 4) | 47 | + spsr |= pstate_read(env) & ~(PSTATE_NZCV | PSTATE_DAIF | PSTATE_ALLINT); |
38 | +FIELD(ID_MMFR1, BPRED, 28, 4) | 48 | pstate_write(env, spsr); |
39 | + | 49 | if (!arm_singlestep_active(env)) { |
40 | +FIELD(ID_MMFR2, L1HVDFG, 0, 4) | 50 | env->pstate &= ~PSTATE_SS; |
41 | +FIELD(ID_MMFR2, L1HVDBG, 4, 4) | ||
42 | +FIELD(ID_MMFR2, L1HVDRNG, 8, 4) | ||
43 | +FIELD(ID_MMFR2, HVDTLB, 12, 4) | ||
44 | +FIELD(ID_MMFR2, UNITLB, 16, 4) | ||
45 | +FIELD(ID_MMFR2, MEMBARR, 20, 4) | ||
46 | +FIELD(ID_MMFR2, WFISTALL, 24, 4) | ||
47 | +FIELD(ID_MMFR2, HWACCFLG, 28, 4) | ||
48 | + | ||
49 | FIELD(ID_MMFR3, CMAINTVA, 0, 4) | ||
50 | FIELD(ID_MMFR3, CMAINTSW, 4, 4) | ||
51 | FIELD(ID_MMFR3, BPMAINT, 8, 4) | ||
52 | @@ -XXX,XX +XXX,XX @@ FIELD(ID_MMFR4, LSM, 20, 4) | ||
53 | FIELD(ID_MMFR4, CCIDX, 24, 4) | ||
54 | FIELD(ID_MMFR4, EVT, 28, 4) | ||
55 | |||
56 | +FIELD(ID_MMFR5, ETS, 0, 4) | ||
57 | + | ||
58 | FIELD(ID_PFR0, STATE0, 0, 4) | ||
59 | FIELD(ID_PFR0, STATE1, 4, 4) | ||
60 | FIELD(ID_PFR0, STATE2, 8, 4) | ||
61 | @@ -XXX,XX +XXX,XX @@ FIELD(ID_PFR1, SEC_FRAC, 20, 4) | ||
62 | FIELD(ID_PFR1, VIRT_FRAC, 24, 4) | ||
63 | FIELD(ID_PFR1, GIC, 28, 4) | ||
64 | |||
65 | +FIELD(ID_PFR2, CSV3, 0, 4) | ||
66 | +FIELD(ID_PFR2, SSBS, 4, 4) | ||
67 | +FIELD(ID_PFR2, RAS_FRAC, 8, 4) | ||
68 | + | ||
69 | FIELD(ID_AA64ISAR0, AES, 4, 4) | ||
70 | FIELD(ID_AA64ISAR0, SHA1, 8, 4) | ||
71 | FIELD(ID_AA64ISAR0, SHA2, 12, 4) | ||
72 | @@ -XXX,XX +XXX,XX @@ FIELD(ID_DFR0, MPROFDBG, 20, 4) | ||
73 | FIELD(ID_DFR0, PERFMON, 24, 4) | ||
74 | FIELD(ID_DFR0, TRACEFILT, 28, 4) | ||
75 | |||
76 | +FIELD(ID_DFR1, MTPMU, 0, 4) | ||
77 | + | ||
78 | FIELD(DBGDIDR, SE_IMP, 12, 1) | ||
79 | FIELD(DBGDIDR, NSUHD_IMP, 14, 1) | ||
80 | FIELD(DBGDIDR, VERSION, 16, 4) | ||
81 | -- | 51 | -- |
82 | 2.20.1 | 52 | 2.34.1 |
83 | |||
84 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Jinjie Ruan <ruanjinjie@huawei.com> | ||
1 | 2 | ||
3 | Add support for FEAT_NMI. NMI (FEAT_NMI) is an mandatory feature in | ||
4 | ARMv8.8-A and ARM v9.3-A. | ||
5 | |||
6 | Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com> | ||
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
9 | Message-id: 20240407081733.3231820-4-ruanjinjie@huawei.com | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
11 | --- | ||
12 | target/arm/internals.h | 3 +++ | ||
13 | 1 file changed, 3 insertions(+) | ||
14 | |||
15 | diff --git a/target/arm/internals.h b/target/arm/internals.h | ||
16 | index XXXXXXX..XXXXXXX 100644 | ||
17 | --- a/target/arm/internals.h | ||
18 | +++ b/target/arm/internals.h | ||
19 | @@ -XXX,XX +XXX,XX @@ static inline uint32_t aarch64_pstate_valid_mask(const ARMISARegisters *id) | ||
20 | if (isar_feature_aa64_mte(id)) { | ||
21 | valid |= PSTATE_TCO; | ||
22 | } | ||
23 | + if (isar_feature_aa64_nmi(id)) { | ||
24 | + valid |= PSTATE_ALLINT; | ||
25 | + } | ||
26 | |||
27 | return valid; | ||
28 | } | ||
29 | -- | ||
30 | 2.34.1 | diff view generated by jsdifflib |
1 | In commit cd8be50e58f63413c0 we converted the A32 coprocessor | 1 | From: Jinjie Ruan <ruanjinjie@huawei.com> |
---|---|---|---|
2 | insns to decodetree. This accidentally broke XScale/iWMMXt insns, | ||
3 | because it moved the handling of "cp insns which are handled | ||
4 | by looking up the cp register in the hashtable" from after the | ||
5 | call to the legacy disas_xscale_insn() decode to before it, | ||
6 | with the result that all XScale/iWMMXt insns now UNDEF. | ||
7 | 2 | ||
8 | Update valid_cp() so that it knows that on XScale cp 0 and 1 | 3 | Add ALLINT MSR (immediate) to decodetree, in which the CRm is 0b000x. The |
9 | are not standard coprocessor instructions; this will cause | 4 | EL0 check is necessary to ALLINT, and the EL1 check is necessary when |
10 | the decodetree trans_ functions to ignore them, so that | 5 | imm == 1. So implement it inline for EL2/3, or EL1 with imm==0. Avoid the |
11 | execution will correctly get through to the legacy decode again. | 6 | unconditional write to pc and use raise_exception_ra to unwind. |
12 | 7 | ||
13 | Cc: qemu-stable@nongnu.org | 8 | Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com> |
14 | Reported-by: Guenter Roeck <linux@roeck-us.net> | 9 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
10 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
11 | Message-id: 20240407081733.3231820-5-ruanjinjie@huawei.com | ||
15 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
16 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
17 | Tested-by: Guenter Roeck <linux@roeck-us.net> | ||
18 | Message-id: 20210108195157.32067-1-peter.maydell@linaro.org | ||
19 | --- | 13 | --- |
20 | target/arm/translate.c | 7 +++++++ | 14 | target/arm/tcg/helper-a64.h | 1 + |
21 | 1 file changed, 7 insertions(+) | 15 | target/arm/tcg/a64.decode | 1 + |
16 | target/arm/tcg/helper-a64.c | 12 ++++++++++++ | ||
17 | target/arm/tcg/translate-a64.c | 19 +++++++++++++++++++ | ||
18 | 4 files changed, 33 insertions(+) | ||
22 | 19 | ||
23 | diff --git a/target/arm/translate.c b/target/arm/translate.c | 20 | diff --git a/target/arm/tcg/helper-a64.h b/target/arm/tcg/helper-a64.h |
24 | index XXXXXXX..XXXXXXX 100644 | 21 | index XXXXXXX..XXXXXXX 100644 |
25 | --- a/target/arm/translate.c | 22 | --- a/target/arm/tcg/helper-a64.h |
26 | +++ b/target/arm/translate.c | 23 | +++ b/target/arm/tcg/helper-a64.h |
27 | @@ -XXX,XX +XXX,XX @@ static bool valid_cp(DisasContext *s, int cp) | 24 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_1(rbit64, TCG_CALL_NO_RWG_SE, i64, i64) |
28 | * only cp14 and cp15 are valid, and other values aren't considered | 25 | DEF_HELPER_2(msr_i_spsel, void, env, i32) |
29 | * to be in the coprocessor-instruction space at all. v8M still | 26 | DEF_HELPER_2(msr_i_daifset, void, env, i32) |
30 | * permits coprocessors 0..7. | 27 | DEF_HELPER_2(msr_i_daifclear, void, env, i32) |
31 | + * For XScale, we must not decode the XScale cp0, cp1 space as | 28 | +DEF_HELPER_1(msr_set_allint_el1, void, env) |
32 | + * a standard coprocessor insn, because we want to fall through to | 29 | DEF_HELPER_3(vfp_cmph_a64, i64, f16, f16, ptr) |
33 | + * the legacy disas_xscale_insn() decoder after decodetree is done. | 30 | DEF_HELPER_3(vfp_cmpeh_a64, i64, f16, f16, ptr) |
34 | */ | 31 | DEF_HELPER_3(vfp_cmps_a64, i64, f32, f32, ptr) |
35 | + if (arm_dc_feature(s, ARM_FEATURE_XSCALE) && (cp == 0 || cp == 1)) { | 32 | diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode |
33 | index XXXXXXX..XXXXXXX 100644 | ||
34 | --- a/target/arm/tcg/a64.decode | ||
35 | +++ b/target/arm/tcg/a64.decode | ||
36 | @@ -XXX,XX +XXX,XX @@ MSR_i_DIT 1101 0101 0000 0 011 0100 .... 010 11111 @msr_i | ||
37 | MSR_i_TCO 1101 0101 0000 0 011 0100 .... 100 11111 @msr_i | ||
38 | MSR_i_DAIFSET 1101 0101 0000 0 011 0100 .... 110 11111 @msr_i | ||
39 | MSR_i_DAIFCLEAR 1101 0101 0000 0 011 0100 .... 111 11111 @msr_i | ||
40 | +MSR_i_ALLINT 1101 0101 0000 0 001 0100 000 imm:1 000 11111 | ||
41 | MSR_i_SVCR 1101 0101 0000 0 011 0100 0 mask:2 imm:1 011 11111 | ||
42 | |||
43 | # MRS, MSR (register), SYS, SYSL. These are all essentially the | ||
44 | diff --git a/target/arm/tcg/helper-a64.c b/target/arm/tcg/helper-a64.c | ||
45 | index XXXXXXX..XXXXXXX 100644 | ||
46 | --- a/target/arm/tcg/helper-a64.c | ||
47 | +++ b/target/arm/tcg/helper-a64.c | ||
48 | @@ -XXX,XX +XXX,XX @@ void HELPER(msr_i_spsel)(CPUARMState *env, uint32_t imm) | ||
49 | update_spsel(env, imm); | ||
50 | } | ||
51 | |||
52 | +void HELPER(msr_set_allint_el1)(CPUARMState *env) | ||
53 | +{ | ||
54 | + /* ALLINT update to PSTATE. */ | ||
55 | + if (arm_hcrx_el2_eff(env) & HCRX_TALLINT) { | ||
56 | + raise_exception_ra(env, EXCP_UDEF, | ||
57 | + syn_aa64_sysregtrap(0, 1, 0, 4, 1, 0x1f, 0), 2, | ||
58 | + GETPC()); | ||
59 | + } | ||
60 | + | ||
61 | + env->pstate |= PSTATE_ALLINT; | ||
62 | +} | ||
63 | + | ||
64 | static void daif_check(CPUARMState *env, uint32_t op, | ||
65 | uint32_t imm, uintptr_t ra) | ||
66 | { | ||
67 | diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c | ||
68 | index XXXXXXX..XXXXXXX 100644 | ||
69 | --- a/target/arm/tcg/translate-a64.c | ||
70 | +++ b/target/arm/tcg/translate-a64.c | ||
71 | @@ -XXX,XX +XXX,XX @@ static bool trans_MSR_i_DAIFCLEAR(DisasContext *s, arg_i *a) | ||
72 | return true; | ||
73 | } | ||
74 | |||
75 | +static bool trans_MSR_i_ALLINT(DisasContext *s, arg_i *a) | ||
76 | +{ | ||
77 | + if (!dc_isar_feature(aa64_nmi, s) || s->current_el == 0) { | ||
36 | + return false; | 78 | + return false; |
37 | + } | 79 | + } |
38 | + | 80 | + |
39 | if (arm_dc_feature(s, ARM_FEATURE_V8) && | 81 | + if (a->imm == 0) { |
40 | !arm_dc_feature(s, ARM_FEATURE_M)) { | 82 | + clear_pstate_bits(PSTATE_ALLINT); |
41 | return cp >= 14; | 83 | + } else if (s->current_el > 1) { |
84 | + set_pstate_bits(PSTATE_ALLINT); | ||
85 | + } else { | ||
86 | + gen_helper_msr_set_allint_el1(tcg_env); | ||
87 | + } | ||
88 | + | ||
89 | + /* Exit the cpu loop to re-evaluate pending IRQs. */ | ||
90 | + s->base.is_jmp = DISAS_UPDATE_EXIT; | ||
91 | + return true; | ||
92 | +} | ||
93 | + | ||
94 | static bool trans_MSR_i_SVCR(DisasContext *s, arg_MSR_i_SVCR *a) | ||
95 | { | ||
96 | if (!dc_isar_feature(aa64_sme, s) || a->mask == 0) { | ||
42 | -- | 97 | -- |
43 | 2.20.1 | 98 | 2.34.1 |
44 | |||
45 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Jinjie Ruan <ruanjinjie@huawei.com> | ||
1 | 2 | ||
3 | Support ALLINT msr access as follow: | ||
4 | mrs <xt>, ALLINT // read allint | ||
5 | msr ALLINT, <xt> // write allint with imm | ||
6 | |||
7 | Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com> | ||
8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
9 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
10 | Message-id: 20240407081733.3231820-6-ruanjinjie@huawei.com | ||
11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
12 | --- | ||
13 | target/arm/helper.c | 35 +++++++++++++++++++++++++++++++++++ | ||
14 | 1 file changed, 35 insertions(+) | ||
15 | |||
16 | diff --git a/target/arm/helper.c b/target/arm/helper.c | ||
17 | index XXXXXXX..XXXXXXX 100644 | ||
18 | --- a/target/arm/helper.c | ||
19 | +++ b/target/arm/helper.c | ||
20 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo rme_mte_reginfo[] = { | ||
21 | .opc0 = 1, .opc1 = 6, .crn = 7, .crm = 14, .opc2 = 5, | ||
22 | .access = PL3_W, .type = ARM_CP_NOP }, | ||
23 | }; | ||
24 | + | ||
25 | +static void aa64_allint_write(CPUARMState *env, const ARMCPRegInfo *ri, | ||
26 | + uint64_t value) | ||
27 | +{ | ||
28 | + env->pstate = (env->pstate & ~PSTATE_ALLINT) | (value & PSTATE_ALLINT); | ||
29 | +} | ||
30 | + | ||
31 | +static uint64_t aa64_allint_read(CPUARMState *env, const ARMCPRegInfo *ri) | ||
32 | +{ | ||
33 | + return env->pstate & PSTATE_ALLINT; | ||
34 | +} | ||
35 | + | ||
36 | +static CPAccessResult aa64_allint_access(CPUARMState *env, | ||
37 | + const ARMCPRegInfo *ri, bool isread) | ||
38 | +{ | ||
39 | + if (!isread && arm_current_el(env) == 1 && | ||
40 | + (arm_hcrx_el2_eff(env) & HCRX_TALLINT)) { | ||
41 | + return CP_ACCESS_TRAP_EL2; | ||
42 | + } | ||
43 | + return CP_ACCESS_OK; | ||
44 | +} | ||
45 | + | ||
46 | +static const ARMCPRegInfo nmi_reginfo[] = { | ||
47 | + { .name = "ALLINT", .state = ARM_CP_STATE_AA64, | ||
48 | + .opc0 = 3, .opc1 = 0, .opc2 = 0, .crn = 4, .crm = 3, | ||
49 | + .type = ARM_CP_NO_RAW, | ||
50 | + .access = PL1_RW, .accessfn = aa64_allint_access, | ||
51 | + .fieldoffset = offsetof(CPUARMState, pstate), | ||
52 | + .writefn = aa64_allint_write, .readfn = aa64_allint_read, | ||
53 | + .resetfn = arm_cp_reset_ignore }, | ||
54 | +}; | ||
55 | #endif /* TARGET_AARCH64 */ | ||
56 | |||
57 | static void define_pmu_regs(ARMCPU *cpu) | ||
58 | @@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu) | ||
59 | if (cpu_isar_feature(aa64_nv2, cpu)) { | ||
60 | define_arm_cp_regs(cpu, nv2_reginfo); | ||
61 | } | ||
62 | + | ||
63 | + if (cpu_isar_feature(aa64_nmi, cpu)) { | ||
64 | + define_arm_cp_regs(cpu, nmi_reginfo); | ||
65 | + } | ||
66 | #endif | ||
67 | |||
68 | if (cpu_isar_feature(any_predinv, cpu)) { | ||
69 | -- | ||
70 | 2.34.1 | diff view generated by jsdifflib |
1 | From: Leif Lindholm <leif@nuviainc.com> | 1 | From: Jinjie Ruan <ruanjinjie@huawei.com> |
---|---|---|---|
2 | 2 | ||
3 | Signed-off-by: Leif Lindholm <leif@nuviainc.com> | 3 | This only implements the external delivery method via the GICv3. |
4 | Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com> | 4 | |
5 | Message-id: 20210108185154.8108-5-leif@nuviainc.com | 5 | Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com> |
6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
8 | Message-id: 20240407081733.3231820-7-ruanjinjie@huawei.com | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | --- | 10 | --- |
8 | target/arm/cpu.h | 31 +++++++++++++++++++++++++++++++ | 11 | target/arm/cpu-qom.h | 5 +- |
9 | 1 file changed, 31 insertions(+) | 12 | target/arm/cpu.h | 6 ++ |
13 | target/arm/internals.h | 18 +++++ | ||
14 | target/arm/cpu.c | 147 ++++++++++++++++++++++++++++++++++++++--- | ||
15 | target/arm/helper.c | 33 +++++++-- | ||
16 | 5 files changed, 193 insertions(+), 16 deletions(-) | ||
10 | 17 | ||
18 | diff --git a/target/arm/cpu-qom.h b/target/arm/cpu-qom.h | ||
19 | index XXXXXXX..XXXXXXX 100644 | ||
20 | --- a/target/arm/cpu-qom.h | ||
21 | +++ b/target/arm/cpu-qom.h | ||
22 | @@ -XXX,XX +XXX,XX @@ DECLARE_CLASS_CHECKERS(AArch64CPUClass, AARCH64_CPU, | ||
23 | #define ARM_CPU_TYPE_SUFFIX "-" TYPE_ARM_CPU | ||
24 | #define ARM_CPU_TYPE_NAME(name) (name ARM_CPU_TYPE_SUFFIX) | ||
25 | |||
26 | -/* Meanings of the ARMCPU object's four inbound GPIO lines */ | ||
27 | +/* Meanings of the ARMCPU object's seven inbound GPIO lines */ | ||
28 | #define ARM_CPU_IRQ 0 | ||
29 | #define ARM_CPU_FIQ 1 | ||
30 | #define ARM_CPU_VIRQ 2 | ||
31 | #define ARM_CPU_VFIQ 3 | ||
32 | +#define ARM_CPU_NMI 4 | ||
33 | +#define ARM_CPU_VINMI 5 | ||
34 | +#define ARM_CPU_VFNMI 6 | ||
35 | |||
36 | /* For M profile, some registers are banked secure vs non-secure; | ||
37 | * these are represented as a 2-element array where the first element | ||
11 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | 38 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h |
12 | index XXXXXXX..XXXXXXX 100644 | 39 | index XXXXXXX..XXXXXXX 100644 |
13 | --- a/target/arm/cpu.h | 40 | --- a/target/arm/cpu.h |
14 | +++ b/target/arm/cpu.h | 41 | +++ b/target/arm/cpu.h |
15 | @@ -XXX,XX +XXX,XX @@ FIELD(V7M_FPCCR, ASPEN, 31, 1) | 42 | @@ -XXX,XX +XXX,XX @@ |
16 | /* | 43 | #define EXCP_DIVBYZERO 23 /* v7M DIVBYZERO UsageFault */ |
17 | * System register ID fields. | 44 | #define EXCP_VSERR 24 |
45 | #define EXCP_GPC 25 /* v9 Granule Protection Check Fault */ | ||
46 | +#define EXCP_NMI 26 | ||
47 | +#define EXCP_VINMI 27 | ||
48 | +#define EXCP_VFNMI 28 | ||
49 | /* NB: add new EXCP_ defines to the array in arm_log_exception() too */ | ||
50 | |||
51 | #define ARMV7M_EXCP_RESET 1 | ||
52 | @@ -XXX,XX +XXX,XX @@ | ||
53 | #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_EXT_2 | ||
54 | #define CPU_INTERRUPT_VFIQ CPU_INTERRUPT_TGT_EXT_3 | ||
55 | #define CPU_INTERRUPT_VSERR CPU_INTERRUPT_TGT_INT_0 | ||
56 | +#define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_4 | ||
57 | +#define CPU_INTERRUPT_VINMI CPU_INTERRUPT_TGT_EXT_0 | ||
58 | +#define CPU_INTERRUPT_VFNMI CPU_INTERRUPT_TGT_INT_1 | ||
59 | |||
60 | /* The usual mapping for an AArch64 system register to its AArch32 | ||
61 | * counterpart is for the 32 bit world to have access to the lower | ||
62 | diff --git a/target/arm/internals.h b/target/arm/internals.h | ||
63 | index XXXXXXX..XXXXXXX 100644 | ||
64 | --- a/target/arm/internals.h | ||
65 | +++ b/target/arm/internals.h | ||
66 | @@ -XXX,XX +XXX,XX @@ void arm_cpu_update_virq(ARMCPU *cpu); | ||
18 | */ | 67 | */ |
19 | +FIELD(CLIDR_EL1, CTYPE1, 0, 3) | 68 | void arm_cpu_update_vfiq(ARMCPU *cpu); |
20 | +FIELD(CLIDR_EL1, CTYPE2, 3, 3) | 69 | |
21 | +FIELD(CLIDR_EL1, CTYPE3, 6, 3) | 70 | +/** |
22 | +FIELD(CLIDR_EL1, CTYPE4, 9, 3) | 71 | + * arm_cpu_update_vinmi: Update CPU_INTERRUPT_VINMI bit in cs->interrupt_request |
23 | +FIELD(CLIDR_EL1, CTYPE5, 12, 3) | 72 | + * |
24 | +FIELD(CLIDR_EL1, CTYPE6, 15, 3) | 73 | + * Update the CPU_INTERRUPT_VINMI bit in cs->interrupt_request, following |
25 | +FIELD(CLIDR_EL1, CTYPE7, 18, 3) | 74 | + * a change to either the input VNMI line from the GIC or the HCRX_EL2.VINMI. |
26 | +FIELD(CLIDR_EL1, LOUIS, 21, 3) | 75 | + * Must be called with the BQL held. |
27 | +FIELD(CLIDR_EL1, LOC, 24, 3) | 76 | + */ |
28 | +FIELD(CLIDR_EL1, LOUU, 27, 3) | 77 | +void arm_cpu_update_vinmi(ARMCPU *cpu); |
29 | +FIELD(CLIDR_EL1, ICB, 30, 3) | 78 | + |
30 | + | 79 | +/** |
31 | +/* When FEAT_CCIDX is implemented */ | 80 | + * arm_cpu_update_vfnmi: Update CPU_INTERRUPT_VFNMI bit in cs->interrupt_request |
32 | +FIELD(CCSIDR_EL1, CCIDX_LINESIZE, 0, 3) | 81 | + * |
33 | +FIELD(CCSIDR_EL1, CCIDX_ASSOCIATIVITY, 3, 21) | 82 | + * Update the CPU_INTERRUPT_VFNMI bit in cs->interrupt_request, following |
34 | +FIELD(CCSIDR_EL1, CCIDX_NUMSETS, 32, 24) | 83 | + * a change to the HCRX_EL2.VFNMI. |
35 | + | 84 | + * Must be called with the BQL held. |
36 | +/* When FEAT_CCIDX is not implemented */ | 85 | + */ |
37 | +FIELD(CCSIDR_EL1, LINESIZE, 0, 3) | 86 | +void arm_cpu_update_vfnmi(ARMCPU *cpu); |
38 | +FIELD(CCSIDR_EL1, ASSOCIATIVITY, 3, 10) | 87 | + |
39 | +FIELD(CCSIDR_EL1, NUMSETS, 13, 15) | 88 | /** |
40 | + | 89 | * arm_cpu_update_vserr: Update CPU_INTERRUPT_VSERR bit |
41 | +FIELD(CTR_EL0, IMINLINE, 0, 4) | 90 | * |
42 | +FIELD(CTR_EL0, L1IP, 14, 2) | 91 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c |
43 | +FIELD(CTR_EL0, DMINLINE, 16, 4) | 92 | index XXXXXXX..XXXXXXX 100644 |
44 | +FIELD(CTR_EL0, ERG, 20, 4) | 93 | --- a/target/arm/cpu.c |
45 | +FIELD(CTR_EL0, CWG, 24, 4) | 94 | +++ b/target/arm/cpu.c |
46 | +FIELD(CTR_EL0, IDC, 28, 1) | 95 | @@ -XXX,XX +XXX,XX @@ void arm_restore_state_to_opc(CPUState *cs, |
47 | +FIELD(CTR_EL0, DIC, 29, 1) | 96 | } |
48 | +FIELD(CTR_EL0, TMINLINE, 32, 6) | 97 | #endif /* CONFIG_TCG */ |
49 | + | 98 | |
50 | FIELD(MIDR_EL1, REVISION, 0, 4) | 99 | +/* |
51 | FIELD(MIDR_EL1, PARTNUM, 4, 12) | 100 | + * With SCTLR_ELx.NMI == 0, IRQ with Superpriority is masked identically with |
52 | FIELD(MIDR_EL1, ARCHITECTURE, 16, 4) | 101 | + * IRQ without Superpriority. Moreover, if the GIC is configured so that |
102 | + * FEAT_GICv3_NMI is only set if FEAT_NMI is set, then we won't ever see | ||
103 | + * CPU_INTERRUPT_*NMI anyway. So we might as well accept NMI here | ||
104 | + * unconditionally. | ||
105 | + */ | ||
106 | static bool arm_cpu_has_work(CPUState *cs) | ||
107 | { | ||
108 | ARMCPU *cpu = ARM_CPU(cs); | ||
109 | @@ -XXX,XX +XXX,XX @@ static bool arm_cpu_has_work(CPUState *cs) | ||
110 | return (cpu->power_state != PSCI_OFF) | ||
111 | && cs->interrupt_request & | ||
112 | (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD | ||
113 | + | CPU_INTERRUPT_NMI | CPU_INTERRUPT_VINMI | CPU_INTERRUPT_VFNMI | ||
114 | | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ | CPU_INTERRUPT_VSERR | ||
115 | | CPU_INTERRUPT_EXITTB); | ||
116 | } | ||
117 | @@ -XXX,XX +XXX,XX @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx, | ||
118 | CPUARMState *env = cpu_env(cs); | ||
119 | bool pstate_unmasked; | ||
120 | bool unmasked = false; | ||
121 | + bool allIntMask = false; | ||
122 | |||
123 | /* | ||
124 | * Don't take exceptions if they target a lower EL. | ||
125 | @@ -XXX,XX +XXX,XX @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx, | ||
126 | return false; | ||
127 | } | ||
128 | |||
129 | + if (cpu_isar_feature(aa64_nmi, env_archcpu(env)) && | ||
130 | + env->cp15.sctlr_el[target_el] & SCTLR_NMI && cur_el == target_el) { | ||
131 | + allIntMask = env->pstate & PSTATE_ALLINT || | ||
132 | + ((env->cp15.sctlr_el[target_el] & SCTLR_SPINTMASK) && | ||
133 | + (env->pstate & PSTATE_SP)); | ||
134 | + } | ||
135 | + | ||
136 | switch (excp_idx) { | ||
137 | + case EXCP_NMI: | ||
138 | + pstate_unmasked = !allIntMask; | ||
139 | + break; | ||
140 | + | ||
141 | + case EXCP_VINMI: | ||
142 | + if (!(hcr_el2 & HCR_IMO) || (hcr_el2 & HCR_TGE)) { | ||
143 | + /* VINMIs are only taken when hypervized. */ | ||
144 | + return false; | ||
145 | + } | ||
146 | + return !allIntMask; | ||
147 | + case EXCP_VFNMI: | ||
148 | + if (!(hcr_el2 & HCR_FMO) || (hcr_el2 & HCR_TGE)) { | ||
149 | + /* VFNMIs are only taken when hypervized. */ | ||
150 | + return false; | ||
151 | + } | ||
152 | + return !allIntMask; | ||
153 | case EXCP_FIQ: | ||
154 | - pstate_unmasked = !(env->daif & PSTATE_F); | ||
155 | + pstate_unmasked = (!(env->daif & PSTATE_F)) && (!allIntMask); | ||
156 | break; | ||
157 | |||
158 | case EXCP_IRQ: | ||
159 | - pstate_unmasked = !(env->daif & PSTATE_I); | ||
160 | + pstate_unmasked = (!(env->daif & PSTATE_I)) && (!allIntMask); | ||
161 | break; | ||
162 | |||
163 | case EXCP_VFIQ: | ||
164 | @@ -XXX,XX +XXX,XX @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx, | ||
165 | /* VFIQs are only taken when hypervized. */ | ||
166 | return false; | ||
167 | } | ||
168 | - return !(env->daif & PSTATE_F); | ||
169 | + return !(env->daif & PSTATE_F) && (!allIntMask); | ||
170 | case EXCP_VIRQ: | ||
171 | if (!(hcr_el2 & HCR_IMO) || (hcr_el2 & HCR_TGE)) { | ||
172 | /* VIRQs are only taken when hypervized. */ | ||
173 | return false; | ||
174 | } | ||
175 | - return !(env->daif & PSTATE_I); | ||
176 | + return !(env->daif & PSTATE_I) && (!allIntMask); | ||
177 | case EXCP_VSERR: | ||
178 | if (!(hcr_el2 & HCR_AMO) || (hcr_el2 & HCR_TGE)) { | ||
179 | /* VIRQs are only taken when hypervized. */ | ||
180 | @@ -XXX,XX +XXX,XX @@ static bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request) | ||
181 | |||
182 | /* The prioritization of interrupts is IMPLEMENTATION DEFINED. */ | ||
183 | |||
184 | + if (cpu_isar_feature(aa64_nmi, env_archcpu(env)) && | ||
185 | + (arm_sctlr(env, cur_el) & SCTLR_NMI)) { | ||
186 | + if (interrupt_request & CPU_INTERRUPT_NMI) { | ||
187 | + excp_idx = EXCP_NMI; | ||
188 | + target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); | ||
189 | + if (arm_excp_unmasked(cs, excp_idx, target_el, | ||
190 | + cur_el, secure, hcr_el2)) { | ||
191 | + goto found; | ||
192 | + } | ||
193 | + } | ||
194 | + if (interrupt_request & CPU_INTERRUPT_VINMI) { | ||
195 | + excp_idx = EXCP_VINMI; | ||
196 | + target_el = 1; | ||
197 | + if (arm_excp_unmasked(cs, excp_idx, target_el, | ||
198 | + cur_el, secure, hcr_el2)) { | ||
199 | + goto found; | ||
200 | + } | ||
201 | + } | ||
202 | + if (interrupt_request & CPU_INTERRUPT_VFNMI) { | ||
203 | + excp_idx = EXCP_VFNMI; | ||
204 | + target_el = 1; | ||
205 | + if (arm_excp_unmasked(cs, excp_idx, target_el, | ||
206 | + cur_el, secure, hcr_el2)) { | ||
207 | + goto found; | ||
208 | + } | ||
209 | + } | ||
210 | + } else { | ||
211 | + /* | ||
212 | + * NMI disabled: interrupts with superpriority are handled | ||
213 | + * as if they didn't have it | ||
214 | + */ | ||
215 | + if (interrupt_request & CPU_INTERRUPT_NMI) { | ||
216 | + interrupt_request |= CPU_INTERRUPT_HARD; | ||
217 | + } | ||
218 | + if (interrupt_request & CPU_INTERRUPT_VINMI) { | ||
219 | + interrupt_request |= CPU_INTERRUPT_VIRQ; | ||
220 | + } | ||
221 | + if (interrupt_request & CPU_INTERRUPT_VFNMI) { | ||
222 | + interrupt_request |= CPU_INTERRUPT_VFIQ; | ||
223 | + } | ||
224 | + } | ||
225 | + | ||
226 | if (interrupt_request & CPU_INTERRUPT_FIQ) { | ||
227 | excp_idx = EXCP_FIQ; | ||
228 | target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); | ||
229 | @@ -XXX,XX +XXX,XX @@ void arm_cpu_update_virq(ARMCPU *cpu) | ||
230 | CPUARMState *env = &cpu->env; | ||
231 | CPUState *cs = CPU(cpu); | ||
232 | |||
233 | - bool new_state = (env->cp15.hcr_el2 & HCR_VI) || | ||
234 | + bool new_state = ((arm_hcr_el2_eff(env) & HCR_VI) && | ||
235 | + !(arm_hcrx_el2_eff(env) & HCRX_VINMI)) || | ||
236 | (env->irq_line_state & CPU_INTERRUPT_VIRQ); | ||
237 | |||
238 | if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VIRQ) != 0)) { | ||
239 | @@ -XXX,XX +XXX,XX @@ void arm_cpu_update_vfiq(ARMCPU *cpu) | ||
240 | CPUARMState *env = &cpu->env; | ||
241 | CPUState *cs = CPU(cpu); | ||
242 | |||
243 | - bool new_state = (env->cp15.hcr_el2 & HCR_VF) || | ||
244 | + bool new_state = ((arm_hcr_el2_eff(env) & HCR_VF) && | ||
245 | + !(arm_hcrx_el2_eff(env) & HCRX_VFNMI)) || | ||
246 | (env->irq_line_state & CPU_INTERRUPT_VFIQ); | ||
247 | |||
248 | if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VFIQ) != 0)) { | ||
249 | @@ -XXX,XX +XXX,XX @@ void arm_cpu_update_vfiq(ARMCPU *cpu) | ||
250 | } | ||
251 | } | ||
252 | |||
253 | +void arm_cpu_update_vinmi(ARMCPU *cpu) | ||
254 | +{ | ||
255 | + /* | ||
256 | + * Update the interrupt level for VINMI, which is the logical OR of | ||
257 | + * the HCRX_EL2.VINMI bit and the input line level from the GIC. | ||
258 | + */ | ||
259 | + CPUARMState *env = &cpu->env; | ||
260 | + CPUState *cs = CPU(cpu); | ||
261 | + | ||
262 | + bool new_state = ((arm_hcr_el2_eff(env) & HCR_VI) && | ||
263 | + (arm_hcrx_el2_eff(env) & HCRX_VINMI)) || | ||
264 | + (env->irq_line_state & CPU_INTERRUPT_VINMI); | ||
265 | + | ||
266 | + if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VINMI) != 0)) { | ||
267 | + if (new_state) { | ||
268 | + cpu_interrupt(cs, CPU_INTERRUPT_VINMI); | ||
269 | + } else { | ||
270 | + cpu_reset_interrupt(cs, CPU_INTERRUPT_VINMI); | ||
271 | + } | ||
272 | + } | ||
273 | +} | ||
274 | + | ||
275 | +void arm_cpu_update_vfnmi(ARMCPU *cpu) | ||
276 | +{ | ||
277 | + /* | ||
278 | + * Update the interrupt level for VFNMI, which is the HCRX_EL2.VFNMI bit. | ||
279 | + */ | ||
280 | + CPUARMState *env = &cpu->env; | ||
281 | + CPUState *cs = CPU(cpu); | ||
282 | + | ||
283 | + bool new_state = (arm_hcr_el2_eff(env) & HCR_VF) && | ||
284 | + (arm_hcrx_el2_eff(env) & HCRX_VFNMI); | ||
285 | + | ||
286 | + if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VFNMI) != 0)) { | ||
287 | + if (new_state) { | ||
288 | + cpu_interrupt(cs, CPU_INTERRUPT_VFNMI); | ||
289 | + } else { | ||
290 | + cpu_reset_interrupt(cs, CPU_INTERRUPT_VFNMI); | ||
291 | + } | ||
292 | + } | ||
293 | +} | ||
294 | + | ||
295 | void arm_cpu_update_vserr(ARMCPU *cpu) | ||
296 | { | ||
297 | /* | ||
298 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_set_irq(void *opaque, int irq, int level) | ||
299 | [ARM_CPU_IRQ] = CPU_INTERRUPT_HARD, | ||
300 | [ARM_CPU_FIQ] = CPU_INTERRUPT_FIQ, | ||
301 | [ARM_CPU_VIRQ] = CPU_INTERRUPT_VIRQ, | ||
302 | - [ARM_CPU_VFIQ] = CPU_INTERRUPT_VFIQ | ||
303 | + [ARM_CPU_VFIQ] = CPU_INTERRUPT_VFIQ, | ||
304 | + [ARM_CPU_NMI] = CPU_INTERRUPT_NMI, | ||
305 | + [ARM_CPU_VINMI] = CPU_INTERRUPT_VINMI, | ||
306 | }; | ||
307 | |||
308 | if (!arm_feature(env, ARM_FEATURE_EL2) && | ||
309 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_set_irq(void *opaque, int irq, int level) | ||
310 | case ARM_CPU_VFIQ: | ||
311 | arm_cpu_update_vfiq(cpu); | ||
312 | break; | ||
313 | + case ARM_CPU_VINMI: | ||
314 | + arm_cpu_update_vinmi(cpu); | ||
315 | + break; | ||
316 | case ARM_CPU_IRQ: | ||
317 | case ARM_CPU_FIQ: | ||
318 | + case ARM_CPU_NMI: | ||
319 | if (level) { | ||
320 | cpu_interrupt(cs, mask[irq]); | ||
321 | } else { | ||
322 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_initfn(Object *obj) | ||
323 | #else | ||
324 | /* Our inbound IRQ and FIQ lines */ | ||
325 | if (kvm_enabled()) { | ||
326 | - /* VIRQ and VFIQ are unused with KVM but we add them to maintain | ||
327 | - * the same interface as non-KVM CPUs. | ||
328 | + /* | ||
329 | + * VIRQ, VFIQ, NMI, VINMI are unused with KVM but we add | ||
330 | + * them to maintain the same interface as non-KVM CPUs. | ||
331 | */ | ||
332 | - qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 4); | ||
333 | + qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 6); | ||
334 | } else { | ||
335 | - qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 4); | ||
336 | + qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 6); | ||
337 | } | ||
338 | |||
339 | qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs, | ||
340 | diff --git a/target/arm/helper.c b/target/arm/helper.c | ||
341 | index XXXXXXX..XXXXXXX 100644 | ||
342 | --- a/target/arm/helper.c | ||
343 | +++ b/target/arm/helper.c | ||
344 | @@ -XXX,XX +XXX,XX @@ static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_mask) | ||
345 | * and the state of the input lines from the GIC. (This requires | ||
346 | * that we have the BQL, which is done by marking the | ||
347 | * reginfo structs as ARM_CP_IO.) | ||
348 | - * Note that if a write to HCR pends a VIRQ or VFIQ it is never | ||
349 | - * possible for it to be taken immediately, because VIRQ and | ||
350 | - * VFIQ are masked unless running at EL0 or EL1, and HCR | ||
351 | - * can only be written at EL2. | ||
352 | + * Note that if a write to HCR pends a VIRQ or VFIQ or VINMI or | ||
353 | + * VFNMI, it is never possible for it to be taken immediately | ||
354 | + * because VIRQ, VFIQ, VINMI and VFNMI are masked unless running | ||
355 | + * at EL0 or EL1, and HCR can only be written at EL2. | ||
356 | */ | ||
357 | g_assert(bql_locked()); | ||
358 | arm_cpu_update_virq(cpu); | ||
359 | arm_cpu_update_vfiq(cpu); | ||
360 | arm_cpu_update_vserr(cpu); | ||
361 | + if (cpu_isar_feature(aa64_nmi, cpu)) { | ||
362 | + arm_cpu_update_vinmi(cpu); | ||
363 | + arm_cpu_update_vfnmi(cpu); | ||
364 | + } | ||
365 | } | ||
366 | |||
367 | static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) | ||
368 | @@ -XXX,XX +XXX,XX @@ static void hcrx_write(CPUARMState *env, const ARMCPRegInfo *ri, | ||
369 | |||
370 | /* Clear RES0 bits. */ | ||
371 | env->cp15.hcrx_el2 = value & valid_mask; | ||
372 | + | ||
373 | + /* | ||
374 | + * Updates to VINMI and VFNMI require us to update the status of | ||
375 | + * virtual NMI, which are the logical OR of these bits | ||
376 | + * and the state of the input lines from the GIC. (This requires | ||
377 | + * that we have the BQL, which is done by marking the | ||
378 | + * reginfo structs as ARM_CP_IO.) | ||
379 | + * Note that if a write to HCRX pends a VINMI or VFNMI it is never | ||
380 | + * possible for it to be taken immediately, because VINMI and | ||
381 | + * VFNMI are masked unless running at EL0 or EL1, and HCRX | ||
382 | + * can only be written at EL2. | ||
383 | + */ | ||
384 | + if (cpu_isar_feature(aa64_nmi, cpu)) { | ||
385 | + g_assert(bql_locked()); | ||
386 | + arm_cpu_update_vinmi(cpu); | ||
387 | + arm_cpu_update_vfnmi(cpu); | ||
388 | + } | ||
389 | } | ||
390 | |||
391 | static CPAccessResult access_hxen(CPUARMState *env, const ARMCPRegInfo *ri, | ||
392 | @@ -XXX,XX +XXX,XX @@ static CPAccessResult access_hxen(CPUARMState *env, const ARMCPRegInfo *ri, | ||
393 | |||
394 | static const ARMCPRegInfo hcrx_el2_reginfo = { | ||
395 | .name = "HCRX_EL2", .state = ARM_CP_STATE_AA64, | ||
396 | + .type = ARM_CP_IO, | ||
397 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 2, .opc2 = 2, | ||
398 | .access = PL2_RW, .writefn = hcrx_write, .accessfn = access_hxen, | ||
399 | .nv2_redirect_offset = 0xa0, | ||
400 | @@ -XXX,XX +XXX,XX @@ void arm_log_exception(CPUState *cs) | ||
401 | [EXCP_DIVBYZERO] = "v7M DIVBYZERO UsageFault", | ||
402 | [EXCP_VSERR] = "Virtual SERR", | ||
403 | [EXCP_GPC] = "Granule Protection Check", | ||
404 | + [EXCP_NMI] = "NMI", | ||
405 | + [EXCP_VINMI] = "Virtual IRQ NMI", | ||
406 | + [EXCP_VFNMI] = "Virtual FIQ NMI", | ||
407 | }; | ||
408 | |||
409 | if (idx >= 0 && idx < ARRAY_SIZE(excnames)) { | ||
53 | -- | 410 | -- |
54 | 2.20.1 | 411 | 2.34.1 |
55 | |||
56 | diff view generated by jsdifflib |
1 | From: Rémi Denis-Courmont <remi.denis.courmont@huawei.com> | 1 | From: Jinjie Ruan <ruanjinjie@huawei.com> |
---|---|---|---|
2 | 2 | ||
3 | Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com> | 3 | According to Arm GIC section 4.6.3 Interrupt superpriority, the interrupt |
4 | with superpriority is always IRQ, never FIQ, so handle NMI same as IRQ in | ||
5 | arm_phys_excp_target_el(). | ||
6 | |||
7 | Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com> | ||
4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
9 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
10 | Message-id: 20240407081733.3231820-8-ruanjinjie@huawei.com | ||
5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
6 | --- | 12 | --- |
7 | target/arm/cpu64.c | 1 + | 13 | target/arm/helper.c | 1 + |
8 | 1 file changed, 1 insertion(+) | 14 | 1 file changed, 1 insertion(+) |
9 | 15 | ||
10 | diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c | 16 | diff --git a/target/arm/helper.c b/target/arm/helper.c |
11 | index XXXXXXX..XXXXXXX 100644 | 17 | index XXXXXXX..XXXXXXX 100644 |
12 | --- a/target/arm/cpu64.c | 18 | --- a/target/arm/helper.c |
13 | +++ b/target/arm/cpu64.c | 19 | +++ b/target/arm/helper.c |
14 | @@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj) | 20 | @@ -XXX,XX +XXX,XX @@ uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, |
15 | t = cpu->isar.id_aa64mmfr2; | 21 | hcr_el2 = arm_hcr_el2_eff(env); |
16 | t = FIELD_DP64(t, ID_AA64MMFR2, UAO, 1); | 22 | switch (excp_idx) { |
17 | t = FIELD_DP64(t, ID_AA64MMFR2, CNP, 1); /* TTCNP */ | 23 | case EXCP_IRQ: |
18 | + t = FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* TTST */ | 24 | + case EXCP_NMI: |
19 | cpu->isar.id_aa64mmfr2 = t; | 25 | scr = ((env->cp15.scr_el3 & SCR_IRQ) == SCR_IRQ); |
20 | 26 | hcr = hcr_el2 & HCR_IMO; | |
21 | /* Replicate the same data to the 32-bit id registers. */ | 27 | break; |
22 | -- | 28 | -- |
23 | 2.20.1 | 29 | 2.34.1 |
24 | |||
25 | diff view generated by jsdifflib |
1 | From: Leif Lindholm <leif@nuviainc.com> | 1 | From: Jinjie Ruan <ruanjinjie@huawei.com> |
---|---|---|---|
2 | 2 | ||
3 | Add entries present in ARM DDI 0487F.c (August 2020). | 3 | Add IS and FS bit in ISR_EL1 and handle the read. With CPU_INTERRUPT_NMI or |
4 | CPU_INTERRUPT_VINMI, both CPSR_I and ISR_IS must be set. With | ||
5 | CPU_INTERRUPT_VFNMI, both CPSR_F and ISR_FS must be set. | ||
4 | 6 | ||
5 | Signed-off-by: Leif Lindholm <leif@nuviainc.com> | 7 | Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com> |
8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
7 | Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com> | 10 | Message-id: 20240407081733.3231820-9-ruanjinjie@huawei.com |
8 | Message-id: 20210108185154.8108-6-leif@nuviainc.com | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
10 | --- | 12 | --- |
11 | target/arm/cpu.h | 15 +++++++++++++++ | 13 | target/arm/cpu.h | 2 ++ |
12 | 1 file changed, 15 insertions(+) | 14 | target/arm/helper.c | 13 +++++++++++++ |
15 | 2 files changed, 15 insertions(+) | ||
13 | 16 | ||
14 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | 17 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h |
15 | index XXXXXXX..XXXXXXX 100644 | 18 | index XXXXXXX..XXXXXXX 100644 |
16 | --- a/target/arm/cpu.h | 19 | --- a/target/arm/cpu.h |
17 | +++ b/target/arm/cpu.h | 20 | +++ b/target/arm/cpu.h |
18 | @@ -XXX,XX +XXX,XX @@ FIELD(ID_AA64ISAR1, GPI, 28, 4) | 21 | @@ -XXX,XX +XXX,XX @@ void pmu_init(ARMCPU *cpu); |
19 | FIELD(ID_AA64ISAR1, FRINTTS, 32, 4) | 22 | #define CPSR_N (1U << 31) |
20 | FIELD(ID_AA64ISAR1, SB, 36, 4) | 23 | #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V) |
21 | FIELD(ID_AA64ISAR1, SPECRES, 40, 4) | 24 | #define CPSR_AIF (CPSR_A | CPSR_I | CPSR_F) |
22 | +FIELD(ID_AA64ISAR1, BF16, 44, 4) | 25 | +#define ISR_FS (1U << 9) |
23 | +FIELD(ID_AA64ISAR1, DGH, 48, 4) | 26 | +#define ISR_IS (1U << 10) |
24 | +FIELD(ID_AA64ISAR1, I8MM, 52, 4) | 27 | |
25 | 28 | #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7) | |
26 | FIELD(ID_AA64PFR0, EL0, 0, 4) | 29 | #define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \ |
27 | FIELD(ID_AA64PFR0, EL1, 4, 4) | 30 | diff --git a/target/arm/helper.c b/target/arm/helper.c |
28 | @@ -XXX,XX +XXX,XX @@ FIELD(ID_AA64PFR0, ADVSIMD, 20, 4) | 31 | index XXXXXXX..XXXXXXX 100644 |
29 | FIELD(ID_AA64PFR0, GIC, 24, 4) | 32 | --- a/target/arm/helper.c |
30 | FIELD(ID_AA64PFR0, RAS, 28, 4) | 33 | +++ b/target/arm/helper.c |
31 | FIELD(ID_AA64PFR0, SVE, 32, 4) | 34 | @@ -XXX,XX +XXX,XX @@ static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
32 | +FIELD(ID_AA64PFR0, SEL2, 36, 4) | 35 | if (cs->interrupt_request & CPU_INTERRUPT_VIRQ) { |
33 | +FIELD(ID_AA64PFR0, MPAM, 40, 4) | 36 | ret |= CPSR_I; |
34 | +FIELD(ID_AA64PFR0, AMU, 44, 4) | 37 | } |
35 | +FIELD(ID_AA64PFR0, DIT, 48, 4) | 38 | + if (cs->interrupt_request & CPU_INTERRUPT_VINMI) { |
36 | +FIELD(ID_AA64PFR0, CSV2, 56, 4) | 39 | + ret |= ISR_IS; |
37 | +FIELD(ID_AA64PFR0, CSV3, 60, 4) | 40 | + ret |= CPSR_I; |
38 | 41 | + } | |
39 | FIELD(ID_AA64PFR1, BT, 0, 4) | 42 | } else { |
40 | FIELD(ID_AA64PFR1, SSBS, 4, 4) | 43 | if (cs->interrupt_request & CPU_INTERRUPT_HARD) { |
41 | FIELD(ID_AA64PFR1, MTE, 8, 4) | 44 | ret |= CPSR_I; |
42 | FIELD(ID_AA64PFR1, RAS_FRAC, 12, 4) | 45 | } |
43 | +FIELD(ID_AA64PFR1, MPAM_FRAC, 16, 4) | 46 | + |
44 | 47 | + if (cs->interrupt_request & CPU_INTERRUPT_NMI) { | |
45 | FIELD(ID_AA64MMFR0, PARANGE, 0, 4) | 48 | + ret |= ISR_IS; |
46 | FIELD(ID_AA64MMFR0, ASIDBITS, 4, 4) | 49 | + ret |= CPSR_I; |
47 | @@ -XXX,XX +XXX,XX @@ FIELD(ID_AA64MMFR0, TGRAN16_2, 32, 4) | 50 | + } |
48 | FIELD(ID_AA64MMFR0, TGRAN64_2, 36, 4) | 51 | } |
49 | FIELD(ID_AA64MMFR0, TGRAN4_2, 40, 4) | 52 | |
50 | FIELD(ID_AA64MMFR0, EXS, 44, 4) | 53 | if (hcr_el2 & HCR_FMO) { |
51 | +FIELD(ID_AA64MMFR0, FGT, 56, 4) | 54 | if (cs->interrupt_request & CPU_INTERRUPT_VFIQ) { |
52 | +FIELD(ID_AA64MMFR0, ECV, 60, 4) | 55 | ret |= CPSR_F; |
53 | 56 | } | |
54 | FIELD(ID_AA64MMFR1, HAFDBS, 0, 4) | 57 | + if (cs->interrupt_request & CPU_INTERRUPT_VFNMI) { |
55 | FIELD(ID_AA64MMFR1, VMIDBITS, 4, 4) | 58 | + ret |= ISR_FS; |
56 | @@ -XXX,XX +XXX,XX @@ FIELD(ID_AA64MMFR1, LO, 16, 4) | 59 | + ret |= CPSR_F; |
57 | FIELD(ID_AA64MMFR1, PAN, 20, 4) | 60 | + } |
58 | FIELD(ID_AA64MMFR1, SPECSEI, 24, 4) | 61 | } else { |
59 | FIELD(ID_AA64MMFR1, XNX, 28, 4) | 62 | if (cs->interrupt_request & CPU_INTERRUPT_FIQ) { |
60 | +FIELD(ID_AA64MMFR1, TWED, 32, 4) | 63 | ret |= CPSR_F; |
61 | +FIELD(ID_AA64MMFR1, ETS, 36, 4) | ||
62 | |||
63 | FIELD(ID_AA64MMFR2, CNP, 0, 4) | ||
64 | FIELD(ID_AA64MMFR2, UAO, 4, 4) | ||
65 | @@ -XXX,XX +XXX,XX @@ FIELD(ID_AA64DFR0, CTX_CMPS, 28, 4) | ||
66 | FIELD(ID_AA64DFR0, PMSVER, 32, 4) | ||
67 | FIELD(ID_AA64DFR0, DOUBLELOCK, 36, 4) | ||
68 | FIELD(ID_AA64DFR0, TRACEFILT, 40, 4) | ||
69 | +FIELD(ID_AA64DFR0, MTPMU, 48, 4) | ||
70 | |||
71 | FIELD(ID_DFR0, COPDBG, 0, 4) | ||
72 | FIELD(ID_DFR0, COPSDBG, 4, 4) | ||
73 | -- | 64 | -- |
74 | 2.20.1 | 65 | 2.34.1 |
75 | |||
76 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Jinjie Ruan <ruanjinjie@huawei.com> | ||
1 | 2 | ||
3 | Set or clear PSTATE.ALLINT on taking an exception to ELx according to the | ||
4 | SCTLR_ELx.SPINTMASK bit. | ||
5 | |||
6 | Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com> | ||
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
9 | Message-id: 20240407081733.3231820-10-ruanjinjie@huawei.com | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
11 | --- | ||
12 | target/arm/helper.c | 8 ++++++++ | ||
13 | 1 file changed, 8 insertions(+) | ||
14 | |||
15 | diff --git a/target/arm/helper.c b/target/arm/helper.c | ||
16 | index XXXXXXX..XXXXXXX 100644 | ||
17 | --- a/target/arm/helper.c | ||
18 | +++ b/target/arm/helper.c | ||
19 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs) | ||
20 | } | ||
21 | } | ||
22 | |||
23 | + if (cpu_isar_feature(aa64_nmi, cpu)) { | ||
24 | + if (!(env->cp15.sctlr_el[new_el] & SCTLR_SPINTMASK)) { | ||
25 | + new_mode |= PSTATE_ALLINT; | ||
26 | + } else { | ||
27 | + new_mode &= ~PSTATE_ALLINT; | ||
28 | + } | ||
29 | + } | ||
30 | + | ||
31 | pstate_write(env, PSTATE_DAIF | new_mode); | ||
32 | env->aarch64 = true; | ||
33 | aarch64_restore_sp(env, new_el); | ||
34 | -- | ||
35 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Jinjie Ruan <ruanjinjie@huawei.com> | ||
1 | 2 | ||
3 | Augment the GICv3's QOM device interface by adding one | ||
4 | new set of sysbus IRQ line, to signal NMI to each CPU. | ||
5 | |||
6 | Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com> | ||
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
9 | Message-id: 20240407081733.3231820-11-ruanjinjie@huawei.com | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
11 | --- | ||
12 | include/hw/intc/arm_gic_common.h | 2 ++ | ||
13 | include/hw/intc/arm_gicv3_common.h | 2 ++ | ||
14 | hw/intc/arm_gicv3_common.c | 6 ++++++ | ||
15 | 3 files changed, 10 insertions(+) | ||
16 | |||
17 | diff --git a/include/hw/intc/arm_gic_common.h b/include/hw/intc/arm_gic_common.h | ||
18 | index XXXXXXX..XXXXXXX 100644 | ||
19 | --- a/include/hw/intc/arm_gic_common.h | ||
20 | +++ b/include/hw/intc/arm_gic_common.h | ||
21 | @@ -XXX,XX +XXX,XX @@ struct GICState { | ||
22 | qemu_irq parent_fiq[GIC_NCPU]; | ||
23 | qemu_irq parent_virq[GIC_NCPU]; | ||
24 | qemu_irq parent_vfiq[GIC_NCPU]; | ||
25 | + qemu_irq parent_nmi[GIC_NCPU]; | ||
26 | + qemu_irq parent_vnmi[GIC_NCPU]; | ||
27 | qemu_irq maintenance_irq[GIC_NCPU]; | ||
28 | |||
29 | /* GICD_CTLR; for a GIC with the security extensions the NS banked version | ||
30 | diff --git a/include/hw/intc/arm_gicv3_common.h b/include/hw/intc/arm_gicv3_common.h | ||
31 | index XXXXXXX..XXXXXXX 100644 | ||
32 | --- a/include/hw/intc/arm_gicv3_common.h | ||
33 | +++ b/include/hw/intc/arm_gicv3_common.h | ||
34 | @@ -XXX,XX +XXX,XX @@ struct GICv3CPUState { | ||
35 | qemu_irq parent_fiq; | ||
36 | qemu_irq parent_virq; | ||
37 | qemu_irq parent_vfiq; | ||
38 | + qemu_irq parent_nmi; | ||
39 | + qemu_irq parent_vnmi; | ||
40 | |||
41 | /* Redistributor */ | ||
42 | uint32_t level; /* Current IRQ level */ | ||
43 | diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c | ||
44 | index XXXXXXX..XXXXXXX 100644 | ||
45 | --- a/hw/intc/arm_gicv3_common.c | ||
46 | +++ b/hw/intc/arm_gicv3_common.c | ||
47 | @@ -XXX,XX +XXX,XX @@ void gicv3_init_irqs_and_mmio(GICv3State *s, qemu_irq_handler handler, | ||
48 | for (i = 0; i < s->num_cpu; i++) { | ||
49 | sysbus_init_irq(sbd, &s->cpu[i].parent_vfiq); | ||
50 | } | ||
51 | + for (i = 0; i < s->num_cpu; i++) { | ||
52 | + sysbus_init_irq(sbd, &s->cpu[i].parent_nmi); | ||
53 | + } | ||
54 | + for (i = 0; i < s->num_cpu; i++) { | ||
55 | + sysbus_init_irq(sbd, &s->cpu[i].parent_vnmi); | ||
56 | + } | ||
57 | |||
58 | memory_region_init_io(&s->iomem_dist, OBJECT(s), ops, s, | ||
59 | "gicv3_dist", 0x10000); | ||
60 | -- | ||
61 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Jinjie Ruan <ruanjinjie@huawei.com> | ||
1 | 2 | ||
3 | Wire the new NMI and VINMI interrupt line from the GIC to each CPU if it | ||
4 | is not GICv2. | ||
5 | |||
6 | Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com> | ||
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Message-id: 20240407081733.3231820-12-ruanjinjie@huawei.com | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
10 | --- | ||
11 | hw/arm/virt.c | 10 +++++++++- | ||
12 | 1 file changed, 9 insertions(+), 1 deletion(-) | ||
13 | |||
14 | diff --git a/hw/arm/virt.c b/hw/arm/virt.c | ||
15 | index XXXXXXX..XXXXXXX 100644 | ||
16 | --- a/hw/arm/virt.c | ||
17 | +++ b/hw/arm/virt.c | ||
18 | @@ -XXX,XX +XXX,XX @@ static void create_gic(VirtMachineState *vms, MemoryRegion *mem) | ||
19 | |||
20 | /* Wire the outputs from each CPU's generic timer and the GICv3 | ||
21 | * maintenance interrupt signal to the appropriate GIC PPI inputs, | ||
22 | - * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs. | ||
23 | + * and the GIC's IRQ/FIQ/VIRQ/VFIQ/NMI/VINMI interrupt outputs to the | ||
24 | + * CPU's inputs. | ||
25 | */ | ||
26 | for (i = 0; i < smp_cpus; i++) { | ||
27 | DeviceState *cpudev = DEVICE(qemu_get_cpu(i)); | ||
28 | @@ -XXX,XX +XXX,XX @@ static void create_gic(VirtMachineState *vms, MemoryRegion *mem) | ||
29 | qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ)); | ||
30 | sysbus_connect_irq(gicbusdev, i + 3 * smp_cpus, | ||
31 | qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); | ||
32 | + | ||
33 | + if (vms->gic_version != VIRT_GIC_VERSION_2) { | ||
34 | + sysbus_connect_irq(gicbusdev, i + 4 * smp_cpus, | ||
35 | + qdev_get_gpio_in(cpudev, ARM_CPU_NMI)); | ||
36 | + sysbus_connect_irq(gicbusdev, i + 5 * smp_cpus, | ||
37 | + qdev_get_gpio_in(cpudev, ARM_CPU_VINMI)); | ||
38 | + } | ||
39 | } | ||
40 | |||
41 | fdt_add_gic_node(vms); | ||
42 | -- | ||
43 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Jinjie Ruan <ruanjinjie@huawei.com> | ||
1 | 2 | ||
3 | According to Arm GIC section 4.6.3 Interrupt superpriority, the interrupt | ||
4 | with superpriority is always IRQ, never FIQ, so the NMI exception trap entry | ||
5 | behave like IRQ. And VINMI(vIRQ with Superpriority) can be raised from the | ||
6 | GIC or come from the hcrx_el2.HCRX_VINMI bit, VFNMI(vFIQ with Superpriority) | ||
7 | come from the hcrx_el2.HCRX_VFNMI bit. | ||
8 | |||
9 | Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com> | ||
10 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
11 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
12 | Message-id: 20240407081733.3231820-13-ruanjinjie@huawei.com | ||
13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
14 | --- | ||
15 | target/arm/helper.c | 3 +++ | ||
16 | 1 file changed, 3 insertions(+) | ||
17 | |||
18 | diff --git a/target/arm/helper.c b/target/arm/helper.c | ||
19 | index XXXXXXX..XXXXXXX 100644 | ||
20 | --- a/target/arm/helper.c | ||
21 | +++ b/target/arm/helper.c | ||
22 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs) | ||
23 | break; | ||
24 | case EXCP_IRQ: | ||
25 | case EXCP_VIRQ: | ||
26 | + case EXCP_NMI: | ||
27 | + case EXCP_VINMI: | ||
28 | addr += 0x80; | ||
29 | break; | ||
30 | case EXCP_FIQ: | ||
31 | case EXCP_VFIQ: | ||
32 | + case EXCP_VFNMI: | ||
33 | addr += 0x100; | ||
34 | break; | ||
35 | case EXCP_VSERR: | ||
36 | -- | ||
37 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Jinjie Ruan <ruanjinjie@huawei.com> | ||
1 | 2 | ||
3 | Add a property has-nmi to the GICv3 device, and use this to set | ||
4 | the NMI bit in the GICD_TYPER register. This isn't visible to | ||
5 | guests yet because the property defaults to false and we won't | ||
6 | set it in the board code until we've landed all of the changes | ||
7 | needed to implement FEAT_GICV3_NMI. | ||
8 | |||
9 | Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com> | ||
10 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
11 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
12 | Message-id: 20240407081733.3231820-14-ruanjinjie@huawei.com | ||
13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
14 | --- | ||
15 | hw/intc/gicv3_internal.h | 1 + | ||
16 | include/hw/intc/arm_gicv3_common.h | 1 + | ||
17 | hw/intc/arm_gicv3_common.c | 1 + | ||
18 | hw/intc/arm_gicv3_dist.c | 2 ++ | ||
19 | 4 files changed, 5 insertions(+) | ||
20 | |||
21 | diff --git a/hw/intc/gicv3_internal.h b/hw/intc/gicv3_internal.h | ||
22 | index XXXXXXX..XXXXXXX 100644 | ||
23 | --- a/hw/intc/gicv3_internal.h | ||
24 | +++ b/hw/intc/gicv3_internal.h | ||
25 | @@ -XXX,XX +XXX,XX @@ | ||
26 | #define GICD_CTLR_E1NWF (1U << 7) | ||
27 | #define GICD_CTLR_RWP (1U << 31) | ||
28 | |||
29 | +#define GICD_TYPER_NMI_SHIFT 9 | ||
30 | #define GICD_TYPER_LPIS_SHIFT 17 | ||
31 | |||
32 | /* 16 bits EventId */ | ||
33 | diff --git a/include/hw/intc/arm_gicv3_common.h b/include/hw/intc/arm_gicv3_common.h | ||
34 | index XXXXXXX..XXXXXXX 100644 | ||
35 | --- a/include/hw/intc/arm_gicv3_common.h | ||
36 | +++ b/include/hw/intc/arm_gicv3_common.h | ||
37 | @@ -XXX,XX +XXX,XX @@ struct GICv3State { | ||
38 | uint32_t num_irq; | ||
39 | uint32_t revision; | ||
40 | bool lpi_enable; | ||
41 | + bool nmi_support; | ||
42 | bool security_extn; | ||
43 | bool force_8bit_prio; | ||
44 | bool irq_reset_nonsecure; | ||
45 | diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c | ||
46 | index XXXXXXX..XXXXXXX 100644 | ||
47 | --- a/hw/intc/arm_gicv3_common.c | ||
48 | +++ b/hw/intc/arm_gicv3_common.c | ||
49 | @@ -XXX,XX +XXX,XX @@ static Property arm_gicv3_common_properties[] = { | ||
50 | DEFINE_PROP_UINT32("num-irq", GICv3State, num_irq, 32), | ||
51 | DEFINE_PROP_UINT32("revision", GICv3State, revision, 3), | ||
52 | DEFINE_PROP_BOOL("has-lpi", GICv3State, lpi_enable, 0), | ||
53 | + DEFINE_PROP_BOOL("has-nmi", GICv3State, nmi_support, 0), | ||
54 | DEFINE_PROP_BOOL("has-security-extensions", GICv3State, security_extn, 0), | ||
55 | /* | ||
56 | * Compatibility property: force 8 bits of physical priority, even | ||
57 | diff --git a/hw/intc/arm_gicv3_dist.c b/hw/intc/arm_gicv3_dist.c | ||
58 | index XXXXXXX..XXXXXXX 100644 | ||
59 | --- a/hw/intc/arm_gicv3_dist.c | ||
60 | +++ b/hw/intc/arm_gicv3_dist.c | ||
61 | @@ -XXX,XX +XXX,XX @@ static bool gicd_readl(GICv3State *s, hwaddr offset, | ||
62 | * by GICD_TYPER.IDbits) | ||
63 | * MBIS == 0 (message-based SPIs not supported) | ||
64 | * SecurityExtn == 1 if security extns supported | ||
65 | + * NMI = 1 if Non-maskable interrupt property is supported | ||
66 | * CPUNumber == 0 since for us ARE is always 1 | ||
67 | * ITLinesNumber == (((max SPI IntID + 1) / 32) - 1) | ||
68 | */ | ||
69 | @@ -XXX,XX +XXX,XX @@ static bool gicd_readl(GICv3State *s, hwaddr offset, | ||
70 | bool dvis = s->revision >= 4; | ||
71 | |||
72 | *data = (1 << 25) | (1 << 24) | (dvis << 18) | (sec_extn << 10) | | ||
73 | + (s->nmi_support << GICD_TYPER_NMI_SHIFT) | | ||
74 | (s->lpi_enable << GICD_TYPER_LPIS_SHIFT) | | ||
75 | (0xf << 19) | itlinesnumber; | ||
76 | return true; | ||
77 | -- | ||
78 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Jinjie Ruan <ruanjinjie@huawei.com> | ||
1 | 2 | ||
3 | So far, there is no FEAT_GICv3_NMI support in the in-kernel GIC, so make it | ||
4 | an error to try to set has-nmi=true for the KVM GICv3. | ||
5 | |||
6 | Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com> | ||
7 | Message-id: 20240407081733.3231820-15-ruanjinjie@huawei.com | ||
8 | Suggested-by: Peter Maydell <peter.maydell@linaro.org> | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
10 | --- | ||
11 | hw/intc/arm_gicv3_kvm.c | 5 +++++ | ||
12 | 1 file changed, 5 insertions(+) | ||
13 | |||
14 | diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c | ||
15 | index XXXXXXX..XXXXXXX 100644 | ||
16 | --- a/hw/intc/arm_gicv3_kvm.c | ||
17 | +++ b/hw/intc/arm_gicv3_kvm.c | ||
18 | @@ -XXX,XX +XXX,XX @@ static void kvm_arm_gicv3_realize(DeviceState *dev, Error **errp) | ||
19 | return; | ||
20 | } | ||
21 | |||
22 | + if (s->nmi_support) { | ||
23 | + error_setg(errp, "NMI is not supported with the in-kernel GIC"); | ||
24 | + return; | ||
25 | + } | ||
26 | + | ||
27 | gicv3_init_irqs_and_mmio(s, kvm_arm_gicv3_set_irq, NULL); | ||
28 | |||
29 | for (i = 0; i < s->num_cpu; i++) { | ||
30 | -- | ||
31 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Jinjie Ruan <ruanjinjie@huawei.com> | ||
1 | 2 | ||
3 | A SPI, PPI or SGI interrupt can have non-maskable property. So maintain | ||
4 | non-maskable property in PendingIrq and GICR/GICD. Since add new device | ||
5 | state, it also needs to be migrated, so also save NMI info in | ||
6 | vmstate_gicv3_cpu and vmstate_gicv3. | ||
7 | |||
8 | Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com> | ||
9 | Acked-by: Richard Henderson <richard.henderson@linaro.org> | ||
10 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
11 | Message-id: 20240407081733.3231820-16-ruanjinjie@huawei.com | ||
12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
13 | --- | ||
14 | include/hw/intc/arm_gicv3_common.h | 4 ++++ | ||
15 | hw/intc/arm_gicv3_common.c | 38 ++++++++++++++++++++++++++++++ | ||
16 | 2 files changed, 42 insertions(+) | ||
17 | |||
18 | diff --git a/include/hw/intc/arm_gicv3_common.h b/include/hw/intc/arm_gicv3_common.h | ||
19 | index XXXXXXX..XXXXXXX 100644 | ||
20 | --- a/include/hw/intc/arm_gicv3_common.h | ||
21 | +++ b/include/hw/intc/arm_gicv3_common.h | ||
22 | @@ -XXX,XX +XXX,XX @@ typedef struct { | ||
23 | int irq; | ||
24 | uint8_t prio; | ||
25 | int grp; | ||
26 | + bool nmi; | ||
27 | } PendingIrq; | ||
28 | |||
29 | struct GICv3CPUState { | ||
30 | @@ -XXX,XX +XXX,XX @@ struct GICv3CPUState { | ||
31 | uint32_t gicr_ienabler0; | ||
32 | uint32_t gicr_ipendr0; | ||
33 | uint32_t gicr_iactiver0; | ||
34 | + uint32_t gicr_inmir0; | ||
35 | uint32_t edge_trigger; /* ICFGR0 and ICFGR1 even bits */ | ||
36 | uint32_t gicr_igrpmodr0; | ||
37 | uint32_t gicr_nsacr; | ||
38 | @@ -XXX,XX +XXX,XX @@ struct GICv3State { | ||
39 | GIC_DECLARE_BITMAP(active); /* GICD_ISACTIVER */ | ||
40 | GIC_DECLARE_BITMAP(level); /* Current level */ | ||
41 | GIC_DECLARE_BITMAP(edge_trigger); /* GICD_ICFGR even bits */ | ||
42 | + GIC_DECLARE_BITMAP(nmi); /* GICD_INMIR */ | ||
43 | uint8_t gicd_ipriority[GICV3_MAXIRQ]; | ||
44 | uint64_t gicd_irouter[GICV3_MAXIRQ]; | ||
45 | /* Cached information: pointer to the cpu i/f for the CPUs specified | ||
46 | @@ -XXX,XX +XXX,XX @@ GICV3_BITMAP_ACCESSORS(pending) | ||
47 | GICV3_BITMAP_ACCESSORS(active) | ||
48 | GICV3_BITMAP_ACCESSORS(level) | ||
49 | GICV3_BITMAP_ACCESSORS(edge_trigger) | ||
50 | +GICV3_BITMAP_ACCESSORS(nmi) | ||
51 | |||
52 | #define TYPE_ARM_GICV3_COMMON "arm-gicv3-common" | ||
53 | typedef struct ARMGICv3CommonClass ARMGICv3CommonClass; | ||
54 | diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c | ||
55 | index XXXXXXX..XXXXXXX 100644 | ||
56 | --- a/hw/intc/arm_gicv3_common.c | ||
57 | +++ b/hw/intc/arm_gicv3_common.c | ||
58 | @@ -XXX,XX +XXX,XX @@ const VMStateDescription vmstate_gicv3_gicv4 = { | ||
59 | } | ||
60 | }; | ||
61 | |||
62 | +static bool gicv3_cpu_nmi_needed(void *opaque) | ||
63 | +{ | ||
64 | + GICv3CPUState *cs = opaque; | ||
65 | + | ||
66 | + return cs->gic->nmi_support; | ||
67 | +} | ||
68 | + | ||
69 | +static const VMStateDescription vmstate_gicv3_cpu_nmi = { | ||
70 | + .name = "arm_gicv3_cpu/nmi", | ||
71 | + .version_id = 1, | ||
72 | + .minimum_version_id = 1, | ||
73 | + .needed = gicv3_cpu_nmi_needed, | ||
74 | + .fields = (const VMStateField[]) { | ||
75 | + VMSTATE_UINT32(gicr_inmir0, GICv3CPUState), | ||
76 | + VMSTATE_END_OF_LIST() | ||
77 | + } | ||
78 | +}; | ||
79 | + | ||
80 | static const VMStateDescription vmstate_gicv3_cpu = { | ||
81 | .name = "arm_gicv3_cpu", | ||
82 | .version_id = 1, | ||
83 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_gicv3_cpu = { | ||
84 | &vmstate_gicv3_cpu_virt, | ||
85 | &vmstate_gicv3_cpu_sre_el1, | ||
86 | &vmstate_gicv3_gicv4, | ||
87 | + &vmstate_gicv3_cpu_nmi, | ||
88 | NULL | ||
89 | } | ||
90 | }; | ||
91 | @@ -XXX,XX +XXX,XX @@ const VMStateDescription vmstate_gicv3_gicd_no_migration_shift_bug = { | ||
92 | } | ||
93 | }; | ||
94 | |||
95 | +static bool gicv3_nmi_needed(void *opaque) | ||
96 | +{ | ||
97 | + GICv3State *cs = opaque; | ||
98 | + | ||
99 | + return cs->nmi_support; | ||
100 | +} | ||
101 | + | ||
102 | +const VMStateDescription vmstate_gicv3_gicd_nmi = { | ||
103 | + .name = "arm_gicv3/gicd_nmi", | ||
104 | + .version_id = 1, | ||
105 | + .minimum_version_id = 1, | ||
106 | + .needed = gicv3_nmi_needed, | ||
107 | + .fields = (const VMStateField[]) { | ||
108 | + VMSTATE_UINT32_ARRAY(nmi, GICv3State, GICV3_BMP_SIZE), | ||
109 | + VMSTATE_END_OF_LIST() | ||
110 | + } | ||
111 | +}; | ||
112 | + | ||
113 | static const VMStateDescription vmstate_gicv3 = { | ||
114 | .name = "arm_gicv3", | ||
115 | .version_id = 1, | ||
116 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_gicv3 = { | ||
117 | }, | ||
118 | .subsections = (const VMStateDescription * const []) { | ||
119 | &vmstate_gicv3_gicd_no_migration_shift_bug, | ||
120 | + &vmstate_gicv3_gicd_nmi, | ||
121 | NULL | ||
122 | } | ||
123 | }; | ||
124 | -- | ||
125 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Jinjie Ruan <ruanjinjie@huawei.com> | ||
1 | 2 | ||
3 | Add GICR_INMIR0 register and support access GICR_INMIR0. | ||
4 | |||
5 | Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com> | ||
6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
8 | Message-id: 20240407081733.3231820-17-ruanjinjie@huawei.com | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
10 | --- | ||
11 | hw/intc/gicv3_internal.h | 1 + | ||
12 | hw/intc/arm_gicv3_redist.c | 19 +++++++++++++++++++ | ||
13 | 2 files changed, 20 insertions(+) | ||
14 | |||
15 | diff --git a/hw/intc/gicv3_internal.h b/hw/intc/gicv3_internal.h | ||
16 | index XXXXXXX..XXXXXXX 100644 | ||
17 | --- a/hw/intc/gicv3_internal.h | ||
18 | +++ b/hw/intc/gicv3_internal.h | ||
19 | @@ -XXX,XX +XXX,XX @@ | ||
20 | #define GICR_ICFGR1 (GICR_SGI_OFFSET + 0x0C04) | ||
21 | #define GICR_IGRPMODR0 (GICR_SGI_OFFSET + 0x0D00) | ||
22 | #define GICR_NSACR (GICR_SGI_OFFSET + 0x0E00) | ||
23 | +#define GICR_INMIR0 (GICR_SGI_OFFSET + 0x0F80) | ||
24 | |||
25 | /* VLPI redistributor registers, offsets from VLPI_base */ | ||
26 | #define GICR_VPROPBASER (GICR_VLPI_OFFSET + 0x70) | ||
27 | diff --git a/hw/intc/arm_gicv3_redist.c b/hw/intc/arm_gicv3_redist.c | ||
28 | index XXXXXXX..XXXXXXX 100644 | ||
29 | --- a/hw/intc/arm_gicv3_redist.c | ||
30 | +++ b/hw/intc/arm_gicv3_redist.c | ||
31 | @@ -XXX,XX +XXX,XX @@ static int gicr_ns_access(GICv3CPUState *cs, int irq) | ||
32 | return extract32(cs->gicr_nsacr, irq * 2, 2); | ||
33 | } | ||
34 | |||
35 | +static void gicr_write_bitmap_reg(GICv3CPUState *cs, MemTxAttrs attrs, | ||
36 | + uint32_t *reg, uint32_t val) | ||
37 | +{ | ||
38 | + /* Helper routine to implement writing to a "set" register */ | ||
39 | + val &= mask_group(cs, attrs); | ||
40 | + *reg = val; | ||
41 | + gicv3_redist_update(cs); | ||
42 | +} | ||
43 | + | ||
44 | static void gicr_write_set_bitmap_reg(GICv3CPUState *cs, MemTxAttrs attrs, | ||
45 | uint32_t *reg, uint32_t val) | ||
46 | { | ||
47 | @@ -XXX,XX +XXX,XX @@ static MemTxResult gicr_readl(GICv3CPUState *cs, hwaddr offset, | ||
48 | *data = value; | ||
49 | return MEMTX_OK; | ||
50 | } | ||
51 | + case GICR_INMIR0: | ||
52 | + *data = cs->gic->nmi_support ? | ||
53 | + gicr_read_bitmap_reg(cs, attrs, cs->gicr_inmir0) : 0; | ||
54 | + return MEMTX_OK; | ||
55 | case GICR_ICFGR0: | ||
56 | case GICR_ICFGR1: | ||
57 | { | ||
58 | @@ -XXX,XX +XXX,XX @@ static MemTxResult gicr_writel(GICv3CPUState *cs, hwaddr offset, | ||
59 | gicv3_redist_update(cs); | ||
60 | return MEMTX_OK; | ||
61 | } | ||
62 | + case GICR_INMIR0: | ||
63 | + if (cs->gic->nmi_support) { | ||
64 | + gicr_write_bitmap_reg(cs, attrs, &cs->gicr_inmir0, value); | ||
65 | + } | ||
66 | + return MEMTX_OK; | ||
67 | + | ||
68 | case GICR_ICFGR0: | ||
69 | /* Register is all RAZ/WI or RAO/WI bits */ | ||
70 | return MEMTX_OK; | ||
71 | -- | ||
72 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Jinjie Ruan <ruanjinjie@huawei.com> | ||
1 | 2 | ||
3 | Add GICD_INMIR, GICD_INMIRnE register and support access GICD_INMIR0. | ||
4 | |||
5 | Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com> | ||
6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
8 | Message-id: 20240407081733.3231820-18-ruanjinjie@huawei.com | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
10 | --- | ||
11 | hw/intc/gicv3_internal.h | 2 ++ | ||
12 | hw/intc/arm_gicv3_dist.c | 34 ++++++++++++++++++++++++++++++++++ | ||
13 | 2 files changed, 36 insertions(+) | ||
14 | |||
15 | diff --git a/hw/intc/gicv3_internal.h b/hw/intc/gicv3_internal.h | ||
16 | index XXXXXXX..XXXXXXX 100644 | ||
17 | --- a/hw/intc/gicv3_internal.h | ||
18 | +++ b/hw/intc/gicv3_internal.h | ||
19 | @@ -XXX,XX +XXX,XX @@ | ||
20 | #define GICD_SGIR 0x0F00 | ||
21 | #define GICD_CPENDSGIR 0x0F10 | ||
22 | #define GICD_SPENDSGIR 0x0F20 | ||
23 | +#define GICD_INMIR 0x0F80 | ||
24 | +#define GICD_INMIRnE 0x3B00 | ||
25 | #define GICD_IROUTER 0x6000 | ||
26 | #define GICD_IDREGS 0xFFD0 | ||
27 | |||
28 | diff --git a/hw/intc/arm_gicv3_dist.c b/hw/intc/arm_gicv3_dist.c | ||
29 | index XXXXXXX..XXXXXXX 100644 | ||
30 | --- a/hw/intc/arm_gicv3_dist.c | ||
31 | +++ b/hw/intc/arm_gicv3_dist.c | ||
32 | @@ -XXX,XX +XXX,XX @@ static int gicd_ns_access(GICv3State *s, int irq) | ||
33 | return extract32(s->gicd_nsacr[irq / 16], (irq % 16) * 2, 2); | ||
34 | } | ||
35 | |||
36 | +static void gicd_write_bitmap_reg(GICv3State *s, MemTxAttrs attrs, | ||
37 | + uint32_t *bmp, maskfn *maskfn, | ||
38 | + int offset, uint32_t val) | ||
39 | +{ | ||
40 | + /* | ||
41 | + * Helper routine to implement writing to a "set" register | ||
42 | + * (GICD_INMIR, etc). | ||
43 | + * Semantics implemented here: | ||
44 | + * RAZ/WI for SGIs, PPIs, unimplemented IRQs | ||
45 | + * Bits corresponding to Group 0 or Secure Group 1 interrupts RAZ/WI. | ||
46 | + * offset should be the offset in bytes of the register from the start | ||
47 | + * of its group. | ||
48 | + */ | ||
49 | + int irq = offset * 8; | ||
50 | + | ||
51 | + if (irq < GIC_INTERNAL || irq >= s->num_irq) { | ||
52 | + return; | ||
53 | + } | ||
54 | + val &= mask_group_and_nsacr(s, attrs, maskfn, irq); | ||
55 | + *gic_bmp_ptr32(bmp, irq) = val; | ||
56 | + gicv3_update(s, irq, 32); | ||
57 | +} | ||
58 | + | ||
59 | static void gicd_write_set_bitmap_reg(GICv3State *s, MemTxAttrs attrs, | ||
60 | uint32_t *bmp, | ||
61 | maskfn *maskfn, | ||
62 | @@ -XXX,XX +XXX,XX @@ static bool gicd_readl(GICv3State *s, hwaddr offset, | ||
63 | /* RAZ/WI since affinity routing is always enabled */ | ||
64 | *data = 0; | ||
65 | return true; | ||
66 | + case GICD_INMIR ... GICD_INMIR + 0x7f: | ||
67 | + *data = (!s->nmi_support) ? 0 : | ||
68 | + gicd_read_bitmap_reg(s, attrs, s->nmi, NULL, | ||
69 | + offset - GICD_INMIR); | ||
70 | + return true; | ||
71 | case GICD_IROUTER ... GICD_IROUTER + 0x1fdf: | ||
72 | { | ||
73 | uint64_t r; | ||
74 | @@ -XXX,XX +XXX,XX @@ static bool gicd_writel(GICv3State *s, hwaddr offset, | ||
75 | case GICD_SPENDSGIR ... GICD_SPENDSGIR + 0xf: | ||
76 | /* RAZ/WI since affinity routing is always enabled */ | ||
77 | return true; | ||
78 | + case GICD_INMIR ... GICD_INMIR + 0x7f: | ||
79 | + if (s->nmi_support) { | ||
80 | + gicd_write_bitmap_reg(s, attrs, s->nmi, NULL, | ||
81 | + offset - GICD_INMIR, value); | ||
82 | + } | ||
83 | + return true; | ||
84 | case GICD_IROUTER ... GICD_IROUTER + 0x1fdf: | ||
85 | { | ||
86 | uint64_t r; | ||
87 | -- | ||
88 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Add the NMIAR CPU interface registers which deal with acknowledging NMI. | ||
1 | 2 | ||
3 | When introduce NMI interrupt, there are some updates to the semantics for the | ||
4 | register ICC_IAR1_EL1 and ICC_HPPIR1_EL1. For ICC_IAR1_EL1 register, it | ||
5 | should return 1022 if the intid has non-maskable property. And for | ||
6 | ICC_NMIAR1_EL1 register, it should return 1023 if the intid do not have | ||
7 | non-maskable property. Howerever, these are not necessary for ICC_HPPIR1_EL1 | ||
8 | register. | ||
9 | |||
10 | And the APR and RPR has NMI bits which should be handled correctly. | ||
11 | |||
12 | Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com> | ||
13 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
14 | [PMM: Separate out whether cpuif supports NMI from whether the | ||
15 | GIC proper (IRI) supports NMI] | ||
16 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
17 | Message-id: 20240407081733.3231820-19-ruanjinjie@huawei.com | ||
18 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
19 | --- | ||
20 | hw/intc/gicv3_internal.h | 5 + | ||
21 | include/hw/intc/arm_gicv3_common.h | 7 ++ | ||
22 | hw/intc/arm_gicv3_cpuif.c | 147 ++++++++++++++++++++++++++++- | ||
23 | hw/intc/trace-events | 1 + | ||
24 | 4 files changed, 155 insertions(+), 5 deletions(-) | ||
25 | |||
26 | diff --git a/hw/intc/gicv3_internal.h b/hw/intc/gicv3_internal.h | ||
27 | index XXXXXXX..XXXXXXX 100644 | ||
28 | --- a/hw/intc/gicv3_internal.h | ||
29 | +++ b/hw/intc/gicv3_internal.h | ||
30 | @@ -XXX,XX +XXX,XX @@ FIELD(GICR_VPENDBASER, VALID, 63, 1) | ||
31 | #define ICC_CTLR_EL3_A3V (1U << 15) | ||
32 | #define ICC_CTLR_EL3_NDS (1U << 17) | ||
33 | |||
34 | +#define ICC_AP1R_EL1_NMI (1ULL << 63) | ||
35 | +#define ICC_RPR_EL1_NSNMI (1ULL << 62) | ||
36 | +#define ICC_RPR_EL1_NMI (1ULL << 63) | ||
37 | + | ||
38 | #define ICH_VMCR_EL2_VENG0_SHIFT 0 | ||
39 | #define ICH_VMCR_EL2_VENG0 (1U << ICH_VMCR_EL2_VENG0_SHIFT) | ||
40 | #define ICH_VMCR_EL2_VENG1_SHIFT 1 | ||
41 | @@ -XXX,XX +XXX,XX @@ FIELD(VTE, RDBASE, 42, RDBASE_PROCNUM_LENGTH) | ||
42 | /* Special interrupt IDs */ | ||
43 | #define INTID_SECURE 1020 | ||
44 | #define INTID_NONSECURE 1021 | ||
45 | +#define INTID_NMI 1022 | ||
46 | #define INTID_SPURIOUS 1023 | ||
47 | |||
48 | /* Functions internal to the emulated GICv3 */ | ||
49 | diff --git a/include/hw/intc/arm_gicv3_common.h b/include/hw/intc/arm_gicv3_common.h | ||
50 | index XXXXXXX..XXXXXXX 100644 | ||
51 | --- a/include/hw/intc/arm_gicv3_common.h | ||
52 | +++ b/include/hw/intc/arm_gicv3_common.h | ||
53 | @@ -XXX,XX +XXX,XX @@ struct GICv3CPUState { | ||
54 | |||
55 | /* This is temporary working state, to avoid a malloc in gicv3_update() */ | ||
56 | bool seenbetter; | ||
57 | + | ||
58 | + /* | ||
59 | + * Whether the CPU interface has NMI support (FEAT_GICv3_NMI). The | ||
60 | + * CPU interface may support NMIs even when the GIC proper (what the | ||
61 | + * spec calls the IRI; the redistributors and distributor) does not. | ||
62 | + */ | ||
63 | + bool nmi_support; | ||
64 | }; | ||
65 | |||
66 | /* | ||
67 | diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c | ||
68 | index XXXXXXX..XXXXXXX 100644 | ||
69 | --- a/hw/intc/arm_gicv3_cpuif.c | ||
70 | +++ b/hw/intc/arm_gicv3_cpuif.c | ||
71 | @@ -XXX,XX +XXX,XX @@ | ||
72 | #include "hw/irq.h" | ||
73 | #include "cpu.h" | ||
74 | #include "target/arm/cpregs.h" | ||
75 | +#include "target/arm/cpu-features.h" | ||
76 | #include "sysemu/tcg.h" | ||
77 | #include "sysemu/qtest.h" | ||
78 | |||
79 | @@ -XXX,XX +XXX,XX @@ static uint64_t icv_iar_read(CPUARMState *env, const ARMCPRegInfo *ri) | ||
80 | return intid; | ||
81 | } | ||
82 | |||
83 | +static uint64_t icv_nmiar1_read(CPUARMState *env, const ARMCPRegInfo *ri) | ||
84 | +{ | ||
85 | + /* todo */ | ||
86 | + uint64_t intid = INTID_SPURIOUS; | ||
87 | + return intid; | ||
88 | +} | ||
89 | + | ||
90 | static uint32_t icc_fullprio_mask(GICv3CPUState *cs) | ||
91 | { | ||
92 | /* | ||
93 | @@ -XXX,XX +XXX,XX @@ static int icc_highest_active_prio(GICv3CPUState *cs) | ||
94 | */ | ||
95 | int i; | ||
96 | |||
97 | + if (cs->nmi_support) { | ||
98 | + /* | ||
99 | + * If an NMI is active this takes precedence over anything else | ||
100 | + * for priority purposes; the NMI bit is only in the AP1R0 bit. | ||
101 | + * We return here the effective priority of the NMI, which is | ||
102 | + * either 0x0 or 0x80. Callers will need to check NMI again for | ||
103 | + * purposes of either setting the RPR register bits or for | ||
104 | + * prioritization of NMI vs non-NMI. | ||
105 | + */ | ||
106 | + if (cs->icc_apr[GICV3_G1][0] & ICC_AP1R_EL1_NMI) { | ||
107 | + return 0; | ||
108 | + } | ||
109 | + if (cs->icc_apr[GICV3_G1NS][0] & ICC_AP1R_EL1_NMI) { | ||
110 | + return (cs->gic->gicd_ctlr & GICD_CTLR_DS) ? 0 : 0x80; | ||
111 | + } | ||
112 | + } | ||
113 | + | ||
114 | for (i = 0; i < icc_num_aprs(cs); i++) { | ||
115 | uint32_t apr = cs->icc_apr[GICV3_G0][i] | | ||
116 | cs->icc_apr[GICV3_G1][i] | cs->icc_apr[GICV3_G1NS][i]; | ||
117 | @@ -XXX,XX +XXX,XX @@ static bool icc_hppi_can_preempt(GICv3CPUState *cs) | ||
118 | */ | ||
119 | int rprio; | ||
120 | uint32_t mask; | ||
121 | + ARMCPU *cpu = ARM_CPU(cs->cpu); | ||
122 | + CPUARMState *env = &cpu->env; | ||
123 | |||
124 | if (icc_no_enabled_hppi(cs)) { | ||
125 | return false; | ||
126 | } | ||
127 | |||
128 | - if (cs->hppi.prio >= cs->icc_pmr_el1) { | ||
129 | + if (cs->hppi.nmi) { | ||
130 | + if (!(cs->gic->gicd_ctlr & GICD_CTLR_DS) && | ||
131 | + cs->hppi.grp == GICV3_G1NS) { | ||
132 | + if (cs->icc_pmr_el1 < 0x80) { | ||
133 | + return false; | ||
134 | + } | ||
135 | + if (arm_is_secure(env) && cs->icc_pmr_el1 == 0x80) { | ||
136 | + return false; | ||
137 | + } | ||
138 | + } | ||
139 | + } else if (cs->hppi.prio >= cs->icc_pmr_el1) { | ||
140 | /* Priority mask masks this interrupt */ | ||
141 | return false; | ||
142 | } | ||
143 | @@ -XXX,XX +XXX,XX @@ static bool icc_hppi_can_preempt(GICv3CPUState *cs) | ||
144 | return true; | ||
145 | } | ||
146 | |||
147 | + if (cs->hppi.nmi && (cs->hppi.prio & mask) == (rprio & mask)) { | ||
148 | + if (!(cs->icc_apr[cs->hppi.grp][0] & ICC_AP1R_EL1_NMI)) { | ||
149 | + return true; | ||
150 | + } | ||
151 | + } | ||
152 | + | ||
153 | return false; | ||
154 | } | ||
155 | |||
156 | @@ -XXX,XX +XXX,XX @@ static void icc_activate_irq(GICv3CPUState *cs, int irq) | ||
157 | int aprbit = prio >> (8 - cs->prebits); | ||
158 | int regno = aprbit / 32; | ||
159 | int regbit = aprbit % 32; | ||
160 | + bool nmi = cs->hppi.nmi; | ||
161 | |||
162 | - cs->icc_apr[cs->hppi.grp][regno] |= (1 << regbit); | ||
163 | + if (nmi) { | ||
164 | + cs->icc_apr[cs->hppi.grp][regno] |= ICC_AP1R_EL1_NMI; | ||
165 | + } else { | ||
166 | + cs->icc_apr[cs->hppi.grp][regno] |= (1 << regbit); | ||
167 | + } | ||
168 | |||
169 | if (irq < GIC_INTERNAL) { | ||
170 | cs->gicr_iactiver0 = deposit32(cs->gicr_iactiver0, irq, 1, 1); | ||
171 | @@ -XXX,XX +XXX,XX @@ static uint64_t icc_iar0_read(CPUARMState *env, const ARMCPRegInfo *ri) | ||
172 | static uint64_t icc_iar1_read(CPUARMState *env, const ARMCPRegInfo *ri) | ||
173 | { | ||
174 | GICv3CPUState *cs = icc_cs_from_env(env); | ||
175 | + int el = arm_current_el(env); | ||
176 | uint64_t intid; | ||
177 | |||
178 | if (icv_access(env, HCR_IMO)) { | ||
179 | @@ -XXX,XX +XXX,XX @@ static uint64_t icc_iar1_read(CPUARMState *env, const ARMCPRegInfo *ri) | ||
180 | } | ||
181 | |||
182 | if (!gicv3_intid_is_special(intid)) { | ||
183 | - icc_activate_irq(cs, intid); | ||
184 | + if (cs->hppi.nmi && env->cp15.sctlr_el[el] & SCTLR_NMI) { | ||
185 | + intid = INTID_NMI; | ||
186 | + } else { | ||
187 | + icc_activate_irq(cs, intid); | ||
188 | + } | ||
189 | } | ||
190 | |||
191 | trace_gicv3_icc_iar1_read(gicv3_redist_affid(cs), intid); | ||
192 | return intid; | ||
193 | } | ||
194 | |||
195 | +static uint64_t icc_nmiar1_read(CPUARMState *env, const ARMCPRegInfo *ri) | ||
196 | +{ | ||
197 | + GICv3CPUState *cs = icc_cs_from_env(env); | ||
198 | + uint64_t intid; | ||
199 | + | ||
200 | + if (icv_access(env, HCR_IMO)) { | ||
201 | + return icv_nmiar1_read(env, ri); | ||
202 | + } | ||
203 | + | ||
204 | + if (!icc_hppi_can_preempt(cs)) { | ||
205 | + intid = INTID_SPURIOUS; | ||
206 | + } else { | ||
207 | + intid = icc_hppir1_value(cs, env); | ||
208 | + } | ||
209 | + | ||
210 | + if (!gicv3_intid_is_special(intid)) { | ||
211 | + if (!cs->hppi.nmi) { | ||
212 | + intid = INTID_SPURIOUS; | ||
213 | + } else { | ||
214 | + icc_activate_irq(cs, intid); | ||
215 | + } | ||
216 | + } | ||
217 | + | ||
218 | + trace_gicv3_icc_nmiar1_read(gicv3_redist_affid(cs), intid); | ||
219 | + return intid; | ||
220 | +} | ||
221 | + | ||
222 | static void icc_drop_prio(GICv3CPUState *cs, int grp) | ||
223 | { | ||
224 | /* Drop the priority of the currently active interrupt in | ||
225 | @@ -XXX,XX +XXX,XX @@ static void icc_drop_prio(GICv3CPUState *cs, int grp) | ||
226 | if (!*papr) { | ||
227 | continue; | ||
228 | } | ||
229 | + | ||
230 | + if (i == 0 && cs->nmi_support && (*papr & ICC_AP1R_EL1_NMI)) { | ||
231 | + *papr &= (~ICC_AP1R_EL1_NMI); | ||
232 | + break; | ||
233 | + } | ||
234 | + | ||
235 | /* Clear the lowest set bit */ | ||
236 | *papr &= *papr - 1; | ||
237 | break; | ||
238 | @@ -XXX,XX +XXX,XX @@ static int icc_highest_active_group(GICv3CPUState *cs) | ||
239 | */ | ||
240 | int i; | ||
241 | |||
242 | + if (cs->nmi_support) { | ||
243 | + if (cs->icc_apr[GICV3_G1][0] & ICC_AP1R_EL1_NMI) { | ||
244 | + return GICV3_G1; | ||
245 | + } | ||
246 | + if (cs->icc_apr[GICV3_G1NS][0] & ICC_AP1R_EL1_NMI) { | ||
247 | + return GICV3_G1NS; | ||
248 | + } | ||
249 | + } | ||
250 | + | ||
251 | for (i = 0; i < ARRAY_SIZE(cs->icc_apr[0]); i++) { | ||
252 | int g0ctz = ctz32(cs->icc_apr[GICV3_G0][i]); | ||
253 | int g1ctz = ctz32(cs->icc_apr[GICV3_G1][i]); | ||
254 | @@ -XXX,XX +XXX,XX @@ static void icc_ap_write(CPUARMState *env, const ARMCPRegInfo *ri, | ||
255 | return; | ||
256 | } | ||
257 | |||
258 | - cs->icc_apr[grp][regno] = value & 0xFFFFFFFFU; | ||
259 | + if (cs->nmi_support) { | ||
260 | + cs->icc_apr[grp][regno] = value & (0xFFFFFFFFU | ICC_AP1R_EL1_NMI); | ||
261 | + } else { | ||
262 | + cs->icc_apr[grp][regno] = value & 0xFFFFFFFFU; | ||
263 | + } | ||
264 | gicv3_cpuif_update(cs); | ||
265 | } | ||
266 | |||
267 | @@ -XXX,XX +XXX,XX @@ static void icc_dir_write(CPUARMState *env, const ARMCPRegInfo *ri, | ||
268 | static uint64_t icc_rpr_read(CPUARMState *env, const ARMCPRegInfo *ri) | ||
269 | { | ||
270 | GICv3CPUState *cs = icc_cs_from_env(env); | ||
271 | - int prio; | ||
272 | + uint64_t prio; | ||
273 | |||
274 | if (icv_access(env, HCR_FMO | HCR_IMO)) { | ||
275 | return icv_rpr_read(env, ri); | ||
276 | @@ -XXX,XX +XXX,XX @@ static uint64_t icc_rpr_read(CPUARMState *env, const ARMCPRegInfo *ri) | ||
277 | } | ||
278 | } | ||
279 | |||
280 | + if (cs->nmi_support) { | ||
281 | + /* NMI info is reported in the high bits of RPR */ | ||
282 | + if (arm_feature(env, ARM_FEATURE_EL3) && !arm_is_secure(env)) { | ||
283 | + if (cs->icc_apr[GICV3_G1NS][0] & ICC_AP1R_EL1_NMI) { | ||
284 | + prio |= ICC_RPR_EL1_NMI; | ||
285 | + } | ||
286 | + } else { | ||
287 | + if (cs->icc_apr[GICV3_G1NS][0] & ICC_AP1R_EL1_NMI) { | ||
288 | + prio |= ICC_RPR_EL1_NSNMI; | ||
289 | + } | ||
290 | + if (cs->icc_apr[GICV3_G1][0] & ICC_AP1R_EL1_NMI) { | ||
291 | + prio |= ICC_RPR_EL1_NMI; | ||
292 | + } | ||
293 | + } | ||
294 | + } | ||
295 | + | ||
296 | trace_gicv3_icc_rpr_read(gicv3_redist_affid(cs), prio); | ||
297 | return prio; | ||
298 | } | ||
299 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo gicv3_cpuif_icc_apxr23_reginfo[] = { | ||
300 | }, | ||
301 | }; | ||
302 | |||
303 | +static const ARMCPRegInfo gicv3_cpuif_gicv3_nmi_reginfo[] = { | ||
304 | + { .name = "ICC_NMIAR1_EL1", .state = ARM_CP_STATE_BOTH, | ||
305 | + .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 9, .opc2 = 5, | ||
306 | + .type = ARM_CP_IO | ARM_CP_NO_RAW, | ||
307 | + .access = PL1_R, .accessfn = gicv3_irq_access, | ||
308 | + .readfn = icc_nmiar1_read, | ||
309 | + }, | ||
310 | +}; | ||
311 | + | ||
312 | static uint64_t ich_ap_read(CPUARMState *env, const ARMCPRegInfo *ri) | ||
313 | { | ||
314 | GICv3CPUState *cs = icc_cs_from_env(env); | ||
315 | @@ -XXX,XX +XXX,XX @@ void gicv3_init_cpuif(GICv3State *s) | ||
316 | */ | ||
317 | define_arm_cp_regs(cpu, gicv3_cpuif_reginfo); | ||
318 | |||
319 | + /* | ||
320 | + * If the CPU implements FEAT_NMI and FEAT_GICv3 it must also | ||
321 | + * implement FEAT_GICv3_NMI, which is the CPU interface part | ||
322 | + * of NMI support. This is distinct from whether the GIC proper | ||
323 | + * (redistributors and distributor) have NMI support. In QEMU | ||
324 | + * that is a property of the GIC device in s->nmi_support; | ||
325 | + * cs->nmi_support indicates the CPU interface's support. | ||
326 | + */ | ||
327 | + if (cpu_isar_feature(aa64_nmi, cpu)) { | ||
328 | + cs->nmi_support = true; | ||
329 | + define_arm_cp_regs(cpu, gicv3_cpuif_gicv3_nmi_reginfo); | ||
330 | + } | ||
331 | + | ||
332 | /* | ||
333 | * The CPU implementation specifies the number of supported | ||
334 | * bits of physical priority. For backwards compatibility | ||
335 | diff --git a/hw/intc/trace-events b/hw/intc/trace-events | ||
336 | index XXXXXXX..XXXXXXX 100644 | ||
337 | --- a/hw/intc/trace-events | ||
338 | +++ b/hw/intc/trace-events | ||
339 | @@ -XXX,XX +XXX,XX @@ gicv3_cpuif_set_irqs(uint32_t cpuid, int fiqlevel, int irqlevel) "GICv3 CPU i/f | ||
340 | gicv3_icc_generate_sgi(uint32_t cpuid, int irq, int irm, uint32_t aff, uint32_t targetlist) "GICv3 CPU i/f 0x%x generating SGI %d IRM %d target affinity 0x%xxx targetlist 0x%x" | ||
341 | gicv3_icc_iar0_read(uint32_t cpu, uint64_t val) "GICv3 ICC_IAR0 read cpu 0x%x value 0x%" PRIx64 | ||
342 | gicv3_icc_iar1_read(uint32_t cpu, uint64_t val) "GICv3 ICC_IAR1 read cpu 0x%x value 0x%" PRIx64 | ||
343 | +gicv3_icc_nmiar1_read(uint32_t cpu, uint64_t val) "GICv3 ICC_NMIAR1 read cpu 0x%x value 0x%" PRIx64 | ||
344 | gicv3_icc_eoir_write(int grp, uint32_t cpu, uint64_t val) "GICv3 ICC_EOIR%d write cpu 0x%x value 0x%" PRIx64 | ||
345 | gicv3_icc_hppir0_read(uint32_t cpu, uint64_t val) "GICv3 ICC_HPPIR0 read cpu 0x%x value 0x%" PRIx64 | ||
346 | gicv3_icc_hppir1_read(uint32_t cpu, uint64_t val) "GICv3 ICC_HPPIR1 read cpu 0x%x value 0x%" PRIx64 | ||
347 | -- | ||
348 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | 1 | Implement icv_nmiar1_read() for icc_nmiar1_read(), so add definition for | |
2 | ICH_LR_EL2.NMI and ICH_AP1R_EL2.NMI bit. | ||
3 | |||
4 | If FEAT_GICv3_NMI is supported, ich_ap_write() should consider ICV_AP1R_EL1.NMI | ||
5 | bit. In icv_activate_irq() and icv_eoir_write(), the ICV_AP1R_EL1.NMI bit | ||
6 | should be set or clear according to the Non-maskable property. And the RPR | ||
7 | priority should also update the NMI bit according to the APR priority NMI bit. | ||
8 | |||
9 | By the way, add gicv3_icv_nmiar1_read trace event. | ||
10 | |||
11 | If the hpp irq is a NMI, the icv iar read should return 1022 and trap for | ||
12 | NMI again | ||
13 | |||
14 | Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com> | ||
15 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
16 | [PMM: use cs->nmi_support instead of cs->gic->nmi_support] | ||
17 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
18 | Message-id: 20240407081733.3231820-20-ruanjinjie@huawei.com | ||
19 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
20 | --- | ||
21 | hw/intc/gicv3_internal.h | 4 ++ | ||
22 | hw/intc/arm_gicv3_cpuif.c | 105 +++++++++++++++++++++++++++++++++----- | ||
23 | hw/intc/trace-events | 1 + | ||
24 | 3 files changed, 98 insertions(+), 12 deletions(-) | ||
25 | |||
26 | diff --git a/hw/intc/gicv3_internal.h b/hw/intc/gicv3_internal.h | ||
27 | index XXXXXXX..XXXXXXX 100644 | ||
28 | --- a/hw/intc/gicv3_internal.h | ||
29 | +++ b/hw/intc/gicv3_internal.h | ||
30 | @@ -XXX,XX +XXX,XX @@ FIELD(GICR_VPENDBASER, VALID, 63, 1) | ||
31 | #define ICH_LR_EL2_PRIORITY_SHIFT 48 | ||
32 | #define ICH_LR_EL2_PRIORITY_LENGTH 8 | ||
33 | #define ICH_LR_EL2_PRIORITY_MASK (0xffULL << ICH_LR_EL2_PRIORITY_SHIFT) | ||
34 | +#define ICH_LR_EL2_NMI (1ULL << 59) | ||
35 | #define ICH_LR_EL2_GROUP (1ULL << 60) | ||
36 | #define ICH_LR_EL2_HW (1ULL << 61) | ||
37 | #define ICH_LR_EL2_STATE_SHIFT 62 | ||
38 | @@ -XXX,XX +XXX,XX @@ FIELD(GICR_VPENDBASER, VALID, 63, 1) | ||
39 | #define ICH_VTR_EL2_PREBITS_SHIFT 26 | ||
40 | #define ICH_VTR_EL2_PRIBITS_SHIFT 29 | ||
41 | |||
42 | +#define ICV_AP1R_EL1_NMI (1ULL << 63) | ||
43 | +#define ICV_RPR_EL1_NMI (1ULL << 63) | ||
44 | + | ||
45 | /* ITS Registers */ | ||
46 | |||
47 | FIELD(GITS_BASER, SIZE, 0, 8) | ||
48 | diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c | ||
49 | index XXXXXXX..XXXXXXX 100644 | ||
50 | --- a/hw/intc/arm_gicv3_cpuif.c | ||
51 | +++ b/hw/intc/arm_gicv3_cpuif.c | ||
52 | @@ -XXX,XX +XXX,XX @@ static int ich_highest_active_virt_prio(GICv3CPUState *cs) | ||
53 | int i; | ||
54 | int aprmax = ich_num_aprs(cs); | ||
55 | |||
56 | + if (cs->ich_apr[GICV3_G1NS][0] & ICV_AP1R_EL1_NMI) { | ||
57 | + return 0x0; | ||
58 | + } | ||
59 | + | ||
60 | for (i = 0; i < aprmax; i++) { | ||
61 | uint32_t apr = cs->ich_apr[GICV3_G0][i] | | ||
62 | cs->ich_apr[GICV3_G1NS][i]; | ||
63 | @@ -XXX,XX +XXX,XX @@ static int hppvi_index(GICv3CPUState *cs) | ||
64 | * correct behaviour. | ||
65 | */ | ||
66 | int prio = 0xff; | ||
67 | + bool nmi = false; | ||
68 | |||
69 | if (!(cs->ich_vmcr_el2 & (ICH_VMCR_EL2_VENG0 | ICH_VMCR_EL2_VENG1))) { | ||
70 | /* Both groups disabled, definitely nothing to do */ | ||
71 | @@ -XXX,XX +XXX,XX @@ static int hppvi_index(GICv3CPUState *cs) | ||
72 | |||
73 | for (i = 0; i < cs->num_list_regs; i++) { | ||
74 | uint64_t lr = cs->ich_lr_el2[i]; | ||
75 | + bool thisnmi; | ||
76 | int thisprio; | ||
77 | |||
78 | if (ich_lr_state(lr) != ICH_LR_EL2_STATE_PENDING) { | ||
79 | @@ -XXX,XX +XXX,XX @@ static int hppvi_index(GICv3CPUState *cs) | ||
80 | } | ||
81 | } | ||
82 | |||
83 | + thisnmi = lr & ICH_LR_EL2_NMI; | ||
84 | thisprio = ich_lr_prio(lr); | ||
85 | |||
86 | - if (thisprio < prio) { | ||
87 | + if ((thisprio < prio) || ((thisprio == prio) && (thisnmi & (!nmi)))) { | ||
88 | prio = thisprio; | ||
89 | + nmi = thisnmi; | ||
90 | idx = i; | ||
91 | } | ||
92 | } | ||
93 | @@ -XXX,XX +XXX,XX @@ static bool icv_hppi_can_preempt(GICv3CPUState *cs, uint64_t lr) | ||
94 | * equivalent of these checks. | ||
95 | */ | ||
96 | int grp; | ||
97 | + bool is_nmi; | ||
98 | uint32_t mask, prio, rprio, vpmr; | ||
99 | |||
100 | if (!(cs->ich_hcr_el2 & ICH_HCR_EL2_EN)) { | ||
101 | @@ -XXX,XX +XXX,XX @@ static bool icv_hppi_can_preempt(GICv3CPUState *cs, uint64_t lr) | ||
102 | */ | ||
103 | |||
104 | prio = ich_lr_prio(lr); | ||
105 | + is_nmi = lr & ICH_LR_EL2_NMI; | ||
106 | vpmr = extract64(cs->ich_vmcr_el2, ICH_VMCR_EL2_VPMR_SHIFT, | ||
107 | ICH_VMCR_EL2_VPMR_LENGTH); | ||
108 | |||
109 | - if (prio >= vpmr) { | ||
110 | + if (!is_nmi && prio >= vpmr) { | ||
111 | /* Priority mask masks this interrupt */ | ||
112 | return false; | ||
113 | } | ||
114 | @@ -XXX,XX +XXX,XX @@ static bool icv_hppi_can_preempt(GICv3CPUState *cs, uint64_t lr) | ||
115 | return true; | ||
116 | } | ||
117 | |||
118 | + if ((prio & mask) == (rprio & mask) && is_nmi && | ||
119 | + !(cs->ich_apr[GICV3_G1NS][0] & ICV_AP1R_EL1_NMI)) { | ||
120 | + return true; | ||
121 | + } | ||
122 | + | ||
123 | return false; | ||
124 | } | ||
125 | |||
126 | @@ -XXX,XX +XXX,XX @@ static void icv_ap_write(CPUARMState *env, const ARMCPRegInfo *ri, | ||
127 | |||
128 | trace_gicv3_icv_ap_write(ri->crm & 1, regno, gicv3_redist_affid(cs), value); | ||
129 | |||
130 | - cs->ich_apr[grp][regno] = value & 0xFFFFFFFFU; | ||
131 | + if (cs->nmi_support) { | ||
132 | + cs->ich_apr[grp][regno] = value & (0xFFFFFFFFU | ICV_AP1R_EL1_NMI); | ||
133 | + } else { | ||
134 | + cs->ich_apr[grp][regno] = value & 0xFFFFFFFFU; | ||
135 | + } | ||
136 | |||
137 | gicv3_cpuif_virt_irq_fiq_update(cs); | ||
138 | return; | ||
139 | @@ -XXX,XX +XXX,XX @@ static void icv_ctlr_write(CPUARMState *env, const ARMCPRegInfo *ri, | ||
140 | static uint64_t icv_rpr_read(CPUARMState *env, const ARMCPRegInfo *ri) | ||
141 | { | ||
142 | GICv3CPUState *cs = icc_cs_from_env(env); | ||
143 | - int prio = ich_highest_active_virt_prio(cs); | ||
144 | + uint64_t prio = ich_highest_active_virt_prio(cs); | ||
145 | + | ||
146 | + if (cs->ich_apr[GICV3_G1NS][0] & ICV_AP1R_EL1_NMI) { | ||
147 | + prio |= ICV_RPR_EL1_NMI; | ||
148 | + } | ||
149 | |||
150 | trace_gicv3_icv_rpr_read(gicv3_redist_affid(cs), prio); | ||
151 | return prio; | ||
152 | @@ -XXX,XX +XXX,XX @@ static void icv_activate_irq(GICv3CPUState *cs, int idx, int grp) | ||
153 | */ | ||
154 | uint32_t mask = icv_gprio_mask(cs, grp); | ||
155 | int prio = ich_lr_prio(cs->ich_lr_el2[idx]) & mask; | ||
156 | + bool nmi = cs->ich_lr_el2[idx] & ICH_LR_EL2_NMI; | ||
157 | int aprbit = prio >> (8 - cs->vprebits); | ||
158 | int regno = aprbit / 32; | ||
159 | int regbit = aprbit % 32; | ||
160 | |||
161 | cs->ich_lr_el2[idx] &= ~ICH_LR_EL2_STATE_PENDING_BIT; | ||
162 | cs->ich_lr_el2[idx] |= ICH_LR_EL2_STATE_ACTIVE_BIT; | ||
163 | - cs->ich_apr[grp][regno] |= (1 << regbit); | ||
164 | + | ||
165 | + if (nmi) { | ||
166 | + cs->ich_apr[grp][regno] |= ICV_AP1R_EL1_NMI; | ||
167 | + } else { | ||
168 | + cs->ich_apr[grp][regno] |= (1 << regbit); | ||
169 | + } | ||
170 | } | ||
171 | |||
172 | static void icv_activate_vlpi(GICv3CPUState *cs) | ||
173 | @@ -XXX,XX +XXX,XX @@ static uint64_t icv_iar_read(CPUARMState *env, const ARMCPRegInfo *ri) | ||
174 | int grp = ri->crm == 8 ? GICV3_G0 : GICV3_G1NS; | ||
175 | int idx = hppvi_index(cs); | ||
176 | uint64_t intid = INTID_SPURIOUS; | ||
177 | + int el = arm_current_el(env); | ||
178 | |||
179 | if (idx == HPPVI_INDEX_VLPI) { | ||
180 | if (cs->hppvlpi.grp == grp && icv_hppvlpi_can_preempt(cs)) { | ||
181 | @@ -XXX,XX +XXX,XX @@ static uint64_t icv_iar_read(CPUARMState *env, const ARMCPRegInfo *ri) | ||
182 | } else if (idx >= 0) { | ||
183 | uint64_t lr = cs->ich_lr_el2[idx]; | ||
184 | int thisgrp = (lr & ICH_LR_EL2_GROUP) ? GICV3_G1NS : GICV3_G0; | ||
185 | + bool nmi = env->cp15.sctlr_el[el] & SCTLR_NMI && lr & ICH_LR_EL2_NMI; | ||
186 | |||
187 | if (thisgrp == grp && icv_hppi_can_preempt(cs, lr)) { | ||
188 | intid = ich_lr_vintid(lr); | ||
189 | if (!gicv3_intid_is_special(intid)) { | ||
190 | - icv_activate_irq(cs, idx, grp); | ||
191 | + if (!nmi) { | ||
192 | + icv_activate_irq(cs, idx, grp); | ||
193 | + } else { | ||
194 | + intid = INTID_NMI; | ||
195 | + } | ||
196 | } else { | ||
197 | /* Interrupt goes from Pending to Invalid */ | ||
198 | cs->ich_lr_el2[idx] &= ~ICH_LR_EL2_STATE_PENDING_BIT; | ||
199 | @@ -XXX,XX +XXX,XX @@ static uint64_t icv_iar_read(CPUARMState *env, const ARMCPRegInfo *ri) | ||
200 | |||
201 | static uint64_t icv_nmiar1_read(CPUARMState *env, const ARMCPRegInfo *ri) | ||
202 | { | ||
203 | - /* todo */ | ||
204 | + GICv3CPUState *cs = icc_cs_from_env(env); | ||
205 | + int idx = hppvi_index(cs); | ||
206 | uint64_t intid = INTID_SPURIOUS; | ||
207 | + | ||
208 | + if (idx >= 0 && idx != HPPVI_INDEX_VLPI) { | ||
209 | + uint64_t lr = cs->ich_lr_el2[idx]; | ||
210 | + int thisgrp = (lr & ICH_LR_EL2_GROUP) ? GICV3_G1NS : GICV3_G0; | ||
211 | + | ||
212 | + if ((thisgrp == GICV3_G1NS) && icv_hppi_can_preempt(cs, lr)) { | ||
213 | + intid = ich_lr_vintid(lr); | ||
214 | + if (!gicv3_intid_is_special(intid)) { | ||
215 | + if (lr & ICH_LR_EL2_NMI) { | ||
216 | + icv_activate_irq(cs, idx, GICV3_G1NS); | ||
217 | + } else { | ||
218 | + intid = INTID_SPURIOUS; | ||
219 | + } | ||
220 | + } else { | ||
221 | + /* Interrupt goes from Pending to Invalid */ | ||
222 | + cs->ich_lr_el2[idx] &= ~ICH_LR_EL2_STATE_PENDING_BIT; | ||
223 | + /* | ||
224 | + * We will now return the (bogus) ID from the list register, | ||
225 | + * as per the pseudocode. | ||
226 | + */ | ||
227 | + } | ||
228 | + } | ||
229 | + } | ||
230 | + | ||
231 | + trace_gicv3_icv_nmiar1_read(gicv3_redist_affid(cs), intid); | ||
232 | + | ||
233 | + gicv3_cpuif_virt_update(cs); | ||
234 | + | ||
235 | return intid; | ||
236 | } | ||
237 | |||
238 | @@ -XXX,XX +XXX,XX @@ static void icv_increment_eoicount(GICv3CPUState *cs) | ||
239 | ICH_HCR_EL2_EOICOUNT_LENGTH, eoicount + 1); | ||
240 | } | ||
241 | |||
242 | -static int icv_drop_prio(GICv3CPUState *cs) | ||
243 | +static int icv_drop_prio(GICv3CPUState *cs, bool *nmi) | ||
244 | { | ||
245 | /* Drop the priority of the currently active virtual interrupt | ||
246 | * (favouring group 0 if there is a set active bit at | ||
247 | @@ -XXX,XX +XXX,XX @@ static int icv_drop_prio(GICv3CPUState *cs) | ||
248 | continue; | ||
249 | } | ||
250 | |||
251 | + if (i == 0 && cs->nmi_support && (*papr1 & ICV_AP1R_EL1_NMI)) { | ||
252 | + *papr1 &= (~ICV_AP1R_EL1_NMI); | ||
253 | + *nmi = true; | ||
254 | + return 0xff; | ||
255 | + } | ||
256 | + | ||
257 | /* We can't just use the bit-twiddling hack icc_drop_prio() does | ||
258 | * because we need to return the bit number we cleared so | ||
259 | * it can be compared against the list register's priority field. | ||
260 | @@ -XXX,XX +XXX,XX @@ static void icv_eoir_write(CPUARMState *env, const ARMCPRegInfo *ri, | ||
261 | int irq = value & 0xffffff; | ||
262 | int grp = ri->crm == 8 ? GICV3_G0 : GICV3_G1NS; | ||
263 | int idx, dropprio; | ||
264 | + bool nmi = false; | ||
265 | |||
266 | trace_gicv3_icv_eoir_write(ri->crm == 8 ? 0 : 1, | ||
267 | gicv3_redist_affid(cs), value); | ||
268 | @@ -XXX,XX +XXX,XX @@ static void icv_eoir_write(CPUARMState *env, const ARMCPRegInfo *ri, | ||
269 | * error checks" (because that lets us avoid scanning the AP | ||
270 | * registers twice). | ||
271 | */ | ||
272 | - dropprio = icv_drop_prio(cs); | ||
273 | - if (dropprio == 0xff) { | ||
274 | + dropprio = icv_drop_prio(cs, &nmi); | ||
275 | + if (dropprio == 0xff && !nmi) { | ||
276 | /* No active interrupt. It is CONSTRAINED UNPREDICTABLE | ||
277 | * whether the list registers are checked in this | ||
278 | * situation; we choose not to. | ||
279 | @@ -XXX,XX +XXX,XX @@ static void icv_eoir_write(CPUARMState *env, const ARMCPRegInfo *ri, | ||
280 | uint64_t lr = cs->ich_lr_el2[idx]; | ||
281 | int thisgrp = (lr & ICH_LR_EL2_GROUP) ? GICV3_G1NS : GICV3_G0; | ||
282 | int lr_gprio = ich_lr_prio(lr) & icv_gprio_mask(cs, grp); | ||
283 | + bool thisnmi = lr & ICH_LR_EL2_NMI; | ||
284 | |||
285 | - if (thisgrp == grp && lr_gprio == dropprio) { | ||
286 | + if (thisgrp == grp && (lr_gprio == dropprio || (thisnmi & nmi))) { | ||
287 | if (!icv_eoi_split(env, cs) || irq >= GICV3_LPI_INTID_START) { | ||
288 | /* | ||
289 | * Priority drop and deactivate not split: deactivate irq now. | ||
290 | @@ -XXX,XX +XXX,XX @@ static void ich_ap_write(CPUARMState *env, const ARMCPRegInfo *ri, | ||
291 | |||
292 | trace_gicv3_ich_ap_write(ri->crm & 1, regno, gicv3_redist_affid(cs), value); | ||
293 | |||
294 | - cs->ich_apr[grp][regno] = value & 0xFFFFFFFFU; | ||
295 | + if (cs->nmi_support) { | ||
296 | + cs->ich_apr[grp][regno] = value & (0xFFFFFFFFU | ICV_AP1R_EL1_NMI); | ||
297 | + } else { | ||
298 | + cs->ich_apr[grp][regno] = value & 0xFFFFFFFFU; | ||
299 | + } | ||
300 | gicv3_cpuif_virt_irq_fiq_update(cs); | ||
301 | } | ||
302 | |||
303 | @@ -XXX,XX +XXX,XX @@ static void ich_lr_write(CPUARMState *env, const ARMCPRegInfo *ri, | ||
304 | 8 - cs->vpribits, 0); | ||
305 | } | ||
306 | |||
307 | + /* Enforce RES0 bit in NMI field when FEAT_GICv3_NMI is not implemented */ | ||
308 | + if (!cs->nmi_support) { | ||
309 | + value &= ~ICH_LR_EL2_NMI; | ||
310 | + } | ||
311 | + | ||
312 | cs->ich_lr_el2[regno] = value; | ||
313 | gicv3_cpuif_virt_update(cs); | ||
314 | } | ||
315 | diff --git a/hw/intc/trace-events b/hw/intc/trace-events | ||
316 | index XXXXXXX..XXXXXXX 100644 | ||
317 | --- a/hw/intc/trace-events | ||
318 | +++ b/hw/intc/trace-events | ||
319 | @@ -XXX,XX +XXX,XX @@ gicv3_icv_rpr_read(uint32_t cpu, uint64_t val) "GICv3 ICV_RPR read cpu 0x%x valu | ||
320 | gicv3_icv_hppir_read(int grp, uint32_t cpu, uint64_t val) "GICv3 ICV_HPPIR%d read cpu 0x%x value 0x%" PRIx64 | ||
321 | gicv3_icv_dir_write(uint32_t cpu, uint64_t val) "GICv3 ICV_DIR write cpu 0x%x value 0x%" PRIx64 | ||
322 | gicv3_icv_iar_read(int grp, uint32_t cpu, uint64_t val) "GICv3 ICV_IAR%d read cpu 0x%x value 0x%" PRIx64 | ||
323 | +gicv3_icv_nmiar1_read(uint32_t cpu, uint64_t val) "GICv3 ICV_NMIAR1 read cpu 0x%x value 0x%" PRIx64 | ||
324 | gicv3_icv_eoir_write(int grp, uint32_t cpu, uint64_t val) "GICv3 ICV_EOIR%d write cpu 0x%x value 0x%" PRIx64 | ||
325 | gicv3_cpuif_virt_update(uint32_t cpuid, int idx, int hppvlpi, int grp, int prio) "GICv3 CPU i/f 0x%x virt HPPI update LR index %d HPPVLPI %d grp %d prio %d" | ||
326 | gicv3_cpuif_virt_set_irqs(uint32_t cpuid, int fiqlevel, int irqlevel) "GICv3 CPU i/f 0x%x virt HPPI update: setting FIQ %d IRQ %d" | ||
327 | -- | ||
328 | 2.34.1 | diff view generated by jsdifflib |
1 | From: Leif Lindholm <leif@nuviainc.com> | 1 | From: Jinjie Ruan <ruanjinjie@huawei.com> |
---|---|---|---|
2 | 2 | ||
3 | SBSS -> SSBS | 3 | If GICD_CTLR_DS bit is zero and the NMI is non-secure, the NMI priority is |
4 | higher than 0x80, otherwise it is higher than 0x0. And save the interrupt | ||
5 | non-maskable property in hppi.nmi to deliver NMI exception. Since both GICR | ||
6 | and GICD can deliver NMI, it is both necessary to check whether the pending | ||
7 | irq is NMI in gicv3_redist_update_noirqset and gicv3_update_noirqset. | ||
4 | 8 | ||
5 | Signed-off-by: Leif Lindholm <leif@nuviainc.com> | 9 | Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com> |
6 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 10 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 11 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
8 | Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com> | 12 | Message-id: 20240407081733.3231820-21-ruanjinjie@huawei.com |
9 | Message-id: 20210108185154.8108-2-leif@nuviainc.com | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
11 | --- | 14 | --- |
12 | target/arm/cpu.h | 2 +- | 15 | hw/intc/arm_gicv3.c | 67 +++++++++++++++++++++++++++++++++----- |
13 | 1 file changed, 1 insertion(+), 1 deletion(-) | 16 | hw/intc/arm_gicv3_common.c | 3 ++ |
17 | hw/intc/arm_gicv3_redist.c | 3 ++ | ||
18 | 3 files changed, 64 insertions(+), 9 deletions(-) | ||
14 | 19 | ||
15 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | 20 | diff --git a/hw/intc/arm_gicv3.c b/hw/intc/arm_gicv3.c |
16 | index XXXXXXX..XXXXXXX 100644 | 21 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/target/arm/cpu.h | 22 | --- a/hw/intc/arm_gicv3.c |
18 | +++ b/target/arm/cpu.h | 23 | +++ b/hw/intc/arm_gicv3.c |
19 | @@ -XXX,XX +XXX,XX @@ FIELD(ID_AA64PFR0, RAS, 28, 4) | 24 | @@ -XXX,XX +XXX,XX @@ |
20 | FIELD(ID_AA64PFR0, SVE, 32, 4) | 25 | #include "hw/intc/arm_gicv3.h" |
21 | 26 | #include "gicv3_internal.h" | |
22 | FIELD(ID_AA64PFR1, BT, 0, 4) | 27 | |
23 | -FIELD(ID_AA64PFR1, SBSS, 4, 4) | 28 | -static bool irqbetter(GICv3CPUState *cs, int irq, uint8_t prio) |
24 | +FIELD(ID_AA64PFR1, SSBS, 4, 4) | 29 | +static bool irqbetter(GICv3CPUState *cs, int irq, uint8_t prio, bool nmi) |
25 | FIELD(ID_AA64PFR1, MTE, 8, 4) | 30 | { |
26 | FIELD(ID_AA64PFR1, RAS_FRAC, 12, 4) | 31 | /* Return true if this IRQ at this priority should take |
32 | * precedence over the current recorded highest priority | ||
33 | @@ -XXX,XX +XXX,XX @@ static bool irqbetter(GICv3CPUState *cs, int irq, uint8_t prio) | ||
34 | * is the same as this one (a property which the calling code | ||
35 | * relies on). | ||
36 | */ | ||
37 | - if (prio < cs->hppi.prio) { | ||
38 | - return true; | ||
39 | + if (prio != cs->hppi.prio) { | ||
40 | + return prio < cs->hppi.prio; | ||
41 | } | ||
42 | + | ||
43 | + /* | ||
44 | + * The same priority IRQ with non-maskable property should signal to | ||
45 | + * the CPU as it have the priority higher than the labelled 0x80 or 0x00. | ||
46 | + */ | ||
47 | + if (nmi != cs->hppi.nmi) { | ||
48 | + return nmi; | ||
49 | + } | ||
50 | + | ||
51 | /* If multiple pending interrupts have the same priority then it is an | ||
52 | * IMPDEF choice which of them to signal to the CPU. We choose to | ||
53 | * signal the one with the lowest interrupt number. | ||
54 | */ | ||
55 | - if (prio == cs->hppi.prio && irq <= cs->hppi.irq) { | ||
56 | + if (irq <= cs->hppi.irq) { | ||
57 | return true; | ||
58 | } | ||
59 | return false; | ||
60 | @@ -XXX,XX +XXX,XX @@ static uint32_t gicr_int_pending(GICv3CPUState *cs) | ||
61 | return pend; | ||
62 | } | ||
63 | |||
64 | +static bool gicv3_get_priority(GICv3CPUState *cs, bool is_redist, int irq, | ||
65 | + uint8_t *prio) | ||
66 | +{ | ||
67 | + uint32_t nmi = 0x0; | ||
68 | + | ||
69 | + if (is_redist) { | ||
70 | + nmi = extract32(cs->gicr_inmir0, irq, 1); | ||
71 | + } else { | ||
72 | + nmi = *gic_bmp_ptr32(cs->gic->nmi, irq); | ||
73 | + nmi = nmi & (1 << (irq & 0x1f)); | ||
74 | + } | ||
75 | + | ||
76 | + if (nmi) { | ||
77 | + /* DS = 0 & Non-secure NMI */ | ||
78 | + if (!(cs->gic->gicd_ctlr & GICD_CTLR_DS) && | ||
79 | + ((is_redist && extract32(cs->gicr_igroupr0, irq, 1)) || | ||
80 | + (!is_redist && gicv3_gicd_group_test(cs->gic, irq)))) { | ||
81 | + *prio = 0x80; | ||
82 | + } else { | ||
83 | + *prio = 0x0; | ||
84 | + } | ||
85 | + | ||
86 | + return true; | ||
87 | + } | ||
88 | + | ||
89 | + if (is_redist) { | ||
90 | + *prio = cs->gicr_ipriorityr[irq]; | ||
91 | + } else { | ||
92 | + *prio = cs->gic->gicd_ipriority[irq]; | ||
93 | + } | ||
94 | + | ||
95 | + return false; | ||
96 | +} | ||
97 | + | ||
98 | /* Update the interrupt status after state in a redistributor | ||
99 | * or CPU interface has changed, but don't tell the CPU i/f. | ||
100 | */ | ||
101 | @@ -XXX,XX +XXX,XX @@ static void gicv3_redist_update_noirqset(GICv3CPUState *cs) | ||
102 | uint8_t prio; | ||
103 | int i; | ||
104 | uint32_t pend; | ||
105 | + bool nmi = false; | ||
106 | |||
107 | /* Find out which redistributor interrupts are eligible to be | ||
108 | * signaled to the CPU interface. | ||
109 | @@ -XXX,XX +XXX,XX @@ static void gicv3_redist_update_noirqset(GICv3CPUState *cs) | ||
110 | if (!(pend & (1 << i))) { | ||
111 | continue; | ||
112 | } | ||
113 | - prio = cs->gicr_ipriorityr[i]; | ||
114 | - if (irqbetter(cs, i, prio)) { | ||
115 | + nmi = gicv3_get_priority(cs, true, i, &prio); | ||
116 | + if (irqbetter(cs, i, prio, nmi)) { | ||
117 | cs->hppi.irq = i; | ||
118 | cs->hppi.prio = prio; | ||
119 | + cs->hppi.nmi = nmi; | ||
120 | seenbetter = true; | ||
121 | } | ||
122 | } | ||
123 | @@ -XXX,XX +XXX,XX @@ static void gicv3_redist_update_noirqset(GICv3CPUState *cs) | ||
124 | if ((cs->gicr_ctlr & GICR_CTLR_ENABLE_LPIS) && cs->gic->lpi_enable && | ||
125 | (cs->gic->gicd_ctlr & GICD_CTLR_EN_GRP1NS) && | ||
126 | (cs->hpplpi.prio != 0xff)) { | ||
127 | - if (irqbetter(cs, cs->hpplpi.irq, cs->hpplpi.prio)) { | ||
128 | + if (irqbetter(cs, cs->hpplpi.irq, cs->hpplpi.prio, cs->hpplpi.nmi)) { | ||
129 | cs->hppi.irq = cs->hpplpi.irq; | ||
130 | cs->hppi.prio = cs->hpplpi.prio; | ||
131 | + cs->hppi.nmi = cs->hpplpi.nmi; | ||
132 | cs->hppi.grp = cs->hpplpi.grp; | ||
133 | seenbetter = true; | ||
134 | } | ||
135 | @@ -XXX,XX +XXX,XX @@ static void gicv3_update_noirqset(GICv3State *s, int start, int len) | ||
136 | int i; | ||
137 | uint8_t prio; | ||
138 | uint32_t pend = 0; | ||
139 | + bool nmi = false; | ||
140 | |||
141 | assert(start >= GIC_INTERNAL); | ||
142 | assert(len > 0); | ||
143 | @@ -XXX,XX +XXX,XX @@ static void gicv3_update_noirqset(GICv3State *s, int start, int len) | ||
144 | */ | ||
145 | continue; | ||
146 | } | ||
147 | - prio = s->gicd_ipriority[i]; | ||
148 | - if (irqbetter(cs, i, prio)) { | ||
149 | + nmi = gicv3_get_priority(cs, false, i, &prio); | ||
150 | + if (irqbetter(cs, i, prio, nmi)) { | ||
151 | cs->hppi.irq = i; | ||
152 | cs->hppi.prio = prio; | ||
153 | + cs->hppi.nmi = nmi; | ||
154 | cs->seenbetter = true; | ||
155 | } | ||
156 | } | ||
157 | @@ -XXX,XX +XXX,XX @@ void gicv3_full_update_noirqset(GICv3State *s) | ||
158 | |||
159 | for (i = 0; i < s->num_cpu; i++) { | ||
160 | s->cpu[i].hppi.prio = 0xff; | ||
161 | + s->cpu[i].hppi.nmi = false; | ||
162 | } | ||
163 | |||
164 | /* Note that we can guarantee that these functions will not | ||
165 | diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c | ||
166 | index XXXXXXX..XXXXXXX 100644 | ||
167 | --- a/hw/intc/arm_gicv3_common.c | ||
168 | +++ b/hw/intc/arm_gicv3_common.c | ||
169 | @@ -XXX,XX +XXX,XX @@ static void arm_gicv3_common_reset_hold(Object *obj) | ||
170 | memset(cs->gicr_ipriorityr, 0, sizeof(cs->gicr_ipriorityr)); | ||
171 | |||
172 | cs->hppi.prio = 0xff; | ||
173 | + cs->hppi.nmi = false; | ||
174 | cs->hpplpi.prio = 0xff; | ||
175 | + cs->hpplpi.nmi = false; | ||
176 | cs->hppvlpi.prio = 0xff; | ||
177 | + cs->hppvlpi.nmi = false; | ||
178 | |||
179 | /* State in the CPU interface must *not* be reset here, because it | ||
180 | * is part of the CPU's reset domain, not the GIC device's. | ||
181 | diff --git a/hw/intc/arm_gicv3_redist.c b/hw/intc/arm_gicv3_redist.c | ||
182 | index XXXXXXX..XXXXXXX 100644 | ||
183 | --- a/hw/intc/arm_gicv3_redist.c | ||
184 | +++ b/hw/intc/arm_gicv3_redist.c | ||
185 | @@ -XXX,XX +XXX,XX @@ static void update_for_one_lpi(GICv3CPUState *cs, int irq, | ||
186 | ((prio == hpp->prio) && (irq <= hpp->irq))) { | ||
187 | hpp->irq = irq; | ||
188 | hpp->prio = prio; | ||
189 | + hpp->nmi = false; | ||
190 | /* LPIs and vLPIs are always non-secure Grp1 interrupts */ | ||
191 | hpp->grp = GICV3_G1NS; | ||
192 | } | ||
193 | @@ -XXX,XX +XXX,XX @@ static void update_for_all_lpis(GICv3CPUState *cs, uint64_t ptbase, | ||
194 | int i, bit; | ||
195 | |||
196 | hpp->prio = 0xff; | ||
197 | + hpp->nmi = false; | ||
198 | |||
199 | for (i = GICV3_LPI_INTID_START / 8; i < pendt_size / 8; i++) { | ||
200 | address_space_read(as, ptbase + i, MEMTXATTRS_UNSPECIFIED, &pend, 1); | ||
201 | @@ -XXX,XX +XXX,XX @@ static void gicv3_redist_update_vlpi_only(GICv3CPUState *cs) | ||
202 | |||
203 | if (!FIELD_EX64(cs->gicr_vpendbaser, GICR_VPENDBASER, VALID)) { | ||
204 | cs->hppvlpi.prio = 0xff; | ||
205 | + cs->hppvlpi.nmi = false; | ||
206 | return; | ||
207 | } | ||
27 | 208 | ||
28 | -- | 209 | -- |
29 | 2.20.1 | 210 | 2.34.1 |
30 | |||
31 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Jinjie Ruan <ruanjinjie@huawei.com> | ||
1 | 2 | ||
3 | In CPU Interface, if the IRQ has the non-maskable property, report NMI to | ||
4 | the corresponding PE. | ||
5 | |||
6 | Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com> | ||
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
9 | Message-id: 20240407081733.3231820-22-ruanjinjie@huawei.com | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
11 | --- | ||
12 | hw/intc/arm_gicv3_cpuif.c | 4 ++++ | ||
13 | 1 file changed, 4 insertions(+) | ||
14 | |||
15 | diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c | ||
16 | index XXXXXXX..XXXXXXX 100644 | ||
17 | --- a/hw/intc/arm_gicv3_cpuif.c | ||
18 | +++ b/hw/intc/arm_gicv3_cpuif.c | ||
19 | @@ -XXX,XX +XXX,XX @@ void gicv3_cpuif_update(GICv3CPUState *cs) | ||
20 | /* Tell the CPU about its highest priority pending interrupt */ | ||
21 | int irqlevel = 0; | ||
22 | int fiqlevel = 0; | ||
23 | + int nmilevel = 0; | ||
24 | ARMCPU *cpu = ARM_CPU(cs->cpu); | ||
25 | CPUARMState *env = &cpu->env; | ||
26 | |||
27 | @@ -XXX,XX +XXX,XX @@ void gicv3_cpuif_update(GICv3CPUState *cs) | ||
28 | |||
29 | if (isfiq) { | ||
30 | fiqlevel = 1; | ||
31 | + } else if (cs->hppi.nmi) { | ||
32 | + nmilevel = 1; | ||
33 | } else { | ||
34 | irqlevel = 1; | ||
35 | } | ||
36 | @@ -XXX,XX +XXX,XX @@ void gicv3_cpuif_update(GICv3CPUState *cs) | ||
37 | |||
38 | qemu_set_irq(cs->parent_fiq, fiqlevel); | ||
39 | qemu_set_irq(cs->parent_irq, irqlevel); | ||
40 | + qemu_set_irq(cs->parent_nmi, nmilevel); | ||
41 | } | ||
42 | |||
43 | static uint64_t icc_pmr_read(CPUARMState *env, const ARMCPRegInfo *ri) | ||
44 | -- | ||
45 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Jinjie Ruan <ruanjinjie@huawei.com> | ||
1 | 2 | ||
3 | In vCPU Interface, if the vIRQ has the non-maskable property, report | ||
4 | vINMI to the corresponding vPE. | ||
5 | |||
6 | Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com> | ||
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
9 | Message-id: 20240407081733.3231820-23-ruanjinjie@huawei.com | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
11 | --- | ||
12 | hw/intc/arm_gicv3_cpuif.c | 14 ++++++++++++-- | ||
13 | 1 file changed, 12 insertions(+), 2 deletions(-) | ||
14 | |||
15 | diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c | ||
16 | index XXXXXXX..XXXXXXX 100644 | ||
17 | --- a/hw/intc/arm_gicv3_cpuif.c | ||
18 | +++ b/hw/intc/arm_gicv3_cpuif.c | ||
19 | @@ -XXX,XX +XXX,XX @@ void gicv3_cpuif_virt_irq_fiq_update(GICv3CPUState *cs) | ||
20 | int idx; | ||
21 | int irqlevel = 0; | ||
22 | int fiqlevel = 0; | ||
23 | + int nmilevel = 0; | ||
24 | |||
25 | idx = hppvi_index(cs); | ||
26 | trace_gicv3_cpuif_virt_update(gicv3_redist_affid(cs), idx, | ||
27 | @@ -XXX,XX +XXX,XX @@ void gicv3_cpuif_virt_irq_fiq_update(GICv3CPUState *cs) | ||
28 | uint64_t lr = cs->ich_lr_el2[idx]; | ||
29 | |||
30 | if (icv_hppi_can_preempt(cs, lr)) { | ||
31 | - /* Virtual interrupts are simple: G0 are always FIQ, and G1 IRQ */ | ||
32 | + /* | ||
33 | + * Virtual interrupts are simple: G0 are always FIQ, and G1 are | ||
34 | + * IRQ or NMI which depends on the ICH_LR<n>_EL2.NMI to have | ||
35 | + * non-maskable property. | ||
36 | + */ | ||
37 | if (lr & ICH_LR_EL2_GROUP) { | ||
38 | - irqlevel = 1; | ||
39 | + if (lr & ICH_LR_EL2_NMI) { | ||
40 | + nmilevel = 1; | ||
41 | + } else { | ||
42 | + irqlevel = 1; | ||
43 | + } | ||
44 | } else { | ||
45 | fiqlevel = 1; | ||
46 | } | ||
47 | @@ -XXX,XX +XXX,XX @@ void gicv3_cpuif_virt_irq_fiq_update(GICv3CPUState *cs) | ||
48 | trace_gicv3_cpuif_virt_set_irqs(gicv3_redist_affid(cs), fiqlevel, irqlevel); | ||
49 | qemu_set_irq(cs->parent_vfiq, fiqlevel); | ||
50 | qemu_set_irq(cs->parent_virq, irqlevel); | ||
51 | + qemu_set_irq(cs->parent_vnmi, nmilevel); | ||
52 | } | ||
53 | |||
54 | static void gicv3_cpuif_virt_update(GICv3CPUState *cs) | ||
55 | -- | ||
56 | 2.34.1 | diff view generated by jsdifflib |
1 | From: Leif Lindholm <leif@nuviainc.com> | 1 | From: Jinjie Ruan <ruanjinjie@huawei.com> |
---|---|---|---|
2 | 2 | ||
3 | When FEAT_MTE is implemented, the AArch64 view of CTR_EL0 adds the | 3 | Enable FEAT_NMI on the 'max' CPU. |
4 | TminLine field in bits [37:32]. | ||
5 | Extend the ctr field to be able to hold this context. | ||
6 | 4 | ||
7 | Signed-off-by: Leif Lindholm <leif@nuviainc.com> | 5 | Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com> |
8 | Reviewed-by: Hao Wu <wuhaotsh@google.com> | ||
9 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
10 | Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com> | 7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
11 | Message-id: 20210108185154.8108-4-leif@nuviainc.com | 8 | Message-id: 20240407081733.3231820-24-ruanjinjie@huawei.com |
12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
13 | --- | 10 | --- |
14 | target/arm/cpu.h | 2 +- | 11 | docs/system/arm/emulation.rst | 1 + |
15 | 1 file changed, 1 insertion(+), 1 deletion(-) | 12 | target/arm/tcg/cpu64.c | 1 + |
13 | 2 files changed, 2 insertions(+) | ||
16 | 14 | ||
17 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | 15 | diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst |
18 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
19 | --- a/target/arm/cpu.h | 17 | --- a/docs/system/arm/emulation.rst |
20 | +++ b/target/arm/cpu.h | 18 | +++ b/docs/system/arm/emulation.rst |
21 | @@ -XXX,XX +XXX,XX @@ struct ARMCPU { | 19 | @@ -XXX,XX +XXX,XX @@ the following architecture extensions: |
22 | uint64_t midr; | 20 | - FEAT_MTE (Memory Tagging Extension) |
23 | uint32_t revidr; | 21 | - FEAT_MTE2 (Memory Tagging Extension) |
24 | uint32_t reset_fpsid; | 22 | - FEAT_MTE3 (MTE Asymmetric Fault Handling) |
25 | - uint32_t ctr; | 23 | +- FEAT_NMI (Non-maskable Interrupt) |
26 | + uint64_t ctr; | 24 | - FEAT_NV (Nested Virtualization) |
27 | uint32_t reset_sctlr; | 25 | - FEAT_NV2 (Enhanced nested virtualization support) |
28 | uint64_t pmceid0; | 26 | - FEAT_PACIMP (Pointer authentication - IMPLEMENTATION DEFINED algorithm) |
29 | uint64_t pmceid1; | 27 | diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c |
28 | index XXXXXXX..XXXXXXX 100644 | ||
29 | --- a/target/arm/tcg/cpu64.c | ||
30 | +++ b/target/arm/tcg/cpu64.c | ||
31 | @@ -XXX,XX +XXX,XX @@ void aarch64_max_tcg_initfn(Object *obj) | ||
32 | t = FIELD_DP64(t, ID_AA64PFR1, RAS_FRAC, 0); /* FEAT_RASv1p1 + FEAT_DoubleFault */ | ||
33 | t = FIELD_DP64(t, ID_AA64PFR1, SME, 1); /* FEAT_SME */ | ||
34 | t = FIELD_DP64(t, ID_AA64PFR1, CSV2_FRAC, 0); /* FEAT_CSV2_2 */ | ||
35 | + t = FIELD_DP64(t, ID_AA64PFR1, NMI, 1); /* FEAT_NMI */ | ||
36 | cpu->isar.id_aa64pfr1 = t; | ||
37 | |||
38 | t = cpu->isar.id_aa64mmfr0; | ||
30 | -- | 39 | -- |
31 | 2.20.1 | 40 | 2.34.1 |
32 | |||
33 | diff view generated by jsdifflib |
1 | From: Roman Bolshakov <r.bolshakov@yadro.com> | 1 | From: Jinjie Ruan <ruanjinjie@huawei.com> |
---|---|---|---|
2 | 2 | ||
3 | ui/cocoa.m:1188:44: warning: 'openFile:' is deprecated: first deprecated in macOS 11.0 - Use -[NSWorkspace openURL:] instead. | 3 | If the CPU implements FEAT_NMI, then turn on the NMI support in the |
4 | [-Wdeprecated-declarations] | 4 | GICv3 too. It's permitted to have a configuration with FEAT_NMI in |
5 | if ([[NSWorkspace sharedWorkspace] openFile: full_file_path] == YES) { | 5 | the CPU (and thus NMI support in the CPU interfaces too) but no NMI |
6 | ^ | 6 | support in the distributor and redistributor, but this isn't a very |
7 | /Library/Developer/CommandLineTools/SDKs/MacOSX.sdk/System/Library/Frameworks/AppKit.framework/Headers/NSWorkspace.h:350:1: note: | 7 | useful setup as it's close to having no NMI support at all. |
8 | 'openFile:' has been explicitly marked deprecated here | ||
9 | - (BOOL)openFile:(NSString *)fullPath API_DEPRECATED("Use -[NSWorkspace openURL:] instead.", macos(10.0, 11.0)); | ||
10 | ^ | ||
11 | 8 | ||
12 | Signed-off-by: Roman Bolshakov <r.bolshakov@yadro.com> | 9 | We don't need to gate the enabling of NMI in the GIC behind a |
13 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 10 | machine version property, because none of our current CPUs |
14 | Message-id: 20210102150718.47618-1-r.bolshakov@yadro.com | 11 | implement FEAT_NMI, and '-cpu max' is not something we maintain |
12 | migration compatibility across versions for. So we can always | ||
13 | enable the GIC NMI support when the CPU has it. | ||
14 | |||
15 | Neither hvf nor KVM support NMI in the GIC yet, so we don't enable | ||
16 | it unless we're using TCG. | ||
17 | |||
18 | Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com> | ||
19 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
20 | Message-id: 20240407081733.3231820-25-ruanjinjie@huawei.com | ||
21 | [PMM: Update comment and commit message] | ||
22 | Suggested-by: Peter Maydell <peter.maydell@linaro.org> | ||
15 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 23 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
16 | --- | 24 | --- |
17 | ui/cocoa.m | 5 ++++- | 25 | hw/arm/virt.c | 19 +++++++++++++++++++ |
18 | 1 file changed, 4 insertions(+), 1 deletion(-) | 26 | 1 file changed, 19 insertions(+) |
19 | 27 | ||
20 | diff --git a/ui/cocoa.m b/ui/cocoa.m | 28 | diff --git a/hw/arm/virt.c b/hw/arm/virt.c |
21 | index XXXXXXX..XXXXXXX 100644 | 29 | index XXXXXXX..XXXXXXX 100644 |
22 | --- a/ui/cocoa.m | 30 | --- a/hw/arm/virt.c |
23 | +++ b/ui/cocoa.m | 31 | +++ b/hw/arm/virt.c |
24 | @@ -XXX,XX +XXX,XX @@ QemuCocoaView *cocoaView; | 32 | @@ -XXX,XX +XXX,XX @@ static void create_v2m(VirtMachineState *vms) |
25 | /* Where to look for local files */ | 33 | vms->msi_controller = VIRT_MSI_CTRL_GICV2M; |
26 | NSString *path_array[] = {@"../share/doc/qemu/", @"../doc/qemu/", @"docs/"}; | 34 | } |
27 | NSString *full_file_path; | 35 | |
28 | + NSURL *full_file_url; | 36 | +/* |
29 | 37 | + * If the CPU has FEAT_NMI, then turn on the NMI support in the GICv3 too. | |
30 | /* iterate thru the possible paths until the file is found */ | 38 | + * It's permitted to have a configuration with NMI in the CPU (and thus the |
31 | int index; | 39 | + * GICv3 CPU interface) but not in the distributor/redistributors, but it's |
32 | @@ -XXX,XX +XXX,XX @@ QemuCocoaView *cocoaView; | 40 | + * not very useful. |
33 | full_file_path = [full_file_path stringByDeletingLastPathComponent]; | 41 | + */ |
34 | full_file_path = [NSString stringWithFormat: @"%@/%@%@", full_file_path, | 42 | +static bool gicv3_nmi_present(VirtMachineState *vms) |
35 | path_array[index], filename]; | 43 | +{ |
36 | - if ([[NSWorkspace sharedWorkspace] openFile: full_file_path] == YES) { | 44 | + ARMCPU *cpu = ARM_CPU(qemu_get_cpu(0)); |
37 | + full_file_url = [NSURL fileURLWithPath: full_file_path | 45 | + |
38 | + isDirectory: false]; | 46 | + return tcg_enabled() && cpu_isar_feature(aa64_nmi, cpu) && |
39 | + if ([[NSWorkspace sharedWorkspace] openURL: full_file_url] == YES) { | 47 | + (vms->gic_version != VIRT_GIC_VERSION_2); |
40 | return; | 48 | +} |
49 | + | ||
50 | static void create_gic(VirtMachineState *vms, MemoryRegion *mem) | ||
51 | { | ||
52 | MachineState *ms = MACHINE(vms); | ||
53 | @@ -XXX,XX +XXX,XX @@ static void create_gic(VirtMachineState *vms, MemoryRegion *mem) | ||
54 | vms->virt); | ||
41 | } | 55 | } |
42 | } | 56 | } |
57 | + | ||
58 | + if (gicv3_nmi_present(vms)) { | ||
59 | + qdev_prop_set_bit(vms->gic, "has-nmi", true); | ||
60 | + } | ||
61 | + | ||
62 | gicbusdev = SYS_BUS_DEVICE(vms->gic); | ||
63 | sysbus_realize_and_unref(gicbusdev, &error_fatal); | ||
64 | sysbus_mmio_map(gicbusdev, 0, vms->memmap[VIRT_GIC_DIST].base); | ||
43 | -- | 65 | -- |
44 | 2.20.1 | 66 | 2.34.1 |
45 | |||
46 | diff view generated by jsdifflib |
1 | From: Roman Bolshakov <r.bolshakov@yadro.com> | 1 | From: Anastasia Belova <abelova@astralinux.ru> |
---|---|---|---|
2 | 2 | ||
3 | QEMU documentation can't be opened if QEMU is run from build tree | 3 | In soc_dma_set_request() we try to set a bit in a uint64_t, but we |
4 | because executables are placed in the top of build tree after conversion | 4 | do it with "1 << ch->num", which can't set any bits past 31; |
5 | to meson. | 5 | any use for a channel number of 32 or more would fail due to |
6 | integer overflow. | ||
6 | 7 | ||
7 | Signed-off-by: Roman Bolshakov <r.bolshakov@yadro.com> | 8 | This doesn't happen in practice for our current use of this code, |
8 | Reported-by: Peter Maydell <peter.maydell@linaro.org> | 9 | because the worst case is when we call soc_dma_init() with an |
9 | Message-id: 20210108213815.64678-1-r.bolshakov@yadro.com | 10 | argument of 32 for the number of channels, and QEMU builds with |
11 | -fwrapv so the shift into the sign bit is well-defined. However, | ||
12 | it's obviously not the intended behaviour of the code. | ||
13 | |||
14 | Add casts to force the shift to be done as 64-bit arithmetic, | ||
15 | allowing up to 64 channels. | ||
16 | |||
17 | Found by Linux Verification Center (linuxtesting.org) with SVACE. | ||
18 | |||
19 | Fixes: afbb5194d4 ("Handle on-chip DMA controllers in one place, convert OMAP DMA to use it.") | ||
20 | Signed-off-by: Anastasia Belova <abelova@astralinux.ru> | ||
21 | Message-id: 20240409115301.21829-1-abelova@astralinux.ru | ||
22 | [PMM: Edit commit message to clarify that this doesn't actually | ||
23 | bite us in our current usage of this code.] | ||
10 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 24 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 25 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
12 | --- | 26 | --- |
13 | ui/cocoa.m | 2 +- | 27 | hw/dma/soc_dma.c | 4 ++-- |
14 | 1 file changed, 1 insertion(+), 1 deletion(-) | 28 | 1 file changed, 2 insertions(+), 2 deletions(-) |
15 | 29 | ||
16 | diff --git a/ui/cocoa.m b/ui/cocoa.m | 30 | diff --git a/hw/dma/soc_dma.c b/hw/dma/soc_dma.c |
17 | index XXXXXXX..XXXXXXX 100644 | 31 | index XXXXXXX..XXXXXXX 100644 |
18 | --- a/ui/cocoa.m | 32 | --- a/hw/dma/soc_dma.c |
19 | +++ b/ui/cocoa.m | 33 | +++ b/hw/dma/soc_dma.c |
20 | @@ -XXX,XX +XXX,XX @@ QemuCocoaView *cocoaView; | 34 | @@ -XXX,XX +XXX,XX @@ void soc_dma_set_request(struct soc_dma_ch_s *ch, int level) |
21 | - (void) openDocumentation: (NSString *) filename | 35 | dma->enabled_count += level - ch->enable; |
22 | { | 36 | |
23 | /* Where to look for local files */ | 37 | if (level) |
24 | - NSString *path_array[] = {@"../share/doc/qemu/", @"../doc/qemu/", @"../docs/"}; | 38 | - dma->ch_enable_mask |= 1 << ch->num; |
25 | + NSString *path_array[] = {@"../share/doc/qemu/", @"../doc/qemu/", @"docs/"}; | 39 | + dma->ch_enable_mask |= (uint64_t)1 << ch->num; |
26 | NSString *full_file_path; | 40 | else |
27 | 41 | - dma->ch_enable_mask &= ~(1 << ch->num); | |
28 | /* iterate thru the possible paths until the file is found */ | 42 | + dma->ch_enable_mask &= ~((uint64_t)1 << ch->num); |
43 | |||
44 | if (level != ch->enable) { | ||
45 | soc_dma_ch_freq_update(dma); | ||
29 | -- | 46 | -- |
30 | 2.20.1 | 47 | 2.34.1 |
31 | |||
32 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | 1 | Ever since the bFLT format support was added in 2006, there has been | |
2 | a chunk of code in the file guarded by CONFIG_BINFMT_SHARED_FLAT | ||
3 | which is supposedly for shared library support. This is not enabled | ||
4 | and it's not possible to enable it, because if you do you'll run into | ||
5 | the "#error needs checking" in the calc_reloc() function. | ||
6 | |||
7 | Similarly, CONFIG_BINFMT_ZFLAT exists but can't be enabled because of | ||
8 | an "#error code needs checking" in load_flat_file(). | ||
9 | |||
10 | This code is obviously unfinished and has never been used; nobody in | ||
11 | the intervening 18 years has complained about this or fixed it, so | ||
12 | just delete the dead code. If anybody ever wants the feature they | ||
13 | can always pull it out of git, or (perhaps better) write it from | ||
14 | scratch based on the current Linux bFLT loader rather than the one of | ||
15 | 18 years ago. | ||
16 | |||
17 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
18 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
19 | Message-id: 20240411115313.680433-1-peter.maydell@linaro.org | ||
20 | --- | ||
21 | linux-user/flat.h | 5 +- | ||
22 | linux-user/flatload.c | 293 ++---------------------------------------- | ||
23 | 2 files changed, 11 insertions(+), 287 deletions(-) | ||
24 | |||
25 | diff --git a/linux-user/flat.h b/linux-user/flat.h | ||
26 | index XXXXXXX..XXXXXXX 100644 | ||
27 | --- a/linux-user/flat.h | ||
28 | +++ b/linux-user/flat.h | ||
29 | @@ -XXX,XX +XXX,XX @@ | ||
30 | |||
31 | #define FLAT_VERSION 0x00000004L | ||
32 | |||
33 | -#ifdef CONFIG_BINFMT_SHARED_FLAT | ||
34 | -#define MAX_SHARED_LIBS (4) | ||
35 | -#else | ||
36 | +/* QEMU doesn't support bflt shared libraries */ | ||
37 | #define MAX_SHARED_LIBS (1) | ||
38 | -#endif | ||
39 | |||
40 | /* | ||
41 | * To make everything easier to port and manage cross platform | ||
42 | diff --git a/linux-user/flatload.c b/linux-user/flatload.c | ||
43 | index XXXXXXX..XXXXXXX 100644 | ||
44 | --- a/linux-user/flatload.c | ||
45 | +++ b/linux-user/flatload.c | ||
46 | @@ -XXX,XX +XXX,XX @@ | ||
47 | * JAN/99 -- coded full program relocation (gerg@snapgear.com) | ||
48 | */ | ||
49 | |||
50 | -/* ??? ZFLAT and shared library support is currently disabled. */ | ||
51 | - | ||
52 | /****************************************************************************/ | ||
53 | |||
54 | #include "qemu/osdep.h" | ||
55 | @@ -XXX,XX +XXX,XX @@ struct lib_info { | ||
56 | short loaded; /* Has this library been loaded? */ | ||
57 | }; | ||
58 | |||
59 | -#ifdef CONFIG_BINFMT_SHARED_FLAT | ||
60 | -static int load_flat_shared_library(int id, struct lib_info *p); | ||
61 | -#endif | ||
62 | - | ||
63 | struct linux_binprm; | ||
64 | |||
65 | /****************************************************************************/ | ||
66 | @@ -XXX,XX +XXX,XX @@ static int target_pread(int fd, abi_ulong ptr, abi_ulong len, | ||
67 | unlock_user(buf, ptr, len); | ||
68 | return ret; | ||
69 | } | ||
70 | -/****************************************************************************/ | ||
71 | - | ||
72 | -#ifdef CONFIG_BINFMT_ZFLAT | ||
73 | - | ||
74 | -#include <linux/zlib.h> | ||
75 | - | ||
76 | -#define LBUFSIZE 4000 | ||
77 | - | ||
78 | -/* gzip flag byte */ | ||
79 | -#define ASCII_FLAG 0x01 /* bit 0 set: file probably ASCII text */ | ||
80 | -#define CONTINUATION 0x02 /* bit 1 set: continuation of multi-part gzip file */ | ||
81 | -#define EXTRA_FIELD 0x04 /* bit 2 set: extra field present */ | ||
82 | -#define ORIG_NAME 0x08 /* bit 3 set: original file name present */ | ||
83 | -#define COMMENT 0x10 /* bit 4 set: file comment present */ | ||
84 | -#define ENCRYPTED 0x20 /* bit 5 set: file is encrypted */ | ||
85 | -#define RESERVED 0xC0 /* bit 6,7: reserved */ | ||
86 | - | ||
87 | -static int decompress_exec( | ||
88 | - struct linux_binprm *bprm, | ||
89 | - unsigned long offset, | ||
90 | - char *dst, | ||
91 | - long len, | ||
92 | - int fd) | ||
93 | -{ | ||
94 | - unsigned char *buf; | ||
95 | - z_stream strm; | ||
96 | - loff_t fpos; | ||
97 | - int ret, retval; | ||
98 | - | ||
99 | - DBG_FLT("decompress_exec(offset=%x,buf=%x,len=%x)\n",(int)offset, (int)dst, (int)len); | ||
100 | - | ||
101 | - memset(&strm, 0, sizeof(strm)); | ||
102 | - strm.workspace = kmalloc(zlib_inflate_workspacesize(), GFP_KERNEL); | ||
103 | - if (strm.workspace == NULL) { | ||
104 | - DBG_FLT("binfmt_flat: no memory for decompress workspace\n"); | ||
105 | - return -ENOMEM; | ||
106 | - } | ||
107 | - buf = kmalloc(LBUFSIZE, GFP_KERNEL); | ||
108 | - if (buf == NULL) { | ||
109 | - DBG_FLT("binfmt_flat: no memory for read buffer\n"); | ||
110 | - retval = -ENOMEM; | ||
111 | - goto out_free; | ||
112 | - } | ||
113 | - | ||
114 | - /* Read in first chunk of data and parse gzip header. */ | ||
115 | - fpos = offset; | ||
116 | - ret = bprm->file->f_op->read(bprm->file, buf, LBUFSIZE, &fpos); | ||
117 | - | ||
118 | - strm.next_in = buf; | ||
119 | - strm.avail_in = ret; | ||
120 | - strm.total_in = 0; | ||
121 | - | ||
122 | - retval = -ENOEXEC; | ||
123 | - | ||
124 | - /* Check minimum size -- gzip header */ | ||
125 | - if (ret < 10) { | ||
126 | - DBG_FLT("binfmt_flat: file too small?\n"); | ||
127 | - goto out_free_buf; | ||
128 | - } | ||
129 | - | ||
130 | - /* Check gzip magic number */ | ||
131 | - if ((buf[0] != 037) || ((buf[1] != 0213) && (buf[1] != 0236))) { | ||
132 | - DBG_FLT("binfmt_flat: unknown compression magic?\n"); | ||
133 | - goto out_free_buf; | ||
134 | - } | ||
135 | - | ||
136 | - /* Check gzip method */ | ||
137 | - if (buf[2] != 8) { | ||
138 | - DBG_FLT("binfmt_flat: unknown compression method?\n"); | ||
139 | - goto out_free_buf; | ||
140 | - } | ||
141 | - /* Check gzip flags */ | ||
142 | - if ((buf[3] & ENCRYPTED) || (buf[3] & CONTINUATION) || | ||
143 | - (buf[3] & RESERVED)) { | ||
144 | - DBG_FLT("binfmt_flat: unknown flags?\n"); | ||
145 | - goto out_free_buf; | ||
146 | - } | ||
147 | - | ||
148 | - ret = 10; | ||
149 | - if (buf[3] & EXTRA_FIELD) { | ||
150 | - ret += 2 + buf[10] + (buf[11] << 8); | ||
151 | - if (unlikely(LBUFSIZE == ret)) { | ||
152 | - DBG_FLT("binfmt_flat: buffer overflow (EXTRA)?\n"); | ||
153 | - goto out_free_buf; | ||
154 | - } | ||
155 | - } | ||
156 | - if (buf[3] & ORIG_NAME) { | ||
157 | - for (; ret < LBUFSIZE && (buf[ret] != 0); ret++) | ||
158 | - ; | ||
159 | - if (unlikely(LBUFSIZE == ret)) { | ||
160 | - DBG_FLT("binfmt_flat: buffer overflow (ORIG_NAME)?\n"); | ||
161 | - goto out_free_buf; | ||
162 | - } | ||
163 | - } | ||
164 | - if (buf[3] & COMMENT) { | ||
165 | - for (; ret < LBUFSIZE && (buf[ret] != 0); ret++) | ||
166 | - ; | ||
167 | - if (unlikely(LBUFSIZE == ret)) { | ||
168 | - DBG_FLT("binfmt_flat: buffer overflow (COMMENT)?\n"); | ||
169 | - goto out_free_buf; | ||
170 | - } | ||
171 | - } | ||
172 | - | ||
173 | - strm.next_in += ret; | ||
174 | - strm.avail_in -= ret; | ||
175 | - | ||
176 | - strm.next_out = dst; | ||
177 | - strm.avail_out = len; | ||
178 | - strm.total_out = 0; | ||
179 | - | ||
180 | - if (zlib_inflateInit2(&strm, -MAX_WBITS) != Z_OK) { | ||
181 | - DBG_FLT("binfmt_flat: zlib init failed?\n"); | ||
182 | - goto out_free_buf; | ||
183 | - } | ||
184 | - | ||
185 | - while ((ret = zlib_inflate(&strm, Z_NO_FLUSH)) == Z_OK) { | ||
186 | - ret = bprm->file->f_op->read(bprm->file, buf, LBUFSIZE, &fpos); | ||
187 | - if (ret <= 0) | ||
188 | - break; | ||
189 | - if (is_error(ret)) { | ||
190 | - break; | ||
191 | - } | ||
192 | - len -= ret; | ||
193 | - | ||
194 | - strm.next_in = buf; | ||
195 | - strm.avail_in = ret; | ||
196 | - strm.total_in = 0; | ||
197 | - } | ||
198 | - | ||
199 | - if (ret < 0) { | ||
200 | - DBG_FLT("binfmt_flat: decompression failed (%d), %s\n", | ||
201 | - ret, strm.msg); | ||
202 | - goto out_zlib; | ||
203 | - } | ||
204 | - | ||
205 | - retval = 0; | ||
206 | -out_zlib: | ||
207 | - zlib_inflateEnd(&strm); | ||
208 | -out_free_buf: | ||
209 | - kfree(buf); | ||
210 | -out_free: | ||
211 | - kfree(strm.workspace); | ||
212 | -out: | ||
213 | - return retval; | ||
214 | -} | ||
215 | - | ||
216 | -#endif /* CONFIG_BINFMT_ZFLAT */ | ||
217 | |||
218 | /****************************************************************************/ | ||
219 | |||
220 | @@ -XXX,XX +XXX,XX @@ calc_reloc(abi_ulong r, struct lib_info *p, int curid, int internalp) | ||
221 | abi_ulong text_len; | ||
222 | abi_ulong start_code; | ||
223 | |||
224 | -#ifdef CONFIG_BINFMT_SHARED_FLAT | ||
225 | -#error needs checking | ||
226 | - if (r == 0) | ||
227 | - id = curid; /* Relocs of 0 are always self referring */ | ||
228 | - else { | ||
229 | - id = (r >> 24) & 0xff; /* Find ID for this reloc */ | ||
230 | - r &= 0x00ffffff; /* Trim ID off here */ | ||
231 | - } | ||
232 | - if (id >= MAX_SHARED_LIBS) { | ||
233 | - fprintf(stderr, "BINFMT_FLAT: reference 0x%x to shared library %d\n", | ||
234 | - (unsigned) r, id); | ||
235 | - goto failed; | ||
236 | - } | ||
237 | - if (curid != id) { | ||
238 | - if (internalp) { | ||
239 | - fprintf(stderr, "BINFMT_FLAT: reloc address 0x%x not " | ||
240 | - "in same module (%d != %d)\n", | ||
241 | - (unsigned) r, curid, id); | ||
242 | - goto failed; | ||
243 | - } else if (!p[id].loaded && is_error(load_flat_shared_library(id, p))) { | ||
244 | - fprintf(stderr, "BINFMT_FLAT: failed to load library %d\n", id); | ||
245 | - goto failed; | ||
246 | - } | ||
247 | - /* Check versioning information (i.e. time stamps) */ | ||
248 | - if (p[id].build_date && p[curid].build_date | ||
249 | - && p[curid].build_date < p[id].build_date) { | ||
250 | - fprintf(stderr, "BINFMT_FLAT: library %d is younger than %d\n", | ||
251 | - id, curid); | ||
252 | - goto failed; | ||
253 | - } | ||
254 | - } | ||
255 | -#else | ||
256 | id = 0; | ||
257 | -#endif | ||
258 | |||
259 | start_brk = p[id].start_brk; | ||
260 | start_data = p[id].start_data; | ||
261 | @@ -XXX,XX +XXX,XX @@ static int load_flat_file(struct linux_binprm * bprm, | ||
262 | if (rev == OLD_FLAT_VERSION && flat_old_ram_flag(flags)) | ||
263 | flags = FLAT_FLAG_RAM; | ||
264 | |||
265 | -#ifndef CONFIG_BINFMT_ZFLAT | ||
266 | if (flags & (FLAT_FLAG_GZIP|FLAT_FLAG_GZDATA)) { | ||
267 | - fprintf(stderr, "Support for ZFLAT executables is not enabled\n"); | ||
268 | + fprintf(stderr, "ZFLAT executables are not supported\n"); | ||
269 | return -ENOEXEC; | ||
270 | } | ||
271 | -#endif | ||
272 | |||
273 | /* | ||
274 | * calculate the extra space we need to map in | ||
275 | @@ -XXX,XX +XXX,XX @@ static int load_flat_file(struct linux_binprm * bprm, | ||
276 | (int)(data_len + bss_len + stack_len), (int)datapos); | ||
277 | |||
278 | fpos = ntohl(hdr->data_start); | ||
279 | -#ifdef CONFIG_BINFMT_ZFLAT | ||
280 | - if (flags & FLAT_FLAG_GZDATA) { | ||
281 | - result = decompress_exec(bprm, fpos, (char *) datapos, | ||
282 | - data_len + (relocs * sizeof(abi_ulong))) | ||
283 | - } else | ||
284 | -#endif | ||
285 | - { | ||
286 | - result = target_pread(bprm->src.fd, datapos, | ||
287 | - data_len + (relocs * sizeof(abi_ulong)), | ||
288 | - fpos); | ||
289 | - } | ||
290 | + result = target_pread(bprm->src.fd, datapos, | ||
291 | + data_len + (relocs * sizeof(abi_ulong)), | ||
292 | + fpos); | ||
293 | if (result < 0) { | ||
294 | fprintf(stderr, "Unable to read data+bss\n"); | ||
295 | return result; | ||
296 | @@ -XXX,XX +XXX,XX @@ static int load_flat_file(struct linux_binprm * bprm, | ||
297 | datapos = realdatastart + indx_len; | ||
298 | reloc = (textpos + ntohl(hdr->reloc_start) + indx_len); | ||
299 | |||
300 | -#ifdef CONFIG_BINFMT_ZFLAT | ||
301 | -#error code needs checking | ||
302 | - /* | ||
303 | - * load it all in and treat it like a RAM load from now on | ||
304 | - */ | ||
305 | - if (flags & FLAT_FLAG_GZIP) { | ||
306 | - result = decompress_exec(bprm, sizeof (struct flat_hdr), | ||
307 | - (((char *) textpos) + sizeof (struct flat_hdr)), | ||
308 | - (text_len + data_len + (relocs * sizeof(unsigned long)) | ||
309 | - - sizeof (struct flat_hdr)), | ||
310 | - 0); | ||
311 | - memmove((void *) datapos, (void *) realdatastart, | ||
312 | - data_len + (relocs * sizeof(unsigned long))); | ||
313 | - } else if (flags & FLAT_FLAG_GZDATA) { | ||
314 | - fpos = 0; | ||
315 | - result = bprm->file->f_op->read(bprm->file, | ||
316 | - (char *) textpos, text_len, &fpos); | ||
317 | - if (!is_error(result)) { | ||
318 | - result = decompress_exec(bprm, text_len, (char *) datapos, | ||
319 | - data_len + (relocs * sizeof(unsigned long)), 0); | ||
320 | - } | ||
321 | - } | ||
322 | - else | ||
323 | -#endif | ||
324 | - { | ||
325 | - result = target_pread(bprm->src.fd, textpos, | ||
326 | - text_len, 0); | ||
327 | - if (result >= 0) { | ||
328 | - result = target_pread(bprm->src.fd, datapos, | ||
329 | - data_len + (relocs * sizeof(abi_ulong)), | ||
330 | - ntohl(hdr->data_start)); | ||
331 | - } | ||
332 | + result = target_pread(bprm->src.fd, textpos, | ||
333 | + text_len, 0); | ||
334 | + if (result >= 0) { | ||
335 | + result = target_pread(bprm->src.fd, datapos, | ||
336 | + data_len + (relocs * sizeof(abi_ulong)), | ||
337 | + ntohl(hdr->data_start)); | ||
338 | } | ||
339 | if (result < 0) { | ||
340 | fprintf(stderr, "Unable to read code+data+bss\n"); | ||
341 | @@ -XXX,XX +XXX,XX @@ static int load_flat_file(struct linux_binprm * bprm, | ||
342 | |||
343 | |||
344 | /****************************************************************************/ | ||
345 | -#ifdef CONFIG_BINFMT_SHARED_FLAT | ||
346 | - | ||
347 | -/* | ||
348 | - * Load a shared library into memory. The library gets its own data | ||
349 | - * segment (including bss) but not argv/argc/environ. | ||
350 | - */ | ||
351 | - | ||
352 | -static int load_flat_shared_library(int id, struct lib_info *libs) | ||
353 | -{ | ||
354 | - struct linux_binprm bprm; | ||
355 | - int res; | ||
356 | - char buf[16]; | ||
357 | - | ||
358 | - /* Create the file name */ | ||
359 | - sprintf(buf, "/lib/lib%d.so", id); | ||
360 | - | ||
361 | - /* Open the file up */ | ||
362 | - bprm.filename = buf; | ||
363 | - bprm.file = open_exec(bprm.filename); | ||
364 | - res = PTR_ERR(bprm.file); | ||
365 | - if (IS_ERR(bprm.file)) | ||
366 | - return res; | ||
367 | - | ||
368 | - res = prepare_binprm(&bprm); | ||
369 | - | ||
370 | - if (!is_error(res)) { | ||
371 | - res = load_flat_file(&bprm, libs, id, NULL); | ||
372 | - } | ||
373 | - if (bprm.file) { | ||
374 | - allow_write_access(bprm.file); | ||
375 | - fput(bprm.file); | ||
376 | - bprm.file = NULL; | ||
377 | - } | ||
378 | - return(res); | ||
379 | -} | ||
380 | - | ||
381 | -#endif /* CONFIG_BINFMT_SHARED_FLAT */ | ||
382 | - | ||
383 | int load_flt_binary(struct linux_binprm *bprm, struct image_info *info) | ||
384 | { | ||
385 | struct lib_info libinfo[MAX_SHARED_LIBS]; | ||
386 | @@ -XXX,XX +XXX,XX @@ int load_flt_binary(struct linux_binprm *bprm, struct image_info *info) | ||
387 | */ | ||
388 | start_addr = libinfo[0].entry; | ||
389 | |||
390 | -#ifdef CONFIG_BINFMT_SHARED_FLAT | ||
391 | -#error here | ||
392 | - for (i = MAX_SHARED_LIBS-1; i>0; i--) { | ||
393 | - if (libinfo[i].loaded) { | ||
394 | - /* Push previous first to call address */ | ||
395 | - --sp; | ||
396 | - if (put_user_ual(start_addr, sp)) | ||
397 | - return -EFAULT; | ||
398 | - start_addr = libinfo[i].entry; | ||
399 | - } | ||
400 | - } | ||
401 | -#endif | ||
402 | - | ||
403 | /* Stash our initial stack pointer into the mm structure */ | ||
404 | info->start_code = libinfo[0].start_code; | ||
405 | info->end_code = libinfo[0].start_code + libinfo[0].text_len; | ||
406 | -- | ||
407 | 2.34.1 | ||
408 | |||
409 | diff view generated by jsdifflib |
1 | From: Hao Wu <wuhaotsh@google.com> | 1 | The npcm7xx_clk and npcm7xx_gcr device reset methods look at |
---|---|---|---|
2 | the ResetType argument and only handle RESET_TYPE_COLD, | ||
3 | producing a warning if another reset type is passed. This | ||
4 | is different from how every other three-phase-reset method | ||
5 | we have works, and makes it difficult to add new reset types. | ||
2 | 6 | ||
3 | A device shouldn't access its parent object which is QOM internal. | 7 | A better pattern is "assume that any reset type you don't know |
4 | Instead it should use type cast for this purporse. This patch fixes this | 8 | about should be handled like RESET_TYPE_COLD"; switch these |
5 | issue for all NPCM7XX Devices. | 9 | devices to do that. Then adding a new reset type will only |
10 | need to touch those devices where its behaviour really needs | ||
11 | to be different from the standard cold reset. | ||
6 | 12 | ||
7 | Signed-off-by: Hao Wu <wuhaotsh@google.com> | ||
8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
9 | Message-id: 20210108190945.949196-7-wuhaotsh@google.com | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
14 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
15 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
16 | Reviewed-by: Luc Michel <luc.michel@amd.com> | ||
17 | Message-id: 20240412160809.1260625-2-peter.maydell@linaro.org | ||
11 | --- | 18 | --- |
12 | hw/arm/npcm7xx_boards.c | 2 +- | 19 | hw/misc/npcm7xx_clk.c | 13 +++---------- |
13 | hw/mem/npcm7xx_mc.c | 2 +- | 20 | hw/misc/npcm7xx_gcr.c | 12 ++++-------- |
14 | hw/misc/npcm7xx_clk.c | 2 +- | 21 | 2 files changed, 7 insertions(+), 18 deletions(-) |
15 | hw/misc/npcm7xx_gcr.c | 2 +- | ||
16 | hw/misc/npcm7xx_rng.c | 2 +- | ||
17 | hw/nvram/npcm7xx_otp.c | 2 +- | ||
18 | hw/ssi/npcm7xx_fiu.c | 2 +- | ||
19 | 7 files changed, 7 insertions(+), 7 deletions(-) | ||
20 | 22 | ||
21 | diff --git a/hw/arm/npcm7xx_boards.c b/hw/arm/npcm7xx_boards.c | ||
22 | index XXXXXXX..XXXXXXX 100644 | ||
23 | --- a/hw/arm/npcm7xx_boards.c | ||
24 | +++ b/hw/arm/npcm7xx_boards.c | ||
25 | @@ -XXX,XX +XXX,XX @@ static NPCM7xxState *npcm7xx_create_soc(MachineState *machine, | ||
26 | uint32_t hw_straps) | ||
27 | { | ||
28 | NPCM7xxMachineClass *nmc = NPCM7XX_MACHINE_GET_CLASS(machine); | ||
29 | - MachineClass *mc = &nmc->parent; | ||
30 | + MachineClass *mc = MACHINE_CLASS(nmc); | ||
31 | Object *obj; | ||
32 | |||
33 | if (strcmp(machine->cpu_type, mc->default_cpu_type) != 0) { | ||
34 | diff --git a/hw/mem/npcm7xx_mc.c b/hw/mem/npcm7xx_mc.c | ||
35 | index XXXXXXX..XXXXXXX 100644 | ||
36 | --- a/hw/mem/npcm7xx_mc.c | ||
37 | +++ b/hw/mem/npcm7xx_mc.c | ||
38 | @@ -XXX,XX +XXX,XX @@ static void npcm7xx_mc_realize(DeviceState *dev, Error **errp) | ||
39 | |||
40 | memory_region_init_io(&s->mmio, OBJECT(s), &npcm7xx_mc_ops, s, "regs", | ||
41 | NPCM7XX_MC_REGS_SIZE); | ||
42 | - sysbus_init_mmio(&s->parent, &s->mmio); | ||
43 | + sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->mmio); | ||
44 | } | ||
45 | |||
46 | static void npcm7xx_mc_class_init(ObjectClass *klass, void *data) | ||
47 | diff --git a/hw/misc/npcm7xx_clk.c b/hw/misc/npcm7xx_clk.c | 23 | diff --git a/hw/misc/npcm7xx_clk.c b/hw/misc/npcm7xx_clk.c |
48 | index XXXXXXX..XXXXXXX 100644 | 24 | index XXXXXXX..XXXXXXX 100644 |
49 | --- a/hw/misc/npcm7xx_clk.c | 25 | --- a/hw/misc/npcm7xx_clk.c |
50 | +++ b/hw/misc/npcm7xx_clk.c | 26 | +++ b/hw/misc/npcm7xx_clk.c |
51 | @@ -XXX,XX +XXX,XX @@ static void npcm7xx_clk_init(Object *obj) | 27 | @@ -XXX,XX +XXX,XX @@ static void npcm7xx_clk_enter_reset(Object *obj, ResetType type) |
52 | 28 | ||
53 | memory_region_init_io(&s->iomem, obj, &npcm7xx_clk_ops, s, | 29 | QEMU_BUILD_BUG_ON(sizeof(s->regs) != sizeof(cold_reset_values)); |
54 | TYPE_NPCM7XX_CLK, 4 * KiB); | 30 | |
55 | - sysbus_init_mmio(&s->parent, &s->iomem); | 31 | - switch (type) { |
56 | + sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem); | 32 | - case RESET_TYPE_COLD: |
33 | - memcpy(s->regs, cold_reset_values, sizeof(cold_reset_values)); | ||
34 | - s->ref_ns = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); | ||
35 | - npcm7xx_clk_update_all_clocks(s); | ||
36 | - return; | ||
37 | - } | ||
38 | - | ||
39 | + memcpy(s->regs, cold_reset_values, sizeof(cold_reset_values)); | ||
40 | + s->ref_ns = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); | ||
41 | + npcm7xx_clk_update_all_clocks(s); | ||
42 | /* | ||
43 | * A small number of registers need to be reset on a core domain reset, | ||
44 | * but no such reset type exists yet. | ||
45 | */ | ||
46 | - qemu_log_mask(LOG_UNIMP, "%s: reset type %d not implemented.", | ||
47 | - __func__, type); | ||
57 | } | 48 | } |
58 | 49 | ||
59 | static int npcm7xx_clk_post_load(void *opaque, int version_id) | 50 | static void npcm7xx_clk_init_clock_hierarchy(NPCM7xxCLKState *s) |
60 | diff --git a/hw/misc/npcm7xx_gcr.c b/hw/misc/npcm7xx_gcr.c | 51 | diff --git a/hw/misc/npcm7xx_gcr.c b/hw/misc/npcm7xx_gcr.c |
61 | index XXXXXXX..XXXXXXX 100644 | 52 | index XXXXXXX..XXXXXXX 100644 |
62 | --- a/hw/misc/npcm7xx_gcr.c | 53 | --- a/hw/misc/npcm7xx_gcr.c |
63 | +++ b/hw/misc/npcm7xx_gcr.c | 54 | +++ b/hw/misc/npcm7xx_gcr.c |
64 | @@ -XXX,XX +XXX,XX @@ static void npcm7xx_gcr_init(Object *obj) | 55 | @@ -XXX,XX +XXX,XX @@ static void npcm7xx_gcr_enter_reset(Object *obj, ResetType type) |
65 | 56 | ||
66 | memory_region_init_io(&s->iomem, obj, &npcm7xx_gcr_ops, s, | 57 | QEMU_BUILD_BUG_ON(sizeof(s->regs) != sizeof(cold_reset_values)); |
67 | TYPE_NPCM7XX_GCR, 4 * KiB); | 58 | |
68 | - sysbus_init_mmio(&s->parent, &s->iomem); | 59 | - switch (type) { |
69 | + sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem); | 60 | - case RESET_TYPE_COLD: |
61 | - memcpy(s->regs, cold_reset_values, sizeof(s->regs)); | ||
62 | - s->regs[NPCM7XX_GCR_PWRON] = s->reset_pwron; | ||
63 | - s->regs[NPCM7XX_GCR_MDLR] = s->reset_mdlr; | ||
64 | - s->regs[NPCM7XX_GCR_INTCR3] = s->reset_intcr3; | ||
65 | - break; | ||
66 | - } | ||
67 | + memcpy(s->regs, cold_reset_values, sizeof(s->regs)); | ||
68 | + s->regs[NPCM7XX_GCR_PWRON] = s->reset_pwron; | ||
69 | + s->regs[NPCM7XX_GCR_MDLR] = s->reset_mdlr; | ||
70 | + s->regs[NPCM7XX_GCR_INTCR3] = s->reset_intcr3; | ||
70 | } | 71 | } |
71 | 72 | ||
72 | static const VMStateDescription vmstate_npcm7xx_gcr = { | 73 | static void npcm7xx_gcr_realize(DeviceState *dev, Error **errp) |
73 | diff --git a/hw/misc/npcm7xx_rng.c b/hw/misc/npcm7xx_rng.c | ||
74 | index XXXXXXX..XXXXXXX 100644 | ||
75 | --- a/hw/misc/npcm7xx_rng.c | ||
76 | +++ b/hw/misc/npcm7xx_rng.c | ||
77 | @@ -XXX,XX +XXX,XX @@ static void npcm7xx_rng_init(Object *obj) | ||
78 | |||
79 | memory_region_init_io(&s->iomem, obj, &npcm7xx_rng_ops, s, "regs", | ||
80 | NPCM7XX_RNG_REGS_SIZE); | ||
81 | - sysbus_init_mmio(&s->parent, &s->iomem); | ||
82 | + sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem); | ||
83 | } | ||
84 | |||
85 | static const VMStateDescription vmstate_npcm7xx_rng = { | ||
86 | diff --git a/hw/nvram/npcm7xx_otp.c b/hw/nvram/npcm7xx_otp.c | ||
87 | index XXXXXXX..XXXXXXX 100644 | ||
88 | --- a/hw/nvram/npcm7xx_otp.c | ||
89 | +++ b/hw/nvram/npcm7xx_otp.c | ||
90 | @@ -XXX,XX +XXX,XX @@ static void npcm7xx_otp_realize(DeviceState *dev, Error **errp) | ||
91 | { | ||
92 | NPCM7xxOTPClass *oc = NPCM7XX_OTP_GET_CLASS(dev); | ||
93 | NPCM7xxOTPState *s = NPCM7XX_OTP(dev); | ||
94 | - SysBusDevice *sbd = &s->parent; | ||
95 | + SysBusDevice *sbd = SYS_BUS_DEVICE(dev); | ||
96 | |||
97 | memset(s->array, 0, sizeof(s->array)); | ||
98 | |||
99 | diff --git a/hw/ssi/npcm7xx_fiu.c b/hw/ssi/npcm7xx_fiu.c | ||
100 | index XXXXXXX..XXXXXXX 100644 | ||
101 | --- a/hw/ssi/npcm7xx_fiu.c | ||
102 | +++ b/hw/ssi/npcm7xx_fiu.c | ||
103 | @@ -XXX,XX +XXX,XX @@ static void npcm7xx_fiu_hold_reset(Object *obj) | ||
104 | static void npcm7xx_fiu_realize(DeviceState *dev, Error **errp) | ||
105 | { | ||
106 | NPCM7xxFIUState *s = NPCM7XX_FIU(dev); | ||
107 | - SysBusDevice *sbd = &s->parent; | ||
108 | + SysBusDevice *sbd = SYS_BUS_DEVICE(dev); | ||
109 | int i; | ||
110 | |||
111 | if (s->cs_count <= 0) { | ||
112 | -- | 74 | -- |
113 | 2.20.1 | 75 | 2.34.1 |
114 | 76 | ||
115 | 77 | diff view generated by jsdifflib |
1 | A copy-and-paste error meant that the return value for register offset 0x44 | 1 | Rather than directly calling the device's implementation of its 'hold' |
---|---|---|---|
2 | (the RX Status FIFO PEEK register) returned a byte from a bogus offset in | 2 | reset phase, call device_cold_reset(). This means we don't have to |
3 | the rx status FIFO. Fix the typo. | 3 | adjust this callsite when we add another argument to the function |
4 | signature for the hold and exit reset methods. | ||
4 | 5 | ||
5 | Cc: qemu-stable@nongnu.org | ||
6 | Fixes: https://bugs.launchpad.net/qemu/+bug/1904954 | ||
7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
8 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
9 | Message-id: 20210108180401.2263-2-peter.maydell@linaro.org | 8 | Reviewed-by: Luc Michel <luc.michel@amd.com> |
9 | Message-id: 20240412160809.1260625-3-peter.maydell@linaro.org | ||
10 | --- | 10 | --- |
11 | hw/net/lan9118.c | 2 +- | 11 | hw/i2c/allwinner-i2c.c | 3 +-- |
12 | 1 file changed, 1 insertion(+), 1 deletion(-) | 12 | hw/sensor/adm1272.c | 2 +- |
13 | 2 files changed, 2 insertions(+), 3 deletions(-) | ||
13 | 14 | ||
14 | diff --git a/hw/net/lan9118.c b/hw/net/lan9118.c | 15 | diff --git a/hw/i2c/allwinner-i2c.c b/hw/i2c/allwinner-i2c.c |
15 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
16 | --- a/hw/net/lan9118.c | 17 | --- a/hw/i2c/allwinner-i2c.c |
17 | +++ b/hw/net/lan9118.c | 18 | +++ b/hw/i2c/allwinner-i2c.c |
18 | @@ -XXX,XX +XXX,XX @@ static uint64_t lan9118_readl(void *opaque, hwaddr offset, | 19 | @@ -XXX,XX +XXX,XX @@ static void allwinner_i2c_write(void *opaque, hwaddr offset, |
19 | case 0x40: | 20 | break; |
20 | return rx_status_fifo_pop(s); | 21 | case TWI_SRST_REG: |
21 | case 0x44: | 22 | if (((value & TWI_SRST_MASK) == 0) && (s->srst & TWI_SRST_MASK)) { |
22 | - return s->rx_status_fifo[s->tx_status_fifo_head]; | 23 | - /* Perform reset */ |
23 | + return s->rx_status_fifo[s->rx_status_fifo_head]; | 24 | - allwinner_i2c_reset_hold(OBJECT(s)); |
24 | case 0x48: | 25 | + device_cold_reset(DEVICE(s)); |
25 | return tx_status_fifo_pop(s); | 26 | } |
26 | case 0x4c: | 27 | s->srst = value & TWI_SRST_MASK; |
28 | break; | ||
29 | diff --git a/hw/sensor/adm1272.c b/hw/sensor/adm1272.c | ||
30 | index XXXXXXX..XXXXXXX 100644 | ||
31 | --- a/hw/sensor/adm1272.c | ||
32 | +++ b/hw/sensor/adm1272.c | ||
33 | @@ -XXX,XX +XXX,XX @@ static int adm1272_write_data(PMBusDevice *pmdev, const uint8_t *buf, | ||
34 | break; | ||
35 | |||
36 | case ADM1272_MFR_POWER_CYCLE: | ||
37 | - adm1272_exit_reset((Object *)s); | ||
38 | + device_cold_reset(DEVICE(s)); | ||
39 | break; | ||
40 | |||
41 | case ADM1272_HYSTERESIS_LOW: | ||
27 | -- | 42 | -- |
28 | 2.20.1 | 43 | 2.34.1 |
29 | |||
30 | diff view generated by jsdifflib |
1 | When we first converted our documentation to Sphinx, we split it into | 1 | We pass a ResetType argument to the Resettable class enter phase |
---|---|---|---|
2 | multiple manuals (system, interop, tools, etc), which are all built | 2 | method, but we don't pass it to hold and exit, even though the |
3 | separately. The primary driver for this was wanting to be able to | 3 | callsites have it readily available. This means that if a device |
4 | avoid shipping the 'devel' manual to end-users. However, this is | 4 | cared about the ResetType it would need to record it in the enter |
5 | working against the grain of the way Sphinx wants to be used and | 5 | phase method to use later on. We should pass the type to all three |
6 | causes some annoyances: | 6 | of the phase methods to avoid having to do that. |
7 | * Cross-references between documents become much harder or | ||
8 | possibly impossible | ||
9 | * There is no single index to the whole documentation | ||
10 | * Within one manual there's no links or table-of-contents info | ||
11 | that lets you easily navigate to the others | ||
12 | * The devel manual doesn't get published on the QEMU website | ||
13 | (it would be nice to able to refer to it there) | ||
14 | 7 | ||
15 | Merely hiding our developer documentation from end users seems like | 8 | This coccinelle script adds the ResetType argument to the hold and |
16 | it's not enough benefit for these costs. Combine all the | 9 | exit phases of the Resettable interface. |
17 | documentation into a single manual (the same way that the readthedocs | ||
18 | site builds it) and install the whole thing. The previous manual | ||
19 | divisions remain as the new top level sections in the manual. | ||
20 | 10 | ||
21 | * The per-manual conf.py files are no longer needed | 11 | The first part of the script (rules holdfn_assigned, holdfn_defined, |
22 | * The man_pages[] specifications previously in each per-manual | 12 | exitfn_assigned, exitfn_defined) update implementations of the |
23 | conf.py move to the top level conf.py | 13 | interface within device models, both to change the signature of their |
24 | * docs/meson.build logic is simplified as we now only need to run | 14 | method implementations and to pass on the reset type when they invoke |
25 | Sphinx once for the HTML and then once for the manpages5B | 15 | reset on some other device. |
26 | * The old index.html.in that produced the top-level page with | ||
27 | links to each manual is no longer needed | ||
28 | 16 | ||
29 | Unfortunately this means that we now have to build the HTML | 17 | The second part of the script is various special cases: |
30 | documentation into docs/manual in the build tree rather than directly | 18 | * method callsites in resettable_phase_hold(), resettable_phase_exit() |
31 | into docs/; otherwise it is too awkward to ensure we install only the | 19 | and device_phases_reset() |
32 | built manual and not also the dependency info, stamp file, etc. The | 20 | * updating the typedefs for the methods |
33 | manual still ends up in the same place in the final installed | 21 | * isl_pmbus_vr.c has some code where one device's reset method directly |
34 | directory, but anybody who was consulting documentation from within | 22 | calls the implementation of a different device's method |
35 | the build tree will have to adjust where they're looking. | ||
36 | 23 | ||
37 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 24 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
38 | Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> | 25 | Reviewed-by: Luc Michel <luc.michel@amd.com> |
39 | Message-id: 20210108161416.21129-3-peter.maydell@linaro.org | 26 | Message-id: 20240412160809.1260625-4-peter.maydell@linaro.org |
40 | --- | 27 | --- |
41 | docs/conf.py | 46 ++++++++++++++++++++++++++++++- | 28 | scripts/coccinelle/reset-type.cocci | 133 ++++++++++++++++++++++++++++ |
42 | docs/devel/conf.py | 15 ----------- | 29 | 1 file changed, 133 insertions(+) |
43 | docs/index.html.in | 17 ------------ | 30 | create mode 100644 scripts/coccinelle/reset-type.cocci |
44 | docs/interop/conf.py | 28 ------------------- | ||
45 | docs/meson.build | 64 +++++++++++++++++--------------------------- | ||
46 | docs/specs/conf.py | 16 ----------- | ||
47 | docs/system/conf.py | 28 ------------------- | ||
48 | docs/tools/conf.py | 37 ------------------------- | ||
49 | docs/user/conf.py | 15 ----------- | ||
50 | 9 files changed, 70 insertions(+), 196 deletions(-) | ||
51 | delete mode 100644 docs/devel/conf.py | ||
52 | delete mode 100644 docs/index.html.in | ||
53 | delete mode 100644 docs/interop/conf.py | ||
54 | delete mode 100644 docs/specs/conf.py | ||
55 | delete mode 100644 docs/system/conf.py | ||
56 | delete mode 100644 docs/tools/conf.py | ||
57 | delete mode 100644 docs/user/conf.py | ||
58 | 31 | ||
59 | diff --git a/docs/conf.py b/docs/conf.py | 32 | diff --git a/scripts/coccinelle/reset-type.cocci b/scripts/coccinelle/reset-type.cocci |
60 | index XXXXXXX..XXXXXXX 100644 | 33 | new file mode 100644 |
61 | --- a/docs/conf.py | ||
62 | +++ b/docs/conf.py | ||
63 | @@ -XXX,XX +XXX,XX @@ latex_documents = [ | ||
64 | |||
65 | # -- Options for manual page output --------------------------------------- | ||
66 | # Individual manual/conf.py can override this to create man pages | ||
67 | -man_pages = [] | ||
68 | +man_pages = [ | ||
69 | + ('interop/qemu-ga', 'qemu-ga', | ||
70 | + 'QEMU Guest Agent', | ||
71 | + ['Michael Roth <mdroth@linux.vnet.ibm.com>'], 8), | ||
72 | + ('interop/qemu-ga-ref', 'qemu-ga-ref', | ||
73 | + 'QEMU Guest Agent Protocol Reference', | ||
74 | + [], 7), | ||
75 | + ('interop/qemu-qmp-ref', 'qemu-qmp-ref', | ||
76 | + 'QEMU QMP Reference Manual', | ||
77 | + [], 7), | ||
78 | + ('interop/qemu-storage-daemon-qmp-ref', 'qemu-storage-daemon-qmp-ref', | ||
79 | + 'QEMU Storage Daemon QMP Reference Manual', | ||
80 | + [], 7), | ||
81 | + ('system/qemu-manpage', 'qemu', | ||
82 | + 'QEMU User Documentation', | ||
83 | + ['Fabrice Bellard'], 1), | ||
84 | + ('system/qemu-block-drivers', 'qemu-block-drivers', | ||
85 | + 'QEMU block drivers reference', | ||
86 | + ['Fabrice Bellard and the QEMU Project developers'], 7), | ||
87 | + ('system/qemu-cpu-models', 'qemu-cpu-models', | ||
88 | + 'QEMU CPU Models', | ||
89 | + ['The QEMU Project developers'], 7), | ||
90 | + ('tools/qemu-img', 'qemu-img', | ||
91 | + 'QEMU disk image utility', | ||
92 | + ['Fabrice Bellard'], 1), | ||
93 | + ('tools/qemu-nbd', 'qemu-nbd', | ||
94 | + 'QEMU Disk Network Block Device Server', | ||
95 | + ['Anthony Liguori <anthony@codemonkey.ws>'], 8), | ||
96 | + ('tools/qemu-pr-helper', 'qemu-pr-helper', | ||
97 | + 'QEMU persistent reservation helper', | ||
98 | + [], 8), | ||
99 | + ('tools/qemu-storage-daemon', 'qemu-storage-daemon', | ||
100 | + 'QEMU storage daemon', | ||
101 | + [], 1), | ||
102 | + ('tools/qemu-trace-stap', 'qemu-trace-stap', | ||
103 | + 'QEMU SystemTap trace tool', | ||
104 | + [], 1), | ||
105 | + ('tools/virtfs-proxy-helper', 'virtfs-proxy-helper', | ||
106 | + 'QEMU 9p virtfs proxy filesystem helper', | ||
107 | + ['M. Mohan Kumar'], 1), | ||
108 | + ('tools/virtiofsd', 'virtiofsd', | ||
109 | + 'QEMU virtio-fs shared file system daemon', | ||
110 | + ['Stefan Hajnoczi <stefanha@redhat.com>', | ||
111 | + 'Masayoshi Mizuma <m.mizuma@jp.fujitsu.com>'], 1), | ||
112 | +] | ||
113 | |||
114 | # -- Options for Texinfo output ------------------------------------------- | ||
115 | |||
116 | diff --git a/docs/devel/conf.py b/docs/devel/conf.py | ||
117 | deleted file mode 100644 | ||
118 | index XXXXXXX..XXXXXXX | 34 | index XXXXXXX..XXXXXXX |
119 | --- a/docs/devel/conf.py | 35 | --- /dev/null |
120 | +++ /dev/null | 36 | +++ b/scripts/coccinelle/reset-type.cocci |
121 | @@ -XXX,XX +XXX,XX @@ | 37 | @@ -XXX,XX +XXX,XX @@ |
122 | -# -*- coding: utf-8 -*- | 38 | +// Convert device code using three-phase reset to add a ResetType |
123 | -# | 39 | +// argument to implementations of ResettableHoldPhase and |
124 | -# QEMU documentation build configuration file for the 'devel' manual. | 40 | +// ResettableEnterPhase methods. |
125 | -# | 41 | +// |
126 | -# This includes the top level conf file and then makes any necessary tweaks. | 42 | +// Copyright Linaro Ltd 2024 |
127 | -import sys | 43 | +// SPDX-License-Identifier: GPL-2.0-or-later |
128 | -import os | 44 | +// |
129 | - | 45 | +// for dir in include hw target; do \ |
130 | -qemu_docdir = os.path.abspath("..") | 46 | +// spatch --macro-file scripts/cocci-macro-file.h \ |
131 | -parent_config = os.path.join(qemu_docdir, "conf.py") | 47 | +// --sp-file scripts/coccinelle/reset-type.cocci \ |
132 | -exec(compile(open(parent_config, "rb").read(), parent_config, 'exec')) | 48 | +// --keep-comments --smpl-spacing --in-place --include-headers \ |
133 | - | 49 | +// --dir $dir; done |
134 | -# This slightly misuses the 'description', but is the best way to get | 50 | +// |
135 | -# the manual title to appear in the sidebar. | 51 | +// This coccinelle script aims to produce a complete change that needs |
136 | -html_theme_options['description'] = u'Developer''s Guide' | 52 | +// no human interaction, so as well as the generic "update device |
137 | diff --git a/docs/index.html.in b/docs/index.html.in | 53 | +// implementations of the hold and exit phase methods" it includes |
138 | deleted file mode 100644 | 54 | +// the special-case transformations needed for the core code and for |
139 | index XXXXXXX..XXXXXXX | 55 | +// one device model that does something a bit nonstandard. Those |
140 | --- a/docs/index.html.in | 56 | +// special cases are at the end of the file. |
141 | +++ /dev/null | ||
142 | @@ -XXX,XX +XXX,XX @@ | ||
143 | -<!DOCTYPE html> | ||
144 | -<html lang="en"> | ||
145 | - <head> | ||
146 | - <meta charset="UTF-8"> | ||
147 | - <title>QEMU @VERSION@ Documentation</title> | ||
148 | - </head> | ||
149 | - <body> | ||
150 | - <h1>QEMU @VERSION@ Documentation</h1> | ||
151 | - <ul> | ||
152 | - <li><a href="system/index.html">System Emulation User's Guide</a></li> | ||
153 | - <li><a href="user/index.html">User Mode Emulation User's Guide</a></li> | ||
154 | - <li><a href="tools/index.html">Tools Guide</a></li> | ||
155 | - <li><a href="interop/index.html">System Emulation Management and Interoperability Guide</a></li> | ||
156 | - <li><a href="specs/index.html">System Emulation Guest Hardware Specifications</a></li> | ||
157 | - </ul> | ||
158 | - </body> | ||
159 | -</html> | ||
160 | diff --git a/docs/interop/conf.py b/docs/interop/conf.py | ||
161 | deleted file mode 100644 | ||
162 | index XXXXXXX..XXXXXXX | ||
163 | --- a/docs/interop/conf.py | ||
164 | +++ /dev/null | ||
165 | @@ -XXX,XX +XXX,XX @@ | ||
166 | -# -*- coding: utf-8 -*- | ||
167 | -# | ||
168 | -# QEMU documentation build configuration file for the 'interop' manual. | ||
169 | -# | ||
170 | -# This includes the top level conf file and then makes any necessary tweaks. | ||
171 | -import sys | ||
172 | -import os | ||
173 | - | ||
174 | -qemu_docdir = os.path.abspath("..") | ||
175 | -parent_config = os.path.join(qemu_docdir, "conf.py") | ||
176 | -exec(compile(open(parent_config, "rb").read(), parent_config, 'exec')) | ||
177 | - | ||
178 | -# This slightly misuses the 'description', but is the best way to get | ||
179 | -# the manual title to appear in the sidebar. | ||
180 | -html_theme_options['description'] = u'System Emulation Management and Interoperability Guide' | ||
181 | - | ||
182 | -# One entry per manual page. List of tuples | ||
183 | -# (source start file, name, description, authors, manual section). | ||
184 | -man_pages = [ | ||
185 | - ('qemu-ga', 'qemu-ga', u'QEMU Guest Agent', | ||
186 | - ['Michael Roth <mdroth@linux.vnet.ibm.com>'], 8), | ||
187 | - ('qemu-ga-ref', 'qemu-ga-ref', 'QEMU Guest Agent Protocol Reference', | ||
188 | - [], 7), | ||
189 | - ('qemu-qmp-ref', 'qemu-qmp-ref', 'QEMU QMP Reference Manual', | ||
190 | - [], 7), | ||
191 | - ('qemu-storage-daemon-qmp-ref', 'qemu-storage-daemon-qmp-ref', | ||
192 | - 'QEMU Storage Daemon QMP Reference Manual', [], 7), | ||
193 | -] | ||
194 | diff --git a/docs/meson.build b/docs/meson.build | ||
195 | index XXXXXXX..XXXXXXX 100644 | ||
196 | --- a/docs/meson.build | ||
197 | +++ b/docs/meson.build | ||
198 | @@ -XXX,XX +XXX,XX @@ if build_docs | ||
199 | meson.source_root() / 'docs/sphinx/qmp_lexer.py', | ||
200 | qapi_gen_depends ] | ||
201 | |||
202 | - configure_file(output: 'index.html', | ||
203 | - input: files('index.html.in'), | ||
204 | - configuration: {'VERSION': meson.project_version()}, | ||
205 | - install_dir: qemu_docdir) | ||
206 | - manuals = [ 'devel', 'interop', 'tools', 'specs', 'system', 'user' ] | ||
207 | man_pages = { | ||
208 | - 'interop' : { | ||
209 | 'qemu-ga.8': (have_tools ? 'man8' : ''), | ||
210 | 'qemu-ga-ref.7': 'man7', | ||
211 | 'qemu-qmp-ref.7': 'man7', | ||
212 | 'qemu-storage-daemon-qmp-ref.7': (have_tools ? 'man7' : ''), | ||
213 | - }, | ||
214 | - 'tools': { | ||
215 | 'qemu-img.1': (have_tools ? 'man1' : ''), | ||
216 | 'qemu-nbd.8': (have_tools ? 'man8' : ''), | ||
217 | 'qemu-pr-helper.8': (have_tools ? 'man8' : ''), | ||
218 | @@ -XXX,XX +XXX,XX @@ if build_docs | ||
219 | 'qemu-trace-stap.1': (config_host.has_key('CONFIG_TRACE_SYSTEMTAP') ? 'man1' : ''), | ||
220 | 'virtfs-proxy-helper.1': (have_virtfs_proxy_helper ? 'man1' : ''), | ||
221 | 'virtiofsd.1': (have_virtiofsd ? 'man1' : ''), | ||
222 | - }, | ||
223 | - 'system': { | ||
224 | 'qemu.1': 'man1', | ||
225 | 'qemu-block-drivers.7': 'man7', | ||
226 | 'qemu-cpu-models.7': 'man7' | ||
227 | - }, | ||
228 | } | ||
229 | |||
230 | sphinxdocs = [] | ||
231 | sphinxmans = [] | ||
232 | - foreach manual : manuals | ||
233 | - private_dir = meson.current_build_dir() / (manual + '.p') | ||
234 | - output_dir = meson.current_build_dir() / manual | ||
235 | - input_dir = meson.current_source_dir() / manual | ||
236 | |||
237 | - this_manual = custom_target(manual + ' manual', | ||
238 | + private_dir = meson.current_build_dir() / 'manual.p' | ||
239 | + output_dir = meson.current_build_dir() / 'manual' | ||
240 | + input_dir = meson.current_source_dir() | ||
241 | + | 57 | + |
242 | + this_manual = custom_target('QEMU manual', | 58 | +// Look for where we use a function as a ResettableHoldPhase method, |
243 | build_by_default: build_docs, | 59 | +// either by directly assigning it to phases.hold or by calling |
244 | - output: [manual + '.stamp'], | 60 | +// resettable_class_set_parent_phases, and remember the function name. |
245 | - input: [files('conf.py'), files(manual / 'conf.py')], | 61 | +@ holdfn_assigned @ |
246 | - depfile: manual + '.d', | 62 | +identifier enterfn, holdfn, exitfn; |
247 | + output: 'docs.stamp', | 63 | +identifier rc; |
248 | + input: files('conf.py'), | 64 | +expression e; |
249 | + depfile: 'docs.d', | 65 | +@@ |
250 | depend_files: sphinx_extn_depends, | 66 | +ResettableClass *rc; |
251 | command: [SPHINX_ARGS, '-Ddepfile=@DEPFILE@', | 67 | +... |
252 | '-Ddepfile_stamp=@OUTPUT0@', | 68 | +( |
253 | '-b', 'html', '-d', private_dir, | 69 | + rc->phases.hold = holdfn; |
254 | input_dir, output_dir]) | 70 | +| |
255 | - sphinxdocs += this_manual | 71 | + resettable_class_set_parent_phases(rc, enterfn, holdfn, exitfn, e); |
256 | - if build_docs and manual != 'devel' | 72 | +) |
257 | - install_subdir(output_dir, install_dir: qemu_docdir) | ||
258 | - endif | ||
259 | + sphinxdocs += this_manual | ||
260 | + install_subdir(output_dir, install_dir: qemu_docdir, strip_directory: true) | ||
261 | |||
262 | - these_man_pages = [] | ||
263 | - install_dirs = [] | ||
264 | - foreach page, section : man_pages.get(manual, {}) | ||
265 | - these_man_pages += page | ||
266 | - install_dirs += section == '' ? false : get_option('mandir') / section | ||
267 | - endforeach | ||
268 | - if these_man_pages.length() > 0 | ||
269 | - sphinxmans += custom_target(manual + ' man pages', | ||
270 | - build_by_default: build_docs, | ||
271 | - output: these_man_pages, | ||
272 | - input: this_manual, | ||
273 | - install: build_docs, | ||
274 | - install_dir: install_dirs, | ||
275 | - command: [SPHINX_ARGS, '-b', 'man', '-d', private_dir, | ||
276 | - input_dir, meson.current_build_dir()]) | ||
277 | - endif | ||
278 | + these_man_pages = [] | ||
279 | + install_dirs = [] | ||
280 | + foreach page, section : man_pages | ||
281 | + these_man_pages += page | ||
282 | + install_dirs += section == '' ? false : get_option('mandir') / section | ||
283 | endforeach | ||
284 | + | 73 | + |
285 | + sphinxmans += custom_target('QEMU man pages', | 74 | +// Look for the definition of the function we found in holdfn_assigned, |
286 | + build_by_default: build_docs, | 75 | +// and add the new argument. If the function calls a hold function |
287 | + output: these_man_pages, | 76 | +// itself (probably chaining to the parent class reset) then add the |
288 | + input: this_manual, | 77 | +// new argument there too. |
289 | + install: build_docs, | 78 | +@ holdfn_defined @ |
290 | + install_dir: install_dirs, | 79 | +identifier holdfn_assigned.holdfn; |
291 | + command: [SPHINX_ARGS, '-b', 'man', '-d', private_dir, | 80 | +typedef Object; |
292 | + input_dir, meson.current_build_dir()]) | 81 | +identifier obj; |
82 | +expression parent; | ||
83 | +@@ | ||
84 | +-holdfn(Object *obj) | ||
85 | ++holdfn(Object *obj, ResetType type) | ||
86 | +{ | ||
87 | + <... | ||
88 | +- parent.hold(obj) | ||
89 | ++ parent.hold(obj, type) | ||
90 | + ...> | ||
91 | +} | ||
293 | + | 92 | + |
294 | alias_target('sphinxdocs', sphinxdocs) | 93 | +// Similarly for ResettableExitPhase. |
295 | alias_target('html', sphinxdocs) | 94 | +@ exitfn_assigned @ |
296 | alias_target('man', sphinxmans) | 95 | +identifier enterfn, holdfn, exitfn; |
297 | diff --git a/docs/specs/conf.py b/docs/specs/conf.py | 96 | +identifier rc; |
298 | deleted file mode 100644 | 97 | +expression e; |
299 | index XXXXXXX..XXXXXXX | 98 | +@@ |
300 | --- a/docs/specs/conf.py | 99 | +ResettableClass *rc; |
301 | +++ /dev/null | 100 | +... |
302 | @@ -XXX,XX +XXX,XX @@ | 101 | +( |
303 | -# -*- coding: utf-8 -*- | 102 | + rc->phases.exit = exitfn; |
304 | -# | 103 | +| |
305 | -# QEMU documentation build configuration file for the 'specs' manual. | 104 | + resettable_class_set_parent_phases(rc, enterfn, holdfn, exitfn, e); |
306 | -# | 105 | +) |
307 | -# This includes the top level conf file and then makes any necessary tweaks. | 106 | +@ exitfn_defined @ |
308 | -import sys | 107 | +identifier exitfn_assigned.exitfn; |
309 | -import os | 108 | +typedef Object; |
310 | - | 109 | +identifier obj; |
311 | -qemu_docdir = os.path.abspath("..") | 110 | +expression parent; |
312 | -parent_config = os.path.join(qemu_docdir, "conf.py") | 111 | +@@ |
313 | -exec(compile(open(parent_config, "rb").read(), parent_config, 'exec')) | 112 | +-exitfn(Object *obj) |
314 | - | 113 | ++exitfn(Object *obj, ResetType type) |
315 | -# This slightly misuses the 'description', but is the best way to get | 114 | +{ |
316 | -# the manual title to appear in the sidebar. | 115 | + <... |
317 | -html_theme_options['description'] = \ | 116 | +- parent.exit(obj) |
318 | - u'System Emulation Guest Hardware Specifications' | 117 | ++ parent.exit(obj, type) |
319 | diff --git a/docs/system/conf.py b/docs/system/conf.py | 118 | + ...> |
320 | deleted file mode 100644 | 119 | +} |
321 | index XXXXXXX..XXXXXXX | 120 | + |
322 | --- a/docs/system/conf.py | 121 | +// SPECIAL CASES ONLY BELOW HERE |
323 | +++ /dev/null | 122 | +// We use a python scripted constraint on the position of the match |
324 | @@ -XXX,XX +XXX,XX @@ | 123 | +// to ensure that they only match in a particular function. See |
325 | -# -*- coding: utf-8 -*- | 124 | +// https://public-inbox.org/git/alpine.DEB.2.21.1808240652370.2344@hadrien/ |
326 | -# | 125 | +// which recommends this as the way to do "match only in this function". |
327 | -# QEMU documentation build configuration file for the 'system' manual. | 126 | + |
328 | -# | 127 | +// Special case: isl_pmbus_vr.c has some reset methods calling others directly |
329 | -# This includes the top level conf file and then makes any necessary tweaks. | 128 | +@ isl_pmbus_vr @ |
330 | -import sys | 129 | +identifier obj; |
331 | -import os | 130 | +@@ |
332 | - | 131 | +- isl_pmbus_vr_exit_reset(obj); |
333 | -qemu_docdir = os.path.abspath("..") | 132 | ++ isl_pmbus_vr_exit_reset(obj, type); |
334 | -parent_config = os.path.join(qemu_docdir, "conf.py") | 133 | + |
335 | -exec(compile(open(parent_config, "rb").read(), parent_config, 'exec')) | 134 | +// Special case: device_phases_reset() needs to pass RESET_TYPE_COLD |
336 | - | 135 | +@ device_phases_reset_hold @ |
337 | -# This slightly misuses the 'description', but is the best way to get | 136 | +expression obj; |
338 | -# the manual title to appear in the sidebar. | 137 | +identifier rc; |
339 | -html_theme_options['description'] = u'System Emulation User''s Guide' | 138 | +identifier phase; |
340 | - | 139 | +position p : script:python() { p[0].current_element == "device_phases_reset" }; |
341 | -# One entry per manual page. List of tuples | 140 | +@@ |
342 | -# (source start file, name, description, authors, manual section). | 141 | +- rc->phases.phase(obj)@p |
343 | -man_pages = [ | 142 | ++ rc->phases.phase(obj, RESET_TYPE_COLD) |
344 | - ('qemu-manpage', 'qemu', u'QEMU User Documentation', | 143 | + |
345 | - ['Fabrice Bellard'], 1), | 144 | +// Special case: in resettable_phase_hold() and resettable_phase_exit() |
346 | - ('qemu-block-drivers', 'qemu-block-drivers', | 145 | +// we need to pass through the ResetType argument to the method being called |
347 | - u'QEMU block drivers reference', | 146 | +@ resettable_phase_hold @ |
348 | - ['Fabrice Bellard and the QEMU Project developers'], 7), | 147 | +expression obj; |
349 | - ('qemu-cpu-models', 'qemu-cpu-models', | 148 | +identifier rc; |
350 | - u'QEMU CPU Models', | 149 | +position p : script:python() { p[0].current_element == "resettable_phase_hold" }; |
351 | - ['The QEMU Project developers'], 7) | 150 | +@@ |
352 | -] | 151 | +- rc->phases.hold(obj)@p |
353 | diff --git a/docs/tools/conf.py b/docs/tools/conf.py | 152 | ++ rc->phases.hold(obj, type) |
354 | deleted file mode 100644 | 153 | +@ resettable_phase_exit @ |
355 | index XXXXXXX..XXXXXXX | 154 | +expression obj; |
356 | --- a/docs/tools/conf.py | 155 | +identifier rc; |
357 | +++ /dev/null | 156 | +position p : script:python() { p[0].current_element == "resettable_phase_exit" }; |
358 | @@ -XXX,XX +XXX,XX @@ | 157 | +@@ |
359 | -# -*- coding: utf-8 -*- | 158 | +- rc->phases.exit(obj)@p |
360 | -# | 159 | ++ rc->phases.exit(obj, type) |
361 | -# QEMU documentation build configuration file for the 'tools' manual. | 160 | +// Special case: the typedefs for the methods need to declare the new argument |
362 | -# | 161 | +@ phase_typedef_hold @ |
363 | -# This includes the top level conf file and then makes any necessary tweaks. | 162 | +identifier obj; |
364 | -import sys | 163 | +@@ |
365 | -import os | 164 | +- typedef void (*ResettableHoldPhase)(Object *obj); |
366 | - | 165 | ++ typedef void (*ResettableHoldPhase)(Object *obj, ResetType type); |
367 | -qemu_docdir = os.path.abspath("..") | 166 | +@ phase_typedef_exit @ |
368 | -parent_config = os.path.join(qemu_docdir, "conf.py") | 167 | +identifier obj; |
369 | -exec(compile(open(parent_config, "rb").read(), parent_config, 'exec')) | 168 | +@@ |
370 | - | 169 | +- typedef void (*ResettableExitPhase)(Object *obj); |
371 | -# This slightly misuses the 'description', but is the best way to get | 170 | ++ typedef void (*ResettableExitPhase)(Object *obj, ResetType type); |
372 | -# the manual title to appear in the sidebar. | ||
373 | -html_theme_options['description'] = \ | ||
374 | - u'Tools Guide' | ||
375 | - | ||
376 | -# One entry per manual page. List of tuples | ||
377 | -# (source start file, name, description, authors, manual section). | ||
378 | -man_pages = [ | ||
379 | - ('qemu-img', 'qemu-img', u'QEMU disk image utility', | ||
380 | - ['Fabrice Bellard'], 1), | ||
381 | - ('qemu-storage-daemon', 'qemu-storage-daemon', u'QEMU storage daemon', | ||
382 | - [], 1), | ||
383 | - ('qemu-nbd', 'qemu-nbd', u'QEMU Disk Network Block Device Server', | ||
384 | - ['Anthony Liguori <anthony@codemonkey.ws>'], 8), | ||
385 | - ('qemu-pr-helper', 'qemu-pr-helper', 'QEMU persistent reservation helper', | ||
386 | - [], 8), | ||
387 | - ('qemu-trace-stap', 'qemu-trace-stap', u'QEMU SystemTap trace tool', | ||
388 | - [], 1), | ||
389 | - ('virtfs-proxy-helper', 'virtfs-proxy-helper', | ||
390 | - u'QEMU 9p virtfs proxy filesystem helper', | ||
391 | - ['M. Mohan Kumar'], 1), | ||
392 | - ('virtiofsd', 'virtiofsd', u'QEMU virtio-fs shared file system daemon', | ||
393 | - ['Stefan Hajnoczi <stefanha@redhat.com>', | ||
394 | - 'Masayoshi Mizuma <m.mizuma@jp.fujitsu.com>'], 1), | ||
395 | -] | ||
396 | diff --git a/docs/user/conf.py b/docs/user/conf.py | ||
397 | deleted file mode 100644 | ||
398 | index XXXXXXX..XXXXXXX | ||
399 | --- a/docs/user/conf.py | ||
400 | +++ /dev/null | ||
401 | @@ -XXX,XX +XXX,XX @@ | ||
402 | -# -*- coding: utf-8 -*- | ||
403 | -# | ||
404 | -# QEMU documentation build configuration file for the 'user' manual. | ||
405 | -# | ||
406 | -# This includes the top level conf file and then makes any necessary tweaks. | ||
407 | -import sys | ||
408 | -import os | ||
409 | - | ||
410 | -qemu_docdir = os.path.abspath("..") | ||
411 | -parent_config = os.path.join(qemu_docdir, "conf.py") | ||
412 | -exec(compile(open(parent_config, "rb").read(), parent_config, 'exec')) | ||
413 | - | ||
414 | -# This slightly misuses the 'description', but is the best way to get | ||
415 | -# the manual title to appear in the sidebar. | ||
416 | -html_theme_options['description'] = u'User Mode Emulation User''s Guide' | ||
417 | -- | 171 | -- |
418 | 2.20.1 | 172 | 2.34.1 |
419 | |||
420 | diff view generated by jsdifflib |
1 | From: Hao Wu <wuhaotsh@google.com> | 1 | We pass a ResetType argument to the Resettable class enter |
---|---|---|---|
2 | phase method, but we don't pass it to hold and exit, even though | ||
3 | the callsites have it readily available. This means that if | ||
4 | a device cared about the ResetType it would need to record it | ||
5 | in the enter phase method to use later on. Pass the type to | ||
6 | all three of the phase methods to avoid having to do that. | ||
2 | 7 | ||
3 | This patch makes NPCM7XX Timer to use a the timer clock generated by the | 8 | Commit created with |
4 | CLK module instead of the magic number TIMER_REF_HZ. | ||
5 | 9 | ||
6 | Reviewed-by: Havard Skinnemoen <hskinnemoen@google.com> | 10 | for dir in hw target include; do \ |
7 | Reviewed-by: Tyrone Ting <kfting@nuvoton.com> | 11 | spatch --macro-file scripts/cocci-macro-file.h \ |
8 | Signed-off-by: Hao Wu <wuhaotsh@google.com> | 12 | --sp-file scripts/coccinelle/reset-type.cocci \ |
9 | Message-id: 20210108190945.949196-3-wuhaotsh@google.com | 13 | --keep-comments --smpl-spacing --in-place \ |
10 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 14 | --include-headers --dir $dir; done |
15 | |||
16 | and no manual edits. | ||
17 | |||
11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 18 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
19 | Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> | ||
20 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
21 | Reviewed-by: Luc Michel <luc.michel@amd.com> | ||
22 | Message-id: 20240412160809.1260625-5-peter.maydell@linaro.org | ||
12 | --- | 23 | --- |
13 | include/hw/misc/npcm7xx_clk.h | 6 ----- | 24 | include/hw/resettable.h | 4 ++-- |
14 | include/hw/timer/npcm7xx_timer.h | 1 + | 25 | hw/adc/npcm7xx_adc.c | 2 +- |
15 | hw/arm/npcm7xx.c | 5 ++++ | 26 | hw/arm/pxa2xx_pic.c | 2 +- |
16 | hw/timer/npcm7xx_timer.c | 39 +++++++++++++++----------------- | 27 | hw/arm/smmu-common.c | 2 +- |
17 | 4 files changed, 24 insertions(+), 27 deletions(-) | 28 | hw/arm/smmuv3.c | 4 ++-- |
29 | hw/arm/stellaris.c | 10 +++++----- | ||
30 | hw/audio/asc.c | 2 +- | ||
31 | hw/char/cadence_uart.c | 2 +- | ||
32 | hw/char/sifive_uart.c | 2 +- | ||
33 | hw/core/cpu-common.c | 2 +- | ||
34 | hw/core/qdev.c | 4 ++-- | ||
35 | hw/core/reset.c | 2 +- | ||
36 | hw/core/resettable.c | 4 ++-- | ||
37 | hw/display/virtio-vga.c | 4 ++-- | ||
38 | hw/gpio/npcm7xx_gpio.c | 2 +- | ||
39 | hw/gpio/pl061.c | 2 +- | ||
40 | hw/gpio/stm32l4x5_gpio.c | 2 +- | ||
41 | hw/hyperv/vmbus.c | 2 +- | ||
42 | hw/i2c/allwinner-i2c.c | 2 +- | ||
43 | hw/i2c/npcm7xx_smbus.c | 2 +- | ||
44 | hw/input/adb.c | 2 +- | ||
45 | hw/input/ps2.c | 12 ++++++------ | ||
46 | hw/intc/arm_gic_common.c | 2 +- | ||
47 | hw/intc/arm_gic_kvm.c | 4 ++-- | ||
48 | hw/intc/arm_gicv3_common.c | 2 +- | ||
49 | hw/intc/arm_gicv3_its.c | 4 ++-- | ||
50 | hw/intc/arm_gicv3_its_common.c | 2 +- | ||
51 | hw/intc/arm_gicv3_its_kvm.c | 4 ++-- | ||
52 | hw/intc/arm_gicv3_kvm.c | 4 ++-- | ||
53 | hw/intc/xics.c | 2 +- | ||
54 | hw/m68k/q800-glue.c | 2 +- | ||
55 | hw/misc/djmemc.c | 2 +- | ||
56 | hw/misc/iosb.c | 2 +- | ||
57 | hw/misc/mac_via.c | 8 ++++---- | ||
58 | hw/misc/macio/cuda.c | 4 ++-- | ||
59 | hw/misc/macio/pmu.c | 4 ++-- | ||
60 | hw/misc/mos6522.c | 2 +- | ||
61 | hw/misc/npcm7xx_mft.c | 2 +- | ||
62 | hw/misc/npcm7xx_pwm.c | 2 +- | ||
63 | hw/misc/stm32l4x5_exti.c | 2 +- | ||
64 | hw/misc/stm32l4x5_rcc.c | 10 +++++----- | ||
65 | hw/misc/stm32l4x5_syscfg.c | 2 +- | ||
66 | hw/misc/xlnx-versal-cframe-reg.c | 2 +- | ||
67 | hw/misc/xlnx-versal-crl.c | 2 +- | ||
68 | hw/misc/xlnx-versal-pmc-iou-slcr.c | 2 +- | ||
69 | hw/misc/xlnx-versal-trng.c | 2 +- | ||
70 | hw/misc/xlnx-versal-xramc.c | 2 +- | ||
71 | hw/misc/xlnx-zynqmp-apu-ctrl.c | 2 +- | ||
72 | hw/misc/xlnx-zynqmp-crf.c | 2 +- | ||
73 | hw/misc/zynq_slcr.c | 4 ++-- | ||
74 | hw/net/can/xlnx-zynqmp-can.c | 2 +- | ||
75 | hw/net/e1000.c | 2 +- | ||
76 | hw/net/e1000e.c | 2 +- | ||
77 | hw/net/igb.c | 2 +- | ||
78 | hw/net/igbvf.c | 2 +- | ||
79 | hw/nvram/xlnx-bbram.c | 2 +- | ||
80 | hw/nvram/xlnx-versal-efuse-ctrl.c | 2 +- | ||
81 | hw/nvram/xlnx-zynqmp-efuse.c | 2 +- | ||
82 | hw/pci-bridge/cxl_root_port.c | 4 ++-- | ||
83 | hw/pci-bridge/pcie_root_port.c | 2 +- | ||
84 | hw/pci-host/bonito.c | 2 +- | ||
85 | hw/pci-host/pnv_phb.c | 4 ++-- | ||
86 | hw/pci-host/pnv_phb3_msi.c | 4 ++-- | ||
87 | hw/pci/pci.c | 4 ++-- | ||
88 | hw/rtc/mc146818rtc.c | 2 +- | ||
89 | hw/s390x/css-bridge.c | 2 +- | ||
90 | hw/sensor/adm1266.c | 2 +- | ||
91 | hw/sensor/adm1272.c | 2 +- | ||
92 | hw/sensor/isl_pmbus_vr.c | 10 +++++----- | ||
93 | hw/sensor/max31785.c | 2 +- | ||
94 | hw/sensor/max34451.c | 2 +- | ||
95 | hw/ssi/npcm7xx_fiu.c | 2 +- | ||
96 | hw/timer/etraxfs_timer.c | 2 +- | ||
97 | hw/timer/npcm7xx_timer.c | 2 +- | ||
98 | hw/usb/hcd-dwc2.c | 8 ++++---- | ||
99 | hw/usb/xlnx-versal-usb2-ctrl-regs.c | 2 +- | ||
100 | hw/virtio/virtio-pci.c | 2 +- | ||
101 | target/arm/cpu.c | 4 ++-- | ||
102 | target/avr/cpu.c | 4 ++-- | ||
103 | target/cris/cpu.c | 4 ++-- | ||
104 | target/hexagon/cpu.c | 4 ++-- | ||
105 | target/i386/cpu.c | 4 ++-- | ||
106 | target/loongarch/cpu.c | 4 ++-- | ||
107 | target/m68k/cpu.c | 4 ++-- | ||
108 | target/microblaze/cpu.c | 4 ++-- | ||
109 | target/mips/cpu.c | 4 ++-- | ||
110 | target/openrisc/cpu.c | 4 ++-- | ||
111 | target/ppc/cpu_init.c | 4 ++-- | ||
112 | target/riscv/cpu.c | 4 ++-- | ||
113 | target/rx/cpu.c | 4 ++-- | ||
114 | target/sh4/cpu.c | 4 ++-- | ||
115 | target/sparc/cpu.c | 4 ++-- | ||
116 | target/tricore/cpu.c | 4 ++-- | ||
117 | target/xtensa/cpu.c | 4 ++-- | ||
118 | 94 files changed, 150 insertions(+), 150 deletions(-) | ||
18 | 119 | ||
19 | diff --git a/include/hw/misc/npcm7xx_clk.h b/include/hw/misc/npcm7xx_clk.h | 120 | diff --git a/include/hw/resettable.h b/include/hw/resettable.h |
20 | index XXXXXXX..XXXXXXX 100644 | 121 | index XXXXXXX..XXXXXXX 100644 |
21 | --- a/include/hw/misc/npcm7xx_clk.h | 122 | --- a/include/hw/resettable.h |
22 | +++ b/include/hw/misc/npcm7xx_clk.h | 123 | +++ b/include/hw/resettable.h |
124 | @@ -XXX,XX +XXX,XX @@ typedef enum ResetType { | ||
125 | * the callback. | ||
126 | */ | ||
127 | typedef void (*ResettableEnterPhase)(Object *obj, ResetType type); | ||
128 | -typedef void (*ResettableHoldPhase)(Object *obj); | ||
129 | -typedef void (*ResettableExitPhase)(Object *obj); | ||
130 | +typedef void (*ResettableHoldPhase)(Object *obj, ResetType type); | ||
131 | +typedef void (*ResettableExitPhase)(Object *obj, ResetType type); | ||
132 | typedef ResettableState * (*ResettableGetState)(Object *obj); | ||
133 | typedef void (*ResettableTrFunction)(Object *obj); | ||
134 | typedef ResettableTrFunction (*ResettableGetTrFunction)(Object *obj); | ||
135 | diff --git a/hw/adc/npcm7xx_adc.c b/hw/adc/npcm7xx_adc.c | ||
136 | index XXXXXXX..XXXXXXX 100644 | ||
137 | --- a/hw/adc/npcm7xx_adc.c | ||
138 | +++ b/hw/adc/npcm7xx_adc.c | ||
139 | @@ -XXX,XX +XXX,XX @@ static void npcm7xx_adc_enter_reset(Object *obj, ResetType type) | ||
140 | npcm7xx_adc_reset(s); | ||
141 | } | ||
142 | |||
143 | -static void npcm7xx_adc_hold_reset(Object *obj) | ||
144 | +static void npcm7xx_adc_hold_reset(Object *obj, ResetType type) | ||
145 | { | ||
146 | NPCM7xxADCState *s = NPCM7XX_ADC(obj); | ||
147 | |||
148 | diff --git a/hw/arm/pxa2xx_pic.c b/hw/arm/pxa2xx_pic.c | ||
149 | index XXXXXXX..XXXXXXX 100644 | ||
150 | --- a/hw/arm/pxa2xx_pic.c | ||
151 | +++ b/hw/arm/pxa2xx_pic.c | ||
152 | @@ -XXX,XX +XXX,XX @@ static int pxa2xx_pic_post_load(void *opaque, int version_id) | ||
153 | return 0; | ||
154 | } | ||
155 | |||
156 | -static void pxa2xx_pic_reset_hold(Object *obj) | ||
157 | +static void pxa2xx_pic_reset_hold(Object *obj, ResetType type) | ||
158 | { | ||
159 | PXA2xxPICState *s = PXA2XX_PIC(obj); | ||
160 | |||
161 | diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c | ||
162 | index XXXXXXX..XXXXXXX 100644 | ||
163 | --- a/hw/arm/smmu-common.c | ||
164 | +++ b/hw/arm/smmu-common.c | ||
165 | @@ -XXX,XX +XXX,XX @@ static void smmu_base_realize(DeviceState *dev, Error **errp) | ||
166 | } | ||
167 | } | ||
168 | |||
169 | -static void smmu_base_reset_hold(Object *obj) | ||
170 | +static void smmu_base_reset_hold(Object *obj, ResetType type) | ||
171 | { | ||
172 | SMMUState *s = ARM_SMMU(obj); | ||
173 | |||
174 | diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c | ||
175 | index XXXXXXX..XXXXXXX 100644 | ||
176 | --- a/hw/arm/smmuv3.c | ||
177 | +++ b/hw/arm/smmuv3.c | ||
178 | @@ -XXX,XX +XXX,XX @@ static void smmu_init_irq(SMMUv3State *s, SysBusDevice *dev) | ||
179 | } | ||
180 | } | ||
181 | |||
182 | -static void smmu_reset_hold(Object *obj) | ||
183 | +static void smmu_reset_hold(Object *obj, ResetType type) | ||
184 | { | ||
185 | SMMUv3State *s = ARM_SMMUV3(obj); | ||
186 | SMMUv3Class *c = ARM_SMMUV3_GET_CLASS(s); | ||
187 | |||
188 | if (c->parent_phases.hold) { | ||
189 | - c->parent_phases.hold(obj); | ||
190 | + c->parent_phases.hold(obj, type); | ||
191 | } | ||
192 | |||
193 | smmuv3_init_regs(s); | ||
194 | diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c | ||
195 | index XXXXXXX..XXXXXXX 100644 | ||
196 | --- a/hw/arm/stellaris.c | ||
197 | +++ b/hw/arm/stellaris.c | ||
198 | @@ -XXX,XX +XXX,XX @@ static void stellaris_sys_reset_enter(Object *obj, ResetType type) | ||
199 | s->dcgc[0] = 1; | ||
200 | } | ||
201 | |||
202 | -static void stellaris_sys_reset_hold(Object *obj) | ||
203 | +static void stellaris_sys_reset_hold(Object *obj, ResetType type) | ||
204 | { | ||
205 | ssys_state *s = STELLARIS_SYS(obj); | ||
206 | |||
207 | @@ -XXX,XX +XXX,XX @@ static void stellaris_sys_reset_hold(Object *obj) | ||
208 | ssys_calculate_system_clock(s, true); | ||
209 | } | ||
210 | |||
211 | -static void stellaris_sys_reset_exit(Object *obj) | ||
212 | +static void stellaris_sys_reset_exit(Object *obj, ResetType type) | ||
213 | { | ||
214 | } | ||
215 | |||
216 | @@ -XXX,XX +XXX,XX @@ static void stellaris_i2c_reset_enter(Object *obj, ResetType type) | ||
217 | i2c_end_transfer(s->bus); | ||
218 | } | ||
219 | |||
220 | -static void stellaris_i2c_reset_hold(Object *obj) | ||
221 | +static void stellaris_i2c_reset_hold(Object *obj, ResetType type) | ||
222 | { | ||
223 | stellaris_i2c_state *s = STELLARIS_I2C(obj); | ||
224 | |||
225 | @@ -XXX,XX +XXX,XX @@ static void stellaris_i2c_reset_hold(Object *obj) | ||
226 | s->mcr = 0; | ||
227 | } | ||
228 | |||
229 | -static void stellaris_i2c_reset_exit(Object *obj) | ||
230 | +static void stellaris_i2c_reset_exit(Object *obj, ResetType type) | ||
231 | { | ||
232 | stellaris_i2c_state *s = STELLARIS_I2C(obj); | ||
233 | |||
234 | @@ -XXX,XX +XXX,XX @@ static void stellaris_adc_trigger(void *opaque, int irq, int level) | ||
235 | } | ||
236 | } | ||
237 | |||
238 | -static void stellaris_adc_reset_hold(Object *obj) | ||
239 | +static void stellaris_adc_reset_hold(Object *obj, ResetType type) | ||
240 | { | ||
241 | StellarisADCState *s = STELLARIS_ADC(obj); | ||
242 | int n; | ||
243 | diff --git a/hw/audio/asc.c b/hw/audio/asc.c | ||
244 | index XXXXXXX..XXXXXXX 100644 | ||
245 | --- a/hw/audio/asc.c | ||
246 | +++ b/hw/audio/asc.c | ||
247 | @@ -XXX,XX +XXX,XX @@ static void asc_fifo_init(ASCFIFOState *fs, int index) | ||
248 | g_free(name); | ||
249 | } | ||
250 | |||
251 | -static void asc_reset_hold(Object *obj) | ||
252 | +static void asc_reset_hold(Object *obj, ResetType type) | ||
253 | { | ||
254 | ASCState *s = ASC(obj); | ||
255 | |||
256 | diff --git a/hw/char/cadence_uart.c b/hw/char/cadence_uart.c | ||
257 | index XXXXXXX..XXXXXXX 100644 | ||
258 | --- a/hw/char/cadence_uart.c | ||
259 | +++ b/hw/char/cadence_uart.c | ||
260 | @@ -XXX,XX +XXX,XX @@ static void cadence_uart_reset_init(Object *obj, ResetType type) | ||
261 | s->r[R_TTRIG] = 0x00000020; | ||
262 | } | ||
263 | |||
264 | -static void cadence_uart_reset_hold(Object *obj) | ||
265 | +static void cadence_uart_reset_hold(Object *obj, ResetType type) | ||
266 | { | ||
267 | CadenceUARTState *s = CADENCE_UART(obj); | ||
268 | |||
269 | diff --git a/hw/char/sifive_uart.c b/hw/char/sifive_uart.c | ||
270 | index XXXXXXX..XXXXXXX 100644 | ||
271 | --- a/hw/char/sifive_uart.c | ||
272 | +++ b/hw/char/sifive_uart.c | ||
273 | @@ -XXX,XX +XXX,XX @@ static void sifive_uart_reset_enter(Object *obj, ResetType type) | ||
274 | s->rx_fifo_len = 0; | ||
275 | } | ||
276 | |||
277 | -static void sifive_uart_reset_hold(Object *obj) | ||
278 | +static void sifive_uart_reset_hold(Object *obj, ResetType type) | ||
279 | { | ||
280 | SiFiveUARTState *s = SIFIVE_UART(obj); | ||
281 | qemu_irq_lower(s->irq); | ||
282 | diff --git a/hw/core/cpu-common.c b/hw/core/cpu-common.c | ||
283 | index XXXXXXX..XXXXXXX 100644 | ||
284 | --- a/hw/core/cpu-common.c | ||
285 | +++ b/hw/core/cpu-common.c | ||
286 | @@ -XXX,XX +XXX,XX @@ void cpu_reset(CPUState *cpu) | ||
287 | trace_cpu_reset(cpu->cpu_index); | ||
288 | } | ||
289 | |||
290 | -static void cpu_common_reset_hold(Object *obj) | ||
291 | +static void cpu_common_reset_hold(Object *obj, ResetType type) | ||
292 | { | ||
293 | CPUState *cpu = CPU(obj); | ||
294 | CPUClass *cc = CPU_GET_CLASS(cpu); | ||
295 | diff --git a/hw/core/qdev.c b/hw/core/qdev.c | ||
296 | index XXXXXXX..XXXXXXX 100644 | ||
297 | --- a/hw/core/qdev.c | ||
298 | +++ b/hw/core/qdev.c | ||
299 | @@ -XXX,XX +XXX,XX @@ static void device_phases_reset(DeviceState *dev) | ||
300 | rc->phases.enter(OBJECT(dev), RESET_TYPE_COLD); | ||
301 | } | ||
302 | if (rc->phases.hold) { | ||
303 | - rc->phases.hold(OBJECT(dev)); | ||
304 | + rc->phases.hold(OBJECT(dev), RESET_TYPE_COLD); | ||
305 | } | ||
306 | if (rc->phases.exit) { | ||
307 | - rc->phases.exit(OBJECT(dev)); | ||
308 | + rc->phases.exit(OBJECT(dev), RESET_TYPE_COLD); | ||
309 | } | ||
310 | } | ||
311 | |||
312 | diff --git a/hw/core/reset.c b/hw/core/reset.c | ||
313 | index XXXXXXX..XXXXXXX 100644 | ||
314 | --- a/hw/core/reset.c | ||
315 | +++ b/hw/core/reset.c | ||
316 | @@ -XXX,XX +XXX,XX @@ static ResettableState *legacy_reset_get_state(Object *obj) | ||
317 | return &lr->reset_state; | ||
318 | } | ||
319 | |||
320 | -static void legacy_reset_hold(Object *obj) | ||
321 | +static void legacy_reset_hold(Object *obj, ResetType type) | ||
322 | { | ||
323 | LegacyReset *lr = LEGACY_RESET(obj); | ||
324 | |||
325 | diff --git a/hw/core/resettable.c b/hw/core/resettable.c | ||
326 | index XXXXXXX..XXXXXXX 100644 | ||
327 | --- a/hw/core/resettable.c | ||
328 | +++ b/hw/core/resettable.c | ||
329 | @@ -XXX,XX +XXX,XX @@ static void resettable_phase_hold(Object *obj, void *opaque, ResetType type) | ||
330 | trace_resettable_transitional_function(obj, obj_typename); | ||
331 | tr_func(obj); | ||
332 | } else if (rc->phases.hold) { | ||
333 | - rc->phases.hold(obj); | ||
334 | + rc->phases.hold(obj, type); | ||
335 | } | ||
336 | } | ||
337 | trace_resettable_phase_hold_end(obj, obj_typename, s->count); | ||
338 | @@ -XXX,XX +XXX,XX @@ static void resettable_phase_exit(Object *obj, void *opaque, ResetType type) | ||
339 | if (--s->count == 0) { | ||
340 | trace_resettable_phase_exit_exec(obj, obj_typename, !!rc->phases.exit); | ||
341 | if (rc->phases.exit && !resettable_get_tr_func(rc, obj)) { | ||
342 | - rc->phases.exit(obj); | ||
343 | + rc->phases.exit(obj, type); | ||
344 | } | ||
345 | } | ||
346 | s->exit_phase_in_progress = false; | ||
347 | diff --git a/hw/display/virtio-vga.c b/hw/display/virtio-vga.c | ||
348 | index XXXXXXX..XXXXXXX 100644 | ||
349 | --- a/hw/display/virtio-vga.c | ||
350 | +++ b/hw/display/virtio-vga.c | ||
351 | @@ -XXX,XX +XXX,XX @@ static void virtio_vga_base_realize(VirtIOPCIProxy *vpci_dev, Error **errp) | ||
352 | } | ||
353 | } | ||
354 | |||
355 | -static void virtio_vga_base_reset_hold(Object *obj) | ||
356 | +static void virtio_vga_base_reset_hold(Object *obj, ResetType type) | ||
357 | { | ||
358 | VirtIOVGABaseClass *klass = VIRTIO_VGA_BASE_GET_CLASS(obj); | ||
359 | VirtIOVGABase *vvga = VIRTIO_VGA_BASE(obj); | ||
360 | |||
361 | /* reset virtio-gpu */ | ||
362 | if (klass->parent_phases.hold) { | ||
363 | - klass->parent_phases.hold(obj); | ||
364 | + klass->parent_phases.hold(obj, type); | ||
365 | } | ||
366 | |||
367 | /* reset vga */ | ||
368 | diff --git a/hw/gpio/npcm7xx_gpio.c b/hw/gpio/npcm7xx_gpio.c | ||
369 | index XXXXXXX..XXXXXXX 100644 | ||
370 | --- a/hw/gpio/npcm7xx_gpio.c | ||
371 | +++ b/hw/gpio/npcm7xx_gpio.c | ||
372 | @@ -XXX,XX +XXX,XX @@ static void npcm7xx_gpio_enter_reset(Object *obj, ResetType type) | ||
373 | s->regs[NPCM7XX_GPIO_ODSC] = s->reset_odsc; | ||
374 | } | ||
375 | |||
376 | -static void npcm7xx_gpio_hold_reset(Object *obj) | ||
377 | +static void npcm7xx_gpio_hold_reset(Object *obj, ResetType type) | ||
378 | { | ||
379 | NPCM7xxGPIOState *s = NPCM7XX_GPIO(obj); | ||
380 | |||
381 | diff --git a/hw/gpio/pl061.c b/hw/gpio/pl061.c | ||
382 | index XXXXXXX..XXXXXXX 100644 | ||
383 | --- a/hw/gpio/pl061.c | ||
384 | +++ b/hw/gpio/pl061.c | ||
385 | @@ -XXX,XX +XXX,XX @@ static void pl061_enter_reset(Object *obj, ResetType type) | ||
386 | s->amsel = 0; | ||
387 | } | ||
388 | |||
389 | -static void pl061_hold_reset(Object *obj) | ||
390 | +static void pl061_hold_reset(Object *obj, ResetType type) | ||
391 | { | ||
392 | PL061State *s = PL061(obj); | ||
393 | int i, level; | ||
394 | diff --git a/hw/gpio/stm32l4x5_gpio.c b/hw/gpio/stm32l4x5_gpio.c | ||
395 | index XXXXXXX..XXXXXXX 100644 | ||
396 | --- a/hw/gpio/stm32l4x5_gpio.c | ||
397 | +++ b/hw/gpio/stm32l4x5_gpio.c | ||
398 | @@ -XXX,XX +XXX,XX @@ static bool is_push_pull(Stm32l4x5GpioState *s, unsigned pin) | ||
399 | return extract32(s->otyper, pin, 1) == 0; | ||
400 | } | ||
401 | |||
402 | -static void stm32l4x5_gpio_reset_hold(Object *obj) | ||
403 | +static void stm32l4x5_gpio_reset_hold(Object *obj, ResetType type) | ||
404 | { | ||
405 | Stm32l4x5GpioState *s = STM32L4X5_GPIO(obj); | ||
406 | |||
407 | diff --git a/hw/hyperv/vmbus.c b/hw/hyperv/vmbus.c | ||
408 | index XXXXXXX..XXXXXXX 100644 | ||
409 | --- a/hw/hyperv/vmbus.c | ||
410 | +++ b/hw/hyperv/vmbus.c | ||
411 | @@ -XXX,XX +XXX,XX @@ static void vmbus_unrealize(BusState *bus) | ||
412 | qemu_mutex_destroy(&vmbus->rx_queue_lock); | ||
413 | } | ||
414 | |||
415 | -static void vmbus_reset_hold(Object *obj) | ||
416 | +static void vmbus_reset_hold(Object *obj, ResetType type) | ||
417 | { | ||
418 | vmbus_deinit(VMBUS(obj)); | ||
419 | } | ||
420 | diff --git a/hw/i2c/allwinner-i2c.c b/hw/i2c/allwinner-i2c.c | ||
421 | index XXXXXXX..XXXXXXX 100644 | ||
422 | --- a/hw/i2c/allwinner-i2c.c | ||
423 | +++ b/hw/i2c/allwinner-i2c.c | ||
424 | @@ -XXX,XX +XXX,XX @@ static inline bool allwinner_i2c_interrupt_is_enabled(AWI2CState *s) | ||
425 | return s->cntr & TWI_CNTR_INT_EN; | ||
426 | } | ||
427 | |||
428 | -static void allwinner_i2c_reset_hold(Object *obj) | ||
429 | +static void allwinner_i2c_reset_hold(Object *obj, ResetType type) | ||
430 | { | ||
431 | AWI2CState *s = AW_I2C(obj); | ||
432 | |||
433 | diff --git a/hw/i2c/npcm7xx_smbus.c b/hw/i2c/npcm7xx_smbus.c | ||
434 | index XXXXXXX..XXXXXXX 100644 | ||
435 | --- a/hw/i2c/npcm7xx_smbus.c | ||
436 | +++ b/hw/i2c/npcm7xx_smbus.c | ||
437 | @@ -XXX,XX +XXX,XX @@ static void npcm7xx_smbus_enter_reset(Object *obj, ResetType type) | ||
438 | s->rx_cur = 0; | ||
439 | } | ||
440 | |||
441 | -static void npcm7xx_smbus_hold_reset(Object *obj) | ||
442 | +static void npcm7xx_smbus_hold_reset(Object *obj, ResetType type) | ||
443 | { | ||
444 | NPCM7xxSMBusState *s = NPCM7XX_SMBUS(obj); | ||
445 | |||
446 | diff --git a/hw/input/adb.c b/hw/input/adb.c | ||
447 | index XXXXXXX..XXXXXXX 100644 | ||
448 | --- a/hw/input/adb.c | ||
449 | +++ b/hw/input/adb.c | ||
450 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_adb_bus = { | ||
451 | } | ||
452 | }; | ||
453 | |||
454 | -static void adb_bus_reset_hold(Object *obj) | ||
455 | +static void adb_bus_reset_hold(Object *obj, ResetType type) | ||
456 | { | ||
457 | ADBBusState *adb_bus = ADB_BUS(obj); | ||
458 | |||
459 | diff --git a/hw/input/ps2.c b/hw/input/ps2.c | ||
460 | index XXXXXXX..XXXXXXX 100644 | ||
461 | --- a/hw/input/ps2.c | ||
462 | +++ b/hw/input/ps2.c | ||
463 | @@ -XXX,XX +XXX,XX @@ void ps2_write_mouse(PS2MouseState *s, int val) | ||
464 | } | ||
465 | } | ||
466 | |||
467 | -static void ps2_reset_hold(Object *obj) | ||
468 | +static void ps2_reset_hold(Object *obj, ResetType type) | ||
469 | { | ||
470 | PS2State *s = PS2_DEVICE(obj); | ||
471 | |||
472 | @@ -XXX,XX +XXX,XX @@ static void ps2_reset_hold(Object *obj) | ||
473 | ps2_reset_queue(s); | ||
474 | } | ||
475 | |||
476 | -static void ps2_reset_exit(Object *obj) | ||
477 | +static void ps2_reset_exit(Object *obj, ResetType type) | ||
478 | { | ||
479 | PS2State *s = PS2_DEVICE(obj); | ||
480 | |||
481 | @@ -XXX,XX +XXX,XX @@ static void ps2_common_post_load(PS2State *s) | ||
482 | q->cwptr = ccount ? (q->rptr + ccount) & (PS2_BUFFER_SIZE - 1) : -1; | ||
483 | } | ||
484 | |||
485 | -static void ps2_kbd_reset_hold(Object *obj) | ||
486 | +static void ps2_kbd_reset_hold(Object *obj, ResetType type) | ||
487 | { | ||
488 | PS2DeviceClass *ps2dc = PS2_DEVICE_GET_CLASS(obj); | ||
489 | PS2KbdState *s = PS2_KBD_DEVICE(obj); | ||
490 | @@ -XXX,XX +XXX,XX @@ static void ps2_kbd_reset_hold(Object *obj) | ||
491 | trace_ps2_kbd_reset(s); | ||
492 | |||
493 | if (ps2dc->parent_phases.hold) { | ||
494 | - ps2dc->parent_phases.hold(obj); | ||
495 | + ps2dc->parent_phases.hold(obj, type); | ||
496 | } | ||
497 | |||
498 | s->scan_enabled = 1; | ||
499 | @@ -XXX,XX +XXX,XX @@ static void ps2_kbd_reset_hold(Object *obj) | ||
500 | s->modifiers = 0; | ||
501 | } | ||
502 | |||
503 | -static void ps2_mouse_reset_hold(Object *obj) | ||
504 | +static void ps2_mouse_reset_hold(Object *obj, ResetType type) | ||
505 | { | ||
506 | PS2DeviceClass *ps2dc = PS2_DEVICE_GET_CLASS(obj); | ||
507 | PS2MouseState *s = PS2_MOUSE_DEVICE(obj); | ||
508 | @@ -XXX,XX +XXX,XX @@ static void ps2_mouse_reset_hold(Object *obj) | ||
509 | trace_ps2_mouse_reset(s); | ||
510 | |||
511 | if (ps2dc->parent_phases.hold) { | ||
512 | - ps2dc->parent_phases.hold(obj); | ||
513 | + ps2dc->parent_phases.hold(obj, type); | ||
514 | } | ||
515 | |||
516 | s->mouse_status = 0; | ||
517 | diff --git a/hw/intc/arm_gic_common.c b/hw/intc/arm_gic_common.c | ||
518 | index XXXXXXX..XXXXXXX 100644 | ||
519 | --- a/hw/intc/arm_gic_common.c | ||
520 | +++ b/hw/intc/arm_gic_common.c | ||
521 | @@ -XXX,XX +XXX,XX @@ static inline void arm_gic_common_reset_irq_state(GICState *s, int cidx, | ||
522 | } | ||
523 | } | ||
524 | |||
525 | -static void arm_gic_common_reset_hold(Object *obj) | ||
526 | +static void arm_gic_common_reset_hold(Object *obj, ResetType type) | ||
527 | { | ||
528 | GICState *s = ARM_GIC_COMMON(obj); | ||
529 | int i, j; | ||
530 | diff --git a/hw/intc/arm_gic_kvm.c b/hw/intc/arm_gic_kvm.c | ||
531 | index XXXXXXX..XXXXXXX 100644 | ||
532 | --- a/hw/intc/arm_gic_kvm.c | ||
533 | +++ b/hw/intc/arm_gic_kvm.c | ||
534 | @@ -XXX,XX +XXX,XX @@ static void kvm_arm_gic_get(GICState *s) | ||
535 | } | ||
536 | } | ||
537 | |||
538 | -static void kvm_arm_gic_reset_hold(Object *obj) | ||
539 | +static void kvm_arm_gic_reset_hold(Object *obj, ResetType type) | ||
540 | { | ||
541 | GICState *s = ARM_GIC_COMMON(obj); | ||
542 | KVMARMGICClass *kgc = KVM_ARM_GIC_GET_CLASS(s); | ||
543 | |||
544 | if (kgc->parent_phases.hold) { | ||
545 | - kgc->parent_phases.hold(obj); | ||
546 | + kgc->parent_phases.hold(obj, type); | ||
547 | } | ||
548 | |||
549 | if (kvm_arm_gic_can_save_restore(s)) { | ||
550 | diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c | ||
551 | index XXXXXXX..XXXXXXX 100644 | ||
552 | --- a/hw/intc/arm_gicv3_common.c | ||
553 | +++ b/hw/intc/arm_gicv3_common.c | ||
554 | @@ -XXX,XX +XXX,XX @@ static void arm_gicv3_finalize(Object *obj) | ||
555 | g_free(s->redist_region_count); | ||
556 | } | ||
557 | |||
558 | -static void arm_gicv3_common_reset_hold(Object *obj) | ||
559 | +static void arm_gicv3_common_reset_hold(Object *obj, ResetType type) | ||
560 | { | ||
561 | GICv3State *s = ARM_GICV3_COMMON(obj); | ||
562 | int i; | ||
563 | diff --git a/hw/intc/arm_gicv3_its.c b/hw/intc/arm_gicv3_its.c | ||
564 | index XXXXXXX..XXXXXXX 100644 | ||
565 | --- a/hw/intc/arm_gicv3_its.c | ||
566 | +++ b/hw/intc/arm_gicv3_its.c | ||
567 | @@ -XXX,XX +XXX,XX @@ static void gicv3_arm_its_realize(DeviceState *dev, Error **errp) | ||
568 | } | ||
569 | } | ||
570 | |||
571 | -static void gicv3_its_reset_hold(Object *obj) | ||
572 | +static void gicv3_its_reset_hold(Object *obj, ResetType type) | ||
573 | { | ||
574 | GICv3ITSState *s = ARM_GICV3_ITS_COMMON(obj); | ||
575 | GICv3ITSClass *c = ARM_GICV3_ITS_GET_CLASS(s); | ||
576 | |||
577 | if (c->parent_phases.hold) { | ||
578 | - c->parent_phases.hold(obj); | ||
579 | + c->parent_phases.hold(obj, type); | ||
580 | } | ||
581 | |||
582 | /* Quiescent bit reset to 1 */ | ||
583 | diff --git a/hw/intc/arm_gicv3_its_common.c b/hw/intc/arm_gicv3_its_common.c | ||
584 | index XXXXXXX..XXXXXXX 100644 | ||
585 | --- a/hw/intc/arm_gicv3_its_common.c | ||
586 | +++ b/hw/intc/arm_gicv3_its_common.c | ||
587 | @@ -XXX,XX +XXX,XX @@ void gicv3_its_init_mmio(GICv3ITSState *s, const MemoryRegionOps *ops, | ||
588 | msi_nonbroken = true; | ||
589 | } | ||
590 | |||
591 | -static void gicv3_its_common_reset_hold(Object *obj) | ||
592 | +static void gicv3_its_common_reset_hold(Object *obj, ResetType type) | ||
593 | { | ||
594 | GICv3ITSState *s = ARM_GICV3_ITS_COMMON(obj); | ||
595 | |||
596 | diff --git a/hw/intc/arm_gicv3_its_kvm.c b/hw/intc/arm_gicv3_its_kvm.c | ||
597 | index XXXXXXX..XXXXXXX 100644 | ||
598 | --- a/hw/intc/arm_gicv3_its_kvm.c | ||
599 | +++ b/hw/intc/arm_gicv3_its_kvm.c | ||
600 | @@ -XXX,XX +XXX,XX @@ static void kvm_arm_its_post_load(GICv3ITSState *s) | ||
601 | GITS_CTLR, &s->ctlr, true, &error_abort); | ||
602 | } | ||
603 | |||
604 | -static void kvm_arm_its_reset_hold(Object *obj) | ||
605 | +static void kvm_arm_its_reset_hold(Object *obj, ResetType type) | ||
606 | { | ||
607 | GICv3ITSState *s = ARM_GICV3_ITS_COMMON(obj); | ||
608 | KVMARMITSClass *c = KVM_ARM_ITS_GET_CLASS(s); | ||
609 | int i; | ||
610 | |||
611 | if (c->parent_phases.hold) { | ||
612 | - c->parent_phases.hold(obj); | ||
613 | + c->parent_phases.hold(obj, type); | ||
614 | } | ||
615 | |||
616 | if (kvm_device_check_attr(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CTRL, | ||
617 | diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c | ||
618 | index XXXXXXX..XXXXXXX 100644 | ||
619 | --- a/hw/intc/arm_gicv3_kvm.c | ||
620 | +++ b/hw/intc/arm_gicv3_kvm.c | ||
621 | @@ -XXX,XX +XXX,XX @@ static void arm_gicv3_icc_reset(CPUARMState *env, const ARMCPRegInfo *ri) | ||
622 | c->icc_ctlr_el1[GICV3_S] = c->icc_ctlr_el1[GICV3_NS]; | ||
623 | } | ||
624 | |||
625 | -static void kvm_arm_gicv3_reset_hold(Object *obj) | ||
626 | +static void kvm_arm_gicv3_reset_hold(Object *obj, ResetType type) | ||
627 | { | ||
628 | GICv3State *s = ARM_GICV3_COMMON(obj); | ||
629 | KVMARMGICv3Class *kgc = KVM_ARM_GICV3_GET_CLASS(s); | ||
630 | @@ -XXX,XX +XXX,XX @@ static void kvm_arm_gicv3_reset_hold(Object *obj) | ||
631 | DPRINTF("Reset\n"); | ||
632 | |||
633 | if (kgc->parent_phases.hold) { | ||
634 | - kgc->parent_phases.hold(obj); | ||
635 | + kgc->parent_phases.hold(obj, type); | ||
636 | } | ||
637 | |||
638 | if (s->migration_blocker) { | ||
639 | diff --git a/hw/intc/xics.c b/hw/intc/xics.c | ||
640 | index XXXXXXX..XXXXXXX 100644 | ||
641 | --- a/hw/intc/xics.c | ||
642 | +++ b/hw/intc/xics.c | ||
643 | @@ -XXX,XX +XXX,XX @@ static void ics_reset_irq(ICSIRQState *irq) | ||
644 | irq->saved_priority = 0xff; | ||
645 | } | ||
646 | |||
647 | -static void ics_reset_hold(Object *obj) | ||
648 | +static void ics_reset_hold(Object *obj, ResetType type) | ||
649 | { | ||
650 | ICSState *ics = ICS(obj); | ||
651 | g_autofree uint8_t *flags = g_malloc(ics->nr_irqs); | ||
652 | diff --git a/hw/m68k/q800-glue.c b/hw/m68k/q800-glue.c | ||
653 | index XXXXXXX..XXXXXXX 100644 | ||
654 | --- a/hw/m68k/q800-glue.c | ||
655 | +++ b/hw/m68k/q800-glue.c | ||
656 | @@ -XXX,XX +XXX,XX @@ static void glue_nmi_release(void *opaque) | ||
657 | GLUE_set_irq(s, GLUE_IRQ_IN_NMI, 0); | ||
658 | } | ||
659 | |||
660 | -static void glue_reset_hold(Object *obj) | ||
661 | +static void glue_reset_hold(Object *obj, ResetType type) | ||
662 | { | ||
663 | GLUEState *s = GLUE(obj); | ||
664 | |||
665 | diff --git a/hw/misc/djmemc.c b/hw/misc/djmemc.c | ||
666 | index XXXXXXX..XXXXXXX 100644 | ||
667 | --- a/hw/misc/djmemc.c | ||
668 | +++ b/hw/misc/djmemc.c | ||
669 | @@ -XXX,XX +XXX,XX @@ static void djmemc_init(Object *obj) | ||
670 | sysbus_init_mmio(sbd, &s->mem_regs); | ||
671 | } | ||
672 | |||
673 | -static void djmemc_reset_hold(Object *obj) | ||
674 | +static void djmemc_reset_hold(Object *obj, ResetType type) | ||
675 | { | ||
676 | DJMEMCState *s = DJMEMC(obj); | ||
677 | |||
678 | diff --git a/hw/misc/iosb.c b/hw/misc/iosb.c | ||
679 | index XXXXXXX..XXXXXXX 100644 | ||
680 | --- a/hw/misc/iosb.c | ||
681 | +++ b/hw/misc/iosb.c | ||
682 | @@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps iosb_mmio_ops = { | ||
683 | .endianness = DEVICE_BIG_ENDIAN, | ||
684 | }; | ||
685 | |||
686 | -static void iosb_reset_hold(Object *obj) | ||
687 | +static void iosb_reset_hold(Object *obj, ResetType type) | ||
688 | { | ||
689 | IOSBState *s = IOSB(obj); | ||
690 | |||
691 | diff --git a/hw/misc/mac_via.c b/hw/misc/mac_via.c | ||
692 | index XXXXXXX..XXXXXXX 100644 | ||
693 | --- a/hw/misc/mac_via.c | ||
694 | +++ b/hw/misc/mac_via.c | ||
695 | @@ -XXX,XX +XXX,XX @@ static int via1_post_load(void *opaque, int version_id) | ||
696 | } | ||
697 | |||
698 | /* VIA 1 */ | ||
699 | -static void mos6522_q800_via1_reset_hold(Object *obj) | ||
700 | +static void mos6522_q800_via1_reset_hold(Object *obj, ResetType type) | ||
701 | { | ||
702 | MOS6522Q800VIA1State *v1s = MOS6522_Q800_VIA1(obj); | ||
703 | MOS6522State *ms = MOS6522(v1s); | ||
704 | @@ -XXX,XX +XXX,XX @@ static void mos6522_q800_via1_reset_hold(Object *obj) | ||
705 | ADBBusState *adb_bus = &v1s->adb_bus; | ||
706 | |||
707 | if (mdc->parent_phases.hold) { | ||
708 | - mdc->parent_phases.hold(obj); | ||
709 | + mdc->parent_phases.hold(obj, type); | ||
710 | } | ||
711 | |||
712 | ms->timers[0].frequency = VIA_TIMER_FREQ; | ||
713 | @@ -XXX,XX +XXX,XX @@ static void mos6522_q800_via2_portB_write(MOS6522State *s) | ||
714 | } | ||
715 | } | ||
716 | |||
717 | -static void mos6522_q800_via2_reset_hold(Object *obj) | ||
718 | +static void mos6522_q800_via2_reset_hold(Object *obj, ResetType type) | ||
719 | { | ||
720 | MOS6522State *ms = MOS6522(obj); | ||
721 | MOS6522DeviceClass *mdc = MOS6522_GET_CLASS(ms); | ||
722 | |||
723 | if (mdc->parent_phases.hold) { | ||
724 | - mdc->parent_phases.hold(obj); | ||
725 | + mdc->parent_phases.hold(obj, type); | ||
726 | } | ||
727 | |||
728 | ms->timers[0].frequency = VIA_TIMER_FREQ; | ||
729 | diff --git a/hw/misc/macio/cuda.c b/hw/misc/macio/cuda.c | ||
730 | index XXXXXXX..XXXXXXX 100644 | ||
731 | --- a/hw/misc/macio/cuda.c | ||
732 | +++ b/hw/misc/macio/cuda.c | ||
733 | @@ -XXX,XX +XXX,XX @@ static void mos6522_cuda_portB_write(MOS6522State *s) | ||
734 | cuda_update(cs); | ||
735 | } | ||
736 | |||
737 | -static void mos6522_cuda_reset_hold(Object *obj) | ||
738 | +static void mos6522_cuda_reset_hold(Object *obj, ResetType type) | ||
739 | { | ||
740 | MOS6522State *ms = MOS6522(obj); | ||
741 | MOS6522DeviceClass *mdc = MOS6522_GET_CLASS(ms); | ||
742 | |||
743 | if (mdc->parent_phases.hold) { | ||
744 | - mdc->parent_phases.hold(obj); | ||
745 | + mdc->parent_phases.hold(obj, type); | ||
746 | } | ||
747 | |||
748 | ms->timers[0].frequency = CUDA_TIMER_FREQ; | ||
749 | diff --git a/hw/misc/macio/pmu.c b/hw/misc/macio/pmu.c | ||
750 | index XXXXXXX..XXXXXXX 100644 | ||
751 | --- a/hw/misc/macio/pmu.c | ||
752 | +++ b/hw/misc/macio/pmu.c | ||
753 | @@ -XXX,XX +XXX,XX @@ static void mos6522_pmu_portB_write(MOS6522State *s) | ||
754 | pmu_update(ps); | ||
755 | } | ||
756 | |||
757 | -static void mos6522_pmu_reset_hold(Object *obj) | ||
758 | +static void mos6522_pmu_reset_hold(Object *obj, ResetType type) | ||
759 | { | ||
760 | MOS6522State *ms = MOS6522(obj); | ||
761 | MOS6522PMUState *mps = container_of(ms, MOS6522PMUState, parent_obj); | ||
762 | @@ -XXX,XX +XXX,XX @@ static void mos6522_pmu_reset_hold(Object *obj) | ||
763 | MOS6522DeviceClass *mdc = MOS6522_GET_CLASS(ms); | ||
764 | |||
765 | if (mdc->parent_phases.hold) { | ||
766 | - mdc->parent_phases.hold(obj); | ||
767 | + mdc->parent_phases.hold(obj, type); | ||
768 | } | ||
769 | |||
770 | ms->timers[0].frequency = VIA_TIMER_FREQ; | ||
771 | diff --git a/hw/misc/mos6522.c b/hw/misc/mos6522.c | ||
772 | index XXXXXXX..XXXXXXX 100644 | ||
773 | --- a/hw/misc/mos6522.c | ||
774 | +++ b/hw/misc/mos6522.c | ||
775 | @@ -XXX,XX +XXX,XX @@ const VMStateDescription vmstate_mos6522 = { | ||
776 | } | ||
777 | }; | ||
778 | |||
779 | -static void mos6522_reset_hold(Object *obj) | ||
780 | +static void mos6522_reset_hold(Object *obj, ResetType type) | ||
781 | { | ||
782 | MOS6522State *s = MOS6522(obj); | ||
783 | |||
784 | diff --git a/hw/misc/npcm7xx_mft.c b/hw/misc/npcm7xx_mft.c | ||
785 | index XXXXXXX..XXXXXXX 100644 | ||
786 | --- a/hw/misc/npcm7xx_mft.c | ||
787 | +++ b/hw/misc/npcm7xx_mft.c | ||
788 | @@ -XXX,XX +XXX,XX @@ static void npcm7xx_mft_enter_reset(Object *obj, ResetType type) | ||
789 | npcm7xx_mft_reset(s); | ||
790 | } | ||
791 | |||
792 | -static void npcm7xx_mft_hold_reset(Object *obj) | ||
793 | +static void npcm7xx_mft_hold_reset(Object *obj, ResetType type) | ||
794 | { | ||
795 | NPCM7xxMFTState *s = NPCM7XX_MFT(obj); | ||
796 | |||
797 | diff --git a/hw/misc/npcm7xx_pwm.c b/hw/misc/npcm7xx_pwm.c | ||
798 | index XXXXXXX..XXXXXXX 100644 | ||
799 | --- a/hw/misc/npcm7xx_pwm.c | ||
800 | +++ b/hw/misc/npcm7xx_pwm.c | ||
801 | @@ -XXX,XX +XXX,XX @@ static void npcm7xx_pwm_enter_reset(Object *obj, ResetType type) | ||
802 | s->piir = 0x00000000; | ||
803 | } | ||
804 | |||
805 | -static void npcm7xx_pwm_hold_reset(Object *obj) | ||
806 | +static void npcm7xx_pwm_hold_reset(Object *obj, ResetType type) | ||
807 | { | ||
808 | NPCM7xxPWMState *s = NPCM7XX_PWM(obj); | ||
809 | int i; | ||
810 | diff --git a/hw/misc/stm32l4x5_exti.c b/hw/misc/stm32l4x5_exti.c | ||
811 | index XXXXXXX..XXXXXXX 100644 | ||
812 | --- a/hw/misc/stm32l4x5_exti.c | ||
813 | +++ b/hw/misc/stm32l4x5_exti.c | ||
814 | @@ -XXX,XX +XXX,XX @@ static unsigned configurable_mask(unsigned bank) | ||
815 | return valid_mask(bank) & ~exti_romask[bank]; | ||
816 | } | ||
817 | |||
818 | -static void stm32l4x5_exti_reset_hold(Object *obj) | ||
819 | +static void stm32l4x5_exti_reset_hold(Object *obj, ResetType type) | ||
820 | { | ||
821 | Stm32l4x5ExtiState *s = STM32L4X5_EXTI(obj); | ||
822 | |||
823 | diff --git a/hw/misc/stm32l4x5_rcc.c b/hw/misc/stm32l4x5_rcc.c | ||
824 | index XXXXXXX..XXXXXXX 100644 | ||
825 | --- a/hw/misc/stm32l4x5_rcc.c | ||
826 | +++ b/hw/misc/stm32l4x5_rcc.c | ||
827 | @@ -XXX,XX +XXX,XX @@ static void clock_mux_reset_enter(Object *obj, ResetType type) | ||
828 | set_clock_mux_init_info(s, s->id); | ||
829 | } | ||
830 | |||
831 | -static void clock_mux_reset_hold(Object *obj) | ||
832 | +static void clock_mux_reset_hold(Object *obj, ResetType type) | ||
833 | { | ||
834 | RccClockMuxState *s = RCC_CLOCK_MUX(obj); | ||
835 | clock_mux_update(s, true); | ||
836 | } | ||
837 | |||
838 | -static void clock_mux_reset_exit(Object *obj) | ||
839 | +static void clock_mux_reset_exit(Object *obj, ResetType type) | ||
840 | { | ||
841 | RccClockMuxState *s = RCC_CLOCK_MUX(obj); | ||
842 | clock_mux_update(s, false); | ||
843 | @@ -XXX,XX +XXX,XX @@ static void pll_reset_enter(Object *obj, ResetType type) | ||
844 | set_pll_init_info(s, s->id); | ||
845 | } | ||
846 | |||
847 | -static void pll_reset_hold(Object *obj) | ||
848 | +static void pll_reset_hold(Object *obj, ResetType type) | ||
849 | { | ||
850 | RccPllState *s = RCC_PLL(obj); | ||
851 | pll_update(s, true); | ||
852 | } | ||
853 | |||
854 | -static void pll_reset_exit(Object *obj) | ||
855 | +static void pll_reset_exit(Object *obj, ResetType type) | ||
856 | { | ||
857 | RccPllState *s = RCC_PLL(obj); | ||
858 | pll_update(s, false); | ||
859 | @@ -XXX,XX +XXX,XX @@ static void rcc_update_csr(Stm32l4x5RccState *s) | ||
860 | rcc_update_irq(s); | ||
861 | } | ||
862 | |||
863 | -static void stm32l4x5_rcc_reset_hold(Object *obj) | ||
864 | +static void stm32l4x5_rcc_reset_hold(Object *obj, ResetType type) | ||
865 | { | ||
866 | Stm32l4x5RccState *s = STM32L4X5_RCC(obj); | ||
867 | s->cr = 0x00000063; | ||
868 | diff --git a/hw/misc/stm32l4x5_syscfg.c b/hw/misc/stm32l4x5_syscfg.c | ||
869 | index XXXXXXX..XXXXXXX 100644 | ||
870 | --- a/hw/misc/stm32l4x5_syscfg.c | ||
871 | +++ b/hw/misc/stm32l4x5_syscfg.c | ||
23 | @@ -XXX,XX +XXX,XX @@ | 872 | @@ -XXX,XX +XXX,XX @@ |
24 | #include "hw/clock.h" | 873 | |
25 | #include "hw/sysbus.h" | 874 | #define NUM_LINES_PER_EXTICR_REG 4 |
26 | 875 | ||
27 | -/* | 876 | -static void stm32l4x5_syscfg_hold_reset(Object *obj) |
28 | - * The reference clock frequency for the timer modules, and the SECCNT and | 877 | +static void stm32l4x5_syscfg_hold_reset(Object *obj, ResetType type) |
29 | - * CNTR25M registers in this module, is always 25 MHz. | 878 | { |
30 | - */ | 879 | Stm32l4x5SyscfgState *s = STM32L4X5_SYSCFG(obj); |
31 | -#define NPCM7XX_TIMER_REF_HZ (25000000) | 880 | |
32 | - | 881 | diff --git a/hw/misc/xlnx-versal-cframe-reg.c b/hw/misc/xlnx-versal-cframe-reg.c |
33 | /* | 882 | index XXXXXXX..XXXXXXX 100644 |
34 | * Number of registers in our device state structure. Don't change this without | 883 | --- a/hw/misc/xlnx-versal-cframe-reg.c |
35 | * incrementing the version_id in the vmstate. | 884 | +++ b/hw/misc/xlnx-versal-cframe-reg.c |
36 | diff --git a/include/hw/timer/npcm7xx_timer.h b/include/hw/timer/npcm7xx_timer.h | 885 | @@ -XXX,XX +XXX,XX @@ static void cframe_reg_reset_enter(Object *obj, ResetType type) |
37 | index XXXXXXX..XXXXXXX 100644 | 886 | } |
38 | --- a/include/hw/timer/npcm7xx_timer.h | 887 | } |
39 | +++ b/include/hw/timer/npcm7xx_timer.h | 888 | |
40 | @@ -XXX,XX +XXX,XX @@ struct NPCM7xxTimerCtrlState { | 889 | -static void cframe_reg_reset_hold(Object *obj) |
41 | 890 | +static void cframe_reg_reset_hold(Object *obj, ResetType type) | |
42 | uint32_t tisr; | 891 | { |
43 | 892 | XlnxVersalCFrameReg *s = XLNX_VERSAL_CFRAME_REG(obj); | |
44 | + Clock *clock; | 893 | |
45 | NPCM7xxTimer timer[NPCM7XX_TIMERS_PER_CTRL]; | 894 | diff --git a/hw/misc/xlnx-versal-crl.c b/hw/misc/xlnx-versal-crl.c |
46 | NPCM7xxWatchdogTimer watchdog_timer; | 895 | index XXXXXXX..XXXXXXX 100644 |
896 | --- a/hw/misc/xlnx-versal-crl.c | ||
897 | +++ b/hw/misc/xlnx-versal-crl.c | ||
898 | @@ -XXX,XX +XXX,XX @@ static void crl_reset_enter(Object *obj, ResetType type) | ||
899 | } | ||
900 | } | ||
901 | |||
902 | -static void crl_reset_hold(Object *obj) | ||
903 | +static void crl_reset_hold(Object *obj, ResetType type) | ||
904 | { | ||
905 | XlnxVersalCRL *s = XLNX_VERSAL_CRL(obj); | ||
906 | |||
907 | diff --git a/hw/misc/xlnx-versal-pmc-iou-slcr.c b/hw/misc/xlnx-versal-pmc-iou-slcr.c | ||
908 | index XXXXXXX..XXXXXXX 100644 | ||
909 | --- a/hw/misc/xlnx-versal-pmc-iou-slcr.c | ||
910 | +++ b/hw/misc/xlnx-versal-pmc-iou-slcr.c | ||
911 | @@ -XXX,XX +XXX,XX @@ static void xlnx_versal_pmc_iou_slcr_reset_init(Object *obj, ResetType type) | ||
912 | } | ||
913 | } | ||
914 | |||
915 | -static void xlnx_versal_pmc_iou_slcr_reset_hold(Object *obj) | ||
916 | +static void xlnx_versal_pmc_iou_slcr_reset_hold(Object *obj, ResetType type) | ||
917 | { | ||
918 | XlnxVersalPmcIouSlcr *s = XILINX_VERSAL_PMC_IOU_SLCR(obj); | ||
919 | |||
920 | diff --git a/hw/misc/xlnx-versal-trng.c b/hw/misc/xlnx-versal-trng.c | ||
921 | index XXXXXXX..XXXXXXX 100644 | ||
922 | --- a/hw/misc/xlnx-versal-trng.c | ||
923 | +++ b/hw/misc/xlnx-versal-trng.c | ||
924 | @@ -XXX,XX +XXX,XX @@ static void trng_unrealize(DeviceState *dev) | ||
925 | s->prng = NULL; | ||
926 | } | ||
927 | |||
928 | -static void trng_reset_hold(Object *obj) | ||
929 | +static void trng_reset_hold(Object *obj, ResetType type) | ||
930 | { | ||
931 | trng_reset(XLNX_VERSAL_TRNG(obj)); | ||
932 | } | ||
933 | diff --git a/hw/misc/xlnx-versal-xramc.c b/hw/misc/xlnx-versal-xramc.c | ||
934 | index XXXXXXX..XXXXXXX 100644 | ||
935 | --- a/hw/misc/xlnx-versal-xramc.c | ||
936 | +++ b/hw/misc/xlnx-versal-xramc.c | ||
937 | @@ -XXX,XX +XXX,XX @@ static void xram_ctrl_reset_enter(Object *obj, ResetType type) | ||
938 | ARRAY_FIELD_DP32(s->regs, XRAM_IMP, SIZE, s->cfg.encoded_size); | ||
939 | } | ||
940 | |||
941 | -static void xram_ctrl_reset_hold(Object *obj) | ||
942 | +static void xram_ctrl_reset_hold(Object *obj, ResetType type) | ||
943 | { | ||
944 | XlnxXramCtrl *s = XLNX_XRAM_CTRL(obj); | ||
945 | |||
946 | diff --git a/hw/misc/xlnx-zynqmp-apu-ctrl.c b/hw/misc/xlnx-zynqmp-apu-ctrl.c | ||
947 | index XXXXXXX..XXXXXXX 100644 | ||
948 | --- a/hw/misc/xlnx-zynqmp-apu-ctrl.c | ||
949 | +++ b/hw/misc/xlnx-zynqmp-apu-ctrl.c | ||
950 | @@ -XXX,XX +XXX,XX @@ static void zynqmp_apu_reset_enter(Object *obj, ResetType type) | ||
951 | s->cpu_in_wfi = 0; | ||
952 | } | ||
953 | |||
954 | -static void zynqmp_apu_reset_hold(Object *obj) | ||
955 | +static void zynqmp_apu_reset_hold(Object *obj, ResetType type) | ||
956 | { | ||
957 | XlnxZynqMPAPUCtrl *s = XLNX_ZYNQMP_APU_CTRL(obj); | ||
958 | |||
959 | diff --git a/hw/misc/xlnx-zynqmp-crf.c b/hw/misc/xlnx-zynqmp-crf.c | ||
960 | index XXXXXXX..XXXXXXX 100644 | ||
961 | --- a/hw/misc/xlnx-zynqmp-crf.c | ||
962 | +++ b/hw/misc/xlnx-zynqmp-crf.c | ||
963 | @@ -XXX,XX +XXX,XX @@ static void crf_reset_enter(Object *obj, ResetType type) | ||
964 | } | ||
965 | } | ||
966 | |||
967 | -static void crf_reset_hold(Object *obj) | ||
968 | +static void crf_reset_hold(Object *obj, ResetType type) | ||
969 | { | ||
970 | XlnxZynqMPCRF *s = XLNX_ZYNQMP_CRF(obj); | ||
971 | ir_update_irq(s); | ||
972 | diff --git a/hw/misc/zynq_slcr.c b/hw/misc/zynq_slcr.c | ||
973 | index XXXXXXX..XXXXXXX 100644 | ||
974 | --- a/hw/misc/zynq_slcr.c | ||
975 | +++ b/hw/misc/zynq_slcr.c | ||
976 | @@ -XXX,XX +XXX,XX @@ static void zynq_slcr_reset_init(Object *obj, ResetType type) | ||
977 | s->regs[R_DDRIOB + 12] = 0x00000021; | ||
978 | } | ||
979 | |||
980 | -static void zynq_slcr_reset_hold(Object *obj) | ||
981 | +static void zynq_slcr_reset_hold(Object *obj, ResetType type) | ||
982 | { | ||
983 | ZynqSLCRState *s = ZYNQ_SLCR(obj); | ||
984 | |||
985 | @@ -XXX,XX +XXX,XX @@ static void zynq_slcr_reset_hold(Object *obj) | ||
986 | zynq_slcr_propagate_clocks(s); | ||
987 | } | ||
988 | |||
989 | -static void zynq_slcr_reset_exit(Object *obj) | ||
990 | +static void zynq_slcr_reset_exit(Object *obj, ResetType type) | ||
991 | { | ||
992 | ZynqSLCRState *s = ZYNQ_SLCR(obj); | ||
993 | |||
994 | diff --git a/hw/net/can/xlnx-zynqmp-can.c b/hw/net/can/xlnx-zynqmp-can.c | ||
995 | index XXXXXXX..XXXXXXX 100644 | ||
996 | --- a/hw/net/can/xlnx-zynqmp-can.c | ||
997 | +++ b/hw/net/can/xlnx-zynqmp-can.c | ||
998 | @@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_can_reset_init(Object *obj, ResetType type) | ||
999 | ptimer_transaction_commit(s->can_timer); | ||
1000 | } | ||
1001 | |||
1002 | -static void xlnx_zynqmp_can_reset_hold(Object *obj) | ||
1003 | +static void xlnx_zynqmp_can_reset_hold(Object *obj, ResetType type) | ||
1004 | { | ||
1005 | XlnxZynqMPCANState *s = XLNX_ZYNQMP_CAN(obj); | ||
1006 | unsigned int i; | ||
1007 | diff --git a/hw/net/e1000.c b/hw/net/e1000.c | ||
1008 | index XXXXXXX..XXXXXXX 100644 | ||
1009 | --- a/hw/net/e1000.c | ||
1010 | +++ b/hw/net/e1000.c | ||
1011 | @@ -XXX,XX +XXX,XX @@ static bool e1000_vet_init_need(void *opaque) | ||
1012 | return chkflag(VET); | ||
1013 | } | ||
1014 | |||
1015 | -static void e1000_reset_hold(Object *obj) | ||
1016 | +static void e1000_reset_hold(Object *obj, ResetType type) | ||
1017 | { | ||
1018 | E1000State *d = E1000(obj); | ||
1019 | E1000BaseClass *edc = E1000_GET_CLASS(d); | ||
1020 | diff --git a/hw/net/e1000e.c b/hw/net/e1000e.c | ||
1021 | index XXXXXXX..XXXXXXX 100644 | ||
1022 | --- a/hw/net/e1000e.c | ||
1023 | +++ b/hw/net/e1000e.c | ||
1024 | @@ -XXX,XX +XXX,XX @@ static void e1000e_pci_uninit(PCIDevice *pci_dev) | ||
1025 | msi_uninit(pci_dev); | ||
1026 | } | ||
1027 | |||
1028 | -static void e1000e_qdev_reset_hold(Object *obj) | ||
1029 | +static void e1000e_qdev_reset_hold(Object *obj, ResetType type) | ||
1030 | { | ||
1031 | E1000EState *s = E1000E(obj); | ||
1032 | |||
1033 | diff --git a/hw/net/igb.c b/hw/net/igb.c | ||
1034 | index XXXXXXX..XXXXXXX 100644 | ||
1035 | --- a/hw/net/igb.c | ||
1036 | +++ b/hw/net/igb.c | ||
1037 | @@ -XXX,XX +XXX,XX @@ static void igb_pci_uninit(PCIDevice *pci_dev) | ||
1038 | msi_uninit(pci_dev); | ||
1039 | } | ||
1040 | |||
1041 | -static void igb_qdev_reset_hold(Object *obj) | ||
1042 | +static void igb_qdev_reset_hold(Object *obj, ResetType type) | ||
1043 | { | ||
1044 | IGBState *s = IGB(obj); | ||
1045 | |||
1046 | diff --git a/hw/net/igbvf.c b/hw/net/igbvf.c | ||
1047 | index XXXXXXX..XXXXXXX 100644 | ||
1048 | --- a/hw/net/igbvf.c | ||
1049 | +++ b/hw/net/igbvf.c | ||
1050 | @@ -XXX,XX +XXX,XX @@ static void igbvf_pci_realize(PCIDevice *dev, Error **errp) | ||
1051 | pcie_ari_init(dev, 0x150); | ||
1052 | } | ||
1053 | |||
1054 | -static void igbvf_qdev_reset_hold(Object *obj) | ||
1055 | +static void igbvf_qdev_reset_hold(Object *obj, ResetType type) | ||
1056 | { | ||
1057 | PCIDevice *vf = PCI_DEVICE(obj); | ||
1058 | |||
1059 | diff --git a/hw/nvram/xlnx-bbram.c b/hw/nvram/xlnx-bbram.c | ||
1060 | index XXXXXXX..XXXXXXX 100644 | ||
1061 | --- a/hw/nvram/xlnx-bbram.c | ||
1062 | +++ b/hw/nvram/xlnx-bbram.c | ||
1063 | @@ -XXX,XX +XXX,XX @@ static RegisterAccessInfo bbram_ctrl_regs_info[] = { | ||
1064 | } | ||
47 | }; | 1065 | }; |
48 | diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c | 1066 | |
49 | index XXXXXXX..XXXXXXX 100644 | 1067 | -static void bbram_ctrl_reset_hold(Object *obj) |
50 | --- a/hw/arm/npcm7xx.c | 1068 | +static void bbram_ctrl_reset_hold(Object *obj, ResetType type) |
51 | +++ b/hw/arm/npcm7xx.c | 1069 | { |
52 | @@ -XXX,XX +XXX,XX @@ | 1070 | XlnxBBRam *s = XLNX_BBRAM(obj); |
53 | #include "hw/char/serial.h" | 1071 | unsigned int i; |
54 | #include "hw/loader.h" | 1072 | diff --git a/hw/nvram/xlnx-versal-efuse-ctrl.c b/hw/nvram/xlnx-versal-efuse-ctrl.c |
55 | #include "hw/misc/unimp.h" | 1073 | index XXXXXXX..XXXXXXX 100644 |
56 | +#include "hw/qdev-clock.h" | 1074 | --- a/hw/nvram/xlnx-versal-efuse-ctrl.c |
57 | #include "hw/qdev-properties.h" | 1075 | +++ b/hw/nvram/xlnx-versal-efuse-ctrl.c |
58 | #include "qapi/error.h" | 1076 | @@ -XXX,XX +XXX,XX @@ static void efuse_ctrl_register_reset(RegisterInfo *reg) |
59 | #include "qemu/units.h" | 1077 | register_reset(reg); |
60 | @@ -XXX,XX +XXX,XX @@ static void npcm7xx_realize(DeviceState *dev, Error **errp) | 1078 | } |
61 | int first_irq; | 1079 | |
62 | int j; | 1080 | -static void efuse_ctrl_reset_hold(Object *obj) |
63 | 1081 | +static void efuse_ctrl_reset_hold(Object *obj, ResetType type) | |
64 | + /* Connect the timer clock. */ | 1082 | { |
65 | + qdev_connect_clock_in(DEVICE(&s->tim[i]), "clock", qdev_get_clock_out( | 1083 | XlnxVersalEFuseCtrl *s = XLNX_VERSAL_EFUSE_CTRL(obj); |
66 | + DEVICE(&s->clk), "timer-clock")); | 1084 | unsigned int i; |
67 | + | 1085 | diff --git a/hw/nvram/xlnx-zynqmp-efuse.c b/hw/nvram/xlnx-zynqmp-efuse.c |
68 | sysbus_realize(sbd, &error_abort); | 1086 | index XXXXXXX..XXXXXXX 100644 |
69 | sysbus_mmio_map(sbd, 0, npcm7xx_tim_addr[i]); | 1087 | --- a/hw/nvram/xlnx-zynqmp-efuse.c |
1088 | +++ b/hw/nvram/xlnx-zynqmp-efuse.c | ||
1089 | @@ -XXX,XX +XXX,XX @@ static void zynqmp_efuse_register_reset(RegisterInfo *reg) | ||
1090 | register_reset(reg); | ||
1091 | } | ||
1092 | |||
1093 | -static void zynqmp_efuse_reset_hold(Object *obj) | ||
1094 | +static void zynqmp_efuse_reset_hold(Object *obj, ResetType type) | ||
1095 | { | ||
1096 | XlnxZynqMPEFuse *s = XLNX_ZYNQMP_EFUSE(obj); | ||
1097 | unsigned int i; | ||
1098 | diff --git a/hw/pci-bridge/cxl_root_port.c b/hw/pci-bridge/cxl_root_port.c | ||
1099 | index XXXXXXX..XXXXXXX 100644 | ||
1100 | --- a/hw/pci-bridge/cxl_root_port.c | ||
1101 | +++ b/hw/pci-bridge/cxl_root_port.c | ||
1102 | @@ -XXX,XX +XXX,XX @@ static void cxl_rp_realize(DeviceState *dev, Error **errp) | ||
1103 | component_bar); | ||
1104 | } | ||
1105 | |||
1106 | -static void cxl_rp_reset_hold(Object *obj) | ||
1107 | +static void cxl_rp_reset_hold(Object *obj, ResetType type) | ||
1108 | { | ||
1109 | PCIERootPortClass *rpc = PCIE_ROOT_PORT_GET_CLASS(obj); | ||
1110 | CXLRootPort *crp = CXL_ROOT_PORT(obj); | ||
1111 | |||
1112 | if (rpc->parent_phases.hold) { | ||
1113 | - rpc->parent_phases.hold(obj); | ||
1114 | + rpc->parent_phases.hold(obj, type); | ||
1115 | } | ||
1116 | |||
1117 | latch_registers(crp); | ||
1118 | diff --git a/hw/pci-bridge/pcie_root_port.c b/hw/pci-bridge/pcie_root_port.c | ||
1119 | index XXXXXXX..XXXXXXX 100644 | ||
1120 | --- a/hw/pci-bridge/pcie_root_port.c | ||
1121 | +++ b/hw/pci-bridge/pcie_root_port.c | ||
1122 | @@ -XXX,XX +XXX,XX @@ static void rp_write_config(PCIDevice *d, uint32_t address, | ||
1123 | pcie_aer_root_write_config(d, address, val, len, root_cmd); | ||
1124 | } | ||
1125 | |||
1126 | -static void rp_reset_hold(Object *obj) | ||
1127 | +static void rp_reset_hold(Object *obj, ResetType type) | ||
1128 | { | ||
1129 | PCIDevice *d = PCI_DEVICE(obj); | ||
1130 | DeviceState *qdev = DEVICE(obj); | ||
1131 | diff --git a/hw/pci-host/bonito.c b/hw/pci-host/bonito.c | ||
1132 | index XXXXXXX..XXXXXXX 100644 | ||
1133 | --- a/hw/pci-host/bonito.c | ||
1134 | +++ b/hw/pci-host/bonito.c | ||
1135 | @@ -XXX,XX +XXX,XX @@ static int pci_bonito_map_irq(PCIDevice *pci_dev, int irq_num) | ||
1136 | } | ||
1137 | } | ||
1138 | |||
1139 | -static void bonito_reset_hold(Object *obj) | ||
1140 | +static void bonito_reset_hold(Object *obj, ResetType type) | ||
1141 | { | ||
1142 | PCIBonitoState *s = PCI_BONITO(obj); | ||
1143 | uint32_t val = 0; | ||
1144 | diff --git a/hw/pci-host/pnv_phb.c b/hw/pci-host/pnv_phb.c | ||
1145 | index XXXXXXX..XXXXXXX 100644 | ||
1146 | --- a/hw/pci-host/pnv_phb.c | ||
1147 | +++ b/hw/pci-host/pnv_phb.c | ||
1148 | @@ -XXX,XX +XXX,XX @@ static void pnv_phb_class_init(ObjectClass *klass, void *data) | ||
1149 | dc->user_creatable = true; | ||
1150 | } | ||
1151 | |||
1152 | -static void pnv_phb_root_port_reset_hold(Object *obj) | ||
1153 | +static void pnv_phb_root_port_reset_hold(Object *obj, ResetType type) | ||
1154 | { | ||
1155 | PCIERootPortClass *rpc = PCIE_ROOT_PORT_GET_CLASS(obj); | ||
1156 | PnvPHBRootPort *phb_rp = PNV_PHB_ROOT_PORT(obj); | ||
1157 | @@ -XXX,XX +XXX,XX @@ static void pnv_phb_root_port_reset_hold(Object *obj) | ||
1158 | uint8_t *conf = d->config; | ||
1159 | |||
1160 | if (rpc->parent_phases.hold) { | ||
1161 | - rpc->parent_phases.hold(obj); | ||
1162 | + rpc->parent_phases.hold(obj, type); | ||
1163 | } | ||
1164 | |||
1165 | if (phb_rp->version == 3) { | ||
1166 | diff --git a/hw/pci-host/pnv_phb3_msi.c b/hw/pci-host/pnv_phb3_msi.c | ||
1167 | index XXXXXXX..XXXXXXX 100644 | ||
1168 | --- a/hw/pci-host/pnv_phb3_msi.c | ||
1169 | +++ b/hw/pci-host/pnv_phb3_msi.c | ||
1170 | @@ -XXX,XX +XXX,XX @@ static void phb3_msi_resend(ICSState *ics) | ||
1171 | } | ||
1172 | } | ||
1173 | |||
1174 | -static void phb3_msi_reset_hold(Object *obj) | ||
1175 | +static void phb3_msi_reset_hold(Object *obj, ResetType type) | ||
1176 | { | ||
1177 | Phb3MsiState *msi = PHB3_MSI(obj); | ||
1178 | ICSStateClass *icsc = ICS_GET_CLASS(obj); | ||
1179 | |||
1180 | if (icsc->parent_phases.hold) { | ||
1181 | - icsc->parent_phases.hold(obj); | ||
1182 | + icsc->parent_phases.hold(obj, type); | ||
1183 | } | ||
1184 | |||
1185 | memset(msi->rba, 0, sizeof(msi->rba)); | ||
1186 | diff --git a/hw/pci/pci.c b/hw/pci/pci.c | ||
1187 | index XXXXXXX..XXXXXXX 100644 | ||
1188 | --- a/hw/pci/pci.c | ||
1189 | +++ b/hw/pci/pci.c | ||
1190 | @@ -XXX,XX +XXX,XX @@ bool pci_available = true; | ||
1191 | |||
1192 | static char *pcibus_get_dev_path(DeviceState *dev); | ||
1193 | static char *pcibus_get_fw_dev_path(DeviceState *dev); | ||
1194 | -static void pcibus_reset_hold(Object *obj); | ||
1195 | +static void pcibus_reset_hold(Object *obj, ResetType type); | ||
1196 | static bool pcie_has_upstream_port(PCIDevice *dev); | ||
1197 | |||
1198 | static Property pci_props[] = { | ||
1199 | @@ -XXX,XX +XXX,XX @@ void pci_device_reset(PCIDevice *dev) | ||
1200 | * Called via bus_cold_reset on RST# assert, after the devices | ||
1201 | * have been reset device_cold_reset-ed already. | ||
1202 | */ | ||
1203 | -static void pcibus_reset_hold(Object *obj) | ||
1204 | +static void pcibus_reset_hold(Object *obj, ResetType type) | ||
1205 | { | ||
1206 | PCIBus *bus = PCI_BUS(obj); | ||
1207 | int i; | ||
1208 | diff --git a/hw/rtc/mc146818rtc.c b/hw/rtc/mc146818rtc.c | ||
1209 | index XXXXXXX..XXXXXXX 100644 | ||
1210 | --- a/hw/rtc/mc146818rtc.c | ||
1211 | +++ b/hw/rtc/mc146818rtc.c | ||
1212 | @@ -XXX,XX +XXX,XX @@ static void rtc_reset_enter(Object *obj, ResetType type) | ||
1213 | } | ||
1214 | } | ||
1215 | |||
1216 | -static void rtc_reset_hold(Object *obj) | ||
1217 | +static void rtc_reset_hold(Object *obj, ResetType type) | ||
1218 | { | ||
1219 | MC146818RtcState *s = MC146818_RTC(obj); | ||
1220 | |||
1221 | diff --git a/hw/s390x/css-bridge.c b/hw/s390x/css-bridge.c | ||
1222 | index XXXXXXX..XXXXXXX 100644 | ||
1223 | --- a/hw/s390x/css-bridge.c | ||
1224 | +++ b/hw/s390x/css-bridge.c | ||
1225 | @@ -XXX,XX +XXX,XX @@ static void ccw_device_unplug(HotplugHandler *hotplug_dev, | ||
1226 | qdev_unrealize(dev); | ||
1227 | } | ||
1228 | |||
1229 | -static void virtual_css_bus_reset_hold(Object *obj) | ||
1230 | +static void virtual_css_bus_reset_hold(Object *obj, ResetType type) | ||
1231 | { | ||
1232 | /* This should actually be modelled via the generic css */ | ||
1233 | css_reset(); | ||
1234 | diff --git a/hw/sensor/adm1266.c b/hw/sensor/adm1266.c | ||
1235 | index XXXXXXX..XXXXXXX 100644 | ||
1236 | --- a/hw/sensor/adm1266.c | ||
1237 | +++ b/hw/sensor/adm1266.c | ||
1238 | @@ -XXX,XX +XXX,XX @@ static const uint8_t adm1266_ic_device_id[] = {0x03, 0x41, 0x12, 0x66}; | ||
1239 | static const uint8_t adm1266_ic_device_rev[] = {0x08, 0x01, 0x08, 0x07, 0x0, | ||
1240 | 0x0, 0x07, 0x41, 0x30}; | ||
1241 | |||
1242 | -static void adm1266_exit_reset(Object *obj) | ||
1243 | +static void adm1266_exit_reset(Object *obj, ResetType type) | ||
1244 | { | ||
1245 | ADM1266State *s = ADM1266(obj); | ||
1246 | PMBusDevice *pmdev = PMBUS_DEVICE(obj); | ||
1247 | diff --git a/hw/sensor/adm1272.c b/hw/sensor/adm1272.c | ||
1248 | index XXXXXXX..XXXXXXX 100644 | ||
1249 | --- a/hw/sensor/adm1272.c | ||
1250 | +++ b/hw/sensor/adm1272.c | ||
1251 | @@ -XXX,XX +XXX,XX @@ static uint32_t adm1272_direct_to_watts(uint16_t value) | ||
1252 | return pmbus_direct_mode2data(c, value); | ||
1253 | } | ||
1254 | |||
1255 | -static void adm1272_exit_reset(Object *obj) | ||
1256 | +static void adm1272_exit_reset(Object *obj, ResetType type) | ||
1257 | { | ||
1258 | ADM1272State *s = ADM1272(obj); | ||
1259 | PMBusDevice *pmdev = PMBUS_DEVICE(obj); | ||
1260 | diff --git a/hw/sensor/isl_pmbus_vr.c b/hw/sensor/isl_pmbus_vr.c | ||
1261 | index XXXXXXX..XXXXXXX 100644 | ||
1262 | --- a/hw/sensor/isl_pmbus_vr.c | ||
1263 | +++ b/hw/sensor/isl_pmbus_vr.c | ||
1264 | @@ -XXX,XX +XXX,XX @@ static void isl_pmbus_vr_set(Object *obj, Visitor *v, const char *name, | ||
1265 | pmbus_check_limits(pmdev); | ||
1266 | } | ||
1267 | |||
1268 | -static void isl_pmbus_vr_exit_reset(Object *obj) | ||
1269 | +static void isl_pmbus_vr_exit_reset(Object *obj, ResetType type) | ||
1270 | { | ||
1271 | PMBusDevice *pmdev = PMBUS_DEVICE(obj); | ||
1272 | |||
1273 | @@ -XXX,XX +XXX,XX @@ static void isl_pmbus_vr_exit_reset(Object *obj) | ||
1274 | } | ||
1275 | |||
1276 | /* The raa228000 uses different direct mode coefficients from most isl devices */ | ||
1277 | -static void raa228000_exit_reset(Object *obj) | ||
1278 | +static void raa228000_exit_reset(Object *obj, ResetType type) | ||
1279 | { | ||
1280 | PMBusDevice *pmdev = PMBUS_DEVICE(obj); | ||
1281 | |||
1282 | - isl_pmbus_vr_exit_reset(obj); | ||
1283 | + isl_pmbus_vr_exit_reset(obj, type); | ||
1284 | |||
1285 | pmdev->pages[0].read_iout = 0; | ||
1286 | pmdev->pages[0].read_pout = 0; | ||
1287 | @@ -XXX,XX +XXX,XX @@ static void raa228000_exit_reset(Object *obj) | ||
1288 | pmdev->pages[0].read_temperature_3 = 0; | ||
1289 | } | ||
1290 | |||
1291 | -static void isl69259_exit_reset(Object *obj) | ||
1292 | +static void isl69259_exit_reset(Object *obj, ResetType type) | ||
1293 | { | ||
1294 | ISLState *s = ISL69260(obj); | ||
1295 | static const uint8_t ic_device_id[] = {0x04, 0x00, 0x81, 0xD2, 0x49, 0x3c}; | ||
1296 | g_assert(sizeof(ic_device_id) <= sizeof(s->ic_device_id)); | ||
1297 | |||
1298 | - isl_pmbus_vr_exit_reset(obj); | ||
1299 | + isl_pmbus_vr_exit_reset(obj, type); | ||
1300 | |||
1301 | s->ic_device_id_len = sizeof(ic_device_id); | ||
1302 | memcpy(s->ic_device_id, ic_device_id, sizeof(ic_device_id)); | ||
1303 | diff --git a/hw/sensor/max31785.c b/hw/sensor/max31785.c | ||
1304 | index XXXXXXX..XXXXXXX 100644 | ||
1305 | --- a/hw/sensor/max31785.c | ||
1306 | +++ b/hw/sensor/max31785.c | ||
1307 | @@ -XXX,XX +XXX,XX @@ static int max31785_write_data(PMBusDevice *pmdev, const uint8_t *buf, | ||
1308 | return 0; | ||
1309 | } | ||
1310 | |||
1311 | -static void max31785_exit_reset(Object *obj) | ||
1312 | +static void max31785_exit_reset(Object *obj, ResetType type) | ||
1313 | { | ||
1314 | PMBusDevice *pmdev = PMBUS_DEVICE(obj); | ||
1315 | MAX31785State *s = MAX31785(obj); | ||
1316 | diff --git a/hw/sensor/max34451.c b/hw/sensor/max34451.c | ||
1317 | index XXXXXXX..XXXXXXX 100644 | ||
1318 | --- a/hw/sensor/max34451.c | ||
1319 | +++ b/hw/sensor/max34451.c | ||
1320 | @@ -XXX,XX +XXX,XX @@ static inline void *memset_word(void *s, uint16_t c, size_t n) | ||
1321 | return s; | ||
1322 | } | ||
1323 | |||
1324 | -static void max34451_exit_reset(Object *obj) | ||
1325 | +static void max34451_exit_reset(Object *obj, ResetType type) | ||
1326 | { | ||
1327 | PMBusDevice *pmdev = PMBUS_DEVICE(obj); | ||
1328 | MAX34451State *s = MAX34451(obj); | ||
1329 | diff --git a/hw/ssi/npcm7xx_fiu.c b/hw/ssi/npcm7xx_fiu.c | ||
1330 | index XXXXXXX..XXXXXXX 100644 | ||
1331 | --- a/hw/ssi/npcm7xx_fiu.c | ||
1332 | +++ b/hw/ssi/npcm7xx_fiu.c | ||
1333 | @@ -XXX,XX +XXX,XX @@ static void npcm7xx_fiu_enter_reset(Object *obj, ResetType type) | ||
1334 | s->regs[NPCM7XX_FIU_CFG] = 0x0000000b; | ||
1335 | } | ||
1336 | |||
1337 | -static void npcm7xx_fiu_hold_reset(Object *obj) | ||
1338 | +static void npcm7xx_fiu_hold_reset(Object *obj, ResetType type) | ||
1339 | { | ||
1340 | NPCM7xxFIUState *s = NPCM7XX_FIU(obj); | ||
1341 | int i; | ||
1342 | diff --git a/hw/timer/etraxfs_timer.c b/hw/timer/etraxfs_timer.c | ||
1343 | index XXXXXXX..XXXXXXX 100644 | ||
1344 | --- a/hw/timer/etraxfs_timer.c | ||
1345 | +++ b/hw/timer/etraxfs_timer.c | ||
1346 | @@ -XXX,XX +XXX,XX @@ static void etraxfs_timer_reset_enter(Object *obj, ResetType type) | ||
1347 | t->rw_intr_mask = 0; | ||
1348 | } | ||
1349 | |||
1350 | -static void etraxfs_timer_reset_hold(Object *obj) | ||
1351 | +static void etraxfs_timer_reset_hold(Object *obj, ResetType type) | ||
1352 | { | ||
1353 | ETRAXTimerState *t = ETRAX_TIMER(obj); | ||
70 | 1354 | ||
71 | diff --git a/hw/timer/npcm7xx_timer.c b/hw/timer/npcm7xx_timer.c | 1355 | diff --git a/hw/timer/npcm7xx_timer.c b/hw/timer/npcm7xx_timer.c |
72 | index XXXXXXX..XXXXXXX 100644 | 1356 | index XXXXXXX..XXXXXXX 100644 |
73 | --- a/hw/timer/npcm7xx_timer.c | 1357 | --- a/hw/timer/npcm7xx_timer.c |
74 | +++ b/hw/timer/npcm7xx_timer.c | 1358 | +++ b/hw/timer/npcm7xx_timer.c |
1359 | @@ -XXX,XX +XXX,XX @@ static void npcm7xx_watchdog_timer_expired(void *opaque) | ||
1360 | } | ||
1361 | } | ||
1362 | |||
1363 | -static void npcm7xx_timer_hold_reset(Object *obj) | ||
1364 | +static void npcm7xx_timer_hold_reset(Object *obj, ResetType type) | ||
1365 | { | ||
1366 | NPCM7xxTimerCtrlState *s = NPCM7XX_TIMER(obj); | ||
1367 | int i; | ||
1368 | diff --git a/hw/usb/hcd-dwc2.c b/hw/usb/hcd-dwc2.c | ||
1369 | index XXXXXXX..XXXXXXX 100644 | ||
1370 | --- a/hw/usb/hcd-dwc2.c | ||
1371 | +++ b/hw/usb/hcd-dwc2.c | ||
1372 | @@ -XXX,XX +XXX,XX @@ static void dwc2_reset_enter(Object *obj, ResetType type) | ||
1373 | } | ||
1374 | } | ||
1375 | |||
1376 | -static void dwc2_reset_hold(Object *obj) | ||
1377 | +static void dwc2_reset_hold(Object *obj, ResetType type) | ||
1378 | { | ||
1379 | DWC2Class *c = DWC2_USB_GET_CLASS(obj); | ||
1380 | DWC2State *s = DWC2_USB(obj); | ||
1381 | @@ -XXX,XX +XXX,XX @@ static void dwc2_reset_hold(Object *obj) | ||
1382 | trace_usb_dwc2_reset_hold(); | ||
1383 | |||
1384 | if (c->parent_phases.hold) { | ||
1385 | - c->parent_phases.hold(obj); | ||
1386 | + c->parent_phases.hold(obj, type); | ||
1387 | } | ||
1388 | |||
1389 | dwc2_update_irq(s); | ||
1390 | } | ||
1391 | |||
1392 | -static void dwc2_reset_exit(Object *obj) | ||
1393 | +static void dwc2_reset_exit(Object *obj, ResetType type) | ||
1394 | { | ||
1395 | DWC2Class *c = DWC2_USB_GET_CLASS(obj); | ||
1396 | DWC2State *s = DWC2_USB(obj); | ||
1397 | @@ -XXX,XX +XXX,XX @@ static void dwc2_reset_exit(Object *obj) | ||
1398 | trace_usb_dwc2_reset_exit(); | ||
1399 | |||
1400 | if (c->parent_phases.exit) { | ||
1401 | - c->parent_phases.exit(obj); | ||
1402 | + c->parent_phases.exit(obj, type); | ||
1403 | } | ||
1404 | |||
1405 | s->hprt0 = HPRT0_PWR; | ||
1406 | diff --git a/hw/usb/xlnx-versal-usb2-ctrl-regs.c b/hw/usb/xlnx-versal-usb2-ctrl-regs.c | ||
1407 | index XXXXXXX..XXXXXXX 100644 | ||
1408 | --- a/hw/usb/xlnx-versal-usb2-ctrl-regs.c | ||
1409 | +++ b/hw/usb/xlnx-versal-usb2-ctrl-regs.c | ||
1410 | @@ -XXX,XX +XXX,XX @@ static void usb2_ctrl_regs_reset_init(Object *obj, ResetType type) | ||
1411 | } | ||
1412 | } | ||
1413 | |||
1414 | -static void usb2_ctrl_regs_reset_hold(Object *obj) | ||
1415 | +static void usb2_ctrl_regs_reset_hold(Object *obj, ResetType type) | ||
1416 | { | ||
1417 | VersalUsb2CtrlRegs *s = XILINX_VERSAL_USB2_CTRL_REGS(obj); | ||
1418 | |||
1419 | diff --git a/hw/virtio/virtio-pci.c b/hw/virtio/virtio-pci.c | ||
1420 | index XXXXXXX..XXXXXXX 100644 | ||
1421 | --- a/hw/virtio/virtio-pci.c | ||
1422 | +++ b/hw/virtio/virtio-pci.c | ||
1423 | @@ -XXX,XX +XXX,XX @@ static void virtio_pci_reset(DeviceState *qdev) | ||
1424 | } | ||
1425 | } | ||
1426 | |||
1427 | -static void virtio_pci_bus_reset_hold(Object *obj) | ||
1428 | +static void virtio_pci_bus_reset_hold(Object *obj, ResetType type) | ||
1429 | { | ||
1430 | PCIDevice *dev = PCI_DEVICE(obj); | ||
1431 | DeviceState *qdev = DEVICE(obj); | ||
1432 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c | ||
1433 | index XXXXXXX..XXXXXXX 100644 | ||
1434 | --- a/target/arm/cpu.c | ||
1435 | +++ b/target/arm/cpu.c | ||
1436 | @@ -XXX,XX +XXX,XX @@ static void cp_reg_check_reset(gpointer key, gpointer value, gpointer opaque) | ||
1437 | assert(oldvalue == newvalue); | ||
1438 | } | ||
1439 | |||
1440 | -static void arm_cpu_reset_hold(Object *obj) | ||
1441 | +static void arm_cpu_reset_hold(Object *obj, ResetType type) | ||
1442 | { | ||
1443 | CPUState *cs = CPU(obj); | ||
1444 | ARMCPU *cpu = ARM_CPU(cs); | ||
1445 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset_hold(Object *obj) | ||
1446 | CPUARMState *env = &cpu->env; | ||
1447 | |||
1448 | if (acc->parent_phases.hold) { | ||
1449 | - acc->parent_phases.hold(obj); | ||
1450 | + acc->parent_phases.hold(obj, type); | ||
1451 | } | ||
1452 | |||
1453 | memset(env, 0, offsetof(CPUARMState, end_reset_fields)); | ||
1454 | diff --git a/target/avr/cpu.c b/target/avr/cpu.c | ||
1455 | index XXXXXXX..XXXXXXX 100644 | ||
1456 | --- a/target/avr/cpu.c | ||
1457 | +++ b/target/avr/cpu.c | ||
1458 | @@ -XXX,XX +XXX,XX @@ static void avr_restore_state_to_opc(CPUState *cs, | ||
1459 | cpu_env(cs)->pc_w = data[0]; | ||
1460 | } | ||
1461 | |||
1462 | -static void avr_cpu_reset_hold(Object *obj) | ||
1463 | +static void avr_cpu_reset_hold(Object *obj, ResetType type) | ||
1464 | { | ||
1465 | CPUState *cs = CPU(obj); | ||
1466 | AVRCPU *cpu = AVR_CPU(cs); | ||
1467 | @@ -XXX,XX +XXX,XX @@ static void avr_cpu_reset_hold(Object *obj) | ||
1468 | CPUAVRState *env = &cpu->env; | ||
1469 | |||
1470 | if (mcc->parent_phases.hold) { | ||
1471 | - mcc->parent_phases.hold(obj); | ||
1472 | + mcc->parent_phases.hold(obj, type); | ||
1473 | } | ||
1474 | |||
1475 | env->pc_w = 0; | ||
1476 | diff --git a/target/cris/cpu.c b/target/cris/cpu.c | ||
1477 | index XXXXXXX..XXXXXXX 100644 | ||
1478 | --- a/target/cris/cpu.c | ||
1479 | +++ b/target/cris/cpu.c | ||
1480 | @@ -XXX,XX +XXX,XX @@ static int cris_cpu_mmu_index(CPUState *cs, bool ifetch) | ||
1481 | return !!(cpu_env(cs)->pregs[PR_CCS] & U_FLAG); | ||
1482 | } | ||
1483 | |||
1484 | -static void cris_cpu_reset_hold(Object *obj) | ||
1485 | +static void cris_cpu_reset_hold(Object *obj, ResetType type) | ||
1486 | { | ||
1487 | CPUState *cs = CPU(obj); | ||
1488 | CRISCPUClass *ccc = CRIS_CPU_GET_CLASS(obj); | ||
1489 | @@ -XXX,XX +XXX,XX @@ static void cris_cpu_reset_hold(Object *obj) | ||
1490 | uint32_t vr; | ||
1491 | |||
1492 | if (ccc->parent_phases.hold) { | ||
1493 | - ccc->parent_phases.hold(obj); | ||
1494 | + ccc->parent_phases.hold(obj, type); | ||
1495 | } | ||
1496 | |||
1497 | vr = env->pregs[PR_VR]; | ||
1498 | diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c | ||
1499 | index XXXXXXX..XXXXXXX 100644 | ||
1500 | --- a/target/hexagon/cpu.c | ||
1501 | +++ b/target/hexagon/cpu.c | ||
1502 | @@ -XXX,XX +XXX,XX @@ static void hexagon_restore_state_to_opc(CPUState *cs, | ||
1503 | cpu_env(cs)->gpr[HEX_REG_PC] = data[0]; | ||
1504 | } | ||
1505 | |||
1506 | -static void hexagon_cpu_reset_hold(Object *obj) | ||
1507 | +static void hexagon_cpu_reset_hold(Object *obj, ResetType type) | ||
1508 | { | ||
1509 | CPUState *cs = CPU(obj); | ||
1510 | HexagonCPUClass *mcc = HEXAGON_CPU_GET_CLASS(obj); | ||
1511 | CPUHexagonState *env = cpu_env(cs); | ||
1512 | |||
1513 | if (mcc->parent_phases.hold) { | ||
1514 | - mcc->parent_phases.hold(obj); | ||
1515 | + mcc->parent_phases.hold(obj, type); | ||
1516 | } | ||
1517 | |||
1518 | set_default_nan_mode(1, &env->fp_status); | ||
1519 | diff --git a/target/i386/cpu.c b/target/i386/cpu.c | ||
1520 | index XXXXXXX..XXXXXXX 100644 | ||
1521 | --- a/target/i386/cpu.c | ||
1522 | +++ b/target/i386/cpu.c | ||
1523 | @@ -XXX,XX +XXX,XX @@ static void x86_cpu_set_sgxlepubkeyhash(CPUX86State *env) | ||
1524 | #endif | ||
1525 | } | ||
1526 | |||
1527 | -static void x86_cpu_reset_hold(Object *obj) | ||
1528 | +static void x86_cpu_reset_hold(Object *obj, ResetType type) | ||
1529 | { | ||
1530 | CPUState *cs = CPU(obj); | ||
1531 | X86CPU *cpu = X86_CPU(cs); | ||
1532 | @@ -XXX,XX +XXX,XX @@ static void x86_cpu_reset_hold(Object *obj) | ||
1533 | int i; | ||
1534 | |||
1535 | if (xcc->parent_phases.hold) { | ||
1536 | - xcc->parent_phases.hold(obj); | ||
1537 | + xcc->parent_phases.hold(obj, type); | ||
1538 | } | ||
1539 | |||
1540 | memset(env, 0, offsetof(CPUX86State, end_reset_fields)); | ||
1541 | diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c | ||
1542 | index XXXXXXX..XXXXXXX 100644 | ||
1543 | --- a/target/loongarch/cpu.c | ||
1544 | +++ b/target/loongarch/cpu.c | ||
1545 | @@ -XXX,XX +XXX,XX @@ static void loongarch_max_initfn(Object *obj) | ||
1546 | loongarch_la464_initfn(obj); | ||
1547 | } | ||
1548 | |||
1549 | -static void loongarch_cpu_reset_hold(Object *obj) | ||
1550 | +static void loongarch_cpu_reset_hold(Object *obj, ResetType type) | ||
1551 | { | ||
1552 | CPUState *cs = CPU(obj); | ||
1553 | LoongArchCPUClass *lacc = LOONGARCH_CPU_GET_CLASS(obj); | ||
1554 | CPULoongArchState *env = cpu_env(cs); | ||
1555 | |||
1556 | if (lacc->parent_phases.hold) { | ||
1557 | - lacc->parent_phases.hold(obj); | ||
1558 | + lacc->parent_phases.hold(obj, type); | ||
1559 | } | ||
1560 | |||
1561 | env->fcsr0_mask = FCSR0_M1 | FCSR0_M2 | FCSR0_M3; | ||
1562 | diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c | ||
1563 | index XXXXXXX..XXXXXXX 100644 | ||
1564 | --- a/target/m68k/cpu.c | ||
1565 | +++ b/target/m68k/cpu.c | ||
1566 | @@ -XXX,XX +XXX,XX @@ static void m68k_unset_feature(CPUM68KState *env, int feature) | ||
1567 | env->features &= ~BIT_ULL(feature); | ||
1568 | } | ||
1569 | |||
1570 | -static void m68k_cpu_reset_hold(Object *obj) | ||
1571 | +static void m68k_cpu_reset_hold(Object *obj, ResetType type) | ||
1572 | { | ||
1573 | CPUState *cs = CPU(obj); | ||
1574 | M68kCPUClass *mcc = M68K_CPU_GET_CLASS(obj); | ||
1575 | @@ -XXX,XX +XXX,XX @@ static void m68k_cpu_reset_hold(Object *obj) | ||
1576 | int i; | ||
1577 | |||
1578 | if (mcc->parent_phases.hold) { | ||
1579 | - mcc->parent_phases.hold(obj); | ||
1580 | + mcc->parent_phases.hold(obj, type); | ||
1581 | } | ||
1582 | |||
1583 | memset(env, 0, offsetof(CPUM68KState, end_reset_fields)); | ||
1584 | diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c | ||
1585 | index XXXXXXX..XXXXXXX 100644 | ||
1586 | --- a/target/microblaze/cpu.c | ||
1587 | +++ b/target/microblaze/cpu.c | ||
1588 | @@ -XXX,XX +XXX,XX @@ static void microblaze_cpu_set_irq(void *opaque, int irq, int level) | ||
1589 | } | ||
1590 | #endif | ||
1591 | |||
1592 | -static void mb_cpu_reset_hold(Object *obj) | ||
1593 | +static void mb_cpu_reset_hold(Object *obj, ResetType type) | ||
1594 | { | ||
1595 | CPUState *cs = CPU(obj); | ||
1596 | MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); | ||
1597 | @@ -XXX,XX +XXX,XX @@ static void mb_cpu_reset_hold(Object *obj) | ||
1598 | CPUMBState *env = &cpu->env; | ||
1599 | |||
1600 | if (mcc->parent_phases.hold) { | ||
1601 | - mcc->parent_phases.hold(obj); | ||
1602 | + mcc->parent_phases.hold(obj, type); | ||
1603 | } | ||
1604 | |||
1605 | memset(env, 0, offsetof(CPUMBState, end_reset_fields)); | ||
1606 | diff --git a/target/mips/cpu.c b/target/mips/cpu.c | ||
1607 | index XXXXXXX..XXXXXXX 100644 | ||
1608 | --- a/target/mips/cpu.c | ||
1609 | +++ b/target/mips/cpu.c | ||
1610 | @@ -XXX,XX +XXX,XX @@ static int mips_cpu_mmu_index(CPUState *cs, bool ifunc) | ||
1611 | |||
1612 | #include "cpu-defs.c.inc" | ||
1613 | |||
1614 | -static void mips_cpu_reset_hold(Object *obj) | ||
1615 | +static void mips_cpu_reset_hold(Object *obj, ResetType type) | ||
1616 | { | ||
1617 | CPUState *cs = CPU(obj); | ||
1618 | MIPSCPU *cpu = MIPS_CPU(cs); | ||
1619 | @@ -XXX,XX +XXX,XX @@ static void mips_cpu_reset_hold(Object *obj) | ||
1620 | CPUMIPSState *env = &cpu->env; | ||
1621 | |||
1622 | if (mcc->parent_phases.hold) { | ||
1623 | - mcc->parent_phases.hold(obj); | ||
1624 | + mcc->parent_phases.hold(obj, type); | ||
1625 | } | ||
1626 | |||
1627 | memset(env, 0, offsetof(CPUMIPSState, end_reset_fields)); | ||
1628 | diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c | ||
1629 | index XXXXXXX..XXXXXXX 100644 | ||
1630 | --- a/target/openrisc/cpu.c | ||
1631 | +++ b/target/openrisc/cpu.c | ||
1632 | @@ -XXX,XX +XXX,XX @@ static void openrisc_disas_set_info(CPUState *cpu, disassemble_info *info) | ||
1633 | info->print_insn = print_insn_or1k; | ||
1634 | } | ||
1635 | |||
1636 | -static void openrisc_cpu_reset_hold(Object *obj) | ||
1637 | +static void openrisc_cpu_reset_hold(Object *obj, ResetType type) | ||
1638 | { | ||
1639 | CPUState *cs = CPU(obj); | ||
1640 | OpenRISCCPU *cpu = OPENRISC_CPU(cs); | ||
1641 | OpenRISCCPUClass *occ = OPENRISC_CPU_GET_CLASS(obj); | ||
1642 | |||
1643 | if (occ->parent_phases.hold) { | ||
1644 | - occ->parent_phases.hold(obj); | ||
1645 | + occ->parent_phases.hold(obj, type); | ||
1646 | } | ||
1647 | |||
1648 | memset(&cpu->env, 0, offsetof(CPUOpenRISCState, end_reset_fields)); | ||
1649 | diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c | ||
1650 | index XXXXXXX..XXXXXXX 100644 | ||
1651 | --- a/target/ppc/cpu_init.c | ||
1652 | +++ b/target/ppc/cpu_init.c | ||
1653 | @@ -XXX,XX +XXX,XX @@ static int ppc_cpu_mmu_index(CPUState *cs, bool ifetch) | ||
1654 | return ppc_env_mmu_index(cpu_env(cs), ifetch); | ||
1655 | } | ||
1656 | |||
1657 | -static void ppc_cpu_reset_hold(Object *obj) | ||
1658 | +static void ppc_cpu_reset_hold(Object *obj, ResetType type) | ||
1659 | { | ||
1660 | CPUState *cs = CPU(obj); | ||
1661 | PowerPCCPU *cpu = POWERPC_CPU(cs); | ||
1662 | @@ -XXX,XX +XXX,XX @@ static void ppc_cpu_reset_hold(Object *obj) | ||
1663 | int i; | ||
1664 | |||
1665 | if (pcc->parent_phases.hold) { | ||
1666 | - pcc->parent_phases.hold(obj); | ||
1667 | + pcc->parent_phases.hold(obj, type); | ||
1668 | } | ||
1669 | |||
1670 | msr = (target_ulong)0; | ||
1671 | diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c | ||
1672 | index XXXXXXX..XXXXXXX 100644 | ||
1673 | --- a/target/riscv/cpu.c | ||
1674 | +++ b/target/riscv/cpu.c | ||
1675 | @@ -XXX,XX +XXX,XX @@ static int riscv_cpu_mmu_index(CPUState *cs, bool ifetch) | ||
1676 | return riscv_env_mmu_index(cpu_env(cs), ifetch); | ||
1677 | } | ||
1678 | |||
1679 | -static void riscv_cpu_reset_hold(Object *obj) | ||
1680 | +static void riscv_cpu_reset_hold(Object *obj, ResetType type) | ||
1681 | { | ||
1682 | #ifndef CONFIG_USER_ONLY | ||
1683 | uint8_t iprio; | ||
1684 | @@ -XXX,XX +XXX,XX @@ static void riscv_cpu_reset_hold(Object *obj) | ||
1685 | CPURISCVState *env = &cpu->env; | ||
1686 | |||
1687 | if (mcc->parent_phases.hold) { | ||
1688 | - mcc->parent_phases.hold(obj); | ||
1689 | + mcc->parent_phases.hold(obj, type); | ||
1690 | } | ||
1691 | #ifndef CONFIG_USER_ONLY | ||
1692 | env->misa_mxl = mcc->misa_mxl_max; | ||
1693 | diff --git a/target/rx/cpu.c b/target/rx/cpu.c | ||
1694 | index XXXXXXX..XXXXXXX 100644 | ||
1695 | --- a/target/rx/cpu.c | ||
1696 | +++ b/target/rx/cpu.c | ||
1697 | @@ -XXX,XX +XXX,XX @@ static int riscv_cpu_mmu_index(CPUState *cs, bool ifunc) | ||
1698 | return 0; | ||
1699 | } | ||
1700 | |||
1701 | -static void rx_cpu_reset_hold(Object *obj) | ||
1702 | +static void rx_cpu_reset_hold(Object *obj, ResetType type) | ||
1703 | { | ||
1704 | CPUState *cs = CPU(obj); | ||
1705 | RXCPUClass *rcc = RX_CPU_GET_CLASS(obj); | ||
1706 | @@ -XXX,XX +XXX,XX @@ static void rx_cpu_reset_hold(Object *obj) | ||
1707 | uint32_t *resetvec; | ||
1708 | |||
1709 | if (rcc->parent_phases.hold) { | ||
1710 | - rcc->parent_phases.hold(obj); | ||
1711 | + rcc->parent_phases.hold(obj, type); | ||
1712 | } | ||
1713 | |||
1714 | memset(env, 0, offsetof(CPURXState, end_reset_fields)); | ||
1715 | diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c | ||
1716 | index XXXXXXX..XXXXXXX 100644 | ||
1717 | --- a/target/sh4/cpu.c | ||
1718 | +++ b/target/sh4/cpu.c | ||
1719 | @@ -XXX,XX +XXX,XX @@ static int sh4_cpu_mmu_index(CPUState *cs, bool ifetch) | ||
1720 | } | ||
1721 | } | ||
1722 | |||
1723 | -static void superh_cpu_reset_hold(Object *obj) | ||
1724 | +static void superh_cpu_reset_hold(Object *obj, ResetType type) | ||
1725 | { | ||
1726 | CPUState *cs = CPU(obj); | ||
1727 | SuperHCPUClass *scc = SUPERH_CPU_GET_CLASS(obj); | ||
1728 | CPUSH4State *env = cpu_env(cs); | ||
1729 | |||
1730 | if (scc->parent_phases.hold) { | ||
1731 | - scc->parent_phases.hold(obj); | ||
1732 | + scc->parent_phases.hold(obj, type); | ||
1733 | } | ||
1734 | |||
1735 | memset(env, 0, offsetof(CPUSH4State, end_reset_fields)); | ||
1736 | diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c | ||
1737 | index XXXXXXX..XXXXXXX 100644 | ||
1738 | --- a/target/sparc/cpu.c | ||
1739 | +++ b/target/sparc/cpu.c | ||
75 | @@ -XXX,XX +XXX,XX @@ | 1740 | @@ -XXX,XX +XXX,XX @@ |
76 | #include "qemu/osdep.h" | 1741 | |
77 | 1742 | //#define DEBUG_FEATURES | |
78 | #include "hw/irq.h" | 1743 | |
79 | +#include "hw/qdev-clock.h" | 1744 | -static void sparc_cpu_reset_hold(Object *obj) |
80 | #include "hw/qdev-properties.h" | 1745 | +static void sparc_cpu_reset_hold(Object *obj, ResetType type) |
81 | -#include "hw/misc/npcm7xx_clk.h" | 1746 | { |
82 | #include "hw/timer/npcm7xx_timer.h" | 1747 | CPUState *cs = CPU(obj); |
83 | #include "migration/vmstate.h" | 1748 | SPARCCPUClass *scc = SPARC_CPU_GET_CLASS(obj); |
84 | #include "qemu/bitops.h" | 1749 | CPUSPARCState *env = cpu_env(cs); |
85 | @@ -XXX,XX +XXX,XX @@ static uint32_t npcm7xx_tcsr_prescaler(uint32_t tcsr) | 1750 | |
86 | /* Convert a timer cycle count to a time interval in nanoseconds. */ | 1751 | if (scc->parent_phases.hold) { |
87 | static int64_t npcm7xx_timer_count_to_ns(NPCM7xxTimer *t, uint32_t count) | 1752 | - scc->parent_phases.hold(obj); |
88 | { | 1753 | + scc->parent_phases.hold(obj, type); |
89 | - int64_t ns = count; | 1754 | } |
90 | + int64_t ticks = count; | 1755 | |
91 | 1756 | memset(env, 0, offsetof(CPUSPARCState, end_reset_fields)); | |
92 | - ns *= NANOSECONDS_PER_SECOND / NPCM7XX_TIMER_REF_HZ; | 1757 | diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c |
93 | - ns *= npcm7xx_tcsr_prescaler(t->tcsr); | 1758 | index XXXXXXX..XXXXXXX 100644 |
94 | + ticks *= npcm7xx_tcsr_prescaler(t->tcsr); | 1759 | --- a/target/tricore/cpu.c |
95 | 1760 | +++ b/target/tricore/cpu.c | |
96 | - return ns; | 1761 | @@ -XXX,XX +XXX,XX @@ static void tricore_restore_state_to_opc(CPUState *cs, |
97 | + return clock_ticks_to_ns(t->ctrl->clock, ticks); | 1762 | cpu_env(cs)->PC = data[0]; |
98 | } | 1763 | } |
99 | 1764 | ||
100 | /* Convert a time interval in nanoseconds to a timer cycle count. */ | 1765 | -static void tricore_cpu_reset_hold(Object *obj) |
101 | static uint32_t npcm7xx_timer_ns_to_count(NPCM7xxTimer *t, int64_t ns) | 1766 | +static void tricore_cpu_reset_hold(Object *obj, ResetType type) |
102 | { | 1767 | { |
103 | - int64_t count; | 1768 | CPUState *cs = CPU(obj); |
104 | - | 1769 | TriCoreCPUClass *tcc = TRICORE_CPU_GET_CLASS(obj); |
105 | - count = ns / (NANOSECONDS_PER_SECOND / NPCM7XX_TIMER_REF_HZ); | 1770 | |
106 | - count /= npcm7xx_tcsr_prescaler(t->tcsr); | 1771 | if (tcc->parent_phases.hold) { |
107 | - | 1772 | - tcc->parent_phases.hold(obj); |
108 | - return count; | 1773 | + tcc->parent_phases.hold(obj, type); |
109 | + return ns / clock_ticks_to_ns(t->ctrl->clock, | 1774 | } |
110 | + npcm7xx_tcsr_prescaler(t->tcsr)); | 1775 | |
111 | } | 1776 | cpu_state_reset(cpu_env(cs)); |
112 | 1777 | diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c | |
113 | static uint32_t npcm7xx_watchdog_timer_prescaler(const NPCM7xxWatchdogTimer *t) | 1778 | index XXXXXXX..XXXXXXX 100644 |
114 | @@ -XXX,XX +XXX,XX @@ static uint32_t npcm7xx_watchdog_timer_prescaler(const NPCM7xxWatchdogTimer *t) | 1779 | --- a/target/xtensa/cpu.c |
115 | static void npcm7xx_watchdog_timer_reset_cycles(NPCM7xxWatchdogTimer *t, | 1780 | +++ b/target/xtensa/cpu.c |
116 | int64_t cycles) | 1781 | @@ -XXX,XX +XXX,XX @@ bool xtensa_abi_call0(void) |
117 | { | 1782 | } |
118 | - uint32_t prescaler = npcm7xx_watchdog_timer_prescaler(t); | 1783 | #endif |
119 | - int64_t ns = (NANOSECONDS_PER_SECOND / NPCM7XX_TIMER_REF_HZ) * cycles; | 1784 | |
120 | + int64_t ticks = cycles * npcm7xx_watchdog_timer_prescaler(t); | 1785 | -static void xtensa_cpu_reset_hold(Object *obj) |
121 | + int64_t ns = clock_ticks_to_ns(t->ctrl->clock, ticks); | 1786 | +static void xtensa_cpu_reset_hold(Object *obj, ResetType type) |
122 | 1787 | { | |
123 | /* | 1788 | CPUState *cs = CPU(obj); |
124 | * The reset function always clears the current timer. The caller of the | 1789 | XtensaCPUClass *xcc = XTENSA_CPU_GET_CLASS(obj); |
125 | @@ -XXX,XX +XXX,XX @@ static void npcm7xx_watchdog_timer_reset_cycles(NPCM7xxWatchdogTimer *t, | 1790 | @@ -XXX,XX +XXX,XX @@ static void xtensa_cpu_reset_hold(Object *obj) |
126 | */ | 1791 | XTENSA_OPTION_DFP_COPROCESSOR); |
127 | npcm7xx_timer_clear(&t->base_timer); | 1792 | |
128 | 1793 | if (xcc->parent_phases.hold) { | |
129 | - ns *= prescaler; | 1794 | - xcc->parent_phases.hold(obj); |
130 | t->base_timer.remaining_ns = ns; | 1795 | + xcc->parent_phases.hold(obj, type); |
131 | } | 1796 | } |
132 | 1797 | ||
133 | @@ -XXX,XX +XXX,XX @@ static void npcm7xx_timer_hold_reset(Object *obj) | 1798 | env->pc = env->config->exception_vector[EXC_RESET0 + env->static_vectors]; |
134 | qemu_irq_lower(s->watchdog_timer.irq); | ||
135 | } | ||
136 | |||
137 | -static void npcm7xx_timer_realize(DeviceState *dev, Error **errp) | ||
138 | +static void npcm7xx_timer_init(Object *obj) | ||
139 | { | ||
140 | - NPCM7xxTimerCtrlState *s = NPCM7XX_TIMER(dev); | ||
141 | - SysBusDevice *sbd = &s->parent; | ||
142 | + NPCM7xxTimerCtrlState *s = NPCM7XX_TIMER(obj); | ||
143 | + DeviceState *dev = DEVICE(obj); | ||
144 | + SysBusDevice *sbd = SYS_BUS_DEVICE(obj); | ||
145 | int i; | ||
146 | NPCM7xxWatchdogTimer *w; | ||
147 | |||
148 | @@ -XXX,XX +XXX,XX @@ static void npcm7xx_timer_realize(DeviceState *dev, Error **errp) | ||
149 | npcm7xx_watchdog_timer_expired, w); | ||
150 | sysbus_init_irq(sbd, &w->irq); | ||
151 | |||
152 | - memory_region_init_io(&s->iomem, OBJECT(s), &npcm7xx_timer_ops, s, | ||
153 | + memory_region_init_io(&s->iomem, obj, &npcm7xx_timer_ops, s, | ||
154 | TYPE_NPCM7XX_TIMER, 4 * KiB); | ||
155 | sysbus_init_mmio(sbd, &s->iomem); | ||
156 | qdev_init_gpio_out_named(dev, &w->reset_signal, | ||
157 | NPCM7XX_WATCHDOG_RESET_GPIO_OUT, 1); | ||
158 | + s->clock = qdev_init_clock_in(dev, "clock", NULL, NULL); | ||
159 | } | ||
160 | |||
161 | static const VMStateDescription vmstate_npcm7xx_base_timer = { | ||
162 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_npcm7xx_watchdog_timer = { | ||
163 | |||
164 | static const VMStateDescription vmstate_npcm7xx_timer_ctrl = { | ||
165 | .name = "npcm7xx-timer-ctrl", | ||
166 | - .version_id = 1, | ||
167 | - .minimum_version_id = 1, | ||
168 | + .version_id = 2, | ||
169 | + .minimum_version_id = 2, | ||
170 | .fields = (VMStateField[]) { | ||
171 | VMSTATE_UINT32(tisr, NPCM7xxTimerCtrlState), | ||
172 | + VMSTATE_CLOCK(clock, NPCM7xxTimerCtrlState), | ||
173 | VMSTATE_STRUCT_ARRAY(timer, NPCM7xxTimerCtrlState, | ||
174 | NPCM7XX_TIMERS_PER_CTRL, 0, vmstate_npcm7xx_timer, | ||
175 | NPCM7xxTimer), | ||
176 | @@ -XXX,XX +XXX,XX @@ static void npcm7xx_timer_class_init(ObjectClass *klass, void *data) | ||
177 | QEMU_BUILD_BUG_ON(NPCM7XX_TIMER_REGS_END > NPCM7XX_TIMER_NR_REGS); | ||
178 | |||
179 | dc->desc = "NPCM7xx Timer Controller"; | ||
180 | - dc->realize = npcm7xx_timer_realize; | ||
181 | dc->vmsd = &vmstate_npcm7xx_timer_ctrl; | ||
182 | rc->phases.enter = npcm7xx_timer_enter_reset; | ||
183 | rc->phases.hold = npcm7xx_timer_hold_reset; | ||
184 | @@ -XXX,XX +XXX,XX @@ static const TypeInfo npcm7xx_timer_info = { | ||
185 | .parent = TYPE_SYS_BUS_DEVICE, | ||
186 | .instance_size = sizeof(NPCM7xxTimerCtrlState), | ||
187 | .class_init = npcm7xx_timer_class_init, | ||
188 | + .instance_init = npcm7xx_timer_init, | ||
189 | }; | ||
190 | |||
191 | static void npcm7xx_timer_register_type(void) | ||
192 | -- | 1799 | -- |
193 | 2.20.1 | 1800 | 2.34.1 |
194 | |||
195 | diff view generated by jsdifflib |
1 | The lan9118 code mostly uses symbolic constants for register offsets; | 1 | Update the reset documentation's example code to match the new API |
---|---|---|---|
2 | the exceptions are those which the datasheet doesn't give an official | 2 | for the hold and exit phase method APIs where they take a ResetType |
3 | symbolic name to. | 3 | argument. |
4 | |||
5 | Add some names for the registers which don't already have them, based | ||
6 | on the longer names they are given in the memory map. | ||
7 | 4 | ||
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
9 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
10 | Message-id: 20210108180401.2263-3-peter.maydell@linaro.org | 7 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
8 | Reviewed-by: Luc Michel <luc.michel@amd.com> | ||
9 | Message-id: 20240412160809.1260625-6-peter.maydell@linaro.org | ||
11 | --- | 10 | --- |
12 | hw/net/lan9118.c | 24 ++++++++++++++++++------ | 11 | docs/devel/reset.rst | 8 ++++---- |
13 | 1 file changed, 18 insertions(+), 6 deletions(-) | 12 | 1 file changed, 4 insertions(+), 4 deletions(-) |
14 | 13 | ||
15 | diff --git a/hw/net/lan9118.c b/hw/net/lan9118.c | 14 | diff --git a/docs/devel/reset.rst b/docs/devel/reset.rst |
16 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/hw/net/lan9118.c | 16 | --- a/docs/devel/reset.rst |
18 | +++ b/hw/net/lan9118.c | 17 | +++ b/docs/devel/reset.rst |
19 | @@ -XXX,XX +XXX,XX @@ do { hw_error("lan9118: error: " fmt , ## __VA_ARGS__);} while (0) | 18 | @@ -XXX,XX +XXX,XX @@ in reset. |
20 | do { fprintf(stderr, "lan9118: error: " fmt , ## __VA_ARGS__);} while (0) | 19 | mydev->var = 0; |
21 | #endif | ||
22 | |||
23 | +/* The tx and rx fifo ports are a range of aliased 32-bit registers */ | ||
24 | +#define RX_DATA_FIFO_PORT_FIRST 0x00 | ||
25 | +#define RX_DATA_FIFO_PORT_LAST 0x1f | ||
26 | +#define TX_DATA_FIFO_PORT_FIRST 0x20 | ||
27 | +#define TX_DATA_FIFO_PORT_LAST 0x3f | ||
28 | + | ||
29 | +#define RX_STATUS_FIFO_PORT 0x40 | ||
30 | +#define RX_STATUS_FIFO_PEEK 0x44 | ||
31 | +#define TX_STATUS_FIFO_PORT 0x48 | ||
32 | +#define TX_STATUS_FIFO_PEEK 0x4c | ||
33 | + | ||
34 | #define CSR_ID_REV 0x50 | ||
35 | #define CSR_IRQ_CFG 0x54 | ||
36 | #define CSR_INT_STS 0x58 | ||
37 | @@ -XXX,XX +XXX,XX @@ static void lan9118_writel(void *opaque, hwaddr offset, | ||
38 | offset &= 0xff; | ||
39 | |||
40 | //DPRINTF("Write reg 0x%02x = 0x%08x\n", (int)offset, val); | ||
41 | - if (offset >= 0x20 && offset < 0x40) { | ||
42 | + if (offset >= TX_DATA_FIFO_PORT_FIRST && | ||
43 | + offset <= TX_DATA_FIFO_PORT_LAST) { | ||
44 | /* TX FIFO */ | ||
45 | tx_fifo_push(s, val); | ||
46 | return; | ||
47 | @@ -XXX,XX +XXX,XX @@ static uint64_t lan9118_readl(void *opaque, hwaddr offset, | ||
48 | lan9118_state *s = (lan9118_state *)opaque; | ||
49 | |||
50 | //DPRINTF("Read reg 0x%02x\n", (int)offset); | ||
51 | - if (offset < 0x20) { | ||
52 | + if (offset <= RX_DATA_FIFO_PORT_LAST) { | ||
53 | /* RX FIFO */ | ||
54 | return rx_fifo_pop(s); | ||
55 | } | 20 | } |
56 | switch (offset) { | 21 | |
57 | - case 0x40: | 22 | - static void mydev_reset_hold(Object *obj) |
58 | + case RX_STATUS_FIFO_PORT: | 23 | + static void mydev_reset_hold(Object *obj, ResetType type) |
59 | return rx_status_fifo_pop(s); | 24 | { |
60 | - case 0x44: | 25 | MyDevClass *myclass = MYDEV_GET_CLASS(obj); |
61 | + case RX_STATUS_FIFO_PEEK: | 26 | MyDevState *mydev = MYDEV(obj); |
62 | return s->rx_status_fifo[s->rx_status_fifo_head]; | 27 | /* call parent class hold phase */ |
63 | - case 0x48: | 28 | if (myclass->parent_phases.hold) { |
64 | + case TX_STATUS_FIFO_PORT: | 29 | - myclass->parent_phases.hold(obj); |
65 | return tx_status_fifo_pop(s); | 30 | + myclass->parent_phases.hold(obj, type); |
66 | - case 0x4c: | 31 | } |
67 | + case TX_STATUS_FIFO_PEEK: | 32 | /* set an IO */ |
68 | return s->tx_status_fifo[s->tx_status_fifo_head]; | 33 | qemu_set_irq(mydev->irq, 1); |
69 | case CSR_ID_REV: | 34 | } |
70 | return 0x01180001; | 35 | |
36 | - static void mydev_reset_exit(Object *obj) | ||
37 | + static void mydev_reset_exit(Object *obj, ResetType type) | ||
38 | { | ||
39 | MyDevClass *myclass = MYDEV_GET_CLASS(obj); | ||
40 | MyDevState *mydev = MYDEV(obj); | ||
41 | /* call parent class exit phase */ | ||
42 | if (myclass->parent_phases.exit) { | ||
43 | - myclass->parent_phases.exit(obj); | ||
44 | + myclass->parent_phases.exit(obj, type); | ||
45 | } | ||
46 | /* clear an IO */ | ||
47 | qemu_set_irq(mydev->irq, 0); | ||
71 | -- | 48 | -- |
72 | 2.20.1 | 49 | 2.34.1 |
73 | 50 | ||
74 | 51 | diff view generated by jsdifflib |
1 | In commit 1982e1602d15 we added a new qemu-storage-daemon(1) manpage. | 1 | Some devices and machines need to handle the reset before a vmsave |
---|---|---|---|
2 | At the moment new manpages have to be listed both in the conf.py for | 2 | snapshot is loaded differently -- the main user is the handling of |
3 | Sphinx and also in docs/meson.build for Meson. We forgot the second | 3 | RNG seed information, which does not want to put a new RNG seed into |
4 | of those -- correct the omission. | 4 | a ROM blob when we are doing a snapshot load. |
5 | |||
6 | Currently this kind of reset handling is supported only for: | ||
7 | * TYPE_MACHINE reset methods, which take a ShutdownCause argument | ||
8 | * reset functions registered with qemu_register_reset_nosnapshotload | ||
9 | |||
10 | To allow a three-phase-reset device to also distinguish "snapshot | ||
11 | load" reset from the normal kind, add a new ResetType | ||
12 | RESET_TYPE_SNAPSHOT_LOAD. All our existing reset methods ignore | ||
13 | the reset type, so we don't need to update any device code. | ||
14 | |||
15 | Add the enum type, and make qemu_devices_reset() use the | ||
16 | right reset type for the ShutdownCause it is passed. This | ||
17 | allows us to get rid of the device_reset_reason global we | ||
18 | were using to implement qemu_register_reset_nosnapshotload(). | ||
5 | 19 | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 20 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> | 21 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
8 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | 22 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
9 | Message-id: 20210108161416.21129-2-peter.maydell@linaro.org | 23 | Reviewed-by: Luc Michel <luc.michel@amd.com> |
24 | Message-id: 20240412160809.1260625-7-peter.maydell@linaro.org | ||
10 | --- | 25 | --- |
11 | docs/meson.build | 1 + | 26 | docs/devel/reset.rst | 17 ++++++++++++++--- |
12 | 1 file changed, 1 insertion(+) | 27 | include/hw/resettable.h | 1 + |
28 | hw/core/reset.c | 15 ++++----------- | ||
29 | hw/core/resettable.c | 4 ---- | ||
30 | 4 files changed, 19 insertions(+), 18 deletions(-) | ||
13 | 31 | ||
14 | diff --git a/docs/meson.build b/docs/meson.build | 32 | diff --git a/docs/devel/reset.rst b/docs/devel/reset.rst |
15 | index XXXXXXX..XXXXXXX 100644 | 33 | index XXXXXXX..XXXXXXX 100644 |
16 | --- a/docs/meson.build | 34 | --- a/docs/devel/reset.rst |
17 | +++ b/docs/meson.build | 35 | +++ b/docs/devel/reset.rst |
18 | @@ -XXX,XX +XXX,XX @@ if build_docs | 36 | @@ -XXX,XX +XXX,XX @@ instantly reset an object, without keeping it in reset state, just call |
19 | 'qemu-img.1': (have_tools ? 'man1' : ''), | 37 | ``resettable_reset()``. These functions take two parameters: a pointer to the |
20 | 'qemu-nbd.8': (have_tools ? 'man8' : ''), | 38 | object to reset and a reset type. |
21 | 'qemu-pr-helper.8': (have_tools ? 'man8' : ''), | 39 | |
22 | + 'qemu-storage-daemon.1': (have_tools ? 'man1' : ''), | 40 | -Several types of reset will be supported. For now only cold reset is defined; |
23 | 'qemu-trace-stap.1': (config_host.has_key('CONFIG_TRACE_SYSTEMTAP') ? 'man1' : ''), | 41 | -others may be added later. The Resettable interface handles reset types with an |
24 | 'virtfs-proxy-helper.1': (have_virtfs_proxy_helper ? 'man1' : ''), | 42 | -enum: |
25 | 'virtiofsd.1': (have_virtiofsd ? 'man1' : ''), | 43 | +The Resettable interface handles reset types with an enum ``ResetType``: |
44 | |||
45 | ``RESET_TYPE_COLD`` | ||
46 | Cold reset is supported by every resettable object. In QEMU, it means we reset | ||
47 | @@ -XXX,XX +XXX,XX @@ enum: | ||
48 | from what is a real hardware cold reset. It differs from other resets (like | ||
49 | warm or bus resets) which may keep certain parts untouched. | ||
50 | |||
51 | +``RESET_TYPE_SNAPSHOT_LOAD`` | ||
52 | + This is called for a reset which is being done to put the system into a | ||
53 | + clean state prior to loading a snapshot. (This corresponds to a reset | ||
54 | + with ``SHUTDOWN_CAUSE_SNAPSHOT_LOAD``.) Almost all devices should treat | ||
55 | + this the same as ``RESET_TYPE_COLD``. The main exception is devices which | ||
56 | + have some non-deterministic state they want to reinitialize to a different | ||
57 | + value on each cold reset, such as RNG seed information, and which they | ||
58 | + must not reinitialize on a snapshot-load reset. | ||
59 | + | ||
60 | +Devices which implement reset methods must treat any unknown ``ResetType`` | ||
61 | +as equivalent to ``RESET_TYPE_COLD``; this will reduce the amount of | ||
62 | +existing code we need to change if we add more types in future. | ||
63 | + | ||
64 | Calling ``resettable_reset()`` is equivalent to calling | ||
65 | ``resettable_assert_reset()`` then ``resettable_release_reset()``. It is | ||
66 | possible to interleave multiple calls to these three functions. There may | ||
67 | diff --git a/include/hw/resettable.h b/include/hw/resettable.h | ||
68 | index XXXXXXX..XXXXXXX 100644 | ||
69 | --- a/include/hw/resettable.h | ||
70 | +++ b/include/hw/resettable.h | ||
71 | @@ -XXX,XX +XXX,XX @@ typedef struct ResettableState ResettableState; | ||
72 | */ | ||
73 | typedef enum ResetType { | ||
74 | RESET_TYPE_COLD, | ||
75 | + RESET_TYPE_SNAPSHOT_LOAD, | ||
76 | } ResetType; | ||
77 | |||
78 | /* | ||
79 | diff --git a/hw/core/reset.c b/hw/core/reset.c | ||
80 | index XXXXXXX..XXXXXXX 100644 | ||
81 | --- a/hw/core/reset.c | ||
82 | +++ b/hw/core/reset.c | ||
83 | @@ -XXX,XX +XXX,XX @@ static ResettableContainer *get_root_reset_container(void) | ||
84 | return root_reset_container; | ||
85 | } | ||
86 | |||
87 | -/* | ||
88 | - * Reason why the currently in-progress qemu_devices_reset() was called. | ||
89 | - * If we made at least SHUTDOWN_CAUSE_SNAPSHOT_LOAD have a corresponding | ||
90 | - * ResetType we could perhaps avoid the need for this global. | ||
91 | - */ | ||
92 | -static ShutdownCause device_reset_reason; | ||
93 | - | ||
94 | /* | ||
95 | * This is an Object which implements Resettable simply to call the | ||
96 | * callback function in the hold phase. | ||
97 | @@ -XXX,XX +XXX,XX @@ static void legacy_reset_hold(Object *obj, ResetType type) | ||
98 | { | ||
99 | LegacyReset *lr = LEGACY_RESET(obj); | ||
100 | |||
101 | - if (device_reset_reason == SHUTDOWN_CAUSE_SNAPSHOT_LOAD && | ||
102 | - lr->skip_on_snapshot_load) { | ||
103 | + if (type == RESET_TYPE_SNAPSHOT_LOAD && lr->skip_on_snapshot_load) { | ||
104 | return; | ||
105 | } | ||
106 | lr->func(lr->opaque); | ||
107 | @@ -XXX,XX +XXX,XX @@ void qemu_unregister_resettable(Object *obj) | ||
108 | |||
109 | void qemu_devices_reset(ShutdownCause reason) | ||
110 | { | ||
111 | - device_reset_reason = reason; | ||
112 | + ResetType type = (reason == SHUTDOWN_CAUSE_SNAPSHOT_LOAD) ? | ||
113 | + RESET_TYPE_SNAPSHOT_LOAD : RESET_TYPE_COLD; | ||
114 | |||
115 | /* Reset the simulation */ | ||
116 | - resettable_reset(OBJECT(get_root_reset_container()), RESET_TYPE_COLD); | ||
117 | + resettable_reset(OBJECT(get_root_reset_container()), type); | ||
118 | } | ||
119 | diff --git a/hw/core/resettable.c b/hw/core/resettable.c | ||
120 | index XXXXXXX..XXXXXXX 100644 | ||
121 | --- a/hw/core/resettable.c | ||
122 | +++ b/hw/core/resettable.c | ||
123 | @@ -XXX,XX +XXX,XX @@ void resettable_reset(Object *obj, ResetType type) | ||
124 | |||
125 | void resettable_assert_reset(Object *obj, ResetType type) | ||
126 | { | ||
127 | - /* TODO: change this assert when adding support for other reset types */ | ||
128 | - assert(type == RESET_TYPE_COLD); | ||
129 | trace_resettable_reset_assert_begin(obj, type); | ||
130 | assert(!enter_phase_in_progress); | ||
131 | |||
132 | @@ -XXX,XX +XXX,XX @@ void resettable_assert_reset(Object *obj, ResetType type) | ||
133 | |||
134 | void resettable_release_reset(Object *obj, ResetType type) | ||
135 | { | ||
136 | - /* TODO: change this assert when adding support for other reset types */ | ||
137 | - assert(type == RESET_TYPE_COLD); | ||
138 | trace_resettable_reset_release_begin(obj, type); | ||
139 | assert(!enter_phase_in_progress); | ||
140 | |||
26 | -- | 141 | -- |
27 | 2.20.1 | 142 | 2.34.1 |
28 | 143 | ||
29 | 144 | diff view generated by jsdifflib |
1 | From: Hao Wu <wuhaotsh@google.com> | 1 | From: Arnaud Minier <arnaud.minier@telecom-paris.fr> |
---|---|---|---|
2 | 2 | ||
3 | The PWM module is part of NPCM7XX module. Each NPCM7XX module has two | 3 | Add the basic infrastructure (register read/write, type...) |
4 | identical PWM modules. Each module contains 4 PWM entries. Each PWM has | 4 | to implement the STM32L4x5 USART. |
5 | two outputs: frequency and duty_cycle. Both are computed using inputs | ||
6 | from software side. | ||
7 | 5 | ||
8 | This module does not model detail pulse signals since it is expensive. | 6 | Also create different types for the USART, UART and LPUART |
9 | It also does not model interrupts and watchdogs that are dependant on | 7 | of the STM32L4x5 to deduplicate code and enable the |
10 | the detail models. The interfaces for these are left in the module so | 8 | implementation of different behaviors depending on the type. |
11 | that anyone in need for these functionalities can implement on their | ||
12 | own. | ||
13 | 9 | ||
14 | The user can read the duty cycle and frequency using qom-get command. | 10 | Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr> |
15 | 11 | Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr> | |
16 | Reviewed-by: Havard Skinnemoen <hskinnemoen@google.com> | ||
17 | Reviewed-by: Tyrone Ting <kfting@nuvoton.com> | ||
18 | Signed-off-by: Hao Wu <wuhaotsh@google.com> | ||
19 | Message-id: 20210108190945.949196-5-wuhaotsh@google.com | ||
20 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 12 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
13 | Message-id: 20240329174402.60382-2-arnaud.minier@telecom-paris.fr | ||
14 | [PMM: update to new reset hold method signature; | ||
15 | fixed a few checkpatch nits] | ||
21 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 16 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
22 | --- | 17 | --- |
23 | docs/system/arm/nuvoton.rst | 2 +- | 18 | MAINTAINERS | 1 + |
24 | include/hw/arm/npcm7xx.h | 2 + | 19 | include/hw/char/stm32l4x5_usart.h | 66 +++++ |
25 | include/hw/misc/npcm7xx_pwm.h | 105 +++++++ | 20 | hw/char/stm32l4x5_usart.c | 396 ++++++++++++++++++++++++++++++ |
26 | hw/arm/npcm7xx.c | 26 +- | 21 | hw/char/Kconfig | 3 + |
27 | hw/misc/npcm7xx_pwm.c | 550 ++++++++++++++++++++++++++++++++++ | 22 | hw/char/meson.build | 1 + |
28 | hw/misc/meson.build | 1 + | 23 | hw/char/trace-events | 4 + |
29 | hw/misc/trace-events | 6 + | 24 | 6 files changed, 471 insertions(+) |
30 | 7 files changed, 689 insertions(+), 3 deletions(-) | 25 | create mode 100644 include/hw/char/stm32l4x5_usart.h |
31 | create mode 100644 include/hw/misc/npcm7xx_pwm.h | 26 | create mode 100644 hw/char/stm32l4x5_usart.c |
32 | create mode 100644 hw/misc/npcm7xx_pwm.c | ||
33 | 27 | ||
34 | diff --git a/docs/system/arm/nuvoton.rst b/docs/system/arm/nuvoton.rst | 28 | diff --git a/MAINTAINERS b/MAINTAINERS |
35 | index XXXXXXX..XXXXXXX 100644 | 29 | index XXXXXXX..XXXXXXX 100644 |
36 | --- a/docs/system/arm/nuvoton.rst | 30 | --- a/MAINTAINERS |
37 | +++ b/docs/system/arm/nuvoton.rst | 31 | +++ b/MAINTAINERS |
38 | @@ -XXX,XX +XXX,XX @@ Supported devices | 32 | @@ -XXX,XX +XXX,XX @@ M: Inès Varhol <ines.varhol@telecom-paris.fr> |
39 | * USB host (USBH) | 33 | L: qemu-arm@nongnu.org |
40 | * GPIO controller | 34 | S: Maintained |
41 | * Analog to Digital Converter (ADC) | 35 | F: hw/arm/stm32l4x5_soc.c |
42 | + * Pulse Width Modulation (PWM) | 36 | +F: hw/char/stm32l4x5_usart.c |
43 | 37 | F: hw/misc/stm32l4x5_exti.c | |
44 | Missing devices | 38 | F: hw/misc/stm32l4x5_syscfg.c |
45 | --------------- | 39 | F: hw/misc/stm32l4x5_rcc.c |
46 | @@ -XXX,XX +XXX,XX @@ Missing devices | 40 | diff --git a/include/hw/char/stm32l4x5_usart.h b/include/hw/char/stm32l4x5_usart.h |
47 | * Peripheral SPI controller (PSPI) | ||
48 | * SD/MMC host | ||
49 | * PECI interface | ||
50 | - * Pulse Width Modulation (PWM) | ||
51 | * Tachometer | ||
52 | * PCI and PCIe root complex and bridges | ||
53 | * VDM and MCTP support | ||
54 | diff --git a/include/hw/arm/npcm7xx.h b/include/hw/arm/npcm7xx.h | ||
55 | index XXXXXXX..XXXXXXX 100644 | ||
56 | --- a/include/hw/arm/npcm7xx.h | ||
57 | +++ b/include/hw/arm/npcm7xx.h | ||
58 | @@ -XXX,XX +XXX,XX @@ | ||
59 | #include "hw/mem/npcm7xx_mc.h" | ||
60 | #include "hw/misc/npcm7xx_clk.h" | ||
61 | #include "hw/misc/npcm7xx_gcr.h" | ||
62 | +#include "hw/misc/npcm7xx_pwm.h" | ||
63 | #include "hw/misc/npcm7xx_rng.h" | ||
64 | #include "hw/nvram/npcm7xx_otp.h" | ||
65 | #include "hw/timer/npcm7xx_timer.h" | ||
66 | @@ -XXX,XX +XXX,XX @@ typedef struct NPCM7xxState { | ||
67 | NPCM7xxCLKState clk; | ||
68 | NPCM7xxTimerCtrlState tim[3]; | ||
69 | NPCM7xxADCState adc; | ||
70 | + NPCM7xxPWMState pwm[2]; | ||
71 | NPCM7xxOTPState key_storage; | ||
72 | NPCM7xxOTPState fuse_array; | ||
73 | NPCM7xxMCState mc; | ||
74 | diff --git a/include/hw/misc/npcm7xx_pwm.h b/include/hw/misc/npcm7xx_pwm.h | ||
75 | new file mode 100644 | 41 | new file mode 100644 |
76 | index XXXXXXX..XXXXXXX | 42 | index XXXXXXX..XXXXXXX |
77 | --- /dev/null | 43 | --- /dev/null |
78 | +++ b/include/hw/misc/npcm7xx_pwm.h | 44 | +++ b/include/hw/char/stm32l4x5_usart.h |
79 | @@ -XXX,XX +XXX,XX @@ | 45 | @@ -XXX,XX +XXX,XX @@ |
80 | +/* | 46 | +/* |
81 | + * Nuvoton NPCM7xx PWM Module | 47 | + * STM32L4X5 USART (Universal Synchronous Asynchronous Receiver Transmitter) |
82 | + * | 48 | + * |
83 | + * Copyright 2020 Google LLC | 49 | + * Copyright (c) 2023 Arnaud Minier <arnaud.minier@telecom-paris.fr> |
84 | + * | 50 | + * Copyright (c) 2023 Inès Varhol <ines.varhol@telecom-paris.fr> |
85 | + * This program is free software; you can redistribute it and/or modify it | 51 | + * |
86 | + * under the terms of the GNU General Public License as published by the | 52 | + * SPDX-License-Identifier: GPL-2.0-or-later |
87 | + * Free Software Foundation; either version 2 of the License, or | 53 | + * |
88 | + * (at your option) any later version. | 54 | + * This work is licensed under the terms of the GNU GPL, version 2 or later. |
89 | + * | 55 | + * See the COPYING file in the top-level directory. |
90 | + * This program is distributed in the hope that it will be useful, but WITHOUT | 56 | + * |
91 | + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | 57 | + * The STM32L4X5 USART is heavily inspired by the stm32f2xx_usart |
92 | + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | 58 | + * by Alistair Francis. |
93 | + * for more details. | 59 | + * The reference used is the STMicroElectronics RM0351 Reference manual |
60 | + * for STM32L4x5 and STM32L4x6 advanced Arm ® -based 32-bit MCUs. | ||
94 | + */ | 61 | + */ |
95 | +#ifndef NPCM7XX_PWM_H | 62 | + |
96 | +#define NPCM7XX_PWM_H | 63 | +#ifndef HW_STM32L4X5_USART_H |
97 | + | 64 | +#define HW_STM32L4X5_USART_H |
98 | +#include "hw/clock.h" | 65 | + |
99 | +#include "hw/sysbus.h" | 66 | +#include "hw/sysbus.h" |
100 | +#include "hw/irq.h" | 67 | +#include "chardev/char-fe.h" |
101 | + | 68 | +#include "qom/object.h" |
102 | +/* Each PWM module holds 4 PWM channels. */ | 69 | + |
103 | +#define NPCM7XX_PWM_PER_MODULE 4 | 70 | +#define TYPE_STM32L4X5_USART_BASE "stm32l4x5-usart-base" |
104 | + | 71 | +#define TYPE_STM32L4X5_USART "stm32l4x5-usart" |
105 | +/* | 72 | +#define TYPE_STM32L4X5_UART "stm32l4x5-uart" |
106 | + * Number of registers in one pwm module. Don't change this without increasing | 73 | +#define TYPE_STM32L4X5_LPUART "stm32l4x5-lpuart" |
107 | + * the version_id in vmstate. | 74 | +OBJECT_DECLARE_TYPE(Stm32l4x5UsartBaseState, Stm32l4x5UsartBaseClass, |
108 | + */ | 75 | + STM32L4X5_USART_BASE) |
109 | +#define NPCM7XX_PWM_NR_REGS (0x54 / sizeof(uint32_t)) | 76 | + |
110 | + | 77 | +typedef enum { |
111 | +/* | 78 | + STM32L4x5_USART, |
112 | + * The maximum duty values. Each duty unit represents 1/NPCM7XX_PWM_MAX_DUTY | 79 | + STM32L4x5_UART, |
113 | + * cycles. For example, if NPCM7XX_PWM_MAX_DUTY=1,000,000 and a PWM has a duty | 80 | + STM32L4x5_LPUART, |
114 | + * value of 100,000 the duty cycle for that PWM is 10%. | 81 | +} Stm32l4x5UsartType; |
115 | + */ | 82 | + |
116 | +#define NPCM7XX_PWM_MAX_DUTY 1000000 | 83 | +struct Stm32l4x5UsartBaseState { |
117 | + | 84 | + SysBusDevice parent_obj; |
118 | +typedef struct NPCM7xxPWMState NPCM7xxPWMState; | 85 | + |
119 | + | 86 | + MemoryRegion mmio; |
120 | +/** | 87 | + |
121 | + * struct NPCM7xxPWM - The state of a single PWM channel. | 88 | + uint32_t cr1; |
122 | + * @module: The PWM module that contains this channel. | 89 | + uint32_t cr2; |
123 | + * @irq: GIC interrupt line to fire on expiration if enabled. | 90 | + uint32_t cr3; |
124 | + * @running: Whether this PWM channel is generating output. | 91 | + uint32_t brr; |
125 | + * @inverted: Whether this PWM channel is inverted. | 92 | + uint32_t gtpr; |
126 | + * @index: The index of this PWM channel. | 93 | + uint32_t rtor; |
127 | + * @cnr: The counter register. | 94 | + /* rqr is write-only */ |
128 | + * @cmr: The comparator register. | 95 | + uint32_t isr; |
129 | + * @pdr: The data register. | 96 | + /* icr is a clear register */ |
130 | + * @pwdr: The watchdog register. | 97 | + uint32_t rdr; |
131 | + * @freq: The frequency of this PWM channel. | 98 | + uint32_t tdr; |
132 | + * @duty: The duty cycle of this PWM channel. One unit represents | 99 | + |
133 | + * 1/NPCM7XX_MAX_DUTY cycles. | 100 | + Clock *clk; |
134 | + */ | 101 | + CharBackend chr; |
135 | +typedef struct NPCM7xxPWM { | 102 | + qemu_irq irq; |
136 | + NPCM7xxPWMState *module; | ||
137 | + | ||
138 | + qemu_irq irq; | ||
139 | + | ||
140 | + bool running; | ||
141 | + bool inverted; | ||
142 | + | ||
143 | + uint8_t index; | ||
144 | + uint32_t cnr; | ||
145 | + uint32_t cmr; | ||
146 | + uint32_t pdr; | ||
147 | + uint32_t pwdr; | ||
148 | + | ||
149 | + uint32_t freq; | ||
150 | + uint32_t duty; | ||
151 | +} NPCM7xxPWM; | ||
152 | + | ||
153 | +/** | ||
154 | + * struct NPCM7xxPWMState - Pulse Width Modulation device state. | ||
155 | + * @parent: System bus device. | ||
156 | + * @iomem: Memory region through which registers are accessed. | ||
157 | + * @clock: The PWM clock. | ||
158 | + * @pwm: The PWM channels owned by this module. | ||
159 | + * @ppr: The prescaler register. | ||
160 | + * @csr: The clock selector register. | ||
161 | + * @pcr: The control register. | ||
162 | + * @pier: The interrupt enable register. | ||
163 | + * @piir: The interrupt indication register. | ||
164 | + */ | ||
165 | +struct NPCM7xxPWMState { | ||
166 | + SysBusDevice parent; | ||
167 | + | ||
168 | + MemoryRegion iomem; | ||
169 | + | ||
170 | + Clock *clock; | ||
171 | + NPCM7xxPWM pwm[NPCM7XX_PWM_PER_MODULE]; | ||
172 | + | ||
173 | + uint32_t ppr; | ||
174 | + uint32_t csr; | ||
175 | + uint32_t pcr; | ||
176 | + uint32_t pier; | ||
177 | + uint32_t piir; | ||
178 | +}; | 103 | +}; |
179 | + | 104 | + |
180 | +#define TYPE_NPCM7XX_PWM "npcm7xx-pwm" | 105 | +struct Stm32l4x5UsartBaseClass { |
181 | +#define NPCM7XX_PWM(obj) \ | 106 | + SysBusDeviceClass parent_class; |
182 | + OBJECT_CHECK(NPCM7xxPWMState, (obj), TYPE_NPCM7XX_PWM) | 107 | + |
183 | + | 108 | + Stm32l4x5UsartType type; |
184 | +#endif /* NPCM7XX_PWM_H */ | ||
185 | diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c | ||
186 | index XXXXXXX..XXXXXXX 100644 | ||
187 | --- a/hw/arm/npcm7xx.c | ||
188 | +++ b/hw/arm/npcm7xx.c | ||
189 | @@ -XXX,XX +XXX,XX @@ enum NPCM7xxInterrupt { | ||
190 | NPCM7XX_WDG2_IRQ, /* Timer Module 2 Watchdog */ | ||
191 | NPCM7XX_EHCI_IRQ = 61, | ||
192 | NPCM7XX_OHCI_IRQ = 62, | ||
193 | + NPCM7XX_PWM0_IRQ = 93, /* PWM module 0 */ | ||
194 | + NPCM7XX_PWM1_IRQ, /* PWM module 1 */ | ||
195 | NPCM7XX_GPIO0_IRQ = 116, | ||
196 | NPCM7XX_GPIO1_IRQ, | ||
197 | NPCM7XX_GPIO2_IRQ, | ||
198 | @@ -XXX,XX +XXX,XX @@ static const hwaddr npcm7xx_fiu3_flash_addr[] = { | ||
199 | 0xb8000000, /* CS3 */ | ||
200 | }; | ||
201 | |||
202 | +/* Register base address for each PWM Module */ | ||
203 | +static const hwaddr npcm7xx_pwm_addr[] = { | ||
204 | + 0xf0103000, | ||
205 | + 0xf0104000, | ||
206 | +}; | 109 | +}; |
207 | + | 110 | + |
208 | static const struct { | 111 | +#endif /* HW_STM32L4X5_USART_H */ |
209 | hwaddr regs_addr; | 112 | diff --git a/hw/char/stm32l4x5_usart.c b/hw/char/stm32l4x5_usart.c |
210 | uint32_t unconnected_pins; | ||
211 | @@ -XXX,XX +XXX,XX @@ static void npcm7xx_init(Object *obj) | ||
212 | object_initialize_child(obj, npcm7xx_fiu[i].name, &s->fiu[i], | ||
213 | TYPE_NPCM7XX_FIU); | ||
214 | } | ||
215 | + | ||
216 | + for (i = 0; i < ARRAY_SIZE(s->pwm); i++) { | ||
217 | + object_initialize_child(obj, "pwm[*]", &s->pwm[i], TYPE_NPCM7XX_PWM); | ||
218 | + } | ||
219 | } | ||
220 | |||
221 | static void npcm7xx_realize(DeviceState *dev, Error **errp) | ||
222 | @@ -XXX,XX +XXX,XX @@ static void npcm7xx_realize(DeviceState *dev, Error **errp) | ||
223 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->ohci), 0, | ||
224 | npcm7xx_irq(s, NPCM7XX_OHCI_IRQ)); | ||
225 | |||
226 | + /* PWM Modules. Cannot fail. */ | ||
227 | + QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_pwm_addr) != ARRAY_SIZE(s->pwm)); | ||
228 | + for (i = 0; i < ARRAY_SIZE(s->pwm); i++) { | ||
229 | + SysBusDevice *sbd = SYS_BUS_DEVICE(&s->pwm[i]); | ||
230 | + | ||
231 | + qdev_connect_clock_in(DEVICE(&s->pwm[i]), "clock", qdev_get_clock_out( | ||
232 | + DEVICE(&s->clk), "apb3-clock")); | ||
233 | + sysbus_realize(sbd, &error_abort); | ||
234 | + sysbus_mmio_map(sbd, 0, npcm7xx_pwm_addr[i]); | ||
235 | + sysbus_connect_irq(sbd, i, npcm7xx_irq(s, NPCM7XX_PWM0_IRQ + i)); | ||
236 | + } | ||
237 | + | ||
238 | /* | ||
239 | * Flash Interface Unit (FIU). Can fail if incorrect number of chip selects | ||
240 | * specified, but this is a programming error. | ||
241 | @@ -XXX,XX +XXX,XX @@ static void npcm7xx_realize(DeviceState *dev, Error **errp) | ||
242 | create_unimplemented_device("npcm7xx.peci", 0xf0100000, 4 * KiB); | ||
243 | create_unimplemented_device("npcm7xx.siox[1]", 0xf0101000, 4 * KiB); | ||
244 | create_unimplemented_device("npcm7xx.siox[2]", 0xf0102000, 4 * KiB); | ||
245 | - create_unimplemented_device("npcm7xx.pwm[0]", 0xf0103000, 4 * KiB); | ||
246 | - create_unimplemented_device("npcm7xx.pwm[1]", 0xf0104000, 4 * KiB); | ||
247 | create_unimplemented_device("npcm7xx.mft[0]", 0xf0180000, 4 * KiB); | ||
248 | create_unimplemented_device("npcm7xx.mft[1]", 0xf0181000, 4 * KiB); | ||
249 | create_unimplemented_device("npcm7xx.mft[2]", 0xf0182000, 4 * KiB); | ||
250 | diff --git a/hw/misc/npcm7xx_pwm.c b/hw/misc/npcm7xx_pwm.c | ||
251 | new file mode 100644 | 113 | new file mode 100644 |
252 | index XXXXXXX..XXXXXXX | 114 | index XXXXXXX..XXXXXXX |
253 | --- /dev/null | 115 | --- /dev/null |
254 | +++ b/hw/misc/npcm7xx_pwm.c | 116 | +++ b/hw/char/stm32l4x5_usart.c |
255 | @@ -XXX,XX +XXX,XX @@ | 117 | @@ -XXX,XX +XXX,XX @@ |
256 | +/* | 118 | +/* |
257 | + * Nuvoton NPCM7xx PWM Module | 119 | + * STM32L4X5 USART (Universal Synchronous Asynchronous Receiver Transmitter) |
258 | + * | 120 | + * |
259 | + * Copyright 2020 Google LLC | 121 | + * Copyright (c) 2023 Arnaud Minier <arnaud.minier@telecom-paris.fr> |
260 | + * | 122 | + * Copyright (c) 2023 Inès Varhol <ines.varhol@telecom-paris.fr> |
261 | + * This program is free software; you can redistribute it and/or modify it | 123 | + * |
262 | + * under the terms of the GNU General Public License as published by the | 124 | + * SPDX-License-Identifier: GPL-2.0-or-later |
263 | + * Free Software Foundation; either version 2 of the License, or | 125 | + * |
264 | + * (at your option) any later version. | 126 | + * This work is licensed under the terms of the GNU GPL, version 2 or later. |
265 | + * | 127 | + * See the COPYING file in the top-level directory. |
266 | + * This program is distributed in the hope that it will be useful, but WITHOUT | 128 | + * |
267 | + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | 129 | + * The STM32L4X5 USART is heavily inspired by the stm32f2xx_usart |
268 | + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | 130 | + * by Alistair Francis. |
269 | + * for more details. | 131 | + * The reference used is the STMicroElectronics RM0351 Reference manual |
132 | + * for STM32L4x5 and STM32L4x6 advanced Arm ® -based 32-bit MCUs. | ||
270 | + */ | 133 | + */ |
271 | + | 134 | + |
272 | +#include "qemu/osdep.h" | 135 | +#include "qemu/osdep.h" |
136 | +#include "qemu/log.h" | ||
137 | +#include "qemu/module.h" | ||
138 | +#include "qapi/error.h" | ||
139 | +#include "chardev/char-fe.h" | ||
140 | +#include "chardev/char-serial.h" | ||
141 | +#include "migration/vmstate.h" | ||
142 | +#include "hw/char/stm32l4x5_usart.h" | ||
143 | +#include "hw/clock.h" | ||
273 | +#include "hw/irq.h" | 144 | +#include "hw/irq.h" |
274 | +#include "hw/qdev-clock.h" | 145 | +#include "hw/qdev-clock.h" |
275 | +#include "hw/qdev-properties.h" | 146 | +#include "hw/qdev-properties.h" |
276 | +#include "hw/misc/npcm7xx_pwm.h" | 147 | +#include "hw/qdev-properties-system.h" |
277 | +#include "hw/registerfields.h" | 148 | +#include "hw/registerfields.h" |
278 | +#include "migration/vmstate.h" | ||
279 | +#include "qemu/bitops.h" | ||
280 | +#include "qemu/error-report.h" | ||
281 | +#include "qemu/log.h" | ||
282 | +#include "qemu/module.h" | ||
283 | +#include "qemu/units.h" | ||
284 | +#include "trace.h" | 149 | +#include "trace.h" |
285 | + | 150 | + |
286 | +REG32(NPCM7XX_PWM_PPR, 0x00); | 151 | + |
287 | +REG32(NPCM7XX_PWM_CSR, 0x04); | 152 | +REG32(CR1, 0x00) |
288 | +REG32(NPCM7XX_PWM_PCR, 0x08); | 153 | + FIELD(CR1, M1, 28, 1) /* Word length (part 2, see M0) */ |
289 | +REG32(NPCM7XX_PWM_CNR0, 0x0c); | 154 | + FIELD(CR1, EOBIE, 27, 1) /* End of Block interrupt enable */ |
290 | +REG32(NPCM7XX_PWM_CMR0, 0x10); | 155 | + FIELD(CR1, RTOIE, 26, 1) /* Receiver timeout interrupt enable */ |
291 | +REG32(NPCM7XX_PWM_PDR0, 0x14); | 156 | + FIELD(CR1, DEAT, 21, 5) /* Driver Enable assertion time */ |
292 | +REG32(NPCM7XX_PWM_CNR1, 0x18); | 157 | + FIELD(CR1, DEDT, 16, 5) /* Driver Enable de-assertion time */ |
293 | +REG32(NPCM7XX_PWM_CMR1, 0x1c); | 158 | + FIELD(CR1, OVER8, 15, 1) /* Oversampling mode */ |
294 | +REG32(NPCM7XX_PWM_PDR1, 0x20); | 159 | + FIELD(CR1, CMIE, 14, 1) /* Character match interrupt enable */ |
295 | +REG32(NPCM7XX_PWM_CNR2, 0x24); | 160 | + FIELD(CR1, MME, 13, 1) /* Mute mode enable */ |
296 | +REG32(NPCM7XX_PWM_CMR2, 0x28); | 161 | + FIELD(CR1, M0, 12, 1) /* Word length (part 1, see M1) */ |
297 | +REG32(NPCM7XX_PWM_PDR2, 0x2c); | 162 | + FIELD(CR1, WAKE, 11, 1) /* Receiver wakeup method */ |
298 | +REG32(NPCM7XX_PWM_CNR3, 0x30); | 163 | + FIELD(CR1, PCE, 10, 1) /* Parity control enable */ |
299 | +REG32(NPCM7XX_PWM_CMR3, 0x34); | 164 | + FIELD(CR1, PS, 9, 1) /* Parity selection */ |
300 | +REG32(NPCM7XX_PWM_PDR3, 0x38); | 165 | + FIELD(CR1, PEIE, 8, 1) /* PE interrupt enable */ |
301 | +REG32(NPCM7XX_PWM_PIER, 0x3c); | 166 | + FIELD(CR1, TXEIE, 7, 1) /* TXE interrupt enable */ |
302 | +REG32(NPCM7XX_PWM_PIIR, 0x40); | 167 | + FIELD(CR1, TCIE, 6, 1) /* Transmission complete interrupt enable */ |
303 | +REG32(NPCM7XX_PWM_PWDR0, 0x44); | 168 | + FIELD(CR1, RXNEIE, 5, 1) /* RXNE interrupt enable */ |
304 | +REG32(NPCM7XX_PWM_PWDR1, 0x48); | 169 | + FIELD(CR1, IDLEIE, 4, 1) /* IDLE interrupt enable */ |
305 | +REG32(NPCM7XX_PWM_PWDR2, 0x4c); | 170 | + FIELD(CR1, TE, 3, 1) /* Transmitter enable */ |
306 | +REG32(NPCM7XX_PWM_PWDR3, 0x50); | 171 | + FIELD(CR1, RE, 2, 1) /* Receiver enable */ |
307 | + | 172 | + FIELD(CR1, UESM, 1, 1) /* USART enable in Stop mode */ |
308 | +/* Register field definitions. */ | 173 | + FIELD(CR1, UE, 0, 1) /* USART enable */ |
309 | +#define NPCM7XX_PPR(rv, index) extract32((rv), npcm7xx_ppr_base[index], 8) | 174 | +REG32(CR2, 0x04) |
310 | +#define NPCM7XX_CSR(rv, index) extract32((rv), npcm7xx_csr_base[index], 3) | 175 | + FIELD(CR2, ADD_1, 28, 4) /* ADD[7:4] */ |
311 | +#define NPCM7XX_CH(rv, index) extract32((rv), npcm7xx_ch_base[index], 4) | 176 | + FIELD(CR2, ADD_0, 24, 1) /* ADD[3:0] */ |
312 | +#define NPCM7XX_CH_EN BIT(0) | 177 | + FIELD(CR2, RTOEN, 23, 1) /* Receiver timeout enable */ |
313 | +#define NPCM7XX_CH_INV BIT(2) | 178 | + FIELD(CR2, ABRMOD, 21, 2) /* Auto baud rate mode */ |
314 | +#define NPCM7XX_CH_MOD BIT(3) | 179 | + FIELD(CR2, ABREN, 20, 1) /* Auto baud rate enable */ |
315 | + | 180 | + FIELD(CR2, MSBFIRST, 19, 1) /* Most significant bit first */ |
316 | +/* Offset of each PWM channel's prescaler in the PPR register. */ | 181 | + FIELD(CR2, DATAINV, 18, 1) /* Binary data inversion */ |
317 | +static const int npcm7xx_ppr_base[] = { 0, 0, 8, 8 }; | 182 | + FIELD(CR2, TXINV, 17, 1) /* TX pin active level inversion */ |
318 | +/* Offset of each PWM channel's clock selector in the CSR register. */ | 183 | + FIELD(CR2, RXINV, 16, 1) /* RX pin active level inversion */ |
319 | +static const int npcm7xx_csr_base[] = { 0, 4, 8, 12 }; | 184 | + FIELD(CR2, SWAP, 15, 1) /* Swap RX/TX pins */ |
320 | +/* Offset of each PWM channel's control variable in the PCR register. */ | 185 | + FIELD(CR2, LINEN, 14, 1) /* LIN mode enable */ |
321 | +static const int npcm7xx_ch_base[] = { 0, 8, 12, 16 }; | 186 | + FIELD(CR2, STOP, 12, 2) /* STOP bits */ |
322 | + | 187 | + FIELD(CR2, CLKEN, 11, 1) /* Clock enable */ |
323 | +static uint32_t npcm7xx_pwm_calculate_freq(NPCM7xxPWM *p) | 188 | + FIELD(CR2, CPOL, 10, 1) /* Clock polarity */ |
324 | +{ | 189 | + FIELD(CR2, CPHA, 9, 1) /* Clock phase */ |
325 | + uint32_t ppr; | 190 | + FIELD(CR2, LBCL, 8, 1) /* Last bit clock pulse */ |
326 | + uint32_t csr; | 191 | + FIELD(CR2, LBDIE, 6, 1) /* LIN break detection interrupt enable */ |
327 | + uint32_t freq; | 192 | + FIELD(CR2, LBDL, 5, 1) /* LIN break detection length */ |
328 | + | 193 | + FIELD(CR2, ADDM7, 4, 1) /* 7-bit / 4-bit Address Detection */ |
329 | + if (!p->running) { | 194 | + |
330 | + return 0; | 195 | +REG32(CR3, 0x08) |
331 | + } | 196 | + /* TCBGTIE only on STM32L496xx/4A6xx devices */ |
332 | + | 197 | + FIELD(CR3, UCESM, 23, 1) /* USART Clock Enable in Stop Mode */ |
333 | + csr = NPCM7XX_CSR(p->module->csr, p->index); | 198 | + FIELD(CR3, WUFIE, 22, 1) /* Wakeup from Stop mode interrupt enable */ |
334 | + ppr = NPCM7XX_PPR(p->module->ppr, p->index); | 199 | + FIELD(CR3, WUS, 20, 2) /* Wakeup from Stop mode interrupt flag selection */ |
335 | + freq = clock_get_hz(p->module->clock); | 200 | + FIELD(CR3, SCARCNT, 17, 3) /* Smartcard auto-retry count */ |
336 | + freq /= ppr + 1; | 201 | + FIELD(CR3, DEP, 15, 1) /* Driver enable polarity selection */ |
337 | + /* csr can only be 0~4 */ | 202 | + FIELD(CR3, DEM, 14, 1) /* Driver enable mode */ |
338 | + if (csr > 4) { | 203 | + FIELD(CR3, DDRE, 13, 1) /* DMA Disable on Reception Error */ |
339 | + qemu_log_mask(LOG_GUEST_ERROR, | 204 | + FIELD(CR3, OVRDIS, 12, 1) /* Overrun Disable */ |
340 | + "%s: invalid csr value %u\n", | 205 | + FIELD(CR3, ONEBIT, 11, 1) /* One sample bit method enable */ |
341 | + __func__, csr); | 206 | + FIELD(CR3, CTSIE, 10, 1) /* CTS interrupt enable */ |
342 | + csr = 4; | 207 | + FIELD(CR3, CTSE, 9, 1) /* CTS enable */ |
343 | + } | 208 | + FIELD(CR3, RTSE, 8, 1) /* RTS enable */ |
344 | + /* freq won't be changed if csr == 4. */ | 209 | + FIELD(CR3, DMAT, 7, 1) /* DMA enable transmitter */ |
345 | + if (csr < 4) { | 210 | + FIELD(CR3, DMAR, 6, 1) /* DMA enable receiver */ |
346 | + freq >>= csr + 1; | 211 | + FIELD(CR3, SCEN, 5, 1) /* Smartcard mode enable */ |
347 | + } | 212 | + FIELD(CR3, NACK, 4, 1) /* Smartcard NACK enable */ |
348 | + | 213 | + FIELD(CR3, HDSEL, 3, 1) /* Half-duplex selection */ |
349 | + return freq / (p->cnr + 1); | 214 | + FIELD(CR3, IRLP, 2, 1) /* IrDA low-power */ |
350 | +} | 215 | + FIELD(CR3, IREN, 1, 1) /* IrDA mode enable */ |
351 | + | 216 | + FIELD(CR3, EIE, 0, 1) /* Error interrupt enable */ |
352 | +static uint32_t npcm7xx_pwm_calculate_duty(NPCM7xxPWM *p) | 217 | +REG32(BRR, 0x0C) |
353 | +{ | 218 | + FIELD(BRR, BRR, 0, 16) |
354 | + uint64_t duty; | 219 | +REG32(GTPR, 0x10) |
355 | + | 220 | + FIELD(GTPR, GT, 8, 8) /* Guard time value */ |
356 | + if (p->running) { | 221 | + FIELD(GTPR, PSC, 0, 8) /* Prescaler value */ |
357 | + if (p->cnr == 0) { | 222 | +REG32(RTOR, 0x14) |
358 | + duty = 0; | 223 | + FIELD(RTOR, BLEN, 24, 8) /* Block Length */ |
359 | + } else if (p->cmr >= p->cnr) { | 224 | + FIELD(RTOR, RTO, 0, 24) /* Receiver timeout value */ |
360 | + duty = NPCM7XX_PWM_MAX_DUTY; | 225 | +REG32(RQR, 0x18) |
361 | + } else { | 226 | + FIELD(RQR, TXFRQ, 4, 1) /* Transmit data flush request */ |
362 | + duty = NPCM7XX_PWM_MAX_DUTY * (p->cmr + 1) / (p->cnr + 1); | 227 | + FIELD(RQR, RXFRQ, 3, 1) /* Receive data flush request */ |
363 | + } | 228 | + FIELD(RQR, MMRQ, 2, 1) /* Mute mode request */ |
364 | + } else { | 229 | + FIELD(RQR, SBKRQ, 1, 1) /* Send break request */ |
365 | + duty = 0; | 230 | + FIELD(RQR, ABBRRQ, 0, 1) /* Auto baud rate request */ |
366 | + } | 231 | +REG32(ISR, 0x1C) |
367 | + | 232 | + /* TCBGT only for STM32L475xx/476xx/486xx devices */ |
368 | + if (p->inverted) { | 233 | + FIELD(ISR, REACK, 22, 1) /* Receive enable acknowledge flag */ |
369 | + duty = NPCM7XX_PWM_MAX_DUTY - duty; | 234 | + FIELD(ISR, TEACK, 21, 1) /* Transmit enable acknowledge flag */ |
370 | + } | 235 | + FIELD(ISR, WUF, 20, 1) /* Wakeup from Stop mode flag */ |
371 | + | 236 | + FIELD(ISR, RWU, 19, 1) /* Receiver wakeup from Mute mode */ |
372 | + return duty; | 237 | + FIELD(ISR, SBKF, 18, 1) /* Send break flag */ |
373 | +} | 238 | + FIELD(ISR, CMF, 17, 1) /* Character match flag */ |
374 | + | 239 | + FIELD(ISR, BUSY, 16, 1) /* Busy flag */ |
375 | +static void npcm7xx_pwm_update_freq(NPCM7xxPWM *p) | 240 | + FIELD(ISR, ABRF, 15, 1) /* Auto Baud rate flag */ |
376 | +{ | 241 | + FIELD(ISR, ABRE, 14, 1) /* Auto Baud rate error */ |
377 | + uint32_t freq = npcm7xx_pwm_calculate_freq(p); | 242 | + FIELD(ISR, EOBF, 12, 1) /* End of block flag */ |
378 | + | 243 | + FIELD(ISR, RTOF, 11, 1) /* Receiver timeout */ |
379 | + if (freq != p->freq) { | 244 | + FIELD(ISR, CTS, 10, 1) /* CTS flag */ |
380 | + trace_npcm7xx_pwm_update_freq(DEVICE(p->module)->canonical_path, | 245 | + FIELD(ISR, CTSIF, 9, 1) /* CTS interrupt flag */ |
381 | + p->index, p->freq, freq); | 246 | + FIELD(ISR, LBDF, 8, 1) /* LIN break detection flag */ |
382 | + p->freq = freq; | 247 | + FIELD(ISR, TXE, 7, 1) /* Transmit data register empty */ |
383 | + } | 248 | + FIELD(ISR, TC, 6, 1) /* Transmission complete */ |
384 | +} | 249 | + FIELD(ISR, RXNE, 5, 1) /* Read data register not empty */ |
385 | + | 250 | + FIELD(ISR, IDLE, 4, 1) /* Idle line detected */ |
386 | +static void npcm7xx_pwm_update_duty(NPCM7xxPWM *p) | 251 | + FIELD(ISR, ORE, 3, 1) /* Overrun error */ |
387 | +{ | 252 | + FIELD(ISR, NF, 2, 1) /* START bit Noise detection flag */ |
388 | + uint32_t duty = npcm7xx_pwm_calculate_duty(p); | 253 | + FIELD(ISR, FE, 1, 1) /* Framing Error */ |
389 | + | 254 | + FIELD(ISR, PE, 0, 1) /* Parity Error */ |
390 | + if (duty != p->duty) { | 255 | +REG32(ICR, 0x20) |
391 | + trace_npcm7xx_pwm_update_duty(DEVICE(p->module)->canonical_path, | 256 | + FIELD(ICR, WUCF, 20, 1) /* Wakeup from Stop mode clear flag */ |
392 | + p->index, p->duty, duty); | 257 | + FIELD(ICR, CMCF, 17, 1) /* Character match clear flag */ |
393 | + p->duty = duty; | 258 | + FIELD(ICR, EOBCF, 12, 1) /* End of block clear flag */ |
394 | + } | 259 | + FIELD(ICR, RTOCF, 11, 1) /* Receiver timeout clear flag */ |
395 | +} | 260 | + FIELD(ICR, CTSCF, 9, 1) /* CTS clear flag */ |
396 | + | 261 | + FIELD(ICR, LBDCF, 8, 1) /* LIN break detection clear flag */ |
397 | +static void npcm7xx_pwm_update_output(NPCM7xxPWM *p) | 262 | + /* TCBGTCF only on STM32L496xx/4A6xx devices */ |
398 | +{ | 263 | + FIELD(ICR, TCCF, 6, 1) /* Transmission complete clear flag */ |
399 | + npcm7xx_pwm_update_freq(p); | 264 | + FIELD(ICR, IDLECF, 4, 1) /* Idle line detected clear flag */ |
400 | + npcm7xx_pwm_update_duty(p); | 265 | + FIELD(ICR, ORECF, 3, 1) /* Overrun error clear flag */ |
401 | +} | 266 | + FIELD(ICR, NCF, 2, 1) /* Noise detected clear flag */ |
402 | + | 267 | + FIELD(ICR, FECF, 1, 1) /* Framing error clear flag */ |
403 | +static void npcm7xx_pwm_write_ppr(NPCM7xxPWMState *s, uint32_t new_ppr) | 268 | + FIELD(ICR, PECF, 0, 1) /* Parity error clear flag */ |
404 | +{ | 269 | +REG32(RDR, 0x24) |
405 | + int i; | 270 | + FIELD(RDR, RDR, 0, 9) |
406 | + uint32_t old_ppr = s->ppr; | 271 | +REG32(TDR, 0x28) |
407 | + | 272 | + FIELD(TDR, TDR, 0, 9) |
408 | + QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_ppr_base) != NPCM7XX_PWM_PER_MODULE); | 273 | + |
409 | + s->ppr = new_ppr; | 274 | +static void stm32l4x5_usart_base_reset_hold(Object *obj, ResetType type) |
410 | + for (i = 0; i < NPCM7XX_PWM_PER_MODULE; ++i) { | 275 | +{ |
411 | + if (NPCM7XX_PPR(old_ppr, i) != NPCM7XX_PPR(new_ppr, i)) { | 276 | + Stm32l4x5UsartBaseState *s = STM32L4X5_USART_BASE(obj); |
412 | + npcm7xx_pwm_update_freq(&s->pwm[i]); | 277 | + |
413 | + } | 278 | + s->cr1 = 0x00000000; |
414 | + } | 279 | + s->cr2 = 0x00000000; |
415 | +} | 280 | + s->cr3 = 0x00000000; |
416 | + | 281 | + s->brr = 0x00000000; |
417 | +static void npcm7xx_pwm_write_csr(NPCM7xxPWMState *s, uint32_t new_csr) | 282 | + s->gtpr = 0x00000000; |
418 | +{ | 283 | + s->rtor = 0x00000000; |
419 | + int i; | 284 | + s->isr = 0x020000C0; |
420 | + uint32_t old_csr = s->csr; | 285 | + s->rdr = 0x00000000; |
421 | + | 286 | + s->tdr = 0x00000000; |
422 | + QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_csr_base) != NPCM7XX_PWM_PER_MODULE); | 287 | +} |
423 | + s->csr = new_csr; | 288 | + |
424 | + for (i = 0; i < NPCM7XX_PWM_PER_MODULE; ++i) { | 289 | +static uint64_t stm32l4x5_usart_base_read(void *opaque, hwaddr addr, |
425 | + if (NPCM7XX_CSR(old_csr, i) != NPCM7XX_CSR(new_csr, i)) { | 290 | + unsigned int size) |
426 | + npcm7xx_pwm_update_freq(&s->pwm[i]); | 291 | +{ |
427 | + } | 292 | + Stm32l4x5UsartBaseState *s = opaque; |
428 | + } | 293 | + uint64_t retvalue = 0; |
429 | +} | 294 | + |
430 | + | 295 | + switch (addr) { |
431 | +static void npcm7xx_pwm_write_pcr(NPCM7xxPWMState *s, uint32_t new_pcr) | 296 | + case A_CR1: |
432 | +{ | 297 | + retvalue = s->cr1; |
433 | + int i; | 298 | + break; |
434 | + bool inverted; | 299 | + case A_CR2: |
435 | + uint32_t pcr; | 300 | + retvalue = s->cr2; |
436 | + NPCM7xxPWM *p; | 301 | + break; |
437 | + | 302 | + case A_CR3: |
438 | + s->pcr = new_pcr; | 303 | + retvalue = s->cr3; |
439 | + QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_ch_base) != NPCM7XX_PWM_PER_MODULE); | 304 | + break; |
440 | + for (i = 0; i < NPCM7XX_PWM_PER_MODULE; ++i) { | 305 | + case A_BRR: |
441 | + p = &s->pwm[i]; | 306 | + retvalue = FIELD_EX32(s->brr, BRR, BRR); |
442 | + pcr = NPCM7XX_CH(new_pcr, i); | 307 | + break; |
443 | + inverted = pcr & NPCM7XX_CH_INV; | 308 | + case A_GTPR: |
444 | + | 309 | + retvalue = s->gtpr; |
445 | + /* | 310 | + break; |
446 | + * We only run a PWM channel with toggle mode. Single-shot mode does not | 311 | + case A_RTOR: |
447 | + * generate frequency and duty-cycle values. | 312 | + retvalue = s->rtor; |
448 | + */ | 313 | + break; |
449 | + if ((pcr & NPCM7XX_CH_EN) && (pcr & NPCM7XX_CH_MOD)) { | 314 | + case A_RQR: |
450 | + if (p->running) { | 315 | + /* RQR is a write only register */ |
451 | + /* Re-run this PWM channel if inverted changed. */ | 316 | + retvalue = 0x00000000; |
452 | + if (p->inverted ^ inverted) { | 317 | + break; |
453 | + p->inverted = inverted; | 318 | + case A_ISR: |
454 | + npcm7xx_pwm_update_duty(p); | 319 | + retvalue = s->isr; |
455 | + } | 320 | + break; |
456 | + } else { | 321 | + case A_ICR: |
457 | + /* Run this PWM channel. */ | 322 | + /* ICR is a clear register */ |
458 | + p->running = true; | 323 | + retvalue = 0x00000000; |
459 | + p->inverted = inverted; | 324 | + break; |
460 | + npcm7xx_pwm_update_output(p); | 325 | + case A_RDR: |
461 | + } | 326 | + retvalue = FIELD_EX32(s->rdr, RDR, RDR); |
462 | + } else { | 327 | + /* Reset RXNE flag */ |
463 | + /* Clear this PWM channel. */ | 328 | + s->isr &= ~R_ISR_RXNE_MASK; |
464 | + p->running = false; | 329 | + break; |
465 | + p->inverted = inverted; | 330 | + case A_TDR: |
466 | + npcm7xx_pwm_update_output(p); | 331 | + retvalue = FIELD_EX32(s->tdr, TDR, TDR); |
467 | + } | 332 | + break; |
468 | + } | ||
469 | + | ||
470 | +} | ||
471 | + | ||
472 | +static hwaddr npcm7xx_cnr_index(hwaddr offset) | ||
473 | +{ | ||
474 | + switch (offset) { | ||
475 | + case A_NPCM7XX_PWM_CNR0: | ||
476 | + return 0; | ||
477 | + case A_NPCM7XX_PWM_CNR1: | ||
478 | + return 1; | ||
479 | + case A_NPCM7XX_PWM_CNR2: | ||
480 | + return 2; | ||
481 | + case A_NPCM7XX_PWM_CNR3: | ||
482 | + return 3; | ||
483 | + default: | ||
484 | + g_assert_not_reached(); | ||
485 | + } | ||
486 | +} | ||
487 | + | ||
488 | +static hwaddr npcm7xx_cmr_index(hwaddr offset) | ||
489 | +{ | ||
490 | + switch (offset) { | ||
491 | + case A_NPCM7XX_PWM_CMR0: | ||
492 | + return 0; | ||
493 | + case A_NPCM7XX_PWM_CMR1: | ||
494 | + return 1; | ||
495 | + case A_NPCM7XX_PWM_CMR2: | ||
496 | + return 2; | ||
497 | + case A_NPCM7XX_PWM_CMR3: | ||
498 | + return 3; | ||
499 | + default: | ||
500 | + g_assert_not_reached(); | ||
501 | + } | ||
502 | +} | ||
503 | + | ||
504 | +static hwaddr npcm7xx_pdr_index(hwaddr offset) | ||
505 | +{ | ||
506 | + switch (offset) { | ||
507 | + case A_NPCM7XX_PWM_PDR0: | ||
508 | + return 0; | ||
509 | + case A_NPCM7XX_PWM_PDR1: | ||
510 | + return 1; | ||
511 | + case A_NPCM7XX_PWM_PDR2: | ||
512 | + return 2; | ||
513 | + case A_NPCM7XX_PWM_PDR3: | ||
514 | + return 3; | ||
515 | + default: | ||
516 | + g_assert_not_reached(); | ||
517 | + } | ||
518 | +} | ||
519 | + | ||
520 | +static hwaddr npcm7xx_pwdr_index(hwaddr offset) | ||
521 | +{ | ||
522 | + switch (offset) { | ||
523 | + case A_NPCM7XX_PWM_PWDR0: | ||
524 | + return 0; | ||
525 | + case A_NPCM7XX_PWM_PWDR1: | ||
526 | + return 1; | ||
527 | + case A_NPCM7XX_PWM_PWDR2: | ||
528 | + return 2; | ||
529 | + case A_NPCM7XX_PWM_PWDR3: | ||
530 | + return 3; | ||
531 | + default: | ||
532 | + g_assert_not_reached(); | ||
533 | + } | ||
534 | +} | ||
535 | + | ||
536 | +static uint64_t npcm7xx_pwm_read(void *opaque, hwaddr offset, unsigned size) | ||
537 | +{ | ||
538 | + NPCM7xxPWMState *s = opaque; | ||
539 | + uint64_t value = 0; | ||
540 | + | ||
541 | + switch (offset) { | ||
542 | + case A_NPCM7XX_PWM_CNR0: | ||
543 | + case A_NPCM7XX_PWM_CNR1: | ||
544 | + case A_NPCM7XX_PWM_CNR2: | ||
545 | + case A_NPCM7XX_PWM_CNR3: | ||
546 | + value = s->pwm[npcm7xx_cnr_index(offset)].cnr; | ||
547 | + break; | ||
548 | + | ||
549 | + case A_NPCM7XX_PWM_CMR0: | ||
550 | + case A_NPCM7XX_PWM_CMR1: | ||
551 | + case A_NPCM7XX_PWM_CMR2: | ||
552 | + case A_NPCM7XX_PWM_CMR3: | ||
553 | + value = s->pwm[npcm7xx_cmr_index(offset)].cmr; | ||
554 | + break; | ||
555 | + | ||
556 | + case A_NPCM7XX_PWM_PDR0: | ||
557 | + case A_NPCM7XX_PWM_PDR1: | ||
558 | + case A_NPCM7XX_PWM_PDR2: | ||
559 | + case A_NPCM7XX_PWM_PDR3: | ||
560 | + value = s->pwm[npcm7xx_pdr_index(offset)].pdr; | ||
561 | + break; | ||
562 | + | ||
563 | + case A_NPCM7XX_PWM_PWDR0: | ||
564 | + case A_NPCM7XX_PWM_PWDR1: | ||
565 | + case A_NPCM7XX_PWM_PWDR2: | ||
566 | + case A_NPCM7XX_PWM_PWDR3: | ||
567 | + value = s->pwm[npcm7xx_pwdr_index(offset)].pwdr; | ||
568 | + break; | ||
569 | + | ||
570 | + case A_NPCM7XX_PWM_PPR: | ||
571 | + value = s->ppr; | ||
572 | + break; | ||
573 | + | ||
574 | + case A_NPCM7XX_PWM_CSR: | ||
575 | + value = s->csr; | ||
576 | + break; | ||
577 | + | ||
578 | + case A_NPCM7XX_PWM_PCR: | ||
579 | + value = s->pcr; | ||
580 | + break; | ||
581 | + | ||
582 | + case A_NPCM7XX_PWM_PIER: | ||
583 | + value = s->pier; | ||
584 | + break; | ||
585 | + | ||
586 | + case A_NPCM7XX_PWM_PIIR: | ||
587 | + value = s->piir; | ||
588 | + break; | ||
589 | + | ||
590 | + default: | 333 | + default: |
591 | + qemu_log_mask(LOG_GUEST_ERROR, | 334 | + qemu_log_mask(LOG_GUEST_ERROR, |
592 | + "%s: invalid offset 0x%04" HWADDR_PRIx "\n", | 335 | + "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr); |
593 | + __func__, offset); | ||
594 | + break; | 336 | + break; |
595 | + } | 337 | + } |
596 | + | 338 | + |
597 | + trace_npcm7xx_pwm_read(DEVICE(s)->canonical_path, offset, value); | 339 | + trace_stm32l4x5_usart_read(addr, retvalue); |
598 | + return value; | 340 | + |
599 | +} | 341 | + return retvalue; |
600 | + | 342 | +} |
601 | +static void npcm7xx_pwm_write(void *opaque, hwaddr offset, | 343 | + |
602 | + uint64_t v, unsigned size) | 344 | +static void stm32l4x5_usart_base_write(void *opaque, hwaddr addr, |
603 | +{ | 345 | + uint64_t val64, unsigned int size) |
604 | + NPCM7xxPWMState *s = opaque; | 346 | +{ |
605 | + NPCM7xxPWM *p; | 347 | + Stm32l4x5UsartBaseState *s = opaque; |
606 | + uint32_t value = v; | 348 | + const uint32_t value = val64; |
607 | + | 349 | + |
608 | + trace_npcm7xx_pwm_write(DEVICE(s)->canonical_path, offset, value); | 350 | + trace_stm32l4x5_usart_write(addr, value); |
609 | + switch (offset) { | 351 | + |
610 | + case A_NPCM7XX_PWM_CNR0: | 352 | + switch (addr) { |
611 | + case A_NPCM7XX_PWM_CNR1: | 353 | + case A_CR1: |
612 | + case A_NPCM7XX_PWM_CNR2: | 354 | + s->cr1 = value; |
613 | + case A_NPCM7XX_PWM_CNR3: | 355 | + return; |
614 | + p = &s->pwm[npcm7xx_cnr_index(offset)]; | 356 | + case A_CR2: |
615 | + p->cnr = value; | 357 | + s->cr2 = value; |
616 | + npcm7xx_pwm_update_output(p); | 358 | + return; |
617 | + break; | 359 | + case A_CR3: |
618 | + | 360 | + s->cr3 = value; |
619 | + case A_NPCM7XX_PWM_CMR0: | 361 | + return; |
620 | + case A_NPCM7XX_PWM_CMR1: | 362 | + case A_BRR: |
621 | + case A_NPCM7XX_PWM_CMR2: | 363 | + s->brr = value; |
622 | + case A_NPCM7XX_PWM_CMR3: | 364 | + return; |
623 | + p = &s->pwm[npcm7xx_cmr_index(offset)]; | 365 | + case A_GTPR: |
624 | + p->cmr = value; | 366 | + s->gtpr = value; |
625 | + npcm7xx_pwm_update_output(p); | 367 | + return; |
626 | + break; | 368 | + case A_RTOR: |
627 | + | 369 | + s->rtor = value; |
628 | + case A_NPCM7XX_PWM_PDR0: | 370 | + return; |
629 | + case A_NPCM7XX_PWM_PDR1: | 371 | + case A_RQR: |
630 | + case A_NPCM7XX_PWM_PDR2: | 372 | + return; |
631 | + case A_NPCM7XX_PWM_PDR3: | 373 | + case A_ISR: |
632 | + qemu_log_mask(LOG_GUEST_ERROR, | 374 | + qemu_log_mask(LOG_GUEST_ERROR, |
633 | + "%s: register @ 0x%04" HWADDR_PRIx " is read-only\n", | 375 | + "%s: ISR is read only !\n", __func__); |
634 | + __func__, offset); | 376 | + return; |
635 | + break; | 377 | + case A_ICR: |
636 | + | 378 | + /* Clear the status flags */ |
637 | + case A_NPCM7XX_PWM_PWDR0: | 379 | + s->isr &= ~value; |
638 | + case A_NPCM7XX_PWM_PWDR1: | 380 | + return; |
639 | + case A_NPCM7XX_PWM_PWDR2: | 381 | + case A_RDR: |
640 | + case A_NPCM7XX_PWM_PWDR3: | 382 | + qemu_log_mask(LOG_GUEST_ERROR, |
641 | + qemu_log_mask(LOG_UNIMP, | 383 | + "%s: RDR is read only !\n", __func__); |
642 | + "%s: register @ 0x%04" HWADDR_PRIx " is not implemented\n", | 384 | + return; |
643 | + __func__, offset); | 385 | + case A_TDR: |
644 | + break; | 386 | + s->tdr = value; |
645 | + | 387 | + return; |
646 | + case A_NPCM7XX_PWM_PPR: | ||
647 | + npcm7xx_pwm_write_ppr(s, value); | ||
648 | + break; | ||
649 | + | ||
650 | + case A_NPCM7XX_PWM_CSR: | ||
651 | + npcm7xx_pwm_write_csr(s, value); | ||
652 | + break; | ||
653 | + | ||
654 | + case A_NPCM7XX_PWM_PCR: | ||
655 | + npcm7xx_pwm_write_pcr(s, value); | ||
656 | + break; | ||
657 | + | ||
658 | + case A_NPCM7XX_PWM_PIER: | ||
659 | + qemu_log_mask(LOG_UNIMP, | ||
660 | + "%s: register @ 0x%04" HWADDR_PRIx " is not implemented\n", | ||
661 | + __func__, offset); | ||
662 | + break; | ||
663 | + | ||
664 | + case A_NPCM7XX_PWM_PIIR: | ||
665 | + qemu_log_mask(LOG_UNIMP, | ||
666 | + "%s: register @ 0x%04" HWADDR_PRIx " is not implemented\n", | ||
667 | + __func__, offset); | ||
668 | + break; | ||
669 | + | ||
670 | + default: | 388 | + default: |
671 | + qemu_log_mask(LOG_GUEST_ERROR, | 389 | + qemu_log_mask(LOG_GUEST_ERROR, |
672 | + "%s: invalid offset 0x%04" HWADDR_PRIx "\n", | 390 | + "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr); |
673 | + __func__, offset); | ||
674 | + break; | ||
675 | + } | 391 | + } |
676 | +} | 392 | +} |
677 | + | 393 | + |
678 | +static const struct MemoryRegionOps npcm7xx_pwm_ops = { | 394 | +static const MemoryRegionOps stm32l4x5_usart_base_ops = { |
679 | + .read = npcm7xx_pwm_read, | 395 | + .read = stm32l4x5_usart_base_read, |
680 | + .write = npcm7xx_pwm_write, | 396 | + .write = stm32l4x5_usart_base_write, |
681 | + .endianness = DEVICE_LITTLE_ENDIAN, | 397 | + .endianness = DEVICE_NATIVE_ENDIAN, |
682 | + .valid = { | 398 | + .valid = { |
683 | + .min_access_size = 4, | 399 | + .max_access_size = 4, |
684 | + .max_access_size = 4, | 400 | + .min_access_size = 4, |
685 | + .unaligned = false, | 401 | + .unaligned = false |
402 | + }, | ||
403 | + .impl = { | ||
404 | + .max_access_size = 4, | ||
405 | + .min_access_size = 4, | ||
406 | + .unaligned = false | ||
686 | + }, | 407 | + }, |
687 | +}; | 408 | +}; |
688 | + | 409 | + |
689 | +static void npcm7xx_pwm_enter_reset(Object *obj, ResetType type) | 410 | +static Property stm32l4x5_usart_base_properties[] = { |
690 | +{ | 411 | + DEFINE_PROP_CHR("chardev", Stm32l4x5UsartBaseState, chr), |
691 | + NPCM7xxPWMState *s = NPCM7XX_PWM(obj); | 412 | + DEFINE_PROP_END_OF_LIST(), |
692 | + int i; | 413 | +}; |
693 | + | 414 | + |
694 | + for (i = 0; i < NPCM7XX_PWM_PER_MODULE; i++) { | 415 | +static void stm32l4x5_usart_base_init(Object *obj) |
695 | + NPCM7xxPWM *p = &s->pwm[i]; | 416 | +{ |
696 | + | 417 | + Stm32l4x5UsartBaseState *s = STM32L4X5_USART_BASE(obj); |
697 | + p->cnr = 0x00000000; | 418 | + |
698 | + p->cmr = 0x00000000; | 419 | + sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq); |
699 | + p->pdr = 0x00000000; | 420 | + |
700 | + p->pwdr = 0x00000000; | 421 | + memory_region_init_io(&s->mmio, obj, &stm32l4x5_usart_base_ops, s, |
422 | + TYPE_STM32L4X5_USART_BASE, 0x400); | ||
423 | + sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); | ||
424 | + | ||
425 | + s->clk = qdev_init_clock_in(DEVICE(s), "clk", NULL, s, 0); | ||
426 | +} | ||
427 | + | ||
428 | +static const VMStateDescription vmstate_stm32l4x5_usart_base = { | ||
429 | + .name = TYPE_STM32L4X5_USART_BASE, | ||
430 | + .version_id = 1, | ||
431 | + .minimum_version_id = 1, | ||
432 | + .fields = (VMStateField[]) { | ||
433 | + VMSTATE_UINT32(cr1, Stm32l4x5UsartBaseState), | ||
434 | + VMSTATE_UINT32(cr2, Stm32l4x5UsartBaseState), | ||
435 | + VMSTATE_UINT32(cr3, Stm32l4x5UsartBaseState), | ||
436 | + VMSTATE_UINT32(brr, Stm32l4x5UsartBaseState), | ||
437 | + VMSTATE_UINT32(gtpr, Stm32l4x5UsartBaseState), | ||
438 | + VMSTATE_UINT32(rtor, Stm32l4x5UsartBaseState), | ||
439 | + VMSTATE_UINT32(isr, Stm32l4x5UsartBaseState), | ||
440 | + VMSTATE_UINT32(rdr, Stm32l4x5UsartBaseState), | ||
441 | + VMSTATE_UINT32(tdr, Stm32l4x5UsartBaseState), | ||
442 | + VMSTATE_CLOCK(clk, Stm32l4x5UsartBaseState), | ||
443 | + VMSTATE_END_OF_LIST() | ||
701 | + } | 444 | + } |
702 | + | 445 | +}; |
703 | + s->ppr = 0x00000000; | 446 | + |
704 | + s->csr = 0x00000000; | 447 | + |
705 | + s->pcr = 0x00000000; | 448 | +static void stm32l4x5_usart_base_realize(DeviceState *dev, Error **errp) |
706 | + s->pier = 0x00000000; | 449 | +{ |
707 | + s->piir = 0x00000000; | 450 | + ERRP_GUARD(); |
708 | +} | 451 | + Stm32l4x5UsartBaseState *s = STM32L4X5_USART_BASE(dev); |
709 | + | 452 | + if (!clock_has_source(s->clk)) { |
710 | +static void npcm7xx_pwm_hold_reset(Object *obj) | 453 | + error_setg(errp, "USART clock must be wired up by SoC code"); |
711 | +{ | 454 | + return; |
712 | + NPCM7xxPWMState *s = NPCM7XX_PWM(obj); | ||
713 | + int i; | ||
714 | + | ||
715 | + for (i = 0; i < NPCM7XX_PWM_PER_MODULE; i++) { | ||
716 | + qemu_irq_lower(s->pwm[i].irq); | ||
717 | + } | 455 | + } |
718 | +} | 456 | +} |
719 | + | 457 | + |
720 | +static void npcm7xx_pwm_init(Object *obj) | 458 | +static void stm32l4x5_usart_base_class_init(ObjectClass *klass, void *data) |
721 | +{ | 459 | +{ |
722 | + NPCM7xxPWMState *s = NPCM7XX_PWM(obj); | 460 | + DeviceClass *dc = DEVICE_CLASS(klass); |
723 | + SysBusDevice *sbd = SYS_BUS_DEVICE(obj); | 461 | + ResettableClass *rc = RESETTABLE_CLASS(klass); |
724 | + int i; | 462 | + |
725 | + | 463 | + rc->phases.hold = stm32l4x5_usart_base_reset_hold; |
726 | + for (i = 0; i < NPCM7XX_PWM_PER_MODULE; i++) { | 464 | + device_class_set_props(dc, stm32l4x5_usart_base_properties); |
727 | + NPCM7xxPWM *p = &s->pwm[i]; | 465 | + dc->realize = stm32l4x5_usart_base_realize; |
728 | + p->module = s; | 466 | + dc->vmsd = &vmstate_stm32l4x5_usart_base; |
729 | + p->index = i; | 467 | +} |
730 | + sysbus_init_irq(sbd, &p->irq); | 468 | + |
469 | +static void stm32l4x5_usart_class_init(ObjectClass *oc, void *data) | ||
470 | +{ | ||
471 | + Stm32l4x5UsartBaseClass *subc = STM32L4X5_USART_BASE_CLASS(oc); | ||
472 | + | ||
473 | + subc->type = STM32L4x5_USART; | ||
474 | +} | ||
475 | + | ||
476 | +static void stm32l4x5_uart_class_init(ObjectClass *oc, void *data) | ||
477 | +{ | ||
478 | + Stm32l4x5UsartBaseClass *subc = STM32L4X5_USART_BASE_CLASS(oc); | ||
479 | + | ||
480 | + subc->type = STM32L4x5_UART; | ||
481 | +} | ||
482 | + | ||
483 | +static void stm32l4x5_lpuart_class_init(ObjectClass *oc, void *data) | ||
484 | +{ | ||
485 | + Stm32l4x5UsartBaseClass *subc = STM32L4X5_USART_BASE_CLASS(oc); | ||
486 | + | ||
487 | + subc->type = STM32L4x5_LPUART; | ||
488 | +} | ||
489 | + | ||
490 | +static const TypeInfo stm32l4x5_usart_types[] = { | ||
491 | + { | ||
492 | + .name = TYPE_STM32L4X5_USART_BASE, | ||
493 | + .parent = TYPE_SYS_BUS_DEVICE, | ||
494 | + .instance_size = sizeof(Stm32l4x5UsartBaseState), | ||
495 | + .instance_init = stm32l4x5_usart_base_init, | ||
496 | + .class_init = stm32l4x5_usart_base_class_init, | ||
497 | + .abstract = true, | ||
498 | + }, { | ||
499 | + .name = TYPE_STM32L4X5_USART, | ||
500 | + .parent = TYPE_STM32L4X5_USART_BASE, | ||
501 | + .class_init = stm32l4x5_usart_class_init, | ||
502 | + }, { | ||
503 | + .name = TYPE_STM32L4X5_UART, | ||
504 | + .parent = TYPE_STM32L4X5_USART_BASE, | ||
505 | + .class_init = stm32l4x5_uart_class_init, | ||
506 | + }, { | ||
507 | + .name = TYPE_STM32L4X5_LPUART, | ||
508 | + .parent = TYPE_STM32L4X5_USART_BASE, | ||
509 | + .class_init = stm32l4x5_lpuart_class_init, | ||
731 | + } | 510 | + } |
732 | + | ||
733 | + memory_region_init_io(&s->iomem, obj, &npcm7xx_pwm_ops, s, | ||
734 | + TYPE_NPCM7XX_PWM, 4 * KiB); | ||
735 | + sysbus_init_mmio(sbd, &s->iomem); | ||
736 | + s->clock = qdev_init_clock_in(DEVICE(s), "clock", NULL, NULL); | ||
737 | + | ||
738 | + for (i = 0; i < NPCM7XX_PWM_PER_MODULE; ++i) { | ||
739 | + object_property_add_uint32_ptr(obj, "freq[*]", | ||
740 | + &s->pwm[i].freq, OBJ_PROP_FLAG_READ); | ||
741 | + object_property_add_uint32_ptr(obj, "duty[*]", | ||
742 | + &s->pwm[i].duty, OBJ_PROP_FLAG_READ); | ||
743 | + } | ||
744 | +} | ||
745 | + | ||
746 | +static const VMStateDescription vmstate_npcm7xx_pwm = { | ||
747 | + .name = "npcm7xx-pwm", | ||
748 | + .version_id = 0, | ||
749 | + .minimum_version_id = 0, | ||
750 | + .fields = (VMStateField[]) { | ||
751 | + VMSTATE_BOOL(running, NPCM7xxPWM), | ||
752 | + VMSTATE_BOOL(inverted, NPCM7xxPWM), | ||
753 | + VMSTATE_UINT8(index, NPCM7xxPWM), | ||
754 | + VMSTATE_UINT32(cnr, NPCM7xxPWM), | ||
755 | + VMSTATE_UINT32(cmr, NPCM7xxPWM), | ||
756 | + VMSTATE_UINT32(pdr, NPCM7xxPWM), | ||
757 | + VMSTATE_UINT32(pwdr, NPCM7xxPWM), | ||
758 | + VMSTATE_UINT32(freq, NPCM7xxPWM), | ||
759 | + VMSTATE_UINT32(duty, NPCM7xxPWM), | ||
760 | + VMSTATE_END_OF_LIST(), | ||
761 | + }, | ||
762 | +}; | 511 | +}; |
763 | + | 512 | + |
764 | +static const VMStateDescription vmstate_npcm7xx_pwm_module = { | 513 | +DEFINE_TYPES(stm32l4x5_usart_types) |
765 | + .name = "npcm7xx-pwm-module", | 514 | diff --git a/hw/char/Kconfig b/hw/char/Kconfig |
766 | + .version_id = 0, | ||
767 | + .minimum_version_id = 0, | ||
768 | + .fields = (VMStateField[]) { | ||
769 | + VMSTATE_CLOCK(clock, NPCM7xxPWMState), | ||
770 | + VMSTATE_STRUCT_ARRAY(pwm, NPCM7xxPWMState, | ||
771 | + NPCM7XX_PWM_PER_MODULE, 0, vmstate_npcm7xx_pwm, | ||
772 | + NPCM7xxPWM), | ||
773 | + VMSTATE_UINT32(ppr, NPCM7xxPWMState), | ||
774 | + VMSTATE_UINT32(csr, NPCM7xxPWMState), | ||
775 | + VMSTATE_UINT32(pcr, NPCM7xxPWMState), | ||
776 | + VMSTATE_UINT32(pier, NPCM7xxPWMState), | ||
777 | + VMSTATE_UINT32(piir, NPCM7xxPWMState), | ||
778 | + VMSTATE_END_OF_LIST(), | ||
779 | + }, | ||
780 | +}; | ||
781 | + | ||
782 | +static void npcm7xx_pwm_class_init(ObjectClass *klass, void *data) | ||
783 | +{ | ||
784 | + ResettableClass *rc = RESETTABLE_CLASS(klass); | ||
785 | + DeviceClass *dc = DEVICE_CLASS(klass); | ||
786 | + | ||
787 | + dc->desc = "NPCM7xx PWM Controller"; | ||
788 | + dc->vmsd = &vmstate_npcm7xx_pwm_module; | ||
789 | + rc->phases.enter = npcm7xx_pwm_enter_reset; | ||
790 | + rc->phases.hold = npcm7xx_pwm_hold_reset; | ||
791 | +} | ||
792 | + | ||
793 | +static const TypeInfo npcm7xx_pwm_info = { | ||
794 | + .name = TYPE_NPCM7XX_PWM, | ||
795 | + .parent = TYPE_SYS_BUS_DEVICE, | ||
796 | + .instance_size = sizeof(NPCM7xxPWMState), | ||
797 | + .class_init = npcm7xx_pwm_class_init, | ||
798 | + .instance_init = npcm7xx_pwm_init, | ||
799 | +}; | ||
800 | + | ||
801 | +static void npcm7xx_pwm_register_type(void) | ||
802 | +{ | ||
803 | + type_register_static(&npcm7xx_pwm_info); | ||
804 | +} | ||
805 | +type_init(npcm7xx_pwm_register_type); | ||
806 | diff --git a/hw/misc/meson.build b/hw/misc/meson.build | ||
807 | index XXXXXXX..XXXXXXX 100644 | 515 | index XXXXXXX..XXXXXXX 100644 |
808 | --- a/hw/misc/meson.build | 516 | --- a/hw/char/Kconfig |
809 | +++ b/hw/misc/meson.build | 517 | +++ b/hw/char/Kconfig |
810 | @@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_MAINSTONE', if_true: files('mst_fpga.c')) | 518 | @@ -XXX,XX +XXX,XX @@ config VIRTIO_SERIAL |
811 | softmmu_ss.add(when: 'CONFIG_NPCM7XX', if_true: files( | 519 | config STM32F2XX_USART |
812 | 'npcm7xx_clk.c', | 520 | bool |
813 | 'npcm7xx_gcr.c', | 521 | |
814 | + 'npcm7xx_pwm.c', | 522 | +config STM32L4X5_USART |
815 | 'npcm7xx_rng.c', | 523 | + bool |
816 | )) | 524 | + |
817 | softmmu_ss.add(when: 'CONFIG_OMAP', if_true: files( | 525 | config CMSDK_APB_UART |
818 | diff --git a/hw/misc/trace-events b/hw/misc/trace-events | 526 | bool |
527 | |||
528 | diff --git a/hw/char/meson.build b/hw/char/meson.build | ||
819 | index XXXXXXX..XXXXXXX 100644 | 529 | index XXXXXXX..XXXXXXX 100644 |
820 | --- a/hw/misc/trace-events | 530 | --- a/hw/char/meson.build |
821 | +++ b/hw/misc/trace-events | 531 | +++ b/hw/char/meson.build |
822 | @@ -XXX,XX +XXX,XX @@ npcm7xx_gcr_write(uint64_t offset, uint32_t value) "offset: 0x%04" PRIx64 " valu | 532 | @@ -XXX,XX +XXX,XX @@ system_ss.add(when: 'CONFIG_RENESAS_SCI', if_true: files('renesas_sci.c')) |
823 | npcm7xx_rng_read(uint64_t offset, uint64_t value, unsigned size) "offset: 0x%04" PRIx64 " value: 0x%02" PRIx64 " size: %u" | 533 | system_ss.add(when: 'CONFIG_SIFIVE_UART', if_true: files('sifive_uart.c')) |
824 | npcm7xx_rng_write(uint64_t offset, uint64_t value, unsigned size) "offset: 0x%04" PRIx64 " value: 0x%02" PRIx64 " size: %u" | 534 | system_ss.add(when: 'CONFIG_SH_SCI', if_true: files('sh_serial.c')) |
825 | 535 | system_ss.add(when: 'CONFIG_STM32F2XX_USART', if_true: files('stm32f2xx_usart.c')) | |
826 | +# npcm7xx_pwm.c | 536 | +system_ss.add(when: 'CONFIG_STM32L4X5_USART', if_true: files('stm32l4x5_usart.c')) |
827 | +npcm7xx_pwm_read(const char *id, uint64_t offset, uint32_t value) "%s offset: 0x%04" PRIx64 " value: 0x%08" PRIx32 | 537 | system_ss.add(when: 'CONFIG_MCHP_PFSOC_MMUART', if_true: files('mchp_pfsoc_mmuart.c')) |
828 | +npcm7xx_pwm_write(const char *id, uint64_t offset, uint32_t value) "%s offset: 0x%04" PRIx64 " value: 0x%08" PRIx32 | 538 | system_ss.add(when: 'CONFIG_HTIF', if_true: files('riscv_htif.c')) |
829 | +npcm7xx_pwm_update_freq(const char *id, uint8_t index, uint32_t old_value, uint32_t new_value) "%s pwm[%u] Update Freq: old_freq: %u, new_freq: %u" | 539 | system_ss.add(when: 'CONFIG_GOLDFISH_TTY', if_true: files('goldfish_tty.c')) |
830 | +npcm7xx_pwm_update_duty(const char *id, uint8_t index, uint32_t old_value, uint32_t new_value) "%s pwm[%u] Update Duty: old_duty: %u, new_duty: %u" | 540 | diff --git a/hw/char/trace-events b/hw/char/trace-events |
831 | + | 541 | index XXXXXXX..XXXXXXX 100644 |
832 | # stm32f4xx_syscfg.c | 542 | --- a/hw/char/trace-events |
833 | stm32f4xx_syscfg_set_irq(int gpio, int line, int level) "Interupt: GPIO: %d, Line: %d; Level: %d" | 543 | +++ b/hw/char/trace-events |
834 | stm32f4xx_pulse_exti(int irq) "Pulse EXTI: %d" | 544 | @@ -XXX,XX +XXX,XX @@ cadence_uart_baudrate(unsigned baudrate) "baudrate %u" |
545 | sh_serial_read(char *id, unsigned size, uint64_t offs, uint64_t val) " %s size %d offs 0x%02" PRIx64 " -> 0x%02" PRIx64 | ||
546 | sh_serial_write(char *id, unsigned size, uint64_t offs, uint64_t val) "%s size %d offs 0x%02" PRIx64 " <- 0x%02" PRIx64 | ||
547 | |||
548 | +# stm32l4x5_usart.c | ||
549 | +stm32l4x5_usart_read(uint64_t addr, uint32_t data) "USART: Read <0x%" PRIx64 "> -> 0x%" PRIx32 "" | ||
550 | +stm32l4x5_usart_write(uint64_t addr, uint32_t data) "USART: Write <0x%" PRIx64 "> <- 0x%" PRIx32 "" | ||
551 | + | ||
552 | # xen_console.c | ||
553 | xen_console_connect(unsigned int idx, unsigned int ring_ref, unsigned int port, unsigned int limit) "idx %u ring_ref %u port %u limit %u" | ||
554 | xen_console_disconnect(unsigned int idx) "idx %u" | ||
835 | -- | 555 | -- |
836 | 2.20.1 | 556 | 2.34.1 |
837 | 557 | ||
838 | 558 | diff view generated by jsdifflib |
1 | From: Leif Lindholm <leif@nuviainc.com> | 1 | From: Arnaud Minier <arnaud.minier@telecom-paris.fr> |
---|---|---|---|
2 | 2 | ||
3 | The AArch64 view of CLIDR_EL1 extends the ICB field to include also bit | 3 | Implement the ability to read and write characters to the |
4 | 32, as well as adding a Ttype<n> field when FEAT_MTE is implemented. | 4 | usart using the serial port. |
5 | Extend the clidr field to be able to hold this context. | 5 | |
6 | 6 | The character transmission is based on the | |
7 | Signed-off-by: Leif Lindholm <leif@nuviainc.com> | 7 | cmsdk-apb-uart implementation. |
8 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 8 | |
9 | Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr> | ||
10 | Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr> | ||
9 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 11 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
10 | Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com> | 12 | Message-id: 20240329174402.60382-3-arnaud.minier@telecom-paris.fr |
11 | Message-id: 20210108185154.8108-3-leif@nuviainc.com | 13 | [PMM: fixed a few checkpatch nits] |
12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 14 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
13 | --- | 15 | --- |
14 | target/arm/cpu.h | 2 +- | 16 | include/hw/char/stm32l4x5_usart.h | 1 + |
15 | 1 file changed, 1 insertion(+), 1 deletion(-) | 17 | hw/char/stm32l4x5_usart.c | 143 ++++++++++++++++++++++++++++++ |
16 | 18 | hw/char/trace-events | 7 ++ | |
17 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | 19 | 3 files changed, 151 insertions(+) |
20 | |||
21 | diff --git a/include/hw/char/stm32l4x5_usart.h b/include/hw/char/stm32l4x5_usart.h | ||
18 | index XXXXXXX..XXXXXXX 100644 | 22 | index XXXXXXX..XXXXXXX 100644 |
19 | --- a/target/arm/cpu.h | 23 | --- a/include/hw/char/stm32l4x5_usart.h |
20 | +++ b/target/arm/cpu.h | 24 | +++ b/include/hw/char/stm32l4x5_usart.h |
21 | @@ -XXX,XX +XXX,XX @@ struct ARMCPU { | 25 | @@ -XXX,XX +XXX,XX @@ struct Stm32l4x5UsartBaseState { |
22 | uint32_t id_afr0; | 26 | Clock *clk; |
23 | uint64_t id_aa64afr0; | 27 | CharBackend chr; |
24 | uint64_t id_aa64afr1; | 28 | qemu_irq irq; |
25 | - uint32_t clidr; | 29 | + guint watch_tag; |
26 | + uint64_t clidr; | 30 | }; |
27 | uint64_t mp_affinity; /* MP ID without feature bits */ | 31 | |
28 | /* The elements of this array are the CCSIDR values for each cache, | 32 | struct Stm32l4x5UsartBaseClass { |
29 | * in the order L1DCache, L1ICache, L2DCache, L2ICache, etc. | 33 | diff --git a/hw/char/stm32l4x5_usart.c b/hw/char/stm32l4x5_usart.c |
34 | index XXXXXXX..XXXXXXX 100644 | ||
35 | --- a/hw/char/stm32l4x5_usart.c | ||
36 | +++ b/hw/char/stm32l4x5_usart.c | ||
37 | @@ -XXX,XX +XXX,XX @@ REG32(RDR, 0x24) | ||
38 | REG32(TDR, 0x28) | ||
39 | FIELD(TDR, TDR, 0, 9) | ||
40 | |||
41 | +static void stm32l4x5_update_irq(Stm32l4x5UsartBaseState *s) | ||
42 | +{ | ||
43 | + if (((s->isr & R_ISR_WUF_MASK) && (s->cr3 & R_CR3_WUFIE_MASK)) || | ||
44 | + ((s->isr & R_ISR_CMF_MASK) && (s->cr1 & R_CR1_CMIE_MASK)) || | ||
45 | + ((s->isr & R_ISR_ABRF_MASK) && (s->cr1 & R_CR1_RXNEIE_MASK)) || | ||
46 | + ((s->isr & R_ISR_EOBF_MASK) && (s->cr1 & R_CR1_EOBIE_MASK)) || | ||
47 | + ((s->isr & R_ISR_RTOF_MASK) && (s->cr1 & R_CR1_RTOIE_MASK)) || | ||
48 | + ((s->isr & R_ISR_CTSIF_MASK) && (s->cr3 & R_CR3_CTSIE_MASK)) || | ||
49 | + ((s->isr & R_ISR_LBDF_MASK) && (s->cr2 & R_CR2_LBDIE_MASK)) || | ||
50 | + ((s->isr & R_ISR_TXE_MASK) && (s->cr1 & R_CR1_TXEIE_MASK)) || | ||
51 | + ((s->isr & R_ISR_TC_MASK) && (s->cr1 & R_CR1_TCIE_MASK)) || | ||
52 | + ((s->isr & R_ISR_RXNE_MASK) && (s->cr1 & R_CR1_RXNEIE_MASK)) || | ||
53 | + ((s->isr & R_ISR_IDLE_MASK) && (s->cr1 & R_CR1_IDLEIE_MASK)) || | ||
54 | + ((s->isr & R_ISR_ORE_MASK) && | ||
55 | + ((s->cr1 & R_CR1_RXNEIE_MASK) || (s->cr3 & R_CR3_EIE_MASK))) || | ||
56 | + /* TODO: Handle NF ? */ | ||
57 | + ((s->isr & R_ISR_FE_MASK) && (s->cr3 & R_CR3_EIE_MASK)) || | ||
58 | + ((s->isr & R_ISR_PE_MASK) && (s->cr1 & R_CR1_PEIE_MASK))) { | ||
59 | + qemu_irq_raise(s->irq); | ||
60 | + trace_stm32l4x5_usart_irq_raised(s->isr); | ||
61 | + } else { | ||
62 | + qemu_irq_lower(s->irq); | ||
63 | + trace_stm32l4x5_usart_irq_lowered(); | ||
64 | + } | ||
65 | +} | ||
66 | + | ||
67 | +static int stm32l4x5_usart_base_can_receive(void *opaque) | ||
68 | +{ | ||
69 | + Stm32l4x5UsartBaseState *s = opaque; | ||
70 | + | ||
71 | + if (!(s->isr & R_ISR_RXNE_MASK)) { | ||
72 | + return 1; | ||
73 | + } | ||
74 | + | ||
75 | + return 0; | ||
76 | +} | ||
77 | + | ||
78 | +static void stm32l4x5_usart_base_receive(void *opaque, const uint8_t *buf, | ||
79 | + int size) | ||
80 | +{ | ||
81 | + Stm32l4x5UsartBaseState *s = opaque; | ||
82 | + | ||
83 | + if (!((s->cr1 & R_CR1_UE_MASK) && (s->cr1 & R_CR1_RE_MASK))) { | ||
84 | + trace_stm32l4x5_usart_receiver_not_enabled( | ||
85 | + FIELD_EX32(s->cr1, CR1, UE), FIELD_EX32(s->cr1, CR1, RE)); | ||
86 | + return; | ||
87 | + } | ||
88 | + | ||
89 | + /* Check if overrun detection is enabled and if there is an overrun */ | ||
90 | + if (!(s->cr3 & R_CR3_OVRDIS_MASK) && (s->isr & R_ISR_RXNE_MASK)) { | ||
91 | + /* | ||
92 | + * A character has been received while | ||
93 | + * the previous has not been read = Overrun. | ||
94 | + */ | ||
95 | + s->isr |= R_ISR_ORE_MASK; | ||
96 | + trace_stm32l4x5_usart_overrun_detected(s->rdr, *buf); | ||
97 | + } else { | ||
98 | + /* No overrun */ | ||
99 | + s->rdr = *buf; | ||
100 | + s->isr |= R_ISR_RXNE_MASK; | ||
101 | + trace_stm32l4x5_usart_rx(s->rdr); | ||
102 | + } | ||
103 | + | ||
104 | + stm32l4x5_update_irq(s); | ||
105 | +} | ||
106 | + | ||
107 | +/* | ||
108 | + * Try to send tx data, and arrange to be called back later if | ||
109 | + * we can't (ie the char backend is busy/blocking). | ||
110 | + */ | ||
111 | +static gboolean usart_transmit(void *do_not_use, GIOCondition cond, | ||
112 | + void *opaque) | ||
113 | +{ | ||
114 | + Stm32l4x5UsartBaseState *s = STM32L4X5_USART_BASE(opaque); | ||
115 | + int ret; | ||
116 | + /* TODO: Handle 9 bits transmission */ | ||
117 | + uint8_t ch = s->tdr; | ||
118 | + | ||
119 | + s->watch_tag = 0; | ||
120 | + | ||
121 | + if (!(s->cr1 & R_CR1_TE_MASK) || (s->isr & R_ISR_TXE_MASK)) { | ||
122 | + return G_SOURCE_REMOVE; | ||
123 | + } | ||
124 | + | ||
125 | + ret = qemu_chr_fe_write(&s->chr, &ch, 1); | ||
126 | + if (ret <= 0) { | ||
127 | + s->watch_tag = qemu_chr_fe_add_watch(&s->chr, G_IO_OUT | G_IO_HUP, | ||
128 | + usart_transmit, s); | ||
129 | + if (!s->watch_tag) { | ||
130 | + /* | ||
131 | + * Most common reason to be here is "no chardev backend": | ||
132 | + * just insta-drain the buffer, so the serial output | ||
133 | + * goes into a void, rather than blocking the guest. | ||
134 | + */ | ||
135 | + goto buffer_drained; | ||
136 | + } | ||
137 | + /* Transmit pending */ | ||
138 | + trace_stm32l4x5_usart_tx_pending(); | ||
139 | + return G_SOURCE_REMOVE; | ||
140 | + } | ||
141 | + | ||
142 | +buffer_drained: | ||
143 | + /* Character successfully sent */ | ||
144 | + trace_stm32l4x5_usart_tx(ch); | ||
145 | + s->isr |= R_ISR_TC_MASK | R_ISR_TXE_MASK; | ||
146 | + stm32l4x5_update_irq(s); | ||
147 | + return G_SOURCE_REMOVE; | ||
148 | +} | ||
149 | + | ||
150 | +static void usart_cancel_transmit(Stm32l4x5UsartBaseState *s) | ||
151 | +{ | ||
152 | + if (s->watch_tag) { | ||
153 | + g_source_remove(s->watch_tag); | ||
154 | + s->watch_tag = 0; | ||
155 | + } | ||
156 | +} | ||
157 | + | ||
158 | static void stm32l4x5_usart_base_reset_hold(Object *obj, ResetType type) | ||
159 | { | ||
160 | Stm32l4x5UsartBaseState *s = STM32L4X5_USART_BASE(obj); | ||
161 | @@ -XXX,XX +XXX,XX @@ static void stm32l4x5_usart_base_reset_hold(Object *obj, ResetType type) | ||
162 | s->isr = 0x020000C0; | ||
163 | s->rdr = 0x00000000; | ||
164 | s->tdr = 0x00000000; | ||
165 | + | ||
166 | + usart_cancel_transmit(s); | ||
167 | + stm32l4x5_update_irq(s); | ||
168 | +} | ||
169 | + | ||
170 | +static void usart_update_rqr(Stm32l4x5UsartBaseState *s, uint32_t value) | ||
171 | +{ | ||
172 | + /* TXFRQ */ | ||
173 | + /* Reset RXNE flag */ | ||
174 | + if (value & R_RQR_RXFRQ_MASK) { | ||
175 | + s->isr &= ~R_ISR_RXNE_MASK; | ||
176 | + } | ||
177 | + /* MMRQ */ | ||
178 | + /* SBKRQ */ | ||
179 | + /* ABRRQ */ | ||
180 | + stm32l4x5_update_irq(s); | ||
181 | } | ||
182 | |||
183 | static uint64_t stm32l4x5_usart_base_read(void *opaque, hwaddr addr, | ||
184 | @@ -XXX,XX +XXX,XX @@ static uint64_t stm32l4x5_usart_base_read(void *opaque, hwaddr addr, | ||
185 | retvalue = FIELD_EX32(s->rdr, RDR, RDR); | ||
186 | /* Reset RXNE flag */ | ||
187 | s->isr &= ~R_ISR_RXNE_MASK; | ||
188 | + stm32l4x5_update_irq(s); | ||
189 | break; | ||
190 | case A_TDR: | ||
191 | retvalue = FIELD_EX32(s->tdr, TDR, TDR); | ||
192 | @@ -XXX,XX +XXX,XX @@ static void stm32l4x5_usart_base_write(void *opaque, hwaddr addr, | ||
193 | switch (addr) { | ||
194 | case A_CR1: | ||
195 | s->cr1 = value; | ||
196 | + stm32l4x5_update_irq(s); | ||
197 | return; | ||
198 | case A_CR2: | ||
199 | s->cr2 = value; | ||
200 | @@ -XXX,XX +XXX,XX @@ static void stm32l4x5_usart_base_write(void *opaque, hwaddr addr, | ||
201 | s->rtor = value; | ||
202 | return; | ||
203 | case A_RQR: | ||
204 | + usart_update_rqr(s, value); | ||
205 | return; | ||
206 | case A_ISR: | ||
207 | qemu_log_mask(LOG_GUEST_ERROR, | ||
208 | @@ -XXX,XX +XXX,XX @@ static void stm32l4x5_usart_base_write(void *opaque, hwaddr addr, | ||
209 | case A_ICR: | ||
210 | /* Clear the status flags */ | ||
211 | s->isr &= ~value; | ||
212 | + stm32l4x5_update_irq(s); | ||
213 | return; | ||
214 | case A_RDR: | ||
215 | qemu_log_mask(LOG_GUEST_ERROR, | ||
216 | @@ -XXX,XX +XXX,XX @@ static void stm32l4x5_usart_base_write(void *opaque, hwaddr addr, | ||
217 | return; | ||
218 | case A_TDR: | ||
219 | s->tdr = value; | ||
220 | + s->isr &= ~R_ISR_TXE_MASK; | ||
221 | + usart_transmit(NULL, G_IO_OUT, s); | ||
222 | return; | ||
223 | default: | ||
224 | qemu_log_mask(LOG_GUEST_ERROR, | ||
225 | @@ -XXX,XX +XXX,XX @@ static void stm32l4x5_usart_base_realize(DeviceState *dev, Error **errp) | ||
226 | error_setg(errp, "USART clock must be wired up by SoC code"); | ||
227 | return; | ||
228 | } | ||
229 | + | ||
230 | + qemu_chr_fe_set_handlers(&s->chr, stm32l4x5_usart_base_can_receive, | ||
231 | + stm32l4x5_usart_base_receive, NULL, NULL, | ||
232 | + s, NULL, true); | ||
233 | } | ||
234 | |||
235 | static void stm32l4x5_usart_base_class_init(ObjectClass *klass, void *data) | ||
236 | diff --git a/hw/char/trace-events b/hw/char/trace-events | ||
237 | index XXXXXXX..XXXXXXX 100644 | ||
238 | --- a/hw/char/trace-events | ||
239 | +++ b/hw/char/trace-events | ||
240 | @@ -XXX,XX +XXX,XX @@ sh_serial_write(char *id, unsigned size, uint64_t offs, uint64_t val) "%s size % | ||
241 | # stm32l4x5_usart.c | ||
242 | stm32l4x5_usart_read(uint64_t addr, uint32_t data) "USART: Read <0x%" PRIx64 "> -> 0x%" PRIx32 "" | ||
243 | stm32l4x5_usart_write(uint64_t addr, uint32_t data) "USART: Write <0x%" PRIx64 "> <- 0x%" PRIx32 "" | ||
244 | +stm32l4x5_usart_rx(uint8_t c) "USART: got character 0x%x from backend" | ||
245 | +stm32l4x5_usart_tx(uint8_t c) "USART: character 0x%x sent to backend" | ||
246 | +stm32l4x5_usart_tx_pending(void) "USART: character send to backend pending" | ||
247 | +stm32l4x5_usart_irq_raised(uint32_t reg) "USART: IRQ raised: 0x%08"PRIx32 | ||
248 | +stm32l4x5_usart_irq_lowered(void) "USART: IRQ lowered" | ||
249 | +stm32l4x5_usart_overrun_detected(uint8_t current, uint8_t received) "USART: Overrun detected, RDR='0x%x', received 0x%x" | ||
250 | +stm32l4x5_usart_receiver_not_enabled(uint8_t ue_bit, uint8_t re_bit) "USART: Receiver not enabled, UE=0x%x, RE=0x%x" | ||
251 | |||
252 | # xen_console.c | ||
253 | xen_console_connect(unsigned int idx, unsigned int ring_ref, unsigned int port, unsigned int limit) "idx %u ring_ref %u port %u limit %u" | ||
30 | -- | 254 | -- |
31 | 2.20.1 | 255 | 2.34.1 |
32 | 256 | ||
33 | 257 | diff view generated by jsdifflib |
1 | From: Hao Wu <wuhaotsh@google.com> | 1 | From: Arnaud Minier <arnaud.minier@telecom-paris.fr> |
---|---|---|---|
2 | 2 | ||
3 | The ADC is part of NPCM7XX Module. Its behavior is controled by the | 3 | Add a function to change the settings of the |
4 | ADC_CON register. It converts one of the eight analog inputs into a | 4 | serial connection. |
5 | digital input and stores it in the ADC_DATA register when enabled. | ||
6 | 5 | ||
7 | Users can alter input value by using qom-set QMP command. | 6 | Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr> |
8 | 7 | Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr> | |
9 | Reviewed-by: Havard Skinnemoen <hskinnemoen@google.com> | ||
10 | Reviewed-by: Tyrone Ting <kfting@nuvoton.com> | ||
11 | Signed-off-by: Hao Wu <wuhaotsh@google.com> | ||
12 | Message-id: 20210108190945.949196-4-wuhaotsh@google.com | ||
13 | [PMM: Added missing hw/adc/trace.h file] | ||
14 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
9 | Message-id: 20240329174402.60382-4-arnaud.minier@telecom-paris.fr | ||
15 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
16 | --- | 11 | --- |
17 | docs/system/arm/nuvoton.rst | 2 +- | 12 | hw/char/stm32l4x5_usart.c | 98 +++++++++++++++++++++++++++++++++++++++ |
18 | meson.build | 1 + | 13 | hw/char/trace-events | 1 + |
19 | hw/adc/trace.h | 1 + | 14 | 2 files changed, 99 insertions(+) |
20 | include/hw/adc/npcm7xx_adc.h | 69 ++++++ | ||
21 | include/hw/arm/npcm7xx.h | 2 + | ||
22 | hw/adc/npcm7xx_adc.c | 301 ++++++++++++++++++++++++++ | ||
23 | hw/arm/npcm7xx.c | 24 ++- | ||
24 | tests/qtest/npcm7xx_adc-test.c | 377 +++++++++++++++++++++++++++++++++ | ||
25 | hw/adc/meson.build | 1 + | ||
26 | hw/adc/trace-events | 5 + | ||
27 | tests/qtest/meson.build | 3 +- | ||
28 | 11 files changed, 783 insertions(+), 3 deletions(-) | ||
29 | create mode 100644 hw/adc/trace.h | ||
30 | create mode 100644 include/hw/adc/npcm7xx_adc.h | ||
31 | create mode 100644 hw/adc/npcm7xx_adc.c | ||
32 | create mode 100644 tests/qtest/npcm7xx_adc-test.c | ||
33 | create mode 100644 hw/adc/trace-events | ||
34 | 15 | ||
35 | diff --git a/docs/system/arm/nuvoton.rst b/docs/system/arm/nuvoton.rst | 16 | diff --git a/hw/char/stm32l4x5_usart.c b/hw/char/stm32l4x5_usart.c |
36 | index XXXXXXX..XXXXXXX 100644 | 17 | index XXXXXXX..XXXXXXX 100644 |
37 | --- a/docs/system/arm/nuvoton.rst | 18 | --- a/hw/char/stm32l4x5_usart.c |
38 | +++ b/docs/system/arm/nuvoton.rst | 19 | +++ b/hw/char/stm32l4x5_usart.c |
39 | @@ -XXX,XX +XXX,XX @@ Supported devices | 20 | @@ -XXX,XX +XXX,XX @@ static void usart_cancel_transmit(Stm32l4x5UsartBaseState *s) |
40 | * Random Number Generator (RNG) | 21 | } |
41 | * USB host (USBH) | 22 | } |
42 | * GPIO controller | 23 | |
43 | + * Analog to Digital Converter (ADC) | 24 | +static void stm32l4x5_update_params(Stm32l4x5UsartBaseState *s) |
44 | 25 | +{ | |
45 | Missing devices | 26 | + int speed, parity, data_bits, stop_bits; |
46 | --------------- | 27 | + uint32_t value, usart_div; |
47 | @@ -XXX,XX +XXX,XX @@ Missing devices | 28 | + QEMUSerialSetParams ssp; |
48 | * USB device (USBD) | ||
49 | * SMBus controller (SMBF) | ||
50 | * Peripheral SPI controller (PSPI) | ||
51 | - * Analog to Digital Converter (ADC) | ||
52 | * SD/MMC host | ||
53 | * PECI interface | ||
54 | * Pulse Width Modulation (PWM) | ||
55 | diff --git a/meson.build b/meson.build | ||
56 | index XXXXXXX..XXXXXXX 100644 | ||
57 | --- a/meson.build | ||
58 | +++ b/meson.build | ||
59 | @@ -XXX,XX +XXX,XX @@ if have_system | ||
60 | 'chardev', | ||
61 | 'hw/9pfs', | ||
62 | 'hw/acpi', | ||
63 | + 'hw/adc', | ||
64 | 'hw/alpha', | ||
65 | 'hw/arm', | ||
66 | 'hw/audio', | ||
67 | diff --git a/hw/adc/trace.h b/hw/adc/trace.h | ||
68 | new file mode 100644 | ||
69 | index XXXXXXX..XXXXXXX | ||
70 | --- /dev/null | ||
71 | +++ b/hw/adc/trace.h | ||
72 | @@ -0,0 +1 @@ | ||
73 | +#include "trace/trace-hw_adc.h" | ||
74 | diff --git a/include/hw/adc/npcm7xx_adc.h b/include/hw/adc/npcm7xx_adc.h | ||
75 | new file mode 100644 | ||
76 | index XXXXXXX..XXXXXXX | ||
77 | --- /dev/null | ||
78 | +++ b/include/hw/adc/npcm7xx_adc.h | ||
79 | @@ -XXX,XX +XXX,XX @@ | ||
80 | +/* | ||
81 | + * Nuvoton NPCM7xx ADC Module | ||
82 | + * | ||
83 | + * Copyright 2020 Google LLC | ||
84 | + * | ||
85 | + * This program is free software; you can redistribute it and/or modify it | ||
86 | + * under the terms of the GNU General Public License as published by the | ||
87 | + * Free Software Foundation; either version 2 of the License, or | ||
88 | + * (at your option) any later version. | ||
89 | + * | ||
90 | + * This program is distributed in the hope that it will be useful, but WITHOUT | ||
91 | + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
92 | + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | ||
93 | + * for more details. | ||
94 | + */ | ||
95 | +#ifndef NPCM7XX_ADC_H | ||
96 | +#define NPCM7XX_ADC_H | ||
97 | + | 29 | + |
98 | +#include "hw/clock.h" | 30 | + /* Select the parity type */ |
99 | +#include "hw/irq.h" | 31 | + if (s->cr1 & R_CR1_PCE_MASK) { |
100 | +#include "hw/sysbus.h" | 32 | + if (s->cr1 & R_CR1_PS_MASK) { |
101 | +#include "qemu/timer.h" | 33 | + parity = 'O'; |
102 | + | 34 | + } else { |
103 | +#define NPCM7XX_ADC_NUM_INPUTS 8 | 35 | + parity = 'E'; |
104 | +/** | 36 | + } |
105 | + * This value should not be changed unless write_adc_calibration function in | 37 | + } else { |
106 | + * hw/arm/npcm7xx.c is also changed. | 38 | + parity = 'N'; |
107 | + */ | ||
108 | +#define NPCM7XX_ADC_NUM_CALIB 2 | ||
109 | + | ||
110 | +/** | ||
111 | + * struct NPCM7xxADCState - Analog to Digital Converter Module device state. | ||
112 | + * @parent: System bus device. | ||
113 | + * @iomem: Memory region through which registers are accessed. | ||
114 | + * @conv_timer: The timer counts down remaining cycles for the conversion. | ||
115 | + * @irq: GIC interrupt line to fire on expiration (if enabled). | ||
116 | + * @con: The Control Register. | ||
117 | + * @data: The Data Buffer. | ||
118 | + * @clock: The ADC Clock. | ||
119 | + * @adci: The input voltage in units of uV. 1uv = 1e-6V. | ||
120 | + * @vref: The external reference voltage. | ||
121 | + * @iref: The internal reference voltage, initialized at launch time. | ||
122 | + * @rv: The calibrated output values of 0.5V and 1.5V for the ADC. | ||
123 | + */ | ||
124 | +typedef struct { | ||
125 | + SysBusDevice parent; | ||
126 | + | ||
127 | + MemoryRegion iomem; | ||
128 | + | ||
129 | + QEMUTimer conv_timer; | ||
130 | + | ||
131 | + qemu_irq irq; | ||
132 | + uint32_t con; | ||
133 | + uint32_t data; | ||
134 | + Clock *clock; | ||
135 | + | ||
136 | + /* Voltages are in unit of uV. 1V = 1000000uV. */ | ||
137 | + uint32_t adci[NPCM7XX_ADC_NUM_INPUTS]; | ||
138 | + uint32_t vref; | ||
139 | + uint32_t iref; | ||
140 | + | ||
141 | + uint16_t calibration_r_values[NPCM7XX_ADC_NUM_CALIB]; | ||
142 | +} NPCM7xxADCState; | ||
143 | + | ||
144 | +#define TYPE_NPCM7XX_ADC "npcm7xx-adc" | ||
145 | +#define NPCM7XX_ADC(obj) \ | ||
146 | + OBJECT_CHECK(NPCM7xxADCState, (obj), TYPE_NPCM7XX_ADC) | ||
147 | + | ||
148 | +#endif /* NPCM7XX_ADC_H */ | ||
149 | diff --git a/include/hw/arm/npcm7xx.h b/include/hw/arm/npcm7xx.h | ||
150 | index XXXXXXX..XXXXXXX 100644 | ||
151 | --- a/include/hw/arm/npcm7xx.h | ||
152 | +++ b/include/hw/arm/npcm7xx.h | ||
153 | @@ -XXX,XX +XXX,XX @@ | ||
154 | #define NPCM7XX_H | ||
155 | |||
156 | #include "hw/boards.h" | ||
157 | +#include "hw/adc/npcm7xx_adc.h" | ||
158 | #include "hw/cpu/a9mpcore.h" | ||
159 | #include "hw/gpio/npcm7xx_gpio.h" | ||
160 | #include "hw/mem/npcm7xx_mc.h" | ||
161 | @@ -XXX,XX +XXX,XX @@ typedef struct NPCM7xxState { | ||
162 | NPCM7xxGCRState gcr; | ||
163 | NPCM7xxCLKState clk; | ||
164 | NPCM7xxTimerCtrlState tim[3]; | ||
165 | + NPCM7xxADCState adc; | ||
166 | NPCM7xxOTPState key_storage; | ||
167 | NPCM7xxOTPState fuse_array; | ||
168 | NPCM7xxMCState mc; | ||
169 | diff --git a/hw/adc/npcm7xx_adc.c b/hw/adc/npcm7xx_adc.c | ||
170 | new file mode 100644 | ||
171 | index XXXXXXX..XXXXXXX | ||
172 | --- /dev/null | ||
173 | +++ b/hw/adc/npcm7xx_adc.c | ||
174 | @@ -XXX,XX +XXX,XX @@ | ||
175 | +/* | ||
176 | + * Nuvoton NPCM7xx ADC Module | ||
177 | + * | ||
178 | + * Copyright 2020 Google LLC | ||
179 | + * | ||
180 | + * This program is free software; you can redistribute it and/or modify it | ||
181 | + * under the terms of the GNU General Public License as published by the | ||
182 | + * Free Software Foundation; either version 2 of the License, or | ||
183 | + * (at your option) any later version. | ||
184 | + * | ||
185 | + * This program is distributed in the hope that it will be useful, but WITHOUT | ||
186 | + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
187 | + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | ||
188 | + * for more details. | ||
189 | + */ | ||
190 | + | ||
191 | +#include "qemu/osdep.h" | ||
192 | +#include "hw/adc/npcm7xx_adc.h" | ||
193 | +#include "hw/qdev-clock.h" | ||
194 | +#include "hw/qdev-properties.h" | ||
195 | +#include "hw/registerfields.h" | ||
196 | +#include "migration/vmstate.h" | ||
197 | +#include "qemu/log.h" | ||
198 | +#include "qemu/module.h" | ||
199 | +#include "qemu/timer.h" | ||
200 | +#include "qemu/units.h" | ||
201 | +#include "trace.h" | ||
202 | + | ||
203 | +REG32(NPCM7XX_ADC_CON, 0x0) | ||
204 | +REG32(NPCM7XX_ADC_DATA, 0x4) | ||
205 | + | ||
206 | +/* Register field definitions. */ | ||
207 | +#define NPCM7XX_ADC_CON_MUX(rv) extract32(rv, 24, 4) | ||
208 | +#define NPCM7XX_ADC_CON_INT_EN BIT(21) | ||
209 | +#define NPCM7XX_ADC_CON_REFSEL BIT(19) | ||
210 | +#define NPCM7XX_ADC_CON_INT BIT(18) | ||
211 | +#define NPCM7XX_ADC_CON_EN BIT(17) | ||
212 | +#define NPCM7XX_ADC_CON_RST BIT(16) | ||
213 | +#define NPCM7XX_ADC_CON_CONV BIT(14) | ||
214 | +#define NPCM7XX_ADC_CON_DIV(rv) extract32(rv, 1, 8) | ||
215 | + | ||
216 | +#define NPCM7XX_ADC_MAX_RESULT 1023 | ||
217 | +#define NPCM7XX_ADC_DEFAULT_IREF 2000000 | ||
218 | +#define NPCM7XX_ADC_CONV_CYCLES 20 | ||
219 | +#define NPCM7XX_ADC_RESET_CYCLES 10 | ||
220 | +#define NPCM7XX_ADC_R0_INPUT 500000 | ||
221 | +#define NPCM7XX_ADC_R1_INPUT 1500000 | ||
222 | + | ||
223 | +static void npcm7xx_adc_reset(NPCM7xxADCState *s) | ||
224 | +{ | ||
225 | + timer_del(&s->conv_timer); | ||
226 | + s->con = 0x000c0001; | ||
227 | + s->data = 0x00000000; | ||
228 | +} | ||
229 | + | ||
230 | +static uint32_t npcm7xx_adc_convert(uint32_t input, uint32_t ref) | ||
231 | +{ | ||
232 | + uint32_t result; | ||
233 | + | ||
234 | + result = input * (NPCM7XX_ADC_MAX_RESULT + 1) / ref; | ||
235 | + if (result > NPCM7XX_ADC_MAX_RESULT) { | ||
236 | + result = NPCM7XX_ADC_MAX_RESULT; | ||
237 | + } | 39 | + } |
238 | + | 40 | + |
239 | + return result; | 41 | + /* Select the number of stop bits */ |
240 | +} | 42 | + switch (FIELD_EX32(s->cr2, CR2, STOP)) { |
241 | + | 43 | + case 0: |
242 | +static uint32_t npcm7xx_adc_prescaler(NPCM7xxADCState *s) | 44 | + stop_bits = 1; |
243 | +{ | 45 | + break; |
244 | + return 2 * (NPCM7XX_ADC_CON_DIV(s->con) + 1); | 46 | + case 2: |
245 | +} | 47 | + stop_bits = 2; |
246 | + | 48 | + break; |
247 | +static void npcm7xx_adc_start_timer(Clock *clk, QEMUTimer *timer, | 49 | + default: |
248 | + uint32_t cycles, uint32_t prescaler) | 50 | + qemu_log_mask(LOG_UNIMP, |
249 | +{ | 51 | + "UNIMPLEMENTED: fractionnal stop bits; CR2[13:12] = %u", |
250 | + int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); | 52 | + FIELD_EX32(s->cr2, CR2, STOP)); |
251 | + int64_t ticks = cycles; | ||
252 | + int64_t ns; | ||
253 | + | ||
254 | + ticks *= prescaler; | ||
255 | + ns = clock_ticks_to_ns(clk, ticks); | ||
256 | + ns += now; | ||
257 | + timer_mod(timer, ns); | ||
258 | +} | ||
259 | + | ||
260 | +static void npcm7xx_adc_start_convert(NPCM7xxADCState *s) | ||
261 | +{ | ||
262 | + uint32_t prescaler = npcm7xx_adc_prescaler(s); | ||
263 | + | ||
264 | + npcm7xx_adc_start_timer(s->clock, &s->conv_timer, NPCM7XX_ADC_CONV_CYCLES, | ||
265 | + prescaler); | ||
266 | +} | ||
267 | + | ||
268 | +static void npcm7xx_adc_convert_done(void *opaque) | ||
269 | +{ | ||
270 | + NPCM7xxADCState *s = opaque; | ||
271 | + uint32_t input = NPCM7XX_ADC_CON_MUX(s->con); | ||
272 | + uint32_t ref = (s->con & NPCM7XX_ADC_CON_REFSEL) | ||
273 | + ? s->iref : s->vref; | ||
274 | + | ||
275 | + if (input >= NPCM7XX_ADC_NUM_INPUTS) { | ||
276 | + qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid input: %u\n", | ||
277 | + __func__, input); | ||
278 | + return; | ||
279 | + } | ||
280 | + s->data = npcm7xx_adc_convert(s->adci[input], ref); | ||
281 | + if (s->con & NPCM7XX_ADC_CON_INT_EN) { | ||
282 | + s->con |= NPCM7XX_ADC_CON_INT; | ||
283 | + qemu_irq_raise(s->irq); | ||
284 | + } | ||
285 | + s->con &= ~NPCM7XX_ADC_CON_CONV; | ||
286 | +} | ||
287 | + | ||
288 | +static void npcm7xx_adc_calibrate(NPCM7xxADCState *adc) | ||
289 | +{ | ||
290 | + adc->calibration_r_values[0] = npcm7xx_adc_convert(NPCM7XX_ADC_R0_INPUT, | ||
291 | + adc->iref); | ||
292 | + adc->calibration_r_values[1] = npcm7xx_adc_convert(NPCM7XX_ADC_R1_INPUT, | ||
293 | + adc->iref); | ||
294 | +} | ||
295 | + | ||
296 | +static void npcm7xx_adc_write_con(NPCM7xxADCState *s, uint32_t new_con) | ||
297 | +{ | ||
298 | + uint32_t old_con = s->con; | ||
299 | + | ||
300 | + /* Write ADC_INT to 1 to clear it */ | ||
301 | + if (new_con & NPCM7XX_ADC_CON_INT) { | ||
302 | + new_con &= ~NPCM7XX_ADC_CON_INT; | ||
303 | + qemu_irq_lower(s->irq); | ||
304 | + } else if (old_con & NPCM7XX_ADC_CON_INT) { | ||
305 | + new_con |= NPCM7XX_ADC_CON_INT; | ||
306 | + } | ||
307 | + | ||
308 | + s->con = new_con; | ||
309 | + | ||
310 | + if (s->con & NPCM7XX_ADC_CON_RST) { | ||
311 | + npcm7xx_adc_reset(s); | ||
312 | + return; | 53 | + return; |
313 | + } | 54 | + } |
314 | + | 55 | + |
315 | + if ((s->con & NPCM7XX_ADC_CON_EN)) { | 56 | + /* Select the length of the word */ |
316 | + if (s->con & NPCM7XX_ADC_CON_CONV) { | 57 | + switch ((FIELD_EX32(s->cr1, CR1, M1) << 1) | FIELD_EX32(s->cr1, CR1, M0)) { |
317 | + if (!(old_con & NPCM7XX_ADC_CON_CONV)) { | 58 | + case 0: |
318 | + npcm7xx_adc_start_convert(s); | 59 | + data_bits = 8; |
319 | + } | 60 | + break; |
320 | + } else { | 61 | + case 1: |
321 | + timer_del(&s->conv_timer); | 62 | + data_bits = 9; |
322 | + } | 63 | + break; |
64 | + case 2: | ||
65 | + data_bits = 7; | ||
66 | + break; | ||
67 | + default: | ||
68 | + qemu_log_mask(LOG_GUEST_ERROR, | ||
69 | + "UNDEFINED: invalid word length, CR1.M = 0b11"); | ||
70 | + return; | ||
323 | + } | 71 | + } |
72 | + | ||
73 | + /* Select the baud rate */ | ||
74 | + value = FIELD_EX32(s->brr, BRR, BRR); | ||
75 | + if (value < 16) { | ||
76 | + qemu_log_mask(LOG_GUEST_ERROR, | ||
77 | + "UNDEFINED: BRR less than 16: %u", value); | ||
78 | + return; | ||
79 | + } | ||
80 | + | ||
81 | + if (FIELD_EX32(s->cr1, CR1, OVER8) == 0) { | ||
82 | + /* | ||
83 | + * Oversampling by 16 | ||
84 | + * BRR = USARTDIV | ||
85 | + */ | ||
86 | + usart_div = value; | ||
87 | + } else { | ||
88 | + /* | ||
89 | + * Oversampling by 8 | ||
90 | + * - BRR[2:0] = USARTDIV[3:0] shifted 1 bit to the right. | ||
91 | + * - BRR[3] must be kept cleared. | ||
92 | + * - BRR[15:4] = USARTDIV[15:4] | ||
93 | + * - The frequency is multiplied by 2 | ||
94 | + */ | ||
95 | + usart_div = ((value & 0xFFF0) | ((value & 0x0007) << 1)) / 2; | ||
96 | + } | ||
97 | + | ||
98 | + speed = clock_get_hz(s->clk) / usart_div; | ||
99 | + | ||
100 | + ssp.speed = speed; | ||
101 | + ssp.parity = parity; | ||
102 | + ssp.data_bits = data_bits; | ||
103 | + ssp.stop_bits = stop_bits; | ||
104 | + | ||
105 | + qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp); | ||
106 | + | ||
107 | + trace_stm32l4x5_usart_update_params(speed, parity, data_bits, stop_bits); | ||
324 | +} | 108 | +} |
325 | + | 109 | + |
326 | +static uint64_t npcm7xx_adc_read(void *opaque, hwaddr offset, unsigned size) | 110 | static void stm32l4x5_usart_base_reset_hold(Object *obj, ResetType type) |
111 | { | ||
112 | Stm32l4x5UsartBaseState *s = STM32L4X5_USART_BASE(obj); | ||
113 | @@ -XXX,XX +XXX,XX @@ static void stm32l4x5_usart_base_write(void *opaque, hwaddr addr, | ||
114 | switch (addr) { | ||
115 | case A_CR1: | ||
116 | s->cr1 = value; | ||
117 | + stm32l4x5_update_params(s); | ||
118 | stm32l4x5_update_irq(s); | ||
119 | return; | ||
120 | case A_CR2: | ||
121 | s->cr2 = value; | ||
122 | + stm32l4x5_update_params(s); | ||
123 | return; | ||
124 | case A_CR3: | ||
125 | s->cr3 = value; | ||
126 | return; | ||
127 | case A_BRR: | ||
128 | s->brr = value; | ||
129 | + stm32l4x5_update_params(s); | ||
130 | return; | ||
131 | case A_GTPR: | ||
132 | s->gtpr = value; | ||
133 | @@ -XXX,XX +XXX,XX @@ static void stm32l4x5_usart_base_init(Object *obj) | ||
134 | s->clk = qdev_init_clock_in(DEVICE(s), "clk", NULL, s, 0); | ||
135 | } | ||
136 | |||
137 | +static int stm32l4x5_usart_base_post_load(void *opaque, int version_id) | ||
327 | +{ | 138 | +{ |
328 | + uint64_t value = 0; | 139 | + Stm32l4x5UsartBaseState *s = (Stm32l4x5UsartBaseState *)opaque; |
329 | + NPCM7xxADCState *s = opaque; | ||
330 | + | 140 | + |
331 | + switch (offset) { | 141 | + stm32l4x5_update_params(s); |
332 | + case A_NPCM7XX_ADC_CON: | 142 | + return 0; |
333 | + value = s->con; | ||
334 | + break; | ||
335 | + | ||
336 | + case A_NPCM7XX_ADC_DATA: | ||
337 | + value = s->data; | ||
338 | + break; | ||
339 | + | ||
340 | + default: | ||
341 | + qemu_log_mask(LOG_GUEST_ERROR, | ||
342 | + "%s: invalid offset 0x%04" HWADDR_PRIx "\n", | ||
343 | + __func__, offset); | ||
344 | + break; | ||
345 | + } | ||
346 | + | ||
347 | + trace_npcm7xx_adc_read(DEVICE(s)->canonical_path, offset, value); | ||
348 | + return value; | ||
349 | +} | 143 | +} |
350 | + | 144 | + |
351 | +static void npcm7xx_adc_write(void *opaque, hwaddr offset, uint64_t v, | 145 | static const VMStateDescription vmstate_stm32l4x5_usart_base = { |
352 | + unsigned size) | 146 | .name = TYPE_STM32L4X5_USART_BASE, |
353 | +{ | 147 | .version_id = 1, |
354 | + NPCM7xxADCState *s = opaque; | 148 | .minimum_version_id = 1, |
355 | + | 149 | + .post_load = stm32l4x5_usart_base_post_load, |
356 | + trace_npcm7xx_adc_write(DEVICE(s)->canonical_path, offset, v); | 150 | .fields = (VMStateField[]) { |
357 | + switch (offset) { | 151 | VMSTATE_UINT32(cr1, Stm32l4x5UsartBaseState), |
358 | + case A_NPCM7XX_ADC_CON: | 152 | VMSTATE_UINT32(cr2, Stm32l4x5UsartBaseState), |
359 | + npcm7xx_adc_write_con(s, v); | 153 | diff --git a/hw/char/trace-events b/hw/char/trace-events |
360 | + break; | ||
361 | + | ||
362 | + case A_NPCM7XX_ADC_DATA: | ||
363 | + qemu_log_mask(LOG_GUEST_ERROR, | ||
364 | + "%s: register @ 0x%04" HWADDR_PRIx " is read-only\n", | ||
365 | + __func__, offset); | ||
366 | + break; | ||
367 | + | ||
368 | + default: | ||
369 | + qemu_log_mask(LOG_GUEST_ERROR, | ||
370 | + "%s: invalid offset 0x%04" HWADDR_PRIx "\n", | ||
371 | + __func__, offset); | ||
372 | + break; | ||
373 | + } | ||
374 | + | ||
375 | +} | ||
376 | + | ||
377 | +static const struct MemoryRegionOps npcm7xx_adc_ops = { | ||
378 | + .read = npcm7xx_adc_read, | ||
379 | + .write = npcm7xx_adc_write, | ||
380 | + .endianness = DEVICE_LITTLE_ENDIAN, | ||
381 | + .valid = { | ||
382 | + .min_access_size = 4, | ||
383 | + .max_access_size = 4, | ||
384 | + .unaligned = false, | ||
385 | + }, | ||
386 | +}; | ||
387 | + | ||
388 | +static void npcm7xx_adc_enter_reset(Object *obj, ResetType type) | ||
389 | +{ | ||
390 | + NPCM7xxADCState *s = NPCM7XX_ADC(obj); | ||
391 | + | ||
392 | + npcm7xx_adc_reset(s); | ||
393 | +} | ||
394 | + | ||
395 | +static void npcm7xx_adc_hold_reset(Object *obj) | ||
396 | +{ | ||
397 | + NPCM7xxADCState *s = NPCM7XX_ADC(obj); | ||
398 | + | ||
399 | + qemu_irq_lower(s->irq); | ||
400 | +} | ||
401 | + | ||
402 | +static void npcm7xx_adc_init(Object *obj) | ||
403 | +{ | ||
404 | + NPCM7xxADCState *s = NPCM7XX_ADC(obj); | ||
405 | + SysBusDevice *sbd = SYS_BUS_DEVICE(obj); | ||
406 | + int i; | ||
407 | + | ||
408 | + sysbus_init_irq(sbd, &s->irq); | ||
409 | + | ||
410 | + timer_init_ns(&s->conv_timer, QEMU_CLOCK_VIRTUAL, | ||
411 | + npcm7xx_adc_convert_done, s); | ||
412 | + memory_region_init_io(&s->iomem, obj, &npcm7xx_adc_ops, s, | ||
413 | + TYPE_NPCM7XX_ADC, 4 * KiB); | ||
414 | + sysbus_init_mmio(sbd, &s->iomem); | ||
415 | + s->clock = qdev_init_clock_in(DEVICE(s), "clock", NULL, NULL); | ||
416 | + | ||
417 | + for (i = 0; i < NPCM7XX_ADC_NUM_INPUTS; ++i) { | ||
418 | + object_property_add_uint32_ptr(obj, "adci[*]", | ||
419 | + &s->adci[i], OBJ_PROP_FLAG_WRITE); | ||
420 | + } | ||
421 | + object_property_add_uint32_ptr(obj, "vref", | ||
422 | + &s->vref, OBJ_PROP_FLAG_WRITE); | ||
423 | + npcm7xx_adc_calibrate(s); | ||
424 | +} | ||
425 | + | ||
426 | +static const VMStateDescription vmstate_npcm7xx_adc = { | ||
427 | + .name = "npcm7xx-adc", | ||
428 | + .version_id = 0, | ||
429 | + .minimum_version_id = 0, | ||
430 | + .fields = (VMStateField[]) { | ||
431 | + VMSTATE_TIMER(conv_timer, NPCM7xxADCState), | ||
432 | + VMSTATE_UINT32(con, NPCM7xxADCState), | ||
433 | + VMSTATE_UINT32(data, NPCM7xxADCState), | ||
434 | + VMSTATE_CLOCK(clock, NPCM7xxADCState), | ||
435 | + VMSTATE_UINT32_ARRAY(adci, NPCM7xxADCState, NPCM7XX_ADC_NUM_INPUTS), | ||
436 | + VMSTATE_UINT32(vref, NPCM7xxADCState), | ||
437 | + VMSTATE_UINT32(iref, NPCM7xxADCState), | ||
438 | + VMSTATE_UINT16_ARRAY(calibration_r_values, NPCM7xxADCState, | ||
439 | + NPCM7XX_ADC_NUM_CALIB), | ||
440 | + VMSTATE_END_OF_LIST(), | ||
441 | + }, | ||
442 | +}; | ||
443 | + | ||
444 | +static Property npcm7xx_timer_properties[] = { | ||
445 | + DEFINE_PROP_UINT32("iref", NPCM7xxADCState, iref, NPCM7XX_ADC_DEFAULT_IREF), | ||
446 | + DEFINE_PROP_END_OF_LIST(), | ||
447 | +}; | ||
448 | + | ||
449 | +static void npcm7xx_adc_class_init(ObjectClass *klass, void *data) | ||
450 | +{ | ||
451 | + ResettableClass *rc = RESETTABLE_CLASS(klass); | ||
452 | + DeviceClass *dc = DEVICE_CLASS(klass); | ||
453 | + | ||
454 | + dc->desc = "NPCM7xx ADC Module"; | ||
455 | + dc->vmsd = &vmstate_npcm7xx_adc; | ||
456 | + rc->phases.enter = npcm7xx_adc_enter_reset; | ||
457 | + rc->phases.hold = npcm7xx_adc_hold_reset; | ||
458 | + | ||
459 | + device_class_set_props(dc, npcm7xx_timer_properties); | ||
460 | +} | ||
461 | + | ||
462 | +static const TypeInfo npcm7xx_adc_info = { | ||
463 | + .name = TYPE_NPCM7XX_ADC, | ||
464 | + .parent = TYPE_SYS_BUS_DEVICE, | ||
465 | + .instance_size = sizeof(NPCM7xxADCState), | ||
466 | + .class_init = npcm7xx_adc_class_init, | ||
467 | + .instance_init = npcm7xx_adc_init, | ||
468 | +}; | ||
469 | + | ||
470 | +static void npcm7xx_adc_register_types(void) | ||
471 | +{ | ||
472 | + type_register_static(&npcm7xx_adc_info); | ||
473 | +} | ||
474 | + | ||
475 | +type_init(npcm7xx_adc_register_types); | ||
476 | diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c | ||
477 | index XXXXXXX..XXXXXXX 100644 | 154 | index XXXXXXX..XXXXXXX 100644 |
478 | --- a/hw/arm/npcm7xx.c | 155 | --- a/hw/char/trace-events |
479 | +++ b/hw/arm/npcm7xx.c | 156 | +++ b/hw/char/trace-events |
480 | @@ -XXX,XX +XXX,XX @@ | 157 | @@ -XXX,XX +XXX,XX @@ stm32l4x5_usart_irq_raised(uint32_t reg) "USART: IRQ raised: 0x%08"PRIx32 |
481 | #define NPCM7XX_EHCI_BA (0xf0806000) | 158 | stm32l4x5_usart_irq_lowered(void) "USART: IRQ lowered" |
482 | #define NPCM7XX_OHCI_BA (0xf0807000) | 159 | stm32l4x5_usart_overrun_detected(uint8_t current, uint8_t received) "USART: Overrun detected, RDR='0x%x', received 0x%x" |
483 | 160 | stm32l4x5_usart_receiver_not_enabled(uint8_t ue_bit, uint8_t re_bit) "USART: Receiver not enabled, UE=0x%x, RE=0x%x" | |
484 | +/* ADC Module */ | 161 | +stm32l4x5_usart_update_params(int speed, uint8_t parity, int data, int stop) "USART: speed: %d, parity: %c, data bits: %d, stop bits: %d" |
485 | +#define NPCM7XX_ADC_BA (0xf000c000) | 162 | |
486 | + | 163 | # xen_console.c |
487 | /* Internal AHB SRAM */ | 164 | xen_console_connect(unsigned int idx, unsigned int ring_ref, unsigned int port, unsigned int limit) "idx %u ring_ref %u port %u limit %u" |
488 | #define NPCM7XX_RAM3_BA (0xc0008000) | ||
489 | #define NPCM7XX_RAM3_SZ (4 * KiB) | ||
490 | @@ -XXX,XX +XXX,XX @@ | ||
491 | #define NPCM7XX_ROM_BA (0xffff0000) | ||
492 | #define NPCM7XX_ROM_SZ (64 * KiB) | ||
493 | |||
494 | + | ||
495 | /* Clock configuration values to be fixed up when bypassing bootloader */ | ||
496 | |||
497 | /* Run PLL1 at 1600 MHz */ | ||
498 | @@ -XXX,XX +XXX,XX @@ | ||
499 | * interrupts. | ||
500 | */ | ||
501 | enum NPCM7xxInterrupt { | ||
502 | + NPCM7XX_ADC_IRQ = 0, | ||
503 | NPCM7XX_UART0_IRQ = 2, | ||
504 | NPCM7XX_UART1_IRQ, | ||
505 | NPCM7XX_UART2_IRQ, | ||
506 | @@ -XXX,XX +XXX,XX @@ static void npcm7xx_init_fuses(NPCM7xxState *s) | ||
507 | sizeof(value)); | ||
508 | } | ||
509 | |||
510 | +static void npcm7xx_write_adc_calibration(NPCM7xxState *s) | ||
511 | +{ | ||
512 | + /* Both ADC and the fuse array must have realized. */ | ||
513 | + QEMU_BUILD_BUG_ON(sizeof(s->adc.calibration_r_values) != 4); | ||
514 | + npcm7xx_otp_array_write(&s->fuse_array, s->adc.calibration_r_values, | ||
515 | + NPCM7XX_FUSE_ADC_CALIB, sizeof(s->adc.calibration_r_values)); | ||
516 | +} | ||
517 | + | ||
518 | static qemu_irq npcm7xx_irq(NPCM7xxState *s, int n) | ||
519 | { | ||
520 | return qdev_get_gpio_in(DEVICE(&s->a9mpcore), n); | ||
521 | @@ -XXX,XX +XXX,XX @@ static void npcm7xx_init(Object *obj) | ||
522 | TYPE_NPCM7XX_FUSE_ARRAY); | ||
523 | object_initialize_child(obj, "mc", &s->mc, TYPE_NPCM7XX_MC); | ||
524 | object_initialize_child(obj, "rng", &s->rng, TYPE_NPCM7XX_RNG); | ||
525 | + object_initialize_child(obj, "adc", &s->adc, TYPE_NPCM7XX_ADC); | ||
526 | |||
527 | for (i = 0; i < ARRAY_SIZE(s->tim); i++) { | ||
528 | object_initialize_child(obj, "tim[*]", &s->tim[i], TYPE_NPCM7XX_TIMER); | ||
529 | @@ -XXX,XX +XXX,XX @@ static void npcm7xx_realize(DeviceState *dev, Error **errp) | ||
530 | sysbus_realize(SYS_BUS_DEVICE(&s->mc), &error_abort); | ||
531 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->mc), 0, NPCM7XX_MC_BA); | ||
532 | |||
533 | + /* ADC Modules. Cannot fail. */ | ||
534 | + qdev_connect_clock_in(DEVICE(&s->adc), "clock", qdev_get_clock_out( | ||
535 | + DEVICE(&s->clk), "adc-clock")); | ||
536 | + sysbus_realize(SYS_BUS_DEVICE(&s->adc), &error_abort); | ||
537 | + sysbus_mmio_map(SYS_BUS_DEVICE(&s->adc), 0, NPCM7XX_ADC_BA); | ||
538 | + sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0, | ||
539 | + npcm7xx_irq(s, NPCM7XX_ADC_IRQ)); | ||
540 | + npcm7xx_write_adc_calibration(s); | ||
541 | + | ||
542 | /* Timer Modules (TIM). Cannot fail. */ | ||
543 | QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_tim_addr) != ARRAY_SIZE(s->tim)); | ||
544 | for (i = 0; i < ARRAY_SIZE(s->tim); i++) { | ||
545 | @@ -XXX,XX +XXX,XX @@ static void npcm7xx_realize(DeviceState *dev, Error **errp) | ||
546 | create_unimplemented_device("npcm7xx.vdmx", 0xe0800000, 4 * KiB); | ||
547 | create_unimplemented_device("npcm7xx.pcierc", 0xe1000000, 64 * KiB); | ||
548 | create_unimplemented_device("npcm7xx.kcs", 0xf0007000, 4 * KiB); | ||
549 | - create_unimplemented_device("npcm7xx.adc", 0xf000c000, 4 * KiB); | ||
550 | create_unimplemented_device("npcm7xx.gfxi", 0xf000e000, 4 * KiB); | ||
551 | create_unimplemented_device("npcm7xx.gpio[0]", 0xf0010000, 4 * KiB); | ||
552 | create_unimplemented_device("npcm7xx.gpio[1]", 0xf0011000, 4 * KiB); | ||
553 | diff --git a/tests/qtest/npcm7xx_adc-test.c b/tests/qtest/npcm7xx_adc-test.c | ||
554 | new file mode 100644 | ||
555 | index XXXXXXX..XXXXXXX | ||
556 | --- /dev/null | ||
557 | +++ b/tests/qtest/npcm7xx_adc-test.c | ||
558 | @@ -XXX,XX +XXX,XX @@ | ||
559 | +/* | ||
560 | + * QTests for Nuvoton NPCM7xx ADCModules. | ||
561 | + * | ||
562 | + * Copyright 2020 Google LLC | ||
563 | + * | ||
564 | + * This program is free software; you can redistribute it and/or modify it | ||
565 | + * under the terms of the GNU General Public License as published by the | ||
566 | + * Free Software Foundation; either version 2 of the License, or | ||
567 | + * (at your option) any later version. | ||
568 | + * | ||
569 | + * This program is distributed in the hope that it will be useful, but WITHOUT | ||
570 | + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
571 | + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | ||
572 | + * for more details. | ||
573 | + */ | ||
574 | + | ||
575 | +#include "qemu/osdep.h" | ||
576 | +#include "qemu/bitops.h" | ||
577 | +#include "qemu/timer.h" | ||
578 | +#include "libqos/libqtest.h" | ||
579 | +#include "qapi/qmp/qdict.h" | ||
580 | + | ||
581 | +#define REF_HZ (25000000) | ||
582 | + | ||
583 | +#define CON_OFFSET 0x0 | ||
584 | +#define DATA_OFFSET 0x4 | ||
585 | + | ||
586 | +#define NUM_INPUTS 8 | ||
587 | +#define DEFAULT_IREF 2000000 | ||
588 | +#define CONV_CYCLES 20 | ||
589 | +#define RESET_CYCLES 10 | ||
590 | +#define R0_INPUT 500000 | ||
591 | +#define R1_INPUT 1500000 | ||
592 | +#define MAX_RESULT 1023 | ||
593 | + | ||
594 | +#define DEFAULT_CLKDIV 5 | ||
595 | + | ||
596 | +#define FUSE_ARRAY_BA 0xf018a000 | ||
597 | +#define FCTL_OFFSET 0x14 | ||
598 | +#define FST_OFFSET 0x0 | ||
599 | +#define FADDR_OFFSET 0x4 | ||
600 | +#define FDATA_OFFSET 0x8 | ||
601 | +#define ADC_CALIB_ADDR 24 | ||
602 | +#define FUSE_READ 0x2 | ||
603 | + | ||
604 | +/* Register field definitions. */ | ||
605 | +#define CON_MUX(rv) ((rv) << 24) | ||
606 | +#define CON_INT_EN BIT(21) | ||
607 | +#define CON_REFSEL BIT(19) | ||
608 | +#define CON_INT BIT(18) | ||
609 | +#define CON_EN BIT(17) | ||
610 | +#define CON_RST BIT(16) | ||
611 | +#define CON_CONV BIT(14) | ||
612 | +#define CON_DIV(rv) extract32(rv, 1, 8) | ||
613 | + | ||
614 | +#define FST_RDST BIT(1) | ||
615 | +#define FDATA_MASK 0xff | ||
616 | + | ||
617 | +#define MAX_ERROR 10000 | ||
618 | +#define MIN_CALIB_INPUT 100000 | ||
619 | +#define MAX_CALIB_INPUT 1800000 | ||
620 | + | ||
621 | +static const uint32_t input_list[] = { | ||
622 | + 100000, | ||
623 | + 500000, | ||
624 | + 1000000, | ||
625 | + 1500000, | ||
626 | + 1800000, | ||
627 | + 2000000, | ||
628 | +}; | ||
629 | + | ||
630 | +static const uint32_t vref_list[] = { | ||
631 | + 2000000, | ||
632 | + 2200000, | ||
633 | + 2500000, | ||
634 | +}; | ||
635 | + | ||
636 | +static const uint32_t iref_list[] = { | ||
637 | + 1800000, | ||
638 | + 1900000, | ||
639 | + 2000000, | ||
640 | + 2100000, | ||
641 | + 2200000, | ||
642 | +}; | ||
643 | + | ||
644 | +static const uint32_t div_list[] = {0, 1, 3, 7, 15}; | ||
645 | + | ||
646 | +typedef struct ADC { | ||
647 | + int irq; | ||
648 | + uint64_t base_addr; | ||
649 | +} ADC; | ||
650 | + | ||
651 | +ADC adc = { | ||
652 | + .irq = 0, | ||
653 | + .base_addr = 0xf000c000 | ||
654 | +}; | ||
655 | + | ||
656 | +static uint32_t adc_read_con(QTestState *qts, const ADC *adc) | ||
657 | +{ | ||
658 | + return qtest_readl(qts, adc->base_addr + CON_OFFSET); | ||
659 | +} | ||
660 | + | ||
661 | +static void adc_write_con(QTestState *qts, const ADC *adc, uint32_t value) | ||
662 | +{ | ||
663 | + qtest_writel(qts, adc->base_addr + CON_OFFSET, value); | ||
664 | +} | ||
665 | + | ||
666 | +static uint32_t adc_read_data(QTestState *qts, const ADC *adc) | ||
667 | +{ | ||
668 | + return qtest_readl(qts, adc->base_addr + DATA_OFFSET); | ||
669 | +} | ||
670 | + | ||
671 | +static uint32_t adc_calibrate(uint32_t measured, uint32_t *rv) | ||
672 | +{ | ||
673 | + return R0_INPUT + (R1_INPUT - R0_INPUT) * (int32_t)(measured - rv[0]) | ||
674 | + / (int32_t)(rv[1] - rv[0]); | ||
675 | +} | ||
676 | + | ||
677 | +static void adc_qom_set(QTestState *qts, const ADC *adc, | ||
678 | + const char *name, uint32_t value) | ||
679 | +{ | ||
680 | + QDict *response; | ||
681 | + const char *path = "/machine/soc/adc"; | ||
682 | + | ||
683 | + g_test_message("Setting properties %s of %s with value %u", | ||
684 | + name, path, value); | ||
685 | + response = qtest_qmp(qts, "{ 'execute': 'qom-set'," | ||
686 | + " 'arguments': { 'path': %s, 'property': %s, 'value': %u}}", | ||
687 | + path, name, value); | ||
688 | + /* The qom set message returns successfully. */ | ||
689 | + g_assert_true(qdict_haskey(response, "return")); | ||
690 | +} | ||
691 | + | ||
692 | +static void adc_write_input(QTestState *qts, const ADC *adc, | ||
693 | + uint32_t index, uint32_t value) | ||
694 | +{ | ||
695 | + char name[100]; | ||
696 | + | ||
697 | + sprintf(name, "adci[%u]", index); | ||
698 | + adc_qom_set(qts, adc, name, value); | ||
699 | +} | ||
700 | + | ||
701 | +static void adc_write_vref(QTestState *qts, const ADC *adc, uint32_t value) | ||
702 | +{ | ||
703 | + adc_qom_set(qts, adc, "vref", value); | ||
704 | +} | ||
705 | + | ||
706 | +static uint32_t adc_calculate_output(uint32_t input, uint32_t ref) | ||
707 | +{ | ||
708 | + uint32_t output; | ||
709 | + | ||
710 | + g_assert_cmpuint(input, <=, ref); | ||
711 | + output = (input * (MAX_RESULT + 1)) / ref; | ||
712 | + if (output > MAX_RESULT) { | ||
713 | + output = MAX_RESULT; | ||
714 | + } | ||
715 | + | ||
716 | + return output; | ||
717 | +} | ||
718 | + | ||
719 | +static uint32_t adc_prescaler(QTestState *qts, const ADC *adc) | ||
720 | +{ | ||
721 | + uint32_t div = extract32(adc_read_con(qts, adc), 1, 8); | ||
722 | + | ||
723 | + return 2 * (div + 1); | ||
724 | +} | ||
725 | + | ||
726 | +static int64_t adc_calculate_steps(uint32_t cycles, uint32_t prescale, | ||
727 | + uint32_t clkdiv) | ||
728 | +{ | ||
729 | + return (NANOSECONDS_PER_SECOND / (REF_HZ >> clkdiv)) * cycles * prescale; | ||
730 | +} | ||
731 | + | ||
732 | +static void adc_wait_conv_finished(QTestState *qts, const ADC *adc, | ||
733 | + uint32_t clkdiv) | ||
734 | +{ | ||
735 | + uint32_t prescaler = adc_prescaler(qts, adc); | ||
736 | + | ||
737 | + /* | ||
738 | + * ADC should takes roughly 20 cycles to convert one sample. So we assert it | ||
739 | + * should take 10~30 cycles here. | ||
740 | + */ | ||
741 | + qtest_clock_step(qts, adc_calculate_steps(CONV_CYCLES / 2, prescaler, | ||
742 | + clkdiv)); | ||
743 | + /* ADC is still converting. */ | ||
744 | + g_assert_true(adc_read_con(qts, adc) & CON_CONV); | ||
745 | + qtest_clock_step(qts, adc_calculate_steps(CONV_CYCLES, prescaler, clkdiv)); | ||
746 | + /* ADC has finished conversion. */ | ||
747 | + g_assert_false(adc_read_con(qts, adc) & CON_CONV); | ||
748 | +} | ||
749 | + | ||
750 | +/* Check ADC can be reset to default value. */ | ||
751 | +static void test_init(gconstpointer adc_p) | ||
752 | +{ | ||
753 | + const ADC *adc = adc_p; | ||
754 | + | ||
755 | + QTestState *qts = qtest_init("-machine quanta-gsj"); | ||
756 | + adc_write_con(qts, adc, CON_REFSEL | CON_INT); | ||
757 | + g_assert_cmphex(adc_read_con(qts, adc), ==, CON_REFSEL); | ||
758 | + qtest_quit(qts); | ||
759 | +} | ||
760 | + | ||
761 | +/* Check ADC can convert from an internal reference. */ | ||
762 | +static void test_convert_internal(gconstpointer adc_p) | ||
763 | +{ | ||
764 | + const ADC *adc = adc_p; | ||
765 | + uint32_t index, input, output, expected_output; | ||
766 | + QTestState *qts = qtest_init("-machine quanta-gsj"); | ||
767 | + qtest_irq_intercept_in(qts, "/machine/soc/a9mpcore/gic"); | ||
768 | + | ||
769 | + for (index = 0; index < NUM_INPUTS; ++index) { | ||
770 | + for (size_t i = 0; i < ARRAY_SIZE(input_list); ++i) { | ||
771 | + input = input_list[i]; | ||
772 | + expected_output = adc_calculate_output(input, DEFAULT_IREF); | ||
773 | + | ||
774 | + adc_write_input(qts, adc, index, input); | ||
775 | + adc_write_con(qts, adc, CON_MUX(index) | CON_REFSEL | CON_INT | | ||
776 | + CON_EN | CON_CONV); | ||
777 | + adc_wait_conv_finished(qts, adc, DEFAULT_CLKDIV); | ||
778 | + g_assert_cmphex(adc_read_con(qts, adc), ==, CON_MUX(index) | | ||
779 | + CON_REFSEL | CON_EN); | ||
780 | + g_assert_false(qtest_get_irq(qts, adc->irq)); | ||
781 | + output = adc_read_data(qts, adc); | ||
782 | + g_assert_cmpuint(output, ==, expected_output); | ||
783 | + } | ||
784 | + } | ||
785 | + | ||
786 | + qtest_quit(qts); | ||
787 | +} | ||
788 | + | ||
789 | +/* Check ADC can convert from an external reference. */ | ||
790 | +static void test_convert_external(gconstpointer adc_p) | ||
791 | +{ | ||
792 | + const ADC *adc = adc_p; | ||
793 | + uint32_t index, input, vref, output, expected_output; | ||
794 | + QTestState *qts = qtest_init("-machine quanta-gsj"); | ||
795 | + qtest_irq_intercept_in(qts, "/machine/soc/a9mpcore/gic"); | ||
796 | + | ||
797 | + for (index = 0; index < NUM_INPUTS; ++index) { | ||
798 | + for (size_t i = 0; i < ARRAY_SIZE(input_list); ++i) { | ||
799 | + for (size_t j = 0; j < ARRAY_SIZE(vref_list); ++j) { | ||
800 | + input = input_list[i]; | ||
801 | + vref = vref_list[j]; | ||
802 | + expected_output = adc_calculate_output(input, vref); | ||
803 | + | ||
804 | + adc_write_input(qts, adc, index, input); | ||
805 | + adc_write_vref(qts, adc, vref); | ||
806 | + adc_write_con(qts, adc, CON_MUX(index) | CON_INT | CON_EN | | ||
807 | + CON_CONV); | ||
808 | + adc_wait_conv_finished(qts, adc, DEFAULT_CLKDIV); | ||
809 | + g_assert_cmphex(adc_read_con(qts, adc), ==, | ||
810 | + CON_MUX(index) | CON_EN); | ||
811 | + g_assert_false(qtest_get_irq(qts, adc->irq)); | ||
812 | + output = adc_read_data(qts, adc); | ||
813 | + g_assert_cmpuint(output, ==, expected_output); | ||
814 | + } | ||
815 | + } | ||
816 | + } | ||
817 | + | ||
818 | + qtest_quit(qts); | ||
819 | +} | ||
820 | + | ||
821 | +/* Check ADC interrupt files if and only if CON_INT_EN is set. */ | ||
822 | +static void test_interrupt(gconstpointer adc_p) | ||
823 | +{ | ||
824 | + const ADC *adc = adc_p; | ||
825 | + uint32_t index, input, output, expected_output; | ||
826 | + QTestState *qts = qtest_init("-machine quanta-gsj"); | ||
827 | + | ||
828 | + index = 1; | ||
829 | + input = input_list[1]; | ||
830 | + expected_output = adc_calculate_output(input, DEFAULT_IREF); | ||
831 | + | ||
832 | + qtest_irq_intercept_in(qts, "/machine/soc/a9mpcore/gic"); | ||
833 | + adc_write_input(qts, adc, index, input); | ||
834 | + g_assert_false(qtest_get_irq(qts, adc->irq)); | ||
835 | + adc_write_con(qts, adc, CON_MUX(index) | CON_INT_EN | CON_REFSEL | CON_INT | ||
836 | + | CON_EN | CON_CONV); | ||
837 | + adc_wait_conv_finished(qts, adc, DEFAULT_CLKDIV); | ||
838 | + g_assert_cmphex(adc_read_con(qts, adc), ==, CON_MUX(index) | CON_INT_EN | ||
839 | + | CON_REFSEL | CON_INT | CON_EN); | ||
840 | + g_assert_true(qtest_get_irq(qts, adc->irq)); | ||
841 | + output = adc_read_data(qts, adc); | ||
842 | + g_assert_cmpuint(output, ==, expected_output); | ||
843 | + | ||
844 | + qtest_quit(qts); | ||
845 | +} | ||
846 | + | ||
847 | +/* Check ADC is reset after setting ADC_RST for 10 ADC cycles. */ | ||
848 | +static void test_reset(gconstpointer adc_p) | ||
849 | +{ | ||
850 | + const ADC *adc = adc_p; | ||
851 | + QTestState *qts = qtest_init("-machine quanta-gsj"); | ||
852 | + | ||
853 | + for (size_t i = 0; i < ARRAY_SIZE(div_list); ++i) { | ||
854 | + uint32_t div = div_list[i]; | ||
855 | + | ||
856 | + adc_write_con(qts, adc, CON_INT | CON_EN | CON_RST | CON_DIV(div)); | ||
857 | + qtest_clock_step(qts, adc_calculate_steps(RESET_CYCLES, | ||
858 | + adc_prescaler(qts, adc), DEFAULT_CLKDIV)); | ||
859 | + g_assert_false(adc_read_con(qts, adc) & CON_EN); | ||
860 | + } | ||
861 | + qtest_quit(qts); | ||
862 | +} | ||
863 | + | ||
864 | +/* Check ADC Calibration works as desired. */ | ||
865 | +static void test_calibrate(gconstpointer adc_p) | ||
866 | +{ | ||
867 | + int i, j; | ||
868 | + const ADC *adc = adc_p; | ||
869 | + | ||
870 | + for (j = 0; j < ARRAY_SIZE(iref_list); ++j) { | ||
871 | + uint32_t iref = iref_list[j]; | ||
872 | + uint32_t expected_rv[] = { | ||
873 | + adc_calculate_output(R0_INPUT, iref), | ||
874 | + adc_calculate_output(R1_INPUT, iref), | ||
875 | + }; | ||
876 | + char buf[100]; | ||
877 | + QTestState *qts; | ||
878 | + | ||
879 | + sprintf(buf, "-machine quanta-gsj -global npcm7xx-adc.iref=%u", iref); | ||
880 | + qts = qtest_init(buf); | ||
881 | + | ||
882 | + /* Check the converted value is correct using the calibration value. */ | ||
883 | + for (i = 0; i < ARRAY_SIZE(input_list); ++i) { | ||
884 | + uint32_t input; | ||
885 | + uint32_t output; | ||
886 | + uint32_t expected_output; | ||
887 | + uint32_t calibrated_voltage; | ||
888 | + uint32_t index = 0; | ||
889 | + | ||
890 | + input = input_list[i]; | ||
891 | + /* Calibration only works for input range 0.1V ~ 1.8V. */ | ||
892 | + if (input < MIN_CALIB_INPUT || input > MAX_CALIB_INPUT) { | ||
893 | + continue; | ||
894 | + } | ||
895 | + expected_output = adc_calculate_output(input, iref); | ||
896 | + | ||
897 | + adc_write_input(qts, adc, index, input); | ||
898 | + adc_write_con(qts, adc, CON_MUX(index) | CON_REFSEL | CON_INT | | ||
899 | + CON_EN | CON_CONV); | ||
900 | + adc_wait_conv_finished(qts, adc, DEFAULT_CLKDIV); | ||
901 | + g_assert_cmphex(adc_read_con(qts, adc), ==, | ||
902 | + CON_REFSEL | CON_MUX(index) | CON_EN); | ||
903 | + output = adc_read_data(qts, adc); | ||
904 | + g_assert_cmpuint(output, ==, expected_output); | ||
905 | + | ||
906 | + calibrated_voltage = adc_calibrate(output, expected_rv); | ||
907 | + g_assert_cmpuint(calibrated_voltage, >, input - MAX_ERROR); | ||
908 | + g_assert_cmpuint(calibrated_voltage, <, input + MAX_ERROR); | ||
909 | + } | ||
910 | + | ||
911 | + qtest_quit(qts); | ||
912 | + } | ||
913 | +} | ||
914 | + | ||
915 | +static void adc_add_test(const char *name, const ADC* wd, | ||
916 | + GTestDataFunc fn) | ||
917 | +{ | ||
918 | + g_autofree char *full_name = g_strdup_printf("npcm7xx_adc/%s", name); | ||
919 | + qtest_add_data_func(full_name, wd, fn); | ||
920 | +} | ||
921 | +#define add_test(name, td) adc_add_test(#name, td, test_##name) | ||
922 | + | ||
923 | +int main(int argc, char **argv) | ||
924 | +{ | ||
925 | + g_test_init(&argc, &argv, NULL); | ||
926 | + | ||
927 | + add_test(init, &adc); | ||
928 | + add_test(convert_internal, &adc); | ||
929 | + add_test(convert_external, &adc); | ||
930 | + add_test(interrupt, &adc); | ||
931 | + add_test(reset, &adc); | ||
932 | + add_test(calibrate, &adc); | ||
933 | + | ||
934 | + return g_test_run(); | ||
935 | +} | ||
936 | diff --git a/hw/adc/meson.build b/hw/adc/meson.build | ||
937 | index XXXXXXX..XXXXXXX 100644 | ||
938 | --- a/hw/adc/meson.build | ||
939 | +++ b/hw/adc/meson.build | ||
940 | @@ -1 +1,2 @@ | ||
941 | softmmu_ss.add(when: 'CONFIG_STM32F2XX_ADC', if_true: files('stm32f2xx_adc.c')) | ||
942 | +softmmu_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx_adc.c')) | ||
943 | diff --git a/hw/adc/trace-events b/hw/adc/trace-events | ||
944 | new file mode 100644 | ||
945 | index XXXXXXX..XXXXXXX | ||
946 | --- /dev/null | ||
947 | +++ b/hw/adc/trace-events | ||
948 | @@ -XXX,XX +XXX,XX @@ | ||
949 | +# See docs/devel/tracing.txt for syntax documentation. | ||
950 | + | ||
951 | +# npcm7xx_adc.c | ||
952 | +npcm7xx_adc_read(const char *id, uint64_t offset, uint32_t value) " %s offset: 0x%04" PRIx64 " value 0x%04" PRIx32 | ||
953 | +npcm7xx_adc_write(const char *id, uint64_t offset, uint32_t value) "%s offset: 0x%04" PRIx64 " value 0x%04" PRIx32 | ||
954 | diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build | ||
955 | index XXXXXXX..XXXXXXX 100644 | ||
956 | --- a/tests/qtest/meson.build | ||
957 | +++ b/tests/qtest/meson.build | ||
958 | @@ -XXX,XX +XXX,XX @@ qtests_sparc64 = \ | ||
959 | ['prom-env-test', 'boot-serial-test'] | ||
960 | |||
961 | qtests_npcm7xx = \ | ||
962 | - ['npcm7xx_gpio-test', | ||
963 | + ['npcm7xx_adc-test', | ||
964 | + 'npcm7xx_gpio-test', | ||
965 | 'npcm7xx_rng-test', | ||
966 | 'npcm7xx_timer-test', | ||
967 | 'npcm7xx_watchdog_timer-test'] | ||
968 | -- | 165 | -- |
969 | 2.20.1 | 166 | 2.34.1 |
970 | 167 | ||
971 | 168 | diff view generated by jsdifflib |
1 | From: Hao Wu <wuhaotsh@google.com> | 1 | From: Arnaud Minier <arnaud.minier@telecom-paris.fr> |
---|---|---|---|
2 | 2 | ||
3 | This patch allows NPCM7XX CLK module to compute clocks that are used by | 3 | Add the USART to the SoC and connect it to the other implemented devices. |
4 | other NPCM7XX modules. | 4 | |
5 | 5 | Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr> | |
6 | Add a new struct NPCM7xxClockConverterState which represents a | 6 | Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr> |
7 | single converter. Each clock converter in CLK module represents one | ||
8 | converter in NPCM7XX CLK Module(PLL, SEL or Divider). Each converter | ||
9 | takes one or more input clocks and converts them into one output clock. | ||
10 | They form a clock hierarchy in the CLK module and are responsible for | ||
11 | outputing clocks for various other modules in an NPCM7XX SoC. | ||
12 | |||
13 | Each converter has a function pointer called "convert" which represents | ||
14 | the unique logic for that converter. | ||
15 | |||
16 | The clock contains two initialization information: ConverterInitInfo and | ||
17 | ConverterConnectionInfo. They represent the vertices and edges in the | ||
18 | clock diagram respectively. | ||
19 | |||
20 | Reviewed-by: Havard Skinnemoen <hskinnemoen@google.com> | ||
21 | Reviewed-by: Tyrone Ting <kfting@nuvoton.com> | ||
22 | Signed-off-by: Hao Wu <wuhaotsh@google.com> | ||
23 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
24 | Message-id: 20210108190945.949196-2-wuhaotsh@google.com | 8 | Message-id: 20240329174402.60382-5-arnaud.minier@telecom-paris.fr |
9 | [PMM: fixed a few checkpatch nits] | ||
25 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
26 | --- | 11 | --- |
27 | include/hw/misc/npcm7xx_clk.h | 140 +++++- | 12 | docs/system/arm/b-l475e-iot01a.rst | 2 +- |
28 | hw/misc/npcm7xx_clk.c | 805 +++++++++++++++++++++++++++++++++- | 13 | include/hw/arm/stm32l4x5_soc.h | 7 +++ |
29 | 2 files changed, 932 insertions(+), 13 deletions(-) | 14 | hw/arm/stm32l4x5_soc.c | 83 +++++++++++++++++++++++++++--- |
30 | 15 | hw/arm/Kconfig | 1 + | |
31 | diff --git a/include/hw/misc/npcm7xx_clk.h b/include/hw/misc/npcm7xx_clk.h | 16 | 4 files changed, 86 insertions(+), 7 deletions(-) |
32 | index XXXXXXX..XXXXXXX 100644 | 17 | |
33 | --- a/include/hw/misc/npcm7xx_clk.h | 18 | diff --git a/docs/system/arm/b-l475e-iot01a.rst b/docs/system/arm/b-l475e-iot01a.rst |
34 | +++ b/include/hw/misc/npcm7xx_clk.h | 19 | index XXXXXXX..XXXXXXX 100644 |
20 | --- a/docs/system/arm/b-l475e-iot01a.rst | ||
21 | +++ b/docs/system/arm/b-l475e-iot01a.rst | ||
22 | @@ -XXX,XX +XXX,XX @@ Currently B-L475E-IOT01A machine's only supports the following devices: | ||
23 | - STM32L4x5 SYSCFG (System configuration controller) | ||
24 | - STM32L4x5 RCC (Reset and clock control) | ||
25 | - STM32L4x5 GPIOs (General-purpose I/Os) | ||
26 | +- STM32L4x5 USARTs, UARTs and LPUART (Serial ports) | ||
27 | |||
28 | Missing devices | ||
29 | """"""""""""""" | ||
30 | |||
31 | The B-L475E-IOT01A does *not* support the following devices: | ||
32 | |||
33 | -- Serial ports (UART) | ||
34 | - Analog to Digital Converter (ADC) | ||
35 | - SPI controller | ||
36 | - Timer controller (TIMER) | ||
37 | diff --git a/include/hw/arm/stm32l4x5_soc.h b/include/hw/arm/stm32l4x5_soc.h | ||
38 | index XXXXXXX..XXXXXXX 100644 | ||
39 | --- a/include/hw/arm/stm32l4x5_soc.h | ||
40 | +++ b/include/hw/arm/stm32l4x5_soc.h | ||
35 | @@ -XXX,XX +XXX,XX @@ | 41 | @@ -XXX,XX +XXX,XX @@ |
36 | #define NPCM7XX_CLK_H | 42 | #include "hw/misc/stm32l4x5_exti.h" |
37 | 43 | #include "hw/misc/stm32l4x5_rcc.h" | |
38 | #include "exec/memory.h" | 44 | #include "hw/gpio/stm32l4x5_gpio.h" |
39 | +#include "hw/clock.h" | 45 | +#include "hw/char/stm32l4x5_usart.h" |
40 | #include "hw/sysbus.h" | 46 | #include "qom/object.h" |
41 | 47 | ||
42 | /* | 48 | #define TYPE_STM32L4X5_SOC "stm32l4x5-soc" |
49 | @@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_TYPE(Stm32l4x5SocState, Stm32l4x5SocClass, STM32L4X5_SOC) | ||
50 | |||
51 | #define NUM_EXTI_OR_GATES 4 | ||
52 | |||
53 | +#define STM_NUM_USARTS 3 | ||
54 | +#define STM_NUM_UARTS 2 | ||
55 | + | ||
56 | struct Stm32l4x5SocState { | ||
57 | SysBusDevice parent_obj; | ||
58 | |||
59 | @@ -XXX,XX +XXX,XX @@ struct Stm32l4x5SocState { | ||
60 | Stm32l4x5SyscfgState syscfg; | ||
61 | Stm32l4x5RccState rcc; | ||
62 | Stm32l4x5GpioState gpio[NUM_GPIOS]; | ||
63 | + Stm32l4x5UsartBaseState usart[STM_NUM_USARTS]; | ||
64 | + Stm32l4x5UsartBaseState uart[STM_NUM_UARTS]; | ||
65 | + Stm32l4x5UsartBaseState lpuart; | ||
66 | |||
67 | MemoryRegion sram1; | ||
68 | MemoryRegion sram2; | ||
69 | diff --git a/hw/arm/stm32l4x5_soc.c b/hw/arm/stm32l4x5_soc.c | ||
70 | index XXXXXXX..XXXXXXX 100644 | ||
71 | --- a/hw/arm/stm32l4x5_soc.c | ||
72 | +++ b/hw/arm/stm32l4x5_soc.c | ||
43 | @@ -XXX,XX +XXX,XX @@ | 73 | @@ -XXX,XX +XXX,XX @@ |
44 | 74 | #include "sysemu/sysemu.h" | |
45 | #define NPCM7XX_WATCHDOG_RESET_GPIO_IN "npcm7xx-clk-watchdog-reset-gpio-in" | 75 | #include "hw/or-irq.h" |
46 | 76 | #include "hw/arm/stm32l4x5_soc.h" | |
47 | -typedef struct NPCM7xxCLKState { | 77 | +#include "hw/char/stm32l4x5_usart.h" |
48 | +/* Maximum amount of clock inputs in a SEL module. */ | 78 | #include "hw/gpio/stm32l4x5_gpio.h" |
49 | +#define NPCM7XX_CLK_SEL_MAX_INPUT 5 | 79 | #include "hw/qdev-clock.h" |
50 | + | 80 | #include "hw/misc/unimp.h" |
51 | +/* PLLs in CLK module. */ | 81 | @@ -XXX,XX +XXX,XX @@ static const struct { |
52 | +typedef enum NPCM7xxClockPLL { | 82 | { 0x48001C00, 0x0000000F, 0x00000000, 0x00000000 }, |
53 | + NPCM7XX_CLOCK_PLL0, | 83 | }; |
54 | + NPCM7XX_CLOCK_PLL1, | 84 | |
55 | + NPCM7XX_CLOCK_PLL2, | 85 | +static const hwaddr usart_addr[] = { |
56 | + NPCM7XX_CLOCK_PLLG, | 86 | + 0x40013800, /* "USART1", 0x400 */ |
57 | + NPCM7XX_CLOCK_NR_PLLS, | 87 | + 0x40004400, /* "USART2", 0x400 */ |
58 | +} NPCM7xxClockPLL; | 88 | + 0x40004800, /* "USART3", 0x400 */ |
59 | + | ||
60 | +/* SEL/MUX in CLK module. */ | ||
61 | +typedef enum NPCM7xxClockSEL { | ||
62 | + NPCM7XX_CLOCK_PIXCKSEL, | ||
63 | + NPCM7XX_CLOCK_MCCKSEL, | ||
64 | + NPCM7XX_CLOCK_CPUCKSEL, | ||
65 | + NPCM7XX_CLOCK_CLKOUTSEL, | ||
66 | + NPCM7XX_CLOCK_UARTCKSEL, | ||
67 | + NPCM7XX_CLOCK_TIMCKSEL, | ||
68 | + NPCM7XX_CLOCK_SDCKSEL, | ||
69 | + NPCM7XX_CLOCK_GFXMSEL, | ||
70 | + NPCM7XX_CLOCK_SUCKSEL, | ||
71 | + NPCM7XX_CLOCK_NR_SELS, | ||
72 | +} NPCM7xxClockSEL; | ||
73 | + | ||
74 | +/* Dividers in CLK module. */ | ||
75 | +typedef enum NPCM7xxClockDivider { | ||
76 | + NPCM7XX_CLOCK_PLL1D2, /* PLL1/2 */ | ||
77 | + NPCM7XX_CLOCK_PLL2D2, /* PLL2/2 */ | ||
78 | + NPCM7XX_CLOCK_MC_DIVIDER, | ||
79 | + NPCM7XX_CLOCK_AXI_DIVIDER, | ||
80 | + NPCM7XX_CLOCK_AHB_DIVIDER, | ||
81 | + NPCM7XX_CLOCK_AHB3_DIVIDER, | ||
82 | + NPCM7XX_CLOCK_SPI0_DIVIDER, | ||
83 | + NPCM7XX_CLOCK_SPIX_DIVIDER, | ||
84 | + NPCM7XX_CLOCK_APB1_DIVIDER, | ||
85 | + NPCM7XX_CLOCK_APB2_DIVIDER, | ||
86 | + NPCM7XX_CLOCK_APB3_DIVIDER, | ||
87 | + NPCM7XX_CLOCK_APB4_DIVIDER, | ||
88 | + NPCM7XX_CLOCK_APB5_DIVIDER, | ||
89 | + NPCM7XX_CLOCK_CLKOUT_DIVIDER, | ||
90 | + NPCM7XX_CLOCK_UART_DIVIDER, | ||
91 | + NPCM7XX_CLOCK_TIMER_DIVIDER, | ||
92 | + NPCM7XX_CLOCK_ADC_DIVIDER, | ||
93 | + NPCM7XX_CLOCK_MMC_DIVIDER, | ||
94 | + NPCM7XX_CLOCK_SDHC_DIVIDER, | ||
95 | + NPCM7XX_CLOCK_GFXM_DIVIDER, /* divide by 3 */ | ||
96 | + NPCM7XX_CLOCK_UTMI_DIVIDER, | ||
97 | + NPCM7XX_CLOCK_NR_DIVIDERS, | ||
98 | +} NPCM7xxClockConverter; | ||
99 | + | ||
100 | +typedef struct NPCM7xxCLKState NPCM7xxCLKState; | ||
101 | + | ||
102 | +/** | ||
103 | + * struct NPCM7xxClockPLLState - A PLL module in CLK module. | ||
104 | + * @name: The name of the module. | ||
105 | + * @clk: The CLK module that owns this module. | ||
106 | + * @clock_in: The input clock of this module. | ||
107 | + * @clock_out: The output clock of this module. | ||
108 | + * @reg: The control registers for this PLL module. | ||
109 | + */ | ||
110 | +typedef struct NPCM7xxClockPLLState { | ||
111 | + DeviceState parent; | ||
112 | + | ||
113 | + const char *name; | ||
114 | + NPCM7xxCLKState *clk; | ||
115 | + Clock *clock_in; | ||
116 | + Clock *clock_out; | ||
117 | + | ||
118 | + int reg; | ||
119 | +} NPCM7xxClockPLLState; | ||
120 | + | ||
121 | +/** | ||
122 | + * struct NPCM7xxClockSELState - A SEL module in CLK module. | ||
123 | + * @name: The name of the module. | ||
124 | + * @clk: The CLK module that owns this module. | ||
125 | + * @input_size: The size of inputs of this module. | ||
126 | + * @clock_in: The input clocks of this module. | ||
127 | + * @clock_out: The output clocks of this module. | ||
128 | + * @offset: The offset of this module in the control register. | ||
129 | + * @len: The length of this module in the control register. | ||
130 | + */ | ||
131 | +typedef struct NPCM7xxClockSELState { | ||
132 | + DeviceState parent; | ||
133 | + | ||
134 | + const char *name; | ||
135 | + NPCM7xxCLKState *clk; | ||
136 | + uint8_t input_size; | ||
137 | + Clock *clock_in[NPCM7XX_CLK_SEL_MAX_INPUT]; | ||
138 | + Clock *clock_out; | ||
139 | + | ||
140 | + int offset; | ||
141 | + int len; | ||
142 | +} NPCM7xxClockSELState; | ||
143 | + | ||
144 | +/** | ||
145 | + * struct NPCM7xxClockDividerState - A Divider module in CLK module. | ||
146 | + * @name: The name of the module. | ||
147 | + * @clk: The CLK module that owns this module. | ||
148 | + * @clock_in: The input clock of this module. | ||
149 | + * @clock_out: The output clock of this module. | ||
150 | + * @divide: The function the divider uses to divide the input. | ||
151 | + * @reg: The index of the control register that contains the divisor. | ||
152 | + * @offset: The offset of the divisor in the control register. | ||
153 | + * @len: The length of the divisor in the control register. | ||
154 | + * @divisor: The divisor for a constant divisor | ||
155 | + */ | ||
156 | +typedef struct NPCM7xxClockDividerState { | ||
157 | + DeviceState parent; | ||
158 | + | ||
159 | + const char *name; | ||
160 | + NPCM7xxCLKState *clk; | ||
161 | + Clock *clock_in; | ||
162 | + Clock *clock_out; | ||
163 | + | ||
164 | + uint32_t (*divide)(struct NPCM7xxClockDividerState *s); | ||
165 | + union { | ||
166 | + struct { | ||
167 | + int reg; | ||
168 | + int offset; | ||
169 | + int len; | ||
170 | + }; | ||
171 | + int divisor; | ||
172 | + }; | ||
173 | +} NPCM7xxClockDividerState; | ||
174 | + | ||
175 | +struct NPCM7xxCLKState { | ||
176 | SysBusDevice parent; | ||
177 | |||
178 | MemoryRegion iomem; | ||
179 | |||
180 | + /* Clock converters */ | ||
181 | + NPCM7xxClockPLLState plls[NPCM7XX_CLOCK_NR_PLLS]; | ||
182 | + NPCM7xxClockSELState sels[NPCM7XX_CLOCK_NR_SELS]; | ||
183 | + NPCM7xxClockDividerState dividers[NPCM7XX_CLOCK_NR_DIVIDERS]; | ||
184 | + | ||
185 | uint32_t regs[NPCM7XX_CLK_NR_REGS]; | ||
186 | |||
187 | /* Time reference for SECCNT and CNTR25M, initialized by power on reset */ | ||
188 | int64_t ref_ns; | ||
189 | -} NPCM7xxCLKState; | ||
190 | + | ||
191 | + /* The incoming reference clock. */ | ||
192 | + Clock *clkref; | ||
193 | +}; | 89 | +}; |
194 | 90 | +static const hwaddr uart_addr[] = { | |
195 | #define TYPE_NPCM7XX_CLK "npcm7xx-clk" | 91 | + 0x40004C00, /* "UART4" , 0x400 */ |
196 | #define NPCM7XX_CLK(obj) OBJECT_CHECK(NPCM7xxCLKState, (obj), TYPE_NPCM7XX_CLK) | 92 | + 0x40005000 /* "UART5" , 0x400 */ |
197 | diff --git a/hw/misc/npcm7xx_clk.c b/hw/misc/npcm7xx_clk.c | ||
198 | index XXXXXXX..XXXXXXX 100644 | ||
199 | --- a/hw/misc/npcm7xx_clk.c | ||
200 | +++ b/hw/misc/npcm7xx_clk.c | ||
201 | @@ -XXX,XX +XXX,XX @@ | ||
202 | |||
203 | #include "hw/misc/npcm7xx_clk.h" | ||
204 | #include "hw/timer/npcm7xx_timer.h" | ||
205 | +#include "hw/qdev-clock.h" | ||
206 | #include "migration/vmstate.h" | ||
207 | #include "qemu/error-report.h" | ||
208 | #include "qemu/log.h" | ||
209 | @@ -XXX,XX +XXX,XX @@ | ||
210 | #include "trace.h" | ||
211 | #include "sysemu/watchdog.h" | ||
212 | |||
213 | +/* | ||
214 | + * The reference clock hz, and the SECCNT and CNTR25M registers in this module, | ||
215 | + * is always 25 MHz. | ||
216 | + */ | ||
217 | +#define NPCM7XX_CLOCK_REF_HZ (25000000) | ||
218 | + | ||
219 | +/* Register Field Definitions */ | ||
220 | +#define NPCM7XX_CLK_WDRCR_CA9C BIT(0) /* Cortex A9 Cores */ | ||
221 | + | ||
222 | #define PLLCON_LOKI BIT(31) | ||
223 | #define PLLCON_LOKS BIT(30) | ||
224 | #define PLLCON_PWDEN BIT(12) | ||
225 | +#define PLLCON_FBDV(con) extract32((con), 16, 12) | ||
226 | +#define PLLCON_OTDV2(con) extract32((con), 13, 3) | ||
227 | +#define PLLCON_OTDV1(con) extract32((con), 8, 3) | ||
228 | +#define PLLCON_INDV(con) extract32((con), 0, 6) | ||
229 | |||
230 | enum NPCM7xxCLKRegisters { | ||
231 | NPCM7XX_CLK_CLKEN1, | ||
232 | @@ -XXX,XX +XXX,XX @@ static const uint32_t cold_reset_values[NPCM7XX_CLK_NR_REGS] = { | ||
233 | [NPCM7XX_CLK_AHBCKFI] = 0x000000c8, | ||
234 | }; | ||
235 | |||
236 | -/* Register Field Definitions */ | ||
237 | -#define NPCM7XX_CLK_WDRCR_CA9C BIT(0) /* Cortex A9 Cores */ | ||
238 | - | ||
239 | /* The number of watchdogs that can trigger a reset. */ | ||
240 | #define NPCM7XX_NR_WATCHDOGS (3) | ||
241 | |||
242 | +/* Clock converter functions */ | ||
243 | + | ||
244 | +#define TYPE_NPCM7XX_CLOCK_PLL "npcm7xx-clock-pll" | ||
245 | +#define NPCM7XX_CLOCK_PLL(obj) OBJECT_CHECK(NPCM7xxClockPLLState, \ | ||
246 | + (obj), TYPE_NPCM7XX_CLOCK_PLL) | ||
247 | +#define TYPE_NPCM7XX_CLOCK_SEL "npcm7xx-clock-sel" | ||
248 | +#define NPCM7XX_CLOCK_SEL(obj) OBJECT_CHECK(NPCM7xxClockSELState, \ | ||
249 | + (obj), TYPE_NPCM7XX_CLOCK_SEL) | ||
250 | +#define TYPE_NPCM7XX_CLOCK_DIVIDER "npcm7xx-clock-divider" | ||
251 | +#define NPCM7XX_CLOCK_DIVIDER(obj) OBJECT_CHECK(NPCM7xxClockDividerState, \ | ||
252 | + (obj), TYPE_NPCM7XX_CLOCK_DIVIDER) | ||
253 | + | ||
254 | +static void npcm7xx_clk_update_pll(void *opaque) | ||
255 | +{ | ||
256 | + NPCM7xxClockPLLState *s = opaque; | ||
257 | + uint32_t con = s->clk->regs[s->reg]; | ||
258 | + uint64_t freq; | ||
259 | + | ||
260 | + /* The PLL is grounded if it is not locked yet. */ | ||
261 | + if (con & PLLCON_LOKI) { | ||
262 | + freq = clock_get_hz(s->clock_in); | ||
263 | + freq *= PLLCON_FBDV(con); | ||
264 | + freq /= PLLCON_INDV(con) * PLLCON_OTDV1(con) * PLLCON_OTDV2(con); | ||
265 | + } else { | ||
266 | + freq = 0; | ||
267 | + } | ||
268 | + | ||
269 | + clock_update_hz(s->clock_out, freq); | ||
270 | +} | ||
271 | + | ||
272 | +static void npcm7xx_clk_update_sel(void *opaque) | ||
273 | +{ | ||
274 | + NPCM7xxClockSELState *s = opaque; | ||
275 | + uint32_t index = extract32(s->clk->regs[NPCM7XX_CLK_CLKSEL], s->offset, | ||
276 | + s->len); | ||
277 | + | ||
278 | + if (index >= s->input_size) { | ||
279 | + qemu_log_mask(LOG_GUEST_ERROR, | ||
280 | + "%s: SEL index: %u out of range\n", | ||
281 | + __func__, index); | ||
282 | + index = 0; | ||
283 | + } | ||
284 | + clock_update_hz(s->clock_out, clock_get_hz(s->clock_in[index])); | ||
285 | +} | ||
286 | + | ||
287 | +static void npcm7xx_clk_update_divider(void *opaque) | ||
288 | +{ | ||
289 | + NPCM7xxClockDividerState *s = opaque; | ||
290 | + uint32_t freq; | ||
291 | + | ||
292 | + freq = s->divide(s); | ||
293 | + clock_update_hz(s->clock_out, freq); | ||
294 | +} | ||
295 | + | ||
296 | +static uint32_t divide_by_constant(NPCM7xxClockDividerState *s) | ||
297 | +{ | ||
298 | + return clock_get_hz(s->clock_in) / s->divisor; | ||
299 | +} | ||
300 | + | ||
301 | +static uint32_t divide_by_reg_divisor(NPCM7xxClockDividerState *s) | ||
302 | +{ | ||
303 | + return clock_get_hz(s->clock_in) / | ||
304 | + (extract32(s->clk->regs[s->reg], s->offset, s->len) + 1); | ||
305 | +} | ||
306 | + | ||
307 | +static uint32_t divide_by_reg_divisor_times_2(NPCM7xxClockDividerState *s) | ||
308 | +{ | ||
309 | + return divide_by_reg_divisor(s) / 2; | ||
310 | +} | ||
311 | + | ||
312 | +static uint32_t shift_by_reg_divisor(NPCM7xxClockDividerState *s) | ||
313 | +{ | ||
314 | + return clock_get_hz(s->clock_in) >> | ||
315 | + extract32(s->clk->regs[s->reg], s->offset, s->len); | ||
316 | +} | ||
317 | + | ||
318 | +static NPCM7xxClockPLL find_pll_by_reg(enum NPCM7xxCLKRegisters reg) | ||
319 | +{ | ||
320 | + switch (reg) { | ||
321 | + case NPCM7XX_CLK_PLLCON0: | ||
322 | + return NPCM7XX_CLOCK_PLL0; | ||
323 | + case NPCM7XX_CLK_PLLCON1: | ||
324 | + return NPCM7XX_CLOCK_PLL1; | ||
325 | + case NPCM7XX_CLK_PLLCON2: | ||
326 | + return NPCM7XX_CLOCK_PLL2; | ||
327 | + case NPCM7XX_CLK_PLLCONG: | ||
328 | + return NPCM7XX_CLOCK_PLLG; | ||
329 | + default: | ||
330 | + g_assert_not_reached(); | ||
331 | + } | ||
332 | +} | ||
333 | + | ||
334 | +static void npcm7xx_clk_update_all_plls(NPCM7xxCLKState *clk) | ||
335 | +{ | ||
336 | + int i; | ||
337 | + | ||
338 | + for (i = 0; i < NPCM7XX_CLOCK_NR_PLLS; ++i) { | ||
339 | + npcm7xx_clk_update_pll(&clk->plls[i]); | ||
340 | + } | ||
341 | +} | ||
342 | + | ||
343 | +static void npcm7xx_clk_update_all_sels(NPCM7xxCLKState *clk) | ||
344 | +{ | ||
345 | + int i; | ||
346 | + | ||
347 | + for (i = 0; i < NPCM7XX_CLOCK_NR_SELS; ++i) { | ||
348 | + npcm7xx_clk_update_sel(&clk->sels[i]); | ||
349 | + } | ||
350 | +} | ||
351 | + | ||
352 | +static void npcm7xx_clk_update_all_dividers(NPCM7xxCLKState *clk) | ||
353 | +{ | ||
354 | + int i; | ||
355 | + | ||
356 | + for (i = 0; i < NPCM7XX_CLOCK_NR_DIVIDERS; ++i) { | ||
357 | + npcm7xx_clk_update_divider(&clk->dividers[i]); | ||
358 | + } | ||
359 | +} | ||
360 | + | ||
361 | +static void npcm7xx_clk_update_all_clocks(NPCM7xxCLKState *clk) | ||
362 | +{ | ||
363 | + clock_update_hz(clk->clkref, NPCM7XX_CLOCK_REF_HZ); | ||
364 | + npcm7xx_clk_update_all_plls(clk); | ||
365 | + npcm7xx_clk_update_all_sels(clk); | ||
366 | + npcm7xx_clk_update_all_dividers(clk); | ||
367 | +} | ||
368 | + | ||
369 | +/* Types of clock sources. */ | ||
370 | +typedef enum ClockSrcType { | ||
371 | + CLKSRC_REF, | ||
372 | + CLKSRC_PLL, | ||
373 | + CLKSRC_SEL, | ||
374 | + CLKSRC_DIV, | ||
375 | +} ClockSrcType; | ||
376 | + | ||
377 | +typedef struct PLLInitInfo { | ||
378 | + const char *name; | ||
379 | + ClockSrcType src_type; | ||
380 | + int src_index; | ||
381 | + int reg; | ||
382 | + const char *public_name; | ||
383 | +} PLLInitInfo; | ||
384 | + | ||
385 | +typedef struct SELInitInfo { | ||
386 | + const char *name; | ||
387 | + uint8_t input_size; | ||
388 | + ClockSrcType src_type[NPCM7XX_CLK_SEL_MAX_INPUT]; | ||
389 | + int src_index[NPCM7XX_CLK_SEL_MAX_INPUT]; | ||
390 | + int offset; | ||
391 | + int len; | ||
392 | + const char *public_name; | ||
393 | +} SELInitInfo; | ||
394 | + | ||
395 | +typedef struct DividerInitInfo { | ||
396 | + const char *name; | ||
397 | + ClockSrcType src_type; | ||
398 | + int src_index; | ||
399 | + uint32_t (*divide)(NPCM7xxClockDividerState *s); | ||
400 | + int reg; /* not used when type == CONSTANT */ | ||
401 | + int offset; /* not used when type == CONSTANT */ | ||
402 | + int len; /* not used when type == CONSTANT */ | ||
403 | + int divisor; /* used only when type == CONSTANT */ | ||
404 | + const char *public_name; | ||
405 | +} DividerInitInfo; | ||
406 | + | ||
407 | +static const PLLInitInfo pll_init_info_list[] = { | ||
408 | + [NPCM7XX_CLOCK_PLL0] = { | ||
409 | + .name = "pll0", | ||
410 | + .src_type = CLKSRC_REF, | ||
411 | + .reg = NPCM7XX_CLK_PLLCON0, | ||
412 | + }, | ||
413 | + [NPCM7XX_CLOCK_PLL1] = { | ||
414 | + .name = "pll1", | ||
415 | + .src_type = CLKSRC_REF, | ||
416 | + .reg = NPCM7XX_CLK_PLLCON1, | ||
417 | + }, | ||
418 | + [NPCM7XX_CLOCK_PLL2] = { | ||
419 | + .name = "pll2", | ||
420 | + .src_type = CLKSRC_REF, | ||
421 | + .reg = NPCM7XX_CLK_PLLCON2, | ||
422 | + }, | ||
423 | + [NPCM7XX_CLOCK_PLLG] = { | ||
424 | + .name = "pllg", | ||
425 | + .src_type = CLKSRC_REF, | ||
426 | + .reg = NPCM7XX_CLK_PLLCONG, | ||
427 | + }, | ||
428 | +}; | 93 | +}; |
429 | + | 94 | + |
430 | +static const SELInitInfo sel_init_info_list[] = { | 95 | +#define LPUART_BASE_ADDRESS 0x40008000 |
431 | + [NPCM7XX_CLOCK_PIXCKSEL] = { | 96 | + |
432 | + .name = "pixcksel", | 97 | +static const int usart_irq[] = { 37, 38, 39 }; |
433 | + .input_size = 2, | 98 | +static const int uart_irq[] = { 52, 53 }; |
434 | + .src_type = {CLKSRC_PLL, CLKSRC_REF}, | 99 | +#define LPUART_IRQ 70 |
435 | + .src_index = {NPCM7XX_CLOCK_PLLG, 0}, | 100 | + |
436 | + .offset = 5, | 101 | static void stm32l4x5_soc_initfn(Object *obj) |
437 | + .len = 1, | ||
438 | + .public_name = "pixel-clock", | ||
439 | + }, | ||
440 | + [NPCM7XX_CLOCK_MCCKSEL] = { | ||
441 | + .name = "mccksel", | ||
442 | + .input_size = 4, | ||
443 | + .src_type = {CLKSRC_DIV, CLKSRC_REF, CLKSRC_REF, | ||
444 | + /*MCBPCK, shouldn't be used in normal operation*/ | ||
445 | + CLKSRC_REF}, | ||
446 | + .src_index = {NPCM7XX_CLOCK_PLL1D2, 0, 0, 0}, | ||
447 | + .offset = 12, | ||
448 | + .len = 2, | ||
449 | + .public_name = "mc-phy-clock", | ||
450 | + }, | ||
451 | + [NPCM7XX_CLOCK_CPUCKSEL] = { | ||
452 | + .name = "cpucksel", | ||
453 | + .input_size = 4, | ||
454 | + .src_type = {CLKSRC_PLL, CLKSRC_DIV, CLKSRC_REF, | ||
455 | + /*SYSBPCK, shouldn't be used in normal operation*/ | ||
456 | + CLKSRC_REF}, | ||
457 | + .src_index = {NPCM7XX_CLOCK_PLL0, NPCM7XX_CLOCK_PLL1D2, 0, 0}, | ||
458 | + .offset = 0, | ||
459 | + .len = 2, | ||
460 | + .public_name = "system-clock", | ||
461 | + }, | ||
462 | + [NPCM7XX_CLOCK_CLKOUTSEL] = { | ||
463 | + .name = "clkoutsel", | ||
464 | + .input_size = 5, | ||
465 | + .src_type = {CLKSRC_PLL, CLKSRC_DIV, CLKSRC_REF, | ||
466 | + CLKSRC_PLL, CLKSRC_DIV}, | ||
467 | + .src_index = {NPCM7XX_CLOCK_PLL0, NPCM7XX_CLOCK_PLL1D2, 0, | ||
468 | + NPCM7XX_CLOCK_PLLG, NPCM7XX_CLOCK_PLL2D2}, | ||
469 | + .offset = 18, | ||
470 | + .len = 3, | ||
471 | + .public_name = "tock", | ||
472 | + }, | ||
473 | + [NPCM7XX_CLOCK_UARTCKSEL] = { | ||
474 | + .name = "uartcksel", | ||
475 | + .input_size = 4, | ||
476 | + .src_type = {CLKSRC_PLL, CLKSRC_DIV, CLKSRC_REF, CLKSRC_DIV}, | ||
477 | + .src_index = {NPCM7XX_CLOCK_PLL0, NPCM7XX_CLOCK_PLL1D2, 0, | ||
478 | + NPCM7XX_CLOCK_PLL2D2}, | ||
479 | + .offset = 8, | ||
480 | + .len = 2, | ||
481 | + }, | ||
482 | + [NPCM7XX_CLOCK_TIMCKSEL] = { | ||
483 | + .name = "timcksel", | ||
484 | + .input_size = 4, | ||
485 | + .src_type = {CLKSRC_PLL, CLKSRC_DIV, CLKSRC_REF, CLKSRC_DIV}, | ||
486 | + .src_index = {NPCM7XX_CLOCK_PLL0, NPCM7XX_CLOCK_PLL1D2, 0, | ||
487 | + NPCM7XX_CLOCK_PLL2D2}, | ||
488 | + .offset = 14, | ||
489 | + .len = 2, | ||
490 | + }, | ||
491 | + [NPCM7XX_CLOCK_SDCKSEL] = { | ||
492 | + .name = "sdcksel", | ||
493 | + .input_size = 4, | ||
494 | + .src_type = {CLKSRC_PLL, CLKSRC_DIV, CLKSRC_REF, CLKSRC_DIV}, | ||
495 | + .src_index = {NPCM7XX_CLOCK_PLL0, NPCM7XX_CLOCK_PLL1D2, 0, | ||
496 | + NPCM7XX_CLOCK_PLL2D2}, | ||
497 | + .offset = 6, | ||
498 | + .len = 2, | ||
499 | + }, | ||
500 | + [NPCM7XX_CLOCK_GFXMSEL] = { | ||
501 | + .name = "gfxmksel", | ||
502 | + .input_size = 2, | ||
503 | + .src_type = {CLKSRC_REF, CLKSRC_PLL}, | ||
504 | + .src_index = {0, NPCM7XX_CLOCK_PLL2}, | ||
505 | + .offset = 21, | ||
506 | + .len = 1, | ||
507 | + }, | ||
508 | + [NPCM7XX_CLOCK_SUCKSEL] = { | ||
509 | + .name = "sucksel", | ||
510 | + .input_size = 4, | ||
511 | + .src_type = {CLKSRC_PLL, CLKSRC_DIV, CLKSRC_REF, CLKSRC_DIV}, | ||
512 | + .src_index = {NPCM7XX_CLOCK_PLL0, NPCM7XX_CLOCK_PLL1D2, 0, | ||
513 | + NPCM7XX_CLOCK_PLL2D2}, | ||
514 | + .offset = 10, | ||
515 | + .len = 2, | ||
516 | + }, | ||
517 | +}; | ||
518 | + | ||
519 | +static const DividerInitInfo divider_init_info_list[] = { | ||
520 | + [NPCM7XX_CLOCK_PLL1D2] = { | ||
521 | + .name = "pll1d2", | ||
522 | + .src_type = CLKSRC_PLL, | ||
523 | + .src_index = NPCM7XX_CLOCK_PLL1, | ||
524 | + .divide = divide_by_constant, | ||
525 | + .divisor = 2, | ||
526 | + }, | ||
527 | + [NPCM7XX_CLOCK_PLL2D2] = { | ||
528 | + .name = "pll2d2", | ||
529 | + .src_type = CLKSRC_PLL, | ||
530 | + .src_index = NPCM7XX_CLOCK_PLL2, | ||
531 | + .divide = divide_by_constant, | ||
532 | + .divisor = 2, | ||
533 | + }, | ||
534 | + [NPCM7XX_CLOCK_MC_DIVIDER] = { | ||
535 | + .name = "mc-divider", | ||
536 | + .src_type = CLKSRC_SEL, | ||
537 | + .src_index = NPCM7XX_CLOCK_MCCKSEL, | ||
538 | + .divide = divide_by_constant, | ||
539 | + .divisor = 2, | ||
540 | + .public_name = "mc-clock" | ||
541 | + }, | ||
542 | + [NPCM7XX_CLOCK_AXI_DIVIDER] = { | ||
543 | + .name = "axi-divider", | ||
544 | + .src_type = CLKSRC_SEL, | ||
545 | + .src_index = NPCM7XX_CLOCK_CPUCKSEL, | ||
546 | + .divide = shift_by_reg_divisor, | ||
547 | + .reg = NPCM7XX_CLK_CLKDIV1, | ||
548 | + .offset = 0, | ||
549 | + .len = 1, | ||
550 | + .public_name = "clk2" | ||
551 | + }, | ||
552 | + [NPCM7XX_CLOCK_AHB_DIVIDER] = { | ||
553 | + .name = "ahb-divider", | ||
554 | + .src_type = CLKSRC_DIV, | ||
555 | + .src_index = NPCM7XX_CLOCK_AXI_DIVIDER, | ||
556 | + .divide = divide_by_reg_divisor, | ||
557 | + .reg = NPCM7XX_CLK_CLKDIV1, | ||
558 | + .offset = 26, | ||
559 | + .len = 2, | ||
560 | + .public_name = "clk4" | ||
561 | + }, | ||
562 | + [NPCM7XX_CLOCK_AHB3_DIVIDER] = { | ||
563 | + .name = "ahb3-divider", | ||
564 | + .src_type = CLKSRC_DIV, | ||
565 | + .src_index = NPCM7XX_CLOCK_AHB_DIVIDER, | ||
566 | + .divide = divide_by_reg_divisor, | ||
567 | + .reg = NPCM7XX_CLK_CLKDIV1, | ||
568 | + .offset = 6, | ||
569 | + .len = 5, | ||
570 | + .public_name = "ahb3-spi3-clock" | ||
571 | + }, | ||
572 | + [NPCM7XX_CLOCK_SPI0_DIVIDER] = { | ||
573 | + .name = "spi0-divider", | ||
574 | + .src_type = CLKSRC_DIV, | ||
575 | + .src_index = NPCM7XX_CLOCK_AHB_DIVIDER, | ||
576 | + .divide = divide_by_reg_divisor, | ||
577 | + .reg = NPCM7XX_CLK_CLKDIV3, | ||
578 | + .offset = 6, | ||
579 | + .len = 5, | ||
580 | + .public_name = "spi0-clock", | ||
581 | + }, | ||
582 | + [NPCM7XX_CLOCK_SPIX_DIVIDER] = { | ||
583 | + .name = "spix-divider", | ||
584 | + .src_type = CLKSRC_DIV, | ||
585 | + .src_index = NPCM7XX_CLOCK_AHB_DIVIDER, | ||
586 | + .divide = divide_by_reg_divisor, | ||
587 | + .reg = NPCM7XX_CLK_CLKDIV3, | ||
588 | + .offset = 1, | ||
589 | + .len = 5, | ||
590 | + .public_name = "spix-clock", | ||
591 | + }, | ||
592 | + [NPCM7XX_CLOCK_APB1_DIVIDER] = { | ||
593 | + .name = "apb1-divider", | ||
594 | + .src_type = CLKSRC_DIV, | ||
595 | + .src_index = NPCM7XX_CLOCK_AHB_DIVIDER, | ||
596 | + .divide = shift_by_reg_divisor, | ||
597 | + .reg = NPCM7XX_CLK_CLKDIV2, | ||
598 | + .offset = 24, | ||
599 | + .len = 2, | ||
600 | + .public_name = "apb1-clock", | ||
601 | + }, | ||
602 | + [NPCM7XX_CLOCK_APB2_DIVIDER] = { | ||
603 | + .name = "apb2-divider", | ||
604 | + .src_type = CLKSRC_DIV, | ||
605 | + .src_index = NPCM7XX_CLOCK_AHB_DIVIDER, | ||
606 | + .divide = shift_by_reg_divisor, | ||
607 | + .reg = NPCM7XX_CLK_CLKDIV2, | ||
608 | + .offset = 26, | ||
609 | + .len = 2, | ||
610 | + .public_name = "apb2-clock", | ||
611 | + }, | ||
612 | + [NPCM7XX_CLOCK_APB3_DIVIDER] = { | ||
613 | + .name = "apb3-divider", | ||
614 | + .src_type = CLKSRC_DIV, | ||
615 | + .src_index = NPCM7XX_CLOCK_AHB_DIVIDER, | ||
616 | + .divide = shift_by_reg_divisor, | ||
617 | + .reg = NPCM7XX_CLK_CLKDIV2, | ||
618 | + .offset = 28, | ||
619 | + .len = 2, | ||
620 | + .public_name = "apb3-clock", | ||
621 | + }, | ||
622 | + [NPCM7XX_CLOCK_APB4_DIVIDER] = { | ||
623 | + .name = "apb4-divider", | ||
624 | + .src_type = CLKSRC_DIV, | ||
625 | + .src_index = NPCM7XX_CLOCK_AHB_DIVIDER, | ||
626 | + .divide = shift_by_reg_divisor, | ||
627 | + .reg = NPCM7XX_CLK_CLKDIV2, | ||
628 | + .offset = 30, | ||
629 | + .len = 2, | ||
630 | + .public_name = "apb4-clock", | ||
631 | + }, | ||
632 | + [NPCM7XX_CLOCK_APB5_DIVIDER] = { | ||
633 | + .name = "apb5-divider", | ||
634 | + .src_type = CLKSRC_DIV, | ||
635 | + .src_index = NPCM7XX_CLOCK_AHB_DIVIDER, | ||
636 | + .divide = shift_by_reg_divisor, | ||
637 | + .reg = NPCM7XX_CLK_CLKDIV2, | ||
638 | + .offset = 22, | ||
639 | + .len = 2, | ||
640 | + .public_name = "apb5-clock", | ||
641 | + }, | ||
642 | + [NPCM7XX_CLOCK_CLKOUT_DIVIDER] = { | ||
643 | + .name = "clkout-divider", | ||
644 | + .src_type = CLKSRC_SEL, | ||
645 | + .src_index = NPCM7XX_CLOCK_CLKOUTSEL, | ||
646 | + .divide = divide_by_reg_divisor, | ||
647 | + .reg = NPCM7XX_CLK_CLKDIV2, | ||
648 | + .offset = 16, | ||
649 | + .len = 5, | ||
650 | + .public_name = "clkout", | ||
651 | + }, | ||
652 | + [NPCM7XX_CLOCK_UART_DIVIDER] = { | ||
653 | + .name = "uart-divider", | ||
654 | + .src_type = CLKSRC_SEL, | ||
655 | + .src_index = NPCM7XX_CLOCK_UARTCKSEL, | ||
656 | + .divide = divide_by_reg_divisor, | ||
657 | + .reg = NPCM7XX_CLK_CLKDIV1, | ||
658 | + .offset = 16, | ||
659 | + .len = 5, | ||
660 | + .public_name = "uart-clock", | ||
661 | + }, | ||
662 | + [NPCM7XX_CLOCK_TIMER_DIVIDER] = { | ||
663 | + .name = "timer-divider", | ||
664 | + .src_type = CLKSRC_SEL, | ||
665 | + .src_index = NPCM7XX_CLOCK_TIMCKSEL, | ||
666 | + .divide = divide_by_reg_divisor, | ||
667 | + .reg = NPCM7XX_CLK_CLKDIV1, | ||
668 | + .offset = 21, | ||
669 | + .len = 5, | ||
670 | + .public_name = "timer-clock", | ||
671 | + }, | ||
672 | + [NPCM7XX_CLOCK_ADC_DIVIDER] = { | ||
673 | + .name = "adc-divider", | ||
674 | + .src_type = CLKSRC_DIV, | ||
675 | + .src_index = NPCM7XX_CLOCK_TIMER_DIVIDER, | ||
676 | + .divide = shift_by_reg_divisor, | ||
677 | + .reg = NPCM7XX_CLK_CLKDIV1, | ||
678 | + .offset = 28, | ||
679 | + .len = 3, | ||
680 | + .public_name = "adc-clock", | ||
681 | + }, | ||
682 | + [NPCM7XX_CLOCK_MMC_DIVIDER] = { | ||
683 | + .name = "mmc-divider", | ||
684 | + .src_type = CLKSRC_SEL, | ||
685 | + .src_index = NPCM7XX_CLOCK_SDCKSEL, | ||
686 | + .divide = divide_by_reg_divisor, | ||
687 | + .reg = NPCM7XX_CLK_CLKDIV1, | ||
688 | + .offset = 11, | ||
689 | + .len = 5, | ||
690 | + .public_name = "mmc-clock", | ||
691 | + }, | ||
692 | + [NPCM7XX_CLOCK_SDHC_DIVIDER] = { | ||
693 | + .name = "sdhc-divider", | ||
694 | + .src_type = CLKSRC_SEL, | ||
695 | + .src_index = NPCM7XX_CLOCK_SDCKSEL, | ||
696 | + .divide = divide_by_reg_divisor_times_2, | ||
697 | + .reg = NPCM7XX_CLK_CLKDIV2, | ||
698 | + .offset = 0, | ||
699 | + .len = 4, | ||
700 | + .public_name = "sdhc-clock", | ||
701 | + }, | ||
702 | + [NPCM7XX_CLOCK_GFXM_DIVIDER] = { | ||
703 | + .name = "gfxm-divider", | ||
704 | + .src_type = CLKSRC_SEL, | ||
705 | + .src_index = NPCM7XX_CLOCK_GFXMSEL, | ||
706 | + .divide = divide_by_constant, | ||
707 | + .divisor = 3, | ||
708 | + .public_name = "gfxm-clock", | ||
709 | + }, | ||
710 | + [NPCM7XX_CLOCK_UTMI_DIVIDER] = { | ||
711 | + .name = "utmi-divider", | ||
712 | + .src_type = CLKSRC_SEL, | ||
713 | + .src_index = NPCM7XX_CLOCK_SUCKSEL, | ||
714 | + .divide = divide_by_reg_divisor, | ||
715 | + .reg = NPCM7XX_CLK_CLKDIV2, | ||
716 | + .offset = 8, | ||
717 | + .len = 5, | ||
718 | + .public_name = "utmi-clock", | ||
719 | + }, | ||
720 | +}; | ||
721 | + | ||
722 | +static void npcm7xx_clk_pll_init(Object *obj) | ||
723 | +{ | ||
724 | + NPCM7xxClockPLLState *pll = NPCM7XX_CLOCK_PLL(obj); | ||
725 | + | ||
726 | + pll->clock_in = qdev_init_clock_in(DEVICE(pll), "clock-in", | ||
727 | + npcm7xx_clk_update_pll, pll); | ||
728 | + pll->clock_out = qdev_init_clock_out(DEVICE(pll), "clock-out"); | ||
729 | +} | ||
730 | + | ||
731 | +static void npcm7xx_clk_sel_init(Object *obj) | ||
732 | +{ | ||
733 | + int i; | ||
734 | + NPCM7xxClockSELState *sel = NPCM7XX_CLOCK_SEL(obj); | ||
735 | + | ||
736 | + for (i = 0; i < NPCM7XX_CLK_SEL_MAX_INPUT; ++i) { | ||
737 | + sel->clock_in[i] = qdev_init_clock_in(DEVICE(sel), | ||
738 | + g_strdup_printf("clock-in[%d]", i), | ||
739 | + npcm7xx_clk_update_sel, sel); | ||
740 | + } | ||
741 | + sel->clock_out = qdev_init_clock_out(DEVICE(sel), "clock-out"); | ||
742 | +} | ||
743 | +static void npcm7xx_clk_divider_init(Object *obj) | ||
744 | +{ | ||
745 | + NPCM7xxClockDividerState *div = NPCM7XX_CLOCK_DIVIDER(obj); | ||
746 | + | ||
747 | + div->clock_in = qdev_init_clock_in(DEVICE(div), "clock-in", | ||
748 | + npcm7xx_clk_update_divider, div); | ||
749 | + div->clock_out = qdev_init_clock_out(DEVICE(div), "clock-out"); | ||
750 | +} | ||
751 | + | ||
752 | +static void npcm7xx_init_clock_pll(NPCM7xxClockPLLState *pll, | ||
753 | + NPCM7xxCLKState *clk, const PLLInitInfo *init_info) | ||
754 | +{ | ||
755 | + pll->name = init_info->name; | ||
756 | + pll->clk = clk; | ||
757 | + pll->reg = init_info->reg; | ||
758 | + if (init_info->public_name != NULL) { | ||
759 | + qdev_alias_clock(DEVICE(pll), "clock-out", DEVICE(clk), | ||
760 | + init_info->public_name); | ||
761 | + } | ||
762 | +} | ||
763 | + | ||
764 | +static void npcm7xx_init_clock_sel(NPCM7xxClockSELState *sel, | ||
765 | + NPCM7xxCLKState *clk, const SELInitInfo *init_info) | ||
766 | +{ | ||
767 | + int input_size = init_info->input_size; | ||
768 | + | ||
769 | + sel->name = init_info->name; | ||
770 | + sel->clk = clk; | ||
771 | + sel->input_size = init_info->input_size; | ||
772 | + g_assert(input_size <= NPCM7XX_CLK_SEL_MAX_INPUT); | ||
773 | + sel->offset = init_info->offset; | ||
774 | + sel->len = init_info->len; | ||
775 | + if (init_info->public_name != NULL) { | ||
776 | + qdev_alias_clock(DEVICE(sel), "clock-out", DEVICE(clk), | ||
777 | + init_info->public_name); | ||
778 | + } | ||
779 | +} | ||
780 | + | ||
781 | +static void npcm7xx_init_clock_divider(NPCM7xxClockDividerState *div, | ||
782 | + NPCM7xxCLKState *clk, const DividerInitInfo *init_info) | ||
783 | +{ | ||
784 | + div->name = init_info->name; | ||
785 | + div->clk = clk; | ||
786 | + | ||
787 | + div->divide = init_info->divide; | ||
788 | + if (div->divide == divide_by_constant) { | ||
789 | + div->divisor = init_info->divisor; | ||
790 | + } else { | ||
791 | + div->reg = init_info->reg; | ||
792 | + div->offset = init_info->offset; | ||
793 | + div->len = init_info->len; | ||
794 | + } | ||
795 | + if (init_info->public_name != NULL) { | ||
796 | + qdev_alias_clock(DEVICE(div), "clock-out", DEVICE(clk), | ||
797 | + init_info->public_name); | ||
798 | + } | ||
799 | +} | ||
800 | + | ||
801 | +static Clock *npcm7xx_get_clock(NPCM7xxCLKState *clk, ClockSrcType type, | ||
802 | + int index) | ||
803 | +{ | ||
804 | + switch (type) { | ||
805 | + case CLKSRC_REF: | ||
806 | + return clk->clkref; | ||
807 | + case CLKSRC_PLL: | ||
808 | + return clk->plls[index].clock_out; | ||
809 | + case CLKSRC_SEL: | ||
810 | + return clk->sels[index].clock_out; | ||
811 | + case CLKSRC_DIV: | ||
812 | + return clk->dividers[index].clock_out; | ||
813 | + default: | ||
814 | + g_assert_not_reached(); | ||
815 | + } | ||
816 | +} | ||
817 | + | ||
818 | +static void npcm7xx_connect_clocks(NPCM7xxCLKState *clk) | ||
819 | +{ | ||
820 | + int i, j; | ||
821 | + Clock *src; | ||
822 | + | ||
823 | + for (i = 0; i < NPCM7XX_CLOCK_NR_PLLS; ++i) { | ||
824 | + src = npcm7xx_get_clock(clk, pll_init_info_list[i].src_type, | ||
825 | + pll_init_info_list[i].src_index); | ||
826 | + clock_set_source(clk->plls[i].clock_in, src); | ||
827 | + } | ||
828 | + for (i = 0; i < NPCM7XX_CLOCK_NR_SELS; ++i) { | ||
829 | + for (j = 0; j < sel_init_info_list[i].input_size; ++j) { | ||
830 | + src = npcm7xx_get_clock(clk, sel_init_info_list[i].src_type[j], | ||
831 | + sel_init_info_list[i].src_index[j]); | ||
832 | + clock_set_source(clk->sels[i].clock_in[j], src); | ||
833 | + } | ||
834 | + } | ||
835 | + for (i = 0; i < NPCM7XX_CLOCK_NR_DIVIDERS; ++i) { | ||
836 | + src = npcm7xx_get_clock(clk, divider_init_info_list[i].src_type, | ||
837 | + divider_init_info_list[i].src_index); | ||
838 | + clock_set_source(clk->dividers[i].clock_in, src); | ||
839 | + } | ||
840 | +} | ||
841 | + | ||
842 | static uint64_t npcm7xx_clk_read(void *opaque, hwaddr offset, unsigned size) | ||
843 | { | 102 | { |
844 | uint32_t reg = offset / sizeof(uint32_t); | 103 | Stm32l4x5SocState *s = STM32L4X5_SOC(obj); |
845 | @@ -XXX,XX +XXX,XX @@ static uint64_t npcm7xx_clk_read(void *opaque, hwaddr offset, unsigned size) | 104 | @@ -XXX,XX +XXX,XX @@ static void stm32l4x5_soc_initfn(Object *obj) |
846 | * | 105 | g_autofree char *name = g_strdup_printf("gpio%c", 'a' + i); |
847 | * The 4 LSBs are always zero: (1e9 / 640) << 4 = 25000000. | 106 | object_initialize_child(obj, name, &s->gpio[i], TYPE_STM32L4X5_GPIO); |
848 | */ | ||
849 | - value = (((now_ns - s->ref_ns) / 640) << 4) % NPCM7XX_TIMER_REF_HZ; | ||
850 | + value = (((now_ns - s->ref_ns) / 640) << 4) % NPCM7XX_CLOCK_REF_HZ; | ||
851 | break; | ||
852 | |||
853 | default: | ||
854 | @@ -XXX,XX +XXX,XX @@ static void npcm7xx_clk_write(void *opaque, hwaddr offset, | ||
855 | value |= (value & PLLCON_LOKS); | ||
856 | } | ||
857 | } | ||
858 | + /* Only update PLL when it is locked. */ | ||
859 | + if (value & PLLCON_LOKI) { | ||
860 | + npcm7xx_clk_update_pll(&s->plls[find_pll_by_reg(reg)]); | ||
861 | + } | ||
862 | + break; | ||
863 | + | ||
864 | + case NPCM7XX_CLK_CLKSEL: | ||
865 | + npcm7xx_clk_update_all_sels(s); | ||
866 | + break; | ||
867 | + | ||
868 | + case NPCM7XX_CLK_CLKDIV1: | ||
869 | + case NPCM7XX_CLK_CLKDIV2: | ||
870 | + case NPCM7XX_CLK_CLKDIV3: | ||
871 | + npcm7xx_clk_update_all_dividers(s); | ||
872 | break; | ||
873 | |||
874 | case NPCM7XX_CLK_CNTR25M: | ||
875 | @@ -XXX,XX +XXX,XX @@ static void npcm7xx_clk_enter_reset(Object *obj, ResetType type) | ||
876 | case RESET_TYPE_COLD: | ||
877 | memcpy(s->regs, cold_reset_values, sizeof(cold_reset_values)); | ||
878 | s->ref_ns = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); | ||
879 | + npcm7xx_clk_update_all_clocks(s); | ||
880 | return; | ||
881 | } | 107 | } |
882 | 108 | + | |
883 | @@ -XXX,XX +XXX,XX @@ static void npcm7xx_clk_enter_reset(Object *obj, ResetType type) | 109 | + for (int i = 0; i < STM_NUM_USARTS; i++) { |
884 | __func__, type); | 110 | + object_initialize_child(obj, "usart[*]", &s->usart[i], |
111 | + TYPE_STM32L4X5_USART); | ||
112 | + } | ||
113 | + | ||
114 | + for (int i = 0; i < STM_NUM_UARTS; i++) { | ||
115 | + object_initialize_child(obj, "uart[*]", &s->uart[i], | ||
116 | + TYPE_STM32L4X5_UART); | ||
117 | + } | ||
118 | + object_initialize_child(obj, "lpuart1", &s->lpuart, | ||
119 | + TYPE_STM32L4X5_LPUART); | ||
885 | } | 120 | } |
886 | 121 | ||
887 | +static void npcm7xx_clk_init_clock_hierarchy(NPCM7xxCLKState *s) | 122 | static void stm32l4x5_soc_realize(DeviceState *dev_soc, Error **errp) |
888 | +{ | 123 | @@ -XXX,XX +XXX,XX @@ static void stm32l4x5_soc_realize(DeviceState *dev_soc, Error **errp) |
889 | + int i; | 124 | sysbus_mmio_map(busdev, 0, RCC_BASE_ADDRESS); |
890 | + | 125 | sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, RCC_IRQ)); |
891 | + s->clkref = qdev_init_clock_in(DEVICE(s), "clkref", NULL, NULL); | 126 | |
892 | + | 127 | + /* USART devices */ |
893 | + /* First pass: init all converter modules */ | 128 | + for (int i = 0; i < STM_NUM_USARTS; i++) { |
894 | + QEMU_BUILD_BUG_ON(ARRAY_SIZE(pll_init_info_list) != NPCM7XX_CLOCK_NR_PLLS); | 129 | + g_autofree char *name = g_strdup_printf("usart%d-out", i + 1); |
895 | + QEMU_BUILD_BUG_ON(ARRAY_SIZE(sel_init_info_list) != NPCM7XX_CLOCK_NR_SELS); | 130 | + dev = DEVICE(&(s->usart[i])); |
896 | + QEMU_BUILD_BUG_ON(ARRAY_SIZE(divider_init_info_list) | 131 | + qdev_prop_set_chr(dev, "chardev", serial_hd(i)); |
897 | + != NPCM7XX_CLOCK_NR_DIVIDERS); | 132 | + qdev_connect_clock_in(dev, "clk", |
898 | + for (i = 0; i < NPCM7XX_CLOCK_NR_PLLS; ++i) { | 133 | + qdev_get_clock_out(DEVICE(&(s->rcc)), name)); |
899 | + object_initialize_child(OBJECT(s), pll_init_info_list[i].name, | 134 | + busdev = SYS_BUS_DEVICE(dev); |
900 | + &s->plls[i], TYPE_NPCM7XX_CLOCK_PLL); | 135 | + if (!sysbus_realize(busdev, errp)) { |
901 | + npcm7xx_init_clock_pll(&s->plls[i], s, | ||
902 | + &pll_init_info_list[i]); | ||
903 | + } | ||
904 | + for (i = 0; i < NPCM7XX_CLOCK_NR_SELS; ++i) { | ||
905 | + object_initialize_child(OBJECT(s), sel_init_info_list[i].name, | ||
906 | + &s->sels[i], TYPE_NPCM7XX_CLOCK_SEL); | ||
907 | + npcm7xx_init_clock_sel(&s->sels[i], s, | ||
908 | + &sel_init_info_list[i]); | ||
909 | + } | ||
910 | + for (i = 0; i < NPCM7XX_CLOCK_NR_DIVIDERS; ++i) { | ||
911 | + object_initialize_child(OBJECT(s), divider_init_info_list[i].name, | ||
912 | + &s->dividers[i], TYPE_NPCM7XX_CLOCK_DIVIDER); | ||
913 | + npcm7xx_init_clock_divider(&s->dividers[i], s, | ||
914 | + ÷r_init_info_list[i]); | ||
915 | + } | ||
916 | + | ||
917 | + /* Second pass: connect converter modules */ | ||
918 | + npcm7xx_connect_clocks(s); | ||
919 | + | ||
920 | + clock_update_hz(s->clkref, NPCM7XX_CLOCK_REF_HZ); | ||
921 | +} | ||
922 | + | ||
923 | static void npcm7xx_clk_init(Object *obj) | ||
924 | { | ||
925 | NPCM7xxCLKState *s = NPCM7XX_CLK(obj); | ||
926 | @@ -XXX,XX +XXX,XX @@ static void npcm7xx_clk_init(Object *obj) | ||
927 | memory_region_init_io(&s->iomem, obj, &npcm7xx_clk_ops, s, | ||
928 | TYPE_NPCM7XX_CLK, 4 * KiB); | ||
929 | sysbus_init_mmio(&s->parent, &s->iomem); | ||
930 | - qdev_init_gpio_in_named(DEVICE(s), npcm7xx_clk_perform_watchdog_reset, | ||
931 | - NPCM7XX_WATCHDOG_RESET_GPIO_IN, NPCM7XX_NR_WATCHDOGS); | ||
932 | } | ||
933 | |||
934 | -static const VMStateDescription vmstate_npcm7xx_clk = { | ||
935 | - .name = "npcm7xx-clk", | ||
936 | +static int npcm7xx_clk_post_load(void *opaque, int version_id) | ||
937 | +{ | ||
938 | + if (version_id >= 1) { | ||
939 | + NPCM7xxCLKState *clk = opaque; | ||
940 | + | ||
941 | + npcm7xx_clk_update_all_clocks(clk); | ||
942 | + } | ||
943 | + | ||
944 | + return 0; | ||
945 | +} | ||
946 | + | ||
947 | +static void npcm7xx_clk_realize(DeviceState *dev, Error **errp) | ||
948 | +{ | ||
949 | + int i; | ||
950 | + NPCM7xxCLKState *s = NPCM7XX_CLK(dev); | ||
951 | + | ||
952 | + qdev_init_gpio_in_named(DEVICE(s), npcm7xx_clk_perform_watchdog_reset, | ||
953 | + NPCM7XX_WATCHDOG_RESET_GPIO_IN, NPCM7XX_NR_WATCHDOGS); | ||
954 | + npcm7xx_clk_init_clock_hierarchy(s); | ||
955 | + | ||
956 | + /* Realize child devices */ | ||
957 | + for (i = 0; i < NPCM7XX_CLOCK_NR_PLLS; ++i) { | ||
958 | + if (!qdev_realize(DEVICE(&s->plls[i]), NULL, errp)) { | ||
959 | + return; | 136 | + return; |
960 | + } | 137 | + } |
961 | + } | 138 | + sysbus_mmio_map(busdev, 0, usart_addr[i]); |
962 | + for (i = 0; i < NPCM7XX_CLOCK_NR_SELS; ++i) { | 139 | + sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, usart_irq[i])); |
963 | + if (!qdev_realize(DEVICE(&s->sels[i]), NULL, errp)) { | 140 | + } |
141 | + | ||
142 | + /* | ||
143 | + * TODO: Connect the USARTs, UARTs and LPUART to the EXTI once the EXTI | ||
144 | + * can handle other gpio-in than the gpios. (e.g. Direct Lines for the | ||
145 | + * usarts) | ||
146 | + */ | ||
147 | + | ||
148 | + /* UART devices */ | ||
149 | + for (int i = 0; i < STM_NUM_UARTS; i++) { | ||
150 | + g_autofree char *name = g_strdup_printf("uart%d-out", STM_NUM_USARTS + i + 1); | ||
151 | + dev = DEVICE(&(s->uart[i])); | ||
152 | + qdev_prop_set_chr(dev, "chardev", serial_hd(STM_NUM_USARTS + i)); | ||
153 | + qdev_connect_clock_in(dev, "clk", | ||
154 | + qdev_get_clock_out(DEVICE(&(s->rcc)), name)); | ||
155 | + busdev = SYS_BUS_DEVICE(dev); | ||
156 | + if (!sysbus_realize(busdev, errp)) { | ||
964 | + return; | 157 | + return; |
965 | + } | 158 | + } |
966 | + } | 159 | + sysbus_mmio_map(busdev, 0, uart_addr[i]); |
967 | + for (i = 0; i < NPCM7XX_CLOCK_NR_DIVIDERS; ++i) { | 160 | + sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, uart_irq[i])); |
968 | + if (!qdev_realize(DEVICE(&s->dividers[i]), NULL, errp)) { | 161 | + } |
969 | + return; | 162 | + |
970 | + } | 163 | + /* LPUART device*/ |
971 | + } | 164 | + dev = DEVICE(&(s->lpuart)); |
972 | +} | 165 | + qdev_prop_set_chr(dev, "chardev", serial_hd(STM_NUM_USARTS + STM_NUM_UARTS)); |
973 | + | 166 | + qdev_connect_clock_in(dev, "clk", |
974 | +static const VMStateDescription vmstate_npcm7xx_clk_pll = { | 167 | + qdev_get_clock_out(DEVICE(&(s->rcc)), "lpuart1-out")); |
975 | + .name = "npcm7xx-clock-pll", | 168 | + busdev = SYS_BUS_DEVICE(dev); |
976 | .version_id = 0, | 169 | + if (!sysbus_realize(busdev, errp)) { |
977 | .minimum_version_id = 0, | 170 | + return; |
978 | - .fields = (VMStateField[]) { | 171 | + } |
979 | - VMSTATE_UINT32_ARRAY(regs, NPCM7xxCLKState, NPCM7XX_CLK_NR_REGS), | 172 | + sysbus_mmio_map(busdev, 0, LPUART_BASE_ADDRESS); |
980 | - VMSTATE_INT64(ref_ns, NPCM7xxCLKState), | 173 | + sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, LPUART_IRQ)); |
981 | + .fields = (VMStateField[]) { | 174 | + |
982 | + VMSTATE_CLOCK(clock_in, NPCM7xxClockPLLState), | 175 | /* APB1 BUS */ |
983 | VMSTATE_END_OF_LIST(), | 176 | create_unimplemented_device("TIM2", 0x40000000, 0x400); |
984 | }, | 177 | create_unimplemented_device("TIM3", 0x40000400, 0x400); |
985 | }; | 178 | @@ -XXX,XX +XXX,XX @@ static void stm32l4x5_soc_realize(DeviceState *dev_soc, Error **errp) |
986 | 179 | create_unimplemented_device("SPI2", 0x40003800, 0x400); | |
987 | +static const VMStateDescription vmstate_npcm7xx_clk_sel = { | 180 | create_unimplemented_device("SPI3", 0x40003C00, 0x400); |
988 | + .name = "npcm7xx-clock-sel", | 181 | /* RESERVED: 0x40004000, 0x400 */ |
989 | + .version_id = 0, | 182 | - create_unimplemented_device("USART2", 0x40004400, 0x400); |
990 | + .minimum_version_id = 0, | 183 | - create_unimplemented_device("USART3", 0x40004800, 0x400); |
991 | + .fields = (VMStateField[]) { | 184 | - create_unimplemented_device("UART4", 0x40004C00, 0x400); |
992 | + VMSTATE_ARRAY_OF_POINTER_TO_STRUCT(clock_in, NPCM7xxClockSELState, | 185 | - create_unimplemented_device("UART5", 0x40005000, 0x400); |
993 | + NPCM7XX_CLK_SEL_MAX_INPUT, 0, vmstate_clock, Clock), | 186 | create_unimplemented_device("I2C1", 0x40005400, 0x400); |
994 | + VMSTATE_END_OF_LIST(), | 187 | create_unimplemented_device("I2C2", 0x40005800, 0x400); |
995 | + }, | 188 | create_unimplemented_device("I2C3", 0x40005C00, 0x400); |
996 | +}; | 189 | @@ -XXX,XX +XXX,XX @@ static void stm32l4x5_soc_realize(DeviceState *dev_soc, Error **errp) |
997 | + | 190 | create_unimplemented_device("DAC1", 0x40007400, 0x400); |
998 | +static const VMStateDescription vmstate_npcm7xx_clk_divider = { | 191 | create_unimplemented_device("OPAMP", 0x40007800, 0x400); |
999 | + .name = "npcm7xx-clock-divider", | 192 | create_unimplemented_device("LPTIM1", 0x40007C00, 0x400); |
1000 | + .version_id = 0, | 193 | - create_unimplemented_device("LPUART1", 0x40008000, 0x400); |
1001 | + .minimum_version_id = 0, | 194 | /* RESERVED: 0x40008400, 0x400 */ |
1002 | + .fields = (VMStateField[]) { | 195 | create_unimplemented_device("SWPMI1", 0x40008800, 0x400); |
1003 | + VMSTATE_CLOCK(clock_in, NPCM7xxClockDividerState), | 196 | /* RESERVED: 0x40008C00, 0x800 */ |
1004 | + VMSTATE_END_OF_LIST(), | 197 | @@ -XXX,XX +XXX,XX @@ static void stm32l4x5_soc_realize(DeviceState *dev_soc, Error **errp) |
1005 | + }, | 198 | create_unimplemented_device("TIM1", 0x40012C00, 0x400); |
1006 | +}; | 199 | create_unimplemented_device("SPI1", 0x40013000, 0x400); |
1007 | + | 200 | create_unimplemented_device("TIM8", 0x40013400, 0x400); |
1008 | +static const VMStateDescription vmstate_npcm7xx_clk = { | 201 | - create_unimplemented_device("USART1", 0x40013800, 0x400); |
1009 | + .name = "npcm7xx-clk", | 202 | /* RESERVED: 0x40013C00, 0x400 */ |
1010 | + .version_id = 1, | 203 | create_unimplemented_device("TIM15", 0x40014000, 0x400); |
1011 | + .minimum_version_id = 1, | 204 | create_unimplemented_device("TIM16", 0x40014400, 0x400); |
1012 | + .post_load = npcm7xx_clk_post_load, | 205 | diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig |
1013 | + .fields = (VMStateField[]) { | 206 | index XXXXXXX..XXXXXXX 100644 |
1014 | + VMSTATE_UINT32_ARRAY(regs, NPCM7xxCLKState, NPCM7XX_CLK_NR_REGS), | 207 | --- a/hw/arm/Kconfig |
1015 | + VMSTATE_INT64(ref_ns, NPCM7xxCLKState), | 208 | +++ b/hw/arm/Kconfig |
1016 | + VMSTATE_CLOCK(clkref, NPCM7xxCLKState), | 209 | @@ -XXX,XX +XXX,XX @@ config STM32L4X5_SOC |
1017 | + VMSTATE_END_OF_LIST(), | 210 | select STM32L4X5_SYSCFG |
1018 | + }, | 211 | select STM32L4X5_RCC |
1019 | +}; | 212 | select STM32L4X5_GPIO |
1020 | + | 213 | + select STM32L4X5_USART |
1021 | +static void npcm7xx_clk_pll_class_init(ObjectClass *klass, void *data) | 214 | |
1022 | +{ | 215 | config XLNX_ZYNQMP_ARM |
1023 | + DeviceClass *dc = DEVICE_CLASS(klass); | 216 | bool |
1024 | + | ||
1025 | + dc->desc = "NPCM7xx Clock PLL Module"; | ||
1026 | + dc->vmsd = &vmstate_npcm7xx_clk_pll; | ||
1027 | +} | ||
1028 | + | ||
1029 | +static void npcm7xx_clk_sel_class_init(ObjectClass *klass, void *data) | ||
1030 | +{ | ||
1031 | + DeviceClass *dc = DEVICE_CLASS(klass); | ||
1032 | + | ||
1033 | + dc->desc = "NPCM7xx Clock SEL Module"; | ||
1034 | + dc->vmsd = &vmstate_npcm7xx_clk_sel; | ||
1035 | +} | ||
1036 | + | ||
1037 | +static void npcm7xx_clk_divider_class_init(ObjectClass *klass, void *data) | ||
1038 | +{ | ||
1039 | + DeviceClass *dc = DEVICE_CLASS(klass); | ||
1040 | + | ||
1041 | + dc->desc = "NPCM7xx Clock Divider Module"; | ||
1042 | + dc->vmsd = &vmstate_npcm7xx_clk_divider; | ||
1043 | +} | ||
1044 | + | ||
1045 | static void npcm7xx_clk_class_init(ObjectClass *klass, void *data) | ||
1046 | { | ||
1047 | ResettableClass *rc = RESETTABLE_CLASS(klass); | ||
1048 | @@ -XXX,XX +XXX,XX @@ static void npcm7xx_clk_class_init(ObjectClass *klass, void *data) | ||
1049 | |||
1050 | dc->desc = "NPCM7xx Clock Control Registers"; | ||
1051 | dc->vmsd = &vmstate_npcm7xx_clk; | ||
1052 | + dc->realize = npcm7xx_clk_realize; | ||
1053 | rc->phases.enter = npcm7xx_clk_enter_reset; | ||
1054 | } | ||
1055 | |||
1056 | +static const TypeInfo npcm7xx_clk_pll_info = { | ||
1057 | + .name = TYPE_NPCM7XX_CLOCK_PLL, | ||
1058 | + .parent = TYPE_DEVICE, | ||
1059 | + .instance_size = sizeof(NPCM7xxClockPLLState), | ||
1060 | + .instance_init = npcm7xx_clk_pll_init, | ||
1061 | + .class_init = npcm7xx_clk_pll_class_init, | ||
1062 | +}; | ||
1063 | + | ||
1064 | +static const TypeInfo npcm7xx_clk_sel_info = { | ||
1065 | + .name = TYPE_NPCM7XX_CLOCK_SEL, | ||
1066 | + .parent = TYPE_DEVICE, | ||
1067 | + .instance_size = sizeof(NPCM7xxClockSELState), | ||
1068 | + .instance_init = npcm7xx_clk_sel_init, | ||
1069 | + .class_init = npcm7xx_clk_sel_class_init, | ||
1070 | +}; | ||
1071 | + | ||
1072 | +static const TypeInfo npcm7xx_clk_divider_info = { | ||
1073 | + .name = TYPE_NPCM7XX_CLOCK_DIVIDER, | ||
1074 | + .parent = TYPE_DEVICE, | ||
1075 | + .instance_size = sizeof(NPCM7xxClockDividerState), | ||
1076 | + .instance_init = npcm7xx_clk_divider_init, | ||
1077 | + .class_init = npcm7xx_clk_divider_class_init, | ||
1078 | +}; | ||
1079 | + | ||
1080 | static const TypeInfo npcm7xx_clk_info = { | ||
1081 | .name = TYPE_NPCM7XX_CLK, | ||
1082 | .parent = TYPE_SYS_BUS_DEVICE, | ||
1083 | @@ -XXX,XX +XXX,XX @@ static const TypeInfo npcm7xx_clk_info = { | ||
1084 | |||
1085 | static void npcm7xx_clk_register_type(void) | ||
1086 | { | ||
1087 | + type_register_static(&npcm7xx_clk_pll_info); | ||
1088 | + type_register_static(&npcm7xx_clk_sel_info); | ||
1089 | + type_register_static(&npcm7xx_clk_divider_info); | ||
1090 | type_register_static(&npcm7xx_clk_info); | ||
1091 | } | ||
1092 | type_init(npcm7xx_clk_register_type); | ||
1093 | -- | 217 | -- |
1094 | 2.20.1 | 218 | 2.34.1 |
1095 | 219 | ||
1096 | 220 | diff view generated by jsdifflib |
1 | From: Hao Wu <wuhaotsh@google.com> | 1 | From: Arnaud Minier <arnaud.minier@telecom-paris.fr> |
---|---|---|---|
2 | 2 | ||
3 | We add a qtest for the PWM in the previous patch. It proves it works as | 3 | Test: |
4 | expected. | 4 | - read/write from/to the usart registers |
5 | 5 | - send/receive a character/string over the serial port | |
6 | Reviewed-by: Havard Skinnemoen <hskinnemoen@google.com> | 6 | |
7 | Reviewed-by: Tyrone Ting <kfting@nuvoton.com> | 7 | Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr> |
8 | Signed-off-by: Hao Wu <wuhaotsh@google.com> | 8 | Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr> |
9 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
10 | Message-id: 20210108190945.949196-6-wuhaotsh@google.com | 10 | Message-id: 20240329174402.60382-6-arnaud.minier@telecom-paris.fr |
11 | [PMM: fix checkpatch nits, remove commented out code] | ||
11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
12 | --- | 13 | --- |
13 | tests/qtest/npcm7xx_pwm-test.c | 490 +++++++++++++++++++++++++++++++++ | 14 | tests/qtest/stm32l4x5_usart-test.c | 315 +++++++++++++++++++++++++++++ |
14 | tests/qtest/meson.build | 1 + | 15 | tests/qtest/meson.build | 4 +- |
15 | 2 files changed, 491 insertions(+) | 16 | 2 files changed, 318 insertions(+), 1 deletion(-) |
16 | create mode 100644 tests/qtest/npcm7xx_pwm-test.c | 17 | create mode 100644 tests/qtest/stm32l4x5_usart-test.c |
17 | 18 | ||
18 | diff --git a/tests/qtest/npcm7xx_pwm-test.c b/tests/qtest/npcm7xx_pwm-test.c | 19 | diff --git a/tests/qtest/stm32l4x5_usart-test.c b/tests/qtest/stm32l4x5_usart-test.c |
19 | new file mode 100644 | 20 | new file mode 100644 |
20 | index XXXXXXX..XXXXXXX | 21 | index XXXXXXX..XXXXXXX |
21 | --- /dev/null | 22 | --- /dev/null |
22 | +++ b/tests/qtest/npcm7xx_pwm-test.c | 23 | +++ b/tests/qtest/stm32l4x5_usart-test.c |
23 | @@ -XXX,XX +XXX,XX @@ | 24 | @@ -XXX,XX +XXX,XX @@ |
24 | +/* | 25 | +/* |
25 | + * QTests for Nuvoton NPCM7xx PWM Modules. | 26 | + * QTest testcase for STML4X5_USART |
26 | + * | 27 | + * |
27 | + * Copyright 2020 Google LLC | 28 | + * Copyright (c) 2023 Arnaud Minier <arnaud.minier@telecom-paris.fr> |
29 | + * Copyright (c) 2023 Inès Varhol <ines.varhol@telecom-paris.fr> | ||
28 | + * | 30 | + * |
29 | + * This program is free software; you can redistribute it and/or modify it | 31 | + * This work is licensed under the terms of the GNU GPL, version 2 or later. |
30 | + * under the terms of the GNU General Public License as published by the | 32 | + * See the COPYING file in the top-level directory. |
31 | + * Free Software Foundation; either version 2 of the License, or | ||
32 | + * (at your option) any later version. | ||
33 | + * | ||
34 | + * This program is distributed in the hope that it will be useful, but WITHOUT | ||
35 | + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
36 | + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | ||
37 | + * for more details. | ||
38 | + */ | 33 | + */ |
39 | + | 34 | + |
40 | +#include "qemu/osdep.h" | 35 | +#include "qemu/osdep.h" |
41 | +#include "qemu/bitops.h" | 36 | +#include "libqtest.h" |
42 | +#include "libqos/libqtest.h" | 37 | +#include "hw/misc/stm32l4x5_rcc_internals.h" |
43 | +#include "qapi/qmp/qdict.h" | 38 | +#include "hw/registerfields.h" |
44 | +#include "qapi/qmp/qnum.h" | 39 | + |
45 | + | 40 | +#define RCC_BASE_ADDR 0x40021000 |
46 | +#define REF_HZ 25000000 | 41 | +/* Use USART 1 ADDR, assume the others work the same */ |
47 | + | 42 | +#define USART1_BASE_ADDR 0x40013800 |
48 | +/* Register field definitions. */ | 43 | + |
49 | +#define CH_EN BIT(0) | 44 | +/* See stm32l4x5_usart for definitions */ |
50 | +#define CH_INV BIT(2) | 45 | +REG32(CR1, 0x00) |
51 | +#define CH_MOD BIT(3) | 46 | + FIELD(CR1, M1, 28, 1) |
52 | + | 47 | + FIELD(CR1, OVER8, 15, 1) |
53 | +/* Registers shared between all PWMs in a module */ | 48 | + FIELD(CR1, M0, 12, 1) |
54 | +#define PPR 0x00 | 49 | + FIELD(CR1, PCE, 10, 1) |
55 | +#define CSR 0x04 | 50 | + FIELD(CR1, TXEIE, 7, 1) |
56 | +#define PCR 0x08 | 51 | + FIELD(CR1, RXNEIE, 5, 1) |
57 | +#define PIER 0x3c | 52 | + FIELD(CR1, TE, 3, 1) |
58 | +#define PIIR 0x40 | 53 | + FIELD(CR1, RE, 2, 1) |
59 | + | 54 | + FIELD(CR1, UE, 0, 1) |
60 | +/* CLK module related */ | 55 | +REG32(CR2, 0x04) |
61 | +#define CLK_BA 0xf0801000 | 56 | +REG32(CR3, 0x08) |
62 | +#define CLKSEL 0x04 | 57 | + FIELD(CR3, OVRDIS, 12, 1) |
63 | +#define CLKDIV1 0x08 | 58 | +REG32(BRR, 0x0C) |
64 | +#define CLKDIV2 0x2c | 59 | +REG32(GTPR, 0x10) |
65 | +#define PLLCON0 0x0c | 60 | +REG32(RTOR, 0x14) |
66 | +#define PLLCON1 0x10 | 61 | +REG32(RQR, 0x18) |
67 | +#define PLL_INDV(rv) extract32((rv), 0, 6) | 62 | +REG32(ISR, 0x1C) |
68 | +#define PLL_FBDV(rv) extract32((rv), 16, 12) | 63 | + FIELD(ISR, TXE, 7, 1) |
69 | +#define PLL_OTDV1(rv) extract32((rv), 8, 3) | 64 | + FIELD(ISR, RXNE, 5, 1) |
70 | +#define PLL_OTDV2(rv) extract32((rv), 13, 3) | 65 | + FIELD(ISR, ORE, 3, 1) |
71 | +#define APB3CKDIV(rv) extract32((rv), 28, 2) | 66 | +REG32(ICR, 0x20) |
72 | +#define CLK2CKDIV(rv) extract32((rv), 0, 1) | 67 | +REG32(RDR, 0x24) |
73 | +#define CLK4CKDIV(rv) extract32((rv), 26, 2) | 68 | +REG32(TDR, 0x28) |
74 | +#define CPUCKSEL(rv) extract32((rv), 0, 2) | 69 | + |
75 | + | 70 | +#define NVIC_ISPR1 0XE000E204 |
76 | +#define MAX_DUTY 1000000 | 71 | +#define NVIC_ICPR1 0xE000E284 |
77 | + | 72 | +#define USART1_IRQ 37 |
78 | +typedef struct PWMModule { | 73 | + |
79 | + int irq; | 74 | +static bool check_nvic_pending(QTestState *qts, unsigned int n) |
80 | + uint64_t base_addr; | 75 | +{ |
81 | +} PWMModule; | 76 | + /* No USART interrupts are less than 32 */ |
82 | + | 77 | + assert(n > 32); |
83 | +typedef struct PWM { | 78 | + n -= 32; |
84 | + uint32_t cnr_offset; | 79 | + return qtest_readl(qts, NVIC_ISPR1) & (1 << n); |
85 | + uint32_t cmr_offset; | 80 | +} |
86 | + uint32_t pdr_offset; | 81 | + |
87 | + uint32_t pwdr_offset; | 82 | +static bool clear_nvic_pending(QTestState *qts, unsigned int n) |
88 | +} PWM; | 83 | +{ |
89 | + | 84 | + /* No USART interrupts are less than 32 */ |
90 | +typedef struct TestData { | 85 | + assert(n > 32); |
91 | + const PWMModule *module; | 86 | + n -= 32; |
92 | + const PWM *pwm; | 87 | + qtest_writel(qts, NVIC_ICPR1, (1 << n)); |
93 | +} TestData; | 88 | + return true; |
94 | + | 89 | +} |
95 | +static const PWMModule pwm_module_list[] = { | 90 | + |
96 | + { | 91 | +/* |
97 | + .irq = 93, | 92 | + * Wait indefinitely for the flag to be updated. |
98 | + .base_addr = 0xf0103000 | 93 | + * If this is run on a slow CI runner, |
99 | + }, | 94 | + * the meson harness will timeout after 10 minutes for us. |
100 | + { | 95 | + */ |
101 | + .irq = 94, | 96 | +static bool usart_wait_for_flag(QTestState *qts, uint32_t event_addr, |
102 | + .base_addr = 0xf0104000 | 97 | + uint32_t flag) |
98 | +{ | ||
99 | + while (true) { | ||
100 | + if ((qtest_readl(qts, event_addr) & flag)) { | ||
101 | + return true; | ||
102 | + } | ||
103 | + g_usleep(1000); | ||
103 | + } | 104 | + } |
104 | +}; | 105 | + |
105 | + | 106 | + return false; |
106 | +static const PWM pwm_list[] = { | 107 | +} |
107 | + { | 108 | + |
108 | + .cnr_offset = 0x0c, | 109 | +static void usart_receive_string(QTestState *qts, int sock_fd, const char *in, |
109 | + .cmr_offset = 0x10, | 110 | + char *out) |
110 | + .pdr_offset = 0x14, | 111 | +{ |
111 | + .pwdr_offset = 0x44, | 112 | + int i, in_len = strlen(in); |
112 | + }, | 113 | + |
113 | + { | 114 | + g_assert_true(send(sock_fd, in, in_len, 0) == in_len); |
114 | + .cnr_offset = 0x18, | 115 | + for (i = 0; i < in_len; i++) { |
115 | + .cmr_offset = 0x1c, | 116 | + g_assert_true(usart_wait_for_flag(qts, |
116 | + .pdr_offset = 0x20, | 117 | + USART1_BASE_ADDR + A_ISR, R_ISR_RXNE_MASK)); |
117 | + .pwdr_offset = 0x48, | 118 | + out[i] = qtest_readl(qts, USART1_BASE_ADDR + A_RDR); |
118 | + }, | ||
119 | + { | ||
120 | + .cnr_offset = 0x24, | ||
121 | + .cmr_offset = 0x28, | ||
122 | + .pdr_offset = 0x2c, | ||
123 | + .pwdr_offset = 0x4c, | ||
124 | + }, | ||
125 | + { | ||
126 | + .cnr_offset = 0x30, | ||
127 | + .cmr_offset = 0x34, | ||
128 | + .pdr_offset = 0x38, | ||
129 | + .pwdr_offset = 0x50, | ||
130 | + }, | ||
131 | +}; | ||
132 | + | ||
133 | +static const int ppr_base[] = { 0, 0, 8, 8 }; | ||
134 | +static const int csr_base[] = { 0, 4, 8, 12 }; | ||
135 | +static const int pcr_base[] = { 0, 8, 12, 16 }; | ||
136 | + | ||
137 | +static const uint32_t ppr_list[] = { | ||
138 | + 0, | ||
139 | + 1, | ||
140 | + 10, | ||
141 | + 100, | ||
142 | + 255, /* Max possible value. */ | ||
143 | +}; | ||
144 | + | ||
145 | +static const uint32_t csr_list[] = { | ||
146 | + 0, | ||
147 | + 1, | ||
148 | + 2, | ||
149 | + 3, | ||
150 | + 4, /* Max possible value. */ | ||
151 | +}; | ||
152 | + | ||
153 | +static const uint32_t cnr_list[] = { | ||
154 | + 0, | ||
155 | + 1, | ||
156 | + 50, | ||
157 | + 100, | ||
158 | + 150, | ||
159 | + 200, | ||
160 | + 1000, | ||
161 | + 10000, | ||
162 | + 65535, /* Max possible value. */ | ||
163 | +}; | ||
164 | + | ||
165 | +static const uint32_t cmr_list[] = { | ||
166 | + 0, | ||
167 | + 1, | ||
168 | + 10, | ||
169 | + 50, | ||
170 | + 100, | ||
171 | + 150, | ||
172 | + 200, | ||
173 | + 1000, | ||
174 | + 10000, | ||
175 | + 65535, /* Max possible value. */ | ||
176 | +}; | ||
177 | + | ||
178 | +/* Returns the index of the PWM module. */ | ||
179 | +static int pwm_module_index(const PWMModule *module) | ||
180 | +{ | ||
181 | + ptrdiff_t diff = module - pwm_module_list; | ||
182 | + | ||
183 | + g_assert_true(diff >= 0 && diff < ARRAY_SIZE(pwm_module_list)); | ||
184 | + | ||
185 | + return diff; | ||
186 | +} | ||
187 | + | ||
188 | +/* Returns the index of the PWM entry. */ | ||
189 | +static int pwm_index(const PWM *pwm) | ||
190 | +{ | ||
191 | + ptrdiff_t diff = pwm - pwm_list; | ||
192 | + | ||
193 | + g_assert_true(diff >= 0 && diff < ARRAY_SIZE(pwm_list)); | ||
194 | + | ||
195 | + return diff; | ||
196 | +} | ||
197 | + | ||
198 | +static uint64_t pwm_qom_get(QTestState *qts, const char *path, const char *name) | ||
199 | +{ | ||
200 | + QDict *response; | ||
201 | + | ||
202 | + g_test_message("Getting properties %s from %s", name, path); | ||
203 | + response = qtest_qmp(qts, "{ 'execute': 'qom-get'," | ||
204 | + " 'arguments': { 'path': %s, 'property': %s}}", | ||
205 | + path, name); | ||
206 | + /* The qom set message returns successfully. */ | ||
207 | + g_assert_true(qdict_haskey(response, "return")); | ||
208 | + return qnum_get_uint(qobject_to(QNum, qdict_get(response, "return"))); | ||
209 | +} | ||
210 | + | ||
211 | +static uint64_t pwm_get_freq(QTestState *qts, int module_index, int pwm_index) | ||
212 | +{ | ||
213 | + char path[100]; | ||
214 | + char name[100]; | ||
215 | + | ||
216 | + sprintf(path, "/machine/soc/pwm[%d]", module_index); | ||
217 | + sprintf(name, "freq[%d]", pwm_index); | ||
218 | + | ||
219 | + return pwm_qom_get(qts, path, name); | ||
220 | +} | ||
221 | + | ||
222 | +static uint64_t pwm_get_duty(QTestState *qts, int module_index, int pwm_index) | ||
223 | +{ | ||
224 | + char path[100]; | ||
225 | + char name[100]; | ||
226 | + | ||
227 | + sprintf(path, "/machine/soc/pwm[%d]", module_index); | ||
228 | + sprintf(name, "duty[%d]", pwm_index); | ||
229 | + | ||
230 | + return pwm_qom_get(qts, path, name); | ||
231 | +} | ||
232 | + | ||
233 | +static uint32_t get_pll(uint32_t con) | ||
234 | +{ | ||
235 | + return REF_HZ * PLL_FBDV(con) / (PLL_INDV(con) * PLL_OTDV1(con) | ||
236 | + * PLL_OTDV2(con)); | ||
237 | +} | ||
238 | + | ||
239 | +static uint64_t read_pclk(QTestState *qts) | ||
240 | +{ | ||
241 | + uint64_t freq = REF_HZ; | ||
242 | + uint32_t clksel = qtest_readl(qts, CLK_BA + CLKSEL); | ||
243 | + uint32_t pllcon; | ||
244 | + uint32_t clkdiv1 = qtest_readl(qts, CLK_BA + CLKDIV1); | ||
245 | + uint32_t clkdiv2 = qtest_readl(qts, CLK_BA + CLKDIV2); | ||
246 | + | ||
247 | + switch (CPUCKSEL(clksel)) { | ||
248 | + case 0: | ||
249 | + pllcon = qtest_readl(qts, CLK_BA + PLLCON0); | ||
250 | + freq = get_pll(pllcon); | ||
251 | + break; | ||
252 | + case 1: | ||
253 | + pllcon = qtest_readl(qts, CLK_BA + PLLCON1); | ||
254 | + freq = get_pll(pllcon); | ||
255 | + break; | ||
256 | + case 2: | ||
257 | + break; | ||
258 | + case 3: | ||
259 | + break; | ||
260 | + default: | ||
261 | + g_assert_not_reached(); | ||
262 | + } | 119 | + } |
263 | + | 120 | + out[i] = '\0'; |
264 | + freq >>= (CLK2CKDIV(clkdiv1) + CLK4CKDIV(clkdiv1) + APB3CKDIV(clkdiv2)); | 121 | +} |
265 | + | 122 | + |
266 | + return freq; | 123 | +static void usart_send_string(QTestState *qts, const char *in) |
267 | +} | 124 | +{ |
268 | + | 125 | + int i, in_len = strlen(in); |
269 | +static uint32_t pwm_selector(uint32_t csr) | 126 | + |
270 | +{ | 127 | + for (i = 0; i < in_len; i++) { |
271 | + switch (csr) { | 128 | + qtest_writel(qts, USART1_BASE_ADDR + A_TDR, in[i]); |
272 | + case 0: | 129 | + g_assert_true(usart_wait_for_flag(qts, |
273 | + return 2; | 130 | + USART1_BASE_ADDR + A_ISR, R_ISR_TXE_MASK)); |
274 | + case 1: | ||
275 | + return 4; | ||
276 | + case 2: | ||
277 | + return 8; | ||
278 | + case 3: | ||
279 | + return 16; | ||
280 | + case 4: | ||
281 | + return 1; | ||
282 | + default: | ||
283 | + g_assert_not_reached(); | ||
284 | + } | 131 | + } |
285 | +} | 132 | +} |
286 | + | 133 | + |
287 | +static uint64_t pwm_compute_freq(QTestState *qts, uint32_t ppr, uint32_t csr, | 134 | +/* Init the RCC clocks to run at 80 MHz */ |
288 | + uint32_t cnr) | 135 | +static void init_clocks(QTestState *qts) |
289 | +{ | 136 | +{ |
290 | + return read_pclk(qts) / ((ppr + 1) * pwm_selector(csr) * (cnr + 1)); | 137 | + uint32_t value; |
291 | +} | 138 | + |
292 | + | 139 | + /* MSIRANGE can be set only when MSI is OFF or READY */ |
293 | +static uint64_t pwm_compute_duty(uint32_t cnr, uint32_t cmr, bool inverted) | 140 | + qtest_writel(qts, (RCC_BASE_ADDR + A_CR), R_CR_MSION_MASK); |
294 | +{ | 141 | + |
295 | + uint64_t duty; | 142 | + /* Clocking from MSI, in case MSI was not the default source */ |
296 | + | 143 | + qtest_writel(qts, (RCC_BASE_ADDR + A_CFGR), 0); |
297 | + if (cnr == 0) { | 144 | + |
298 | + /* PWM is stopped. */ | 145 | + /* |
299 | + duty = 0; | 146 | + * Update PLL and set MSI as the source clock. |
300 | + } else if (cmr >= cnr) { | 147 | + * PLLM = 1 --> 000 |
301 | + duty = MAX_DUTY; | 148 | + * PLLN = 40 --> 40 |
302 | + } else { | 149 | + * PPLLR = 2 --> 00 |
303 | + duty = MAX_DUTY * (cmr + 1) / (cnr + 1); | 150 | + * PLLDIV = unused, PLLP = unused (SAI3), PLLQ = unused (48M1) |
304 | + } | 151 | + * SRC = MSI --> 01 |
305 | + | 152 | + */ |
306 | + if (inverted) { | 153 | + qtest_writel(qts, (RCC_BASE_ADDR + A_PLLCFGR), R_PLLCFGR_PLLREN_MASK | |
307 | + duty = MAX_DUTY - duty; | 154 | + (40 << R_PLLCFGR_PLLN_SHIFT) | |
308 | + } | 155 | + (0b01 << R_PLLCFGR_PLLSRC_SHIFT)); |
309 | + | 156 | + |
310 | + return duty; | 157 | + /* PLL activation */ |
311 | +} | 158 | + |
312 | + | 159 | + value = qtest_readl(qts, (RCC_BASE_ADDR + A_CR)); |
313 | +static uint32_t pwm_read(QTestState *qts, const TestData *td, unsigned offset) | 160 | + qtest_writel(qts, (RCC_BASE_ADDR + A_CR), value | R_CR_PLLON_MASK); |
314 | +{ | 161 | + |
315 | + return qtest_readl(qts, td->module->base_addr + offset); | 162 | + /* RCC_CFGR is OK by defaut */ |
316 | +} | 163 | + qtest_writel(qts, (RCC_BASE_ADDR + A_CFGR), 0); |
317 | + | 164 | + |
318 | +static void pwm_write(QTestState *qts, const TestData *td, unsigned offset, | 165 | + /* CCIPR : no periph clock by default */ |
319 | + uint32_t value) | 166 | + qtest_writel(qts, (RCC_BASE_ADDR + A_CCIPR), 0); |
320 | +{ | 167 | + |
321 | + qtest_writel(qts, td->module->base_addr + offset, value); | 168 | + /* Switches on the PLL clock source */ |
322 | +} | 169 | + value = qtest_readl(qts, (RCC_BASE_ADDR + A_CFGR)); |
323 | + | 170 | + qtest_writel(qts, (RCC_BASE_ADDR + A_CFGR), (value & ~R_CFGR_SW_MASK) | |
324 | +static uint32_t pwm_read_ppr(QTestState *qts, const TestData *td) | 171 | + (0b11 << R_CFGR_SW_SHIFT)); |
325 | +{ | 172 | + |
326 | + return extract32(pwm_read(qts, td, PPR), ppr_base[pwm_index(td->pwm)], 8); | 173 | + /* Enable SYSCFG clock enabled */ |
327 | +} | 174 | + qtest_writel(qts, (RCC_BASE_ADDR + A_APB2ENR), R_APB2ENR_SYSCFGEN_MASK); |
328 | + | 175 | + |
329 | +static void pwm_write_ppr(QTestState *qts, const TestData *td, uint32_t value) | 176 | + /* Enable the IO port B clock (See p.252) */ |
330 | +{ | 177 | + qtest_writel(qts, (RCC_BASE_ADDR + A_AHB2ENR), R_AHB2ENR_GPIOBEN_MASK); |
331 | + pwm_write(qts, td, PPR, value << ppr_base[pwm_index(td->pwm)]); | 178 | + |
332 | +} | 179 | + /* Enable the clock for USART1 (cf p.259) */ |
333 | + | 180 | + /* We rewrite SYSCFGEN to not disable it */ |
334 | +static uint32_t pwm_read_csr(QTestState *qts, const TestData *td) | 181 | + qtest_writel(qts, (RCC_BASE_ADDR + A_APB2ENR), |
335 | +{ | 182 | + R_APB2ENR_SYSCFGEN_MASK | R_APB2ENR_USART1EN_MASK); |
336 | + return extract32(pwm_read(qts, td, CSR), csr_base[pwm_index(td->pwm)], 3); | 183 | + |
337 | +} | 184 | + /* TODO: Enable usart via gpio */ |
338 | + | 185 | + |
339 | +static void pwm_write_csr(QTestState *qts, const TestData *td, uint32_t value) | 186 | + /* Set PCLK as the clock for USART1(cf p.272) i.e. reset both bits */ |
340 | +{ | 187 | + qtest_writel(qts, (RCC_BASE_ADDR + A_CCIPR), 0); |
341 | + pwm_write(qts, td, CSR, value << csr_base[pwm_index(td->pwm)]); | 188 | + |
342 | +} | 189 | + /* Reset USART1 (see p.249) */ |
343 | + | 190 | + qtest_writel(qts, (RCC_BASE_ADDR + A_APB2RSTR), 1 << 14); |
344 | +static uint32_t pwm_read_pcr(QTestState *qts, const TestData *td) | 191 | + qtest_writel(qts, (RCC_BASE_ADDR + A_APB2RSTR), 0); |
345 | +{ | 192 | +} |
346 | + return extract32(pwm_read(qts, td, PCR), pcr_base[pwm_index(td->pwm)], 4); | 193 | + |
347 | +} | 194 | +static void init_uart(QTestState *qts) |
348 | + | 195 | +{ |
349 | +static void pwm_write_pcr(QTestState *qts, const TestData *td, uint32_t value) | 196 | + uint32_t cr1; |
350 | +{ | 197 | + |
351 | + pwm_write(qts, td, PCR, value << pcr_base[pwm_index(td->pwm)]); | 198 | + init_clocks(qts); |
352 | +} | 199 | + |
353 | + | 200 | + /* |
354 | +static uint32_t pwm_read_cnr(QTestState *qts, const TestData *td) | 201 | + * For 115200 bauds, see p.1349. |
355 | +{ | 202 | + * The clock has a frequency of 80Mhz, |
356 | + return pwm_read(qts, td, td->pwm->cnr_offset); | 203 | + * for 115200, we have to put a divider of 695 = 0x2B7. |
357 | +} | 204 | + */ |
358 | + | 205 | + qtest_writel(qts, (USART1_BASE_ADDR + A_BRR), 0x2B7); |
359 | +static void pwm_write_cnr(QTestState *qts, const TestData *td, uint32_t value) | 206 | + |
360 | +{ | 207 | + /* |
361 | + pwm_write(qts, td, td->pwm->cnr_offset, value); | 208 | + * Set the oversampling by 16, |
362 | +} | 209 | + * disable the parity control and |
363 | + | 210 | + * set the word length to 8. (cf p.1377) |
364 | +static uint32_t pwm_read_cmr(QTestState *qts, const TestData *td) | 211 | + */ |
365 | +{ | 212 | + cr1 = qtest_readl(qts, (USART1_BASE_ADDR + A_CR1)); |
366 | + return pwm_read(qts, td, td->pwm->cmr_offset); | 213 | + cr1 &= ~(R_CR1_M1_MASK | R_CR1_M0_MASK | R_CR1_OVER8_MASK | R_CR1_PCE_MASK); |
367 | +} | 214 | + qtest_writel(qts, (USART1_BASE_ADDR + A_CR1), cr1); |
368 | + | 215 | + |
369 | +static void pwm_write_cmr(QTestState *qts, const TestData *td, uint32_t value) | 216 | + /* Enable the transmitter, the receiver and the USART. */ |
370 | +{ | 217 | + qtest_writel(qts, (USART1_BASE_ADDR + A_CR1), |
371 | + pwm_write(qts, td, td->pwm->cmr_offset, value); | 218 | + R_CR1_UE_MASK | R_CR1_RE_MASK | R_CR1_TE_MASK); |
372 | +} | 219 | +} |
373 | + | 220 | + |
374 | +/* Check pwm registers can be reset to default value */ | 221 | +static void test_write_read(void) |
375 | +static void test_init(gconstpointer test_data) | 222 | +{ |
376 | +{ | 223 | + QTestState *qts = qtest_init("-M b-l475e-iot01a"); |
377 | + const TestData *td = test_data; | 224 | + |
378 | + QTestState *qts = qtest_init("-machine quanta-gsj"); | 225 | + /* Test that we can write and retrieve a value from the device */ |
379 | + int module = pwm_module_index(td->module); | 226 | + qtest_writel(qts, USART1_BASE_ADDR + A_TDR, 0xFFFFFFFF); |
380 | + int pwm = pwm_index(td->pwm); | 227 | + const uint32_t tdr = qtest_readl(qts, USART1_BASE_ADDR + A_TDR); |
381 | + | 228 | + g_assert_cmpuint(tdr, ==, 0x000001FF); |
382 | + g_assert_cmpuint(pwm_get_freq(qts, module, pwm), ==, 0); | 229 | +} |
383 | + g_assert_cmpuint(pwm_get_duty(qts, module, pwm), ==, 0); | 230 | + |
231 | +static void test_receive_char(void) | ||
232 | +{ | ||
233 | + int sock_fd; | ||
234 | + uint32_t cr1; | ||
235 | + QTestState *qts = qtest_init_with_serial("-M b-l475e-iot01a", &sock_fd); | ||
236 | + | ||
237 | + init_uart(qts); | ||
238 | + | ||
239 | + /* Try without initializing IRQ */ | ||
240 | + g_assert_true(send(sock_fd, "a", 1, 0) == 1); | ||
241 | + usart_wait_for_flag(qts, USART1_BASE_ADDR + A_ISR, R_ISR_RXNE_MASK); | ||
242 | + g_assert_cmphex(qtest_readl(qts, USART1_BASE_ADDR + A_RDR), ==, 'a'); | ||
243 | + g_assert_false(check_nvic_pending(qts, USART1_IRQ)); | ||
244 | + | ||
245 | + /* Now with the IRQ */ | ||
246 | + cr1 = qtest_readl(qts, (USART1_BASE_ADDR + A_CR1)); | ||
247 | + cr1 |= R_CR1_RXNEIE_MASK; | ||
248 | + qtest_writel(qts, USART1_BASE_ADDR + A_CR1, cr1); | ||
249 | + g_assert_true(send(sock_fd, "b", 1, 0) == 1); | ||
250 | + usart_wait_for_flag(qts, USART1_BASE_ADDR + A_ISR, R_ISR_RXNE_MASK); | ||
251 | + g_assert_cmphex(qtest_readl(qts, USART1_BASE_ADDR + A_RDR), ==, 'b'); | ||
252 | + g_assert_true(check_nvic_pending(qts, USART1_IRQ)); | ||
253 | + clear_nvic_pending(qts, USART1_IRQ); | ||
254 | + | ||
255 | + close(sock_fd); | ||
384 | + | 256 | + |
385 | + qtest_quit(qts); | 257 | + qtest_quit(qts); |
386 | +} | 258 | +} |
387 | + | 259 | + |
388 | +/* One-shot mode should not change frequency and duty cycle. */ | 260 | +static void test_send_char(void) |
389 | +static void test_oneshot(gconstpointer test_data) | 261 | +{ |
390 | +{ | 262 | + int sock_fd; |
391 | + const TestData *td = test_data; | 263 | + char s[1]; |
392 | + QTestState *qts = qtest_init("-machine quanta-gsj"); | 264 | + uint32_t cr1; |
393 | + int module = pwm_module_index(td->module); | 265 | + QTestState *qts = qtest_init_with_serial("-M b-l475e-iot01a", &sock_fd); |
394 | + int pwm = pwm_index(td->pwm); | 266 | + |
395 | + uint32_t ppr, csr, pcr; | 267 | + init_uart(qts); |
396 | + int i, j; | 268 | + |
397 | + | 269 | + /* Try without initializing IRQ */ |
398 | + pcr = CH_EN; | 270 | + qtest_writel(qts, USART1_BASE_ADDR + A_TDR, 'c'); |
399 | + for (i = 0; i < ARRAY_SIZE(ppr_list); ++i) { | 271 | + g_assert_true(recv(sock_fd, s, 1, 0) == 1); |
400 | + ppr = ppr_list[i]; | 272 | + g_assert_cmphex(s[0], ==, 'c'); |
401 | + pwm_write_ppr(qts, td, ppr); | 273 | + g_assert_false(check_nvic_pending(qts, USART1_IRQ)); |
402 | + | 274 | + |
403 | + for (j = 0; j < ARRAY_SIZE(csr_list); ++j) { | 275 | + /* Now with the IRQ */ |
404 | + csr = csr_list[j]; | 276 | + cr1 = qtest_readl(qts, (USART1_BASE_ADDR + A_CR1)); |
405 | + pwm_write_csr(qts, td, csr); | 277 | + cr1 |= R_CR1_TXEIE_MASK; |
406 | + pwm_write_pcr(qts, td, pcr); | 278 | + qtest_writel(qts, USART1_BASE_ADDR + A_CR1, cr1); |
407 | + | 279 | + qtest_writel(qts, USART1_BASE_ADDR + A_TDR, 'd'); |
408 | + g_assert_cmpuint(pwm_read_ppr(qts, td), ==, ppr); | 280 | + g_assert_true(recv(sock_fd, s, 1, 0) == 1); |
409 | + g_assert_cmpuint(pwm_read_csr(qts, td), ==, csr); | 281 | + g_assert_cmphex(s[0], ==, 'd'); |
410 | + g_assert_cmpuint(pwm_read_pcr(qts, td), ==, pcr); | 282 | + g_assert_true(check_nvic_pending(qts, USART1_IRQ)); |
411 | + g_assert_cmpuint(pwm_get_freq(qts, module, pwm), ==, 0); | 283 | + clear_nvic_pending(qts, USART1_IRQ); |
412 | + g_assert_cmpuint(pwm_get_duty(qts, module, pwm), ==, 0); | 284 | + |
413 | + } | 285 | + close(sock_fd); |
414 | + } | ||
415 | + | 286 | + |
416 | + qtest_quit(qts); | 287 | + qtest_quit(qts); |
417 | +} | 288 | +} |
418 | + | 289 | + |
419 | +/* In toggle mode, the PWM generates correct outputs. */ | 290 | +static void test_receive_str(void) |
420 | +static void test_toggle(gconstpointer test_data) | 291 | +{ |
421 | +{ | 292 | + int sock_fd; |
422 | + const TestData *td = test_data; | 293 | + char s[10]; |
423 | + QTestState *qts = qtest_init("-machine quanta-gsj"); | 294 | + QTestState *qts = qtest_init_with_serial("-M b-l475e-iot01a", &sock_fd); |
424 | + int module = pwm_module_index(td->module); | 295 | + |
425 | + int pwm = pwm_index(td->pwm); | 296 | + init_uart(qts); |
426 | + uint32_t ppr, csr, pcr, cnr, cmr; | 297 | + |
427 | + int i, j, k, l; | 298 | + usart_receive_string(qts, sock_fd, "hello", s); |
428 | + uint64_t expected_freq, expected_duty; | 299 | + g_assert_true(memcmp(s, "hello", 5) == 0); |
429 | + | 300 | + |
430 | + pcr = CH_EN | CH_MOD; | 301 | + close(sock_fd); |
431 | + for (i = 0; i < ARRAY_SIZE(ppr_list); ++i) { | ||
432 | + ppr = ppr_list[i]; | ||
433 | + pwm_write_ppr(qts, td, ppr); | ||
434 | + | ||
435 | + for (j = 0; j < ARRAY_SIZE(csr_list); ++j) { | ||
436 | + csr = csr_list[j]; | ||
437 | + pwm_write_csr(qts, td, csr); | ||
438 | + | ||
439 | + for (k = 0; k < ARRAY_SIZE(cnr_list); ++k) { | ||
440 | + cnr = cnr_list[k]; | ||
441 | + pwm_write_cnr(qts, td, cnr); | ||
442 | + | ||
443 | + for (l = 0; l < ARRAY_SIZE(cmr_list); ++l) { | ||
444 | + cmr = cmr_list[l]; | ||
445 | + pwm_write_cmr(qts, td, cmr); | ||
446 | + expected_freq = pwm_compute_freq(qts, ppr, csr, cnr); | ||
447 | + expected_duty = pwm_compute_duty(cnr, cmr, false); | ||
448 | + | ||
449 | + pwm_write_pcr(qts, td, pcr); | ||
450 | + g_assert_cmpuint(pwm_read_ppr(qts, td), ==, ppr); | ||
451 | + g_assert_cmpuint(pwm_read_csr(qts, td), ==, csr); | ||
452 | + g_assert_cmpuint(pwm_read_pcr(qts, td), ==, pcr); | ||
453 | + g_assert_cmpuint(pwm_read_cnr(qts, td), ==, cnr); | ||
454 | + g_assert_cmpuint(pwm_read_cmr(qts, td), ==, cmr); | ||
455 | + g_assert_cmpuint(pwm_get_duty(qts, module, pwm), | ||
456 | + ==, expected_duty); | ||
457 | + if (expected_duty != 0 && expected_duty != 100) { | ||
458 | + /* Duty cycle with 0 or 100 doesn't need frequency. */ | ||
459 | + g_assert_cmpuint(pwm_get_freq(qts, module, pwm), | ||
460 | + ==, expected_freq); | ||
461 | + } | ||
462 | + | ||
463 | + /* Test inverted mode */ | ||
464 | + expected_duty = pwm_compute_duty(cnr, cmr, true); | ||
465 | + pwm_write_pcr(qts, td, pcr | CH_INV); | ||
466 | + g_assert_cmpuint(pwm_read_pcr(qts, td), ==, pcr | CH_INV); | ||
467 | + g_assert_cmpuint(pwm_get_duty(qts, module, pwm), | ||
468 | + ==, expected_duty); | ||
469 | + if (expected_duty != 0 && expected_duty != 100) { | ||
470 | + /* Duty cycle with 0 or 100 doesn't need frequency. */ | ||
471 | + g_assert_cmpuint(pwm_get_freq(qts, module, pwm), | ||
472 | + ==, expected_freq); | ||
473 | + } | ||
474 | + | ||
475 | + } | ||
476 | + } | ||
477 | + } | ||
478 | + } | ||
479 | + | 302 | + |
480 | + qtest_quit(qts); | 303 | + qtest_quit(qts); |
481 | +} | 304 | +} |
482 | + | 305 | + |
483 | +static void pwm_add_test(const char *name, const TestData* td, | 306 | +static void test_send_str(void) |
484 | + GTestDataFunc fn) | 307 | +{ |
485 | +{ | 308 | + int sock_fd; |
486 | + g_autofree char *full_name = g_strdup_printf( | 309 | + char s[10]; |
487 | + "npcm7xx_pwm/module[%d]/pwm[%d]/%s", pwm_module_index(td->module), | 310 | + QTestState *qts = qtest_init_with_serial("-M b-l475e-iot01a", &sock_fd); |
488 | + pwm_index(td->pwm), name); | 311 | + |
489 | + qtest_add_data_func(full_name, td, fn); | 312 | + init_uart(qts); |
490 | +} | 313 | + |
491 | +#define add_test(name, td) pwm_add_test(#name, td, test_##name) | 314 | + usart_send_string(qts, "world"); |
315 | + g_assert_true(recv(sock_fd, s, 10, 0) == 5); | ||
316 | + g_assert_true(memcmp(s, "world", 5) == 0); | ||
317 | + | ||
318 | + close(sock_fd); | ||
319 | + | ||
320 | + qtest_quit(qts); | ||
321 | +} | ||
492 | + | 322 | + |
493 | +int main(int argc, char **argv) | 323 | +int main(int argc, char **argv) |
494 | +{ | 324 | +{ |
495 | + TestData test_data_list[ARRAY_SIZE(pwm_module_list) * ARRAY_SIZE(pwm_list)]; | 325 | + int ret; |
496 | + | 326 | + |
497 | + g_test_init(&argc, &argv, NULL); | 327 | + g_test_init(&argc, &argv, NULL); |
498 | + | 328 | + g_test_set_nonfatal_assertions(); |
499 | + for (int i = 0; i < ARRAY_SIZE(pwm_module_list); ++i) { | 329 | + |
500 | + for (int j = 0; j < ARRAY_SIZE(pwm_list); ++j) { | 330 | + qtest_add_func("stm32l4x5/usart/write_read", test_write_read); |
501 | + TestData *td = &test_data_list[i * ARRAY_SIZE(pwm_list) + j]; | 331 | + qtest_add_func("stm32l4x5/usart/receive_char", test_receive_char); |
502 | + | 332 | + qtest_add_func("stm32l4x5/usart/send_char", test_send_char); |
503 | + td->module = &pwm_module_list[i]; | 333 | + qtest_add_func("stm32l4x5/usart/receive_str", test_receive_str); |
504 | + td->pwm = &pwm_list[j]; | 334 | + qtest_add_func("stm32l4x5/usart/send_str", test_send_str); |
505 | + | 335 | + ret = g_test_run(); |
506 | + add_test(init, td); | 336 | + |
507 | + add_test(oneshot, td); | 337 | + return ret; |
508 | + add_test(toggle, td); | 338 | +} |
509 | + } | 339 | + |
510 | + } | ||
511 | + | ||
512 | + return g_test_run(); | ||
513 | +} | ||
514 | diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build | 340 | diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build |
515 | index XXXXXXX..XXXXXXX 100644 | 341 | index XXXXXXX..XXXXXXX 100644 |
516 | --- a/tests/qtest/meson.build | 342 | --- a/tests/qtest/meson.build |
517 | +++ b/tests/qtest/meson.build | 343 | +++ b/tests/qtest/meson.build |
518 | @@ -XXX,XX +XXX,XX @@ qtests_sparc64 = \ | 344 | @@ -XXX,XX +XXX,XX @@ slow_qtests = { |
519 | qtests_npcm7xx = \ | 345 | 'npcm7xx_pwm-test': 300, |
520 | ['npcm7xx_adc-test', | 346 | 'npcm7xx_watchdog_timer-test': 120, |
521 | 'npcm7xx_gpio-test', | 347 | 'qom-test' : 900, |
522 | + 'npcm7xx_pwm-test', | 348 | + 'stm32l4x5_usart-test' : 600, |
523 | 'npcm7xx_rng-test', | 349 | 'test-hmp' : 240, |
524 | 'npcm7xx_timer-test', | 350 | 'pxe-test': 610, |
525 | 'npcm7xx_watchdog_timer-test'] | 351 | 'prom-env-test': 360, |
352 | @@ -XXX,XX +XXX,XX @@ qtests_stm32l4x5 = \ | ||
353 | ['stm32l4x5_exti-test', | ||
354 | 'stm32l4x5_syscfg-test', | ||
355 | 'stm32l4x5_rcc-test', | ||
356 | - 'stm32l4x5_gpio-test'] | ||
357 | + 'stm32l4x5_gpio-test', | ||
358 | + 'stm32l4x5_usart-test'] | ||
359 | |||
360 | qtests_arm = \ | ||
361 | (config_all_devices.has_key('CONFIG_MPS2') ? ['sse-timer-test'] : []) + \ | ||
526 | -- | 362 | -- |
527 | 2.20.1 | 363 | 2.34.1 |
528 | 364 | ||
529 | 365 | diff view generated by jsdifflib |