Series comparison

-[PULL 00/21] target-arm queue
+[PULL 00/24] target-arm queue
-Arm queue; not huge but I figured I might as well send it out since
+Hi; here's a queue of arm patches (plus a few elf2dmp changes);
-I've been doing code review today and there's no queue of unprocessed
+mostly these are minor cleanups and bugfixes.
 pullreqs...
 thanks
 -- PMM
-The following changes since commit b3f846c59d8405bb87c551187721fc92ff2f1b92:
+The following changes since commit deaca3fd30d3a8829160f8d3705d65ad83176800:
-  Merge remote-tracking branch 'remotes/huth-gitlab/tags/pull-request-2021-01-11v2' into staging (2021-01-11 15:15:35 +0000)
+  Merge tag 'pull-vfio-20231018' of https://github.com/legoater/qemu into staging (2023-10-18 06:21:15 -0400)
 are available in the Git repository at:
-  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210112
+  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20231019
-for you to fetch changes up to 19d131395ccaf503db21dadd8257e6dc9fc1d7de:
+for you to fetch changes up to 2a052b4ee01b3c413cef2ef49cb780cde17d4ba1:
-  ui/cocoa: Fix openFile: deprecation on Big Sur (2021-01-12 11:38:37 +0000)
+  contrib/elf2dmp: Use g_malloc(), g_new() and g_free() (2023-10-19 14:32:13 +0100)
 ----------------------------------------------------------------
 target-arm queue:
- * arm: Support emulation of ARMv8.4-TTST extension
+ * hw/arm: Move raspberrypi-fw-defs.h to the include/hw/arm/ folder
- * arm: Update cpu.h ID register field definitions
+ * hw/arm/exynos4210: Get arm_boot_info declaration from 'hw/arm/boot'
- * arm: Fix breakage of XScale instruction emulation
+ * xlnx devices: remove deprecated device reset
- * hw/net/lan9118: Fix RX Status FIFO PEEK value
+ * xlnx-bbram: hw/nvram: Use dot in device type name
- * npcm7xx: Add ADC and PWM emulation
+ * elf2dmp: fix coverity issues
- * ui/cocoa: Make "open docs" help menu entry work again when binary
+ * elf2dmp: convert to g_malloc, g_new and g_free
-   is run from the build tree
+ * target/arm: Fix CNTPCT_EL0 trapping from EL0 when HCR_EL2.E2H is 0
- * ui/cocoa: Fix openFile: deprecation on Big Sur
+ * hw/arm: refactor virt PPI logic
- * docs: Add qemu-storage-daemon(1) manpage to meson.build
+ * arm/kvm: convert to kvm_set_one_reg, kvm_get_one_reg
- * docs: Build and install all the docs in a single manual
+ * target/arm: Permit T32 LDM with single register
  * smmuv3: Advertise SMMUv3.1-XNX
  * target/arm: Implement FEAT_HPMN0
  * Remove some unnecessary include lines
  * target/arm/arm-powerctl: Correctly init CPUs when powered on to lower EL
  * hw/timer/npcm7xx_timer: Prevent timer from counting down past zero
 ----------------------------------------------------------------
-Hao Wu (6):
+Chris Rauer (1):
-      hw/misc: Add clock converter in NPCM7XX CLK module
+      hw/timer/npcm7xx_timer: Prevent timer from counting down past zero
       hw/timer: Refactor NPCM7XX Timer to use CLK clock
       hw/adc: Add an ADC module for NPCM7XX
       hw/misc: Add a PWM module for NPCM7XX
       hw/misc: Add QTest for NPCM7XX PWM Module
       hw/*: Use type casting for SysBusDevice in NPCM7XX
-Leif Lindholm (6):
+Cornelia Huck (2):
-      target/arm: fix typo in cpu.h ID_AA64PFR1 field name
+      arm/kvm: convert to kvm_set_one_reg
-      target/arm: make ARMCPU.clidr 64-bit
+      arm/kvm: convert to kvm_get_one_reg
       target/arm: make ARMCPU.ctr 64-bit
       target/arm: add descriptions of CLIDR_EL1, CCSIDR_EL1, CTR_EL0 to cpu.h
       target/arm: add aarch64 ID register fields to cpu.h
       target/arm: add aarch32 ID register fields to cpu.h
-Peter Maydell (5):
+Leif Lindholm (3):
-      docs: Add qemu-storage-daemon(1) manpage to meson.build
+      {include/}hw/arm: refactor virt PPI logic
-      docs: Build and install all the docs in a single manual
+      include/hw/arm: move BSA definitions to bsa.h
-      target/arm: Don't decode insns in the XScale/iWMMXt space as cp insns
+      hw/arm/sbsa-ref: use bsa.h for PPI definitions
       hw/net/lan9118: Fix RX Status FIFO PEEK value
       hw/net/lan9118: Add symbolic constants for register offsets
-Roman Bolshakov (2):
+Michal Orzel (1):
-      ui/cocoa: Update path to docs in build tree
+      target/arm: Fix CNTPCT_EL0 trapping from EL0 when HCR_EL2.E2H is 0
       ui/cocoa: Fix openFile: deprecation on Big Sur
-Rémi Denis-Courmont (2):
+Peter Maydell (8):
-      target/arm: ARMv8.4-TTST extension
+      target/arm: Permit T32 LDM with single register
-      target/arm: enable Small Translation tables in max CPU
+      hw/arm/smmuv3: Update ID register bit field definitions
       hw/arm/smmuv3: Sort ID register setting into field order
       hw/arm/smmuv3: Advertise SMMUv3.1-XNX feature
       target/arm: Implement FEAT_HPMN0
       target/arm/kvm64.c: Remove unused include
       target/arm/common-semi-target.h: Remove unnecessary boot.h include
       target/arm/arm-powerctl: Correctly init CPUs when powered on to lower EL
- docs/conf.py                     |  46 ++-
+Philippe Mathieu-Daudé (1):
- docs/devel/conf.py               |  15 -
+      hw/arm/exynos4210: Get arm_boot_info declaration from 'hw/arm/boot.h'
  docs/index.html.in               |  17 -
  docs/interop/conf.py             |  28 --
  docs/meson.build                 |  65 ++--
  docs/specs/conf.py               |  16 -
  docs/system/arm/nuvoton.rst      |   4 +-
  docs/system/conf.py              |  28 --
  docs/tools/conf.py               |  37 --
  docs/user/conf.py                |  15 -
  meson.build                      |   1 +
  hw/adc/trace.h                   |   1 +
  include/hw/adc/npcm7xx_adc.h     |  69 ++++
  include/hw/arm/npcm7xx.h         |   4 +
  include/hw/misc/npcm7xx_clk.h    | 146 ++++++-
  include/hw/misc/npcm7xx_pwm.h    | 105 +++++
  include/hw/timer/npcm7xx_timer.h |   1 +
  target/arm/cpu.h                 |  85 ++++-
  hw/adc/npcm7xx_adc.c             | 301 +++++++++++++++
  hw/arm/npcm7xx.c                 |  55 ++-
  hw/arm/npcm7xx_boards.c          |   2 +-
  hw/mem/npcm7xx_mc.c              |   2 +-
  hw/misc/npcm7xx_clk.c            | 807 ++++++++++++++++++++++++++++++++++++++-
  hw/misc/npcm7xx_gcr.c            |   2 +-
  hw/misc/npcm7xx_pwm.c            | 550 ++++++++++++++++++++++++++
  hw/misc/npcm7xx_rng.c            |   2 +-
  hw/net/lan9118.c                 |  26 +-
  hw/nvram/npcm7xx_otp.c           |   2 +-
  hw/ssi/npcm7xx_fiu.c             |   2 +-
  hw/timer/npcm7xx_timer.c         |  39 +-
  target/arm/cpu64.c               |   1 +
  target/arm/helper.c              |  15 +-
  target/arm/translate.c           |   7 +
  tests/qtest/npcm7xx_adc-test.c   | 377 ++++++++++++++++++
  tests/qtest/npcm7xx_pwm-test.c   | 490 ++++++++++++++++++++++++
  hw/adc/meson.build               |   1 +
  hw/adc/trace-events              |   5 +
  hw/misc/meson.build              |   1 +
  hw/misc/trace-events             |   6 +
  tests/qtest/meson.build          |   4 +-
  ui/cocoa.m                       |   7 +-
 files changed, 3124 insertions(+), 263 deletions(-)
  delete mode 100644 docs/devel/conf.py
  delete mode 100644 docs/index.html.in
  delete mode 100644 docs/interop/conf.py
  delete mode 100644 docs/specs/conf.py
  delete mode 100644 docs/system/conf.py
  delete mode 100644 docs/tools/conf.py
  delete mode 100644 docs/user/conf.py
  create mode 100644 hw/adc/trace.h
  create mode 100644 include/hw/adc/npcm7xx_adc.h
  create mode 100644 include/hw/misc/npcm7xx_pwm.h
  create mode 100644 hw/adc/npcm7xx_adc.c
  create mode 100644 hw/misc/npcm7xx_pwm.c
  create mode 100644 tests/qtest/npcm7xx_adc-test.c
  create mode 100644 tests/qtest/npcm7xx_pwm-test.c
  create mode 100644 hw/adc/trace-events
+Suraj Shirvankar (1):
+      contrib/elf2dmp: Use g_malloc(), g_new() and g_free()
+Thomas Huth (1):
+      hw/arm: Move raspberrypi-fw-defs.h to the include/hw/arm/ folder
+Tong Ho (4):
+      xlnx-bbram: hw/nvram: Remove deprecated device reset
+      xlnx-zynqmp-efuse: hw/nvram: Remove deprecated device reset
+      xlnx-versal-efuse: hw/nvram: Remove deprecated device reset
+      xlnx-bbram: hw/nvram: Use dot in device type name
+Viktor Prutyanov (2):
+      elf2dmp: limit print length for sign_rsds
+      elf2dmp: check array bounds in pdb_get_file_size
+ MAINTAINERS                                    |   2 +-
+ docs/system/arm/emulation.rst                  |   1 +
+ hw/arm/smmuv3-internal.h                       |  38 ++++++++
+ include/hw/arm/bsa.h                           |  35 +++++++
+ include/hw/arm/exynos4210.h                    |   2 +-
+ include/hw/{misc => arm}/raspberrypi-fw-defs.h |   0
+ include/hw/arm/virt.h                          |  12 +--
+ include/hw/nvram/xlnx-bbram.h                  |   2 +-
+ target/arm/common-semi-target.h                |   4 +-
+ target/arm/cpu-qom.h                           |   2 -
+ target/arm/cpu.h                               |  22 +++++
+ contrib/elf2dmp/addrspace.c                    |   7 +-
+ contrib/elf2dmp/main.c                         |  11 +--
+ contrib/elf2dmp/pdb.c                          |  32 ++++---
+ contrib/elf2dmp/qemu_elf.c                     |   7 +-
+ hw/arm/boot.c                                  |  95 +++++--------------
+ hw/arm/sbsa-ref.c                              |  21 ++---
+ hw/arm/smmuv3.c                                |   8 +-
+ hw/arm/virt-acpi-build.c                       |  12 +--
+ hw/arm/virt.c                                  |  24 +++--
+ hw/misc/bcm2835_property.c                     |   2 +-
+ hw/nvram/xlnx-bbram.c                          |   8 +-
+ hw/nvram/xlnx-versal-efuse-ctrl.c              |   8 +-
+ hw/nvram/xlnx-zynqmp-efuse.c                   |   8 +-
+ hw/timer/npcm7xx_timer.c                       |   3 +
+ target/arm/arm-powerctl.c                      |  53 +----------
+ target/arm/cpu.c                               |  95 +++++++++++++++++++
+ target/arm/helper.c                            |  19 +---
+ target/arm/kvm.c                               |  28 ++----
+ target/arm/kvm64.c                             | 124 +++++++------------------
+ target/arm/tcg/cpu32.c                         |   4 +
+ target/arm/tcg/cpu64.c                         |   1 +
+ target/arm/tcg/translate.c                     |  37 +++++---
+files changed, 368 insertions(+), 359 deletions(-)
+ create mode 100644 include/hw/arm/bsa.h
+ rename include/hw/{misc => arm}/raspberrypi-fw-defs.h (100%)

-[PULL 13/21] hw/net/lan9118: Fix RX Status FIFO PEEK value
+[PULL 01/24] hw/arm: Move raspberrypi-fw-defs.h to the include/hw/arm/ folder
-A copy-and-paste error meant that the return value for register offset 0x44
+From: Thomas Huth <thuth@redhat.com>
 (the RX Status FIFO PEEK register) returned a byte from a bogus offset in
 the rx status FIFO. Fix the typo.
-Cc: qemu-stable@nongnu.org
+The file is obviously related to the raspberrypi machine, so
-Fixes: https://bugs.launchpad.net/qemu/+bug/1904954
+it should reside in hw/arm/ instead of hw/misc/. And while we're
 at it, also adjust the wildcard in MAINTAINERS so that it covers
 this file, too.
 Signed-off-by: Thomas Huth <thuth@redhat.com>
 Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
 Acked-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 Message-id: 20231012073458.860187-1-thuth@redhat.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
-Message-id: 20210108180401.2263-2-peter.maydell@linaro.org
 ---
- hw/net/lan9118.c | 2 +-
+ MAINTAINERS                                    | 2 +-
-file changed, 1 insertion(+), 1 deletion(-)
+ include/hw/{misc => arm}/raspberrypi-fw-defs.h | 0
  hw/misc/bcm2835_property.c                     | 2 +-
 files changed, 2 insertions(+), 2 deletions(-)
  rename include/hw/{misc => arm}/raspberrypi-fw-defs.h (100%)
-diff --git a/hw/net/lan9118.c b/hw/net/lan9118.c
+diff --git a/MAINTAINERS b/MAINTAINERS
 index XXXXXXX..XXXXXXX 100644
---- a/hw/net/lan9118.c
+--- a/MAINTAINERS
-+++ b/hw/net/lan9118.c
++++ b/MAINTAINERS
-@@ -XXX,XX +XXX,XX @@ static uint64_t lan9118_readl(void *opaque, hwaddr offset,
+@@ -XXX,XX +XXX,XX @@ S: Odd Fixes
-     case 0x40:
+ F: hw/arm/raspi.c
-         return rx_status_fifo_pop(s);
+ F: hw/arm/raspi_platform.h
-     case 0x44:
+ F: hw/*/bcm283*
--        return s->rx_status_fifo[s->tx_status_fifo_head];
+-F: include/hw/arm/raspi*
-+        return s->rx_status_fifo[s->rx_status_fifo_head];
++F: include/hw/arm/rasp*
-     case 0x48:
+ F: include/hw/*/bcm283*
-         return tx_status_fifo_pop(s);
+ F: docs/system/arm/raspi.rst
-     case 0x4c:
 diff --git a/include/hw/misc/raspberrypi-fw-defs.h b/include/hw/arm/raspberrypi-fw-defs.h
 similarity index 100%
 rename from include/hw/misc/raspberrypi-fw-defs.h
 rename to include/hw/arm/raspberrypi-fw-defs.h
 diff --git a/hw/misc/bcm2835_property.c b/hw/misc/bcm2835_property.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/misc/bcm2835_property.c
 +++ b/hw/misc/bcm2835_property.c
@@ -XXX,XX +XXX,XX @@
  #include "migration/vmstate.h"
  #include "hw/irq.h"
  #include "hw/misc/bcm2835_mbox_defs.h"
 -#include "hw/misc/raspberrypi-fw-defs.h"
 +#include "hw/arm/raspberrypi-fw-defs.h"
  #include "sysemu/dma.h"
  #include "qemu/log.h"
  #include "qemu/module.h"
 --
-.20.1
+.34.1

-[PULL 08/21] target/arm: add aarch32 ID register fields to cpu.h
+[PULL 02/24] hw/arm/exynos4210: Get arm_boot_info declaration from 'hw/arm/boot.h'
-From: Leif Lindholm <leif@nuviainc.com>
+From: Philippe Mathieu-Daudé <philmd@linaro.org>
-Add entries present in ARM DDI 0487F.c (August 2020).
+struct arm_boot_info is declared in "hw/arm/boot.h".
 By including the correct header we don't need to declare
 it again in "target/arm/cpu-qom.h".
-Signed-off-by: Leif Lindholm <leif@nuviainc.com>
+Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>
+Message-id: 20231013130214.95742-1-philmd@linaro.org
 Message-id: 20210108185154.8108-7-leif@nuviainc.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- target/arm/cpu.h | 28 ++++++++++++++++++++++++++++
+ include/hw/arm/exynos4210.h | 2 +-
-file changed, 28 insertions(+)
+ target/arm/cpu-qom.h        | 2 --
 files changed, 1 insertion(+), 3 deletions(-)
-diff --git a/target/arm/cpu.h b/target/arm/cpu.h
+diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpu.h
+--- a/include/hw/arm/exynos4210.h
-+++ b/target/arm/cpu.h
++++ b/include/hw/arm/exynos4210.h
-@@ -XXX,XX +XXX,XX @@ FIELD(ID_ISAR6, DP, 4, 4)
+@@ -XXX,XX +XXX,XX @@
- FIELD(ID_ISAR6, FHM, 8, 4)
+ #include "hw/intc/exynos4210_gic.h"
- FIELD(ID_ISAR6, SB, 12, 4)
+ #include "hw/intc/exynos4210_combiner.h"
- FIELD(ID_ISAR6, SPECRES, 16, 4)
+ #include "hw/core/split-irq.h"
-+FIELD(ID_ISAR6, BF16, 20, 4)
+-#include "target/arm/cpu-qom.h"
-+FIELD(ID_ISAR6, I8MM, 24, 4)
++#include "hw/arm/boot.h"
+ #include "qom/object.h"
- FIELD(ID_MMFR0, VMSA, 0, 4)
- FIELD(ID_MMFR0, PMSA, 4, 4)
+ #define EXYNOS4210_NCPUS                    2
-@@ -XXX,XX +XXX,XX @@ FIELD(ID_MMFR0, AUXREG, 20, 4)
+diff --git a/target/arm/cpu-qom.h b/target/arm/cpu-qom.h
- FIELD(ID_MMFR0, FCSE, 24, 4)
+index XXXXXXX..XXXXXXX 100644
- FIELD(ID_MMFR0, INNERSHR, 28, 4)
+--- a/target/arm/cpu-qom.h
++++ b/target/arm/cpu-qom.h
-+FIELD(ID_MMFR1, L1HVDVA, 0, 4)
+@@ -XXX,XX +XXX,XX @@
-+FIELD(ID_MMFR1, L1UNIVA, 4, 4)
+ #include "hw/core/cpu.h"
-+FIELD(ID_MMFR1, L1HVDSW, 8, 4)
+ #include "qom/object.h"
-+FIELD(ID_MMFR1, L1UNISW, 12, 4)
-+FIELD(ID_MMFR1, L1HVD, 16, 4)
+-struct arm_boot_info;
-+FIELD(ID_MMFR1, L1UNI, 20, 4)
+-
-+FIELD(ID_MMFR1, L1TSTCLN, 24, 4)
+ #define TYPE_ARM_CPU "arm-cpu"
-+FIELD(ID_MMFR1, BPRED, 28, 4)
-+
+ OBJECT_DECLARE_CPU_TYPE(ARMCPU, ARMCPUClass, ARM_CPU)
 +FIELD(ID_MMFR2, L1HVDFG, 0, 4)
 +FIELD(ID_MMFR2, L1HVDBG, 4, 4)
 +FIELD(ID_MMFR2, L1HVDRNG, 8, 4)
 +FIELD(ID_MMFR2, HVDTLB, 12, 4)
 +FIELD(ID_MMFR2, UNITLB, 16, 4)
 +FIELD(ID_MMFR2, MEMBARR, 20, 4)
 +FIELD(ID_MMFR2, WFISTALL, 24, 4)
 +FIELD(ID_MMFR2, HWACCFLG, 28, 4)
 +
  FIELD(ID_MMFR3, CMAINTVA, 0, 4)
  FIELD(ID_MMFR3, CMAINTSW, 4, 4)
  FIELD(ID_MMFR3, BPMAINT, 8, 4)
@@ -XXX,XX +XXX,XX @@ FIELD(ID_MMFR4, LSM, 20, 4)
  FIELD(ID_MMFR4, CCIDX, 24, 4)
  FIELD(ID_MMFR4, EVT, 28, 4)
 +FIELD(ID_MMFR5, ETS, 0, 4)
 +
  FIELD(ID_PFR0, STATE0, 0, 4)
  FIELD(ID_PFR0, STATE1, 4, 4)
  FIELD(ID_PFR0, STATE2, 8, 4)
@@ -XXX,XX +XXX,XX @@ FIELD(ID_PFR1, SEC_FRAC, 20, 4)
  FIELD(ID_PFR1, VIRT_FRAC, 24, 4)
  FIELD(ID_PFR1, GIC, 28, 4)
 +FIELD(ID_PFR2, CSV3, 0, 4)
 +FIELD(ID_PFR2, SSBS, 4, 4)
 +FIELD(ID_PFR2, RAS_FRAC, 8, 4)
 +
  FIELD(ID_AA64ISAR0, AES, 4, 4)
  FIELD(ID_AA64ISAR0, SHA1, 8, 4)
  FIELD(ID_AA64ISAR0, SHA2, 12, 4)
@@ -XXX,XX +XXX,XX @@ FIELD(ID_DFR0, MPROFDBG, 20, 4)
  FIELD(ID_DFR0, PERFMON, 24, 4)
  FIELD(ID_DFR0, TRACEFILT, 28, 4)
 +FIELD(ID_DFR1, MTPMU, 0, 4)
 +
  FIELD(DBGDIDR, SE_IMP, 12, 1)
  FIELD(DBGDIDR, NSUHD_IMP, 14, 1)
  FIELD(DBGDIDR, VERSION, 16, 4)
 --
-.20.1
+.34.1

-[PULL 07/21] target/arm: add aarch64 ID register fields to cpu.h
+[PULL 03/24] xlnx-bbram: hw/nvram: Remove deprecated device reset
-From: Leif Lindholm <leif@nuviainc.com>
+From: Tong Ho <tong.ho@amd.com>
-Add entries present in ARM DDI 0487F.c (August 2020).
+This change implements the ResettableClass interface for the device.
-Signed-off-by: Leif Lindholm <leif@nuviainc.com>
+Signed-off-by: Tong Ho <tong.ho@amd.com>
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
-Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>
+Message-id: 20231003052345.199725-1-tong.ho@amd.com
 Message-id: 20210108185154.8108-6-leif@nuviainc.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- target/arm/cpu.h | 15 +++++++++++++++
+ hw/nvram/xlnx-bbram.c | 8 +++++---
-file changed, 15 insertions(+)
+file changed, 5 insertions(+), 3 deletions(-)
-diff --git a/target/arm/cpu.h b/target/arm/cpu.h
+diff --git a/hw/nvram/xlnx-bbram.c b/hw/nvram/xlnx-bbram.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpu.h
+--- a/hw/nvram/xlnx-bbram.c
-+++ b/target/arm/cpu.h
++++ b/hw/nvram/xlnx-bbram.c
-@@ -XXX,XX +XXX,XX @@ FIELD(ID_AA64ISAR1, GPI, 28, 4)
+@@ -XXX,XX +XXX,XX @@
- FIELD(ID_AA64ISAR1, FRINTTS, 32, 4)
+  * QEMU model of the Xilinx BBRAM Battery Backed RAM
- FIELD(ID_AA64ISAR1, SB, 36, 4)
+  *
- FIELD(ID_AA64ISAR1, SPECRES, 40, 4)
+  * Copyright (c) 2014-2021 Xilinx Inc.
-+FIELD(ID_AA64ISAR1, BF16, 44, 4)
++ * Copyright (c) 2023 Advanced Micro Devices, Inc.
-+FIELD(ID_AA64ISAR1, DGH, 48, 4)
+  *
-+FIELD(ID_AA64ISAR1, I8MM, 52, 4)
+  * Permission is hereby granted, free of charge, to any person obtaining a copy
+  * of this software and associated documentation files (the "Software"), to deal
- FIELD(ID_AA64PFR0, EL0, 0, 4)
+@@ -XXX,XX +XXX,XX @@ static RegisterAccessInfo bbram_ctrl_regs_info[] = {
- FIELD(ID_AA64PFR0, EL1, 4, 4)
+     }
-@@ -XXX,XX +XXX,XX @@ FIELD(ID_AA64PFR0, ADVSIMD, 20, 4)
+ };
- FIELD(ID_AA64PFR0, GIC, 24, 4)
- FIELD(ID_AA64PFR0, RAS, 28, 4)
+-static void bbram_ctrl_reset(DeviceState *dev)
- FIELD(ID_AA64PFR0, SVE, 32, 4)
++static void bbram_ctrl_reset_hold(Object *obj)
-+FIELD(ID_AA64PFR0, SEL2, 36, 4)
+ {
-+FIELD(ID_AA64PFR0, MPAM, 40, 4)
+-    XlnxBBRam *s = XLNX_BBRAM(dev);
-+FIELD(ID_AA64PFR0, AMU, 44, 4)
++    XlnxBBRam *s = XLNX_BBRAM(obj);
-+FIELD(ID_AA64PFR0, DIT, 48, 4)
+     unsigned int i;
-+FIELD(ID_AA64PFR0, CSV2, 56, 4)
-+FIELD(ID_AA64PFR0, CSV3, 60, 4)
+     for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) {
+@@ -XXX,XX +XXX,XX @@ static Property bbram_ctrl_props[] = {
- FIELD(ID_AA64PFR1, BT, 0, 4)
+ static void bbram_ctrl_class_init(ObjectClass *klass, void *data)
- FIELD(ID_AA64PFR1, SSBS, 4, 4)
+ {
- FIELD(ID_AA64PFR1, MTE, 8, 4)
+     DeviceClass *dc = DEVICE_CLASS(klass);
- FIELD(ID_AA64PFR1, RAS_FRAC, 12, 4)
++    ResettableClass *rc = RESETTABLE_CLASS(klass);
-+FIELD(ID_AA64PFR1, MPAM_FRAC, 16, 4)
+-    dc->reset = bbram_ctrl_reset;
- FIELD(ID_AA64MMFR0, PARANGE, 0, 4)
++    rc->phases.hold = bbram_ctrl_reset_hold;
- FIELD(ID_AA64MMFR0, ASIDBITS, 4, 4)
+     dc->realize = bbram_ctrl_realize;
-@@ -XXX,XX +XXX,XX @@ FIELD(ID_AA64MMFR0, TGRAN16_2, 32, 4)
+     dc->vmsd = &vmstate_bbram_ctrl;
- FIELD(ID_AA64MMFR0, TGRAN64_2, 36, 4)
+     device_class_set_props(dc, bbram_ctrl_props);
  FIELD(ID_AA64MMFR0, TGRAN4_2, 40, 4)
  FIELD(ID_AA64MMFR0, EXS, 44, 4)
 +FIELD(ID_AA64MMFR0, FGT, 56, 4)
 +FIELD(ID_AA64MMFR0, ECV, 60, 4)
  FIELD(ID_AA64MMFR1, HAFDBS, 0, 4)
  FIELD(ID_AA64MMFR1, VMIDBITS, 4, 4)
@@ -XXX,XX +XXX,XX @@ FIELD(ID_AA64MMFR1, LO, 16, 4)
  FIELD(ID_AA64MMFR1, PAN, 20, 4)
  FIELD(ID_AA64MMFR1, SPECSEI, 24, 4)
  FIELD(ID_AA64MMFR1, XNX, 28, 4)
 +FIELD(ID_AA64MMFR1, TWED, 32, 4)
 +FIELD(ID_AA64MMFR1, ETS, 36, 4)
  FIELD(ID_AA64MMFR2, CNP, 0, 4)
  FIELD(ID_AA64MMFR2, UAO, 4, 4)
@@ -XXX,XX +XXX,XX @@ FIELD(ID_AA64DFR0, CTX_CMPS, 28, 4)
  FIELD(ID_AA64DFR0, PMSVER, 32, 4)
  FIELD(ID_AA64DFR0, DOUBLELOCK, 36, 4)
  FIELD(ID_AA64DFR0, TRACEFILT, 40, 4)
 +FIELD(ID_AA64DFR0, MTPMU, 48, 4)
  FIELD(ID_DFR0, COPDBG, 0, 4)
  FIELD(ID_DFR0, COPSDBG, 4, 4)
 --
-.20.1
+.34.1

-New patch
+[PULL 04/24] xlnx-zynqmp-efuse: hw/nvram: Remove deprecated device reset
+From: Tong Ho <tong.ho@amd.com>
+This change implements the ResettableClass interface for the device.
+Signed-off-by: Tong Ho <tong.ho@amd.com>
+Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
+Message-id: 20231004055713.324009-1-tong.ho@amd.com
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ hw/nvram/xlnx-zynqmp-efuse.c | 8 +++++---
+file changed, 5 insertions(+), 3 deletions(-)
+diff --git a/hw/nvram/xlnx-zynqmp-efuse.c b/hw/nvram/xlnx-zynqmp-efuse.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/nvram/xlnx-zynqmp-efuse.c
++++ b/hw/nvram/xlnx-zynqmp-efuse.c
+@@ -XXX,XX +XXX,XX @@
+  * QEMU model of the ZynqMP eFuse
+  *
+  * Copyright (c) 2015 Xilinx Inc.
++ * Copyright (c) 2023 Advanced Micro Devices, Inc.
+  *
+  * Written by Edgar E. Iglesias <edgari@xilinx.com>
+  *
+@@ -XXX,XX +XXX,XX @@ static void zynqmp_efuse_register_reset(RegisterInfo *reg)
+     register_reset(reg);
+ }
+-static void zynqmp_efuse_reset(DeviceState *dev)
++static void zynqmp_efuse_reset_hold(Object *obj)
+ {
+-    XlnxZynqMPEFuse *s = XLNX_ZYNQMP_EFUSE(dev);
++    XlnxZynqMPEFuse *s = XLNX_ZYNQMP_EFUSE(obj);
+     unsigned int i;
+     for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) {
+@@ -XXX,XX +XXX,XX @@ static Property zynqmp_efuse_props[] = {
+ static void zynqmp_efuse_class_init(ObjectClass *klass, void *data)
+ {
+     DeviceClass *dc = DEVICE_CLASS(klass);
++    ResettableClass *rc = RESETTABLE_CLASS(klass);
+-    dc->reset = zynqmp_efuse_reset;
++    rc->phases.hold = zynqmp_efuse_reset_hold;
+     dc->realize = zynqmp_efuse_realize;
+     dc->vmsd = &vmstate_efuse;
+     device_class_set_props(dc, zynqmp_efuse_props);
+--
+.34.1

-[PULL 06/21] target/arm: add descriptions of CLIDR_EL1, CCSIDR_EL1, CTR_EL0 to cpu.h
+[PULL 05/24] xlnx-versal-efuse: hw/nvram: Remove deprecated device reset
-From: Leif Lindholm <leif@nuviainc.com>
+From: Tong Ho <tong.ho@amd.com>
-Signed-off-by: Leif Lindholm <leif@nuviainc.com>
+This change implements the ResettableClass interface for the device.
-Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>
-Message-id: 20210108185154.8108-5-leif@nuviainc.com
+Signed-off-by: Tong Ho <tong.ho@amd.com>
 Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
 Message-id: 20231004055339.323833-1-tong.ho@amd.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- target/arm/cpu.h | 31 +++++++++++++++++++++++++++++++
+ hw/nvram/xlnx-versal-efuse-ctrl.c | 8 +++++---
-file changed, 31 insertions(+)
+file changed, 5 insertions(+), 3 deletions(-)
-diff --git a/target/arm/cpu.h b/target/arm/cpu.h
+diff --git a/hw/nvram/xlnx-versal-efuse-ctrl.c b/hw/nvram/xlnx-versal-efuse-ctrl.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpu.h
+--- a/hw/nvram/xlnx-versal-efuse-ctrl.c
-+++ b/target/arm/cpu.h
++++ b/hw/nvram/xlnx-versal-efuse-ctrl.c
-@@ -XXX,XX +XXX,XX @@ FIELD(V7M_FPCCR, ASPEN, 31, 1)
+@@ -XXX,XX +XXX,XX @@
- /*
+  * QEMU model of the Versal eFuse controller
-  * System register ID fields.
+  *
-  */
+  * Copyright (c) 2020 Xilinx Inc.
-+FIELD(CLIDR_EL1, CTYPE1, 0, 3)
++ * Copyright (c) 2023 Advanced Micro Devices, Inc.
-+FIELD(CLIDR_EL1, CTYPE2, 3, 3)
+  *
-+FIELD(CLIDR_EL1, CTYPE3, 6, 3)
+  * Permission is hereby granted, free of charge, to any person obtaining a copy
-+FIELD(CLIDR_EL1, CTYPE4, 9, 3)
+  * of this software and associated documentation files (the "Software"), to deal
-+FIELD(CLIDR_EL1, CTYPE5, 12, 3)
+@@ -XXX,XX +XXX,XX @@ static void efuse_ctrl_register_reset(RegisterInfo *reg)
-+FIELD(CLIDR_EL1, CTYPE6, 15, 3)
+     register_reset(reg);
-+FIELD(CLIDR_EL1, CTYPE7, 18, 3)
+ }
-+FIELD(CLIDR_EL1, LOUIS, 21, 3)
-+FIELD(CLIDR_EL1, LOC, 24, 3)
+-static void efuse_ctrl_reset(DeviceState *dev)
-+FIELD(CLIDR_EL1, LOUU, 27, 3)
++static void efuse_ctrl_reset_hold(Object *obj)
-+FIELD(CLIDR_EL1, ICB, 30, 3)
+ {
-+
+-    XlnxVersalEFuseCtrl *s = XLNX_VERSAL_EFUSE_CTRL(dev);
-+/* When FEAT_CCIDX is implemented */
++    XlnxVersalEFuseCtrl *s = XLNX_VERSAL_EFUSE_CTRL(obj);
-+FIELD(CCSIDR_EL1, CCIDX_LINESIZE, 0, 3)
+     unsigned int i;
-+FIELD(CCSIDR_EL1, CCIDX_ASSOCIATIVITY, 3, 21)
-+FIELD(CCSIDR_EL1, CCIDX_NUMSETS, 32, 24)
+     for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) {
-+
+@@ -XXX,XX +XXX,XX @@ static Property efuse_ctrl_props[] = {
-+/* When FEAT_CCIDX is not implemented */
+ static void efuse_ctrl_class_init(ObjectClass *klass, void *data)
-+FIELD(CCSIDR_EL1, LINESIZE, 0, 3)
+ {
-+FIELD(CCSIDR_EL1, ASSOCIATIVITY, 3, 10)
+     DeviceClass *dc = DEVICE_CLASS(klass);
-+FIELD(CCSIDR_EL1, NUMSETS, 13, 15)
++    ResettableClass *rc = RESETTABLE_CLASS(klass);
-+
-+FIELD(CTR_EL0,  IMINLINE, 0, 4)
+-    dc->reset = efuse_ctrl_reset;
-+FIELD(CTR_EL0,  L1IP, 14, 2)
++    rc->phases.hold = efuse_ctrl_reset_hold;
-+FIELD(CTR_EL0,  DMINLINE, 16, 4)
+     dc->realize = efuse_ctrl_realize;
-+FIELD(CTR_EL0,  ERG, 20, 4)
+     dc->vmsd = &vmstate_efuse_ctrl;
-+FIELD(CTR_EL0,  CWG, 24, 4)
+     device_class_set_props(dc, efuse_ctrl_props);
 +FIELD(CTR_EL0,  IDC, 28, 1)
 +FIELD(CTR_EL0,  DIC, 29, 1)
 +FIELD(CTR_EL0,  TMINLINE, 32, 6)
 +
  FIELD(MIDR_EL1, REVISION, 0, 4)
  FIELD(MIDR_EL1, PARTNUM, 4, 12)
  FIELD(MIDR_EL1, ARCHITECTURE, 16, 4)
 --
-.20.1
+.34.1

-[PULL 05/21] target/arm: make ARMCPU.ctr 64-bit
+[PULL 06/24] xlnx-bbram: hw/nvram: Use dot in device type name
-From: Leif Lindholm <leif@nuviainc.com>
+From: Tong Ho <tong.ho@amd.com>
-When FEAT_MTE is implemented, the AArch64 view of CTR_EL0 adds the
+This replaces the comma (,) to dot (.) in the device type name
-TminLine field in bits [37:32].
+so the name can be used with the 'driver=' command line option.
 Extend the ctr field to be able to hold this context.
-Signed-off-by: Leif Lindholm <leif@nuviainc.com>
+Signed-off-by: Tong Ho <tong.ho@amd.com>
-Reviewed-by: Hao Wu <wuhaotsh@google.com>
+Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20231003052139.199665-1-tong.ho@amd.com
 Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>
 Message-id: 20210108185154.8108-4-leif@nuviainc.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- target/arm/cpu.h | 2 +-
+ include/hw/nvram/xlnx-bbram.h | 2 +-
 file changed, 1 insertion(+), 1 deletion(-)
-diff --git a/target/arm/cpu.h b/target/arm/cpu.h
+diff --git a/include/hw/nvram/xlnx-bbram.h b/include/hw/nvram/xlnx-bbram.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpu.h
+--- a/include/hw/nvram/xlnx-bbram.h
-+++ b/target/arm/cpu.h
++++ b/include/hw/nvram/xlnx-bbram.h
-@@ -XXX,XX +XXX,XX @@ struct ARMCPU {
+@@ -XXX,XX +XXX,XX @@
-     uint64_t midr;
-     uint32_t revidr;
+ #define RMAX_XLNX_BBRAM ((0x4c / 4) + 1)
-     uint32_t reset_fpsid;
--    uint32_t ctr;
+-#define TYPE_XLNX_BBRAM "xlnx,bbram-ctrl"
-+    uint64_t ctr;
++#define TYPE_XLNX_BBRAM "xlnx.bbram-ctrl"
-     uint32_t reset_sctlr;
+ OBJECT_DECLARE_SIMPLE_TYPE(XlnxBBRam, XLNX_BBRAM);
-     uint64_t pmceid0;
-     uint64_t pmceid1;
+ struct XlnxBBRam {
 --
-.20.1
+.34.1

-[PULL 04/21] target/arm: make ARMCPU.clidr 64-bit
+[PULL 07/24] elf2dmp: limit print length for sign_rsds
-From: Leif Lindholm <leif@nuviainc.com>
+From: Viktor Prutyanov <viktor@daynix.com>
-The AArch64 view of CLIDR_EL1 extends the ICB field to include also bit
+String sign_rsds isn't terminated, so the print length must be limited.
 , as well as adding a Ttype<n> field when FEAT_MTE is implemented.
 Extend the clidr field to be able to hold this context.
-Signed-off-by: Leif Lindholm <leif@nuviainc.com>
+Fixes: Coverity CID 1521598
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+Signed-off-by: Viktor Prutyanov <viktor@daynix.com>
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Akihiko Odaki <akihiko.odaki@daynix.com>
-Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>
+Message-id: 20230930235317.11469-2-viktor@daynix.com
 Message-id: 20210108185154.8108-3-leif@nuviainc.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- target/arm/cpu.h | 2 +-
+ contrib/elf2dmp/main.c | 2 +-
 file changed, 1 insertion(+), 1 deletion(-)
-diff --git a/target/arm/cpu.h b/target/arm/cpu.h
+diff --git a/contrib/elf2dmp/main.c b/contrib/elf2dmp/main.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpu.h
+--- a/contrib/elf2dmp/main.c
-+++ b/target/arm/cpu.h
++++ b/contrib/elf2dmp/main.c
-@@ -XXX,XX +XXX,XX @@ struct ARMCPU {
+@@ -XXX,XX +XXX,XX @@ static bool pe_check_pdb_name(uint64_t base, void *start_addr,
-     uint32_t id_afr0;
+     }
-     uint64_t id_aa64afr0;
-     uint64_t id_aa64afr1;
+     if (memcmp(&rsds->Signature, sign_rsds, sizeof(sign_rsds))) {
--    uint32_t clidr;
+-        eprintf("CodeView signature is \'%.4s\', \'%s\' expected\n",
-+    uint64_t clidr;
++        eprintf("CodeView signature is \'%.4s\', \'%.4s\' expected\n",
-     uint64_t mp_affinity; /* MP ID without feature bits */
+                 rsds->Signature, sign_rsds);
-     /* The elements of this array are the CCSIDR values for each cache,
+         return false;
-      * in the order L1DCache, L1ICache, L2DCache, L2ICache, etc.
+     }
 --
-.20.1
+.34.1

-[PULL 03/21] target/arm: fix typo in cpu.h ID_AA64PFR1 field name
+[PULL 08/24] elf2dmp: check array bounds in pdb_get_file_size
-From: Leif Lindholm <leif@nuviainc.com>
+From: Viktor Prutyanov <viktor@daynix.com>
-SBSS -> SSBS
+Index in file_size array must be checked against num_files, because the
 entries we are looking for may be absent in the PDB.
-Signed-off-by: Leif Lindholm <leif@nuviainc.com>
+Fixes: Coverity CID 1521597
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+Signed-off-by: Viktor Prutyanov <viktor@daynix.com>
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Akihiko Odaki <akihiko.odaki@daynix.com>
-Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
-Message-id: 20210108185154.8108-2-leif@nuviainc.com
+Message-id: 20230930235317.11469-3-viktor@daynix.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- target/arm/cpu.h | 2 +-
+ contrib/elf2dmp/pdb.c | 13 +++++++++----
-file changed, 1 insertion(+), 1 deletion(-)
+file changed, 9 insertions(+), 4 deletions(-)
-diff --git a/target/arm/cpu.h b/target/arm/cpu.h
+diff --git a/contrib/elf2dmp/pdb.c b/contrib/elf2dmp/pdb.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpu.h
+--- a/contrib/elf2dmp/pdb.c
-+++ b/target/arm/cpu.h
++++ b/contrib/elf2dmp/pdb.c
-@@ -XXX,XX +XXX,XX @@ FIELD(ID_AA64PFR0, RAS, 28, 4)
+@@ -XXX,XX +XXX,XX @@
- FIELD(ID_AA64PFR0, SVE, 32, 4)
+ static uint32_t pdb_get_file_size(const struct pdb_reader *r, unsigned idx)
- FIELD(ID_AA64PFR1, BT, 0, 4)
+ {
--FIELD(ID_AA64PFR1, SBSS, 4, 4)
++    if (idx >= r->ds.toc->num_files) {
-+FIELD(ID_AA64PFR1, SSBS, 4, 4)
++        return 0;
- FIELD(ID_AA64PFR1, MTE, 8, 4)
++    }
- FIELD(ID_AA64PFR1, RAS_FRAC, 12, 4)
++
+     return r->ds.toc->file_size[idx];
  }
@@ -XXX,XX +XXX,XX @@ static void *pdb_ds_read_file(struct pdb_reader* r, uint32_t file_number)
  static int pdb_init_segments(struct pdb_reader *r)
  {
 -    char *segs;
      unsigned stream_idx = r->segments;
 -    segs = pdb_ds_read_file(r, stream_idx);
 -    if (!segs) {
 +    r->segs = pdb_ds_read_file(r, stream_idx);
 +    if (!r->segs) {
          return 1;
      }
 -    r->segs = segs;
      r->segs_size = pdb_get_file_size(r, stream_idx);
 +    if (!r->segs_size) {
 +        return 1;
 +    }
      return 0;
  }
 --
-.20.1
+.34.1

-[PULL 01/21] target/arm: ARMv8.4-TTST extension
+[PULL 09/24] target/arm: Fix CNTPCT_EL0 trapping from EL0 when HCR_EL2.E2H is 0
-From: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
+From: Michal Orzel <michal.orzel@amd.com>
-This adds for the Small Translation tables extension in AArch64 state.
+On an attempt to access CNTPCT_EL0 from EL0 using a guest running on top
 of Xen, a trap from EL2 was observed which is something not reproducible
 on HW (also, Xen does not trap accesses to physical counter).
-Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
+This is because gt_counter_access() checks for an incorrect bit (1
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+instead of 0) of CNTHCTL_EL2 if HCR_EL2.E2H is 0 and access is made to
 physical counter. Refer ARM ARM DDI 0487J.a, D19.12.2:
 When HCR_EL2.E2H is 0:
  - EL1PCTEN, bit [0]: refers to physical counter
  - EL1PCEN, bit [1]: refers to physical timer registers
 Drop entire block "if (hcr & HCR_E2H) {...} else {...}" from EL0 case
 and fall through to EL1 case, given that after fixing checking for the
 correct bit, the handling is the same.
 Fixes: 5bc8437136fb ("target/arm: Update timer access for VHE")
 Signed-off-by: Michal Orzel <michal.orzel@amd.com>
 Tested-by: Oleksandr Tyshchenko <oleksandr_tyshchenko@epam.com>
 Message-id: 20230928094404.20802-1-michal.orzel@amd.com
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- target/arm/cpu.h    |  5 +++++
+ target/arm/helper.c | 17 +----------------
- target/arm/helper.c | 15 +++++++++++++--
+file changed, 1 insertion(+), 16 deletions(-)
 files changed, 18 insertions(+), 2 deletions(-)
-diff --git a/target/arm/cpu.h b/target/arm/cpu.h
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpu.h
-+++ b/target/arm/cpu.h
-@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_uao(const ARMISARegisters *id)
-     return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, UAO) != 0;
- }
-+static inline bool isar_feature_aa64_st(const ARMISARegisters *id)
-+{
-+    return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, ST) != 0;
-+}
-+
- static inline bool isar_feature_aa64_bti(const ARMISARegisters *id)
- {
-     return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) != 0;
 diff --git a/target/arm/helper.c b/target/arm/helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/helper.c
 +++ b/target/arm/helper.c
-@@ -XXX,XX +XXX,XX @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
+@@ -XXX,XX +XXX,XX @@ static CPAccessResult gt_counter_access(CPUARMState *env, int timeridx,
- {
+         if (!extract32(env->cp15.c14_cntkctl, timeridx, 1)) {
-     uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr;
+             return CP_ACCESS_TRAP;
      bool epd, hpd, using16k, using64k;
 -    int select, tsz, tbi;
 +    int select, tsz, tbi, max_tsz;
      if (!regime_has_2_ranges(mmu_idx)) {
          select = 0;
@@ -XXX,XX +XXX,XX @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
              hpd = extract64(tcr, 42, 1);
          }
-     }
+-
--    tsz = MIN(tsz, 39);  /* TODO: ARMv8.4-TTST */
+-        /* If HCR_EL2.<E2H,TGE> == '10': check CNTHCTL_EL2.EL1PCTEN. */
-+
+-        if (hcr & HCR_E2H) {
-+    if (cpu_isar_feature(aa64_st, env_archcpu(env))) {
+-            if (timeridx == GTIMER_PHYS &&
-+        max_tsz = 48 - using64k;
+-                !extract32(env->cp15.cnthctl_el2, 10, 1)) {
-+    } else {
+-                return CP_ACCESS_TRAP_EL2;
-+        max_tsz = 39;
+-            }
-+    }
+-        } else {
-+
+-            /* If HCR_EL2.<E2H> == 0: check CNTHCTL_EL2.EL1PCEN. */
-+    tsz = MIN(tsz, max_tsz);
+-            if (has_el2 && timeridx == GTIMER_PHYS &&
-     tsz = MAX(tsz, 16);  /* TODO: ARMv8.2-LVA  */
+-                !extract32(env->cp15.cnthctl_el2, 1, 1)) {
+-                return CP_ACCESS_TRAP_EL2;
-     /* Present TBI as a composite with TBID.  */
+-            }
-@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address,
+-        }
-         if (!aarch64 || stride == 9) {
+-        break;
-             /* AArch32 or 4KB pages */
+-
-             startlevel = 2 - sl0;
++        /* fall through */
-+
+     case 1:
-+            if (cpu_isar_feature(aa64_st, cpu)) {
+         /* Check CNTHCTL_EL2.EL1PCTEN, which changes location based on E2H. */
-+                startlevel &= 3;
+         if (has_el2 && timeridx == GTIMER_PHYS &&
 +            }
          } else {
              /* 16KB or 64KB pages */
              startlevel = 3 - sl0;
 --
-.20.1
+.34.1

-[PULL 18/21] hw/misc: Add a PWM module for NPCM7XX
+[PULL 10/24] {include/}hw/arm: refactor virt PPI logic
-From: Hao Wu <wuhaotsh@google.com>
+From: Leif Lindholm <quic_llindhol@quicinc.com>
-The PWM module is part of NPCM7XX module. Each NPCM7XX module has two
+GIC Private Peripheral Interrupts (PPI) are defined as GIC INTID 16-31.
-identical PWM modules. Each module contains 4 PWM entries. Each PWM has
+As in, PPI0 is INTID16 .. PPI15 is INTID31.
-two outputs: frequency and duty_cycle. Both are computed using inputs
+Arm's Base System Architecture specification (BSA) lists the mandated and
-from software side.
+recommended private interrupt IDs by INTID, not by PPI index. But current
 definitions in virt define them by PPI index, complicating cross
 referencing.
-This module does not model detail pulse signals since it is expensive.
+Meanwhile, the PPI(x) macro counterintuitively adds 16 to the input value,
-It also does not model interrupts and watchdogs that are dependant on
+converting a PPI index to an INTID.
 the detail models. The interfaces for these are left in the module so
 that anyone in need for these functionalities can implement on their
 own.
-The user can read the duty cycle and frequency using qom-get command.
+Resolve this by redefining the BSA-allocated PPIs by their INTIDs,
 and replacing the PPI(x) macro with an INTID_TO_PPI(x) one where required.
-Reviewed-by: Havard Skinnemoen <hskinnemoen@google.com>
+Signed-off-by: Leif Lindholm <quic_llindhol@quicinc.com>
-Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
+Message-id: 20230919090229.188092-2-quic_llindhol@quicinc.com
 Signed-off-by: Hao Wu <wuhaotsh@google.com>
 Message-id: 20210108190945.949196-5-wuhaotsh@google.com
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- docs/system/arm/nuvoton.rst   |   2 +-
+ include/hw/arm/virt.h    | 14 +++++++-------
- include/hw/arm/npcm7xx.h      |   2 +
+ hw/arm/virt-acpi-build.c | 12 ++++++------
- include/hw/misc/npcm7xx_pwm.h | 105 +++++++
+ hw/arm/virt.c            | 24 ++++++++++++++----------
- hw/arm/npcm7xx.c              |  26 +-
+files changed, 27 insertions(+), 23 deletions(-)
  hw/misc/npcm7xx_pwm.c         | 550 ++++++++++++++++++++++++++++++++++
  hw/misc/meson.build           |   1 +
  hw/misc/trace-events          |   6 +
 files changed, 689 insertions(+), 3 deletions(-)
  create mode 100644 include/hw/misc/npcm7xx_pwm.h
  create mode 100644 hw/misc/npcm7xx_pwm.c
-diff --git a/docs/system/arm/nuvoton.rst b/docs/system/arm/nuvoton.rst
+diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
 index XXXXXXX..XXXXXXX 100644
---- a/docs/system/arm/nuvoton.rst
+--- a/include/hw/arm/virt.h
-+++ b/docs/system/arm/nuvoton.rst
++++ b/include/hw/arm/virt.h
-@@ -XXX,XX +XXX,XX @@ Supported devices
+@@ -XXX,XX +XXX,XX @@
-  * USB host (USBH)
+ #define NUM_VIRTIO_TRANSPORTS 32
-  * GPIO controller
+ #define NUM_SMMU_IRQS          4
-  * Analog to Digital Converter (ADC)
-+ * Pulse Width Modulation (PWM)
+-#define ARCH_GIC_MAINT_IRQ  9
++#define ARCH_GIC_MAINT_IRQ  25
- Missing devices
- ---------------
+-#define ARCH_TIMER_VIRT_IRQ   11
-@@ -XXX,XX +XXX,XX @@ Missing devices
+-#define ARCH_TIMER_S_EL1_IRQ  13
-  * Peripheral SPI controller (PSPI)
+-#define ARCH_TIMER_NS_EL1_IRQ 14
-  * SD/MMC host
+-#define ARCH_TIMER_NS_EL2_IRQ 10
-  * PECI interface
++#define ARCH_TIMER_VIRT_IRQ   27
-- * Pulse Width Modulation (PWM)
++#define ARCH_TIMER_S_EL1_IRQ  29
-  * Tachometer
++#define ARCH_TIMER_NS_EL1_IRQ 30
-  * PCI and PCIe root complex and bridges
++#define ARCH_TIMER_NS_EL2_IRQ 26
-  * VDM and MCTP support
-diff --git a/include/hw/arm/npcm7xx.h b/include/hw/arm/npcm7xx.h
+-#define VIRTUAL_PMU_IRQ 7
 +#define VIRTUAL_PMU_IRQ 23
 -#define PPI(irq) ((irq) + 16)
 +#define INTID_TO_PPI(irq) ((irq) - 16)
  /* See Linux kernel arch/arm64/include/asm/pvclock-abi.h */
  #define PVTIME_SIZE_PER_CPU 64
 diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/arm/npcm7xx.h
+--- a/hw/arm/virt-acpi-build.c
-+++ b/include/hw/arm/npcm7xx.h
++++ b/hw/arm/virt-acpi-build.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ build_gtdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
- #include "hw/mem/npcm7xx_mc.h"
+      * The interrupt values are the same with the device tree when adding 16
- #include "hw/misc/npcm7xx_clk.h"
+      */
- #include "hw/misc/npcm7xx_gcr.h"
+     /* Secure EL1 timer GSIV */
-+#include "hw/misc/npcm7xx_pwm.h"
+-    build_append_int_noprefix(table_data, ARCH_TIMER_S_EL1_IRQ + 16, 4);
- #include "hw/misc/npcm7xx_rng.h"
++    build_append_int_noprefix(table_data, ARCH_TIMER_S_EL1_IRQ, 4);
- #include "hw/nvram/npcm7xx_otp.h"
+     /* Secure EL1 timer Flags */
- #include "hw/timer/npcm7xx_timer.h"
+     build_append_int_noprefix(table_data, irqflags, 4);
-@@ -XXX,XX +XXX,XX @@ typedef struct NPCM7xxState {
+     /* Non-Secure EL1 timer GSIV */
-     NPCM7xxCLKState     clk;
+-    build_append_int_noprefix(table_data, ARCH_TIMER_NS_EL1_IRQ + 16, 4);
-     NPCM7xxTimerCtrlState tim[3];
++    build_append_int_noprefix(table_data, ARCH_TIMER_NS_EL1_IRQ, 4);
-     NPCM7xxADCState     adc;
+     /* Non-Secure EL1 timer Flags */
-+    NPCM7xxPWMState     pwm[2];
+     build_append_int_noprefix(table_data, irqflags |
-     NPCM7xxOTPState     key_storage;
+UL << 2, /* Always-on Capability */
-     NPCM7xxOTPState     fuse_array;
+);
-     NPCM7xxMCState      mc;
+     /* Virtual timer GSIV */
-diff --git a/include/hw/misc/npcm7xx_pwm.h b/include/hw/misc/npcm7xx_pwm.h
+-    build_append_int_noprefix(table_data, ARCH_TIMER_VIRT_IRQ + 16, 4);
-new file mode 100644
++    build_append_int_noprefix(table_data, ARCH_TIMER_VIRT_IRQ, 4);
-index XXXXXXX..XXXXXXX
+     /* Virtual Timer Flags */
---- /dev/null
+     build_append_int_noprefix(table_data, irqflags, 4);
-+++ b/include/hw/misc/npcm7xx_pwm.h
+     /* Non-Secure EL2 timer GSIV */
-@@ -XXX,XX +XXX,XX @@
+-    build_append_int_noprefix(table_data, ARCH_TIMER_NS_EL2_IRQ + 16, 4);
-+/*
++    build_append_int_noprefix(table_data, ARCH_TIMER_NS_EL2_IRQ, 4);
-+ * Nuvoton NPCM7xx PWM Module
+     /* Non-Secure EL2 timer Flags */
-+ *
+     build_append_int_noprefix(table_data, irqflags, 4);
-+ * Copyright 2020 Google LLC
+     /* CntReadBase Physical address */
-+ *
+@@ -XXX,XX +XXX,XX @@ build_madt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
-+ * This program is free software; you can redistribute it and/or modify it
+     for (i = 0; i < MACHINE(vms)->smp.cpus; i++) {
-+ * under the terms of the GNU General Public License as published by the
+         ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(i));
-+ * Free Software Foundation; either version 2 of the License, or
+         uint64_t physical_base_address = 0, gich = 0, gicv = 0;
-+ * (at your option) any later version.
+-        uint32_t vgic_interrupt = vms->virt ? PPI(ARCH_GIC_MAINT_IRQ) : 0;
-+ *
++        uint32_t vgic_interrupt = vms->virt ? ARCH_GIC_MAINT_IRQ : 0;
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
+         uint32_t pmu_interrupt = arm_feature(&armcpu->env, ARM_FEATURE_PMU) ?
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-                                             PPI(VIRTUAL_PMU_IRQ) : 0;
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
++                                             VIRTUAL_PMU_IRQ : 0;
-+ * for more details.
-+ */
+         if (vms->gic_version == VIRT_GIC_VERSION_2) {
-+#ifndef NPCM7XX_PWM_H
+             physical_base_address = memmap[VIRT_GIC_CPU].base;
-+#define NPCM7XX_PWM_H
+diff --git a/hw/arm/virt.c b/hw/arm/virt.c
 +
 +#include "hw/clock.h"
 +#include "hw/sysbus.h"
 +#include "hw/irq.h"
 +
 +/* Each PWM module holds 4 PWM channels. */
 +#define NPCM7XX_PWM_PER_MODULE 4
 +
 +/*
 + * Number of registers in one pwm module. Don't change this without increasing
 + * the version_id in vmstate.
 + */
 +#define NPCM7XX_PWM_NR_REGS (0x54 / sizeof(uint32_t))
 +
 +/*
 + * The maximum duty values. Each duty unit represents 1/NPCM7XX_PWM_MAX_DUTY
 + * cycles. For example, if NPCM7XX_PWM_MAX_DUTY=1,000,000 and a PWM has a duty
 + * value of 100,000 the duty cycle for that PWM is 10%.
 + */
 +#define NPCM7XX_PWM_MAX_DUTY 1000000
 +
 +typedef struct NPCM7xxPWMState NPCM7xxPWMState;
 +
 +/**
 + * struct NPCM7xxPWM - The state of a single PWM channel.
 + * @module: The PWM module that contains this channel.
 + * @irq: GIC interrupt line to fire on expiration if enabled.
 + * @running: Whether this PWM channel is generating output.
 + * @inverted: Whether this PWM channel is inverted.
 + * @index: The index of this PWM channel.
 + * @cnr: The counter register.
 + * @cmr: The comparator register.
 + * @pdr: The data register.
 + * @pwdr: The watchdog register.
 + * @freq: The frequency of this PWM channel.
 + * @duty: The duty cycle of this PWM channel. One unit represents
 + *   1/NPCM7XX_MAX_DUTY cycles.
 + */
 +typedef struct NPCM7xxPWM {
 +    NPCM7xxPWMState         *module;
 +
 +    qemu_irq                irq;
 +
 +    bool                    running;
 +    bool                    inverted;
 +
 +    uint8_t                 index;
 +    uint32_t                cnr;
 +    uint32_t                cmr;
 +    uint32_t                pdr;
 +    uint32_t                pwdr;
 +
 +    uint32_t                freq;
 +    uint32_t                duty;
 +} NPCM7xxPWM;
 +
 +/**
 + * struct NPCM7xxPWMState - Pulse Width Modulation device state.
 + * @parent: System bus device.
 + * @iomem: Memory region through which registers are accessed.
 + * @clock: The PWM clock.
 + * @pwm: The PWM channels owned by this module.
 + * @ppr: The prescaler register.
 + * @csr: The clock selector register.
 + * @pcr: The control register.
 + * @pier: The interrupt enable register.
 + * @piir: The interrupt indication register.
 + */
 +struct NPCM7xxPWMState {
 +    SysBusDevice parent;
 +
 +    MemoryRegion iomem;
 +
 +    Clock       *clock;
 +    NPCM7xxPWM pwm[NPCM7XX_PWM_PER_MODULE];
 +
 +    uint32_t    ppr;
 +    uint32_t    csr;
 +    uint32_t    pcr;
 +    uint32_t    pier;
 +    uint32_t    piir;
 +};
 +
 +#define TYPE_NPCM7XX_PWM "npcm7xx-pwm"
 +#define NPCM7XX_PWM(obj) \
 +    OBJECT_CHECK(NPCM7xxPWMState, (obj), TYPE_NPCM7XX_PWM)
 +
 +#endif /* NPCM7XX_PWM_H */
 diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/npcm7xx.c
+--- a/hw/arm/virt.c
-+++ b/hw/arm/npcm7xx.c
++++ b/hw/arm/virt.c
-@@ -XXX,XX +XXX,XX @@ enum NPCM7xxInterrupt {
+@@ -XXX,XX +XXX,XX @@ static void fdt_add_timer_nodes(const VirtMachineState *vms)
      NPCM7XX_WDG2_IRQ,                   /* Timer Module 2 Watchdog */
      NPCM7XX_EHCI_IRQ            = 61,
      NPCM7XX_OHCI_IRQ            = 62,
 +    NPCM7XX_PWM0_IRQ            = 93,   /* PWM module 0 */
 +    NPCM7XX_PWM1_IRQ,                   /* PWM module 1 */
      NPCM7XX_GPIO0_IRQ           = 116,
      NPCM7XX_GPIO1_IRQ,
      NPCM7XX_GPIO2_IRQ,
@@ -XXX,XX +XXX,XX @@ static const hwaddr npcm7xx_fiu3_flash_addr[] = {
 xb8000000, /* CS3 */
  };
 +/* Register base address for each PWM Module */
 +static const hwaddr npcm7xx_pwm_addr[] = {
 +    0xf0103000,
 +    0xf0104000,
 +};
 +
  static const struct {
      hwaddr regs_addr;
      uint32_t unconnected_pins;
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_init(Object *obj)
          object_initialize_child(obj, npcm7xx_fiu[i].name, &s->fiu[i],
                                  TYPE_NPCM7XX_FIU);
      }
-+
+     qemu_fdt_setprop(ms->fdt, "/timer", "always-on", NULL, 0);
-+    for (i = 0; i < ARRAY_SIZE(s->pwm); i++) {
+     qemu_fdt_setprop_cells(ms->fdt, "/timer", "interrupts",
-+        object_initialize_child(obj, "pwm[*]", &s->pwm[i], TYPE_NPCM7XX_PWM);
+-                       GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_S_EL1_IRQ, irqflags,
-+    }
+-                       GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL1_IRQ, irqflags,
 -                       GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_VIRT_IRQ, irqflags,
 -                       GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL2_IRQ, irqflags);
 +                           GIC_FDT_IRQ_TYPE_PPI,
 +                           INTID_TO_PPI(ARCH_TIMER_S_EL1_IRQ), irqflags,
 +                           GIC_FDT_IRQ_TYPE_PPI,
 +                           INTID_TO_PPI(ARCH_TIMER_NS_EL1_IRQ), irqflags,
 +                           GIC_FDT_IRQ_TYPE_PPI,
 +                           INTID_TO_PPI(ARCH_TIMER_VIRT_IRQ), irqflags,
 +                           GIC_FDT_IRQ_TYPE_PPI,
 +                           INTID_TO_PPI(ARCH_TIMER_NS_EL2_IRQ), irqflags);
  }
- static void npcm7xx_realize(DeviceState *dev, Error **errp)
+ static void fdt_add_cpu_nodes(const VirtMachineState *vms)
-@@ -XXX,XX +XXX,XX @@ static void npcm7xx_realize(DeviceState *dev, Error **errp)
+@@ -XXX,XX +XXX,XX @@ static void create_gic(VirtMachineState *vms, MemoryRegion *mem)
-     sysbus_connect_irq(SYS_BUS_DEVICE(&s->ohci), 0,
+      */
-                        npcm7xx_irq(s, NPCM7XX_OHCI_IRQ));
+     for (i = 0; i < smp_cpus; i++) {
+         DeviceState *cpudev = DEVICE(qemu_get_cpu(i));
-+    /* PWM Modules. Cannot fail. */
+-        int ppibase = NUM_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS;
-+    QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_pwm_addr) != ARRAY_SIZE(s->pwm));
++        int intidbase = NUM_IRQS + i * GIC_INTERNAL;
-+    for (i = 0; i < ARRAY_SIZE(s->pwm); i++) {
+         /* Mapping from the output timer irq lines from the CPU to the
-+        SysBusDevice *sbd = SYS_BUS_DEVICE(&s->pwm[i]);
+          * GIC PPI inputs we use for the virt board.
-+
+          */
-+        qdev_connect_clock_in(DEVICE(&s->pwm[i]), "clock", qdev_get_clock_out(
+@@ -XXX,XX +XXX,XX @@ static void create_gic(VirtMachineState *vms, MemoryRegion *mem)
-+                    DEVICE(&s->clk), "apb3-clock"));
+         for (unsigned irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) {
-+        sysbus_realize(sbd, &error_abort);
+             qdev_connect_gpio_out(cpudev, irq,
-+        sysbus_mmio_map(sbd, 0, npcm7xx_pwm_addr[i]);
+                                   qdev_get_gpio_in(vms->gic,
-+        sysbus_connect_irq(sbd, i, npcm7xx_irq(s, NPCM7XX_PWM0_IRQ + i));
+-                                                   ppibase + timer_irq[irq]));
-+    }
++                                                   intidbase + timer_irq[irq]));
-+
+         }
-     /*
-      * Flash Interface Unit (FIU). Can fail if incorrect number of chip selects
+         if (vms->gic_version != VIRT_GIC_VERSION_2) {
-      * specified, but this is a programming error.
+             qemu_irq irq = qdev_get_gpio_in(vms->gic,
-@@ -XXX,XX +XXX,XX @@ static void npcm7xx_realize(DeviceState *dev, Error **errp)
+-                                            ppibase + ARCH_GIC_MAINT_IRQ);
-     create_unimplemented_device("npcm7xx.peci",         0xf0100000,   4 * KiB);
++                                            intidbase + ARCH_GIC_MAINT_IRQ);
-     create_unimplemented_device("npcm7xx.siox[1]",      0xf0101000,   4 * KiB);
+             qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt",
-     create_unimplemented_device("npcm7xx.siox[2]",      0xf0102000,   4 * KiB);
+, irq);
--    create_unimplemented_device("npcm7xx.pwm[0]",       0xf0103000,   4 * KiB);
+         } else if (vms->virt) {
--    create_unimplemented_device("npcm7xx.pwm[1]",       0xf0104000,   4 * KiB);
+             qemu_irq irq = qdev_get_gpio_in(vms->gic,
-     create_unimplemented_device("npcm7xx.mft[0]",       0xf0180000,   4 * KiB);
+-                                            ppibase + ARCH_GIC_MAINT_IRQ);
-     create_unimplemented_device("npcm7xx.mft[1]",       0xf0181000,   4 * KiB);
++                                            intidbase + ARCH_GIC_MAINT_IRQ);
-     create_unimplemented_device("npcm7xx.mft[2]",       0xf0182000,   4 * KiB);
+             sysbus_connect_irq(gicbusdev, i + 4 * smp_cpus, irq);
-diff --git a/hw/misc/npcm7xx_pwm.c b/hw/misc/npcm7xx_pwm.c
+         }
-new file mode 100644
-index XXXXXXX..XXXXXXX
+         qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0,
---- /dev/null
+-                                    qdev_get_gpio_in(vms->gic, ppibase
-+++ b/hw/misc/npcm7xx_pwm.c
++                                    qdev_get_gpio_in(vms->gic, intidbase
-@@ -XXX,XX +XXX,XX @@
+                                                      + VIRTUAL_PMU_IRQ));
-+/*
-+ * Nuvoton NPCM7xx PWM Module
+         sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));
-+ *
+@@ -XXX,XX +XXX,XX @@ static void virt_cpu_post_init(VirtMachineState *vms, MemoryRegion *sysmem)
-+ * Copyright 2020 Google LLC
+             if (pmu) {
-+ *
+                 assert(arm_feature(&ARM_CPU(cpu)->env, ARM_FEATURE_PMU));
-+ * This program is free software; you can redistribute it and/or modify it
+                 if (kvm_irqchip_in_kernel()) {
-+ * under the terms of the GNU General Public License as published by the
+-                    kvm_arm_pmu_set_irq(cpu, PPI(VIRTUAL_PMU_IRQ));
-+ * Free Software Foundation; either version 2 of the License, or
++                    kvm_arm_pmu_set_irq(cpu, VIRTUAL_PMU_IRQ);
-+ * (at your option) any later version.
+                 }
-+ *
+                 kvm_arm_pmu_init(cpu);
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
+             }
 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
 + * for more details.
 + */
 +
 +#include "qemu/osdep.h"
 +#include "hw/irq.h"
 +#include "hw/qdev-clock.h"
 +#include "hw/qdev-properties.h"
 +#include "hw/misc/npcm7xx_pwm.h"
 +#include "hw/registerfields.h"
 +#include "migration/vmstate.h"
 +#include "qemu/bitops.h"
 +#include "qemu/error-report.h"
 +#include "qemu/log.h"
 +#include "qemu/module.h"
 +#include "qemu/units.h"
 +#include "trace.h"
 +
 +REG32(NPCM7XX_PWM_PPR, 0x00);
 +REG32(NPCM7XX_PWM_CSR, 0x04);
 +REG32(NPCM7XX_PWM_PCR, 0x08);
 +REG32(NPCM7XX_PWM_CNR0, 0x0c);
 +REG32(NPCM7XX_PWM_CMR0, 0x10);
 +REG32(NPCM7XX_PWM_PDR0, 0x14);
 +REG32(NPCM7XX_PWM_CNR1, 0x18);
 +REG32(NPCM7XX_PWM_CMR1, 0x1c);
 +REG32(NPCM7XX_PWM_PDR1, 0x20);
 +REG32(NPCM7XX_PWM_CNR2, 0x24);
 +REG32(NPCM7XX_PWM_CMR2, 0x28);
 +REG32(NPCM7XX_PWM_PDR2, 0x2c);
 +REG32(NPCM7XX_PWM_CNR3, 0x30);
 +REG32(NPCM7XX_PWM_CMR3, 0x34);
 +REG32(NPCM7XX_PWM_PDR3, 0x38);
 +REG32(NPCM7XX_PWM_PIER, 0x3c);
 +REG32(NPCM7XX_PWM_PIIR, 0x40);
 +REG32(NPCM7XX_PWM_PWDR0, 0x44);
 +REG32(NPCM7XX_PWM_PWDR1, 0x48);
 +REG32(NPCM7XX_PWM_PWDR2, 0x4c);
 +REG32(NPCM7XX_PWM_PWDR3, 0x50);
 +
 +/* Register field definitions. */
 +#define NPCM7XX_PPR(rv, index)      extract32((rv), npcm7xx_ppr_base[index], 8)
 +#define NPCM7XX_CSR(rv, index)      extract32((rv), npcm7xx_csr_base[index], 3)
 +#define NPCM7XX_CH(rv, index)       extract32((rv), npcm7xx_ch_base[index], 4)
 +#define NPCM7XX_CH_EN               BIT(0)
 +#define NPCM7XX_CH_INV              BIT(2)
 +#define NPCM7XX_CH_MOD              BIT(3)
 +
 +/* Offset of each PWM channel's prescaler in the PPR register. */
 +static const int npcm7xx_ppr_base[] = { 0, 0, 8, 8 };
 +/* Offset of each PWM channel's clock selector in the CSR register. */
 +static const int npcm7xx_csr_base[] = { 0, 4, 8, 12 };
 +/* Offset of each PWM channel's control variable in the PCR register. */
 +static const int npcm7xx_ch_base[] = { 0, 8, 12, 16 };
 +
 +static uint32_t npcm7xx_pwm_calculate_freq(NPCM7xxPWM *p)
 +{
 +    uint32_t ppr;
 +    uint32_t csr;
 +    uint32_t freq;
 +
 +    if (!p->running) {
 +        return 0;
 +    }
 +
 +    csr = NPCM7XX_CSR(p->module->csr, p->index);
 +    ppr = NPCM7XX_PPR(p->module->ppr, p->index);
 +    freq = clock_get_hz(p->module->clock);
 +    freq /= ppr + 1;
 +    /* csr can only be 0~4 */
 +    if (csr > 4) {
 +        qemu_log_mask(LOG_GUEST_ERROR,
 +                      "%s: invalid csr value %u\n",
 +                      __func__, csr);
 +        csr = 4;
 +    }
 +    /* freq won't be changed if csr == 4. */
 +    if (csr < 4) {
 +        freq >>= csr + 1;
 +    }
 +
 +    return freq / (p->cnr + 1);
 +}
 +
 +static uint32_t npcm7xx_pwm_calculate_duty(NPCM7xxPWM *p)
 +{
 +    uint64_t duty;
 +
 +    if (p->running) {
 +        if (p->cnr == 0) {
 +            duty = 0;
 +        } else if (p->cmr >= p->cnr) {
 +            duty = NPCM7XX_PWM_MAX_DUTY;
 +        } else {
 +            duty = NPCM7XX_PWM_MAX_DUTY * (p->cmr + 1) / (p->cnr + 1);
 +        }
 +    } else {
 +        duty = 0;
 +    }
 +
 +    if (p->inverted) {
 +        duty = NPCM7XX_PWM_MAX_DUTY - duty;
 +    }
 +
 +    return duty;
 +}
 +
 +static void npcm7xx_pwm_update_freq(NPCM7xxPWM *p)
 +{
 +    uint32_t freq = npcm7xx_pwm_calculate_freq(p);
 +
 +    if (freq != p->freq) {
 +        trace_npcm7xx_pwm_update_freq(DEVICE(p->module)->canonical_path,
 +                                      p->index, p->freq, freq);
 +        p->freq = freq;
 +    }
 +}
 +
 +static void npcm7xx_pwm_update_duty(NPCM7xxPWM *p)
 +{
 +    uint32_t duty = npcm7xx_pwm_calculate_duty(p);
 +
 +    if (duty != p->duty) {
 +        trace_npcm7xx_pwm_update_duty(DEVICE(p->module)->canonical_path,
 +                                      p->index, p->duty, duty);
 +        p->duty = duty;
 +    }
 +}
 +
 +static void npcm7xx_pwm_update_output(NPCM7xxPWM *p)
 +{
 +    npcm7xx_pwm_update_freq(p);
 +    npcm7xx_pwm_update_duty(p);
 +}
 +
 +static void npcm7xx_pwm_write_ppr(NPCM7xxPWMState *s, uint32_t new_ppr)
 +{
 +    int i;
 +    uint32_t old_ppr = s->ppr;
 +
 +    QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_ppr_base) != NPCM7XX_PWM_PER_MODULE);
 +    s->ppr = new_ppr;
 +    for (i = 0; i < NPCM7XX_PWM_PER_MODULE; ++i) {
 +        if (NPCM7XX_PPR(old_ppr, i) != NPCM7XX_PPR(new_ppr, i)) {
 +            npcm7xx_pwm_update_freq(&s->pwm[i]);
 +        }
 +    }
 +}
 +
 +static void npcm7xx_pwm_write_csr(NPCM7xxPWMState *s, uint32_t new_csr)
 +{
 +    int i;
 +    uint32_t old_csr = s->csr;
 +
 +    QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_csr_base) != NPCM7XX_PWM_PER_MODULE);
 +    s->csr = new_csr;
 +    for (i = 0; i < NPCM7XX_PWM_PER_MODULE; ++i) {
 +        if (NPCM7XX_CSR(old_csr, i) != NPCM7XX_CSR(new_csr, i)) {
 +            npcm7xx_pwm_update_freq(&s->pwm[i]);
 +        }
 +    }
 +}
 +
 +static void npcm7xx_pwm_write_pcr(NPCM7xxPWMState *s, uint32_t new_pcr)
 +{
 +    int i;
 +    bool inverted;
 +    uint32_t pcr;
 +    NPCM7xxPWM *p;
 +
 +    s->pcr = new_pcr;
 +    QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_ch_base) != NPCM7XX_PWM_PER_MODULE);
 +    for (i = 0; i < NPCM7XX_PWM_PER_MODULE; ++i) {
 +        p = &s->pwm[i];
 +        pcr = NPCM7XX_CH(new_pcr, i);
 +        inverted = pcr & NPCM7XX_CH_INV;
 +
 +        /*
 +         * We only run a PWM channel with toggle mode. Single-shot mode does not
 +         * generate frequency and duty-cycle values.
 +         */
 +        if ((pcr & NPCM7XX_CH_EN) && (pcr & NPCM7XX_CH_MOD)) {
 +            if (p->running) {
 +                /* Re-run this PWM channel if inverted changed. */
 +                if (p->inverted ^ inverted) {
 +                    p->inverted = inverted;
 +                    npcm7xx_pwm_update_duty(p);
 +                }
 +            } else {
 +                /* Run this PWM channel. */
 +                p->running = true;
 +                p->inverted = inverted;
 +                npcm7xx_pwm_update_output(p);
 +            }
 +        } else {
 +            /* Clear this PWM channel. */
 +            p->running = false;
 +            p->inverted = inverted;
 +            npcm7xx_pwm_update_output(p);
 +        }
 +    }
 +
 +}
 +
 +static hwaddr npcm7xx_cnr_index(hwaddr offset)
 +{
 +    switch (offset) {
 +    case A_NPCM7XX_PWM_CNR0:
 +        return 0;
 +    case A_NPCM7XX_PWM_CNR1:
 +        return 1;
 +    case A_NPCM7XX_PWM_CNR2:
 +        return 2;
 +    case A_NPCM7XX_PWM_CNR3:
 +        return 3;
 +    default:
 +        g_assert_not_reached();
 +    }
 +}
 +
 +static hwaddr npcm7xx_cmr_index(hwaddr offset)
 +{
 +    switch (offset) {
 +    case A_NPCM7XX_PWM_CMR0:
 +        return 0;
 +    case A_NPCM7XX_PWM_CMR1:
 +        return 1;
 +    case A_NPCM7XX_PWM_CMR2:
 +        return 2;
 +    case A_NPCM7XX_PWM_CMR3:
 +        return 3;
 +    default:
 +        g_assert_not_reached();
 +    }
 +}
 +
 +static hwaddr npcm7xx_pdr_index(hwaddr offset)
 +{
 +    switch (offset) {
 +    case A_NPCM7XX_PWM_PDR0:
 +        return 0;
 +    case A_NPCM7XX_PWM_PDR1:
 +        return 1;
 +    case A_NPCM7XX_PWM_PDR2:
 +        return 2;
 +    case A_NPCM7XX_PWM_PDR3:
 +        return 3;
 +    default:
 +        g_assert_not_reached();
 +    }
 +}
 +
 +static hwaddr npcm7xx_pwdr_index(hwaddr offset)
 +{
 +    switch (offset) {
 +    case A_NPCM7XX_PWM_PWDR0:
 +        return 0;
 +    case A_NPCM7XX_PWM_PWDR1:
 +        return 1;
 +    case A_NPCM7XX_PWM_PWDR2:
 +        return 2;
 +    case A_NPCM7XX_PWM_PWDR3:
 +        return 3;
 +    default:
 +        g_assert_not_reached();
 +    }
 +}
 +
 +static uint64_t npcm7xx_pwm_read(void *opaque, hwaddr offset, unsigned size)
 +{
 +    NPCM7xxPWMState *s = opaque;
 +    uint64_t value = 0;
 +
 +    switch (offset) {
 +    case A_NPCM7XX_PWM_CNR0:
 +    case A_NPCM7XX_PWM_CNR1:
 +    case A_NPCM7XX_PWM_CNR2:
 +    case A_NPCM7XX_PWM_CNR3:
 +        value = s->pwm[npcm7xx_cnr_index(offset)].cnr;
 +        break;
 +
 +    case A_NPCM7XX_PWM_CMR0:
 +    case A_NPCM7XX_PWM_CMR1:
 +    case A_NPCM7XX_PWM_CMR2:
 +    case A_NPCM7XX_PWM_CMR3:
 +        value = s->pwm[npcm7xx_cmr_index(offset)].cmr;
 +        break;
 +
 +    case A_NPCM7XX_PWM_PDR0:
 +    case A_NPCM7XX_PWM_PDR1:
 +    case A_NPCM7XX_PWM_PDR2:
 +    case A_NPCM7XX_PWM_PDR3:
 +        value = s->pwm[npcm7xx_pdr_index(offset)].pdr;
 +        break;
 +
 +    case A_NPCM7XX_PWM_PWDR0:
 +    case A_NPCM7XX_PWM_PWDR1:
 +    case A_NPCM7XX_PWM_PWDR2:
 +    case A_NPCM7XX_PWM_PWDR3:
 +        value = s->pwm[npcm7xx_pwdr_index(offset)].pwdr;
 +        break;
 +
 +    case A_NPCM7XX_PWM_PPR:
 +        value = s->ppr;
 +        break;
 +
 +    case A_NPCM7XX_PWM_CSR:
 +        value = s->csr;
 +        break;
 +
 +    case A_NPCM7XX_PWM_PCR:
 +        value = s->pcr;
 +        break;
 +
 +    case A_NPCM7XX_PWM_PIER:
 +        value = s->pier;
 +        break;
 +
 +    case A_NPCM7XX_PWM_PIIR:
 +        value = s->piir;
 +        break;
 +
 +    default:
 +        qemu_log_mask(LOG_GUEST_ERROR,
 +                      "%s: invalid offset 0x%04" HWADDR_PRIx "\n",
 +                      __func__, offset);
 +        break;
 +    }
 +
 +    trace_npcm7xx_pwm_read(DEVICE(s)->canonical_path, offset, value);
 +    return value;
 +}
 +
 +static void npcm7xx_pwm_write(void *opaque, hwaddr offset,
 +                                uint64_t v, unsigned size)
 +{
 +    NPCM7xxPWMState *s = opaque;
 +    NPCM7xxPWM *p;
 +    uint32_t value = v;
 +
 +    trace_npcm7xx_pwm_write(DEVICE(s)->canonical_path, offset, value);
 +    switch (offset) {
 +    case A_NPCM7XX_PWM_CNR0:
 +    case A_NPCM7XX_PWM_CNR1:
 +    case A_NPCM7XX_PWM_CNR2:
 +    case A_NPCM7XX_PWM_CNR3:
 +        p = &s->pwm[npcm7xx_cnr_index(offset)];
 +        p->cnr = value;
 +        npcm7xx_pwm_update_output(p);
 +        break;
 +
 +    case A_NPCM7XX_PWM_CMR0:
 +    case A_NPCM7XX_PWM_CMR1:
 +    case A_NPCM7XX_PWM_CMR2:
 +    case A_NPCM7XX_PWM_CMR3:
 +        p = &s->pwm[npcm7xx_cmr_index(offset)];
 +        p->cmr = value;
 +        npcm7xx_pwm_update_output(p);
 +        break;
 +
 +    case A_NPCM7XX_PWM_PDR0:
 +    case A_NPCM7XX_PWM_PDR1:
 +    case A_NPCM7XX_PWM_PDR2:
 +    case A_NPCM7XX_PWM_PDR3:
 +        qemu_log_mask(LOG_GUEST_ERROR,
 +                      "%s: register @ 0x%04" HWADDR_PRIx " is read-only\n",
 +                      __func__, offset);
 +        break;
 +
 +    case A_NPCM7XX_PWM_PWDR0:
 +    case A_NPCM7XX_PWM_PWDR1:
 +    case A_NPCM7XX_PWM_PWDR2:
 +    case A_NPCM7XX_PWM_PWDR3:
 +        qemu_log_mask(LOG_UNIMP,
 +                     "%s: register @ 0x%04" HWADDR_PRIx " is not implemented\n",
 +                     __func__, offset);
 +        break;
 +
 +    case A_NPCM7XX_PWM_PPR:
 +        npcm7xx_pwm_write_ppr(s, value);
 +        break;
 +
 +    case A_NPCM7XX_PWM_CSR:
 +        npcm7xx_pwm_write_csr(s, value);
 +        break;
 +
 +    case A_NPCM7XX_PWM_PCR:
 +        npcm7xx_pwm_write_pcr(s, value);
 +        break;
 +
 +    case A_NPCM7XX_PWM_PIER:
 +        qemu_log_mask(LOG_UNIMP,
 +                     "%s: register @ 0x%04" HWADDR_PRIx " is not implemented\n",
 +                     __func__, offset);
 +        break;
 +
 +    case A_NPCM7XX_PWM_PIIR:
 +        qemu_log_mask(LOG_UNIMP,
 +                     "%s: register @ 0x%04" HWADDR_PRIx " is not implemented\n",
 +                     __func__, offset);
 +        break;
 +
 +    default:
 +        qemu_log_mask(LOG_GUEST_ERROR,
 +                      "%s: invalid offset 0x%04" HWADDR_PRIx "\n",
 +                      __func__, offset);
 +        break;
 +    }
 +}
 +
 +static const struct MemoryRegionOps npcm7xx_pwm_ops = {
 +    .read       = npcm7xx_pwm_read,
 +    .write      = npcm7xx_pwm_write,
 +    .endianness = DEVICE_LITTLE_ENDIAN,
 +    .valid      = {
 +        .min_access_size        = 4,
 +        .max_access_size        = 4,
 +        .unaligned              = false,
 +    },
 +};
 +
 +static void npcm7xx_pwm_enter_reset(Object *obj, ResetType type)
 +{
 +    NPCM7xxPWMState *s = NPCM7XX_PWM(obj);
 +    int i;
 +
 +    for (i = 0; i < NPCM7XX_PWM_PER_MODULE; i++) {
 +        NPCM7xxPWM *p = &s->pwm[i];
 +
 +        p->cnr = 0x00000000;
 +        p->cmr = 0x00000000;
 +        p->pdr = 0x00000000;
 +        p->pwdr = 0x00000000;
 +    }
 +
 +    s->ppr = 0x00000000;
 +    s->csr = 0x00000000;
 +    s->pcr = 0x00000000;
 +    s->pier = 0x00000000;
 +    s->piir = 0x00000000;
 +}
 +
 +static void npcm7xx_pwm_hold_reset(Object *obj)
 +{
 +    NPCM7xxPWMState *s = NPCM7XX_PWM(obj);
 +    int i;
 +
 +    for (i = 0; i < NPCM7XX_PWM_PER_MODULE; i++) {
 +        qemu_irq_lower(s->pwm[i].irq);
 +    }
 +}
 +
 +static void npcm7xx_pwm_init(Object *obj)
 +{
 +    NPCM7xxPWMState *s = NPCM7XX_PWM(obj);
 +    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 +    int i;
 +
 +    for (i = 0; i < NPCM7XX_PWM_PER_MODULE; i++) {
 +        NPCM7xxPWM *p = &s->pwm[i];
 +        p->module = s;
 +        p->index = i;
 +        sysbus_init_irq(sbd, &p->irq);
 +    }
 +
 +    memory_region_init_io(&s->iomem, obj, &npcm7xx_pwm_ops, s,
 +                          TYPE_NPCM7XX_PWM, 4 * KiB);
 +    sysbus_init_mmio(sbd, &s->iomem);
 +    s->clock = qdev_init_clock_in(DEVICE(s), "clock", NULL, NULL);
 +
 +    for (i = 0; i < NPCM7XX_PWM_PER_MODULE; ++i) {
 +        object_property_add_uint32_ptr(obj, "freq[*]",
 +                &s->pwm[i].freq, OBJ_PROP_FLAG_READ);
 +        object_property_add_uint32_ptr(obj, "duty[*]",
 +                &s->pwm[i].duty, OBJ_PROP_FLAG_READ);
 +    }
 +}
 +
 +static const VMStateDescription vmstate_npcm7xx_pwm = {
 +    .name = "npcm7xx-pwm",
 +    .version_id = 0,
 +    .minimum_version_id = 0,
 +    .fields = (VMStateField[]) {
 +        VMSTATE_BOOL(running, NPCM7xxPWM),
 +        VMSTATE_BOOL(inverted, NPCM7xxPWM),
 +        VMSTATE_UINT8(index, NPCM7xxPWM),
 +        VMSTATE_UINT32(cnr, NPCM7xxPWM),
 +        VMSTATE_UINT32(cmr, NPCM7xxPWM),
 +        VMSTATE_UINT32(pdr, NPCM7xxPWM),
 +        VMSTATE_UINT32(pwdr, NPCM7xxPWM),
 +        VMSTATE_UINT32(freq, NPCM7xxPWM),
 +        VMSTATE_UINT32(duty, NPCM7xxPWM),
 +        VMSTATE_END_OF_LIST(),
 +    },
 +};
 +
 +static const VMStateDescription vmstate_npcm7xx_pwm_module = {
 +    .name = "npcm7xx-pwm-module",
 +    .version_id = 0,
 +    .minimum_version_id = 0,
 +    .fields = (VMStateField[]) {
 +        VMSTATE_CLOCK(clock, NPCM7xxPWMState),
 +        VMSTATE_STRUCT_ARRAY(pwm, NPCM7xxPWMState,
 +                             NPCM7XX_PWM_PER_MODULE, 0, vmstate_npcm7xx_pwm,
 +                             NPCM7xxPWM),
 +        VMSTATE_UINT32(ppr, NPCM7xxPWMState),
 +        VMSTATE_UINT32(csr, NPCM7xxPWMState),
 +        VMSTATE_UINT32(pcr, NPCM7xxPWMState),
 +        VMSTATE_UINT32(pier, NPCM7xxPWMState),
 +        VMSTATE_UINT32(piir, NPCM7xxPWMState),
 +        VMSTATE_END_OF_LIST(),
 +    },
 +};
 +
 +static void npcm7xx_pwm_class_init(ObjectClass *klass, void *data)
 +{
 +    ResettableClass *rc = RESETTABLE_CLASS(klass);
 +    DeviceClass *dc = DEVICE_CLASS(klass);
 +
 +    dc->desc = "NPCM7xx PWM Controller";
 +    dc->vmsd = &vmstate_npcm7xx_pwm_module;
 +    rc->phases.enter = npcm7xx_pwm_enter_reset;
 +    rc->phases.hold = npcm7xx_pwm_hold_reset;
 +}
 +
 +static const TypeInfo npcm7xx_pwm_info = {
 +    .name               = TYPE_NPCM7XX_PWM,
 +    .parent             = TYPE_SYS_BUS_DEVICE,
 +    .instance_size      = sizeof(NPCM7xxPWMState),
 +    .class_init         = npcm7xx_pwm_class_init,
 +    .instance_init      = npcm7xx_pwm_init,
 +};
 +
 +static void npcm7xx_pwm_register_type(void)
 +{
 +    type_register_static(&npcm7xx_pwm_info);
 +}
 +type_init(npcm7xx_pwm_register_type);
 diff --git a/hw/misc/meson.build b/hw/misc/meson.build
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/misc/meson.build
 +++ b/hw/misc/meson.build
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_MAINSTONE', if_true: files('mst_fpga.c'))
  softmmu_ss.add(when: 'CONFIG_NPCM7XX', if_true: files(
    'npcm7xx_clk.c',
    'npcm7xx_gcr.c',
 +  'npcm7xx_pwm.c',
    'npcm7xx_rng.c',
  ))
  softmmu_ss.add(when: 'CONFIG_OMAP', if_true: files(
 diff --git a/hw/misc/trace-events b/hw/misc/trace-events
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/misc/trace-events
 +++ b/hw/misc/trace-events
@@ -XXX,XX +XXX,XX @@ npcm7xx_gcr_write(uint64_t offset, uint32_t value) "offset: 0x%04" PRIx64 " valu
  npcm7xx_rng_read(uint64_t offset, uint64_t value, unsigned size) "offset: 0x%04" PRIx64 " value: 0x%02" PRIx64 " size: %u"
  npcm7xx_rng_write(uint64_t offset, uint64_t value, unsigned size) "offset: 0x%04" PRIx64 " value: 0x%02" PRIx64 " size: %u"
 +# npcm7xx_pwm.c
 +npcm7xx_pwm_read(const char *id, uint64_t offset, uint32_t value) "%s offset: 0x%04" PRIx64 " value: 0x%08" PRIx32
 +npcm7xx_pwm_write(const char *id, uint64_t offset, uint32_t value) "%s offset: 0x%04" PRIx64 " value: 0x%08" PRIx32
 +npcm7xx_pwm_update_freq(const char *id, uint8_t index, uint32_t old_value, uint32_t new_value) "%s pwm[%u] Update Freq: old_freq: %u, new_freq: %u"
 +npcm7xx_pwm_update_duty(const char *id, uint8_t index, uint32_t old_value, uint32_t new_value) "%s pwm[%u] Update Duty: old_duty: %u, new_duty: %u"
 +
  # stm32f4xx_syscfg.c
  stm32f4xx_syscfg_set_irq(int gpio, int line, int level) "Interupt: GPIO: %d, Line: %d; Level: %d"
  stm32f4xx_pulse_exti(int irq) "Pulse EXTI: %d"
 --
-.20.1
+.34.1

-[PULL 17/21] hw/adc: Add an ADC module for NPCM7XX
+[PULL 11/24] include/hw/arm: move BSA definitions to bsa.h
-From: Hao Wu <wuhaotsh@google.com>
+From: Leif Lindholm <quic_llindhol@quicinc.com>
-The ADC is part of NPCM7XX Module. Its behavior is controled by the
+virt.h defines a number of IRQs that are ultimately described by Arm's
-ADC_CON register. It converts one of the eight analog inputs into a
+Base System Architecture specification. Move these to a dedicated header
-digital input and stores it in the ADC_DATA register when enabled.
+so that they can be reused by other platforms that do the same.
 Include that header from virt.h to minimise churn.
-Users can alter input value by using qom-set QMP command.
+While we're moving the definitions, sort them into numerical order,
 and add the ARCH_TIMER_NS_EL2_VIRT_IRQ definition used by sbsa-ref
 and which will eventually be needed by virt also.
-Reviewed-by: Havard Skinnemoen <hskinnemoen@google.com>
+Signed-off-by: Leif Lindholm <quic_llindhol@quicinc.com>
-Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
+Message-id: 20230919090229.188092-3-quic_llindhol@quicinc.com
-Signed-off-by: Hao Wu <wuhaotsh@google.com>
+[PMM: Remove unused PPI_TO_INTID macro; sort numerically;
-Message-id: 20210108190945.949196-4-wuhaotsh@google.com
+ add ARCH_TIMER_NS_EL2_VIRT_IRQ]
 [PMM: Added missing hw/adc/trace.h file]
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- docs/system/arm/nuvoton.rst    |   2 +-
+ include/hw/arm/bsa.h  | 35 +++++++++++++++++++++++++++++++++++
- meson.build                    |   1 +
+ include/hw/arm/virt.h | 12 +-----------
- hw/adc/trace.h                 |   1 +
+files changed, 36 insertions(+), 11 deletions(-)
- include/hw/adc/npcm7xx_adc.h   |  69 ++++++
+ create mode 100644 include/hw/arm/bsa.h
  include/hw/arm/npcm7xx.h       |   2 +
  hw/adc/npcm7xx_adc.c           | 301 ++++++++++++++++++++++++++
  hw/arm/npcm7xx.c               |  24 ++-
  tests/qtest/npcm7xx_adc-test.c | 377 +++++++++++++++++++++++++++++++++
  hw/adc/meson.build             |   1 +
  hw/adc/trace-events            |   5 +
  tests/qtest/meson.build        |   3 +-
 files changed, 783 insertions(+), 3 deletions(-)
  create mode 100644 hw/adc/trace.h
  create mode 100644 include/hw/adc/npcm7xx_adc.h
  create mode 100644 hw/adc/npcm7xx_adc.c
  create mode 100644 tests/qtest/npcm7xx_adc-test.c
  create mode 100644 hw/adc/trace-events
-diff --git a/docs/system/arm/nuvoton.rst b/docs/system/arm/nuvoton.rst
+diff --git a/include/hw/arm/bsa.h b/include/hw/arm/bsa.h
 index XXXXXXX..XXXXXXX 100644
 --- a/docs/system/arm/nuvoton.rst
 +++ b/docs/system/arm/nuvoton.rst
@@ -XXX,XX +XXX,XX @@ Supported devices
   * Random Number Generator (RNG)
   * USB host (USBH)
   * GPIO controller
 + * Analog to Digital Converter (ADC)
  Missing devices
  ---------------
@@ -XXX,XX +XXX,XX @@ Missing devices
   * USB device (USBD)
   * SMBus controller (SMBF)
   * Peripheral SPI controller (PSPI)
 - * Analog to Digital Converter (ADC)
   * SD/MMC host
   * PECI interface
   * Pulse Width Modulation (PWM)
 diff --git a/meson.build b/meson.build
 index XXXXXXX..XXXXXXX 100644
 --- a/meson.build
 +++ b/meson.build
@@ -XXX,XX +XXX,XX @@ if have_system
      'chardev',
      'hw/9pfs',
      'hw/acpi',
 +    'hw/adc',
      'hw/alpha',
      'hw/arm',
      'hw/audio',
 diff --git a/hw/adc/trace.h b/hw/adc/trace.h
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
-+++ b/hw/adc/trace.h
++++ b/include/hw/arm/bsa.h
@@ -0,0 +1 @@
 +#include "trace/trace-hw_adc.h"
 diff --git a/include/hw/adc/npcm7xx_adc.h b/include/hw/adc/npcm7xx_adc.h
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/include/hw/adc/npcm7xx_adc.h
 @@ -XXX,XX +XXX,XX @@
 +/*
-+ * Nuvoton NPCM7xx ADC Module
++ * Common definitions for Arm Base System Architecture (BSA) platforms.
 + *
-+ * Copyright 2020 Google LLC
++ * Copyright (c) 2015 Linaro Limited
 + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
 + *
 + * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
++ * under the terms and conditions of the GNU General Public License,
-+ * Free Software Foundation; either version 2 of the License, or
++ * version 2 or later, as published by the Free Software Foundation.
 + * (at your option) any later version.
 + *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * This program is distributed in the hope it will be useful, but WITHOUT
 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-+ * for more details.
++ * more details.
 + */
 +#ifndef NPCM7XX_ADC_H
 +#define NPCM7XX_ADC_H
 +
 +#include "hw/clock.h"
 +#include "hw/irq.h"
 +#include "hw/sysbus.h"
 +#include "qemu/timer.h"
 +
 +#define NPCM7XX_ADC_NUM_INPUTS      8
 +/**
 + * This value should not be changed unless write_adc_calibration function in
 + * hw/arm/npcm7xx.c is also changed.
 + */
 +#define NPCM7XX_ADC_NUM_CALIB       2
 +
 +/**
 + * struct NPCM7xxADCState - Analog to Digital Converter Module device state.
 + * @parent: System bus device.
 + * @iomem: Memory region through which registers are accessed.
 + * @conv_timer: The timer counts down remaining cycles for the conversion.
 + * @irq: GIC interrupt line to fire on expiration (if enabled).
 + * @con: The Control Register.
 + * @data: The Data Buffer.
 + * @clock: The ADC Clock.
 + * @adci: The input voltage in units of uV. 1uv = 1e-6V.
 + * @vref: The external reference voltage.
 + * @iref: The internal reference voltage, initialized at launch time.
 + * @rv: The calibrated output values of 0.5V and 1.5V for the ADC.
 + */
 +typedef struct {
 +    SysBusDevice parent;
 +
 +    MemoryRegion iomem;
 +
 +    QEMUTimer    conv_timer;
 +
 +    qemu_irq     irq;
 +    uint32_t     con;
 +    uint32_t     data;
 +    Clock       *clock;
 +
 +    /* Voltages are in unit of uV. 1V = 1000000uV. */
 +    uint32_t     adci[NPCM7XX_ADC_NUM_INPUTS];
 +    uint32_t     vref;
 +    uint32_t     iref;
 +
 +    uint16_t     calibration_r_values[NPCM7XX_ADC_NUM_CALIB];
 +} NPCM7xxADCState;
 +
 +#define TYPE_NPCM7XX_ADC "npcm7xx-adc"
 +#define NPCM7XX_ADC(obj) \
 +    OBJECT_CHECK(NPCM7xxADCState, (obj), TYPE_NPCM7XX_ADC)
 +
 +#endif /* NPCM7XX_ADC_H */
 diff --git a/include/hw/arm/npcm7xx.h b/include/hw/arm/npcm7xx.h
 index XXXXXXX..XXXXXXX 100644
 --- a/include/hw/arm/npcm7xx.h
 +++ b/include/hw/arm/npcm7xx.h
@@ -XXX,XX +XXX,XX @@
  #define NPCM7XX_H
  #include "hw/boards.h"
 +#include "hw/adc/npcm7xx_adc.h"
  #include "hw/cpu/a9mpcore.h"
  #include "hw/gpio/npcm7xx_gpio.h"
  #include "hw/mem/npcm7xx_mc.h"
@@ -XXX,XX +XXX,XX @@ typedef struct NPCM7xxState {
      NPCM7xxGCRState     gcr;
      NPCM7xxCLKState     clk;
      NPCM7xxTimerCtrlState tim[3];
 +    NPCM7xxADCState     adc;
      NPCM7xxOTPState     key_storage;
      NPCM7xxOTPState     fuse_array;
      NPCM7xxMCState      mc;
 diff --git a/hw/adc/npcm7xx_adc.c b/hw/adc/npcm7xx_adc.c
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/hw/adc/npcm7xx_adc.c
@@ -XXX,XX +XXX,XX @@
 +/*
 + * Nuvoton NPCM7xx ADC Module
 + *
-+ * Copyright 2020 Google LLC
++ * You should have received a copy of the GNU General Public License along with
 + * this program.  If not, see <http://www.gnu.org/licenses/>.
 + *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-+ * for more details.
 + */
 +
-+#include "qemu/osdep.h"
++#ifndef QEMU_ARM_BSA_H
-+#include "hw/adc/npcm7xx_adc.h"
++#define QEMU_ARM_BSA_H
 +#include "hw/qdev-clock.h"
 +#include "hw/qdev-properties.h"
 +#include "hw/registerfields.h"
 +#include "migration/vmstate.h"
 +#include "qemu/log.h"
 +#include "qemu/module.h"
 +#include "qemu/timer.h"
 +#include "qemu/units.h"
 +#include "trace.h"
 +
-+REG32(NPCM7XX_ADC_CON, 0x0)
++/* These are architectural INTID values */
-+REG32(NPCM7XX_ADC_DATA, 0x4)
++#define VIRTUAL_PMU_IRQ            23
 +#define ARCH_GIC_MAINT_IRQ         25
 +#define ARCH_TIMER_NS_EL2_IRQ      26
 +#define ARCH_TIMER_VIRT_IRQ        27
 +#define ARCH_TIMER_NS_EL2_VIRT_IRQ 28
 +#define ARCH_TIMER_S_EL1_IRQ       29
 +#define ARCH_TIMER_NS_EL1_IRQ      30
 +
-+/* Register field definitions. */
++#define INTID_TO_PPI(irq) ((irq) - 16)
 +#define NPCM7XX_ADC_CON_MUX(rv) extract32(rv, 24, 4)
 +#define NPCM7XX_ADC_CON_INT_EN  BIT(21)
 +#define NPCM7XX_ADC_CON_REFSEL  BIT(19)
 +#define NPCM7XX_ADC_CON_INT     BIT(18)
 +#define NPCM7XX_ADC_CON_EN      BIT(17)
 +#define NPCM7XX_ADC_CON_RST     BIT(16)
 +#define NPCM7XX_ADC_CON_CONV    BIT(14)
 +#define NPCM7XX_ADC_CON_DIV(rv) extract32(rv, 1, 8)
 +
-+#define NPCM7XX_ADC_MAX_RESULT      1023
++#endif /* QEMU_ARM_BSA_H */
-+#define NPCM7XX_ADC_DEFAULT_IREF    2000000
+diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
 +#define NPCM7XX_ADC_CONV_CYCLES     20
 +#define NPCM7XX_ADC_RESET_CYCLES    10
 +#define NPCM7XX_ADC_R0_INPUT        500000
 +#define NPCM7XX_ADC_R1_INPUT        1500000
 +
 +static void npcm7xx_adc_reset(NPCM7xxADCState *s)
 +{
 +    timer_del(&s->conv_timer);
 +    s->con = 0x000c0001;
 +    s->data = 0x00000000;
 +}
 +
 +static uint32_t npcm7xx_adc_convert(uint32_t input, uint32_t ref)
 +{
 +    uint32_t result;
 +
 +    result = input * (NPCM7XX_ADC_MAX_RESULT + 1) / ref;
 +    if (result > NPCM7XX_ADC_MAX_RESULT) {
 +        result = NPCM7XX_ADC_MAX_RESULT;
 +    }
 +
 +    return result;
 +}
 +
 +static uint32_t npcm7xx_adc_prescaler(NPCM7xxADCState *s)
 +{
 +    return 2 * (NPCM7XX_ADC_CON_DIV(s->con) + 1);
 +}
 +
 +static void npcm7xx_adc_start_timer(Clock *clk, QEMUTimer *timer,
 +        uint32_t cycles, uint32_t prescaler)
 +{
 +    int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
 +    int64_t ticks = cycles;
 +    int64_t ns;
 +
 +    ticks *= prescaler;
 +    ns = clock_ticks_to_ns(clk, ticks);
 +    ns += now;
 +    timer_mod(timer, ns);
 +}
 +
 +static void npcm7xx_adc_start_convert(NPCM7xxADCState *s)
 +{
 +    uint32_t prescaler = npcm7xx_adc_prescaler(s);
 +
 +    npcm7xx_adc_start_timer(s->clock, &s->conv_timer, NPCM7XX_ADC_CONV_CYCLES,
 +            prescaler);
 +}
 +
 +static void npcm7xx_adc_convert_done(void *opaque)
 +{
 +    NPCM7xxADCState *s = opaque;
 +    uint32_t input = NPCM7XX_ADC_CON_MUX(s->con);
 +    uint32_t ref = (s->con & NPCM7XX_ADC_CON_REFSEL)
 +        ? s->iref : s->vref;
 +
 +    if (input >= NPCM7XX_ADC_NUM_INPUTS) {
 +        qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid input: %u\n",
 +                      __func__, input);
 +        return;
 +    }
 +    s->data = npcm7xx_adc_convert(s->adci[input], ref);
 +    if (s->con & NPCM7XX_ADC_CON_INT_EN) {
 +        s->con |= NPCM7XX_ADC_CON_INT;
 +        qemu_irq_raise(s->irq);
 +    }
 +    s->con &= ~NPCM7XX_ADC_CON_CONV;
 +}
 +
 +static void npcm7xx_adc_calibrate(NPCM7xxADCState *adc)
 +{
 +    adc->calibration_r_values[0] = npcm7xx_adc_convert(NPCM7XX_ADC_R0_INPUT,
 +            adc->iref);
 +    adc->calibration_r_values[1] = npcm7xx_adc_convert(NPCM7XX_ADC_R1_INPUT,
 +            adc->iref);
 +}
 +
 +static void npcm7xx_adc_write_con(NPCM7xxADCState *s, uint32_t new_con)
 +{
 +    uint32_t old_con = s->con;
 +
 +    /* Write ADC_INT to 1 to clear it */
 +    if (new_con & NPCM7XX_ADC_CON_INT) {
 +        new_con &= ~NPCM7XX_ADC_CON_INT;
 +        qemu_irq_lower(s->irq);
 +    } else if (old_con & NPCM7XX_ADC_CON_INT) {
 +        new_con |= NPCM7XX_ADC_CON_INT;
 +    }
 +
 +    s->con = new_con;
 +
 +    if (s->con & NPCM7XX_ADC_CON_RST) {
 +        npcm7xx_adc_reset(s);
 +        return;
 +    }
 +
 +    if ((s->con & NPCM7XX_ADC_CON_EN)) {
 +        if (s->con & NPCM7XX_ADC_CON_CONV) {
 +            if (!(old_con & NPCM7XX_ADC_CON_CONV)) {
 +                npcm7xx_adc_start_convert(s);
 +            }
 +        } else {
 +            timer_del(&s->conv_timer);
 +        }
 +    }
 +}
 +
 +static uint64_t npcm7xx_adc_read(void *opaque, hwaddr offset, unsigned size)
 +{
 +    uint64_t value = 0;
 +    NPCM7xxADCState *s = opaque;
 +
 +    switch (offset) {
 +    case A_NPCM7XX_ADC_CON:
 +        value = s->con;
 +        break;
 +
 +    case A_NPCM7XX_ADC_DATA:
 +        value = s->data;
 +        break;
 +
 +    default:
 +        qemu_log_mask(LOG_GUEST_ERROR,
 +                      "%s: invalid offset 0x%04" HWADDR_PRIx "\n",
 +                      __func__, offset);
 +        break;
 +    }
 +
 +    trace_npcm7xx_adc_read(DEVICE(s)->canonical_path, offset, value);
 +    return value;
 +}
 +
 +static void npcm7xx_adc_write(void *opaque, hwaddr offset, uint64_t v,
 +        unsigned size)
 +{
 +    NPCM7xxADCState *s = opaque;
 +
 +    trace_npcm7xx_adc_write(DEVICE(s)->canonical_path, offset, v);
 +    switch (offset) {
 +    case A_NPCM7XX_ADC_CON:
 +        npcm7xx_adc_write_con(s, v);
 +        break;
 +
 +    case A_NPCM7XX_ADC_DATA:
 +        qemu_log_mask(LOG_GUEST_ERROR,
 +                      "%s: register @ 0x%04" HWADDR_PRIx " is read-only\n",
 +                      __func__, offset);
 +        break;
 +
 +    default:
 +        qemu_log_mask(LOG_GUEST_ERROR,
 +                      "%s: invalid offset 0x%04" HWADDR_PRIx "\n",
 +                      __func__, offset);
 +        break;
 +    }
 +
 +}
 +
 +static const struct MemoryRegionOps npcm7xx_adc_ops = {
 +    .read       = npcm7xx_adc_read,
 +    .write      = npcm7xx_adc_write,
 +    .endianness = DEVICE_LITTLE_ENDIAN,
 +    .valid      = {
 +        .min_access_size        = 4,
 +        .max_access_size        = 4,
 +        .unaligned              = false,
 +    },
 +};
 +
 +static void npcm7xx_adc_enter_reset(Object *obj, ResetType type)
 +{
 +    NPCM7xxADCState *s = NPCM7XX_ADC(obj);
 +
 +    npcm7xx_adc_reset(s);
 +}
 +
 +static void npcm7xx_adc_hold_reset(Object *obj)
 +{
 +    NPCM7xxADCState *s = NPCM7XX_ADC(obj);
 +
 +    qemu_irq_lower(s->irq);
 +}
 +
 +static void npcm7xx_adc_init(Object *obj)
 +{
 +    NPCM7xxADCState *s = NPCM7XX_ADC(obj);
 +    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 +    int i;
 +
 +    sysbus_init_irq(sbd, &s->irq);
 +
 +    timer_init_ns(&s->conv_timer, QEMU_CLOCK_VIRTUAL,
 +            npcm7xx_adc_convert_done, s);
 +    memory_region_init_io(&s->iomem, obj, &npcm7xx_adc_ops, s,
 +                          TYPE_NPCM7XX_ADC, 4 * KiB);
 +    sysbus_init_mmio(sbd, &s->iomem);
 +    s->clock = qdev_init_clock_in(DEVICE(s), "clock", NULL, NULL);
 +
 +    for (i = 0; i < NPCM7XX_ADC_NUM_INPUTS; ++i) {
 +        object_property_add_uint32_ptr(obj, "adci[*]",
 +                &s->adci[i], OBJ_PROP_FLAG_WRITE);
 +    }
 +    object_property_add_uint32_ptr(obj, "vref",
 +            &s->vref, OBJ_PROP_FLAG_WRITE);
 +    npcm7xx_adc_calibrate(s);
 +}
 +
 +static const VMStateDescription vmstate_npcm7xx_adc = {
 +    .name = "npcm7xx-adc",
 +    .version_id = 0,
 +    .minimum_version_id = 0,
 +    .fields = (VMStateField[]) {
 +        VMSTATE_TIMER(conv_timer, NPCM7xxADCState),
 +        VMSTATE_UINT32(con, NPCM7xxADCState),
 +        VMSTATE_UINT32(data, NPCM7xxADCState),
 +        VMSTATE_CLOCK(clock, NPCM7xxADCState),
 +        VMSTATE_UINT32_ARRAY(adci, NPCM7xxADCState, NPCM7XX_ADC_NUM_INPUTS),
 +        VMSTATE_UINT32(vref, NPCM7xxADCState),
 +        VMSTATE_UINT32(iref, NPCM7xxADCState),
 +        VMSTATE_UINT16_ARRAY(calibration_r_values, NPCM7xxADCState,
 +                NPCM7XX_ADC_NUM_CALIB),
 +        VMSTATE_END_OF_LIST(),
 +    },
 +};
 +
 +static Property npcm7xx_timer_properties[] = {
 +    DEFINE_PROP_UINT32("iref", NPCM7xxADCState, iref, NPCM7XX_ADC_DEFAULT_IREF),
 +    DEFINE_PROP_END_OF_LIST(),
 +};
 +
 +static void npcm7xx_adc_class_init(ObjectClass *klass, void *data)
 +{
 +    ResettableClass *rc = RESETTABLE_CLASS(klass);
 +    DeviceClass *dc = DEVICE_CLASS(klass);
 +
 +    dc->desc = "NPCM7xx ADC Module";
 +    dc->vmsd = &vmstate_npcm7xx_adc;
 +    rc->phases.enter = npcm7xx_adc_enter_reset;
 +    rc->phases.hold = npcm7xx_adc_hold_reset;
 +
 +    device_class_set_props(dc, npcm7xx_timer_properties);
 +}
 +
 +static const TypeInfo npcm7xx_adc_info = {
 +    .name               = TYPE_NPCM7XX_ADC,
 +    .parent             = TYPE_SYS_BUS_DEVICE,
 +    .instance_size      = sizeof(NPCM7xxADCState),
 +    .class_init         = npcm7xx_adc_class_init,
 +    .instance_init      = npcm7xx_adc_init,
 +};
 +
 +static void npcm7xx_adc_register_types(void)
 +{
 +    type_register_static(&npcm7xx_adc_info);
 +}
 +
 +type_init(npcm7xx_adc_register_types);
 diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/npcm7xx.c
+--- a/include/hw/arm/virt.h
-+++ b/hw/arm/npcm7xx.c
++++ b/include/hw/arm/virt.h
 @@ -XXX,XX +XXX,XX @@
- #define NPCM7XX_EHCI_BA         (0xf0806000)
+ #include "qemu/notify.h"
- #define NPCM7XX_OHCI_BA         (0xf0807000)
+ #include "hw/boards.h"
+ #include "hw/arm/boot.h"
-+/* ADC Module */
++#include "hw/arm/bsa.h"
-+#define NPCM7XX_ADC_BA          (0xf000c000)
+ #include "hw/block/flash.h"
-+
+ #include "sysemu/kvm.h"
- /* Internal AHB SRAM */
+ #include "hw/intc/arm_gicv3_common.h"
  #define NPCM7XX_RAM3_BA         (0xc0008000)
  #define NPCM7XX_RAM3_SZ         (4 * KiB)
 @@ -XXX,XX +XXX,XX @@
- #define NPCM7XX_ROM_BA          (0xffff0000)
+ #define NUM_VIRTIO_TRANSPORTS 32
- #define NPCM7XX_ROM_SZ          (64 * KiB)
+ #define NUM_SMMU_IRQS          4
-+
+-#define ARCH_GIC_MAINT_IRQ  25
- /* Clock configuration values to be fixed up when bypassing bootloader */
+-
+-#define ARCH_TIMER_VIRT_IRQ   27
- /* Run PLL1 at 1600 MHz */
+-#define ARCH_TIMER_S_EL1_IRQ  29
-@@ -XXX,XX +XXX,XX @@
+-#define ARCH_TIMER_NS_EL1_IRQ 30
-  * interrupts.
+-#define ARCH_TIMER_NS_EL2_IRQ 26
-  */
+-
- enum NPCM7xxInterrupt {
+-#define VIRTUAL_PMU_IRQ 23
-+    NPCM7XX_ADC_IRQ             = 0,
+-
-     NPCM7XX_UART0_IRQ           = 2,
+-#define INTID_TO_PPI(irq) ((irq) - 16)
-     NPCM7XX_UART1_IRQ,
+-
-     NPCM7XX_UART2_IRQ,
+ /* See Linux kernel arch/arm64/include/asm/pvclock-abi.h */
-@@ -XXX,XX +XXX,XX @@ static void npcm7xx_init_fuses(NPCM7xxState *s)
+ #define PVTIME_SIZE_PER_CPU 64
-                             sizeof(value));
  }
 +static void npcm7xx_write_adc_calibration(NPCM7xxState *s)
 +{
 +    /* Both ADC and the fuse array must have realized. */
 +    QEMU_BUILD_BUG_ON(sizeof(s->adc.calibration_r_values) != 4);
 +    npcm7xx_otp_array_write(&s->fuse_array, s->adc.calibration_r_values,
 +            NPCM7XX_FUSE_ADC_CALIB, sizeof(s->adc.calibration_r_values));
 +}
 +
  static qemu_irq npcm7xx_irq(NPCM7xxState *s, int n)
  {
      return qdev_get_gpio_in(DEVICE(&s->a9mpcore), n);
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_init(Object *obj)
                              TYPE_NPCM7XX_FUSE_ARRAY);
      object_initialize_child(obj, "mc", &s->mc, TYPE_NPCM7XX_MC);
      object_initialize_child(obj, "rng", &s->rng, TYPE_NPCM7XX_RNG);
 +    object_initialize_child(obj, "adc", &s->adc, TYPE_NPCM7XX_ADC);
      for (i = 0; i < ARRAY_SIZE(s->tim); i++) {
          object_initialize_child(obj, "tim[*]", &s->tim[i], TYPE_NPCM7XX_TIMER);
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_realize(DeviceState *dev, Error **errp)
      sysbus_realize(SYS_BUS_DEVICE(&s->mc), &error_abort);
      sysbus_mmio_map(SYS_BUS_DEVICE(&s->mc), 0, NPCM7XX_MC_BA);
 +    /* ADC Modules. Cannot fail. */
 +    qdev_connect_clock_in(DEVICE(&s->adc), "clock", qdev_get_clock_out(
 +                          DEVICE(&s->clk), "adc-clock"));
 +    sysbus_realize(SYS_BUS_DEVICE(&s->adc), &error_abort);
 +    sysbus_mmio_map(SYS_BUS_DEVICE(&s->adc), 0, NPCM7XX_ADC_BA);
 +    sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0,
 +            npcm7xx_irq(s, NPCM7XX_ADC_IRQ));
 +    npcm7xx_write_adc_calibration(s);
 +
      /* Timer Modules (TIM). Cannot fail. */
      QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_tim_addr) != ARRAY_SIZE(s->tim));
      for (i = 0; i < ARRAY_SIZE(s->tim); i++) {
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_realize(DeviceState *dev, Error **errp)
      create_unimplemented_device("npcm7xx.vdmx",         0xe0800000,   4 * KiB);
      create_unimplemented_device("npcm7xx.pcierc",       0xe1000000,  64 * KiB);
      create_unimplemented_device("npcm7xx.kcs",          0xf0007000,   4 * KiB);
 -    create_unimplemented_device("npcm7xx.adc",          0xf000c000,   4 * KiB);
      create_unimplemented_device("npcm7xx.gfxi",         0xf000e000,   4 * KiB);
      create_unimplemented_device("npcm7xx.gpio[0]",      0xf0010000,   4 * KiB);
      create_unimplemented_device("npcm7xx.gpio[1]",      0xf0011000,   4 * KiB);
 diff --git a/tests/qtest/npcm7xx_adc-test.c b/tests/qtest/npcm7xx_adc-test.c
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/tests/qtest/npcm7xx_adc-test.c
@@ -XXX,XX +XXX,XX @@
 +/*
 + * QTests for Nuvoton NPCM7xx ADCModules.
 + *
 + * Copyright 2020 Google LLC
 + *
 + * This program is free software; you can redistribute it and/or modify it
 + * under the terms of the GNU General Public License as published by the
 + * Free Software Foundation; either version 2 of the License, or
 + * (at your option) any later version.
 + *
 + * This program is distributed in the hope that it will be useful, but WITHOUT
 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
 + * for more details.
 + */
 +
 +#include "qemu/osdep.h"
 +#include "qemu/bitops.h"
 +#include "qemu/timer.h"
 +#include "libqos/libqtest.h"
 +#include "qapi/qmp/qdict.h"
 +
 +#define REF_HZ          (25000000)
 +
 +#define CON_OFFSET      0x0
 +#define DATA_OFFSET     0x4
 +
 +#define NUM_INPUTS      8
 +#define DEFAULT_IREF    2000000
 +#define CONV_CYCLES     20
 +#define RESET_CYCLES    10
 +#define R0_INPUT        500000
 +#define R1_INPUT        1500000
 +#define MAX_RESULT      1023
 +
 +#define DEFAULT_CLKDIV  5
 +
 +#define FUSE_ARRAY_BA   0xf018a000
 +#define FCTL_OFFSET     0x14
 +#define FST_OFFSET      0x0
 +#define FADDR_OFFSET    0x4
 +#define FDATA_OFFSET    0x8
 +#define ADC_CALIB_ADDR  24
 +#define FUSE_READ       0x2
 +
 +/* Register field definitions. */
 +#define CON_MUX(rv) ((rv) << 24)
 +#define CON_INT_EN  BIT(21)
 +#define CON_REFSEL  BIT(19)
 +#define CON_INT     BIT(18)
 +#define CON_EN      BIT(17)
 +#define CON_RST     BIT(16)
 +#define CON_CONV    BIT(14)
 +#define CON_DIV(rv) extract32(rv, 1, 8)
 +
 +#define FST_RDST    BIT(1)
 +#define FDATA_MASK  0xff
 +
 +#define MAX_ERROR   10000
 +#define MIN_CALIB_INPUT 100000
 +#define MAX_CALIB_INPUT 1800000
 +
 +static const uint32_t input_list[] = {
 +    100000,
 +    500000,
 +    1000000,
 +    1500000,
 +    1800000,
 +    2000000,
 +};
 +
 +static const uint32_t vref_list[] = {
 +    2000000,
 +    2200000,
 +    2500000,
 +};
 +
 +static const uint32_t iref_list[] = {
 +    1800000,
 +    1900000,
 +    2000000,
 +    2100000,
 +    2200000,
 +};
 +
 +static const uint32_t div_list[] = {0, 1, 3, 7, 15};
 +
 +typedef struct ADC {
 +    int irq;
 +    uint64_t base_addr;
 +} ADC;
 +
 +ADC adc = {
 +    .irq        = 0,
 +    .base_addr  = 0xf000c000
 +};
 +
 +static uint32_t adc_read_con(QTestState *qts, const ADC *adc)
 +{
 +    return qtest_readl(qts, adc->base_addr + CON_OFFSET);
 +}
 +
 +static void adc_write_con(QTestState *qts, const ADC *adc, uint32_t value)
 +{
 +    qtest_writel(qts, adc->base_addr + CON_OFFSET, value);
 +}
 +
 +static uint32_t adc_read_data(QTestState *qts, const ADC *adc)
 +{
 +    return qtest_readl(qts, adc->base_addr + DATA_OFFSET);
 +}
 +
 +static uint32_t adc_calibrate(uint32_t measured, uint32_t *rv)
 +{
 +    return R0_INPUT + (R1_INPUT - R0_INPUT) * (int32_t)(measured - rv[0])
 +        / (int32_t)(rv[1] - rv[0]);
 +}
 +
 +static void adc_qom_set(QTestState *qts, const ADC *adc,
 +        const char *name, uint32_t value)
 +{
 +    QDict *response;
 +    const char *path = "/machine/soc/adc";
 +
 +    g_test_message("Setting properties %s of %s with value %u",
 +            name, path, value);
 +    response = qtest_qmp(qts, "{ 'execute': 'qom-set',"
 +            " 'arguments': { 'path': %s, 'property': %s, 'value': %u}}",
 +            path, name, value);
 +    /* The qom set message returns successfully. */
 +    g_assert_true(qdict_haskey(response, "return"));
 +}
 +
 +static void adc_write_input(QTestState *qts, const ADC *adc,
 +        uint32_t index, uint32_t value)
 +{
 +    char name[100];
 +
 +    sprintf(name, "adci[%u]", index);
 +    adc_qom_set(qts, adc, name, value);
 +}
 +
 +static void adc_write_vref(QTestState *qts, const ADC *adc, uint32_t value)
 +{
 +    adc_qom_set(qts, adc, "vref", value);
 +}
 +
 +static uint32_t adc_calculate_output(uint32_t input, uint32_t ref)
 +{
 +    uint32_t output;
 +
 +    g_assert_cmpuint(input, <=, ref);
 +    output = (input * (MAX_RESULT + 1)) / ref;
 +    if (output > MAX_RESULT) {
 +        output = MAX_RESULT;
 +    }
 +
 +    return output;
 +}
 +
 +static uint32_t adc_prescaler(QTestState *qts, const ADC *adc)
 +{
 +    uint32_t div = extract32(adc_read_con(qts, adc), 1, 8);
 +
 +    return 2 * (div + 1);
 +}
 +
 +static int64_t adc_calculate_steps(uint32_t cycles, uint32_t prescale,
 +        uint32_t clkdiv)
 +{
 +    return (NANOSECONDS_PER_SECOND / (REF_HZ >> clkdiv)) * cycles * prescale;
 +}
 +
 +static void adc_wait_conv_finished(QTestState *qts, const ADC *adc,
 +        uint32_t clkdiv)
 +{
 +    uint32_t prescaler = adc_prescaler(qts, adc);
 +
 +    /*
 +     * ADC should takes roughly 20 cycles to convert one sample. So we assert it
 +     * should take 10~30 cycles here.
 +     */
 +    qtest_clock_step(qts, adc_calculate_steps(CONV_CYCLES / 2, prescaler,
 +                clkdiv));
 +    /* ADC is still converting. */
 +    g_assert_true(adc_read_con(qts, adc) & CON_CONV);
 +    qtest_clock_step(qts, adc_calculate_steps(CONV_CYCLES, prescaler, clkdiv));
 +    /* ADC has finished conversion. */
 +    g_assert_false(adc_read_con(qts, adc) & CON_CONV);
 +}
 +
 +/* Check ADC can be reset to default value. */
 +static void test_init(gconstpointer adc_p)
 +{
 +    const ADC *adc = adc_p;
 +
 +    QTestState *qts = qtest_init("-machine quanta-gsj");
 +    adc_write_con(qts, adc, CON_REFSEL | CON_INT);
 +    g_assert_cmphex(adc_read_con(qts, adc), ==, CON_REFSEL);
 +    qtest_quit(qts);
 +}
 +
 +/* Check ADC can convert from an internal reference. */
 +static void test_convert_internal(gconstpointer adc_p)
 +{
 +    const ADC *adc = adc_p;
 +    uint32_t index, input, output, expected_output;
 +    QTestState *qts = qtest_init("-machine quanta-gsj");
 +    qtest_irq_intercept_in(qts, "/machine/soc/a9mpcore/gic");
 +
 +    for (index = 0; index < NUM_INPUTS; ++index) {
 +        for (size_t i = 0; i < ARRAY_SIZE(input_list); ++i) {
 +            input = input_list[i];
 +            expected_output = adc_calculate_output(input, DEFAULT_IREF);
 +
 +            adc_write_input(qts, adc, index, input);
 +            adc_write_con(qts, adc, CON_MUX(index) | CON_REFSEL | CON_INT |
 +                    CON_EN | CON_CONV);
 +            adc_wait_conv_finished(qts, adc, DEFAULT_CLKDIV);
 +            g_assert_cmphex(adc_read_con(qts, adc), ==, CON_MUX(index) |
 +                    CON_REFSEL | CON_EN);
 +            g_assert_false(qtest_get_irq(qts, adc->irq));
 +            output = adc_read_data(qts, adc);
 +            g_assert_cmpuint(output, ==, expected_output);
 +        }
 +    }
 +
 +    qtest_quit(qts);
 +}
 +
 +/* Check ADC can convert from an external reference. */
 +static void test_convert_external(gconstpointer adc_p)
 +{
 +    const ADC *adc = adc_p;
 +    uint32_t index, input, vref, output, expected_output;
 +    QTestState *qts = qtest_init("-machine quanta-gsj");
 +    qtest_irq_intercept_in(qts, "/machine/soc/a9mpcore/gic");
 +
 +    for (index = 0; index < NUM_INPUTS; ++index) {
 +        for (size_t i = 0; i < ARRAY_SIZE(input_list); ++i) {
 +            for (size_t j = 0; j < ARRAY_SIZE(vref_list); ++j) {
 +                input = input_list[i];
 +                vref = vref_list[j];
 +                expected_output = adc_calculate_output(input, vref);
 +
 +                adc_write_input(qts, adc, index, input);
 +                adc_write_vref(qts, adc, vref);
 +                adc_write_con(qts, adc, CON_MUX(index) | CON_INT | CON_EN |
 +                        CON_CONV);
 +                adc_wait_conv_finished(qts, adc, DEFAULT_CLKDIV);
 +                g_assert_cmphex(adc_read_con(qts, adc), ==,
 +                        CON_MUX(index) | CON_EN);
 +                g_assert_false(qtest_get_irq(qts, adc->irq));
 +                output = adc_read_data(qts, adc);
 +                g_assert_cmpuint(output, ==, expected_output);
 +            }
 +        }
 +    }
 +
 +    qtest_quit(qts);
 +}
 +
 +/* Check ADC interrupt files if and only if CON_INT_EN is set. */
 +static void test_interrupt(gconstpointer adc_p)
 +{
 +    const ADC *adc = adc_p;
 +    uint32_t index, input, output, expected_output;
 +    QTestState *qts = qtest_init("-machine quanta-gsj");
 +
 +    index = 1;
 +    input = input_list[1];
 +    expected_output = adc_calculate_output(input, DEFAULT_IREF);
 +
 +    qtest_irq_intercept_in(qts, "/machine/soc/a9mpcore/gic");
 +    adc_write_input(qts, adc, index, input);
 +    g_assert_false(qtest_get_irq(qts, adc->irq));
 +    adc_write_con(qts, adc, CON_MUX(index) | CON_INT_EN | CON_REFSEL | CON_INT
 +            | CON_EN | CON_CONV);
 +    adc_wait_conv_finished(qts, adc, DEFAULT_CLKDIV);
 +    g_assert_cmphex(adc_read_con(qts, adc), ==, CON_MUX(index) | CON_INT_EN
 +            | CON_REFSEL | CON_INT | CON_EN);
 +    g_assert_true(qtest_get_irq(qts, adc->irq));
 +    output = adc_read_data(qts, adc);
 +    g_assert_cmpuint(output, ==, expected_output);
 +
 +    qtest_quit(qts);
 +}
 +
 +/* Check ADC is reset after setting ADC_RST for 10 ADC cycles. */
 +static void test_reset(gconstpointer adc_p)
 +{
 +    const ADC *adc = adc_p;
 +    QTestState *qts = qtest_init("-machine quanta-gsj");
 +
 +    for (size_t i = 0; i < ARRAY_SIZE(div_list); ++i) {
 +        uint32_t div = div_list[i];
 +
 +        adc_write_con(qts, adc, CON_INT | CON_EN | CON_RST | CON_DIV(div));
 +        qtest_clock_step(qts, adc_calculate_steps(RESET_CYCLES,
 +                    adc_prescaler(qts, adc), DEFAULT_CLKDIV));
 +        g_assert_false(adc_read_con(qts, adc) & CON_EN);
 +    }
 +    qtest_quit(qts);
 +}
 +
 +/* Check ADC Calibration works as desired. */
 +static void test_calibrate(gconstpointer adc_p)
 +{
 +    int i, j;
 +    const ADC *adc = adc_p;
 +
 +    for (j = 0; j < ARRAY_SIZE(iref_list); ++j) {
 +        uint32_t iref = iref_list[j];
 +        uint32_t expected_rv[] = {
 +            adc_calculate_output(R0_INPUT, iref),
 +            adc_calculate_output(R1_INPUT, iref),
 +        };
 +        char buf[100];
 +        QTestState *qts;
 +
 +        sprintf(buf, "-machine quanta-gsj -global npcm7xx-adc.iref=%u", iref);
 +        qts = qtest_init(buf);
 +
 +        /* Check the converted value is correct using the calibration value. */
 +        for (i = 0; i < ARRAY_SIZE(input_list); ++i) {
 +            uint32_t input;
 +            uint32_t output;
 +            uint32_t expected_output;
 +            uint32_t calibrated_voltage;
 +            uint32_t index = 0;
 +
 +            input = input_list[i];
 +            /* Calibration only works for input range 0.1V ~ 1.8V. */
 +            if (input < MIN_CALIB_INPUT || input > MAX_CALIB_INPUT) {
 +                continue;
 +            }
 +            expected_output = adc_calculate_output(input, iref);
 +
 +            adc_write_input(qts, adc, index, input);
 +            adc_write_con(qts, adc, CON_MUX(index) | CON_REFSEL | CON_INT |
 +                    CON_EN | CON_CONV);
 +            adc_wait_conv_finished(qts, adc, DEFAULT_CLKDIV);
 +            g_assert_cmphex(adc_read_con(qts, adc), ==,
 +                    CON_REFSEL | CON_MUX(index) | CON_EN);
 +            output = adc_read_data(qts, adc);
 +            g_assert_cmpuint(output, ==, expected_output);
 +
 +            calibrated_voltage = adc_calibrate(output, expected_rv);
 +            g_assert_cmpuint(calibrated_voltage, >, input - MAX_ERROR);
 +            g_assert_cmpuint(calibrated_voltage, <, input + MAX_ERROR);
 +        }
 +
 +        qtest_quit(qts);
 +    }
 +}
 +
 +static void adc_add_test(const char *name, const ADC* wd,
 +        GTestDataFunc fn)
 +{
 +    g_autofree char *full_name = g_strdup_printf("npcm7xx_adc/%s",  name);
 +    qtest_add_data_func(full_name, wd, fn);
 +}
 +#define add_test(name, td) adc_add_test(#name, td, test_##name)
 +
 +int main(int argc, char **argv)
 +{
 +    g_test_init(&argc, &argv, NULL);
 +
 +    add_test(init, &adc);
 +    add_test(convert_internal, &adc);
 +    add_test(convert_external, &adc);
 +    add_test(interrupt, &adc);
 +    add_test(reset, &adc);
 +    add_test(calibrate, &adc);
 +
 +    return g_test_run();
 +}
 diff --git a/hw/adc/meson.build b/hw/adc/meson.build
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/adc/meson.build
 +++ b/hw/adc/meson.build
@@ -1 +1,2 @@
  softmmu_ss.add(when: 'CONFIG_STM32F2XX_ADC', if_true: files('stm32f2xx_adc.c'))
 +softmmu_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx_adc.c'))
 diff --git a/hw/adc/trace-events b/hw/adc/trace-events
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/hw/adc/trace-events
@@ -XXX,XX +XXX,XX @@
 +# See docs/devel/tracing.txt for syntax documentation.
 +
 +# npcm7xx_adc.c
 +npcm7xx_adc_read(const char *id, uint64_t offset, uint32_t value) " %s offset: 0x%04" PRIx64 " value 0x%04" PRIx32
 +npcm7xx_adc_write(const char *id, uint64_t offset, uint32_t value) "%s offset: 0x%04" PRIx64 " value 0x%04" PRIx32
 diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
 index XXXXXXX..XXXXXXX 100644
 --- a/tests/qtest/meson.build
 +++ b/tests/qtest/meson.build
@@ -XXX,XX +XXX,XX @@ qtests_sparc64 = \
    ['prom-env-test', 'boot-serial-test']
  qtests_npcm7xx = \
 -  ['npcm7xx_gpio-test',
 +  ['npcm7xx_adc-test',
 +   'npcm7xx_gpio-test',
     'npcm7xx_rng-test',
     'npcm7xx_timer-test',
     'npcm7xx_watchdog_timer-test']
 --
-.20.1
+.34.1

-[PULL 09/21] ui/cocoa: Update path to docs in build tree
+[PULL 12/24] hw/arm/sbsa-ref: use bsa.h for PPI definitions
-From: Roman Bolshakov <r.bolshakov@yadro.com>
+From: Leif Lindholm <quic_llindhol@quicinc.com>
-QEMU documentation can't be opened if QEMU is run from build tree
+Use the private peripheral interrupt definitions from bsa.h instead of
-because executables are placed in the top of build tree after conversion
+defining them locally. Refactor to use the INTIDs defined there instead
-to meson.
+of the PPI# used previously.
-Signed-off-by: Roman Bolshakov <r.bolshakov@yadro.com>
+Signed-off-by: Leif Lindholm <quic_llindhol@quicinc.com>
-Reported-by: Peter Maydell <peter.maydell@linaro.org>
+Message-id: 20230919090229.188092-4-quic_llindhol@quicinc.com
 Message-id: 20210108213815.64678-1-r.bolshakov@yadro.com
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- ui/cocoa.m | 2 +-
+ hw/arm/sbsa-ref.c | 21 +++++++++------------
-file changed, 1 insertion(+), 1 deletion(-)
+file changed, 9 insertions(+), 12 deletions(-)
-diff --git a/ui/cocoa.m b/ui/cocoa.m
+diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
 index XXXXXXX..XXXXXXX 100644
---- a/ui/cocoa.m
+--- a/hw/arm/sbsa-ref.c
-+++ b/ui/cocoa.m
++++ b/hw/arm/sbsa-ref.c
-@@ -XXX,XX +XXX,XX @@ QemuCocoaView *cocoaView;
+@@ -XXX,XX +XXX,XX @@
- - (void) openDocumentation: (NSString *) filename
+  * ARM SBSA Reference Platform emulation
- {
+  *
-     /* Where to look for local files */
+  * Copyright (c) 2018 Linaro Limited
--    NSString *path_array[] = {@"../share/doc/qemu/", @"../doc/qemu/", @"../docs/"};
++ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
-+    NSString *path_array[] = {@"../share/doc/qemu/", @"../doc/qemu/", @"docs/"};
+  * Written by Hongbo Zhang <hongbo.zhang@linaro.org>
-     NSString *full_file_path;
+  *
+  * This program is free software; you can redistribute it and/or modify it
-     /* iterate thru the possible paths until the file is found */
+@@ -XXX,XX +XXX,XX @@
  #include "exec/hwaddr.h"
  #include "kvm_arm.h"
  #include "hw/arm/boot.h"
 +#include "hw/arm/bsa.h"
  #include "hw/arm/fdt.h"
  #include "hw/arm/smmuv3.h"
  #include "hw/block/flash.h"
@@ -XXX,XX +XXX,XX @@
  #define NUM_SMMU_IRQS   4
  #define NUM_SATA_PORTS  6
 -#define VIRTUAL_PMU_IRQ        7
 -#define ARCH_GIC_MAINT_IRQ     9
 -#define ARCH_TIMER_VIRT_IRQ    11
 -#define ARCH_TIMER_S_EL1_IRQ   13
 -#define ARCH_TIMER_NS_EL1_IRQ  14
 -#define ARCH_TIMER_NS_EL2_IRQ  10
 -#define ARCH_TIMER_NS_EL2_VIRT_IRQ  12
 -
  enum {
      SBSA_FLASH,
      SBSA_MEM,
@@ -XXX,XX +XXX,XX @@ static void create_gic(SBSAMachineState *sms, MemoryRegion *mem)
       */
      for (i = 0; i < smp_cpus; i++) {
          DeviceState *cpudev = DEVICE(qemu_get_cpu(i));
 -        int ppibase = NUM_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS;
 +        int intidbase = NUM_IRQS + i * GIC_INTERNAL;
          int irq;
          /*
           * Mapping from the output timer irq lines from the CPU to the
@@ -XXX,XX +XXX,XX @@ static void create_gic(SBSAMachineState *sms, MemoryRegion *mem)
          for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) {
              qdev_connect_gpio_out(cpudev, irq,
                                    qdev_get_gpio_in(sms->gic,
 -                                                   ppibase + timer_irq[irq]));
 +                                                   intidbase + timer_irq[irq]));
          }
          qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt", 0,
 -                                    qdev_get_gpio_in(sms->gic, ppibase
 +                                    qdev_get_gpio_in(sms->gic,
 +                                                     intidbase
                                                       + ARCH_GIC_MAINT_IRQ));
 +
          qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0,
 -                                    qdev_get_gpio_in(sms->gic, ppibase
 +                                    qdev_get_gpio_in(sms->gic,
 +                                                     intidbase
                                                       + VIRTUAL_PMU_IRQ));
          sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));
 --
-.20.1
+.34.1

-[PULL 02/21] target/arm: enable Small Translation tables in max CPU
+[PULL 13/24] arm/kvm: convert to kvm_set_one_reg
-From: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
+From: Cornelia Huck <cohuck@redhat.com>
-Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
+We can neaten the code by switching to the kvm_set_one_reg function.
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Reviewed-by: Gavin Shan <gshan@redhat.com>
 Signed-off-by: Cornelia Huck <cohuck@redhat.com>
 Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 Message-id: 20231010142453.224369-2-cohuck@redhat.com
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- target/arm/cpu64.c | 1 +
+ target/arm/kvm.c   | 13 +++------
-file changed, 1 insertion(+)
+ target/arm/kvm64.c | 66 +++++++++++++---------------------------------
+files changed, 21 insertions(+), 58 deletions(-)
-diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
 diff --git a/target/arm/kvm.c b/target/arm/kvm.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpu64.c
+--- a/target/arm/kvm.c
-+++ b/target/arm/cpu64.c
++++ b/target/arm/kvm.c
-@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
+@@ -XXX,XX +XXX,XX @@ bool write_list_to_kvmstate(ARMCPU *cpu, int level)
-         t = cpu->isar.id_aa64mmfr2;
+     bool ok = true;
-         t = FIELD_DP64(t, ID_AA64MMFR2, UAO, 1);
-         t = FIELD_DP64(t, ID_AA64MMFR2, CNP, 1); /* TTCNP */
+     for (i = 0; i < cpu->cpreg_array_len; i++) {
-+        t = FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* TTST */
+-        struct kvm_one_reg r;
-         cpu->isar.id_aa64mmfr2 = t;
+         uint64_t regidx = cpu->cpreg_indexes[i];
+         uint32_t v32;
-         /* Replicate the same data to the 32-bit id registers.  */
+         int ret;
@@ -XXX,XX +XXX,XX @@ bool write_list_to_kvmstate(ARMCPU *cpu, int level)
              continue;
          }
 -        r.id = regidx;
          switch (regidx & KVM_REG_SIZE_MASK) {
          case KVM_REG_SIZE_U32:
              v32 = cpu->cpreg_values[i];
 -            r.addr = (uintptr_t)&v32;
 +            ret = kvm_set_one_reg(cs, regidx, &v32);
              break;
          case KVM_REG_SIZE_U64:
 -            r.addr = (uintptr_t)(cpu->cpreg_values + i);
 +            ret = kvm_set_one_reg(cs, regidx, cpu->cpreg_values + i);
              break;
          default:
              g_assert_not_reached();
          }
 -        ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &r);
          if (ret) {
              /* We might fail for "unknown register" and also for
               * "you tried to set a register which is constant with
@@ -XXX,XX +XXX,XX @@ void kvm_arm_get_virtual_time(CPUState *cs)
  void kvm_arm_put_virtual_time(CPUState *cs)
  {
      ARMCPU *cpu = ARM_CPU(cs);
 -    struct kvm_one_reg reg = {
 -        .id = KVM_REG_ARM_TIMER_CNT,
 -        .addr = (uintptr_t)&cpu->kvm_vtime,
 -    };
      int ret;
      if (!cpu->kvm_vtime_dirty) {
          return;
      }
 -    ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
 +    ret = kvm_set_one_reg(cs, KVM_REG_ARM_TIMER_CNT, &cpu->kvm_vtime);
      if (ret) {
          error_report("Failed to set KVM_REG_ARM_TIMER_CNT");
          abort();
 diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/kvm64.c
 +++ b/target/arm/kvm64.c
@@ -XXX,XX +XXX,XX @@ static int kvm_arm_sve_set_vls(CPUState *cs)
  {
      ARMCPU *cpu = ARM_CPU(cs);
      uint64_t vls[KVM_ARM64_SVE_VLS_WORDS] = { cpu->sve_vq.map };
 -    struct kvm_one_reg reg = {
 -        .id = KVM_REG_ARM64_SVE_VLS,
 -        .addr = (uint64_t)&vls[0],
 -    };
      assert(cpu->sve_max_vq <= KVM_ARM64_SVE_VQ_MAX);
 -    return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
 +    return kvm_set_one_reg(cs, KVM_REG_ARM64_SVE_VLS, &vls[0]);
  }
  #define ARM_CPU_ID_MPIDR       3, 0, 0, 0, 5
@@ -XXX,XX +XXX,XX @@ static void kvm_inject_arm_sea(CPUState *c)
  static int kvm_arch_put_fpsimd(CPUState *cs)
  {
      CPUARMState *env = &ARM_CPU(cs)->env;
 -    struct kvm_one_reg reg;
      int i, ret;
      for (i = 0; i < 32; i++) {
          uint64_t *q = aa64_vfp_qreg(env, i);
  #if HOST_BIG_ENDIAN
          uint64_t fp_val[2] = { q[1], q[0] };
 -        reg.addr = (uintptr_t)fp_val;
 +        ret = kvm_set_one_reg(cs, AARCH64_SIMD_CORE_REG(fp_regs.vregs[i]),
 +                                                        fp_val);
  #else
 -        reg.addr = (uintptr_t)q;
 +        ret = kvm_set_one_reg(cs, AARCH64_SIMD_CORE_REG(fp_regs.vregs[i]), q);
  #endif
 -        reg.id = AARCH64_SIMD_CORE_REG(fp_regs.vregs[i]);
 -        ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
          if (ret) {
              return ret;
          }
@@ -XXX,XX +XXX,XX @@ static int kvm_arch_put_sve(CPUState *cs)
      CPUARMState *env = &cpu->env;
      uint64_t tmp[ARM_MAX_VQ * 2];
      uint64_t *r;
 -    struct kvm_one_reg reg;
      int n, ret;
      for (n = 0; n < KVM_ARM64_SVE_NUM_ZREGS; ++n) {
          r = sve_bswap64(tmp, &env->vfp.zregs[n].d[0], cpu->sve_max_vq * 2);
 -        reg.addr = (uintptr_t)r;
 -        reg.id = KVM_REG_ARM64_SVE_ZREG(n, 0);
 -        ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
 +        ret = kvm_set_one_reg(cs, KVM_REG_ARM64_SVE_ZREG(n, 0), r);
          if (ret) {
              return ret;
          }
@@ -XXX,XX +XXX,XX @@ static int kvm_arch_put_sve(CPUState *cs)
      for (n = 0; n < KVM_ARM64_SVE_NUM_PREGS; ++n) {
          r = sve_bswap64(tmp, r = &env->vfp.pregs[n].p[0],
                          DIV_ROUND_UP(cpu->sve_max_vq * 2, 8));
 -        reg.addr = (uintptr_t)r;
 -        reg.id = KVM_REG_ARM64_SVE_PREG(n, 0);
 -        ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
 +        ret = kvm_set_one_reg(cs, KVM_REG_ARM64_SVE_PREG(n, 0), r);
          if (ret) {
              return ret;
          }
@@ -XXX,XX +XXX,XX @@ static int kvm_arch_put_sve(CPUState *cs)
      r = sve_bswap64(tmp, &env->vfp.pregs[FFR_PRED_NUM].p[0],
                      DIV_ROUND_UP(cpu->sve_max_vq * 2, 8));
 -    reg.addr = (uintptr_t)r;
 -    reg.id = KVM_REG_ARM64_SVE_FFR(0);
 -    ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
 +    ret = kvm_set_one_reg(cs, KVM_REG_ARM64_SVE_FFR(0), r);
      if (ret) {
          return ret;
      }
@@ -XXX,XX +XXX,XX @@ static int kvm_arch_put_sve(CPUState *cs)
  int kvm_arch_put_registers(CPUState *cs, int level)
  {
 -    struct kvm_one_reg reg;
      uint64_t val;
      uint32_t fpr;
      int i, ret;
@@ -XXX,XX +XXX,XX @@ int kvm_arch_put_registers(CPUState *cs, int level)
      }
      for (i = 0; i < 31; i++) {
 -        reg.id = AARCH64_CORE_REG(regs.regs[i]);
 -        reg.addr = (uintptr_t) &env->xregs[i];
 -        ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
 +        ret = kvm_set_one_reg(cs, AARCH64_CORE_REG(regs.regs[i]),
 +                              &env->xregs[i]);
          if (ret) {
              return ret;
          }
@@ -XXX,XX +XXX,XX @@ int kvm_arch_put_registers(CPUState *cs, int level)
       */
      aarch64_save_sp(env, 1);
 -    reg.id = AARCH64_CORE_REG(regs.sp);
 -    reg.addr = (uintptr_t) &env->sp_el[0];
 -    ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
 +    ret = kvm_set_one_reg(cs, AARCH64_CORE_REG(regs.sp), &env->sp_el[0]);
      if (ret) {
          return ret;
      }
 -    reg.id = AARCH64_CORE_REG(sp_el1);
 -    reg.addr = (uintptr_t) &env->sp_el[1];
 -    ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
 +    ret = kvm_set_one_reg(cs, AARCH64_CORE_REG(sp_el1), &env->sp_el[1]);
      if (ret) {
          return ret;
      }
@@ -XXX,XX +XXX,XX @@ int kvm_arch_put_registers(CPUState *cs, int level)
      } else {
          val = cpsr_read(env);
      }
 -    reg.id = AARCH64_CORE_REG(regs.pstate);
 -    reg.addr = (uintptr_t) &val;
 -    ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
 +    ret = kvm_set_one_reg(cs, AARCH64_CORE_REG(regs.pstate), &val);
      if (ret) {
          return ret;
      }
 -    reg.id = AARCH64_CORE_REG(regs.pc);
 -    reg.addr = (uintptr_t) &env->pc;
 -    ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
 +    ret = kvm_set_one_reg(cs, AARCH64_CORE_REG(regs.pc), &env->pc);
      if (ret) {
          return ret;
      }
 -    reg.id = AARCH64_CORE_REG(elr_el1);
 -    reg.addr = (uintptr_t) &env->elr_el[1];
 -    ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
 +    ret = kvm_set_one_reg(cs, AARCH64_CORE_REG(elr_el1), &env->elr_el[1]);
      if (ret) {
          return ret;
      }
@@ -XXX,XX +XXX,XX @@ int kvm_arch_put_registers(CPUState *cs, int level)
      /* KVM 0-4 map to QEMU banks 1-5 */
      for (i = 0; i < KVM_NR_SPSR; i++) {
 -        reg.id = AARCH64_CORE_REG(spsr[i]);
 -        reg.addr = (uintptr_t) &env->banked_spsr[i + 1];
 -        ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
 +        ret = kvm_set_one_reg(cs, AARCH64_CORE_REG(spsr[i]),
 +                              &env->banked_spsr[i + 1]);
          if (ret) {
              return ret;
          }
@@ -XXX,XX +XXX,XX @@ int kvm_arch_put_registers(CPUState *cs, int level)
          return ret;
      }
 -    reg.addr = (uintptr_t)(&fpr);
      fpr = vfp_get_fpsr(env);
 -    reg.id = AARCH64_SIMD_CTRL_REG(fp_regs.fpsr);
 -    ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
 +    ret = kvm_set_one_reg(cs, AARCH64_SIMD_CTRL_REG(fp_regs.fpsr), &fpr);
      if (ret) {
          return ret;
      }
 -    reg.addr = (uintptr_t)(&fpr);
      fpr = vfp_get_fpcr(env);
 -    reg.id = AARCH64_SIMD_CTRL_REG(fp_regs.fpcr);
 -    ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
 +    ret = kvm_set_one_reg(cs, AARCH64_SIMD_CTRL_REG(fp_regs.fpcr), &fpr);
      if (ret) {
          return ret;
      }
 --
-.20.1
+.34.1

-[PULL 21/21] ui/cocoa: Fix openFile: deprecation on Big Sur
+[PULL 14/24] arm/kvm: convert to kvm_get_one_reg
-From: Roman Bolshakov <r.bolshakov@yadro.com>
+From: Cornelia Huck <cohuck@redhat.com>
-ui/cocoa.m:1188:44: warning: 'openFile:' is deprecated: first deprecated in macOS 11.0 - Use -[NSWorkspace openURL:] instead.
+We can neaten the code by switching the callers that work on a
-      [-Wdeprecated-declarations]
+CPUstate to the kvm_get_one_reg function.
-        if ([[NSWorkspace sharedWorkspace] openFile: full_file_path] == YES) {
-                                           ^
+Reviewed-by: Gavin Shan <gshan@redhat.com>
-/Library/Developer/CommandLineTools/SDKs/MacOSX.sdk/System/Library/Frameworks/AppKit.framework/Headers/NSWorkspace.h:350:1: note:
+Signed-off-by: Cornelia Huck <cohuck@redhat.com>
-      'openFile:' has been explicitly marked deprecated here
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
-- (BOOL)openFile:(NSString *)fullPath API_DEPRECATED("Use -[NSWorkspace openURL:] instead.", macos(10.0, 11.0));
+Message-id: 20231010142453.224369-3-cohuck@redhat.com
 ^
 Signed-off-by: Roman Bolshakov <r.bolshakov@yadro.com>
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Message-id: 20210102150718.47618-1-r.bolshakov@yadro.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- ui/cocoa.m | 5 ++++-
+ target/arm/kvm.c   | 15 +++---------
-file changed, 4 insertions(+), 1 deletion(-)
+ target/arm/kvm64.c | 57 ++++++++++++----------------------------------
+files changed, 18 insertions(+), 54 deletions(-)
-diff --git a/ui/cocoa.m b/ui/cocoa.m
 diff --git a/target/arm/kvm.c b/target/arm/kvm.c
 index XXXXXXX..XXXXXXX 100644
---- a/ui/cocoa.m
+--- a/target/arm/kvm.c
-+++ b/ui/cocoa.m
++++ b/target/arm/kvm.c
-@@ -XXX,XX +XXX,XX @@ QemuCocoaView *cocoaView;
+@@ -XXX,XX +XXX,XX @@ bool write_kvmstate_to_list(ARMCPU *cpu)
-     /* Where to look for local files */
+     bool ok = true;
-     NSString *path_array[] = {@"../share/doc/qemu/", @"../doc/qemu/", @"docs/"};
-     NSString *full_file_path;
+     for (i = 0; i < cpu->cpreg_array_len; i++) {
-+    NSURL *full_file_url;
+-        struct kvm_one_reg r;
+         uint64_t regidx = cpu->cpreg_indexes[i];
-     /* iterate thru the possible paths until the file is found */
+         uint32_t v32;
-     int index;
+         int ret;
-@@ -XXX,XX +XXX,XX @@ QemuCocoaView *cocoaView;
-         full_file_path = [full_file_path stringByDeletingLastPathComponent];
+-        r.id = regidx;
-         full_file_path = [NSString stringWithFormat: @"%@/%@%@", full_file_path,
+-
-                           path_array[index], filename];
+         switch (regidx & KVM_REG_SIZE_MASK) {
--        if ([[NSWorkspace sharedWorkspace] openFile: full_file_path] == YES) {
+         case KVM_REG_SIZE_U32:
-+        full_file_url = [NSURL fileURLWithPath: full_file_path
+-            r.addr = (uintptr_t)&v32;
-+                                   isDirectory: false];
+-            ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r);
-+        if ([[NSWorkspace sharedWorkspace] openURL: full_file_url] == YES) {
++            ret = kvm_get_one_reg(cs, regidx, &v32);
-             return;
+             if (!ret) {
-         }
+                 cpu->cpreg_values[i] = v32;
              }
              break;
          case KVM_REG_SIZE_U64:
 -            r.addr = (uintptr_t)(cpu->cpreg_values + i);
 -            ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r);
 +            ret = kvm_get_one_reg(cs, regidx, cpu->cpreg_values + i);
              break;
          default:
              g_assert_not_reached();
@@ -XXX,XX +XXX,XX @@ int kvm_arm_sync_mpstate_to_qemu(ARMCPU *cpu)
  void kvm_arm_get_virtual_time(CPUState *cs)
  {
      ARMCPU *cpu = ARM_CPU(cs);
 -    struct kvm_one_reg reg = {
 -        .id = KVM_REG_ARM_TIMER_CNT,
 -        .addr = (uintptr_t)&cpu->kvm_vtime,
 -    };
      int ret;
      if (cpu->kvm_vtime_dirty) {
          return;
      }
 -    ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
 +    ret = kvm_get_one_reg(cs, KVM_REG_ARM_TIMER_CNT, &cpu->kvm_vtime);
      if (ret) {
          error_report("Failed to get KVM_REG_ARM_TIMER_CNT");
          abort();
 diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/kvm64.c
 +++ b/target/arm/kvm64.c
@@ -XXX,XX +XXX,XX @@ int kvm_arch_put_registers(CPUState *cs, int level)
  static int kvm_arch_get_fpsimd(CPUState *cs)
  {
      CPUARMState *env = &ARM_CPU(cs)->env;
 -    struct kvm_one_reg reg;
      int i, ret;
      for (i = 0; i < 32; i++) {
          uint64_t *q = aa64_vfp_qreg(env, i);
 -        reg.id = AARCH64_SIMD_CORE_REG(fp_regs.vregs[i]);
 -        reg.addr = (uintptr_t)q;
 -        ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
 +        ret = kvm_get_one_reg(cs, AARCH64_SIMD_CORE_REG(fp_regs.vregs[i]), q);
          if (ret) {
              return ret;
          } else {
@@ -XXX,XX +XXX,XX @@ static int kvm_arch_get_sve(CPUState *cs)
  {
      ARMCPU *cpu = ARM_CPU(cs);
      CPUARMState *env = &cpu->env;
 -    struct kvm_one_reg reg;
      uint64_t *r;
      int n, ret;
      for (n = 0; n < KVM_ARM64_SVE_NUM_ZREGS; ++n) {
          r = &env->vfp.zregs[n].d[0];
 -        reg.addr = (uintptr_t)r;
 -        reg.id = KVM_REG_ARM64_SVE_ZREG(n, 0);
 -        ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
 +        ret = kvm_get_one_reg(cs, KVM_REG_ARM64_SVE_ZREG(n, 0), r);
          if (ret) {
              return ret;
          }
@@ -XXX,XX +XXX,XX @@ static int kvm_arch_get_sve(CPUState *cs)
      for (n = 0; n < KVM_ARM64_SVE_NUM_PREGS; ++n) {
          r = &env->vfp.pregs[n].p[0];
 -        reg.addr = (uintptr_t)r;
 -        reg.id = KVM_REG_ARM64_SVE_PREG(n, 0);
 -        ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
 +        ret = kvm_get_one_reg(cs, KVM_REG_ARM64_SVE_PREG(n, 0), r);
          if (ret) {
              return ret;
          }
@@ -XXX,XX +XXX,XX @@ static int kvm_arch_get_sve(CPUState *cs)
      }
      r = &env->vfp.pregs[FFR_PRED_NUM].p[0];
 -    reg.addr = (uintptr_t)r;
 -    reg.id = KVM_REG_ARM64_SVE_FFR(0);
 -    ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
 +    ret = kvm_get_one_reg(cs, KVM_REG_ARM64_SVE_FFR(0), r);
      if (ret) {
          return ret;
      }
@@ -XXX,XX +XXX,XX @@ static int kvm_arch_get_sve(CPUState *cs)
  int kvm_arch_get_registers(CPUState *cs)
  {
 -    struct kvm_one_reg reg;
      uint64_t val;
      unsigned int el;
      uint32_t fpr;
@@ -XXX,XX +XXX,XX @@ int kvm_arch_get_registers(CPUState *cs)
      CPUARMState *env = &cpu->env;
      for (i = 0; i < 31; i++) {
 -        reg.id = AARCH64_CORE_REG(regs.regs[i]);
 -        reg.addr = (uintptr_t) &env->xregs[i];
 -        ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
 +        ret = kvm_get_one_reg(cs, AARCH64_CORE_REG(regs.regs[i]),
 +                              &env->xregs[i]);
          if (ret) {
              return ret;
          }
      }
 -    reg.id = AARCH64_CORE_REG(regs.sp);
 -    reg.addr = (uintptr_t) &env->sp_el[0];
 -    ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
 +    ret = kvm_get_one_reg(cs, AARCH64_CORE_REG(regs.sp), &env->sp_el[0]);
      if (ret) {
          return ret;
      }
 -    reg.id = AARCH64_CORE_REG(sp_el1);
 -    reg.addr = (uintptr_t) &env->sp_el[1];
 -    ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
 +    ret = kvm_get_one_reg(cs, AARCH64_CORE_REG(sp_el1), &env->sp_el[1]);
      if (ret) {
          return ret;
      }
 -    reg.id = AARCH64_CORE_REG(regs.pstate);
 -    reg.addr = (uintptr_t) &val;
 -    ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
 +    ret = kvm_get_one_reg(cs, AARCH64_CORE_REG(regs.pstate), &val);
      if (ret) {
          return ret;
      }
@@ -XXX,XX +XXX,XX @@ int kvm_arch_get_registers(CPUState *cs)
       */
      aarch64_restore_sp(env, 1);
 -    reg.id = AARCH64_CORE_REG(regs.pc);
 -    reg.addr = (uintptr_t) &env->pc;
 -    ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
 +    ret = kvm_get_one_reg(cs, AARCH64_CORE_REG(regs.pc), &env->pc);
      if (ret) {
          return ret;
      }
@@ -XXX,XX +XXX,XX @@ int kvm_arch_get_registers(CPUState *cs)
          aarch64_sync_64_to_32(env);
      }
 -    reg.id = AARCH64_CORE_REG(elr_el1);
 -    reg.addr = (uintptr_t) &env->elr_el[1];
 -    ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
 +    ret = kvm_get_one_reg(cs, AARCH64_CORE_REG(elr_el1), &env->elr_el[1]);
      if (ret) {
          return ret;
      }
@@ -XXX,XX +XXX,XX @@ int kvm_arch_get_registers(CPUState *cs)
       * KVM SPSRs 0-4 map to QEMU banks 1-5
       */
      for (i = 0; i < KVM_NR_SPSR; i++) {
 -        reg.id = AARCH64_CORE_REG(spsr[i]);
 -        reg.addr = (uintptr_t) &env->banked_spsr[i + 1];
 -        ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
 +        ret = kvm_get_one_reg(cs, AARCH64_CORE_REG(spsr[i]),
 +                              &env->banked_spsr[i + 1]);
          if (ret) {
              return ret;
          }
@@ -XXX,XX +XXX,XX @@ int kvm_arch_get_registers(CPUState *cs)
          return ret;
      }
 -    reg.addr = (uintptr_t)(&fpr);
 -    reg.id = AARCH64_SIMD_CTRL_REG(fp_regs.fpsr);
 -    ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
 +    ret = kvm_get_one_reg(cs, AARCH64_SIMD_CTRL_REG(fp_regs.fpsr), &fpr);
      if (ret) {
          return ret;
      }
      vfp_set_fpsr(env, fpr);
 -    reg.addr = (uintptr_t)(&fpr);
 -    reg.id = AARCH64_SIMD_CTRL_REG(fp_regs.fpcr);
 -    ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
 +    ret = kvm_get_one_reg(cs, AARCH64_SIMD_CTRL_REG(fp_regs.fpcr), &fpr);
      if (ret) {
          return ret;
      }
 --
-.20.1
+.34.1

-[PULL 20/21] hw/*: Use type casting for SysBusDevice in NPCM7XX
+[PULL 15/24] target/arm: Permit T32 LDM with single register
-From: Hao Wu <wuhaotsh@google.com>
+For the Thumb T32 encoding of LDM, if only a single register is
 specified in the register list this instruction is UNPREDICTABLE,
 with the following choices:
  * instruction UNDEFs
  * instruction is a NOP
  * instruction loads a single register
  * instruction loads an unspecified set of registers
-A device shouldn't access its parent object which is QOM internal.
+Currently we choose to UNDEF (a behaviour chosen in commit
-Instead it should use type cast for this purporse. This patch fixes this
+b222545dbf30 in 2019; previously we treated it as "load the
-issue for all NPCM7XX Devices.
+specified single register").
-Signed-off-by: Hao Wu <wuhaotsh@google.com>
+Unfortunately there is real world code out there (which shipped in at
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+least Android 11, 12 and 13) which incorrectly uses this
-Message-id: 20210108190945.949196-7-wuhaotsh@google.com
+UNPREDICTABLE insn on the assumption that it does a single register
 load, which is (presumably) what it happens to do on real hardware,
 and is also what it does on the equivalent A32 encoding.
 Revert to the pre-4b222545dbf30 behaviour of not UNDEFing
 for this T32 encoding.
 Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1799
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20230927101853.39288-1-peter.maydell@linaro.org
 ---
- hw/arm/npcm7xx_boards.c | 2 +-
+ target/arm/tcg/translate.c | 37 +++++++++++++++++++++++--------------
- hw/mem/npcm7xx_mc.c     | 2 +-
+file changed, 23 insertions(+), 14 deletions(-)
  hw/misc/npcm7xx_clk.c   | 2 +-
  hw/misc/npcm7xx_gcr.c   | 2 +-
  hw/misc/npcm7xx_rng.c   | 2 +-
  hw/nvram/npcm7xx_otp.c  | 2 +-
  hw/ssi/npcm7xx_fiu.c    | 2 +-
 files changed, 7 insertions(+), 7 deletions(-)
-diff --git a/hw/arm/npcm7xx_boards.c b/hw/arm/npcm7xx_boards.c
+diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/npcm7xx_boards.c
+--- a/target/arm/tcg/translate.c
-+++ b/hw/arm/npcm7xx_boards.c
++++ b/target/arm/tcg/translate.c
-@@ -XXX,XX +XXX,XX @@ static NPCM7xxState *npcm7xx_create_soc(MachineState *machine,
+@@ -XXX,XX +XXX,XX @@ static void op_addr_block_post(DisasContext *s, arg_ldst_block *a,
-                                         uint32_t hw_straps)
+     }
  }
 -static bool op_stm(DisasContext *s, arg_ldst_block *a, int min_n)
 +static bool op_stm(DisasContext *s, arg_ldst_block *a)
  {
-     NPCM7xxMachineClass *nmc = NPCM7XX_MACHINE_GET_CLASS(machine);
+     int i, j, n, list, mem_idx;
--    MachineClass *mc = &nmc->parent;
+     bool user = a->u;
-+    MachineClass *mc = MACHINE_CLASS(nmc);
+@@ -XXX,XX +XXX,XX @@ static bool op_stm(DisasContext *s, arg_ldst_block *a, int min_n)
-     Object *obj;
+     list = a->list;
-     if (strcmp(machine->cpu_type, mc->default_cpu_type) != 0) {
+     n = ctpop16(list);
-diff --git a/hw/mem/npcm7xx_mc.c b/hw/mem/npcm7xx_mc.c
+-    if (n < min_n || a->rn == 15) {
-index XXXXXXX..XXXXXXX 100644
++    /*
---- a/hw/mem/npcm7xx_mc.c
++     * This is UNPREDICTABLE for n < 1 in all encodings, and we choose
-+++ b/hw/mem/npcm7xx_mc.c
++     * to UNDEF. In the T32 STM encoding n == 1 is also UNPREDICTABLE,
-@@ -XXX,XX +XXX,XX @@ static void npcm7xx_mc_realize(DeviceState *dev, Error **errp)
++     * but hardware treats it like the A32 version and implements the
++     * single-register-store, and some in-the-wild (buggy) software
-     memory_region_init_io(&s->mmio, OBJECT(s), &npcm7xx_mc_ops, s, "regs",
++     * assumes that, so we don't UNDEF on that case.
-                           NPCM7XX_MC_REGS_SIZE);
++     */
--    sysbus_init_mmio(&s->parent, &s->mmio);
++    if (n < 1 || a->rn == 15) {
-+    sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->mmio);
+         unallocated_encoding(s);
          return true;
      }
@@ -XXX,XX +XXX,XX @@ static bool op_stm(DisasContext *s, arg_ldst_block *a, int min_n)
  static bool trans_STM(DisasContext *s, arg_ldst_block *a)
  {
 -    /* BitCount(list) < 1 is UNPREDICTABLE */
 -    return op_stm(s, a, 1);
 +    return op_stm(s, a);
  }
- static void npcm7xx_mc_class_init(ObjectClass *klass, void *data)
+ static bool trans_STM_t32(DisasContext *s, arg_ldst_block *a)
-diff --git a/hw/misc/npcm7xx_clk.c b/hw/misc/npcm7xx_clk.c
+@@ -XXX,XX +XXX,XX @@ static bool trans_STM_t32(DisasContext *s, arg_ldst_block *a)
-index XXXXXXX..XXXXXXX 100644
+         unallocated_encoding(s);
---- a/hw/misc/npcm7xx_clk.c
+         return true;
-+++ b/hw/misc/npcm7xx_clk.c
+     }
-@@ -XXX,XX +XXX,XX @@ static void npcm7xx_clk_init(Object *obj)
+-    /* BitCount(list) < 2 is UNPREDICTABLE */
+-    return op_stm(s, a, 2);
-     memory_region_init_io(&s->iomem, obj, &npcm7xx_clk_ops, s,
++    return op_stm(s, a);
                            TYPE_NPCM7XX_CLK, 4 * KiB);
 -    sysbus_init_mmio(&s->parent, &s->iomem);
 +    sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem);
  }
- static int npcm7xx_clk_post_load(void *opaque, int version_id)
+-static bool do_ldm(DisasContext *s, arg_ldst_block *a, int min_n)
-diff --git a/hw/misc/npcm7xx_gcr.c b/hw/misc/npcm7xx_gcr.c
++static bool do_ldm(DisasContext *s, arg_ldst_block *a)
-index XXXXXXX..XXXXXXX 100644
+ {
---- a/hw/misc/npcm7xx_gcr.c
+     int i, j, n, list, mem_idx;
-+++ b/hw/misc/npcm7xx_gcr.c
+     bool loaded_base;
-@@ -XXX,XX +XXX,XX @@ static void npcm7xx_gcr_init(Object *obj)
+@@ -XXX,XX +XXX,XX @@ static bool do_ldm(DisasContext *s, arg_ldst_block *a, int min_n)
-     memory_region_init_io(&s->iomem, obj, &npcm7xx_gcr_ops, s,
+     list = a->list;
-                           TYPE_NPCM7XX_GCR, 4 * KiB);
+     n = ctpop16(list);
--    sysbus_init_mmio(&s->parent, &s->iomem);
+-    if (n < min_n || a->rn == 15) {
-+    sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem);
++    /*
 +     * This is UNPREDICTABLE for n < 1 in all encodings, and we choose
 +     * to UNDEF. In the T32 LDM encoding n == 1 is also UNPREDICTABLE,
 +     * but hardware treats it like the A32 version and implements the
 +     * single-register-load, and some in-the-wild (buggy) software
 +     * assumes that, so we don't UNDEF on that case.
 +     */
 +    if (n < 1 || a->rn == 15) {
          unallocated_encoding(s);
          return true;
      }
@@ -XXX,XX +XXX,XX @@ static bool trans_LDM_a32(DisasContext *s, arg_ldst_block *a)
          unallocated_encoding(s);
          return true;
      }
 -    /* BitCount(list) < 1 is UNPREDICTABLE */
 -    return do_ldm(s, a, 1);
 +    return do_ldm(s, a);
  }
- static const VMStateDescription vmstate_npcm7xx_gcr = {
+ static bool trans_LDM_t32(DisasContext *s, arg_ldst_block *a)
-diff --git a/hw/misc/npcm7xx_rng.c b/hw/misc/npcm7xx_rng.c
+@@ -XXX,XX +XXX,XX @@ static bool trans_LDM_t32(DisasContext *s, arg_ldst_block *a)
-index XXXXXXX..XXXXXXX 100644
+         unallocated_encoding(s);
---- a/hw/misc/npcm7xx_rng.c
+         return true;
-+++ b/hw/misc/npcm7xx_rng.c
+     }
-@@ -XXX,XX +XXX,XX @@ static void npcm7xx_rng_init(Object *obj)
+-    /* BitCount(list) < 2 is UNPREDICTABLE */
+-    return do_ldm(s, a, 2);
-     memory_region_init_io(&s->iomem, obj, &npcm7xx_rng_ops, s, "regs",
++    return do_ldm(s, a);
                            NPCM7XX_RNG_REGS_SIZE);
 -    sysbus_init_mmio(&s->parent, &s->iomem);
 +    sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem);
  }
- static const VMStateDescription vmstate_npcm7xx_rng = {
+ static bool trans_LDM_t16(DisasContext *s, arg_ldst_block *a)
 diff --git a/hw/nvram/npcm7xx_otp.c b/hw/nvram/npcm7xx_otp.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/nvram/npcm7xx_otp.c
 +++ b/hw/nvram/npcm7xx_otp.c
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_otp_realize(DeviceState *dev, Error **errp)
  {
-     NPCM7xxOTPClass *oc = NPCM7XX_OTP_GET_CLASS(dev);
+     /* Writeback is conditional on the base register not being loaded.  */
-     NPCM7xxOTPState *s = NPCM7XX_OTP(dev);
+     a->w = !(a->list & (1 << a->rn));
--    SysBusDevice *sbd = &s->parent;
+-    /* BitCount(list) < 1 is UNPREDICTABLE */
-+    SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
+-    return do_ldm(s, a, 1);
++    return do_ldm(s, a);
-     memset(s->array, 0, sizeof(s->array));
+ }
-diff --git a/hw/ssi/npcm7xx_fiu.c b/hw/ssi/npcm7xx_fiu.c
+ static bool trans_CLRM(DisasContext *s, arg_CLRM *a)
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/ssi/npcm7xx_fiu.c
 +++ b/hw/ssi/npcm7xx_fiu.c
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_fiu_hold_reset(Object *obj)
  static void npcm7xx_fiu_realize(DeviceState *dev, Error **errp)
  {
      NPCM7xxFIUState *s = NPCM7XX_FIU(dev);
 -    SysBusDevice *sbd = &s->parent;
 +    SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
      int i;
      if (s->cs_count <= 0) {
 --
-.20.1
+.34.1

-[PULL 14/21] hw/net/lan9118: Add symbolic constants for register offsets
+[PULL 16/24] hw/arm/smmuv3: Update ID register bit field definitions
-The lan9118 code mostly uses symbolic constants for register offsets;
+Update the SMMUv3 ID register bit field definitions to the
-the exceptions are those which the datasheet doesn't give an official
+set in the most recent specification (IHI0700 F.a).
 symbolic name to.
 Add some names for the registers which don't already have them, based
 on the longer names they are given in the memory map.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20210108180401.2263-3-peter.maydell@linaro.org
+Reviewed-by: Mostafa Saleh <smostafa@google.com>
 Reviewed-by: Eric Auger <eric.auger@redhat.com>
 Message-id: 20230914145705.1648377-2-peter.maydell@linaro.org
 ---
- hw/net/lan9118.c | 24 ++++++++++++++++++------
+ hw/arm/smmuv3-internal.h | 38 ++++++++++++++++++++++++++++++++++++++
-file changed, 18 insertions(+), 6 deletions(-)
+file changed, 38 insertions(+)
-diff --git a/hw/net/lan9118.c b/hw/net/lan9118.c
+diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h
 index XXXXXXX..XXXXXXX 100644
---- a/hw/net/lan9118.c
+--- a/hw/arm/smmuv3-internal.h
-+++ b/hw/net/lan9118.c
++++ b/hw/arm/smmuv3-internal.h
-@@ -XXX,XX +XXX,XX @@ do { hw_error("lan9118: error: " fmt , ## __VA_ARGS__);} while (0)
+@@ -XXX,XX +XXX,XX @@ REG32(IDR0,                0x0)
- do { fprintf(stderr, "lan9118: error: " fmt , ## __VA_ARGS__);} while (0)
+     FIELD(IDR0, S1P,         1 , 1)
- #endif
+     FIELD(IDR0, TTF,         2 , 2)
+     FIELD(IDR0, COHACC,      4 , 1)
-+/* The tx and rx fifo ports are a range of aliased 32-bit registers */
++    FIELD(IDR0, BTM,         5 , 1)
-+#define RX_DATA_FIFO_PORT_FIRST 0x00
++    FIELD(IDR0, HTTU,        6 , 2)
-+#define RX_DATA_FIFO_PORT_LAST 0x1f
++    FIELD(IDR0, DORMHINT,    8 , 1)
-+#define TX_DATA_FIFO_PORT_FIRST 0x20
++    FIELD(IDR0, HYP,         9 , 1)
-+#define TX_DATA_FIFO_PORT_LAST 0x3f
++    FIELD(IDR0, ATS,         10, 1)
 +    FIELD(IDR0, NS1ATS,      11, 1)
      FIELD(IDR0, ASID16,      12, 1)
 +    FIELD(IDR0, MSI,         13, 1)
 +    FIELD(IDR0, SEV,         14, 1)
 +    FIELD(IDR0, ATOS,        15, 1)
 +    FIELD(IDR0, PRI,         16, 1)
 +    FIELD(IDR0, VMW,         17, 1)
      FIELD(IDR0, VMID16,      18, 1)
 +    FIELD(IDR0, CD2L,        19, 1)
 +    FIELD(IDR0, VATOS,       20, 1)
      FIELD(IDR0, TTENDIAN,    21, 2)
 +    FIELD(IDR0, ATSRECERR,   23, 1)
      FIELD(IDR0, STALL_MODEL, 24, 2)
      FIELD(IDR0, TERM_MODEL,  26, 1)
      FIELD(IDR0, STLEVEL,     27, 2)
 +    FIELD(IDR0, RME_IMPL,    30, 1)
  REG32(IDR1,                0x4)
      FIELD(IDR1, SIDSIZE,      0 , 6)
 +    FIELD(IDR1, SSIDSIZE,     6 , 5)
 +    FIELD(IDR1, PRIQS,        11, 5)
      FIELD(IDR1, EVENTQS,      16, 5)
      FIELD(IDR1, CMDQS,        21, 5)
 +    FIELD(IDR1, ATTR_PERMS_OVR, 26, 1)
 +    FIELD(IDR1, ATTR_TYPES_OVR, 27, 1)
 +    FIELD(IDR1, REL,          28, 1)
 +    FIELD(IDR1, QUEUES_PRESET, 29, 1)
 +    FIELD(IDR1, TABLES_PRESET, 30, 1)
 +    FIELD(IDR1, ECMDQ,        31, 1)
  #define SMMU_IDR1_SIDSIZE 16
  #define SMMU_CMDQS   19
  #define SMMU_EVENTQS 19
  REG32(IDR2,                0x8)
 +     FIELD(IDR2, BA_VATOS, 0, 10)
 +
-+#define RX_STATUS_FIFO_PORT 0x40
+ REG32(IDR3,                0xc)
-+#define RX_STATUS_FIFO_PEEK 0x44
+      FIELD(IDR3, HAD,         2, 1);
-+#define TX_STATUS_FIFO_PORT 0x48
++     FIELD(IDR3, PBHA,        3, 1);
-+#define TX_STATUS_FIFO_PEEK 0x4c
++     FIELD(IDR3, XNX,         4, 1);
 +     FIELD(IDR3, PPS,         5, 1);
 +     FIELD(IDR3, MPAM,        7, 1);
 +     FIELD(IDR3, FWB,         8, 1);
 +     FIELD(IDR3, STT,         9, 1);
       FIELD(IDR3, RIL,        10, 1);
       FIELD(IDR3, BBML,       11, 2);
 +     FIELD(IDR3, E0PD,       13, 1);
 +     FIELD(IDR3, PTWNNC,     14, 1);
 +     FIELD(IDR3, DPT,        15, 1);
 +
- #define CSR_ID_REV      0x50
+ REG32(IDR4,                0x10)
- #define CSR_IRQ_CFG     0x54
++
- #define CSR_INT_STS     0x58
+ REG32(IDR5,                0x14)
-@@ -XXX,XX +XXX,XX @@ static void lan9118_writel(void *opaque, hwaddr offset,
+      FIELD(IDR5, OAS,         0, 3);
-     offset &= 0xff;
+      FIELD(IDR5, GRAN4K,      4, 1);
+      FIELD(IDR5, GRAN16K,     5, 1);
-     //DPRINTF("Write reg 0x%02x = 0x%08x\n", (int)offset, val);
+      FIELD(IDR5, GRAN64K,     6, 1);
--    if (offset >= 0x20 && offset < 0x40) {
++     FIELD(IDR5, VAX,        10, 2);
-+    if (offset >= TX_DATA_FIFO_PORT_FIRST &&
++     FIELD(IDR5, STALL_MAX,  16, 16);
-+        offset <= TX_DATA_FIFO_PORT_LAST) {
-         /* TX FIFO */
+ #define SMMU_IDR5_OAS 4
-         tx_fifo_push(s, val);
          return;
@@ -XXX,XX +XXX,XX @@ static uint64_t lan9118_readl(void *opaque, hwaddr offset,
      lan9118_state *s = (lan9118_state *)opaque;
      //DPRINTF("Read reg 0x%02x\n", (int)offset);
 -    if (offset < 0x20) {
 +    if (offset <= RX_DATA_FIFO_PORT_LAST) {
          /* RX FIFO */
          return rx_fifo_pop(s);
      }
      switch (offset) {
 -    case 0x40:
 +    case RX_STATUS_FIFO_PORT:
          return rx_status_fifo_pop(s);
 -    case 0x44:
 +    case RX_STATUS_FIFO_PEEK:
          return s->rx_status_fifo[s->rx_status_fifo_head];
 -    case 0x48:
 +    case TX_STATUS_FIFO_PORT:
          return tx_status_fifo_pop(s);
 -    case 0x4c:
 +    case TX_STATUS_FIFO_PEEK:
          return s->tx_status_fifo[s->tx_status_fifo_head];
      case CSR_ID_REV:
          return 0x01180001;
 --
-.20.1
+.34.1

-New patch
+[PULL 17/24] hw/arm/smmuv3: Sort ID register setting into field order
+In smmuv3_init_regs() when we set the various bits in the ID
+registers, we do this almost in order of the fields in the
+registers, but not quite. Move the initialization of
+SMMU_IDR3.RIL and SMMU_IDR5.OAS into their correct places.
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Mostafa Saleh <smostafa@google.com>
+Reviewed-by: Eric Auger <eric.auger@redhat.com>
+Message-id: 20230914145705.1648377-3-peter.maydell@linaro.org
+---
+ hw/arm/smmuv3.c | 4 ++--
+file changed, 2 insertions(+), 2 deletions(-)
+diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/smmuv3.c
++++ b/hw/arm/smmuv3.c
+@@ -XXX,XX +XXX,XX @@ static void smmuv3_init_regs(SMMUv3State *s)
+     s->idr[1] = FIELD_DP32(s->idr[1], IDR1, EVENTQS, SMMU_EVENTQS);
+     s->idr[1] = FIELD_DP32(s->idr[1], IDR1, CMDQS,   SMMU_CMDQS);
+-    s->idr[3] = FIELD_DP32(s->idr[3], IDR3, RIL, 1);
+     s->idr[3] = FIELD_DP32(s->idr[3], IDR3, HAD, 1);
++    s->idr[3] = FIELD_DP32(s->idr[3], IDR3, RIL, 1);
+     s->idr[3] = FIELD_DP32(s->idr[3], IDR3, BBML, 2);
++    s->idr[5] = FIELD_DP32(s->idr[5], IDR5, OAS, SMMU_IDR5_OAS); /* 44 bits */
+     /* 4K, 16K and 64K granule support */
+     s->idr[5] = FIELD_DP32(s->idr[5], IDR5, GRAN4K, 1);
+     s->idr[5] = FIELD_DP32(s->idr[5], IDR5, GRAN16K, 1);
+     s->idr[5] = FIELD_DP32(s->idr[5], IDR5, GRAN64K, 1);
+-    s->idr[5] = FIELD_DP32(s->idr[5], IDR5, OAS, SMMU_IDR5_OAS); /* 44 bits */
+     s->cmdq.base = deposit64(s->cmdq.base, 0, 5, SMMU_CMDQS);
+     s->cmdq.prod = 0;
+--
+.34.1

-New patch
+[PULL 18/24] hw/arm/smmuv3: Advertise SMMUv3.1-XNX feature
+The SMMUv3.1-XNX feature is mandatory for an SMMUv3.1 if S2P is
+supported, so we should theoretically have implemented it as part of
+the recent S2P work.  Fortunately, for us the implementation is a
+no-op.
+This feature is about interpretation of the stage 2 page table
+descriptor XN bits, which control execute permissions.
+For QEMU, the permission bits passed to an IOMMU (via MemTxAttrs and
+IOMMUAccessFlags) only indicate read and write; we do not distinguish
+data reads from instruction reads outside the CPU proper.  In the
+SMMU architecture's terms, our interconnect between the client device
+and the SMMU doesn't have the ability to convey the INST attribute,
+and we therefore use the default value of "data" for this attribute.
+We also do not support the bits in the Stream Table Entry that can
+override the on-the-bus transaction attribute permissions (we do not
+set SMMU_IDR1.ATTR_PERMS_OVR=1).
+These two things together mean that for our implementation, it never
+has to deal with transactions with the INST attribute, and so it can
+correctly ignore the XN bits entirely.  So we already implement
+FEAT_XNX's "XN field is now 2 bits, not 1" behaviour to the extent
+that we need to.
+Advertise the presence of the feature in SMMU_IDR3.XNX.
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Mostafa Saleh <smostafa@google.com>
+Reviewed-by: Eric Auger <eric.auger@redhat.com>
+Message-id: 20230914145705.1648377-4-peter.maydell@linaro.org
+---
+ hw/arm/smmuv3.c | 4 ++++
+file changed, 4 insertions(+)
+diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/smmuv3.c
++++ b/hw/arm/smmuv3.c
+@@ -XXX,XX +XXX,XX @@ static void smmuv3_init_regs(SMMUv3State *s)
+     s->idr[1] = FIELD_DP32(s->idr[1], IDR1, CMDQS,   SMMU_CMDQS);
+     s->idr[3] = FIELD_DP32(s->idr[3], IDR3, HAD, 1);
++    if (FIELD_EX32(s->idr[0], IDR0, S2P)) {
++        /* XNX is a stage-2-specific feature */
++        s->idr[3] = FIELD_DP32(s->idr[3], IDR3, XNX, 1);
++    }
+     s->idr[3] = FIELD_DP32(s->idr[3], IDR3, RIL, 1);
+     s->idr[3] = FIELD_DP32(s->idr[3], IDR3, BBML, 2);
+--
+.34.1

-[PULL 11/21] docs: Build and install all the docs in a single manual
+[PULL 19/24] target/arm: Implement FEAT_HPMN0
-When we first converted our documentation to Sphinx, we split it into
+FEAT_HPMN0 is a small feature which defines that it is valid for
-multiple manuals (system, interop, tools, etc), which are all built
+MDCR_EL2.HPMN to be set to 0, meaning "no PMU event counters provided
-separately.  The primary driver for this was wanting to be able to
+to an EL1 guest" (previously this setting was reserved). QEMU's
-avoid shipping the 'devel' manual to end-users.  However, this is
+implementation almost gets HPMN == 0 right, but we need to fix
-working against the grain of the way Sphinx wants to be used and
+one check in pmevcntr_is_64_bit(). That is enough for us to
-causes some annoyances:
+advertise the feature in the 'max' CPU.
  * Cross-references between documents become much harder or
    possibly impossible
  * There is no single index to the whole documentation
  * Within one manual there's no links or table-of-contents info
    that lets you easily navigate to the others
  * The devel manual doesn't get published on the QEMU website
    (it would be nice to able to refer to it there)
-Merely hiding our developer documentation from end users seems like
+(We don't need to make the behaviour conditional on feature
-it's not enough benefit for these costs.  Combine all the
+presence, because the FEAT_HPMN0 behaviour is within the range
-documentation into a single manual (the same way that the readthedocs
+of permitted UNPREDICTABLE behaviour for a non-FEAT_HPMN0
-site builds it) and install the whole thing.  The previous manual
+implementation.)
 divisions remain as the new top level sections in the manual.
  * The per-manual conf.py files are no longer needed
  * The man_pages[] specifications previously in each per-manual
    conf.py move to the top level conf.py
  * docs/meson.build logic is simplified as we now only need to run
    Sphinx once for the HTML and then once for the manpages5B
  * The old index.html.in that produced the top-level page with
    links to each manual is no longer needed
 Unfortunately this means that we now have to build the HTML
 documentation into docs/manual in the build tree rather than directly
 into docs/; otherwise it is too awkward to ensure we install only the
 built manual and not also the dependency info, stamp file, etc.  The
 manual still ends up in the same place in the final installed
 directory, but anybody who was consulting documentation from within
 the build tree will have to adjust where they're looking.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20210108161416.21129-3-peter.maydell@linaro.org
+Message-id: 20230921185445.3339214-1-peter.maydell@linaro.org
 ---
- docs/conf.py         | 46 ++++++++++++++++++++++++++++++-
+ docs/system/arm/emulation.rst | 1 +
- docs/devel/conf.py   | 15 -----------
+ target/arm/helper.c           | 2 +-
- docs/index.html.in   | 17 ------------
+ target/arm/tcg/cpu32.c        | 4 ++++
- docs/interop/conf.py | 28 -------------------
+ target/arm/tcg/cpu64.c        | 1 +
- docs/meson.build     | 64 +++++++++++++++++---------------------------
+files changed, 7 insertions(+), 1 deletion(-)
  docs/specs/conf.py   | 16 -----------
  docs/system/conf.py  | 28 -------------------
  docs/tools/conf.py   | 37 -------------------------
  docs/user/conf.py    | 15 -----------
 files changed, 70 insertions(+), 196 deletions(-)
  delete mode 100644 docs/devel/conf.py
  delete mode 100644 docs/index.html.in
  delete mode 100644 docs/interop/conf.py
  delete mode 100644 docs/specs/conf.py
  delete mode 100644 docs/system/conf.py
  delete mode 100644 docs/tools/conf.py
  delete mode 100644 docs/user/conf.py
-diff --git a/docs/conf.py b/docs/conf.py
+diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
 index XXXXXXX..XXXXXXX 100644
---- a/docs/conf.py
+--- a/docs/system/arm/emulation.rst
-+++ b/docs/conf.py
++++ b/docs/system/arm/emulation.rst
-@@ -XXX,XX +XXX,XX @@ latex_documents = [
+@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
+ - FEAT_HCX (Support for the HCRX_EL2 register)
- # -- Options for manual page output ---------------------------------------
+ - FEAT_HPDS (Hierarchical permission disables)
- # Individual manual/conf.py can override this to create man pages
+ - FEAT_HPDS2 (Translation table page-based hardware attributes)
--man_pages = []
++- FEAT_HPMN0 (Setting of MDCR_EL2.HPMN to zero)
-+man_pages = [
+ - FEAT_I8MM (AArch64 Int8 matrix multiplication instructions)
-+    ('interop/qemu-ga', 'qemu-ga',
+ - FEAT_IDST (ID space trap handling)
-+     'QEMU Guest Agent',
+ - FEAT_IESB (Implicit error synchronization event)
-+     ['Michael Roth <mdroth@linux.vnet.ibm.com>'], 8),
+diff --git a/target/arm/helper.c b/target/arm/helper.c
 +    ('interop/qemu-ga-ref', 'qemu-ga-ref',
 +     'QEMU Guest Agent Protocol Reference',
 +     [], 7),
 +    ('interop/qemu-qmp-ref', 'qemu-qmp-ref',
 +     'QEMU QMP Reference Manual',
 +     [], 7),
 +    ('interop/qemu-storage-daemon-qmp-ref', 'qemu-storage-daemon-qmp-ref',
 +     'QEMU Storage Daemon QMP Reference Manual',
 +     [], 7),
 +    ('system/qemu-manpage', 'qemu',
 +     'QEMU User Documentation',
 +     ['Fabrice Bellard'], 1),
 +    ('system/qemu-block-drivers', 'qemu-block-drivers',
 +     'QEMU block drivers reference',
 +     ['Fabrice Bellard and the QEMU Project developers'], 7),
 +    ('system/qemu-cpu-models', 'qemu-cpu-models',
 +     'QEMU CPU Models',
 +     ['The QEMU Project developers'], 7),
 +    ('tools/qemu-img', 'qemu-img',
 +     'QEMU disk image utility',
 +     ['Fabrice Bellard'], 1),
 +    ('tools/qemu-nbd', 'qemu-nbd',
 +     'QEMU Disk Network Block Device Server',
 +     ['Anthony Liguori <anthony@codemonkey.ws>'], 8),
 +    ('tools/qemu-pr-helper', 'qemu-pr-helper',
 +     'QEMU persistent reservation helper',
 +     [], 8),
 +    ('tools/qemu-storage-daemon', 'qemu-storage-daemon',
 +     'QEMU storage daemon',
 +     [], 1),
 +    ('tools/qemu-trace-stap', 'qemu-trace-stap',
 +     'QEMU SystemTap trace tool',
 +     [], 1),
 +    ('tools/virtfs-proxy-helper', 'virtfs-proxy-helper',
 +     'QEMU 9p virtfs proxy filesystem helper',
 +     ['M. Mohan Kumar'], 1),
 +    ('tools/virtiofsd', 'virtiofsd',
 +     'QEMU virtio-fs shared file system daemon',
 +     ['Stefan Hajnoczi <stefanha@redhat.com>',
 +      'Masayoshi Mizuma <m.mizuma@jp.fujitsu.com>'], 1),
 +]
  # -- Options for Texinfo output -------------------------------------------
 diff --git a/docs/devel/conf.py b/docs/devel/conf.py
 deleted file mode 100644
 index XXXXXXX..XXXXXXX
 --- a/docs/devel/conf.py
 +++ /dev/null
@@ -XXX,XX +XXX,XX @@
 -# -*- coding: utf-8 -*-
 -#
 -# QEMU documentation build configuration file for the 'devel' manual.
 -#
 -# This includes the top level conf file and then makes any necessary tweaks.
 -import sys
 -import os
 -
 -qemu_docdir = os.path.abspath("..")
 -parent_config = os.path.join(qemu_docdir, "conf.py")
 -exec(compile(open(parent_config, "rb").read(), parent_config, 'exec'))
 -
 -# This slightly misuses the 'description', but is the best way to get
 -# the manual title to appear in the sidebar.
 -html_theme_options['description'] = u'Developer''s Guide'
 diff --git a/docs/index.html.in b/docs/index.html.in
 deleted file mode 100644
 index XXXXXXX..XXXXXXX
 --- a/docs/index.html.in
 +++ /dev/null
@@ -XXX,XX +XXX,XX @@
 -<!DOCTYPE html>
 -<html lang="en">
 -    <head>
 -        <meta charset="UTF-8">
 -        <title>QEMU @VERSION@ Documentation</title>
 -    </head>
 -    <body>
 -        <h1>QEMU @VERSION@ Documentation</h1>
 -        <ul>
 -            <li><a href="system/index.html">System Emulation User's Guide</a></li>
 -            <li><a href="user/index.html">User Mode Emulation User's Guide</a></li>
 -            <li><a href="tools/index.html">Tools Guide</a></li>
 -            <li><a href="interop/index.html">System Emulation Management and Interoperability Guide</a></li>
 -            <li><a href="specs/index.html">System Emulation Guest Hardware Specifications</a></li>
 -        </ul>
 -    </body>
 -</html>
 diff --git a/docs/interop/conf.py b/docs/interop/conf.py
 deleted file mode 100644
 index XXXXXXX..XXXXXXX
 --- a/docs/interop/conf.py
 +++ /dev/null
@@ -XXX,XX +XXX,XX @@
 -# -*- coding: utf-8 -*-
 -#
 -# QEMU documentation build configuration file for the 'interop' manual.
 -#
 -# This includes the top level conf file and then makes any necessary tweaks.
 -import sys
 -import os
 -
 -qemu_docdir = os.path.abspath("..")
 -parent_config = os.path.join(qemu_docdir, "conf.py")
 -exec(compile(open(parent_config, "rb").read(), parent_config, 'exec'))
 -
 -# This slightly misuses the 'description', but is the best way to get
 -# the manual title to appear in the sidebar.
 -html_theme_options['description'] = u'System Emulation Management and Interoperability Guide'
 -
 -# One entry per manual page. List of tuples
 -# (source start file, name, description, authors, manual section).
 -man_pages = [
 -    ('qemu-ga', 'qemu-ga', u'QEMU Guest Agent',
 -     ['Michael Roth <mdroth@linux.vnet.ibm.com>'], 8),
 -    ('qemu-ga-ref', 'qemu-ga-ref', 'QEMU Guest Agent Protocol Reference',
 -     [], 7),
 -    ('qemu-qmp-ref', 'qemu-qmp-ref', 'QEMU QMP Reference Manual',
 -     [], 7),
 -    ('qemu-storage-daemon-qmp-ref', 'qemu-storage-daemon-qmp-ref',
 -     'QEMU Storage Daemon QMP Reference Manual', [], 7),
 -]
 diff --git a/docs/meson.build b/docs/meson.build
 index XXXXXXX..XXXXXXX 100644
---- a/docs/meson.build
+--- a/target/arm/helper.c
-+++ b/docs/meson.build
++++ b/target/arm/helper.c
-@@ -XXX,XX +XXX,XX @@ if build_docs
+@@ -XXX,XX +XXX,XX @@ static bool pmevcntr_is_64_bit(CPUARMState *env, int counter)
-                           meson.source_root() / 'docs/sphinx/qmp_lexer.py',
+         bool hlp = env->cp15.mdcr_el2 & MDCR_HLP;
-                           qapi_gen_depends ]
+         int hpmn = env->cp15.mdcr_el2 & MDCR_HPMN;
--  configure_file(output: 'index.html',
+-        if (hpmn != 0 && counter >= hpmn) {
--                 input: files('index.html.in'),
++        if (counter >= hpmn) {
--                 configuration: {'VERSION': meson.project_version()},
+             return hlp;
--                 install_dir: qemu_docdir)
+         }
--  manuals = [ 'devel', 'interop', 'tools', 'specs', 'system', 'user' ]
+     }
-   man_pages = {
+diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c
--    'interop' : {
+index XXXXXXX..XXXXXXX 100644
-         'qemu-ga.8': (have_tools ? 'man8' : ''),
+--- a/target/arm/tcg/cpu32.c
-         'qemu-ga-ref.7': 'man7',
++++ b/target/arm/tcg/cpu32.c
-         'qemu-qmp-ref.7': 'man7',
+@@ -XXX,XX +XXX,XX @@ void aa32_max_features(ARMCPU *cpu)
-         'qemu-storage-daemon-qmp-ref.7': (have_tools ? 'man7' : ''),
+     t = FIELD_DP32(t, ID_DFR0, COPSDBG, 9);       /* FEAT_Debugv8p4 */
--    },
+     t = FIELD_DP32(t, ID_DFR0, PERFMON, 6);       /* FEAT_PMUv3p5 */
--    'tools': {
+     cpu->isar.id_dfr0 = t;
          'qemu-img.1': (have_tools ? 'man1' : ''),
          'qemu-nbd.8': (have_tools ? 'man8' : ''),
          'qemu-pr-helper.8': (have_tools ? 'man8' : ''),
@@ -XXX,XX +XXX,XX @@ if build_docs
          'qemu-trace-stap.1': (config_host.has_key('CONFIG_TRACE_SYSTEMTAP') ? 'man1' : ''),
          'virtfs-proxy-helper.1': (have_virtfs_proxy_helper ? 'man1' : ''),
          'virtiofsd.1': (have_virtiofsd ? 'man1' : ''),
 -    },
 -    'system': {
          'qemu.1': 'man1',
          'qemu-block-drivers.7': 'man7',
          'qemu-cpu-models.7': 'man7'
 -    },
    }
    sphinxdocs = []
    sphinxmans = []
 -  foreach manual : manuals
 -    private_dir = meson.current_build_dir() / (manual + '.p')
 -    output_dir = meson.current_build_dir() / manual
 -    input_dir = meson.current_source_dir() / manual
 -    this_manual = custom_target(manual + ' manual',
 +  private_dir = meson.current_build_dir() / 'manual.p'
 +  output_dir = meson.current_build_dir() / 'manual'
 +  input_dir = meson.current_source_dir()
 +
-+  this_manual = custom_target('QEMU manual',
++    t = cpu->isar.id_dfr1;
-                 build_by_default: build_docs,
++    t = FIELD_DP32(t, ID_DFR1, HPMN0, 1);         /* FEAT_HPMN0 */
--                output: [manual + '.stamp'],
++    cpu->isar.id_dfr1 = t;
--                input: [files('conf.py'), files(manual / 'conf.py')],
+ }
--                depfile: manual + '.d',
-+                output: 'docs.stamp',
+ /* CPU models. These are not needed for the AArch64 linux-user build. */
-+                input: files('conf.py'),
+diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
-+                depfile: 'docs.d',
+index XXXXXXX..XXXXXXX 100644
-                 depend_files: sphinx_extn_depends,
+--- a/target/arm/tcg/cpu64.c
-                 command: [SPHINX_ARGS, '-Ddepfile=@DEPFILE@',
++++ b/target/arm/tcg/cpu64.c
-                           '-Ddepfile_stamp=@OUTPUT0@',
+@@ -XXX,XX +XXX,XX @@ void aarch64_max_tcg_initfn(Object *obj)
-                           '-b', 'html', '-d', private_dir,
+     t = cpu->isar.id_aa64dfr0;
-                           input_dir, output_dir])
+     t = FIELD_DP64(t, ID_AA64DFR0, DEBUGVER, 9);  /* FEAT_Debugv8p4 */
--    sphinxdocs += this_manual
+     t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 6);    /* FEAT_PMUv3p5 */
--    if build_docs and manual != 'devel'
++    t = FIELD_DP64(t, ID_AA64DFR0, HPMN0, 1);     /* FEAT_HPMN0 */
--      install_subdir(output_dir, install_dir: qemu_docdir)
+     cpu->isar.id_aa64dfr0 = t;
--    endif
-+  sphinxdocs += this_manual
+     t = cpu->isar.id_aa64smfr0;
 +  install_subdir(output_dir, install_dir: qemu_docdir, strip_directory: true)
 -    these_man_pages = []
 -    install_dirs = []
 -    foreach page, section : man_pages.get(manual, {})
 -      these_man_pages += page
 -      install_dirs += section == '' ? false : get_option('mandir') / section
 -    endforeach
 -    if these_man_pages.length() > 0
 -      sphinxmans += custom_target(manual + ' man pages',
 -                         build_by_default: build_docs,
 -                         output: these_man_pages,
 -                         input: this_manual,
 -                         install: build_docs,
 -                         install_dir: install_dirs,
 -                         command: [SPHINX_ARGS, '-b', 'man', '-d', private_dir,
 -                                   input_dir, meson.current_build_dir()])
 -    endif
 +  these_man_pages = []
 +  install_dirs = []
 +  foreach page, section : man_pages
 +    these_man_pages += page
 +    install_dirs += section == '' ? false : get_option('mandir') / section
    endforeach
 +
 +  sphinxmans += custom_target('QEMU man pages',
 +                              build_by_default: build_docs,
 +                              output: these_man_pages,
 +                              input: this_manual,
 +                              install: build_docs,
 +                              install_dir: install_dirs,
 +                              command: [SPHINX_ARGS, '-b', 'man', '-d', private_dir,
 +                                        input_dir, meson.current_build_dir()])
 +
    alias_target('sphinxdocs', sphinxdocs)
    alias_target('html', sphinxdocs)
    alias_target('man', sphinxmans)
 diff --git a/docs/specs/conf.py b/docs/specs/conf.py
 deleted file mode 100644
 index XXXXXXX..XXXXXXX
 --- a/docs/specs/conf.py
 +++ /dev/null
@@ -XXX,XX +XXX,XX @@
 -# -*- coding: utf-8 -*-
 -#
 -# QEMU documentation build configuration file for the 'specs' manual.
 -#
 -# This includes the top level conf file and then makes any necessary tweaks.
 -import sys
 -import os
 -
 -qemu_docdir = os.path.abspath("..")
 -parent_config = os.path.join(qemu_docdir, "conf.py")
 -exec(compile(open(parent_config, "rb").read(), parent_config, 'exec'))
 -
 -# This slightly misuses the 'description', but is the best way to get
 -# the manual title to appear in the sidebar.
 -html_theme_options['description'] = \
 -    u'System Emulation Guest Hardware Specifications'
 diff --git a/docs/system/conf.py b/docs/system/conf.py
 deleted file mode 100644
 index XXXXXXX..XXXXXXX
 --- a/docs/system/conf.py
 +++ /dev/null
@@ -XXX,XX +XXX,XX @@
 -# -*- coding: utf-8 -*-
 -#
 -# QEMU documentation build configuration file for the 'system' manual.
 -#
 -# This includes the top level conf file and then makes any necessary tweaks.
 -import sys
 -import os
 -
 -qemu_docdir = os.path.abspath("..")
 -parent_config = os.path.join(qemu_docdir, "conf.py")
 -exec(compile(open(parent_config, "rb").read(), parent_config, 'exec'))
 -
 -# This slightly misuses the 'description', but is the best way to get
 -# the manual title to appear in the sidebar.
 -html_theme_options['description'] = u'System Emulation User''s Guide'
 -
 -# One entry per manual page. List of tuples
 -# (source start file, name, description, authors, manual section).
 -man_pages = [
 -    ('qemu-manpage', 'qemu', u'QEMU User Documentation',
 -     ['Fabrice Bellard'], 1),
 -    ('qemu-block-drivers', 'qemu-block-drivers',
 -     u'QEMU block drivers reference',
 -     ['Fabrice Bellard and the QEMU Project developers'], 7),
 -    ('qemu-cpu-models', 'qemu-cpu-models',
 -     u'QEMU CPU Models',
 -     ['The QEMU Project developers'], 7)
 -]
 diff --git a/docs/tools/conf.py b/docs/tools/conf.py
 deleted file mode 100644
 index XXXXXXX..XXXXXXX
 --- a/docs/tools/conf.py
 +++ /dev/null
@@ -XXX,XX +XXX,XX @@
 -# -*- coding: utf-8 -*-
 -#
 -# QEMU documentation build configuration file for the 'tools' manual.
 -#
 -# This includes the top level conf file and then makes any necessary tweaks.
 -import sys
 -import os
 -
 -qemu_docdir = os.path.abspath("..")
 -parent_config = os.path.join(qemu_docdir, "conf.py")
 -exec(compile(open(parent_config, "rb").read(), parent_config, 'exec'))
 -
 -# This slightly misuses the 'description', but is the best way to get
 -# the manual title to appear in the sidebar.
 -html_theme_options['description'] = \
 -    u'Tools Guide'
 -
 -# One entry per manual page. List of tuples
 -# (source start file, name, description, authors, manual section).
 -man_pages = [
 -    ('qemu-img', 'qemu-img', u'QEMU disk image utility',
 -     ['Fabrice Bellard'], 1),
 -    ('qemu-storage-daemon', 'qemu-storage-daemon', u'QEMU storage daemon',
 -     [], 1),
 -    ('qemu-nbd', 'qemu-nbd', u'QEMU Disk Network Block Device Server',
 -     ['Anthony Liguori <anthony@codemonkey.ws>'], 8),
 -    ('qemu-pr-helper', 'qemu-pr-helper', 'QEMU persistent reservation helper',
 -     [], 8),
 -    ('qemu-trace-stap', 'qemu-trace-stap', u'QEMU SystemTap trace tool',
 -     [], 1),
 -    ('virtfs-proxy-helper', 'virtfs-proxy-helper',
 -     u'QEMU 9p virtfs proxy filesystem helper',
 -     ['M. Mohan Kumar'], 1),
 -    ('virtiofsd', 'virtiofsd', u'QEMU virtio-fs shared file system daemon',
 -     ['Stefan Hajnoczi <stefanha@redhat.com>',
 -      'Masayoshi Mizuma <m.mizuma@jp.fujitsu.com>'], 1),
 -]
 diff --git a/docs/user/conf.py b/docs/user/conf.py
 deleted file mode 100644
 index XXXXXXX..XXXXXXX
 --- a/docs/user/conf.py
 +++ /dev/null
@@ -XXX,XX +XXX,XX @@
 -# -*- coding: utf-8 -*-
 -#
 -# QEMU documentation build configuration file for the 'user' manual.
 -#
 -# This includes the top level conf file and then makes any necessary tweaks.
 -import sys
 -import os
 -
 -qemu_docdir = os.path.abspath("..")
 -parent_config = os.path.join(qemu_docdir, "conf.py")
 -exec(compile(open(parent_config, "rb").read(), parent_config, 'exec'))
 -
 -# This slightly misuses the 'description', but is the best way to get
 -# the manual title to appear in the sidebar.
 -html_theme_options['description'] = u'User Mode Emulation User''s Guide'
 --
-.20.1
+.34.1

-[PULL 10/21] docs: Add qemu-storage-daemon(1) manpage to meson.build
+[PULL 20/24] target/arm/kvm64.c: Remove unused include
-In commit 1982e1602d15 we added a new qemu-storage-daemon(1) manpage.
+The include of hw/arm/virt.h in kvm64.c is unnecessary and also a
-At the moment new manpages have to be listed both in the conf.py for
+layering violation since the generic KVM code shouldn't need to know
-Sphinx and also in docs/meson.build for Meson. We forgot the second
+anything about board-specifics.  The include line is an accidental
-of those -- correct the omission.
+leftover from commit 15613357ba53a4763, where we cleaned up the code
 to not depend on virt board internals but forgot to also remove the
 now-redundant include line.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
+Reviewed-by: Gavin Shan <gshan@redhat.com>
-Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
-Message-id: 20210108161416.21129-2-peter.maydell@linaro.org
+Message-id: 20230925110429.3917202-1-peter.maydell@linaro.org
 ---
- docs/meson.build | 1 +
+ target/arm/kvm64.c | 1 -
-file changed, 1 insertion(+)
+file changed, 1 deletion(-)
-diff --git a/docs/meson.build b/docs/meson.build
+diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
 index XXXXXXX..XXXXXXX 100644
---- a/docs/meson.build
+--- a/target/arm/kvm64.c
-+++ b/docs/meson.build
++++ b/target/arm/kvm64.c
-@@ -XXX,XX +XXX,XX @@ if build_docs
+@@ -XXX,XX +XXX,XX @@
-         'qemu-img.1': (have_tools ? 'man1' : ''),
+ #include "internals.h"
-         'qemu-nbd.8': (have_tools ? 'man8' : ''),
+ #include "hw/acpi/acpi.h"
-         'qemu-pr-helper.8': (have_tools ? 'man8' : ''),
+ #include "hw/acpi/ghes.h"
-+        'qemu-storage-daemon.1': (have_tools ? 'man1' : ''),
+-#include "hw/arm/virt.h"
-         'qemu-trace-stap.1': (config_host.has_key('CONFIG_TRACE_SYSTEMTAP') ? 'man1' : ''),
-         'virtfs-proxy-helper.1': (have_virtfs_proxy_helper ? 'man1' : ''),
+ static bool have_guest_debug;
-         'virtiofsd.1': (have_virtiofsd ? 'man1' : ''),
 --
-.20.1
+.34.1

-[PULL 12/21] target/arm: Don't decode insns in the XScale/iWMMXt space as cp insns
+[PULL 21/24] target/arm/common-semi-target.h: Remove unnecessary boot.h include
-In commit cd8be50e58f63413c0 we converted the A32 coprocessor
+The hw/arm/boot.h include in common-semi-target.h is not actually
-insns to decodetree. This accidentally broke XScale/iWMMXt insns,
+needed, and it's a bit odd because it pulls a hw/arm header into a
-because it moved the handling of "cp insns which are handled
+target/arm file.
 by looking up the cp register in the hashtable" from after the
 call to the legacy disas_xscale_insn() decode to before it,
 with the result that all XScale/iWMMXt insns now UNDEF.
-Update valid_cp() so that it knows that on XScale cp 0 and 1
+This include was originally needed because the semihosting code used
-are not standard coprocessor instructions; this will cause
+the arm_boot_info struct to get the base address of the RAM in system
-the decodetree trans_ functions to ignore them, so that
+emulation, to use in a (bad) heuristic for the return values for the
-execution will correctly get through to the legacy decode again.
+SYS_HEAPINFO semihosting call.  We've since overhauled how we
 calculate the HEAPINFO values in system emulation, and the code no
 longer uses the arm_boot_info struct.
-Cc: qemu-stable@nongnu.org
+Remove the now-redundant include line, and instead directly include
-Reported-by: Guenter Roeck <linux@roeck-us.net>
+the cpu-qom.h header that we were previously getting via boot.h.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Tested-by: Guenter Roeck <linux@roeck-us.net>
+Message-id: 20230925112219.3919261-1-peter.maydell@linaro.org
 Message-id: 20210108195157.32067-1-peter.maydell@linaro.org
 ---
- target/arm/translate.c | 7 +++++++
+ target/arm/common-semi-target.h | 4 +---
-file changed, 7 insertions(+)
+file changed, 1 insertion(+), 3 deletions(-)
-diff --git a/target/arm/translate.c b/target/arm/translate.c
+diff --git a/target/arm/common-semi-target.h b/target/arm/common-semi-target.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate.c
+--- a/target/arm/common-semi-target.h
-+++ b/target/arm/translate.c
++++ b/target/arm/common-semi-target.h
-@@ -XXX,XX +XXX,XX @@ static bool valid_cp(DisasContext *s, int cp)
+@@ -XXX,XX +XXX,XX @@
-      * only cp14 and cp15 are valid, and other values aren't considered
+ #ifndef TARGET_ARM_COMMON_SEMI_TARGET_H
-      * to be in the coprocessor-instruction space at all. v8M still
+ #define TARGET_ARM_COMMON_SEMI_TARGET_H
-      * permits coprocessors 0..7.
-+     * For XScale, we must not decode the XScale cp0, cp1 space as
+-#ifndef CONFIG_USER_ONLY
-+     * a standard coprocessor insn, because we want to fall through to
+-#include "hw/arm/boot.h"
-+     * the legacy disas_xscale_insn() decoder after decodetree is done.
+-#endif
-      */
++#include "target/arm/cpu-qom.h"
-+    if (arm_dc_feature(s, ARM_FEATURE_XSCALE) && (cp == 0 || cp == 1)) {
-+        return false;
+ static inline target_ulong common_semi_arg(CPUState *cs, int argno)
-+    }
+ {
 +
      if (arm_dc_feature(s, ARM_FEATURE_V8) &&
          !arm_dc_feature(s, ARM_FEATURE_M)) {
          return cp >= 14;
 --
-.20.1
+.34.1

-[PULL 19/21] hw/misc: Add QTest for NPCM7XX PWM Module
+[PULL 22/24] target/arm/arm-powerctl: Correctly init CPUs when powered on to lower EL
-From: Hao Wu <wuhaotsh@google.com>
+The code for powering on a CPU in arm-powerctl.c has two separate
+use cases:
-We add a qtest for the PWM in the previous patch. It proves it works as
+ * emulation of a real hardware power controller
-expected.
+ * emulation of firmware interfaces (primarily PSCI) with
+   CPU on/off APIs
-Reviewed-by: Havard Skinnemoen <hskinnemoen@google.com>
-Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
+For the first case, we only need to reset the CPU and set its
-Signed-off-by: Hao Wu <wuhaotsh@google.com>
+starting PC and X0.  For the second case, because we're emulating the
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+firmware we need to ensure that it's in the state that the firmware
-Message-id: 20210108190945.949196-6-wuhaotsh@google.com
+provides.  In particular, when we reset to a lower EL than the
 highest one we are emulating, we need to put the CPU into a state
 that permits correct running at that lower EL.  We already do a
 little of this in arm-powerctl.c (for instance we set SCR_HCE to
 enable the HVC insn) but we don't do enough of it.  This means that
 in the case where we are emulating EL3 but also providing emulated
 PSCI the guest will crash when a secondary core tries to use a
 feature that needs an SCR_EL3 bit to be set, such as MTE or PAuth.
 The hw/arm/boot.c code also has to support this "start guest code in
 an EL that's lower than the highest emulated EL" case in order to do
 direct guest kernel booting; it has all the necessary initialization
 code to set the SCR_EL3 bits.  Pull the relevant boot.c code out into
 a separate function so we can share it between there and
 arm-powerctl.c.
 This refactoring has a few code changes that look like they
 might be behaviour changes but aren't:
  * if info->secure_boot is false and info->secure_board_setup is
    true, then the old code would start the first CPU in Hyp
    mode but without changing SCR.NS and NSACR.{CP11,CP10}.
    This was wrong behaviour because there's no such thing
    as Secure Hyp mode. The new code will leave the CPU in SVC.
    (There is no board which sets secure_boot to false and
    secure_board_setup to true, so this isn't a behaviour
    change for any of our boards.)
  * we don't explicitly clear SCR.NS when arm-powerctl.c
    does a CPU-on to EL3. This was a no-op because CPU reset
    will reset to NS == 0.
 And some real behaviour changes:
  * we no longer set HCR_EL2.RW when booting into EL2: the guest
    can and should do that themselves before dropping into their
    EL1 code. (arm-powerctl and boot did this differently; I
    opted to use the logic from arm-powerctl, which only sets
    HCR_EL2.RW when it's directly starting the guest in EL1,
    because it's more correct, and I don't expect guests to be
    accidentally depending on our having set the RW bit for them.)
  * if we are booting a CPU into AArch32 Secure SVC then we won't
    set SCR.HCE any more. This affects only the vexpress-a15 and
    raspi2b machine types. Guests booting in this case will either:
     - be able to set SCR.HCE themselves as part of moving from
       Secure SVC into NS Hyp mode
     - will move from Secure SVC to NS SVC, and won't care about
       behaviour of the HVC insn
     - will stay in Secure SVC, and won't care about HVC
  * on an arm-powerctl CPU-on we will now set the SCR bits for
    pauth/mte/sve/sme/hcx/fgt features
 The first two of these are very minor and I don't expect guest
 code to trip over them, so I didn't judge it worth convoluting
 the code in an attempt to keep exactly the same boot.c behaviour.
 The third change fixes issue 1899.
 Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1899
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20230926155619.4028618-1-peter.maydell@linaro.org
 ---
- tests/qtest/npcm7xx_pwm-test.c | 490 +++++++++++++++++++++++++++++++++
+ target/arm/cpu.h          | 22 +++++++++
- tests/qtest/meson.build        |   1 +
+ hw/arm/boot.c             | 95 ++++++++++-----------------------------
-files changed, 491 insertions(+)
+ target/arm/arm-powerctl.c | 53 +---------------------
- create mode 100644 tests/qtest/npcm7xx_pwm-test.c
+ target/arm/cpu.c          | 95 +++++++++++++++++++++++++++++++++++++++
+files changed, 141 insertions(+), 124 deletions(-)
-diff --git a/tests/qtest/npcm7xx_pwm-test.c b/tests/qtest/npcm7xx_pwm-test.c
-new file mode 100644
+diff --git a/target/arm/cpu.h b/target/arm/cpu.h
-index XXXXXXX..XXXXXXX
+index XXXXXXX..XXXXXXX 100644
---- /dev/null
+--- a/target/arm/cpu.h
-+++ b/tests/qtest/npcm7xx_pwm-test.c
++++ b/target/arm/cpu.h
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ int arm_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs,
-+/*
+ int arm_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs,
-+ * QTests for Nuvoton NPCM7xx PWM Modules.
+                              int cpuid, DumpState *s);
 +/**
 + * arm_emulate_firmware_reset: Emulate firmware CPU reset handling
 + * @cpu: CPU (which must have been freshly reset)
 + * @target_el: exception level to put the CPU into
 + * @secure: whether to put the CPU in secure state
 + *
-+ * Copyright 2020 Google LLC
++ * When QEMU is directly running a guest kernel at a lower level than
 + * EL3 it implicitly emulates some aspects of the guest firmware.
 + * This includes that on reset we need to configure the parts of the
 + * CPU corresponding to EL3 so that the real guest code can run at its
 + * lower exception level. This function does that post-reset CPU setup,
 + * for when we do direct boot of a guest kernel, and for when we
 + * emulate PSCI and similar firmware interfaces starting a CPU at a
 + * lower exception level.
 + *
-+ * This program is free software; you can redistribute it and/or modify it
++ * @target_el must be an EL implemented by the CPU between 1 and 3.
-+ * under the terms of the GNU General Public License as published by the
++ * We do not support dropping into a Secure EL other than 3.
 + * Free Software Foundation; either version 2 of the License, or
 + * (at your option) any later version.
 + *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * It is the responsibility of the caller to call arm_rebuild_hflags().
 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
 + * for more details.
 + */
-+
++void arm_emulate_firmware_reset(CPUState *cpustate, int target_el);
-+#include "qemu/osdep.h"
++
-+#include "qemu/bitops.h"
+ #ifdef TARGET_AARCH64
-+#include "libqos/libqtest.h"
+ int aarch64_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
-+#include "qapi/qmp/qdict.h"
+ int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
-+#include "qapi/qmp/qnum.h"
+diff --git a/hw/arm/boot.c b/hw/arm/boot.c
-+
+index XXXXXXX..XXXXXXX 100644
-+#define REF_HZ          25000000
+--- a/hw/arm/boot.c
-+
++++ b/hw/arm/boot.c
-+/* Register field definitions. */
+@@ -XXX,XX +XXX,XX @@ static void do_cpu_reset(void *opaque)
-+#define CH_EN           BIT(0)
-+#define CH_INV          BIT(2)
+             cpu_set_pc(cs, entry);
-+#define CH_MOD          BIT(3)
+         } else {
-+
+-            /* If we are booting Linux then we need to check whether we are
-+/* Registers shared between all PWMs in a module */
+-             * booting into secure or non-secure state and adjust the state
-+#define PPR             0x00
+-             * accordingly.  Out of reset, ARM is defined to be in secure state
-+#define CSR             0x04
+-             * (SCR.NS = 0), we change that here if non-secure boot has been
-+#define PCR             0x08
+-             * requested.
-+#define PIER            0x3c
++            /*
-+#define PIIR            0x40
++             * If we are booting Linux then we might need to do so at:
-+
++             *  - AArch64 NS EL2 or NS EL1
-+/* CLK module related */
++             *  - AArch32 Secure SVC (EL3)
-+#define CLK_BA          0xf0801000
++             *  - AArch32 NS Hyp (EL2)
-+#define CLKSEL          0x04
++             *  - AArch32 NS SVC (EL1)
-+#define CLKDIV1         0x08
++             * Configure the CPU in the way boot firmware would do to
-+#define CLKDIV2         0x2c
++             * drop us down to the appropriate level.
-+#define PLLCON0         0x0c
+              */
-+#define PLLCON1         0x10
+-            if (arm_feature(env, ARM_FEATURE_EL3)) {
-+#define PLL_INDV(rv)    extract32((rv), 0, 6)
+-                /* AArch64 is defined to come out of reset into EL3 if enabled.
-+#define PLL_FBDV(rv)    extract32((rv), 16, 12)
+-                 * If we are booting Linux then we need to adjust our EL as
-+#define PLL_OTDV1(rv)   extract32((rv), 8, 3)
+-                 * Linux expects us to be in EL2 or EL1.  AArch32 resets into
-+#define PLL_OTDV2(rv)   extract32((rv), 13, 3)
+-                 * SVC, which Linux expects, so no privilege/exception level to
-+#define APB3CKDIV(rv)   extract32((rv), 28, 2)
+-                 * adjust.
-+#define CLK2CKDIV(rv)   extract32((rv), 0, 1)
+-                 */
-+#define CLK4CKDIV(rv)   extract32((rv), 26, 2)
+-                if (env->aarch64) {
-+#define CPUCKSEL(rv)    extract32((rv), 0, 2)
+-                    env->cp15.scr_el3 |= SCR_RW;
-+
+-                    if (arm_feature(env, ARM_FEATURE_EL2)) {
-+#define MAX_DUTY        1000000
+-                        env->cp15.hcr_el2 |= HCR_RW;
-+
+-                        env->pstate = PSTATE_MODE_EL2h;
-+typedef struct PWMModule {
+-                    } else {
-+    int irq;
+-                        env->pstate = PSTATE_MODE_EL1h;
-+    uint64_t base_addr;
+-                    }
-+} PWMModule;
+-                    if (cpu_isar_feature(aa64_pauth, cpu)) {
-+
+-                        env->cp15.scr_el3 |= SCR_API | SCR_APK;
-+typedef struct PWM {
+-                    }
-+    uint32_t cnr_offset;
+-                    if (cpu_isar_feature(aa64_mte, cpu)) {
-+    uint32_t cmr_offset;
+-                        env->cp15.scr_el3 |= SCR_ATA;
-+    uint32_t pdr_offset;
+-                    }
-+    uint32_t pwdr_offset;
+-                    if (cpu_isar_feature(aa64_sve, cpu)) {
-+} PWM;
+-                        env->cp15.cptr_el[3] |= R_CPTR_EL3_EZ_MASK;
-+
+-                        env->vfp.zcr_el[3] = 0xf;
-+typedef struct TestData {
+-                    }
-+    const PWMModule *module;
+-                    if (cpu_isar_feature(aa64_sme, cpu)) {
-+    const PWM *pwm;
+-                        env->cp15.cptr_el[3] |= R_CPTR_EL3_ESM_MASK;
-+} TestData;
+-                        env->cp15.scr_el3 |= SCR_ENTP2;
-+
+-                        env->vfp.smcr_el[3] = 0xf;
-+static const PWMModule pwm_module_list[] = {
+-                    }
-+    {
+-                    if (cpu_isar_feature(aa64_hcx, cpu)) {
-+        .irq        = 93,
+-                        env->cp15.scr_el3 |= SCR_HXEN;
-+        .base_addr  = 0xf0103000
+-                    }
-+    },
+-                    if (cpu_isar_feature(aa64_fgt, cpu)) {
-+    {
+-                        env->cp15.scr_el3 |= SCR_FGTEN;
-+        .irq        = 94,
+-                    }
-+        .base_addr  = 0xf0104000
++            int target_el = arm_feature(env, ARM_FEATURE_EL2) ? 2 : 1;
-+    }
-+};
+-                    /* AArch64 kernels never boot in secure mode */
-+
+-                    assert(!info->secure_boot);
-+static const PWM pwm_list[] = {
+-                    /* This hook is only supported for AArch32 currently:
-+    {
+-                     * bootloader_aarch64[] will not call the hook, and
-+        .cnr_offset     = 0x0c,
+-                     * the code above has already dropped us into EL2 or EL1.
-+        .cmr_offset     = 0x10,
+-                     */
-+        .pdr_offset     = 0x14,
+-                    assert(!info->secure_board_setup);
-+        .pwdr_offset    = 0x44,
+-                }
-+    },
+-
-+    {
+-                if (arm_feature(env, ARM_FEATURE_EL2)) {
-+        .cnr_offset     = 0x18,
+-                    /* If we have EL2 then Linux expects the HVC insn to work */
-+        .cmr_offset     = 0x1c,
+-                    env->cp15.scr_el3 |= SCR_HCE;
-+        .pdr_offset     = 0x20,
+-                }
-+        .pwdr_offset    = 0x48,
+-
-+    },
+-                /* Set to non-secure if not a secure boot */
-+    {
+-                if (!info->secure_boot &&
-+        .cnr_offset     = 0x24,
+-                    (cs != first_cpu || !info->secure_board_setup)) {
-+        .cmr_offset     = 0x28,
+-                    /* Linux expects non-secure state */
-+        .pdr_offset     = 0x2c,
+-                    env->cp15.scr_el3 |= SCR_NS;
-+        .pwdr_offset    = 0x4c,
+-                    /* Set NSACR.{CP11,CP10} so NS can access the FPU */
-+    },
+-                    env->cp15.nsacr |= 3 << 10;
-+    {
+-                }
-+        .cnr_offset     = 0x30,
+-            }
-+        .cmr_offset     = 0x34,
+-
-+        .pdr_offset     = 0x38,
+-            if (!env->aarch64 && !info->secure_boot &&
-+        .pwdr_offset    = 0x50,
+-                arm_feature(env, ARM_FEATURE_EL2)) {
-+    },
++            if (env->aarch64) {
-+};
+                 /*
-+
+-                 * This is an AArch32 boot not to Secure state, and
-+static const int ppr_base[] = { 0, 0, 8, 8 };
+-                 * we have Hyp mode available, so boot the kernel into
-+static const int csr_base[] = { 0, 4, 8, 12 };
+-                 * Hyp mode. This is not how the CPU comes out of reset,
-+static const int pcr_base[] = { 0, 8, 12, 16 };
+-                 * so we need to manually put it there.
-+
++                 * AArch64 kernels never boot in secure mode, and we don't
-+static const uint32_t ppr_list[] = {
++                 * support the secure_board_setup hook for AArch64.
-+    0,
+                  */
-+    1,
+-                cpsr_write(env, ARM_CPU_MODE_HYP, CPSR_M, CPSRWriteRaw);
-+    10,
++                assert(!info->secure_boot);
-+    100,
++                assert(!info->secure_board_setup);
-+    255, /* Max possible value. */
++            } else {
-+};
++                if (arm_feature(env, ARM_FEATURE_EL3) &&
-+
++                    (info->secure_boot ||
-+static const uint32_t csr_list[] = {
++                     (info->secure_board_setup && cs == first_cpu))) {
-+    0,
++                    /* Start this CPU in Secure SVC */
-+    1,
++                    target_el = 3;
-+    2,
++                }
-+    3,
+             }
-+    4, /* Max possible value. */
-+};
++            arm_emulate_firmware_reset(cs, target_el);
 +
-+static const uint32_t cnr_list[] = {
+             if (cs == first_cpu) {
-+    0,
+                 AddressSpace *as = arm_boot_address_space(cpu, info);
-+    1,
-+    50,
+diff --git a/target/arm/arm-powerctl.c b/target/arm/arm-powerctl.c
-+    100,
+index XXXXXXX..XXXXXXX 100644
-+    150,
+--- a/target/arm/arm-powerctl.c
-+    200,
++++ b/target/arm/arm-powerctl.c
-+    1000,
+@@ -XXX,XX +XXX,XX @@ static void arm_set_cpu_on_async_work(CPUState *target_cpu_state,
-+    10000,
-+    65535, /* Max possible value. */
+     /* Initialize the cpu we are turning on */
-+};
+     cpu_reset(target_cpu_state);
-+
++    arm_emulate_firmware_reset(target_cpu_state, info->target_el);
-+static const uint32_t cmr_list[] = {
+     target_cpu_state->halted = 0;
-+    0,
-+    1,
+-    if (info->target_aa64) {
-+    10,
+-        if ((info->target_el < 3) && arm_feature(&target_cpu->env,
-+    50,
+-                                                 ARM_FEATURE_EL3)) {
-+    100,
+-            /*
-+    150,
+-             * As target mode is AArch64, we need to set lower
-+    200,
+-             * exception level (the requested level 2) to AArch64
-+    1000,
+-             */
-+    10000,
+-            target_cpu->env.cp15.scr_el3 |= SCR_RW;
-+    65535, /* Max possible value. */
+-        }
-+};
+-
-+
+-        if ((info->target_el < 2) && arm_feature(&target_cpu->env,
-+/* Returns the index of the PWM module. */
+-                                                 ARM_FEATURE_EL2)) {
-+static int pwm_module_index(const PWMModule *module)
+-            /*
 -             * As target mode is AArch64, we need to set lower
 -             * exception level (the requested level 1) to AArch64
 -             */
 -            target_cpu->env.cp15.hcr_el2 |= HCR_RW;
 -        }
 -
 -        target_cpu->env.pstate = aarch64_pstate_mode(info->target_el, true);
 -    } else {
 -        /* We are requested to boot in AArch32 mode */
 -        static const uint32_t mode_for_el[] = { 0,
 -                                                ARM_CPU_MODE_SVC,
 -                                                ARM_CPU_MODE_HYP,
 -                                                ARM_CPU_MODE_SVC };
 -
 -        cpsr_write(&target_cpu->env, mode_for_el[info->target_el], CPSR_M,
 -                   CPSRWriteRaw);
 -    }
 -
 -    if (info->target_el == 3) {
 -        /* Processor is in secure mode */
 -        target_cpu->env.cp15.scr_el3 &= ~SCR_NS;
 -    } else {
 -        /* Processor is not in secure mode */
 -        target_cpu->env.cp15.scr_el3 |= SCR_NS;
 -
 -        /* Set NSACR.{CP11,CP10} so NS can access the FPU */
 -        target_cpu->env.cp15.nsacr |= 3 << 10;
 -
 -        /*
 -         * If QEMU is providing the equivalent of EL3 firmware, then we need
 -         * to make sure a CPU targeting EL2 comes out of reset with a
 -         * functional HVC insn.
 -         */
 -        if (arm_feature(&target_cpu->env, ARM_FEATURE_EL3)
 -            && info->target_el == 2) {
 -            target_cpu->env.cp15.scr_el3 |= SCR_HCE;
 -        }
 -    }
 -
      /* We check if the started CPU is now at the correct level */
      assert(info->target_el == arm_current_el(&target_cpu->env));
 diff --git a/target/arm/cpu.c b/target/arm/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu.c
 +++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset_hold(Object *obj)
      }
  }
 +void arm_emulate_firmware_reset(CPUState *cpustate, int target_el)
 +{
-+    ptrdiff_t diff = module - pwm_module_list;
++    ARMCPU *cpu = ARM_CPU(cpustate);
-+
++    CPUARMState *env = &cpu->env;
-+    g_assert_true(diff >= 0 && diff < ARRAY_SIZE(pwm_module_list));
++    bool have_el3 = arm_feature(env, ARM_FEATURE_EL3);
-+
++    bool have_el2 = arm_feature(env, ARM_FEATURE_EL2);
-+    return diff;
++
-+}
++    /*
-+
++     * Check we have the EL we're aiming for. If that is the
-+/* Returns the index of the PWM entry. */
++     * highest implemented EL, then cpu_reset has already done
-+static int pwm_index(const PWM *pwm)
++     * all the work.
-+{
++     */
-+    ptrdiff_t diff = pwm - pwm_list;
++    switch (target_el) {
-+
++    case 3:
-+    g_assert_true(diff >= 0 && diff < ARRAY_SIZE(pwm_list));
++        assert(have_el3);
-+
++        return;
-+    return diff;
++    case 2:
-+}
++        assert(have_el2);
-+
++        if (!have_el3) {
-+static uint64_t pwm_qom_get(QTestState *qts, const char *path, const char *name)
++            return;
-+{
++        }
 +    QDict *response;
 +
 +    g_test_message("Getting properties %s from %s", name, path);
 +    response = qtest_qmp(qts, "{ 'execute': 'qom-get',"
 +            " 'arguments': { 'path': %s, 'property': %s}}",
 +            path, name);
 +    /* The qom set message returns successfully. */
 +    g_assert_true(qdict_haskey(response, "return"));
 +    return qnum_get_uint(qobject_to(QNum, qdict_get(response, "return")));
 +}
 +
 +static uint64_t pwm_get_freq(QTestState *qts, int module_index, int pwm_index)
 +{
 +    char path[100];
 +    char name[100];
 +
 +    sprintf(path, "/machine/soc/pwm[%d]", module_index);
 +    sprintf(name, "freq[%d]", pwm_index);
 +
 +    return pwm_qom_get(qts, path, name);
 +}
 +
 +static uint64_t pwm_get_duty(QTestState *qts, int module_index, int pwm_index)
 +{
 +    char path[100];
 +    char name[100];
 +
 +    sprintf(path, "/machine/soc/pwm[%d]", module_index);
 +    sprintf(name, "duty[%d]", pwm_index);
 +
 +    return pwm_qom_get(qts, path, name);
 +}
 +
 +static uint32_t get_pll(uint32_t con)
 +{
 +    return REF_HZ * PLL_FBDV(con) / (PLL_INDV(con) * PLL_OTDV1(con)
 +            * PLL_OTDV2(con));
 +}
 +
 +static uint64_t read_pclk(QTestState *qts)
 +{
 +    uint64_t freq = REF_HZ;
 +    uint32_t clksel = qtest_readl(qts, CLK_BA + CLKSEL);
 +    uint32_t pllcon;
 +    uint32_t clkdiv1 = qtest_readl(qts, CLK_BA + CLKDIV1);
 +    uint32_t clkdiv2 = qtest_readl(qts, CLK_BA + CLKDIV2);
 +
 +    switch (CPUCKSEL(clksel)) {
 +    case 0:
 +        pllcon = qtest_readl(qts, CLK_BA + PLLCON0);
 +        freq = get_pll(pllcon);
 +        break;
 +    case 1:
-+        pllcon = qtest_readl(qts, CLK_BA + PLLCON1);
++        if (!have_el3 && !have_el2) {
-+        freq = get_pll(pllcon);
++            return;
-+        break;
++        }
 +    case 2:
 +        break;
 +    case 3:
 +        break;
 +    default:
 +        g_assert_not_reached();
 +    }
 +
-+    freq >>= (CLK2CKDIV(clkdiv1) + CLK4CKDIV(clkdiv1) + APB3CKDIV(clkdiv2));
++    if (have_el3) {
-+
++        /*
-+    return freq;
++         * Set the EL3 state so code can run at EL2. This should match
-+}
++         * the requirements set by Linux in its booting spec.
-+
++         */
-+static uint32_t pwm_selector(uint32_t csr)
++        if (env->aarch64) {
-+{
++            env->cp15.scr_el3 |= SCR_RW;
-+    switch (csr) {
++            if (cpu_isar_feature(aa64_pauth, cpu)) {
-+    case 0:
++                env->cp15.scr_el3 |= SCR_API | SCR_APK;
-+        return 2;
++            }
-+    case 1:
++            if (cpu_isar_feature(aa64_mte, cpu)) {
-+        return 4;
++                env->cp15.scr_el3 |= SCR_ATA;
-+    case 2:
++            }
-+        return 8;
++            if (cpu_isar_feature(aa64_sve, cpu)) {
-+    case 3:
++                env->cp15.cptr_el[3] |= R_CPTR_EL3_EZ_MASK;
-+        return 16;
++                env->vfp.zcr_el[3] = 0xf;
-+    case 4:
++            }
-+        return 1;
++            if (cpu_isar_feature(aa64_sme, cpu)) {
-+    default:
++                env->cp15.cptr_el[3] |= R_CPTR_EL3_ESM_MASK;
-+        g_assert_not_reached();
++                env->cp15.scr_el3 |= SCR_ENTP2;
 +                env->vfp.smcr_el[3] = 0xf;
 +            }
 +            if (cpu_isar_feature(aa64_hcx, cpu)) {
 +                env->cp15.scr_el3 |= SCR_HXEN;
 +            }
 +            if (cpu_isar_feature(aa64_fgt, cpu)) {
 +                env->cp15.scr_el3 |= SCR_FGTEN;
 +            }
 +        }
 +
 +        if (target_el == 2) {
 +            /* If the guest is at EL2 then Linux expects the HVC insn to work */
 +            env->cp15.scr_el3 |= SCR_HCE;
 +        }
 +
 +        /* Put CPU into non-secure state */
 +        env->cp15.scr_el3 |= SCR_NS;
 +        /* Set NSACR.{CP11,CP10} so NS can access the FPU */
 +        env->cp15.nsacr |= 3 << 10;
 +    }
 +
 +    if (have_el2 && target_el < 2) {
 +        /* Set EL2 state so code can run at EL1. */
 +        if (env->aarch64) {
 +            env->cp15.hcr_el2 |= HCR_RW;
 +        }
 +    }
 +
 +    /* Set the CPU to the desired state */
 +    if (env->aarch64) {
 +        env->pstate = aarch64_pstate_mode(target_el, true);
 +    } else {
 +        static const uint32_t mode_for_el[] = {
 +            0,
 +            ARM_CPU_MODE_SVC,
 +            ARM_CPU_MODE_HYP,
 +            ARM_CPU_MODE_SVC,
 +        };
 +
 +        cpsr_write(env, mode_for_el[target_el], CPSR_M, CPSRWriteRaw);
 +    }
 +}
 +
-+static uint64_t pwm_compute_freq(QTestState *qts, uint32_t ppr, uint32_t csr,
++
-+        uint32_t cnr)
+ #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
-+{
-+    return read_pclk(qts) / ((ppr + 1) * pwm_selector(csr) * (cnr + 1));
+ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx,
 +}
 +
 +static uint64_t pwm_compute_duty(uint32_t cnr, uint32_t cmr, bool inverted)
 +{
 +    uint64_t duty;
 +
 +    if (cnr == 0) {
 +        /* PWM is stopped. */
 +        duty = 0;
 +    } else if (cmr >= cnr) {
 +        duty = MAX_DUTY;
 +    } else {
 +        duty = MAX_DUTY * (cmr + 1) / (cnr + 1);
 +    }
 +
 +    if (inverted) {
 +        duty = MAX_DUTY - duty;
 +    }
 +
 +    return duty;
 +}
 +
 +static uint32_t pwm_read(QTestState *qts, const TestData *td, unsigned offset)
 +{
 +    return qtest_readl(qts, td->module->base_addr + offset);
 +}
 +
 +static void pwm_write(QTestState *qts, const TestData *td, unsigned offset,
 +        uint32_t value)
 +{
 +    qtest_writel(qts, td->module->base_addr + offset, value);
 +}
 +
 +static uint32_t pwm_read_ppr(QTestState *qts, const TestData *td)
 +{
 +    return extract32(pwm_read(qts, td, PPR), ppr_base[pwm_index(td->pwm)], 8);
 +}
 +
 +static void pwm_write_ppr(QTestState *qts, const TestData *td, uint32_t value)
 +{
 +    pwm_write(qts, td, PPR, value << ppr_base[pwm_index(td->pwm)]);
 +}
 +
 +static uint32_t pwm_read_csr(QTestState *qts, const TestData *td)
 +{
 +    return extract32(pwm_read(qts, td, CSR), csr_base[pwm_index(td->pwm)], 3);
 +}
 +
 +static void pwm_write_csr(QTestState *qts, const TestData *td, uint32_t value)
 +{
 +    pwm_write(qts, td, CSR, value << csr_base[pwm_index(td->pwm)]);
 +}
 +
 +static uint32_t pwm_read_pcr(QTestState *qts, const TestData *td)
 +{
 +    return extract32(pwm_read(qts, td, PCR), pcr_base[pwm_index(td->pwm)], 4);
 +}
 +
 +static void pwm_write_pcr(QTestState *qts, const TestData *td, uint32_t value)
 +{
 +    pwm_write(qts, td, PCR, value << pcr_base[pwm_index(td->pwm)]);
 +}
 +
 +static uint32_t pwm_read_cnr(QTestState *qts, const TestData *td)
 +{
 +    return pwm_read(qts, td, td->pwm->cnr_offset);
 +}
 +
 +static void pwm_write_cnr(QTestState *qts, const TestData *td, uint32_t value)
 +{
 +    pwm_write(qts, td, td->pwm->cnr_offset, value);
 +}
 +
 +static uint32_t pwm_read_cmr(QTestState *qts, const TestData *td)
 +{
 +    return pwm_read(qts, td, td->pwm->cmr_offset);
 +}
 +
 +static void pwm_write_cmr(QTestState *qts, const TestData *td, uint32_t value)
 +{
 +    pwm_write(qts, td, td->pwm->cmr_offset, value);
 +}
 +
 +/* Check pwm registers can be reset to default value */
 +static void test_init(gconstpointer test_data)
 +{
 +    const TestData *td = test_data;
 +    QTestState *qts = qtest_init("-machine quanta-gsj");
 +    int module = pwm_module_index(td->module);
 +    int pwm = pwm_index(td->pwm);
 +
 +    g_assert_cmpuint(pwm_get_freq(qts, module, pwm), ==, 0);
 +    g_assert_cmpuint(pwm_get_duty(qts, module, pwm), ==, 0);
 +
 +    qtest_quit(qts);
 +}
 +
 +/* One-shot mode should not change frequency and duty cycle. */
 +static void test_oneshot(gconstpointer test_data)
 +{
 +    const TestData *td = test_data;
 +    QTestState *qts = qtest_init("-machine quanta-gsj");
 +    int module = pwm_module_index(td->module);
 +    int pwm = pwm_index(td->pwm);
 +    uint32_t ppr, csr, pcr;
 +    int i, j;
 +
 +    pcr = CH_EN;
 +    for (i = 0; i < ARRAY_SIZE(ppr_list); ++i) {
 +        ppr = ppr_list[i];
 +        pwm_write_ppr(qts, td, ppr);
 +
 +        for (j = 0; j < ARRAY_SIZE(csr_list); ++j) {
 +            csr = csr_list[j];
 +            pwm_write_csr(qts, td, csr);
 +            pwm_write_pcr(qts, td, pcr);
 +
 +            g_assert_cmpuint(pwm_read_ppr(qts, td), ==, ppr);
 +            g_assert_cmpuint(pwm_read_csr(qts, td), ==, csr);
 +            g_assert_cmpuint(pwm_read_pcr(qts, td), ==, pcr);
 +            g_assert_cmpuint(pwm_get_freq(qts, module, pwm), ==, 0);
 +            g_assert_cmpuint(pwm_get_duty(qts, module, pwm), ==, 0);
 +        }
 +    }
 +
 +    qtest_quit(qts);
 +}
 +
 +/* In toggle mode, the PWM generates correct outputs. */
 +static void test_toggle(gconstpointer test_data)
 +{
 +    const TestData *td = test_data;
 +    QTestState *qts = qtest_init("-machine quanta-gsj");
 +    int module = pwm_module_index(td->module);
 +    int pwm = pwm_index(td->pwm);
 +    uint32_t ppr, csr, pcr, cnr, cmr;
 +    int i, j, k, l;
 +    uint64_t expected_freq, expected_duty;
 +
 +    pcr = CH_EN | CH_MOD;
 +    for (i = 0; i < ARRAY_SIZE(ppr_list); ++i) {
 +        ppr = ppr_list[i];
 +        pwm_write_ppr(qts, td, ppr);
 +
 +        for (j = 0; j < ARRAY_SIZE(csr_list); ++j) {
 +            csr = csr_list[j];
 +            pwm_write_csr(qts, td, csr);
 +
 +            for (k = 0; k < ARRAY_SIZE(cnr_list); ++k) {
 +                cnr = cnr_list[k];
 +                pwm_write_cnr(qts, td, cnr);
 +
 +                for (l = 0; l < ARRAY_SIZE(cmr_list); ++l) {
 +                    cmr = cmr_list[l];
 +                    pwm_write_cmr(qts, td, cmr);
 +                    expected_freq = pwm_compute_freq(qts, ppr, csr, cnr);
 +                    expected_duty = pwm_compute_duty(cnr, cmr, false);
 +
 +                    pwm_write_pcr(qts, td, pcr);
 +                    g_assert_cmpuint(pwm_read_ppr(qts, td), ==, ppr);
 +                    g_assert_cmpuint(pwm_read_csr(qts, td), ==, csr);
 +                    g_assert_cmpuint(pwm_read_pcr(qts, td), ==, pcr);
 +                    g_assert_cmpuint(pwm_read_cnr(qts, td), ==, cnr);
 +                    g_assert_cmpuint(pwm_read_cmr(qts, td), ==, cmr);
 +                    g_assert_cmpuint(pwm_get_duty(qts, module, pwm),
 +                            ==, expected_duty);
 +                    if (expected_duty != 0 && expected_duty != 100) {
 +                        /* Duty cycle with 0 or 100 doesn't need frequency. */
 +                        g_assert_cmpuint(pwm_get_freq(qts, module, pwm),
 +                                ==, expected_freq);
 +                    }
 +
 +                    /* Test inverted mode */
 +                    expected_duty = pwm_compute_duty(cnr, cmr, true);
 +                    pwm_write_pcr(qts, td, pcr | CH_INV);
 +                    g_assert_cmpuint(pwm_read_pcr(qts, td), ==, pcr | CH_INV);
 +                    g_assert_cmpuint(pwm_get_duty(qts, module, pwm),
 +                            ==, expected_duty);
 +                    if (expected_duty != 0 && expected_duty != 100) {
 +                        /* Duty cycle with 0 or 100 doesn't need frequency. */
 +                        g_assert_cmpuint(pwm_get_freq(qts, module, pwm),
 +                                ==, expected_freq);
 +                    }
 +
 +                }
 +            }
 +        }
 +    }
 +
 +    qtest_quit(qts);
 +}
 +
 +static void pwm_add_test(const char *name, const TestData* td,
 +        GTestDataFunc fn)
 +{
 +    g_autofree char *full_name = g_strdup_printf(
 +            "npcm7xx_pwm/module[%d]/pwm[%d]/%s", pwm_module_index(td->module),
 +            pwm_index(td->pwm), name);
 +    qtest_add_data_func(full_name, td, fn);
 +}
 +#define add_test(name, td) pwm_add_test(#name, td, test_##name)
 +
 +int main(int argc, char **argv)
 +{
 +    TestData test_data_list[ARRAY_SIZE(pwm_module_list) * ARRAY_SIZE(pwm_list)];
 +
 +    g_test_init(&argc, &argv, NULL);
 +
 +    for (int i = 0; i < ARRAY_SIZE(pwm_module_list); ++i) {
 +        for (int j = 0; j < ARRAY_SIZE(pwm_list); ++j) {
 +            TestData *td = &test_data_list[i * ARRAY_SIZE(pwm_list) + j];
 +
 +            td->module = &pwm_module_list[i];
 +            td->pwm = &pwm_list[j];
 +
 +            add_test(init, td);
 +            add_test(oneshot, td);
 +            add_test(toggle, td);
 +        }
 +    }
 +
 +    return g_test_run();
 +}
 diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
 index XXXXXXX..XXXXXXX 100644
 --- a/tests/qtest/meson.build
 +++ b/tests/qtest/meson.build
@@ -XXX,XX +XXX,XX @@ qtests_sparc64 = \
  qtests_npcm7xx = \
    ['npcm7xx_adc-test',
     'npcm7xx_gpio-test',
 +   'npcm7xx_pwm-test',
     'npcm7xx_rng-test',
     'npcm7xx_timer-test',
     'npcm7xx_watchdog_timer-test']
 --
-.20.1
+.34.1

-[PULL 16/21] hw/timer: Refactor NPCM7XX Timer to use CLK clock
+[PULL 23/24] hw/timer/npcm7xx_timer: Prevent timer from counting down past zero
-From: Hao Wu <wuhaotsh@google.com>
+From: Chris Rauer <crauer@google.com>
-This patch makes NPCM7XX Timer to use a the timer clock generated by the
+The counter register is only 24-bits and counts down.  If the timer is
-CLK module instead of the magic number TIMER_REF_HZ.
+running but the qtimer to reset it hasn't fired off yet, there is a chance
 the regster read can return an invalid result.
-Reviewed-by: Havard Skinnemoen <hskinnemoen@google.com>
+Signed-off-by: Chris Rauer <crauer@google.com>
-Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
+Message-id: 20230922181411.2697135-1-crauer@google.com
 Signed-off-by: Hao Wu <wuhaotsh@google.com>
 Message-id: 20210108190945.949196-3-wuhaotsh@google.com
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- include/hw/misc/npcm7xx_clk.h    |  6 -----
+ hw/timer/npcm7xx_timer.c | 3 +++
- include/hw/timer/npcm7xx_timer.h |  1 +
+file changed, 3 insertions(+)
  hw/arm/npcm7xx.c                 |  5 ++++
  hw/timer/npcm7xx_timer.c         | 39 +++++++++++++++-----------------
 files changed, 24 insertions(+), 27 deletions(-)
-diff --git a/include/hw/misc/npcm7xx_clk.h b/include/hw/misc/npcm7xx_clk.h
-index XXXXXXX..XXXXXXX 100644
---- a/include/hw/misc/npcm7xx_clk.h
-+++ b/include/hw/misc/npcm7xx_clk.h
-@@ -XXX,XX +XXX,XX @@
- #include "hw/clock.h"
- #include "hw/sysbus.h"
--/*
-- * The reference clock frequency for the timer modules, and the SECCNT and
-- * CNTR25M registers in this module, is always 25 MHz.
-- */
--#define NPCM7XX_TIMER_REF_HZ            (25000000)
--
- /*
-  * Number of registers in our device state structure. Don't change this without
-  * incrementing the version_id in the vmstate.
-diff --git a/include/hw/timer/npcm7xx_timer.h b/include/hw/timer/npcm7xx_timer.h
-index XXXXXXX..XXXXXXX 100644
---- a/include/hw/timer/npcm7xx_timer.h
-+++ b/include/hw/timer/npcm7xx_timer.h
-@@ -XXX,XX +XXX,XX @@ struct NPCM7xxTimerCtrlState {
-     uint32_t    tisr;
-+    Clock       *clock;
-     NPCM7xxTimer timer[NPCM7XX_TIMERS_PER_CTRL];
-     NPCM7xxWatchdogTimer watchdog_timer;
- };
-diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/npcm7xx.c
-+++ b/hw/arm/npcm7xx.c
-@@ -XXX,XX +XXX,XX @@
- #include "hw/char/serial.h"
- #include "hw/loader.h"
- #include "hw/misc/unimp.h"
-+#include "hw/qdev-clock.h"
- #include "hw/qdev-properties.h"
- #include "qapi/error.h"
- #include "qemu/units.h"
-@@ -XXX,XX +XXX,XX @@ static void npcm7xx_realize(DeviceState *dev, Error **errp)
-         int first_irq;
-         int j;
-+        /* Connect the timer clock. */
-+        qdev_connect_clock_in(DEVICE(&s->tim[i]), "clock", qdev_get_clock_out(
-+                    DEVICE(&s->clk), "timer-clock"));
-+
-         sysbus_realize(sbd, &error_abort);
-         sysbus_mmio_map(sbd, 0, npcm7xx_tim_addr[i]);
 diff --git a/hw/timer/npcm7xx_timer.c b/hw/timer/npcm7xx_timer.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/timer/npcm7xx_timer.c
 +++ b/hw/timer/npcm7xx_timer.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ static int64_t npcm7xx_timer_count_to_ns(NPCM7xxTimer *t, uint32_t count)
  #include "qemu/osdep.h"
  #include "hw/irq.h"
 +#include "hw/qdev-clock.h"
  #include "hw/qdev-properties.h"
 -#include "hw/misc/npcm7xx_clk.h"
  #include "hw/timer/npcm7xx_timer.h"
  #include "migration/vmstate.h"
  #include "qemu/bitops.h"
@@ -XXX,XX +XXX,XX @@ static uint32_t npcm7xx_tcsr_prescaler(uint32_t tcsr)
  /* Convert a timer cycle count to a time interval in nanoseconds. */
  static int64_t npcm7xx_timer_count_to_ns(NPCM7xxTimer *t, uint32_t count)
  {
 -    int64_t ns = count;
 +    int64_t ticks = count;
 -    ns *= NANOSECONDS_PER_SECOND / NPCM7XX_TIMER_REF_HZ;
 -    ns *= npcm7xx_tcsr_prescaler(t->tcsr);
 +    ticks *= npcm7xx_tcsr_prescaler(t->tcsr);
 -    return ns;
 +    return clock_ticks_to_ns(t->ctrl->clock, ticks);
  }
  /* Convert a time interval in nanoseconds to a timer cycle count. */
  static uint32_t npcm7xx_timer_ns_to_count(NPCM7xxTimer *t, int64_t ns)
  {
--    int64_t count;
++    if (ns < 0) {
--
++        return 0;
--    count = ns / (NANOSECONDS_PER_SECOND / NPCM7XX_TIMER_REF_HZ);
++    }
--    count /= npcm7xx_tcsr_prescaler(t->tcsr);
+     return clock_ns_to_ticks(t->ctrl->clock, ns) /
--
+         npcm7xx_tcsr_prescaler(t->tcsr);
 -    return count;
 +    return ns / clock_ticks_to_ns(t->ctrl->clock,
 +                                  npcm7xx_tcsr_prescaler(t->tcsr));
  }
- static uint32_t npcm7xx_watchdog_timer_prescaler(const NPCM7xxWatchdogTimer *t)
-@@ -XXX,XX +XXX,XX @@ static uint32_t npcm7xx_watchdog_timer_prescaler(const NPCM7xxWatchdogTimer *t)
- static void npcm7xx_watchdog_timer_reset_cycles(NPCM7xxWatchdogTimer *t,
-         int64_t cycles)
- {
--    uint32_t prescaler = npcm7xx_watchdog_timer_prescaler(t);
--    int64_t ns = (NANOSECONDS_PER_SECOND / NPCM7XX_TIMER_REF_HZ) * cycles;
-+    int64_t ticks = cycles * npcm7xx_watchdog_timer_prescaler(t);
-+    int64_t ns = clock_ticks_to_ns(t->ctrl->clock, ticks);
-     /*
-      * The reset function always clears the current timer. The caller of the
-@@ -XXX,XX +XXX,XX @@ static void npcm7xx_watchdog_timer_reset_cycles(NPCM7xxWatchdogTimer *t,
-      */
-     npcm7xx_timer_clear(&t->base_timer);
--    ns *= prescaler;
-     t->base_timer.remaining_ns = ns;
- }
-@@ -XXX,XX +XXX,XX @@ static void npcm7xx_timer_hold_reset(Object *obj)
-     qemu_irq_lower(s->watchdog_timer.irq);
- }
--static void npcm7xx_timer_realize(DeviceState *dev, Error **errp)
-+static void npcm7xx_timer_init(Object *obj)
- {
--    NPCM7xxTimerCtrlState *s = NPCM7XX_TIMER(dev);
--    SysBusDevice *sbd = &s->parent;
-+    NPCM7xxTimerCtrlState *s = NPCM7XX_TIMER(obj);
-+    DeviceState *dev = DEVICE(obj);
-+    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
-     int i;
-     NPCM7xxWatchdogTimer *w;
-@@ -XXX,XX +XXX,XX @@ static void npcm7xx_timer_realize(DeviceState *dev, Error **errp)
-             npcm7xx_watchdog_timer_expired, w);
-     sysbus_init_irq(sbd, &w->irq);
--    memory_region_init_io(&s->iomem, OBJECT(s), &npcm7xx_timer_ops, s,
-+    memory_region_init_io(&s->iomem, obj, &npcm7xx_timer_ops, s,
-                           TYPE_NPCM7XX_TIMER, 4 * KiB);
-     sysbus_init_mmio(sbd, &s->iomem);
-     qdev_init_gpio_out_named(dev, &w->reset_signal,
-             NPCM7XX_WATCHDOG_RESET_GPIO_OUT, 1);
-+    s->clock = qdev_init_clock_in(dev, "clock", NULL, NULL);
- }
- static const VMStateDescription vmstate_npcm7xx_base_timer = {
-@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_npcm7xx_watchdog_timer = {
- static const VMStateDescription vmstate_npcm7xx_timer_ctrl = {
-     .name = "npcm7xx-timer-ctrl",
--    .version_id = 1,
--    .minimum_version_id = 1,
-+    .version_id = 2,
-+    .minimum_version_id = 2,
-     .fields = (VMStateField[]) {
-         VMSTATE_UINT32(tisr, NPCM7xxTimerCtrlState),
-+        VMSTATE_CLOCK(clock, NPCM7xxTimerCtrlState),
-         VMSTATE_STRUCT_ARRAY(timer, NPCM7xxTimerCtrlState,
-                              NPCM7XX_TIMERS_PER_CTRL, 0, vmstate_npcm7xx_timer,
-                              NPCM7xxTimer),
-@@ -XXX,XX +XXX,XX @@ static void npcm7xx_timer_class_init(ObjectClass *klass, void *data)
-     QEMU_BUILD_BUG_ON(NPCM7XX_TIMER_REGS_END > NPCM7XX_TIMER_NR_REGS);
-     dc->desc = "NPCM7xx Timer Controller";
--    dc->realize = npcm7xx_timer_realize;
-     dc->vmsd = &vmstate_npcm7xx_timer_ctrl;
-     rc->phases.enter = npcm7xx_timer_enter_reset;
-     rc->phases.hold = npcm7xx_timer_hold_reset;
-@@ -XXX,XX +XXX,XX @@ static const TypeInfo npcm7xx_timer_info = {
-     .parent             = TYPE_SYS_BUS_DEVICE,
-     .instance_size      = sizeof(NPCM7xxTimerCtrlState),
-     .class_init         = npcm7xx_timer_class_init,
-+    .instance_init      = npcm7xx_timer_init,
- };
- static void npcm7xx_timer_register_type(void)
 --
-.20.1
+.34.1

-[PULL 15/21] hw/misc: Add clock converter in NPCM7XX CLK module
+[PULL 24/24] contrib/elf2dmp: Use g_malloc(), g_new() and g_free()
-From: Hao Wu <wuhaotsh@google.com>
+From: Suraj Shirvankar <surajshirvankar@gmail.com>
-This patch allows NPCM7XX CLK module to compute clocks that are used by
+QEMU coding style uses the glib memory allocation APIs, not
-other NPCM7XX modules.
+the raw libc malloc/free. Switch the allocation and free
 calls in elf2dmp to use these functions (dropping the now-unneeded
 checks for failure).
-Add a new struct NPCM7xxClockConverterState which represents a
+Signed-off-by: Suraj Shirvankar <surajshirvankar@gmail.com>
-single converter.  Each clock converter in CLK module represents one
+Message-id: 169753938460.23804.11418813007617535750-1@git.sr.ht
-converter in NPCM7XX CLK Module(PLL, SEL or Divider). Each converter
+[PMM: also remove NULL checks from g_malloc() calls;
-takes one or more input clocks and converts them into one output clock.
+ beef up commit message]
 They form a clock hierarchy in the CLK module and are responsible for
 outputing clocks for various other modules in an NPCM7XX SoC.
 Each converter has a function pointer called "convert" which represents
 the unique logic for that converter.
 The clock contains two initialization information: ConverterInitInfo and
 ConverterConnectionInfo. They represent the vertices and edges in the
 clock diagram respectively.
 Reviewed-by: Havard Skinnemoen <hskinnemoen@google.com>
 Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
 Signed-off-by: Hao Wu <wuhaotsh@google.com>
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Message-id: 20210108190945.949196-2-wuhaotsh@google.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- include/hw/misc/npcm7xx_clk.h | 140 +++++-
+ contrib/elf2dmp/addrspace.c |  7 ++-----
- hw/misc/npcm7xx_clk.c         | 805 +++++++++++++++++++++++++++++++++-
+ contrib/elf2dmp/main.c      |  9 +++------
-files changed, 932 insertions(+), 13 deletions(-)
+ contrib/elf2dmp/pdb.c       | 19 ++++++++-----------
  contrib/elf2dmp/qemu_elf.c  |  7 ++-----
 files changed, 15 insertions(+), 27 deletions(-)
-diff --git a/include/hw/misc/npcm7xx_clk.h b/include/hw/misc/npcm7xx_clk.h
+diff --git a/contrib/elf2dmp/addrspace.c b/contrib/elf2dmp/addrspace.c
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/misc/npcm7xx_clk.h
+--- a/contrib/elf2dmp/addrspace.c
-+++ b/include/hw/misc/npcm7xx_clk.h
++++ b/contrib/elf2dmp/addrspace.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ int pa_space_create(struct pa_space *ps, QEMU_Elf *qemu_elf)
- #define NPCM7XX_CLK_H
+         }
+     }
- #include "exec/memory.h"
-+#include "hw/clock.h"
+-    ps->block = malloc(sizeof(*ps->block) * ps->block_nr);
- #include "hw/sysbus.h"
+-    if (!ps->block) {
+-        return 1;
- /*
+-    }
-@@ -XXX,XX +XXX,XX @@
++    ps->block = g_new(struct pa_block, ps->block_nr);
- #define NPCM7XX_WATCHDOG_RESET_GPIO_IN "npcm7xx-clk-watchdog-reset-gpio-in"
+     for (i = 0; i < phdr_nr; i++) {
+         if (phdr[i].p_type == PT_LOAD) {
--typedef struct NPCM7xxCLKState {
+@@ -XXX,XX +XXX,XX @@ int pa_space_create(struct pa_space *ps, QEMU_Elf *qemu_elf)
-+/* Maximum amount of clock inputs in a SEL module. */
+ void pa_space_destroy(struct pa_space *ps)
-+#define NPCM7XX_CLK_SEL_MAX_INPUT 5
+ {
-+
+     ps->block_nr = 0;
-+/* PLLs in CLK module. */
+-    free(ps->block);
-+typedef enum NPCM7xxClockPLL {
++    g_free(ps->block);
-+    NPCM7XX_CLOCK_PLL0,
+ }
-+    NPCM7XX_CLOCK_PLL1,
-+    NPCM7XX_CLOCK_PLL2,
+ void va_space_set_dtb(struct va_space *vs, uint64_t dtb)
-+    NPCM7XX_CLOCK_PLLG,
+diff --git a/contrib/elf2dmp/main.c b/contrib/elf2dmp/main.c
 +    NPCM7XX_CLOCK_NR_PLLS,
 +} NPCM7xxClockPLL;
 +
 +/* SEL/MUX in CLK module. */
 +typedef enum NPCM7xxClockSEL {
 +    NPCM7XX_CLOCK_PIXCKSEL,
 +    NPCM7XX_CLOCK_MCCKSEL,
 +    NPCM7XX_CLOCK_CPUCKSEL,
 +    NPCM7XX_CLOCK_CLKOUTSEL,
 +    NPCM7XX_CLOCK_UARTCKSEL,
 +    NPCM7XX_CLOCK_TIMCKSEL,
 +    NPCM7XX_CLOCK_SDCKSEL,
 +    NPCM7XX_CLOCK_GFXMSEL,
 +    NPCM7XX_CLOCK_SUCKSEL,
 +    NPCM7XX_CLOCK_NR_SELS,
 +} NPCM7xxClockSEL;
 +
 +/* Dividers in CLK module. */
 +typedef enum NPCM7xxClockDivider {
 +    NPCM7XX_CLOCK_PLL1D2, /* PLL1/2 */
 +    NPCM7XX_CLOCK_PLL2D2, /* PLL2/2 */
 +    NPCM7XX_CLOCK_MC_DIVIDER,
 +    NPCM7XX_CLOCK_AXI_DIVIDER,
 +    NPCM7XX_CLOCK_AHB_DIVIDER,
 +    NPCM7XX_CLOCK_AHB3_DIVIDER,
 +    NPCM7XX_CLOCK_SPI0_DIVIDER,
 +    NPCM7XX_CLOCK_SPIX_DIVIDER,
 +    NPCM7XX_CLOCK_APB1_DIVIDER,
 +    NPCM7XX_CLOCK_APB2_DIVIDER,
 +    NPCM7XX_CLOCK_APB3_DIVIDER,
 +    NPCM7XX_CLOCK_APB4_DIVIDER,
 +    NPCM7XX_CLOCK_APB5_DIVIDER,
 +    NPCM7XX_CLOCK_CLKOUT_DIVIDER,
 +    NPCM7XX_CLOCK_UART_DIVIDER,
 +    NPCM7XX_CLOCK_TIMER_DIVIDER,
 +    NPCM7XX_CLOCK_ADC_DIVIDER,
 +    NPCM7XX_CLOCK_MMC_DIVIDER,
 +    NPCM7XX_CLOCK_SDHC_DIVIDER,
 +    NPCM7XX_CLOCK_GFXM_DIVIDER, /* divide by 3 */
 +    NPCM7XX_CLOCK_UTMI_DIVIDER,
 +    NPCM7XX_CLOCK_NR_DIVIDERS,
 +} NPCM7xxClockConverter;
 +
 +typedef struct NPCM7xxCLKState NPCM7xxCLKState;
 +
 +/**
 + * struct NPCM7xxClockPLLState - A PLL module in CLK module.
 + * @name: The name of the module.
 + * @clk: The CLK module that owns this module.
 + * @clock_in: The input clock of this module.
 + * @clock_out: The output clock of this module.
 + * @reg: The control registers for this PLL module.
 + */
 +typedef struct NPCM7xxClockPLLState {
 +    DeviceState parent;
 +
 +    const char *name;
 +    NPCM7xxCLKState *clk;
 +    Clock *clock_in;
 +    Clock *clock_out;
 +
 +    int reg;
 +} NPCM7xxClockPLLState;
 +
 +/**
 + * struct NPCM7xxClockSELState - A SEL module in CLK module.
 + * @name: The name of the module.
 + * @clk: The CLK module that owns this module.
 + * @input_size: The size of inputs of this module.
 + * @clock_in: The input clocks of this module.
 + * @clock_out: The output clocks of this module.
 + * @offset: The offset of this module in the control register.
 + * @len: The length of this module in the control register.
 + */
 +typedef struct NPCM7xxClockSELState {
 +    DeviceState parent;
 +
 +    const char *name;
 +    NPCM7xxCLKState *clk;
 +    uint8_t input_size;
 +    Clock *clock_in[NPCM7XX_CLK_SEL_MAX_INPUT];
 +    Clock *clock_out;
 +
 +    int offset;
 +    int len;
 +} NPCM7xxClockSELState;
 +
 +/**
 + * struct NPCM7xxClockDividerState - A Divider module in CLK module.
 + * @name: The name of the module.
 + * @clk: The CLK module that owns this module.
 + * @clock_in: The input clock of this module.
 + * @clock_out: The output clock of this module.
 + * @divide: The function the divider uses to divide the input.
 + * @reg: The index of the control register that contains the divisor.
 + * @offset: The offset of the divisor in the control register.
 + * @len: The length of the divisor in the control register.
 + * @divisor: The divisor for a constant divisor
 + */
 +typedef struct NPCM7xxClockDividerState {
 +    DeviceState parent;
 +
 +    const char *name;
 +    NPCM7xxCLKState *clk;
 +    Clock *clock_in;
 +    Clock *clock_out;
 +
 +    uint32_t (*divide)(struct NPCM7xxClockDividerState *s);
 +    union {
 +        struct {
 +            int reg;
 +            int offset;
 +            int len;
 +        };
 +        int divisor;
 +    };
 +} NPCM7xxClockDividerState;
 +
 +struct NPCM7xxCLKState {
      SysBusDevice parent;
      MemoryRegion iomem;
 +    /* Clock converters */
 +    NPCM7xxClockPLLState plls[NPCM7XX_CLOCK_NR_PLLS];
 +    NPCM7xxClockSELState sels[NPCM7XX_CLOCK_NR_SELS];
 +    NPCM7xxClockDividerState dividers[NPCM7XX_CLOCK_NR_DIVIDERS];
 +
      uint32_t regs[NPCM7XX_CLK_NR_REGS];
      /* Time reference for SECCNT and CNTR25M, initialized by power on reset */
      int64_t ref_ns;
 -} NPCM7xxCLKState;
 +
 +    /* The incoming reference clock. */
 +    Clock *clkref;
 +};
  #define TYPE_NPCM7XX_CLK "npcm7xx-clk"
  #define NPCM7XX_CLK(obj) OBJECT_CHECK(NPCM7xxCLKState, (obj), TYPE_NPCM7XX_CLK)
 diff --git a/hw/misc/npcm7xx_clk.c b/hw/misc/npcm7xx_clk.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/misc/npcm7xx_clk.c
+--- a/contrib/elf2dmp/main.c
-+++ b/hw/misc/npcm7xx_clk.c
++++ b/contrib/elf2dmp/main.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ static KDDEBUGGER_DATA64 *get_kdbg(uint64_t KernBase, struct pdb_reader *pdb,
+         }
- #include "hw/misc/npcm7xx_clk.h"
+     }
- #include "hw/timer/npcm7xx_timer.h"
-+#include "hw/qdev-clock.h"
+-    kdbg = malloc(kdbg_hdr.Size);
- #include "migration/vmstate.h"
+-    if (!kdbg) {
- #include "qemu/error-report.h"
+-        return NULL;
- #include "qemu/log.h"
+-    }
-@@ -XXX,XX +XXX,XX @@
++    kdbg = g_malloc(kdbg_hdr.Size);
- #include "trace.h"
- #include "sysemu/watchdog.h"
+     if (va_space_rw(vs, KdDebuggerDataBlock, kdbg, kdbg_hdr.Size, 0)) {
+         eprintf("Failed to extract entire KDBG\n");
-+/*
+-        free(kdbg);
-+ * The reference clock hz, and the SECCNT and CNTR25M registers in this module,
++        g_free(kdbg);
-+ * is always 25 MHz.
+         return NULL;
-+ */
+     }
-+#define NPCM7XX_CLOCK_REF_HZ            (25000000)
-+
+@@ -XXX,XX +XXX,XX @@ int main(int argc, char *argv[])
-+/* Register Field Definitions */
+     }
-+#define NPCM7XX_CLK_WDRCR_CA9C  BIT(0) /* Cortex A9 Cores */
-+
+ out_kdbg:
- #define PLLCON_LOKI     BIT(31)
+-    free(kdbg);
- #define PLLCON_LOKS     BIT(30)
++    g_free(kdbg);
- #define PLLCON_PWDEN    BIT(12)
+ out_pdb:
-+#define PLLCON_FBDV(con) extract32((con), 16, 12)
+     pdb_exit(&pdb);
-+#define PLLCON_OTDV2(con) extract32((con), 13, 3)
+ out_pdb_file:
-+#define PLLCON_OTDV1(con) extract32((con), 8, 3)
+diff --git a/contrib/elf2dmp/pdb.c b/contrib/elf2dmp/pdb.c
-+#define PLLCON_INDV(con) extract32((con), 0, 6)
+index XXXXXXX..XXXXXXX 100644
+--- a/contrib/elf2dmp/pdb.c
- enum NPCM7xxCLKRegisters {
++++ b/contrib/elf2dmp/pdb.c
-     NPCM7XX_CLK_CLKEN1,
+@@ -XXX,XX +XXX,XX @@ uint64_t pdb_resolve(uint64_t img_base, struct pdb_reader *r, const char *name)
-@@ -XXX,XX +XXX,XX @@ static const uint32_t cold_reset_values[NPCM7XX_CLK_NR_REGS] = {
-     [NPCM7XX_CLK_AHBCKFI]       = 0x000000c8,
+ static void pdb_reader_ds_exit(struct pdb_reader *r)
  };
 -/* Register Field Definitions */
 -#define NPCM7XX_CLK_WDRCR_CA9C  BIT(0) /* Cortex A9 Cores */
 -
  /* The number of watchdogs that can trigger a reset. */
  #define NPCM7XX_NR_WATCHDOGS    (3)
 +/* Clock converter functions */
 +
 +#define TYPE_NPCM7XX_CLOCK_PLL "npcm7xx-clock-pll"
 +#define NPCM7XX_CLOCK_PLL(obj) OBJECT_CHECK(NPCM7xxClockPLLState, \
 +        (obj), TYPE_NPCM7XX_CLOCK_PLL)
 +#define TYPE_NPCM7XX_CLOCK_SEL "npcm7xx-clock-sel"
 +#define NPCM7XX_CLOCK_SEL(obj) OBJECT_CHECK(NPCM7xxClockSELState, \
 +        (obj), TYPE_NPCM7XX_CLOCK_SEL)
 +#define TYPE_NPCM7XX_CLOCK_DIVIDER "npcm7xx-clock-divider"
 +#define NPCM7XX_CLOCK_DIVIDER(obj) OBJECT_CHECK(NPCM7xxClockDividerState, \
 +        (obj), TYPE_NPCM7XX_CLOCK_DIVIDER)
 +
 +static void npcm7xx_clk_update_pll(void *opaque)
 +{
 +    NPCM7xxClockPLLState *s = opaque;
 +    uint32_t con = s->clk->regs[s->reg];
 +    uint64_t freq;
 +
 +    /* The PLL is grounded if it is not locked yet. */
 +    if (con & PLLCON_LOKI) {
 +        freq = clock_get_hz(s->clock_in);
 +        freq *= PLLCON_FBDV(con);
 +        freq /= PLLCON_INDV(con) * PLLCON_OTDV1(con) * PLLCON_OTDV2(con);
 +    } else {
 +        freq = 0;
 +    }
 +
 +    clock_update_hz(s->clock_out, freq);
 +}
 +
 +static void npcm7xx_clk_update_sel(void *opaque)
 +{
 +    NPCM7xxClockSELState *s = opaque;
 +    uint32_t index = extract32(s->clk->regs[NPCM7XX_CLK_CLKSEL], s->offset,
 +            s->len);
 +
 +    if (index >= s->input_size) {
 +        qemu_log_mask(LOG_GUEST_ERROR,
 +                      "%s: SEL index: %u out of range\n",
 +                      __func__, index);
 +        index = 0;
 +    }
 +    clock_update_hz(s->clock_out, clock_get_hz(s->clock_in[index]));
 +}
 +
 +static void npcm7xx_clk_update_divider(void *opaque)
 +{
 +    NPCM7xxClockDividerState *s = opaque;
 +    uint32_t freq;
 +
 +    freq = s->divide(s);
 +    clock_update_hz(s->clock_out, freq);
 +}
 +
 +static uint32_t divide_by_constant(NPCM7xxClockDividerState *s)
 +{
 +    return clock_get_hz(s->clock_in) / s->divisor;
 +}
 +
 +static uint32_t divide_by_reg_divisor(NPCM7xxClockDividerState *s)
 +{
 +    return clock_get_hz(s->clock_in) /
 +            (extract32(s->clk->regs[s->reg], s->offset, s->len) + 1);
 +}
 +
 +static uint32_t divide_by_reg_divisor_times_2(NPCM7xxClockDividerState *s)
 +{
 +    return divide_by_reg_divisor(s) / 2;
 +}
 +
 +static uint32_t shift_by_reg_divisor(NPCM7xxClockDividerState *s)
 +{
 +    return clock_get_hz(s->clock_in) >>
 +        extract32(s->clk->regs[s->reg], s->offset, s->len);
 +}
 +
 +static NPCM7xxClockPLL find_pll_by_reg(enum NPCM7xxCLKRegisters reg)
 +{
 +    switch (reg) {
 +    case NPCM7XX_CLK_PLLCON0:
 +        return NPCM7XX_CLOCK_PLL0;
 +    case NPCM7XX_CLK_PLLCON1:
 +        return NPCM7XX_CLOCK_PLL1;
 +    case NPCM7XX_CLK_PLLCON2:
 +        return NPCM7XX_CLOCK_PLL2;
 +    case NPCM7XX_CLK_PLLCONG:
 +        return NPCM7XX_CLOCK_PLLG;
 +    default:
 +        g_assert_not_reached();
 +    }
 +}
 +
 +static void npcm7xx_clk_update_all_plls(NPCM7xxCLKState *clk)
 +{
 +    int i;
 +
 +    for (i = 0; i < NPCM7XX_CLOCK_NR_PLLS; ++i) {
 +        npcm7xx_clk_update_pll(&clk->plls[i]);
 +    }
 +}
 +
 +static void npcm7xx_clk_update_all_sels(NPCM7xxCLKState *clk)
 +{
 +    int i;
 +
 +    for (i = 0; i < NPCM7XX_CLOCK_NR_SELS; ++i) {
 +        npcm7xx_clk_update_sel(&clk->sels[i]);
 +    }
 +}
 +
 +static void npcm7xx_clk_update_all_dividers(NPCM7xxCLKState *clk)
 +{
 +    int i;
 +
 +    for (i = 0; i < NPCM7XX_CLOCK_NR_DIVIDERS; ++i) {
 +        npcm7xx_clk_update_divider(&clk->dividers[i]);
 +    }
 +}
 +
 +static void npcm7xx_clk_update_all_clocks(NPCM7xxCLKState *clk)
 +{
 +    clock_update_hz(clk->clkref, NPCM7XX_CLOCK_REF_HZ);
 +    npcm7xx_clk_update_all_plls(clk);
 +    npcm7xx_clk_update_all_sels(clk);
 +    npcm7xx_clk_update_all_dividers(clk);
 +}
 +
 +/* Types of clock sources. */
 +typedef enum ClockSrcType {
 +    CLKSRC_REF,
 +    CLKSRC_PLL,
 +    CLKSRC_SEL,
 +    CLKSRC_DIV,
 +} ClockSrcType;
 +
 +typedef struct PLLInitInfo {
 +    const char *name;
 +    ClockSrcType src_type;
 +    int src_index;
 +    int reg;
 +    const char *public_name;
 +} PLLInitInfo;
 +
 +typedef struct SELInitInfo {
 +    const char *name;
 +    uint8_t input_size;
 +    ClockSrcType src_type[NPCM7XX_CLK_SEL_MAX_INPUT];
 +    int src_index[NPCM7XX_CLK_SEL_MAX_INPUT];
 +    int offset;
 +    int len;
 +    const char *public_name;
 +} SELInitInfo;
 +
 +typedef struct DividerInitInfo {
 +    const char *name;
 +    ClockSrcType src_type;
 +    int src_index;
 +    uint32_t (*divide)(NPCM7xxClockDividerState *s);
 +    int reg; /* not used when type == CONSTANT */
 +    int offset; /* not used when type == CONSTANT */
 +    int len; /* not used when type == CONSTANT */
 +    int divisor; /* used only when type == CONSTANT */
 +    const char *public_name;
 +} DividerInitInfo;
 +
 +static const PLLInitInfo pll_init_info_list[] = {
 +    [NPCM7XX_CLOCK_PLL0] = {
 +        .name = "pll0",
 +        .src_type = CLKSRC_REF,
 +        .reg = NPCM7XX_CLK_PLLCON0,
 +    },
 +    [NPCM7XX_CLOCK_PLL1] = {
 +        .name = "pll1",
 +        .src_type = CLKSRC_REF,
 +        .reg = NPCM7XX_CLK_PLLCON1,
 +    },
 +    [NPCM7XX_CLOCK_PLL2] = {
 +        .name = "pll2",
 +        .src_type = CLKSRC_REF,
 +        .reg = NPCM7XX_CLK_PLLCON2,
 +    },
 +    [NPCM7XX_CLOCK_PLLG] = {
 +        .name = "pllg",
 +        .src_type = CLKSRC_REF,
 +        .reg = NPCM7XX_CLK_PLLCONG,
 +    },
 +};
 +
 +static const SELInitInfo sel_init_info_list[] = {
 +    [NPCM7XX_CLOCK_PIXCKSEL] = {
 +        .name = "pixcksel",
 +        .input_size = 2,
 +        .src_type = {CLKSRC_PLL, CLKSRC_REF},
 +        .src_index = {NPCM7XX_CLOCK_PLLG, 0},
 +        .offset = 5,
 +        .len = 1,
 +        .public_name = "pixel-clock",
 +    },
 +    [NPCM7XX_CLOCK_MCCKSEL] = {
 +        .name = "mccksel",
 +        .input_size = 4,
 +        .src_type = {CLKSRC_DIV, CLKSRC_REF, CLKSRC_REF,
 +            /*MCBPCK, shouldn't be used in normal operation*/
 +            CLKSRC_REF},
 +        .src_index = {NPCM7XX_CLOCK_PLL1D2, 0, 0, 0},
 +        .offset = 12,
 +        .len = 2,
 +        .public_name = "mc-phy-clock",
 +    },
 +    [NPCM7XX_CLOCK_CPUCKSEL] = {
 +        .name = "cpucksel",
 +        .input_size = 4,
 +        .src_type = {CLKSRC_PLL, CLKSRC_DIV, CLKSRC_REF,
 +            /*SYSBPCK, shouldn't be used in normal operation*/
 +            CLKSRC_REF},
 +        .src_index = {NPCM7XX_CLOCK_PLL0, NPCM7XX_CLOCK_PLL1D2, 0, 0},
 +        .offset = 0,
 +        .len = 2,
 +        .public_name = "system-clock",
 +    },
 +    [NPCM7XX_CLOCK_CLKOUTSEL] = {
 +        .name = "clkoutsel",
 +        .input_size = 5,
 +        .src_type = {CLKSRC_PLL, CLKSRC_DIV, CLKSRC_REF,
 +            CLKSRC_PLL, CLKSRC_DIV},
 +        .src_index = {NPCM7XX_CLOCK_PLL0, NPCM7XX_CLOCK_PLL1D2, 0,
 +            NPCM7XX_CLOCK_PLLG, NPCM7XX_CLOCK_PLL2D2},
 +        .offset = 18,
 +        .len = 3,
 +        .public_name = "tock",
 +    },
 +    [NPCM7XX_CLOCK_UARTCKSEL] = {
 +        .name = "uartcksel",
 +        .input_size = 4,
 +        .src_type = {CLKSRC_PLL, CLKSRC_DIV, CLKSRC_REF, CLKSRC_DIV},
 +        .src_index = {NPCM7XX_CLOCK_PLL0, NPCM7XX_CLOCK_PLL1D2, 0,
 +            NPCM7XX_CLOCK_PLL2D2},
 +        .offset = 8,
 +        .len = 2,
 +    },
 +    [NPCM7XX_CLOCK_TIMCKSEL] = {
 +        .name = "timcksel",
 +        .input_size = 4,
 +        .src_type = {CLKSRC_PLL, CLKSRC_DIV, CLKSRC_REF, CLKSRC_DIV},
 +        .src_index = {NPCM7XX_CLOCK_PLL0, NPCM7XX_CLOCK_PLL1D2, 0,
 +            NPCM7XX_CLOCK_PLL2D2},
 +        .offset = 14,
 +        .len = 2,
 +    },
 +    [NPCM7XX_CLOCK_SDCKSEL] = {
 +        .name = "sdcksel",
 +        .input_size = 4,
 +        .src_type = {CLKSRC_PLL, CLKSRC_DIV, CLKSRC_REF, CLKSRC_DIV},
 +        .src_index = {NPCM7XX_CLOCK_PLL0, NPCM7XX_CLOCK_PLL1D2, 0,
 +            NPCM7XX_CLOCK_PLL2D2},
 +        .offset = 6,
 +        .len = 2,
 +    },
 +    [NPCM7XX_CLOCK_GFXMSEL] = {
 +        .name = "gfxmksel",
 +        .input_size = 2,
 +        .src_type = {CLKSRC_REF, CLKSRC_PLL},
 +        .src_index = {0, NPCM7XX_CLOCK_PLL2},
 +        .offset = 21,
 +        .len = 1,
 +    },
 +    [NPCM7XX_CLOCK_SUCKSEL] = {
 +        .name = "sucksel",
 +        .input_size = 4,
 +        .src_type = {CLKSRC_PLL, CLKSRC_DIV, CLKSRC_REF, CLKSRC_DIV},
 +        .src_index = {NPCM7XX_CLOCK_PLL0, NPCM7XX_CLOCK_PLL1D2, 0,
 +            NPCM7XX_CLOCK_PLL2D2},
 +        .offset = 10,
 +        .len = 2,
 +    },
 +};
 +
 +static const DividerInitInfo divider_init_info_list[] = {
 +    [NPCM7XX_CLOCK_PLL1D2] = {
 +        .name = "pll1d2",
 +        .src_type = CLKSRC_PLL,
 +        .src_index = NPCM7XX_CLOCK_PLL1,
 +        .divide = divide_by_constant,
 +        .divisor = 2,
 +    },
 +    [NPCM7XX_CLOCK_PLL2D2] = {
 +        .name = "pll2d2",
 +        .src_type = CLKSRC_PLL,
 +        .src_index = NPCM7XX_CLOCK_PLL2,
 +        .divide = divide_by_constant,
 +        .divisor = 2,
 +    },
 +    [NPCM7XX_CLOCK_MC_DIVIDER] = {
 +        .name = "mc-divider",
 +        .src_type = CLKSRC_SEL,
 +        .src_index = NPCM7XX_CLOCK_MCCKSEL,
 +        .divide = divide_by_constant,
 +        .divisor = 2,
 +        .public_name = "mc-clock"
 +    },
 +    [NPCM7XX_CLOCK_AXI_DIVIDER] = {
 +        .name = "axi-divider",
 +        .src_type = CLKSRC_SEL,
 +        .src_index = NPCM7XX_CLOCK_CPUCKSEL,
 +        .divide = shift_by_reg_divisor,
 +        .reg = NPCM7XX_CLK_CLKDIV1,
 +        .offset = 0,
 +        .len = 1,
 +        .public_name = "clk2"
 +    },
 +    [NPCM7XX_CLOCK_AHB_DIVIDER] = {
 +        .name = "ahb-divider",
 +        .src_type = CLKSRC_DIV,
 +        .src_index = NPCM7XX_CLOCK_AXI_DIVIDER,
 +        .divide = divide_by_reg_divisor,
 +        .reg = NPCM7XX_CLK_CLKDIV1,
 +        .offset = 26,
 +        .len = 2,
 +        .public_name = "clk4"
 +    },
 +    [NPCM7XX_CLOCK_AHB3_DIVIDER] = {
 +        .name = "ahb3-divider",
 +        .src_type = CLKSRC_DIV,
 +        .src_index = NPCM7XX_CLOCK_AHB_DIVIDER,
 +        .divide = divide_by_reg_divisor,
 +        .reg = NPCM7XX_CLK_CLKDIV1,
 +        .offset = 6,
 +        .len = 5,
 +        .public_name = "ahb3-spi3-clock"
 +    },
 +    [NPCM7XX_CLOCK_SPI0_DIVIDER] = {
 +        .name = "spi0-divider",
 +        .src_type = CLKSRC_DIV,
 +        .src_index = NPCM7XX_CLOCK_AHB_DIVIDER,
 +        .divide = divide_by_reg_divisor,
 +        .reg = NPCM7XX_CLK_CLKDIV3,
 +        .offset = 6,
 +        .len = 5,
 +        .public_name = "spi0-clock",
 +    },
 +    [NPCM7XX_CLOCK_SPIX_DIVIDER] = {
 +        .name = "spix-divider",
 +        .src_type = CLKSRC_DIV,
 +        .src_index = NPCM7XX_CLOCK_AHB_DIVIDER,
 +        .divide = divide_by_reg_divisor,
 +        .reg = NPCM7XX_CLK_CLKDIV3,
 +        .offset = 1,
 +        .len = 5,
 +        .public_name = "spix-clock",
 +    },
 +    [NPCM7XX_CLOCK_APB1_DIVIDER] = {
 +        .name = "apb1-divider",
 +        .src_type = CLKSRC_DIV,
 +        .src_index = NPCM7XX_CLOCK_AHB_DIVIDER,
 +        .divide = shift_by_reg_divisor,
 +        .reg = NPCM7XX_CLK_CLKDIV2,
 +        .offset = 24,
 +        .len = 2,
 +        .public_name = "apb1-clock",
 +    },
 +    [NPCM7XX_CLOCK_APB2_DIVIDER] = {
 +        .name = "apb2-divider",
 +        .src_type = CLKSRC_DIV,
 +        .src_index = NPCM7XX_CLOCK_AHB_DIVIDER,
 +        .divide = shift_by_reg_divisor,
 +        .reg = NPCM7XX_CLK_CLKDIV2,
 +        .offset = 26,
 +        .len = 2,
 +        .public_name = "apb2-clock",
 +    },
 +    [NPCM7XX_CLOCK_APB3_DIVIDER] = {
 +        .name = "apb3-divider",
 +        .src_type = CLKSRC_DIV,
 +        .src_index = NPCM7XX_CLOCK_AHB_DIVIDER,
 +        .divide = shift_by_reg_divisor,
 +        .reg = NPCM7XX_CLK_CLKDIV2,
 +        .offset = 28,
 +        .len = 2,
 +        .public_name = "apb3-clock",
 +    },
 +    [NPCM7XX_CLOCK_APB4_DIVIDER] = {
 +        .name = "apb4-divider",
 +        .src_type = CLKSRC_DIV,
 +        .src_index = NPCM7XX_CLOCK_AHB_DIVIDER,
 +        .divide = shift_by_reg_divisor,
 +        .reg = NPCM7XX_CLK_CLKDIV2,
 +        .offset = 30,
 +        .len = 2,
 +        .public_name = "apb4-clock",
 +    },
 +    [NPCM7XX_CLOCK_APB5_DIVIDER] = {
 +        .name = "apb5-divider",
 +        .src_type = CLKSRC_DIV,
 +        .src_index = NPCM7XX_CLOCK_AHB_DIVIDER,
 +        .divide = shift_by_reg_divisor,
 +        .reg = NPCM7XX_CLK_CLKDIV2,
 +        .offset = 22,
 +        .len = 2,
 +        .public_name = "apb5-clock",
 +    },
 +    [NPCM7XX_CLOCK_CLKOUT_DIVIDER] = {
 +        .name = "clkout-divider",
 +        .src_type = CLKSRC_SEL,
 +        .src_index = NPCM7XX_CLOCK_CLKOUTSEL,
 +        .divide = divide_by_reg_divisor,
 +        .reg = NPCM7XX_CLK_CLKDIV2,
 +        .offset = 16,
 +        .len = 5,
 +        .public_name = "clkout",
 +    },
 +    [NPCM7XX_CLOCK_UART_DIVIDER] = {
 +        .name = "uart-divider",
 +        .src_type = CLKSRC_SEL,
 +        .src_index = NPCM7XX_CLOCK_UARTCKSEL,
 +        .divide = divide_by_reg_divisor,
 +        .reg = NPCM7XX_CLK_CLKDIV1,
 +        .offset = 16,
 +        .len = 5,
 +        .public_name = "uart-clock",
 +    },
 +    [NPCM7XX_CLOCK_TIMER_DIVIDER] = {
 +        .name = "timer-divider",
 +        .src_type = CLKSRC_SEL,
 +        .src_index = NPCM7XX_CLOCK_TIMCKSEL,
 +        .divide = divide_by_reg_divisor,
 +        .reg = NPCM7XX_CLK_CLKDIV1,
 +        .offset = 21,
 +        .len = 5,
 +        .public_name = "timer-clock",
 +    },
 +    [NPCM7XX_CLOCK_ADC_DIVIDER] = {
 +        .name = "adc-divider",
 +        .src_type = CLKSRC_DIV,
 +        .src_index = NPCM7XX_CLOCK_TIMER_DIVIDER,
 +        .divide = shift_by_reg_divisor,
 +        .reg = NPCM7XX_CLK_CLKDIV1,
 +        .offset = 28,
 +        .len = 3,
 +        .public_name = "adc-clock",
 +    },
 +    [NPCM7XX_CLOCK_MMC_DIVIDER] = {
 +        .name = "mmc-divider",
 +        .src_type = CLKSRC_SEL,
 +        .src_index = NPCM7XX_CLOCK_SDCKSEL,
 +        .divide = divide_by_reg_divisor,
 +        .reg = NPCM7XX_CLK_CLKDIV1,
 +        .offset = 11,
 +        .len = 5,
 +        .public_name = "mmc-clock",
 +    },
 +    [NPCM7XX_CLOCK_SDHC_DIVIDER] = {
 +        .name = "sdhc-divider",
 +        .src_type = CLKSRC_SEL,
 +        .src_index = NPCM7XX_CLOCK_SDCKSEL,
 +        .divide = divide_by_reg_divisor_times_2,
 +        .reg = NPCM7XX_CLK_CLKDIV2,
 +        .offset = 0,
 +        .len = 4,
 +        .public_name = "sdhc-clock",
 +    },
 +    [NPCM7XX_CLOCK_GFXM_DIVIDER] = {
 +        .name = "gfxm-divider",
 +        .src_type = CLKSRC_SEL,
 +        .src_index = NPCM7XX_CLOCK_GFXMSEL,
 +        .divide = divide_by_constant,
 +        .divisor = 3,
 +        .public_name = "gfxm-clock",
 +    },
 +    [NPCM7XX_CLOCK_UTMI_DIVIDER] = {
 +        .name = "utmi-divider",
 +        .src_type = CLKSRC_SEL,
 +        .src_index = NPCM7XX_CLOCK_SUCKSEL,
 +        .divide = divide_by_reg_divisor,
 +        .reg = NPCM7XX_CLK_CLKDIV2,
 +        .offset = 8,
 +        .len = 5,
 +        .public_name = "utmi-clock",
 +    },
 +};
 +
 +static void npcm7xx_clk_pll_init(Object *obj)
 +{
 +    NPCM7xxClockPLLState *pll = NPCM7XX_CLOCK_PLL(obj);
 +
 +    pll->clock_in = qdev_init_clock_in(DEVICE(pll), "clock-in",
 +            npcm7xx_clk_update_pll, pll);
 +    pll->clock_out = qdev_init_clock_out(DEVICE(pll), "clock-out");
 +}
 +
 +static void npcm7xx_clk_sel_init(Object *obj)
 +{
 +    int i;
 +    NPCM7xxClockSELState *sel = NPCM7XX_CLOCK_SEL(obj);
 +
 +    for (i = 0; i < NPCM7XX_CLK_SEL_MAX_INPUT; ++i) {
 +        sel->clock_in[i] = qdev_init_clock_in(DEVICE(sel),
 +                g_strdup_printf("clock-in[%d]", i),
 +                npcm7xx_clk_update_sel, sel);
 +    }
 +    sel->clock_out = qdev_init_clock_out(DEVICE(sel), "clock-out");
 +}
 +static void npcm7xx_clk_divider_init(Object *obj)
 +{
 +    NPCM7xxClockDividerState *div = NPCM7XX_CLOCK_DIVIDER(obj);
 +
 +    div->clock_in = qdev_init_clock_in(DEVICE(div), "clock-in",
 +            npcm7xx_clk_update_divider, div);
 +    div->clock_out = qdev_init_clock_out(DEVICE(div), "clock-out");
 +}
 +
 +static void npcm7xx_init_clock_pll(NPCM7xxClockPLLState *pll,
 +        NPCM7xxCLKState *clk, const PLLInitInfo *init_info)
 +{
 +    pll->name = init_info->name;
 +    pll->clk = clk;
 +    pll->reg = init_info->reg;
 +    if (init_info->public_name != NULL) {
 +        qdev_alias_clock(DEVICE(pll), "clock-out", DEVICE(clk),
 +                init_info->public_name);
 +    }
 +}
 +
 +static void npcm7xx_init_clock_sel(NPCM7xxClockSELState *sel,
 +        NPCM7xxCLKState *clk, const SELInitInfo *init_info)
 +{
 +    int input_size = init_info->input_size;
 +
 +    sel->name = init_info->name;
 +    sel->clk = clk;
 +    sel->input_size = init_info->input_size;
 +    g_assert(input_size <= NPCM7XX_CLK_SEL_MAX_INPUT);
 +    sel->offset = init_info->offset;
 +    sel->len = init_info->len;
 +    if (init_info->public_name != NULL) {
 +        qdev_alias_clock(DEVICE(sel), "clock-out", DEVICE(clk),
 +                init_info->public_name);
 +    }
 +}
 +
 +static void npcm7xx_init_clock_divider(NPCM7xxClockDividerState *div,
 +        NPCM7xxCLKState *clk, const DividerInitInfo *init_info)
 +{
 +    div->name = init_info->name;
 +    div->clk = clk;
 +
 +    div->divide = init_info->divide;
 +    if (div->divide == divide_by_constant) {
 +        div->divisor = init_info->divisor;
 +    } else {
 +        div->reg = init_info->reg;
 +        div->offset = init_info->offset;
 +        div->len = init_info->len;
 +    }
 +    if (init_info->public_name != NULL) {
 +        qdev_alias_clock(DEVICE(div), "clock-out", DEVICE(clk),
 +                init_info->public_name);
 +    }
 +}
 +
 +static Clock *npcm7xx_get_clock(NPCM7xxCLKState *clk, ClockSrcType type,
 +        int index)
 +{
 +    switch (type) {
 +    case CLKSRC_REF:
 +        return clk->clkref;
 +    case CLKSRC_PLL:
 +        return clk->plls[index].clock_out;
 +    case CLKSRC_SEL:
 +        return clk->sels[index].clock_out;
 +    case CLKSRC_DIV:
 +        return clk->dividers[index].clock_out;
 +    default:
 +        g_assert_not_reached();
 +    }
 +}
 +
 +static void npcm7xx_connect_clocks(NPCM7xxCLKState *clk)
 +{
 +    int i, j;
 +    Clock *src;
 +
 +    for (i = 0; i < NPCM7XX_CLOCK_NR_PLLS; ++i) {
 +        src = npcm7xx_get_clock(clk, pll_init_info_list[i].src_type,
 +                pll_init_info_list[i].src_index);
 +        clock_set_source(clk->plls[i].clock_in, src);
 +    }
 +    for (i = 0; i < NPCM7XX_CLOCK_NR_SELS; ++i) {
 +        for (j = 0; j < sel_init_info_list[i].input_size; ++j) {
 +            src = npcm7xx_get_clock(clk, sel_init_info_list[i].src_type[j],
 +                    sel_init_info_list[i].src_index[j]);
 +            clock_set_source(clk->sels[i].clock_in[j], src);
 +        }
 +    }
 +    for (i = 0; i < NPCM7XX_CLOCK_NR_DIVIDERS; ++i) {
 +        src = npcm7xx_get_clock(clk, divider_init_info_list[i].src_type,
 +                divider_init_info_list[i].src_index);
 +        clock_set_source(clk->dividers[i].clock_in, src);
 +    }
 +}
 +
  static uint64_t npcm7xx_clk_read(void *opaque, hwaddr offset, unsigned size)
  {
-     uint32_t reg = offset / sizeof(uint32_t);
+-    free(r->ds.toc);
-@@ -XXX,XX +XXX,XX @@ static uint64_t npcm7xx_clk_read(void *opaque, hwaddr offset, unsigned size)
++    g_free(r->ds.toc);
           *
           * The 4 LSBs are always zero: (1e9 / 640) << 4 = 25000000.
           */
 -        value = (((now_ns - s->ref_ns) / 640) << 4) % NPCM7XX_TIMER_REF_HZ;
 +        value = (((now_ns - s->ref_ns) / 640) << 4) % NPCM7XX_CLOCK_REF_HZ;
          break;
      default:
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_clk_write(void *opaque, hwaddr offset,
                  value |= (value & PLLCON_LOKS);
              }
          }
 +        /* Only update PLL when it is locked. */
 +        if (value & PLLCON_LOKI) {
 +            npcm7xx_clk_update_pll(&s->plls[find_pll_by_reg(reg)]);
 +        }
 +        break;
 +
 +    case NPCM7XX_CLK_CLKSEL:
 +        npcm7xx_clk_update_all_sels(s);
 +        break;
 +
 +    case NPCM7XX_CLK_CLKDIV1:
 +    case NPCM7XX_CLK_CLKDIV2:
 +    case NPCM7XX_CLK_CLKDIV3:
 +        npcm7xx_clk_update_all_dividers(s);
          break;
      case NPCM7XX_CLK_CNTR25M:
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_clk_enter_reset(Object *obj, ResetType type)
      case RESET_TYPE_COLD:
          memcpy(s->regs, cold_reset_values, sizeof(cold_reset_values));
          s->ref_ns = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
 +        npcm7xx_clk_update_all_clocks(s);
          return;
      }
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_clk_enter_reset(Object *obj, ResetType type)
                    __func__, type);
  }
-+static void npcm7xx_clk_init_clock_hierarchy(NPCM7xxCLKState *s)
+ static void pdb_exit_symbols(struct pdb_reader *r)
 +{
 +    int i;
 +
 +    s->clkref = qdev_init_clock_in(DEVICE(s), "clkref", NULL, NULL);
 +
 +    /* First pass: init all converter modules */
 +    QEMU_BUILD_BUG_ON(ARRAY_SIZE(pll_init_info_list) != NPCM7XX_CLOCK_NR_PLLS);
 +    QEMU_BUILD_BUG_ON(ARRAY_SIZE(sel_init_info_list) != NPCM7XX_CLOCK_NR_SELS);
 +    QEMU_BUILD_BUG_ON(ARRAY_SIZE(divider_init_info_list)
 +            != NPCM7XX_CLOCK_NR_DIVIDERS);
 +    for (i = 0; i < NPCM7XX_CLOCK_NR_PLLS; ++i) {
 +        object_initialize_child(OBJECT(s), pll_init_info_list[i].name,
 +                &s->plls[i], TYPE_NPCM7XX_CLOCK_PLL);
 +        npcm7xx_init_clock_pll(&s->plls[i], s,
 +                &pll_init_info_list[i]);
 +    }
 +    for (i = 0; i < NPCM7XX_CLOCK_NR_SELS; ++i) {
 +        object_initialize_child(OBJECT(s), sel_init_info_list[i].name,
 +                &s->sels[i], TYPE_NPCM7XX_CLOCK_SEL);
 +        npcm7xx_init_clock_sel(&s->sels[i], s,
 +                &sel_init_info_list[i]);
 +    }
 +    for (i = 0; i < NPCM7XX_CLOCK_NR_DIVIDERS; ++i) {
 +        object_initialize_child(OBJECT(s), divider_init_info_list[i].name,
 +                &s->dividers[i], TYPE_NPCM7XX_CLOCK_DIVIDER);
 +        npcm7xx_init_clock_divider(&s->dividers[i], s,
 +                &divider_init_info_list[i]);
 +    }
 +
 +    /* Second pass: connect converter modules */
 +    npcm7xx_connect_clocks(s);
 +
 +    clock_update_hz(s->clkref, NPCM7XX_CLOCK_REF_HZ);
 +}
 +
  static void npcm7xx_clk_init(Object *obj)
  {
-     NPCM7xxCLKState *s = NPCM7XX_CLK(obj);
+-    free(r->modimage);
-@@ -XXX,XX +XXX,XX @@ static void npcm7xx_clk_init(Object *obj)
+-    free(r->symbols);
-     memory_region_init_io(&s->iomem, obj, &npcm7xx_clk_ops, s,
++    g_free(r->modimage);
-                           TYPE_NPCM7XX_CLK, 4 * KiB);
++    g_free(r->symbols);
      sysbus_init_mmio(&s->parent, &s->iomem);
 -    qdev_init_gpio_in_named(DEVICE(s), npcm7xx_clk_perform_watchdog_reset,
 -            NPCM7XX_WATCHDOG_RESET_GPIO_IN, NPCM7XX_NR_WATCHDOGS);
  }
--static const VMStateDescription vmstate_npcm7xx_clk = {
+ static void pdb_exit_segments(struct pdb_reader *r)
 -    .name = "npcm7xx-clk",
 +static int npcm7xx_clk_post_load(void *opaque, int version_id)
 +{
 +    if (version_id >= 1) {
 +        NPCM7xxCLKState *clk = opaque;
 +
 +        npcm7xx_clk_update_all_clocks(clk);
 +    }
 +
 +    return 0;
 +}
 +
 +static void npcm7xx_clk_realize(DeviceState *dev, Error **errp)
 +{
 +    int i;
 +    NPCM7xxCLKState *s = NPCM7XX_CLK(dev);
 +
 +    qdev_init_gpio_in_named(DEVICE(s), npcm7xx_clk_perform_watchdog_reset,
 +            NPCM7XX_WATCHDOG_RESET_GPIO_IN, NPCM7XX_NR_WATCHDOGS);
 +    npcm7xx_clk_init_clock_hierarchy(s);
 +
 +    /* Realize child devices */
 +    for (i = 0; i < NPCM7XX_CLOCK_NR_PLLS; ++i) {
 +        if (!qdev_realize(DEVICE(&s->plls[i]), NULL, errp)) {
 +            return;
 +        }
 +    }
 +    for (i = 0; i < NPCM7XX_CLOCK_NR_SELS; ++i) {
 +        if (!qdev_realize(DEVICE(&s->sels[i]), NULL, errp)) {
 +            return;
 +        }
 +    }
 +    for (i = 0; i < NPCM7XX_CLOCK_NR_DIVIDERS; ++i) {
 +        if (!qdev_realize(DEVICE(&s->dividers[i]), NULL, errp)) {
 +            return;
 +        }
 +    }
 +}
 +
 +static const VMStateDescription vmstate_npcm7xx_clk_pll = {
 +    .name = "npcm7xx-clock-pll",
      .version_id = 0,
      .minimum_version_id = 0,
 -    .fields = (VMStateField[]) {
 -        VMSTATE_UINT32_ARRAY(regs, NPCM7xxCLKState, NPCM7XX_CLK_NR_REGS),
 -        VMSTATE_INT64(ref_ns, NPCM7xxCLKState),
 +    .fields =  (VMStateField[]) {
 +        VMSTATE_CLOCK(clock_in, NPCM7xxClockPLLState),
          VMSTATE_END_OF_LIST(),
      },
  };
 +static const VMStateDescription vmstate_npcm7xx_clk_sel = {
 +    .name = "npcm7xx-clock-sel",
 +    .version_id = 0,
 +    .minimum_version_id = 0,
 +    .fields =  (VMStateField[]) {
 +        VMSTATE_ARRAY_OF_POINTER_TO_STRUCT(clock_in, NPCM7xxClockSELState,
 +                NPCM7XX_CLK_SEL_MAX_INPUT, 0, vmstate_clock, Clock),
 +        VMSTATE_END_OF_LIST(),
 +    },
 +};
 +
 +static const VMStateDescription vmstate_npcm7xx_clk_divider = {
 +    .name = "npcm7xx-clock-divider",
 +    .version_id = 0,
 +    .minimum_version_id = 0,
 +    .fields =  (VMStateField[]) {
 +        VMSTATE_CLOCK(clock_in, NPCM7xxClockDividerState),
 +        VMSTATE_END_OF_LIST(),
 +    },
 +};
 +
 +static const VMStateDescription vmstate_npcm7xx_clk = {
 +    .name = "npcm7xx-clk",
 +    .version_id = 1,
 +    .minimum_version_id = 1,
 +    .post_load = npcm7xx_clk_post_load,
 +    .fields = (VMStateField[]) {
 +        VMSTATE_UINT32_ARRAY(regs, NPCM7xxCLKState, NPCM7XX_CLK_NR_REGS),
 +        VMSTATE_INT64(ref_ns, NPCM7xxCLKState),
 +        VMSTATE_CLOCK(clkref, NPCM7xxCLKState),
 +        VMSTATE_END_OF_LIST(),
 +    },
 +};
 +
 +static void npcm7xx_clk_pll_class_init(ObjectClass *klass, void *data)
 +{
 +    DeviceClass *dc = DEVICE_CLASS(klass);
 +
 +    dc->desc = "NPCM7xx Clock PLL Module";
 +    dc->vmsd = &vmstate_npcm7xx_clk_pll;
 +}
 +
 +static void npcm7xx_clk_sel_class_init(ObjectClass *klass, void *data)
 +{
 +    DeviceClass *dc = DEVICE_CLASS(klass);
 +
 +    dc->desc = "NPCM7xx Clock SEL Module";
 +    dc->vmsd = &vmstate_npcm7xx_clk_sel;
 +}
 +
 +static void npcm7xx_clk_divider_class_init(ObjectClass *klass, void *data)
 +{
 +    DeviceClass *dc = DEVICE_CLASS(klass);
 +
 +    dc->desc = "NPCM7xx Clock Divider Module";
 +    dc->vmsd = &vmstate_npcm7xx_clk_divider;
 +}
 +
  static void npcm7xx_clk_class_init(ObjectClass *klass, void *data)
  {
-     ResettableClass *rc = RESETTABLE_CLASS(klass);
+-    free(r->segs);
-@@ -XXX,XX +XXX,XX @@ static void npcm7xx_clk_class_init(ObjectClass *klass, void *data)
++    g_free(r->segs);
      dc->desc = "NPCM7xx Clock Control Registers";
      dc->vmsd = &vmstate_npcm7xx_clk;
 +    dc->realize = npcm7xx_clk_realize;
      rc->phases.enter = npcm7xx_clk_enter_reset;
  }
-+static const TypeInfo npcm7xx_clk_pll_info = {
+ static void *pdb_ds_read(const PDB_DS_HEADER *header,
-+    .name               = TYPE_NPCM7XX_CLOCK_PLL,
+@@ -XXX,XX +XXX,XX @@ static void *pdb_ds_read(const PDB_DS_HEADER *header,
-+    .parent             = TYPE_DEVICE,
-+    .instance_size      = sizeof(NPCM7xxClockPLLState),
+     nBlocks = (size + header->block_size - 1) / header->block_size;
-+    .instance_init      = npcm7xx_clk_pll_init,
-+    .class_init         = npcm7xx_clk_pll_class_init,
+-    buffer = malloc(nBlocks * header->block_size);
-+};
+-    if (!buffer) {
-+
+-        return NULL;
-+static const TypeInfo npcm7xx_clk_sel_info = {
+-    }
-+    .name               = TYPE_NPCM7XX_CLOCK_SEL,
++    buffer = g_malloc(nBlocks * header->block_size);
-+    .parent             = TYPE_DEVICE,
-+    .instance_size      = sizeof(NPCM7xxClockSELState),
+     for (i = 0; i < nBlocks; i++) {
-+    .instance_init      = npcm7xx_clk_sel_init,
+         memcpy(buffer + i * header->block_size, (const char *)header +
-+    .class_init         = npcm7xx_clk_sel_class_init,
+@@ -XXX,XX +XXX,XX @@ static int pdb_init_symbols(struct pdb_reader *r)
-+};
+     return 0;
-+
-+static const TypeInfo npcm7xx_clk_divider_info = {
+ out_symbols:
-+    .name               = TYPE_NPCM7XX_CLOCK_DIVIDER,
+-    free(symbols);
-+    .parent             = TYPE_DEVICE,
++    g_free(symbols);
-+    .instance_size      = sizeof(NPCM7xxClockDividerState),
-+    .instance_init      = npcm7xx_clk_divider_init,
+     return err;
-+    .class_init         = npcm7xx_clk_divider_class_init,
+ }
-+};
+@@ -XXX,XX +XXX,XX @@ static int pdb_reader_init(struct pdb_reader *r, void *data)
-+
+ out_sym:
- static const TypeInfo npcm7xx_clk_info = {
+     pdb_exit_symbols(r);
-     .name               = TYPE_NPCM7XX_CLK,
+ out_root:
-     .parent             = TYPE_SYS_BUS_DEVICE,
+-    free(r->ds.root);
-@@ -XXX,XX +XXX,XX @@ static const TypeInfo npcm7xx_clk_info = {
++    g_free(r->ds.root);
+ out_ds:
- static void npcm7xx_clk_register_type(void)
+     pdb_reader_ds_exit(r);
@@ -XXX,XX +XXX,XX @@ static void pdb_reader_exit(struct pdb_reader *r)
  {
-+    type_register_static(&npcm7xx_clk_pll_info);
+     pdb_exit_segments(r);
-+    type_register_static(&npcm7xx_clk_sel_info);
+     pdb_exit_symbols(r);
-+    type_register_static(&npcm7xx_clk_divider_info);
+-    free(r->ds.root);
-     type_register_static(&npcm7xx_clk_info);
++    g_free(r->ds.root);
      pdb_reader_ds_exit(r);
  }
- type_init(npcm7xx_clk_register_type);
 diff --git a/contrib/elf2dmp/qemu_elf.c b/contrib/elf2dmp/qemu_elf.c
 index XXXXXXX..XXXXXXX 100644
 --- a/contrib/elf2dmp/qemu_elf.c
 +++ b/contrib/elf2dmp/qemu_elf.c
@@ -XXX,XX +XXX,XX @@ static int init_states(QEMU_Elf *qe)
      printf("%zu CPU states has been found\n", cpu_nr);
 -    qe->state = malloc(sizeof(*qe->state) * cpu_nr);
 -    if (!qe->state) {
 -        return 1;
 -    }
 +    qe->state = g_new(QEMUCPUState*, cpu_nr);
      cpu_nr = 0;
@@ -XXX,XX +XXX,XX @@ static int init_states(QEMU_Elf *qe)
  static void exit_states(QEMU_Elf *qe)
  {
 -    free(qe->state);
 +    g_free(qe->state);
  }
  static bool check_ehdr(QEMU_Elf *qe)
 --
-.20.1
+.34.1

Arm queue; not huge but I figured I might as well send it out since
I've been doing code review today and there's no queue of unprocessed
pullreqs...

thanks
-- PMM

The following changes since commit b3f846c59d8405bb87c551187721fc92ff2f1b92:

Merge remote-tracking branch 'remotes/huth-gitlab/tags/pull-request-2021-01-11v2' into staging (2021-01-11 15:15:35 +0000)

are available in the Git repository at:

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210112

for you to fetch changes up to 19d131395ccaf503db21dadd8257e6dc9fc1d7de:

ui/cocoa: Fix openFile: deprecation on Big Sur (2021-01-12 11:38:37 +0000)

----------------------------------------------------------------
target-arm queue:
 * arm: Support emulation of ARMv8.4-TTST extension
 * arm: Update cpu.h ID register field definitions
 * arm: Fix breakage of XScale instruction emulation
 * hw/net/lan9118: Fix RX Status FIFO PEEK value
 * npcm7xx: Add ADC and PWM emulation
 * ui/cocoa: Make "open docs" help menu entry work again when binary
   is run from the build tree
 * ui/cocoa: Fix openFile: deprecation on Big Sur
 * docs: Add qemu-storage-daemon(1) manpage to meson.build
 * docs: Build and install all the docs in a single manual

----------------------------------------------------------------
Hao Wu (6):
      hw/misc: Add clock converter in NPCM7XX CLK module
      hw/timer: Refactor NPCM7XX Timer to use CLK clock
      hw/adc: Add an ADC module for NPCM7XX
      hw/misc: Add a PWM module for NPCM7XX
      hw/misc: Add QTest for NPCM7XX PWM Module
      hw/*: Use type casting for SysBusDevice in NPCM7XX

Leif Lindholm (6):
      target/arm: fix typo in cpu.h ID_AA64PFR1 field name
      target/arm: make ARMCPU.clidr 64-bit
      target/arm: make ARMCPU.ctr 64-bit
      target/arm: add descriptions of CLIDR_EL1, CCSIDR_EL1, CTR_EL0 to cpu.h
      target/arm: add aarch64 ID register fields to cpu.h
      target/arm: add aarch32 ID register fields to cpu.h

Peter Maydell (5):
      docs: Add qemu-storage-daemon(1) manpage to meson.build
      docs: Build and install all the docs in a single manual
      target/arm: Don't decode insns in the XScale/iWMMXt space as cp insns
      hw/net/lan9118: Fix RX Status FIFO PEEK value
      hw/net/lan9118: Add symbolic constants for register offsets

Roman Bolshakov (2):
      ui/cocoa: Update path to docs in build tree
      ui/cocoa: Fix openFile: deprecation on Big Sur

Rémi Denis-Courmont (2):
      target/arm: ARMv8.4-TTST extension
      target/arm: enable Small Translation tables in max CPU

docs/conf.py                     |  46 ++-
 docs/devel/conf.py               |  15 -
 docs/index.html.in               |  17 -
 docs/interop/conf.py             |  28 --
 docs/meson.build                 |  65 ++--
 docs/specs/conf.py               |  16 -
 docs/system/arm/nuvoton.rst      |   4 +-
 docs/system/conf.py              |  28 --
 docs/tools/conf.py               |  37 --
 docs/user/conf.py                |  15 -
 meson.build                      |   1 +
 hw/adc/trace.h                   |   1 +
 include/hw/adc/npcm7xx_adc.h     |  69 ++++
 include/hw/arm/npcm7xx.h         |   4 +
 include/hw/misc/npcm7xx_clk.h    | 146 ++++++-
 include/hw/misc/npcm7xx_pwm.h    | 105 +++++
 include/hw/timer/npcm7xx_timer.h |   1 +
 target/arm/cpu.h                 |  85 ++++-
 hw/adc/npcm7xx_adc.c             | 301 +++++++++++++++
 hw/arm/npcm7xx.c                 |  55 ++-
 hw/arm/npcm7xx_boards.c          |   2 +-
 hw/mem/npcm7xx_mc.c              |   2 +-
 hw/misc/npcm7xx_clk.c            | 807 ++++++++++++++++++++++++++++++++++++++-
 hw/misc/npcm7xx_gcr.c            |   2 +-
 hw/misc/npcm7xx_pwm.c            | 550 ++++++++++++++++++++++++++
 hw/misc/npcm7xx_rng.c            |   2 +-
 hw/net/lan9118.c                 |  26 +-
 hw/nvram/npcm7xx_otp.c           |   2 +-
 hw/ssi/npcm7xx_fiu.c             |   2 +-
 hw/timer/npcm7xx_timer.c         |  39 +-
 target/arm/cpu64.c               |   1 +
 target/arm/helper.c              |  15 +-
 target/arm/translate.c           |   7 +
 tests/qtest/npcm7xx_adc-test.c   | 377 ++++++++++++++++++
 tests/qtest/npcm7xx_pwm-test.c   | 490 ++++++++++++++++++++++++
 hw/adc/meson.build               |   1 +
 hw/adc/trace-events              |   5 +
 hw/misc/meson.build              |   1 +
 hw/misc/trace-events             |   6 +
 tests/qtest/meson.build          |   4 +-
 ui/cocoa.m                       |   7 +-
 41 files changed, 3124 insertions(+), 263 deletions(-)
 delete mode 100644 docs/devel/conf.py
 delete mode 100644 docs/index.html.in
 delete mode 100644 docs/interop/conf.py
 delete mode 100644 docs/specs/conf.py
 delete mode 100644 docs/system/conf.py
 delete mode 100644 docs/tools/conf.py
 delete mode 100644 docs/user/conf.py
 create mode 100644 hw/adc/trace.h
 create mode 100644 include/hw/adc/npcm7xx_adc.h
 create mode 100644 include/hw/misc/npcm7xx_pwm.h
 create mode 100644 hw/adc/npcm7xx_adc.c
 create mode 100644 hw/misc/npcm7xx_pwm.c
 create mode 100644 tests/qtest/npcm7xx_adc-test.c
 create mode 100644 tests/qtest/npcm7xx_pwm-test.c
 create mode 100644 hw/adc/trace-events

From: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>

This adds for the Small Translation tables extension in AArch64 state.

Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.h    |  5 +++++
 target/arm/helper.c | 15 +++++++++++++--
 2 files changed, 18 insertions(+), 2 deletions(-)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_uao(const ARMISARegisters *id)
     return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, UAO) != 0;
 }
 
+static inline bool isar_feature_aa64_st(const ARMISARegisters *id)
+{
+    return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, ST) != 0;
+}
+
 static inline bool isar_feature_aa64_bti(const ARMISARegisters *id)
 {
     return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) != 0;
diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
 {
     uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr;
     bool epd, hpd, using16k, using64k;
-    int select, tsz, tbi;
+    int select, tsz, tbi, max_tsz;
 
     if (!regime_has_2_ranges(mmu_idx)) {
         select = 0;
@@ -XXX,XX +XXX,XX @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
             hpd = extract64(tcr, 42, 1);
         }
     }
-    tsz = MIN(tsz, 39);  /* TODO: ARMv8.4-TTST */
+
+    if (cpu_isar_feature(aa64_st, env_archcpu(env))) {
+        max_tsz = 48 - using64k;
+    } else {
+        max_tsz = 39;
+    }
+
+    tsz = MIN(tsz, max_tsz);
     tsz = MAX(tsz, 16);  /* TODO: ARMv8.2-LVA  */
 
     /* Present TBI as a composite with TBID.  */
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address,
         if (!aarch64 || stride == 9) {
             /* AArch32 or 4KB pages */
             startlevel = 2 - sl0;
+
+            if (cpu_isar_feature(aa64_st, cpu)) {
+                startlevel &= 3;
+            }
         } else {
             /* 16KB or 64KB pages */
             startlevel = 3 - sl0;
-- 
2.20.1

From: Leif Lindholm <leif@nuviainc.com>

The AArch64 view of CLIDR_EL1 extends the ICB field to include also bit
32, as well as adding a Ttype<n> field when FEAT_MTE is implemented.
Extend the clidr field to be able to hold this context.

Signed-off-by: Leif Lindholm <leif@nuviainc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Message-id: 20210108185154.8108-3-leif@nuviainc.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ struct ARMCPU {
     uint32_t id_afr0;
     uint64_t id_aa64afr0;
     uint64_t id_aa64afr1;
-    uint32_t clidr;
+    uint64_t clidr;
     uint64_t mp_affinity; /* MP ID without feature bits */
     /* The elements of this array are the CCSIDR values for each cache,
      * in the order L1DCache, L1ICache, L2DCache, L2ICache, etc.
-- 
2.20.1

From: Leif Lindholm <leif@nuviainc.com>

Signed-off-by: Leif Lindholm <leif@nuviainc.com>
Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Message-id: 20210108185154.8108-5-leif@nuviainc.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.h | 31 +++++++++++++++++++++++++++++++
 1 file changed, 31 insertions(+)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ FIELD(V7M_FPCCR, ASPEN, 31, 1)
 /*
  * System register ID fields.
  */
+FIELD(CLIDR_EL1, CTYPE1, 0, 3)
+FIELD(CLIDR_EL1, CTYPE2, 3, 3)
+FIELD(CLIDR_EL1, CTYPE3, 6, 3)
+FIELD(CLIDR_EL1, CTYPE4, 9, 3)
+FIELD(CLIDR_EL1, CTYPE5, 12, 3)
+FIELD(CLIDR_EL1, CTYPE6, 15, 3)
+FIELD(CLIDR_EL1, CTYPE7, 18, 3)
+FIELD(CLIDR_EL1, LOUIS, 21, 3)
+FIELD(CLIDR_EL1, LOC, 24, 3)
+FIELD(CLIDR_EL1, LOUU, 27, 3)
+FIELD(CLIDR_EL1, ICB, 30, 3)
+
+/* When FEAT_CCIDX is implemented */
+FIELD(CCSIDR_EL1, CCIDX_LINESIZE, 0, 3)
+FIELD(CCSIDR_EL1, CCIDX_ASSOCIATIVITY, 3, 21)
+FIELD(CCSIDR_EL1, CCIDX_NUMSETS, 32, 24)
+
+/* When FEAT_CCIDX is not implemented */
+FIELD(CCSIDR_EL1, LINESIZE, 0, 3)
+FIELD(CCSIDR_EL1, ASSOCIATIVITY, 3, 10)
+FIELD(CCSIDR_EL1, NUMSETS, 13, 15)
+
+FIELD(CTR_EL0,  IMINLINE, 0, 4)
+FIELD(CTR_EL0,  L1IP, 14, 2)
+FIELD(CTR_EL0,  DMINLINE, 16, 4)
+FIELD(CTR_EL0,  ERG, 20, 4)
+FIELD(CTR_EL0,  CWG, 24, 4)
+FIELD(CTR_EL0,  IDC, 28, 1)
+FIELD(CTR_EL0,  DIC, 29, 1)
+FIELD(CTR_EL0,  TMINLINE, 32, 6)
+
 FIELD(MIDR_EL1, REVISION, 0, 4)
 FIELD(MIDR_EL1, PARTNUM, 4, 12)
 FIELD(MIDR_EL1, ARCHITECTURE, 16, 4)
-- 
2.20.1

From: Leif Lindholm <leif@nuviainc.com>

Add entries present in ARM DDI 0487F.c (August 2020).

Signed-off-by: Leif Lindholm <leif@nuviainc.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Message-id: 20210108185154.8108-6-leif@nuviainc.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.h | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ FIELD(ID_AA64ISAR1, GPI, 28, 4)
 FIELD(ID_AA64ISAR1, FRINTTS, 32, 4)
 FIELD(ID_AA64ISAR1, SB, 36, 4)
 FIELD(ID_AA64ISAR1, SPECRES, 40, 4)
+FIELD(ID_AA64ISAR1, BF16, 44, 4)
+FIELD(ID_AA64ISAR1, DGH, 48, 4)
+FIELD(ID_AA64ISAR1, I8MM, 52, 4)
 
 FIELD(ID_AA64PFR0, EL0, 0, 4)
 FIELD(ID_AA64PFR0, EL1, 4, 4)
@@ -XXX,XX +XXX,XX @@ FIELD(ID_AA64PFR0, ADVSIMD, 20, 4)
 FIELD(ID_AA64PFR0, GIC, 24, 4)
 FIELD(ID_AA64PFR0, RAS, 28, 4)
 FIELD(ID_AA64PFR0, SVE, 32, 4)
+FIELD(ID_AA64PFR0, SEL2, 36, 4)
+FIELD(ID_AA64PFR0, MPAM, 40, 4)
+FIELD(ID_AA64PFR0, AMU, 44, 4)
+FIELD(ID_AA64PFR0, DIT, 48, 4)
+FIELD(ID_AA64PFR0, CSV2, 56, 4)
+FIELD(ID_AA64PFR0, CSV3, 60, 4)
 
 FIELD(ID_AA64PFR1, BT, 0, 4)
 FIELD(ID_AA64PFR1, SSBS, 4, 4)
 FIELD(ID_AA64PFR1, MTE, 8, 4)
 FIELD(ID_AA64PFR1, RAS_FRAC, 12, 4)
+FIELD(ID_AA64PFR1, MPAM_FRAC, 16, 4)
 
 FIELD(ID_AA64MMFR0, PARANGE, 0, 4)
 FIELD(ID_AA64MMFR0, ASIDBITS, 4, 4)
@@ -XXX,XX +XXX,XX @@ FIELD(ID_AA64MMFR0, TGRAN16_2, 32, 4)
 FIELD(ID_AA64MMFR0, TGRAN64_2, 36, 4)
 FIELD(ID_AA64MMFR0, TGRAN4_2, 40, 4)
 FIELD(ID_AA64MMFR0, EXS, 44, 4)
+FIELD(ID_AA64MMFR0, FGT, 56, 4)
+FIELD(ID_AA64MMFR0, ECV, 60, 4)
 
 FIELD(ID_AA64MMFR1, HAFDBS, 0, 4)
 FIELD(ID_AA64MMFR1, VMIDBITS, 4, 4)
@@ -XXX,XX +XXX,XX @@ FIELD(ID_AA64MMFR1, LO, 16, 4)
 FIELD(ID_AA64MMFR1, PAN, 20, 4)
 FIELD(ID_AA64MMFR1, SPECSEI, 24, 4)
 FIELD(ID_AA64MMFR1, XNX, 28, 4)
+FIELD(ID_AA64MMFR1, TWED, 32, 4)
+FIELD(ID_AA64MMFR1, ETS, 36, 4)
 
 FIELD(ID_AA64MMFR2, CNP, 0, 4)
 FIELD(ID_AA64MMFR2, UAO, 4, 4)
@@ -XXX,XX +XXX,XX @@ FIELD(ID_AA64DFR0, CTX_CMPS, 28, 4)
 FIELD(ID_AA64DFR0, PMSVER, 32, 4)
 FIELD(ID_AA64DFR0, DOUBLELOCK, 36, 4)
 FIELD(ID_AA64DFR0, TRACEFILT, 40, 4)
+FIELD(ID_AA64DFR0, MTPMU, 48, 4)
 
 FIELD(ID_DFR0, COPDBG, 0, 4)
 FIELD(ID_DFR0, COPSDBG, 4, 4)
-- 
2.20.1

From: Leif Lindholm <leif@nuviainc.com>

Add entries present in ARM DDI 0487F.c (August 2020).

Signed-off-by: Leif Lindholm <leif@nuviainc.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Message-id: 20210108185154.8108-7-leif@nuviainc.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.h | 28 ++++++++++++++++++++++++++++
 1 file changed, 28 insertions(+)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ FIELD(ID_ISAR6, DP, 4, 4)
 FIELD(ID_ISAR6, FHM, 8, 4)
 FIELD(ID_ISAR6, SB, 12, 4)
 FIELD(ID_ISAR6, SPECRES, 16, 4)
+FIELD(ID_ISAR6, BF16, 20, 4)
+FIELD(ID_ISAR6, I8MM, 24, 4)
 
 FIELD(ID_MMFR0, VMSA, 0, 4)
 FIELD(ID_MMFR0, PMSA, 4, 4)
@@ -XXX,XX +XXX,XX @@ FIELD(ID_MMFR0, AUXREG, 20, 4)
 FIELD(ID_MMFR0, FCSE, 24, 4)
 FIELD(ID_MMFR0, INNERSHR, 28, 4)
 
+FIELD(ID_MMFR1, L1HVDVA, 0, 4)
+FIELD(ID_MMFR1, L1UNIVA, 4, 4)
+FIELD(ID_MMFR1, L1HVDSW, 8, 4)
+FIELD(ID_MMFR1, L1UNISW, 12, 4)
+FIELD(ID_MMFR1, L1HVD, 16, 4)
+FIELD(ID_MMFR1, L1UNI, 20, 4)
+FIELD(ID_MMFR1, L1TSTCLN, 24, 4)
+FIELD(ID_MMFR1, BPRED, 28, 4)
+
+FIELD(ID_MMFR2, L1HVDFG, 0, 4)
+FIELD(ID_MMFR2, L1HVDBG, 4, 4)
+FIELD(ID_MMFR2, L1HVDRNG, 8, 4)
+FIELD(ID_MMFR2, HVDTLB, 12, 4)
+FIELD(ID_MMFR2, UNITLB, 16, 4)
+FIELD(ID_MMFR2, MEMBARR, 20, 4)
+FIELD(ID_MMFR2, WFISTALL, 24, 4)
+FIELD(ID_MMFR2, HWACCFLG, 28, 4)
+
 FIELD(ID_MMFR3, CMAINTVA, 0, 4)
 FIELD(ID_MMFR3, CMAINTSW, 4, 4)
 FIELD(ID_MMFR3, BPMAINT, 8, 4)
@@ -XXX,XX +XXX,XX @@ FIELD(ID_MMFR4, LSM, 20, 4)
 FIELD(ID_MMFR4, CCIDX, 24, 4)
 FIELD(ID_MMFR4, EVT, 28, 4)
 
+FIELD(ID_MMFR5, ETS, 0, 4)
+
 FIELD(ID_PFR0, STATE0, 0, 4)
 FIELD(ID_PFR0, STATE1, 4, 4)
 FIELD(ID_PFR0, STATE2, 8, 4)
@@ -XXX,XX +XXX,XX @@ FIELD(ID_PFR1, SEC_FRAC, 20, 4)
 FIELD(ID_PFR1, VIRT_FRAC, 24, 4)
 FIELD(ID_PFR1, GIC, 28, 4)
 
+FIELD(ID_PFR2, CSV3, 0, 4)
+FIELD(ID_PFR2, SSBS, 4, 4)
+FIELD(ID_PFR2, RAS_FRAC, 8, 4)
+
 FIELD(ID_AA64ISAR0, AES, 4, 4)
 FIELD(ID_AA64ISAR0, SHA1, 8, 4)
 FIELD(ID_AA64ISAR0, SHA2, 12, 4)
@@ -XXX,XX +XXX,XX @@ FIELD(ID_DFR0, MPROFDBG, 20, 4)
 FIELD(ID_DFR0, PERFMON, 24, 4)
 FIELD(ID_DFR0, TRACEFILT, 28, 4)
 
+FIELD(ID_DFR1, MTPMU, 0, 4)
+
 FIELD(DBGDIDR, SE_IMP, 12, 1)
 FIELD(DBGDIDR, NSUHD_IMP, 14, 1)
 FIELD(DBGDIDR, VERSION, 16, 4)
-- 
2.20.1

From: Roman Bolshakov <r.bolshakov@yadro.com>

QEMU documentation can't be opened if QEMU is run from build tree
because executables are placed in the top of build tree after conversion
to meson.

Signed-off-by: Roman Bolshakov <r.bolshakov@yadro.com>
Reported-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20210108213815.64678-1-r.bolshakov@yadro.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 ui/cocoa.m | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/ui/cocoa.m b/ui/cocoa.m
index XXXXXXX..XXXXXXX 100644
--- a/ui/cocoa.m
+++ b/ui/cocoa.m
@@ -XXX,XX +XXX,XX @@ QemuCocoaView *cocoaView;
 - (void) openDocumentation: (NSString *) filename
 {
     /* Where to look for local files */
-    NSString *path_array[] = {@"../share/doc/qemu/", @"../doc/qemu/", @"../docs/"};
+    NSString *path_array[] = {@"../share/doc/qemu/", @"../doc/qemu/", @"docs/"};
     NSString *full_file_path;
 
     /* iterate thru the possible paths until the file is found */
-- 
2.20.1

In commit 1982e1602d15 we added a new qemu-storage-daemon(1) manpage.
At the moment new manpages have to be listed both in the conf.py for
Sphinx and also in docs/meson.build for Meson. We forgot the second
of those -- correct the omission.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 20210108161416.21129-2-peter.maydell@linaro.org
---
 docs/meson.build | 1 +
 1 file changed, 1 insertion(+)

diff --git a/docs/meson.build b/docs/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/docs/meson.build
+++ b/docs/meson.build
@@ -XXX,XX +XXX,XX @@ if build_docs
         'qemu-img.1': (have_tools ? 'man1' : ''),
         'qemu-nbd.8': (have_tools ? 'man8' : ''),
         'qemu-pr-helper.8': (have_tools ? 'man8' : ''),
+        'qemu-storage-daemon.1': (have_tools ? 'man1' : ''),
         'qemu-trace-stap.1': (config_host.has_key('CONFIG_TRACE_SYSTEMTAP') ? 'man1' : ''),
         'virtfs-proxy-helper.1': (have_virtfs_proxy_helper ? 'man1' : ''),
         'virtiofsd.1': (have_virtiofsd ? 'man1' : ''),
-- 
2.20.1

When we first converted our documentation to Sphinx, we split it into
multiple manuals (system, interop, tools, etc), which are all built
separately.  The primary driver for this was wanting to be able to
avoid shipping the 'devel' manual to end-users.  However, this is
working against the grain of the way Sphinx wants to be used and
causes some annoyances:
 * Cross-references between documents become much harder or
   possibly impossible
 * There is no single index to the whole documentation
 * Within one manual there's no links or table-of-contents info
   that lets you easily navigate to the others
 * The devel manual doesn't get published on the QEMU website
   (it would be nice to able to refer to it there)

Merely hiding our developer documentation from end users seems like
it's not enough benefit for these costs.  Combine all the
documentation into a single manual (the same way that the readthedocs
site builds it) and install the whole thing.  The previous manual
divisions remain as the new top level sections in the manual.

* The per-manual conf.py files are no longer needed
 * The man_pages[] specifications previously in each per-manual
   conf.py move to the top level conf.py
 * docs/meson.build logic is simplified as we now only need to run
   Sphinx once for the HTML and then once for the manpages5B
 * The old index.html.in that produced the top-level page with
   links to each manual is no longer needed

Unfortunately this means that we now have to build the HTML
documentation into docs/manual in the build tree rather than directly
into docs/; otherwise it is too awkward to ensure we install only the
built manual and not also the dependency info, stamp file, etc.  The
manual still ends up in the same place in the final installed
directory, but anybody who was consulting documentation from within
the build tree will have to adjust where they're looking.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Message-id: 20210108161416.21129-3-peter.maydell@linaro.org
---
 docs/conf.py         | 46 ++++++++++++++++++++++++++++++-
 docs/devel/conf.py   | 15 -----------
 docs/index.html.in   | 17 ------------
 docs/interop/conf.py | 28 -------------------
 docs/meson.build     | 64 +++++++++++++++++---------------------------
 docs/specs/conf.py   | 16 -----------
 docs/system/conf.py  | 28 -------------------
 docs/tools/conf.py   | 37 -------------------------
 docs/user/conf.py    | 15 -----------
 9 files changed, 70 insertions(+), 196 deletions(-)
 delete mode 100644 docs/devel/conf.py
 delete mode 100644 docs/index.html.in
 delete mode 100644 docs/interop/conf.py
 delete mode 100644 docs/specs/conf.py
 delete mode 100644 docs/system/conf.py
 delete mode 100644 docs/tools/conf.py
 delete mode 100644 docs/user/conf.py

diff --git a/docs/conf.py b/docs/conf.py
index XXXXXXX..XXXXXXX 100644
--- a/docs/conf.py
+++ b/docs/conf.py
@@ -XXX,XX +XXX,XX @@ latex_documents = [
 
 # -- Options for manual page output ---------------------------------------
 # Individual manual/conf.py can override this to create man pages
-man_pages = []
+man_pages = [
+    ('interop/qemu-ga', 'qemu-ga',
+     'QEMU Guest Agent',
+     ['Michael Roth <mdroth@linux.vnet.ibm.com>'], 8),
+    ('interop/qemu-ga-ref', 'qemu-ga-ref',
+     'QEMU Guest Agent Protocol Reference',
+     [], 7),
+    ('interop/qemu-qmp-ref', 'qemu-qmp-ref',
+     'QEMU QMP Reference Manual',
+     [], 7),
+    ('interop/qemu-storage-daemon-qmp-ref', 'qemu-storage-daemon-qmp-ref',
+     'QEMU Storage Daemon QMP Reference Manual',
+     [], 7),
+    ('system/qemu-manpage', 'qemu',
+     'QEMU User Documentation',
+     ['Fabrice Bellard'], 1),
+    ('system/qemu-block-drivers', 'qemu-block-drivers',
+     'QEMU block drivers reference',
+     ['Fabrice Bellard and the QEMU Project developers'], 7),
+    ('system/qemu-cpu-models', 'qemu-cpu-models',
+     'QEMU CPU Models',
+     ['The QEMU Project developers'], 7),
+    ('tools/qemu-img', 'qemu-img',
+     'QEMU disk image utility',
+     ['Fabrice Bellard'], 1),
+    ('tools/qemu-nbd', 'qemu-nbd',
+     'QEMU Disk Network Block Device Server',
+     ['Anthony Liguori <anthony@codemonkey.ws>'], 8),
+    ('tools/qemu-pr-helper', 'qemu-pr-helper',
+     'QEMU persistent reservation helper',
+     [], 8),
+    ('tools/qemu-storage-daemon', 'qemu-storage-daemon',
+     'QEMU storage daemon',
+     [], 1),
+    ('tools/qemu-trace-stap', 'qemu-trace-stap',
+     'QEMU SystemTap trace tool',
+     [], 1),
+    ('tools/virtfs-proxy-helper', 'virtfs-proxy-helper',
+     'QEMU 9p virtfs proxy filesystem helper',
+     ['M. Mohan Kumar'], 1),
+    ('tools/virtiofsd', 'virtiofsd',
+     'QEMU virtio-fs shared file system daemon',
+     ['Stefan Hajnoczi <stefanha@redhat.com>',
+      'Masayoshi Mizuma <m.mizuma@jp.fujitsu.com>'], 1),
+]
 
 # -- Options for Texinfo output -------------------------------------------
 
diff --git a/docs/devel/conf.py b/docs/devel/conf.py
deleted file mode 100644
index XXXXXXX..XXXXXXX
--- a/docs/devel/conf.py
+++ /dev/null
@@ -XXX,XX +XXX,XX @@
-# -*- coding: utf-8 -*-
-#
-# QEMU documentation build configuration file for the 'devel' manual.
-#
-# This includes the top level conf file and then makes any necessary tweaks.
-import sys
-import os
-
-qemu_docdir = os.path.abspath("..")
-parent_config = os.path.join(qemu_docdir, "conf.py")
-exec(compile(open(parent_config, "rb").read(), parent_config, 'exec'))
-
-# This slightly misuses the 'description', but is the best way to get
-# the manual title to appear in the sidebar.
-html_theme_options['description'] = u'Developer''s Guide'
diff --git a/docs/index.html.in b/docs/index.html.in
deleted file mode 100644
index XXXXXXX..XXXXXXX
--- a/docs/index.html.in
+++ /dev/null
@@ -XXX,XX +XXX,XX @@
-<!DOCTYPE html>
-<html lang="en">
-    <head>
-        <meta charset="UTF-8">
-        <title>QEMU @VERSION@ Documentation</title>
-    </head>
-    <body>
-        <h1>QEMU @VERSION@ Documentation</h1>
-        <ul>
-            <li><a href="system/index.html">System Emulation User's Guide</a></li>
-            <li><a href="user/index.html">User Mode Emulation User's Guide</a></li>
-            <li><a href="tools/index.html">Tools Guide</a></li>
-            <li><a href="interop/index.html">System Emulation Management and Interoperability Guide</a></li>
-            <li><a href="specs/index.html">System Emulation Guest Hardware Specifications</a></li>
-        </ul>
-    </body>
-</html>
diff --git a/docs/interop/conf.py b/docs/interop/conf.py
deleted file mode 100644
index XXXXXXX..XXXXXXX
--- a/docs/interop/conf.py
+++ /dev/null
@@ -XXX,XX +XXX,XX @@
-# -*- coding: utf-8 -*-
-#
-# QEMU documentation build configuration file for the 'interop' manual.
-#
-# This includes the top level conf file and then makes any necessary tweaks.
-import sys
-import os
-
-qemu_docdir = os.path.abspath("..")
-parent_config = os.path.join(qemu_docdir, "conf.py")
-exec(compile(open(parent_config, "rb").read(), parent_config, 'exec'))
-
-# This slightly misuses the 'description', but is the best way to get
-# the manual title to appear in the sidebar.
-html_theme_options['description'] = u'System Emulation Management and Interoperability Guide'
-
-# One entry per manual page. List of tuples
-# (source start file, name, description, authors, manual section).
-man_pages = [
-    ('qemu-ga', 'qemu-ga', u'QEMU Guest Agent',
-     ['Michael Roth <mdroth@linux.vnet.ibm.com>'], 8),
-    ('qemu-ga-ref', 'qemu-ga-ref', 'QEMU Guest Agent Protocol Reference',
-     [], 7),
-    ('qemu-qmp-ref', 'qemu-qmp-ref', 'QEMU QMP Reference Manual',
-     [], 7),
-    ('qemu-storage-daemon-qmp-ref', 'qemu-storage-daemon-qmp-ref',
-     'QEMU Storage Daemon QMP Reference Manual', [], 7),
-]
diff --git a/docs/meson.build b/docs/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/docs/meson.build
+++ b/docs/meson.build
@@ -XXX,XX +XXX,XX @@ if build_docs
                           meson.source_root() / 'docs/sphinx/qmp_lexer.py',
                           qapi_gen_depends ]
 
-  configure_file(output: 'index.html',
-                 input: files('index.html.in'),
-                 configuration: {'VERSION': meson.project_version()},
-                 install_dir: qemu_docdir)
-  manuals = [ 'devel', 'interop', 'tools', 'specs', 'system', 'user' ]
   man_pages = {
-    'interop' : {
         'qemu-ga.8': (have_tools ? 'man8' : ''),
         'qemu-ga-ref.7': 'man7',
         'qemu-qmp-ref.7': 'man7',
         'qemu-storage-daemon-qmp-ref.7': (have_tools ? 'man7' : ''),
-    },
-    'tools': {
         'qemu-img.1': (have_tools ? 'man1' : ''),
         'qemu-nbd.8': (have_tools ? 'man8' : ''),
         'qemu-pr-helper.8': (have_tools ? 'man8' : ''),
@@ -XXX,XX +XXX,XX @@ if build_docs
         'qemu-trace-stap.1': (config_host.has_key('CONFIG_TRACE_SYSTEMTAP') ? 'man1' : ''),
         'virtfs-proxy-helper.1': (have_virtfs_proxy_helper ? 'man1' : ''),
         'virtiofsd.1': (have_virtiofsd ? 'man1' : ''),
-    },
-    'system': {
         'qemu.1': 'man1',
         'qemu-block-drivers.7': 'man7',
         'qemu-cpu-models.7': 'man7'
-    },
   }
 
   sphinxdocs = []
   sphinxmans = []
-  foreach manual : manuals
-    private_dir = meson.current_build_dir() / (manual + '.p')
-    output_dir = meson.current_build_dir() / manual
-    input_dir = meson.current_source_dir() / manual
 
-    this_manual = custom_target(manual + ' manual',
+  private_dir = meson.current_build_dir() / 'manual.p'
+  output_dir = meson.current_build_dir() / 'manual'
+  input_dir = meson.current_source_dir()
+
+  this_manual = custom_target('QEMU manual',
                 build_by_default: build_docs,
-                output: [manual + '.stamp'],
-                input: [files('conf.py'), files(manual / 'conf.py')],
-                depfile: manual + '.d',
+                output: 'docs.stamp',
+                input: files('conf.py'),
+                depfile: 'docs.d',
                 depend_files: sphinx_extn_depends,
                 command: [SPHINX_ARGS, '-Ddepfile=@DEPFILE@',
                           '-Ddepfile_stamp=@OUTPUT0@',
                           '-b', 'html', '-d', private_dir,
                           input_dir, output_dir])
-    sphinxdocs += this_manual
-    if build_docs and manual != 'devel'
-      install_subdir(output_dir, install_dir: qemu_docdir)
-    endif
+  sphinxdocs += this_manual
+  install_subdir(output_dir, install_dir: qemu_docdir, strip_directory: true)
 
-    these_man_pages = []
-    install_dirs = []
-    foreach page, section : man_pages.get(manual, {})
-      these_man_pages += page
-      install_dirs += section == '' ? false : get_option('mandir') / section
-    endforeach
-    if these_man_pages.length() > 0
-      sphinxmans += custom_target(manual + ' man pages',
-                         build_by_default: build_docs,
-                         output: these_man_pages,
-                         input: this_manual,
-                         install: build_docs,
-                         install_dir: install_dirs,
-                         command: [SPHINX_ARGS, '-b', 'man', '-d', private_dir,
-                                   input_dir, meson.current_build_dir()])
-    endif
+  these_man_pages = []
+  install_dirs = []
+  foreach page, section : man_pages
+    these_man_pages += page
+    install_dirs += section == '' ? false : get_option('mandir') / section
   endforeach
+
+  sphinxmans += custom_target('QEMU man pages',
+                              build_by_default: build_docs,
+                              output: these_man_pages,
+                              input: this_manual,
+                              install: build_docs,
+                              install_dir: install_dirs,
+                              command: [SPHINX_ARGS, '-b', 'man', '-d', private_dir,
+                                        input_dir, meson.current_build_dir()])
+
   alias_target('sphinxdocs', sphinxdocs)
   alias_target('html', sphinxdocs)
   alias_target('man', sphinxmans)
diff --git a/docs/specs/conf.py b/docs/specs/conf.py
deleted file mode 100644
index XXXXXXX..XXXXXXX
--- a/docs/specs/conf.py
+++ /dev/null
@@ -XXX,XX +XXX,XX @@
-# -*- coding: utf-8 -*-
-#
-# QEMU documentation build configuration file for the 'specs' manual.
-#
-# This includes the top level conf file and then makes any necessary tweaks.
-import sys
-import os
-
-qemu_docdir = os.path.abspath("..")
-parent_config = os.path.join(qemu_docdir, "conf.py")
-exec(compile(open(parent_config, "rb").read(), parent_config, 'exec'))
-
-# This slightly misuses the 'description', but is the best way to get
-# the manual title to appear in the sidebar.
-html_theme_options['description'] = \
-    u'System Emulation Guest Hardware Specifications'
diff --git a/docs/system/conf.py b/docs/system/conf.py
deleted file mode 100644
index XXXXXXX..XXXXXXX
--- a/docs/system/conf.py
+++ /dev/null
@@ -XXX,XX +XXX,XX @@
-# -*- coding: utf-8 -*-
-#
-# QEMU documentation build configuration file for the 'system' manual.
-#
-# This includes the top level conf file and then makes any necessary tweaks.
-import sys
-import os
-
-qemu_docdir = os.path.abspath("..")
-parent_config = os.path.join(qemu_docdir, "conf.py")
-exec(compile(open(parent_config, "rb").read(), parent_config, 'exec'))
-
-# This slightly misuses the 'description', but is the best way to get
-# the manual title to appear in the sidebar.
-html_theme_options['description'] = u'System Emulation User''s Guide'
-
-# One entry per manual page. List of tuples
-# (source start file, name, description, authors, manual section).
-man_pages = [
-    ('qemu-manpage', 'qemu', u'QEMU User Documentation',
-     ['Fabrice Bellard'], 1),
-    ('qemu-block-drivers', 'qemu-block-drivers',
-     u'QEMU block drivers reference',
-     ['Fabrice Bellard and the QEMU Project developers'], 7),
-    ('qemu-cpu-models', 'qemu-cpu-models',
-     u'QEMU CPU Models',
-     ['The QEMU Project developers'], 7)
-]
diff --git a/docs/tools/conf.py b/docs/tools/conf.py
deleted file mode 100644
index XXXXXXX..XXXXXXX
--- a/docs/tools/conf.py
+++ /dev/null
@@ -XXX,XX +XXX,XX @@
-# -*- coding: utf-8 -*-
-#
-# QEMU documentation build configuration file for the 'tools' manual.
-#
-# This includes the top level conf file and then makes any necessary tweaks.
-import sys
-import os
-
-qemu_docdir = os.path.abspath("..")
-parent_config = os.path.join(qemu_docdir, "conf.py")
-exec(compile(open(parent_config, "rb").read(), parent_config, 'exec'))
-
-# This slightly misuses the 'description', but is the best way to get
-# the manual title to appear in the sidebar.
-html_theme_options['description'] = \
-    u'Tools Guide'
-
-# One entry per manual page. List of tuples
-# (source start file, name, description, authors, manual section).
-man_pages = [
-    ('qemu-img', 'qemu-img', u'QEMU disk image utility',
-     ['Fabrice Bellard'], 1),
-    ('qemu-storage-daemon', 'qemu-storage-daemon', u'QEMU storage daemon',
-     [], 1),
-    ('qemu-nbd', 'qemu-nbd', u'QEMU Disk Network Block Device Server',
-     ['Anthony Liguori <anthony@codemonkey.ws>'], 8),
-    ('qemu-pr-helper', 'qemu-pr-helper', 'QEMU persistent reservation helper',
-     [], 8),
-    ('qemu-trace-stap', 'qemu-trace-stap', u'QEMU SystemTap trace tool',
-     [], 1),
-    ('virtfs-proxy-helper', 'virtfs-proxy-helper',
-     u'QEMU 9p virtfs proxy filesystem helper',
-     ['M. Mohan Kumar'], 1),
-    ('virtiofsd', 'virtiofsd', u'QEMU virtio-fs shared file system daemon',
-     ['Stefan Hajnoczi <stefanha@redhat.com>',
-      'Masayoshi Mizuma <m.mizuma@jp.fujitsu.com>'], 1),
-]
diff --git a/docs/user/conf.py b/docs/user/conf.py
deleted file mode 100644
index XXXXXXX..XXXXXXX
--- a/docs/user/conf.py
+++ /dev/null
@@ -XXX,XX +XXX,XX @@
-# -*- coding: utf-8 -*-
-#
-# QEMU documentation build configuration file for the 'user' manual.
-#
-# This includes the top level conf file and then makes any necessary tweaks.
-import sys
-import os
-
-qemu_docdir = os.path.abspath("..")
-parent_config = os.path.join(qemu_docdir, "conf.py")
-exec(compile(open(parent_config, "rb").read(), parent_config, 'exec'))
-
-# This slightly misuses the 'description', but is the best way to get
-# the manual title to appear in the sidebar.
-html_theme_options['description'] = u'User Mode Emulation User''s Guide'
-- 
2.20.1

In commit cd8be50e58f63413c0 we converted the A32 coprocessor
insns to decodetree. This accidentally broke XScale/iWMMXt insns,
because it moved the handling of "cp insns which are handled
by looking up the cp register in the hashtable" from after the
call to the legacy disas_xscale_insn() decode to before it,
with the result that all XScale/iWMMXt insns now UNDEF.

Update valid_cp() so that it knows that on XScale cp 0 and 1
are not standard coprocessor instructions; this will cause
the decodetree trans_ functions to ignore them, so that
execution will correctly get through to the legacy decode again.

Cc: qemu-stable@nongnu.org
Reported-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Guenter Roeck <linux@roeck-us.net>
Message-id: 20210108195157.32067-1-peter.maydell@linaro.org
---
 target/arm/translate.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static bool valid_cp(DisasContext *s, int cp)
      * only cp14 and cp15 are valid, and other values aren't considered
      * to be in the coprocessor-instruction space at all. v8M still
      * permits coprocessors 0..7.
+     * For XScale, we must not decode the XScale cp0, cp1 space as
+     * a standard coprocessor insn, because we want to fall through to
+     * the legacy disas_xscale_insn() decoder after decodetree is done.
      */
+    if (arm_dc_feature(s, ARM_FEATURE_XSCALE) && (cp == 0 || cp == 1)) {
+        return false;
+    }
+
     if (arm_dc_feature(s, ARM_FEATURE_V8) &&
         !arm_dc_feature(s, ARM_FEATURE_M)) {
         return cp >= 14;
-- 
2.20.1

The lan9118 code mostly uses symbolic constants for register offsets;
the exceptions are those which the datasheet doesn't give an official
symbolic name to.

Add some names for the registers which don't already have them, based
on the longer names they are given in the memory map.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20210108180401.2263-3-peter.maydell@linaro.org
---
 hw/net/lan9118.c | 24 ++++++++++++++++++------
 1 file changed, 18 insertions(+), 6 deletions(-)

diff --git a/hw/net/lan9118.c b/hw/net/lan9118.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/net/lan9118.c
+++ b/hw/net/lan9118.c
@@ -XXX,XX +XXX,XX @@ do { hw_error("lan9118: error: " fmt , ## __VA_ARGS__);} while (0)
 do { fprintf(stderr, "lan9118: error: " fmt , ## __VA_ARGS__);} while (0)
 #endif
 
+/* The tx and rx fifo ports are a range of aliased 32-bit registers */
+#define RX_DATA_FIFO_PORT_FIRST 0x00
+#define RX_DATA_FIFO_PORT_LAST 0x1f
+#define TX_DATA_FIFO_PORT_FIRST 0x20
+#define TX_DATA_FIFO_PORT_LAST 0x3f
+
+#define RX_STATUS_FIFO_PORT 0x40
+#define RX_STATUS_FIFO_PEEK 0x44
+#define TX_STATUS_FIFO_PORT 0x48
+#define TX_STATUS_FIFO_PEEK 0x4c
+
 #define CSR_ID_REV      0x50
 #define CSR_IRQ_CFG     0x54
 #define CSR_INT_STS     0x58
@@ -XXX,XX +XXX,XX @@ static void lan9118_writel(void *opaque, hwaddr offset,
     offset &= 0xff;
 
     //DPRINTF("Write reg 0x%02x = 0x%08x\n", (int)offset, val);
-    if (offset >= 0x20 && offset < 0x40) {
+    if (offset >= TX_DATA_FIFO_PORT_FIRST &&
+        offset <= TX_DATA_FIFO_PORT_LAST) {
         /* TX FIFO */
         tx_fifo_push(s, val);
         return;
@@ -XXX,XX +XXX,XX @@ static uint64_t lan9118_readl(void *opaque, hwaddr offset,
     lan9118_state *s = (lan9118_state *)opaque;
 
     //DPRINTF("Read reg 0x%02x\n", (int)offset);
-    if (offset < 0x20) {
+    if (offset <= RX_DATA_FIFO_PORT_LAST) {
         /* RX FIFO */
         return rx_fifo_pop(s);
     }
     switch (offset) {
-    case 0x40:
+    case RX_STATUS_FIFO_PORT:
         return rx_status_fifo_pop(s);
-    case 0x44:
+    case RX_STATUS_FIFO_PEEK:
         return s->rx_status_fifo[s->rx_status_fifo_head];
-    case 0x48:
+    case TX_STATUS_FIFO_PORT:
         return tx_status_fifo_pop(s);
-    case 0x4c:
+    case TX_STATUS_FIFO_PEEK:
         return s->tx_status_fifo[s->tx_status_fifo_head];
     case CSR_ID_REV:
         return 0x01180001;
-- 
2.20.1

From: Hao Wu <wuhaotsh@google.com>

This patch allows NPCM7XX CLK module to compute clocks that are used by
other NPCM7XX modules.

Add a new struct NPCM7xxClockConverterState which represents a
single converter.  Each clock converter in CLK module represents one
converter in NPCM7XX CLK Module(PLL, SEL or Divider). Each converter
takes one or more input clocks and converts them into one output clock.
They form a clock hierarchy in the CLK module and are responsible for
outputing clocks for various other modules in an NPCM7XX SoC.

Each converter has a function pointer called "convert" which represents
the unique logic for that converter.

The clock contains two initialization information: ConverterInitInfo and
ConverterConnectionInfo. They represent the vertices and edges in the
clock diagram respectively.

Reviewed-by: Havard Skinnemoen <hskinnemoen@google.com>
Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
Signed-off-by: Hao Wu <wuhaotsh@google.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20210108190945.949196-2-wuhaotsh@google.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/misc/npcm7xx_clk.h | 140 +++++-
 hw/misc/npcm7xx_clk.c         | 805 +++++++++++++++++++++++++++++++++-
 2 files changed, 932 insertions(+), 13 deletions(-)

diff --git a/include/hw/misc/npcm7xx_clk.h b/include/hw/misc/npcm7xx_clk.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/misc/npcm7xx_clk.h
+++ b/include/hw/misc/npcm7xx_clk.h
@@ -XXX,XX +XXX,XX @@
 #define NPCM7XX_CLK_H
 
 #include "exec/memory.h"
+#include "hw/clock.h"
 #include "hw/sysbus.h"
 
 /*
@@ -XXX,XX +XXX,XX @@
 
 #define NPCM7XX_WATCHDOG_RESET_GPIO_IN "npcm7xx-clk-watchdog-reset-gpio-in"
 
-typedef struct NPCM7xxCLKState {
+/* Maximum amount of clock inputs in a SEL module. */
+#define NPCM7XX_CLK_SEL_MAX_INPUT 5
+
+/* PLLs in CLK module. */
+typedef enum NPCM7xxClockPLL {
+    NPCM7XX_CLOCK_PLL0,
+    NPCM7XX_CLOCK_PLL1,
+    NPCM7XX_CLOCK_PLL2,
+    NPCM7XX_CLOCK_PLLG,
+    NPCM7XX_CLOCK_NR_PLLS,
+} NPCM7xxClockPLL;
+
+/* SEL/MUX in CLK module. */
+typedef enum NPCM7xxClockSEL {
+    NPCM7XX_CLOCK_PIXCKSEL,
+    NPCM7XX_CLOCK_MCCKSEL,
+    NPCM7XX_CLOCK_CPUCKSEL,
+    NPCM7XX_CLOCK_CLKOUTSEL,
+    NPCM7XX_CLOCK_UARTCKSEL,
+    NPCM7XX_CLOCK_TIMCKSEL,
+    NPCM7XX_CLOCK_SDCKSEL,
+    NPCM7XX_CLOCK_GFXMSEL,
+    NPCM7XX_CLOCK_SUCKSEL,
+    NPCM7XX_CLOCK_NR_SELS,
+} NPCM7xxClockSEL;
+
+/* Dividers in CLK module. */
+typedef enum NPCM7xxClockDivider {
+    NPCM7XX_CLOCK_PLL1D2, /* PLL1/2 */
+    NPCM7XX_CLOCK_PLL2D2, /* PLL2/2 */
+    NPCM7XX_CLOCK_MC_DIVIDER,
+    NPCM7XX_CLOCK_AXI_DIVIDER,
+    NPCM7XX_CLOCK_AHB_DIVIDER,
+    NPCM7XX_CLOCK_AHB3_DIVIDER,
+    NPCM7XX_CLOCK_SPI0_DIVIDER,
+    NPCM7XX_CLOCK_SPIX_DIVIDER,
+    NPCM7XX_CLOCK_APB1_DIVIDER,
+    NPCM7XX_CLOCK_APB2_DIVIDER,
+    NPCM7XX_CLOCK_APB3_DIVIDER,
+    NPCM7XX_CLOCK_APB4_DIVIDER,
+    NPCM7XX_CLOCK_APB5_DIVIDER,
+    NPCM7XX_CLOCK_CLKOUT_DIVIDER,
+    NPCM7XX_CLOCK_UART_DIVIDER,
+    NPCM7XX_CLOCK_TIMER_DIVIDER,
+    NPCM7XX_CLOCK_ADC_DIVIDER,
+    NPCM7XX_CLOCK_MMC_DIVIDER,
+    NPCM7XX_CLOCK_SDHC_DIVIDER,
+    NPCM7XX_CLOCK_GFXM_DIVIDER, /* divide by 3 */
+    NPCM7XX_CLOCK_UTMI_DIVIDER,
+    NPCM7XX_CLOCK_NR_DIVIDERS,
+} NPCM7xxClockConverter;
+
+typedef struct NPCM7xxCLKState NPCM7xxCLKState;
+
+/**
+ * struct NPCM7xxClockPLLState - A PLL module in CLK module.
+ * @name: The name of the module.
+ * @clk: The CLK module that owns this module.
+ * @clock_in: The input clock of this module.
+ * @clock_out: The output clock of this module.
+ * @reg: The control registers for this PLL module.
+ */
+typedef struct NPCM7xxClockPLLState {
+    DeviceState parent;
+
+    const char *name;
+    NPCM7xxCLKState *clk;
+    Clock *clock_in;
+    Clock *clock_out;
+
+    int reg;
+} NPCM7xxClockPLLState;
+
+/**
+ * struct NPCM7xxClockSELState - A SEL module in CLK module.
+ * @name: The name of the module.
+ * @clk: The CLK module that owns this module.
+ * @input_size: The size of inputs of this module.
+ * @clock_in: The input clocks of this module.
+ * @clock_out: The output clocks of this module.
+ * @offset: The offset of this module in the control register.
+ * @len: The length of this module in the control register.
+ */
+typedef struct NPCM7xxClockSELState {
+    DeviceState parent;
+
+    const char *name;
+    NPCM7xxCLKState *clk;
+    uint8_t input_size;
+    Clock *clock_in[NPCM7XX_CLK_SEL_MAX_INPUT];
+    Clock *clock_out;
+
+    int offset;
+    int len;
+} NPCM7xxClockSELState;
+
+/**
+ * struct NPCM7xxClockDividerState - A Divider module in CLK module.
+ * @name: The name of the module.
+ * @clk: The CLK module that owns this module.
+ * @clock_in: The input clock of this module.
+ * @clock_out: The output clock of this module.
+ * @divide: The function the divider uses to divide the input.
+ * @reg: The index of the control register that contains the divisor.
+ * @offset: The offset of the divisor in the control register.
+ * @len: The length of the divisor in the control register.
+ * @divisor: The divisor for a constant divisor
+ */
+typedef struct NPCM7xxClockDividerState {
+    DeviceState parent;
+
+    const char *name;
+    NPCM7xxCLKState *clk;
+    Clock *clock_in;
+    Clock *clock_out;
+
+    uint32_t (*divide)(struct NPCM7xxClockDividerState *s);
+    union {
+        struct {
+            int reg;
+            int offset;
+            int len;
+        };
+        int divisor;
+    };
+} NPCM7xxClockDividerState;
+
+struct NPCM7xxCLKState {
     SysBusDevice parent;
 
     MemoryRegion iomem;
 
+    /* Clock converters */
+    NPCM7xxClockPLLState plls[NPCM7XX_CLOCK_NR_PLLS];
+    NPCM7xxClockSELState sels[NPCM7XX_CLOCK_NR_SELS];
+    NPCM7xxClockDividerState dividers[NPCM7XX_CLOCK_NR_DIVIDERS];
+
     uint32_t regs[NPCM7XX_CLK_NR_REGS];
 
     /* Time reference for SECCNT and CNTR25M, initialized by power on reset */
     int64_t ref_ns;
-} NPCM7xxCLKState;
+
+    /* The incoming reference clock. */
+    Clock *clkref;
+};
 
 #define TYPE_NPCM7XX_CLK "npcm7xx-clk"
 #define NPCM7XX_CLK(obj) OBJECT_CHECK(NPCM7xxCLKState, (obj), TYPE_NPCM7XX_CLK)
diff --git a/hw/misc/npcm7xx_clk.c b/hw/misc/npcm7xx_clk.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/misc/npcm7xx_clk.c
+++ b/hw/misc/npcm7xx_clk.c
@@ -XXX,XX +XXX,XX @@
 
 #include "hw/misc/npcm7xx_clk.h"
 #include "hw/timer/npcm7xx_timer.h"
+#include "hw/qdev-clock.h"
 #include "migration/vmstate.h"
 #include "qemu/error-report.h"
 #include "qemu/log.h"
@@ -XXX,XX +XXX,XX @@
 #include "trace.h"
 #include "sysemu/watchdog.h"
 
+/*
+ * The reference clock hz, and the SECCNT and CNTR25M registers in this module,
+ * is always 25 MHz.
+ */
+#define NPCM7XX_CLOCK_REF_HZ            (25000000)
+
+/* Register Field Definitions */
+#define NPCM7XX_CLK_WDRCR_CA9C  BIT(0) /* Cortex A9 Cores */
+
 #define PLLCON_LOKI     BIT(31)
 #define PLLCON_LOKS     BIT(30)
 #define PLLCON_PWDEN    BIT(12)
+#define PLLCON_FBDV(con) extract32((con), 16, 12)
+#define PLLCON_OTDV2(con) extract32((con), 13, 3)
+#define PLLCON_OTDV1(con) extract32((con), 8, 3)
+#define PLLCON_INDV(con) extract32((con), 0, 6)
 
 enum NPCM7xxCLKRegisters {
     NPCM7XX_CLK_CLKEN1,
@@ -XXX,XX +XXX,XX @@ static const uint32_t cold_reset_values[NPCM7XX_CLK_NR_REGS] = {
     [NPCM7XX_CLK_AHBCKFI]       = 0x000000c8,
 };
 
-/* Register Field Definitions */
-#define NPCM7XX_CLK_WDRCR_CA9C  BIT(0) /* Cortex A9 Cores */
-
 /* The number of watchdogs that can trigger a reset. */
 #define NPCM7XX_NR_WATCHDOGS    (3)
 
+/* Clock converter functions */
+
+#define TYPE_NPCM7XX_CLOCK_PLL "npcm7xx-clock-pll"
+#define NPCM7XX_CLOCK_PLL(obj) OBJECT_CHECK(NPCM7xxClockPLLState, \
+        (obj), TYPE_NPCM7XX_CLOCK_PLL)
+#define TYPE_NPCM7XX_CLOCK_SEL "npcm7xx-clock-sel"
+#define NPCM7XX_CLOCK_SEL(obj) OBJECT_CHECK(NPCM7xxClockSELState, \
+        (obj), TYPE_NPCM7XX_CLOCK_SEL)
+#define TYPE_NPCM7XX_CLOCK_DIVIDER "npcm7xx-clock-divider"
+#define NPCM7XX_CLOCK_DIVIDER(obj) OBJECT_CHECK(NPCM7xxClockDividerState, \
+        (obj), TYPE_NPCM7XX_CLOCK_DIVIDER)
+
+static void npcm7xx_clk_update_pll(void *opaque)
+{
+    NPCM7xxClockPLLState *s = opaque;
+    uint32_t con = s->clk->regs[s->reg];
+    uint64_t freq;
+
+    /* The PLL is grounded if it is not locked yet. */
+    if (con & PLLCON_LOKI) {
+        freq = clock_get_hz(s->clock_in);
+        freq *= PLLCON_FBDV(con);
+        freq /= PLLCON_INDV(con) * PLLCON_OTDV1(con) * PLLCON_OTDV2(con);
+    } else {
+        freq = 0;
+    }
+
+    clock_update_hz(s->clock_out, freq);
+}
+
+static void npcm7xx_clk_update_sel(void *opaque)
+{
+    NPCM7xxClockSELState *s = opaque;
+    uint32_t index = extract32(s->clk->regs[NPCM7XX_CLK_CLKSEL], s->offset,
+            s->len);
+
+    if (index >= s->input_size) {
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: SEL index: %u out of range\n",
+                      __func__, index);
+        index = 0;
+    }
+    clock_update_hz(s->clock_out, clock_get_hz(s->clock_in[index]));
+}
+
+static void npcm7xx_clk_update_divider(void *opaque)
+{
+    NPCM7xxClockDividerState *s = opaque;
+    uint32_t freq;
+
+    freq = s->divide(s);
+    clock_update_hz(s->clock_out, freq);
+}
+
+static uint32_t divide_by_constant(NPCM7xxClockDividerState *s)
+{
+    return clock_get_hz(s->clock_in) / s->divisor;
+}
+
+static uint32_t divide_by_reg_divisor(NPCM7xxClockDividerState *s)
+{
+    return clock_get_hz(s->clock_in) /
+            (extract32(s->clk->regs[s->reg], s->offset, s->len) + 1);
+}
+
+static uint32_t divide_by_reg_divisor_times_2(NPCM7xxClockDividerState *s)
+{
+    return divide_by_reg_divisor(s) / 2;
+}
+
+static uint32_t shift_by_reg_divisor(NPCM7xxClockDividerState *s)
+{
+    return clock_get_hz(s->clock_in) >>
+        extract32(s->clk->regs[s->reg], s->offset, s->len);
+}
+
+static NPCM7xxClockPLL find_pll_by_reg(enum NPCM7xxCLKRegisters reg)
+{
+    switch (reg) {
+    case NPCM7XX_CLK_PLLCON0:
+        return NPCM7XX_CLOCK_PLL0;
+    case NPCM7XX_CLK_PLLCON1:
+        return NPCM7XX_CLOCK_PLL1;
+    case NPCM7XX_CLK_PLLCON2:
+        return NPCM7XX_CLOCK_PLL2;
+    case NPCM7XX_CLK_PLLCONG:
+        return NPCM7XX_CLOCK_PLLG;
+    default:
+        g_assert_not_reached();
+    }
+}
+
+static void npcm7xx_clk_update_all_plls(NPCM7xxCLKState *clk)
+{
+    int i;
+
+    for (i = 0; i < NPCM7XX_CLOCK_NR_PLLS; ++i) {
+        npcm7xx_clk_update_pll(&clk->plls[i]);
+    }
+}
+
+static void npcm7xx_clk_update_all_sels(NPCM7xxCLKState *clk)
+{
+    int i;
+
+    for (i = 0; i < NPCM7XX_CLOCK_NR_SELS; ++i) {
+        npcm7xx_clk_update_sel(&clk->sels[i]);
+    }
+}
+
+static void npcm7xx_clk_update_all_dividers(NPCM7xxCLKState *clk)
+{
+    int i;
+
+    for (i = 0; i < NPCM7XX_CLOCK_NR_DIVIDERS; ++i) {
+        npcm7xx_clk_update_divider(&clk->dividers[i]);
+    }
+}
+
+static void npcm7xx_clk_update_all_clocks(NPCM7xxCLKState *clk)
+{
+    clock_update_hz(clk->clkref, NPCM7XX_CLOCK_REF_HZ);
+    npcm7xx_clk_update_all_plls(clk);
+    npcm7xx_clk_update_all_sels(clk);
+    npcm7xx_clk_update_all_dividers(clk);
+}
+
+/* Types of clock sources. */
+typedef enum ClockSrcType {
+    CLKSRC_REF,
+    CLKSRC_PLL,
+    CLKSRC_SEL,
+    CLKSRC_DIV,
+} ClockSrcType;
+
+typedef struct PLLInitInfo {
+    const char *name;
+    ClockSrcType src_type;
+    int src_index;
+    int reg;
+    const char *public_name;
+} PLLInitInfo;
+
+typedef struct SELInitInfo {
+    const char *name;
+    uint8_t input_size;
+    ClockSrcType src_type[NPCM7XX_CLK_SEL_MAX_INPUT];
+    int src_index[NPCM7XX_CLK_SEL_MAX_INPUT];
+    int offset;
+    int len;
+    const char *public_name;
+} SELInitInfo;
+
+typedef struct DividerInitInfo {
+    const char *name;
+    ClockSrcType src_type;
+    int src_index;
+    uint32_t (*divide)(NPCM7xxClockDividerState *s);
+    int reg; /* not used when type == CONSTANT */
+    int offset; /* not used when type == CONSTANT */
+    int len; /* not used when type == CONSTANT */
+    int divisor; /* used only when type == CONSTANT */
+    const char *public_name;
+} DividerInitInfo;
+
+static const PLLInitInfo pll_init_info_list[] = {
+    [NPCM7XX_CLOCK_PLL0] = {
+        .name = "pll0",
+        .src_type = CLKSRC_REF,
+        .reg = NPCM7XX_CLK_PLLCON0,
+    },
+    [NPCM7XX_CLOCK_PLL1] = {
+        .name = "pll1",
+        .src_type = CLKSRC_REF,
+        .reg = NPCM7XX_CLK_PLLCON1,
+    },
+    [NPCM7XX_CLOCK_PLL2] = {
+        .name = "pll2",
+        .src_type = CLKSRC_REF,
+        .reg = NPCM7XX_CLK_PLLCON2,
+    },
+    [NPCM7XX_CLOCK_PLLG] = {
+        .name = "pllg",
+        .src_type = CLKSRC_REF,
+        .reg = NPCM7XX_CLK_PLLCONG,
+    },
+};
+
+static const SELInitInfo sel_init_info_list[] = {
+    [NPCM7XX_CLOCK_PIXCKSEL] = {
+        .name = "pixcksel",
+        .input_size = 2,
+        .src_type = {CLKSRC_PLL, CLKSRC_REF},
+        .src_index = {NPCM7XX_CLOCK_PLLG, 0},
+        .offset = 5,
+        .len = 1,
+        .public_name = "pixel-clock",
+    },
+    [NPCM7XX_CLOCK_MCCKSEL] = {
+        .name = "mccksel",
+        .input_size = 4,
+        .src_type = {CLKSRC_DIV, CLKSRC_REF, CLKSRC_REF,
+            /*MCBPCK, shouldn't be used in normal operation*/
+            CLKSRC_REF},
+        .src_index = {NPCM7XX_CLOCK_PLL1D2, 0, 0, 0},
+        .offset = 12,
+        .len = 2,
+        .public_name = "mc-phy-clock",
+    },
+    [NPCM7XX_CLOCK_CPUCKSEL] = {
+        .name = "cpucksel",
+        .input_size = 4,
+        .src_type = {CLKSRC_PLL, CLKSRC_DIV, CLKSRC_REF,
+            /*SYSBPCK, shouldn't be used in normal operation*/
+            CLKSRC_REF},
+        .src_index = {NPCM7XX_CLOCK_PLL0, NPCM7XX_CLOCK_PLL1D2, 0, 0},
+        .offset = 0,
+        .len = 2,
+        .public_name = "system-clock",
+    },
+    [NPCM7XX_CLOCK_CLKOUTSEL] = {
+        .name = "clkoutsel",
+        .input_size = 5,
+        .src_type = {CLKSRC_PLL, CLKSRC_DIV, CLKSRC_REF,
+            CLKSRC_PLL, CLKSRC_DIV},
+        .src_index = {NPCM7XX_CLOCK_PLL0, NPCM7XX_CLOCK_PLL1D2, 0,
+            NPCM7XX_CLOCK_PLLG, NPCM7XX_CLOCK_PLL2D2},
+        .offset = 18,
+        .len = 3,
+        .public_name = "tock",
+    },
+    [NPCM7XX_CLOCK_UARTCKSEL] = {
+        .name = "uartcksel",
+        .input_size = 4,
+        .src_type = {CLKSRC_PLL, CLKSRC_DIV, CLKSRC_REF, CLKSRC_DIV},
+        .src_index = {NPCM7XX_CLOCK_PLL0, NPCM7XX_CLOCK_PLL1D2, 0,
+            NPCM7XX_CLOCK_PLL2D2},
+        .offset = 8,
+        .len = 2,
+    },
+    [NPCM7XX_CLOCK_TIMCKSEL] = {
+        .name = "timcksel",
+        .input_size = 4,
+        .src_type = {CLKSRC_PLL, CLKSRC_DIV, CLKSRC_REF, CLKSRC_DIV},
+        .src_index = {NPCM7XX_CLOCK_PLL0, NPCM7XX_CLOCK_PLL1D2, 0,
+            NPCM7XX_CLOCK_PLL2D2},
+        .offset = 14,
+        .len = 2,
+    },
+    [NPCM7XX_CLOCK_SDCKSEL] = {
+        .name = "sdcksel",
+        .input_size = 4,
+        .src_type = {CLKSRC_PLL, CLKSRC_DIV, CLKSRC_REF, CLKSRC_DIV},
+        .src_index = {NPCM7XX_CLOCK_PLL0, NPCM7XX_CLOCK_PLL1D2, 0,
+            NPCM7XX_CLOCK_PLL2D2},
+        .offset = 6,
+        .len = 2,
+    },
+    [NPCM7XX_CLOCK_GFXMSEL] = {
+        .name = "gfxmksel",
+        .input_size = 2,
+        .src_type = {CLKSRC_REF, CLKSRC_PLL},
+        .src_index = {0, NPCM7XX_CLOCK_PLL2},
+        .offset = 21,
+        .len = 1,
+    },
+    [NPCM7XX_CLOCK_SUCKSEL] = {
+        .name = "sucksel",
+        .input_size = 4,
+        .src_type = {CLKSRC_PLL, CLKSRC_DIV, CLKSRC_REF, CLKSRC_DIV},
+        .src_index = {NPCM7XX_CLOCK_PLL0, NPCM7XX_CLOCK_PLL1D2, 0,
+            NPCM7XX_CLOCK_PLL2D2},
+        .offset = 10,
+        .len = 2,
+    },
+};
+
+static const DividerInitInfo divider_init_info_list[] = {
+    [NPCM7XX_CLOCK_PLL1D2] = {
+        .name = "pll1d2",
+        .src_type = CLKSRC_PLL,
+        .src_index = NPCM7XX_CLOCK_PLL1,
+        .divide = divide_by_constant,
+        .divisor = 2,
+    },
+    [NPCM7XX_CLOCK_PLL2D2] = {
+        .name = "pll2d2",
+        .src_type = CLKSRC_PLL,
+        .src_index = NPCM7XX_CLOCK_PLL2,
+        .divide = divide_by_constant,
+        .divisor = 2,
+    },
+    [NPCM7XX_CLOCK_MC_DIVIDER] = {
+        .name = "mc-divider",
+        .src_type = CLKSRC_SEL,
+        .src_index = NPCM7XX_CLOCK_MCCKSEL,
+        .divide = divide_by_constant,
+        .divisor = 2,
+        .public_name = "mc-clock"
+    },
+    [NPCM7XX_CLOCK_AXI_DIVIDER] = {
+        .name = "axi-divider",
+        .src_type = CLKSRC_SEL,
+        .src_index = NPCM7XX_CLOCK_CPUCKSEL,
+        .divide = shift_by_reg_divisor,
+        .reg = NPCM7XX_CLK_CLKDIV1,
+        .offset = 0,
+        .len = 1,
+        .public_name = "clk2"
+    },
+    [NPCM7XX_CLOCK_AHB_DIVIDER] = {
+        .name = "ahb-divider",
+        .src_type = CLKSRC_DIV,
+        .src_index = NPCM7XX_CLOCK_AXI_DIVIDER,
+        .divide = divide_by_reg_divisor,
+        .reg = NPCM7XX_CLK_CLKDIV1,
+        .offset = 26,
+        .len = 2,
+        .public_name = "clk4"
+    },
+    [NPCM7XX_CLOCK_AHB3_DIVIDER] = {
+        .name = "ahb3-divider",
+        .src_type = CLKSRC_DIV,
+        .src_index = NPCM7XX_CLOCK_AHB_DIVIDER,
+        .divide = divide_by_reg_divisor,
+        .reg = NPCM7XX_CLK_CLKDIV1,
+        .offset = 6,
+        .len = 5,
+        .public_name = "ahb3-spi3-clock"
+    },
+    [NPCM7XX_CLOCK_SPI0_DIVIDER] = {
+        .name = "spi0-divider",
+        .src_type = CLKSRC_DIV,
+        .src_index = NPCM7XX_CLOCK_AHB_DIVIDER,
+        .divide = divide_by_reg_divisor,
+        .reg = NPCM7XX_CLK_CLKDIV3,
+        .offset = 6,
+        .len = 5,
+        .public_name = "spi0-clock",
+    },
+    [NPCM7XX_CLOCK_SPIX_DIVIDER] = {
+        .name = "spix-divider",
+        .src_type = CLKSRC_DIV,
+        .src_index = NPCM7XX_CLOCK_AHB_DIVIDER,
+        .divide = divide_by_reg_divisor,
+        .reg = NPCM7XX_CLK_CLKDIV3,
+        .offset = 1,
+        .len = 5,
+        .public_name = "spix-clock",
+    },
+    [NPCM7XX_CLOCK_APB1_DIVIDER] = {
+        .name = "apb1-divider",
+        .src_type = CLKSRC_DIV,
+        .src_index = NPCM7XX_CLOCK_AHB_DIVIDER,
+        .divide = shift_by_reg_divisor,
+        .reg = NPCM7XX_CLK_CLKDIV2,
+        .offset = 24,
+        .len = 2,
+        .public_name = "apb1-clock",
+    },
+    [NPCM7XX_CLOCK_APB2_DIVIDER] = {
+        .name = "apb2-divider",
+        .src_type = CLKSRC_DIV,
+        .src_index = NPCM7XX_CLOCK_AHB_DIVIDER,
+        .divide = shift_by_reg_divisor,
+        .reg = NPCM7XX_CLK_CLKDIV2,
+        .offset = 26,
+        .len = 2,
+        .public_name = "apb2-clock",
+    },
+    [NPCM7XX_CLOCK_APB3_DIVIDER] = {
+        .name = "apb3-divider",
+        .src_type = CLKSRC_DIV,
+        .src_index = NPCM7XX_CLOCK_AHB_DIVIDER,
+        .divide = shift_by_reg_divisor,
+        .reg = NPCM7XX_CLK_CLKDIV2,
+        .offset = 28,
+        .len = 2,
+        .public_name = "apb3-clock",
+    },
+    [NPCM7XX_CLOCK_APB4_DIVIDER] = {
+        .name = "apb4-divider",
+        .src_type = CLKSRC_DIV,
+        .src_index = NPCM7XX_CLOCK_AHB_DIVIDER,
+        .divide = shift_by_reg_divisor,
+        .reg = NPCM7XX_CLK_CLKDIV2,
+        .offset = 30,
+        .len = 2,
+        .public_name = "apb4-clock",
+    },
+    [NPCM7XX_CLOCK_APB5_DIVIDER] = {
+        .name = "apb5-divider",
+        .src_type = CLKSRC_DIV,
+        .src_index = NPCM7XX_CLOCK_AHB_DIVIDER,
+        .divide = shift_by_reg_divisor,
+        .reg = NPCM7XX_CLK_CLKDIV2,
+        .offset = 22,
+        .len = 2,
+        .public_name = "apb5-clock",
+    },
+    [NPCM7XX_CLOCK_CLKOUT_DIVIDER] = {
+        .name = "clkout-divider",
+        .src_type = CLKSRC_SEL,
+        .src_index = NPCM7XX_CLOCK_CLKOUTSEL,
+        .divide = divide_by_reg_divisor,
+        .reg = NPCM7XX_CLK_CLKDIV2,
+        .offset = 16,
+        .len = 5,
+        .public_name = "clkout",
+    },
+    [NPCM7XX_CLOCK_UART_DIVIDER] = {
+        .name = "uart-divider",
+        .src_type = CLKSRC_SEL,
+        .src_index = NPCM7XX_CLOCK_UARTCKSEL,
+        .divide = divide_by_reg_divisor,
+        .reg = NPCM7XX_CLK_CLKDIV1,
+        .offset = 16,
+        .len = 5,
+        .public_name = "uart-clock",
+    },
+    [NPCM7XX_CLOCK_TIMER_DIVIDER] = {
+        .name = "timer-divider",
+        .src_type = CLKSRC_SEL,
+        .src_index = NPCM7XX_CLOCK_TIMCKSEL,
+        .divide = divide_by_reg_divisor,
+        .reg = NPCM7XX_CLK_CLKDIV1,
+        .offset = 21,
+        .len = 5,
+        .public_name = "timer-clock",
+    },
+    [NPCM7XX_CLOCK_ADC_DIVIDER] = {
+        .name = "adc-divider",
+        .src_type = CLKSRC_DIV,
+        .src_index = NPCM7XX_CLOCK_TIMER_DIVIDER,
+        .divide = shift_by_reg_divisor,
+        .reg = NPCM7XX_CLK_CLKDIV1,
+        .offset = 28,
+        .len = 3,
+        .public_name = "adc-clock",
+    },
+    [NPCM7XX_CLOCK_MMC_DIVIDER] = {
+        .name = "mmc-divider",
+        .src_type = CLKSRC_SEL,
+        .src_index = NPCM7XX_CLOCK_SDCKSEL,
+        .divide = divide_by_reg_divisor,
+        .reg = NPCM7XX_CLK_CLKDIV1,
+        .offset = 11,
+        .len = 5,
+        .public_name = "mmc-clock",
+    },
+    [NPCM7XX_CLOCK_SDHC_DIVIDER] = {
+        .name = "sdhc-divider",
+        .src_type = CLKSRC_SEL,
+        .src_index = NPCM7XX_CLOCK_SDCKSEL,
+        .divide = divide_by_reg_divisor_times_2,
+        .reg = NPCM7XX_CLK_CLKDIV2,
+        .offset = 0,
+        .len = 4,
+        .public_name = "sdhc-clock",
+    },
+    [NPCM7XX_CLOCK_GFXM_DIVIDER] = {
+        .name = "gfxm-divider",
+        .src_type = CLKSRC_SEL,
+        .src_index = NPCM7XX_CLOCK_GFXMSEL,
+        .divide = divide_by_constant,
+        .divisor = 3,
+        .public_name = "gfxm-clock",
+    },
+    [NPCM7XX_CLOCK_UTMI_DIVIDER] = {
+        .name = "utmi-divider",
+        .src_type = CLKSRC_SEL,
+        .src_index = NPCM7XX_CLOCK_SUCKSEL,
+        .divide = divide_by_reg_divisor,
+        .reg = NPCM7XX_CLK_CLKDIV2,
+        .offset = 8,
+        .len = 5,
+        .public_name = "utmi-clock",
+    },
+};
+
+static void npcm7xx_clk_pll_init(Object *obj)
+{
+    NPCM7xxClockPLLState *pll = NPCM7XX_CLOCK_PLL(obj);
+
+    pll->clock_in = qdev_init_clock_in(DEVICE(pll), "clock-in",
+            npcm7xx_clk_update_pll, pll);
+    pll->clock_out = qdev_init_clock_out(DEVICE(pll), "clock-out");
+}
+
+static void npcm7xx_clk_sel_init(Object *obj)
+{
+    int i;
+    NPCM7xxClockSELState *sel = NPCM7XX_CLOCK_SEL(obj);
+
+    for (i = 0; i < NPCM7XX_CLK_SEL_MAX_INPUT; ++i) {
+        sel->clock_in[i] = qdev_init_clock_in(DEVICE(sel),
+                g_strdup_printf("clock-in[%d]", i),
+                npcm7xx_clk_update_sel, sel);
+    }
+    sel->clock_out = qdev_init_clock_out(DEVICE(sel), "clock-out");
+}
+static void npcm7xx_clk_divider_init(Object *obj)
+{
+    NPCM7xxClockDividerState *div = NPCM7XX_CLOCK_DIVIDER(obj);
+
+    div->clock_in = qdev_init_clock_in(DEVICE(div), "clock-in",
+            npcm7xx_clk_update_divider, div);
+    div->clock_out = qdev_init_clock_out(DEVICE(div), "clock-out");
+}
+
+static void npcm7xx_init_clock_pll(NPCM7xxClockPLLState *pll,
+        NPCM7xxCLKState *clk, const PLLInitInfo *init_info)
+{
+    pll->name = init_info->name;
+    pll->clk = clk;
+    pll->reg = init_info->reg;
+    if (init_info->public_name != NULL) {
+        qdev_alias_clock(DEVICE(pll), "clock-out", DEVICE(clk),
+                init_info->public_name);
+    }
+}
+
+static void npcm7xx_init_clock_sel(NPCM7xxClockSELState *sel,
+        NPCM7xxCLKState *clk, const SELInitInfo *init_info)
+{
+    int input_size = init_info->input_size;
+
+    sel->name = init_info->name;
+    sel->clk = clk;
+    sel->input_size = init_info->input_size;
+    g_assert(input_size <= NPCM7XX_CLK_SEL_MAX_INPUT);
+    sel->offset = init_info->offset;
+    sel->len = init_info->len;
+    if (init_info->public_name != NULL) {
+        qdev_alias_clock(DEVICE(sel), "clock-out", DEVICE(clk),
+                init_info->public_name);
+    }
+}
+
+static void npcm7xx_init_clock_divider(NPCM7xxClockDividerState *div,
+        NPCM7xxCLKState *clk, const DividerInitInfo *init_info)
+{
+    div->name = init_info->name;
+    div->clk = clk;
+
+    div->divide = init_info->divide;
+    if (div->divide == divide_by_constant) {
+        div->divisor = init_info->divisor;
+    } else {
+        div->reg = init_info->reg;
+        div->offset = init_info->offset;
+        div->len = init_info->len;
+    }
+    if (init_info->public_name != NULL) {
+        qdev_alias_clock(DEVICE(div), "clock-out", DEVICE(clk),
+                init_info->public_name);
+    }
+}
+
+static Clock *npcm7xx_get_clock(NPCM7xxCLKState *clk, ClockSrcType type,
+        int index)
+{
+    switch (type) {
+    case CLKSRC_REF:
+        return clk->clkref;
+    case CLKSRC_PLL:
+        return clk->plls[index].clock_out;
+    case CLKSRC_SEL:
+        return clk->sels[index].clock_out;
+    case CLKSRC_DIV:
+        return clk->dividers[index].clock_out;
+    default:
+        g_assert_not_reached();
+    }
+}
+
+static void npcm7xx_connect_clocks(NPCM7xxCLKState *clk)
+{
+    int i, j;
+    Clock *src;
+
+    for (i = 0; i < NPCM7XX_CLOCK_NR_PLLS; ++i) {
+        src = npcm7xx_get_clock(clk, pll_init_info_list[i].src_type,
+                pll_init_info_list[i].src_index);
+        clock_set_source(clk->plls[i].clock_in, src);
+    }
+    for (i = 0; i < NPCM7XX_CLOCK_NR_SELS; ++i) {
+        for (j = 0; j < sel_init_info_list[i].input_size; ++j) {
+            src = npcm7xx_get_clock(clk, sel_init_info_list[i].src_type[j],
+                    sel_init_info_list[i].src_index[j]);
+            clock_set_source(clk->sels[i].clock_in[j], src);
+        }
+    }
+    for (i = 0; i < NPCM7XX_CLOCK_NR_DIVIDERS; ++i) {
+        src = npcm7xx_get_clock(clk, divider_init_info_list[i].src_type,
+                divider_init_info_list[i].src_index);
+        clock_set_source(clk->dividers[i].clock_in, src);
+    }
+}
+
 static uint64_t npcm7xx_clk_read(void *opaque, hwaddr offset, unsigned size)
 {
     uint32_t reg = offset / sizeof(uint32_t);
@@ -XXX,XX +XXX,XX @@ static uint64_t npcm7xx_clk_read(void *opaque, hwaddr offset, unsigned size)
          *
          * The 4 LSBs are always zero: (1e9 / 640) << 4 = 25000000.
          */
-        value = (((now_ns - s->ref_ns) / 640) << 4) % NPCM7XX_TIMER_REF_HZ;
+        value = (((now_ns - s->ref_ns) / 640) << 4) % NPCM7XX_CLOCK_REF_HZ;
         break;
 
     default:
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_clk_write(void *opaque, hwaddr offset,
                 value |= (value & PLLCON_LOKS);
             }
         }
+        /* Only update PLL when it is locked. */
+        if (value & PLLCON_LOKI) {
+            npcm7xx_clk_update_pll(&s->plls[find_pll_by_reg(reg)]);
+        }
+        break;
+
+    case NPCM7XX_CLK_CLKSEL:
+        npcm7xx_clk_update_all_sels(s);
+        break;
+
+    case NPCM7XX_CLK_CLKDIV1:
+    case NPCM7XX_CLK_CLKDIV2:
+    case NPCM7XX_CLK_CLKDIV3:
+        npcm7xx_clk_update_all_dividers(s);
         break;
 
     case NPCM7XX_CLK_CNTR25M:
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_clk_enter_reset(Object *obj, ResetType type)
     case RESET_TYPE_COLD:
         memcpy(s->regs, cold_reset_values, sizeof(cold_reset_values));
         s->ref_ns = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
+        npcm7xx_clk_update_all_clocks(s);
         return;
     }
 
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_clk_enter_reset(Object *obj, ResetType type)
                   __func__, type);
 }
 
+static void npcm7xx_clk_init_clock_hierarchy(NPCM7xxCLKState *s)
+{
+    int i;
+
+    s->clkref = qdev_init_clock_in(DEVICE(s), "clkref", NULL, NULL);
+
+    /* First pass: init all converter modules */
+    QEMU_BUILD_BUG_ON(ARRAY_SIZE(pll_init_info_list) != NPCM7XX_CLOCK_NR_PLLS);
+    QEMU_BUILD_BUG_ON(ARRAY_SIZE(sel_init_info_list) != NPCM7XX_CLOCK_NR_SELS);
+    QEMU_BUILD_BUG_ON(ARRAY_SIZE(divider_init_info_list)
+            != NPCM7XX_CLOCK_NR_DIVIDERS);
+    for (i = 0; i < NPCM7XX_CLOCK_NR_PLLS; ++i) {
+        object_initialize_child(OBJECT(s), pll_init_info_list[i].name,
+                &s->plls[i], TYPE_NPCM7XX_CLOCK_PLL);
+        npcm7xx_init_clock_pll(&s->plls[i], s,
+                &pll_init_info_list[i]);
+    }
+    for (i = 0; i < NPCM7XX_CLOCK_NR_SELS; ++i) {
+        object_initialize_child(OBJECT(s), sel_init_info_list[i].name,
+                &s->sels[i], TYPE_NPCM7XX_CLOCK_SEL);
+        npcm7xx_init_clock_sel(&s->sels[i], s,
+                &sel_init_info_list[i]);
+    }
+    for (i = 0; i < NPCM7XX_CLOCK_NR_DIVIDERS; ++i) {
+        object_initialize_child(OBJECT(s), divider_init_info_list[i].name,
+                &s->dividers[i], TYPE_NPCM7XX_CLOCK_DIVIDER);
+        npcm7xx_init_clock_divider(&s->dividers[i], s,
+                &divider_init_info_list[i]);
+    }
+
+    /* Second pass: connect converter modules */
+    npcm7xx_connect_clocks(s);
+
+    clock_update_hz(s->clkref, NPCM7XX_CLOCK_REF_HZ);
+}
+
 static void npcm7xx_clk_init(Object *obj)
 {
     NPCM7xxCLKState *s = NPCM7XX_CLK(obj);
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_clk_init(Object *obj)
     memory_region_init_io(&s->iomem, obj, &npcm7xx_clk_ops, s,
                           TYPE_NPCM7XX_CLK, 4 * KiB);
     sysbus_init_mmio(&s->parent, &s->iomem);
-    qdev_init_gpio_in_named(DEVICE(s), npcm7xx_clk_perform_watchdog_reset,
-            NPCM7XX_WATCHDOG_RESET_GPIO_IN, NPCM7XX_NR_WATCHDOGS);
 }
 
-static const VMStateDescription vmstate_npcm7xx_clk = {
-    .name = "npcm7xx-clk",
+static int npcm7xx_clk_post_load(void *opaque, int version_id)
+{
+    if (version_id >= 1) {
+        NPCM7xxCLKState *clk = opaque;
+
+        npcm7xx_clk_update_all_clocks(clk);
+    }
+
+    return 0;
+}
+
+static void npcm7xx_clk_realize(DeviceState *dev, Error **errp)
+{
+    int i;
+    NPCM7xxCLKState *s = NPCM7XX_CLK(dev);
+
+    qdev_init_gpio_in_named(DEVICE(s), npcm7xx_clk_perform_watchdog_reset,
+            NPCM7XX_WATCHDOG_RESET_GPIO_IN, NPCM7XX_NR_WATCHDOGS);
+    npcm7xx_clk_init_clock_hierarchy(s);
+
+    /* Realize child devices */
+    for (i = 0; i < NPCM7XX_CLOCK_NR_PLLS; ++i) {
+        if (!qdev_realize(DEVICE(&s->plls[i]), NULL, errp)) {
+            return;
+        }
+    }
+    for (i = 0; i < NPCM7XX_CLOCK_NR_SELS; ++i) {
+        if (!qdev_realize(DEVICE(&s->sels[i]), NULL, errp)) {
+            return;
+        }
+    }
+    for (i = 0; i < NPCM7XX_CLOCK_NR_DIVIDERS; ++i) {
+        if (!qdev_realize(DEVICE(&s->dividers[i]), NULL, errp)) {
+            return;
+        }
+    }
+}
+
+static const VMStateDescription vmstate_npcm7xx_clk_pll = {
+    .name = "npcm7xx-clock-pll",
     .version_id = 0,
     .minimum_version_id = 0,
-    .fields = (VMStateField[]) {
-        VMSTATE_UINT32_ARRAY(regs, NPCM7xxCLKState, NPCM7XX_CLK_NR_REGS),
-        VMSTATE_INT64(ref_ns, NPCM7xxCLKState),
+    .fields =  (VMStateField[]) {
+        VMSTATE_CLOCK(clock_in, NPCM7xxClockPLLState),
         VMSTATE_END_OF_LIST(),
     },
 };
 
+static const VMStateDescription vmstate_npcm7xx_clk_sel = {
+    .name = "npcm7xx-clock-sel",
+    .version_id = 0,
+    .minimum_version_id = 0,
+    .fields =  (VMStateField[]) {
+        VMSTATE_ARRAY_OF_POINTER_TO_STRUCT(clock_in, NPCM7xxClockSELState,
+                NPCM7XX_CLK_SEL_MAX_INPUT, 0, vmstate_clock, Clock),
+        VMSTATE_END_OF_LIST(),
+    },
+};
+
+static const VMStateDescription vmstate_npcm7xx_clk_divider = {
+    .name = "npcm7xx-clock-divider",
+    .version_id = 0,
+    .minimum_version_id = 0,
+    .fields =  (VMStateField[]) {
+        VMSTATE_CLOCK(clock_in, NPCM7xxClockDividerState),
+        VMSTATE_END_OF_LIST(),
+    },
+};
+
+static const VMStateDescription vmstate_npcm7xx_clk = {
+    .name = "npcm7xx-clk",
+    .version_id = 1,
+    .minimum_version_id = 1,
+    .post_load = npcm7xx_clk_post_load,
+    .fields = (VMStateField[]) {
+        VMSTATE_UINT32_ARRAY(regs, NPCM7xxCLKState, NPCM7XX_CLK_NR_REGS),
+        VMSTATE_INT64(ref_ns, NPCM7xxCLKState),
+        VMSTATE_CLOCK(clkref, NPCM7xxCLKState),
+        VMSTATE_END_OF_LIST(),
+    },
+};
+
+static void npcm7xx_clk_pll_class_init(ObjectClass *klass, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+
+    dc->desc = "NPCM7xx Clock PLL Module";
+    dc->vmsd = &vmstate_npcm7xx_clk_pll;
+}
+
+static void npcm7xx_clk_sel_class_init(ObjectClass *klass, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+
+    dc->desc = "NPCM7xx Clock SEL Module";
+    dc->vmsd = &vmstate_npcm7xx_clk_sel;
+}
+
+static void npcm7xx_clk_divider_class_init(ObjectClass *klass, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+
+    dc->desc = "NPCM7xx Clock Divider Module";
+    dc->vmsd = &vmstate_npcm7xx_clk_divider;
+}
+
 static void npcm7xx_clk_class_init(ObjectClass *klass, void *data)
 {
     ResettableClass *rc = RESETTABLE_CLASS(klass);
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_clk_class_init(ObjectClass *klass, void *data)
 
     dc->desc = "NPCM7xx Clock Control Registers";
     dc->vmsd = &vmstate_npcm7xx_clk;
+    dc->realize = npcm7xx_clk_realize;
     rc->phases.enter = npcm7xx_clk_enter_reset;
 }
 
+static const TypeInfo npcm7xx_clk_pll_info = {
+    .name               = TYPE_NPCM7XX_CLOCK_PLL,
+    .parent             = TYPE_DEVICE,
+    .instance_size      = sizeof(NPCM7xxClockPLLState),
+    .instance_init      = npcm7xx_clk_pll_init,
+    .class_init         = npcm7xx_clk_pll_class_init,
+};
+
+static const TypeInfo npcm7xx_clk_sel_info = {
+    .name               = TYPE_NPCM7XX_CLOCK_SEL,
+    .parent             = TYPE_DEVICE,
+    .instance_size      = sizeof(NPCM7xxClockSELState),
+    .instance_init      = npcm7xx_clk_sel_init,
+    .class_init         = npcm7xx_clk_sel_class_init,
+};
+
+static const TypeInfo npcm7xx_clk_divider_info = {
+    .name               = TYPE_NPCM7XX_CLOCK_DIVIDER,
+    .parent             = TYPE_DEVICE,
+    .instance_size      = sizeof(NPCM7xxClockDividerState),
+    .instance_init      = npcm7xx_clk_divider_init,
+    .class_init         = npcm7xx_clk_divider_class_init,
+};
+
 static const TypeInfo npcm7xx_clk_info = {
     .name               = TYPE_NPCM7XX_CLK,
     .parent             = TYPE_SYS_BUS_DEVICE,
@@ -XXX,XX +XXX,XX @@ static const TypeInfo npcm7xx_clk_info = {
 
 static void npcm7xx_clk_register_type(void)
 {
+    type_register_static(&npcm7xx_clk_pll_info);
+    type_register_static(&npcm7xx_clk_sel_info);
+    type_register_static(&npcm7xx_clk_divider_info);
     type_register_static(&npcm7xx_clk_info);
 }
 type_init(npcm7xx_clk_register_type);
-- 
2.20.1

From: Hao Wu <wuhaotsh@google.com>

This patch makes NPCM7XX Timer to use a the timer clock generated by the
CLK module instead of the magic number TIMER_REF_HZ.

diff --git a/include/hw/misc/npcm7xx_clk.h b/include/hw/misc/npcm7xx_clk.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/misc/npcm7xx_clk.h
+++ b/include/hw/misc/npcm7xx_clk.h
@@ -XXX,XX +XXX,XX @@
 #include "hw/clock.h"
 #include "hw/sysbus.h"
 
-/*
- * The reference clock frequency for the timer modules, and the SECCNT and
- * CNTR25M registers in this module, is always 25 MHz.
- */
-#define NPCM7XX_TIMER_REF_HZ            (25000000)
-
 /*
  * Number of registers in our device state structure. Don't change this without
  * incrementing the version_id in the vmstate.
diff --git a/include/hw/timer/npcm7xx_timer.h b/include/hw/timer/npcm7xx_timer.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/timer/npcm7xx_timer.h
+++ b/include/hw/timer/npcm7xx_timer.h
@@ -XXX,XX +XXX,XX @@ struct NPCM7xxTimerCtrlState {
 
     uint32_t    tisr;
 
+    Clock       *clock;
     NPCM7xxTimer timer[NPCM7XX_TIMERS_PER_CTRL];
     NPCM7xxWatchdogTimer watchdog_timer;
 };
diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/npcm7xx.c
+++ b/hw/arm/npcm7xx.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/char/serial.h"
 #include "hw/loader.h"
 #include "hw/misc/unimp.h"
+#include "hw/qdev-clock.h"
 #include "hw/qdev-properties.h"
 #include "qapi/error.h"
 #include "qemu/units.h"
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_realize(DeviceState *dev, Error **errp)
         int first_irq;
         int j;
 
+        /* Connect the timer clock. */
+        qdev_connect_clock_in(DEVICE(&s->tim[i]), "clock", qdev_get_clock_out(
+                    DEVICE(&s->clk), "timer-clock"));
+
         sysbus_realize(sbd, &error_abort);
         sysbus_mmio_map(sbd, 0, npcm7xx_tim_addr[i]);
 
diff --git a/hw/timer/npcm7xx_timer.c b/hw/timer/npcm7xx_timer.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/timer/npcm7xx_timer.c
+++ b/hw/timer/npcm7xx_timer.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu/osdep.h"
 
 #include "hw/irq.h"
+#include "hw/qdev-clock.h"
 #include "hw/qdev-properties.h"
-#include "hw/misc/npcm7xx_clk.h"
 #include "hw/timer/npcm7xx_timer.h"
 #include "migration/vmstate.h"
 #include "qemu/bitops.h"
@@ -XXX,XX +XXX,XX @@ static uint32_t npcm7xx_tcsr_prescaler(uint32_t tcsr)
 /* Convert a timer cycle count to a time interval in nanoseconds. */
 static int64_t npcm7xx_timer_count_to_ns(NPCM7xxTimer *t, uint32_t count)
 {
-    int64_t ns = count;
+    int64_t ticks = count;
 
-    ns *= NANOSECONDS_PER_SECOND / NPCM7XX_TIMER_REF_HZ;
-    ns *= npcm7xx_tcsr_prescaler(t->tcsr);
+    ticks *= npcm7xx_tcsr_prescaler(t->tcsr);
 
-    return ns;
+    return clock_ticks_to_ns(t->ctrl->clock, ticks);
 }
 
 /* Convert a time interval in nanoseconds to a timer cycle count. */
 static uint32_t npcm7xx_timer_ns_to_count(NPCM7xxTimer *t, int64_t ns)
 {
-    int64_t count;
-
-    count = ns / (NANOSECONDS_PER_SECOND / NPCM7XX_TIMER_REF_HZ);
-    count /= npcm7xx_tcsr_prescaler(t->tcsr);
-
-    return count;
+    return ns / clock_ticks_to_ns(t->ctrl->clock,
+                                  npcm7xx_tcsr_prescaler(t->tcsr));
 }
 
 static uint32_t npcm7xx_watchdog_timer_prescaler(const NPCM7xxWatchdogTimer *t)
@@ -XXX,XX +XXX,XX @@ static uint32_t npcm7xx_watchdog_timer_prescaler(const NPCM7xxWatchdogTimer *t)
 static void npcm7xx_watchdog_timer_reset_cycles(NPCM7xxWatchdogTimer *t,
         int64_t cycles)
 {
-    uint32_t prescaler = npcm7xx_watchdog_timer_prescaler(t);
-    int64_t ns = (NANOSECONDS_PER_SECOND / NPCM7XX_TIMER_REF_HZ) * cycles;
+    int64_t ticks = cycles * npcm7xx_watchdog_timer_prescaler(t);
+    int64_t ns = clock_ticks_to_ns(t->ctrl->clock, ticks);
 
     /*
      * The reset function always clears the current timer. The caller of the
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_watchdog_timer_reset_cycles(NPCM7xxWatchdogTimer *t,
      */
     npcm7xx_timer_clear(&t->base_timer);
 
-    ns *= prescaler;
     t->base_timer.remaining_ns = ns;
 }
 
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_timer_hold_reset(Object *obj)
     qemu_irq_lower(s->watchdog_timer.irq);
 }
 
-static void npcm7xx_timer_realize(DeviceState *dev, Error **errp)
+static void npcm7xx_timer_init(Object *obj)
 {
-    NPCM7xxTimerCtrlState *s = NPCM7XX_TIMER(dev);
-    SysBusDevice *sbd = &s->parent;
+    NPCM7xxTimerCtrlState *s = NPCM7XX_TIMER(obj);
+    DeviceState *dev = DEVICE(obj);
+    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
     int i;
     NPCM7xxWatchdogTimer *w;
 
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_timer_realize(DeviceState *dev, Error **errp)
             npcm7xx_watchdog_timer_expired, w);
     sysbus_init_irq(sbd, &w->irq);
 
-    memory_region_init_io(&s->iomem, OBJECT(s), &npcm7xx_timer_ops, s,
+    memory_region_init_io(&s->iomem, obj, &npcm7xx_timer_ops, s,
                           TYPE_NPCM7XX_TIMER, 4 * KiB);
     sysbus_init_mmio(sbd, &s->iomem);
     qdev_init_gpio_out_named(dev, &w->reset_signal,
             NPCM7XX_WATCHDOG_RESET_GPIO_OUT, 1);
+    s->clock = qdev_init_clock_in(dev, "clock", NULL, NULL);
 }
 
 static const VMStateDescription vmstate_npcm7xx_base_timer = {
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_npcm7xx_watchdog_timer = {
 
 static const VMStateDescription vmstate_npcm7xx_timer_ctrl = {
     .name = "npcm7xx-timer-ctrl",
-    .version_id = 1,
-    .minimum_version_id = 1,
+    .version_id = 2,
+    .minimum_version_id = 2,
     .fields = (VMStateField[]) {
         VMSTATE_UINT32(tisr, NPCM7xxTimerCtrlState),
+        VMSTATE_CLOCK(clock, NPCM7xxTimerCtrlState),
         VMSTATE_STRUCT_ARRAY(timer, NPCM7xxTimerCtrlState,
                              NPCM7XX_TIMERS_PER_CTRL, 0, vmstate_npcm7xx_timer,
                              NPCM7xxTimer),
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_timer_class_init(ObjectClass *klass, void *data)
     QEMU_BUILD_BUG_ON(NPCM7XX_TIMER_REGS_END > NPCM7XX_TIMER_NR_REGS);
 
     dc->desc = "NPCM7xx Timer Controller";
-    dc->realize = npcm7xx_timer_realize;
     dc->vmsd = &vmstate_npcm7xx_timer_ctrl;
     rc->phases.enter = npcm7xx_timer_enter_reset;
     rc->phases.hold = npcm7xx_timer_hold_reset;
@@ -XXX,XX +XXX,XX @@ static const TypeInfo npcm7xx_timer_info = {
     .parent             = TYPE_SYS_BUS_DEVICE,
     .instance_size      = sizeof(NPCM7xxTimerCtrlState),
     .class_init         = npcm7xx_timer_class_init,
+    .instance_init      = npcm7xx_timer_init,
 };
 
 static void npcm7xx_timer_register_type(void)
-- 
2.20.1

From: Hao Wu <wuhaotsh@google.com>

The ADC is part of NPCM7XX Module. Its behavior is controled by the
ADC_CON register. It converts one of the eight analog inputs into a
digital input and stores it in the ADC_DATA register when enabled.

Users can alter input value by using qom-set QMP command.

Reviewed-by: Havard Skinnemoen <hskinnemoen@google.com>
Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
Signed-off-by: Hao Wu <wuhaotsh@google.com>
Message-id: 20210108190945.949196-4-wuhaotsh@google.com
[PMM: Added missing hw/adc/trace.h file]
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 docs/system/arm/nuvoton.rst    |   2 +-
 meson.build                    |   1 +
 hw/adc/trace.h                 |   1 +
 include/hw/adc/npcm7xx_adc.h   |  69 ++++++
 include/hw/arm/npcm7xx.h       |   2 +
 hw/adc/npcm7xx_adc.c           | 301 ++++++++++++++++++++++++++
 hw/arm/npcm7xx.c               |  24 ++-
 tests/qtest/npcm7xx_adc-test.c | 377 +++++++++++++++++++++++++++++++++
 hw/adc/meson.build             |   1 +
 hw/adc/trace-events            |   5 +
 tests/qtest/meson.build        |   3 +-
 11 files changed, 783 insertions(+), 3 deletions(-)
 create mode 100644 hw/adc/trace.h
 create mode 100644 include/hw/adc/npcm7xx_adc.h
 create mode 100644 hw/adc/npcm7xx_adc.c
 create mode 100644 tests/qtest/npcm7xx_adc-test.c
 create mode 100644 hw/adc/trace-events

diff --git a/docs/system/arm/nuvoton.rst b/docs/system/arm/nuvoton.rst
index XXXXXXX..XXXXXXX 100644
--- a/docs/system/arm/nuvoton.rst
+++ b/docs/system/arm/nuvoton.rst
@@ -XXX,XX +XXX,XX @@ Supported devices
  * Random Number Generator (RNG)
  * USB host (USBH)
  * GPIO controller
+ * Analog to Digital Converter (ADC)
 
 Missing devices
 ---------------
@@ -XXX,XX +XXX,XX @@ Missing devices
  * USB device (USBD)
  * SMBus controller (SMBF)
  * Peripheral SPI controller (PSPI)
- * Analog to Digital Converter (ADC)
  * SD/MMC host
  * PECI interface
  * Pulse Width Modulation (PWM)
diff --git a/meson.build b/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/meson.build
+++ b/meson.build
@@ -XXX,XX +XXX,XX @@ if have_system
     'chardev',
     'hw/9pfs',
     'hw/acpi',
+    'hw/adc',
     'hw/alpha',
     'hw/arm',
     'hw/audio',
diff --git a/hw/adc/trace.h b/hw/adc/trace.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/hw/adc/trace.h
@@ -0,0 +1 @@
+#include "trace/trace-hw_adc.h"
diff --git a/include/hw/adc/npcm7xx_adc.h b/include/hw/adc/npcm7xx_adc.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/include/hw/adc/npcm7xx_adc.h
@@ -XXX,XX +XXX,XX @@
+/*
+ * Nuvoton NPCM7xx ADC Module
+ *
+ * Copyright 2020 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ */
+#ifndef NPCM7XX_ADC_H
+#define NPCM7XX_ADC_H
+
+#include "hw/clock.h"
+#include "hw/irq.h"
+#include "hw/sysbus.h"
+#include "qemu/timer.h"
+
+#define NPCM7XX_ADC_NUM_INPUTS      8
+/**
+ * This value should not be changed unless write_adc_calibration function in
+ * hw/arm/npcm7xx.c is also changed.
+ */
+#define NPCM7XX_ADC_NUM_CALIB       2
+
+/**
+ * struct NPCM7xxADCState - Analog to Digital Converter Module device state.
+ * @parent: System bus device.
+ * @iomem: Memory region through which registers are accessed.
+ * @conv_timer: The timer counts down remaining cycles for the conversion.
+ * @irq: GIC interrupt line to fire on expiration (if enabled).
+ * @con: The Control Register.
+ * @data: The Data Buffer.
+ * @clock: The ADC Clock.
+ * @adci: The input voltage in units of uV. 1uv = 1e-6V.
+ * @vref: The external reference voltage.
+ * @iref: The internal reference voltage, initialized at launch time.
+ * @rv: The calibrated output values of 0.5V and 1.5V for the ADC.
+ */
+typedef struct {
+    SysBusDevice parent;
+
+    MemoryRegion iomem;
+
+    QEMUTimer    conv_timer;
+
+    qemu_irq     irq;
+    uint32_t     con;
+    uint32_t     data;
+    Clock       *clock;
+
+    /* Voltages are in unit of uV. 1V = 1000000uV. */
+    uint32_t     adci[NPCM7XX_ADC_NUM_INPUTS];
+    uint32_t     vref;
+    uint32_t     iref;
+
+    uint16_t     calibration_r_values[NPCM7XX_ADC_NUM_CALIB];
+} NPCM7xxADCState;
+
+#define TYPE_NPCM7XX_ADC "npcm7xx-adc"
+#define NPCM7XX_ADC(obj) \
+    OBJECT_CHECK(NPCM7xxADCState, (obj), TYPE_NPCM7XX_ADC)
+
+#endif /* NPCM7XX_ADC_H */
diff --git a/include/hw/arm/npcm7xx.h b/include/hw/arm/npcm7xx.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/npcm7xx.h
+++ b/include/hw/arm/npcm7xx.h
@@ -XXX,XX +XXX,XX @@
 #define NPCM7XX_H
 
 #include "hw/boards.h"
+#include "hw/adc/npcm7xx_adc.h"
 #include "hw/cpu/a9mpcore.h"
 #include "hw/gpio/npcm7xx_gpio.h"
 #include "hw/mem/npcm7xx_mc.h"
@@ -XXX,XX +XXX,XX @@ typedef struct NPCM7xxState {
     NPCM7xxGCRState     gcr;
     NPCM7xxCLKState     clk;
     NPCM7xxTimerCtrlState tim[3];
+    NPCM7xxADCState     adc;
     NPCM7xxOTPState     key_storage;
     NPCM7xxOTPState     fuse_array;
     NPCM7xxMCState      mc;
diff --git a/hw/adc/npcm7xx_adc.c b/hw/adc/npcm7xx_adc.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/hw/adc/npcm7xx_adc.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * Nuvoton NPCM7xx ADC Module
+ *
+ * Copyright 2020 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ */
+
+#include "qemu/osdep.h"
+#include "hw/adc/npcm7xx_adc.h"
+#include "hw/qdev-clock.h"
+#include "hw/qdev-properties.h"
+#include "hw/registerfields.h"
+#include "migration/vmstate.h"
+#include "qemu/log.h"
+#include "qemu/module.h"
+#include "qemu/timer.h"
+#include "qemu/units.h"
+#include "trace.h"
+
+REG32(NPCM7XX_ADC_CON, 0x0)
+REG32(NPCM7XX_ADC_DATA, 0x4)
+
+/* Register field definitions. */
+#define NPCM7XX_ADC_CON_MUX(rv) extract32(rv, 24, 4)
+#define NPCM7XX_ADC_CON_INT_EN  BIT(21)
+#define NPCM7XX_ADC_CON_REFSEL  BIT(19)
+#define NPCM7XX_ADC_CON_INT     BIT(18)
+#define NPCM7XX_ADC_CON_EN      BIT(17)
+#define NPCM7XX_ADC_CON_RST     BIT(16)
+#define NPCM7XX_ADC_CON_CONV    BIT(14)
+#define NPCM7XX_ADC_CON_DIV(rv) extract32(rv, 1, 8)
+
+#define NPCM7XX_ADC_MAX_RESULT      1023
+#define NPCM7XX_ADC_DEFAULT_IREF    2000000
+#define NPCM7XX_ADC_CONV_CYCLES     20
+#define NPCM7XX_ADC_RESET_CYCLES    10
+#define NPCM7XX_ADC_R0_INPUT        500000
+#define NPCM7XX_ADC_R1_INPUT        1500000
+
+static void npcm7xx_adc_reset(NPCM7xxADCState *s)
+{
+    timer_del(&s->conv_timer);
+    s->con = 0x000c0001;
+    s->data = 0x00000000;
+}
+
+static uint32_t npcm7xx_adc_convert(uint32_t input, uint32_t ref)
+{
+    uint32_t result;
+
+    result = input * (NPCM7XX_ADC_MAX_RESULT + 1) / ref;
+    if (result > NPCM7XX_ADC_MAX_RESULT) {
+        result = NPCM7XX_ADC_MAX_RESULT;
+    }
+
+    return result;
+}
+
+static uint32_t npcm7xx_adc_prescaler(NPCM7xxADCState *s)
+{
+    return 2 * (NPCM7XX_ADC_CON_DIV(s->con) + 1);
+}
+
+static void npcm7xx_adc_start_timer(Clock *clk, QEMUTimer *timer,
+        uint32_t cycles, uint32_t prescaler)
+{
+    int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
+    int64_t ticks = cycles;
+    int64_t ns;
+
+    ticks *= prescaler;
+    ns = clock_ticks_to_ns(clk, ticks);
+    ns += now;
+    timer_mod(timer, ns);
+}
+
+static void npcm7xx_adc_start_convert(NPCM7xxADCState *s)
+{
+    uint32_t prescaler = npcm7xx_adc_prescaler(s);
+
+    npcm7xx_adc_start_timer(s->clock, &s->conv_timer, NPCM7XX_ADC_CONV_CYCLES,
+            prescaler);
+}
+
+static void npcm7xx_adc_convert_done(void *opaque)
+{
+    NPCM7xxADCState *s = opaque;
+    uint32_t input = NPCM7XX_ADC_CON_MUX(s->con);
+    uint32_t ref = (s->con & NPCM7XX_ADC_CON_REFSEL)
+        ? s->iref : s->vref;
+
+    if (input >= NPCM7XX_ADC_NUM_INPUTS) {
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid input: %u\n",
+                      __func__, input);
+        return;
+    }
+    s->data = npcm7xx_adc_convert(s->adci[input], ref);
+    if (s->con & NPCM7XX_ADC_CON_INT_EN) {
+        s->con |= NPCM7XX_ADC_CON_INT;
+        qemu_irq_raise(s->irq);
+    }
+    s->con &= ~NPCM7XX_ADC_CON_CONV;
+}
+
+static void npcm7xx_adc_calibrate(NPCM7xxADCState *adc)
+{
+    adc->calibration_r_values[0] = npcm7xx_adc_convert(NPCM7XX_ADC_R0_INPUT,
+            adc->iref);
+    adc->calibration_r_values[1] = npcm7xx_adc_convert(NPCM7XX_ADC_R1_INPUT,
+            adc->iref);
+}
+
+static void npcm7xx_adc_write_con(NPCM7xxADCState *s, uint32_t new_con)
+{
+    uint32_t old_con = s->con;
+
+    /* Write ADC_INT to 1 to clear it */
+    if (new_con & NPCM7XX_ADC_CON_INT) {
+        new_con &= ~NPCM7XX_ADC_CON_INT;
+        qemu_irq_lower(s->irq);
+    } else if (old_con & NPCM7XX_ADC_CON_INT) {
+        new_con |= NPCM7XX_ADC_CON_INT;
+    }
+
+    s->con = new_con;
+
+    if (s->con & NPCM7XX_ADC_CON_RST) {
+        npcm7xx_adc_reset(s);
+        return;
+    }
+
+    if ((s->con & NPCM7XX_ADC_CON_EN)) {
+        if (s->con & NPCM7XX_ADC_CON_CONV) {
+            if (!(old_con & NPCM7XX_ADC_CON_CONV)) {
+                npcm7xx_adc_start_convert(s);
+            }
+        } else {
+            timer_del(&s->conv_timer);
+        }
+    }
+}
+
+static uint64_t npcm7xx_adc_read(void *opaque, hwaddr offset, unsigned size)
+{
+    uint64_t value = 0;
+    NPCM7xxADCState *s = opaque;
+
+    switch (offset) {
+    case A_NPCM7XX_ADC_CON:
+        value = s->con;
+        break;
+
+    case A_NPCM7XX_ADC_DATA:
+        value = s->data;
+        break;
+
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: invalid offset 0x%04" HWADDR_PRIx "\n",
+                      __func__, offset);
+        break;
+    }
+
+    trace_npcm7xx_adc_read(DEVICE(s)->canonical_path, offset, value);
+    return value;
+}
+
+static void npcm7xx_adc_write(void *opaque, hwaddr offset, uint64_t v,
+        unsigned size)
+{
+    NPCM7xxADCState *s = opaque;
+
+    trace_npcm7xx_adc_write(DEVICE(s)->canonical_path, offset, v);
+    switch (offset) {
+    case A_NPCM7XX_ADC_CON:
+        npcm7xx_adc_write_con(s, v);
+        break;
+
+    case A_NPCM7XX_ADC_DATA:
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: register @ 0x%04" HWADDR_PRIx " is read-only\n",
+                      __func__, offset);
+        break;
+
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: invalid offset 0x%04" HWADDR_PRIx "\n",
+                      __func__, offset);
+        break;
+    }
+
+}
+
+static const struct MemoryRegionOps npcm7xx_adc_ops = {
+    .read       = npcm7xx_adc_read,
+    .write      = npcm7xx_adc_write,
+    .endianness = DEVICE_LITTLE_ENDIAN,
+    .valid      = {
+        .min_access_size        = 4,
+        .max_access_size        = 4,
+        .unaligned              = false,
+    },
+};
+
+static void npcm7xx_adc_enter_reset(Object *obj, ResetType type)
+{
+    NPCM7xxADCState *s = NPCM7XX_ADC(obj);
+
+    npcm7xx_adc_reset(s);
+}
+
+static void npcm7xx_adc_hold_reset(Object *obj)
+{
+    NPCM7xxADCState *s = NPCM7XX_ADC(obj);
+
+    qemu_irq_lower(s->irq);
+}
+
+static void npcm7xx_adc_init(Object *obj)
+{
+    NPCM7xxADCState *s = NPCM7XX_ADC(obj);
+    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
+    int i;
+
+    sysbus_init_irq(sbd, &s->irq);
+
+    timer_init_ns(&s->conv_timer, QEMU_CLOCK_VIRTUAL,
+            npcm7xx_adc_convert_done, s);
+    memory_region_init_io(&s->iomem, obj, &npcm7xx_adc_ops, s,
+                          TYPE_NPCM7XX_ADC, 4 * KiB);
+    sysbus_init_mmio(sbd, &s->iomem);
+    s->clock = qdev_init_clock_in(DEVICE(s), "clock", NULL, NULL);
+
+    for (i = 0; i < NPCM7XX_ADC_NUM_INPUTS; ++i) {
+        object_property_add_uint32_ptr(obj, "adci[*]",
+                &s->adci[i], OBJ_PROP_FLAG_WRITE);
+    }
+    object_property_add_uint32_ptr(obj, "vref",
+            &s->vref, OBJ_PROP_FLAG_WRITE);
+    npcm7xx_adc_calibrate(s);
+}
+
+static const VMStateDescription vmstate_npcm7xx_adc = {
+    .name = "npcm7xx-adc",
+    .version_id = 0,
+    .minimum_version_id = 0,
+    .fields = (VMStateField[]) {
+        VMSTATE_TIMER(conv_timer, NPCM7xxADCState),
+        VMSTATE_UINT32(con, NPCM7xxADCState),
+        VMSTATE_UINT32(data, NPCM7xxADCState),
+        VMSTATE_CLOCK(clock, NPCM7xxADCState),
+        VMSTATE_UINT32_ARRAY(adci, NPCM7xxADCState, NPCM7XX_ADC_NUM_INPUTS),
+        VMSTATE_UINT32(vref, NPCM7xxADCState),
+        VMSTATE_UINT32(iref, NPCM7xxADCState),
+        VMSTATE_UINT16_ARRAY(calibration_r_values, NPCM7xxADCState,
+                NPCM7XX_ADC_NUM_CALIB),
+        VMSTATE_END_OF_LIST(),
+    },
+};
+
+static Property npcm7xx_timer_properties[] = {
+    DEFINE_PROP_UINT32("iref", NPCM7xxADCState, iref, NPCM7XX_ADC_DEFAULT_IREF),
+    DEFINE_PROP_END_OF_LIST(),
+};
+
+static void npcm7xx_adc_class_init(ObjectClass *klass, void *data)
+{
+    ResettableClass *rc = RESETTABLE_CLASS(klass);
+    DeviceClass *dc = DEVICE_CLASS(klass);
+
+    dc->desc = "NPCM7xx ADC Module";
+    dc->vmsd = &vmstate_npcm7xx_adc;
+    rc->phases.enter = npcm7xx_adc_enter_reset;
+    rc->phases.hold = npcm7xx_adc_hold_reset;
+
+    device_class_set_props(dc, npcm7xx_timer_properties);
+}
+
+static const TypeInfo npcm7xx_adc_info = {
+    .name               = TYPE_NPCM7XX_ADC,
+    .parent             = TYPE_SYS_BUS_DEVICE,
+    .instance_size      = sizeof(NPCM7xxADCState),
+    .class_init         = npcm7xx_adc_class_init,
+    .instance_init      = npcm7xx_adc_init,
+};
+
+static void npcm7xx_adc_register_types(void)
+{
+    type_register_static(&npcm7xx_adc_info);
+}
+
+type_init(npcm7xx_adc_register_types);
diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/npcm7xx.c
+++ b/hw/arm/npcm7xx.c
@@ -XXX,XX +XXX,XX @@
 #define NPCM7XX_EHCI_BA         (0xf0806000)
 #define NPCM7XX_OHCI_BA         (0xf0807000)
 
+/* ADC Module */
+#define NPCM7XX_ADC_BA          (0xf000c000)
+
 /* Internal AHB SRAM */
 #define NPCM7XX_RAM3_BA         (0xc0008000)
 #define NPCM7XX_RAM3_SZ         (4 * KiB)
@@ -XXX,XX +XXX,XX @@
 #define NPCM7XX_ROM_BA          (0xffff0000)
 #define NPCM7XX_ROM_SZ          (64 * KiB)
 
+
 /* Clock configuration values to be fixed up when bypassing bootloader */
 
 /* Run PLL1 at 1600 MHz */
@@ -XXX,XX +XXX,XX @@
  * interrupts.
  */
 enum NPCM7xxInterrupt {
+    NPCM7XX_ADC_IRQ             = 0,
     NPCM7XX_UART0_IRQ           = 2,
     NPCM7XX_UART1_IRQ,
     NPCM7XX_UART2_IRQ,
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_init_fuses(NPCM7xxState *s)
                             sizeof(value));
 }
 
+static void npcm7xx_write_adc_calibration(NPCM7xxState *s)
+{
+    /* Both ADC and the fuse array must have realized. */
+    QEMU_BUILD_BUG_ON(sizeof(s->adc.calibration_r_values) != 4);
+    npcm7xx_otp_array_write(&s->fuse_array, s->adc.calibration_r_values,
+            NPCM7XX_FUSE_ADC_CALIB, sizeof(s->adc.calibration_r_values));
+}
+
 static qemu_irq npcm7xx_irq(NPCM7xxState *s, int n)
 {
     return qdev_get_gpio_in(DEVICE(&s->a9mpcore), n);
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_init(Object *obj)
                             TYPE_NPCM7XX_FUSE_ARRAY);
     object_initialize_child(obj, "mc", &s->mc, TYPE_NPCM7XX_MC);
     object_initialize_child(obj, "rng", &s->rng, TYPE_NPCM7XX_RNG);
+    object_initialize_child(obj, "adc", &s->adc, TYPE_NPCM7XX_ADC);
 
     for (i = 0; i < ARRAY_SIZE(s->tim); i++) {
         object_initialize_child(obj, "tim[*]", &s->tim[i], TYPE_NPCM7XX_TIMER);
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_realize(DeviceState *dev, Error **errp)
     sysbus_realize(SYS_BUS_DEVICE(&s->mc), &error_abort);
     sysbus_mmio_map(SYS_BUS_DEVICE(&s->mc), 0, NPCM7XX_MC_BA);
 
+    /* ADC Modules. Cannot fail. */
+    qdev_connect_clock_in(DEVICE(&s->adc), "clock", qdev_get_clock_out(
+                          DEVICE(&s->clk), "adc-clock"));
+    sysbus_realize(SYS_BUS_DEVICE(&s->adc), &error_abort);
+    sysbus_mmio_map(SYS_BUS_DEVICE(&s->adc), 0, NPCM7XX_ADC_BA);
+    sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0,
+            npcm7xx_irq(s, NPCM7XX_ADC_IRQ));
+    npcm7xx_write_adc_calibration(s);
+
     /* Timer Modules (TIM). Cannot fail. */
     QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_tim_addr) != ARRAY_SIZE(s->tim));
     for (i = 0; i < ARRAY_SIZE(s->tim); i++) {
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_realize(DeviceState *dev, Error **errp)
     create_unimplemented_device("npcm7xx.vdmx",         0xe0800000,   4 * KiB);
     create_unimplemented_device("npcm7xx.pcierc",       0xe1000000,  64 * KiB);
     create_unimplemented_device("npcm7xx.kcs",          0xf0007000,   4 * KiB);
-    create_unimplemented_device("npcm7xx.adc",          0xf000c000,   4 * KiB);
     create_unimplemented_device("npcm7xx.gfxi",         0xf000e000,   4 * KiB);
     create_unimplemented_device("npcm7xx.gpio[0]",      0xf0010000,   4 * KiB);
     create_unimplemented_device("npcm7xx.gpio[1]",      0xf0011000,   4 * KiB);
diff --git a/tests/qtest/npcm7xx_adc-test.c b/tests/qtest/npcm7xx_adc-test.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/tests/qtest/npcm7xx_adc-test.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * QTests for Nuvoton NPCM7xx ADCModules.
+ *
+ * Copyright 2020 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/bitops.h"
+#include "qemu/timer.h"
+#include "libqos/libqtest.h"
+#include "qapi/qmp/qdict.h"
+
+#define REF_HZ          (25000000)
+
+#define CON_OFFSET      0x0
+#define DATA_OFFSET     0x4
+
+#define NUM_INPUTS      8
+#define DEFAULT_IREF    2000000
+#define CONV_CYCLES     20
+#define RESET_CYCLES    10
+#define R0_INPUT        500000
+#define R1_INPUT        1500000
+#define MAX_RESULT      1023
+
+#define DEFAULT_CLKDIV  5
+
+#define FUSE_ARRAY_BA   0xf018a000
+#define FCTL_OFFSET     0x14
+#define FST_OFFSET      0x0
+#define FADDR_OFFSET    0x4
+#define FDATA_OFFSET    0x8
+#define ADC_CALIB_ADDR  24
+#define FUSE_READ       0x2
+
+/* Register field definitions. */
+#define CON_MUX(rv) ((rv) << 24)
+#define CON_INT_EN  BIT(21)
+#define CON_REFSEL  BIT(19)
+#define CON_INT     BIT(18)
+#define CON_EN      BIT(17)
+#define CON_RST     BIT(16)
+#define CON_CONV    BIT(14)
+#define CON_DIV(rv) extract32(rv, 1, 8)
+
+#define FST_RDST    BIT(1)
+#define FDATA_MASK  0xff
+
+#define MAX_ERROR   10000
+#define MIN_CALIB_INPUT 100000
+#define MAX_CALIB_INPUT 1800000
+
+static const uint32_t input_list[] = {
+    100000,
+    500000,
+    1000000,
+    1500000,
+    1800000,
+    2000000,
+};
+
+static const uint32_t vref_list[] = {
+    2000000,
+    2200000,
+    2500000,
+};
+
+static const uint32_t iref_list[] = {
+    1800000,
+    1900000,
+    2000000,
+    2100000,
+    2200000,
+};
+
+static const uint32_t div_list[] = {0, 1, 3, 7, 15};
+
+typedef struct ADC {
+    int irq;
+    uint64_t base_addr;
+} ADC;
+
+ADC adc = {
+    .irq        = 0,
+    .base_addr  = 0xf000c000
+};
+
+static uint32_t adc_read_con(QTestState *qts, const ADC *adc)
+{
+    return qtest_readl(qts, adc->base_addr + CON_OFFSET);
+}
+
+static void adc_write_con(QTestState *qts, const ADC *adc, uint32_t value)
+{
+    qtest_writel(qts, adc->base_addr + CON_OFFSET, value);
+}
+
+static uint32_t adc_read_data(QTestState *qts, const ADC *adc)
+{
+    return qtest_readl(qts, adc->base_addr + DATA_OFFSET);
+}
+
+static uint32_t adc_calibrate(uint32_t measured, uint32_t *rv)
+{
+    return R0_INPUT + (R1_INPUT - R0_INPUT) * (int32_t)(measured - rv[0])
+        / (int32_t)(rv[1] - rv[0]);
+}
+
+static void adc_qom_set(QTestState *qts, const ADC *adc,
+        const char *name, uint32_t value)
+{
+    QDict *response;
+    const char *path = "/machine/soc/adc";
+
+    g_test_message("Setting properties %s of %s with value %u",
+            name, path, value);
+    response = qtest_qmp(qts, "{ 'execute': 'qom-set',"
+            " 'arguments': { 'path': %s, 'property': %s, 'value': %u}}",
+            path, name, value);
+    /* The qom set message returns successfully. */
+    g_assert_true(qdict_haskey(response, "return"));
+}
+
+static void adc_write_input(QTestState *qts, const ADC *adc,
+        uint32_t index, uint32_t value)
+{
+    char name[100];
+
+    sprintf(name, "adci[%u]", index);
+    adc_qom_set(qts, adc, name, value);
+}
+
+static void adc_write_vref(QTestState *qts, const ADC *adc, uint32_t value)
+{
+    adc_qom_set(qts, adc, "vref", value);
+}
+
+static uint32_t adc_calculate_output(uint32_t input, uint32_t ref)
+{
+    uint32_t output;
+
+    g_assert_cmpuint(input, <=, ref);
+    output = (input * (MAX_RESULT + 1)) / ref;
+    if (output > MAX_RESULT) {
+        output = MAX_RESULT;
+    }
+
+    return output;
+}
+
+static uint32_t adc_prescaler(QTestState *qts, const ADC *adc)
+{
+    uint32_t div = extract32(adc_read_con(qts, adc), 1, 8);
+
+    return 2 * (div + 1);
+}
+
+static int64_t adc_calculate_steps(uint32_t cycles, uint32_t prescale,
+        uint32_t clkdiv)
+{
+    return (NANOSECONDS_PER_SECOND / (REF_HZ >> clkdiv)) * cycles * prescale;
+}
+
+static void adc_wait_conv_finished(QTestState *qts, const ADC *adc,
+        uint32_t clkdiv)
+{
+    uint32_t prescaler = adc_prescaler(qts, adc);
+
+    /*
+     * ADC should takes roughly 20 cycles to convert one sample. So we assert it
+     * should take 10~30 cycles here.
+     */
+    qtest_clock_step(qts, adc_calculate_steps(CONV_CYCLES / 2, prescaler,
+                clkdiv));
+    /* ADC is still converting. */
+    g_assert_true(adc_read_con(qts, adc) & CON_CONV);
+    qtest_clock_step(qts, adc_calculate_steps(CONV_CYCLES, prescaler, clkdiv));
+    /* ADC has finished conversion. */
+    g_assert_false(adc_read_con(qts, adc) & CON_CONV);
+}
+
+/* Check ADC can be reset to default value. */
+static void test_init(gconstpointer adc_p)
+{
+    const ADC *adc = adc_p;
+
+    QTestState *qts = qtest_init("-machine quanta-gsj");
+    adc_write_con(qts, adc, CON_REFSEL | CON_INT);
+    g_assert_cmphex(adc_read_con(qts, adc), ==, CON_REFSEL);
+    qtest_quit(qts);
+}
+
+/* Check ADC can convert from an internal reference. */
+static void test_convert_internal(gconstpointer adc_p)
+{
+    const ADC *adc = adc_p;
+    uint32_t index, input, output, expected_output;
+    QTestState *qts = qtest_init("-machine quanta-gsj");
+    qtest_irq_intercept_in(qts, "/machine/soc/a9mpcore/gic");
+
+    for (index = 0; index < NUM_INPUTS; ++index) {
+        for (size_t i = 0; i < ARRAY_SIZE(input_list); ++i) {
+            input = input_list[i];
+            expected_output = adc_calculate_output(input, DEFAULT_IREF);
+
+            adc_write_input(qts, adc, index, input);
+            adc_write_con(qts, adc, CON_MUX(index) | CON_REFSEL | CON_INT |
+                    CON_EN | CON_CONV);
+            adc_wait_conv_finished(qts, adc, DEFAULT_CLKDIV);
+            g_assert_cmphex(adc_read_con(qts, adc), ==, CON_MUX(index) |
+                    CON_REFSEL | CON_EN);
+            g_assert_false(qtest_get_irq(qts, adc->irq));
+            output = adc_read_data(qts, adc);
+            g_assert_cmpuint(output, ==, expected_output);
+        }
+    }
+
+    qtest_quit(qts);
+}
+
+/* Check ADC can convert from an external reference. */
+static void test_convert_external(gconstpointer adc_p)
+{
+    const ADC *adc = adc_p;
+    uint32_t index, input, vref, output, expected_output;
+    QTestState *qts = qtest_init("-machine quanta-gsj");
+    qtest_irq_intercept_in(qts, "/machine/soc/a9mpcore/gic");
+
+    for (index = 0; index < NUM_INPUTS; ++index) {
+        for (size_t i = 0; i < ARRAY_SIZE(input_list); ++i) {
+            for (size_t j = 0; j < ARRAY_SIZE(vref_list); ++j) {
+                input = input_list[i];
+                vref = vref_list[j];
+                expected_output = adc_calculate_output(input, vref);
+
+                adc_write_input(qts, adc, index, input);
+                adc_write_vref(qts, adc, vref);
+                adc_write_con(qts, adc, CON_MUX(index) | CON_INT | CON_EN |
+                        CON_CONV);
+                adc_wait_conv_finished(qts, adc, DEFAULT_CLKDIV);
+                g_assert_cmphex(adc_read_con(qts, adc), ==,
+                        CON_MUX(index) | CON_EN);
+                g_assert_false(qtest_get_irq(qts, adc->irq));
+                output = adc_read_data(qts, adc);
+                g_assert_cmpuint(output, ==, expected_output);
+            }
+        }
+    }
+
+    qtest_quit(qts);
+}
+
+/* Check ADC interrupt files if and only if CON_INT_EN is set. */
+static void test_interrupt(gconstpointer adc_p)
+{
+    const ADC *adc = adc_p;
+    uint32_t index, input, output, expected_output;
+    QTestState *qts = qtest_init("-machine quanta-gsj");
+
+    index = 1;
+    input = input_list[1];
+    expected_output = adc_calculate_output(input, DEFAULT_IREF);
+
+    qtest_irq_intercept_in(qts, "/machine/soc/a9mpcore/gic");
+    adc_write_input(qts, adc, index, input);
+    g_assert_false(qtest_get_irq(qts, adc->irq));
+    adc_write_con(qts, adc, CON_MUX(index) | CON_INT_EN | CON_REFSEL | CON_INT
+            | CON_EN | CON_CONV);
+    adc_wait_conv_finished(qts, adc, DEFAULT_CLKDIV);
+    g_assert_cmphex(adc_read_con(qts, adc), ==, CON_MUX(index) | CON_INT_EN
+            | CON_REFSEL | CON_INT | CON_EN);
+    g_assert_true(qtest_get_irq(qts, adc->irq));
+    output = adc_read_data(qts, adc);
+    g_assert_cmpuint(output, ==, expected_output);
+
+    qtest_quit(qts);
+}
+
+/* Check ADC is reset after setting ADC_RST for 10 ADC cycles. */
+static void test_reset(gconstpointer adc_p)
+{
+    const ADC *adc = adc_p;
+    QTestState *qts = qtest_init("-machine quanta-gsj");
+
+    for (size_t i = 0; i < ARRAY_SIZE(div_list); ++i) {
+        uint32_t div = div_list[i];
+
+        adc_write_con(qts, adc, CON_INT | CON_EN | CON_RST | CON_DIV(div));
+        qtest_clock_step(qts, adc_calculate_steps(RESET_CYCLES,
+                    adc_prescaler(qts, adc), DEFAULT_CLKDIV));
+        g_assert_false(adc_read_con(qts, adc) & CON_EN);
+    }
+    qtest_quit(qts);
+}
+
+/* Check ADC Calibration works as desired. */
+static void test_calibrate(gconstpointer adc_p)
+{
+    int i, j;
+    const ADC *adc = adc_p;
+
+    for (j = 0; j < ARRAY_SIZE(iref_list); ++j) {
+        uint32_t iref = iref_list[j];
+        uint32_t expected_rv[] = {
+            adc_calculate_output(R0_INPUT, iref),
+            adc_calculate_output(R1_INPUT, iref),
+        };
+        char buf[100];
+        QTestState *qts;
+
+        sprintf(buf, "-machine quanta-gsj -global npcm7xx-adc.iref=%u", iref);
+        qts = qtest_init(buf);
+
+        /* Check the converted value is correct using the calibration value. */
+        for (i = 0; i < ARRAY_SIZE(input_list); ++i) {
+            uint32_t input;
+            uint32_t output;
+            uint32_t expected_output;
+            uint32_t calibrated_voltage;
+            uint32_t index = 0;
+
+            input = input_list[i];
+            /* Calibration only works for input range 0.1V ~ 1.8V. */
+            if (input < MIN_CALIB_INPUT || input > MAX_CALIB_INPUT) {
+                continue;
+            }
+            expected_output = adc_calculate_output(input, iref);
+
+            adc_write_input(qts, adc, index, input);
+            adc_write_con(qts, adc, CON_MUX(index) | CON_REFSEL | CON_INT |
+                    CON_EN | CON_CONV);
+            adc_wait_conv_finished(qts, adc, DEFAULT_CLKDIV);
+            g_assert_cmphex(adc_read_con(qts, adc), ==,
+                    CON_REFSEL | CON_MUX(index) | CON_EN);
+            output = adc_read_data(qts, adc);
+            g_assert_cmpuint(output, ==, expected_output);
+
+            calibrated_voltage = adc_calibrate(output, expected_rv);
+            g_assert_cmpuint(calibrated_voltage, >, input - MAX_ERROR);
+            g_assert_cmpuint(calibrated_voltage, <, input + MAX_ERROR);
+        }
+
+        qtest_quit(qts);
+    }
+}
+
+static void adc_add_test(const char *name, const ADC* wd,
+        GTestDataFunc fn)
+{
+    g_autofree char *full_name = g_strdup_printf("npcm7xx_adc/%s",  name);
+    qtest_add_data_func(full_name, wd, fn);
+}
+#define add_test(name, td) adc_add_test(#name, td, test_##name)
+
+int main(int argc, char **argv)
+{
+    g_test_init(&argc, &argv, NULL);
+
+    add_test(init, &adc);
+    add_test(convert_internal, &adc);
+    add_test(convert_external, &adc);
+    add_test(interrupt, &adc);
+    add_test(reset, &adc);
+    add_test(calibrate, &adc);
+
+    return g_test_run();
+}
diff --git a/hw/adc/meson.build b/hw/adc/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/hw/adc/meson.build
+++ b/hw/adc/meson.build
@@ -1 +1,2 @@
 softmmu_ss.add(when: 'CONFIG_STM32F2XX_ADC', if_true: files('stm32f2xx_adc.c'))
+softmmu_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx_adc.c'))
diff --git a/hw/adc/trace-events b/hw/adc/trace-events
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/hw/adc/trace-events
@@ -XXX,XX +XXX,XX @@
+# See docs/devel/tracing.txt for syntax documentation.
+
+# npcm7xx_adc.c
+npcm7xx_adc_read(const char *id, uint64_t offset, uint32_t value) " %s offset: 0x%04" PRIx64 " value 0x%04" PRIx32
+npcm7xx_adc_write(const char *id, uint64_t offset, uint32_t value) "%s offset: 0x%04" PRIx64 " value 0x%04" PRIx32
diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/tests/qtest/meson.build
+++ b/tests/qtest/meson.build
@@ -XXX,XX +XXX,XX @@ qtests_sparc64 = \
   ['prom-env-test', 'boot-serial-test']
 
 qtests_npcm7xx = \
-  ['npcm7xx_gpio-test',
+  ['npcm7xx_adc-test',
+   'npcm7xx_gpio-test',
    'npcm7xx_rng-test',
    'npcm7xx_timer-test',
    'npcm7xx_watchdog_timer-test']
-- 
2.20.1

From: Hao Wu <wuhaotsh@google.com>

The PWM module is part of NPCM7XX module. Each NPCM7XX module has two
identical PWM modules. Each module contains 4 PWM entries. Each PWM has
two outputs: frequency and duty_cycle. Both are computed using inputs
from software side.

This module does not model detail pulse signals since it is expensive.
It also does not model interrupts and watchdogs that are dependant on
the detail models. The interfaces for these are left in the module so
that anyone in need for these functionalities can implement on their
own.

The user can read the duty cycle and frequency using qom-get command.

diff --git a/docs/system/arm/nuvoton.rst b/docs/system/arm/nuvoton.rst
index XXXXXXX..XXXXXXX 100644
--- a/docs/system/arm/nuvoton.rst
+++ b/docs/system/arm/nuvoton.rst
@@ -XXX,XX +XXX,XX @@ Supported devices
  * USB host (USBH)
  * GPIO controller
  * Analog to Digital Converter (ADC)
+ * Pulse Width Modulation (PWM)
 
 Missing devices
 ---------------
@@ -XXX,XX +XXX,XX @@ Missing devices
  * Peripheral SPI controller (PSPI)
  * SD/MMC host
  * PECI interface
- * Pulse Width Modulation (PWM)
  * Tachometer
  * PCI and PCIe root complex and bridges
  * VDM and MCTP support
diff --git a/include/hw/arm/npcm7xx.h b/include/hw/arm/npcm7xx.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/npcm7xx.h
+++ b/include/hw/arm/npcm7xx.h
@@ -XXX,XX +XXX,XX @@
 #include "hw/mem/npcm7xx_mc.h"
 #include "hw/misc/npcm7xx_clk.h"
 #include "hw/misc/npcm7xx_gcr.h"
+#include "hw/misc/npcm7xx_pwm.h"
 #include "hw/misc/npcm7xx_rng.h"
 #include "hw/nvram/npcm7xx_otp.h"
 #include "hw/timer/npcm7xx_timer.h"
@@ -XXX,XX +XXX,XX @@ typedef struct NPCM7xxState {
     NPCM7xxCLKState     clk;
     NPCM7xxTimerCtrlState tim[3];
     NPCM7xxADCState     adc;
+    NPCM7xxPWMState     pwm[2];
     NPCM7xxOTPState     key_storage;
     NPCM7xxOTPState     fuse_array;
     NPCM7xxMCState      mc;
diff --git a/include/hw/misc/npcm7xx_pwm.h b/include/hw/misc/npcm7xx_pwm.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/include/hw/misc/npcm7xx_pwm.h
@@ -XXX,XX +XXX,XX @@
+/*
+ * Nuvoton NPCM7xx PWM Module
+ *
+ * Copyright 2020 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ */
+#ifndef NPCM7XX_PWM_H
+#define NPCM7XX_PWM_H
+
+#include "hw/clock.h"
+#include "hw/sysbus.h"
+#include "hw/irq.h"
+
+/* Each PWM module holds 4 PWM channels. */
+#define NPCM7XX_PWM_PER_MODULE 4
+
+/*
+ * Number of registers in one pwm module. Don't change this without increasing
+ * the version_id in vmstate.
+ */
+#define NPCM7XX_PWM_NR_REGS (0x54 / sizeof(uint32_t))
+
+/*
+ * The maximum duty values. Each duty unit represents 1/NPCM7XX_PWM_MAX_DUTY
+ * cycles. For example, if NPCM7XX_PWM_MAX_DUTY=1,000,000 and a PWM has a duty
+ * value of 100,000 the duty cycle for that PWM is 10%.
+ */
+#define NPCM7XX_PWM_MAX_DUTY 1000000
+
+typedef struct NPCM7xxPWMState NPCM7xxPWMState;
+
+/**
+ * struct NPCM7xxPWM - The state of a single PWM channel.
+ * @module: The PWM module that contains this channel.
+ * @irq: GIC interrupt line to fire on expiration if enabled.
+ * @running: Whether this PWM channel is generating output.
+ * @inverted: Whether this PWM channel is inverted.
+ * @index: The index of this PWM channel.
+ * @cnr: The counter register.
+ * @cmr: The comparator register.
+ * @pdr: The data register.
+ * @pwdr: The watchdog register.
+ * @freq: The frequency of this PWM channel.
+ * @duty: The duty cycle of this PWM channel. One unit represents
+ *   1/NPCM7XX_MAX_DUTY cycles.
+ */
+typedef struct NPCM7xxPWM {
+    NPCM7xxPWMState         *module;
+
+    qemu_irq                irq;
+
+    bool                    running;
+    bool                    inverted;
+
+    uint8_t                 index;
+    uint32_t                cnr;
+    uint32_t                cmr;
+    uint32_t                pdr;
+    uint32_t                pwdr;
+
+    uint32_t                freq;
+    uint32_t                duty;
+} NPCM7xxPWM;
+
+/**
+ * struct NPCM7xxPWMState - Pulse Width Modulation device state.
+ * @parent: System bus device.
+ * @iomem: Memory region through which registers are accessed.
+ * @clock: The PWM clock.
+ * @pwm: The PWM channels owned by this module.
+ * @ppr: The prescaler register.
+ * @csr: The clock selector register.
+ * @pcr: The control register.
+ * @pier: The interrupt enable register.
+ * @piir: The interrupt indication register.
+ */
+struct NPCM7xxPWMState {
+    SysBusDevice parent;
+
+    MemoryRegion iomem;
+
+    Clock       *clock;
+    NPCM7xxPWM pwm[NPCM7XX_PWM_PER_MODULE];
+
+    uint32_t    ppr;
+    uint32_t    csr;
+    uint32_t    pcr;
+    uint32_t    pier;
+    uint32_t    piir;
+};
+
+#define TYPE_NPCM7XX_PWM "npcm7xx-pwm"
+#define NPCM7XX_PWM(obj) \
+    OBJECT_CHECK(NPCM7xxPWMState, (obj), TYPE_NPCM7XX_PWM)
+
+#endif /* NPCM7XX_PWM_H */
diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/npcm7xx.c
+++ b/hw/arm/npcm7xx.c
@@ -XXX,XX +XXX,XX @@ enum NPCM7xxInterrupt {
     NPCM7XX_WDG2_IRQ,                   /* Timer Module 2 Watchdog */
     NPCM7XX_EHCI_IRQ            = 61,
     NPCM7XX_OHCI_IRQ            = 62,
+    NPCM7XX_PWM0_IRQ            = 93,   /* PWM module 0 */
+    NPCM7XX_PWM1_IRQ,                   /* PWM module 1 */
     NPCM7XX_GPIO0_IRQ           = 116,
     NPCM7XX_GPIO1_IRQ,
     NPCM7XX_GPIO2_IRQ,
@@ -XXX,XX +XXX,XX @@ static const hwaddr npcm7xx_fiu3_flash_addr[] = {
     0xb8000000, /* CS3 */
 };
 
+/* Register base address for each PWM Module */
+static const hwaddr npcm7xx_pwm_addr[] = {
+    0xf0103000,
+    0xf0104000,
+};
+
 static const struct {
     hwaddr regs_addr;
     uint32_t unconnected_pins;
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_init(Object *obj)
         object_initialize_child(obj, npcm7xx_fiu[i].name, &s->fiu[i],
                                 TYPE_NPCM7XX_FIU);
     }
+
+    for (i = 0; i < ARRAY_SIZE(s->pwm); i++) {
+        object_initialize_child(obj, "pwm[*]", &s->pwm[i], TYPE_NPCM7XX_PWM);
+    }
 }
 
 static void npcm7xx_realize(DeviceState *dev, Error **errp)
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_realize(DeviceState *dev, Error **errp)
     sysbus_connect_irq(SYS_BUS_DEVICE(&s->ohci), 0,
                        npcm7xx_irq(s, NPCM7XX_OHCI_IRQ));
 
+    /* PWM Modules. Cannot fail. */
+    QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_pwm_addr) != ARRAY_SIZE(s->pwm));
+    for (i = 0; i < ARRAY_SIZE(s->pwm); i++) {
+        SysBusDevice *sbd = SYS_BUS_DEVICE(&s->pwm[i]);
+
+        qdev_connect_clock_in(DEVICE(&s->pwm[i]), "clock", qdev_get_clock_out(
+                    DEVICE(&s->clk), "apb3-clock"));
+        sysbus_realize(sbd, &error_abort);
+        sysbus_mmio_map(sbd, 0, npcm7xx_pwm_addr[i]);
+        sysbus_connect_irq(sbd, i, npcm7xx_irq(s, NPCM7XX_PWM0_IRQ + i));
+    }
+
     /*
      * Flash Interface Unit (FIU). Can fail if incorrect number of chip selects
      * specified, but this is a programming error.
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_realize(DeviceState *dev, Error **errp)
     create_unimplemented_device("npcm7xx.peci",         0xf0100000,   4 * KiB);
     create_unimplemented_device("npcm7xx.siox[1]",      0xf0101000,   4 * KiB);
     create_unimplemented_device("npcm7xx.siox[2]",      0xf0102000,   4 * KiB);
-    create_unimplemented_device("npcm7xx.pwm[0]",       0xf0103000,   4 * KiB);
-    create_unimplemented_device("npcm7xx.pwm[1]",       0xf0104000,   4 * KiB);
     create_unimplemented_device("npcm7xx.mft[0]",       0xf0180000,   4 * KiB);
     create_unimplemented_device("npcm7xx.mft[1]",       0xf0181000,   4 * KiB);
     create_unimplemented_device("npcm7xx.mft[2]",       0xf0182000,   4 * KiB);
diff --git a/hw/misc/npcm7xx_pwm.c b/hw/misc/npcm7xx_pwm.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/hw/misc/npcm7xx_pwm.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * Nuvoton NPCM7xx PWM Module
+ *
+ * Copyright 2020 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ */
+
+#include "qemu/osdep.h"
+#include "hw/irq.h"
+#include "hw/qdev-clock.h"
+#include "hw/qdev-properties.h"
+#include "hw/misc/npcm7xx_pwm.h"
+#include "hw/registerfields.h"
+#include "migration/vmstate.h"
+#include "qemu/bitops.h"
+#include "qemu/error-report.h"
+#include "qemu/log.h"
+#include "qemu/module.h"
+#include "qemu/units.h"
+#include "trace.h"
+
+REG32(NPCM7XX_PWM_PPR, 0x00);
+REG32(NPCM7XX_PWM_CSR, 0x04);
+REG32(NPCM7XX_PWM_PCR, 0x08);
+REG32(NPCM7XX_PWM_CNR0, 0x0c);
+REG32(NPCM7XX_PWM_CMR0, 0x10);
+REG32(NPCM7XX_PWM_PDR0, 0x14);
+REG32(NPCM7XX_PWM_CNR1, 0x18);
+REG32(NPCM7XX_PWM_CMR1, 0x1c);
+REG32(NPCM7XX_PWM_PDR1, 0x20);
+REG32(NPCM7XX_PWM_CNR2, 0x24);
+REG32(NPCM7XX_PWM_CMR2, 0x28);
+REG32(NPCM7XX_PWM_PDR2, 0x2c);
+REG32(NPCM7XX_PWM_CNR3, 0x30);
+REG32(NPCM7XX_PWM_CMR3, 0x34);
+REG32(NPCM7XX_PWM_PDR3, 0x38);
+REG32(NPCM7XX_PWM_PIER, 0x3c);
+REG32(NPCM7XX_PWM_PIIR, 0x40);
+REG32(NPCM7XX_PWM_PWDR0, 0x44);
+REG32(NPCM7XX_PWM_PWDR1, 0x48);
+REG32(NPCM7XX_PWM_PWDR2, 0x4c);
+REG32(NPCM7XX_PWM_PWDR3, 0x50);
+
+/* Register field definitions. */
+#define NPCM7XX_PPR(rv, index)      extract32((rv), npcm7xx_ppr_base[index], 8)
+#define NPCM7XX_CSR(rv, index)      extract32((rv), npcm7xx_csr_base[index], 3)
+#define NPCM7XX_CH(rv, index)       extract32((rv), npcm7xx_ch_base[index], 4)
+#define NPCM7XX_CH_EN               BIT(0)
+#define NPCM7XX_CH_INV              BIT(2)
+#define NPCM7XX_CH_MOD              BIT(3)
+
+/* Offset of each PWM channel's prescaler in the PPR register. */
+static const int npcm7xx_ppr_base[] = { 0, 0, 8, 8 };
+/* Offset of each PWM channel's clock selector in the CSR register. */
+static const int npcm7xx_csr_base[] = { 0, 4, 8, 12 };
+/* Offset of each PWM channel's control variable in the PCR register. */
+static const int npcm7xx_ch_base[] = { 0, 8, 12, 16 };
+
+static uint32_t npcm7xx_pwm_calculate_freq(NPCM7xxPWM *p)
+{
+    uint32_t ppr;
+    uint32_t csr;
+    uint32_t freq;
+
+    if (!p->running) {
+        return 0;
+    }
+
+    csr = NPCM7XX_CSR(p->module->csr, p->index);
+    ppr = NPCM7XX_PPR(p->module->ppr, p->index);
+    freq = clock_get_hz(p->module->clock);
+    freq /= ppr + 1;
+    /* csr can only be 0~4 */
+    if (csr > 4) {
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: invalid csr value %u\n",
+                      __func__, csr);
+        csr = 4;
+    }
+    /* freq won't be changed if csr == 4. */
+    if (csr < 4) {
+        freq >>= csr + 1;
+    }
+
+    return freq / (p->cnr + 1);
+}
+
+static uint32_t npcm7xx_pwm_calculate_duty(NPCM7xxPWM *p)
+{
+    uint64_t duty;
+
+    if (p->running) {
+        if (p->cnr == 0) {
+            duty = 0;
+        } else if (p->cmr >= p->cnr) {
+            duty = NPCM7XX_PWM_MAX_DUTY;
+        } else {
+            duty = NPCM7XX_PWM_MAX_DUTY * (p->cmr + 1) / (p->cnr + 1);
+        }
+    } else {
+        duty = 0;
+    }
+
+    if (p->inverted) {
+        duty = NPCM7XX_PWM_MAX_DUTY - duty;
+    }
+
+    return duty;
+}
+
+static void npcm7xx_pwm_update_freq(NPCM7xxPWM *p)
+{
+    uint32_t freq = npcm7xx_pwm_calculate_freq(p);
+
+    if (freq != p->freq) {
+        trace_npcm7xx_pwm_update_freq(DEVICE(p->module)->canonical_path,
+                                      p->index, p->freq, freq);
+        p->freq = freq;
+    }
+}
+
+static void npcm7xx_pwm_update_duty(NPCM7xxPWM *p)
+{
+    uint32_t duty = npcm7xx_pwm_calculate_duty(p);
+
+    if (duty != p->duty) {
+        trace_npcm7xx_pwm_update_duty(DEVICE(p->module)->canonical_path,
+                                      p->index, p->duty, duty);
+        p->duty = duty;
+    }
+}
+
+static void npcm7xx_pwm_update_output(NPCM7xxPWM *p)
+{
+    npcm7xx_pwm_update_freq(p);
+    npcm7xx_pwm_update_duty(p);
+}
+
+static void npcm7xx_pwm_write_ppr(NPCM7xxPWMState *s, uint32_t new_ppr)
+{
+    int i;
+    uint32_t old_ppr = s->ppr;
+
+    QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_ppr_base) != NPCM7XX_PWM_PER_MODULE);
+    s->ppr = new_ppr;
+    for (i = 0; i < NPCM7XX_PWM_PER_MODULE; ++i) {
+        if (NPCM7XX_PPR(old_ppr, i) != NPCM7XX_PPR(new_ppr, i)) {
+            npcm7xx_pwm_update_freq(&s->pwm[i]);
+        }
+    }
+}
+
+static void npcm7xx_pwm_write_csr(NPCM7xxPWMState *s, uint32_t new_csr)
+{
+    int i;
+    uint32_t old_csr = s->csr;
+
+    QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_csr_base) != NPCM7XX_PWM_PER_MODULE);
+    s->csr = new_csr;
+    for (i = 0; i < NPCM7XX_PWM_PER_MODULE; ++i) {
+        if (NPCM7XX_CSR(old_csr, i) != NPCM7XX_CSR(new_csr, i)) {
+            npcm7xx_pwm_update_freq(&s->pwm[i]);
+        }
+    }
+}
+
+static void npcm7xx_pwm_write_pcr(NPCM7xxPWMState *s, uint32_t new_pcr)
+{
+    int i;
+    bool inverted;
+    uint32_t pcr;
+    NPCM7xxPWM *p;
+
+    s->pcr = new_pcr;
+    QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_ch_base) != NPCM7XX_PWM_PER_MODULE);
+    for (i = 0; i < NPCM7XX_PWM_PER_MODULE; ++i) {
+        p = &s->pwm[i];
+        pcr = NPCM7XX_CH(new_pcr, i);
+        inverted = pcr & NPCM7XX_CH_INV;
+
+        /*
+         * We only run a PWM channel with toggle mode. Single-shot mode does not
+         * generate frequency and duty-cycle values.
+         */
+        if ((pcr & NPCM7XX_CH_EN) && (pcr & NPCM7XX_CH_MOD)) {
+            if (p->running) {
+                /* Re-run this PWM channel if inverted changed. */
+                if (p->inverted ^ inverted) {
+                    p->inverted = inverted;
+                    npcm7xx_pwm_update_duty(p);
+                }
+            } else {
+                /* Run this PWM channel. */
+                p->running = true;
+                p->inverted = inverted;
+                npcm7xx_pwm_update_output(p);
+            }
+        } else {
+            /* Clear this PWM channel. */
+            p->running = false;
+            p->inverted = inverted;
+            npcm7xx_pwm_update_output(p);
+        }
+    }
+
+}
+
+static hwaddr npcm7xx_cnr_index(hwaddr offset)
+{
+    switch (offset) {
+    case A_NPCM7XX_PWM_CNR0:
+        return 0;
+    case A_NPCM7XX_PWM_CNR1:
+        return 1;
+    case A_NPCM7XX_PWM_CNR2:
+        return 2;
+    case A_NPCM7XX_PWM_CNR3:
+        return 3;
+    default:
+        g_assert_not_reached();
+    }
+}
+
+static hwaddr npcm7xx_cmr_index(hwaddr offset)
+{
+    switch (offset) {
+    case A_NPCM7XX_PWM_CMR0:
+        return 0;
+    case A_NPCM7XX_PWM_CMR1:
+        return 1;
+    case A_NPCM7XX_PWM_CMR2:
+        return 2;
+    case A_NPCM7XX_PWM_CMR3:
+        return 3;
+    default:
+        g_assert_not_reached();
+    }
+}
+
+static hwaddr npcm7xx_pdr_index(hwaddr offset)
+{
+    switch (offset) {
+    case A_NPCM7XX_PWM_PDR0:
+        return 0;
+    case A_NPCM7XX_PWM_PDR1:
+        return 1;
+    case A_NPCM7XX_PWM_PDR2:
+        return 2;
+    case A_NPCM7XX_PWM_PDR3:
+        return 3;
+    default:
+        g_assert_not_reached();
+    }
+}
+
+static hwaddr npcm7xx_pwdr_index(hwaddr offset)
+{
+    switch (offset) {
+    case A_NPCM7XX_PWM_PWDR0:
+        return 0;
+    case A_NPCM7XX_PWM_PWDR1:
+        return 1;
+    case A_NPCM7XX_PWM_PWDR2:
+        return 2;
+    case A_NPCM7XX_PWM_PWDR3:
+        return 3;
+    default:
+        g_assert_not_reached();
+    }
+}
+
+static uint64_t npcm7xx_pwm_read(void *opaque, hwaddr offset, unsigned size)
+{
+    NPCM7xxPWMState *s = opaque;
+    uint64_t value = 0;
+
+    switch (offset) {
+    case A_NPCM7XX_PWM_CNR0:
+    case A_NPCM7XX_PWM_CNR1:
+    case A_NPCM7XX_PWM_CNR2:
+    case A_NPCM7XX_PWM_CNR3:
+        value = s->pwm[npcm7xx_cnr_index(offset)].cnr;
+        break;
+
+    case A_NPCM7XX_PWM_CMR0:
+    case A_NPCM7XX_PWM_CMR1:
+    case A_NPCM7XX_PWM_CMR2:
+    case A_NPCM7XX_PWM_CMR3:
+        value = s->pwm[npcm7xx_cmr_index(offset)].cmr;
+        break;
+
+    case A_NPCM7XX_PWM_PDR0:
+    case A_NPCM7XX_PWM_PDR1:
+    case A_NPCM7XX_PWM_PDR2:
+    case A_NPCM7XX_PWM_PDR3:
+        value = s->pwm[npcm7xx_pdr_index(offset)].pdr;
+        break;
+
+    case A_NPCM7XX_PWM_PWDR0:
+    case A_NPCM7XX_PWM_PWDR1:
+    case A_NPCM7XX_PWM_PWDR2:
+    case A_NPCM7XX_PWM_PWDR3:
+        value = s->pwm[npcm7xx_pwdr_index(offset)].pwdr;
+        break;
+
+    case A_NPCM7XX_PWM_PPR:
+        value = s->ppr;
+        break;
+
+    case A_NPCM7XX_PWM_CSR:
+        value = s->csr;
+        break;
+
+    case A_NPCM7XX_PWM_PCR:
+        value = s->pcr;
+        break;
+
+    case A_NPCM7XX_PWM_PIER:
+        value = s->pier;
+        break;
+
+    case A_NPCM7XX_PWM_PIIR:
+        value = s->piir;
+        break;
+
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: invalid offset 0x%04" HWADDR_PRIx "\n",
+                      __func__, offset);
+        break;
+    }
+
+    trace_npcm7xx_pwm_read(DEVICE(s)->canonical_path, offset, value);
+    return value;
+}
+
+static void npcm7xx_pwm_write(void *opaque, hwaddr offset,
+                                uint64_t v, unsigned size)
+{
+    NPCM7xxPWMState *s = opaque;
+    NPCM7xxPWM *p;
+    uint32_t value = v;
+
+    trace_npcm7xx_pwm_write(DEVICE(s)->canonical_path, offset, value);
+    switch (offset) {
+    case A_NPCM7XX_PWM_CNR0:
+    case A_NPCM7XX_PWM_CNR1:
+    case A_NPCM7XX_PWM_CNR2:
+    case A_NPCM7XX_PWM_CNR3:
+        p = &s->pwm[npcm7xx_cnr_index(offset)];
+        p->cnr = value;
+        npcm7xx_pwm_update_output(p);
+        break;
+
+    case A_NPCM7XX_PWM_CMR0:
+    case A_NPCM7XX_PWM_CMR1:
+    case A_NPCM7XX_PWM_CMR2:
+    case A_NPCM7XX_PWM_CMR3:
+        p = &s->pwm[npcm7xx_cmr_index(offset)];
+        p->cmr = value;
+        npcm7xx_pwm_update_output(p);
+        break;
+
+    case A_NPCM7XX_PWM_PDR0:
+    case A_NPCM7XX_PWM_PDR1:
+    case A_NPCM7XX_PWM_PDR2:
+    case A_NPCM7XX_PWM_PDR3:
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: register @ 0x%04" HWADDR_PRIx " is read-only\n",
+                      __func__, offset);
+        break;
+
+    case A_NPCM7XX_PWM_PWDR0:
+    case A_NPCM7XX_PWM_PWDR1:
+    case A_NPCM7XX_PWM_PWDR2:
+    case A_NPCM7XX_PWM_PWDR3:
+        qemu_log_mask(LOG_UNIMP,
+                     "%s: register @ 0x%04" HWADDR_PRIx " is not implemented\n",
+                     __func__, offset);
+        break;
+
+    case A_NPCM7XX_PWM_PPR:
+        npcm7xx_pwm_write_ppr(s, value);
+        break;
+
+    case A_NPCM7XX_PWM_CSR:
+        npcm7xx_pwm_write_csr(s, value);
+        break;
+
+    case A_NPCM7XX_PWM_PCR:
+        npcm7xx_pwm_write_pcr(s, value);
+        break;
+
+    case A_NPCM7XX_PWM_PIER:
+        qemu_log_mask(LOG_UNIMP,
+                     "%s: register @ 0x%04" HWADDR_PRIx " is not implemented\n",
+                     __func__, offset);
+        break;
+
+    case A_NPCM7XX_PWM_PIIR:
+        qemu_log_mask(LOG_UNIMP,
+                     "%s: register @ 0x%04" HWADDR_PRIx " is not implemented\n",
+                     __func__, offset);
+        break;
+
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: invalid offset 0x%04" HWADDR_PRIx "\n",
+                      __func__, offset);
+        break;
+    }
+}
+
+static const struct MemoryRegionOps npcm7xx_pwm_ops = {
+    .read       = npcm7xx_pwm_read,
+    .write      = npcm7xx_pwm_write,
+    .endianness = DEVICE_LITTLE_ENDIAN,
+    .valid      = {
+        .min_access_size        = 4,
+        .max_access_size        = 4,
+        .unaligned              = false,
+    },
+};
+
+static void npcm7xx_pwm_enter_reset(Object *obj, ResetType type)
+{
+    NPCM7xxPWMState *s = NPCM7XX_PWM(obj);
+    int i;
+
+    for (i = 0; i < NPCM7XX_PWM_PER_MODULE; i++) {
+        NPCM7xxPWM *p = &s->pwm[i];
+
+        p->cnr = 0x00000000;
+        p->cmr = 0x00000000;
+        p->pdr = 0x00000000;
+        p->pwdr = 0x00000000;
+    }
+
+    s->ppr = 0x00000000;
+    s->csr = 0x00000000;
+    s->pcr = 0x00000000;
+    s->pier = 0x00000000;
+    s->piir = 0x00000000;
+}
+
+static void npcm7xx_pwm_hold_reset(Object *obj)
+{
+    NPCM7xxPWMState *s = NPCM7XX_PWM(obj);
+    int i;
+
+    for (i = 0; i < NPCM7XX_PWM_PER_MODULE; i++) {
+        qemu_irq_lower(s->pwm[i].irq);
+    }
+}
+
+static void npcm7xx_pwm_init(Object *obj)
+{
+    NPCM7xxPWMState *s = NPCM7XX_PWM(obj);
+    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
+    int i;
+
+    for (i = 0; i < NPCM7XX_PWM_PER_MODULE; i++) {
+        NPCM7xxPWM *p = &s->pwm[i];
+        p->module = s;
+        p->index = i;
+        sysbus_init_irq(sbd, &p->irq);
+    }
+
+    memory_region_init_io(&s->iomem, obj, &npcm7xx_pwm_ops, s,
+                          TYPE_NPCM7XX_PWM, 4 * KiB);
+    sysbus_init_mmio(sbd, &s->iomem);
+    s->clock = qdev_init_clock_in(DEVICE(s), "clock", NULL, NULL);
+
+    for (i = 0; i < NPCM7XX_PWM_PER_MODULE; ++i) {
+        object_property_add_uint32_ptr(obj, "freq[*]",
+                &s->pwm[i].freq, OBJ_PROP_FLAG_READ);
+        object_property_add_uint32_ptr(obj, "duty[*]",
+                &s->pwm[i].duty, OBJ_PROP_FLAG_READ);
+    }
+}
+
+static const VMStateDescription vmstate_npcm7xx_pwm = {
+    .name = "npcm7xx-pwm",
+    .version_id = 0,
+    .minimum_version_id = 0,
+    .fields = (VMStateField[]) {
+        VMSTATE_BOOL(running, NPCM7xxPWM),
+        VMSTATE_BOOL(inverted, NPCM7xxPWM),
+        VMSTATE_UINT8(index, NPCM7xxPWM),
+        VMSTATE_UINT32(cnr, NPCM7xxPWM),
+        VMSTATE_UINT32(cmr, NPCM7xxPWM),
+        VMSTATE_UINT32(pdr, NPCM7xxPWM),
+        VMSTATE_UINT32(pwdr, NPCM7xxPWM),
+        VMSTATE_UINT32(freq, NPCM7xxPWM),
+        VMSTATE_UINT32(duty, NPCM7xxPWM),
+        VMSTATE_END_OF_LIST(),
+    },
+};
+
+static const VMStateDescription vmstate_npcm7xx_pwm_module = {
+    .name = "npcm7xx-pwm-module",
+    .version_id = 0,
+    .minimum_version_id = 0,
+    .fields = (VMStateField[]) {
+        VMSTATE_CLOCK(clock, NPCM7xxPWMState),
+        VMSTATE_STRUCT_ARRAY(pwm, NPCM7xxPWMState,
+                             NPCM7XX_PWM_PER_MODULE, 0, vmstate_npcm7xx_pwm,
+                             NPCM7xxPWM),
+        VMSTATE_UINT32(ppr, NPCM7xxPWMState),
+        VMSTATE_UINT32(csr, NPCM7xxPWMState),
+        VMSTATE_UINT32(pcr, NPCM7xxPWMState),
+        VMSTATE_UINT32(pier, NPCM7xxPWMState),
+        VMSTATE_UINT32(piir, NPCM7xxPWMState),
+        VMSTATE_END_OF_LIST(),
+    },
+};
+
+static void npcm7xx_pwm_class_init(ObjectClass *klass, void *data)
+{
+    ResettableClass *rc = RESETTABLE_CLASS(klass);
+    DeviceClass *dc = DEVICE_CLASS(klass);
+
+    dc->desc = "NPCM7xx PWM Controller";
+    dc->vmsd = &vmstate_npcm7xx_pwm_module;
+    rc->phases.enter = npcm7xx_pwm_enter_reset;
+    rc->phases.hold = npcm7xx_pwm_hold_reset;
+}
+
+static const TypeInfo npcm7xx_pwm_info = {
+    .name               = TYPE_NPCM7XX_PWM,
+    .parent             = TYPE_SYS_BUS_DEVICE,
+    .instance_size      = sizeof(NPCM7xxPWMState),
+    .class_init         = npcm7xx_pwm_class_init,
+    .instance_init      = npcm7xx_pwm_init,
+};
+
+static void npcm7xx_pwm_register_type(void)
+{
+    type_register_static(&npcm7xx_pwm_info);
+}
+type_init(npcm7xx_pwm_register_type);
diff --git a/hw/misc/meson.build b/hw/misc/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/hw/misc/meson.build
+++ b/hw/misc/meson.build
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_MAINSTONE', if_true: files('mst_fpga.c'))
 softmmu_ss.add(when: 'CONFIG_NPCM7XX', if_true: files(
   'npcm7xx_clk.c',
   'npcm7xx_gcr.c',
+  'npcm7xx_pwm.c',
   'npcm7xx_rng.c',
 ))
 softmmu_ss.add(when: 'CONFIG_OMAP', if_true: files(
diff --git a/hw/misc/trace-events b/hw/misc/trace-events
index XXXXXXX..XXXXXXX 100644
--- a/hw/misc/trace-events
+++ b/hw/misc/trace-events
@@ -XXX,XX +XXX,XX @@ npcm7xx_gcr_write(uint64_t offset, uint32_t value) "offset: 0x%04" PRIx64 " valu
 npcm7xx_rng_read(uint64_t offset, uint64_t value, unsigned size) "offset: 0x%04" PRIx64 " value: 0x%02" PRIx64 " size: %u"
 npcm7xx_rng_write(uint64_t offset, uint64_t value, unsigned size) "offset: 0x%04" PRIx64 " value: 0x%02" PRIx64 " size: %u"
 
+# npcm7xx_pwm.c
+npcm7xx_pwm_read(const char *id, uint64_t offset, uint32_t value) "%s offset: 0x%04" PRIx64 " value: 0x%08" PRIx32
+npcm7xx_pwm_write(const char *id, uint64_t offset, uint32_t value) "%s offset: 0x%04" PRIx64 " value: 0x%08" PRIx32
+npcm7xx_pwm_update_freq(const char *id, uint8_t index, uint32_t old_value, uint32_t new_value) "%s pwm[%u] Update Freq: old_freq: %u, new_freq: %u"
+npcm7xx_pwm_update_duty(const char *id, uint8_t index, uint32_t old_value, uint32_t new_value) "%s pwm[%u] Update Duty: old_duty: %u, new_duty: %u"
+
 # stm32f4xx_syscfg.c
 stm32f4xx_syscfg_set_irq(int gpio, int line, int level) "Interupt: GPIO: %d, Line: %d; Level: %d"
 stm32f4xx_pulse_exti(int irq) "Pulse EXTI: %d"
-- 
2.20.1

From: Hao Wu <wuhaotsh@google.com>

We add a qtest for the PWM in the previous patch. It proves it works as
expected.

Reviewed-by: Havard Skinnemoen <hskinnemoen@google.com>
Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
Signed-off-by: Hao Wu <wuhaotsh@google.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20210108190945.949196-6-wuhaotsh@google.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 tests/qtest/npcm7xx_pwm-test.c | 490 +++++++++++++++++++++++++++++++++
 tests/qtest/meson.build        |   1 +
 2 files changed, 491 insertions(+)
 create mode 100644 tests/qtest/npcm7xx_pwm-test.c

diff --git a/tests/qtest/npcm7xx_pwm-test.c b/tests/qtest/npcm7xx_pwm-test.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/tests/qtest/npcm7xx_pwm-test.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * QTests for Nuvoton NPCM7xx PWM Modules.
+ *
+ * Copyright 2020 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/bitops.h"
+#include "libqos/libqtest.h"
+#include "qapi/qmp/qdict.h"
+#include "qapi/qmp/qnum.h"
+
+#define REF_HZ          25000000
+
+/* Register field definitions. */
+#define CH_EN           BIT(0)
+#define CH_INV          BIT(2)
+#define CH_MOD          BIT(3)
+
+/* Registers shared between all PWMs in a module */
+#define PPR             0x00
+#define CSR             0x04
+#define PCR             0x08
+#define PIER            0x3c
+#define PIIR            0x40
+
+/* CLK module related */
+#define CLK_BA          0xf0801000
+#define CLKSEL          0x04
+#define CLKDIV1         0x08
+#define CLKDIV2         0x2c
+#define PLLCON0         0x0c
+#define PLLCON1         0x10
+#define PLL_INDV(rv)    extract32((rv), 0, 6)
+#define PLL_FBDV(rv)    extract32((rv), 16, 12)
+#define PLL_OTDV1(rv)   extract32((rv), 8, 3)
+#define PLL_OTDV2(rv)   extract32((rv), 13, 3)
+#define APB3CKDIV(rv)   extract32((rv), 28, 2)
+#define CLK2CKDIV(rv)   extract32((rv), 0, 1)
+#define CLK4CKDIV(rv)   extract32((rv), 26, 2)
+#define CPUCKSEL(rv)    extract32((rv), 0, 2)
+
+#define MAX_DUTY        1000000
+
+typedef struct PWMModule {
+    int irq;
+    uint64_t base_addr;
+} PWMModule;
+
+typedef struct PWM {
+    uint32_t cnr_offset;
+    uint32_t cmr_offset;
+    uint32_t pdr_offset;
+    uint32_t pwdr_offset;
+} PWM;
+
+typedef struct TestData {
+    const PWMModule *module;
+    const PWM *pwm;
+} TestData;
+
+static const PWMModule pwm_module_list[] = {
+    {
+        .irq        = 93,
+        .base_addr  = 0xf0103000
+    },
+    {
+        .irq        = 94,
+        .base_addr  = 0xf0104000
+    }
+};
+
+static const PWM pwm_list[] = {
+    {
+        .cnr_offset     = 0x0c,
+        .cmr_offset     = 0x10,
+        .pdr_offset     = 0x14,
+        .pwdr_offset    = 0x44,
+    },
+    {
+        .cnr_offset     = 0x18,
+        .cmr_offset     = 0x1c,
+        .pdr_offset     = 0x20,
+        .pwdr_offset    = 0x48,
+    },
+    {
+        .cnr_offset     = 0x24,
+        .cmr_offset     = 0x28,
+        .pdr_offset     = 0x2c,
+        .pwdr_offset    = 0x4c,
+    },
+    {
+        .cnr_offset     = 0x30,
+        .cmr_offset     = 0x34,
+        .pdr_offset     = 0x38,
+        .pwdr_offset    = 0x50,
+    },
+};
+
+static const int ppr_base[] = { 0, 0, 8, 8 };
+static const int csr_base[] = { 0, 4, 8, 12 };
+static const int pcr_base[] = { 0, 8, 12, 16 };
+
+static const uint32_t ppr_list[] = {
+    0,
+    1,
+    10,
+    100,
+    255, /* Max possible value. */
+};
+
+static const uint32_t csr_list[] = {
+    0,
+    1,
+    2,
+    3,
+    4, /* Max possible value. */
+};
+
+static const uint32_t cnr_list[] = {
+    0,
+    1,
+    50,
+    100,
+    150,
+    200,
+    1000,
+    10000,
+    65535, /* Max possible value. */
+};
+
+static const uint32_t cmr_list[] = {
+    0,
+    1,
+    10,
+    50,
+    100,
+    150,
+    200,
+    1000,
+    10000,
+    65535, /* Max possible value. */
+};
+
+/* Returns the index of the PWM module. */
+static int pwm_module_index(const PWMModule *module)
+{
+    ptrdiff_t diff = module - pwm_module_list;
+
+    g_assert_true(diff >= 0 && diff < ARRAY_SIZE(pwm_module_list));
+
+    return diff;
+}
+
+/* Returns the index of the PWM entry. */
+static int pwm_index(const PWM *pwm)
+{
+    ptrdiff_t diff = pwm - pwm_list;
+
+    g_assert_true(diff >= 0 && diff < ARRAY_SIZE(pwm_list));
+
+    return diff;
+}
+
+static uint64_t pwm_qom_get(QTestState *qts, const char *path, const char *name)
+{
+    QDict *response;
+
+    g_test_message("Getting properties %s from %s", name, path);
+    response = qtest_qmp(qts, "{ 'execute': 'qom-get',"
+            " 'arguments': { 'path': %s, 'property': %s}}",
+            path, name);
+    /* The qom set message returns successfully. */
+    g_assert_true(qdict_haskey(response, "return"));
+    return qnum_get_uint(qobject_to(QNum, qdict_get(response, "return")));
+}
+
+static uint64_t pwm_get_freq(QTestState *qts, int module_index, int pwm_index)
+{
+    char path[100];
+    char name[100];
+
+    sprintf(path, "/machine/soc/pwm[%d]", module_index);
+    sprintf(name, "freq[%d]", pwm_index);
+
+    return pwm_qom_get(qts, path, name);
+}
+
+static uint64_t pwm_get_duty(QTestState *qts, int module_index, int pwm_index)
+{
+    char path[100];
+    char name[100];
+
+    sprintf(path, "/machine/soc/pwm[%d]", module_index);
+    sprintf(name, "duty[%d]", pwm_index);
+
+    return pwm_qom_get(qts, path, name);
+}
+
+static uint32_t get_pll(uint32_t con)
+{
+    return REF_HZ * PLL_FBDV(con) / (PLL_INDV(con) * PLL_OTDV1(con)
+            * PLL_OTDV2(con));
+}
+
+static uint64_t read_pclk(QTestState *qts)
+{
+    uint64_t freq = REF_HZ;
+    uint32_t clksel = qtest_readl(qts, CLK_BA + CLKSEL);
+    uint32_t pllcon;
+    uint32_t clkdiv1 = qtest_readl(qts, CLK_BA + CLKDIV1);
+    uint32_t clkdiv2 = qtest_readl(qts, CLK_BA + CLKDIV2);
+
+    switch (CPUCKSEL(clksel)) {
+    case 0:
+        pllcon = qtest_readl(qts, CLK_BA + PLLCON0);
+        freq = get_pll(pllcon);
+        break;
+    case 1:
+        pllcon = qtest_readl(qts, CLK_BA + PLLCON1);
+        freq = get_pll(pllcon);
+        break;
+    case 2:
+        break;
+    case 3:
+        break;
+    default:
+        g_assert_not_reached();
+    }
+
+    freq >>= (CLK2CKDIV(clkdiv1) + CLK4CKDIV(clkdiv1) + APB3CKDIV(clkdiv2));
+
+    return freq;
+}
+
+static uint32_t pwm_selector(uint32_t csr)
+{
+    switch (csr) {
+    case 0:
+        return 2;
+    case 1:
+        return 4;
+    case 2:
+        return 8;
+    case 3:
+        return 16;
+    case 4:
+        return 1;
+    default:
+        g_assert_not_reached();
+    }
+}
+
+static uint64_t pwm_compute_freq(QTestState *qts, uint32_t ppr, uint32_t csr,
+        uint32_t cnr)
+{
+    return read_pclk(qts) / ((ppr + 1) * pwm_selector(csr) * (cnr + 1));
+}
+
+static uint64_t pwm_compute_duty(uint32_t cnr, uint32_t cmr, bool inverted)
+{
+    uint64_t duty;
+
+    if (cnr == 0) {
+        /* PWM is stopped. */
+        duty = 0;
+    } else if (cmr >= cnr) {
+        duty = MAX_DUTY;
+    } else {
+        duty = MAX_DUTY * (cmr + 1) / (cnr + 1);
+    }
+
+    if (inverted) {
+        duty = MAX_DUTY - duty;
+    }
+
+    return duty;
+}
+
+static uint32_t pwm_read(QTestState *qts, const TestData *td, unsigned offset)
+{
+    return qtest_readl(qts, td->module->base_addr + offset);
+}
+
+static void pwm_write(QTestState *qts, const TestData *td, unsigned offset,
+        uint32_t value)
+{
+    qtest_writel(qts, td->module->base_addr + offset, value);
+}
+
+static uint32_t pwm_read_ppr(QTestState *qts, const TestData *td)
+{
+    return extract32(pwm_read(qts, td, PPR), ppr_base[pwm_index(td->pwm)], 8);
+}
+
+static void pwm_write_ppr(QTestState *qts, const TestData *td, uint32_t value)
+{
+    pwm_write(qts, td, PPR, value << ppr_base[pwm_index(td->pwm)]);
+}
+
+static uint32_t pwm_read_csr(QTestState *qts, const TestData *td)
+{
+    return extract32(pwm_read(qts, td, CSR), csr_base[pwm_index(td->pwm)], 3);
+}
+
+static void pwm_write_csr(QTestState *qts, const TestData *td, uint32_t value)
+{
+    pwm_write(qts, td, CSR, value << csr_base[pwm_index(td->pwm)]);
+}
+
+static uint32_t pwm_read_pcr(QTestState *qts, const TestData *td)
+{
+    return extract32(pwm_read(qts, td, PCR), pcr_base[pwm_index(td->pwm)], 4);
+}
+
+static void pwm_write_pcr(QTestState *qts, const TestData *td, uint32_t value)
+{
+    pwm_write(qts, td, PCR, value << pcr_base[pwm_index(td->pwm)]);
+}
+
+static uint32_t pwm_read_cnr(QTestState *qts, const TestData *td)
+{
+    return pwm_read(qts, td, td->pwm->cnr_offset);
+}
+
+static void pwm_write_cnr(QTestState *qts, const TestData *td, uint32_t value)
+{
+    pwm_write(qts, td, td->pwm->cnr_offset, value);
+}
+
+static uint32_t pwm_read_cmr(QTestState *qts, const TestData *td)
+{
+    return pwm_read(qts, td, td->pwm->cmr_offset);
+}
+
+static void pwm_write_cmr(QTestState *qts, const TestData *td, uint32_t value)
+{
+    pwm_write(qts, td, td->pwm->cmr_offset, value);
+}
+
+/* Check pwm registers can be reset to default value */
+static void test_init(gconstpointer test_data)
+{
+    const TestData *td = test_data;
+    QTestState *qts = qtest_init("-machine quanta-gsj");
+    int module = pwm_module_index(td->module);
+    int pwm = pwm_index(td->pwm);
+
+    g_assert_cmpuint(pwm_get_freq(qts, module, pwm), ==, 0);
+    g_assert_cmpuint(pwm_get_duty(qts, module, pwm), ==, 0);
+
+    qtest_quit(qts);
+}
+
+/* One-shot mode should not change frequency and duty cycle. */
+static void test_oneshot(gconstpointer test_data)
+{
+    const TestData *td = test_data;
+    QTestState *qts = qtest_init("-machine quanta-gsj");
+    int module = pwm_module_index(td->module);
+    int pwm = pwm_index(td->pwm);
+    uint32_t ppr, csr, pcr;
+    int i, j;
+
+    pcr = CH_EN;
+    for (i = 0; i < ARRAY_SIZE(ppr_list); ++i) {
+        ppr = ppr_list[i];
+        pwm_write_ppr(qts, td, ppr);
+
+        for (j = 0; j < ARRAY_SIZE(csr_list); ++j) {
+            csr = csr_list[j];
+            pwm_write_csr(qts, td, csr);
+            pwm_write_pcr(qts, td, pcr);
+
+            g_assert_cmpuint(pwm_read_ppr(qts, td), ==, ppr);
+            g_assert_cmpuint(pwm_read_csr(qts, td), ==, csr);
+            g_assert_cmpuint(pwm_read_pcr(qts, td), ==, pcr);
+            g_assert_cmpuint(pwm_get_freq(qts, module, pwm), ==, 0);
+            g_assert_cmpuint(pwm_get_duty(qts, module, pwm), ==, 0);
+        }
+    }
+
+    qtest_quit(qts);
+}
+
+/* In toggle mode, the PWM generates correct outputs. */
+static void test_toggle(gconstpointer test_data)
+{
+    const TestData *td = test_data;
+    QTestState *qts = qtest_init("-machine quanta-gsj");
+    int module = pwm_module_index(td->module);
+    int pwm = pwm_index(td->pwm);
+    uint32_t ppr, csr, pcr, cnr, cmr;
+    int i, j, k, l;
+    uint64_t expected_freq, expected_duty;
+
+    pcr = CH_EN | CH_MOD;
+    for (i = 0; i < ARRAY_SIZE(ppr_list); ++i) {
+        ppr = ppr_list[i];
+        pwm_write_ppr(qts, td, ppr);
+
+        for (j = 0; j < ARRAY_SIZE(csr_list); ++j) {
+            csr = csr_list[j];
+            pwm_write_csr(qts, td, csr);
+
+            for (k = 0; k < ARRAY_SIZE(cnr_list); ++k) {
+                cnr = cnr_list[k];
+                pwm_write_cnr(qts, td, cnr);
+
+                for (l = 0; l < ARRAY_SIZE(cmr_list); ++l) {
+                    cmr = cmr_list[l];
+                    pwm_write_cmr(qts, td, cmr);
+                    expected_freq = pwm_compute_freq(qts, ppr, csr, cnr);
+                    expected_duty = pwm_compute_duty(cnr, cmr, false);
+
+                    pwm_write_pcr(qts, td, pcr);
+                    g_assert_cmpuint(pwm_read_ppr(qts, td), ==, ppr);
+                    g_assert_cmpuint(pwm_read_csr(qts, td), ==, csr);
+                    g_assert_cmpuint(pwm_read_pcr(qts, td), ==, pcr);
+                    g_assert_cmpuint(pwm_read_cnr(qts, td), ==, cnr);
+                    g_assert_cmpuint(pwm_read_cmr(qts, td), ==, cmr);
+                    g_assert_cmpuint(pwm_get_duty(qts, module, pwm),
+                            ==, expected_duty);
+                    if (expected_duty != 0 && expected_duty != 100) {
+                        /* Duty cycle with 0 or 100 doesn't need frequency. */
+                        g_assert_cmpuint(pwm_get_freq(qts, module, pwm),
+                                ==, expected_freq);
+                    }
+
+                    /* Test inverted mode */
+                    expected_duty = pwm_compute_duty(cnr, cmr, true);
+                    pwm_write_pcr(qts, td, pcr | CH_INV);
+                    g_assert_cmpuint(pwm_read_pcr(qts, td), ==, pcr | CH_INV);
+                    g_assert_cmpuint(pwm_get_duty(qts, module, pwm),
+                            ==, expected_duty);
+                    if (expected_duty != 0 && expected_duty != 100) {
+                        /* Duty cycle with 0 or 100 doesn't need frequency. */
+                        g_assert_cmpuint(pwm_get_freq(qts, module, pwm),
+                                ==, expected_freq);
+                    }
+
+                }
+            }
+        }
+    }
+
+    qtest_quit(qts);
+}
+
+static void pwm_add_test(const char *name, const TestData* td,
+        GTestDataFunc fn)
+{
+    g_autofree char *full_name = g_strdup_printf(
+            "npcm7xx_pwm/module[%d]/pwm[%d]/%s", pwm_module_index(td->module),
+            pwm_index(td->pwm), name);
+    qtest_add_data_func(full_name, td, fn);
+}
+#define add_test(name, td) pwm_add_test(#name, td, test_##name)
+
+int main(int argc, char **argv)
+{
+    TestData test_data_list[ARRAY_SIZE(pwm_module_list) * ARRAY_SIZE(pwm_list)];
+
+    g_test_init(&argc, &argv, NULL);
+
+    for (int i = 0; i < ARRAY_SIZE(pwm_module_list); ++i) {
+        for (int j = 0; j < ARRAY_SIZE(pwm_list); ++j) {
+            TestData *td = &test_data_list[i * ARRAY_SIZE(pwm_list) + j];
+
+            td->module = &pwm_module_list[i];
+            td->pwm = &pwm_list[j];
+
+            add_test(init, td);
+            add_test(oneshot, td);
+            add_test(toggle, td);
+        }
+    }
+
+    return g_test_run();
+}
diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/tests/qtest/meson.build
+++ b/tests/qtest/meson.build
@@ -XXX,XX +XXX,XX @@ qtests_sparc64 = \
 qtests_npcm7xx = \
   ['npcm7xx_adc-test',
    'npcm7xx_gpio-test',
+   'npcm7xx_pwm-test',
    'npcm7xx_rng-test',
    'npcm7xx_timer-test',
    'npcm7xx_watchdog_timer-test']
-- 
2.20.1

From: Hao Wu <wuhaotsh@google.com>

A device shouldn't access its parent object which is QOM internal.
Instead it should use type cast for this purporse. This patch fixes this
issue for all NPCM7XX Devices.

Signed-off-by: Hao Wu <wuhaotsh@google.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20210108190945.949196-7-wuhaotsh@google.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/npcm7xx_boards.c | 2 +-
 hw/mem/npcm7xx_mc.c     | 2 +-
 hw/misc/npcm7xx_clk.c   | 2 +-
 hw/misc/npcm7xx_gcr.c   | 2 +-
 hw/misc/npcm7xx_rng.c   | 2 +-
 hw/nvram/npcm7xx_otp.c  | 2 +-
 hw/ssi/npcm7xx_fiu.c    | 2 +-
 7 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/hw/arm/npcm7xx_boards.c b/hw/arm/npcm7xx_boards.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/npcm7xx_boards.c
+++ b/hw/arm/npcm7xx_boards.c
@@ -XXX,XX +XXX,XX @@ static NPCM7xxState *npcm7xx_create_soc(MachineState *machine,
                                         uint32_t hw_straps)
 {
     NPCM7xxMachineClass *nmc = NPCM7XX_MACHINE_GET_CLASS(machine);
-    MachineClass *mc = &nmc->parent;
+    MachineClass *mc = MACHINE_CLASS(nmc);
     Object *obj;
 
     if (strcmp(machine->cpu_type, mc->default_cpu_type) != 0) {
diff --git a/hw/mem/npcm7xx_mc.c b/hw/mem/npcm7xx_mc.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/mem/npcm7xx_mc.c
+++ b/hw/mem/npcm7xx_mc.c
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_mc_realize(DeviceState *dev, Error **errp)
 
     memory_region_init_io(&s->mmio, OBJECT(s), &npcm7xx_mc_ops, s, "regs",
                           NPCM7XX_MC_REGS_SIZE);
-    sysbus_init_mmio(&s->parent, &s->mmio);
+    sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->mmio);
 }
 
 static void npcm7xx_mc_class_init(ObjectClass *klass, void *data)
diff --git a/hw/misc/npcm7xx_clk.c b/hw/misc/npcm7xx_clk.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/misc/npcm7xx_clk.c
+++ b/hw/misc/npcm7xx_clk.c
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_clk_init(Object *obj)
 
     memory_region_init_io(&s->iomem, obj, &npcm7xx_clk_ops, s,
                           TYPE_NPCM7XX_CLK, 4 * KiB);
-    sysbus_init_mmio(&s->parent, &s->iomem);
+    sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem);
 }
 
 static int npcm7xx_clk_post_load(void *opaque, int version_id)
diff --git a/hw/misc/npcm7xx_gcr.c b/hw/misc/npcm7xx_gcr.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/misc/npcm7xx_gcr.c
+++ b/hw/misc/npcm7xx_gcr.c
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_gcr_init(Object *obj)
 
     memory_region_init_io(&s->iomem, obj, &npcm7xx_gcr_ops, s,
                           TYPE_NPCM7XX_GCR, 4 * KiB);
-    sysbus_init_mmio(&s->parent, &s->iomem);
+    sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem);
 }
 
 static const VMStateDescription vmstate_npcm7xx_gcr = {
diff --git a/hw/misc/npcm7xx_rng.c b/hw/misc/npcm7xx_rng.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/misc/npcm7xx_rng.c
+++ b/hw/misc/npcm7xx_rng.c
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_rng_init(Object *obj)
 
     memory_region_init_io(&s->iomem, obj, &npcm7xx_rng_ops, s, "regs",
                           NPCM7XX_RNG_REGS_SIZE);
-    sysbus_init_mmio(&s->parent, &s->iomem);
+    sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem);
 }
 
 static const VMStateDescription vmstate_npcm7xx_rng = {
diff --git a/hw/nvram/npcm7xx_otp.c b/hw/nvram/npcm7xx_otp.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/nvram/npcm7xx_otp.c
+++ b/hw/nvram/npcm7xx_otp.c
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_otp_realize(DeviceState *dev, Error **errp)
 {
     NPCM7xxOTPClass *oc = NPCM7XX_OTP_GET_CLASS(dev);
     NPCM7xxOTPState *s = NPCM7XX_OTP(dev);
-    SysBusDevice *sbd = &s->parent;
+    SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
 
     memset(s->array, 0, sizeof(s->array));
 
diff --git a/hw/ssi/npcm7xx_fiu.c b/hw/ssi/npcm7xx_fiu.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/ssi/npcm7xx_fiu.c
+++ b/hw/ssi/npcm7xx_fiu.c
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_fiu_hold_reset(Object *obj)
 static void npcm7xx_fiu_realize(DeviceState *dev, Error **errp)
 {
     NPCM7xxFIUState *s = NPCM7XX_FIU(dev);
-    SysBusDevice *sbd = &s->parent;
+    SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
     int i;
 
     if (s->cs_count <= 0) {
-- 
2.20.1

From: Roman Bolshakov <r.bolshakov@yadro.com>

ui/cocoa.m:1188:44: warning: 'openFile:' is deprecated: first deprecated in macOS 11.0 - Use -[NSWorkspace openURL:] instead.
      [-Wdeprecated-declarations]
        if ([[NSWorkspace sharedWorkspace] openFile: full_file_path] == YES) {
                                           ^
/Library/Developer/CommandLineTools/SDKs/MacOSX.sdk/System/Library/Frameworks/AppKit.framework/Headers/NSWorkspace.h:350:1: note:
      'openFile:' has been explicitly marked deprecated here
- (BOOL)openFile:(NSString *)fullPath API_DEPRECATED("Use -[NSWorkspace openURL:] instead.", macos(10.0, 11.0));
^

Signed-off-by: Roman Bolshakov <r.bolshakov@yadro.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20210102150718.47618-1-r.bolshakov@yadro.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 ui/cocoa.m | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/ui/cocoa.m b/ui/cocoa.m
index XXXXXXX..XXXXXXX 100644
--- a/ui/cocoa.m
+++ b/ui/cocoa.m
@@ -XXX,XX +XXX,XX @@ QemuCocoaView *cocoaView;
     /* Where to look for local files */
     NSString *path_array[] = {@"../share/doc/qemu/", @"../doc/qemu/", @"docs/"};
     NSString *full_file_path;
+    NSURL *full_file_url;
 
     /* iterate thru the possible paths until the file is found */
     int index;
@@ -XXX,XX +XXX,XX @@ QemuCocoaView *cocoaView;
         full_file_path = [full_file_path stringByDeletingLastPathComponent];
         full_file_path = [NSString stringWithFormat: @"%@/%@%@", full_file_path,
                           path_array[index], filename];
-        if ([[NSWorkspace sharedWorkspace] openFile: full_file_path] == YES) {
+        full_file_url = [NSURL fileURLWithPath: full_file_path
+                                   isDirectory: false];
+        if ([[NSWorkspace sharedWorkspace] openURL: full_file_url] == YES) {
             return;
         }
     }
-- 
2.20.1

Hi; here's a queue of arm patches (plus a few elf2dmp changes);
mostly these are minor cleanups and bugfixes.

thanks
-- PMM

The following changes since commit deaca3fd30d3a8829160f8d3705d65ad83176800:

Merge tag 'pull-vfio-20231018' of https://github.com/legoater/qemu into staging (2023-10-18 06:21:15 -0400)

are available in the Git repository at:

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20231019

for you to fetch changes up to 2a052b4ee01b3c413cef2ef49cb780cde17d4ba1:

contrib/elf2dmp: Use g_malloc(), g_new() and g_free() (2023-10-19 14:32:13 +0100)

----------------------------------------------------------------
target-arm queue:
 * hw/arm: Move raspberrypi-fw-defs.h to the include/hw/arm/ folder
 * hw/arm/exynos4210: Get arm_boot_info declaration from 'hw/arm/boot'
 * xlnx devices: remove deprecated device reset
 * xlnx-bbram: hw/nvram: Use dot in device type name
 * elf2dmp: fix coverity issues
 * elf2dmp: convert to g_malloc, g_new and g_free
 * target/arm: Fix CNTPCT_EL0 trapping from EL0 when HCR_EL2.E2H is 0
 * hw/arm: refactor virt PPI logic
 * arm/kvm: convert to kvm_set_one_reg, kvm_get_one_reg
 * target/arm: Permit T32 LDM with single register
 * smmuv3: Advertise SMMUv3.1-XNX
 * target/arm: Implement FEAT_HPMN0
 * Remove some unnecessary include lines
 * target/arm/arm-powerctl: Correctly init CPUs when powered on to lower EL
 * hw/timer/npcm7xx_timer: Prevent timer from counting down past zero

----------------------------------------------------------------
Chris Rauer (1):
      hw/timer/npcm7xx_timer: Prevent timer from counting down past zero

Cornelia Huck (2):
      arm/kvm: convert to kvm_set_one_reg
      arm/kvm: convert to kvm_get_one_reg

Leif Lindholm (3):
      {include/}hw/arm: refactor virt PPI logic
      include/hw/arm: move BSA definitions to bsa.h
      hw/arm/sbsa-ref: use bsa.h for PPI definitions

Michal Orzel (1):
      target/arm: Fix CNTPCT_EL0 trapping from EL0 when HCR_EL2.E2H is 0

Peter Maydell (8):
      target/arm: Permit T32 LDM with single register
      hw/arm/smmuv3: Update ID register bit field definitions
      hw/arm/smmuv3: Sort ID register setting into field order
      hw/arm/smmuv3: Advertise SMMUv3.1-XNX feature
      target/arm: Implement FEAT_HPMN0
      target/arm/kvm64.c: Remove unused include
      target/arm/common-semi-target.h: Remove unnecessary boot.h include
      target/arm/arm-powerctl: Correctly init CPUs when powered on to lower EL

Philippe Mathieu-Daudé (1):
      hw/arm/exynos4210: Get arm_boot_info declaration from 'hw/arm/boot.h'

Suraj Shirvankar (1):
      contrib/elf2dmp: Use g_malloc(), g_new() and g_free()

Thomas Huth (1):
      hw/arm: Move raspberrypi-fw-defs.h to the include/hw/arm/ folder

Tong Ho (4):
      xlnx-bbram: hw/nvram: Remove deprecated device reset
      xlnx-zynqmp-efuse: hw/nvram: Remove deprecated device reset
      xlnx-versal-efuse: hw/nvram: Remove deprecated device reset
      xlnx-bbram: hw/nvram: Use dot in device type name

Viktor Prutyanov (2):
      elf2dmp: limit print length for sign_rsds
      elf2dmp: check array bounds in pdb_get_file_size

MAINTAINERS                                    |   2 +-
 docs/system/arm/emulation.rst                  |   1 +
 hw/arm/smmuv3-internal.h                       |  38 ++++++++
 include/hw/arm/bsa.h                           |  35 +++++++
 include/hw/arm/exynos4210.h                    |   2 +-
 include/hw/{misc => arm}/raspberrypi-fw-defs.h |   0
 include/hw/arm/virt.h                          |  12 +--
 include/hw/nvram/xlnx-bbram.h                  |   2 +-
 target/arm/common-semi-target.h                |   4 +-
 target/arm/cpu-qom.h                           |   2 -
 target/arm/cpu.h                               |  22 +++++
 contrib/elf2dmp/addrspace.c                    |   7 +-
 contrib/elf2dmp/main.c                         |  11 +--
 contrib/elf2dmp/pdb.c                          |  32 ++++---
 contrib/elf2dmp/qemu_elf.c                     |   7 +-
 hw/arm/boot.c                                  |  95 +++++--------------
 hw/arm/sbsa-ref.c                              |  21 ++---
 hw/arm/smmuv3.c                                |   8 +-
 hw/arm/virt-acpi-build.c                       |  12 +--
 hw/arm/virt.c                                  |  24 +++--
 hw/misc/bcm2835_property.c                     |   2 +-
 hw/nvram/xlnx-bbram.c                          |   8 +-
 hw/nvram/xlnx-versal-efuse-ctrl.c              |   8 +-
 hw/nvram/xlnx-zynqmp-efuse.c                   |   8 +-
 hw/timer/npcm7xx_timer.c                       |   3 +
 target/arm/arm-powerctl.c                      |  53 +----------
 target/arm/cpu.c                               |  95 +++++++++++++++++++
 target/arm/helper.c                            |  19 +---
 target/arm/kvm.c                               |  28 ++----
 target/arm/kvm64.c                             | 124 +++++++------------------
 target/arm/tcg/cpu32.c                         |   4 +
 target/arm/tcg/cpu64.c                         |   1 +
 target/arm/tcg/translate.c                     |  37 +++++---
 33 files changed, 368 insertions(+), 359 deletions(-)
 create mode 100644 include/hw/arm/bsa.h
 rename include/hw/{misc => arm}/raspberrypi-fw-defs.h (100%)

From: Thomas Huth <thuth@redhat.com>

The file is obviously related to the raspberrypi machine, so
it should reside in hw/arm/ instead of hw/misc/. And while we're
at it, also adjust the wildcard in MAINTAINERS so that it covers
this file, too.

Signed-off-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Acked-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20231012073458.860187-1-thuth@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 MAINTAINERS                                    | 2 +-
 include/hw/{misc => arm}/raspberrypi-fw-defs.h | 0
 hw/misc/bcm2835_property.c                     | 2 +-
 3 files changed, 2 insertions(+), 2 deletions(-)
 rename include/hw/{misc => arm}/raspberrypi-fw-defs.h (100%)

diff --git a/MAINTAINERS b/MAINTAINERS
index XXXXXXX..XXXXXXX 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -XXX,XX +XXX,XX @@ S: Odd Fixes
 F: hw/arm/raspi.c
 F: hw/arm/raspi_platform.h
 F: hw/*/bcm283*
-F: include/hw/arm/raspi*
+F: include/hw/arm/rasp*
 F: include/hw/*/bcm283*
 F: docs/system/arm/raspi.rst
 
diff --git a/include/hw/misc/raspberrypi-fw-defs.h b/include/hw/arm/raspberrypi-fw-defs.h
similarity index 100%
rename from include/hw/misc/raspberrypi-fw-defs.h
rename to include/hw/arm/raspberrypi-fw-defs.h
diff --git a/hw/misc/bcm2835_property.c b/hw/misc/bcm2835_property.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/misc/bcm2835_property.c
+++ b/hw/misc/bcm2835_property.c
@@ -XXX,XX +XXX,XX @@
 #include "migration/vmstate.h"
 #include "hw/irq.h"
 #include "hw/misc/bcm2835_mbox_defs.h"
-#include "hw/misc/raspberrypi-fw-defs.h"
+#include "hw/arm/raspberrypi-fw-defs.h"
 #include "sysemu/dma.h"
 #include "qemu/log.h"
 #include "qemu/module.h"
-- 
2.34.1

From: Philippe Mathieu-Daudé <philmd@linaro.org>

struct arm_boot_info is declared in "hw/arm/boot.h".
By including the correct header we don't need to declare
it again in "target/arm/cpu-qom.h".

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20231013130214.95742-1-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/exynos4210.h | 2 +-
 target/arm/cpu-qom.h        | 2 --
 2 files changed, 1 insertion(+), 3 deletions(-)

diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/exynos4210.h
+++ b/include/hw/arm/exynos4210.h
@@ -XXX,XX +XXX,XX @@
 #include "hw/intc/exynos4210_gic.h"
 #include "hw/intc/exynos4210_combiner.h"
 #include "hw/core/split-irq.h"
-#include "target/arm/cpu-qom.h"
+#include "hw/arm/boot.h"
 #include "qom/object.h"
 
 #define EXYNOS4210_NCPUS                    2
diff --git a/target/arm/cpu-qom.h b/target/arm/cpu-qom.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu-qom.h
+++ b/target/arm/cpu-qom.h
@@ -XXX,XX +XXX,XX @@
 #include "hw/core/cpu.h"
 #include "qom/object.h"
 
-struct arm_boot_info;
-
 #define TYPE_ARM_CPU "arm-cpu"
 
 OBJECT_DECLARE_CPU_TYPE(ARMCPU, ARMCPUClass, ARM_CPU)
-- 
2.34.1

From: Tong Ho <tong.ho@amd.com>

This change implements the ResettableClass interface for the device.

Signed-off-by: Tong Ho <tong.ho@amd.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20231003052345.199725-1-tong.ho@amd.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/nvram/xlnx-bbram.c | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/hw/nvram/xlnx-bbram.c b/hw/nvram/xlnx-bbram.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/nvram/xlnx-bbram.c
+++ b/hw/nvram/xlnx-bbram.c
@@ -XXX,XX +XXX,XX @@
  * QEMU model of the Xilinx BBRAM Battery Backed RAM
  *
  * Copyright (c) 2014-2021 Xilinx Inc.
+ * Copyright (c) 2023 Advanced Micro Devices, Inc.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy
  * of this software and associated documentation files (the "Software"), to deal
@@ -XXX,XX +XXX,XX @@ static RegisterAccessInfo bbram_ctrl_regs_info[] = {
     }
 };
 
-static void bbram_ctrl_reset(DeviceState *dev)
+static void bbram_ctrl_reset_hold(Object *obj)
 {
-    XlnxBBRam *s = XLNX_BBRAM(dev);
+    XlnxBBRam *s = XLNX_BBRAM(obj);
     unsigned int i;
 
     for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) {
@@ -XXX,XX +XXX,XX @@ static Property bbram_ctrl_props[] = {
 static void bbram_ctrl_class_init(ObjectClass *klass, void *data)
 {
     DeviceClass *dc = DEVICE_CLASS(klass);
+    ResettableClass *rc = RESETTABLE_CLASS(klass);
 
-    dc->reset = bbram_ctrl_reset;
+    rc->phases.hold = bbram_ctrl_reset_hold;
     dc->realize = bbram_ctrl_realize;
     dc->vmsd = &vmstate_bbram_ctrl;
     device_class_set_props(dc, bbram_ctrl_props);
-- 
2.34.1

From: Tong Ho <tong.ho@amd.com>

This change implements the ResettableClass interface for the device.

Signed-off-by: Tong Ho <tong.ho@amd.com>
Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
Message-id: 20231004055713.324009-1-tong.ho@amd.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/nvram/xlnx-zynqmp-efuse.c | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/hw/nvram/xlnx-zynqmp-efuse.c b/hw/nvram/xlnx-zynqmp-efuse.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/nvram/xlnx-zynqmp-efuse.c
+++ b/hw/nvram/xlnx-zynqmp-efuse.c
@@ -XXX,XX +XXX,XX @@
  * QEMU model of the ZynqMP eFuse
  *
  * Copyright (c) 2015 Xilinx Inc.
+ * Copyright (c) 2023 Advanced Micro Devices, Inc.
  *
  * Written by Edgar E. Iglesias <edgari@xilinx.com>
  *
@@ -XXX,XX +XXX,XX @@ static void zynqmp_efuse_register_reset(RegisterInfo *reg)
     register_reset(reg);
 }
 
-static void zynqmp_efuse_reset(DeviceState *dev)
+static void zynqmp_efuse_reset_hold(Object *obj)
 {
-    XlnxZynqMPEFuse *s = XLNX_ZYNQMP_EFUSE(dev);
+    XlnxZynqMPEFuse *s = XLNX_ZYNQMP_EFUSE(obj);
     unsigned int i;
 
     for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) {
@@ -XXX,XX +XXX,XX @@ static Property zynqmp_efuse_props[] = {
 static void zynqmp_efuse_class_init(ObjectClass *klass, void *data)
 {
     DeviceClass *dc = DEVICE_CLASS(klass);
+    ResettableClass *rc = RESETTABLE_CLASS(klass);
 
-    dc->reset = zynqmp_efuse_reset;
+    rc->phases.hold = zynqmp_efuse_reset_hold;
     dc->realize = zynqmp_efuse_realize;
     dc->vmsd = &vmstate_efuse;
     device_class_set_props(dc, zynqmp_efuse_props);
-- 
2.34.1

From: Tong Ho <tong.ho@amd.com>

This change implements the ResettableClass interface for the device.

Signed-off-by: Tong Ho <tong.ho@amd.com>
Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
Message-id: 20231004055339.323833-1-tong.ho@amd.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/nvram/xlnx-versal-efuse-ctrl.c | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/hw/nvram/xlnx-versal-efuse-ctrl.c b/hw/nvram/xlnx-versal-efuse-ctrl.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/nvram/xlnx-versal-efuse-ctrl.c
+++ b/hw/nvram/xlnx-versal-efuse-ctrl.c
@@ -XXX,XX +XXX,XX @@
  * QEMU model of the Versal eFuse controller
  *
  * Copyright (c) 2020 Xilinx Inc.
+ * Copyright (c) 2023 Advanced Micro Devices, Inc.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy
  * of this software and associated documentation files (the "Software"), to deal
@@ -XXX,XX +XXX,XX @@ static void efuse_ctrl_register_reset(RegisterInfo *reg)
     register_reset(reg);
 }
 
-static void efuse_ctrl_reset(DeviceState *dev)
+static void efuse_ctrl_reset_hold(Object *obj)
 {
-    XlnxVersalEFuseCtrl *s = XLNX_VERSAL_EFUSE_CTRL(dev);
+    XlnxVersalEFuseCtrl *s = XLNX_VERSAL_EFUSE_CTRL(obj);
     unsigned int i;
 
     for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) {
@@ -XXX,XX +XXX,XX @@ static Property efuse_ctrl_props[] = {
 static void efuse_ctrl_class_init(ObjectClass *klass, void *data)
 {
     DeviceClass *dc = DEVICE_CLASS(klass);
+    ResettableClass *rc = RESETTABLE_CLASS(klass);
 
-    dc->reset = efuse_ctrl_reset;
+    rc->phases.hold = efuse_ctrl_reset_hold;
     dc->realize = efuse_ctrl_realize;
     dc->vmsd = &vmstate_efuse_ctrl;
     device_class_set_props(dc, efuse_ctrl_props);
-- 
2.34.1

From: Viktor Prutyanov <viktor@daynix.com>

Index in file_size array must be checked against num_files, because the
entries we are looking for may be absent in the PDB.

Fixes: Coverity CID 1521597
Signed-off-by: Viktor Prutyanov <viktor@daynix.com>
Reviewed-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20230930235317.11469-3-viktor@daynix.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 contrib/elf2dmp/pdb.c | 13 +++++++++----
 1 file changed, 9 insertions(+), 4 deletions(-)

diff --git a/contrib/elf2dmp/pdb.c b/contrib/elf2dmp/pdb.c
index XXXXXXX..XXXXXXX 100644
--- a/contrib/elf2dmp/pdb.c
+++ b/contrib/elf2dmp/pdb.c
@@ -XXX,XX +XXX,XX @@
 
 static uint32_t pdb_get_file_size(const struct pdb_reader *r, unsigned idx)
 {
+    if (idx >= r->ds.toc->num_files) {
+        return 0;
+    }
+
     return r->ds.toc->file_size[idx];
 }
 
@@ -XXX,XX +XXX,XX @@ static void *pdb_ds_read_file(struct pdb_reader* r, uint32_t file_number)
 
 static int pdb_init_segments(struct pdb_reader *r)
 {
-    char *segs;
     unsigned stream_idx = r->segments;
 
-    segs = pdb_ds_read_file(r, stream_idx);
-    if (!segs) {
+    r->segs = pdb_ds_read_file(r, stream_idx);
+    if (!r->segs) {
         return 1;
     }
 
-    r->segs = segs;
     r->segs_size = pdb_get_file_size(r, stream_idx);
+    if (!r->segs_size) {
+        return 1;
+    }
 
     return 0;
 }
-- 
2.34.1

From: Michal Orzel <michal.orzel@amd.com>

On an attempt to access CNTPCT_EL0 from EL0 using a guest running on top
of Xen, a trap from EL2 was observed which is something not reproducible
on HW (also, Xen does not trap accesses to physical counter).

This is because gt_counter_access() checks for an incorrect bit (1
instead of 0) of CNTHCTL_EL2 if HCR_EL2.E2H is 0 and access is made to
physical counter. Refer ARM ARM DDI 0487J.a, D19.12.2:
When HCR_EL2.E2H is 0:
 - EL1PCTEN, bit [0]: refers to physical counter
 - EL1PCEN, bit [1]: refers to physical timer registers

Drop entire block "if (hcr & HCR_E2H) {...} else {...}" from EL0 case
and fall through to EL1 case, given that after fixing checking for the
correct bit, the handling is the same.

Fixes: 5bc8437136fb ("target/arm: Update timer access for VHE")
Signed-off-by: Michal Orzel <michal.orzel@amd.com>
Tested-by: Oleksandr Tyshchenko <oleksandr_tyshchenko@epam.com>
Message-id: 20230928094404.20802-1-michal.orzel@amd.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper.c | 17 +----------------
 1 file changed, 1 insertion(+), 16 deletions(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static CPAccessResult gt_counter_access(CPUARMState *env, int timeridx,
         if (!extract32(env->cp15.c14_cntkctl, timeridx, 1)) {
             return CP_ACCESS_TRAP;
         }
-
-        /* If HCR_EL2.<E2H,TGE> == '10': check CNTHCTL_EL2.EL1PCTEN. */
-        if (hcr & HCR_E2H) {
-            if (timeridx == GTIMER_PHYS &&
-                !extract32(env->cp15.cnthctl_el2, 10, 1)) {
-                return CP_ACCESS_TRAP_EL2;
-            }
-        } else {
-            /* If HCR_EL2.<E2H> == 0: check CNTHCTL_EL2.EL1PCEN. */
-            if (has_el2 && timeridx == GTIMER_PHYS &&
-                !extract32(env->cp15.cnthctl_el2, 1, 1)) {
-                return CP_ACCESS_TRAP_EL2;
-            }
-        }
-        break;
-
+        /* fall through */
     case 1:
         /* Check CNTHCTL_EL2.EL1PCTEN, which changes location based on E2H. */
         if (has_el2 && timeridx == GTIMER_PHYS &&
-- 
2.34.1

From: Leif Lindholm <quic_llindhol@quicinc.com>

GIC Private Peripheral Interrupts (PPI) are defined as GIC INTID 16-31.
As in, PPI0 is INTID16 .. PPI15 is INTID31.
Arm's Base System Architecture specification (BSA) lists the mandated and
recommended private interrupt IDs by INTID, not by PPI index. But current
definitions in virt define them by PPI index, complicating cross
referencing.

Meanwhile, the PPI(x) macro counterintuitively adds 16 to the input value,
converting a PPI index to an INTID.

Resolve this by redefining the BSA-allocated PPIs by their INTIDs,
and replacing the PPI(x) macro with an INTID_TO_PPI(x) one where required.

Signed-off-by: Leif Lindholm <quic_llindhol@quicinc.com>
Message-id: 20230919090229.188092-2-quic_llindhol@quicinc.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/virt.h    | 14 +++++++-------
 hw/arm/virt-acpi-build.c | 12 ++++++------
 hw/arm/virt.c            | 24 ++++++++++++++----------
 3 files changed, 27 insertions(+), 23 deletions(-)

diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/virt.h
+++ b/include/hw/arm/virt.h
@@ -XXX,XX +XXX,XX @@
 #define NUM_VIRTIO_TRANSPORTS 32
 #define NUM_SMMU_IRQS          4
 
-#define ARCH_GIC_MAINT_IRQ  9
+#define ARCH_GIC_MAINT_IRQ  25
 
-#define ARCH_TIMER_VIRT_IRQ   11
-#define ARCH_TIMER_S_EL1_IRQ  13
-#define ARCH_TIMER_NS_EL1_IRQ 14
-#define ARCH_TIMER_NS_EL2_IRQ 10
+#define ARCH_TIMER_VIRT_IRQ   27
+#define ARCH_TIMER_S_EL1_IRQ  29
+#define ARCH_TIMER_NS_EL1_IRQ 30
+#define ARCH_TIMER_NS_EL2_IRQ 26
 
-#define VIRTUAL_PMU_IRQ 7
+#define VIRTUAL_PMU_IRQ 23
 
-#define PPI(irq) ((irq) + 16)
+#define INTID_TO_PPI(irq) ((irq) - 16)
 
 /* See Linux kernel arch/arm64/include/asm/pvclock-abi.h */
 #define PVTIME_SIZE_PER_CPU 64
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/virt-acpi-build.c
+++ b/hw/arm/virt-acpi-build.c
@@ -XXX,XX +XXX,XX @@ build_gtdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
      * The interrupt values are the same with the device tree when adding 16
      */
     /* Secure EL1 timer GSIV */
-    build_append_int_noprefix(table_data, ARCH_TIMER_S_EL1_IRQ + 16, 4);
+    build_append_int_noprefix(table_data, ARCH_TIMER_S_EL1_IRQ, 4);
     /* Secure EL1 timer Flags */
     build_append_int_noprefix(table_data, irqflags, 4);
     /* Non-Secure EL1 timer GSIV */
-    build_append_int_noprefix(table_data, ARCH_TIMER_NS_EL1_IRQ + 16, 4);
+    build_append_int_noprefix(table_data, ARCH_TIMER_NS_EL1_IRQ, 4);
     /* Non-Secure EL1 timer Flags */
     build_append_int_noprefix(table_data, irqflags |
                               1UL << 2, /* Always-on Capability */
                               4);
     /* Virtual timer GSIV */
-    build_append_int_noprefix(table_data, ARCH_TIMER_VIRT_IRQ + 16, 4);
+    build_append_int_noprefix(table_data, ARCH_TIMER_VIRT_IRQ, 4);
     /* Virtual Timer Flags */
     build_append_int_noprefix(table_data, irqflags, 4);
     /* Non-Secure EL2 timer GSIV */
-    build_append_int_noprefix(table_data, ARCH_TIMER_NS_EL2_IRQ + 16, 4);
+    build_append_int_noprefix(table_data, ARCH_TIMER_NS_EL2_IRQ, 4);
     /* Non-Secure EL2 timer Flags */
     build_append_int_noprefix(table_data, irqflags, 4);
     /* CntReadBase Physical address */
@@ -XXX,XX +XXX,XX @@ build_madt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
     for (i = 0; i < MACHINE(vms)->smp.cpus; i++) {
         ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(i));
         uint64_t physical_base_address = 0, gich = 0, gicv = 0;
-        uint32_t vgic_interrupt = vms->virt ? PPI(ARCH_GIC_MAINT_IRQ) : 0;
+        uint32_t vgic_interrupt = vms->virt ? ARCH_GIC_MAINT_IRQ : 0;
         uint32_t pmu_interrupt = arm_feature(&armcpu->env, ARM_FEATURE_PMU) ?
-                                             PPI(VIRTUAL_PMU_IRQ) : 0;
+                                             VIRTUAL_PMU_IRQ : 0;
 
         if (vms->gic_version == VIRT_GIC_VERSION_2) {
             physical_base_address = memmap[VIRT_GIC_CPU].base;
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -XXX,XX +XXX,XX @@ static void fdt_add_timer_nodes(const VirtMachineState *vms)
     }
     qemu_fdt_setprop(ms->fdt, "/timer", "always-on", NULL, 0);
     qemu_fdt_setprop_cells(ms->fdt, "/timer", "interrupts",
-                       GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_S_EL1_IRQ, irqflags,
-                       GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL1_IRQ, irqflags,
-                       GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_VIRT_IRQ, irqflags,
-                       GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL2_IRQ, irqflags);
+                           GIC_FDT_IRQ_TYPE_PPI,
+                           INTID_TO_PPI(ARCH_TIMER_S_EL1_IRQ), irqflags,
+                           GIC_FDT_IRQ_TYPE_PPI,
+                           INTID_TO_PPI(ARCH_TIMER_NS_EL1_IRQ), irqflags,
+                           GIC_FDT_IRQ_TYPE_PPI,
+                           INTID_TO_PPI(ARCH_TIMER_VIRT_IRQ), irqflags,
+                           GIC_FDT_IRQ_TYPE_PPI,
+                           INTID_TO_PPI(ARCH_TIMER_NS_EL2_IRQ), irqflags);
 }
 
 static void fdt_add_cpu_nodes(const VirtMachineState *vms)
@@ -XXX,XX +XXX,XX @@ static void create_gic(VirtMachineState *vms, MemoryRegion *mem)
      */
     for (i = 0; i < smp_cpus; i++) {
         DeviceState *cpudev = DEVICE(qemu_get_cpu(i));
-        int ppibase = NUM_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS;
+        int intidbase = NUM_IRQS + i * GIC_INTERNAL;
         /* Mapping from the output timer irq lines from the CPU to the
          * GIC PPI inputs we use for the virt board.
          */
@@ -XXX,XX +XXX,XX @@ static void create_gic(VirtMachineState *vms, MemoryRegion *mem)
         for (unsigned irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) {
             qdev_connect_gpio_out(cpudev, irq,
                                   qdev_get_gpio_in(vms->gic,
-                                                   ppibase + timer_irq[irq]));
+                                                   intidbase + timer_irq[irq]));
         }
 
         if (vms->gic_version != VIRT_GIC_VERSION_2) {
             qemu_irq irq = qdev_get_gpio_in(vms->gic,
-                                            ppibase + ARCH_GIC_MAINT_IRQ);
+                                            intidbase + ARCH_GIC_MAINT_IRQ);
             qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt",
                                         0, irq);
         } else if (vms->virt) {
             qemu_irq irq = qdev_get_gpio_in(vms->gic,
-                                            ppibase + ARCH_GIC_MAINT_IRQ);
+                                            intidbase + ARCH_GIC_MAINT_IRQ);
             sysbus_connect_irq(gicbusdev, i + 4 * smp_cpus, irq);
         }
 
         qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0,
-                                    qdev_get_gpio_in(vms->gic, ppibase
+                                    qdev_get_gpio_in(vms->gic, intidbase
                                                      + VIRTUAL_PMU_IRQ));
 
         sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));
@@ -XXX,XX +XXX,XX @@ static void virt_cpu_post_init(VirtMachineState *vms, MemoryRegion *sysmem)
             if (pmu) {
                 assert(arm_feature(&ARM_CPU(cpu)->env, ARM_FEATURE_PMU));
                 if (kvm_irqchip_in_kernel()) {
-                    kvm_arm_pmu_set_irq(cpu, PPI(VIRTUAL_PMU_IRQ));
+                    kvm_arm_pmu_set_irq(cpu, VIRTUAL_PMU_IRQ);
                 }
                 kvm_arm_pmu_init(cpu);
             }
-- 
2.34.1

From: Leif Lindholm <quic_llindhol@quicinc.com>

virt.h defines a number of IRQs that are ultimately described by Arm's
Base System Architecture specification. Move these to a dedicated header
so that they can be reused by other platforms that do the same.
Include that header from virt.h to minimise churn.

While we're moving the definitions, sort them into numerical order,
and add the ARCH_TIMER_NS_EL2_VIRT_IRQ definition used by sbsa-ref
and which will eventually be needed by virt also.

Signed-off-by: Leif Lindholm <quic_llindhol@quicinc.com>
Message-id: 20230919090229.188092-3-quic_llindhol@quicinc.com
[PMM: Remove unused PPI_TO_INTID macro; sort numerically;
 add ARCH_TIMER_NS_EL2_VIRT_IRQ]
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/bsa.h  | 35 +++++++++++++++++++++++++++++++++++
 include/hw/arm/virt.h | 12 +-----------
 2 files changed, 36 insertions(+), 11 deletions(-)
 create mode 100644 include/hw/arm/bsa.h

diff --git a/include/hw/arm/bsa.h b/include/hw/arm/bsa.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/include/hw/arm/bsa.h
@@ -XXX,XX +XXX,XX @@
+/*
+ * Common definitions for Arm Base System Architecture (BSA) platforms.
+ *
+ * Copyright (c) 2015 Linaro Limited
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ */
+
+#ifndef QEMU_ARM_BSA_H
+#define QEMU_ARM_BSA_H
+
+/* These are architectural INTID values */
+#define VIRTUAL_PMU_IRQ            23
+#define ARCH_GIC_MAINT_IRQ         25
+#define ARCH_TIMER_NS_EL2_IRQ      26
+#define ARCH_TIMER_VIRT_IRQ        27
+#define ARCH_TIMER_NS_EL2_VIRT_IRQ 28
+#define ARCH_TIMER_S_EL1_IRQ       29
+#define ARCH_TIMER_NS_EL1_IRQ      30
+
+#define INTID_TO_PPI(irq) ((irq) - 16)
+
+#endif /* QEMU_ARM_BSA_H */
diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/virt.h
+++ b/include/hw/arm/virt.h
@@ -XXX,XX +XXX,XX @@
 #include "qemu/notify.h"
 #include "hw/boards.h"
 #include "hw/arm/boot.h"
+#include "hw/arm/bsa.h"
 #include "hw/block/flash.h"
 #include "sysemu/kvm.h"
 #include "hw/intc/arm_gicv3_common.h"
@@ -XXX,XX +XXX,XX @@
 #define NUM_VIRTIO_TRANSPORTS 32
 #define NUM_SMMU_IRQS          4
 
-#define ARCH_GIC_MAINT_IRQ  25
-
-#define ARCH_TIMER_VIRT_IRQ   27
-#define ARCH_TIMER_S_EL1_IRQ  29
-#define ARCH_TIMER_NS_EL1_IRQ 30
-#define ARCH_TIMER_NS_EL2_IRQ 26
-
-#define VIRTUAL_PMU_IRQ 23
-
-#define INTID_TO_PPI(irq) ((irq) - 16)
-
 /* See Linux kernel arch/arm64/include/asm/pvclock-abi.h */
 #define PVTIME_SIZE_PER_CPU 64
 
-- 
2.34.1

From: Leif Lindholm <quic_llindhol@quicinc.com>

Use the private peripheral interrupt definitions from bsa.h instead of
defining them locally. Refactor to use the INTIDs defined there instead
of the PPI# used previously.

Signed-off-by: Leif Lindholm <quic_llindhol@quicinc.com>
Message-id: 20230919090229.188092-4-quic_llindhol@quicinc.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/sbsa-ref.c | 21 +++++++++------------
 1 file changed, 9 insertions(+), 12 deletions(-)

diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/sbsa-ref.c
+++ b/hw/arm/sbsa-ref.c
@@ -XXX,XX +XXX,XX @@
  * ARM SBSA Reference Platform emulation
  *
  * Copyright (c) 2018 Linaro Limited
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
  * Written by Hongbo Zhang <hongbo.zhang@linaro.org>
  *
  * This program is free software; you can redistribute it and/or modify it
@@ -XXX,XX +XXX,XX @@
 #include "exec/hwaddr.h"
 #include "kvm_arm.h"
 #include "hw/arm/boot.h"
+#include "hw/arm/bsa.h"
 #include "hw/arm/fdt.h"
 #include "hw/arm/smmuv3.h"
 #include "hw/block/flash.h"
@@ -XXX,XX +XXX,XX @@
 #define NUM_SMMU_IRQS   4
 #define NUM_SATA_PORTS  6
 
-#define VIRTUAL_PMU_IRQ        7
-#define ARCH_GIC_MAINT_IRQ     9
-#define ARCH_TIMER_VIRT_IRQ    11
-#define ARCH_TIMER_S_EL1_IRQ   13
-#define ARCH_TIMER_NS_EL1_IRQ  14
-#define ARCH_TIMER_NS_EL2_IRQ  10
-#define ARCH_TIMER_NS_EL2_VIRT_IRQ  12
-
 enum {
     SBSA_FLASH,
     SBSA_MEM,
@@ -XXX,XX +XXX,XX @@ static void create_gic(SBSAMachineState *sms, MemoryRegion *mem)
      */
     for (i = 0; i < smp_cpus; i++) {
         DeviceState *cpudev = DEVICE(qemu_get_cpu(i));
-        int ppibase = NUM_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS;
+        int intidbase = NUM_IRQS + i * GIC_INTERNAL;
         int irq;
         /*
          * Mapping from the output timer irq lines from the CPU to the
@@ -XXX,XX +XXX,XX @@ static void create_gic(SBSAMachineState *sms, MemoryRegion *mem)
         for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) {
             qdev_connect_gpio_out(cpudev, irq,
                                   qdev_get_gpio_in(sms->gic,
-                                                   ppibase + timer_irq[irq]));
+                                                   intidbase + timer_irq[irq]));
         }
 
         qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt", 0,
-                                    qdev_get_gpio_in(sms->gic, ppibase
+                                    qdev_get_gpio_in(sms->gic,
+                                                     intidbase
                                                      + ARCH_GIC_MAINT_IRQ));
+
         qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0,
-                                    qdev_get_gpio_in(sms->gic, ppibase
+                                    qdev_get_gpio_in(sms->gic,
+                                                     intidbase
                                                      + VIRTUAL_PMU_IRQ));
 
         sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));
-- 
2.34.1

From: Cornelia Huck <cohuck@redhat.com>

We can neaten the code by switching to the kvm_set_one_reg function.

Reviewed-by: Gavin Shan <gshan@redhat.com>
Signed-off-by: Cornelia Huck <cohuck@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20231010142453.224369-2-cohuck@redhat.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/kvm.c   | 13 +++------
 target/arm/kvm64.c | 66 +++++++++++++---------------------------------
 2 files changed, 21 insertions(+), 58 deletions(-)

diff --git a/target/arm/kvm.c b/target/arm/kvm.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/kvm.c
+++ b/target/arm/kvm.c
@@ -XXX,XX +XXX,XX @@ bool write_list_to_kvmstate(ARMCPU *cpu, int level)
     bool ok = true;
 
     for (i = 0; i < cpu->cpreg_array_len; i++) {
-        struct kvm_one_reg r;
         uint64_t regidx = cpu->cpreg_indexes[i];
         uint32_t v32;
         int ret;
@@ -XXX,XX +XXX,XX @@ bool write_list_to_kvmstate(ARMCPU *cpu, int level)
             continue;
         }
 
-        r.id = regidx;
         switch (regidx & KVM_REG_SIZE_MASK) {
         case KVM_REG_SIZE_U32:
             v32 = cpu->cpreg_values[i];
-            r.addr = (uintptr_t)&v32;
+            ret = kvm_set_one_reg(cs, regidx, &v32);
             break;
         case KVM_REG_SIZE_U64:
-            r.addr = (uintptr_t)(cpu->cpreg_values + i);
+            ret = kvm_set_one_reg(cs, regidx, cpu->cpreg_values + i);
             break;
         default:
             g_assert_not_reached();
         }
-        ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &r);
         if (ret) {
             /* We might fail for "unknown register" and also for
              * "you tried to set a register which is constant with
@@ -XXX,XX +XXX,XX @@ void kvm_arm_get_virtual_time(CPUState *cs)
 void kvm_arm_put_virtual_time(CPUState *cs)
 {
     ARMCPU *cpu = ARM_CPU(cs);
-    struct kvm_one_reg reg = {
-        .id = KVM_REG_ARM_TIMER_CNT,
-        .addr = (uintptr_t)&cpu->kvm_vtime,
-    };
     int ret;
 
     if (!cpu->kvm_vtime_dirty) {
         return;
     }
 
-    ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
+    ret = kvm_set_one_reg(cs, KVM_REG_ARM_TIMER_CNT, &cpu->kvm_vtime);
     if (ret) {
         error_report("Failed to set KVM_REG_ARM_TIMER_CNT");
         abort();
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/kvm64.c
+++ b/target/arm/kvm64.c
@@ -XXX,XX +XXX,XX @@ static int kvm_arm_sve_set_vls(CPUState *cs)
 {
     ARMCPU *cpu = ARM_CPU(cs);
     uint64_t vls[KVM_ARM64_SVE_VLS_WORDS] = { cpu->sve_vq.map };
-    struct kvm_one_reg reg = {
-        .id = KVM_REG_ARM64_SVE_VLS,
-        .addr = (uint64_t)&vls[0],
-    };
 
     assert(cpu->sve_max_vq <= KVM_ARM64_SVE_VQ_MAX);
 
-    return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
+    return kvm_set_one_reg(cs, KVM_REG_ARM64_SVE_VLS, &vls[0]);
 }
 
 #define ARM_CPU_ID_MPIDR       3, 0, 0, 0, 5
@@ -XXX,XX +XXX,XX @@ static void kvm_inject_arm_sea(CPUState *c)
 static int kvm_arch_put_fpsimd(CPUState *cs)
 {
     CPUARMState *env = &ARM_CPU(cs)->env;
-    struct kvm_one_reg reg;
     int i, ret;
 
     for (i = 0; i < 32; i++) {
         uint64_t *q = aa64_vfp_qreg(env, i);
 #if HOST_BIG_ENDIAN
         uint64_t fp_val[2] = { q[1], q[0] };
-        reg.addr = (uintptr_t)fp_val;
+        ret = kvm_set_one_reg(cs, AARCH64_SIMD_CORE_REG(fp_regs.vregs[i]),
+                                                        fp_val);
 #else
-        reg.addr = (uintptr_t)q;
+        ret = kvm_set_one_reg(cs, AARCH64_SIMD_CORE_REG(fp_regs.vregs[i]), q);
 #endif
-        reg.id = AARCH64_SIMD_CORE_REG(fp_regs.vregs[i]);
-        ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
         if (ret) {
             return ret;
         }
@@ -XXX,XX +XXX,XX @@ static int kvm_arch_put_sve(CPUState *cs)
     CPUARMState *env = &cpu->env;
     uint64_t tmp[ARM_MAX_VQ * 2];
     uint64_t *r;
-    struct kvm_one_reg reg;
     int n, ret;
 
     for (n = 0; n < KVM_ARM64_SVE_NUM_ZREGS; ++n) {
         r = sve_bswap64(tmp, &env->vfp.zregs[n].d[0], cpu->sve_max_vq * 2);
-        reg.addr = (uintptr_t)r;
-        reg.id = KVM_REG_ARM64_SVE_ZREG(n, 0);
-        ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
+        ret = kvm_set_one_reg(cs, KVM_REG_ARM64_SVE_ZREG(n, 0), r);
         if (ret) {
             return ret;
         }
@@ -XXX,XX +XXX,XX @@ static int kvm_arch_put_sve(CPUState *cs)
     for (n = 0; n < KVM_ARM64_SVE_NUM_PREGS; ++n) {
         r = sve_bswap64(tmp, r = &env->vfp.pregs[n].p[0],
                         DIV_ROUND_UP(cpu->sve_max_vq * 2, 8));
-        reg.addr = (uintptr_t)r;
-        reg.id = KVM_REG_ARM64_SVE_PREG(n, 0);
-        ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
+        ret = kvm_set_one_reg(cs, KVM_REG_ARM64_SVE_PREG(n, 0), r);
         if (ret) {
             return ret;
         }
@@ -XXX,XX +XXX,XX @@ static int kvm_arch_put_sve(CPUState *cs)
 
     r = sve_bswap64(tmp, &env->vfp.pregs[FFR_PRED_NUM].p[0],
                     DIV_ROUND_UP(cpu->sve_max_vq * 2, 8));
-    reg.addr = (uintptr_t)r;
-    reg.id = KVM_REG_ARM64_SVE_FFR(0);
-    ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
+    ret = kvm_set_one_reg(cs, KVM_REG_ARM64_SVE_FFR(0), r);
     if (ret) {
         return ret;
     }
@@ -XXX,XX +XXX,XX @@ static int kvm_arch_put_sve(CPUState *cs)
 
 int kvm_arch_put_registers(CPUState *cs, int level)
 {
-    struct kvm_one_reg reg;
     uint64_t val;
     uint32_t fpr;
     int i, ret;
@@ -XXX,XX +XXX,XX @@ int kvm_arch_put_registers(CPUState *cs, int level)
     }
 
     for (i = 0; i < 31; i++) {
-        reg.id = AARCH64_CORE_REG(regs.regs[i]);
-        reg.addr = (uintptr_t) &env->xregs[i];
-        ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
+        ret = kvm_set_one_reg(cs, AARCH64_CORE_REG(regs.regs[i]),
+                              &env->xregs[i]);
         if (ret) {
             return ret;
         }
@@ -XXX,XX +XXX,XX @@ int kvm_arch_put_registers(CPUState *cs, int level)
      */
     aarch64_save_sp(env, 1);
 
-    reg.id = AARCH64_CORE_REG(regs.sp);
-    reg.addr = (uintptr_t) &env->sp_el[0];
-    ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
+    ret = kvm_set_one_reg(cs, AARCH64_CORE_REG(regs.sp), &env->sp_el[0]);
     if (ret) {
         return ret;
     }
 
-    reg.id = AARCH64_CORE_REG(sp_el1);
-    reg.addr = (uintptr_t) &env->sp_el[1];
-    ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
+    ret = kvm_set_one_reg(cs, AARCH64_CORE_REG(sp_el1), &env->sp_el[1]);
     if (ret) {
         return ret;
     }
@@ -XXX,XX +XXX,XX @@ int kvm_arch_put_registers(CPUState *cs, int level)
     } else {
         val = cpsr_read(env);
     }
-    reg.id = AARCH64_CORE_REG(regs.pstate);
-    reg.addr = (uintptr_t) &val;
-    ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
+    ret = kvm_set_one_reg(cs, AARCH64_CORE_REG(regs.pstate), &val);
     if (ret) {
         return ret;
     }
 
-    reg.id = AARCH64_CORE_REG(regs.pc);
-    reg.addr = (uintptr_t) &env->pc;
-    ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
+    ret = kvm_set_one_reg(cs, AARCH64_CORE_REG(regs.pc), &env->pc);
     if (ret) {
         return ret;
     }
 
-    reg.id = AARCH64_CORE_REG(elr_el1);
-    reg.addr = (uintptr_t) &env->elr_el[1];
-    ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
+    ret = kvm_set_one_reg(cs, AARCH64_CORE_REG(elr_el1), &env->elr_el[1]);
     if (ret) {
         return ret;
     }
@@ -XXX,XX +XXX,XX @@ int kvm_arch_put_registers(CPUState *cs, int level)
 
     /* KVM 0-4 map to QEMU banks 1-5 */
     for (i = 0; i < KVM_NR_SPSR; i++) {
-        reg.id = AARCH64_CORE_REG(spsr[i]);
-        reg.addr = (uintptr_t) &env->banked_spsr[i + 1];
-        ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
+        ret = kvm_set_one_reg(cs, AARCH64_CORE_REG(spsr[i]),
+                              &env->banked_spsr[i + 1]);
         if (ret) {
             return ret;
         }
@@ -XXX,XX +XXX,XX @@ int kvm_arch_put_registers(CPUState *cs, int level)
         return ret;
     }
 
-    reg.addr = (uintptr_t)(&fpr);
     fpr = vfp_get_fpsr(env);
-    reg.id = AARCH64_SIMD_CTRL_REG(fp_regs.fpsr);
-    ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
+    ret = kvm_set_one_reg(cs, AARCH64_SIMD_CTRL_REG(fp_regs.fpsr), &fpr);
     if (ret) {
         return ret;
     }
 
-    reg.addr = (uintptr_t)(&fpr);
     fpr = vfp_get_fpcr(env);
-    reg.id = AARCH64_SIMD_CTRL_REG(fp_regs.fpcr);
-    ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
+    ret = kvm_set_one_reg(cs, AARCH64_SIMD_CTRL_REG(fp_regs.fpcr), &fpr);
     if (ret) {
         return ret;
     }
-- 
2.34.1

From: Cornelia Huck <cohuck@redhat.com>

We can neaten the code by switching the callers that work on a
CPUstate to the kvm_get_one_reg function.

Reviewed-by: Gavin Shan <gshan@redhat.com>
Signed-off-by: Cornelia Huck <cohuck@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20231010142453.224369-3-cohuck@redhat.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/kvm.c   | 15 +++---------
 target/arm/kvm64.c | 57 ++++++++++++----------------------------------
 2 files changed, 18 insertions(+), 54 deletions(-)

diff --git a/target/arm/kvm.c b/target/arm/kvm.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/kvm.c
+++ b/target/arm/kvm.c
@@ -XXX,XX +XXX,XX @@ bool write_kvmstate_to_list(ARMCPU *cpu)
     bool ok = true;
 
     for (i = 0; i < cpu->cpreg_array_len; i++) {
-        struct kvm_one_reg r;
         uint64_t regidx = cpu->cpreg_indexes[i];
         uint32_t v32;
         int ret;
 
-        r.id = regidx;
-
         switch (regidx & KVM_REG_SIZE_MASK) {
         case KVM_REG_SIZE_U32:
-            r.addr = (uintptr_t)&v32;
-            ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r);
+            ret = kvm_get_one_reg(cs, regidx, &v32);
             if (!ret) {
                 cpu->cpreg_values[i] = v32;
             }
             break;
         case KVM_REG_SIZE_U64:
-            r.addr = (uintptr_t)(cpu->cpreg_values + i);
-            ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r);
+            ret = kvm_get_one_reg(cs, regidx, cpu->cpreg_values + i);
             break;
         default:
             g_assert_not_reached();
@@ -XXX,XX +XXX,XX @@ int kvm_arm_sync_mpstate_to_qemu(ARMCPU *cpu)
 void kvm_arm_get_virtual_time(CPUState *cs)
 {
     ARMCPU *cpu = ARM_CPU(cs);
-    struct kvm_one_reg reg = {
-        .id = KVM_REG_ARM_TIMER_CNT,
-        .addr = (uintptr_t)&cpu->kvm_vtime,
-    };
     int ret;
 
     if (cpu->kvm_vtime_dirty) {
         return;
     }
 
-    ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
+    ret = kvm_get_one_reg(cs, KVM_REG_ARM_TIMER_CNT, &cpu->kvm_vtime);
     if (ret) {
         error_report("Failed to get KVM_REG_ARM_TIMER_CNT");
         abort();
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/kvm64.c
+++ b/target/arm/kvm64.c
@@ -XXX,XX +XXX,XX @@ int kvm_arch_put_registers(CPUState *cs, int level)
 static int kvm_arch_get_fpsimd(CPUState *cs)
 {
     CPUARMState *env = &ARM_CPU(cs)->env;
-    struct kvm_one_reg reg;
     int i, ret;
 
     for (i = 0; i < 32; i++) {
         uint64_t *q = aa64_vfp_qreg(env, i);
-        reg.id = AARCH64_SIMD_CORE_REG(fp_regs.vregs[i]);
-        reg.addr = (uintptr_t)q;
-        ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
+        ret = kvm_get_one_reg(cs, AARCH64_SIMD_CORE_REG(fp_regs.vregs[i]), q);
         if (ret) {
             return ret;
         } else {
@@ -XXX,XX +XXX,XX @@ static int kvm_arch_get_sve(CPUState *cs)
 {
     ARMCPU *cpu = ARM_CPU(cs);
     CPUARMState *env = &cpu->env;
-    struct kvm_one_reg reg;
     uint64_t *r;
     int n, ret;
 
     for (n = 0; n < KVM_ARM64_SVE_NUM_ZREGS; ++n) {
         r = &env->vfp.zregs[n].d[0];
-        reg.addr = (uintptr_t)r;
-        reg.id = KVM_REG_ARM64_SVE_ZREG(n, 0);
-        ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
+        ret = kvm_get_one_reg(cs, KVM_REG_ARM64_SVE_ZREG(n, 0), r);
         if (ret) {
             return ret;
         }
@@ -XXX,XX +XXX,XX @@ static int kvm_arch_get_sve(CPUState *cs)
 
     for (n = 0; n < KVM_ARM64_SVE_NUM_PREGS; ++n) {
         r = &env->vfp.pregs[n].p[0];
-        reg.addr = (uintptr_t)r;
-        reg.id = KVM_REG_ARM64_SVE_PREG(n, 0);
-        ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
+        ret = kvm_get_one_reg(cs, KVM_REG_ARM64_SVE_PREG(n, 0), r);
         if (ret) {
             return ret;
         }
@@ -XXX,XX +XXX,XX @@ static int kvm_arch_get_sve(CPUState *cs)
     }
 
     r = &env->vfp.pregs[FFR_PRED_NUM].p[0];
-    reg.addr = (uintptr_t)r;
-    reg.id = KVM_REG_ARM64_SVE_FFR(0);
-    ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
+    ret = kvm_get_one_reg(cs, KVM_REG_ARM64_SVE_FFR(0), r);
     if (ret) {
         return ret;
     }
@@ -XXX,XX +XXX,XX @@ static int kvm_arch_get_sve(CPUState *cs)
 
 int kvm_arch_get_registers(CPUState *cs)
 {
-    struct kvm_one_reg reg;
     uint64_t val;
     unsigned int el;
     uint32_t fpr;
@@ -XXX,XX +XXX,XX @@ int kvm_arch_get_registers(CPUState *cs)
     CPUARMState *env = &cpu->env;
 
     for (i = 0; i < 31; i++) {
-        reg.id = AARCH64_CORE_REG(regs.regs[i]);
-        reg.addr = (uintptr_t) &env->xregs[i];
-        ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
+        ret = kvm_get_one_reg(cs, AARCH64_CORE_REG(regs.regs[i]),
+                              &env->xregs[i]);
         if (ret) {
             return ret;
         }
     }
 
-    reg.id = AARCH64_CORE_REG(regs.sp);
-    reg.addr = (uintptr_t) &env->sp_el[0];
-    ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
+    ret = kvm_get_one_reg(cs, AARCH64_CORE_REG(regs.sp), &env->sp_el[0]);
     if (ret) {
         return ret;
     }
 
-    reg.id = AARCH64_CORE_REG(sp_el1);
-    reg.addr = (uintptr_t) &env->sp_el[1];
-    ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
+    ret = kvm_get_one_reg(cs, AARCH64_CORE_REG(sp_el1), &env->sp_el[1]);
     if (ret) {
         return ret;
     }
 
-    reg.id = AARCH64_CORE_REG(regs.pstate);
-    reg.addr = (uintptr_t) &val;
-    ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
+    ret = kvm_get_one_reg(cs, AARCH64_CORE_REG(regs.pstate), &val);
     if (ret) {
         return ret;
     }
@@ -XXX,XX +XXX,XX @@ int kvm_arch_get_registers(CPUState *cs)
      */
     aarch64_restore_sp(env, 1);
 
-    reg.id = AARCH64_CORE_REG(regs.pc);
-    reg.addr = (uintptr_t) &env->pc;
-    ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
+    ret = kvm_get_one_reg(cs, AARCH64_CORE_REG(regs.pc), &env->pc);
     if (ret) {
         return ret;
     }
@@ -XXX,XX +XXX,XX @@ int kvm_arch_get_registers(CPUState *cs)
         aarch64_sync_64_to_32(env);
     }
 
-    reg.id = AARCH64_CORE_REG(elr_el1);
-    reg.addr = (uintptr_t) &env->elr_el[1];
-    ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
+    ret = kvm_get_one_reg(cs, AARCH64_CORE_REG(elr_el1), &env->elr_el[1]);
     if (ret) {
         return ret;
     }
@@ -XXX,XX +XXX,XX @@ int kvm_arch_get_registers(CPUState *cs)
      * KVM SPSRs 0-4 map to QEMU banks 1-5
      */
     for (i = 0; i < KVM_NR_SPSR; i++) {
-        reg.id = AARCH64_CORE_REG(spsr[i]);
-        reg.addr = (uintptr_t) &env->banked_spsr[i + 1];
-        ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
+        ret = kvm_get_one_reg(cs, AARCH64_CORE_REG(spsr[i]),
+                              &env->banked_spsr[i + 1]);
         if (ret) {
             return ret;
         }
@@ -XXX,XX +XXX,XX @@ int kvm_arch_get_registers(CPUState *cs)
         return ret;
     }
 
-    reg.addr = (uintptr_t)(&fpr);
-    reg.id = AARCH64_SIMD_CTRL_REG(fp_regs.fpsr);
-    ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
+    ret = kvm_get_one_reg(cs, AARCH64_SIMD_CTRL_REG(fp_regs.fpsr), &fpr);
     if (ret) {
         return ret;
     }
     vfp_set_fpsr(env, fpr);
 
-    reg.addr = (uintptr_t)(&fpr);
-    reg.id = AARCH64_SIMD_CTRL_REG(fp_regs.fpcr);
-    ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
+    ret = kvm_get_one_reg(cs, AARCH64_SIMD_CTRL_REG(fp_regs.fpcr), &fpr);
     if (ret) {
         return ret;
     }
-- 
2.34.1

For the Thumb T32 encoding of LDM, if only a single register is
specified in the register list this instruction is UNPREDICTABLE,
with the following choices:
 * instruction UNDEFs
 * instruction is a NOP
 * instruction loads a single register
 * instruction loads an unspecified set of registers

Currently we choose to UNDEF (a behaviour chosen in commit
4b222545dbf30 in 2019; previously we treated it as "load the
specified single register").

Unfortunately there is real world code out there (which shipped in at
least Android 11, 12 and 13) which incorrectly uses this
UNPREDICTABLE insn on the assumption that it does a single register
load, which is (presumably) what it happens to do on real hardware,
and is also what it does on the equivalent A32 encoding.

Revert to the pre-4b222545dbf30 behaviour of not UNDEFing
for this T32 encoding.

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1799
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230927101853.39288-1-peter.maydell@linaro.org
---
 target/arm/tcg/translate.c | 37 +++++++++++++++++++++++--------------
 1 file changed, 23 insertions(+), 14 deletions(-)

diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/tcg/translate.c
+++ b/target/arm/tcg/translate.c
@@ -XXX,XX +XXX,XX @@ static void op_addr_block_post(DisasContext *s, arg_ldst_block *a,
     }
 }
 
-static bool op_stm(DisasContext *s, arg_ldst_block *a, int min_n)
+static bool op_stm(DisasContext *s, arg_ldst_block *a)
 {
     int i, j, n, list, mem_idx;
     bool user = a->u;
@@ -XXX,XX +XXX,XX @@ static bool op_stm(DisasContext *s, arg_ldst_block *a, int min_n)
 
     list = a->list;
     n = ctpop16(list);
-    if (n < min_n || a->rn == 15) {
+    /*
+     * This is UNPREDICTABLE for n < 1 in all encodings, and we choose
+     * to UNDEF. In the T32 STM encoding n == 1 is also UNPREDICTABLE,
+     * but hardware treats it like the A32 version and implements the
+     * single-register-store, and some in-the-wild (buggy) software
+     * assumes that, so we don't UNDEF on that case.
+     */
+    if (n < 1 || a->rn == 15) {
         unallocated_encoding(s);
         return true;
     }
@@ -XXX,XX +XXX,XX @@ static bool op_stm(DisasContext *s, arg_ldst_block *a, int min_n)
 
 static bool trans_STM(DisasContext *s, arg_ldst_block *a)
 {
-    /* BitCount(list) < 1 is UNPREDICTABLE */
-    return op_stm(s, a, 1);
+    return op_stm(s, a);
 }
 
 static bool trans_STM_t32(DisasContext *s, arg_ldst_block *a)
@@ -XXX,XX +XXX,XX @@ static bool trans_STM_t32(DisasContext *s, arg_ldst_block *a)
         unallocated_encoding(s);
         return true;
     }
-    /* BitCount(list) < 2 is UNPREDICTABLE */
-    return op_stm(s, a, 2);
+    return op_stm(s, a);
 }
 
-static bool do_ldm(DisasContext *s, arg_ldst_block *a, int min_n)
+static bool do_ldm(DisasContext *s, arg_ldst_block *a)
 {
     int i, j, n, list, mem_idx;
     bool loaded_base;
@@ -XXX,XX +XXX,XX @@ static bool do_ldm(DisasContext *s, arg_ldst_block *a, int min_n)
 
     list = a->list;
     n = ctpop16(list);
-    if (n < min_n || a->rn == 15) {
+    /*
+     * This is UNPREDICTABLE for n < 1 in all encodings, and we choose
+     * to UNDEF. In the T32 LDM encoding n == 1 is also UNPREDICTABLE,
+     * but hardware treats it like the A32 version and implements the
+     * single-register-load, and some in-the-wild (buggy) software
+     * assumes that, so we don't UNDEF on that case.
+     */
+    if (n < 1 || a->rn == 15) {
         unallocated_encoding(s);
         return true;
     }
@@ -XXX,XX +XXX,XX @@ static bool trans_LDM_a32(DisasContext *s, arg_ldst_block *a)
         unallocated_encoding(s);
         return true;
     }
-    /* BitCount(list) < 1 is UNPREDICTABLE */
-    return do_ldm(s, a, 1);
+    return do_ldm(s, a);
 }
 
 static bool trans_LDM_t32(DisasContext *s, arg_ldst_block *a)
@@ -XXX,XX +XXX,XX @@ static bool trans_LDM_t32(DisasContext *s, arg_ldst_block *a)
         unallocated_encoding(s);
         return true;
     }
-    /* BitCount(list) < 2 is UNPREDICTABLE */
-    return do_ldm(s, a, 2);
+    return do_ldm(s, a);
 }
 
 static bool trans_LDM_t16(DisasContext *s, arg_ldst_block *a)
 {
     /* Writeback is conditional on the base register not being loaded.  */
     a->w = !(a->list & (1 << a->rn));
-    /* BitCount(list) < 1 is UNPREDICTABLE */
-    return do_ldm(s, a, 1);
+    return do_ldm(s, a);
 }
 
 static bool trans_CLRM(DisasContext *s, arg_CLRM *a)
-- 
2.34.1

Update the SMMUv3 ID register bit field definitions to the
set in the most recent specification (IHI0700 F.a).

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Mostafa Saleh <smostafa@google.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Message-id: 20230914145705.1648377-2-peter.maydell@linaro.org
---
 hw/arm/smmuv3-internal.h | 38 ++++++++++++++++++++++++++++++++++++++
 1 file changed, 38 insertions(+)

diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/smmuv3-internal.h
+++ b/hw/arm/smmuv3-internal.h
@@ -XXX,XX +XXX,XX @@ REG32(IDR0,                0x0)
     FIELD(IDR0, S1P,         1 , 1)
     FIELD(IDR0, TTF,         2 , 2)
     FIELD(IDR0, COHACC,      4 , 1)
+    FIELD(IDR0, BTM,         5 , 1)
+    FIELD(IDR0, HTTU,        6 , 2)
+    FIELD(IDR0, DORMHINT,    8 , 1)
+    FIELD(IDR0, HYP,         9 , 1)
+    FIELD(IDR0, ATS,         10, 1)
+    FIELD(IDR0, NS1ATS,      11, 1)
     FIELD(IDR0, ASID16,      12, 1)
+    FIELD(IDR0, MSI,         13, 1)
+    FIELD(IDR0, SEV,         14, 1)
+    FIELD(IDR0, ATOS,        15, 1)
+    FIELD(IDR0, PRI,         16, 1)
+    FIELD(IDR0, VMW,         17, 1)
     FIELD(IDR0, VMID16,      18, 1)
+    FIELD(IDR0, CD2L,        19, 1)
+    FIELD(IDR0, VATOS,       20, 1)
     FIELD(IDR0, TTENDIAN,    21, 2)
+    FIELD(IDR0, ATSRECERR,   23, 1)
     FIELD(IDR0, STALL_MODEL, 24, 2)
     FIELD(IDR0, TERM_MODEL,  26, 1)
     FIELD(IDR0, STLEVEL,     27, 2)
+    FIELD(IDR0, RME_IMPL,    30, 1)
 
 REG32(IDR1,                0x4)
     FIELD(IDR1, SIDSIZE,      0 , 6)
+    FIELD(IDR1, SSIDSIZE,     6 , 5)
+    FIELD(IDR1, PRIQS,        11, 5)
     FIELD(IDR1, EVENTQS,      16, 5)
     FIELD(IDR1, CMDQS,        21, 5)
+    FIELD(IDR1, ATTR_PERMS_OVR, 26, 1)
+    FIELD(IDR1, ATTR_TYPES_OVR, 27, 1)
+    FIELD(IDR1, REL,          28, 1)
+    FIELD(IDR1, QUEUES_PRESET, 29, 1)
+    FIELD(IDR1, TABLES_PRESET, 30, 1)
+    FIELD(IDR1, ECMDQ,        31, 1)
 
 #define SMMU_IDR1_SIDSIZE 16
 #define SMMU_CMDQS   19
 #define SMMU_EVENTQS 19
 
 REG32(IDR2,                0x8)
+     FIELD(IDR2, BA_VATOS, 0, 10)
+
 REG32(IDR3,                0xc)
      FIELD(IDR3, HAD,         2, 1);
+     FIELD(IDR3, PBHA,        3, 1);
+     FIELD(IDR3, XNX,         4, 1);
+     FIELD(IDR3, PPS,         5, 1);
+     FIELD(IDR3, MPAM,        7, 1);
+     FIELD(IDR3, FWB,         8, 1);
+     FIELD(IDR3, STT,         9, 1);
      FIELD(IDR3, RIL,        10, 1);
      FIELD(IDR3, BBML,       11, 2);
+     FIELD(IDR3, E0PD,       13, 1);
+     FIELD(IDR3, PTWNNC,     14, 1);
+     FIELD(IDR3, DPT,        15, 1);
+
 REG32(IDR4,                0x10)
+
 REG32(IDR5,                0x14)
      FIELD(IDR5, OAS,         0, 3);
      FIELD(IDR5, GRAN4K,      4, 1);
      FIELD(IDR5, GRAN16K,     5, 1);
      FIELD(IDR5, GRAN64K,     6, 1);
+     FIELD(IDR5, VAX,        10, 2);
+     FIELD(IDR5, STALL_MAX,  16, 16);
 
 #define SMMU_IDR5_OAS 4
 
-- 
2.34.1

In smmuv3_init_regs() when we set the various bits in the ID
registers, we do this almost in order of the fields in the
registers, but not quite. Move the initialization of
SMMU_IDR3.RIL and SMMU_IDR5.OAS into their correct places.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Mostafa Saleh <smostafa@google.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Message-id: 20230914145705.1648377-3-peter.maydell@linaro.org
---
 hw/arm/smmuv3.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/smmuv3.c
+++ b/hw/arm/smmuv3.c
@@ -XXX,XX +XXX,XX @@ static void smmuv3_init_regs(SMMUv3State *s)
     s->idr[1] = FIELD_DP32(s->idr[1], IDR1, EVENTQS, SMMU_EVENTQS);
     s->idr[1] = FIELD_DP32(s->idr[1], IDR1, CMDQS,   SMMU_CMDQS);
 
-    s->idr[3] = FIELD_DP32(s->idr[3], IDR3, RIL, 1);
     s->idr[3] = FIELD_DP32(s->idr[3], IDR3, HAD, 1);
+    s->idr[3] = FIELD_DP32(s->idr[3], IDR3, RIL, 1);
     s->idr[3] = FIELD_DP32(s->idr[3], IDR3, BBML, 2);
 
+    s->idr[5] = FIELD_DP32(s->idr[5], IDR5, OAS, SMMU_IDR5_OAS); /* 44 bits */
     /* 4K, 16K and 64K granule support */
     s->idr[5] = FIELD_DP32(s->idr[5], IDR5, GRAN4K, 1);
     s->idr[5] = FIELD_DP32(s->idr[5], IDR5, GRAN16K, 1);
     s->idr[5] = FIELD_DP32(s->idr[5], IDR5, GRAN64K, 1);
-    s->idr[5] = FIELD_DP32(s->idr[5], IDR5, OAS, SMMU_IDR5_OAS); /* 44 bits */
 
     s->cmdq.base = deposit64(s->cmdq.base, 0, 5, SMMU_CMDQS);
     s->cmdq.prod = 0;
-- 
2.34.1

The SMMUv3.1-XNX feature is mandatory for an SMMUv3.1 if S2P is
supported, so we should theoretically have implemented it as part of
the recent S2P work.  Fortunately, for us the implementation is a
no-op.

This feature is about interpretation of the stage 2 page table
descriptor XN bits, which control execute permissions.

For QEMU, the permission bits passed to an IOMMU (via MemTxAttrs and
IOMMUAccessFlags) only indicate read and write; we do not distinguish
data reads from instruction reads outside the CPU proper.  In the
SMMU architecture's terms, our interconnect between the client device
and the SMMU doesn't have the ability to convey the INST attribute,
and we therefore use the default value of "data" for this attribute.

We also do not support the bits in the Stream Table Entry that can
override the on-the-bus transaction attribute permissions (we do not
set SMMU_IDR1.ATTR_PERMS_OVR=1).

These two things together mean that for our implementation, it never
has to deal with transactions with the INST attribute, and so it can
correctly ignore the XN bits entirely.  So we already implement
FEAT_XNX's "XN field is now 2 bits, not 1" behaviour to the extent
that we need to.

Advertise the presence of the feature in SMMU_IDR3.XNX.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Mostafa Saleh <smostafa@google.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Message-id: 20230914145705.1648377-4-peter.maydell@linaro.org
---
 hw/arm/smmuv3.c | 4 ++++
 1 file changed, 4 insertions(+)

FEAT_HPMN0 is a small feature which defines that it is valid for
MDCR_EL2.HPMN to be set to 0, meaning "no PMU event counters provided
to an EL1 guest" (previously this setting was reserved). QEMU's
implementation almost gets HPMN == 0 right, but we need to fix
one check in pmevcntr_is_64_bit(). That is enough for us to
advertise the feature in the 'max' CPU.

(We don't need to make the behaviour conditional on feature
presence, because the FEAT_HPMN0 behaviour is within the range
of permitted UNPREDICTABLE behaviour for a non-FEAT_HPMN0
implementation.)

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230921185445.3339214-1-peter.maydell@linaro.org
---
 docs/system/arm/emulation.rst | 1 +
 target/arm/helper.c           | 2 +-
 target/arm/tcg/cpu32.c        | 4 ++++
 target/arm/tcg/cpu64.c        | 1 +
 4 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
index XXXXXXX..XXXXXXX 100644
--- a/docs/system/arm/emulation.rst
+++ b/docs/system/arm/emulation.rst
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
 - FEAT_HCX (Support for the HCRX_EL2 register)
 - FEAT_HPDS (Hierarchical permission disables)
 - FEAT_HPDS2 (Translation table page-based hardware attributes)
+- FEAT_HPMN0 (Setting of MDCR_EL2.HPMN to zero)
 - FEAT_I8MM (AArch64 Int8 matrix multiplication instructions)
 - FEAT_IDST (ID space trap handling)
 - FEAT_IESB (Implicit error synchronization event)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static bool pmevcntr_is_64_bit(CPUARMState *env, int counter)
         bool hlp = env->cp15.mdcr_el2 & MDCR_HLP;
         int hpmn = env->cp15.mdcr_el2 & MDCR_HPMN;
 
-        if (hpmn != 0 && counter >= hpmn) {
+        if (counter >= hpmn) {
             return hlp;
         }
     }
diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/tcg/cpu32.c
+++ b/target/arm/tcg/cpu32.c
@@ -XXX,XX +XXX,XX @@ void aa32_max_features(ARMCPU *cpu)
     t = FIELD_DP32(t, ID_DFR0, COPSDBG, 9);       /* FEAT_Debugv8p4 */
     t = FIELD_DP32(t, ID_DFR0, PERFMON, 6);       /* FEAT_PMUv3p5 */
     cpu->isar.id_dfr0 = t;
+
+    t = cpu->isar.id_dfr1;
+    t = FIELD_DP32(t, ID_DFR1, HPMN0, 1);         /* FEAT_HPMN0 */
+    cpu->isar.id_dfr1 = t;
 }
 
 /* CPU models. These are not needed for the AArch64 linux-user build. */
diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/tcg/cpu64.c
+++ b/target/arm/tcg/cpu64.c
@@ -XXX,XX +XXX,XX @@ void aarch64_max_tcg_initfn(Object *obj)
     t = cpu->isar.id_aa64dfr0;
     t = FIELD_DP64(t, ID_AA64DFR0, DEBUGVER, 9);  /* FEAT_Debugv8p4 */
     t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 6);    /* FEAT_PMUv3p5 */
+    t = FIELD_DP64(t, ID_AA64DFR0, HPMN0, 1);     /* FEAT_HPMN0 */
     cpu->isar.id_aa64dfr0 = t;
 
     t = cpu->isar.id_aa64smfr0;
-- 
2.34.1

The hw/arm/boot.h include in common-semi-target.h is not actually
needed, and it's a bit odd because it pulls a hw/arm header into a
target/arm file.

This include was originally needed because the semihosting code used
the arm_boot_info struct to get the base address of the RAM in system
emulation, to use in a (bad) heuristic for the return values for the
SYS_HEAPINFO semihosting call.  We've since overhauled how we
calculate the HEAPINFO values in system emulation, and the code no
longer uses the arm_boot_info struct.

Remove the now-redundant include line, and instead directly include
the cpu-qom.h header that we were previously getting via boot.h.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230925112219.3919261-1-peter.maydell@linaro.org
---
 target/arm/common-semi-target.h | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/target/arm/common-semi-target.h b/target/arm/common-semi-target.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/common-semi-target.h
+++ b/target/arm/common-semi-target.h
@@ -XXX,XX +XXX,XX @@
 #ifndef TARGET_ARM_COMMON_SEMI_TARGET_H
 #define TARGET_ARM_COMMON_SEMI_TARGET_H
 
-#ifndef CONFIG_USER_ONLY
-#include "hw/arm/boot.h"
-#endif
+#include "target/arm/cpu-qom.h"
 
 static inline target_ulong common_semi_arg(CPUState *cs, int argno)
 {
-- 
2.34.1

The code for powering on a CPU in arm-powerctl.c has two separate
use cases:
 * emulation of a real hardware power controller
 * emulation of firmware interfaces (primarily PSCI) with
   CPU on/off APIs

For the first case, we only need to reset the CPU and set its
starting PC and X0.  For the second case, because we're emulating the
firmware we need to ensure that it's in the state that the firmware
provides.  In particular, when we reset to a lower EL than the
highest one we are emulating, we need to put the CPU into a state
that permits correct running at that lower EL.  We already do a
little of this in arm-powerctl.c (for instance we set SCR_HCE to
enable the HVC insn) but we don't do enough of it.  This means that
in the case where we are emulating EL3 but also providing emulated
PSCI the guest will crash when a secondary core tries to use a
feature that needs an SCR_EL3 bit to be set, such as MTE or PAuth.

The hw/arm/boot.c code also has to support this "start guest code in
an EL that's lower than the highest emulated EL" case in order to do
direct guest kernel booting; it has all the necessary initialization
code to set the SCR_EL3 bits.  Pull the relevant boot.c code out into
a separate function so we can share it between there and
arm-powerctl.c.

This refactoring has a few code changes that look like they
might be behaviour changes but aren't:
 * if info->secure_boot is false and info->secure_board_setup is
   true, then the old code would start the first CPU in Hyp
   mode but without changing SCR.NS and NSACR.{CP11,CP10}.
   This was wrong behaviour because there's no such thing
   as Secure Hyp mode. The new code will leave the CPU in SVC.
   (There is no board which sets secure_boot to false and
   secure_board_setup to true, so this isn't a behaviour
   change for any of our boards.)
 * we don't explicitly clear SCR.NS when arm-powerctl.c
   does a CPU-on to EL3. This was a no-op because CPU reset
   will reset to NS == 0.

And some real behaviour changes:
 * we no longer set HCR_EL2.RW when booting into EL2: the guest
   can and should do that themselves before dropping into their
   EL1 code. (arm-powerctl and boot did this differently; I
   opted to use the logic from arm-powerctl, which only sets
   HCR_EL2.RW when it's directly starting the guest in EL1,
   because it's more correct, and I don't expect guests to be
   accidentally depending on our having set the RW bit for them.)
 * if we are booting a CPU into AArch32 Secure SVC then we won't
   set SCR.HCE any more. This affects only the vexpress-a15 and
   raspi2b machine types. Guests booting in this case will either:
    - be able to set SCR.HCE themselves as part of moving from
      Secure SVC into NS Hyp mode
    - will move from Secure SVC to NS SVC, and won't care about
      behaviour of the HVC insn
    - will stay in Secure SVC, and won't care about HVC
 * on an arm-powerctl CPU-on we will now set the SCR bits for
   pauth/mte/sve/sme/hcx/fgt features

The first two of these are very minor and I don't expect guest
code to trip over them, so I didn't judge it worth convoluting
the code in an attempt to keep exactly the same boot.c behaviour.
The third change fixes issue 1899.

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1899
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230926155619.4028618-1-peter.maydell@linaro.org
---
 target/arm/cpu.h          | 22 +++++++++
 hw/arm/boot.c             | 95 ++++++++++-----------------------------
 target/arm/arm-powerctl.c | 53 +---------------------
 target/arm/cpu.c          | 95 +++++++++++++++++++++++++++++++++++++++
 4 files changed, 141 insertions(+), 124 deletions(-)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ int arm_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs,
 int arm_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs,
                              int cpuid, DumpState *s);
 
+/**
+ * arm_emulate_firmware_reset: Emulate firmware CPU reset handling
+ * @cpu: CPU (which must have been freshly reset)
+ * @target_el: exception level to put the CPU into
+ * @secure: whether to put the CPU in secure state
+ *
+ * When QEMU is directly running a guest kernel at a lower level than
+ * EL3 it implicitly emulates some aspects of the guest firmware.
+ * This includes that on reset we need to configure the parts of the
+ * CPU corresponding to EL3 so that the real guest code can run at its
+ * lower exception level. This function does that post-reset CPU setup,
+ * for when we do direct boot of a guest kernel, and for when we
+ * emulate PSCI and similar firmware interfaces starting a CPU at a
+ * lower exception level.
+ *
+ * @target_el must be an EL implemented by the CPU between 1 and 3.
+ * We do not support dropping into a Secure EL other than 3.
+ *
+ * It is the responsibility of the caller to call arm_rebuild_hflags().
+ */
+void arm_emulate_firmware_reset(CPUState *cpustate, int target_el);
+
 #ifdef TARGET_AARCH64
 int aarch64_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
 int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/boot.c
+++ b/hw/arm/boot.c
@@ -XXX,XX +XXX,XX @@ static void do_cpu_reset(void *opaque)
 
             cpu_set_pc(cs, entry);
         } else {
-            /* If we are booting Linux then we need to check whether we are
-             * booting into secure or non-secure state and adjust the state
-             * accordingly.  Out of reset, ARM is defined to be in secure state
-             * (SCR.NS = 0), we change that here if non-secure boot has been
-             * requested.
+            /*
+             * If we are booting Linux then we might need to do so at:
+             *  - AArch64 NS EL2 or NS EL1
+             *  - AArch32 Secure SVC (EL3)
+             *  - AArch32 NS Hyp (EL2)
+             *  - AArch32 NS SVC (EL1)
+             * Configure the CPU in the way boot firmware would do to
+             * drop us down to the appropriate level.
              */
-            if (arm_feature(env, ARM_FEATURE_EL3)) {
-                /* AArch64 is defined to come out of reset into EL3 if enabled.
-                 * If we are booting Linux then we need to adjust our EL as
-                 * Linux expects us to be in EL2 or EL1.  AArch32 resets into
-                 * SVC, which Linux expects, so no privilege/exception level to
-                 * adjust.
-                 */
-                if (env->aarch64) {
-                    env->cp15.scr_el3 |= SCR_RW;
-                    if (arm_feature(env, ARM_FEATURE_EL2)) {
-                        env->cp15.hcr_el2 |= HCR_RW;
-                        env->pstate = PSTATE_MODE_EL2h;
-                    } else {
-                        env->pstate = PSTATE_MODE_EL1h;
-                    }
-                    if (cpu_isar_feature(aa64_pauth, cpu)) {
-                        env->cp15.scr_el3 |= SCR_API | SCR_APK;
-                    }
-                    if (cpu_isar_feature(aa64_mte, cpu)) {
-                        env->cp15.scr_el3 |= SCR_ATA;
-                    }
-                    if (cpu_isar_feature(aa64_sve, cpu)) {
-                        env->cp15.cptr_el[3] |= R_CPTR_EL3_EZ_MASK;
-                        env->vfp.zcr_el[3] = 0xf;
-                    }
-                    if (cpu_isar_feature(aa64_sme, cpu)) {
-                        env->cp15.cptr_el[3] |= R_CPTR_EL3_ESM_MASK;
-                        env->cp15.scr_el3 |= SCR_ENTP2;
-                        env->vfp.smcr_el[3] = 0xf;
-                    }
-                    if (cpu_isar_feature(aa64_hcx, cpu)) {
-                        env->cp15.scr_el3 |= SCR_HXEN;
-                    }
-                    if (cpu_isar_feature(aa64_fgt, cpu)) {
-                        env->cp15.scr_el3 |= SCR_FGTEN;
-                    }
+            int target_el = arm_feature(env, ARM_FEATURE_EL2) ? 2 : 1;
 
-                    /* AArch64 kernels never boot in secure mode */
-                    assert(!info->secure_boot);
-                    /* This hook is only supported for AArch32 currently:
-                     * bootloader_aarch64[] will not call the hook, and
-                     * the code above has already dropped us into EL2 or EL1.
-                     */
-                    assert(!info->secure_board_setup);
-                }
-
-                if (arm_feature(env, ARM_FEATURE_EL2)) {
-                    /* If we have EL2 then Linux expects the HVC insn to work */
-                    env->cp15.scr_el3 |= SCR_HCE;
-                }
-
-                /* Set to non-secure if not a secure boot */
-                if (!info->secure_boot &&
-                    (cs != first_cpu || !info->secure_board_setup)) {
-                    /* Linux expects non-secure state */
-                    env->cp15.scr_el3 |= SCR_NS;
-                    /* Set NSACR.{CP11,CP10} so NS can access the FPU */
-                    env->cp15.nsacr |= 3 << 10;
-                }
-            }
-
-            if (!env->aarch64 && !info->secure_boot &&
-                arm_feature(env, ARM_FEATURE_EL2)) {
+            if (env->aarch64) {
                 /*
-                 * This is an AArch32 boot not to Secure state, and
-                 * we have Hyp mode available, so boot the kernel into
-                 * Hyp mode. This is not how the CPU comes out of reset,
-                 * so we need to manually put it there.
+                 * AArch64 kernels never boot in secure mode, and we don't
+                 * support the secure_board_setup hook for AArch64.
                  */
-                cpsr_write(env, ARM_CPU_MODE_HYP, CPSR_M, CPSRWriteRaw);
+                assert(!info->secure_boot);
+                assert(!info->secure_board_setup);
+            } else {
+                if (arm_feature(env, ARM_FEATURE_EL3) &&
+                    (info->secure_boot ||
+                     (info->secure_board_setup && cs == first_cpu))) {
+                    /* Start this CPU in Secure SVC */
+                    target_el = 3;
+                }
             }
 
+            arm_emulate_firmware_reset(cs, target_el);
+
             if (cs == first_cpu) {
                 AddressSpace *as = arm_boot_address_space(cpu, info);
 
diff --git a/target/arm/arm-powerctl.c b/target/arm/arm-powerctl.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/arm-powerctl.c
+++ b/target/arm/arm-powerctl.c
@@ -XXX,XX +XXX,XX @@ static void arm_set_cpu_on_async_work(CPUState *target_cpu_state,
 
     /* Initialize the cpu we are turning on */
     cpu_reset(target_cpu_state);
+    arm_emulate_firmware_reset(target_cpu_state, info->target_el);
     target_cpu_state->halted = 0;
 
-    if (info->target_aa64) {
-        if ((info->target_el < 3) && arm_feature(&target_cpu->env,
-                                                 ARM_FEATURE_EL3)) {
-            /*
-             * As target mode is AArch64, we need to set lower
-             * exception level (the requested level 2) to AArch64
-             */
-            target_cpu->env.cp15.scr_el3 |= SCR_RW;
-        }
-
-        if ((info->target_el < 2) && arm_feature(&target_cpu->env,
-                                                 ARM_FEATURE_EL2)) {
-            /*
-             * As target mode is AArch64, we need to set lower
-             * exception level (the requested level 1) to AArch64
-             */
-            target_cpu->env.cp15.hcr_el2 |= HCR_RW;
-        }
-
-        target_cpu->env.pstate = aarch64_pstate_mode(info->target_el, true);
-    } else {
-        /* We are requested to boot in AArch32 mode */
-        static const uint32_t mode_for_el[] = { 0,
-                                                ARM_CPU_MODE_SVC,
-                                                ARM_CPU_MODE_HYP,
-                                                ARM_CPU_MODE_SVC };
-
-        cpsr_write(&target_cpu->env, mode_for_el[info->target_el], CPSR_M,
-                   CPSRWriteRaw);
-    }
-
-    if (info->target_el == 3) {
-        /* Processor is in secure mode */
-        target_cpu->env.cp15.scr_el3 &= ~SCR_NS;
-    } else {
-        /* Processor is not in secure mode */
-        target_cpu->env.cp15.scr_el3 |= SCR_NS;
-
-        /* Set NSACR.{CP11,CP10} so NS can access the FPU */
-        target_cpu->env.cp15.nsacr |= 3 << 10;
-
-        /*
-         * If QEMU is providing the equivalent of EL3 firmware, then we need
-         * to make sure a CPU targeting EL2 comes out of reset with a
-         * functional HVC insn.
-         */
-        if (arm_feature(&target_cpu->env, ARM_FEATURE_EL3)
-            && info->target_el == 2) {
-            target_cpu->env.cp15.scr_el3 |= SCR_HCE;
-        }
-    }
-
     /* We check if the started CPU is now at the correct level */
     assert(info->target_el == arm_current_el(&target_cpu->env));
 
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset_hold(Object *obj)
     }
 }
 
+void arm_emulate_firmware_reset(CPUState *cpustate, int target_el)
+{
+    ARMCPU *cpu = ARM_CPU(cpustate);
+    CPUARMState *env = &cpu->env;
+    bool have_el3 = arm_feature(env, ARM_FEATURE_EL3);
+    bool have_el2 = arm_feature(env, ARM_FEATURE_EL2);
+
+    /*
+     * Check we have the EL we're aiming for. If that is the
+     * highest implemented EL, then cpu_reset has already done
+     * all the work.
+     */
+    switch (target_el) {
+    case 3:
+        assert(have_el3);
+        return;
+    case 2:
+        assert(have_el2);
+        if (!have_el3) {
+            return;
+        }
+        break;
+    case 1:
+        if (!have_el3 && !have_el2) {
+            return;
+        }
+        break;
+    default:
+        g_assert_not_reached();
+    }
+
+    if (have_el3) {
+        /*
+         * Set the EL3 state so code can run at EL2. This should match
+         * the requirements set by Linux in its booting spec.
+         */
+        if (env->aarch64) {
+            env->cp15.scr_el3 |= SCR_RW;
+            if (cpu_isar_feature(aa64_pauth, cpu)) {
+                env->cp15.scr_el3 |= SCR_API | SCR_APK;
+            }
+            if (cpu_isar_feature(aa64_mte, cpu)) {
+                env->cp15.scr_el3 |= SCR_ATA;
+            }
+            if (cpu_isar_feature(aa64_sve, cpu)) {
+                env->cp15.cptr_el[3] |= R_CPTR_EL3_EZ_MASK;
+                env->vfp.zcr_el[3] = 0xf;
+            }
+            if (cpu_isar_feature(aa64_sme, cpu)) {
+                env->cp15.cptr_el[3] |= R_CPTR_EL3_ESM_MASK;
+                env->cp15.scr_el3 |= SCR_ENTP2;
+                env->vfp.smcr_el[3] = 0xf;
+            }
+            if (cpu_isar_feature(aa64_hcx, cpu)) {
+                env->cp15.scr_el3 |= SCR_HXEN;
+            }
+            if (cpu_isar_feature(aa64_fgt, cpu)) {
+                env->cp15.scr_el3 |= SCR_FGTEN;
+            }
+        }
+
+        if (target_el == 2) {
+            /* If the guest is at EL2 then Linux expects the HVC insn to work */
+            env->cp15.scr_el3 |= SCR_HCE;
+        }
+
+        /* Put CPU into non-secure state */
+        env->cp15.scr_el3 |= SCR_NS;
+        /* Set NSACR.{CP11,CP10} so NS can access the FPU */
+        env->cp15.nsacr |= 3 << 10;
+    }
+
+    if (have_el2 && target_el < 2) {
+        /* Set EL2 state so code can run at EL1. */
+        if (env->aarch64) {
+            env->cp15.hcr_el2 |= HCR_RW;
+        }
+    }
+
+    /* Set the CPU to the desired state */
+    if (env->aarch64) {
+        env->pstate = aarch64_pstate_mode(target_el, true);
+    } else {
+        static const uint32_t mode_for_el[] = {
+            0,
+            ARM_CPU_MODE_SVC,
+            ARM_CPU_MODE_HYP,
+            ARM_CPU_MODE_SVC,
+        };
+
+        cpsr_write(env, mode_for_el[target_el], CPSR_M, CPSRWriteRaw);
+    }
+}
+
+
 #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
 
 static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx,
-- 
2.34.1

From: Chris Rauer <crauer@google.com>

The counter register is only 24-bits and counts down.  If the timer is
running but the qtimer to reset it hasn't fired off yet, there is a chance
the regster read can return an invalid result.

Signed-off-by: Chris Rauer <crauer@google.com>
Message-id: 20230922181411.2697135-1-crauer@google.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/timer/npcm7xx_timer.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/hw/timer/npcm7xx_timer.c b/hw/timer/npcm7xx_timer.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/timer/npcm7xx_timer.c
+++ b/hw/timer/npcm7xx_timer.c
@@ -XXX,XX +XXX,XX @@ static int64_t npcm7xx_timer_count_to_ns(NPCM7xxTimer *t, uint32_t count)
 /* Convert a time interval in nanoseconds to a timer cycle count. */
 static uint32_t npcm7xx_timer_ns_to_count(NPCM7xxTimer *t, int64_t ns)
 {
+    if (ns < 0) {
+        return 0;
+    }
     return clock_ns_to_ticks(t->ctrl->clock, ns) /
         npcm7xx_tcsr_prescaler(t->tcsr);
 }
-- 
2.34.1

From: Suraj Shirvankar <surajshirvankar@gmail.com>

QEMU coding style uses the glib memory allocation APIs, not
the raw libc malloc/free. Switch the allocation and free
calls in elf2dmp to use these functions (dropping the now-unneeded
checks for failure).

Signed-off-by: Suraj Shirvankar <surajshirvankar@gmail.com>
Message-id: 169753938460.23804.11418813007617535750-1@git.sr.ht
[PMM: also remove NULL checks from g_malloc() calls;
 beef up commit message]
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 contrib/elf2dmp/addrspace.c |  7 ++-----
 contrib/elf2dmp/main.c      |  9 +++------
 contrib/elf2dmp/pdb.c       | 19 ++++++++-----------
 contrib/elf2dmp/qemu_elf.c  |  7 ++-----
 4 files changed, 15 insertions(+), 27 deletions(-)

diff --git a/contrib/elf2dmp/addrspace.c b/contrib/elf2dmp/addrspace.c
index XXXXXXX..XXXXXXX 100644
--- a/contrib/elf2dmp/addrspace.c
+++ b/contrib/elf2dmp/addrspace.c
@@ -XXX,XX +XXX,XX @@ int pa_space_create(struct pa_space *ps, QEMU_Elf *qemu_elf)
         }
     }
 
-    ps->block = malloc(sizeof(*ps->block) * ps->block_nr);
-    if (!ps->block) {
-        return 1;
-    }
+    ps->block = g_new(struct pa_block, ps->block_nr);
 
     for (i = 0; i < phdr_nr; i++) {
         if (phdr[i].p_type == PT_LOAD) {
@@ -XXX,XX +XXX,XX @@ int pa_space_create(struct pa_space *ps, QEMU_Elf *qemu_elf)
 void pa_space_destroy(struct pa_space *ps)
 {
     ps->block_nr = 0;
-    free(ps->block);
+    g_free(ps->block);
 }
 
 void va_space_set_dtb(struct va_space *vs, uint64_t dtb)
diff --git a/contrib/elf2dmp/main.c b/contrib/elf2dmp/main.c
index XXXXXXX..XXXXXXX 100644
--- a/contrib/elf2dmp/main.c
+++ b/contrib/elf2dmp/main.c
@@ -XXX,XX +XXX,XX @@ static KDDEBUGGER_DATA64 *get_kdbg(uint64_t KernBase, struct pdb_reader *pdb,
         }
     }
 
-    kdbg = malloc(kdbg_hdr.Size);
-    if (!kdbg) {
-        return NULL;
-    }
+    kdbg = g_malloc(kdbg_hdr.Size);
 
     if (va_space_rw(vs, KdDebuggerDataBlock, kdbg, kdbg_hdr.Size, 0)) {
         eprintf("Failed to extract entire KDBG\n");
-        free(kdbg);
+        g_free(kdbg);
         return NULL;
     }
 
@@ -XXX,XX +XXX,XX @@ int main(int argc, char *argv[])
     }
 
 out_kdbg:
-    free(kdbg);
+    g_free(kdbg);
 out_pdb:
     pdb_exit(&pdb);
 out_pdb_file:
diff --git a/contrib/elf2dmp/pdb.c b/contrib/elf2dmp/pdb.c
index XXXXXXX..XXXXXXX 100644
--- a/contrib/elf2dmp/pdb.c
+++ b/contrib/elf2dmp/pdb.c
@@ -XXX,XX +XXX,XX @@ uint64_t pdb_resolve(uint64_t img_base, struct pdb_reader *r, const char *name)
 
 static void pdb_reader_ds_exit(struct pdb_reader *r)
 {
-    free(r->ds.toc);
+    g_free(r->ds.toc);
 }
 
 static void pdb_exit_symbols(struct pdb_reader *r)
 {
-    free(r->modimage);
-    free(r->symbols);
+    g_free(r->modimage);
+    g_free(r->symbols);
 }
 
 static void pdb_exit_segments(struct pdb_reader *r)
 {
-    free(r->segs);
+    g_free(r->segs);
 }
 
 static void *pdb_ds_read(const PDB_DS_HEADER *header,
@@ -XXX,XX +XXX,XX @@ static void *pdb_ds_read(const PDB_DS_HEADER *header,
 
     nBlocks = (size + header->block_size - 1) / header->block_size;
 
-    buffer = malloc(nBlocks * header->block_size);
-    if (!buffer) {
-        return NULL;
-    }
+    buffer = g_malloc(nBlocks * header->block_size);
 
     for (i = 0; i < nBlocks; i++) {
         memcpy(buffer + i * header->block_size, (const char *)header +
@@ -XXX,XX +XXX,XX @@ static int pdb_init_symbols(struct pdb_reader *r)
     return 0;
 
 out_symbols:
-    free(symbols);
+    g_free(symbols);
 
     return err;
 }
@@ -XXX,XX +XXX,XX @@ static int pdb_reader_init(struct pdb_reader *r, void *data)
 out_sym:
     pdb_exit_symbols(r);
 out_root:
-    free(r->ds.root);
+    g_free(r->ds.root);
 out_ds:
     pdb_reader_ds_exit(r);
 
@@ -XXX,XX +XXX,XX @@ static void pdb_reader_exit(struct pdb_reader *r)
 {
     pdb_exit_segments(r);
     pdb_exit_symbols(r);
-    free(r->ds.root);
+    g_free(r->ds.root);
     pdb_reader_ds_exit(r);
 }
 
diff --git a/contrib/elf2dmp/qemu_elf.c b/contrib/elf2dmp/qemu_elf.c
index XXXXXXX..XXXXXXX 100644
--- a/contrib/elf2dmp/qemu_elf.c
+++ b/contrib/elf2dmp/qemu_elf.c
@@ -XXX,XX +XXX,XX @@ static int init_states(QEMU_Elf *qe)
 
     printf("%zu CPU states has been found\n", cpu_nr);
 
-    qe->state = malloc(sizeof(*qe->state) * cpu_nr);
-    if (!qe->state) {
-        return 1;
-    }
+    qe->state = g_new(QEMUCPUState*, cpu_nr);
 
     cpu_nr = 0;
 
@@ -XXX,XX +XXX,XX @@ static int init_states(QEMU_Elf *qe)
 
 static void exit_states(QEMU_Elf *qe)
 {
-    free(qe->state);
+    g_free(qe->state);
 }
 
 static bool check_ehdr(QEMU_Elf *qe)
-- 
2.34.1