Arm queue; not huge but I figured I might as well send it out since

I've been doing code review today and there's no queue of unprocessed

pullreqs...

The following changes since commit b3f846c59d8405bb87c551187721fc92ff2f1b92:

Merge remote-tracking branch 'remotes/huth-gitlab/tags/pull-request-2021-01-11v2' into staging (2021-01-11 15:15:35 +0000)

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210112

for you to fetch changes up to 19d131395ccaf503db21dadd8257e6dc9fc1d7de:

ui/cocoa: Fix openFile: deprecation on Big Sur (2021-01-12 11:38:37 +0000)

* arm: Support emulation of ARMv8.4-TTST extension

* arm: Update cpu.h ID register field definitions

* arm: Fix breakage of XScale instruction emulation

* hw/net/lan9118: Fix RX Status FIFO PEEK value

* npcm7xx: Add ADC and PWM emulation

* ui/cocoa: Make "open docs" help menu entry work again when binary

is run from the build tree

* ui/cocoa: Fix openFile: deprecation on Big Sur

* docs: Add qemu-storage-daemon(1) manpage to meson.build

* docs: Build and install all the docs in a single manual

Hao Wu (6):

hw/misc: Add clock converter in NPCM7XX CLK module

hw/timer: Refactor NPCM7XX Timer to use CLK clock

hw/adc: Add an ADC module for NPCM7XX

hw/misc: Add a PWM module for NPCM7XX

hw/misc: Add QTest for NPCM7XX PWM Module

hw/*: Use type casting for SysBusDevice in NPCM7XX

Leif Lindholm (6):

target/arm: fix typo in cpu.h ID_AA64PFR1 field name

target/arm: make ARMCPU.clidr 64-bit

target/arm: make ARMCPU.ctr 64-bit

target/arm: add descriptions of CLIDR_EL1, CCSIDR_EL1, CTR_EL0 to cpu.h

target/arm: add aarch64 ID register fields to cpu.h

target/arm: add aarch32 ID register fields to cpu.h

Peter Maydell (5):

docs: Add qemu-storage-daemon(1) manpage to meson.build

docs: Build and install all the docs in a single manual

target/arm: Don't decode insns in the XScale/iWMMXt space as cp insns

hw/net/lan9118: Fix RX Status FIFO PEEK value

hw/net/lan9118: Add symbolic constants for register offsets

Roman Bolshakov (2):

ui/cocoa: Update path to docs in build tree

ui/cocoa: Fix openFile: deprecation on Big Sur

Rémi Denis-Courmont (2):

target/arm: ARMv8.4-TTST extension

target/arm: enable Small Translation tables in max CPU

docs/conf.py | 46 ++-

docs/devel/conf.py | 15 -

docs/index.html.in | 17 -

docs/interop/conf.py | 28 --

docs/meson.build | 65 ++--

docs/specs/conf.py | 16 -

docs/system/arm/nuvoton.rst | 4 +-

docs/system/conf.py | 28 --

docs/tools/conf.py | 37 --

docs/user/conf.py | 15 -

meson.build | 1 +

hw/adc/trace.h | 1 +

include/hw/adc/npcm7xx_adc.h | 69 ++++

include/hw/arm/npcm7xx.h | 4 +

include/hw/misc/npcm7xx_clk.h | 146 ++++++-

include/hw/misc/npcm7xx_pwm.h | 105 +++++

include/hw/timer/npcm7xx_timer.h | 1 +

target/arm/cpu.h | 85 ++++-

hw/adc/npcm7xx_adc.c | 301 +++++++++++++++

hw/arm/npcm7xx.c | 55 ++-

hw/arm/npcm7xx_boards.c | 2 +-

hw/mem/npcm7xx_mc.c | 2 +-

hw/misc/npcm7xx_clk.c | 807 ++++++++++++++++++++++++++++++++++++++-

hw/misc/npcm7xx_gcr.c | 2 +-

hw/misc/npcm7xx_pwm.c | 550 ++++++++++++++++++++++++++

hw/misc/npcm7xx_rng.c | 2 +-

hw/net/lan9118.c | 26 +-

hw/nvram/npcm7xx_otp.c | 2 +-

hw/ssi/npcm7xx_fiu.c | 2 +-

hw/timer/npcm7xx_timer.c | 39 +-

target/arm/cpu64.c | 1 +

target/arm/helper.c | 15 +-

target/arm/translate.c | 7 +

tests/qtest/npcm7xx_adc-test.c | 377 ++++++++++++++++++

tests/qtest/npcm7xx_pwm-test.c | 490 ++++++++++++++++++++++++

hw/adc/meson.build | 1 +

hw/adc/trace-events | 5 +

hw/misc/meson.build | 1 +

hw/misc/trace-events | 6 +

tests/qtest/meson.build | 4 +-

ui/cocoa.m | 7 +-

41 files changed, 3124 insertions(+), 263 deletions(-)

delete mode 100644 docs/devel/conf.py

delete mode 100644 docs/index.html.in

delete mode 100644 docs/interop/conf.py

delete mode 100644 docs/specs/conf.py

delete mode 100644 docs/system/conf.py

delete mode 100644 docs/tools/conf.py

delete mode 100644 docs/user/conf.py

create mode 100644 hw/adc/trace.h

create mode 100644 include/hw/adc/npcm7xx_adc.h

create mode 100644 include/hw/misc/npcm7xx_pwm.h

create mode 100644 hw/adc/npcm7xx_adc.c

create mode 100644 hw/misc/npcm7xx_pwm.c

create mode 100644 tests/qtest/npcm7xx_adc-test.c

create mode 100644 tests/qtest/npcm7xx_pwm-test.c

create mode 100644 hw/adc/trace-events

From: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>

This adds for the Small Translation tables extension in AArch64 state.

Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

target/arm/cpu.h | 5 +++++

target/arm/helper.c | 15 +++++++++++++--

2 files changed, 18 insertions(+), 2 deletions(-)

@@ -XXX,XX +XXX,XX @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,

{

uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr;

bool epd, hpd, using16k, using64k;

- int select, tsz, tbi;

+ int select, tsz, tbi, max_tsz;

if (!regime_has_2_ranges(mmu_idx)) {

select = 0;

@@ -XXX,XX +XXX,XX @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,

hpd = extract64(tcr, 42, 1);

}

}

- tsz = MIN(tsz, 39); /* TODO: ARMv8.4-TTST */

+

+ if (cpu_isar_feature(aa64_st, env_archcpu(env))) {

+ max_tsz = 48 - using64k;

+ } else {

+ max_tsz = 39;

+ }

+

+ tsz = MIN(tsz, max_tsz);

tsz = MAX(tsz, 16); /* TODO: ARMv8.2-LVA */

/* Present TBI as a composite with TBID. */

@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address,

if (!aarch64 || stride == 9) {

/* AArch32 or 4KB pages */

startlevel = 2 - sl0;

+

+ if (cpu_isar_feature(aa64_st, cpu)) {

+ startlevel &= 3;

+ }

} else {

/* 16KB or 64KB pages */

startlevel = 3 - sl0;

2.20.1

From: Leif Lindholm <leif@nuviainc.com>

SBSS -> SSBS

Signed-off-by: Leif Lindholm <leif@nuviainc.com>

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

target/arm/cpu.h | 2 +-

1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h

--- a/target/arm/cpu.h

+++ b/target/arm/cpu.h

@@ -XXX,XX +XXX,XX @@ FIELD(ID_AA64PFR0, RAS, 28, 4)

FIELD(ID_AA64PFR0, SVE, 32, 4)

FIELD(ID_AA64PFR1, BT, 0, 4)

-FIELD(ID_AA64PFR1, SBSS, 4, 4)

+FIELD(ID_AA64PFR1, SSBS, 4, 4)

FIELD(ID_AA64PFR1, MTE, 8, 4)

FIELD(ID_AA64PFR1, RAS_FRAC, 12, 4)

2.20.1

From: Hao Wu <wuhaotsh@google.com>

This patch makes NPCM7XX Timer to use a the timer clock generated by the

CLK module instead of the magic number TIMER_REF_HZ.

Reviewed-by: Havard Skinnemoen <hskinnemoen@google.com>

Reviewed-by: Tyrone Ting <kfting@nuvoton.com>

Signed-off-by: Hao Wu <wuhaotsh@google.com>

Message-id: 20210108190945.949196-3-wuhaotsh@google.com

include/hw/misc/npcm7xx_clk.h | 6 -----

include/hw/timer/npcm7xx_timer.h | 1 +

hw/arm/npcm7xx.c | 5 ++++

hw/timer/npcm7xx_timer.c | 39 +++++++++++++++-----------------

4 files changed, 24 insertions(+), 27 deletions(-)

diff --git a/include/hw/misc/npcm7xx_clk.h b/include/hw/misc/npcm7xx_clk.h

--- a/include/hw/misc/npcm7xx_clk.h

+++ b/include/hw/misc/npcm7xx_clk.h

@@ -XXX,XX +XXX,XX @@

#include "hw/clock.h"

#include "hw/sysbus.h"

-/*

- * The reference clock frequency for the timer modules, and the SECCNT and

- * CNTR25M registers in this module, is always 25 MHz.

- */

-#define NPCM7XX_TIMER_REF_HZ (25000000)

-

/*

* Number of registers in our device state structure. Don't change this without

* incrementing the version_id in the vmstate.

diff --git a/include/hw/timer/npcm7xx_timer.h b/include/hw/timer/npcm7xx_timer.h

index XXXXXXX..XXXXXXX 100644

--- a/include/hw/timer/npcm7xx_timer.h

+++ b/include/hw/timer/npcm7xx_timer.h

@@ -XXX,XX +XXX,XX @@ struct NPCM7xxTimerCtrlState {

uint32_t tisr;

+ Clock *clock;

NPCM7xxTimer timer[NPCM7XX_TIMERS_PER_CTRL];

NPCM7xxWatchdogTimer watchdog_timer;

};

diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/arm/npcm7xx.c

+++ b/hw/arm/npcm7xx.c

@@ -XXX,XX +XXX,XX @@

#include "hw/char/serial.h"

#include "hw/loader.h"

#include "hw/misc/unimp.h"

+#include "hw/qdev-clock.h"

#include "hw/qdev-properties.h"

#include "qapi/error.h"

#include "qemu/units.h"

@@ -XXX,XX +XXX,XX @@ static void npcm7xx_realize(DeviceState *dev, Error **errp)

int first_irq;

int j;

+ /* Connect the timer clock. */

+ qdev_connect_clock_in(DEVICE(&s->tim[i]), "clock", qdev_get_clock_out(

+ DEVICE(&s->clk), "timer-clock"));

+

sysbus_realize(sbd, &error_abort);

sysbus_mmio_map(sbd, 0, npcm7xx_tim_addr[i]);

diff --git a/hw/timer/npcm7xx_timer.c b/hw/timer/npcm7xx_timer.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/timer/npcm7xx_timer.c

+++ b/hw/timer/npcm7xx_timer.c

@@ -XXX,XX +XXX,XX @@

#include "qemu/osdep.h"

#include "hw/irq.h"

+#include "hw/qdev-clock.h"

#include "hw/qdev-properties.h"

-#include "hw/misc/npcm7xx_clk.h"

#include "hw/timer/npcm7xx_timer.h"

#include "migration/vmstate.h"

#include "qemu/bitops.h"

@@ -XXX,XX +XXX,XX @@ static uint32_t npcm7xx_tcsr_prescaler(uint32_t tcsr)

/* Convert a timer cycle count to a time interval in nanoseconds. */

static int64_t npcm7xx_timer_count_to_ns(NPCM7xxTimer *t, uint32_t count)

{

- int64_t ns = count;

+ int64_t ticks = count;

- ns *= NANOSECONDS_PER_SECOND / NPCM7XX_TIMER_REF_HZ;

- ns *= npcm7xx_tcsr_prescaler(t->tcsr);

+ ticks *= npcm7xx_tcsr_prescaler(t->tcsr);

- return ns;

+ return clock_ticks_to_ns(t->ctrl->clock, ticks);

}

/* Convert a time interval in nanoseconds to a timer cycle count. */

static uint32_t npcm7xx_timer_ns_to_count(NPCM7xxTimer *t, int64_t ns)

{

- int64_t count;

-

- count = ns / (NANOSECONDS_PER_SECOND / NPCM7XX_TIMER_REF_HZ);

- count /= npcm7xx_tcsr_prescaler(t->tcsr);

-

- return count;

+ return ns / clock_ticks_to_ns(t->ctrl->clock,

+ npcm7xx_tcsr_prescaler(t->tcsr));

}

static uint32_t npcm7xx_watchdog_timer_prescaler(const NPCM7xxWatchdogTimer *t)

@@ -XXX,XX +XXX,XX @@ static uint32_t npcm7xx_watchdog_timer_prescaler(const NPCM7xxWatchdogTimer *t)

static void npcm7xx_watchdog_timer_reset_cycles(NPCM7xxWatchdogTimer *t,

int64_t cycles)

{

- uint32_t prescaler = npcm7xx_watchdog_timer_prescaler(t);

- int64_t ns = (NANOSECONDS_PER_SECOND / NPCM7XX_TIMER_REF_HZ) * cycles;

+ int64_t ticks = cycles * npcm7xx_watchdog_timer_prescaler(t);

+ int64_t ns = clock_ticks_to_ns(t->ctrl->clock, ticks);

/*

* The reset function always clears the current timer. The caller of the

@@ -XXX,XX +XXX,XX @@ static void npcm7xx_watchdog_timer_reset_cycles(NPCM7xxWatchdogTimer *t,

*/

npcm7xx_timer_clear(&t->base_timer);

- ns *= prescaler;

t->base_timer.remaining_ns = ns;

}

@@ -XXX,XX +XXX,XX @@ static void npcm7xx_timer_hold_reset(Object *obj)

qemu_irq_lower(s->watchdog_timer.irq);

}

-static void npcm7xx_timer_realize(DeviceState *dev, Error **errp)

+static void npcm7xx_timer_init(Object *obj)

{

- NPCM7xxTimerCtrlState *s = NPCM7XX_TIMER(dev);

- SysBusDevice *sbd = &s->parent;

+ NPCM7xxTimerCtrlState *s = NPCM7XX_TIMER(obj);

+ DeviceState *dev = DEVICE(obj);

+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);

int i;

NPCM7xxWatchdogTimer *w;

@@ -XXX,XX +XXX,XX @@ static void npcm7xx_timer_realize(DeviceState *dev, Error **errp)

npcm7xx_watchdog_timer_expired, w);

sysbus_init_irq(sbd, &w->irq);

- memory_region_init_io(&s->iomem, OBJECT(s), &npcm7xx_timer_ops, s,

+ memory_region_init_io(&s->iomem, obj, &npcm7xx_timer_ops, s,

TYPE_NPCM7XX_TIMER, 4 * KiB);

sysbus_init_mmio(sbd, &s->iomem);

qdev_init_gpio_out_named(dev, &w->reset_signal,

NPCM7XX_WATCHDOG_RESET_GPIO_OUT, 1);

+ s->clock = qdev_init_clock_in(dev, "clock", NULL, NULL);

}

static const VMStateDescription vmstate_npcm7xx_base_timer = {

@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_npcm7xx_watchdog_timer = {

static const VMStateDescription vmstate_npcm7xx_timer_ctrl = {

.name = "npcm7xx-timer-ctrl",

- .version_id = 1,

- .minimum_version_id = 1,

+ .version_id = 2,

+ .minimum_version_id = 2,

.fields = (VMStateField[]) {

VMSTATE_UINT32(tisr, NPCM7xxTimerCtrlState),

+ VMSTATE_CLOCK(clock, NPCM7xxTimerCtrlState),

VMSTATE_STRUCT_ARRAY(timer, NPCM7xxTimerCtrlState,

NPCM7XX_TIMERS_PER_CTRL, 0, vmstate_npcm7xx_timer,

NPCM7xxTimer),

@@ -XXX,XX +XXX,XX @@ static void npcm7xx_timer_class_init(ObjectClass *klass, void *data)

QEMU_BUILD_BUG_ON(NPCM7XX_TIMER_REGS_END > NPCM7XX_TIMER_NR_REGS);

dc->desc = "NPCM7xx Timer Controller";

- dc->realize = npcm7xx_timer_realize;

dc->vmsd = &vmstate_npcm7xx_timer_ctrl;

rc->phases.enter = npcm7xx_timer_enter_reset;

rc->phases.hold = npcm7xx_timer_hold_reset;

@@ -XXX,XX +XXX,XX @@ static const TypeInfo npcm7xx_timer_info = {

.parent = TYPE_SYS_BUS_DEVICE,

.instance_size = sizeof(NPCM7xxTimerCtrlState),

.class_init = npcm7xx_timer_class_init,

+ .instance_init = npcm7xx_timer_init,

};

static void npcm7xx_timer_register_type(void)

2.20.1

From: Hao Wu <wuhaotsh@google.com>

The PWM module is part of NPCM7XX module. Each NPCM7XX module has two

identical PWM modules. Each module contains 4 PWM entries. Each PWM has

two outputs: frequency and duty_cycle. Both are computed using inputs

from software side.

This module does not model detail pulse signals since it is expensive.

It also does not model interrupts and watchdogs that are dependant on

the detail models. The interfaces for these are left in the module so

that anyone in need for these functionalities can implement on their

own.

The user can read the duty cycle and frequency using qom-get command.

Reviewed-by: Havard Skinnemoen <hskinnemoen@google.com>

Reviewed-by: Tyrone Ting <kfting@nuvoton.com>

Signed-off-by: Hao Wu <wuhaotsh@google.com>

Message-id: 20210108190945.949196-5-wuhaotsh@google.com

docs/system/arm/nuvoton.rst | 2 +-

include/hw/arm/npcm7xx.h | 2 +

include/hw/misc/npcm7xx_pwm.h | 105 +++++++

hw/arm/npcm7xx.c | 26 +-

hw/misc/npcm7xx_pwm.c | 550 ++++++++++++++++++++++++++++++++++

hw/misc/meson.build | 1 +

hw/misc/trace-events | 6 +

7 files changed, 689 insertions(+), 3 deletions(-)

create mode 100644 include/hw/misc/npcm7xx_pwm.h

create mode 100644 hw/misc/npcm7xx_pwm.c

diff --git a/docs/system/arm/nuvoton.rst b/docs/system/arm/nuvoton.rst

--- a/docs/system/arm/nuvoton.rst

+++ b/docs/system/arm/nuvoton.rst

@@ -XXX,XX +XXX,XX @@ Supported devices

* USB host (USBH)

* GPIO controller

* Analog to Digital Converter (ADC)

+ * Pulse Width Modulation (PWM)

Missing devices

---------------

@@ -XXX,XX +XXX,XX @@ Missing devices

* Peripheral SPI controller (PSPI)

* SD/MMC host

* PECI interface

- * Pulse Width Modulation (PWM)

* Tachometer

* PCI and PCIe root complex and bridges

* VDM and MCTP support

diff --git a/include/hw/arm/npcm7xx.h b/include/hw/arm/npcm7xx.h

index XXXXXXX..XXXXXXX 100644

--- a/include/hw/arm/npcm7xx.h

+++ b/include/hw/arm/npcm7xx.h

@@ -XXX,XX +XXX,XX @@

#include "hw/mem/npcm7xx_mc.h"

#include "hw/misc/npcm7xx_clk.h"

#include "hw/misc/npcm7xx_gcr.h"

+#include "hw/misc/npcm7xx_pwm.h"

#include "hw/misc/npcm7xx_rng.h"

#include "hw/nvram/npcm7xx_otp.h"

#include "hw/timer/npcm7xx_timer.h"

@@ -XXX,XX +XXX,XX @@ typedef struct NPCM7xxState {

NPCM7xxCLKState clk;

NPCM7xxTimerCtrlState tim[3];

NPCM7xxADCState adc;

+ NPCM7xxPWMState pwm[2];

NPCM7xxOTPState key_storage;

NPCM7xxOTPState fuse_array;

NPCM7xxMCState mc;

diff --git a/include/hw/misc/npcm7xx_pwm.h b/include/hw/misc/npcm7xx_pwm.h

new file mode 100644

index XXXXXXX..XXXXXXX

--- /dev/null

+++ b/include/hw/misc/npcm7xx_pwm.h

@@ -XXX,XX +XXX,XX @@

+/*

+ * Nuvoton NPCM7xx PWM Module

+ *

+ * Copyright 2020 Google LLC

+ *

+ * This program is free software; you can redistribute it and/or modify it

+ * under the terms of the GNU General Public License as published by the

+ * Free Software Foundation; either version 2 of the License, or

+ * (at your option) any later version.

+ *

+ * This program is distributed in the hope that it will be useful, but WITHOUT

+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License

+ * for more details.

+ */

+#ifndef NPCM7XX_PWM_H

+#define NPCM7XX_PWM_H

+

+#include "hw/clock.h"

+#include "hw/sysbus.h"

+#include "hw/irq.h"

+

+/* Each PWM module holds 4 PWM channels. */

+#define NPCM7XX_PWM_PER_MODULE 4

+

+/*

+ * Number of registers in one pwm module. Don't change this without increasing

+ * the version_id in vmstate.

+ */

+#define NPCM7XX_PWM_NR_REGS (0x54 / sizeof(uint32_t))

+

+/*

+ * The maximum duty values. Each duty unit represents 1/NPCM7XX_PWM_MAX_DUTY

+ * cycles. For example, if NPCM7XX_PWM_MAX_DUTY=1,000,000 and a PWM has a duty

+ * value of 100,000 the duty cycle for that PWM is 10%.

+ */

+#define NPCM7XX_PWM_MAX_DUTY 1000000

+

+typedef struct NPCM7xxPWMState NPCM7xxPWMState;

+

+/**

+ * struct NPCM7xxPWM - The state of a single PWM channel.

+ * @module: The PWM module that contains this channel.

+ * @irq: GIC interrupt line to fire on expiration if enabled.

+ * @running: Whether this PWM channel is generating output.

+ * @inverted: Whether this PWM channel is inverted.

+ * @index: The index of this PWM channel.

+ * @cnr: The counter register.

+ * @cmr: The comparator register.

+ * @pdr: The data register.

+ * @pwdr: The watchdog register.

+ * @freq: The frequency of this PWM channel.

+ * @duty: The duty cycle of this PWM channel. One unit represents

+ * 1/NPCM7XX_MAX_DUTY cycles.

+ */

+typedef struct NPCM7xxPWM {

+ NPCM7xxPWMState *module;

+

+ qemu_irq irq;

+

+ bool running;

+ bool inverted;

+

+ uint8_t index;

+ uint32_t cnr;

+ uint32_t cmr;

+ uint32_t pdr;

+ uint32_t pwdr;

+

+ uint32_t freq;

+ uint32_t duty;

+} NPCM7xxPWM;

+

+/**

+ * struct NPCM7xxPWMState - Pulse Width Modulation device state.

+ * @parent: System bus device.

+ * @iomem: Memory region through which registers are accessed.

+ * @clock: The PWM clock.

+ * @pwm: The PWM channels owned by this module.

+ * @ppr: The prescaler register.

+ * @csr: The clock selector register.

+ * @pcr: The control register.

+ * @pier: The interrupt enable register.

+ * @piir: The interrupt indication register.

+ */

+struct NPCM7xxPWMState {

+ SysBusDevice parent;

+

+ MemoryRegion iomem;

+

+ Clock *clock;

+ NPCM7xxPWM pwm[NPCM7XX_PWM_PER_MODULE];

+

+ uint32_t ppr;

+ uint32_t csr;

+ uint32_t pcr;

+ uint32_t pier;

+ uint32_t piir;

+};

+

+#define TYPE_NPCM7XX_PWM "npcm7xx-pwm"

+#define NPCM7XX_PWM(obj) \

+ OBJECT_CHECK(NPCM7xxPWMState, (obj), TYPE_NPCM7XX_PWM)

+

+#endif /* NPCM7XX_PWM_H */

diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/arm/npcm7xx.c

+++ b/hw/arm/npcm7xx.c

@@ -XXX,XX +XXX,XX @@ enum NPCM7xxInterrupt {

NPCM7XX_WDG2_IRQ, /* Timer Module 2 Watchdog */

NPCM7XX_EHCI_IRQ = 61,

NPCM7XX_OHCI_IRQ = 62,

+ NPCM7XX_PWM0_IRQ = 93, /* PWM module 0 */

+ NPCM7XX_PWM1_IRQ, /* PWM module 1 */

NPCM7XX_GPIO0_IRQ = 116,

NPCM7XX_GPIO1_IRQ,

NPCM7XX_GPIO2_IRQ,

@@ -XXX,XX +XXX,XX @@ static const hwaddr npcm7xx_fiu3_flash_addr[] = {

0xb8000000, /* CS3 */

};

+/* Register base address for each PWM Module */

+static const hwaddr npcm7xx_pwm_addr[] = {

+ 0xf0103000,

+ 0xf0104000,

+};

+

static const struct {

hwaddr regs_addr;

uint32_t unconnected_pins;

@@ -XXX,XX +XXX,XX @@ static void npcm7xx_init(Object *obj)

object_initialize_child(obj, npcm7xx_fiu[i].name, &s->fiu[i],

TYPE_NPCM7XX_FIU);

+ for (i = 0; i < ARRAY_SIZE(s->pwm); i++) {

+ object_initialize_child(obj, "pwm[*]", &s->pwm[i], TYPE_NPCM7XX_PWM);

static void npcm7xx_realize(DeviceState *dev, Error **errp)

@@ -XXX,XX +XXX,XX @@ static void npcm7xx_realize(DeviceState *dev, Error **errp)

sysbus_connect_irq(SYS_BUS_DEVICE(&s->ohci), 0,

npcm7xx_irq(s, NPCM7XX_OHCI_IRQ));

+ /* PWM Modules. Cannot fail. */

+ QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_pwm_addr) != ARRAY_SIZE(s->pwm));

+ for (i = 0; i < ARRAY_SIZE(s->pwm); i++) {

+ SysBusDevice *sbd = SYS_BUS_DEVICE(&s->pwm[i]);

+

+ qdev_connect_clock_in(DEVICE(&s->pwm[i]), "clock", qdev_get_clock_out(

+ DEVICE(&s->clk), "apb3-clock"));

+ sysbus_realize(sbd, &error_abort);

+ sysbus_mmio_map(sbd, 0, npcm7xx_pwm_addr[i]);

+ sysbus_connect_irq(sbd, i, npcm7xx_irq(s, NPCM7XX_PWM0_IRQ + i));

+ }

+

/*

* Flash Interface Unit (FIU). Can fail if incorrect number of chip selects

* specified, but this is a programming error.

@@ -XXX,XX +XXX,XX @@ static void npcm7xx_realize(DeviceState *dev, Error **errp)

create_unimplemented_device("npcm7xx.peci", 0xf0100000, 4 * KiB);

create_unimplemented_device("npcm7xx.siox[1]", 0xf0101000, 4 * KiB);

create_unimplemented_device("npcm7xx.siox[2]", 0xf0102000, 4 * KiB);

- create_unimplemented_device("npcm7xx.pwm[0]", 0xf0103000, 4 * KiB);

- create_unimplemented_device("npcm7xx.pwm[1]", 0xf0104000, 4 * KiB);

create_unimplemented_device("npcm7xx.mft[0]", 0xf0180000, 4 * KiB);

create_unimplemented_device("npcm7xx.mft[1]", 0xf0181000, 4 * KiB);

create_unimplemented_device("npcm7xx.mft[2]", 0xf0182000, 4 * KiB);

diff --git a/hw/misc/npcm7xx_pwm.c b/hw/misc/npcm7xx_pwm.c

new file mode 100644

index XXXXXXX..XXXXXXX

--- /dev/null

+++ b/hw/misc/npcm7xx_pwm.c

@@ -XXX,XX +XXX,XX @@

+/*

+ * Nuvoton NPCM7xx PWM Module

+ *

+ * Copyright 2020 Google LLC

+ *

+ * This program is free software; you can redistribute it and/or modify it

+ * under the terms of the GNU General Public License as published by the

+ * Free Software Foundation; either version 2 of the License, or

+ * (at your option) any later version.

+ *

+ * This program is distributed in the hope that it will be useful, but WITHOUT

+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License

+ * for more details.

+ */

+

+#include "qemu/osdep.h"

+#include "hw/irq.h"

+#include "hw/qdev-clock.h"

+#include "hw/qdev-properties.h"

+#include "hw/misc/npcm7xx_pwm.h"

+#include "hw/registerfields.h"

+#include "migration/vmstate.h"

+#include "qemu/bitops.h"

+#include "qemu/error-report.h"

+#include "qemu/log.h"

+#include "qemu/module.h"

+#include "qemu/units.h"

+#include "trace.h"

+

+REG32(NPCM7XX_PWM_PPR, 0x00);

+REG32(NPCM7XX_PWM_CSR, 0x04);

+REG32(NPCM7XX_PWM_PCR, 0x08);

+REG32(NPCM7XX_PWM_CNR0, 0x0c);

+REG32(NPCM7XX_PWM_CMR0, 0x10);

+REG32(NPCM7XX_PWM_PDR0, 0x14);

+REG32(NPCM7XX_PWM_CNR1, 0x18);

+REG32(NPCM7XX_PWM_CMR1, 0x1c);

+REG32(NPCM7XX_PWM_PDR1, 0x20);

+REG32(NPCM7XX_PWM_CNR2, 0x24);

+REG32(NPCM7XX_PWM_CMR2, 0x28);

+REG32(NPCM7XX_PWM_PDR2, 0x2c);

+REG32(NPCM7XX_PWM_CNR3, 0x30);

+REG32(NPCM7XX_PWM_CMR3, 0x34);

+REG32(NPCM7XX_PWM_PDR3, 0x38);

+REG32(NPCM7XX_PWM_PIER, 0x3c);

+REG32(NPCM7XX_PWM_PIIR, 0x40);

+REG32(NPCM7XX_PWM_PWDR0, 0x44);

+REG32(NPCM7XX_PWM_PWDR1, 0x48);

+REG32(NPCM7XX_PWM_PWDR2, 0x4c);

+REG32(NPCM7XX_PWM_PWDR3, 0x50);

+

+/* Register field definitions. */

+#define NPCM7XX_PPR(rv, index) extract32((rv), npcm7xx_ppr_base[index], 8)

+#define NPCM7XX_CSR(rv, index) extract32((rv), npcm7xx_csr_base[index], 3)

+#define NPCM7XX_CH(rv, index) extract32((rv), npcm7xx_ch_base[index], 4)

+#define NPCM7XX_CH_EN BIT(0)

+#define NPCM7XX_CH_INV BIT(2)

+#define NPCM7XX_CH_MOD BIT(3)

+

+/* Offset of each PWM channel's prescaler in the PPR register. */

+static const int npcm7xx_ppr_base[] = { 0, 0, 8, 8 };

+/* Offset of each PWM channel's clock selector in the CSR register. */

+static const int npcm7xx_csr_base[] = { 0, 4, 8, 12 };

+/* Offset of each PWM channel's control variable in the PCR register. */

+static const int npcm7xx_ch_base[] = { 0, 8, 12, 16 };

+

+static uint32_t npcm7xx_pwm_calculate_freq(NPCM7xxPWM *p)

+{

+ uint32_t ppr;

+ uint32_t csr;

+ uint32_t freq;

+

+ if (!p->running) {

+ return 0;

+ }

+

+ csr = NPCM7XX_CSR(p->module->csr, p->index);

+ ppr = NPCM7XX_PPR(p->module->ppr, p->index);

+ freq = clock_get_hz(p->module->clock);

+ freq /= ppr + 1;

+ /* csr can only be 0~4 */

+ if (csr > 4) {

+ qemu_log_mask(LOG_GUEST_ERROR,

+ "%s: invalid csr value %u\n",

+ __func__, csr);

+ csr = 4;

+ }

+ /* freq won't be changed if csr == 4. */

+ if (csr < 4) {

+ freq >>= csr + 1;

+ }

+

+ return freq / (p->cnr + 1);

+}

+

+static uint32_t npcm7xx_pwm_calculate_duty(NPCM7xxPWM *p)

+{

+ uint64_t duty;

+

+ if (p->running) {

+ if (p->cnr == 0) {

+ duty = 0;

+ } else if (p->cmr >= p->cnr) {

+ duty = NPCM7XX_PWM_MAX_DUTY;

+ } else {

+ duty = NPCM7XX_PWM_MAX_DUTY * (p->cmr + 1) / (p->cnr + 1);

+ }

+ } else {

+ duty = 0;

+ }

+

+ if (p->inverted) {

+ duty = NPCM7XX_PWM_MAX_DUTY - duty;

+ }

+

+ return duty;

+}

+

+static void npcm7xx_pwm_update_freq(NPCM7xxPWM *p)

+{

+ uint32_t freq = npcm7xx_pwm_calculate_freq(p);

+

+ if (freq != p->freq) {

+ trace_npcm7xx_pwm_update_freq(DEVICE(p->module)->canonical_path,

+ p->index, p->freq, freq);

+ p->freq = freq;

+ }

+}

+

+static void npcm7xx_pwm_update_duty(NPCM7xxPWM *p)

+{

+ uint32_t duty = npcm7xx_pwm_calculate_duty(p);

+

+ if (duty != p->duty) {

+ trace_npcm7xx_pwm_update_duty(DEVICE(p->module)->canonical_path,

+ p->index, p->duty, duty);

+ p->duty = duty;

+ }

+}

+

+static void npcm7xx_pwm_update_output(NPCM7xxPWM *p)

+{

+ npcm7xx_pwm_update_freq(p);

+ npcm7xx_pwm_update_duty(p);

+}

+

+static void npcm7xx_pwm_write_ppr(NPCM7xxPWMState *s, uint32_t new_ppr)

+{

+ int i;

+ uint32_t old_ppr = s->ppr;

+

+ QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_ppr_base) != NPCM7XX_PWM_PER_MODULE);

+ s->ppr = new_ppr;

+ for (i = 0; i < NPCM7XX_PWM_PER_MODULE; ++i) {

+ if (NPCM7XX_PPR(old_ppr, i) != NPCM7XX_PPR(new_ppr, i)) {

+ npcm7xx_pwm_update_freq(&s->pwm[i]);

+ }

+ }

+}

+

+static void npcm7xx_pwm_write_csr(NPCM7xxPWMState *s, uint32_t new_csr)

+{

+ int i;

+ uint32_t old_csr = s->csr;

+

+ QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_csr_base) != NPCM7XX_PWM_PER_MODULE);

+ s->csr = new_csr;

+ for (i = 0; i < NPCM7XX_PWM_PER_MODULE; ++i) {

+ if (NPCM7XX_CSR(old_csr, i) != NPCM7XX_CSR(new_csr, i)) {

+ npcm7xx_pwm_update_freq(&s->pwm[i]);

+ }

+ }

+}

+

+static void npcm7xx_pwm_write_pcr(NPCM7xxPWMState *s, uint32_t new_pcr)

+{

+ int i;

+ bool inverted;

+ uint32_t pcr;

+ NPCM7xxPWM *p;

+

+ s->pcr = new_pcr;

+ QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_ch_base) != NPCM7XX_PWM_PER_MODULE);

+ for (i = 0; i < NPCM7XX_PWM_PER_MODULE; ++i) {

+ p = &s->pwm[i];

+ pcr = NPCM7XX_CH(new_pcr, i);

+ inverted = pcr & NPCM7XX_CH_INV;

+

+ /*

+ * We only run a PWM channel with toggle mode. Single-shot mode does not

+ * generate frequency and duty-cycle values.

+ */

+ if ((pcr & NPCM7XX_CH_EN) && (pcr & NPCM7XX_CH_MOD)) {

+ if (p->running) {

+ /* Re-run this PWM channel if inverted changed. */

+ if (p->inverted ^ inverted) {

+ p->inverted = inverted;

+ npcm7xx_pwm_update_duty(p);

+ }

+ } else {

+ /* Run this PWM channel. */

+ p->running = true;

+ p->inverted = inverted;

+ npcm7xx_pwm_update_output(p);

+ }

+ } else {

+ /* Clear this PWM channel. */

+ p->running = false;

+ p->inverted = inverted;

+ npcm7xx_pwm_update_output(p);

+ }

+ }

+

+}

+

+static hwaddr npcm7xx_cnr_index(hwaddr offset)

+{

+ switch (offset) {

+ case A_NPCM7XX_PWM_CNR0:

+ return 0;

+ case A_NPCM7XX_PWM_CNR1:

+ return 1;

+ case A_NPCM7XX_PWM_CNR2:

+ return 2;

+ case A_NPCM7XX_PWM_CNR3:

+ return 3;

+ default:

+ g_assert_not_reached();

+ }

+}

+

+static hwaddr npcm7xx_cmr_index(hwaddr offset)

+{

+ switch (offset) {

+ case A_NPCM7XX_PWM_CMR0:

+ return 0;

+ case A_NPCM7XX_PWM_CMR1:

+ return 1;

+ case A_NPCM7XX_PWM_CMR2:

+ return 2;

+ case A_NPCM7XX_PWM_CMR3:

+ return 3;

+ default:

+ g_assert_not_reached();

+ }

+}

+

+static hwaddr npcm7xx_pdr_index(hwaddr offset)

+{

+ switch (offset) {

+ case A_NPCM7XX_PWM_PDR0:

+ return 0;

+ case A_NPCM7XX_PWM_PDR1:

+ return 1;

+ case A_NPCM7XX_PWM_PDR2:

+ return 2;

+ case A_NPCM7XX_PWM_PDR3:

+ return 3;

+ default:

+ g_assert_not_reached();

+ }

+}

+

+static hwaddr npcm7xx_pwdr_index(hwaddr offset)

+{

+ switch (offset) {

+ case A_NPCM7XX_PWM_PWDR0:

+ return 0;

+ case A_NPCM7XX_PWM_PWDR1:

+ return 1;

+ case A_NPCM7XX_PWM_PWDR2:

+ return 2;

+ case A_NPCM7XX_PWM_PWDR3:

+ return 3;

+ default:

+ g_assert_not_reached();

+ }

+}

+

+static uint64_t npcm7xx_pwm_read(void *opaque, hwaddr offset, unsigned size)

+{

+ NPCM7xxPWMState *s = opaque;

+ uint64_t value = 0;

+

+ switch (offset) {

+ case A_NPCM7XX_PWM_CNR0:

+ case A_NPCM7XX_PWM_CNR1:

+ case A_NPCM7XX_PWM_CNR2:

+ case A_NPCM7XX_PWM_CNR3:

+ value = s->pwm[npcm7xx_cnr_index(offset)].cnr;

+ break;

+

+ case A_NPCM7XX_PWM_CMR0:

+ case A_NPCM7XX_PWM_CMR1:

+ case A_NPCM7XX_PWM_CMR2:

+ case A_NPCM7XX_PWM_CMR3:

+ value = s->pwm[npcm7xx_cmr_index(offset)].cmr;

+ break;

+

+ case A_NPCM7XX_PWM_PDR0:

+ case A_NPCM7XX_PWM_PDR1:

+ case A_NPCM7XX_PWM_PDR2:

+ case A_NPCM7XX_PWM_PDR3:

+ value = s->pwm[npcm7xx_pdr_index(offset)].pdr;

+ break;

+

+ case A_NPCM7XX_PWM_PWDR0:

+ case A_NPCM7XX_PWM_PWDR1:

+ case A_NPCM7XX_PWM_PWDR2:

+ case A_NPCM7XX_PWM_PWDR3:

+ value = s->pwm[npcm7xx_pwdr_index(offset)].pwdr;

+ break;

+

+ case A_NPCM7XX_PWM_PPR:

+ value = s->ppr;

+ break;

+

+ case A_NPCM7XX_PWM_CSR:

+ value = s->csr;

+ break;

+

+ case A_NPCM7XX_PWM_PCR:

+ value = s->pcr;

+ break;

+

+ case A_NPCM7XX_PWM_PIER:

+ value = s->pier;

+ break;

+

+ case A_NPCM7XX_PWM_PIIR:

+ value = s->piir;

+ break;

+

+ default:

+ qemu_log_mask(LOG_GUEST_ERROR,

+ "%s: invalid offset 0x%04" HWADDR_PRIx "\n",

+ __func__, offset);

+ break;

+ }

+

+ trace_npcm7xx_pwm_read(DEVICE(s)->canonical_path, offset, value);

+ return value;

+}

+

+static void npcm7xx_pwm_write(void *opaque, hwaddr offset,

+ uint64_t v, unsigned size)

+{

+ NPCM7xxPWMState *s = opaque;

+ NPCM7xxPWM *p;

+ uint32_t value = v;

+

+ trace_npcm7xx_pwm_write(DEVICE(s)->canonical_path, offset, value);

+ switch (offset) {

+ case A_NPCM7XX_PWM_CNR0:

+ case A_NPCM7XX_PWM_CNR1:

+ case A_NPCM7XX_PWM_CNR2:

+ case A_NPCM7XX_PWM_CNR3:

+ p = &s->pwm[npcm7xx_cnr_index(offset)];

+ p->cnr = value;

+ npcm7xx_pwm_update_output(p);

+ break;

+

+ case A_NPCM7XX_PWM_CMR0:

+ case A_NPCM7XX_PWM_CMR1:

+ case A_NPCM7XX_PWM_CMR2:

+ case A_NPCM7XX_PWM_CMR3:

+ p = &s->pwm[npcm7xx_cmr_index(offset)];

+ p->cmr = value;

+ npcm7xx_pwm_update_output(p);

+ break;

+

+ case A_NPCM7XX_PWM_PDR0:

+ case A_NPCM7XX_PWM_PDR1:

+ case A_NPCM7XX_PWM_PDR2:

+ case A_NPCM7XX_PWM_PDR3:

+ qemu_log_mask(LOG_GUEST_ERROR,

+ "%s: register @ 0x%04" HWADDR_PRIx " is read-only\n",

+ __func__, offset);

+ break;

+

+ case A_NPCM7XX_PWM_PWDR0:

+ case A_NPCM7XX_PWM_PWDR1:

+ case A_NPCM7XX_PWM_PWDR2:

+ case A_NPCM7XX_PWM_PWDR3:

+ qemu_log_mask(LOG_UNIMP,