[PULL 00/21] target-arm queue
[PULL 00/21] target-arm queue
1
Arm queue; not huge but I figured I might as well send it out since
1
Hi; here's the latest batch of arm changes. The big thing
2
I've been doing code review today and there's no queue of unprocessed
2
in here is the SMMUv3 changes to add stage-2 translation support.
3
pullreqs...
4
3
5
thanks
4
thanks
6
-- PMM
5
-- PMM
7
6
8
The following changes since commit b3f846c59d8405bb87c551187721fc92ff2f1b92:
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The following changes since commit aa9bbd865502ed517624ab6fe7d4b5d89ca95e43:
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8
10
Merge remote-tracking branch 'remotes/huth-gitlab/tags/pull-request-2021-01-11v2' into staging (2021-01-11 15:15:35 +0000)
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Merge tag 'pull-ppc-20230528' of https://gitlab.com/danielhb/qemu into staging (2023-05-29 14:31:52 -0700)
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10
12
are available in the Git repository at:
11
are available in the Git repository at:
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12
14
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210112
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230530
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14
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for you to fetch changes up to 19d131395ccaf503db21dadd8257e6dc9fc1d7de:
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for you to fetch changes up to b03d0d4f531a8b867e0aac1fab0b876903015680:
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16
18
ui/cocoa: Fix openFile: deprecation on Big Sur (2021-01-12 11:38:37 +0000)
17
docs: sbsa: correct graphics card name (2023-05-30 13:32:46 +0100)
19
18
20
----------------------------------------------------------------
19
----------------------------------------------------------------
21
target-arm queue:
20
target-arm queue:
22
* arm: Support emulation of ARMv8.4-TTST extension
21
* fsl-imx6: Add SNVS support for i.MX6 boards
23
* arm: Update cpu.h ID register field definitions
22
* smmuv3: Add support for stage 2 translations
24
* arm: Fix breakage of XScale instruction emulation
23
* hw/dma/xilinx_axidma: Check DMASR.HALTED to prevent infinite loop
25
* hw/net/lan9118: Fix RX Status FIFO PEEK value
24
* hw/arm/xlnx-zynqmp: fix unsigned error when checking the RPUs number
26
* npcm7xx: Add ADC and PWM emulation
25
* cleanups for recent Kconfig changes
27
* ui/cocoa: Make "open docs" help menu entry work again when binary
26
* target/arm: Explicitly select short-format FSR for M-profile
28
is run from the build tree
27
* tests/qtest: Run arm-specific tests only if the required machine is available
29
* ui/cocoa: Fix openFile: deprecation on Big Sur
28
* hw/arm/sbsa-ref: add GIC node into DT
30
* docs: Add qemu-storage-daemon(1) manpage to meson.build
29
* docs: sbsa: correct graphics card name
31
* docs: Build and install all the docs in a single manual
30
* Update copyright dates to 2023
32
31
33
----------------------------------------------------------------
32
----------------------------------------------------------------
34
Hao Wu (6):
33
Clément Chigot (1):
35
hw/misc: Add clock converter in NPCM7XX CLK module
34
hw/arm/xlnx-zynqmp: fix unsigned error when checking the RPUs number
36
hw/timer: Refactor NPCM7XX Timer to use CLK clock
37
hw/adc: Add an ADC module for NPCM7XX
38
hw/misc: Add a PWM module for NPCM7XX
39
hw/misc: Add QTest for NPCM7XX PWM Module
40
hw/*: Use type casting for SysBusDevice in NPCM7XX
41
35
42
Leif Lindholm (6):
36
Enze Li (1):
43
target/arm: fix typo in cpu.h ID_AA64PFR1 field name
37
Update copyright dates to 2023
44
target/arm: make ARMCPU.clidr 64-bit
45
target/arm: make ARMCPU.ctr 64-bit
46
target/arm: add descriptions of CLIDR_EL1, CCSIDR_EL1, CTR_EL0 to cpu.h
47
target/arm: add aarch64 ID register fields to cpu.h
48
target/arm: add aarch32 ID register fields to cpu.h
49
38
50
Peter Maydell (5):
39
Fabiano Rosas (3):
51
docs: Add qemu-storage-daemon(1) manpage to meson.build
40
target/arm: Explain why we need to select ARM_V7M
52
docs: Build and install all the docs in a single manual
41
arm/Kconfig: Keep Kconfig default entries in default.mak as documentation
53
target/arm: Don't decode insns in the XScale/iWMMXt space as cp insns
42
arm/Kconfig: Make TCG dependence explicit
54
hw/net/lan9118: Fix RX Status FIFO PEEK value
55
hw/net/lan9118: Add symbolic constants for register offsets
56
43
57
Roman Bolshakov (2):
44
Marcin Juszkiewicz (2):
58
ui/cocoa: Update path to docs in build tree
45
hw/arm/sbsa-ref: add GIC node into DT
59
ui/cocoa: Fix openFile: deprecation on Big Sur
46
docs: sbsa: correct graphics card name
60
47
61
Rémi Denis-Courmont (2):
48
Mostafa Saleh (10):
62
target/arm: ARMv8.4-TTST extension
49
hw/arm/smmuv3: Add missing fields for IDR0
63
target/arm: enable Small Translation tables in max CPU
50
hw/arm/smmuv3: Update translation config to hold stage-2
51
hw/arm/smmuv3: Refactor stage-1 PTW
52
hw/arm/smmuv3: Add page table walk for stage-2
53
hw/arm/smmuv3: Parse STE config for stage-2
54
hw/arm/smmuv3: Make TLB lookup work for stage-2
55
hw/arm/smmuv3: Add VMID to TLB tagging
56
hw/arm/smmuv3: Add CMDs related to stage-2
57
hw/arm/smmuv3: Add stage-2 support in iova notifier
58
hw/arm/smmuv3: Add knob to choose translation stage and enable stage-2
64
59
65
docs/conf.py | 46 ++-
60
Peter Maydell (1):
66
docs/devel/conf.py | 15 -
61
target/arm: Explicitly select short-format FSR for M-profile
67
docs/index.html.in | 17 -
68
docs/interop/conf.py | 28 --
69
docs/meson.build | 65 ++--
70
docs/specs/conf.py | 16 -
71
docs/system/arm/nuvoton.rst | 4 +-
72
docs/system/conf.py | 28 --
73
docs/tools/conf.py | 37 --
74
docs/user/conf.py | 15 -
75
meson.build | 1 +
76
hw/adc/trace.h | 1 +
77
include/hw/adc/npcm7xx_adc.h | 69 ++++
78
include/hw/arm/npcm7xx.h | 4 +
79
include/hw/misc/npcm7xx_clk.h | 146 ++++++-
80
include/hw/misc/npcm7xx_pwm.h | 105 +++++
81
include/hw/timer/npcm7xx_timer.h | 1 +
82
target/arm/cpu.h | 85 ++++-
83
hw/adc/npcm7xx_adc.c | 301 +++++++++++++++
84
hw/arm/npcm7xx.c | 55 ++-
85
hw/arm/npcm7xx_boards.c | 2 +-
86
hw/mem/npcm7xx_mc.c | 2 +-
87
hw/misc/npcm7xx_clk.c | 807 ++++++++++++++++++++++++++++++++++++++-
88
hw/misc/npcm7xx_gcr.c | 2 +-
89
hw/misc/npcm7xx_pwm.c | 550 ++++++++++++++++++++++++++
90
hw/misc/npcm7xx_rng.c | 2 +-
91
hw/net/lan9118.c | 26 +-
92
hw/nvram/npcm7xx_otp.c | 2 +-
93
hw/ssi/npcm7xx_fiu.c | 2 +-
94
hw/timer/npcm7xx_timer.c | 39 +-
95
target/arm/cpu64.c | 1 +
96
target/arm/helper.c | 15 +-
97
target/arm/translate.c | 7 +
98
tests/qtest/npcm7xx_adc-test.c | 377 ++++++++++++++++++
99
tests/qtest/npcm7xx_pwm-test.c | 490 ++++++++++++++++++++++++
100
hw/adc/meson.build | 1 +
101
hw/adc/trace-events | 5 +
102
hw/misc/meson.build | 1 +
103
hw/misc/trace-events | 6 +
104
tests/qtest/meson.build | 4 +-
105
ui/cocoa.m | 7 +-
106
41 files changed, 3124 insertions(+), 263 deletions(-)
107
delete mode 100644 docs/devel/conf.py
108
delete mode 100644 docs/index.html.in
109
delete mode 100644 docs/interop/conf.py
110
delete mode 100644 docs/specs/conf.py
111
delete mode 100644 docs/system/conf.py
112
delete mode 100644 docs/tools/conf.py
113
delete mode 100644 docs/user/conf.py
114
create mode 100644 hw/adc/trace.h
115
create mode 100644 include/hw/adc/npcm7xx_adc.h
116
create mode 100644 include/hw/misc/npcm7xx_pwm.h
117
create mode 100644 hw/adc/npcm7xx_adc.c
118
create mode 100644 hw/misc/npcm7xx_pwm.c
119
create mode 100644 tests/qtest/npcm7xx_adc-test.c
120
create mode 100644 tests/qtest/npcm7xx_pwm-test.c
121
create mode 100644 hw/adc/trace-events
122
62
63
Thomas Huth (1):
64
tests/qtest: Run arm-specific tests only if the required machine is available
65
66
Tommy Wu (1):
67
hw/dma/xilinx_axidma: Check DMASR.HALTED to prevent infinite loop.
68
69
Vitaly Cheptsov (1):
70
fsl-imx6: Add SNVS support for i.MX6 boards
71
72
docs/conf.py | 2 +-
73
docs/system/arm/sbsa.rst | 2 +-
74
configs/devices/aarch64-softmmu/default.mak | 6 +
75
configs/devices/arm-softmmu/default.mak | 40 ++++
76
hw/arm/smmu-internal.h | 37 +++
77
hw/arm/smmuv3-internal.h | 12 +-
78
include/hw/arm/fsl-imx6.h | 2 +
79
include/hw/arm/smmu-common.h | 45 +++-
80
include/hw/arm/smmuv3.h | 4 +
81
include/qemu/help-texts.h | 2 +-
82
hw/arm/fsl-imx6.c | 8 +
83
hw/arm/sbsa-ref.c | 19 +-
84
hw/arm/smmu-common.c | 209 ++++++++++++++--
85
hw/arm/smmuv3.c | 357 ++++++++++++++++++++++++----
86
hw/arm/xlnx-zynqmp.c | 2 +-
87
hw/dma/xilinx_axidma.c | 11 +-
88
target/arm/tcg/tlb_helper.c | 13 +-
89
hw/arm/Kconfig | 123 ++++++----
90
hw/arm/trace-events | 14 +-
91
target/arm/Kconfig | 3 +
92
tests/qtest/meson.build | 7 +-
93
21 files changed, 773 insertions(+), 145 deletions(-)
94
diff view generated by jsdifflib
[PULL 13/21] hw/net/lan9118: Fix RX Status FIFO PEEK value
[PULL 01/21] fsl-imx6: Add SNVS support for i.MX6 boards
1
A copy-and-paste error meant that the return value for register offset 0x44
1
From: Vitaly Cheptsov <cheptsov@ispras.ru>
2
(the RX Status FIFO PEEK register) returned a byte from a bogus offset in
3
the rx status FIFO. Fix the typo.
4
2
5
Cc: qemu-stable@nongnu.org
3
SNVS is supported on both i.MX6 and i.MX6UL and is needed
6
Fixes: https://bugs.launchpad.net/qemu/+bug/1904954
4
to support shutdown on the board.
5
6
Cc: Peter Maydell <peter.maydell@linaro.org> (odd fixer:SABRELITE / i.MX6)
7
Cc: Jean-Christophe Dubois <jcd@tribudubois.net> (reviewer:SABRELITE / i.MX6)
8
Cc: qemu-arm@nongnu.org (open list:SABRELITE / i.MX6)
9
Cc: qemu-devel@nongnu.org (open list:All patches CC here)
10
Signed-off-by: Vitaly Cheptsov <cheptsov@ispras.ru>
11
Message-id: 20230515095015.66860-1-cheptsov@ispras.ru
12
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
Message-id: 20210108180401.2263-2-peter.maydell@linaro.org
10
---
14
---
11
hw/net/lan9118.c | 2 +-
15
include/hw/arm/fsl-imx6.h | 2 ++
12
1 file changed, 1 insertion(+), 1 deletion(-)
16
hw/arm/fsl-imx6.c | 8 ++++++++
17
2 files changed, 10 insertions(+)
13
18
14
diff --git a/hw/net/lan9118.c b/hw/net/lan9118.c
19
diff --git a/include/hw/arm/fsl-imx6.h b/include/hw/arm/fsl-imx6.h
15
index XXXXXXX..XXXXXXX 100644
20
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/net/lan9118.c
21
--- a/include/hw/arm/fsl-imx6.h
17
+++ b/hw/net/lan9118.c
22
+++ b/include/hw/arm/fsl-imx6.h
18
@@ -XXX,XX +XXX,XX @@ static uint64_t lan9118_readl(void *opaque, hwaddr offset,
23
@@ -XXX,XX +XXX,XX @@
19
case 0x40:
24
#include "hw/cpu/a9mpcore.h"
20
return rx_status_fifo_pop(s);
25
#include "hw/misc/imx6_ccm.h"
21
case 0x44:
26
#include "hw/misc/imx6_src.h"
22
- return s->rx_status_fifo[s->tx_status_fifo_head];
27
+#include "hw/misc/imx7_snvs.h"
23
+ return s->rx_status_fifo[s->rx_status_fifo_head];
28
#include "hw/watchdog/wdt_imx2.h"
24
case 0x48:
29
#include "hw/char/imx_serial.h"
25
return tx_status_fifo_pop(s);
30
#include "hw/timer/imx_gpt.h"
26
case 0x4c:
31
@@ -XXX,XX +XXX,XX @@ struct FslIMX6State {
32
A9MPPrivState a9mpcore;
33
IMX6CCMState ccm;
34
IMX6SRCState src;
35
+ IMX7SNVSState snvs;
36
IMXSerialState uart[FSL_IMX6_NUM_UARTS];
37
IMXGPTState gpt;
38
IMXEPITState epit[FSL_IMX6_NUM_EPITS];
39
diff --git a/hw/arm/fsl-imx6.c b/hw/arm/fsl-imx6.c
40
index XXXXXXX..XXXXXXX 100644
41
--- a/hw/arm/fsl-imx6.c
42
+++ b/hw/arm/fsl-imx6.c
43
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6_init(Object *obj)
44
45
object_initialize_child(obj, "src", &s->src, TYPE_IMX6_SRC);
46
47
+ object_initialize_child(obj, "snvs", &s->snvs, TYPE_IMX7_SNVS);
48
+
49
for (i = 0; i < FSL_IMX6_NUM_UARTS; i++) {
50
snprintf(name, NAME_SIZE, "uart%d", i + 1);
51
object_initialize_child(obj, name, &s->uart[i], TYPE_IMX_SERIAL);
52
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6_realize(DeviceState *dev, Error **errp)
53
qdev_get_gpio_in(DEVICE(&s->a9mpcore),
54
FSL_IMX6_ENET_MAC_1588_IRQ));
55
56
+ /*
57
+ * SNVS
58
+ */
59
+ sysbus_realize(SYS_BUS_DEVICE(&s->snvs), &error_abort);
60
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->snvs), 0, FSL_IMX6_SNVSHP_ADDR);
61
+
62
/*
63
* Watchdog
64
*/
27
--
65
--
28
2.20.1
66
2.34.1
29
30
diff view generated by jsdifflib
[PULL 05/21] target/arm: make ARMCPU.ctr 64-bit
[PULL 02/21] hw/arm/smmuv3: Add missing fields for IDR0
1
From: Leif Lindholm <leif@nuviainc.com>
1
From: Mostafa Saleh <smostafa@google.com>
2
2
3
When FEAT_MTE is implemented, the AArch64 view of CTR_EL0 adds the
3
In preparation for adding stage-2 support.
4
TminLine field in bits [37:32].
4
Add IDR0 fields related to stage-2.
5
Extend the ctr field to be able to hold this context.
6
5
7
Signed-off-by: Leif Lindholm <leif@nuviainc.com>
6
VMID16: 16-bit VMID supported.
8
Reviewed-by: Hao Wu <wuhaotsh@google.com>
7
S2P: Stage-2 translation supported.
8
9
They are described in 6.3.1 SMMU_IDR0.
10
11
No functional change intended.
12
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
13
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>
14
Reviewed-by: Eric Auger <eric.auger@redhat.com>
11
Message-id: 20210108185154.8108-4-leif@nuviainc.com
15
Signed-off-by: Mostafa Saleh <smostafa@google.com>
16
Tested-by: Eric Auger <eric.auger@redhat.com>
17
Tested-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
18
Message-id: 20230516203327.2051088-2-smostafa@google.com
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
20
---
14
target/arm/cpu.h | 2 +-
21
hw/arm/smmuv3-internal.h | 2 ++
15
1 file changed, 1 insertion(+), 1 deletion(-)
22
1 file changed, 2 insertions(+)
16
23
17
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
24
diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h
18
index XXXXXXX..XXXXXXX 100644
25
index XXXXXXX..XXXXXXX 100644
19
--- a/target/arm/cpu.h
26
--- a/hw/arm/smmuv3-internal.h
20
+++ b/target/arm/cpu.h
27
+++ b/hw/arm/smmuv3-internal.h
21
@@ -XXX,XX +XXX,XX @@ struct ARMCPU {
28
@@ -XXX,XX +XXX,XX @@ typedef enum SMMUTranslationStatus {
22
uint64_t midr;
29
/* MMIO Registers */
23
uint32_t revidr;
30
24
uint32_t reset_fpsid;
31
REG32(IDR0, 0x0)
25
- uint32_t ctr;
32
+ FIELD(IDR0, S2P, 0 , 1)
26
+ uint64_t ctr;
33
FIELD(IDR0, S1P, 1 , 1)
27
uint32_t reset_sctlr;
34
FIELD(IDR0, TTF, 2 , 2)
28
uint64_t pmceid0;
35
FIELD(IDR0, COHACC, 4 , 1)
29
uint64_t pmceid1;
36
FIELD(IDR0, ASID16, 12, 1)
37
+ FIELD(IDR0, VMID16, 18, 1)
38
FIELD(IDR0, TTENDIAN, 21, 2)
39
FIELD(IDR0, STALL_MODEL, 24, 2)
40
FIELD(IDR0, TERM_MODEL, 26, 1)
30
--
41
--
31
2.20.1
42
2.34.1
32
33
diff view generated by jsdifflib
[PULL 14/21] hw/net/lan9118: Add symbolic constants for register offsets
[PULL 03/21] hw/arm/smmuv3: Update translation config to hold stage-2
1
The lan9118 code mostly uses symbolic constants for register offsets;
1
From: Mostafa Saleh <smostafa@google.com>
2
the exceptions are those which the datasheet doesn't give an official
3
symbolic name to.
4
2
5
Add some names for the registers which don't already have them, based
3
In preparation for adding stage-2 support, add a S2 config
6
on the longer names they are given in the memory map.
4
struct(SMMUS2Cfg), composed of the following fields and embedded in
5
the main SMMUTransCfg:
6
-tsz: Size of IPA input region (S2T0SZ)
7
-sl0: Start level of translation (S2SL0)
8
-affd: AF Fault Disable (S2AFFD)
9
-record_faults: Record fault events (S2R)
10
-granule_sz: Granule page shift (based on S2TG)
11
-vmid: Virtual Machine ID (S2VMID)
12
-vttb: Address of translation table base (S2TTB)
13
-eff_ps: Effective PA output range (based on S2PS)
7
14
15
They will be used in the next patches in stage-2 address translation.
16
17
The fields in SMMUS2Cfg, are reordered to make the shared and stage-1
18
fields next to each other, this reordering didn't change the struct
19
size (104 bytes before and after).
20
21
Stage-1 only fields: aa64, asid, tt, ttb, tbi, record_faults, oas.
22
oas is stage-1 output address size. However, it is used to check
23
input address in case stage-1 is unimplemented or bypassed according
24
to SMMUv3 manual IHI0070.E "3.4. Address sizes"
25
26
Shared fields: stage, disabled, bypassed, aborted, iotlb_*.
27
28
No functional change intended.
29
30
Reviewed-by: Eric Auger <eric.auger@redhat.com>
31
Signed-off-by: Mostafa Saleh <smostafa@google.com>
32
Tested-by: Eric Auger <eric.auger@redhat.com>
33
Tested-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
34
Message-id: 20230516203327.2051088-3-smostafa@google.com
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
35
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
10
Message-id: 20210108180401.2263-3-peter.maydell@linaro.org
11
---
36
---
12
hw/net/lan9118.c | 24 ++++++++++++++++++------
37
include/hw/arm/smmu-common.h | 22 +++++++++++++++++++---
13
1 file changed, 18 insertions(+), 6 deletions(-)
38
1 file changed, 19 insertions(+), 3 deletions(-)
14
39
15
diff --git a/hw/net/lan9118.c b/hw/net/lan9118.c
40
diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h
16
index XXXXXXX..XXXXXXX 100644
41
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/net/lan9118.c
42
--- a/include/hw/arm/smmu-common.h
18
+++ b/hw/net/lan9118.c
43
+++ b/include/hw/arm/smmu-common.h
19
@@ -XXX,XX +XXX,XX @@ do { hw_error("lan9118: error: " fmt , ## __VA_ARGS__);} while (0)
44
@@ -XXX,XX +XXX,XX @@ typedef struct SMMUTLBEntry {
20
do { fprintf(stderr, "lan9118: error: " fmt , ## __VA_ARGS__);} while (0)
45
uint8_t granule;
21
#endif
46
} SMMUTLBEntry;
22
47
23
+/* The tx and rx fifo ports are a range of aliased 32-bit registers */
48
+/* Stage-2 configuration. */
24
+#define RX_DATA_FIFO_PORT_FIRST 0x00
49
+typedef struct SMMUS2Cfg {
25
+#define RX_DATA_FIFO_PORT_LAST 0x1f
50
+ uint8_t tsz; /* Size of IPA input region (S2T0SZ) */
26
+#define TX_DATA_FIFO_PORT_FIRST 0x20
51
+ uint8_t sl0; /* Start level of translation (S2SL0) */
27
+#define TX_DATA_FIFO_PORT_LAST 0x3f
52
+ bool affd; /* AF Fault Disable (S2AFFD) */
53
+ bool record_faults; /* Record fault events (S2R) */
54
+ uint8_t granule_sz; /* Granule page shift (based on S2TG) */
55
+ uint8_t eff_ps; /* Effective PA output range (based on S2PS) */
56
+ uint16_t vmid; /* Virtual Machine ID (S2VMID) */
57
+ uint64_t vttb; /* Address of translation table base (S2TTB) */
58
+} SMMUS2Cfg;
28
+
59
+
29
+#define RX_STATUS_FIFO_PORT 0x40
60
/*
30
+#define RX_STATUS_FIFO_PEEK 0x44
61
* Generic structure populated by derived SMMU devices
31
+#define TX_STATUS_FIFO_PORT 0x48
62
* after decoding the configuration information and used as
32
+#define TX_STATUS_FIFO_PEEK 0x4c
63
* input to the page table walk
33
+
64
*/
34
#define CSR_ID_REV 0x50
65
typedef struct SMMUTransCfg {
35
#define CSR_IRQ_CFG 0x54
66
+ /* Shared fields between stage-1 and stage-2. */
36
#define CSR_INT_STS 0x58
67
int stage; /* translation stage */
37
@@ -XXX,XX +XXX,XX @@ static void lan9118_writel(void *opaque, hwaddr offset,
68
- bool aa64; /* arch64 or aarch32 translation table */
38
offset &= 0xff;
69
bool disabled; /* smmu is disabled */
39
70
bool bypassed; /* translation is bypassed */
40
//DPRINTF("Write reg 0x%02x = 0x%08x\n", (int)offset, val);
71
bool aborted; /* translation is aborted */
41
- if (offset >= 0x20 && offset < 0x40) {
72
+ uint32_t iotlb_hits; /* counts IOTLB hits */
42
+ if (offset >= TX_DATA_FIFO_PORT_FIRST &&
73
+ uint32_t iotlb_misses; /* counts IOTLB misses*/
43
+ offset <= TX_DATA_FIFO_PORT_LAST) {
74
+ /* Used by stage-1 only. */
44
/* TX FIFO */
75
+ bool aa64; /* arch64 or aarch32 translation table */
45
tx_fifo_push(s, val);
76
bool record_faults; /* record fault events */
46
return;
77
uint64_t ttb; /* TT base address */
47
@@ -XXX,XX +XXX,XX @@ static uint64_t lan9118_readl(void *opaque, hwaddr offset,
78
uint8_t oas; /* output address width */
48
lan9118_state *s = (lan9118_state *)opaque;
79
uint8_t tbi; /* Top Byte Ignore */
49
80
uint16_t asid;
50
//DPRINTF("Read reg 0x%02x\n", (int)offset);
81
SMMUTransTableInfo tt[2];
51
- if (offset < 0x20) {
82
- uint32_t iotlb_hits; /* counts IOTLB hits for this asid */
52
+ if (offset <= RX_DATA_FIFO_PORT_LAST) {
83
- uint32_t iotlb_misses; /* counts IOTLB misses for this asid */
53
/* RX FIFO */
84
+ /* Used by stage-2 only. */
54
return rx_fifo_pop(s);
85
+ struct SMMUS2Cfg s2cfg;
55
}
86
} SMMUTransCfg;
56
switch (offset) {
87
57
- case 0x40:
88
typedef struct SMMUDevice {
58
+ case RX_STATUS_FIFO_PORT:
59
return rx_status_fifo_pop(s);
60
- case 0x44:
61
+ case RX_STATUS_FIFO_PEEK:
62
return s->rx_status_fifo[s->rx_status_fifo_head];
63
- case 0x48:
64
+ case TX_STATUS_FIFO_PORT:
65
return tx_status_fifo_pop(s);
66
- case 0x4c:
67
+ case TX_STATUS_FIFO_PEEK:
68
return s->tx_status_fifo[s->tx_status_fifo_head];
69
case CSR_ID_REV:
70
return 0x01180001;
71
--
89
--
72
2.20.1
90
2.34.1
73
74
diff view generated by jsdifflib
[PULL 10/21] docs: Add qemu-storage-daemon(1) manpage to meson.build
[PULL 04/21] hw/arm/smmuv3: Refactor stage-1 PTW
1
In commit 1982e1602d15 we added a new qemu-storage-daemon(1) manpage.
1
From: Mostafa Saleh <smostafa@google.com>
2
At the moment new manpages have to be listed both in the conf.py for
3
Sphinx and also in docs/meson.build for Meson. We forgot the second
4
of those -- correct the omission.
5
2
3
In preparation for adding stage-2 support, rename smmu_ptw_64 to
4
smmu_ptw_64_s1 and refactor some of the code so it can be reused in
5
stage-2 page table walk.
6
7
Remove AA64 check from PTW as decode_cd already ensures that AA64 is
8
used, otherwise it faults with C_BAD_CD.
9
10
A stage member is added to SMMUPTWEventInfo to differentiate
11
between stage-1 and stage-2 ptw faults.
12
13
Add stage argument to trace_smmu_ptw_level be consistent with other
14
trace events.
15
16
Signed-off-by: Mostafa Saleh <smostafa@google.com>
17
Reviewed-by: Eric Auger <eric.auger@redhat.com>
18
Tested-by: Eric Auger <eric.auger@redhat.com>
19
Tested-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
20
Message-id: 20230516203327.2051088-4-smostafa@google.com
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
21
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
8
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
9
Message-id: 20210108161416.21129-2-peter.maydell@linaro.org
10
---
22
---
11
docs/meson.build | 1 +
23
include/hw/arm/smmu-common.h | 16 +++++++++++++---
12
1 file changed, 1 insertion(+)
24
hw/arm/smmu-common.c | 27 ++++++++++-----------------
25
hw/arm/smmuv3.c | 2 ++
26
hw/arm/trace-events | 2 +-
27
4 files changed, 26 insertions(+), 21 deletions(-)
13
28
14
diff --git a/docs/meson.build b/docs/meson.build
29
diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h
15
index XXXXXXX..XXXXXXX 100644
30
index XXXXXXX..XXXXXXX 100644
16
--- a/docs/meson.build
31
--- a/include/hw/arm/smmu-common.h
17
+++ b/docs/meson.build
32
+++ b/include/hw/arm/smmu-common.h
18
@@ -XXX,XX +XXX,XX @@ if build_docs
33
@@ -XXX,XX +XXX,XX @@
19
'qemu-img.1': (have_tools ? 'man1' : ''),
34
#include "hw/pci/pci.h"
20
'qemu-nbd.8': (have_tools ? 'man8' : ''),
35
#include "qom/object.h"
21
'qemu-pr-helper.8': (have_tools ? 'man8' : ''),
36
22
+ 'qemu-storage-daemon.1': (have_tools ? 'man1' : ''),
37
-#define SMMU_PCI_BUS_MAX 256
23
'qemu-trace-stap.1': (config_host.has_key('CONFIG_TRACE_SYSTEMTAP') ? 'man1' : ''),
38
-#define SMMU_PCI_DEVFN_MAX 256
24
'virtfs-proxy-helper.1': (have_virtfs_proxy_helper ? 'man1' : ''),
39
-#define SMMU_PCI_DEVFN(sid) (sid & 0xFF)
25
'virtiofsd.1': (have_virtiofsd ? 'man1' : ''),
40
+#define SMMU_PCI_BUS_MAX 256
41
+#define SMMU_PCI_DEVFN_MAX 256
42
+#define SMMU_PCI_DEVFN(sid) (sid & 0xFF)
43
+
44
+/* VMSAv8-64 Translation constants and functions */
45
+#define VMSA_LEVELS 4
46
+
47
+#define VMSA_STRIDE(gran) ((gran) - VMSA_LEVELS + 1)
48
+#define VMSA_BIT_LVL(isz, strd, lvl) ((isz) - (strd) * \
49
+ (VMSA_LEVELS - (lvl)))
50
+#define VMSA_IDXMSK(isz, strd, lvl) ((1ULL << \
51
+ VMSA_BIT_LVL(isz, strd, lvl)) - 1)
52
53
/*
54
* Page table walk error types
55
@@ -XXX,XX +XXX,XX @@ typedef enum {
56
} SMMUPTWEventType;
57
58
typedef struct SMMUPTWEventInfo {
59
+ int stage;
60
SMMUPTWEventType type;
61
dma_addr_t addr; /* fetched address that induced an abort, if any */
62
} SMMUPTWEventInfo;
63
diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c
64
index XXXXXXX..XXXXXXX 100644
65
--- a/hw/arm/smmu-common.c
66
+++ b/hw/arm/smmu-common.c
67
@@ -XXX,XX +XXX,XX @@ SMMUTransTableInfo *select_tt(SMMUTransCfg *cfg, dma_addr_t iova)
68
}
69
70
/**
71
- * smmu_ptw_64 - VMSAv8-64 Walk of the page tables for a given IOVA
72
+ * smmu_ptw_64_s1 - VMSAv8-64 Walk of the page tables for a given IOVA
73
* @cfg: translation config
74
* @iova: iova to translate
75
* @perm: access type
76
@@ -XXX,XX +XXX,XX @@ SMMUTransTableInfo *select_tt(SMMUTransCfg *cfg, dma_addr_t iova)
77
* Upon success, @tlbe is filled with translated_addr and entry
78
* permission rights.
79
*/
80
-static int smmu_ptw_64(SMMUTransCfg *cfg,
81
- dma_addr_t iova, IOMMUAccessFlags perm,
82
- SMMUTLBEntry *tlbe, SMMUPTWEventInfo *info)
83
+static int smmu_ptw_64_s1(SMMUTransCfg *cfg,
84
+ dma_addr_t iova, IOMMUAccessFlags perm,
85
+ SMMUTLBEntry *tlbe, SMMUPTWEventInfo *info)
86
{
87
dma_addr_t baseaddr, indexmask;
88
int stage = cfg->stage;
89
@@ -XXX,XX +XXX,XX @@ static int smmu_ptw_64(SMMUTransCfg *cfg,
90
}
91
92
granule_sz = tt->granule_sz;
93
- stride = granule_sz - 3;
94
+ stride = VMSA_STRIDE(granule_sz);
95
inputsize = 64 - tt->tsz;
96
level = 4 - (inputsize - 4) / stride;
97
- indexmask = (1ULL << (inputsize - (stride * (4 - level)))) - 1;
98
+ indexmask = VMSA_IDXMSK(inputsize, stride, level);
99
baseaddr = extract64(tt->ttb, 0, 48);
100
baseaddr &= ~indexmask;
101
102
- while (level <= 3) {
103
+ while (level < VMSA_LEVELS) {
104
uint64_t subpage_size = 1ULL << level_shift(level, granule_sz);
105
uint64_t mask = subpage_size - 1;
106
uint32_t offset = iova_level_offset(iova, inputsize, level, granule_sz);
107
@@ -XXX,XX +XXX,XX @@ static int smmu_ptw_64(SMMUTransCfg *cfg,
108
if (get_pte(baseaddr, offset, &pte, info)) {
109
goto error;
110
}
111
- trace_smmu_ptw_level(level, iova, subpage_size,
112
+ trace_smmu_ptw_level(stage, level, iova, subpage_size,
113
baseaddr, offset, pte);
114
115
if (is_invalid_pte(pte) || is_reserved_pte(pte, level)) {
116
@@ -XXX,XX +XXX,XX @@ static int smmu_ptw_64(SMMUTransCfg *cfg,
117
info->type = SMMU_PTW_ERR_TRANSLATION;
118
119
error:
120
+ info->stage = 1;
121
tlbe->entry.perm = IOMMU_NONE;
122
return -EINVAL;
123
}
124
@@ -XXX,XX +XXX,XX @@ error:
125
int smmu_ptw(SMMUTransCfg *cfg, dma_addr_t iova, IOMMUAccessFlags perm,
126
SMMUTLBEntry *tlbe, SMMUPTWEventInfo *info)
127
{
128
- if (!cfg->aa64) {
129
- /*
130
- * This code path is not entered as we check this while decoding
131
- * the configuration data in the derived SMMU model.
132
- */
133
- g_assert_not_reached();
134
- }
135
-
136
- return smmu_ptw_64(cfg, iova, perm, tlbe, info);
137
+ return smmu_ptw_64_s1(cfg, iova, perm, tlbe, info);
138
}
139
140
/**
141
diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
142
index XXXXXXX..XXXXXXX 100644
143
--- a/hw/arm/smmuv3.c
144
+++ b/hw/arm/smmuv3.c
145
@@ -XXX,XX +XXX,XX @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegion *mr, hwaddr addr,
146
cached_entry = g_new0(SMMUTLBEntry, 1);
147
148
if (smmu_ptw(cfg, aligned_addr, flag, cached_entry, &ptw_info)) {
149
+ /* All faults from PTW has S2 field. */
150
+ event.u.f_walk_eabt.s2 = (ptw_info.stage == 2);
151
g_free(cached_entry);
152
switch (ptw_info.type) {
153
case SMMU_PTW_ERR_WALK_EABT:
154
diff --git a/hw/arm/trace-events b/hw/arm/trace-events
155
index XXXXXXX..XXXXXXX 100644
156
--- a/hw/arm/trace-events
157
+++ b/hw/arm/trace-events
158
@@ -XXX,XX +XXX,XX @@ virt_acpi_setup(void) "No fw cfg or ACPI disabled. Bailing out."
159
160
# smmu-common.c
161
smmu_add_mr(const char *name) "%s"
162
-smmu_ptw_level(int level, uint64_t iova, size_t subpage_size, uint64_t baseaddr, uint32_t offset, uint64_t pte) "level=%d iova=0x%"PRIx64" subpage_sz=0x%zx baseaddr=0x%"PRIx64" offset=%d => pte=0x%"PRIx64
163
+smmu_ptw_level(int stage, int level, uint64_t iova, size_t subpage_size, uint64_t baseaddr, uint32_t offset, uint64_t pte) "stage=%d level=%d iova=0x%"PRIx64" subpage_sz=0x%zx baseaddr=0x%"PRIx64" offset=%d => pte=0x%"PRIx64
164
smmu_ptw_invalid_pte(int stage, int level, uint64_t baseaddr, uint64_t pteaddr, uint32_t offset, uint64_t pte) "stage=%d level=%d base@=0x%"PRIx64" pte@=0x%"PRIx64" offset=%d pte=0x%"PRIx64
165
smmu_ptw_page_pte(int stage, int level, uint64_t iova, uint64_t baseaddr, uint64_t pteaddr, uint64_t pte, uint64_t address) "stage=%d level=%d iova=0x%"PRIx64" base@=0x%"PRIx64" pte@=0x%"PRIx64" pte=0x%"PRIx64" page address = 0x%"PRIx64
166
smmu_ptw_block_pte(int stage, int level, uint64_t baseaddr, uint64_t pteaddr, uint64_t pte, uint64_t iova, uint64_t gpa, int bsize_mb) "stage=%d level=%d base@=0x%"PRIx64" pte@=0x%"PRIx64" pte=0x%"PRIx64" iova=0x%"PRIx64" block address = 0x%"PRIx64" block size = %d MiB"
26
--
167
--
27
2.20.1
168
2.34.1
28
29
diff view generated by jsdifflib
[PULL 01/21] target/arm: ARMv8.4-TTST extension
[PULL 05/21] hw/arm/smmuv3: Add page table walk for stage-2
1
From: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
1
From: Mostafa Saleh <smostafa@google.com>
2
2
3
This adds for the Small Translation tables extension in AArch64 state.
3
In preparation for adding stage-2 support, add Stage-2 PTW code.
4
4
Only Aarch64 format is supported as stage-1.
5
Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
5
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Nesting stage-1 and stage-2 is not supported right now.
7
8
HTTU is not supported, SW is expected to maintain the Access flag.
9
This is described in the SMMUv3 manual(IHI 0070.E.a)
10
"5.2. Stream Table Entry" in "[181] S2AFFD".
11
This flag determines the behavior on access of a stage-2 page whose
12
descriptor has AF == 0:
13
- 0b0: An Access flag fault occurs (stall not supported).
14
- 0b1: An Access flag fault never occurs.
15
An Access fault takes priority over a Permission fault.
16
17
There are 3 address size checks for stage-2 according to
18
(IHI 0070.E.a) in "3.4. Address sizes".
19
- As nesting is not supported, input address is passed directly to
20
stage-2, and is checked against IAS.
21
We use cfg->oas to hold the OAS when stage-1 is not used, this is set
22
in the next patch.
23
This check is done outside of smmu_ptw_64_s2 as it is not part of
24
stage-2(it throws stage-1 fault), and the stage-2 function shouldn't
25
change it's behavior when nesting is supported.
26
When nesting is supported and we figure out how to combine TLB for
27
stage-1 and stage-2 we can move this check into the stage-1 function
28
as described in ARM DDI0487I.a in pseudocode
29
aarch64/translation/vmsa_translation/AArch64.S1Translate
30
aarch64/translation/vmsa_translation/AArch64.S1DisabledOutput
31
32
- Input to stage-2 is checked against s2t0sz, and throws stage-2
33
transaltion fault if exceeds it.
34
35
- Output of stage-2 is checked against effective PA output range.
36
37
Reviewed-by: Eric Auger <eric.auger@redhat.com>
38
Signed-off-by: Mostafa Saleh <smostafa@google.com>
39
Tested-by: Eric Auger <eric.auger@redhat.com>
40
Tested-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
41
Message-id: 20230516203327.2051088-5-smostafa@google.com
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
42
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
---
43
---
9
target/arm/cpu.h | 5 +++++
44
hw/arm/smmu-internal.h | 35 ++++++++++
10
target/arm/helper.c | 15 +++++++++++++--
45
hw/arm/smmu-common.c | 142 ++++++++++++++++++++++++++++++++++++++++-
11
2 files changed, 18 insertions(+), 2 deletions(-)
46
2 files changed, 176 insertions(+), 1 deletion(-)
12
47
13
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
48
diff --git a/hw/arm/smmu-internal.h b/hw/arm/smmu-internal.h
14
index XXXXXXX..XXXXXXX 100644
49
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/cpu.h
50
--- a/hw/arm/smmu-internal.h
16
+++ b/target/arm/cpu.h
51
+++ b/hw/arm/smmu-internal.h
17
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_uao(const ARMISARegisters *id)
52
@@ -XXX,XX +XXX,XX @@
18
return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, UAO) != 0;
53
#define PTE_APTABLE(pte) \
54
(extract64(pte, 61, 2))
55
56
+#define PTE_AF(pte) \
57
+ (extract64(pte, 10, 1))
58
/*
59
* TODO: At the moment all transactions are considered as privileged (EL1)
60
* as IOMMU translation callback does not pass user/priv attributes.
61
@@ -XXX,XX +XXX,XX @@
62
#define is_permission_fault(ap, perm) \
63
(((perm) & IOMMU_WO) && ((ap) & 0x2))
64
65
+#define is_permission_fault_s2(s2ap, perm) \
66
+ (!(((s2ap) & (perm)) == (perm)))
67
+
68
#define PTE_AP_TO_PERM(ap) \
69
(IOMMU_ACCESS_FLAG(true, !((ap) & 0x2)))
70
71
@@ -XXX,XX +XXX,XX @@ uint64_t iova_level_offset(uint64_t iova, int inputsize,
72
MAKE_64BIT_MASK(0, gsz - 3);
19
}
73
}
20
74
21
+static inline bool isar_feature_aa64_st(const ARMISARegisters *id)
75
+/* FEAT_LPA2 and FEAT_TTST are not implemented. */
76
+static inline int get_start_level(int sl0 , int granule_sz)
22
+{
77
+{
23
+ return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, ST) != 0;
78
+ /* ARM DDI0487I.a: Table D8-12. */
79
+ if (granule_sz == 12) {
80
+ return 2 - sl0;
81
+ }
82
+ /* ARM DDI0487I.a: Table D8-22 and Table D8-31. */
83
+ return 3 - sl0;
24
+}
84
+}
25
+
85
+
26
static inline bool isar_feature_aa64_bti(const ARMISARegisters *id)
86
+/*
87
+ * Index in a concatenated first level stage-2 page table.
88
+ * ARM DDI0487I.a: D8.2.2 Concatenated translation tables.
89
+ */
90
+static inline int pgd_concat_idx(int start_level, int granule_sz,
91
+ dma_addr_t ipa)
92
+{
93
+ uint64_t ret;
94
+ /*
95
+ * Get the number of bits handled by next levels, then any extra bits in
96
+ * the address should index the concatenated tables. This relation can be
97
+ * deduced from tables in ARM DDI0487I.a: D8.2.7-9
98
+ */
99
+ int shift = level_shift(start_level - 1, granule_sz);
100
+
101
+ ret = ipa >> shift;
102
+ return ret;
103
+}
104
+
105
#define SMMU_IOTLB_ASID(key) ((key).asid)
106
107
typedef struct SMMUIOTLBPageInvInfo {
108
diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c
109
index XXXXXXX..XXXXXXX 100644
110
--- a/hw/arm/smmu-common.c
111
+++ b/hw/arm/smmu-common.c
112
@@ -XXX,XX +XXX,XX @@ error:
113
return -EINVAL;
114
}
115
116
+/**
117
+ * smmu_ptw_64_s2 - VMSAv8-64 Walk of the page tables for a given ipa
118
+ * for stage-2.
119
+ * @cfg: translation config
120
+ * @ipa: ipa to translate
121
+ * @perm: access type
122
+ * @tlbe: SMMUTLBEntry (out)
123
+ * @info: handle to an error info
124
+ *
125
+ * Return 0 on success, < 0 on error. In case of error, @info is filled
126
+ * and tlbe->perm is set to IOMMU_NONE.
127
+ * Upon success, @tlbe is filled with translated_addr and entry
128
+ * permission rights.
129
+ */
130
+static int smmu_ptw_64_s2(SMMUTransCfg *cfg,
131
+ dma_addr_t ipa, IOMMUAccessFlags perm,
132
+ SMMUTLBEntry *tlbe, SMMUPTWEventInfo *info)
133
+{
134
+ const int stage = 2;
135
+ int granule_sz = cfg->s2cfg.granule_sz;
136
+ /* ARM DDI0487I.a: Table D8-7. */
137
+ int inputsize = 64 - cfg->s2cfg.tsz;
138
+ int level = get_start_level(cfg->s2cfg.sl0, granule_sz);
139
+ int stride = VMSA_STRIDE(granule_sz);
140
+ int idx = pgd_concat_idx(level, granule_sz, ipa);
141
+ /*
142
+ * Get the ttb from concatenated structure.
143
+ * The offset is the idx * size of each ttb(number of ptes * (sizeof(pte))
144
+ */
145
+ uint64_t baseaddr = extract64(cfg->s2cfg.vttb, 0, 48) + (1 << stride) *
146
+ idx * sizeof(uint64_t);
147
+ dma_addr_t indexmask = VMSA_IDXMSK(inputsize, stride, level);
148
+
149
+ baseaddr &= ~indexmask;
150
+
151
+ /*
152
+ * On input, a stage 2 Translation fault occurs if the IPA is outside the
153
+ * range configured by the relevant S2T0SZ field of the STE.
154
+ */
155
+ if (ipa >= (1ULL << inputsize)) {
156
+ info->type = SMMU_PTW_ERR_TRANSLATION;
157
+ goto error;
158
+ }
159
+
160
+ while (level < VMSA_LEVELS) {
161
+ uint64_t subpage_size = 1ULL << level_shift(level, granule_sz);
162
+ uint64_t mask = subpage_size - 1;
163
+ uint32_t offset = iova_level_offset(ipa, inputsize, level, granule_sz);
164
+ uint64_t pte, gpa;
165
+ dma_addr_t pte_addr = baseaddr + offset * sizeof(pte);
166
+ uint8_t s2ap;
167
+
168
+ if (get_pte(baseaddr, offset, &pte, info)) {
169
+ goto error;
170
+ }
171
+ trace_smmu_ptw_level(stage, level, ipa, subpage_size,
172
+ baseaddr, offset, pte);
173
+ if (is_invalid_pte(pte) || is_reserved_pte(pte, level)) {
174
+ trace_smmu_ptw_invalid_pte(stage, level, baseaddr,
175
+ pte_addr, offset, pte);
176
+ break;
177
+ }
178
+
179
+ if (is_table_pte(pte, level)) {
180
+ baseaddr = get_table_pte_address(pte, granule_sz);
181
+ level++;
182
+ continue;
183
+ } else if (is_page_pte(pte, level)) {
184
+ gpa = get_page_pte_address(pte, granule_sz);
185
+ trace_smmu_ptw_page_pte(stage, level, ipa,
186
+ baseaddr, pte_addr, pte, gpa);
187
+ } else {
188
+ uint64_t block_size;
189
+
190
+ gpa = get_block_pte_address(pte, level, granule_sz,
191
+ &block_size);
192
+ trace_smmu_ptw_block_pte(stage, level, baseaddr,
193
+ pte_addr, pte, ipa, gpa,
194
+ block_size >> 20);
195
+ }
196
+
197
+ /*
198
+ * If S2AFFD and PTE.AF are 0 => fault. (5.2. Stream Table Entry)
199
+ * An Access fault takes priority over a Permission fault.
200
+ */
201
+ if (!PTE_AF(pte) && !cfg->s2cfg.affd) {
202
+ info->type = SMMU_PTW_ERR_ACCESS;
203
+ goto error;
204
+ }
205
+
206
+ s2ap = PTE_AP(pte);
207
+ if (is_permission_fault_s2(s2ap, perm)) {
208
+ info->type = SMMU_PTW_ERR_PERMISSION;
209
+ goto error;
210
+ }
211
+
212
+ /*
213
+ * The address output from the translation causes a stage 2 Address
214
+ * Size fault if it exceeds the effective PA output range.
215
+ */
216
+ if (gpa >= (1ULL << cfg->s2cfg.eff_ps)) {
217
+ info->type = SMMU_PTW_ERR_ADDR_SIZE;
218
+ goto error;
219
+ }
220
+
221
+ tlbe->entry.translated_addr = gpa;
222
+ tlbe->entry.iova = ipa & ~mask;
223
+ tlbe->entry.addr_mask = mask;
224
+ tlbe->entry.perm = s2ap;
225
+ tlbe->level = level;
226
+ tlbe->granule = granule_sz;
227
+ return 0;
228
+ }
229
+ info->type = SMMU_PTW_ERR_TRANSLATION;
230
+
231
+error:
232
+ info->stage = 2;
233
+ tlbe->entry.perm = IOMMU_NONE;
234
+ return -EINVAL;
235
+}
236
+
237
/**
238
* smmu_ptw - Walk the page tables for an IOVA, according to @cfg
239
*
240
@@ -XXX,XX +XXX,XX @@ error:
241
int smmu_ptw(SMMUTransCfg *cfg, dma_addr_t iova, IOMMUAccessFlags perm,
242
SMMUTLBEntry *tlbe, SMMUPTWEventInfo *info)
27
{
243
{
28
return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) != 0;
244
- return smmu_ptw_64_s1(cfg, iova, perm, tlbe, info);
29
diff --git a/target/arm/helper.c b/target/arm/helper.c
245
+ if (cfg->stage == 1) {
30
index XXXXXXX..XXXXXXX 100644
246
+ return smmu_ptw_64_s1(cfg, iova, perm, tlbe, info);
31
--- a/target/arm/helper.c
247
+ } else if (cfg->stage == 2) {
32
+++ b/target/arm/helper.c
248
+ /*
33
@@ -XXX,XX +XXX,XX @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
249
+ * If bypassing stage 1(or unimplemented), the input address is passed
34
{
250
+ * directly to stage 2 as IPA. If the input address of a transaction
35
uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr;
251
+ * exceeds the size of the IAS, a stage 1 Address Size fault occurs.
36
bool epd, hpd, using16k, using64k;
252
+ * For AA64, IAS = OAS according to (IHI 0070.E.a) "3.4 Address sizes"
37
- int select, tsz, tbi;
253
+ */
38
+ int select, tsz, tbi, max_tsz;
254
+ if (iova >= (1ULL << cfg->oas)) {
39
255
+ info->type = SMMU_PTW_ERR_ADDR_SIZE;
40
if (!regime_has_2_ranges(mmu_idx)) {
256
+ info->stage = 1;
41
select = 0;
257
+ tlbe->entry.perm = IOMMU_NONE;
42
@@ -XXX,XX +XXX,XX @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
258
+ return -EINVAL;
43
hpd = extract64(tcr, 42, 1);
259
+ }
44
}
260
+
45
}
261
+ return smmu_ptw_64_s2(cfg, iova, perm, tlbe, info);
46
- tsz = MIN(tsz, 39); /* TODO: ARMv8.4-TTST */
262
+ }
47
+
263
+
48
+ if (cpu_isar_feature(aa64_st, env_archcpu(env))) {
264
+ g_assert_not_reached();
49
+ max_tsz = 48 - using64k;
265
}
50
+ } else {
266
51
+ max_tsz = 39;
267
/**
52
+ }
53
+
54
+ tsz = MIN(tsz, max_tsz);
55
tsz = MAX(tsz, 16); /* TODO: ARMv8.2-LVA */
56
57
/* Present TBI as a composite with TBID. */
58
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address,
59
if (!aarch64 || stride == 9) {
60
/* AArch32 or 4KB pages */
61
startlevel = 2 - sl0;
62
+
63
+ if (cpu_isar_feature(aa64_st, cpu)) {
64
+ startlevel &= 3;
65
+ }
66
} else {
67
/* 16KB or 64KB pages */
68
startlevel = 3 - sl0;
69
--
268
--
70
2.20.1
269
2.34.1
71
72
diff view generated by jsdifflib
[PULL 18/21] hw/misc: Add a PWM module for NPCM7XX
[PULL 06/21] hw/arm/smmuv3: Parse STE config for stage-2
1
From: Hao Wu <wuhaotsh@google.com>
1
From: Mostafa Saleh <smostafa@google.com>
2
2
3
The PWM module is part of NPCM7XX module. Each NPCM7XX module has two
3
Parse stage-2 configuration from STE and populate it in SMMUS2Cfg.
4
identical PWM modules. Each module contains 4 PWM entries. Each PWM has
4
Validity of field values are checked when possible.
5
two outputs: frequency and duty_cycle. Both are computed using inputs
5
6
from software side.
6
Only AA64 tables are supported and Small Translation Tables (STT) are
7
7
not supported.
8
This module does not model detail pulse signals since it is expensive.
8
9
It also does not model interrupts and watchdogs that are dependant on
9
According to SMMUv3 UM(IHI0070E) "5.2 Stream Table Entry": All fields
10
the detail models. The interfaces for these are left in the module so
10
with an S2 prefix (with the exception of S2VMID) are IGNORED when
11
that anyone in need for these functionalities can implement on their
11
stage-2 bypasses translation (Config[1] == 0).
12
own.
12
13
13
Which means that VMID can be used(for TLB tagging) even if stage-2 is
14
The user can read the duty cycle and frequency using qom-get command.
14
bypassed, so we parse it unconditionally when S2P exists. Otherwise
15
15
it is set to -1.(only S1P)
16
Reviewed-by: Havard Skinnemoen <hskinnemoen@google.com>
16
17
Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
17
As stall is not supported, if S2S is set the translation would abort.
18
Signed-off-by: Hao Wu <wuhaotsh@google.com>
18
For S2R, we reuse the same code used for stage-1 with flag
19
Message-id: 20210108190945.949196-5-wuhaotsh@google.com
19
record_faults. However when nested translation is supported we would
20
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
20
need to separate stage-1 and stage-2 faults.
21
22
Fix wrong shift in STE_S2HD, STE_S2HA, STE_S2S.
23
24
Signed-off-by: Mostafa Saleh <smostafa@google.com>
25
Tested-by: Eric Auger <eric.auger@redhat.com>
26
Tested-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
27
Reviewed-by: Eric Auger <eric.auger@redhat.com>
28
Message-id: 20230516203327.2051088-6-smostafa@google.com
21
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
29
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
22
---
30
---
23
docs/system/arm/nuvoton.rst | 2 +-
31
hw/arm/smmuv3-internal.h | 10 +-
24
include/hw/arm/npcm7xx.h | 2 +
32
include/hw/arm/smmu-common.h | 1 +
25
include/hw/misc/npcm7xx_pwm.h | 105 +++++++
33
include/hw/arm/smmuv3.h | 3 +
26
hw/arm/npcm7xx.c | 26 +-
34
hw/arm/smmuv3.c | 181 +++++++++++++++++++++++++++++++++--
27
hw/misc/npcm7xx_pwm.c | 550 ++++++++++++++++++++++++++++++++++
35
4 files changed, 185 insertions(+), 10 deletions(-)
28
hw/misc/meson.build | 1 +
36
29
hw/misc/trace-events | 6 +
37
diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h
30
7 files changed, 689 insertions(+), 3 deletions(-)
31
create mode 100644 include/hw/misc/npcm7xx_pwm.h
32
create mode 100644 hw/misc/npcm7xx_pwm.c
33
34
diff --git a/docs/system/arm/nuvoton.rst b/docs/system/arm/nuvoton.rst
35
index XXXXXXX..XXXXXXX 100644
38
index XXXXXXX..XXXXXXX 100644
36
--- a/docs/system/arm/nuvoton.rst
39
--- a/hw/arm/smmuv3-internal.h
37
+++ b/docs/system/arm/nuvoton.rst
40
+++ b/hw/arm/smmuv3-internal.h
38
@@ -XXX,XX +XXX,XX @@ Supported devices
41
@@ -XXX,XX +XXX,XX @@ typedef struct CD {
39
* USB host (USBH)
42
#define STE_S2TG(x) extract32((x)->word[5], 14, 2)
40
* GPIO controller
43
#define STE_S2PS(x) extract32((x)->word[5], 16, 3)
41
* Analog to Digital Converter (ADC)
44
#define STE_S2AA64(x) extract32((x)->word[5], 19, 1)
42
+ * Pulse Width Modulation (PWM)
45
-#define STE_S2HD(x) extract32((x)->word[5], 24, 1)
43
46
-#define STE_S2HA(x) extract32((x)->word[5], 25, 1)
44
Missing devices
47
-#define STE_S2S(x) extract32((x)->word[5], 26, 1)
45
---------------
48
+#define STE_S2ENDI(x) extract32((x)->word[5], 20, 1)
46
@@ -XXX,XX +XXX,XX @@ Missing devices
49
+#define STE_S2AFFD(x) extract32((x)->word[5], 21, 1)
47
* Peripheral SPI controller (PSPI)
50
+#define STE_S2HD(x) extract32((x)->word[5], 23, 1)
48
* SD/MMC host
51
+#define STE_S2HA(x) extract32((x)->word[5], 24, 1)
49
* PECI interface
52
+#define STE_S2S(x) extract32((x)->word[5], 25, 1)
50
- * Pulse Width Modulation (PWM)
53
+#define STE_S2R(x) extract32((x)->word[5], 26, 1)
51
* Tachometer
54
+
52
* PCI and PCIe root complex and bridges
55
#define STE_CTXPTR(x) \
53
* VDM and MCTP support
56
({ \
54
diff --git a/include/hw/arm/npcm7xx.h b/include/hw/arm/npcm7xx.h
57
unsigned long addr; \
58
diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h
55
index XXXXXXX..XXXXXXX 100644
59
index XXXXXXX..XXXXXXX 100644
56
--- a/include/hw/arm/npcm7xx.h
60
--- a/include/hw/arm/smmu-common.h
57
+++ b/include/hw/arm/npcm7xx.h
61
+++ b/include/hw/arm/smmu-common.h
58
@@ -XXX,XX +XXX,XX @@
62
@@ -XXX,XX +XXX,XX @@
59
#include "hw/mem/npcm7xx_mc.h"
63
60
#include "hw/misc/npcm7xx_clk.h"
64
/* VMSAv8-64 Translation constants and functions */
61
#include "hw/misc/npcm7xx_gcr.h"
65
#define VMSA_LEVELS 4
62
+#include "hw/misc/npcm7xx_pwm.h"
66
+#define VMSA_MAX_S2_CONCAT 16
63
#include "hw/misc/npcm7xx_rng.h"
67
64
#include "hw/nvram/npcm7xx_otp.h"
68
#define VMSA_STRIDE(gran) ((gran) - VMSA_LEVELS + 1)
65
#include "hw/timer/npcm7xx_timer.h"
69
#define VMSA_BIT_LVL(isz, strd, lvl) ((isz) - (strd) * \
66
@@ -XXX,XX +XXX,XX @@ typedef struct NPCM7xxState {
70
diff --git a/include/hw/arm/smmuv3.h b/include/hw/arm/smmuv3.h
67
NPCM7xxCLKState clk;
71
index XXXXXXX..XXXXXXX 100644
68
NPCM7xxTimerCtrlState tim[3];
72
--- a/include/hw/arm/smmuv3.h
69
NPCM7xxADCState adc;
73
+++ b/include/hw/arm/smmuv3.h
70
+ NPCM7xxPWMState pwm[2];
74
@@ -XXX,XX +XXX,XX @@ struct SMMUv3Class {
71
NPCM7xxOTPState key_storage;
75
#define TYPE_ARM_SMMUV3 "arm-smmuv3"
72
NPCM7xxOTPState fuse_array;
76
OBJECT_DECLARE_TYPE(SMMUv3State, SMMUv3Class, ARM_SMMUV3)
73
NPCM7xxMCState mc;
77
74
diff --git a/include/hw/misc/npcm7xx_pwm.h b/include/hw/misc/npcm7xx_pwm.h
78
+#define STAGE1_SUPPORTED(s) FIELD_EX32(s->idr[0], IDR0, S1P)
75
new file mode 100644
79
+#define STAGE2_SUPPORTED(s) FIELD_EX32(s->idr[0], IDR0, S2P)
76
index XXXXXXX..XXXXXXX
80
+
77
--- /dev/null
81
#endif
78
+++ b/include/hw/misc/npcm7xx_pwm.h
82
diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
83
index XXXXXXX..XXXXXXX 100644
84
--- a/hw/arm/smmuv3.c
85
+++ b/hw/arm/smmuv3.c
79
@@ -XXX,XX +XXX,XX @@
86
@@ -XXX,XX +XXX,XX @@
87
#include "smmuv3-internal.h"
88
#include "smmu-internal.h"
89
90
+#define PTW_RECORD_FAULT(cfg) (((cfg)->stage == 1) ? (cfg)->record_faults : \
91
+ (cfg)->s2cfg.record_faults)
92
+
93
/**
94
* smmuv3_trigger_irq - pulse @irq if enabled and update
95
* GERROR register in case of GERROR interrupt
96
@@ -XXX,XX +XXX,XX @@ static int smmu_get_cd(SMMUv3State *s, STE *ste, uint32_t ssid,
97
return 0;
98
}
99
80
+/*
100
+/*
81
+ * Nuvoton NPCM7xx PWM Module
101
+ * Max valid value is 39 when SMMU_IDR3.STT == 0.
82
+ *
102
+ * In architectures after SMMUv3.0:
83
+ * Copyright 2020 Google LLC
103
+ * - If STE.S2TG selects a 4KB or 16KB granule, the minimum valid value for this
84
+ *
104
+ * field is MAX(16, 64-IAS)
85
+ * This program is free software; you can redistribute it and/or modify it
105
+ * - If STE.S2TG selects a 64KB granule, the minimum valid value for this field
86
+ * under the terms of the GNU General Public License as published by the
106
+ * is (64-IAS).
87
+ * Free Software Foundation; either version 2 of the License, or
107
+ * As we only support AA64, IAS = OAS.
88
+ * (at your option) any later version.
89
+ *
90
+ * This program is distributed in the hope that it will be useful, but WITHOUT
91
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
92
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
93
+ * for more details.
94
+ */
108
+ */
95
+#ifndef NPCM7XX_PWM_H
109
+static bool s2t0sz_valid(SMMUTransCfg *cfg)
96
+#define NPCM7XX_PWM_H
110
+{
97
+
111
+ if (cfg->s2cfg.tsz > 39) {
98
+#include "hw/clock.h"
112
+ return false;
99
+#include "hw/sysbus.h"
113
+ }
100
+#include "hw/irq.h"
114
+
101
+
115
+ if (cfg->s2cfg.granule_sz == 16) {
102
+/* Each PWM module holds 4 PWM channels. */
116
+ return (cfg->s2cfg.tsz >= 64 - oas2bits(SMMU_IDR5_OAS));
103
+#define NPCM7XX_PWM_PER_MODULE 4
117
+ }
118
+
119
+ return (cfg->s2cfg.tsz >= MAX(64 - oas2bits(SMMU_IDR5_OAS), 16));
120
+}
104
+
121
+
105
+/*
122
+/*
106
+ * Number of registers in one pwm module. Don't change this without increasing
123
+ * Return true if s2 page table config is valid.
107
+ * the version_id in vmstate.
124
+ * This checks with the configured start level, ias_bits and granularity we can
125
+ * have a valid page table as described in ARM ARM D8.2 Translation process.
126
+ * The idea here is to see for the highest possible number of IPA bits, how
127
+ * many concatenated tables we would need, if it is more than 16, then this is
128
+ * not possible.
108
+ */
129
+ */
109
+#define NPCM7XX_PWM_NR_REGS (0x54 / sizeof(uint32_t))
130
+static bool s2_pgtable_config_valid(uint8_t sl0, uint8_t t0sz, uint8_t gran)
110
+
111
+/*
112
+ * The maximum duty values. Each duty unit represents 1/NPCM7XX_PWM_MAX_DUTY
113
+ * cycles. For example, if NPCM7XX_PWM_MAX_DUTY=1,000,000 and a PWM has a duty
114
+ * value of 100,000 the duty cycle for that PWM is 10%.
115
+ */
116
+#define NPCM7XX_PWM_MAX_DUTY 1000000
117
+
118
+typedef struct NPCM7xxPWMState NPCM7xxPWMState;
119
+
120
+/**
121
+ * struct NPCM7xxPWM - The state of a single PWM channel.
122
+ * @module: The PWM module that contains this channel.
123
+ * @irq: GIC interrupt line to fire on expiration if enabled.
124
+ * @running: Whether this PWM channel is generating output.
125
+ * @inverted: Whether this PWM channel is inverted.
126
+ * @index: The index of this PWM channel.
127
+ * @cnr: The counter register.
128
+ * @cmr: The comparator register.
129
+ * @pdr: The data register.
130
+ * @pwdr: The watchdog register.
131
+ * @freq: The frequency of this PWM channel.
132
+ * @duty: The duty cycle of this PWM channel. One unit represents
133
+ * 1/NPCM7XX_MAX_DUTY cycles.
134
+ */
135
+typedef struct NPCM7xxPWM {
136
+ NPCM7xxPWMState *module;
137
+
138
+ qemu_irq irq;
139
+
140
+ bool running;
141
+ bool inverted;
142
+
143
+ uint8_t index;
144
+ uint32_t cnr;
145
+ uint32_t cmr;
146
+ uint32_t pdr;
147
+ uint32_t pwdr;
148
+
149
+ uint32_t freq;
150
+ uint32_t duty;
151
+} NPCM7xxPWM;
152
+
153
+/**
154
+ * struct NPCM7xxPWMState - Pulse Width Modulation device state.
155
+ * @parent: System bus device.
156
+ * @iomem: Memory region through which registers are accessed.
157
+ * @clock: The PWM clock.
158
+ * @pwm: The PWM channels owned by this module.
159
+ * @ppr: The prescaler register.
160
+ * @csr: The clock selector register.
161
+ * @pcr: The control register.
162
+ * @pier: The interrupt enable register.
163
+ * @piir: The interrupt indication register.
164
+ */
165
+struct NPCM7xxPWMState {
166
+ SysBusDevice parent;
167
+
168
+ MemoryRegion iomem;
169
+
170
+ Clock *clock;
171
+ NPCM7xxPWM pwm[NPCM7XX_PWM_PER_MODULE];
172
+
173
+ uint32_t ppr;
174
+ uint32_t csr;
175
+ uint32_t pcr;
176
+ uint32_t pier;
177
+ uint32_t piir;
178
+};
179
+
180
+#define TYPE_NPCM7XX_PWM "npcm7xx-pwm"
181
+#define NPCM7XX_PWM(obj) \
182
+ OBJECT_CHECK(NPCM7xxPWMState, (obj), TYPE_NPCM7XX_PWM)
183
+
184
+#endif /* NPCM7XX_PWM_H */
185
diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c
186
index XXXXXXX..XXXXXXX 100644
187
--- a/hw/arm/npcm7xx.c
188
+++ b/hw/arm/npcm7xx.c
189
@@ -XXX,XX +XXX,XX @@ enum NPCM7xxInterrupt {
190
NPCM7XX_WDG2_IRQ, /* Timer Module 2 Watchdog */
191
NPCM7XX_EHCI_IRQ = 61,
192
NPCM7XX_OHCI_IRQ = 62,
193
+ NPCM7XX_PWM0_IRQ = 93, /* PWM module 0 */
194
+ NPCM7XX_PWM1_IRQ, /* PWM module 1 */
195
NPCM7XX_GPIO0_IRQ = 116,
196
NPCM7XX_GPIO1_IRQ,
197
NPCM7XX_GPIO2_IRQ,
198
@@ -XXX,XX +XXX,XX @@ static const hwaddr npcm7xx_fiu3_flash_addr[] = {
199
0xb8000000, /* CS3 */
200
};
201
202
+/* Register base address for each PWM Module */
203
+static const hwaddr npcm7xx_pwm_addr[] = {
204
+ 0xf0103000,
205
+ 0xf0104000,
206
+};
207
+
208
static const struct {
209
hwaddr regs_addr;
210
uint32_t unconnected_pins;
211
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_init(Object *obj)
212
object_initialize_child(obj, npcm7xx_fiu[i].name, &s->fiu[i],
213
TYPE_NPCM7XX_FIU);
214
}
215
+
216
+ for (i = 0; i < ARRAY_SIZE(s->pwm); i++) {
217
+ object_initialize_child(obj, "pwm[*]", &s->pwm[i], TYPE_NPCM7XX_PWM);
218
+ }
219
}
220
221
static void npcm7xx_realize(DeviceState *dev, Error **errp)
222
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_realize(DeviceState *dev, Error **errp)
223
sysbus_connect_irq(SYS_BUS_DEVICE(&s->ohci), 0,
224
npcm7xx_irq(s, NPCM7XX_OHCI_IRQ));
225
226
+ /* PWM Modules. Cannot fail. */
227
+ QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_pwm_addr) != ARRAY_SIZE(s->pwm));
228
+ for (i = 0; i < ARRAY_SIZE(s->pwm); i++) {
229
+ SysBusDevice *sbd = SYS_BUS_DEVICE(&s->pwm[i]);
230
+
231
+ qdev_connect_clock_in(DEVICE(&s->pwm[i]), "clock", qdev_get_clock_out(
232
+ DEVICE(&s->clk), "apb3-clock"));
233
+ sysbus_realize(sbd, &error_abort);
234
+ sysbus_mmio_map(sbd, 0, npcm7xx_pwm_addr[i]);
235
+ sysbus_connect_irq(sbd, i, npcm7xx_irq(s, NPCM7XX_PWM0_IRQ + i));
236
+ }
237
+
238
/*
239
* Flash Interface Unit (FIU). Can fail if incorrect number of chip selects
240
* specified, but this is a programming error.
241
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_realize(DeviceState *dev, Error **errp)
242
create_unimplemented_device("npcm7xx.peci", 0xf0100000, 4 * KiB);
243
create_unimplemented_device("npcm7xx.siox[1]", 0xf0101000, 4 * KiB);
244
create_unimplemented_device("npcm7xx.siox[2]", 0xf0102000, 4 * KiB);
245
- create_unimplemented_device("npcm7xx.pwm[0]", 0xf0103000, 4 * KiB);
246
- create_unimplemented_device("npcm7xx.pwm[1]", 0xf0104000, 4 * KiB);
247
create_unimplemented_device("npcm7xx.mft[0]", 0xf0180000, 4 * KiB);
248
create_unimplemented_device("npcm7xx.mft[1]", 0xf0181000, 4 * KiB);
249
create_unimplemented_device("npcm7xx.mft[2]", 0xf0182000, 4 * KiB);
250
diff --git a/hw/misc/npcm7xx_pwm.c b/hw/misc/npcm7xx_pwm.c
251
new file mode 100644
252
index XXXXXXX..XXXXXXX
253
--- /dev/null
254
+++ b/hw/misc/npcm7xx_pwm.c
255
@@ -XXX,XX +XXX,XX @@
256
+/*
257
+ * Nuvoton NPCM7xx PWM Module
258
+ *
259
+ * Copyright 2020 Google LLC
260
+ *
261
+ * This program is free software; you can redistribute it and/or modify it
262
+ * under the terms of the GNU General Public License as published by the
263
+ * Free Software Foundation; either version 2 of the License, or
264
+ * (at your option) any later version.
265
+ *
266
+ * This program is distributed in the hope that it will be useful, but WITHOUT
267
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
268
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
269
+ * for more details.
270
+ */
271
+
272
+#include "qemu/osdep.h"
273
+#include "hw/irq.h"
274
+#include "hw/qdev-clock.h"
275
+#include "hw/qdev-properties.h"
276
+#include "hw/misc/npcm7xx_pwm.h"
277
+#include "hw/registerfields.h"
278
+#include "migration/vmstate.h"
279
+#include "qemu/bitops.h"
280
+#include "qemu/error-report.h"
281
+#include "qemu/log.h"
282
+#include "qemu/module.h"
283
+#include "qemu/units.h"
284
+#include "trace.h"
285
+
286
+REG32(NPCM7XX_PWM_PPR, 0x00);
287
+REG32(NPCM7XX_PWM_CSR, 0x04);
288
+REG32(NPCM7XX_PWM_PCR, 0x08);
289
+REG32(NPCM7XX_PWM_CNR0, 0x0c);
290
+REG32(NPCM7XX_PWM_CMR0, 0x10);
291
+REG32(NPCM7XX_PWM_PDR0, 0x14);
292
+REG32(NPCM7XX_PWM_CNR1, 0x18);
293
+REG32(NPCM7XX_PWM_CMR1, 0x1c);
294
+REG32(NPCM7XX_PWM_PDR1, 0x20);
295
+REG32(NPCM7XX_PWM_CNR2, 0x24);
296
+REG32(NPCM7XX_PWM_CMR2, 0x28);
297
+REG32(NPCM7XX_PWM_PDR2, 0x2c);
298
+REG32(NPCM7XX_PWM_CNR3, 0x30);
299
+REG32(NPCM7XX_PWM_CMR3, 0x34);
300
+REG32(NPCM7XX_PWM_PDR3, 0x38);
301
+REG32(NPCM7XX_PWM_PIER, 0x3c);
302
+REG32(NPCM7XX_PWM_PIIR, 0x40);
303
+REG32(NPCM7XX_PWM_PWDR0, 0x44);
304
+REG32(NPCM7XX_PWM_PWDR1, 0x48);
305
+REG32(NPCM7XX_PWM_PWDR2, 0x4c);
306
+REG32(NPCM7XX_PWM_PWDR3, 0x50);
307
+
308
+/* Register field definitions. */
309
+#define NPCM7XX_PPR(rv, index) extract32((rv), npcm7xx_ppr_base[index], 8)
310
+#define NPCM7XX_CSR(rv, index) extract32((rv), npcm7xx_csr_base[index], 3)
311
+#define NPCM7XX_CH(rv, index) extract32((rv), npcm7xx_ch_base[index], 4)
312
+#define NPCM7XX_CH_EN BIT(0)
313
+#define NPCM7XX_CH_INV BIT(2)
314
+#define NPCM7XX_CH_MOD BIT(3)
315
+
316
+/* Offset of each PWM channel's prescaler in the PPR register. */
317
+static const int npcm7xx_ppr_base[] = { 0, 0, 8, 8 };
318
+/* Offset of each PWM channel's clock selector in the CSR register. */
319
+static const int npcm7xx_csr_base[] = { 0, 4, 8, 12 };
320
+/* Offset of each PWM channel's control variable in the PCR register. */
321
+static const int npcm7xx_ch_base[] = { 0, 8, 12, 16 };
322
+
323
+static uint32_t npcm7xx_pwm_calculate_freq(NPCM7xxPWM *p)
324
+{
131
+{
325
+ uint32_t ppr;
132
+ int level = get_start_level(sl0, gran);
326
+ uint32_t csr;
133
+ uint64_t ipa_bits = 64 - t0sz;
327
+ uint32_t freq;
134
+ uint64_t max_ipa = (1ULL << ipa_bits) - 1;
328
+
135
+ int nr_concat = pgd_concat_idx(level, gran, max_ipa) + 1;
329
+ if (!p->running) {
136
+
330
+ return 0;
137
+ return nr_concat <= VMSA_MAX_S2_CONCAT;
331
+ }
332
+
333
+ csr = NPCM7XX_CSR(p->module->csr, p->index);
334
+ ppr = NPCM7XX_PPR(p->module->ppr, p->index);
335
+ freq = clock_get_hz(p->module->clock);
336
+ freq /= ppr + 1;
337
+ /* csr can only be 0~4 */
338
+ if (csr > 4) {
339
+ qemu_log_mask(LOG_GUEST_ERROR,
340
+ "%s: invalid csr value %u\n",
341
+ __func__, csr);
342
+ csr = 4;
343
+ }
344
+ /* freq won't be changed if csr == 4. */
345
+ if (csr < 4) {
346
+ freq >>= csr + 1;
347
+ }
348
+
349
+ return freq / (p->cnr + 1);
350
+}
138
+}
351
+
139
+
352
+static uint32_t npcm7xx_pwm_calculate_duty(NPCM7xxPWM *p)
140
+static int decode_ste_s2_cfg(SMMUTransCfg *cfg, STE *ste)
353
+{
141
+{
354
+ uint64_t duty;
142
+ cfg->stage = 2;
355
+
143
+
356
+ if (p->running) {
144
+ if (STE_S2AA64(ste) == 0x0) {
357
+ if (p->cnr == 0) {
145
+ qemu_log_mask(LOG_UNIMP,
358
+ duty = 0;
146
+ "SMMUv3 AArch32 tables not supported\n");
359
+ } else if (p->cmr >= p->cnr) {
360
+ duty = NPCM7XX_PWM_MAX_DUTY;
361
+ } else {
362
+ duty = NPCM7XX_PWM_MAX_DUTY * (p->cmr + 1) / (p->cnr + 1);
363
+ }
364
+ } else {
365
+ duty = 0;
366
+ }
367
+
368
+ if (p->inverted) {
369
+ duty = NPCM7XX_PWM_MAX_DUTY - duty;
370
+ }
371
+
372
+ return duty;
373
+}
374
+
375
+static void npcm7xx_pwm_update_freq(NPCM7xxPWM *p)
376
+{
377
+ uint32_t freq = npcm7xx_pwm_calculate_freq(p);
378
+
379
+ if (freq != p->freq) {
380
+ trace_npcm7xx_pwm_update_freq(DEVICE(p->module)->canonical_path,
381
+ p->index, p->freq, freq);
382
+ p->freq = freq;
383
+ }
384
+}
385
+
386
+static void npcm7xx_pwm_update_duty(NPCM7xxPWM *p)
387
+{
388
+ uint32_t duty = npcm7xx_pwm_calculate_duty(p);
389
+
390
+ if (duty != p->duty) {
391
+ trace_npcm7xx_pwm_update_duty(DEVICE(p->module)->canonical_path,
392
+ p->index, p->duty, duty);
393
+ p->duty = duty;
394
+ }
395
+}
396
+
397
+static void npcm7xx_pwm_update_output(NPCM7xxPWM *p)
398
+{
399
+ npcm7xx_pwm_update_freq(p);
400
+ npcm7xx_pwm_update_duty(p);
401
+}
402
+
403
+static void npcm7xx_pwm_write_ppr(NPCM7xxPWMState *s, uint32_t new_ppr)
404
+{
405
+ int i;
406
+ uint32_t old_ppr = s->ppr;
407
+
408
+ QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_ppr_base) != NPCM7XX_PWM_PER_MODULE);
409
+ s->ppr = new_ppr;
410
+ for (i = 0; i < NPCM7XX_PWM_PER_MODULE; ++i) {
411
+ if (NPCM7XX_PPR(old_ppr, i) != NPCM7XX_PPR(new_ppr, i)) {
412
+ npcm7xx_pwm_update_freq(&s->pwm[i]);
413
+ }
414
+ }
415
+}
416
+
417
+static void npcm7xx_pwm_write_csr(NPCM7xxPWMState *s, uint32_t new_csr)
418
+{
419
+ int i;
420
+ uint32_t old_csr = s->csr;
421
+
422
+ QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_csr_base) != NPCM7XX_PWM_PER_MODULE);
423
+ s->csr = new_csr;
424
+ for (i = 0; i < NPCM7XX_PWM_PER_MODULE; ++i) {
425
+ if (NPCM7XX_CSR(old_csr, i) != NPCM7XX_CSR(new_csr, i)) {
426
+ npcm7xx_pwm_update_freq(&s->pwm[i]);
427
+ }
428
+ }
429
+}
430
+
431
+static void npcm7xx_pwm_write_pcr(NPCM7xxPWMState *s, uint32_t new_pcr)
432
+{
433
+ int i;
434
+ bool inverted;
435
+ uint32_t pcr;
436
+ NPCM7xxPWM *p;
437
+
438
+ s->pcr = new_pcr;
439
+ QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_ch_base) != NPCM7XX_PWM_PER_MODULE);
440
+ for (i = 0; i < NPCM7XX_PWM_PER_MODULE; ++i) {
441
+ p = &s->pwm[i];
442
+ pcr = NPCM7XX_CH(new_pcr, i);
443
+ inverted = pcr & NPCM7XX_CH_INV;
444
+
445
+ /*
446
+ * We only run a PWM channel with toggle mode. Single-shot mode does not
447
+ * generate frequency and duty-cycle values.
448
+ */
449
+ if ((pcr & NPCM7XX_CH_EN) && (pcr & NPCM7XX_CH_MOD)) {
450
+ if (p->running) {
451
+ /* Re-run this PWM channel if inverted changed. */
452
+ if (p->inverted ^ inverted) {
453
+ p->inverted = inverted;
454
+ npcm7xx_pwm_update_duty(p);
455
+ }
456
+ } else {
457
+ /* Run this PWM channel. */
458
+ p->running = true;
459
+ p->inverted = inverted;
460
+ npcm7xx_pwm_update_output(p);
461
+ }
462
+ } else {
463
+ /* Clear this PWM channel. */
464
+ p->running = false;
465
+ p->inverted = inverted;
466
+ npcm7xx_pwm_update_output(p);
467
+ }
468
+ }
469
+
470
+}
471
+
472
+static hwaddr npcm7xx_cnr_index(hwaddr offset)
473
+{
474
+ switch (offset) {
475
+ case A_NPCM7XX_PWM_CNR0:
476
+ return 0;
477
+ case A_NPCM7XX_PWM_CNR1:
478
+ return 1;
479
+ case A_NPCM7XX_PWM_CNR2:
480
+ return 2;
481
+ case A_NPCM7XX_PWM_CNR3:
482
+ return 3;
483
+ default:
484
+ g_assert_not_reached();
147
+ g_assert_not_reached();
485
+ }
148
+ }
486
+}
149
+
487
+
150
+ switch (STE_S2TG(ste)) {
488
+static hwaddr npcm7xx_cmr_index(hwaddr offset)
151
+ case 0x0: /* 4KB */
489
+{
152
+ cfg->s2cfg.granule_sz = 12;
490
+ switch (offset) {
491
+ case A_NPCM7XX_PWM_CMR0:
492
+ return 0;
493
+ case A_NPCM7XX_PWM_CMR1:
494
+ return 1;
495
+ case A_NPCM7XX_PWM_CMR2:
496
+ return 2;
497
+ case A_NPCM7XX_PWM_CMR3:
498
+ return 3;
499
+ default:
500
+ g_assert_not_reached();
501
+ }
502
+}
503
+
504
+static hwaddr npcm7xx_pdr_index(hwaddr offset)
505
+{
506
+ switch (offset) {
507
+ case A_NPCM7XX_PWM_PDR0:
508
+ return 0;
509
+ case A_NPCM7XX_PWM_PDR1:
510
+ return 1;
511
+ case A_NPCM7XX_PWM_PDR2:
512
+ return 2;
513
+ case A_NPCM7XX_PWM_PDR3:
514
+ return 3;
515
+ default:
516
+ g_assert_not_reached();
517
+ }
518
+}
519
+
520
+static hwaddr npcm7xx_pwdr_index(hwaddr offset)
521
+{
522
+ switch (offset) {
523
+ case A_NPCM7XX_PWM_PWDR0:
524
+ return 0;
525
+ case A_NPCM7XX_PWM_PWDR1:
526
+ return 1;
527
+ case A_NPCM7XX_PWM_PWDR2:
528
+ return 2;
529
+ case A_NPCM7XX_PWM_PWDR3:
530
+ return 3;
531
+ default:
532
+ g_assert_not_reached();
533
+ }
534
+}
535
+
536
+static uint64_t npcm7xx_pwm_read(void *opaque, hwaddr offset, unsigned size)
537
+{
538
+ NPCM7xxPWMState *s = opaque;
539
+ uint64_t value = 0;
540
+
541
+ switch (offset) {
542
+ case A_NPCM7XX_PWM_CNR0:
543
+ case A_NPCM7XX_PWM_CNR1:
544
+ case A_NPCM7XX_PWM_CNR2:
545
+ case A_NPCM7XX_PWM_CNR3:
546
+ value = s->pwm[npcm7xx_cnr_index(offset)].cnr;
547
+ break;
153
+ break;
548
+
154
+ case 0x1: /* 64KB */
549
+ case A_NPCM7XX_PWM_CMR0:
155
+ cfg->s2cfg.granule_sz = 16;
550
+ case A_NPCM7XX_PWM_CMR1:
551
+ case A_NPCM7XX_PWM_CMR2:
552
+ case A_NPCM7XX_PWM_CMR3:
553
+ value = s->pwm[npcm7xx_cmr_index(offset)].cmr;
554
+ break;
156
+ break;
555
+
157
+ case 0x2: /* 16KB */
556
+ case A_NPCM7XX_PWM_PDR0:
158
+ cfg->s2cfg.granule_sz = 14;
557
+ case A_NPCM7XX_PWM_PDR1:
558
+ case A_NPCM7XX_PWM_PDR2:
559
+ case A_NPCM7XX_PWM_PDR3:
560
+ value = s->pwm[npcm7xx_pdr_index(offset)].pdr;
561
+ break;
159
+ break;
562
+
563
+ case A_NPCM7XX_PWM_PWDR0:
564
+ case A_NPCM7XX_PWM_PWDR1:
565
+ case A_NPCM7XX_PWM_PWDR2:
566
+ case A_NPCM7XX_PWM_PWDR3:
567
+ value = s->pwm[npcm7xx_pwdr_index(offset)].pwdr;
568
+ break;
569
+
570
+ case A_NPCM7XX_PWM_PPR:
571
+ value = s->ppr;
572
+ break;
573
+
574
+ case A_NPCM7XX_PWM_CSR:
575
+ value = s->csr;
576
+ break;
577
+
578
+ case A_NPCM7XX_PWM_PCR:
579
+ value = s->pcr;
580
+ break;
581
+
582
+ case A_NPCM7XX_PWM_PIER:
583
+ value = s->pier;
584
+ break;
585
+
586
+ case A_NPCM7XX_PWM_PIIR:
587
+ value = s->piir;
588
+ break;
589
+
590
+ default:
160
+ default:
591
+ qemu_log_mask(LOG_GUEST_ERROR,
161
+ qemu_log_mask(LOG_GUEST_ERROR,
592
+ "%s: invalid offset 0x%04" HWADDR_PRIx "\n",
162
+ "SMMUv3 bad STE S2TG: %x\n", STE_S2TG(ste));
593
+ __func__, offset);
163
+ goto bad_ste;
594
+ break;
164
+ }
595
+ }
165
+
596
+
166
+ cfg->s2cfg.vttb = STE_S2TTB(ste);
597
+ trace_npcm7xx_pwm_read(DEVICE(s)->canonical_path, offset, value);
167
+
598
+ return value;
168
+ cfg->s2cfg.sl0 = STE_S2SL0(ste);
169
+ /* FEAT_TTST not supported. */
170
+ if (cfg->s2cfg.sl0 == 0x3) {
171
+ qemu_log_mask(LOG_UNIMP, "SMMUv3 S2SL0 = 0x3 has no meaning!\n");
172
+ goto bad_ste;
173
+ }
174
+
175
+ /* For AA64, The effective S2PS size is capped to the OAS. */
176
+ cfg->s2cfg.eff_ps = oas2bits(MIN(STE_S2PS(ste), SMMU_IDR5_OAS));
177
+ /*
178
+ * It is ILLEGAL for the address in S2TTB to be outside the range
179
+ * described by the effective S2PS value.
180
+ */
181
+ if (cfg->s2cfg.vttb & ~(MAKE_64BIT_MASK(0, cfg->s2cfg.eff_ps))) {
182
+ qemu_log_mask(LOG_GUEST_ERROR,
183
+ "SMMUv3 S2TTB too large 0x%lx, effective PS %d bits\n",
184
+ cfg->s2cfg.vttb, cfg->s2cfg.eff_ps);
185
+ goto bad_ste;
186
+ }
187
+
188
+ cfg->s2cfg.tsz = STE_S2T0SZ(ste);
189
+
190
+ if (!s2t0sz_valid(cfg)) {
191
+ qemu_log_mask(LOG_GUEST_ERROR, "SMMUv3 bad STE S2T0SZ = %d\n",
192
+ cfg->s2cfg.tsz);
193
+ goto bad_ste;
194
+ }
195
+
196
+ if (!s2_pgtable_config_valid(cfg->s2cfg.sl0, cfg->s2cfg.tsz,
197
+ cfg->s2cfg.granule_sz)) {
198
+ qemu_log_mask(LOG_GUEST_ERROR,
199
+ "SMMUv3 STE stage 2 config not valid!\n");
200
+ goto bad_ste;
201
+ }
202
+
203
+ /* Only LE supported(IDR0.TTENDIAN). */
204
+ if (STE_S2ENDI(ste)) {
205
+ qemu_log_mask(LOG_GUEST_ERROR,
206
+ "SMMUv3 STE_S2ENDI only supports LE!\n");
207
+ goto bad_ste;
208
+ }
209
+
210
+ cfg->s2cfg.affd = STE_S2AFFD(ste);
211
+
212
+ cfg->s2cfg.record_faults = STE_S2R(ste);
213
+ /* As stall is not supported. */
214
+ if (STE_S2S(ste)) {
215
+ qemu_log_mask(LOG_UNIMP, "SMMUv3 Stall not implemented!\n");
216
+ goto bad_ste;
217
+ }
218
+
219
+ /* This is still here as stage 2 has not been fully enabled yet. */
220
+ qemu_log_mask(LOG_UNIMP, "SMMUv3 does not support stage 2 yet\n");
221
+ goto bad_ste;
222
+
223
+ return 0;
224
+
225
+bad_ste:
226
+ return -EINVAL;
599
+}
227
+}
600
+
228
+
601
+static void npcm7xx_pwm_write(void *opaque, hwaddr offset,
229
/* Returns < 0 in case of invalid STE, 0 otherwise */
602
+ uint64_t v, unsigned size)
230
static int decode_ste(SMMUv3State *s, SMMUTransCfg *cfg,
603
+{
231
STE *ste, SMMUEventInfo *event)
604
+ NPCM7xxPWMState *s = opaque;
232
{
605
+ NPCM7xxPWM *p;
233
uint32_t config;
606
+ uint32_t value = v;
234
+ int ret;
607
+
235
608
+ trace_npcm7xx_pwm_write(DEVICE(s)->canonical_path, offset, value);
236
if (!STE_VALID(ste)) {
609
+ switch (offset) {
237
if (!event->inval_ste_allowed) {
610
+ case A_NPCM7XX_PWM_CNR0:
238
@@ -XXX,XX +XXX,XX @@ static int decode_ste(SMMUv3State *s, SMMUTransCfg *cfg,
611
+ case A_NPCM7XX_PWM_CNR1:
239
return 0;
612
+ case A_NPCM7XX_PWM_CNR2:
240
}
613
+ case A_NPCM7XX_PWM_CNR3:
241
614
+ p = &s->pwm[npcm7xx_cnr_index(offset)];
242
- if (STE_CFG_S2_ENABLED(config)) {
615
+ p->cnr = value;
243
- qemu_log_mask(LOG_UNIMP, "SMMUv3 does not support stage 2 yet\n");
616
+ npcm7xx_pwm_update_output(p);
244
+ /*
617
+ break;
245
+ * If a stage is enabled in SW while not advertised, throw bad ste
618
+
246
+ * according to user manual(IHI0070E) "5.2 Stream Table Entry".
619
+ case A_NPCM7XX_PWM_CMR0:
247
+ */
620
+ case A_NPCM7XX_PWM_CMR1:
248
+ if (!STAGE1_SUPPORTED(s) && STE_CFG_S1_ENABLED(config)) {
621
+ case A_NPCM7XX_PWM_CMR2:
249
+ qemu_log_mask(LOG_GUEST_ERROR, "SMMUv3 S1 used but not supported.\n");
622
+ case A_NPCM7XX_PWM_CMR3:
250
goto bad_ste;
623
+ p = &s->pwm[npcm7xx_cmr_index(offset)];
251
}
624
+ p->cmr = value;
252
+ if (!STAGE2_SUPPORTED(s) && STE_CFG_S2_ENABLED(config)) {
625
+ npcm7xx_pwm_update_output(p);
253
+ qemu_log_mask(LOG_GUEST_ERROR, "SMMUv3 S2 used but not supported.\n");
626
+ break;
254
+ goto bad_ste;
627
+
255
+ }
628
+ case A_NPCM7XX_PWM_PDR0:
256
+
629
+ case A_NPCM7XX_PWM_PDR1:
257
+ if (STAGE2_SUPPORTED(s)) {
630
+ case A_NPCM7XX_PWM_PDR2:
258
+ /* VMID is considered even if s2 is disabled. */
631
+ case A_NPCM7XX_PWM_PDR3:
259
+ cfg->s2cfg.vmid = STE_S2VMID(ste);
632
+ qemu_log_mask(LOG_GUEST_ERROR,
260
+ } else {
633
+ "%s: register @ 0x%04" HWADDR_PRIx " is read-only\n",
261
+ /* Default to -1 */
634
+ __func__, offset);
262
+ cfg->s2cfg.vmid = -1;
635
+ break;
263
+ }
636
+
264
+
637
+ case A_NPCM7XX_PWM_PWDR0:
265
+ if (STE_CFG_S2_ENABLED(config)) {
638
+ case A_NPCM7XX_PWM_PWDR1:
266
+ /*
639
+ case A_NPCM7XX_PWM_PWDR2:
267
+ * Stage-1 OAS defaults to OAS even if not enabled as it would be used
640
+ case A_NPCM7XX_PWM_PWDR3:
268
+ * in input address check for stage-2.
641
+ qemu_log_mask(LOG_UNIMP,
269
+ */
642
+ "%s: register @ 0x%04" HWADDR_PRIx " is not implemented\n",
270
+ cfg->oas = oas2bits(SMMU_IDR5_OAS);
643
+ __func__, offset);
271
+ ret = decode_ste_s2_cfg(cfg, ste);
644
+ break;
272
+ if (ret) {
645
+
273
+ goto bad_ste;
646
+ case A_NPCM7XX_PWM_PPR:
274
+ }
647
+ npcm7xx_pwm_write_ppr(s, value);
275
+ }
648
+ break;
276
649
+
277
if (STE_S1CDMAX(ste) != 0) {
650
+ case A_NPCM7XX_PWM_CSR:
278
qemu_log_mask(LOG_UNIMP,
651
+ npcm7xx_pwm_write_csr(s, value);
279
@@ -XXX,XX +XXX,XX @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegion *mr, hwaddr addr,
652
+ break;
280
if (cached_entry) {
653
+
281
if ((flag & IOMMU_WO) && !(cached_entry->entry.perm & IOMMU_WO)) {
654
+ case A_NPCM7XX_PWM_PCR:
282
status = SMMU_TRANS_ERROR;
655
+ npcm7xx_pwm_write_pcr(s, value);
283
- if (cfg->record_faults) {
656
+ break;
284
+ /*
657
+
285
+ * We know that the TLB only contains either stage-1 or stage-2 as
658
+ case A_NPCM7XX_PWM_PIER:
286
+ * nesting is not supported. So it is sufficient to check the
659
+ qemu_log_mask(LOG_UNIMP,
287
+ * translation stage to know the TLB stage for now.
660
+ "%s: register @ 0x%04" HWADDR_PRIx " is not implemented\n",
288
+ */
661
+ __func__, offset);
289
+ event.u.f_walk_eabt.s2 = (cfg->stage == 2);
662
+ break;
290
+ if (PTW_RECORD_FAULT(cfg)) {
663
+
291
event.type = SMMU_EVT_F_PERMISSION;
664
+ case A_NPCM7XX_PWM_PIIR:
292
event.u.f_permission.addr = addr;
665
+ qemu_log_mask(LOG_UNIMP,
293
event.u.f_permission.rnw = flag & 0x1;
666
+ "%s: register @ 0x%04" HWADDR_PRIx " is not implemented\n",
294
@@ -XXX,XX +XXX,XX @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegion *mr, hwaddr addr,
667
+ __func__, offset);
295
event.u.f_walk_eabt.addr2 = ptw_info.addr;
668
+ break;
296
break;
669
+
297
case SMMU_PTW_ERR_TRANSLATION:
670
+ default:
298
- if (cfg->record_faults) {
671
+ qemu_log_mask(LOG_GUEST_ERROR,
299
+ if (PTW_RECORD_FAULT(cfg)) {
672
+ "%s: invalid offset 0x%04" HWADDR_PRIx "\n",
300
event.type = SMMU_EVT_F_TRANSLATION;
673
+ __func__, offset);
301
event.u.f_translation.addr = addr;
674
+ break;
302
event.u.f_translation.rnw = flag & 0x1;
675
+ }
303
}
676
+}
304
break;
677
+
305
case SMMU_PTW_ERR_ADDR_SIZE:
678
+static const struct MemoryRegionOps npcm7xx_pwm_ops = {
306
- if (cfg->record_faults) {
679
+ .read = npcm7xx_pwm_read,
307
+ if (PTW_RECORD_FAULT(cfg)) {
680
+ .write = npcm7xx_pwm_write,
308
event.type = SMMU_EVT_F_ADDR_SIZE;
681
+ .endianness = DEVICE_LITTLE_ENDIAN,
309
event.u.f_addr_size.addr = addr;
682
+ .valid = {
310
event.u.f_addr_size.rnw = flag & 0x1;
683
+ .min_access_size = 4,
311
}
684
+ .max_access_size = 4,
312
break;
685
+ .unaligned = false,
313
case SMMU_PTW_ERR_ACCESS:
686
+ },
314
- if (cfg->record_faults) {
687
+};
315
+ if (PTW_RECORD_FAULT(cfg)) {
688
+
316
event.type = SMMU_EVT_F_ACCESS;
689
+static void npcm7xx_pwm_enter_reset(Object *obj, ResetType type)
317
event.u.f_access.addr = addr;
690
+{
318
event.u.f_access.rnw = flag & 0x1;
691
+ NPCM7xxPWMState *s = NPCM7XX_PWM(obj);
319
}
692
+ int i;
320
break;
693
+
321
case SMMU_PTW_ERR_PERMISSION:
694
+ for (i = 0; i < NPCM7XX_PWM_PER_MODULE; i++) {
322
- if (cfg->record_faults) {
695
+ NPCM7xxPWM *p = &s->pwm[i];
323
+ if (PTW_RECORD_FAULT(cfg)) {
696
+
324
event.type = SMMU_EVT_F_PERMISSION;
697
+ p->cnr = 0x00000000;
325
event.u.f_permission.addr = addr;
698
+ p->cmr = 0x00000000;
326
event.u.f_permission.rnw = flag & 0x1;
699
+ p->pdr = 0x00000000;
700
+ p->pwdr = 0x00000000;
701
+ }
702
+
703
+ s->ppr = 0x00000000;
704
+ s->csr = 0x00000000;
705
+ s->pcr = 0x00000000;
706
+ s->pier = 0x00000000;
707
+ s->piir = 0x00000000;
708
+}
709
+
710
+static void npcm7xx_pwm_hold_reset(Object *obj)
711
+{
712
+ NPCM7xxPWMState *s = NPCM7XX_PWM(obj);
713
+ int i;
714
+
715
+ for (i = 0; i < NPCM7XX_PWM_PER_MODULE; i++) {
716
+ qemu_irq_lower(s->pwm[i].irq);
717
+ }
718
+}
719
+
720
+static void npcm7xx_pwm_init(Object *obj)
721
+{
722
+ NPCM7xxPWMState *s = NPCM7XX_PWM(obj);
723
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
724
+ int i;
725
+
726
+ for (i = 0; i < NPCM7XX_PWM_PER_MODULE; i++) {
727
+ NPCM7xxPWM *p = &s->pwm[i];
728
+ p->module = s;
729
+ p->index = i;
730
+ sysbus_init_irq(sbd, &p->irq);
731
+ }
732
+
733
+ memory_region_init_io(&s->iomem, obj, &npcm7xx_pwm_ops, s,
734
+ TYPE_NPCM7XX_PWM, 4 * KiB);
735
+ sysbus_init_mmio(sbd, &s->iomem);
736
+ s->clock = qdev_init_clock_in(DEVICE(s), "clock", NULL, NULL);
737
+
738
+ for (i = 0; i < NPCM7XX_PWM_PER_MODULE; ++i) {
739
+ object_property_add_uint32_ptr(obj, "freq[*]",
740
+ &s->pwm[i].freq, OBJ_PROP_FLAG_READ);
741
+ object_property_add_uint32_ptr(obj, "duty[*]",
742
+ &s->pwm[i].duty, OBJ_PROP_FLAG_READ);
743
+ }
744
+}
745
+
746
+static const VMStateDescription vmstate_npcm7xx_pwm = {
747
+ .name = "npcm7xx-pwm",
748
+ .version_id = 0,
749
+ .minimum_version_id = 0,
750
+ .fields = (VMStateField[]) {
751
+ VMSTATE_BOOL(running, NPCM7xxPWM),
752
+ VMSTATE_BOOL(inverted, NPCM7xxPWM),
753
+ VMSTATE_UINT8(index, NPCM7xxPWM),
754
+ VMSTATE_UINT32(cnr, NPCM7xxPWM),
755
+ VMSTATE_UINT32(cmr, NPCM7xxPWM),
756
+ VMSTATE_UINT32(pdr, NPCM7xxPWM),
757
+ VMSTATE_UINT32(pwdr, NPCM7xxPWM),
758
+ VMSTATE_UINT32(freq, NPCM7xxPWM),
759
+ VMSTATE_UINT32(duty, NPCM7xxPWM),
760
+ VMSTATE_END_OF_LIST(),
761
+ },
762
+};
763
+
764
+static const VMStateDescription vmstate_npcm7xx_pwm_module = {
765
+ .name = "npcm7xx-pwm-module",
766
+ .version_id = 0,
767
+ .minimum_version_id = 0,
768
+ .fields = (VMStateField[]) {
769
+ VMSTATE_CLOCK(clock, NPCM7xxPWMState),
770
+ VMSTATE_STRUCT_ARRAY(pwm, NPCM7xxPWMState,
771
+ NPCM7XX_PWM_PER_MODULE, 0, vmstate_npcm7xx_pwm,
772
+ NPCM7xxPWM),
773
+ VMSTATE_UINT32(ppr, NPCM7xxPWMState),
774
+ VMSTATE_UINT32(csr, NPCM7xxPWMState),
775
+ VMSTATE_UINT32(pcr, NPCM7xxPWMState),
776
+ VMSTATE_UINT32(pier, NPCM7xxPWMState),
777
+ VMSTATE_UINT32(piir, NPCM7xxPWMState),
778
+ VMSTATE_END_OF_LIST(),
779
+ },
780
+};
781
+
782
+static void npcm7xx_pwm_class_init(ObjectClass *klass, void *data)
783
+{
784
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
785
+ DeviceClass *dc = DEVICE_CLASS(klass);
786
+
787
+ dc->desc = "NPCM7xx PWM Controller";
788
+ dc->vmsd = &vmstate_npcm7xx_pwm_module;
789
+ rc->phases.enter = npcm7xx_pwm_enter_reset;
790
+ rc->phases.hold = npcm7xx_pwm_hold_reset;
791
+}
792
+
793
+static const TypeInfo npcm7xx_pwm_info = {
794
+ .name = TYPE_NPCM7XX_PWM,
795
+ .parent = TYPE_SYS_BUS_DEVICE,
796
+ .instance_size = sizeof(NPCM7xxPWMState),
797
+ .class_init = npcm7xx_pwm_class_init,
798
+ .instance_init = npcm7xx_pwm_init,
799
+};
800
+
801
+static void npcm7xx_pwm_register_type(void)
802
+{
803
+ type_register_static(&npcm7xx_pwm_info);
804
+}
805
+type_init(npcm7xx_pwm_register_type);
806
diff --git a/hw/misc/meson.build b/hw/misc/meson.build
807
index XXXXXXX..XXXXXXX 100644
808
--- a/hw/misc/meson.build
809
+++ b/hw/misc/meson.build
810
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_MAINSTONE', if_true: files('mst_fpga.c'))
811
softmmu_ss.add(when: 'CONFIG_NPCM7XX', if_true: files(
812
'npcm7xx_clk.c',
813
'npcm7xx_gcr.c',
814
+ 'npcm7xx_pwm.c',
815
'npcm7xx_rng.c',
816
))
817
softmmu_ss.add(when: 'CONFIG_OMAP', if_true: files(
818
diff --git a/hw/misc/trace-events b/hw/misc/trace-events
819
index XXXXXXX..XXXXXXX 100644
820
--- a/hw/misc/trace-events
821
+++ b/hw/misc/trace-events
822
@@ -XXX,XX +XXX,XX @@ npcm7xx_gcr_write(uint64_t offset, uint32_t value) "offset: 0x%04" PRIx64 " valu
823
npcm7xx_rng_read(uint64_t offset, uint64_t value, unsigned size) "offset: 0x%04" PRIx64 " value: 0x%02" PRIx64 " size: %u"
824
npcm7xx_rng_write(uint64_t offset, uint64_t value, unsigned size) "offset: 0x%04" PRIx64 " value: 0x%02" PRIx64 " size: %u"
825
826
+# npcm7xx_pwm.c
827
+npcm7xx_pwm_read(const char *id, uint64_t offset, uint32_t value) "%s offset: 0x%04" PRIx64 " value: 0x%08" PRIx32
828
+npcm7xx_pwm_write(const char *id, uint64_t offset, uint32_t value) "%s offset: 0x%04" PRIx64 " value: 0x%08" PRIx32
829
+npcm7xx_pwm_update_freq(const char *id, uint8_t index, uint32_t old_value, uint32_t new_value) "%s pwm[%u] Update Freq: old_freq: %u, new_freq: %u"
830
+npcm7xx_pwm_update_duty(const char *id, uint8_t index, uint32_t old_value, uint32_t new_value) "%s pwm[%u] Update Duty: old_duty: %u, new_duty: %u"
831
+
832
# stm32f4xx_syscfg.c
833
stm32f4xx_syscfg_set_irq(int gpio, int line, int level) "Interupt: GPIO: %d, Line: %d; Level: %d"
834
stm32f4xx_pulse_exti(int irq) "Pulse EXTI: %d"
835
--
327
--
836
2.20.1
328
2.34.1
837
838
diff view generated by jsdifflib
[PULL 08/21] target/arm: add aarch32 ID register fields to cpu.h
[PULL 07/21] hw/arm/smmuv3: Make TLB lookup work for stage-2
1
From: Leif Lindholm <leif@nuviainc.com>
1
From: Mostafa Saleh <smostafa@google.com>
2
2
3
Add entries present in ARM DDI 0487F.c (August 2020).
3
Right now, either stage-1 or stage-2 are supported, this simplifies
4
how we can deal with TLBs.
5
This patch makes TLB lookup work if stage-2 is enabled instead of
6
stage-1.
7
TLB lookup is done before a PTW, if a valid entry is found we won't
8
do the PTW.
9
To be able to do TLB lookup, we need the correct tagging info, as
10
granularity and input size, so we get this based on the supported
11
translation stage. The TLB entries are added correctly from each
12
stage PTW.
4
13
5
Signed-off-by: Leif Lindholm <leif@nuviainc.com>
14
When nested translation is supported, this would need to change, for
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
15
example if we go with a combined TLB implementation, we would need to
7
Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>
16
use the min of the granularities in TLB.
8
Message-id: 20210108185154.8108-7-leif@nuviainc.com
17
18
As stage-2 shouldn't be tagged by ASID, it will be set to -1 if S1P
19
is not enabled.
20
21
Signed-off-by: Mostafa Saleh <smostafa@google.com>
22
Reviewed-by: Eric Auger <eric.auger@redhat.com>
23
Tested-by: Eric Auger <eric.auger@redhat.com>
24
Tested-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
25
Message-id: 20230516203327.2051088-7-smostafa@google.com
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
26
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
27
---
11
target/arm/cpu.h | 28 ++++++++++++++++++++++++++++
28
hw/arm/smmuv3.c | 44 +++++++++++++++++++++++++++++++++-----------
12
1 file changed, 28 insertions(+)
29
1 file changed, 33 insertions(+), 11 deletions(-)
13
30
14
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
31
diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
15
index XXXXXXX..XXXXXXX 100644
32
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/cpu.h
33
--- a/hw/arm/smmuv3.c
17
+++ b/target/arm/cpu.h
34
+++ b/hw/arm/smmuv3.c
18
@@ -XXX,XX +XXX,XX @@ FIELD(ID_ISAR6, DP, 4, 4)
35
@@ -XXX,XX +XXX,XX @@ static int smmuv3_decode_config(IOMMUMemoryRegion *mr, SMMUTransCfg *cfg,
19
FIELD(ID_ISAR6, FHM, 8, 4)
36
STE ste;
20
FIELD(ID_ISAR6, SB, 12, 4)
37
CD cd;
21
FIELD(ID_ISAR6, SPECRES, 16, 4)
38
22
+FIELD(ID_ISAR6, BF16, 20, 4)
39
+ /* ASID defaults to -1 (if s1 is not supported). */
23
+FIELD(ID_ISAR6, I8MM, 24, 4)
40
+ cfg->asid = -1;
24
25
FIELD(ID_MMFR0, VMSA, 0, 4)
26
FIELD(ID_MMFR0, PMSA, 4, 4)
27
@@ -XXX,XX +XXX,XX @@ FIELD(ID_MMFR0, AUXREG, 20, 4)
28
FIELD(ID_MMFR0, FCSE, 24, 4)
29
FIELD(ID_MMFR0, INNERSHR, 28, 4)
30
31
+FIELD(ID_MMFR1, L1HVDVA, 0, 4)
32
+FIELD(ID_MMFR1, L1UNIVA, 4, 4)
33
+FIELD(ID_MMFR1, L1HVDSW, 8, 4)
34
+FIELD(ID_MMFR1, L1UNISW, 12, 4)
35
+FIELD(ID_MMFR1, L1HVD, 16, 4)
36
+FIELD(ID_MMFR1, L1UNI, 20, 4)
37
+FIELD(ID_MMFR1, L1TSTCLN, 24, 4)
38
+FIELD(ID_MMFR1, BPRED, 28, 4)
39
+
41
+
40
+FIELD(ID_MMFR2, L1HVDFG, 0, 4)
42
ret = smmu_find_ste(s, sid, &ste, event);
41
+FIELD(ID_MMFR2, L1HVDBG, 4, 4)
43
if (ret) {
42
+FIELD(ID_MMFR2, L1HVDRNG, 8, 4)
44
return ret;
43
+FIELD(ID_MMFR2, HVDTLB, 12, 4)
45
@@ -XXX,XX +XXX,XX @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegion *mr, hwaddr addr,
44
+FIELD(ID_MMFR2, UNITLB, 16, 4)
46
.addr_mask = ~(hwaddr)0,
45
+FIELD(ID_MMFR2, MEMBARR, 20, 4)
47
.perm = IOMMU_NONE,
46
+FIELD(ID_MMFR2, WFISTALL, 24, 4)
48
};
47
+FIELD(ID_MMFR2, HWACCFLG, 28, 4)
49
+ /*
48
+
50
+ * Combined attributes used for TLB lookup, as only one stage is supported,
49
FIELD(ID_MMFR3, CMAINTVA, 0, 4)
51
+ * it will hold attributes based on the enabled stage.
50
FIELD(ID_MMFR3, CMAINTSW, 4, 4)
52
+ */
51
FIELD(ID_MMFR3, BPMAINT, 8, 4)
53
+ SMMUTransTableInfo tt_combined;
52
@@ -XXX,XX +XXX,XX @@ FIELD(ID_MMFR4, LSM, 20, 4)
54
53
FIELD(ID_MMFR4, CCIDX, 24, 4)
55
qemu_mutex_lock(&s->mutex);
54
FIELD(ID_MMFR4, EVT, 28, 4)
56
55
57
@@ -XXX,XX +XXX,XX @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegion *mr, hwaddr addr,
56
+FIELD(ID_MMFR5, ETS, 0, 4)
58
goto epilogue;
57
+
59
}
58
FIELD(ID_PFR0, STATE0, 0, 4)
60
59
FIELD(ID_PFR0, STATE1, 4, 4)
61
- tt = select_tt(cfg, addr);
60
FIELD(ID_PFR0, STATE2, 8, 4)
62
- if (!tt) {
61
@@ -XXX,XX +XXX,XX @@ FIELD(ID_PFR1, SEC_FRAC, 20, 4)
63
- if (cfg->record_faults) {
62
FIELD(ID_PFR1, VIRT_FRAC, 24, 4)
64
- event.type = SMMU_EVT_F_TRANSLATION;
63
FIELD(ID_PFR1, GIC, 28, 4)
65
- event.u.f_translation.addr = addr;
64
66
- event.u.f_translation.rnw = flag & 0x1;
65
+FIELD(ID_PFR2, CSV3, 0, 4)
67
+ if (cfg->stage == 1) {
66
+FIELD(ID_PFR2, SSBS, 4, 4)
68
+ /* Select stage1 translation table. */
67
+FIELD(ID_PFR2, RAS_FRAC, 8, 4)
69
+ tt = select_tt(cfg, addr);
68
+
70
+ if (!tt) {
69
FIELD(ID_AA64ISAR0, AES, 4, 4)
71
+ if (cfg->record_faults) {
70
FIELD(ID_AA64ISAR0, SHA1, 8, 4)
72
+ event.type = SMMU_EVT_F_TRANSLATION;
71
FIELD(ID_AA64ISAR0, SHA2, 12, 4)
73
+ event.u.f_translation.addr = addr;
72
@@ -XXX,XX +XXX,XX @@ FIELD(ID_DFR0, MPROFDBG, 20, 4)
74
+ event.u.f_translation.rnw = flag & 0x1;
73
FIELD(ID_DFR0, PERFMON, 24, 4)
75
+ }
74
FIELD(ID_DFR0, TRACEFILT, 28, 4)
76
+ status = SMMU_TRANS_ERROR;
75
77
+ goto epilogue;
76
+FIELD(ID_DFR1, MTPMU, 0, 4)
78
}
77
+
79
- status = SMMU_TRANS_ERROR;
78
FIELD(DBGDIDR, SE_IMP, 12, 1)
80
- goto epilogue;
79
FIELD(DBGDIDR, NSUHD_IMP, 14, 1)
81
- }
80
FIELD(DBGDIDR, VERSION, 16, 4)
82
+ tt_combined.granule_sz = tt->granule_sz;
83
+ tt_combined.tsz = tt->tsz;
84
85
- page_mask = (1ULL << (tt->granule_sz)) - 1;
86
+ } else {
87
+ /* Stage2. */
88
+ tt_combined.granule_sz = cfg->s2cfg.granule_sz;
89
+ tt_combined.tsz = cfg->s2cfg.tsz;
90
+ }
91
+ /*
92
+ * TLB lookup looks for granule and input size for a translation stage,
93
+ * as only one stage is supported right now, choose the right values
94
+ * from the configuration.
95
+ */
96
+ page_mask = (1ULL << tt_combined.granule_sz) - 1;
97
aligned_addr = addr & ~page_mask;
98
99
- cached_entry = smmu_iotlb_lookup(bs, cfg, tt, aligned_addr);
100
+ cached_entry = smmu_iotlb_lookup(bs, cfg, &tt_combined, aligned_addr);
101
if (cached_entry) {
102
if ((flag & IOMMU_WO) && !(cached_entry->entry.perm & IOMMU_WO)) {
103
status = SMMU_TRANS_ERROR;
81
--
104
--
82
2.20.1
105
2.34.1
83
84
diff view generated by jsdifflib
[PULL 07/21] target/arm: add aarch64 ID register fields to cpu.h
[PULL 08/21] hw/arm/smmuv3: Add VMID to TLB tagging
1
From: Leif Lindholm <leif@nuviainc.com>
1
From: Mostafa Saleh <smostafa@google.com>
2
2
3
Add entries present in ARM DDI 0487F.c (August 2020).
3
Allow TLB to be tagged with VMID.
4
4
5
Signed-off-by: Leif Lindholm <leif@nuviainc.com>
5
If stage-1 is only supported, VMID is set to -1 and ignored from STE
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
and CMD_TLBI_NH* cmds.
7
Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>
7
8
Message-id: 20210108185154.8108-6-leif@nuviainc.com
8
Update smmu_iotlb_insert trace event to have vmid.
9
10
Signed-off-by: Mostafa Saleh <smostafa@google.com>
11
Reviewed-by: Eric Auger <eric.auger@redhat.com>
12
Tested-by: Eric Auger <eric.auger@redhat.com>
13
Tested-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
14
Message-id: 20230516203327.2051088-8-smostafa@google.com
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
16
---
11
target/arm/cpu.h | 15 +++++++++++++++
17
hw/arm/smmu-internal.h | 2 ++
12
1 file changed, 15 insertions(+)
18
include/hw/arm/smmu-common.h | 5 +++--
13
19
hw/arm/smmu-common.c | 36 ++++++++++++++++++++++--------------
14
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
20
hw/arm/smmuv3.c | 12 +++++++++---
15
index XXXXXXX..XXXXXXX 100644
21
hw/arm/trace-events | 6 +++---
16
--- a/target/arm/cpu.h
22
5 files changed, 39 insertions(+), 22 deletions(-)
17
+++ b/target/arm/cpu.h
23
18
@@ -XXX,XX +XXX,XX @@ FIELD(ID_AA64ISAR1, GPI, 28, 4)
24
diff --git a/hw/arm/smmu-internal.h b/hw/arm/smmu-internal.h
19
FIELD(ID_AA64ISAR1, FRINTTS, 32, 4)
25
index XXXXXXX..XXXXXXX 100644
20
FIELD(ID_AA64ISAR1, SB, 36, 4)
26
--- a/hw/arm/smmu-internal.h
21
FIELD(ID_AA64ISAR1, SPECRES, 40, 4)
27
+++ b/hw/arm/smmu-internal.h
22
+FIELD(ID_AA64ISAR1, BF16, 44, 4)
28
@@ -XXX,XX +XXX,XX @@ static inline int pgd_concat_idx(int start_level, int granule_sz,
23
+FIELD(ID_AA64ISAR1, DGH, 48, 4)
29
}
24
+FIELD(ID_AA64ISAR1, I8MM, 52, 4)
30
25
31
#define SMMU_IOTLB_ASID(key) ((key).asid)
26
FIELD(ID_AA64PFR0, EL0, 0, 4)
32
+#define SMMU_IOTLB_VMID(key) ((key).vmid)
27
FIELD(ID_AA64PFR0, EL1, 4, 4)
33
28
@@ -XXX,XX +XXX,XX @@ FIELD(ID_AA64PFR0, ADVSIMD, 20, 4)
34
typedef struct SMMUIOTLBPageInvInfo {
29
FIELD(ID_AA64PFR0, GIC, 24, 4)
35
int asid;
30
FIELD(ID_AA64PFR0, RAS, 28, 4)
36
+ int vmid;
31
FIELD(ID_AA64PFR0, SVE, 32, 4)
37
uint64_t iova;
32
+FIELD(ID_AA64PFR0, SEL2, 36, 4)
38
uint64_t mask;
33
+FIELD(ID_AA64PFR0, MPAM, 40, 4)
39
} SMMUIOTLBPageInvInfo;
34
+FIELD(ID_AA64PFR0, AMU, 44, 4)
40
diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h
35
+FIELD(ID_AA64PFR0, DIT, 48, 4)
41
index XXXXXXX..XXXXXXX 100644
36
+FIELD(ID_AA64PFR0, CSV2, 56, 4)
42
--- a/include/hw/arm/smmu-common.h
37
+FIELD(ID_AA64PFR0, CSV3, 60, 4)
43
+++ b/include/hw/arm/smmu-common.h
38
44
@@ -XXX,XX +XXX,XX @@ typedef struct SMMUPciBus {
39
FIELD(ID_AA64PFR1, BT, 0, 4)
45
typedef struct SMMUIOTLBKey {
40
FIELD(ID_AA64PFR1, SSBS, 4, 4)
46
uint64_t iova;
41
FIELD(ID_AA64PFR1, MTE, 8, 4)
47
uint16_t asid;
42
FIELD(ID_AA64PFR1, RAS_FRAC, 12, 4)
48
+ uint16_t vmid;
43
+FIELD(ID_AA64PFR1, MPAM_FRAC, 16, 4)
49
uint8_t tg;
44
50
uint8_t level;
45
FIELD(ID_AA64MMFR0, PARANGE, 0, 4)
51
} SMMUIOTLBKey;
46
FIELD(ID_AA64MMFR0, ASIDBITS, 4, 4)
52
@@ -XXX,XX +XXX,XX @@ IOMMUMemoryRegion *smmu_iommu_mr(SMMUState *s, uint32_t sid);
47
@@ -XXX,XX +XXX,XX @@ FIELD(ID_AA64MMFR0, TGRAN16_2, 32, 4)
53
SMMUTLBEntry *smmu_iotlb_lookup(SMMUState *bs, SMMUTransCfg *cfg,
48
FIELD(ID_AA64MMFR0, TGRAN64_2, 36, 4)
54
SMMUTransTableInfo *tt, hwaddr iova);
49
FIELD(ID_AA64MMFR0, TGRAN4_2, 40, 4)
55
void smmu_iotlb_insert(SMMUState *bs, SMMUTransCfg *cfg, SMMUTLBEntry *entry);
50
FIELD(ID_AA64MMFR0, EXS, 44, 4)
56
-SMMUIOTLBKey smmu_get_iotlb_key(uint16_t asid, uint64_t iova,
51
+FIELD(ID_AA64MMFR0, FGT, 56, 4)
57
+SMMUIOTLBKey smmu_get_iotlb_key(uint16_t asid, uint16_t vmid, uint64_t iova,
52
+FIELD(ID_AA64MMFR0, ECV, 60, 4)
58
uint8_t tg, uint8_t level);
53
59
void smmu_iotlb_inv_all(SMMUState *s);
54
FIELD(ID_AA64MMFR1, HAFDBS, 0, 4)
60
void smmu_iotlb_inv_asid(SMMUState *s, uint16_t asid);
55
FIELD(ID_AA64MMFR1, VMIDBITS, 4, 4)
61
-void smmu_iotlb_inv_iova(SMMUState *s, int asid, dma_addr_t iova,
56
@@ -XXX,XX +XXX,XX @@ FIELD(ID_AA64MMFR1, LO, 16, 4)
62
+void smmu_iotlb_inv_iova(SMMUState *s, int asid, int vmid, dma_addr_t iova,
57
FIELD(ID_AA64MMFR1, PAN, 20, 4)
63
uint8_t tg, uint64_t num_pages, uint8_t ttl);
58
FIELD(ID_AA64MMFR1, SPECSEI, 24, 4)
64
59
FIELD(ID_AA64MMFR1, XNX, 28, 4)
65
/* Unmap the range of all the notifiers registered to any IOMMU mr */
60
+FIELD(ID_AA64MMFR1, TWED, 32, 4)
66
diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c
61
+FIELD(ID_AA64MMFR1, ETS, 36, 4)
67
index XXXXXXX..XXXXXXX 100644
62
68
--- a/hw/arm/smmu-common.c
63
FIELD(ID_AA64MMFR2, CNP, 0, 4)
69
+++ b/hw/arm/smmu-common.c
64
FIELD(ID_AA64MMFR2, UAO, 4, 4)
70
@@ -XXX,XX +XXX,XX @@ static guint smmu_iotlb_key_hash(gconstpointer v)
65
@@ -XXX,XX +XXX,XX @@ FIELD(ID_AA64DFR0, CTX_CMPS, 28, 4)
71
66
FIELD(ID_AA64DFR0, PMSVER, 32, 4)
72
/* Jenkins hash */
67
FIELD(ID_AA64DFR0, DOUBLELOCK, 36, 4)
73
a = b = c = JHASH_INITVAL + sizeof(*key);
68
FIELD(ID_AA64DFR0, TRACEFILT, 40, 4)
74
- a += key->asid + key->level + key->tg;
69
+FIELD(ID_AA64DFR0, MTPMU, 48, 4)
75
+ a += key->asid + key->vmid + key->level + key->tg;
70
76
b += extract64(key->iova, 0, 32);
71
FIELD(ID_DFR0, COPDBG, 0, 4)
77
c += extract64(key->iova, 32, 32);
72
FIELD(ID_DFR0, COPSDBG, 4, 4)
78
79
@@ -XXX,XX +XXX,XX @@ static gboolean smmu_iotlb_key_equal(gconstpointer v1, gconstpointer v2)
80
SMMUIOTLBKey *k1 = (SMMUIOTLBKey *)v1, *k2 = (SMMUIOTLBKey *)v2;
81
82
return (k1->asid == k2->asid) && (k1->iova == k2->iova) &&
83
- (k1->level == k2->level) && (k1->tg == k2->tg);
84
+ (k1->level == k2->level) && (k1->tg == k2->tg) &&
85
+ (k1->vmid == k2->vmid);
86
}
87
88
-SMMUIOTLBKey smmu_get_iotlb_key(uint16_t asid, uint64_t iova,
89
+SMMUIOTLBKey smmu_get_iotlb_key(uint16_t asid, uint16_t vmid, uint64_t iova,
90
uint8_t tg, uint8_t level)
91
{
92
- SMMUIOTLBKey key = {.asid = asid, .iova = iova, .tg = tg, .level = level};
93
+ SMMUIOTLBKey key = {.asid = asid, .vmid = vmid, .iova = iova,
94
+ .tg = tg, .level = level};
95
96
return key;
97
}
98
@@ -XXX,XX +XXX,XX @@ SMMUTLBEntry *smmu_iotlb_lookup(SMMUState *bs, SMMUTransCfg *cfg,
99
uint64_t mask = subpage_size - 1;
100
SMMUIOTLBKey key;
101
102
- key = smmu_get_iotlb_key(cfg->asid, iova & ~mask, tg, level);
103
+ key = smmu_get_iotlb_key(cfg->asid, cfg->s2cfg.vmid,
104
+ iova & ~mask, tg, level);
105
entry = g_hash_table_lookup(bs->iotlb, &key);
106
if (entry) {
107
break;
108
@@ -XXX,XX +XXX,XX @@ SMMUTLBEntry *smmu_iotlb_lookup(SMMUState *bs, SMMUTransCfg *cfg,
109
110
if (entry) {
111
cfg->iotlb_hits++;
112
- trace_smmu_iotlb_lookup_hit(cfg->asid, iova,
113
+ trace_smmu_iotlb_lookup_hit(cfg->asid, cfg->s2cfg.vmid, iova,
114
cfg->iotlb_hits, cfg->iotlb_misses,
115
100 * cfg->iotlb_hits /
116
(cfg->iotlb_hits + cfg->iotlb_misses));
117
} else {
118
cfg->iotlb_misses++;
119
- trace_smmu_iotlb_lookup_miss(cfg->asid, iova,
120
+ trace_smmu_iotlb_lookup_miss(cfg->asid, cfg->s2cfg.vmid, iova,
121
cfg->iotlb_hits, cfg->iotlb_misses,
122
100 * cfg->iotlb_hits /
123
(cfg->iotlb_hits + cfg->iotlb_misses));
124
@@ -XXX,XX +XXX,XX @@ void smmu_iotlb_insert(SMMUState *bs, SMMUTransCfg *cfg, SMMUTLBEntry *new)
125
smmu_iotlb_inv_all(bs);
126
}
127
128
- *key = smmu_get_iotlb_key(cfg->asid, new->entry.iova, tg, new->level);
129
- trace_smmu_iotlb_insert(cfg->asid, new->entry.iova, tg, new->level);
130
+ *key = smmu_get_iotlb_key(cfg->asid, cfg->s2cfg.vmid, new->entry.iova,
131
+ tg, new->level);
132
+ trace_smmu_iotlb_insert(cfg->asid, cfg->s2cfg.vmid, new->entry.iova,
133
+ tg, new->level);
134
g_hash_table_insert(bs->iotlb, key, new);
135
}
136
137
@@ -XXX,XX +XXX,XX @@ static gboolean smmu_hash_remove_by_asid(gpointer key, gpointer value,
138
139
return SMMU_IOTLB_ASID(*iotlb_key) == asid;
140
}
141
-
142
-static gboolean smmu_hash_remove_by_asid_iova(gpointer key, gpointer value,
143
+static gboolean smmu_hash_remove_by_asid_vmid_iova(gpointer key, gpointer value,
144
gpointer user_data)
145
{
146
SMMUTLBEntry *iter = (SMMUTLBEntry *)value;
147
@@ -XXX,XX +XXX,XX @@ static gboolean smmu_hash_remove_by_asid_iova(gpointer key, gpointer value,
148
if (info->asid >= 0 && info->asid != SMMU_IOTLB_ASID(iotlb_key)) {
149
return false;
150
}
151
+ if (info->vmid >= 0 && info->vmid != SMMU_IOTLB_VMID(iotlb_key)) {
152
+ return false;
153
+ }
154
return ((info->iova & ~entry->addr_mask) == entry->iova) ||
155
((entry->iova & ~info->mask) == info->iova);
156
}
157
158
-void smmu_iotlb_inv_iova(SMMUState *s, int asid, dma_addr_t iova,
159
+void smmu_iotlb_inv_iova(SMMUState *s, int asid, int vmid, dma_addr_t iova,
160
uint8_t tg, uint64_t num_pages, uint8_t ttl)
161
{
162
/* if tg is not set we use 4KB range invalidation */
163
uint8_t granule = tg ? tg * 2 + 10 : 12;
164
165
if (ttl && (num_pages == 1) && (asid >= 0)) {
166
- SMMUIOTLBKey key = smmu_get_iotlb_key(asid, iova, tg, ttl);
167
+ SMMUIOTLBKey key = smmu_get_iotlb_key(asid, vmid, iova, tg, ttl);
168
169
if (g_hash_table_remove(s->iotlb, &key)) {
170
return;
171
@@ -XXX,XX +XXX,XX @@ void smmu_iotlb_inv_iova(SMMUState *s, int asid, dma_addr_t iova,
172
173
SMMUIOTLBPageInvInfo info = {
174
.asid = asid, .iova = iova,
175
+ .vmid = vmid,
176
.mask = (num_pages * 1 << granule) - 1};
177
178
g_hash_table_foreach_remove(s->iotlb,
179
- smmu_hash_remove_by_asid_iova,
180
+ smmu_hash_remove_by_asid_vmid_iova,
181
&info);
182
}
183
184
diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
185
index XXXXXXX..XXXXXXX 100644
186
--- a/hw/arm/smmuv3.c
187
+++ b/hw/arm/smmuv3.c
188
@@ -XXX,XX +XXX,XX @@ static void smmuv3_s1_range_inval(SMMUState *s, Cmd *cmd)
189
{
190
dma_addr_t end, addr = CMD_ADDR(cmd);
191
uint8_t type = CMD_TYPE(cmd);
192
- uint16_t vmid = CMD_VMID(cmd);
193
+ int vmid = -1;
194
uint8_t scale = CMD_SCALE(cmd);
195
uint8_t num = CMD_NUM(cmd);
196
uint8_t ttl = CMD_TTL(cmd);
197
@@ -XXX,XX +XXX,XX @@ static void smmuv3_s1_range_inval(SMMUState *s, Cmd *cmd)
198
uint64_t num_pages;
199
uint8_t granule;
200
int asid = -1;
201
+ SMMUv3State *smmuv3 = ARM_SMMUV3(s);
202
+
203
+ /* Only consider VMID if stage-2 is supported. */
204
+ if (STAGE2_SUPPORTED(smmuv3)) {
205
+ vmid = CMD_VMID(cmd);
206
+ }
207
208
if (type == SMMU_CMD_TLBI_NH_VA) {
209
asid = CMD_ASID(cmd);
210
@@ -XXX,XX +XXX,XX @@ static void smmuv3_s1_range_inval(SMMUState *s, Cmd *cmd)
211
if (!tg) {
212
trace_smmuv3_s1_range_inval(vmid, asid, addr, tg, 1, ttl, leaf);
213
smmuv3_inv_notifiers_iova(s, asid, addr, tg, 1);
214
- smmu_iotlb_inv_iova(s, asid, addr, tg, 1, ttl);
215
+ smmu_iotlb_inv_iova(s, asid, vmid, addr, tg, 1, ttl);
216
return;
217
}
218
219
@@ -XXX,XX +XXX,XX @@ static void smmuv3_s1_range_inval(SMMUState *s, Cmd *cmd)
220
num_pages = (mask + 1) >> granule;
221
trace_smmuv3_s1_range_inval(vmid, asid, addr, tg, num_pages, ttl, leaf);
222
smmuv3_inv_notifiers_iova(s, asid, addr, tg, num_pages);
223
- smmu_iotlb_inv_iova(s, asid, addr, tg, num_pages, ttl);
224
+ smmu_iotlb_inv_iova(s, asid, vmid, addr, tg, num_pages, ttl);
225
addr += mask + 1;
226
}
227
}
228
diff --git a/hw/arm/trace-events b/hw/arm/trace-events
229
index XXXXXXX..XXXXXXX 100644
230
--- a/hw/arm/trace-events
231
+++ b/hw/arm/trace-events
232
@@ -XXX,XX +XXX,XX @@ smmu_iotlb_inv_all(void) "IOTLB invalidate all"
233
smmu_iotlb_inv_asid(uint16_t asid) "IOTLB invalidate asid=%d"
234
smmu_iotlb_inv_iova(uint16_t asid, uint64_t addr) "IOTLB invalidate asid=%d addr=0x%"PRIx64
235
smmu_inv_notifiers_mr(const char *name) "iommu mr=%s"
236
-smmu_iotlb_lookup_hit(uint16_t asid, uint64_t addr, uint32_t hit, uint32_t miss, uint32_t p) "IOTLB cache HIT asid=%d addr=0x%"PRIx64" hit=%d miss=%d hit rate=%d"
237
-smmu_iotlb_lookup_miss(uint16_t asid, uint64_t addr, uint32_t hit, uint32_t miss, uint32_t p) "IOTLB cache MISS asid=%d addr=0x%"PRIx64" hit=%d miss=%d hit rate=%d"
238
-smmu_iotlb_insert(uint16_t asid, uint64_t addr, uint8_t tg, uint8_t level) "IOTLB ++ asid=%d addr=0x%"PRIx64" tg=%d level=%d"
239
+smmu_iotlb_lookup_hit(uint16_t asid, uint16_t vmid, uint64_t addr, uint32_t hit, uint32_t miss, uint32_t p) "IOTLB cache HIT asid=%d vmid=%d addr=0x%"PRIx64" hit=%d miss=%d hit rate=%d"
240
+smmu_iotlb_lookup_miss(uint16_t asid, uint16_t vmid, uint64_t addr, uint32_t hit, uint32_t miss, uint32_t p) "IOTLB cache MISS asid=%d vmid=%d addr=0x%"PRIx64" hit=%d miss=%d hit rate=%d"
241
+smmu_iotlb_insert(uint16_t asid, uint16_t vmid, uint64_t addr, uint8_t tg, uint8_t level) "IOTLB ++ asid=%d vmid=%d addr=0x%"PRIx64" tg=%d level=%d"
242
243
# smmuv3.c
244
smmuv3_read_mmio(uint64_t addr, uint64_t val, unsigned size, uint32_t r) "addr: 0x%"PRIx64" val:0x%"PRIx64" size: 0x%x(%d)"
73
--
245
--
74
2.20.1
246
2.34.1
75
76
diff view generated by jsdifflib
[PULL 20/21] hw/*: Use type casting for SysBusDevice in NPCM7XX
[PULL 09/21] hw/arm/smmuv3: Add CMDs related to stage-2
1
From: Hao Wu <wuhaotsh@google.com>
1
From: Mostafa Saleh <smostafa@google.com>
2
2
3
A device shouldn't access its parent object which is QOM internal.
3
CMD_TLBI_S2_IPA: As S1+S2 is not enabled, for now this can be the
4
Instead it should use type cast for this purporse. This patch fixes this
4
same as CMD_TLBI_NH_VAA.
5
issue for all NPCM7XX Devices.
5
6
6
CMD_TLBI_S12_VMALL: Added new function to invalidate TLB by VMID.
7
Signed-off-by: Hao Wu <wuhaotsh@google.com>
7
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
For stage-1 only commands, add a check to throw CERROR_ILL if used
9
Message-id: 20210108190945.949196-7-wuhaotsh@google.com
9
when stage-1 is not supported.
10
11
Reviewed-by: Eric Auger <eric.auger@redhat.com>
12
Signed-off-by: Mostafa Saleh <smostafa@google.com>
13
Tested-by: Eric Auger <eric.auger@redhat.com>
14
Tested-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
15
Message-id: 20230516203327.2051088-9-smostafa@google.com
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
17
---
12
hw/arm/npcm7xx_boards.c | 2 +-
18
include/hw/arm/smmu-common.h | 1 +
13
hw/mem/npcm7xx_mc.c | 2 +-
19
hw/arm/smmu-common.c | 16 +++++++++++
14
hw/misc/npcm7xx_clk.c | 2 +-
20
hw/arm/smmuv3.c | 55 ++++++++++++++++++++++++++++++------
15
hw/misc/npcm7xx_gcr.c | 2 +-
21
hw/arm/trace-events | 4 ++-
16
hw/misc/npcm7xx_rng.c | 2 +-
22
4 files changed, 67 insertions(+), 9 deletions(-)
17
hw/nvram/npcm7xx_otp.c | 2 +-
23
18
hw/ssi/npcm7xx_fiu.c | 2 +-
24
diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h
19
7 files changed, 7 insertions(+), 7 deletions(-)
25
index XXXXXXX..XXXXXXX 100644
20
26
--- a/include/hw/arm/smmu-common.h
21
diff --git a/hw/arm/npcm7xx_boards.c b/hw/arm/npcm7xx_boards.c
27
+++ b/include/hw/arm/smmu-common.h
22
index XXXXXXX..XXXXXXX 100644
28
@@ -XXX,XX +XXX,XX @@ SMMUIOTLBKey smmu_get_iotlb_key(uint16_t asid, uint16_t vmid, uint64_t iova,
23
--- a/hw/arm/npcm7xx_boards.c
29
uint8_t tg, uint8_t level);
24
+++ b/hw/arm/npcm7xx_boards.c
30
void smmu_iotlb_inv_all(SMMUState *s);
25
@@ -XXX,XX +XXX,XX @@ static NPCM7xxState *npcm7xx_create_soc(MachineState *machine,
31
void smmu_iotlb_inv_asid(SMMUState *s, uint16_t asid);
26
uint32_t hw_straps)
32
+void smmu_iotlb_inv_vmid(SMMUState *s, uint16_t vmid);
33
void smmu_iotlb_inv_iova(SMMUState *s, int asid, int vmid, dma_addr_t iova,
34
uint8_t tg, uint64_t num_pages, uint8_t ttl);
35
36
diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c
37
index XXXXXXX..XXXXXXX 100644
38
--- a/hw/arm/smmu-common.c
39
+++ b/hw/arm/smmu-common.c
40
@@ -XXX,XX +XXX,XX @@ static gboolean smmu_hash_remove_by_asid(gpointer key, gpointer value,
41
42
return SMMU_IOTLB_ASID(*iotlb_key) == asid;
43
}
44
+
45
+static gboolean smmu_hash_remove_by_vmid(gpointer key, gpointer value,
46
+ gpointer user_data)
47
+{
48
+ uint16_t vmid = *(uint16_t *)user_data;
49
+ SMMUIOTLBKey *iotlb_key = (SMMUIOTLBKey *)key;
50
+
51
+ return SMMU_IOTLB_VMID(*iotlb_key) == vmid;
52
+}
53
+
54
static gboolean smmu_hash_remove_by_asid_vmid_iova(gpointer key, gpointer value,
55
gpointer user_data)
27
{
56
{
28
NPCM7xxMachineClass *nmc = NPCM7XX_MACHINE_GET_CLASS(machine);
57
@@ -XXX,XX +XXX,XX @@ void smmu_iotlb_inv_asid(SMMUState *s, uint16_t asid)
29
- MachineClass *mc = &nmc->parent;
58
g_hash_table_foreach_remove(s->iotlb, smmu_hash_remove_by_asid, &asid);
30
+ MachineClass *mc = MACHINE_CLASS(nmc);
31
Object *obj;
32
33
if (strcmp(machine->cpu_type, mc->default_cpu_type) != 0) {
34
diff --git a/hw/mem/npcm7xx_mc.c b/hw/mem/npcm7xx_mc.c
35
index XXXXXXX..XXXXXXX 100644
36
--- a/hw/mem/npcm7xx_mc.c
37
+++ b/hw/mem/npcm7xx_mc.c
38
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_mc_realize(DeviceState *dev, Error **errp)
39
40
memory_region_init_io(&s->mmio, OBJECT(s), &npcm7xx_mc_ops, s, "regs",
41
NPCM7XX_MC_REGS_SIZE);
42
- sysbus_init_mmio(&s->parent, &s->mmio);
43
+ sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->mmio);
44
}
59
}
45
60
46
static void npcm7xx_mc_class_init(ObjectClass *klass, void *data)
61
+inline void smmu_iotlb_inv_vmid(SMMUState *s, uint16_t vmid)
47
diff --git a/hw/misc/npcm7xx_clk.c b/hw/misc/npcm7xx_clk.c
62
+{
48
index XXXXXXX..XXXXXXX 100644
63
+ trace_smmu_iotlb_inv_vmid(vmid);
49
--- a/hw/misc/npcm7xx_clk.c
64
+ g_hash_table_foreach_remove(s->iotlb, smmu_hash_remove_by_vmid, &vmid);
50
+++ b/hw/misc/npcm7xx_clk.c
65
+}
51
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_clk_init(Object *obj)
66
+
52
67
/* VMSAv8-64 Translation */
53
memory_region_init_io(&s->iomem, obj, &npcm7xx_clk_ops, s,
68
54
TYPE_NPCM7XX_CLK, 4 * KiB);
69
/**
55
- sysbus_init_mmio(&s->parent, &s->iomem);
70
diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
56
+ sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem);
71
index XXXXXXX..XXXXXXX 100644
72
--- a/hw/arm/smmuv3.c
73
+++ b/hw/arm/smmuv3.c
74
@@ -XXX,XX +XXX,XX @@ static void smmuv3_inv_notifiers_iova(SMMUState *s, int asid, dma_addr_t iova,
75
}
57
}
76
}
58
77
59
static int npcm7xx_clk_post_load(void *opaque, int version_id)
78
-static void smmuv3_s1_range_inval(SMMUState *s, Cmd *cmd)
60
diff --git a/hw/misc/npcm7xx_gcr.c b/hw/misc/npcm7xx_gcr.c
79
+static void smmuv3_range_inval(SMMUState *s, Cmd *cmd)
61
index XXXXXXX..XXXXXXX 100644
62
--- a/hw/misc/npcm7xx_gcr.c
63
+++ b/hw/misc/npcm7xx_gcr.c
64
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_gcr_init(Object *obj)
65
66
memory_region_init_io(&s->iomem, obj, &npcm7xx_gcr_ops, s,
67
TYPE_NPCM7XX_GCR, 4 * KiB);
68
- sysbus_init_mmio(&s->parent, &s->iomem);
69
+ sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem);
70
}
71
72
static const VMStateDescription vmstate_npcm7xx_gcr = {
73
diff --git a/hw/misc/npcm7xx_rng.c b/hw/misc/npcm7xx_rng.c
74
index XXXXXXX..XXXXXXX 100644
75
--- a/hw/misc/npcm7xx_rng.c
76
+++ b/hw/misc/npcm7xx_rng.c
77
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_rng_init(Object *obj)
78
79
memory_region_init_io(&s->iomem, obj, &npcm7xx_rng_ops, s, "regs",
80
NPCM7XX_RNG_REGS_SIZE);
81
- sysbus_init_mmio(&s->parent, &s->iomem);
82
+ sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem);
83
}
84
85
static const VMStateDescription vmstate_npcm7xx_rng = {
86
diff --git a/hw/nvram/npcm7xx_otp.c b/hw/nvram/npcm7xx_otp.c
87
index XXXXXXX..XXXXXXX 100644
88
--- a/hw/nvram/npcm7xx_otp.c
89
+++ b/hw/nvram/npcm7xx_otp.c
90
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_otp_realize(DeviceState *dev, Error **errp)
91
{
80
{
92
NPCM7xxOTPClass *oc = NPCM7XX_OTP_GET_CLASS(dev);
81
dma_addr_t end, addr = CMD_ADDR(cmd);
93
NPCM7xxOTPState *s = NPCM7XX_OTP(dev);
82
uint8_t type = CMD_TYPE(cmd);
94
- SysBusDevice *sbd = &s->parent;
83
@@ -XXX,XX +XXX,XX @@ static void smmuv3_s1_range_inval(SMMUState *s, Cmd *cmd)
95
+ SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
84
}
96
85
97
memset(s->array, 0, sizeof(s->array));
86
if (!tg) {
98
87
- trace_smmuv3_s1_range_inval(vmid, asid, addr, tg, 1, ttl, leaf);
99
diff --git a/hw/ssi/npcm7xx_fiu.c b/hw/ssi/npcm7xx_fiu.c
88
+ trace_smmuv3_range_inval(vmid, asid, addr, tg, 1, ttl, leaf);
100
index XXXXXXX..XXXXXXX 100644
89
smmuv3_inv_notifiers_iova(s, asid, addr, tg, 1);
101
--- a/hw/ssi/npcm7xx_fiu.c
90
smmu_iotlb_inv_iova(s, asid, vmid, addr, tg, 1, ttl);
102
+++ b/hw/ssi/npcm7xx_fiu.c
91
return;
103
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_fiu_hold_reset(Object *obj)
92
@@ -XXX,XX +XXX,XX @@ static void smmuv3_s1_range_inval(SMMUState *s, Cmd *cmd)
104
static void npcm7xx_fiu_realize(DeviceState *dev, Error **errp)
93
uint64_t mask = dma_aligned_pow2_mask(addr, end, 64);
105
{
94
106
NPCM7xxFIUState *s = NPCM7XX_FIU(dev);
95
num_pages = (mask + 1) >> granule;
107
- SysBusDevice *sbd = &s->parent;
96
- trace_smmuv3_s1_range_inval(vmid, asid, addr, tg, num_pages, ttl, leaf);
108
+ SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
97
+ trace_smmuv3_range_inval(vmid, asid, addr, tg, num_pages, ttl, leaf);
109
int i;
98
smmuv3_inv_notifiers_iova(s, asid, addr, tg, num_pages);
110
99
smmu_iotlb_inv_iova(s, asid, vmid, addr, tg, num_pages, ttl);
111
if (s->cs_count <= 0) {
100
addr += mask + 1;
101
@@ -XXX,XX +XXX,XX @@ static int smmuv3_cmdq_consume(SMMUv3State *s)
102
{
103
uint16_t asid = CMD_ASID(&cmd);
104
105
+ if (!STAGE1_SUPPORTED(s)) {
106
+ cmd_error = SMMU_CERROR_ILL;
107
+ break;
108
+ }
109
+
110
trace_smmuv3_cmdq_tlbi_nh_asid(asid);
111
smmu_inv_notifiers_all(&s->smmu_state);
112
smmu_iotlb_inv_asid(bs, asid);
113
break;
114
}
115
case SMMU_CMD_TLBI_NH_ALL:
116
+ if (!STAGE1_SUPPORTED(s)) {
117
+ cmd_error = SMMU_CERROR_ILL;
118
+ break;
119
+ }
120
+ QEMU_FALLTHROUGH;
121
case SMMU_CMD_TLBI_NSNH_ALL:
122
trace_smmuv3_cmdq_tlbi_nh();
123
smmu_inv_notifiers_all(&s->smmu_state);
124
@@ -XXX,XX +XXX,XX @@ static int smmuv3_cmdq_consume(SMMUv3State *s)
125
break;
126
case SMMU_CMD_TLBI_NH_VAA:
127
case SMMU_CMD_TLBI_NH_VA:
128
- smmuv3_s1_range_inval(bs, &cmd);
129
+ if (!STAGE1_SUPPORTED(s)) {
130
+ cmd_error = SMMU_CERROR_ILL;
131
+ break;
132
+ }
133
+ smmuv3_range_inval(bs, &cmd);
134
+ break;
135
+ case SMMU_CMD_TLBI_S12_VMALL:
136
+ {
137
+ uint16_t vmid = CMD_VMID(&cmd);
138
+
139
+ if (!STAGE2_SUPPORTED(s)) {
140
+ cmd_error = SMMU_CERROR_ILL;
141
+ break;
142
+ }
143
+
144
+ trace_smmuv3_cmdq_tlbi_s12_vmid(vmid);
145
+ smmu_inv_notifiers_all(&s->smmu_state);
146
+ smmu_iotlb_inv_vmid(bs, vmid);
147
+ break;
148
+ }
149
+ case SMMU_CMD_TLBI_S2_IPA:
150
+ if (!STAGE2_SUPPORTED(s)) {
151
+ cmd_error = SMMU_CERROR_ILL;
152
+ break;
153
+ }
154
+ /*
155
+ * As currently only either s1 or s2 are supported
156
+ * we can reuse same function for s2.
157
+ */
158
+ smmuv3_range_inval(bs, &cmd);
159
break;
160
case SMMU_CMD_TLBI_EL3_ALL:
161
case SMMU_CMD_TLBI_EL3_VA:
162
@@ -XXX,XX +XXX,XX @@ static int smmuv3_cmdq_consume(SMMUv3State *s)
163
case SMMU_CMD_TLBI_EL2_ASID:
164
case SMMU_CMD_TLBI_EL2_VA:
165
case SMMU_CMD_TLBI_EL2_VAA:
166
- case SMMU_CMD_TLBI_S12_VMALL:
167
- case SMMU_CMD_TLBI_S2_IPA:
168
case SMMU_CMD_ATC_INV:
169
case SMMU_CMD_PRI_RESP:
170
case SMMU_CMD_RESUME:
171
@@ -XXX,XX +XXX,XX @@ static int smmuv3_cmdq_consume(SMMUv3State *s)
172
break;
173
default:
174
cmd_error = SMMU_CERROR_ILL;
175
- qemu_log_mask(LOG_GUEST_ERROR,
176
- "Illegal command type: %d\n", CMD_TYPE(&cmd));
177
break;
178
}
179
qemu_mutex_unlock(&s->mutex);
180
if (cmd_error) {
181
+ if (cmd_error == SMMU_CERROR_ILL) {
182
+ qemu_log_mask(LOG_GUEST_ERROR,
183
+ "Illegal command type: %d\n", CMD_TYPE(&cmd));
184
+ }
185
break;
186
}
187
/*
188
diff --git a/hw/arm/trace-events b/hw/arm/trace-events
189
index XXXXXXX..XXXXXXX 100644
190
--- a/hw/arm/trace-events
191
+++ b/hw/arm/trace-events
192
@@ -XXX,XX +XXX,XX @@ smmu_ptw_block_pte(int stage, int level, uint64_t baseaddr, uint64_t pteaddr, ui
193
smmu_get_pte(uint64_t baseaddr, int index, uint64_t pteaddr, uint64_t pte) "baseaddr=0x%"PRIx64" index=0x%x, pteaddr=0x%"PRIx64", pte=0x%"PRIx64
194
smmu_iotlb_inv_all(void) "IOTLB invalidate all"
195
smmu_iotlb_inv_asid(uint16_t asid) "IOTLB invalidate asid=%d"
196
+smmu_iotlb_inv_vmid(uint16_t vmid) "IOTLB invalidate vmid=%d"
197
smmu_iotlb_inv_iova(uint16_t asid, uint64_t addr) "IOTLB invalidate asid=%d addr=0x%"PRIx64
198
smmu_inv_notifiers_mr(const char *name) "iommu mr=%s"
199
smmu_iotlb_lookup_hit(uint16_t asid, uint16_t vmid, uint64_t addr, uint32_t hit, uint32_t miss, uint32_t p) "IOTLB cache HIT asid=%d vmid=%d addr=0x%"PRIx64" hit=%d miss=%d hit rate=%d"
200
@@ -XXX,XX +XXX,XX @@ smmuv3_cmdq_cfgi_ste_range(int start, int end) "start=0x%x - end=0x%x"
201
smmuv3_cmdq_cfgi_cd(uint32_t sid) "sid=0x%x"
202
smmuv3_config_cache_hit(uint32_t sid, uint32_t hits, uint32_t misses, uint32_t perc) "Config cache HIT for sid=0x%x (hits=%d, misses=%d, hit rate=%d)"
203
smmuv3_config_cache_miss(uint32_t sid, uint32_t hits, uint32_t misses, uint32_t perc) "Config cache MISS for sid=0x%x (hits=%d, misses=%d, hit rate=%d)"
204
-smmuv3_s1_range_inval(int vmid, int asid, uint64_t addr, uint8_t tg, uint64_t num_pages, uint8_t ttl, bool leaf) "vmid=%d asid=%d addr=0x%"PRIx64" tg=%d num_pages=0x%"PRIx64" ttl=%d leaf=%d"
205
+smmuv3_range_inval(int vmid, int asid, uint64_t addr, uint8_t tg, uint64_t num_pages, uint8_t ttl, bool leaf) "vmid=%d asid=%d addr=0x%"PRIx64" tg=%d num_pages=0x%"PRIx64" ttl=%d leaf=%d"
206
smmuv3_cmdq_tlbi_nh(void) ""
207
smmuv3_cmdq_tlbi_nh_asid(uint16_t asid) "asid=%d"
208
+smmuv3_cmdq_tlbi_s12_vmid(uint16_t vmid) "vmid=%d"
209
smmuv3_config_cache_inv(uint32_t sid) "Config cache INV for sid=0x%x"
210
smmuv3_notify_flag_add(const char *iommu) "ADD SMMUNotifier node for iommu mr=%s"
211
smmuv3_notify_flag_del(const char *iommu) "DEL SMMUNotifier node for iommu mr=%s"
112
--
212
--
113
2.20.1
213
2.34.1
114
115
diff view generated by jsdifflib
[PULL 21/21] ui/cocoa: Fix openFile: deprecation on Big Sur
[PULL 10/21] hw/arm/smmuv3: Add stage-2 support in iova notifier
1
From: Roman Bolshakov <r.bolshakov@yadro.com>
1
From: Mostafa Saleh <smostafa@google.com>
2
2
3
ui/cocoa.m:1188:44: warning: 'openFile:' is deprecated: first deprecated in macOS 11.0 - Use -[NSWorkspace openURL:] instead.
3
In smmuv3_notify_iova, read the granule based on translation stage
4
[-Wdeprecated-declarations]
4
and use VMID if valid value is sent.
5
if ([[NSWorkspace sharedWorkspace] openFile: full_file_path] == YES) {
6
^
7
/Library/Developer/CommandLineTools/SDKs/MacOSX.sdk/System/Library/Frameworks/AppKit.framework/Headers/NSWorkspace.h:350:1: note:
8
'openFile:' has been explicitly marked deprecated here
9
- (BOOL)openFile:(NSString *)fullPath API_DEPRECATED("Use -[NSWorkspace openURL:] instead.", macos(10.0, 11.0));
10
^
11
5
12
Signed-off-by: Roman Bolshakov <r.bolshakov@yadro.com>
6
Signed-off-by: Mostafa Saleh <smostafa@google.com>
13
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Eric Auger <eric.auger@redhat.com>
14
Message-id: 20210102150718.47618-1-r.bolshakov@yadro.com
8
Tested-by: Eric Auger <eric.auger@redhat.com>
9
Tested-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
10
Message-id: 20230516203327.2051088-10-smostafa@google.com
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
---
12
---
17
ui/cocoa.m | 5 ++++-
13
hw/arm/smmuv3.c | 39 ++++++++++++++++++++++++++-------------
18
1 file changed, 4 insertions(+), 1 deletion(-)
14
hw/arm/trace-events | 2 +-
15
2 files changed, 27 insertions(+), 14 deletions(-)
19
16
20
diff --git a/ui/cocoa.m b/ui/cocoa.m
17
diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
21
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
22
--- a/ui/cocoa.m
19
--- a/hw/arm/smmuv3.c
23
+++ b/ui/cocoa.m
20
+++ b/hw/arm/smmuv3.c
24
@@ -XXX,XX +XXX,XX @@ QemuCocoaView *cocoaView;
21
@@ -XXX,XX +XXX,XX @@ epilogue:
25
/* Where to look for local files */
22
* @mr: IOMMU mr region handle
26
NSString *path_array[] = {@"../share/doc/qemu/", @"../doc/qemu/", @"docs/"};
23
* @n: notifier to be called
27
NSString *full_file_path;
24
* @asid: address space ID or negative value if we don't care
28
+ NSURL *full_file_url;
25
+ * @vmid: virtual machine ID or negative value if we don't care
29
26
* @iova: iova
30
/* iterate thru the possible paths until the file is found */
27
* @tg: translation granule (if communicated through range invalidation)
31
int index;
28
* @num_pages: number of @granule sized pages (if tg != 0), otherwise 1
32
@@ -XXX,XX +XXX,XX @@ QemuCocoaView *cocoaView;
29
*/
33
full_file_path = [full_file_path stringByDeletingLastPathComponent];
30
static void smmuv3_notify_iova(IOMMUMemoryRegion *mr,
34
full_file_path = [NSString stringWithFormat: @"%@/%@%@", full_file_path,
31
IOMMUNotifier *n,
35
path_array[index], filename];
32
- int asid, dma_addr_t iova,
36
- if ([[NSWorkspace sharedWorkspace] openFile: full_file_path] == YES) {
33
- uint8_t tg, uint64_t num_pages)
37
+ full_file_url = [NSURL fileURLWithPath: full_file_path
34
+ int asid, int vmid,
38
+ isDirectory: false];
35
+ dma_addr_t iova, uint8_t tg,
39
+ if ([[NSWorkspace sharedWorkspace] openURL: full_file_url] == YES) {
36
+ uint64_t num_pages)
37
{
38
SMMUDevice *sdev = container_of(mr, SMMUDevice, iommu);
39
IOMMUTLBEvent event;
40
uint8_t granule;
41
+ SMMUv3State *s = sdev->smmu;
42
43
if (!tg) {
44
SMMUEventInfo event = {.inval_ste_allowed = true};
45
@@ -XXX,XX +XXX,XX @@ static void smmuv3_notify_iova(IOMMUMemoryRegion *mr,
40
return;
46
return;
41
}
47
}
48
49
- tt = select_tt(cfg, iova);
50
- if (!tt) {
51
+ if (vmid >= 0 && cfg->s2cfg.vmid != vmid) {
52
return;
53
}
54
- granule = tt->granule_sz;
55
+
56
+ if (STAGE1_SUPPORTED(s)) {
57
+ tt = select_tt(cfg, iova);
58
+ if (!tt) {
59
+ return;
60
+ }
61
+ granule = tt->granule_sz;
62
+ } else {
63
+ granule = cfg->s2cfg.granule_sz;
64
+ }
65
+
66
} else {
67
granule = tg * 2 + 10;
42
}
68
}
69
@@ -XXX,XX +XXX,XX @@ static void smmuv3_notify_iova(IOMMUMemoryRegion *mr,
70
memory_region_notify_iommu_one(n, &event);
71
}
72
73
-/* invalidate an asid/iova range tuple in all mr's */
74
-static void smmuv3_inv_notifiers_iova(SMMUState *s, int asid, dma_addr_t iova,
75
- uint8_t tg, uint64_t num_pages)
76
+/* invalidate an asid/vmid/iova range tuple in all mr's */
77
+static void smmuv3_inv_notifiers_iova(SMMUState *s, int asid, int vmid,
78
+ dma_addr_t iova, uint8_t tg,
79
+ uint64_t num_pages)
80
{
81
SMMUDevice *sdev;
82
83
@@ -XXX,XX +XXX,XX @@ static void smmuv3_inv_notifiers_iova(SMMUState *s, int asid, dma_addr_t iova,
84
IOMMUMemoryRegion *mr = &sdev->iommu;
85
IOMMUNotifier *n;
86
87
- trace_smmuv3_inv_notifiers_iova(mr->parent_obj.name, asid, iova,
88
- tg, num_pages);
89
+ trace_smmuv3_inv_notifiers_iova(mr->parent_obj.name, asid, vmid,
90
+ iova, tg, num_pages);
91
92
IOMMU_NOTIFIER_FOREACH(n, mr) {
93
- smmuv3_notify_iova(mr, n, asid, iova, tg, num_pages);
94
+ smmuv3_notify_iova(mr, n, asid, vmid, iova, tg, num_pages);
95
}
96
}
97
}
98
@@ -XXX,XX +XXX,XX @@ static void smmuv3_range_inval(SMMUState *s, Cmd *cmd)
99
100
if (!tg) {
101
trace_smmuv3_range_inval(vmid, asid, addr, tg, 1, ttl, leaf);
102
- smmuv3_inv_notifiers_iova(s, asid, addr, tg, 1);
103
+ smmuv3_inv_notifiers_iova(s, asid, vmid, addr, tg, 1);
104
smmu_iotlb_inv_iova(s, asid, vmid, addr, tg, 1, ttl);
105
return;
106
}
107
@@ -XXX,XX +XXX,XX @@ static void smmuv3_range_inval(SMMUState *s, Cmd *cmd)
108
109
num_pages = (mask + 1) >> granule;
110
trace_smmuv3_range_inval(vmid, asid, addr, tg, num_pages, ttl, leaf);
111
- smmuv3_inv_notifiers_iova(s, asid, addr, tg, num_pages);
112
+ smmuv3_inv_notifiers_iova(s, asid, vmid, addr, tg, num_pages);
113
smmu_iotlb_inv_iova(s, asid, vmid, addr, tg, num_pages, ttl);
114
addr += mask + 1;
115
}
116
diff --git a/hw/arm/trace-events b/hw/arm/trace-events
117
index XXXXXXX..XXXXXXX 100644
118
--- a/hw/arm/trace-events
119
+++ b/hw/arm/trace-events
120
@@ -XXX,XX +XXX,XX @@ smmuv3_cmdq_tlbi_s12_vmid(uint16_t vmid) "vmid=%d"
121
smmuv3_config_cache_inv(uint32_t sid) "Config cache INV for sid=0x%x"
122
smmuv3_notify_flag_add(const char *iommu) "ADD SMMUNotifier node for iommu mr=%s"
123
smmuv3_notify_flag_del(const char *iommu) "DEL SMMUNotifier node for iommu mr=%s"
124
-smmuv3_inv_notifiers_iova(const char *name, uint16_t asid, uint64_t iova, uint8_t tg, uint64_t num_pages) "iommu mr=%s asid=%d iova=0x%"PRIx64" tg=%d num_pages=0x%"PRIx64
125
+smmuv3_inv_notifiers_iova(const char *name, uint16_t asid, uint16_t vmid, uint64_t iova, uint8_t tg, uint64_t num_pages) "iommu mr=%s asid=%d vmid=%d iova=0x%"PRIx64" tg=%d num_pages=0x%"PRIx64
126
43
--
127
--
44
2.20.1
128
2.34.1
45
46
diff view generated by jsdifflib
[PULL 17/21] hw/adc: Add an ADC module for NPCM7XX
[PULL 11/21] hw/arm/smmuv3: Add knob to choose translation stage and enable stage-2
1
From: Hao Wu <wuhaotsh@google.com>
1
From: Mostafa Saleh <smostafa@google.com>
2
2
3
The ADC is part of NPCM7XX Module. Its behavior is controled by the
3
As everything is in place, we can use a new system property to
4
ADC_CON register. It converts one of the eight analog inputs into a
4
advertise which stage is supported and remove bad_ste from STE
5
digital input and stores it in the ADC_DATA register when enabled.
5
stage2 config.
6
6
7
Users can alter input value by using qom-set QMP command.
7
The property added arm-smmuv3.stage can have 3 values:
8
- "1": Stage-1 only is advertised.
9
- "2": Stage-2 only is advertised.
8
10
9
Reviewed-by: Havard Skinnemoen <hskinnemoen@google.com>
11
If not passed or an unsupported value is passed, it will default to
10
Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
12
stage-1.
11
Signed-off-by: Hao Wu <wuhaotsh@google.com>
13
12
Message-id: 20210108190945.949196-4-wuhaotsh@google.com
14
Advertise VMID16.
13
[PMM: Added missing hw/adc/trace.h file]
15
14
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
16
Don't try to decode CD, if stage-2 is configured.
17
18
Reviewed-by: Eric Auger <eric.auger@redhat.com>
19
Signed-off-by: Mostafa Saleh <smostafa@google.com>
20
Tested-by: Eric Auger <eric.auger@redhat.com>
21
Tested-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
22
Message-id: 20230516203327.2051088-11-smostafa@google.com
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
23
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
---
24
---
17
docs/system/arm/nuvoton.rst | 2 +-
25
include/hw/arm/smmuv3.h | 1 +
18
meson.build | 1 +
26
hw/arm/smmuv3.c | 32 ++++++++++++++++++++++----------
19
hw/adc/trace.h | 1 +
27
2 files changed, 23 insertions(+), 10 deletions(-)
20
include/hw/adc/npcm7xx_adc.h | 69 ++++++
21
include/hw/arm/npcm7xx.h | 2 +
22
hw/adc/npcm7xx_adc.c | 301 ++++++++++++++++++++++++++
23
hw/arm/npcm7xx.c | 24 ++-
24
tests/qtest/npcm7xx_adc-test.c | 377 +++++++++++++++++++++++++++++++++
25
hw/adc/meson.build | 1 +
26
hw/adc/trace-events | 5 +
27
tests/qtest/meson.build | 3 +-
28
11 files changed, 783 insertions(+), 3 deletions(-)
29
create mode 100644 hw/adc/trace.h
30
create mode 100644 include/hw/adc/npcm7xx_adc.h
31
create mode 100644 hw/adc/npcm7xx_adc.c
32
create mode 100644 tests/qtest/npcm7xx_adc-test.c
33
create mode 100644 hw/adc/trace-events
34
28
35
diff --git a/docs/system/arm/nuvoton.rst b/docs/system/arm/nuvoton.rst
29
diff --git a/include/hw/arm/smmuv3.h b/include/hw/arm/smmuv3.h
36
index XXXXXXX..XXXXXXX 100644
30
index XXXXXXX..XXXXXXX 100644
37
--- a/docs/system/arm/nuvoton.rst
31
--- a/include/hw/arm/smmuv3.h
38
+++ b/docs/system/arm/nuvoton.rst
32
+++ b/include/hw/arm/smmuv3.h
39
@@ -XXX,XX +XXX,XX @@ Supported devices
33
@@ -XXX,XX +XXX,XX @@ struct SMMUv3State {
40
* Random Number Generator (RNG)
34
41
* USB host (USBH)
35
qemu_irq irq[4];
42
* GPIO controller
36
QemuMutex mutex;
43
+ * Analog to Digital Converter (ADC)
37
+ char *stage;
44
38
};
45
Missing devices
39
46
---------------
40
typedef enum {
47
@@ -XXX,XX +XXX,XX @@ Missing devices
41
diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
48
* USB device (USBD)
49
* SMBus controller (SMBF)
50
* Peripheral SPI controller (PSPI)
51
- * Analog to Digital Converter (ADC)
52
* SD/MMC host
53
* PECI interface
54
* Pulse Width Modulation (PWM)
55
diff --git a/meson.build b/meson.build
56
index XXXXXXX..XXXXXXX 100644
42
index XXXXXXX..XXXXXXX 100644
57
--- a/meson.build
43
--- a/hw/arm/smmuv3.c
58
+++ b/meson.build
44
+++ b/hw/arm/smmuv3.c
59
@@ -XXX,XX +XXX,XX @@ if have_system
60
'chardev',
61
'hw/9pfs',
62
'hw/acpi',
63
+ 'hw/adc',
64
'hw/alpha',
65
'hw/arm',
66
'hw/audio',
67
diff --git a/hw/adc/trace.h b/hw/adc/trace.h
68
new file mode 100644
69
index XXXXXXX..XXXXXXX
70
--- /dev/null
71
+++ b/hw/adc/trace.h
72
@@ -0,0 +1 @@
73
+#include "trace/trace-hw_adc.h"
74
diff --git a/include/hw/adc/npcm7xx_adc.h b/include/hw/adc/npcm7xx_adc.h
75
new file mode 100644
76
index XXXXXXX..XXXXXXX
77
--- /dev/null
78
+++ b/include/hw/adc/npcm7xx_adc.h
79
@@ -XXX,XX +XXX,XX @@
45
@@ -XXX,XX +XXX,XX @@
80
+/*
46
#include "hw/irq.h"
81
+ * Nuvoton NPCM7xx ADC Module
47
#include "hw/sysbus.h"
82
+ *
48
#include "migration/vmstate.h"
83
+ * Copyright 2020 Google LLC
84
+ *
85
+ * This program is free software; you can redistribute it and/or modify it
86
+ * under the terms of the GNU General Public License as published by the
87
+ * Free Software Foundation; either version 2 of the License, or
88
+ * (at your option) any later version.
89
+ *
90
+ * This program is distributed in the hope that it will be useful, but WITHOUT
91
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
92
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
93
+ * for more details.
94
+ */
95
+#ifndef NPCM7XX_ADC_H
96
+#define NPCM7XX_ADC_H
97
+
98
+#include "hw/clock.h"
99
+#include "hw/irq.h"
100
+#include "hw/sysbus.h"
101
+#include "qemu/timer.h"
102
+
103
+#define NPCM7XX_ADC_NUM_INPUTS 8
104
+/**
105
+ * This value should not be changed unless write_adc_calibration function in
106
+ * hw/arm/npcm7xx.c is also changed.
107
+ */
108
+#define NPCM7XX_ADC_NUM_CALIB 2
109
+
110
+/**
111
+ * struct NPCM7xxADCState - Analog to Digital Converter Module device state.
112
+ * @parent: System bus device.
113
+ * @iomem: Memory region through which registers are accessed.
114
+ * @conv_timer: The timer counts down remaining cycles for the conversion.
115
+ * @irq: GIC interrupt line to fire on expiration (if enabled).
116
+ * @con: The Control Register.
117
+ * @data: The Data Buffer.
118
+ * @clock: The ADC Clock.
119
+ * @adci: The input voltage in units of uV. 1uv = 1e-6V.
120
+ * @vref: The external reference voltage.
121
+ * @iref: The internal reference voltage, initialized at launch time.
122
+ * @rv: The calibrated output values of 0.5V and 1.5V for the ADC.
123
+ */
124
+typedef struct {
125
+ SysBusDevice parent;
126
+
127
+ MemoryRegion iomem;
128
+
129
+ QEMUTimer conv_timer;
130
+
131
+ qemu_irq irq;
132
+ uint32_t con;
133
+ uint32_t data;
134
+ Clock *clock;
135
+
136
+ /* Voltages are in unit of uV. 1V = 1000000uV. */
137
+ uint32_t adci[NPCM7XX_ADC_NUM_INPUTS];
138
+ uint32_t vref;
139
+ uint32_t iref;
140
+
141
+ uint16_t calibration_r_values[NPCM7XX_ADC_NUM_CALIB];
142
+} NPCM7xxADCState;
143
+
144
+#define TYPE_NPCM7XX_ADC "npcm7xx-adc"
145
+#define NPCM7XX_ADC(obj) \
146
+ OBJECT_CHECK(NPCM7xxADCState, (obj), TYPE_NPCM7XX_ADC)
147
+
148
+#endif /* NPCM7XX_ADC_H */
149
diff --git a/include/hw/arm/npcm7xx.h b/include/hw/arm/npcm7xx.h
150
index XXXXXXX..XXXXXXX 100644
151
--- a/include/hw/arm/npcm7xx.h
152
+++ b/include/hw/arm/npcm7xx.h
153
@@ -XXX,XX +XXX,XX @@
154
#define NPCM7XX_H
155
156
#include "hw/boards.h"
157
+#include "hw/adc/npcm7xx_adc.h"
158
#include "hw/cpu/a9mpcore.h"
159
#include "hw/gpio/npcm7xx_gpio.h"
160
#include "hw/mem/npcm7xx_mc.h"
161
@@ -XXX,XX +XXX,XX @@ typedef struct NPCM7xxState {
162
NPCM7xxGCRState gcr;
163
NPCM7xxCLKState clk;
164
NPCM7xxTimerCtrlState tim[3];
165
+ NPCM7xxADCState adc;
166
NPCM7xxOTPState key_storage;
167
NPCM7xxOTPState fuse_array;
168
NPCM7xxMCState mc;
169
diff --git a/hw/adc/npcm7xx_adc.c b/hw/adc/npcm7xx_adc.c
170
new file mode 100644
171
index XXXXXXX..XXXXXXX
172
--- /dev/null
173
+++ b/hw/adc/npcm7xx_adc.c
174
@@ -XXX,XX +XXX,XX @@
175
+/*
176
+ * Nuvoton NPCM7xx ADC Module
177
+ *
178
+ * Copyright 2020 Google LLC
179
+ *
180
+ * This program is free software; you can redistribute it and/or modify it
181
+ * under the terms of the GNU General Public License as published by the
182
+ * Free Software Foundation; either version 2 of the License, or
183
+ * (at your option) any later version.
184
+ *
185
+ * This program is distributed in the hope that it will be useful, but WITHOUT
186
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
187
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
188
+ * for more details.
189
+ */
190
+
191
+#include "qemu/osdep.h"
192
+#include "hw/adc/npcm7xx_adc.h"
193
+#include "hw/qdev-clock.h"
194
+#include "hw/qdev-properties.h"
49
+#include "hw/qdev-properties.h"
195
+#include "hw/registerfields.h"
50
#include "hw/qdev-core.h"
196
+#include "migration/vmstate.h"
51
#include "hw/pci/pci.h"
197
+#include "qemu/log.h"
52
#include "cpu.h"
198
+#include "qemu/module.h"
53
@@ -XXX,XX +XXX,XX @@ void smmuv3_record_event(SMMUv3State *s, SMMUEventInfo *info)
199
+#include "qemu/timer.h"
54
200
+#include "qemu/units.h"
55
static void smmuv3_init_regs(SMMUv3State *s)
201
+#include "trace.h"
56
{
202
+
57
- /**
203
+REG32(NPCM7XX_ADC_CON, 0x0)
58
- * IDR0: stage1 only, AArch64 only, coherent access, 16b ASID,
204
+REG32(NPCM7XX_ADC_DATA, 0x4)
59
- * multi-level stream table
205
+
60
- */
206
+/* Register field definitions. */
61
- s->idr[0] = FIELD_DP32(s->idr[0], IDR0, S1P, 1); /* stage 1 supported */
207
+#define NPCM7XX_ADC_CON_MUX(rv) extract32(rv, 24, 4)
62
+ /* Based on sys property, the stages supported in smmu will be advertised.*/
208
+#define NPCM7XX_ADC_CON_INT_EN BIT(21)
63
+ if (s->stage && !strcmp("2", s->stage)) {
209
+#define NPCM7XX_ADC_CON_REFSEL BIT(19)
64
+ s->idr[0] = FIELD_DP32(s->idr[0], IDR0, S2P, 1);
210
+#define NPCM7XX_ADC_CON_INT BIT(18)
65
+ } else {
211
+#define NPCM7XX_ADC_CON_EN BIT(17)
66
+ s->idr[0] = FIELD_DP32(s->idr[0], IDR0, S1P, 1);
212
+#define NPCM7XX_ADC_CON_RST BIT(16)
213
+#define NPCM7XX_ADC_CON_CONV BIT(14)
214
+#define NPCM7XX_ADC_CON_DIV(rv) extract32(rv, 1, 8)
215
+
216
+#define NPCM7XX_ADC_MAX_RESULT 1023
217
+#define NPCM7XX_ADC_DEFAULT_IREF 2000000
218
+#define NPCM7XX_ADC_CONV_CYCLES 20
219
+#define NPCM7XX_ADC_RESET_CYCLES 10
220
+#define NPCM7XX_ADC_R0_INPUT 500000
221
+#define NPCM7XX_ADC_R1_INPUT 1500000
222
+
223
+static void npcm7xx_adc_reset(NPCM7xxADCState *s)
224
+{
225
+ timer_del(&s->conv_timer);
226
+ s->con = 0x000c0001;
227
+ s->data = 0x00000000;
228
+}
229
+
230
+static uint32_t npcm7xx_adc_convert(uint32_t input, uint32_t ref)
231
+{
232
+ uint32_t result;
233
+
234
+ result = input * (NPCM7XX_ADC_MAX_RESULT + 1) / ref;
235
+ if (result > NPCM7XX_ADC_MAX_RESULT) {
236
+ result = NPCM7XX_ADC_MAX_RESULT;
237
+ }
67
+ }
238
+
68
+
239
+ return result;
69
s->idr[0] = FIELD_DP32(s->idr[0], IDR0, TTF, 2); /* AArch64 PTW only */
240
+}
70
s->idr[0] = FIELD_DP32(s->idr[0], IDR0, COHACC, 1); /* IO coherent */
241
+
71
s->idr[0] = FIELD_DP32(s->idr[0], IDR0, ASID16, 1); /* 16-bit ASID */
242
+static uint32_t npcm7xx_adc_prescaler(NPCM7xxADCState *s)
72
+ s->idr[0] = FIELD_DP32(s->idr[0], IDR0, VMID16, 1); /* 16-bit VMID */
243
+{
73
s->idr[0] = FIELD_DP32(s->idr[0], IDR0, TTENDIAN, 2); /* little endian */
244
+ return 2 * (NPCM7XX_ADC_CON_DIV(s->con) + 1);
74
s->idr[0] = FIELD_DP32(s->idr[0], IDR0, STALL_MODEL, 1); /* No stall */
245
+}
75
/* terminated transaction will always be aborted/error returned */
246
+
76
@@ -XXX,XX +XXX,XX @@ static int decode_ste_s2_cfg(SMMUTransCfg *cfg, STE *ste)
247
+static void npcm7xx_adc_start_timer(Clock *clk, QEMUTimer *timer,
77
goto bad_ste;
248
+ uint32_t cycles, uint32_t prescaler)
78
}
249
+{
79
250
+ int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
80
- /* This is still here as stage 2 has not been fully enabled yet. */
251
+ int64_t ticks = cycles;
81
- qemu_log_mask(LOG_UNIMP, "SMMUv3 does not support stage 2 yet\n");
252
+ int64_t ns;
82
- goto bad_ste;
253
+
83
-
254
+ ticks *= prescaler;
84
return 0;
255
+ ns = clock_ticks_to_ns(clk, ticks);
85
256
+ ns += now;
86
bad_ste:
257
+ timer_mod(timer, ns);
87
@@ -XXX,XX +XXX,XX @@ static int smmuv3_decode_config(IOMMUMemoryRegion *mr, SMMUTransCfg *cfg,
258
+}
88
return ret;
259
+
89
}
260
+static void npcm7xx_adc_start_convert(NPCM7xxADCState *s)
90
261
+{
91
- if (cfg->aborted || cfg->bypassed) {
262
+ uint32_t prescaler = npcm7xx_adc_prescaler(s);
92
+ if (cfg->aborted || cfg->bypassed || (cfg->stage == 2)) {
263
+
93
return 0;
264
+ npcm7xx_adc_start_timer(s->clock, &s->conv_timer, NPCM7XX_ADC_CONV_CYCLES,
94
}
265
+ prescaler);
95
266
+}
96
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_smmuv3 = {
267
+
97
}
268
+static void npcm7xx_adc_convert_done(void *opaque)
98
};
269
+{
99
270
+ NPCM7xxADCState *s = opaque;
100
+static Property smmuv3_properties[] = {
271
+ uint32_t input = NPCM7XX_ADC_CON_MUX(s->con);
101
+ /*
272
+ uint32_t ref = (s->con & NPCM7XX_ADC_CON_REFSEL)
102
+ * Stages of translation advertised.
273
+ ? s->iref : s->vref;
103
+ * "1": Stage 1
274
+
104
+ * "2": Stage 2
275
+ if (input >= NPCM7XX_ADC_NUM_INPUTS) {
105
+ * Defaults to stage 1
276
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid input: %u\n",
106
+ */
277
+ __func__, input);
107
+ DEFINE_PROP_STRING("stage", SMMUv3State, stage),
278
+ return;
108
+ DEFINE_PROP_END_OF_LIST()
279
+ }
280
+ s->data = npcm7xx_adc_convert(s->adci[input], ref);
281
+ if (s->con & NPCM7XX_ADC_CON_INT_EN) {
282
+ s->con |= NPCM7XX_ADC_CON_INT;
283
+ qemu_irq_raise(s->irq);
284
+ }
285
+ s->con &= ~NPCM7XX_ADC_CON_CONV;
286
+}
287
+
288
+static void npcm7xx_adc_calibrate(NPCM7xxADCState *adc)
289
+{
290
+ adc->calibration_r_values[0] = npcm7xx_adc_convert(NPCM7XX_ADC_R0_INPUT,
291
+ adc->iref);
292
+ adc->calibration_r_values[1] = npcm7xx_adc_convert(NPCM7XX_ADC_R1_INPUT,
293
+ adc->iref);
294
+}
295
+
296
+static void npcm7xx_adc_write_con(NPCM7xxADCState *s, uint32_t new_con)
297
+{
298
+ uint32_t old_con = s->con;
299
+
300
+ /* Write ADC_INT to 1 to clear it */
301
+ if (new_con & NPCM7XX_ADC_CON_INT) {
302
+ new_con &= ~NPCM7XX_ADC_CON_INT;
303
+ qemu_irq_lower(s->irq);
304
+ } else if (old_con & NPCM7XX_ADC_CON_INT) {
305
+ new_con |= NPCM7XX_ADC_CON_INT;
306
+ }
307
+
308
+ s->con = new_con;
309
+
310
+ if (s->con & NPCM7XX_ADC_CON_RST) {
311
+ npcm7xx_adc_reset(s);
312
+ return;
313
+ }
314
+
315
+ if ((s->con & NPCM7XX_ADC_CON_EN)) {
316
+ if (s->con & NPCM7XX_ADC_CON_CONV) {
317
+ if (!(old_con & NPCM7XX_ADC_CON_CONV)) {
318
+ npcm7xx_adc_start_convert(s);
319
+ }
320
+ } else {
321
+ timer_del(&s->conv_timer);
322
+ }
323
+ }
324
+}
325
+
326
+static uint64_t npcm7xx_adc_read(void *opaque, hwaddr offset, unsigned size)
327
+{
328
+ uint64_t value = 0;
329
+ NPCM7xxADCState *s = opaque;
330
+
331
+ switch (offset) {
332
+ case A_NPCM7XX_ADC_CON:
333
+ value = s->con;
334
+ break;
335
+
336
+ case A_NPCM7XX_ADC_DATA:
337
+ value = s->data;
338
+ break;
339
+
340
+ default:
341
+ qemu_log_mask(LOG_GUEST_ERROR,
342
+ "%s: invalid offset 0x%04" HWADDR_PRIx "\n",
343
+ __func__, offset);
344
+ break;
345
+ }
346
+
347
+ trace_npcm7xx_adc_read(DEVICE(s)->canonical_path, offset, value);
348
+ return value;
349
+}
350
+
351
+static void npcm7xx_adc_write(void *opaque, hwaddr offset, uint64_t v,
352
+ unsigned size)
353
+{
354
+ NPCM7xxADCState *s = opaque;
355
+
356
+ trace_npcm7xx_adc_write(DEVICE(s)->canonical_path, offset, v);
357
+ switch (offset) {
358
+ case A_NPCM7XX_ADC_CON:
359
+ npcm7xx_adc_write_con(s, v);
360
+ break;
361
+
362
+ case A_NPCM7XX_ADC_DATA:
363
+ qemu_log_mask(LOG_GUEST_ERROR,
364
+ "%s: register @ 0x%04" HWADDR_PRIx " is read-only\n",
365
+ __func__, offset);
366
+ break;
367
+
368
+ default:
369
+ qemu_log_mask(LOG_GUEST_ERROR,
370
+ "%s: invalid offset 0x%04" HWADDR_PRIx "\n",
371
+ __func__, offset);
372
+ break;
373
+ }
374
+
375
+}
376
+
377
+static const struct MemoryRegionOps npcm7xx_adc_ops = {
378
+ .read = npcm7xx_adc_read,
379
+ .write = npcm7xx_adc_write,
380
+ .endianness = DEVICE_LITTLE_ENDIAN,
381
+ .valid = {
382
+ .min_access_size = 4,
383
+ .max_access_size = 4,
384
+ .unaligned = false,
385
+ },
386
+};
109
+};
387
+
110
+
388
+static void npcm7xx_adc_enter_reset(Object *obj, ResetType type)
111
static void smmuv3_instance_init(Object *obj)
389
+{
112
{
390
+ NPCM7xxADCState *s = NPCM7XX_ADC(obj);
113
/* Nothing much to do here as of now */
391
+
114
@@ -XXX,XX +XXX,XX @@ static void smmuv3_class_init(ObjectClass *klass, void *data)
392
+ npcm7xx_adc_reset(s);
115
&c->parent_phases);
393
+}
116
c->parent_realize = dc->realize;
394
+
117
dc->realize = smmu_realize;
395
+static void npcm7xx_adc_hold_reset(Object *obj)
118
+ device_class_set_props(dc, smmuv3_properties);
396
+{
397
+ NPCM7xxADCState *s = NPCM7XX_ADC(obj);
398
+
399
+ qemu_irq_lower(s->irq);
400
+}
401
+
402
+static void npcm7xx_adc_init(Object *obj)
403
+{
404
+ NPCM7xxADCState *s = NPCM7XX_ADC(obj);
405
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
406
+ int i;
407
+
408
+ sysbus_init_irq(sbd, &s->irq);
409
+
410
+ timer_init_ns(&s->conv_timer, QEMU_CLOCK_VIRTUAL,
411
+ npcm7xx_adc_convert_done, s);
412
+ memory_region_init_io(&s->iomem, obj, &npcm7xx_adc_ops, s,
413
+ TYPE_NPCM7XX_ADC, 4 * KiB);
414
+ sysbus_init_mmio(sbd, &s->iomem);
415
+ s->clock = qdev_init_clock_in(DEVICE(s), "clock", NULL, NULL);
416
+
417
+ for (i = 0; i < NPCM7XX_ADC_NUM_INPUTS; ++i) {
418
+ object_property_add_uint32_ptr(obj, "adci[*]",
419
+ &s->adci[i], OBJ_PROP_FLAG_WRITE);
420
+ }
421
+ object_property_add_uint32_ptr(obj, "vref",
422
+ &s->vref, OBJ_PROP_FLAG_WRITE);
423
+ npcm7xx_adc_calibrate(s);
424
+}
425
+
426
+static const VMStateDescription vmstate_npcm7xx_adc = {
427
+ .name = "npcm7xx-adc",
428
+ .version_id = 0,
429
+ .minimum_version_id = 0,
430
+ .fields = (VMStateField[]) {
431
+ VMSTATE_TIMER(conv_timer, NPCM7xxADCState),
432
+ VMSTATE_UINT32(con, NPCM7xxADCState),
433
+ VMSTATE_UINT32(data, NPCM7xxADCState),
434
+ VMSTATE_CLOCK(clock, NPCM7xxADCState),
435
+ VMSTATE_UINT32_ARRAY(adci, NPCM7xxADCState, NPCM7XX_ADC_NUM_INPUTS),
436
+ VMSTATE_UINT32(vref, NPCM7xxADCState),
437
+ VMSTATE_UINT32(iref, NPCM7xxADCState),
438
+ VMSTATE_UINT16_ARRAY(calibration_r_values, NPCM7xxADCState,
439
+ NPCM7XX_ADC_NUM_CALIB),
440
+ VMSTATE_END_OF_LIST(),
441
+ },
442
+};
443
+
444
+static Property npcm7xx_timer_properties[] = {
445
+ DEFINE_PROP_UINT32("iref", NPCM7xxADCState, iref, NPCM7XX_ADC_DEFAULT_IREF),
446
+ DEFINE_PROP_END_OF_LIST(),
447
+};
448
+
449
+static void npcm7xx_adc_class_init(ObjectClass *klass, void *data)
450
+{
451
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
452
+ DeviceClass *dc = DEVICE_CLASS(klass);
453
+
454
+ dc->desc = "NPCM7xx ADC Module";
455
+ dc->vmsd = &vmstate_npcm7xx_adc;
456
+ rc->phases.enter = npcm7xx_adc_enter_reset;
457
+ rc->phases.hold = npcm7xx_adc_hold_reset;
458
+
459
+ device_class_set_props(dc, npcm7xx_timer_properties);
460
+}
461
+
462
+static const TypeInfo npcm7xx_adc_info = {
463
+ .name = TYPE_NPCM7XX_ADC,
464
+ .parent = TYPE_SYS_BUS_DEVICE,
465
+ .instance_size = sizeof(NPCM7xxADCState),
466
+ .class_init = npcm7xx_adc_class_init,
467
+ .instance_init = npcm7xx_adc_init,
468
+};
469
+
470
+static void npcm7xx_adc_register_types(void)
471
+{
472
+ type_register_static(&npcm7xx_adc_info);
473
+}
474
+
475
+type_init(npcm7xx_adc_register_types);
476
diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c
477
index XXXXXXX..XXXXXXX 100644
478
--- a/hw/arm/npcm7xx.c
479
+++ b/hw/arm/npcm7xx.c
480
@@ -XXX,XX +XXX,XX @@
481
#define NPCM7XX_EHCI_BA (0xf0806000)
482
#define NPCM7XX_OHCI_BA (0xf0807000)
483
484
+/* ADC Module */
485
+#define NPCM7XX_ADC_BA (0xf000c000)
486
+
487
/* Internal AHB SRAM */
488
#define NPCM7XX_RAM3_BA (0xc0008000)
489
#define NPCM7XX_RAM3_SZ (4 * KiB)
490
@@ -XXX,XX +XXX,XX @@
491
#define NPCM7XX_ROM_BA (0xffff0000)
492
#define NPCM7XX_ROM_SZ (64 * KiB)
493
494
+
495
/* Clock configuration values to be fixed up when bypassing bootloader */
496
497
/* Run PLL1 at 1600 MHz */
498
@@ -XXX,XX +XXX,XX @@
499
* interrupts.
500
*/
501
enum NPCM7xxInterrupt {
502
+ NPCM7XX_ADC_IRQ = 0,
503
NPCM7XX_UART0_IRQ = 2,
504
NPCM7XX_UART1_IRQ,
505
NPCM7XX_UART2_IRQ,
506
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_init_fuses(NPCM7xxState *s)
507
sizeof(value));
508
}
119
}
509
120
510
+static void npcm7xx_write_adc_calibration(NPCM7xxState *s)
121
static int smmuv3_notify_flag_changed(IOMMUMemoryRegion *iommu,
511
+{
512
+ /* Both ADC and the fuse array must have realized. */
513
+ QEMU_BUILD_BUG_ON(sizeof(s->adc.calibration_r_values) != 4);
514
+ npcm7xx_otp_array_write(&s->fuse_array, s->adc.calibration_r_values,
515
+ NPCM7XX_FUSE_ADC_CALIB, sizeof(s->adc.calibration_r_values));
516
+}
517
+
518
static qemu_irq npcm7xx_irq(NPCM7xxState *s, int n)
519
{
520
return qdev_get_gpio_in(DEVICE(&s->a9mpcore), n);
521
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_init(Object *obj)
522
TYPE_NPCM7XX_FUSE_ARRAY);
523
object_initialize_child(obj, "mc", &s->mc, TYPE_NPCM7XX_MC);
524
object_initialize_child(obj, "rng", &s->rng, TYPE_NPCM7XX_RNG);
525
+ object_initialize_child(obj, "adc", &s->adc, TYPE_NPCM7XX_ADC);
526
527
for (i = 0; i < ARRAY_SIZE(s->tim); i++) {
528
object_initialize_child(obj, "tim[*]", &s->tim[i], TYPE_NPCM7XX_TIMER);
529
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_realize(DeviceState *dev, Error **errp)
530
sysbus_realize(SYS_BUS_DEVICE(&s->mc), &error_abort);
531
sysbus_mmio_map(SYS_BUS_DEVICE(&s->mc), 0, NPCM7XX_MC_BA);
532
533
+ /* ADC Modules. Cannot fail. */
534
+ qdev_connect_clock_in(DEVICE(&s->adc), "clock", qdev_get_clock_out(
535
+ DEVICE(&s->clk), "adc-clock"));
536
+ sysbus_realize(SYS_BUS_DEVICE(&s->adc), &error_abort);
537
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->adc), 0, NPCM7XX_ADC_BA);
538
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0,
539
+ npcm7xx_irq(s, NPCM7XX_ADC_IRQ));
540
+ npcm7xx_write_adc_calibration(s);
541
+
542
/* Timer Modules (TIM). Cannot fail. */
543
QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_tim_addr) != ARRAY_SIZE(s->tim));
544
for (i = 0; i < ARRAY_SIZE(s->tim); i++) {
545
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_realize(DeviceState *dev, Error **errp)
546
create_unimplemented_device("npcm7xx.vdmx", 0xe0800000, 4 * KiB);
547
create_unimplemented_device("npcm7xx.pcierc", 0xe1000000, 64 * KiB);
548
create_unimplemented_device("npcm7xx.kcs", 0xf0007000, 4 * KiB);
549
- create_unimplemented_device("npcm7xx.adc", 0xf000c000, 4 * KiB);
550
create_unimplemented_device("npcm7xx.gfxi", 0xf000e000, 4 * KiB);
551
create_unimplemented_device("npcm7xx.gpio[0]", 0xf0010000, 4 * KiB);
552
create_unimplemented_device("npcm7xx.gpio[1]", 0xf0011000, 4 * KiB);
553
diff --git a/tests/qtest/npcm7xx_adc-test.c b/tests/qtest/npcm7xx_adc-test.c
554
new file mode 100644
555
index XXXXXXX..XXXXXXX
556
--- /dev/null
557
+++ b/tests/qtest/npcm7xx_adc-test.c
558
@@ -XXX,XX +XXX,XX @@
559
+/*
560
+ * QTests for Nuvoton NPCM7xx ADCModules.
561
+ *
562
+ * Copyright 2020 Google LLC
563
+ *
564
+ * This program is free software; you can redistribute it and/or modify it
565
+ * under the terms of the GNU General Public License as published by the
566
+ * Free Software Foundation; either version 2 of the License, or
567
+ * (at your option) any later version.
568
+ *
569
+ * This program is distributed in the hope that it will be useful, but WITHOUT
570
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
571
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
572
+ * for more details.
573
+ */
574
+
575
+#include "qemu/osdep.h"
576
+#include "qemu/bitops.h"
577
+#include "qemu/timer.h"
578
+#include "libqos/libqtest.h"
579
+#include "qapi/qmp/qdict.h"
580
+
581
+#define REF_HZ (25000000)
582
+
583
+#define CON_OFFSET 0x0
584
+#define DATA_OFFSET 0x4
585
+
586
+#define NUM_INPUTS 8
587
+#define DEFAULT_IREF 2000000
588
+#define CONV_CYCLES 20
589
+#define RESET_CYCLES 10
590
+#define R0_INPUT 500000
591
+#define R1_INPUT 1500000
592
+#define MAX_RESULT 1023
593
+
594
+#define DEFAULT_CLKDIV 5
595
+
596
+#define FUSE_ARRAY_BA 0xf018a000
597
+#define FCTL_OFFSET 0x14
598
+#define FST_OFFSET 0x0
599
+#define FADDR_OFFSET 0x4
600
+#define FDATA_OFFSET 0x8
601
+#define ADC_CALIB_ADDR 24
602
+#define FUSE_READ 0x2
603
+
604
+/* Register field definitions. */
605
+#define CON_MUX(rv) ((rv) << 24)
606
+#define CON_INT_EN BIT(21)
607
+#define CON_REFSEL BIT(19)
608
+#define CON_INT BIT(18)
609
+#define CON_EN BIT(17)
610
+#define CON_RST BIT(16)
611
+#define CON_CONV BIT(14)
612
+#define CON_DIV(rv) extract32(rv, 1, 8)
613
+
614
+#define FST_RDST BIT(1)
615
+#define FDATA_MASK 0xff
616
+
617
+#define MAX_ERROR 10000
618
+#define MIN_CALIB_INPUT 100000
619
+#define MAX_CALIB_INPUT 1800000
620
+
621
+static const uint32_t input_list[] = {
622
+ 100000,
623
+ 500000,
624
+ 1000000,
625
+ 1500000,
626
+ 1800000,
627
+ 2000000,
628
+};
629
+
630
+static const uint32_t vref_list[] = {
631
+ 2000000,
632
+ 2200000,
633
+ 2500000,
634
+};
635
+
636
+static const uint32_t iref_list[] = {
637
+ 1800000,
638
+ 1900000,
639
+ 2000000,
640
+ 2100000,
641
+ 2200000,
642
+};
643
+
644
+static const uint32_t div_list[] = {0, 1, 3, 7, 15};
645
+
646
+typedef struct ADC {
647
+ int irq;
648
+ uint64_t base_addr;
649
+} ADC;
650
+
651
+ADC adc = {
652
+ .irq = 0,
653
+ .base_addr = 0xf000c000
654
+};
655
+
656
+static uint32_t adc_read_con(QTestState *qts, const ADC *adc)
657
+{
658
+ return qtest_readl(qts, adc->base_addr + CON_OFFSET);
659
+}
660
+
661
+static void adc_write_con(QTestState *qts, const ADC *adc, uint32_t value)
662
+{
663
+ qtest_writel(qts, adc->base_addr + CON_OFFSET, value);
664
+}
665
+
666
+static uint32_t adc_read_data(QTestState *qts, const ADC *adc)
667
+{
668
+ return qtest_readl(qts, adc->base_addr + DATA_OFFSET);
669
+}
670
+
671
+static uint32_t adc_calibrate(uint32_t measured, uint32_t *rv)
672
+{
673
+ return R0_INPUT + (R1_INPUT - R0_INPUT) * (int32_t)(measured - rv[0])
674
+ / (int32_t)(rv[1] - rv[0]);
675
+}
676
+
677
+static void adc_qom_set(QTestState *qts, const ADC *adc,
678
+ const char *name, uint32_t value)
679
+{
680
+ QDict *response;
681
+ const char *path = "/machine/soc/adc";
682
+
683
+ g_test_message("Setting properties %s of %s with value %u",
684
+ name, path, value);
685
+ response = qtest_qmp(qts, "{ 'execute': 'qom-set',"
686
+ " 'arguments': { 'path': %s, 'property': %s, 'value': %u}}",
687
+ path, name, value);
688
+ /* The qom set message returns successfully. */
689
+ g_assert_true(qdict_haskey(response, "return"));
690
+}
691
+
692
+static void adc_write_input(QTestState *qts, const ADC *adc,
693
+ uint32_t index, uint32_t value)
694
+{
695
+ char name[100];
696
+
697
+ sprintf(name, "adci[%u]", index);
698
+ adc_qom_set(qts, adc, name, value);
699
+}
700
+
701
+static void adc_write_vref(QTestState *qts, const ADC *adc, uint32_t value)
702
+{
703
+ adc_qom_set(qts, adc, "vref", value);
704
+}
705
+
706
+static uint32_t adc_calculate_output(uint32_t input, uint32_t ref)
707
+{
708
+ uint32_t output;
709
+
710
+ g_assert_cmpuint(input, <=, ref);
711
+ output = (input * (MAX_RESULT + 1)) / ref;
712
+ if (output > MAX_RESULT) {
713
+ output = MAX_RESULT;
714
+ }
715
+
716
+ return output;
717
+}
718
+
719
+static uint32_t adc_prescaler(QTestState *qts, const ADC *adc)
720
+{
721
+ uint32_t div = extract32(adc_read_con(qts, adc), 1, 8);
722
+
723
+ return 2 * (div + 1);
724
+}
725
+
726
+static int64_t adc_calculate_steps(uint32_t cycles, uint32_t prescale,
727
+ uint32_t clkdiv)
728
+{
729
+ return (NANOSECONDS_PER_SECOND / (REF_HZ >> clkdiv)) * cycles * prescale;
730
+}
731
+
732
+static void adc_wait_conv_finished(QTestState *qts, const ADC *adc,
733
+ uint32_t clkdiv)
734
+{
735
+ uint32_t prescaler = adc_prescaler(qts, adc);
736
+
737
+ /*
738
+ * ADC should takes roughly 20 cycles to convert one sample. So we assert it
739
+ * should take 10~30 cycles here.
740
+ */
741
+ qtest_clock_step(qts, adc_calculate_steps(CONV_CYCLES / 2, prescaler,
742
+ clkdiv));
743
+ /* ADC is still converting. */
744
+ g_assert_true(adc_read_con(qts, adc) & CON_CONV);
745
+ qtest_clock_step(qts, adc_calculate_steps(CONV_CYCLES, prescaler, clkdiv));
746
+ /* ADC has finished conversion. */
747
+ g_assert_false(adc_read_con(qts, adc) & CON_CONV);
748
+}
749
+
750
+/* Check ADC can be reset to default value. */
751
+static void test_init(gconstpointer adc_p)
752
+{
753
+ const ADC *adc = adc_p;
754
+
755
+ QTestState *qts = qtest_init("-machine quanta-gsj");
756
+ adc_write_con(qts, adc, CON_REFSEL | CON_INT);
757
+ g_assert_cmphex(adc_read_con(qts, adc), ==, CON_REFSEL);
758
+ qtest_quit(qts);
759
+}
760
+
761
+/* Check ADC can convert from an internal reference. */
762
+static void test_convert_internal(gconstpointer adc_p)
763
+{
764
+ const ADC *adc = adc_p;
765
+ uint32_t index, input, output, expected_output;
766
+ QTestState *qts = qtest_init("-machine quanta-gsj");
767
+ qtest_irq_intercept_in(qts, "/machine/soc/a9mpcore/gic");
768
+
769
+ for (index = 0; index < NUM_INPUTS; ++index) {
770
+ for (size_t i = 0; i < ARRAY_SIZE(input_list); ++i) {
771
+ input = input_list[i];
772
+ expected_output = adc_calculate_output(input, DEFAULT_IREF);
773
+
774
+ adc_write_input(qts, adc, index, input);
775
+ adc_write_con(qts, adc, CON_MUX(index) | CON_REFSEL | CON_INT |
776
+ CON_EN | CON_CONV);
777
+ adc_wait_conv_finished(qts, adc, DEFAULT_CLKDIV);
778
+ g_assert_cmphex(adc_read_con(qts, adc), ==, CON_MUX(index) |
779
+ CON_REFSEL | CON_EN);
780
+ g_assert_false(qtest_get_irq(qts, adc->irq));
781
+ output = adc_read_data(qts, adc);
782
+ g_assert_cmpuint(output, ==, expected_output);
783
+ }
784
+ }
785
+
786
+ qtest_quit(qts);
787
+}
788
+
789
+/* Check ADC can convert from an external reference. */
790
+static void test_convert_external(gconstpointer adc_p)
791
+{
792
+ const ADC *adc = adc_p;
793
+ uint32_t index, input, vref, output, expected_output;
794
+ QTestState *qts = qtest_init("-machine quanta-gsj");
795
+ qtest_irq_intercept_in(qts, "/machine/soc/a9mpcore/gic");
796
+
797
+ for (index = 0; index < NUM_INPUTS; ++index) {
798
+ for (size_t i = 0; i < ARRAY_SIZE(input_list); ++i) {
799
+ for (size_t j = 0; j < ARRAY_SIZE(vref_list); ++j) {
800
+ input = input_list[i];
801
+ vref = vref_list[j];
802
+ expected_output = adc_calculate_output(input, vref);
803
+
804
+ adc_write_input(qts, adc, index, input);
805
+ adc_write_vref(qts, adc, vref);
806
+ adc_write_con(qts, adc, CON_MUX(index) | CON_INT | CON_EN |
807
+ CON_CONV);
808
+ adc_wait_conv_finished(qts, adc, DEFAULT_CLKDIV);
809
+ g_assert_cmphex(adc_read_con(qts, adc), ==,
810
+ CON_MUX(index) | CON_EN);
811
+ g_assert_false(qtest_get_irq(qts, adc->irq));
812
+ output = adc_read_data(qts, adc);
813
+ g_assert_cmpuint(output, ==, expected_output);
814
+ }
815
+ }
816
+ }
817
+
818
+ qtest_quit(qts);
819
+}
820
+
821
+/* Check ADC interrupt files if and only if CON_INT_EN is set. */
822
+static void test_interrupt(gconstpointer adc_p)
823
+{
824
+ const ADC *adc = adc_p;
825
+ uint32_t index, input, output, expected_output;
826
+ QTestState *qts = qtest_init("-machine quanta-gsj");
827
+
828
+ index = 1;
829
+ input = input_list[1];
830
+ expected_output = adc_calculate_output(input, DEFAULT_IREF);
831
+
832
+ qtest_irq_intercept_in(qts, "/machine/soc/a9mpcore/gic");
833
+ adc_write_input(qts, adc, index, input);
834
+ g_assert_false(qtest_get_irq(qts, adc->irq));
835
+ adc_write_con(qts, adc, CON_MUX(index) | CON_INT_EN | CON_REFSEL | CON_INT
836
+ | CON_EN | CON_CONV);
837
+ adc_wait_conv_finished(qts, adc, DEFAULT_CLKDIV);
838
+ g_assert_cmphex(adc_read_con(qts, adc), ==, CON_MUX(index) | CON_INT_EN
839
+ | CON_REFSEL | CON_INT | CON_EN);
840
+ g_assert_true(qtest_get_irq(qts, adc->irq));
841
+ output = adc_read_data(qts, adc);
842
+ g_assert_cmpuint(output, ==, expected_output);
843
+
844
+ qtest_quit(qts);
845
+}
846
+
847
+/* Check ADC is reset after setting ADC_RST for 10 ADC cycles. */
848
+static void test_reset(gconstpointer adc_p)
849
+{
850
+ const ADC *adc = adc_p;
851
+ QTestState *qts = qtest_init("-machine quanta-gsj");
852
+
853
+ for (size_t i = 0; i < ARRAY_SIZE(div_list); ++i) {
854
+ uint32_t div = div_list[i];
855
+
856
+ adc_write_con(qts, adc, CON_INT | CON_EN | CON_RST | CON_DIV(div));
857
+ qtest_clock_step(qts, adc_calculate_steps(RESET_CYCLES,
858
+ adc_prescaler(qts, adc), DEFAULT_CLKDIV));
859
+ g_assert_false(adc_read_con(qts, adc) & CON_EN);
860
+ }
861
+ qtest_quit(qts);
862
+}
863
+
864
+/* Check ADC Calibration works as desired. */
865
+static void test_calibrate(gconstpointer adc_p)
866
+{
867
+ int i, j;
868
+ const ADC *adc = adc_p;
869
+
870
+ for (j = 0; j < ARRAY_SIZE(iref_list); ++j) {
871
+ uint32_t iref = iref_list[j];
872
+ uint32_t expected_rv[] = {
873
+ adc_calculate_output(R0_INPUT, iref),
874
+ adc_calculate_output(R1_INPUT, iref),
875
+ };
876
+ char buf[100];
877
+ QTestState *qts;
878
+
879
+ sprintf(buf, "-machine quanta-gsj -global npcm7xx-adc.iref=%u", iref);
880
+ qts = qtest_init(buf);
881
+
882
+ /* Check the converted value is correct using the calibration value. */
883
+ for (i = 0; i < ARRAY_SIZE(input_list); ++i) {
884
+ uint32_t input;
885
+ uint32_t output;
886
+ uint32_t expected_output;
887
+ uint32_t calibrated_voltage;
888
+ uint32_t index = 0;
889
+
890
+ input = input_list[i];
891
+ /* Calibration only works for input range 0.1V ~ 1.8V. */
892
+ if (input < MIN_CALIB_INPUT || input > MAX_CALIB_INPUT) {
893
+ continue;
894
+ }
895
+ expected_output = adc_calculate_output(input, iref);
896
+
897
+ adc_write_input(qts, adc, index, input);
898
+ adc_write_con(qts, adc, CON_MUX(index) | CON_REFSEL | CON_INT |
899
+ CON_EN | CON_CONV);
900
+ adc_wait_conv_finished(qts, adc, DEFAULT_CLKDIV);
901
+ g_assert_cmphex(adc_read_con(qts, adc), ==,
902
+ CON_REFSEL | CON_MUX(index) | CON_EN);
903
+ output = adc_read_data(qts, adc);
904
+ g_assert_cmpuint(output, ==, expected_output);
905
+
906
+ calibrated_voltage = adc_calibrate(output, expected_rv);
907
+ g_assert_cmpuint(calibrated_voltage, >, input - MAX_ERROR);
908
+ g_assert_cmpuint(calibrated_voltage, <, input + MAX_ERROR);
909
+ }
910
+
911
+ qtest_quit(qts);
912
+ }
913
+}
914
+
915
+static void adc_add_test(const char *name, const ADC* wd,
916
+ GTestDataFunc fn)
917
+{
918
+ g_autofree char *full_name = g_strdup_printf("npcm7xx_adc/%s", name);
919
+ qtest_add_data_func(full_name, wd, fn);
920
+}
921
+#define add_test(name, td) adc_add_test(#name, td, test_##name)
922
+
923
+int main(int argc, char **argv)
924
+{
925
+ g_test_init(&argc, &argv, NULL);
926
+
927
+ add_test(init, &adc);
928
+ add_test(convert_internal, &adc);
929
+ add_test(convert_external, &adc);
930
+ add_test(interrupt, &adc);
931
+ add_test(reset, &adc);
932
+ add_test(calibrate, &adc);
933
+
934
+ return g_test_run();
935
+}
936
diff --git a/hw/adc/meson.build b/hw/adc/meson.build
937
index XXXXXXX..XXXXXXX 100644
938
--- a/hw/adc/meson.build
939
+++ b/hw/adc/meson.build
940
@@ -1 +1,2 @@
941
softmmu_ss.add(when: 'CONFIG_STM32F2XX_ADC', if_true: files('stm32f2xx_adc.c'))
942
+softmmu_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx_adc.c'))
943
diff --git a/hw/adc/trace-events b/hw/adc/trace-events
944
new file mode 100644
945
index XXXXXXX..XXXXXXX
946
--- /dev/null
947
+++ b/hw/adc/trace-events
948
@@ -XXX,XX +XXX,XX @@
949
+# See docs/devel/tracing.txt for syntax documentation.
950
+
951
+# npcm7xx_adc.c
952
+npcm7xx_adc_read(const char *id, uint64_t offset, uint32_t value) " %s offset: 0x%04" PRIx64 " value 0x%04" PRIx32
953
+npcm7xx_adc_write(const char *id, uint64_t offset, uint32_t value) "%s offset: 0x%04" PRIx64 " value 0x%04" PRIx32
954
diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
955
index XXXXXXX..XXXXXXX 100644
956
--- a/tests/qtest/meson.build
957
+++ b/tests/qtest/meson.build
958
@@ -XXX,XX +XXX,XX @@ qtests_sparc64 = \
959
['prom-env-test', 'boot-serial-test']
960
961
qtests_npcm7xx = \
962
- ['npcm7xx_gpio-test',
963
+ ['npcm7xx_adc-test',
964
+ 'npcm7xx_gpio-test',
965
'npcm7xx_rng-test',
966
'npcm7xx_timer-test',
967
'npcm7xx_watchdog_timer-test']
968
--
122
--
969
2.20.1
123
2.34.1
970
971
diff view generated by jsdifflib
[PULL 15/21] hw/misc: Add clock converter in NPCM7XX CLK module
[PULL 12/21] hw/dma/xilinx_axidma: Check DMASR.HALTED to prevent infinite loop.
1
From: Hao Wu <wuhaotsh@google.com>
1
From: Tommy Wu <tommy.wu@sifive.com>
2
2
3
This patch allows NPCM7XX CLK module to compute clocks that are used by
3
When we receive a packet from the xilinx_axienet and then try to s2mem
4
other NPCM7XX modules.
4
through the xilinx_axidma, if the descriptor ring buffer is full in the
5
xilinx axidma driver, we’ll assert the DMASR.HALTED in the
6
function : stream_process_s2mem and return 0. In the end, we’ll be stuck in
7
an infinite loop in axienet_eth_rx_notify.
5
8
6
Add a new struct NPCM7xxClockConverterState which represents a
9
This patch checks the DMASR.HALTED state when we try to push data
7
single converter. Each clock converter in CLK module represents one
10
from xilinx axi-enet to xilinx axi-dma. When the DMASR.HALTED is asserted,
8
converter in NPCM7XX CLK Module(PLL, SEL or Divider). Each converter
11
we will not keep pushing the data and then prevent the infinte loop.
9
takes one or more input clocks and converts them into one output clock.
10
They form a clock hierarchy in the CLK module and are responsible for
11
outputing clocks for various other modules in an NPCM7XX SoC.
12
12
13
Each converter has a function pointer called "convert" which represents
13
Signed-off-by: Tommy Wu <tommy.wu@sifive.com>
14
the unique logic for that converter.
14
Reviewed-by: Edgar E. Iglesias <edgar@zeroasic.com>
15
15
Reviewed-by: Frank Chang <frank.chang@sifive.com>
16
The clock contains two initialization information: ConverterInitInfo and
16
Message-id: 20230519062137.1251741-1-tommy.wu@sifive.com
17
ConverterConnectionInfo. They represent the vertices and edges in the
18
clock diagram respectively.
19
20
Reviewed-by: Havard Skinnemoen <hskinnemoen@google.com>
21
Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
22
Signed-off-by: Hao Wu <wuhaotsh@google.com>
23
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
24
Message-id: 20210108190945.949196-2-wuhaotsh@google.com
25
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
26
---
18
---
27
include/hw/misc/npcm7xx_clk.h | 140 +++++-
19
hw/dma/xilinx_axidma.c | 11 ++++++++---
28
hw/misc/npcm7xx_clk.c | 805 +++++++++++++++++++++++++++++++++-
20
1 file changed, 8 insertions(+), 3 deletions(-)
29
2 files changed, 932 insertions(+), 13 deletions(-)
30
21
31
diff --git a/include/hw/misc/npcm7xx_clk.h b/include/hw/misc/npcm7xx_clk.h
22
diff --git a/hw/dma/xilinx_axidma.c b/hw/dma/xilinx_axidma.c
32
index XXXXXXX..XXXXXXX 100644
23
index XXXXXXX..XXXXXXX 100644
33
--- a/include/hw/misc/npcm7xx_clk.h
24
--- a/hw/dma/xilinx_axidma.c
34
+++ b/include/hw/misc/npcm7xx_clk.h
25
+++ b/hw/dma/xilinx_axidma.c
35
@@ -XXX,XX +XXX,XX @@
26
@@ -XXX,XX +XXX,XX @@ static inline int stream_idle(struct Stream *s)
36
#define NPCM7XX_CLK_H
27
return !!(s->regs[R_DMASR] & DMASR_IDLE);
37
28
}
38
#include "exec/memory.h"
29
39
+#include "hw/clock.h"
30
+static inline int stream_halted(struct Stream *s)
40
#include "hw/sysbus.h"
41
42
/*
43
@@ -XXX,XX +XXX,XX @@
44
45
#define NPCM7XX_WATCHDOG_RESET_GPIO_IN "npcm7xx-clk-watchdog-reset-gpio-in"
46
47
-typedef struct NPCM7xxCLKState {
48
+/* Maximum amount of clock inputs in a SEL module. */
49
+#define NPCM7XX_CLK_SEL_MAX_INPUT 5
50
+
51
+/* PLLs in CLK module. */
52
+typedef enum NPCM7xxClockPLL {
53
+ NPCM7XX_CLOCK_PLL0,
54
+ NPCM7XX_CLOCK_PLL1,
55
+ NPCM7XX_CLOCK_PLL2,
56
+ NPCM7XX_CLOCK_PLLG,
57
+ NPCM7XX_CLOCK_NR_PLLS,
58
+} NPCM7xxClockPLL;
59
+
60
+/* SEL/MUX in CLK module. */
61
+typedef enum NPCM7xxClockSEL {
62
+ NPCM7XX_CLOCK_PIXCKSEL,
63
+ NPCM7XX_CLOCK_MCCKSEL,
64
+ NPCM7XX_CLOCK_CPUCKSEL,
65
+ NPCM7XX_CLOCK_CLKOUTSEL,
66
+ NPCM7XX_CLOCK_UARTCKSEL,
67
+ NPCM7XX_CLOCK_TIMCKSEL,
68
+ NPCM7XX_CLOCK_SDCKSEL,
69
+ NPCM7XX_CLOCK_GFXMSEL,
70
+ NPCM7XX_CLOCK_SUCKSEL,
71
+ NPCM7XX_CLOCK_NR_SELS,
72
+} NPCM7xxClockSEL;
73
+
74
+/* Dividers in CLK module. */
75
+typedef enum NPCM7xxClockDivider {
76
+ NPCM7XX_CLOCK_PLL1D2, /* PLL1/2 */
77
+ NPCM7XX_CLOCK_PLL2D2, /* PLL2/2 */
78
+ NPCM7XX_CLOCK_MC_DIVIDER,
79
+ NPCM7XX_CLOCK_AXI_DIVIDER,
80
+ NPCM7XX_CLOCK_AHB_DIVIDER,
81
+ NPCM7XX_CLOCK_AHB3_DIVIDER,
82
+ NPCM7XX_CLOCK_SPI0_DIVIDER,
83
+ NPCM7XX_CLOCK_SPIX_DIVIDER,
84
+ NPCM7XX_CLOCK_APB1_DIVIDER,
85
+ NPCM7XX_CLOCK_APB2_DIVIDER,
86
+ NPCM7XX_CLOCK_APB3_DIVIDER,
87
+ NPCM7XX_CLOCK_APB4_DIVIDER,
88
+ NPCM7XX_CLOCK_APB5_DIVIDER,
89
+ NPCM7XX_CLOCK_CLKOUT_DIVIDER,
90
+ NPCM7XX_CLOCK_UART_DIVIDER,
91
+ NPCM7XX_CLOCK_TIMER_DIVIDER,
92
+ NPCM7XX_CLOCK_ADC_DIVIDER,
93
+ NPCM7XX_CLOCK_MMC_DIVIDER,
94
+ NPCM7XX_CLOCK_SDHC_DIVIDER,
95
+ NPCM7XX_CLOCK_GFXM_DIVIDER, /* divide by 3 */
96
+ NPCM7XX_CLOCK_UTMI_DIVIDER,
97
+ NPCM7XX_CLOCK_NR_DIVIDERS,
98
+} NPCM7xxClockConverter;
99
+
100
+typedef struct NPCM7xxCLKState NPCM7xxCLKState;
101
+
102
+/**
103
+ * struct NPCM7xxClockPLLState - A PLL module in CLK module.
104
+ * @name: The name of the module.
105
+ * @clk: The CLK module that owns this module.
106
+ * @clock_in: The input clock of this module.
107
+ * @clock_out: The output clock of this module.
108
+ * @reg: The control registers for this PLL module.
109
+ */
110
+typedef struct NPCM7xxClockPLLState {
111
+ DeviceState parent;
112
+
113
+ const char *name;
114
+ NPCM7xxCLKState *clk;
115
+ Clock *clock_in;
116
+ Clock *clock_out;
117
+
118
+ int reg;
119
+} NPCM7xxClockPLLState;
120
+
121
+/**
122
+ * struct NPCM7xxClockSELState - A SEL module in CLK module.
123
+ * @name: The name of the module.
124
+ * @clk: The CLK module that owns this module.
125
+ * @input_size: The size of inputs of this module.
126
+ * @clock_in: The input clocks of this module.
127
+ * @clock_out: The output clocks of this module.
128
+ * @offset: The offset of this module in the control register.
129
+ * @len: The length of this module in the control register.
130
+ */
131
+typedef struct NPCM7xxClockSELState {
132
+ DeviceState parent;
133
+
134
+ const char *name;
135
+ NPCM7xxCLKState *clk;
136
+ uint8_t input_size;
137
+ Clock *clock_in[NPCM7XX_CLK_SEL_MAX_INPUT];
138
+ Clock *clock_out;
139
+
140
+ int offset;
141
+ int len;
142
+} NPCM7xxClockSELState;
143
+
144
+/**
145
+ * struct NPCM7xxClockDividerState - A Divider module in CLK module.
146
+ * @name: The name of the module.
147
+ * @clk: The CLK module that owns this module.
148
+ * @clock_in: The input clock of this module.
149
+ * @clock_out: The output clock of this module.
150
+ * @divide: The function the divider uses to divide the input.
151
+ * @reg: The index of the control register that contains the divisor.
152
+ * @offset: The offset of the divisor in the control register.
153
+ * @len: The length of the divisor in the control register.
154
+ * @divisor: The divisor for a constant divisor
155
+ */
156
+typedef struct NPCM7xxClockDividerState {
157
+ DeviceState parent;
158
+
159
+ const char *name;
160
+ NPCM7xxCLKState *clk;
161
+ Clock *clock_in;
162
+ Clock *clock_out;
163
+
164
+ uint32_t (*divide)(struct NPCM7xxClockDividerState *s);
165
+ union {
166
+ struct {
167
+ int reg;
168
+ int offset;
169
+ int len;
170
+ };
171
+ int divisor;
172
+ };
173
+} NPCM7xxClockDividerState;
174
+
175
+struct NPCM7xxCLKState {
176
SysBusDevice parent;
177
178
MemoryRegion iomem;
179
180
+ /* Clock converters */
181
+ NPCM7xxClockPLLState plls[NPCM7XX_CLOCK_NR_PLLS];
182
+ NPCM7xxClockSELState sels[NPCM7XX_CLOCK_NR_SELS];
183
+ NPCM7xxClockDividerState dividers[NPCM7XX_CLOCK_NR_DIVIDERS];
184
+
185
uint32_t regs[NPCM7XX_CLK_NR_REGS];
186
187
/* Time reference for SECCNT and CNTR25M, initialized by power on reset */
188
int64_t ref_ns;
189
-} NPCM7xxCLKState;
190
+
191
+ /* The incoming reference clock. */
192
+ Clock *clkref;
193
+};
194
195
#define TYPE_NPCM7XX_CLK "npcm7xx-clk"
196
#define NPCM7XX_CLK(obj) OBJECT_CHECK(NPCM7xxCLKState, (obj), TYPE_NPCM7XX_CLK)
197
diff --git a/hw/misc/npcm7xx_clk.c b/hw/misc/npcm7xx_clk.c
198
index XXXXXXX..XXXXXXX 100644
199
--- a/hw/misc/npcm7xx_clk.c
200
+++ b/hw/misc/npcm7xx_clk.c
201
@@ -XXX,XX +XXX,XX @@
202
203
#include "hw/misc/npcm7xx_clk.h"
204
#include "hw/timer/npcm7xx_timer.h"
205
+#include "hw/qdev-clock.h"
206
#include "migration/vmstate.h"
207
#include "qemu/error-report.h"
208
#include "qemu/log.h"
209
@@ -XXX,XX +XXX,XX @@
210
#include "trace.h"
211
#include "sysemu/watchdog.h"
212
213
+/*
214
+ * The reference clock hz, and the SECCNT and CNTR25M registers in this module,
215
+ * is always 25 MHz.
216
+ */
217
+#define NPCM7XX_CLOCK_REF_HZ (25000000)
218
+
219
+/* Register Field Definitions */
220
+#define NPCM7XX_CLK_WDRCR_CA9C BIT(0) /* Cortex A9 Cores */
221
+
222
#define PLLCON_LOKI BIT(31)
223
#define PLLCON_LOKS BIT(30)
224
#define PLLCON_PWDEN BIT(12)
225
+#define PLLCON_FBDV(con) extract32((con), 16, 12)
226
+#define PLLCON_OTDV2(con) extract32((con), 13, 3)
227
+#define PLLCON_OTDV1(con) extract32((con), 8, 3)
228
+#define PLLCON_INDV(con) extract32((con), 0, 6)
229
230
enum NPCM7xxCLKRegisters {
231
NPCM7XX_CLK_CLKEN1,
232
@@ -XXX,XX +XXX,XX @@ static const uint32_t cold_reset_values[NPCM7XX_CLK_NR_REGS] = {
233
[NPCM7XX_CLK_AHBCKFI] = 0x000000c8,
234
};
235
236
-/* Register Field Definitions */
237
-#define NPCM7XX_CLK_WDRCR_CA9C BIT(0) /* Cortex A9 Cores */
238
-
239
/* The number of watchdogs that can trigger a reset. */
240
#define NPCM7XX_NR_WATCHDOGS (3)
241
242
+/* Clock converter functions */
243
+
244
+#define TYPE_NPCM7XX_CLOCK_PLL "npcm7xx-clock-pll"
245
+#define NPCM7XX_CLOCK_PLL(obj) OBJECT_CHECK(NPCM7xxClockPLLState, \
246
+ (obj), TYPE_NPCM7XX_CLOCK_PLL)
247
+#define TYPE_NPCM7XX_CLOCK_SEL "npcm7xx-clock-sel"
248
+#define NPCM7XX_CLOCK_SEL(obj) OBJECT_CHECK(NPCM7xxClockSELState, \
249
+ (obj), TYPE_NPCM7XX_CLOCK_SEL)
250
+#define TYPE_NPCM7XX_CLOCK_DIVIDER "npcm7xx-clock-divider"
251
+#define NPCM7XX_CLOCK_DIVIDER(obj) OBJECT_CHECK(NPCM7xxClockDividerState, \
252
+ (obj), TYPE_NPCM7XX_CLOCK_DIVIDER)
253
+
254
+static void npcm7xx_clk_update_pll(void *opaque)
255
+{
31
+{
256
+ NPCM7xxClockPLLState *s = opaque;
32
+ return !!(s->regs[R_DMASR] & DMASR_HALTED);
257
+ uint32_t con = s->clk->regs[s->reg];
258
+ uint64_t freq;
259
+
260
+ /* The PLL is grounded if it is not locked yet. */
261
+ if (con & PLLCON_LOKI) {
262
+ freq = clock_get_hz(s->clock_in);
263
+ freq *= PLLCON_FBDV(con);
264
+ freq /= PLLCON_INDV(con) * PLLCON_OTDV1(con) * PLLCON_OTDV2(con);
265
+ } else {
266
+ freq = 0;
267
+ }
268
+
269
+ clock_update_hz(s->clock_out, freq);
270
+}
33
+}
271
+
34
+
272
+static void npcm7xx_clk_update_sel(void *opaque)
35
static void stream_reset(struct Stream *s)
273
+{
274
+ NPCM7xxClockSELState *s = opaque;
275
+ uint32_t index = extract32(s->clk->regs[NPCM7XX_CLK_CLKSEL], s->offset,
276
+ s->len);
277
+
278
+ if (index >= s->input_size) {
279
+ qemu_log_mask(LOG_GUEST_ERROR,
280
+ "%s: SEL index: %u out of range\n",
281
+ __func__, index);
282
+ index = 0;
283
+ }
284
+ clock_update_hz(s->clock_out, clock_get_hz(s->clock_in[index]));
285
+}
286
+
287
+static void npcm7xx_clk_update_divider(void *opaque)
288
+{
289
+ NPCM7xxClockDividerState *s = opaque;
290
+ uint32_t freq;
291
+
292
+ freq = s->divide(s);
293
+ clock_update_hz(s->clock_out, freq);
294
+}
295
+
296
+static uint32_t divide_by_constant(NPCM7xxClockDividerState *s)
297
+{
298
+ return clock_get_hz(s->clock_in) / s->divisor;
299
+}
300
+
301
+static uint32_t divide_by_reg_divisor(NPCM7xxClockDividerState *s)
302
+{
303
+ return clock_get_hz(s->clock_in) /
304
+ (extract32(s->clk->regs[s->reg], s->offset, s->len) + 1);
305
+}
306
+
307
+static uint32_t divide_by_reg_divisor_times_2(NPCM7xxClockDividerState *s)
308
+{
309
+ return divide_by_reg_divisor(s) / 2;
310
+}
311
+
312
+static uint32_t shift_by_reg_divisor(NPCM7xxClockDividerState *s)
313
+{
314
+ return clock_get_hz(s->clock_in) >>
315
+ extract32(s->clk->regs[s->reg], s->offset, s->len);
316
+}
317
+
318
+static NPCM7xxClockPLL find_pll_by_reg(enum NPCM7xxCLKRegisters reg)
319
+{
320
+ switch (reg) {
321
+ case NPCM7XX_CLK_PLLCON0:
322
+ return NPCM7XX_CLOCK_PLL0;
323
+ case NPCM7XX_CLK_PLLCON1:
324
+ return NPCM7XX_CLOCK_PLL1;
325
+ case NPCM7XX_CLK_PLLCON2:
326
+ return NPCM7XX_CLOCK_PLL2;
327
+ case NPCM7XX_CLK_PLLCONG:
328
+ return NPCM7XX_CLOCK_PLLG;
329
+ default:
330
+ g_assert_not_reached();
331
+ }
332
+}
333
+
334
+static void npcm7xx_clk_update_all_plls(NPCM7xxCLKState *clk)
335
+{
336
+ int i;
337
+
338
+ for (i = 0; i < NPCM7XX_CLOCK_NR_PLLS; ++i) {
339
+ npcm7xx_clk_update_pll(&clk->plls[i]);
340
+ }
341
+}
342
+
343
+static void npcm7xx_clk_update_all_sels(NPCM7xxCLKState *clk)
344
+{
345
+ int i;
346
+
347
+ for (i = 0; i < NPCM7XX_CLOCK_NR_SELS; ++i) {
348
+ npcm7xx_clk_update_sel(&clk->sels[i]);
349
+ }
350
+}
351
+
352
+static void npcm7xx_clk_update_all_dividers(NPCM7xxCLKState *clk)
353
+{
354
+ int i;
355
+
356
+ for (i = 0; i < NPCM7XX_CLOCK_NR_DIVIDERS; ++i) {
357
+ npcm7xx_clk_update_divider(&clk->dividers[i]);
358
+ }
359
+}
360
+
361
+static void npcm7xx_clk_update_all_clocks(NPCM7xxCLKState *clk)
362
+{
363
+ clock_update_hz(clk->clkref, NPCM7XX_CLOCK_REF_HZ);
364
+ npcm7xx_clk_update_all_plls(clk);
365
+ npcm7xx_clk_update_all_sels(clk);
366
+ npcm7xx_clk_update_all_dividers(clk);
367
+}
368
+
369
+/* Types of clock sources. */
370
+typedef enum ClockSrcType {
371
+ CLKSRC_REF,
372
+ CLKSRC_PLL,
373
+ CLKSRC_SEL,
374
+ CLKSRC_DIV,
375
+} ClockSrcType;
376
+
377
+typedef struct PLLInitInfo {
378
+ const char *name;
379
+ ClockSrcType src_type;
380
+ int src_index;
381
+ int reg;
382
+ const char *public_name;
383
+} PLLInitInfo;
384
+
385
+typedef struct SELInitInfo {
386
+ const char *name;
387
+ uint8_t input_size;
388
+ ClockSrcType src_type[NPCM7XX_CLK_SEL_MAX_INPUT];
389
+ int src_index[NPCM7XX_CLK_SEL_MAX_INPUT];
390
+ int offset;
391
+ int len;
392
+ const char *public_name;
393
+} SELInitInfo;
394
+
395
+typedef struct DividerInitInfo {
396
+ const char *name;
397
+ ClockSrcType src_type;
398
+ int src_index;
399
+ uint32_t (*divide)(NPCM7xxClockDividerState *s);
400
+ int reg; /* not used when type == CONSTANT */
401
+ int offset; /* not used when type == CONSTANT */
402
+ int len; /* not used when type == CONSTANT */
403
+ int divisor; /* used only when type == CONSTANT */
404
+ const char *public_name;
405
+} DividerInitInfo;
406
+
407
+static const PLLInitInfo pll_init_info_list[] = {
408
+ [NPCM7XX_CLOCK_PLL0] = {
409
+ .name = "pll0",
410
+ .src_type = CLKSRC_REF,
411
+ .reg = NPCM7XX_CLK_PLLCON0,
412
+ },
413
+ [NPCM7XX_CLOCK_PLL1] = {
414
+ .name = "pll1",
415
+ .src_type = CLKSRC_REF,
416
+ .reg = NPCM7XX_CLK_PLLCON1,
417
+ },
418
+ [NPCM7XX_CLOCK_PLL2] = {
419
+ .name = "pll2",
420
+ .src_type = CLKSRC_REF,
421
+ .reg = NPCM7XX_CLK_PLLCON2,
422
+ },
423
+ [NPCM7XX_CLOCK_PLLG] = {
424
+ .name = "pllg",
425
+ .src_type = CLKSRC_REF,
426
+ .reg = NPCM7XX_CLK_PLLCONG,
427
+ },
428
+};
429
+
430
+static const SELInitInfo sel_init_info_list[] = {
431
+ [NPCM7XX_CLOCK_PIXCKSEL] = {
432
+ .name = "pixcksel",
433
+ .input_size = 2,
434
+ .src_type = {CLKSRC_PLL, CLKSRC_REF},
435
+ .src_index = {NPCM7XX_CLOCK_PLLG, 0},
436
+ .offset = 5,
437
+ .len = 1,
438
+ .public_name = "pixel-clock",
439
+ },
440
+ [NPCM7XX_CLOCK_MCCKSEL] = {
441
+ .name = "mccksel",
442
+ .input_size = 4,
443
+ .src_type = {CLKSRC_DIV, CLKSRC_REF, CLKSRC_REF,
444
+ /*MCBPCK, shouldn't be used in normal operation*/
445
+ CLKSRC_REF},
446
+ .src_index = {NPCM7XX_CLOCK_PLL1D2, 0, 0, 0},
447
+ .offset = 12,
448
+ .len = 2,
449
+ .public_name = "mc-phy-clock",
450
+ },
451
+ [NPCM7XX_CLOCK_CPUCKSEL] = {
452
+ .name = "cpucksel",
453
+ .input_size = 4,
454
+ .src_type = {CLKSRC_PLL, CLKSRC_DIV, CLKSRC_REF,
455
+ /*SYSBPCK, shouldn't be used in normal operation*/
456
+ CLKSRC_REF},
457
+ .src_index = {NPCM7XX_CLOCK_PLL0, NPCM7XX_CLOCK_PLL1D2, 0, 0},
458
+ .offset = 0,
459
+ .len = 2,
460
+ .public_name = "system-clock",
461
+ },
462
+ [NPCM7XX_CLOCK_CLKOUTSEL] = {
463
+ .name = "clkoutsel",
464
+ .input_size = 5,
465
+ .src_type = {CLKSRC_PLL, CLKSRC_DIV, CLKSRC_REF,
466
+ CLKSRC_PLL, CLKSRC_DIV},
467
+ .src_index = {NPCM7XX_CLOCK_PLL0, NPCM7XX_CLOCK_PLL1D2, 0,
468
+ NPCM7XX_CLOCK_PLLG, NPCM7XX_CLOCK_PLL2D2},
469
+ .offset = 18,
470
+ .len = 3,
471
+ .public_name = "tock",
472
+ },
473
+ [NPCM7XX_CLOCK_UARTCKSEL] = {
474
+ .name = "uartcksel",
475
+ .input_size = 4,
476
+ .src_type = {CLKSRC_PLL, CLKSRC_DIV, CLKSRC_REF, CLKSRC_DIV},
477
+ .src_index = {NPCM7XX_CLOCK_PLL0, NPCM7XX_CLOCK_PLL1D2, 0,
478
+ NPCM7XX_CLOCK_PLL2D2},
479
+ .offset = 8,
480
+ .len = 2,
481
+ },
482
+ [NPCM7XX_CLOCK_TIMCKSEL] = {
483
+ .name = "timcksel",
484
+ .input_size = 4,
485
+ .src_type = {CLKSRC_PLL, CLKSRC_DIV, CLKSRC_REF, CLKSRC_DIV},
486
+ .src_index = {NPCM7XX_CLOCK_PLL0, NPCM7XX_CLOCK_PLL1D2, 0,
487
+ NPCM7XX_CLOCK_PLL2D2},
488
+ .offset = 14,
489
+ .len = 2,
490
+ },
491
+ [NPCM7XX_CLOCK_SDCKSEL] = {
492
+ .name = "sdcksel",
493
+ .input_size = 4,
494
+ .src_type = {CLKSRC_PLL, CLKSRC_DIV, CLKSRC_REF, CLKSRC_DIV},
495
+ .src_index = {NPCM7XX_CLOCK_PLL0, NPCM7XX_CLOCK_PLL1D2, 0,
496
+ NPCM7XX_CLOCK_PLL2D2},
497
+ .offset = 6,
498
+ .len = 2,
499
+ },
500
+ [NPCM7XX_CLOCK_GFXMSEL] = {
501
+ .name = "gfxmksel",
502
+ .input_size = 2,
503
+ .src_type = {CLKSRC_REF, CLKSRC_PLL},
504
+ .src_index = {0, NPCM7XX_CLOCK_PLL2},
505
+ .offset = 21,
506
+ .len = 1,
507
+ },
508
+ [NPCM7XX_CLOCK_SUCKSEL] = {
509
+ .name = "sucksel",
510
+ .input_size = 4,
511
+ .src_type = {CLKSRC_PLL, CLKSRC_DIV, CLKSRC_REF, CLKSRC_DIV},
512
+ .src_index = {NPCM7XX_CLOCK_PLL0, NPCM7XX_CLOCK_PLL1D2, 0,
513
+ NPCM7XX_CLOCK_PLL2D2},
514
+ .offset = 10,
515
+ .len = 2,
516
+ },
517
+};
518
+
519
+static const DividerInitInfo divider_init_info_list[] = {
520
+ [NPCM7XX_CLOCK_PLL1D2] = {
521
+ .name = "pll1d2",
522
+ .src_type = CLKSRC_PLL,
523
+ .src_index = NPCM7XX_CLOCK_PLL1,
524
+ .divide = divide_by_constant,
525
+ .divisor = 2,
526
+ },
527
+ [NPCM7XX_CLOCK_PLL2D2] = {
528
+ .name = "pll2d2",
529
+ .src_type = CLKSRC_PLL,
530
+ .src_index = NPCM7XX_CLOCK_PLL2,
531
+ .divide = divide_by_constant,
532
+ .divisor = 2,
533
+ },
534
+ [NPCM7XX_CLOCK_MC_DIVIDER] = {
535
+ .name = "mc-divider",
536
+ .src_type = CLKSRC_SEL,
537
+ .src_index = NPCM7XX_CLOCK_MCCKSEL,
538
+ .divide = divide_by_constant,
539
+ .divisor = 2,
540
+ .public_name = "mc-clock"
541
+ },
542
+ [NPCM7XX_CLOCK_AXI_DIVIDER] = {
543
+ .name = "axi-divider",
544
+ .src_type = CLKSRC_SEL,
545
+ .src_index = NPCM7XX_CLOCK_CPUCKSEL,
546
+ .divide = shift_by_reg_divisor,
547
+ .reg = NPCM7XX_CLK_CLKDIV1,
548
+ .offset = 0,
549
+ .len = 1,
550
+ .public_name = "clk2"
551
+ },
552
+ [NPCM7XX_CLOCK_AHB_DIVIDER] = {
553
+ .name = "ahb-divider",
554
+ .src_type = CLKSRC_DIV,
555
+ .src_index = NPCM7XX_CLOCK_AXI_DIVIDER,
556
+ .divide = divide_by_reg_divisor,
557
+ .reg = NPCM7XX_CLK_CLKDIV1,
558
+ .offset = 26,
559
+ .len = 2,
560
+ .public_name = "clk4"
561
+ },
562
+ [NPCM7XX_CLOCK_AHB3_DIVIDER] = {
563
+ .name = "ahb3-divider",
564
+ .src_type = CLKSRC_DIV,
565
+ .src_index = NPCM7XX_CLOCK_AHB_DIVIDER,
566
+ .divide = divide_by_reg_divisor,
567
+ .reg = NPCM7XX_CLK_CLKDIV1,
568
+ .offset = 6,
569
+ .len = 5,
570
+ .public_name = "ahb3-spi3-clock"
571
+ },
572
+ [NPCM7XX_CLOCK_SPI0_DIVIDER] = {
573
+ .name = "spi0-divider",
574
+ .src_type = CLKSRC_DIV,
575
+ .src_index = NPCM7XX_CLOCK_AHB_DIVIDER,
576
+ .divide = divide_by_reg_divisor,
577
+ .reg = NPCM7XX_CLK_CLKDIV3,
578
+ .offset = 6,
579
+ .len = 5,
580
+ .public_name = "spi0-clock",
581
+ },
582
+ [NPCM7XX_CLOCK_SPIX_DIVIDER] = {
583
+ .name = "spix-divider",
584
+ .src_type = CLKSRC_DIV,
585
+ .src_index = NPCM7XX_CLOCK_AHB_DIVIDER,
586
+ .divide = divide_by_reg_divisor,
587
+ .reg = NPCM7XX_CLK_CLKDIV3,
588
+ .offset = 1,
589
+ .len = 5,
590
+ .public_name = "spix-clock",
591
+ },
592
+ [NPCM7XX_CLOCK_APB1_DIVIDER] = {
593
+ .name = "apb1-divider",
594
+ .src_type = CLKSRC_DIV,
595
+ .src_index = NPCM7XX_CLOCK_AHB_DIVIDER,
596
+ .divide = shift_by_reg_divisor,
597
+ .reg = NPCM7XX_CLK_CLKDIV2,
598
+ .offset = 24,
599
+ .len = 2,
600
+ .public_name = "apb1-clock",
601
+ },
602
+ [NPCM7XX_CLOCK_APB2_DIVIDER] = {
603
+ .name = "apb2-divider",
604
+ .src_type = CLKSRC_DIV,
605
+ .src_index = NPCM7XX_CLOCK_AHB_DIVIDER,
606
+ .divide = shift_by_reg_divisor,
607
+ .reg = NPCM7XX_CLK_CLKDIV2,
608
+ .offset = 26,
609
+ .len = 2,
610
+ .public_name = "apb2-clock",
611
+ },
612
+ [NPCM7XX_CLOCK_APB3_DIVIDER] = {
613
+ .name = "apb3-divider",
614
+ .src_type = CLKSRC_DIV,
615
+ .src_index = NPCM7XX_CLOCK_AHB_DIVIDER,
616
+ .divide = shift_by_reg_divisor,
617
+ .reg = NPCM7XX_CLK_CLKDIV2,
618
+ .offset = 28,
619
+ .len = 2,
620
+ .public_name = "apb3-clock",
621
+ },
622
+ [NPCM7XX_CLOCK_APB4_DIVIDER] = {
623
+ .name = "apb4-divider",
624
+ .src_type = CLKSRC_DIV,
625
+ .src_index = NPCM7XX_CLOCK_AHB_DIVIDER,
626
+ .divide = shift_by_reg_divisor,
627
+ .reg = NPCM7XX_CLK_CLKDIV2,
628
+ .offset = 30,
629
+ .len = 2,
630
+ .public_name = "apb4-clock",
631
+ },
632
+ [NPCM7XX_CLOCK_APB5_DIVIDER] = {
633
+ .name = "apb5-divider",
634
+ .src_type = CLKSRC_DIV,
635
+ .src_index = NPCM7XX_CLOCK_AHB_DIVIDER,
636
+ .divide = shift_by_reg_divisor,
637
+ .reg = NPCM7XX_CLK_CLKDIV2,
638
+ .offset = 22,
639
+ .len = 2,
640
+ .public_name = "apb5-clock",
641
+ },
642
+ [NPCM7XX_CLOCK_CLKOUT_DIVIDER] = {
643
+ .name = "clkout-divider",
644
+ .src_type = CLKSRC_SEL,
645
+ .src_index = NPCM7XX_CLOCK_CLKOUTSEL,
646
+ .divide = divide_by_reg_divisor,
647
+ .reg = NPCM7XX_CLK_CLKDIV2,
648
+ .offset = 16,
649
+ .len = 5,
650
+ .public_name = "clkout",
651
+ },
652
+ [NPCM7XX_CLOCK_UART_DIVIDER] = {
653
+ .name = "uart-divider",
654
+ .src_type = CLKSRC_SEL,
655
+ .src_index = NPCM7XX_CLOCK_UARTCKSEL,
656
+ .divide = divide_by_reg_divisor,
657
+ .reg = NPCM7XX_CLK_CLKDIV1,
658
+ .offset = 16,
659
+ .len = 5,
660
+ .public_name = "uart-clock",
661
+ },
662
+ [NPCM7XX_CLOCK_TIMER_DIVIDER] = {
663
+ .name = "timer-divider",
664
+ .src_type = CLKSRC_SEL,
665
+ .src_index = NPCM7XX_CLOCK_TIMCKSEL,
666
+ .divide = divide_by_reg_divisor,
667
+ .reg = NPCM7XX_CLK_CLKDIV1,
668
+ .offset = 21,
669
+ .len = 5,
670
+ .public_name = "timer-clock",
671
+ },
672
+ [NPCM7XX_CLOCK_ADC_DIVIDER] = {
673
+ .name = "adc-divider",
674
+ .src_type = CLKSRC_DIV,
675
+ .src_index = NPCM7XX_CLOCK_TIMER_DIVIDER,
676
+ .divide = shift_by_reg_divisor,
677
+ .reg = NPCM7XX_CLK_CLKDIV1,
678
+ .offset = 28,
679
+ .len = 3,
680
+ .public_name = "adc-clock",
681
+ },
682
+ [NPCM7XX_CLOCK_MMC_DIVIDER] = {
683
+ .name = "mmc-divider",
684
+ .src_type = CLKSRC_SEL,
685
+ .src_index = NPCM7XX_CLOCK_SDCKSEL,
686
+ .divide = divide_by_reg_divisor,
687
+ .reg = NPCM7XX_CLK_CLKDIV1,
688
+ .offset = 11,
689
+ .len = 5,
690
+ .public_name = "mmc-clock",
691
+ },
692
+ [NPCM7XX_CLOCK_SDHC_DIVIDER] = {
693
+ .name = "sdhc-divider",
694
+ .src_type = CLKSRC_SEL,
695
+ .src_index = NPCM7XX_CLOCK_SDCKSEL,
696
+ .divide = divide_by_reg_divisor_times_2,
697
+ .reg = NPCM7XX_CLK_CLKDIV2,
698
+ .offset = 0,
699
+ .len = 4,
700
+ .public_name = "sdhc-clock",
701
+ },
702
+ [NPCM7XX_CLOCK_GFXM_DIVIDER] = {
703
+ .name = "gfxm-divider",
704
+ .src_type = CLKSRC_SEL,
705
+ .src_index = NPCM7XX_CLOCK_GFXMSEL,
706
+ .divide = divide_by_constant,
707
+ .divisor = 3,
708
+ .public_name = "gfxm-clock",
709
+ },
710
+ [NPCM7XX_CLOCK_UTMI_DIVIDER] = {
711
+ .name = "utmi-divider",
712
+ .src_type = CLKSRC_SEL,
713
+ .src_index = NPCM7XX_CLOCK_SUCKSEL,
714
+ .divide = divide_by_reg_divisor,
715
+ .reg = NPCM7XX_CLK_CLKDIV2,
716
+ .offset = 8,
717
+ .len = 5,
718
+ .public_name = "utmi-clock",
719
+ },
720
+};
721
+
722
+static void npcm7xx_clk_pll_init(Object *obj)
723
+{
724
+ NPCM7xxClockPLLState *pll = NPCM7XX_CLOCK_PLL(obj);
725
+
726
+ pll->clock_in = qdev_init_clock_in(DEVICE(pll), "clock-in",
727
+ npcm7xx_clk_update_pll, pll);
728
+ pll->clock_out = qdev_init_clock_out(DEVICE(pll), "clock-out");
729
+}
730
+
731
+static void npcm7xx_clk_sel_init(Object *obj)
732
+{
733
+ int i;
734
+ NPCM7xxClockSELState *sel = NPCM7XX_CLOCK_SEL(obj);
735
+
736
+ for (i = 0; i < NPCM7XX_CLK_SEL_MAX_INPUT; ++i) {
737
+ sel->clock_in[i] = qdev_init_clock_in(DEVICE(sel),
738
+ g_strdup_printf("clock-in[%d]", i),
739
+ npcm7xx_clk_update_sel, sel);
740
+ }
741
+ sel->clock_out = qdev_init_clock_out(DEVICE(sel), "clock-out");
742
+}
743
+static void npcm7xx_clk_divider_init(Object *obj)
744
+{
745
+ NPCM7xxClockDividerState *div = NPCM7XX_CLOCK_DIVIDER(obj);
746
+
747
+ div->clock_in = qdev_init_clock_in(DEVICE(div), "clock-in",
748
+ npcm7xx_clk_update_divider, div);
749
+ div->clock_out = qdev_init_clock_out(DEVICE(div), "clock-out");
750
+}
751
+
752
+static void npcm7xx_init_clock_pll(NPCM7xxClockPLLState *pll,
753
+ NPCM7xxCLKState *clk, const PLLInitInfo *init_info)
754
+{
755
+ pll->name = init_info->name;
756
+ pll->clk = clk;
757
+ pll->reg = init_info->reg;
758
+ if (init_info->public_name != NULL) {
759
+ qdev_alias_clock(DEVICE(pll), "clock-out", DEVICE(clk),
760
+ init_info->public_name);
761
+ }
762
+}
763
+
764
+static void npcm7xx_init_clock_sel(NPCM7xxClockSELState *sel,
765
+ NPCM7xxCLKState *clk, const SELInitInfo *init_info)
766
+{
767
+ int input_size = init_info->input_size;
768
+
769
+ sel->name = init_info->name;
770
+ sel->clk = clk;
771
+ sel->input_size = init_info->input_size;
772
+ g_assert(input_size <= NPCM7XX_CLK_SEL_MAX_INPUT);
773
+ sel->offset = init_info->offset;
774
+ sel->len = init_info->len;
775
+ if (init_info->public_name != NULL) {
776
+ qdev_alias_clock(DEVICE(sel), "clock-out", DEVICE(clk),
777
+ init_info->public_name);
778
+ }
779
+}
780
+
781
+static void npcm7xx_init_clock_divider(NPCM7xxClockDividerState *div,
782
+ NPCM7xxCLKState *clk, const DividerInitInfo *init_info)
783
+{
784
+ div->name = init_info->name;
785
+ div->clk = clk;
786
+
787
+ div->divide = init_info->divide;
788
+ if (div->divide == divide_by_constant) {
789
+ div->divisor = init_info->divisor;
790
+ } else {
791
+ div->reg = init_info->reg;
792
+ div->offset = init_info->offset;
793
+ div->len = init_info->len;
794
+ }
795
+ if (init_info->public_name != NULL) {
796
+ qdev_alias_clock(DEVICE(div), "clock-out", DEVICE(clk),
797
+ init_info->public_name);
798
+ }
799
+}
800
+
801
+static Clock *npcm7xx_get_clock(NPCM7xxCLKState *clk, ClockSrcType type,
802
+ int index)
803
+{
804
+ switch (type) {
805
+ case CLKSRC_REF:
806
+ return clk->clkref;
807
+ case CLKSRC_PLL:
808
+ return clk->plls[index].clock_out;
809
+ case CLKSRC_SEL:
810
+ return clk->sels[index].clock_out;
811
+ case CLKSRC_DIV:
812
+ return clk->dividers[index].clock_out;
813
+ default:
814
+ g_assert_not_reached();
815
+ }
816
+}
817
+
818
+static void npcm7xx_connect_clocks(NPCM7xxCLKState *clk)
819
+{
820
+ int i, j;
821
+ Clock *src;
822
+
823
+ for (i = 0; i < NPCM7XX_CLOCK_NR_PLLS; ++i) {
824
+ src = npcm7xx_get_clock(clk, pll_init_info_list[i].src_type,
825
+ pll_init_info_list[i].src_index);
826
+ clock_set_source(clk->plls[i].clock_in, src);
827
+ }
828
+ for (i = 0; i < NPCM7XX_CLOCK_NR_SELS; ++i) {
829
+ for (j = 0; j < sel_init_info_list[i].input_size; ++j) {
830
+ src = npcm7xx_get_clock(clk, sel_init_info_list[i].src_type[j],
831
+ sel_init_info_list[i].src_index[j]);
832
+ clock_set_source(clk->sels[i].clock_in[j], src);
833
+ }
834
+ }
835
+ for (i = 0; i < NPCM7XX_CLOCK_NR_DIVIDERS; ++i) {
836
+ src = npcm7xx_get_clock(clk, divider_init_info_list[i].src_type,
837
+ divider_init_info_list[i].src_index);
838
+ clock_set_source(clk->dividers[i].clock_in, src);
839
+ }
840
+}
841
+
842
static uint64_t npcm7xx_clk_read(void *opaque, hwaddr offset, unsigned size)
843
{
36
{
844
uint32_t reg = offset / sizeof(uint32_t);
37
s->regs[R_DMASR] = DMASR_HALTED; /* starts up halted. */
845
@@ -XXX,XX +XXX,XX @@ static uint64_t npcm7xx_clk_read(void *opaque, hwaddr offset, unsigned size)
38
@@ -XXX,XX +XXX,XX @@ static void stream_process_mem2s(struct Stream *s, StreamSink *tx_data_dev,
846
*
39
uint64_t addr;
847
* The 4 LSBs are always zero: (1e9 / 640) << 4 = 25000000.
40
bool eop;
848
*/
41
849
- value = (((now_ns - s->ref_ns) / 640) << 4) % NPCM7XX_TIMER_REF_HZ;
42
- if (!stream_running(s) || stream_idle(s)) {
850
+ value = (((now_ns - s->ref_ns) / 640) << 4) % NPCM7XX_CLOCK_REF_HZ;
43
+ if (!stream_running(s) || stream_idle(s) || stream_halted(s)) {
851
break;
852
853
default:
854
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_clk_write(void *opaque, hwaddr offset,
855
value |= (value & PLLCON_LOKS);
856
}
857
}
858
+ /* Only update PLL when it is locked. */
859
+ if (value & PLLCON_LOKI) {
860
+ npcm7xx_clk_update_pll(&s->plls[find_pll_by_reg(reg)]);
861
+ }
862
+ break;
863
+
864
+ case NPCM7XX_CLK_CLKSEL:
865
+ npcm7xx_clk_update_all_sels(s);
866
+ break;
867
+
868
+ case NPCM7XX_CLK_CLKDIV1:
869
+ case NPCM7XX_CLK_CLKDIV2:
870
+ case NPCM7XX_CLK_CLKDIV3:
871
+ npcm7xx_clk_update_all_dividers(s);
872
break;
873
874
case NPCM7XX_CLK_CNTR25M:
875
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_clk_enter_reset(Object *obj, ResetType type)
876
case RESET_TYPE_COLD:
877
memcpy(s->regs, cold_reset_values, sizeof(cold_reset_values));
878
s->ref_ns = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
879
+ npcm7xx_clk_update_all_clocks(s);
880
return;
44
return;
881
}
45
}
882
46
883
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_clk_enter_reset(Object *obj, ResetType type)
47
@@ -XXX,XX +XXX,XX @@ static size_t stream_process_s2mem(struct Stream *s, unsigned char *buf,
884
__func__, type);
48
unsigned int rxlen;
885
}
49
size_t pos = 0;
886
50
887
+static void npcm7xx_clk_init_clock_hierarchy(NPCM7xxCLKState *s)
51
- if (!stream_running(s) || stream_idle(s)) {
888
+{
52
+ if (!stream_running(s) || stream_idle(s) || stream_halted(s)) {
889
+ int i;
53
return 0;
890
+
54
}
891
+ s->clkref = qdev_init_clock_in(DEVICE(s), "clkref", NULL, NULL);
55
892
+
56
@@ -XXX,XX +XXX,XX @@ xilinx_axidma_data_stream_can_push(StreamSink *obj,
893
+ /* First pass: init all converter modules */
57
XilinxAXIDMAStreamSink *ds = XILINX_AXI_DMA_DATA_STREAM(obj);
894
+ QEMU_BUILD_BUG_ON(ARRAY_SIZE(pll_init_info_list) != NPCM7XX_CLOCK_NR_PLLS);
58
struct Stream *s = &ds->dma->streams[1];
895
+ QEMU_BUILD_BUG_ON(ARRAY_SIZE(sel_init_info_list) != NPCM7XX_CLOCK_NR_SELS);
59
896
+ QEMU_BUILD_BUG_ON(ARRAY_SIZE(divider_init_info_list)
60
- if (!stream_running(s) || stream_idle(s)) {
897
+ != NPCM7XX_CLOCK_NR_DIVIDERS);
61
+ if (!stream_running(s) || stream_idle(s) || stream_halted(s)) {
898
+ for (i = 0; i < NPCM7XX_CLOCK_NR_PLLS; ++i) {
62
ds->dma->notify = notify;
899
+ object_initialize_child(OBJECT(s), pll_init_info_list[i].name,
63
ds->dma->notify_opaque = notify_opaque;
900
+ &s->plls[i], TYPE_NPCM7XX_CLOCK_PLL);
64
return false;
901
+ npcm7xx_init_clock_pll(&s->plls[i], s,
902
+ &pll_init_info_list[i]);
903
+ }
904
+ for (i = 0; i < NPCM7XX_CLOCK_NR_SELS; ++i) {
905
+ object_initialize_child(OBJECT(s), sel_init_info_list[i].name,
906
+ &s->sels[i], TYPE_NPCM7XX_CLOCK_SEL);
907
+ npcm7xx_init_clock_sel(&s->sels[i], s,
908
+ &sel_init_info_list[i]);
909
+ }
910
+ for (i = 0; i < NPCM7XX_CLOCK_NR_DIVIDERS; ++i) {
911
+ object_initialize_child(OBJECT(s), divider_init_info_list[i].name,
912
+ &s->dividers[i], TYPE_NPCM7XX_CLOCK_DIVIDER);
913
+ npcm7xx_init_clock_divider(&s->dividers[i], s,
914
+ &divider_init_info_list[i]);
915
+ }
916
+
917
+ /* Second pass: connect converter modules */
918
+ npcm7xx_connect_clocks(s);
919
+
920
+ clock_update_hz(s->clkref, NPCM7XX_CLOCK_REF_HZ);
921
+}
922
+
923
static void npcm7xx_clk_init(Object *obj)
924
{
925
NPCM7xxCLKState *s = NPCM7XX_CLK(obj);
926
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_clk_init(Object *obj)
927
memory_region_init_io(&s->iomem, obj, &npcm7xx_clk_ops, s,
928
TYPE_NPCM7XX_CLK, 4 * KiB);
929
sysbus_init_mmio(&s->parent, &s->iomem);
930
- qdev_init_gpio_in_named(DEVICE(s), npcm7xx_clk_perform_watchdog_reset,
931
- NPCM7XX_WATCHDOG_RESET_GPIO_IN, NPCM7XX_NR_WATCHDOGS);
932
}
933
934
-static const VMStateDescription vmstate_npcm7xx_clk = {
935
- .name = "npcm7xx-clk",
936
+static int npcm7xx_clk_post_load(void *opaque, int version_id)
937
+{
938
+ if (version_id >= 1) {
939
+ NPCM7xxCLKState *clk = opaque;
940
+
941
+ npcm7xx_clk_update_all_clocks(clk);
942
+ }
943
+
944
+ return 0;
945
+}
946
+
947
+static void npcm7xx_clk_realize(DeviceState *dev, Error **errp)
948
+{
949
+ int i;
950
+ NPCM7xxCLKState *s = NPCM7XX_CLK(dev);
951
+
952
+ qdev_init_gpio_in_named(DEVICE(s), npcm7xx_clk_perform_watchdog_reset,
953
+ NPCM7XX_WATCHDOG_RESET_GPIO_IN, NPCM7XX_NR_WATCHDOGS);
954
+ npcm7xx_clk_init_clock_hierarchy(s);
955
+
956
+ /* Realize child devices */
957
+ for (i = 0; i < NPCM7XX_CLOCK_NR_PLLS; ++i) {
958
+ if (!qdev_realize(DEVICE(&s->plls[i]), NULL, errp)) {
959
+ return;
960
+ }
961
+ }
962
+ for (i = 0; i < NPCM7XX_CLOCK_NR_SELS; ++i) {
963
+ if (!qdev_realize(DEVICE(&s->sels[i]), NULL, errp)) {
964
+ return;
965
+ }
966
+ }
967
+ for (i = 0; i < NPCM7XX_CLOCK_NR_DIVIDERS; ++i) {
968
+ if (!qdev_realize(DEVICE(&s->dividers[i]), NULL, errp)) {
969
+ return;
970
+ }
971
+ }
972
+}
973
+
974
+static const VMStateDescription vmstate_npcm7xx_clk_pll = {
975
+ .name = "npcm7xx-clock-pll",
976
.version_id = 0,
977
.minimum_version_id = 0,
978
- .fields = (VMStateField[]) {
979
- VMSTATE_UINT32_ARRAY(regs, NPCM7xxCLKState, NPCM7XX_CLK_NR_REGS),
980
- VMSTATE_INT64(ref_ns, NPCM7xxCLKState),
981
+ .fields = (VMStateField[]) {
982
+ VMSTATE_CLOCK(clock_in, NPCM7xxClockPLLState),
983
VMSTATE_END_OF_LIST(),
984
},
985
};
986
987
+static const VMStateDescription vmstate_npcm7xx_clk_sel = {
988
+ .name = "npcm7xx-clock-sel",
989
+ .version_id = 0,
990
+ .minimum_version_id = 0,
991
+ .fields = (VMStateField[]) {
992
+ VMSTATE_ARRAY_OF_POINTER_TO_STRUCT(clock_in, NPCM7xxClockSELState,
993
+ NPCM7XX_CLK_SEL_MAX_INPUT, 0, vmstate_clock, Clock),
994
+ VMSTATE_END_OF_LIST(),
995
+ },
996
+};
997
+
998
+static const VMStateDescription vmstate_npcm7xx_clk_divider = {
999
+ .name = "npcm7xx-clock-divider",
1000
+ .version_id = 0,
1001
+ .minimum_version_id = 0,
1002
+ .fields = (VMStateField[]) {
1003
+ VMSTATE_CLOCK(clock_in, NPCM7xxClockDividerState),
1004
+ VMSTATE_END_OF_LIST(),
1005
+ },
1006
+};
1007
+
1008
+static const VMStateDescription vmstate_npcm7xx_clk = {
1009
+ .name = "npcm7xx-clk",
1010
+ .version_id = 1,
1011
+ .minimum_version_id = 1,
1012
+ .post_load = npcm7xx_clk_post_load,
1013
+ .fields = (VMStateField[]) {
1014
+ VMSTATE_UINT32_ARRAY(regs, NPCM7xxCLKState, NPCM7XX_CLK_NR_REGS),
1015
+ VMSTATE_INT64(ref_ns, NPCM7xxCLKState),
1016
+ VMSTATE_CLOCK(clkref, NPCM7xxCLKState),
1017
+ VMSTATE_END_OF_LIST(),
1018
+ },
1019
+};
1020
+
1021
+static void npcm7xx_clk_pll_class_init(ObjectClass *klass, void *data)
1022
+{
1023
+ DeviceClass *dc = DEVICE_CLASS(klass);
1024
+
1025
+ dc->desc = "NPCM7xx Clock PLL Module";
1026
+ dc->vmsd = &vmstate_npcm7xx_clk_pll;
1027
+}
1028
+
1029
+static void npcm7xx_clk_sel_class_init(ObjectClass *klass, void *data)
1030
+{
1031
+ DeviceClass *dc = DEVICE_CLASS(klass);
1032
+
1033
+ dc->desc = "NPCM7xx Clock SEL Module";
1034
+ dc->vmsd = &vmstate_npcm7xx_clk_sel;
1035
+}
1036
+
1037
+static void npcm7xx_clk_divider_class_init(ObjectClass *klass, void *data)
1038
+{
1039
+ DeviceClass *dc = DEVICE_CLASS(klass);
1040
+
1041
+ dc->desc = "NPCM7xx Clock Divider Module";
1042
+ dc->vmsd = &vmstate_npcm7xx_clk_divider;
1043
+}
1044
+
1045
static void npcm7xx_clk_class_init(ObjectClass *klass, void *data)
1046
{
1047
ResettableClass *rc = RESETTABLE_CLASS(klass);
1048
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_clk_class_init(ObjectClass *klass, void *data)
1049
1050
dc->desc = "NPCM7xx Clock Control Registers";
1051
dc->vmsd = &vmstate_npcm7xx_clk;
1052
+ dc->realize = npcm7xx_clk_realize;
1053
rc->phases.enter = npcm7xx_clk_enter_reset;
1054
}
1055
1056
+static const TypeInfo npcm7xx_clk_pll_info = {
1057
+ .name = TYPE_NPCM7XX_CLOCK_PLL,
1058
+ .parent = TYPE_DEVICE,
1059
+ .instance_size = sizeof(NPCM7xxClockPLLState),
1060
+ .instance_init = npcm7xx_clk_pll_init,
1061
+ .class_init = npcm7xx_clk_pll_class_init,
1062
+};
1063
+
1064
+static const TypeInfo npcm7xx_clk_sel_info = {
1065
+ .name = TYPE_NPCM7XX_CLOCK_SEL,
1066
+ .parent = TYPE_DEVICE,
1067
+ .instance_size = sizeof(NPCM7xxClockSELState),
1068
+ .instance_init = npcm7xx_clk_sel_init,
1069
+ .class_init = npcm7xx_clk_sel_class_init,
1070
+};
1071
+
1072
+static const TypeInfo npcm7xx_clk_divider_info = {
1073
+ .name = TYPE_NPCM7XX_CLOCK_DIVIDER,
1074
+ .parent = TYPE_DEVICE,
1075
+ .instance_size = sizeof(NPCM7xxClockDividerState),
1076
+ .instance_init = npcm7xx_clk_divider_init,
1077
+ .class_init = npcm7xx_clk_divider_class_init,
1078
+};
1079
+
1080
static const TypeInfo npcm7xx_clk_info = {
1081
.name = TYPE_NPCM7XX_CLK,
1082
.parent = TYPE_SYS_BUS_DEVICE,
1083
@@ -XXX,XX +XXX,XX @@ static const TypeInfo npcm7xx_clk_info = {
1084
1085
static void npcm7xx_clk_register_type(void)
1086
{
1087
+ type_register_static(&npcm7xx_clk_pll_info);
1088
+ type_register_static(&npcm7xx_clk_sel_info);
1089
+ type_register_static(&npcm7xx_clk_divider_info);
1090
type_register_static(&npcm7xx_clk_info);
1091
}
1092
type_init(npcm7xx_clk_register_type);
1093
--
65
--
1094
2.20.1
66
2.34.1
1095
67
1096
68
diff view generated by jsdifflib
[PULL 04/21] target/arm: make ARMCPU.clidr 64-bit
[PULL 13/21] hw/arm/xlnx-zynqmp: fix unsigned error when checking the RPUs number
1
From: Leif Lindholm <leif@nuviainc.com>
1
From: Clément Chigot <chigot@adacore.com>
2
2
3
The AArch64 view of CLIDR_EL1 extends the ICB field to include also bit
3
When passing --smp with a number lower than XLNX_ZYNQMP_NUM_APU_CPUS,
4
32, as well as adding a Ttype<n> field when FEAT_MTE is implemented.
4
the expression (ms->smp.cpus - XLNX_ZYNQMP_NUM_APU_CPUS) will result
5
Extend the clidr field to be able to hold this context.
5
in a positive number as ms->smp.cpus is a unsigned int.
6
This will raise the following error afterwards, as Qemu will try to
7
instantiate some additional RPUs.
8
| $ qemu-system-aarch64 --smp 1 -M xlnx-zcu102
9
| **
10
| ERROR:../src/tcg/tcg.c:777:tcg_register_thread:
11
| assertion failed: (n < tcg_max_ctxs)
6
12
7
Signed-off-by: Leif Lindholm <leif@nuviainc.com>
13
Signed-off-by: Clément Chigot <chigot@adacore.com>
8
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
14
Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
15
Tested-by: Francisco Iglesias <frasse.iglesias@gmail.com>
10
Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>
16
Message-id: 20230524143714.565792-1-chigot@adacore.com
11
Message-id: 20210108185154.8108-3-leif@nuviainc.com
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
18
---
14
target/arm/cpu.h | 2 +-
19
hw/arm/xlnx-zynqmp.c | 2 +-
15
1 file changed, 1 insertion(+), 1 deletion(-)
20
1 file changed, 1 insertion(+), 1 deletion(-)
16
21
17
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
22
diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
18
index XXXXXXX..XXXXXXX 100644
23
index XXXXXXX..XXXXXXX 100644
19
--- a/target/arm/cpu.h
24
--- a/hw/arm/xlnx-zynqmp.c
20
+++ b/target/arm/cpu.h
25
+++ b/hw/arm/xlnx-zynqmp.c
21
@@ -XXX,XX +XXX,XX @@ struct ARMCPU {
26
@@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_create_rpu(MachineState *ms, XlnxZynqMPState *s,
22
uint32_t id_afr0;
27
const char *boot_cpu, Error **errp)
23
uint64_t id_aa64afr0;
28
{
24
uint64_t id_aa64afr1;
29
int i;
25
- uint32_t clidr;
30
- int num_rpus = MIN(ms->smp.cpus - XLNX_ZYNQMP_NUM_APU_CPUS,
26
+ uint64_t clidr;
31
+ int num_rpus = MIN((int)(ms->smp.cpus - XLNX_ZYNQMP_NUM_APU_CPUS),
27
uint64_t mp_affinity; /* MP ID without feature bits */
32
XLNX_ZYNQMP_NUM_RPU_CPUS);
28
/* The elements of this array are the CCSIDR values for each cache,
33
29
* in the order L1DCache, L1ICache, L2DCache, L2ICache, etc.
34
if (num_rpus <= 0) {
30
--
35
--
31
2.20.1
36
2.34.1
32
37
33
38
diff view generated by jsdifflib
[PULL 19/21] hw/misc: Add QTest for NPCM7XX PWM Module
[PULL 14/21] tests/qtest: Run arm-specific tests only if the required machine is available
1
From: Hao Wu <wuhaotsh@google.com>
1
From: Thomas Huth <thuth@redhat.com>
2
2
3
We add a qtest for the PWM in the previous patch. It proves it works as
3
pflash-cfi02-test.c always uses the "musicpal" machine for testing,
4
expected.
4
test-arm-mptimer.c always uses the "vexpress-a9" machine, and
5
microbit-test.c requires the "microbit" machine, so we should only
6
run these tests if the machines have been enabled in the configuration.
5
7
6
Reviewed-by: Havard Skinnemoen <hskinnemoen@google.com>
8
Signed-off-by: Thomas Huth <thuth@redhat.com>
7
Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
9
Reviewed-by: Fabiano Rosas <farosas@suse.de>
8
Signed-off-by: Hao Wu <wuhaotsh@google.com>
10
Message-id: 20230524080600.1618137-1-thuth@redhat.com
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Message-id: 20210108190945.949196-6-wuhaotsh@google.com
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
12
---
13
tests/qtest/npcm7xx_pwm-test.c | 490 +++++++++++++++++++++++++++++++++
13
tests/qtest/meson.build | 7 ++++---
14
tests/qtest/meson.build | 1 +
14
1 file changed, 4 insertions(+), 3 deletions(-)
15
2 files changed, 491 insertions(+)
16
create mode 100644 tests/qtest/npcm7xx_pwm-test.c
17
15
18
diff --git a/tests/qtest/npcm7xx_pwm-test.c b/tests/qtest/npcm7xx_pwm-test.c
19
new file mode 100644
20
index XXXXXXX..XXXXXXX
21
--- /dev/null
22
+++ b/tests/qtest/npcm7xx_pwm-test.c
23
@@ -XXX,XX +XXX,XX @@
24
+/*
25
+ * QTests for Nuvoton NPCM7xx PWM Modules.
26
+ *
27
+ * Copyright 2020 Google LLC
28
+ *
29
+ * This program is free software; you can redistribute it and/or modify it
30
+ * under the terms of the GNU General Public License as published by the
31
+ * Free Software Foundation; either version 2 of the License, or
32
+ * (at your option) any later version.
33
+ *
34
+ * This program is distributed in the hope that it will be useful, but WITHOUT
35
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
36
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
37
+ * for more details.
38
+ */
39
+
40
+#include "qemu/osdep.h"
41
+#include "qemu/bitops.h"
42
+#include "libqos/libqtest.h"
43
+#include "qapi/qmp/qdict.h"
44
+#include "qapi/qmp/qnum.h"
45
+
46
+#define REF_HZ 25000000
47
+
48
+/* Register field definitions. */
49
+#define CH_EN BIT(0)
50
+#define CH_INV BIT(2)
51
+#define CH_MOD BIT(3)
52
+
53
+/* Registers shared between all PWMs in a module */
54
+#define PPR 0x00
55
+#define CSR 0x04
56
+#define PCR 0x08
57
+#define PIER 0x3c
58
+#define PIIR 0x40
59
+
60
+/* CLK module related */
61
+#define CLK_BA 0xf0801000
62
+#define CLKSEL 0x04
63
+#define CLKDIV1 0x08
64
+#define CLKDIV2 0x2c
65
+#define PLLCON0 0x0c
66
+#define PLLCON1 0x10
67
+#define PLL_INDV(rv) extract32((rv), 0, 6)
68
+#define PLL_FBDV(rv) extract32((rv), 16, 12)
69
+#define PLL_OTDV1(rv) extract32((rv), 8, 3)
70
+#define PLL_OTDV2(rv) extract32((rv), 13, 3)
71
+#define APB3CKDIV(rv) extract32((rv), 28, 2)
72
+#define CLK2CKDIV(rv) extract32((rv), 0, 1)
73
+#define CLK4CKDIV(rv) extract32((rv), 26, 2)
74
+#define CPUCKSEL(rv) extract32((rv), 0, 2)
75
+
76
+#define MAX_DUTY 1000000
77
+
78
+typedef struct PWMModule {
79
+ int irq;
80
+ uint64_t base_addr;
81
+} PWMModule;
82
+
83
+typedef struct PWM {
84
+ uint32_t cnr_offset;
85
+ uint32_t cmr_offset;
86
+ uint32_t pdr_offset;
87
+ uint32_t pwdr_offset;
88
+} PWM;
89
+
90
+typedef struct TestData {
91
+ const PWMModule *module;
92
+ const PWM *pwm;
93
+} TestData;
94
+
95
+static const PWMModule pwm_module_list[] = {
96
+ {
97
+ .irq = 93,
98
+ .base_addr = 0xf0103000
99
+ },
100
+ {
101
+ .irq = 94,
102
+ .base_addr = 0xf0104000
103
+ }
104
+};
105
+
106
+static const PWM pwm_list[] = {
107
+ {
108
+ .cnr_offset = 0x0c,
109
+ .cmr_offset = 0x10,
110
+ .pdr_offset = 0x14,
111
+ .pwdr_offset = 0x44,
112
+ },
113
+ {
114
+ .cnr_offset = 0x18,
115
+ .cmr_offset = 0x1c,
116
+ .pdr_offset = 0x20,
117
+ .pwdr_offset = 0x48,
118
+ },
119
+ {
120
+ .cnr_offset = 0x24,
121
+ .cmr_offset = 0x28,
122
+ .pdr_offset = 0x2c,
123
+ .pwdr_offset = 0x4c,
124
+ },
125
+ {
126
+ .cnr_offset = 0x30,
127
+ .cmr_offset = 0x34,
128
+ .pdr_offset = 0x38,
129
+ .pwdr_offset = 0x50,
130
+ },
131
+};
132
+
133
+static const int ppr_base[] = { 0, 0, 8, 8 };
134
+static const int csr_base[] = { 0, 4, 8, 12 };
135
+static const int pcr_base[] = { 0, 8, 12, 16 };
136
+
137
+static const uint32_t ppr_list[] = {
138
+ 0,
139
+ 1,
140
+ 10,
141
+ 100,
142
+ 255, /* Max possible value. */
143
+};
144
+
145
+static const uint32_t csr_list[] = {
146
+ 0,
147
+ 1,
148
+ 2,
149
+ 3,
150
+ 4, /* Max possible value. */
151
+};
152
+
153
+static const uint32_t cnr_list[] = {
154
+ 0,
155
+ 1,
156
+ 50,
157
+ 100,
158
+ 150,
159
+ 200,
160
+ 1000,
161
+ 10000,
162
+ 65535, /* Max possible value. */
163
+};
164
+
165
+static const uint32_t cmr_list[] = {
166
+ 0,
167
+ 1,
168
+ 10,
169
+ 50,
170
+ 100,
171
+ 150,
172
+ 200,
173
+ 1000,
174
+ 10000,
175
+ 65535, /* Max possible value. */
176
+};
177
+
178
+/* Returns the index of the PWM module. */
179
+static int pwm_module_index(const PWMModule *module)
180
+{
181
+ ptrdiff_t diff = module - pwm_module_list;
182
+
183
+ g_assert_true(diff >= 0 && diff < ARRAY_SIZE(pwm_module_list));
184
+
185
+ return diff;
186
+}
187
+
188
+/* Returns the index of the PWM entry. */
189
+static int pwm_index(const PWM *pwm)
190
+{
191
+ ptrdiff_t diff = pwm - pwm_list;
192
+
193
+ g_assert_true(diff >= 0 && diff < ARRAY_SIZE(pwm_list));
194
+
195
+ return diff;
196
+}
197
+
198
+static uint64_t pwm_qom_get(QTestState *qts, const char *path, const char *name)
199
+{
200
+ QDict *response;
201
+
202
+ g_test_message("Getting properties %s from %s", name, path);
203
+ response = qtest_qmp(qts, "{ 'execute': 'qom-get',"
204
+ " 'arguments': { 'path': %s, 'property': %s}}",
205
+ path, name);
206
+ /* The qom set message returns successfully. */
207
+ g_assert_true(qdict_haskey(response, "return"));
208
+ return qnum_get_uint(qobject_to(QNum, qdict_get(response, "return")));
209
+}
210
+
211
+static uint64_t pwm_get_freq(QTestState *qts, int module_index, int pwm_index)
212
+{
213
+ char path[100];
214
+ char name[100];
215
+
216
+ sprintf(path, "/machine/soc/pwm[%d]", module_index);
217
+ sprintf(name, "freq[%d]", pwm_index);
218
+
219
+ return pwm_qom_get(qts, path, name);
220
+}
221
+
222
+static uint64_t pwm_get_duty(QTestState *qts, int module_index, int pwm_index)
223
+{
224
+ char path[100];
225
+ char name[100];
226
+
227
+ sprintf(path, "/machine/soc/pwm[%d]", module_index);
228
+ sprintf(name, "duty[%d]", pwm_index);
229
+
230
+ return pwm_qom_get(qts, path, name);
231
+}
232
+
233
+static uint32_t get_pll(uint32_t con)
234
+{
235
+ return REF_HZ * PLL_FBDV(con) / (PLL_INDV(con) * PLL_OTDV1(con)
236
+ * PLL_OTDV2(con));
237
+}
238
+
239
+static uint64_t read_pclk(QTestState *qts)
240
+{
241
+ uint64_t freq = REF_HZ;
242
+ uint32_t clksel = qtest_readl(qts, CLK_BA + CLKSEL);
243
+ uint32_t pllcon;
244
+ uint32_t clkdiv1 = qtest_readl(qts, CLK_BA + CLKDIV1);
245
+ uint32_t clkdiv2 = qtest_readl(qts, CLK_BA + CLKDIV2);
246
+
247
+ switch (CPUCKSEL(clksel)) {
248
+ case 0:
249
+ pllcon = qtest_readl(qts, CLK_BA + PLLCON0);
250
+ freq = get_pll(pllcon);
251
+ break;
252
+ case 1:
253
+ pllcon = qtest_readl(qts, CLK_BA + PLLCON1);
254
+ freq = get_pll(pllcon);
255
+ break;
256
+ case 2:
257
+ break;
258
+ case 3:
259
+ break;
260
+ default:
261
+ g_assert_not_reached();
262
+ }
263
+
264
+ freq >>= (CLK2CKDIV(clkdiv1) + CLK4CKDIV(clkdiv1) + APB3CKDIV(clkdiv2));
265
+
266
+ return freq;
267
+}
268
+
269
+static uint32_t pwm_selector(uint32_t csr)
270
+{
271
+ switch (csr) {
272
+ case 0:
273
+ return 2;
274
+ case 1:
275
+ return 4;
276
+ case 2:
277
+ return 8;
278
+ case 3:
279
+ return 16;
280
+ case 4:
281
+ return 1;
282
+ default:
283
+ g_assert_not_reached();
284
+ }
285
+}
286
+
287
+static uint64_t pwm_compute_freq(QTestState *qts, uint32_t ppr, uint32_t csr,
288
+ uint32_t cnr)
289
+{
290
+ return read_pclk(qts) / ((ppr + 1) * pwm_selector(csr) * (cnr + 1));
291
+}
292
+
293
+static uint64_t pwm_compute_duty(uint32_t cnr, uint32_t cmr, bool inverted)
294
+{
295
+ uint64_t duty;
296
+
297
+ if (cnr == 0) {
298
+ /* PWM is stopped. */
299
+ duty = 0;
300
+ } else if (cmr >= cnr) {
301
+ duty = MAX_DUTY;
302
+ } else {
303
+ duty = MAX_DUTY * (cmr + 1) / (cnr + 1);
304
+ }
305
+
306
+ if (inverted) {
307
+ duty = MAX_DUTY - duty;
308
+ }
309
+
310
+ return duty;
311
+}
312
+
313
+static uint32_t pwm_read(QTestState *qts, const TestData *td, unsigned offset)
314
+{
315
+ return qtest_readl(qts, td->module->base_addr + offset);
316
+}
317
+
318
+static void pwm_write(QTestState *qts, const TestData *td, unsigned offset,
319
+ uint32_t value)
320
+{
321
+ qtest_writel(qts, td->module->base_addr + offset, value);
322
+}
323
+
324
+static uint32_t pwm_read_ppr(QTestState *qts, const TestData *td)
325
+{
326
+ return extract32(pwm_read(qts, td, PPR), ppr_base[pwm_index(td->pwm)], 8);
327
+}
328
+
329
+static void pwm_write_ppr(QTestState *qts, const TestData *td, uint32_t value)
330
+{
331
+ pwm_write(qts, td, PPR, value << ppr_base[pwm_index(td->pwm)]);
332
+}
333
+
334
+static uint32_t pwm_read_csr(QTestState *qts, const TestData *td)
335
+{
336
+ return extract32(pwm_read(qts, td, CSR), csr_base[pwm_index(td->pwm)], 3);
337
+}
338
+
339
+static void pwm_write_csr(QTestState *qts, const TestData *td, uint32_t value)
340
+{
341
+ pwm_write(qts, td, CSR, value << csr_base[pwm_index(td->pwm)]);
342
+}
343
+
344
+static uint32_t pwm_read_pcr(QTestState *qts, const TestData *td)
345
+{
346
+ return extract32(pwm_read(qts, td, PCR), pcr_base[pwm_index(td->pwm)], 4);
347
+}
348
+
349
+static void pwm_write_pcr(QTestState *qts, const TestData *td, uint32_t value)
350
+{
351
+ pwm_write(qts, td, PCR, value << pcr_base[pwm_index(td->pwm)]);
352
+}
353
+
354
+static uint32_t pwm_read_cnr(QTestState *qts, const TestData *td)
355
+{
356
+ return pwm_read(qts, td, td->pwm->cnr_offset);
357
+}
358
+
359
+static void pwm_write_cnr(QTestState *qts, const TestData *td, uint32_t value)
360
+{
361
+ pwm_write(qts, td, td->pwm->cnr_offset, value);
362
+}
363
+
364
+static uint32_t pwm_read_cmr(QTestState *qts, const TestData *td)
365
+{
366
+ return pwm_read(qts, td, td->pwm->cmr_offset);
367
+}
368
+
369
+static void pwm_write_cmr(QTestState *qts, const TestData *td, uint32_t value)
370
+{
371
+ pwm_write(qts, td, td->pwm->cmr_offset, value);
372
+}
373
+
374
+/* Check pwm registers can be reset to default value */
375
+static void test_init(gconstpointer test_data)
376
+{
377
+ const TestData *td = test_data;
378
+ QTestState *qts = qtest_init("-machine quanta-gsj");
379
+ int module = pwm_module_index(td->module);
380
+ int pwm = pwm_index(td->pwm);
381
+
382
+ g_assert_cmpuint(pwm_get_freq(qts, module, pwm), ==, 0);
383
+ g_assert_cmpuint(pwm_get_duty(qts, module, pwm), ==, 0);
384
+
385
+ qtest_quit(qts);
386
+}
387
+
388
+/* One-shot mode should not change frequency and duty cycle. */
389
+static void test_oneshot(gconstpointer test_data)
390
+{
391
+ const TestData *td = test_data;
392
+ QTestState *qts = qtest_init("-machine quanta-gsj");
393
+ int module = pwm_module_index(td->module);
394
+ int pwm = pwm_index(td->pwm);
395
+ uint32_t ppr, csr, pcr;
396
+ int i, j;
397
+
398
+ pcr = CH_EN;
399
+ for (i = 0; i < ARRAY_SIZE(ppr_list); ++i) {
400
+ ppr = ppr_list[i];
401
+ pwm_write_ppr(qts, td, ppr);
402
+
403
+ for (j = 0; j < ARRAY_SIZE(csr_list); ++j) {
404
+ csr = csr_list[j];
405
+ pwm_write_csr(qts, td, csr);
406
+ pwm_write_pcr(qts, td, pcr);
407
+
408
+ g_assert_cmpuint(pwm_read_ppr(qts, td), ==, ppr);
409
+ g_assert_cmpuint(pwm_read_csr(qts, td), ==, csr);
410
+ g_assert_cmpuint(pwm_read_pcr(qts, td), ==, pcr);
411
+ g_assert_cmpuint(pwm_get_freq(qts, module, pwm), ==, 0);
412
+ g_assert_cmpuint(pwm_get_duty(qts, module, pwm), ==, 0);
413
+ }
414
+ }
415
+
416
+ qtest_quit(qts);
417
+}
418
+
419
+/* In toggle mode, the PWM generates correct outputs. */
420
+static void test_toggle(gconstpointer test_data)
421
+{
422
+ const TestData *td = test_data;
423
+ QTestState *qts = qtest_init("-machine quanta-gsj");
424
+ int module = pwm_module_index(td->module);
425
+ int pwm = pwm_index(td->pwm);
426
+ uint32_t ppr, csr, pcr, cnr, cmr;
427
+ int i, j, k, l;
428
+ uint64_t expected_freq, expected_duty;
429
+
430
+ pcr = CH_EN | CH_MOD;
431
+ for (i = 0; i < ARRAY_SIZE(ppr_list); ++i) {
432
+ ppr = ppr_list[i];
433
+ pwm_write_ppr(qts, td, ppr);
434
+
435
+ for (j = 0; j < ARRAY_SIZE(csr_list); ++j) {
436
+ csr = csr_list[j];
437
+ pwm_write_csr(qts, td, csr);
438
+
439
+ for (k = 0; k < ARRAY_SIZE(cnr_list); ++k) {
440
+ cnr = cnr_list[k];
441
+ pwm_write_cnr(qts, td, cnr);
442
+
443
+ for (l = 0; l < ARRAY_SIZE(cmr_list); ++l) {
444
+ cmr = cmr_list[l];
445
+ pwm_write_cmr(qts, td, cmr);
446
+ expected_freq = pwm_compute_freq(qts, ppr, csr, cnr);
447
+ expected_duty = pwm_compute_duty(cnr, cmr, false);
448
+
449
+ pwm_write_pcr(qts, td, pcr);
450
+ g_assert_cmpuint(pwm_read_ppr(qts, td), ==, ppr);
451
+ g_assert_cmpuint(pwm_read_csr(qts, td), ==, csr);
452
+ g_assert_cmpuint(pwm_read_pcr(qts, td), ==, pcr);
453
+ g_assert_cmpuint(pwm_read_cnr(qts, td), ==, cnr);
454
+ g_assert_cmpuint(pwm_read_cmr(qts, td), ==, cmr);
455
+ g_assert_cmpuint(pwm_get_duty(qts, module, pwm),
456
+ ==, expected_duty);
457
+ if (expected_duty != 0 && expected_duty != 100) {
458
+ /* Duty cycle with 0 or 100 doesn't need frequency. */
459
+ g_assert_cmpuint(pwm_get_freq(qts, module, pwm),
460
+ ==, expected_freq);
461
+ }
462
+
463
+ /* Test inverted mode */
464
+ expected_duty = pwm_compute_duty(cnr, cmr, true);
465
+ pwm_write_pcr(qts, td, pcr | CH_INV);
466
+ g_assert_cmpuint(pwm_read_pcr(qts, td), ==, pcr | CH_INV);
467
+ g_assert_cmpuint(pwm_get_duty(qts, module, pwm),
468
+ ==, expected_duty);
469
+ if (expected_duty != 0 && expected_duty != 100) {
470
+ /* Duty cycle with 0 or 100 doesn't need frequency. */
471
+ g_assert_cmpuint(pwm_get_freq(qts, module, pwm),
472
+ ==, expected_freq);
473
+ }
474
+
475
+ }
476
+ }
477
+ }
478
+ }
479
+
480
+ qtest_quit(qts);
481
+}
482
+
483
+static void pwm_add_test(const char *name, const TestData* td,
484
+ GTestDataFunc fn)
485
+{
486
+ g_autofree char *full_name = g_strdup_printf(
487
+ "npcm7xx_pwm/module[%d]/pwm[%d]/%s", pwm_module_index(td->module),
488
+ pwm_index(td->pwm), name);
489
+ qtest_add_data_func(full_name, td, fn);
490
+}
491
+#define add_test(name, td) pwm_add_test(#name, td, test_##name)
492
+
493
+int main(int argc, char **argv)
494
+{
495
+ TestData test_data_list[ARRAY_SIZE(pwm_module_list) * ARRAY_SIZE(pwm_list)];
496
+
497
+ g_test_init(&argc, &argv, NULL);
498
+
499
+ for (int i = 0; i < ARRAY_SIZE(pwm_module_list); ++i) {
500
+ for (int j = 0; j < ARRAY_SIZE(pwm_list); ++j) {
501
+ TestData *td = &test_data_list[i * ARRAY_SIZE(pwm_list) + j];
502
+
503
+ td->module = &pwm_module_list[i];
504
+ td->pwm = &pwm_list[j];
505
+
506
+ add_test(init, td);
507
+ add_test(oneshot, td);
508
+ add_test(toggle, td);
509
+ }
510
+ }
511
+
512
+ return g_test_run();
513
+}
514
diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
16
diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
515
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
516
--- a/tests/qtest/meson.build
18
--- a/tests/qtest/meson.build
517
+++ b/tests/qtest/meson.build
19
+++ b/tests/qtest/meson.build
518
@@ -XXX,XX +XXX,XX @@ qtests_sparc64 = \
20
@@ -XXX,XX +XXX,XX @@ qtests_arm = \
519
qtests_npcm7xx = \
21
(config_all_devices.has_key('CONFIG_CMSDK_APB_DUALTIMER') ? ['cmsdk-apb-dualtimer-test'] : []) + \
520
['npcm7xx_adc-test',
22
(config_all_devices.has_key('CONFIG_CMSDK_APB_TIMER') ? ['cmsdk-apb-timer-test'] : []) + \
521
'npcm7xx_gpio-test',
23
(config_all_devices.has_key('CONFIG_CMSDK_APB_WATCHDOG') ? ['cmsdk-apb-watchdog-test'] : []) + \
522
+ 'npcm7xx_pwm-test',
24
- (config_all_devices.has_key('CONFIG_PFLASH_CFI02') ? ['pflash-cfi02-test'] : []) + \
523
'npcm7xx_rng-test',
25
+ (config_all_devices.has_key('CONFIG_PFLASH_CFI02') and
524
'npcm7xx_timer-test',
26
+ config_all_devices.has_key('CONFIG_MUSICPAL') ? ['pflash-cfi02-test'] : []) + \
525
'npcm7xx_watchdog_timer-test']
27
(config_all_devices.has_key('CONFIG_ASPEED_SOC') ? qtests_aspeed : []) + \
28
(config_all_devices.has_key('CONFIG_NPCM7XX') ? qtests_npcm7xx : []) + \
29
(config_all_devices.has_key('CONFIG_GENERIC_LOADER') ? ['hexloader-test'] : []) + \
30
(config_all_devices.has_key('CONFIG_TPM_TIS_I2C') ? ['tpm-tis-i2c-test'] : []) + \
31
+ (config_all_devices.has_key('CONFIG_VEXPRESS') ? ['test-arm-mptimer'] : []) + \
32
+ (config_all_devices.has_key('CONFIG_MICROBIT') ? ['microbit-test'] : []) + \
33
['arm-cpu-features',
34
- 'microbit-test',
35
- 'test-arm-mptimer',
36
'boot-serial-test']
37
38
# TODO: once aarch64 TCG is fixed on ARM 32 bit host, make bios-tables-test unconditional
526
--
39
--
527
2.20.1
40
2.34.1
528
529
diff view generated by jsdifflib
[PULL 12/21] target/arm: Don't decode insns in the XScale/iWMMXt space as cp insns
[PULL 15/21] target/arm: Explicitly select short-format FSR for M-profile
1
In commit cd8be50e58f63413c0 we converted the A32 coprocessor
1
For M-profile, there is no guest-facing A-profile format FSR, but we
2
insns to decodetree. This accidentally broke XScale/iWMMXt insns,
2
still use the env->exception.fsr field to pass fault information from
3
because it moved the handling of "cp insns which are handled
3
the point where a fault is raised to the code in
4
by looking up the cp register in the hashtable" from after the
4
arm_v7m_cpu_do_interrupt() which interprets it and sets the M-profile
5
call to the legacy disas_xscale_insn() decode to before it,
5
specific fault status registers. So it doesn't matter whether we
6
with the result that all XScale/iWMMXt insns now UNDEF.
6
fill in env->exception.fsr in the short format or the LPAE format, as
7
long as both sides agree. As it happens arm_v7m_cpu_do_interrupt()
8
assumes short-form.
7
9
8
Update valid_cp() so that it knows that on XScale cp 0 and 1
10
In compute_fsr_fsc() we weren't explicitly choosing short-form for
9
are not standard coprocessor instructions; this will cause
11
M-profile, but instead relied on it falling out in the wash because
10
the decodetree trans_ functions to ignore them, so that
12
arm_s1_regime_using_lpae_format() would be false. This was broken in
11
execution will correctly get through to the legacy decode again.
13
commit 452c67a4 when we added v8R support, because we said "PMSAv8 is
14
always LPAE format" (as it is for v8R), forgetting that we were
15
implicitly using this code path on M-profile. At that point we would
16
hit a g_assert_not_reached():
17
ERROR:../../target/arm/internals.h:549:arm_fi_to_lfsc: code should not be reached
12
18
19
#7 0x0000555555e055f7 in arm_fi_to_lfsc (fi=0x7fffecff9a90) at ../../target/arm/internals.h:549
20
#8 0x0000555555e05a27 in compute_fsr_fsc (env=0x555557356670, fi=0x7fffecff9a90, target_el=1, mmu_idx=1, ret_fsc=0x7fffecff9a1c)
21
at ../../target/arm/tlb_helper.c:95
22
#9 0x0000555555e05b62 in arm_deliver_fault (cpu=0x555557354800, addr=268961344, access_type=MMU_INST_FETCH, mmu_idx=1, fi=0x7fffecff9a90)
23
at ../../target/arm/tlb_helper.c:132
24
#10 0x0000555555e06095 in arm_cpu_tlb_fill (cs=0x555557354800, address=268961344, size=1, access_type=MMU_INST_FETCH, mmu_idx=1, probe=false, retaddr=0)
25
at ../../target/arm/tlb_helper.c:260
26
27
The specific assertion changed when commit fcc7404eff24b4c added
28
"assert not M-profile" to arm_is_secure_below_el3(), because the
29
conditions being checked in compute_fsr_fsc() include
30
arm_el_is_aa64(), which will end up calling arm_is_secure_below_el3()
31
and asserting before we try to call arm_fi_to_lfsc():
32
33
#7 0x0000555555efaf43 in arm_is_secure_below_el3 (env=0x5555574665a0) at ../../target/arm/cpu.h:2396
34
#8 0x0000555555efb103 in arm_is_el2_enabled (env=0x5555574665a0) at ../../target/arm/cpu.h:2448
35
#9 0x0000555555efb204 in arm_el_is_aa64 (env=0x5555574665a0, el=1) at ../../target/arm/cpu.h:2509
36
#10 0x0000555555efbdfd in compute_fsr_fsc (env=0x5555574665a0, fi=0x7fffecff99e0, target_el=1, mmu_idx=1, ret_fsc=0x7fffecff996c)
37
38
Avoid the assertion and the incorrect FSR format selection by
39
explicitly making M-profile use the short-format in this function.
40
41
Fixes: 452c67a42704 ("target/arm: Enable TTBCR_EAE for ARMv8-R AArch32")a
42
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1658
13
Cc: qemu-stable@nongnu.org
43
Cc: qemu-stable@nongnu.org
14
Reported-by: Guenter Roeck <linux@roeck-us.net>
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
44
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
45
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
17
Tested-by: Guenter Roeck <linux@roeck-us.net>
46
Message-id: 20230523131726.866635-1-peter.maydell@linaro.org
18
Message-id: 20210108195157.32067-1-peter.maydell@linaro.org
19
---
47
---
20
target/arm/translate.c | 7 +++++++
48
target/arm/tcg/tlb_helper.c | 13 +++++++++++--
21
1 file changed, 7 insertions(+)
49
1 file changed, 11 insertions(+), 2 deletions(-)
22
50
23
diff --git a/target/arm/translate.c b/target/arm/translate.c
51
diff --git a/target/arm/tcg/tlb_helper.c b/target/arm/tcg/tlb_helper.c
24
index XXXXXXX..XXXXXXX 100644
52
index XXXXXXX..XXXXXXX 100644
25
--- a/target/arm/translate.c
53
--- a/target/arm/tcg/tlb_helper.c
26
+++ b/target/arm/translate.c
54
+++ b/target/arm/tcg/tlb_helper.c
27
@@ -XXX,XX +XXX,XX @@ static bool valid_cp(DisasContext *s, int cp)
55
@@ -XXX,XX +XXX,XX @@ static uint32_t compute_fsr_fsc(CPUARMState *env, ARMMMUFaultInfo *fi,
28
* only cp14 and cp15 are valid, and other values aren't considered
56
ARMMMUIdx arm_mmu_idx = core_to_arm_mmu_idx(env, mmu_idx);
29
* to be in the coprocessor-instruction space at all. v8M still
57
uint32_t fsr, fsc;
30
* permits coprocessors 0..7.
58
31
+ * For XScale, we must not decode the XScale cp0, cp1 space as
59
- if (target_el == 2 || arm_el_is_aa64(env, target_el) ||
32
+ * a standard coprocessor insn, because we want to fall through to
60
- arm_s1_regime_using_lpae_format(env, arm_mmu_idx)) {
33
+ * the legacy disas_xscale_insn() decoder after decodetree is done.
61
+ /*
34
*/
62
+ * For M-profile there is no guest-facing FSR. We compute a
35
+ if (arm_dc_feature(s, ARM_FEATURE_XSCALE) && (cp == 0 || cp == 1)) {
63
+ * short-form value for env->exception.fsr which we will then
36
+ return false;
64
+ * examine in arm_v7m_cpu_do_interrupt(). In theory we could
37
+ }
65
+ * use the LPAE format instead as long as both bits of code agree
38
+
66
+ * (and arm_fi_to_lfsc() handled the M-profile specific
39
if (arm_dc_feature(s, ARM_FEATURE_V8) &&
67
+ * ARMFault_QEMU_NSCExec and ARMFault_QEMU_SFault cases).
40
!arm_dc_feature(s, ARM_FEATURE_M)) {
68
+ */
41
return cp >= 14;
69
+ if (!arm_feature(env, ARM_FEATURE_M) &&
70
+ (target_el == 2 || arm_el_is_aa64(env, target_el) ||
71
+ arm_s1_regime_using_lpae_format(env, arm_mmu_idx))) {
72
/*
73
* LPAE format fault status register : bottom 6 bits are
74
* status code in the same form as needed for syndrome
42
--
75
--
43
2.20.1
76
2.34.1
44
45
diff view generated by jsdifflib
[PULL 06/21] target/arm: add descriptions of CLIDR_EL1, CCSIDR_EL1, CTR_EL0 to cpu.h
[PULL 16/21] target/arm: Explain why we need to select ARM_V7M
1
From: Leif Lindholm <leif@nuviainc.com>
1
From: Fabiano Rosas <farosas@suse.de>
2
2
3
Signed-off-by: Leif Lindholm <leif@nuviainc.com>
3
We currently need to select ARM_V7M unconditionally when TCG is
4
Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>
4
present in the build because some translate.c helpers and the whole of
5
Message-id: 20210108185154.8108-5-leif@nuviainc.com
5
m_helpers.c are not yet under CONFIG_ARM_V7M.
6
7
Suggested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
8
Signed-off-by: Fabiano Rosas <farosas@suse.de>
9
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
10
Message-id: 20230523180525.29994-2-farosas@suse.de
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
12
---
8
target/arm/cpu.h | 31 +++++++++++++++++++++++++++++++
13
target/arm/Kconfig | 3 +++
9
1 file changed, 31 insertions(+)
14
1 file changed, 3 insertions(+)
10
15
11
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
16
diff --git a/target/arm/Kconfig b/target/arm/Kconfig
12
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/cpu.h
18
--- a/target/arm/Kconfig
14
+++ b/target/arm/cpu.h
19
+++ b/target/arm/Kconfig
15
@@ -XXX,XX +XXX,XX @@ FIELD(V7M_FPCCR, ASPEN, 31, 1)
20
@@ -XXX,XX +XXX,XX @@
16
/*
21
config ARM
17
* System register ID fields.
22
bool
18
*/
23
select ARM_COMPATIBLE_SEMIHOSTING if TCG
19
+FIELD(CLIDR_EL1, CTYPE1, 0, 3)
20
+FIELD(CLIDR_EL1, CTYPE2, 3, 3)
21
+FIELD(CLIDR_EL1, CTYPE3, 6, 3)
22
+FIELD(CLIDR_EL1, CTYPE4, 9, 3)
23
+FIELD(CLIDR_EL1, CTYPE5, 12, 3)
24
+FIELD(CLIDR_EL1, CTYPE6, 15, 3)
25
+FIELD(CLIDR_EL1, CTYPE7, 18, 3)
26
+FIELD(CLIDR_EL1, LOUIS, 21, 3)
27
+FIELD(CLIDR_EL1, LOC, 24, 3)
28
+FIELD(CLIDR_EL1, LOUU, 27, 3)
29
+FIELD(CLIDR_EL1, ICB, 30, 3)
30
+
24
+
31
+/* When FEAT_CCIDX is implemented */
25
+ # We need to select this until we move m_helper.c and the
32
+FIELD(CCSIDR_EL1, CCIDX_LINESIZE, 0, 3)
26
+ # translate.c v7m helpers under ARM_V7M.
33
+FIELD(CCSIDR_EL1, CCIDX_ASSOCIATIVITY, 3, 21)
27
select ARM_V7M if TCG
34
+FIELD(CCSIDR_EL1, CCIDX_NUMSETS, 32, 24)
28
35
+
29
config AARCH64
36
+/* When FEAT_CCIDX is not implemented */
37
+FIELD(CCSIDR_EL1, LINESIZE, 0, 3)
38
+FIELD(CCSIDR_EL1, ASSOCIATIVITY, 3, 10)
39
+FIELD(CCSIDR_EL1, NUMSETS, 13, 15)
40
+
41
+FIELD(CTR_EL0, IMINLINE, 0, 4)
42
+FIELD(CTR_EL0, L1IP, 14, 2)
43
+FIELD(CTR_EL0, DMINLINE, 16, 4)
44
+FIELD(CTR_EL0, ERG, 20, 4)
45
+FIELD(CTR_EL0, CWG, 24, 4)
46
+FIELD(CTR_EL0, IDC, 28, 1)
47
+FIELD(CTR_EL0, DIC, 29, 1)
48
+FIELD(CTR_EL0, TMINLINE, 32, 6)
49
+
50
FIELD(MIDR_EL1, REVISION, 0, 4)
51
FIELD(MIDR_EL1, PARTNUM, 4, 12)
52
FIELD(MIDR_EL1, ARCHITECTURE, 16, 4)
53
--
30
--
54
2.20.1
31
2.34.1
55
32
56
33
diff view generated by jsdifflib
[PULL 02/21] target/arm: enable Small Translation tables in max CPU
[PULL 17/21] arm/Kconfig: Keep Kconfig default entries in default.mak as documentation
1
From: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
1
From: Fabiano Rosas <farosas@suse.de>
2
2
3
Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
3
When we moved the arm default CONFIGs into Kconfig and removed them
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
4
from default.mak, we made it harder to identify which CONFIGs are
5
selected by default in case users want to disable them.
6
7
Bring back the default entries into default.mak, but keep them
8
commented out. This way users can keep their workflows of editing
9
default.mak to remove build options without needing to search through
10
Kconfig.
11
12
Reported-by: Thomas Huth <thuth@redhat.com>
13
Signed-off-by: Fabiano Rosas <farosas@suse.de>
14
Reviewed-by: Thomas Huth <thuth@redhat.com>
15
Message-id: 20230523180525.29994-3-farosas@suse.de
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
---
17
---
7
target/arm/cpu64.c | 1 +
18
configs/devices/aarch64-softmmu/default.mak | 6 ++++
8
1 file changed, 1 insertion(+)
19
configs/devices/arm-softmmu/default.mak | 40 +++++++++++++++++++++
20
2 files changed, 46 insertions(+)
9
21
10
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
22
diff --git a/configs/devices/aarch64-softmmu/default.mak b/configs/devices/aarch64-softmmu/default.mak
11
index XXXXXXX..XXXXXXX 100644
23
index XXXXXXX..XXXXXXX 100644
12
--- a/target/arm/cpu64.c
24
--- a/configs/devices/aarch64-softmmu/default.mak
13
+++ b/target/arm/cpu64.c
25
+++ b/configs/devices/aarch64-softmmu/default.mak
14
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
26
@@ -XXX,XX +XXX,XX @@
15
t = cpu->isar.id_aa64mmfr2;
27
16
t = FIELD_DP64(t, ID_AA64MMFR2, UAO, 1);
28
# We support all the 32 bit boards so need all their config
17
t = FIELD_DP64(t, ID_AA64MMFR2, CNP, 1); /* TTCNP */
29
include ../arm-softmmu/default.mak
18
+ t = FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* TTST */
30
+
19
cpu->isar.id_aa64mmfr2 = t;
31
+# These are selected by default when TCG is enabled, uncomment them to
20
32
+# keep out of the build.
21
/* Replicate the same data to the 32-bit id registers. */
33
+# CONFIG_XLNX_ZYNQMP_ARM=n
34
+# CONFIG_XLNX_VERSAL=n
35
+# CONFIG_SBSA_REF=n
36
diff --git a/configs/devices/arm-softmmu/default.mak b/configs/devices/arm-softmmu/default.mak
37
index XXXXXXX..XXXXXXX 100644
38
--- a/configs/devices/arm-softmmu/default.mak
39
+++ b/configs/devices/arm-softmmu/default.mak
40
@@ -XXX,XX +XXX,XX @@
41
# CONFIG_TEST_DEVICES=n
42
43
CONFIG_ARM_VIRT=y
44
+
45
+# These are selected by default when TCG is enabled, uncomment them to
46
+# keep out of the build.
47
+# CONFIG_CUBIEBOARD=n
48
+# CONFIG_EXYNOS4=n
49
+# CONFIG_HIGHBANK=n
50
+# CONFIG_INTEGRATOR=n
51
+# CONFIG_FSL_IMX31=n
52
+# CONFIG_MUSICPAL=n
53
+# CONFIG_MUSCA=n
54
+# CONFIG_CHEETAH=n
55
+# CONFIG_SX1=n
56
+# CONFIG_NSERIES=n
57
+# CONFIG_STELLARIS=n
58
+# CONFIG_STM32VLDISCOVERY=n
59
+# CONFIG_REALVIEW=n
60
+# CONFIG_VERSATILE=n
61
+# CONFIG_VEXPRESS=n
62
+# CONFIG_ZYNQ=n
63
+# CONFIG_MAINSTONE=n
64
+# CONFIG_GUMSTIX=n
65
+# CONFIG_SPITZ=n
66
+# CONFIG_TOSA=n
67
+# CONFIG_Z2=n
68
+# CONFIG_NPCM7XX=n
69
+# CONFIG_COLLIE=n
70
+# CONFIG_ASPEED_SOC=n
71
+# CONFIG_NETDUINO2=n
72
+# CONFIG_NETDUINOPLUS2=n
73
+# CONFIG_OLIMEX_STM32_H405=n
74
+# CONFIG_MPS2=n
75
+# CONFIG_RASPI=n
76
+# CONFIG_DIGIC=n
77
+# CONFIG_SABRELITE=n
78
+# CONFIG_EMCRAFT_SF2=n
79
+# CONFIG_MICROBIT=n
80
+# CONFIG_FSL_IMX25=n
81
+# CONFIG_FSL_IMX7=n
82
+# CONFIG_FSL_IMX6UL=n
83
+# CONFIG_ALLWINNER_H3=n
22
--
84
--
23
2.20.1
85
2.34.1
24
25
diff view generated by jsdifflib
[PULL 03/21] target/arm: fix typo in cpu.h ID_AA64PFR1 field name
[PULL 18/21] arm/Kconfig: Make TCG dependence explicit
1
From: Leif Lindholm <leif@nuviainc.com>
1
From: Fabiano Rosas <farosas@suse.de>
2
2
3
SBSS -> SSBS
3
Replace the 'default y if TCG' pattern with 'default y; depends on
4
4
TCG'.
5
Signed-off-by: Leif Lindholm <leif@nuviainc.com>
5
6
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
6
That makes explict that there is a dependence on TCG and enabling
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
these CONFIGs via .mak files without TCG present will fail earlier.
8
Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>
8
9
Message-id: 20210108185154.8108-2-leif@nuviainc.com
9
Suggested-by: Paolo Bonzini <pbonzini@redhat.com>
10
Signed-off-by: Fabiano Rosas <farosas@suse.de>
11
Reviewed-by: Thomas Huth <thuth@redhat.com>
12
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
13
Message-id: 20230523180525.29994-4-farosas@suse.de
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
15
---
12
target/arm/cpu.h | 2 +-
16
hw/arm/Kconfig | 123 ++++++++++++++++++++++++++++++++-----------------
13
1 file changed, 1 insertion(+), 1 deletion(-)
17
1 file changed, 82 insertions(+), 41 deletions(-)
14
18
15
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
19
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
16
index XXXXXXX..XXXXXXX 100644
20
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/cpu.h
21
--- a/hw/arm/Kconfig
18
+++ b/target/arm/cpu.h
22
+++ b/hw/arm/Kconfig
19
@@ -XXX,XX +XXX,XX @@ FIELD(ID_AA64PFR0, RAS, 28, 4)
23
@@ -XXX,XX +XXX,XX @@ config ARM_VIRT
20
FIELD(ID_AA64PFR0, SVE, 32, 4)
24
21
25
config CHEETAH
22
FIELD(ID_AA64PFR1, BT, 0, 4)
26
bool
23
-FIELD(ID_AA64PFR1, SBSS, 4, 4)
27
- default y if TCG && ARM
24
+FIELD(ID_AA64PFR1, SSBS, 4, 4)
28
+ default y
25
FIELD(ID_AA64PFR1, MTE, 8, 4)
29
+ depends on TCG && ARM
26
FIELD(ID_AA64PFR1, RAS_FRAC, 12, 4)
30
select OMAP
31
select TSC210X
32
33
config CUBIEBOARD
34
bool
35
- default y if TCG && ARM
36
+ default y
37
+ depends on TCG && ARM
38
select ALLWINNER_A10
39
40
config DIGIC
41
bool
42
- default y if TCG && ARM
43
+ default y
44
+ depends on TCG && ARM
45
select PTIMER
46
select PFLASH_CFI02
47
48
config EXYNOS4
49
bool
50
- default y if TCG && ARM
51
+ default y
52
+ depends on TCG && ARM
53
imply I2C_DEVICES
54
select A9MPCORE
55
select I2C
56
@@ -XXX,XX +XXX,XX @@ config EXYNOS4
57
58
config HIGHBANK
59
bool
60
- default y if TCG && ARM
61
+ default y
62
+ depends on TCG && ARM
63
select A9MPCORE
64
select A15MPCORE
65
select AHCI
66
@@ -XXX,XX +XXX,XX @@ config HIGHBANK
67
68
config INTEGRATOR
69
bool
70
- default y if TCG && ARM
71
+ default y
72
+ depends on TCG && ARM
73
select ARM_TIMER
74
select INTEGRATOR_DEBUG
75
select PL011 # UART
76
@@ -XXX,XX +XXX,XX @@ config INTEGRATOR
77
78
config MAINSTONE
79
bool
80
- default y if TCG && ARM
81
+ default y
82
+ depends on TCG && ARM
83
select PXA2XX
84
select PFLASH_CFI01
85
select SMC91C111
86
87
config MUSCA
88
bool
89
- default y if TCG && ARM
90
+ default y
91
+ depends on TCG && ARM
92
select ARMSSE
93
select PL011
94
select PL031
95
@@ -XXX,XX +XXX,XX @@ config MARVELL_88W8618
96
97
config MUSICPAL
98
bool
99
- default y if TCG && ARM
100
+ default y
101
+ depends on TCG && ARM
102
select OR_IRQ
103
select BITBANG_I2C
104
select MARVELL_88W8618
105
@@ -XXX,XX +XXX,XX @@ config MUSICPAL
106
107
config NETDUINO2
108
bool
109
- default y if TCG && ARM
110
+ default y
111
+ depends on TCG && ARM
112
select STM32F205_SOC
113
114
config NETDUINOPLUS2
115
bool
116
- default y if TCG && ARM
117
+ default y
118
+ depends on TCG && ARM
119
select STM32F405_SOC
120
121
config OLIMEX_STM32_H405
122
bool
123
- default y if TCG && ARM
124
+ default y
125
+ depends on TCG && ARM
126
select STM32F405_SOC
127
128
config NSERIES
129
bool
130
- default y if TCG && ARM
131
+ default y
132
+ depends on TCG && ARM
133
select OMAP
134
select TMP105 # temperature sensor
135
select BLIZZARD # LCD/TV controller
136
@@ -XXX,XX +XXX,XX @@ config PXA2XX
137
138
config GUMSTIX
139
bool
140
- default y if TCG && ARM
141
+ default y
142
+ depends on TCG && ARM
143
select PFLASH_CFI01
144
select SMC91C111
145
select PXA2XX
146
147
config TOSA
148
bool
149
- default y if TCG && ARM
150
+ default y
151
+ depends on TCG && ARM
152
select ZAURUS # scoop
153
select MICRODRIVE
154
select PXA2XX
155
@@ -XXX,XX +XXX,XX @@ config TOSA
156
157
config SPITZ
158
bool
159
- default y if TCG && ARM
160
+ default y
161
+ depends on TCG && ARM
162
select ADS7846 # touch-screen controller
163
select MAX111X # A/D converter
164
select WM8750 # audio codec
165
@@ -XXX,XX +XXX,XX @@ config SPITZ
166
167
config Z2
168
bool
169
- default y if TCG && ARM
170
+ default y
171
+ depends on TCG && ARM
172
select PFLASH_CFI01
173
select WM8750
174
select PL011 # UART
175
@@ -XXX,XX +XXX,XX @@ config Z2
176
177
config REALVIEW
178
bool
179
- default y if TCG && ARM
180
+ default y
181
+ depends on TCG && ARM
182
imply PCI_DEVICES
183
imply PCI_TESTDEV
184
imply I2C_DEVICES
185
@@ -XXX,XX +XXX,XX @@ config REALVIEW
186
187
config SBSA_REF
188
bool
189
- default y if TCG && AARCH64
190
+ default y
191
+ depends on TCG && AARCH64
192
imply PCI_DEVICES
193
select AHCI
194
select ARM_SMMUV3
195
@@ -XXX,XX +XXX,XX @@ config SBSA_REF
196
197
config SABRELITE
198
bool
199
- default y if TCG && ARM
200
+ default y
201
+ depends on TCG && ARM
202
select FSL_IMX6
203
select SSI_M25P80
204
205
config STELLARIS
206
bool
207
- default y if TCG && ARM
208
+ default y
209
+ depends on TCG && ARM
210
imply I2C_DEVICES
211
select ARM_V7M
212
select CMSDK_APB_WATCHDOG
213
@@ -XXX,XX +XXX,XX @@ config STELLARIS
214
215
config STM32VLDISCOVERY
216
bool
217
- default y if TCG && ARM
218
+ default y
219
+ depends on TCG && ARM
220
select STM32F100_SOC
221
222
config STRONGARM
223
@@ -XXX,XX +XXX,XX @@ config STRONGARM
224
225
config COLLIE
226
bool
227
- default y if TCG && ARM
228
+ default y
229
+ depends on TCG && ARM
230
select PFLASH_CFI01
231
select ZAURUS # scoop
232
select STRONGARM
233
234
config SX1
235
bool
236
- default y if TCG && ARM
237
+ default y
238
+ depends on TCG && ARM
239
select OMAP
240
241
config VERSATILE
242
bool
243
- default y if TCG && ARM
244
+ default y
245
+ depends on TCG && ARM
246
select ARM_TIMER # sp804
247
select PFLASH_CFI01
248
select LSI_SCSI_PCI
249
@@ -XXX,XX +XXX,XX @@ config VERSATILE
250
251
config VEXPRESS
252
bool
253
- default y if TCG && ARM
254
+ default y
255
+ depends on TCG && ARM
256
select A9MPCORE
257
select A15MPCORE
258
select ARM_MPTIMER
259
@@ -XXX,XX +XXX,XX @@ config VEXPRESS
260
261
config ZYNQ
262
bool
263
- default y if TCG && ARM
264
+ default y
265
+ depends on TCG && ARM
266
select A9MPCORE
267
select CADENCE # UART
268
select PFLASH_CFI02
269
@@ -XXX,XX +XXX,XX @@ config ZYNQ
270
config ARM_V7M
271
bool
272
# currently v7M must be included in a TCG build due to translate.c
273
- default y if TCG && ARM
274
+ default y
275
+ depends on TCG && ARM
276
select PTIMER
277
278
config ALLWINNER_A10
279
@@ -XXX,XX +XXX,XX @@ config ALLWINNER_A10
280
281
config ALLWINNER_H3
282
bool
283
- default y if TCG && ARM
284
+ default y
285
+ depends on TCG && ARM
286
select ALLWINNER_A10_PIT
287
select ALLWINNER_SUN8I_EMAC
288
select ALLWINNER_I2C
289
@@ -XXX,XX +XXX,XX @@ config ALLWINNER_H3
290
291
config RASPI
292
bool
293
- default y if TCG && ARM
294
+ default y
295
+ depends on TCG && ARM
296
select FRAMEBUFFER
297
select PL011 # UART
298
select SDHCI
299
@@ -XXX,XX +XXX,XX @@ config STM32F405_SOC
300
301
config XLNX_ZYNQMP_ARM
302
bool
303
- default y if TCG && AARCH64
304
+ default y
305
+ depends on TCG && AARCH64
306
select AHCI
307
select ARM_GIC
308
select CADENCE
309
@@ -XXX,XX +XXX,XX @@ config XLNX_ZYNQMP_ARM
310
311
config XLNX_VERSAL
312
bool
313
- default y if TCG && AARCH64
314
+ default y
315
+ depends on TCG && AARCH64
316
select ARM_GIC
317
select PL011
318
select CADENCE
319
@@ -XXX,XX +XXX,XX @@ config XLNX_VERSAL
320
321
config NPCM7XX
322
bool
323
- default y if TCG && ARM
324
+ default y
325
+ depends on TCG && ARM
326
select A9MPCORE
327
select ADM1272
328
select ARM_GIC
329
@@ -XXX,XX +XXX,XX @@ config NPCM7XX
330
331
config FSL_IMX25
332
bool
333
- default y if TCG && ARM
334
+ default y
335
+ depends on TCG && ARM
336
imply I2C_DEVICES
337
select IMX
338
select IMX_FEC
339
@@ -XXX,XX +XXX,XX @@ config FSL_IMX25
340
341
config FSL_IMX31
342
bool
343
- default y if TCG && ARM
344
+ default y
345
+ depends on TCG && ARM
346
imply I2C_DEVICES
347
select SERIAL
348
select IMX
349
@@ -XXX,XX +XXX,XX @@ config FSL_IMX6
350
351
config ASPEED_SOC
352
bool
353
- default y if TCG && ARM
354
+ default y
355
+ depends on TCG && ARM
356
select DS1338
357
select FTGMAC100
358
select I2C
359
@@ -XXX,XX +XXX,XX @@ config ASPEED_SOC
360
361
config MPS2
362
bool
363
- default y if TCG && ARM
364
+ default y
365
+ depends on TCG && ARM
366
imply I2C_DEVICES
367
select ARMSSE
368
select LAN9118
369
@@ -XXX,XX +XXX,XX @@ config MPS2
370
371
config FSL_IMX7
372
bool
373
- default y if TCG && ARM
374
+ default y
375
+ depends on TCG && ARM
376
imply PCI_DEVICES
377
imply TEST_DEVICES
378
imply I2C_DEVICES
379
@@ -XXX,XX +XXX,XX @@ config ARM_SMMUV3
380
381
config FSL_IMX6UL
382
bool
383
- default y if TCG && ARM
384
+ default y
385
+ depends on TCG && ARM
386
imply I2C_DEVICES
387
select A15MPCORE
388
select IMX
389
@@ -XXX,XX +XXX,XX @@ config FSL_IMX6UL
390
391
config MICROBIT
392
bool
393
- default y if TCG && ARM
394
+ default y
395
+ depends on TCG && ARM
396
select NRF51_SOC
397
398
config NRF51_SOC
399
@@ -XXX,XX +XXX,XX @@ config NRF51_SOC
400
401
config EMCRAFT_SF2
402
bool
403
- default y if TCG && ARM
404
+ default y
405
+ depends on TCG && ARM
406
select MSF2
407
select SSI_M25P80
27
408
28
--
409
--
29
2.20.1
410
2.34.1
30
411
31
412
diff view generated by jsdifflib
[PULL 11/21] docs: Build and install all the docs in a single manual
[PULL 19/21] Update copyright dates to 2023
1
When we first converted our documentation to Sphinx, we split it into
1
From: Enze Li <lienze@kylinos.cn>
2
multiple manuals (system, interop, tools, etc), which are all built
3
separately. The primary driver for this was wanting to be able to
4
avoid shipping the 'devel' manual to end-users. However, this is
5
working against the grain of the way Sphinx wants to be used and
6
causes some annoyances:
7
* Cross-references between documents become much harder or
8
possibly impossible
9
* There is no single index to the whole documentation
10
* Within one manual there's no links or table-of-contents info
11
that lets you easily navigate to the others
12
* The devel manual doesn't get published on the QEMU website
13
(it would be nice to able to refer to it there)
14
2
15
Merely hiding our developer documentation from end users seems like
3
I noticed that in the latest version, the copyright string is still
16
it's not enough benefit for these costs. Combine all the
4
2022, even though 2023 is halfway through. This patch fixes that and
17
documentation into a single manual (the same way that the readthedocs
5
fixes the documentation along with it.
18
site builds it) and install the whole thing. The previous manual
19
divisions remain as the new top level sections in the manual.
20
6
21
* The per-manual conf.py files are no longer needed
7
Signed-off-by: Enze Li <lienze@kylinos.cn>
22
* The man_pages[] specifications previously in each per-manual
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
23
conf.py move to the top level conf.py
9
Message-id: 20230525064345.1152801-1-lienze@kylinos.cn
24
* docs/meson.build logic is simplified as we now only need to run
25
Sphinx once for the HTML and then once for the manpages5B
26
* The old index.html.in that produced the top-level page with
27
links to each manual is no longer needed
28
29
Unfortunately this means that we now have to build the HTML
30
documentation into docs/manual in the build tree rather than directly
31
into docs/; otherwise it is too awkward to ensure we install only the
32
built manual and not also the dependency info, stamp file, etc. The
33
manual still ends up in the same place in the final installed
34
directory, but anybody who was consulting documentation from within
35
the build tree will have to adjust where they're looking.
36
37
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
38
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
39
Message-id: 20210108161416.21129-3-peter.maydell@linaro.org
40
---
11
---
41
docs/conf.py | 46 ++++++++++++++++++++++++++++++-
12
docs/conf.py | 2 +-
42
docs/devel/conf.py | 15 -----------
13
include/qemu/help-texts.h | 2 +-
43
docs/index.html.in | 17 ------------
14
2 files changed, 2 insertions(+), 2 deletions(-)
44
docs/interop/conf.py | 28 -------------------
45
docs/meson.build | 64 +++++++++++++++++---------------------------
46
docs/specs/conf.py | 16 -----------
47
docs/system/conf.py | 28 -------------------
48
docs/tools/conf.py | 37 -------------------------
49
docs/user/conf.py | 15 -----------
50
9 files changed, 70 insertions(+), 196 deletions(-)
51
delete mode 100644 docs/devel/conf.py
52
delete mode 100644 docs/index.html.in
53
delete mode 100644 docs/interop/conf.py
54
delete mode 100644 docs/specs/conf.py
55
delete mode 100644 docs/system/conf.py
56
delete mode 100644 docs/tools/conf.py
57
delete mode 100644 docs/user/conf.py
58
15
59
diff --git a/docs/conf.py b/docs/conf.py
16
diff --git a/docs/conf.py b/docs/conf.py
60
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
61
--- a/docs/conf.py
18
--- a/docs/conf.py
62
+++ b/docs/conf.py
19
+++ b/docs/conf.py
63
@@ -XXX,XX +XXX,XX @@ latex_documents = [
64
65
# -- Options for manual page output ---------------------------------------
66
# Individual manual/conf.py can override this to create man pages
67
-man_pages = []
68
+man_pages = [
69
+ ('interop/qemu-ga', 'qemu-ga',
70
+ 'QEMU Guest Agent',
71
+ ['Michael Roth <mdroth@linux.vnet.ibm.com>'], 8),
72
+ ('interop/qemu-ga-ref', 'qemu-ga-ref',
73
+ 'QEMU Guest Agent Protocol Reference',
74
+ [], 7),
75
+ ('interop/qemu-qmp-ref', 'qemu-qmp-ref',
76
+ 'QEMU QMP Reference Manual',
77
+ [], 7),
78
+ ('interop/qemu-storage-daemon-qmp-ref', 'qemu-storage-daemon-qmp-ref',
79
+ 'QEMU Storage Daemon QMP Reference Manual',
80
+ [], 7),
81
+ ('system/qemu-manpage', 'qemu',
82
+ 'QEMU User Documentation',
83
+ ['Fabrice Bellard'], 1),
84
+ ('system/qemu-block-drivers', 'qemu-block-drivers',
85
+ 'QEMU block drivers reference',
86
+ ['Fabrice Bellard and the QEMU Project developers'], 7),
87
+ ('system/qemu-cpu-models', 'qemu-cpu-models',
88
+ 'QEMU CPU Models',
89
+ ['The QEMU Project developers'], 7),
90
+ ('tools/qemu-img', 'qemu-img',
91
+ 'QEMU disk image utility',
92
+ ['Fabrice Bellard'], 1),
93
+ ('tools/qemu-nbd', 'qemu-nbd',
94
+ 'QEMU Disk Network Block Device Server',
95
+ ['Anthony Liguori <anthony@codemonkey.ws>'], 8),
96
+ ('tools/qemu-pr-helper', 'qemu-pr-helper',
97
+ 'QEMU persistent reservation helper',
98
+ [], 8),
99
+ ('tools/qemu-storage-daemon', 'qemu-storage-daemon',
100
+ 'QEMU storage daemon',
101
+ [], 1),
102
+ ('tools/qemu-trace-stap', 'qemu-trace-stap',
103
+ 'QEMU SystemTap trace tool',
104
+ [], 1),
105
+ ('tools/virtfs-proxy-helper', 'virtfs-proxy-helper',
106
+ 'QEMU 9p virtfs proxy filesystem helper',
107
+ ['M. Mohan Kumar'], 1),
108
+ ('tools/virtiofsd', 'virtiofsd',
109
+ 'QEMU virtio-fs shared file system daemon',
110
+ ['Stefan Hajnoczi <stefanha@redhat.com>',
111
+ 'Masayoshi Mizuma <m.mizuma@jp.fujitsu.com>'], 1),
112
+]
113
114
# -- Options for Texinfo output -------------------------------------------
115
116
diff --git a/docs/devel/conf.py b/docs/devel/conf.py
117
deleted file mode 100644
118
index XXXXXXX..XXXXXXX
119
--- a/docs/devel/conf.py
120
+++ /dev/null
121
@@ -XXX,XX +XXX,XX @@
20
@@ -XXX,XX +XXX,XX @@
122
-# -*- coding: utf-8 -*-
21
123
-#
22
# General information about the project.
124
-# QEMU documentation build configuration file for the 'devel' manual.
23
project = u'QEMU'
125
-#
24
-copyright = u'2022, The QEMU Project Developers'
126
-# This includes the top level conf file and then makes any necessary tweaks.
25
+copyright = u'2023, The QEMU Project Developers'
127
-import sys
26
author = u'The QEMU Project Developers'
128
-import os
27
129
-
28
# The version info for the project you're documenting, acts as replacement for
130
-qemu_docdir = os.path.abspath("..")
29
diff --git a/include/qemu/help-texts.h b/include/qemu/help-texts.h
131
-parent_config = os.path.join(qemu_docdir, "conf.py")
30
index XXXXXXX..XXXXXXX 100644
132
-exec(compile(open(parent_config, "rb").read(), parent_config, 'exec'))
31
--- a/include/qemu/help-texts.h
133
-
32
+++ b/include/qemu/help-texts.h
134
-# This slightly misuses the 'description', but is the best way to get
135
-# the manual title to appear in the sidebar.
136
-html_theme_options['description'] = u'Developer''s Guide'
137
diff --git a/docs/index.html.in b/docs/index.html.in
138
deleted file mode 100644
139
index XXXXXXX..XXXXXXX
140
--- a/docs/index.html.in
141
+++ /dev/null
142
@@ -XXX,XX +XXX,XX @@
33
@@ -XXX,XX +XXX,XX @@
143
-<!DOCTYPE html>
34
#define QEMU_HELP_TEXTS_H
144
-<html lang="en">
35
145
- <head>
36
/* Copyright string for -version arguments, About dialogs, etc */
146
- <meta charset="UTF-8">
37
-#define QEMU_COPYRIGHT "Copyright (c) 2003-2022 " \
147
- <title>QEMU @VERSION@ Documentation</title>
38
+#define QEMU_COPYRIGHT "Copyright (c) 2003-2023 " \
148
- </head>
39
"Fabrice Bellard and the QEMU Project developers"
149
- <body>
40
150
- <h1>QEMU @VERSION@ Documentation</h1>
41
/* Bug reporting information for --help arguments, About dialogs, etc */
151
- <ul>
152
- <li><a href="system/index.html">System Emulation User's Guide</a></li>
153
- <li><a href="user/index.html">User Mode Emulation User's Guide</a></li>
154
- <li><a href="tools/index.html">Tools Guide</a></li>
155
- <li><a href="interop/index.html">System Emulation Management and Interoperability Guide</a></li>
156
- <li><a href="specs/index.html">System Emulation Guest Hardware Specifications</a></li>
157
- </ul>
158
- </body>
159
-</html>
160
diff --git a/docs/interop/conf.py b/docs/interop/conf.py
161
deleted file mode 100644
162
index XXXXXXX..XXXXXXX
163
--- a/docs/interop/conf.py
164
+++ /dev/null
165
@@ -XXX,XX +XXX,XX @@
166
-# -*- coding: utf-8 -*-
167
-#
168
-# QEMU documentation build configuration file for the 'interop' manual.
169
-#
170
-# This includes the top level conf file and then makes any necessary tweaks.
171
-import sys
172
-import os
173
-
174
-qemu_docdir = os.path.abspath("..")
175
-parent_config = os.path.join(qemu_docdir, "conf.py")
176
-exec(compile(open(parent_config, "rb").read(), parent_config, 'exec'))
177
-
178
-# This slightly misuses the 'description', but is the best way to get
179
-# the manual title to appear in the sidebar.
180
-html_theme_options['description'] = u'System Emulation Management and Interoperability Guide'
181
-
182
-# One entry per manual page. List of tuples
183
-# (source start file, name, description, authors, manual section).
184
-man_pages = [
185
- ('qemu-ga', 'qemu-ga', u'QEMU Guest Agent',
186
- ['Michael Roth <mdroth@linux.vnet.ibm.com>'], 8),
187
- ('qemu-ga-ref', 'qemu-ga-ref', 'QEMU Guest Agent Protocol Reference',
188
- [], 7),
189
- ('qemu-qmp-ref', 'qemu-qmp-ref', 'QEMU QMP Reference Manual',
190
- [], 7),
191
- ('qemu-storage-daemon-qmp-ref', 'qemu-storage-daemon-qmp-ref',
192
- 'QEMU Storage Daemon QMP Reference Manual', [], 7),
193
-]
194
diff --git a/docs/meson.build b/docs/meson.build
195
index XXXXXXX..XXXXXXX 100644
196
--- a/docs/meson.build
197
+++ b/docs/meson.build
198
@@ -XXX,XX +XXX,XX @@ if build_docs
199
meson.source_root() / 'docs/sphinx/qmp_lexer.py',
200
qapi_gen_depends ]
201
202
- configure_file(output: 'index.html',
203
- input: files('index.html.in'),
204
- configuration: {'VERSION': meson.project_version()},
205
- install_dir: qemu_docdir)
206
- manuals = [ 'devel', 'interop', 'tools', 'specs', 'system', 'user' ]
207
man_pages = {
208
- 'interop' : {
209
'qemu-ga.8': (have_tools ? 'man8' : ''),
210
'qemu-ga-ref.7': 'man7',
211
'qemu-qmp-ref.7': 'man7',
212
'qemu-storage-daemon-qmp-ref.7': (have_tools ? 'man7' : ''),
213
- },
214
- 'tools': {
215
'qemu-img.1': (have_tools ? 'man1' : ''),
216
'qemu-nbd.8': (have_tools ? 'man8' : ''),
217
'qemu-pr-helper.8': (have_tools ? 'man8' : ''),
218
@@ -XXX,XX +XXX,XX @@ if build_docs
219
'qemu-trace-stap.1': (config_host.has_key('CONFIG_TRACE_SYSTEMTAP') ? 'man1' : ''),
220
'virtfs-proxy-helper.1': (have_virtfs_proxy_helper ? 'man1' : ''),
221
'virtiofsd.1': (have_virtiofsd ? 'man1' : ''),
222
- },
223
- 'system': {
224
'qemu.1': 'man1',
225
'qemu-block-drivers.7': 'man7',
226
'qemu-cpu-models.7': 'man7'
227
- },
228
}
229
230
sphinxdocs = []
231
sphinxmans = []
232
- foreach manual : manuals
233
- private_dir = meson.current_build_dir() / (manual + '.p')
234
- output_dir = meson.current_build_dir() / manual
235
- input_dir = meson.current_source_dir() / manual
236
237
- this_manual = custom_target(manual + ' manual',
238
+ private_dir = meson.current_build_dir() / 'manual.p'
239
+ output_dir = meson.current_build_dir() / 'manual'
240
+ input_dir = meson.current_source_dir()
241
+
242
+ this_manual = custom_target('QEMU manual',
243
build_by_default: build_docs,
244
- output: [manual + '.stamp'],
245
- input: [files('conf.py'), files(manual / 'conf.py')],
246
- depfile: manual + '.d',
247
+ output: 'docs.stamp',
248
+ input: files('conf.py'),
249
+ depfile: 'docs.d',
250
depend_files: sphinx_extn_depends,
251
command: [SPHINX_ARGS, '-Ddepfile=@DEPFILE@',
252
'-Ddepfile_stamp=@OUTPUT0@',
253
'-b', 'html', '-d', private_dir,
254
input_dir, output_dir])
255
- sphinxdocs += this_manual
256
- if build_docs and manual != 'devel'
257
- install_subdir(output_dir, install_dir: qemu_docdir)
258
- endif
259
+ sphinxdocs += this_manual
260
+ install_subdir(output_dir, install_dir: qemu_docdir, strip_directory: true)
261
262
- these_man_pages = []
263
- install_dirs = []
264
- foreach page, section : man_pages.get(manual, {})
265
- these_man_pages += page
266
- install_dirs += section == '' ? false : get_option('mandir') / section
267
- endforeach
268
- if these_man_pages.length() > 0
269
- sphinxmans += custom_target(manual + ' man pages',
270
- build_by_default: build_docs,
271
- output: these_man_pages,
272
- input: this_manual,
273
- install: build_docs,
274
- install_dir: install_dirs,
275
- command: [SPHINX_ARGS, '-b', 'man', '-d', private_dir,
276
- input_dir, meson.current_build_dir()])
277
- endif
278
+ these_man_pages = []
279
+ install_dirs = []
280
+ foreach page, section : man_pages
281
+ these_man_pages += page
282
+ install_dirs += section == '' ? false : get_option('mandir') / section
283
endforeach
284
+
285
+ sphinxmans += custom_target('QEMU man pages',
286
+ build_by_default: build_docs,
287
+ output: these_man_pages,
288
+ input: this_manual,
289
+ install: build_docs,
290
+ install_dir: install_dirs,
291
+ command: [SPHINX_ARGS, '-b', 'man', '-d', private_dir,
292
+ input_dir, meson.current_build_dir()])
293
+
294
alias_target('sphinxdocs', sphinxdocs)
295
alias_target('html', sphinxdocs)
296
alias_target('man', sphinxmans)
297
diff --git a/docs/specs/conf.py b/docs/specs/conf.py
298
deleted file mode 100644
299
index XXXXXXX..XXXXXXX
300
--- a/docs/specs/conf.py
301
+++ /dev/null
302
@@ -XXX,XX +XXX,XX @@
303
-# -*- coding: utf-8 -*-
304
-#
305
-# QEMU documentation build configuration file for the 'specs' manual.
306
-#
307
-# This includes the top level conf file and then makes any necessary tweaks.
308
-import sys
309
-import os
310
-
311
-qemu_docdir = os.path.abspath("..")
312
-parent_config = os.path.join(qemu_docdir, "conf.py")
313
-exec(compile(open(parent_config, "rb").read(), parent_config, 'exec'))
314
-
315
-# This slightly misuses the 'description', but is the best way to get
316
-# the manual title to appear in the sidebar.
317
-html_theme_options['description'] = \
318
- u'System Emulation Guest Hardware Specifications'
319
diff --git a/docs/system/conf.py b/docs/system/conf.py
320
deleted file mode 100644
321
index XXXXXXX..XXXXXXX
322
--- a/docs/system/conf.py
323
+++ /dev/null
324
@@ -XXX,XX +XXX,XX @@
325
-# -*- coding: utf-8 -*-
326
-#
327
-# QEMU documentation build configuration file for the 'system' manual.
328
-#
329
-# This includes the top level conf file and then makes any necessary tweaks.
330
-import sys
331
-import os
332
-
333
-qemu_docdir = os.path.abspath("..")
334
-parent_config = os.path.join(qemu_docdir, "conf.py")
335
-exec(compile(open(parent_config, "rb").read(), parent_config, 'exec'))
336
-
337
-# This slightly misuses the 'description', but is the best way to get
338
-# the manual title to appear in the sidebar.
339
-html_theme_options['description'] = u'System Emulation User''s Guide'
340
-
341
-# One entry per manual page. List of tuples
342
-# (source start file, name, description, authors, manual section).
343
-man_pages = [
344
- ('qemu-manpage', 'qemu', u'QEMU User Documentation',
345
- ['Fabrice Bellard'], 1),
346
- ('qemu-block-drivers', 'qemu-block-drivers',
347
- u'QEMU block drivers reference',
348
- ['Fabrice Bellard and the QEMU Project developers'], 7),
349
- ('qemu-cpu-models', 'qemu-cpu-models',
350
- u'QEMU CPU Models',
351
- ['The QEMU Project developers'], 7)
352
-]
353
diff --git a/docs/tools/conf.py b/docs/tools/conf.py
354
deleted file mode 100644
355
index XXXXXXX..XXXXXXX
356
--- a/docs/tools/conf.py
357
+++ /dev/null
358
@@ -XXX,XX +XXX,XX @@
359
-# -*- coding: utf-8 -*-
360
-#
361
-# QEMU documentation build configuration file for the 'tools' manual.
362
-#
363
-# This includes the top level conf file and then makes any necessary tweaks.
364
-import sys
365
-import os
366
-
367
-qemu_docdir = os.path.abspath("..")
368
-parent_config = os.path.join(qemu_docdir, "conf.py")
369
-exec(compile(open(parent_config, "rb").read(), parent_config, 'exec'))
370
-
371
-# This slightly misuses the 'description', but is the best way to get
372
-# the manual title to appear in the sidebar.
373
-html_theme_options['description'] = \
374
- u'Tools Guide'
375
-
376
-# One entry per manual page. List of tuples
377
-# (source start file, name, description, authors, manual section).
378
-man_pages = [
379
- ('qemu-img', 'qemu-img', u'QEMU disk image utility',
380
- ['Fabrice Bellard'], 1),
381
- ('qemu-storage-daemon', 'qemu-storage-daemon', u'QEMU storage daemon',
382
- [], 1),
383
- ('qemu-nbd', 'qemu-nbd', u'QEMU Disk Network Block Device Server',
384
- ['Anthony Liguori <anthony@codemonkey.ws>'], 8),
385
- ('qemu-pr-helper', 'qemu-pr-helper', 'QEMU persistent reservation helper',
386
- [], 8),
387
- ('qemu-trace-stap', 'qemu-trace-stap', u'QEMU SystemTap trace tool',
388
- [], 1),
389
- ('virtfs-proxy-helper', 'virtfs-proxy-helper',
390
- u'QEMU 9p virtfs proxy filesystem helper',
391
- ['M. Mohan Kumar'], 1),
392
- ('virtiofsd', 'virtiofsd', u'QEMU virtio-fs shared file system daemon',
393
- ['Stefan Hajnoczi <stefanha@redhat.com>',
394
- 'Masayoshi Mizuma <m.mizuma@jp.fujitsu.com>'], 1),
395
-]
396
diff --git a/docs/user/conf.py b/docs/user/conf.py
397
deleted file mode 100644
398
index XXXXXXX..XXXXXXX
399
--- a/docs/user/conf.py
400
+++ /dev/null
401
@@ -XXX,XX +XXX,XX @@
402
-# -*- coding: utf-8 -*-
403
-#
404
-# QEMU documentation build configuration file for the 'user' manual.
405
-#
406
-# This includes the top level conf file and then makes any necessary tweaks.
407
-import sys
408
-import os
409
-
410
-qemu_docdir = os.path.abspath("..")
411
-parent_config = os.path.join(qemu_docdir, "conf.py")
412
-exec(compile(open(parent_config, "rb").read(), parent_config, 'exec'))
413
-
414
-# This slightly misuses the 'description', but is the best way to get
415
-# the manual title to appear in the sidebar.
416
-html_theme_options['description'] = u'User Mode Emulation User''s Guide'
417
--
42
--
418
2.20.1
43
2.34.1
419
420
diff view generated by jsdifflib
[PULL 16/21] hw/timer: Refactor NPCM7XX Timer to use CLK clock
[PULL 20/21] hw/arm/sbsa-ref: add GIC node into DT
1
From: Hao Wu <wuhaotsh@google.com>
1
From: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
2
2
3
This patch makes NPCM7XX Timer to use a the timer clock generated by the
3
Let add GIC information into DeviceTree as part of SBSA-REF versioning.
4
CLK module instead of the magic number TIMER_REF_HZ.
5
4
6
Reviewed-by: Havard Skinnemoen <hskinnemoen@google.com>
5
Trusted Firmware will read it and provide to next firmware level.
7
Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
6
8
Signed-off-by: Hao Wu <wuhaotsh@google.com>
7
Bumps platform version to 0.1 one so we can check is node is present.
9
Message-id: 20210108190945.949196-3-wuhaotsh@google.com
8
9
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
12
---
13
include/hw/misc/npcm7xx_clk.h | 6 -----
13
hw/arm/sbsa-ref.c | 19 ++++++++++++++++++-
14
include/hw/timer/npcm7xx_timer.h | 1 +
14
1 file changed, 18 insertions(+), 1 deletion(-)
15
hw/arm/npcm7xx.c | 5 ++++
16
hw/timer/npcm7xx_timer.c | 39 +++++++++++++++-----------------
17
4 files changed, 24 insertions(+), 27 deletions(-)
18
15
19
diff --git a/include/hw/misc/npcm7xx_clk.h b/include/hw/misc/npcm7xx_clk.h
16
diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
20
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
21
--- a/include/hw/misc/npcm7xx_clk.h
18
--- a/hw/arm/sbsa-ref.c
22
+++ b/include/hw/misc/npcm7xx_clk.h
19
+++ b/hw/arm/sbsa-ref.c
23
@@ -XXX,XX +XXX,XX @@
20
@@ -XXX,XX +XXX,XX @@
24
#include "hw/clock.h"
21
#include "exec/hwaddr.h"
25
#include "hw/sysbus.h"
22
#include "kvm_arm.h"
26
23
#include "hw/arm/boot.h"
27
-/*
24
+#include "hw/arm/fdt.h"
28
- * The reference clock frequency for the timer modules, and the SECCNT and
25
#include "hw/arm/smmuv3.h"
29
- * CNTR25M registers in this module, is always 25 MHz.
26
#include "hw/block/flash.h"
30
- */
27
#include "hw/boards.h"
31
-#define NPCM7XX_TIMER_REF_HZ (25000000)
28
@@ -XXX,XX +XXX,XX @@ static uint64_t sbsa_ref_cpu_mp_affinity(SBSAMachineState *sms, int idx)
32
-
29
return arm_cpu_mp_affinity(idx, clustersz);
30
}
31
32
+static void sbsa_fdt_add_gic_node(SBSAMachineState *sms)
33
+{
34
+ char *nodename;
35
+
36
+ nodename = g_strdup_printf("/intc");
37
+ qemu_fdt_add_subnode(sms->fdt, nodename);
38
+ qemu_fdt_setprop_sized_cells(sms->fdt, nodename, "reg",
39
+ 2, sbsa_ref_memmap[SBSA_GIC_DIST].base,
40
+ 2, sbsa_ref_memmap[SBSA_GIC_DIST].size,
41
+ 2, sbsa_ref_memmap[SBSA_GIC_REDIST].base,
42
+ 2, sbsa_ref_memmap[SBSA_GIC_REDIST].size);
43
+
44
+ g_free(nodename);
45
+}
33
/*
46
/*
34
* Number of registers in our device state structure. Don't change this without
47
* Firmware on this machine only uses ACPI table to load OS, these limited
35
* incrementing the version_id in the vmstate.
48
* device tree nodes are just to let firmware know the info which varies from
36
diff --git a/include/hw/timer/npcm7xx_timer.h b/include/hw/timer/npcm7xx_timer.h
49
@@ -XXX,XX +XXX,XX @@ static void create_fdt(SBSAMachineState *sms)
37
index XXXXXXX..XXXXXXX 100644
50
* fw compatibility.
38
--- a/include/hw/timer/npcm7xx_timer.h
51
*/
39
+++ b/include/hw/timer/npcm7xx_timer.h
52
qemu_fdt_setprop_cell(fdt, "/", "machine-version-major", 0);
40
@@ -XXX,XX +XXX,XX @@ struct NPCM7xxTimerCtrlState {
53
- qemu_fdt_setprop_cell(fdt, "/", "machine-version-minor", 0);
41
54
+ qemu_fdt_setprop_cell(fdt, "/", "machine-version-minor", 1);
42
uint32_t tisr;
55
43
56
if (ms->numa_state->have_numa_distance) {
44
+ Clock *clock;
57
int size = nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t);
45
NPCM7xxTimer timer[NPCM7XX_TIMERS_PER_CTRL];
58
@@ -XXX,XX +XXX,XX @@ static void create_fdt(SBSAMachineState *sms)
46
NPCM7xxWatchdogTimer watchdog_timer;
59
47
};
60
g_free(nodename);
48
diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c
61
}
49
index XXXXXXX..XXXXXXX 100644
50
--- a/hw/arm/npcm7xx.c
51
+++ b/hw/arm/npcm7xx.c
52
@@ -XXX,XX +XXX,XX @@
53
#include "hw/char/serial.h"
54
#include "hw/loader.h"
55
#include "hw/misc/unimp.h"
56
+#include "hw/qdev-clock.h"
57
#include "hw/qdev-properties.h"
58
#include "qapi/error.h"
59
#include "qemu/units.h"
60
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_realize(DeviceState *dev, Error **errp)
61
int first_irq;
62
int j;
63
64
+ /* Connect the timer clock. */
65
+ qdev_connect_clock_in(DEVICE(&s->tim[i]), "clock", qdev_get_clock_out(
66
+ DEVICE(&s->clk), "timer-clock"));
67
+
62
+
68
sysbus_realize(sbd, &error_abort);
63
+ sbsa_fdt_add_gic_node(sms);
69
sysbus_mmio_map(sbd, 0, npcm7xx_tim_addr[i]);
70
71
diff --git a/hw/timer/npcm7xx_timer.c b/hw/timer/npcm7xx_timer.c
72
index XXXXXXX..XXXXXXX 100644
73
--- a/hw/timer/npcm7xx_timer.c
74
+++ b/hw/timer/npcm7xx_timer.c
75
@@ -XXX,XX +XXX,XX @@
76
#include "qemu/osdep.h"
77
78
#include "hw/irq.h"
79
+#include "hw/qdev-clock.h"
80
#include "hw/qdev-properties.h"
81
-#include "hw/misc/npcm7xx_clk.h"
82
#include "hw/timer/npcm7xx_timer.h"
83
#include "migration/vmstate.h"
84
#include "qemu/bitops.h"
85
@@ -XXX,XX +XXX,XX @@ static uint32_t npcm7xx_tcsr_prescaler(uint32_t tcsr)
86
/* Convert a timer cycle count to a time interval in nanoseconds. */
87
static int64_t npcm7xx_timer_count_to_ns(NPCM7xxTimer *t, uint32_t count)
88
{
89
- int64_t ns = count;
90
+ int64_t ticks = count;
91
92
- ns *= NANOSECONDS_PER_SECOND / NPCM7XX_TIMER_REF_HZ;
93
- ns *= npcm7xx_tcsr_prescaler(t->tcsr);
94
+ ticks *= npcm7xx_tcsr_prescaler(t->tcsr);
95
96
- return ns;
97
+ return clock_ticks_to_ns(t->ctrl->clock, ticks);
98
}
64
}
99
65
100
/* Convert a time interval in nanoseconds to a timer cycle count. */
66
#define SBSA_FLASH_SECTOR_SIZE (256 * KiB)
101
static uint32_t npcm7xx_timer_ns_to_count(NPCM7xxTimer *t, int64_t ns)
102
{
103
- int64_t count;
104
-
105
- count = ns / (NANOSECONDS_PER_SECOND / NPCM7XX_TIMER_REF_HZ);
106
- count /= npcm7xx_tcsr_prescaler(t->tcsr);
107
-
108
- return count;
109
+ return ns / clock_ticks_to_ns(t->ctrl->clock,
110
+ npcm7xx_tcsr_prescaler(t->tcsr));
111
}
112
113
static uint32_t npcm7xx_watchdog_timer_prescaler(const NPCM7xxWatchdogTimer *t)
114
@@ -XXX,XX +XXX,XX @@ static uint32_t npcm7xx_watchdog_timer_prescaler(const NPCM7xxWatchdogTimer *t)
115
static void npcm7xx_watchdog_timer_reset_cycles(NPCM7xxWatchdogTimer *t,
116
int64_t cycles)
117
{
118
- uint32_t prescaler = npcm7xx_watchdog_timer_prescaler(t);
119
- int64_t ns = (NANOSECONDS_PER_SECOND / NPCM7XX_TIMER_REF_HZ) * cycles;
120
+ int64_t ticks = cycles * npcm7xx_watchdog_timer_prescaler(t);
121
+ int64_t ns = clock_ticks_to_ns(t->ctrl->clock, ticks);
122
123
/*
124
* The reset function always clears the current timer. The caller of the
125
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_watchdog_timer_reset_cycles(NPCM7xxWatchdogTimer *t,
126
*/
127
npcm7xx_timer_clear(&t->base_timer);
128
129
- ns *= prescaler;
130
t->base_timer.remaining_ns = ns;
131
}
132
133
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_timer_hold_reset(Object *obj)
134
qemu_irq_lower(s->watchdog_timer.irq);
135
}
136
137
-static void npcm7xx_timer_realize(DeviceState *dev, Error **errp)
138
+static void npcm7xx_timer_init(Object *obj)
139
{
140
- NPCM7xxTimerCtrlState *s = NPCM7XX_TIMER(dev);
141
- SysBusDevice *sbd = &s->parent;
142
+ NPCM7xxTimerCtrlState *s = NPCM7XX_TIMER(obj);
143
+ DeviceState *dev = DEVICE(obj);
144
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
145
int i;
146
NPCM7xxWatchdogTimer *w;
147
148
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_timer_realize(DeviceState *dev, Error **errp)
149
npcm7xx_watchdog_timer_expired, w);
150
sysbus_init_irq(sbd, &w->irq);
151
152
- memory_region_init_io(&s->iomem, OBJECT(s), &npcm7xx_timer_ops, s,
153
+ memory_region_init_io(&s->iomem, obj, &npcm7xx_timer_ops, s,
154
TYPE_NPCM7XX_TIMER, 4 * KiB);
155
sysbus_init_mmio(sbd, &s->iomem);
156
qdev_init_gpio_out_named(dev, &w->reset_signal,
157
NPCM7XX_WATCHDOG_RESET_GPIO_OUT, 1);
158
+ s->clock = qdev_init_clock_in(dev, "clock", NULL, NULL);
159
}
160
161
static const VMStateDescription vmstate_npcm7xx_base_timer = {
162
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_npcm7xx_watchdog_timer = {
163
164
static const VMStateDescription vmstate_npcm7xx_timer_ctrl = {
165
.name = "npcm7xx-timer-ctrl",
166
- .version_id = 1,
167
- .minimum_version_id = 1,
168
+ .version_id = 2,
169
+ .minimum_version_id = 2,
170
.fields = (VMStateField[]) {
171
VMSTATE_UINT32(tisr, NPCM7xxTimerCtrlState),
172
+ VMSTATE_CLOCK(clock, NPCM7xxTimerCtrlState),
173
VMSTATE_STRUCT_ARRAY(timer, NPCM7xxTimerCtrlState,
174
NPCM7XX_TIMERS_PER_CTRL, 0, vmstate_npcm7xx_timer,
175
NPCM7xxTimer),
176
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_timer_class_init(ObjectClass *klass, void *data)
177
QEMU_BUILD_BUG_ON(NPCM7XX_TIMER_REGS_END > NPCM7XX_TIMER_NR_REGS);
178
179
dc->desc = "NPCM7xx Timer Controller";
180
- dc->realize = npcm7xx_timer_realize;
181
dc->vmsd = &vmstate_npcm7xx_timer_ctrl;
182
rc->phases.enter = npcm7xx_timer_enter_reset;
183
rc->phases.hold = npcm7xx_timer_hold_reset;
184
@@ -XXX,XX +XXX,XX @@ static const TypeInfo npcm7xx_timer_info = {
185
.parent = TYPE_SYS_BUS_DEVICE,
186
.instance_size = sizeof(NPCM7xxTimerCtrlState),
187
.class_init = npcm7xx_timer_class_init,
188
+ .instance_init = npcm7xx_timer_init,
189
};
190
191
static void npcm7xx_timer_register_type(void)
192
--
67
--
193
2.20.1
68
2.34.1
194
195
diff view generated by jsdifflib
[PULL 09/21] ui/cocoa: Update path to docs in build tree
[PULL 21/21] docs: sbsa: correct graphics card name
1
From: Roman Bolshakov <r.bolshakov@yadro.com>
1
From: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
2
2
3
QEMU documentation can't be opened if QEMU is run from build tree
3
We moved from VGA to Bochs to have PCIe card.
4
because executables are placed in the top of build tree after conversion
5
to meson.
6
4
7
Signed-off-by: Roman Bolshakov <r.bolshakov@yadro.com>
5
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
8
Reported-by: Peter Maydell <peter.maydell@linaro.org>
9
Message-id: 20210108213815.64678-1-r.bolshakov@yadro.com
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
8
---
13
ui/cocoa.m | 2 +-
9
docs/system/arm/sbsa.rst | 2 +-
14
1 file changed, 1 insertion(+), 1 deletion(-)
10
1 file changed, 1 insertion(+), 1 deletion(-)
15
11
16
diff --git a/ui/cocoa.m b/ui/cocoa.m
12
diff --git a/docs/system/arm/sbsa.rst b/docs/system/arm/sbsa.rst
17
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
18
--- a/ui/cocoa.m
14
--- a/docs/system/arm/sbsa.rst
19
+++ b/ui/cocoa.m
15
+++ b/docs/system/arm/sbsa.rst
20
@@ -XXX,XX +XXX,XX @@ QemuCocoaView *cocoaView;
16
@@ -XXX,XX +XXX,XX @@ The sbsa-ref board supports:
21
- (void) openDocumentation: (NSString *) filename
17
- System bus EHCI controller
22
{
18
- CDROM and hard disc on AHCI bus
23
/* Where to look for local files */
19
- E1000E ethernet card on PCIe bus
24
- NSString *path_array[] = {@"../share/doc/qemu/", @"../doc/qemu/", @"../docs/"};
20
- - VGA display adaptor on PCIe bus
25
+ NSString *path_array[] = {@"../share/doc/qemu/", @"../doc/qemu/", @"docs/"};
21
+ - Bochs display adapter on PCIe bus
26
NSString *full_file_path;
22
- A generic SBSA watchdog device
27
23
28
/* iterate thru the possible paths until the file is found */
29
--
24
--
30
2.20.1
25
2.34.1
31
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diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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