Arm queue; not huge but I figured I might as well send it out since

I've been doing code review today and there's no queue of unprocessed

pullreqs...

thanks

-- PMM

The following changes since commit b3f846c59d8405bb87c551187721fc92ff2f1b92:

Merge remote-tracking branch 'remotes/huth-gitlab/tags/pull-request-2021-01-11v2' into staging (2021-01-11 15:15:35 +0000)

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210112

for you to fetch changes up to 19d131395ccaf503db21dadd8257e6dc9fc1d7de:

ui/cocoa: Fix openFile: deprecation on Big Sur (2021-01-12 11:38:37 +0000)

* arm: Support emulation of ARMv8.4-TTST extension

* arm: Update cpu.h ID register field definitions

* arm: Fix breakage of XScale instruction emulation

* hw/net/lan9118: Fix RX Status FIFO PEEK value

* npcm7xx: Add ADC and PWM emulation

* ui/cocoa: Make "open docs" help menu entry work again when binary

is run from the build tree

* ui/cocoa: Fix openFile: deprecation on Big Sur

* docs: Add qemu-storage-daemon(1) manpage to meson.build

* docs: Build and install all the docs in a single manual

Hao Wu (6):

hw/misc: Add clock converter in NPCM7XX CLK module

hw/timer: Refactor NPCM7XX Timer to use CLK clock

hw/adc: Add an ADC module for NPCM7XX

hw/misc: Add a PWM module for NPCM7XX

hw/misc: Add QTest for NPCM7XX PWM Module

hw/*: Use type casting for SysBusDevice in NPCM7XX

Leif Lindholm (6):

target/arm: fix typo in cpu.h ID_AA64PFR1 field name

target/arm: make ARMCPU.clidr 64-bit

target/arm: make ARMCPU.ctr 64-bit

target/arm: add descriptions of CLIDR_EL1, CCSIDR_EL1, CTR_EL0 to cpu.h

target/arm: add aarch64 ID register fields to cpu.h

target/arm: add aarch32 ID register fields to cpu.h

Peter Maydell (5):

docs: Add qemu-storage-daemon(1) manpage to meson.build

docs: Build and install all the docs in a single manual

target/arm: Don't decode insns in the XScale/iWMMXt space as cp insns

hw/net/lan9118: Fix RX Status FIFO PEEK value

hw/net/lan9118: Add symbolic constants for register offsets

Roman Bolshakov (2):

ui/cocoa: Update path to docs in build tree

ui/cocoa: Fix openFile: deprecation on Big Sur

Rémi Denis-Courmont (2):

target/arm: ARMv8.4-TTST extension

target/arm: enable Small Translation tables in max CPU

From: Hao Wu <wuhaotsh@google.com>

This patch makes NPCM7XX Timer to use a the timer clock generated by the

CLK module instead of the magic number TIMER_REF_HZ.

Reviewed-by: Havard Skinnemoen <hskinnemoen@google.com>

Reviewed-by: Tyrone Ting <kfting@nuvoton.com>

Signed-off-by: Hao Wu <wuhaotsh@google.com>

Message-id: 20210108190945.949196-3-wuhaotsh@google.com

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

include/hw/misc/npcm7xx_clk.h | 6 -----

include/hw/timer/npcm7xx_timer.h | 1 +

hw/arm/npcm7xx.c | 5 ++++

hw/timer/npcm7xx_timer.c | 39 +++++++++++++++-----------------

4 files changed, 24 insertions(+), 27 deletions(-)

diff --git a/include/hw/misc/npcm7xx_clk.h b/include/hw/misc/npcm7xx_clk.h

--- a/include/hw/misc/npcm7xx_clk.h

+++ b/include/hw/misc/npcm7xx_clk.h

#include "hw/clock.h"

#include "hw/sysbus.h"

-/*

- * The reference clock frequency for the timer modules, and the SECCNT and

- * CNTR25M registers in this module, is always 25 MHz.

- */

-#define NPCM7XX_TIMER_REF_HZ (25000000)

-

/*

* Number of registers in our device state structure. Don't change this without

* incrementing the version_id in the vmstate.

diff --git a/include/hw/timer/npcm7xx_timer.h b/include/hw/timer/npcm7xx_timer.h

--- a/include/hw/timer/npcm7xx_timer.h

+++ b/include/hw/timer/npcm7xx_timer.h

@@ -XXX,XX +XXX,XX @@ struct NPCM7xxTimerCtrlState {

uint32_t tisr;

+ Clock *clock;

NPCM7xxTimer timer[NPCM7XX_TIMERS_PER_CTRL];

NPCM7xxWatchdogTimer watchdog_timer;

};

diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/arm/npcm7xx.c

+++ b/hw/arm/npcm7xx.c

@@ -XXX,XX +XXX,XX @@

#include "hw/char/serial.h"

#include "hw/loader.h"

#include "hw/misc/unimp.h"

+#include "hw/qdev-clock.h"

#include "hw/qdev-properties.h"

#include "qapi/error.h"

#include "qemu/units.h"

@@ -XXX,XX +XXX,XX @@ static void npcm7xx_realize(DeviceState *dev, Error **errp)

int first_irq;

int j;

+ /* Connect the timer clock. */

+ qdev_connect_clock_in(DEVICE(&s->tim[i]), "clock", qdev_get_clock_out(

+ DEVICE(&s->clk), "timer-clock"));

+

sysbus_realize(sbd, &error_abort);

sysbus_mmio_map(sbd, 0, npcm7xx_tim_addr[i]);

diff --git a/hw/timer/npcm7xx_timer.c b/hw/timer/npcm7xx_timer.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/timer/npcm7xx_timer.c

+++ b/hw/timer/npcm7xx_timer.c

#include "hw/irq.h"

+#include "hw/qdev-clock.h"

#include "hw/qdev-properties.h"

-#include "hw/misc/npcm7xx_clk.h"

#include "hw/timer/npcm7xx_timer.h"

#include "migration/vmstate.h"

#include "qemu/bitops.h"

@@ -XXX,XX +XXX,XX @@ static uint32_t npcm7xx_tcsr_prescaler(uint32_t tcsr)

/* Convert a timer cycle count to a time interval in nanoseconds. */

static int64_t npcm7xx_timer_count_to_ns(NPCM7xxTimer *t, uint32_t count)

{

- int64_t ns = count;

+ int64_t ticks = count;

- ns *= NANOSECONDS_PER_SECOND / NPCM7XX_TIMER_REF_HZ;

- ns *= npcm7xx_tcsr_prescaler(t->tcsr);

+ ticks *= npcm7xx_tcsr_prescaler(t->tcsr);

- return ns;

+ return clock_ticks_to_ns(t->ctrl->clock, ticks);

}

/* Convert a time interval in nanoseconds to a timer cycle count. */

static uint32_t npcm7xx_timer_ns_to_count(NPCM7xxTimer *t, int64_t ns)

{

- int64_t count;

-

- count = ns / (NANOSECONDS_PER_SECOND / NPCM7XX_TIMER_REF_HZ);

- count /= npcm7xx_tcsr_prescaler(t->tcsr);

-

- return count;

+ return ns / clock_ticks_to_ns(t->ctrl->clock,

+ npcm7xx_tcsr_prescaler(t->tcsr));

}

static uint32_t npcm7xx_watchdog_timer_prescaler(const NPCM7xxWatchdogTimer *t)

@@ -XXX,XX +XXX,XX @@ static uint32_t npcm7xx_watchdog_timer_prescaler(const NPCM7xxWatchdogTimer *t)

static void npcm7xx_watchdog_timer_reset_cycles(NPCM7xxWatchdogTimer *t,

int64_t cycles)

{

- uint32_t prescaler = npcm7xx_watchdog_timer_prescaler(t);

- int64_t ns = (NANOSECONDS_PER_SECOND / NPCM7XX_TIMER_REF_HZ) * cycles;

+ int64_t ticks = cycles * npcm7xx_watchdog_timer_prescaler(t);

+ int64_t ns = clock_ticks_to_ns(t->ctrl->clock, ticks);

/*

* The reset function always clears the current timer. The caller of the

@@ -XXX,XX +XXX,XX @@ static void npcm7xx_watchdog_timer_reset_cycles(NPCM7xxWatchdogTimer *t,

*/

npcm7xx_timer_clear(&t->base_timer);

- ns *= prescaler;

t->base_timer.remaining_ns = ns;

}

@@ -XXX,XX +XXX,XX @@ static void npcm7xx_timer_hold_reset(Object *obj)

qemu_irq_lower(s->watchdog_timer.irq);

}

-static void npcm7xx_timer_realize(DeviceState *dev, Error **errp)

+static void npcm7xx_timer_init(Object *obj)

{

- NPCM7xxTimerCtrlState *s = NPCM7XX_TIMER(dev);

- SysBusDevice *sbd = &s->parent;

+ NPCM7xxTimerCtrlState *s = NPCM7XX_TIMER(obj);

+ DeviceState *dev = DEVICE(obj);

+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);

int i;

NPCM7xxWatchdogTimer *w;

@@ -XXX,XX +XXX,XX @@ static void npcm7xx_timer_realize(DeviceState *dev, Error **errp)

npcm7xx_watchdog_timer_expired, w);

sysbus_init_irq(sbd, &w->irq);

- memory_region_init_io(&s->iomem, OBJECT(s), &npcm7xx_timer_ops, s,

+ memory_region_init_io(&s->iomem, obj, &npcm7xx_timer_ops, s,

TYPE_NPCM7XX_TIMER, 4 * KiB);

sysbus_init_mmio(sbd, &s->iomem);

qdev_init_gpio_out_named(dev, &w->reset_signal,

NPCM7XX_WATCHDOG_RESET_GPIO_OUT, 1);

+ s->clock = qdev_init_clock_in(dev, "clock", NULL, NULL);

}

static const VMStateDescription vmstate_npcm7xx_base_timer = {

@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_npcm7xx_watchdog_timer = {

static const VMStateDescription vmstate_npcm7xx_timer_ctrl = {

.name = "npcm7xx-timer-ctrl",

- .version_id = 1,

- .minimum_version_id = 1,

+ .version_id = 2,

+ .minimum_version_id = 2,

.fields = (VMStateField[]) {

VMSTATE_UINT32(tisr, NPCM7xxTimerCtrlState),

+ VMSTATE_CLOCK(clock, NPCM7xxTimerCtrlState),

VMSTATE_STRUCT_ARRAY(timer, NPCM7xxTimerCtrlState,

NPCM7XX_TIMERS_PER_CTRL, 0, vmstate_npcm7xx_timer,

NPCM7xxTimer),

@@ -XXX,XX +XXX,XX @@ static void npcm7xx_timer_class_init(ObjectClass *klass, void *data)

QEMU_BUILD_BUG_ON(NPCM7XX_TIMER_REGS_END > NPCM7XX_TIMER_NR_REGS);

dc->desc = "NPCM7xx Timer Controller";

- dc->realize = npcm7xx_timer_realize;

dc->vmsd = &vmstate_npcm7xx_timer_ctrl;

rc->phases.enter = npcm7xx_timer_enter_reset;

rc->phases.hold = npcm7xx_timer_hold_reset;

@@ -XXX,XX +XXX,XX @@ static const TypeInfo npcm7xx_timer_info = {

.parent = TYPE_SYS_BUS_DEVICE,

.instance_size = sizeof(NPCM7xxTimerCtrlState),

.class_init = npcm7xx_timer_class_init,

+ .instance_init = npcm7xx_timer_init,

};

static void npcm7xx_timer_register_type(void)

2.20.1

From: Hao Wu <wuhaotsh@google.com>

This patch allows NPCM7XX CLK module to compute clocks that are used by

other NPCM7XX modules.

Add a new struct NPCM7xxClockConverterState which represents a

single converter. Each clock converter in CLK module represents one

converter in NPCM7XX CLK Module(PLL, SEL or Divider). Each converter

takes one or more input clocks and converts them into one output clock.

They form a clock hierarchy in the CLK module and are responsible for

outputing clocks for various other modules in an NPCM7XX SoC.

Each converter has a function pointer called "convert" which represents

the unique logic for that converter.

The clock contains two initialization information: ConverterInitInfo and

ConverterConnectionInfo. They represent the vertices and edges in the

clock diagram respectively.

Reviewed-by: Havard Skinnemoen <hskinnemoen@google.com>

Reviewed-by: Tyrone Ting <kfting@nuvoton.com>

Signed-off-by: Hao Wu <wuhaotsh@google.com>

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

Message-id: 20210108190945.949196-2-wuhaotsh@google.com

include/hw/misc/npcm7xx_clk.h | 140 +++++-

hw/misc/npcm7xx_clk.c | 805 +++++++++++++++++++++++++++++++++-

2 files changed, 932 insertions(+), 13 deletions(-)

diff --git a/include/hw/misc/npcm7xx_clk.h b/include/hw/misc/npcm7xx_clk.h

--- a/include/hw/misc/npcm7xx_clk.h

+++ b/include/hw/misc/npcm7xx_clk.h

#define NPCM7XX_CLK_H

#include "exec/memory.h"

+#include "hw/clock.h"

#include "hw/sysbus.h"

/*

@@ -XXX,XX +XXX,XX @@

#define NPCM7XX_WATCHDOG_RESET_GPIO_IN "npcm7xx-clk-watchdog-reset-gpio-in"

-typedef struct NPCM7xxCLKState {

+/* Maximum amount of clock inputs in a SEL module. */

+#define NPCM7XX_CLK_SEL_MAX_INPUT 5

+

+/* PLLs in CLK module. */

+typedef enum NPCM7xxClockPLL {

+ NPCM7XX_CLOCK_PLL0,

+ NPCM7XX_CLOCK_PLL1,

+ NPCM7XX_CLOCK_PLL2,

+ NPCM7XX_CLOCK_PLLG,

+ NPCM7XX_CLOCK_NR_PLLS,

+} NPCM7xxClockPLL;

+

+/* SEL/MUX in CLK module. */

+typedef enum NPCM7xxClockSEL {

+ NPCM7XX_CLOCK_PIXCKSEL,

+ NPCM7XX_CLOCK_MCCKSEL,

+ NPCM7XX_CLOCK_CPUCKSEL,

+ NPCM7XX_CLOCK_CLKOUTSEL,

+ NPCM7XX_CLOCK_UARTCKSEL,

+ NPCM7XX_CLOCK_TIMCKSEL,

+ NPCM7XX_CLOCK_SDCKSEL,

+ NPCM7XX_CLOCK_GFXMSEL,

+ NPCM7XX_CLOCK_SUCKSEL,

+ NPCM7XX_CLOCK_NR_SELS,

+} NPCM7xxClockSEL;

+

+/* Dividers in CLK module. */

+typedef enum NPCM7xxClockDivider {

+ NPCM7XX_CLOCK_PLL1D2, /* PLL1/2 */

+ NPCM7XX_CLOCK_PLL2D2, /* PLL2/2 */

+ NPCM7XX_CLOCK_MC_DIVIDER,

+ NPCM7XX_CLOCK_AXI_DIVIDER,

+ NPCM7XX_CLOCK_AHB_DIVIDER,

+ NPCM7XX_CLOCK_AHB3_DIVIDER,

+ NPCM7XX_CLOCK_SPI0_DIVIDER,

+ NPCM7XX_CLOCK_SPIX_DIVIDER,

+ NPCM7XX_CLOCK_APB1_DIVIDER,

+ NPCM7XX_CLOCK_APB2_DIVIDER,

+ NPCM7XX_CLOCK_APB3_DIVIDER,

+ NPCM7XX_CLOCK_APB4_DIVIDER,

+ NPCM7XX_CLOCK_APB5_DIVIDER,

+ NPCM7XX_CLOCK_CLKOUT_DIVIDER,

+ NPCM7XX_CLOCK_UART_DIVIDER,

+ NPCM7XX_CLOCK_TIMER_DIVIDER,

+ NPCM7XX_CLOCK_ADC_DIVIDER,

+ NPCM7XX_CLOCK_MMC_DIVIDER,

+ NPCM7XX_CLOCK_SDHC_DIVIDER,

+ NPCM7XX_CLOCK_GFXM_DIVIDER, /* divide by 3 */

+ NPCM7XX_CLOCK_UTMI_DIVIDER,

+ NPCM7XX_CLOCK_NR_DIVIDERS,

+} NPCM7xxClockConverter;

+

+typedef struct NPCM7xxCLKState NPCM7xxCLKState;

+

+/**

+ * struct NPCM7xxClockPLLState - A PLL module in CLK module.

+ * @name: The name of the module.

+ * @clk: The CLK module that owns this module.

+ * @clock_in: The input clock of this module.

+ * @clock_out: The output clock of this module.

+ * @reg: The control registers for this PLL module.

+ */

+typedef struct NPCM7xxClockPLLState {

+ DeviceState parent;

+

+ const char *name;

+ NPCM7xxCLKState *clk;

+ Clock *clock_in;

+ Clock *clock_out;

+

+ int reg;

+} NPCM7xxClockPLLState;

+

+/**

+ * struct NPCM7xxClockSELState - A SEL module in CLK module.

+ * @name: The name of the module.

+ * @clk: The CLK module that owns this module.

+ * @input_size: The size of inputs of this module.

+ * @clock_in: The input clocks of this module.

+ * @clock_out: The output clocks of this module.

+ * @offset: The offset of this module in the control register.

+ * @len: The length of this module in the control register.

+ */

+typedef struct NPCM7xxClockSELState {

+ DeviceState parent;

+

+ const char *name;

+ NPCM7xxCLKState *clk;

+ uint8_t input_size;

+ Clock *clock_in[NPCM7XX_CLK_SEL_MAX_INPUT];

+ Clock *clock_out;

+

+ int offset;

+ int len;

+} NPCM7xxClockSELState;

+

+/**

+ * struct NPCM7xxClockDividerState - A Divider module in CLK module.

+ * @name: The name of the module.

+ * @clk: The CLK module that owns this module.

+ * @clock_in: The input clock of this module.

+ * @clock_out: The output clock of this module.

+ * @divide: The function the divider uses to divide the input.

+ * @reg: The index of the control register that contains the divisor.

+ * @offset: The offset of the divisor in the control register.

+ * @len: The length of the divisor in the control register.

+ * @divisor: The divisor for a constant divisor

+ */

+typedef struct NPCM7xxClockDividerState {

+ DeviceState parent;

+

+ const char *name;

+ NPCM7xxCLKState *clk;

+ Clock *clock_in;

+ Clock *clock_out;

+

+ uint32_t (*divide)(struct NPCM7xxClockDividerState *s);

+ union {

+ struct {

+ int reg;

+ int offset;

+ int len;

+ };

+ int divisor;

+ };

+} NPCM7xxClockDividerState;

+

+struct NPCM7xxCLKState {

SysBusDevice parent;

MemoryRegion iomem;

+ /* Clock converters */

+ NPCM7xxClockPLLState plls[NPCM7XX_CLOCK_NR_PLLS];

+ NPCM7xxClockSELState sels[NPCM7XX_CLOCK_NR_SELS];

+ NPCM7xxClockDividerState dividers[NPCM7XX_CLOCK_NR_DIVIDERS];

+

uint32_t regs[NPCM7XX_CLK_NR_REGS];

/* Time reference for SECCNT and CNTR25M, initialized by power on reset */

int64_t ref_ns;

-} NPCM7xxCLKState;

+

+ /* The incoming reference clock. */

+ Clock *clkref;

+};

#define TYPE_NPCM7XX_CLK "npcm7xx-clk"

#define NPCM7XX_CLK(obj) OBJECT_CHECK(NPCM7xxCLKState, (obj), TYPE_NPCM7XX_CLK)

diff --git a/hw/misc/npcm7xx_clk.c b/hw/misc/npcm7xx_clk.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/misc/npcm7xx_clk.c

+++ b/hw/misc/npcm7xx_clk.c

@@ -XXX,XX +XXX,XX @@

#include "hw/misc/npcm7xx_clk.h"

#include "hw/timer/npcm7xx_timer.h"

+#include "hw/qdev-clock.h"

#include "migration/vmstate.h"

#include "qemu/error-report.h"

#include "qemu/log.h"

@@ -XXX,XX +XXX,XX @@

#include "trace.h"

#include "sysemu/watchdog.h"

+/*

+ * The reference clock hz, and the SECCNT and CNTR25M registers in this module,

+ * is always 25 MHz.

+ */

+#define NPCM7XX_CLOCK_REF_HZ (25000000)

+

+/* Register Field Definitions */

+#define NPCM7XX_CLK_WDRCR_CA9C BIT(0) /* Cortex A9 Cores */

+

#define PLLCON_LOKI BIT(31)

#define PLLCON_LOKS BIT(30)

#define PLLCON_PWDEN BIT(12)

+#define PLLCON_FBDV(con) extract32((con), 16, 12)

+#define PLLCON_OTDV2(con) extract32((con), 13, 3)

+#define PLLCON_OTDV1(con) extract32((con), 8, 3)

+#define PLLCON_INDV(con) extract32((con), 0, 6)

enum NPCM7xxCLKRegisters {

NPCM7XX_CLK_CLKEN1,

@@ -XXX,XX +XXX,XX @@ static const uint32_t cold_reset_values[NPCM7XX_CLK_NR_REGS] = {

[NPCM7XX_CLK_AHBCKFI] = 0x000000c8,

};

-/* Register Field Definitions */

-#define NPCM7XX_CLK_WDRCR_CA9C BIT(0) /* Cortex A9 Cores */

-

/* The number of watchdogs that can trigger a reset. */

#define NPCM7XX_NR_WATCHDOGS (3)

+/* Clock converter functions */

+

+#define TYPE_NPCM7XX_CLOCK_PLL "npcm7xx-clock-pll"

+#define NPCM7XX_CLOCK_PLL(obj) OBJECT_CHECK(NPCM7xxClockPLLState, \

+ (obj), TYPE_NPCM7XX_CLOCK_PLL)

+#define TYPE_NPCM7XX_CLOCK_SEL "npcm7xx-clock-sel"

+#define NPCM7XX_CLOCK_SEL(obj) OBJECT_CHECK(NPCM7xxClockSELState, \

+ (obj), TYPE_NPCM7XX_CLOCK_SEL)

+#define TYPE_NPCM7XX_CLOCK_DIVIDER "npcm7xx-clock-divider"

+#define NPCM7XX_CLOCK_DIVIDER(obj) OBJECT_CHECK(NPCM7xxClockDividerState, \

+ (obj), TYPE_NPCM7XX_CLOCK_DIVIDER)

+

+static void npcm7xx_clk_update_pll(void *opaque)

+ NPCM7xxClockPLLState *s = opaque;

+ uint32_t con = s->clk->regs[s->reg];

+ uint64_t freq;

+

+ /* The PLL is grounded if it is not locked yet. */

+ if (con & PLLCON_LOKI) {

+ freq = clock_get_hz(s->clock_in);

+ freq *= PLLCON_FBDV(con);

+ freq /= PLLCON_INDV(con) * PLLCON_OTDV1(con) * PLLCON_OTDV2(con);

+ freq = 0;

+ }

+

+ clock_update_hz(s->clock_out, freq);

+static void npcm7xx_clk_update_sel(void *opaque)

+{

+ NPCM7xxClockSELState *s = opaque;

+ uint32_t index = extract32(s->clk->regs[NPCM7XX_CLK_CLKSEL], s->offset,

+ s->len);

+

+ if (index >= s->input_size) {

+ qemu_log_mask(LOG_GUEST_ERROR,

+ "%s: SEL index: %u out of range\n",

+ __func__, index);

+ index = 0;

+ }

+ clock_update_hz(s->clock_out, clock_get_hz(s->clock_in[index]));

+}

+

+static void npcm7xx_clk_update_divider(void *opaque)

+{

+ NPCM7xxClockDividerState *s = opaque;

+ uint32_t freq;

+

+ freq = s->divide(s);

+ clock_update_hz(s->clock_out, freq);

+}

+

+static uint32_t divide_by_constant(NPCM7xxClockDividerState *s)

+{

+ return clock_get_hz(s->clock_in) / s->divisor;

+}

+

+static uint32_t divide_by_reg_divisor(NPCM7xxClockDividerState *s)

+{

+ return clock_get_hz(s->clock_in) /

+ (extract32(s->clk->regs[s->reg], s->offset, s->len) + 1);

+}

+

+static uint32_t divide_by_reg_divisor_times_2(NPCM7xxClockDividerState *s)

+{

+ return divide_by_reg_divisor(s) / 2;

+}

+

+static uint32_t shift_by_reg_divisor(NPCM7xxClockDividerState *s)

+{

+ return clock_get_hz(s->clock_in) >>

+ extract32(s->clk->regs[s->reg], s->offset, s->len);

+}

+

+static NPCM7xxClockPLL find_pll_by_reg(enum NPCM7xxCLKRegisters reg)

+{

+ switch (reg) {

+ case NPCM7XX_CLK_PLLCON0:

+ return NPCM7XX_CLOCK_PLL0;

+ case NPCM7XX_CLK_PLLCON1:

+ return NPCM7XX_CLOCK_PLL1;

+ case NPCM7XX_CLK_PLLCON2:

+ return NPCM7XX_CLOCK_PLL2;

+ case NPCM7XX_CLK_PLLCONG:

+ return NPCM7XX_CLOCK_PLLG;

+ default:

+ g_assert_not_reached();

+ }

+}

+

+static void npcm7xx_clk_update_all_plls(NPCM7xxCLKState *clk)

+

+ for (i = 0; i < NPCM7XX_CLOCK_NR_PLLS; ++i) {

+ npcm7xx_clk_update_pll(&clk->plls[i]);

+static void npcm7xx_clk_update_all_sels(NPCM7xxCLKState *clk)

+

+ for (i = 0; i < NPCM7XX_CLOCK_NR_SELS; ++i) {

+ npcm7xx_clk_update_sel(&clk->sels[i]);

+static void npcm7xx_clk_update_all_dividers(NPCM7xxCLKState *clk)

+ int i;

+

+ for (i = 0; i < NPCM7XX_CLOCK_NR_DIVIDERS; ++i) {

+ npcm7xx_clk_update_divider(&clk->dividers[i]);

+ }

+static void npcm7xx_clk_update_all_clocks(NPCM7xxCLKState *clk)

+{

+ clock_update_hz(clk->clkref, NPCM7XX_CLOCK_REF_HZ);

+ npcm7xx_clk_update_all_plls(clk);

+ npcm7xx_clk_update_all_sels(clk);

+ npcm7xx_clk_update_all_dividers(clk);

+}

+

+/* Types of clock sources. */

+typedef enum ClockSrcType {

+ CLKSRC_REF,

+ CLKSRC_PLL,

+ CLKSRC_SEL,

+ CLKSRC_DIV,

+} ClockSrcType;

+

+typedef struct PLLInitInfo {

+ const char *name;

+ ClockSrcType src_type;

+ int src_index;

+ int reg;

+ const char *public_name;

+} PLLInitInfo;

+

+typedef struct SELInitInfo {

+ const char *name;

+ uint8_t input_size;

+ ClockSrcType src_type[NPCM7XX_CLK_SEL_MAX_INPUT];

+ int src_index[NPCM7XX_CLK_SEL_MAX_INPUT];

+ int offset;

+ int len;

+ const char *public_name;

+} SELInitInfo;

+

+typedef struct DividerInitInfo {

+ const char *name;

+ ClockSrcType src_type;

+ int src_index;

+ uint32_t (*divide)(NPCM7xxClockDividerState *s);

+ int reg; /* not used when type == CONSTANT */

+ int offset; /* not used when type == CONSTANT */

+ int len; /* not used when type == CONSTANT */

+ int divisor; /* used only when type == CONSTANT */

+ const char *public_name;

+} DividerInitInfo;

+

+static const PLLInitInfo pll_init_info_list[] = {

+ [NPCM7XX_CLOCK_PLL0] = {

+ .name = "pll0",

+ .src_type = CLKSRC_REF,

+ .reg = NPCM7XX_CLK_PLLCON0,

+ },

+ [NPCM7XX_CLOCK_PLL1] = {

+ .name = "pll1",

+ .src_type = CLKSRC_REF,

+ .reg = NPCM7XX_CLK_PLLCON1,

+ },

+ [NPCM7XX_CLOCK_PLL2] = {

+ .name = "pll2",

+ .src_type = CLKSRC_REF,

+ .reg = NPCM7XX_CLK_PLLCON2,

+ },

+ [NPCM7XX_CLOCK_PLLG] = {

+ .name = "pllg",

+ .src_type = CLKSRC_REF,

+ .reg = NPCM7XX_CLK_PLLCONG,

+ },

+};

+

+static const SELInitInfo sel_init_info_list[] = {

+ [NPCM7XX_CLOCK_PIXCKSEL] = {

+ .name = "pixcksel",

+ .input_size = 2,

+ .src_type = {CLKSRC_PLL, CLKSRC_REF},

+ .src_index = {NPCM7XX_CLOCK_PLLG, 0},

+ .offset = 5,

+ .len = 1,

+ .public_name = "pixel-clock",

+ },

+ [NPCM7XX_CLOCK_MCCKSEL] = {

+ .name = "mccksel",

+ .input_size = 4,

+ .src_type = {CLKSRC_DIV, CLKSRC_REF, CLKSRC_REF,

+ /*MCBPCK, shouldn't be used in normal operation*/

+ CLKSRC_REF},

+ .src_index = {NPCM7XX_CLOCK_PLL1D2, 0, 0, 0},

+ .offset = 12,

+ .len = 2,

+ .public_name = "mc-phy-clock",

+ },

+ [NPCM7XX_CLOCK_CPUCKSEL] = {

+ .name = "cpucksel",

+ .input_size = 4,

+ .src_type = {CLKSRC_PLL, CLKSRC_DIV, CLKSRC_REF,

+ /*SYSBPCK, shouldn't be used in normal operation*/

+ CLKSRC_REF},

+ .src_index = {NPCM7XX_CLOCK_PLL0, NPCM7XX_CLOCK_PLL1D2, 0, 0},

+ .offset = 0,

+ .len = 2,

+ .public_name = "system-clock",

+ },

+ [NPCM7XX_CLOCK_CLKOUTSEL] = {

+ .name = "clkoutsel",

+ .input_size = 5,

+ .src_type = {CLKSRC_PLL, CLKSRC_DIV, CLKSRC_REF,

+ CLKSRC_PLL, CLKSRC_DIV},

+ .src_index = {NPCM7XX_CLOCK_PLL0, NPCM7XX_CLOCK_PLL1D2, 0,

+ NPCM7XX_CLOCK_PLLG, NPCM7XX_CLOCK_PLL2D2},

+ .offset = 18,

+ .len = 3,

+ .public_name = "tock",

+ },

+ [NPCM7XX_CLOCK_UARTCKSEL] = {

+ .name = "uartcksel",

+ .input_size = 4,

+ .src_type = {CLKSRC_PLL, CLKSRC_DIV, CLKSRC_REF, CLKSRC_DIV},

+ .src_index = {NPCM7XX_CLOCK_PLL0, NPCM7XX_CLOCK_PLL1D2, 0,

+ NPCM7XX_CLOCK_PLL2D2},

+ .offset = 8,

+ .len = 2,

+ },

+ [NPCM7XX_CLOCK_TIMCKSEL] = {

+ .name = "timcksel",

+ .input_size = 4,

+ .src_type = {CLKSRC_PLL, CLKSRC_DIV, CLKSRC_REF, CLKSRC_DIV},

+ .src_index = {NPCM7XX_CLOCK_PLL0, NPCM7XX_CLOCK_PLL1D2, 0,

+ NPCM7XX_CLOCK_PLL2D2},

+ .offset = 14,

+ .len = 2,

+ },

+ [NPCM7XX_CLOCK_SDCKSEL] = {

+ .name = "sdcksel",

+ .input_size = 4,

+ .src_type = {CLKSRC_PLL, CLKSRC_DIV, CLKSRC_REF, CLKSRC_DIV},

+ .src_index = {NPCM7XX_CLOCK_PLL0, NPCM7XX_CLOCK_PLL1D2, 0,

+ NPCM7XX_CLOCK_PLL2D2},

+ .offset = 6,

+ .len = 2,

+ },

+ [NPCM7XX_CLOCK_GFXMSEL] = {

+ .name = "gfxmksel",

+ .input_size = 2,

+ .src_type = {CLKSRC_REF, CLKSRC_PLL},

+ .src_index = {0, NPCM7XX_CLOCK_PLL2},

+ .offset = 21,

+ .len = 1,

+ },

+ [NPCM7XX_CLOCK_SUCKSEL] = {

+ .name = "sucksel",

+ .input_size = 4,

+ .src_type = {CLKSRC_PLL, CLKSRC_DIV, CLKSRC_REF, CLKSRC_DIV},

+ .src_index = {NPCM7XX_CLOCK_PLL0, NPCM7XX_CLOCK_PLL1D2, 0,

+ NPCM7XX_CLOCK_PLL2D2},

+ .offset = 10,

+ .len = 2,

+ },

+};

+

+static const DividerInitInfo divider_init_info_list[] = {

+ [NPCM7XX_CLOCK_PLL1D2] = {

+ .name = "pll1d2",

+ .src_type = CLKSRC_PLL,

+ .src_index = NPCM7XX_CLOCK_PLL1,

+ .divide = divide_by_constant,

+ .divisor = 2,

+ },

+ [NPCM7XX_CLOCK_PLL2D2] = {