[v6] support vector extension v1.0

[PATCH v6 20/72] target/riscv: rvv-1.0: fix address index overflow bug of indexed load/store insns

Posted by frank.chang@sifive.com 5 years ago

From: Frank Chang <frank.chang@sifive.com>

Replace ETYPE from signed int to unsigned int to prevent index overflow
issue, which would lead to wrong index address.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/riscv/vector_helper.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 368259f75a0..9349a36b41b 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -361,10 +361,10 @@ static target_ulong NAME(target_ulong base,            \
     return (base + *((ETYPE *)vs2 + H(idx)));          \
 }
 
-GEN_VEXT_GET_INDEX_ADDR(idx_b, int8_t,  H1)
-GEN_VEXT_GET_INDEX_ADDR(idx_h, int16_t, H2)
-GEN_VEXT_GET_INDEX_ADDR(idx_w, int32_t, H4)
-GEN_VEXT_GET_INDEX_ADDR(idx_d, int64_t, H8)
+GEN_VEXT_GET_INDEX_ADDR(idx_b, uint8_t,  H1)
+GEN_VEXT_GET_INDEX_ADDR(idx_h, uint16_t, H2)
+GEN_VEXT_GET_INDEX_ADDR(idx_w, uint32_t, H4)
+GEN_VEXT_GET_INDEX_ADDR(idx_d, uint64_t, H8)
 
 static inline void
 vext_ldst_index(void *vd, void *v0, target_ulong base,
-- 
2.17.1

Re: [PATCH v6 20/72] target/riscv: rvv-1.0: fix address index overflow bug of indexed load/store insns

Posted by Alistair Francis 5 years ago

On Tue, Jan 12, 2021 at 1:57 AM <frank.chang@sifive.com> wrote:
>
> From: Frank Chang <frank.chang@sifive.com>
>
> Replace ETYPE from signed int to unsigned int to prevent index overflow
> issue, which would lead to wrong index address.
>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/vector_helper.c | 8 ++++----
>  1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
> index 368259f75a0..9349a36b41b 100644
> --- a/target/riscv/vector_helper.c
> +++ b/target/riscv/vector_helper.c
> @@ -361,10 +361,10 @@ static target_ulong NAME(target_ulong base,            \
>      return (base + *((ETYPE *)vs2 + H(idx)));          \
>  }
>
> -GEN_VEXT_GET_INDEX_ADDR(idx_b, int8_t,  H1)
> -GEN_VEXT_GET_INDEX_ADDR(idx_h, int16_t, H2)
> -GEN_VEXT_GET_INDEX_ADDR(idx_w, int32_t, H4)
> -GEN_VEXT_GET_INDEX_ADDR(idx_d, int64_t, H8)
> +GEN_VEXT_GET_INDEX_ADDR(idx_b, uint8_t,  H1)
> +GEN_VEXT_GET_INDEX_ADDR(idx_h, uint16_t, H2)
> +GEN_VEXT_GET_INDEX_ADDR(idx_w, uint32_t, H4)
> +GEN_VEXT_GET_INDEX_ADDR(idx_d, uint64_t, H8)
>
>  static inline void
>  vext_ldst_index(void *vd, void *v0, target_ulong base,
> --
> 2.17.1
>
>