1
Nothing too exciting, but does include the last bits of v8.1M support work.
1
The following changes since commit b11728dc3ae67ddedf34b7a4f318170e7092803c:
2
2
3
-- PMM
3
Merge tag 'pull-riscv-to-apply-20230224' of github.com:palmer-dabbelt/qemu into staging (2023-02-26 20:14:46 +0000)
4
5
The following changes since commit e79de63ab1bd1f6550e7b915e433bec1ad1a870a:
6
7
Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-tcg-20210107' into staging (2021-01-07 20:34:05 +0000)
8
4
9
are available in the Git repository at:
5
are available in the Git repository at:
10
6
11
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210108
7
https://git.linaro.org/people/pmaydell/qemu-arm.git pull-target-arm-20230227
12
8
13
for you to fetch changes up to c9f8511ea8d2b80723af0fea1f716d752c1b5208:
9
for you to fetch changes up to e844f0c5d0bd2c4d8d3c1622eb2a88586c9c4677:
14
10
15
docs/system: arm: Add sabrelite board description (2021-01-08 15:13:39 +0000)
11
hw: Replace qemu_or_irq typedef by OrIRQState (2023-02-27 13:27:05 +0000)
16
12
17
----------------------------------------------------------------
13
----------------------------------------------------------------
18
target-arm queue:
14
target-arm queue:
19
* intc/arm_gic: Fix gic_irq_signaling_enabled() for vCPUs
15
* Various code cleanups
20
* target/arm: Fix MTE0_ACTIVE
16
* More refactoring working towards allowing a build
21
* target/arm: Implement v8.1M and Cortex-M55 model
17
without CONFIG_TCG
22
* hw/arm/highbank: Drop dead KVM support code
23
* util/qemu-timer: Make timer_free() imply timer_del()
24
* various devices: Use ptimer_free() in finalize function
25
* docs/system: arm: Add sabrelite board description
26
* sabrelite: Minor fixes to allow booting U-Boot
27
18
28
----------------------------------------------------------------
19
----------------------------------------------------------------
29
Andrew Jones (1):
20
Claudio Fontana (2):
30
hw/arm/virt: Remove virt machine state 'smp_cpus'
21
target/arm: move helpers to tcg/
22
target/arm: Move psci.c into the tcg directory
31
23
32
Bin Meng (4):
24
Fabiano Rosas (9):
33
hw/misc: imx6_ccm: Update PMU_MISC0 reset value
25
target/arm: Wrap breakpoint/watchpoint updates with tcg_enabled
34
hw/msic: imx6_ccm: Correct register value for silicon type
26
target/arm: Wrap TCG-only code in debug_helper.c
35
hw/arm: sabrelite: Connect the Ethernet PHY at address 6
27
target/arm: move translate modules to tcg/
36
docs/system: arm: Add sabrelite board description
28
target/arm: Wrap arm_rebuild_hflags calls with tcg_enabled
29
target/arm: Move hflags code into the tcg directory
30
target/arm: Move regime_using_lpae_format into internal.h
31
target/arm: Don't access TCG code when debugging with KVM
32
cpu-defs.h: Expose CPUTLBEntryFull to non-TCG code
33
tests/avocado: add machine:none tag to version.py
37
34
38
Edgar E. Iglesias (1):
35
Philippe Mathieu-Daudé (13):
39
intc/arm_gic: Fix gic_irq_signaling_enabled() for vCPUs
36
hw/gpio/max7310: Simplify max7310_realize()
37
hw/char/pl011: Un-inline pl011_create()
38
hw/char/pl011: Open-code pl011_luminary_create()
39
hw/char/xilinx_uartlite: Expose XILINX_UARTLITE QOM type
40
hw/char/xilinx_uartlite: Open-code xilinx_uartlite_create()
41
hw/char/cmsdk-apb-uart: Open-code cmsdk_apb_uart_create()
42
hw/timer/cmsdk-apb-timer: Remove unused 'qdev-properties.h' header
43
hw/intc/armv7m_nvic: Use QOM cast CPU() macro
44
hw/arm/musicpal: Remove unused dummy MemoryRegion
45
iothread: Remove unused IOThreadClass / IOTHREAD_CLASS
46
hw/irq: Declare QOM macros using OBJECT_DECLARE_SIMPLE_TYPE()
47
hw/or-irq: Declare QOM macros using OBJECT_DECLARE_SIMPLE_TYPE()
48
hw: Replace qemu_or_irq typedef by OrIRQState
40
49
41
Gan Qixin (7):
50
Thomas Huth (1):
42
digic-timer: Use ptimer_free() in the finalize function to avoid memleaks
51
include/hw/arm/allwinner-a10.h: Remove superfluous includes from the header
43
allwinner-a10-pit: Use ptimer_free() in the finalize function to avoid memleaks
44
exynos4210_rtc: Use ptimer_free() in the finalize function to avoid memleaks
45
exynos4210_pwm: Use ptimer_free() in the finalize function to avoid memleaks
46
mss-timer: Use ptimer_free() in the finalize function to avoid memleaks
47
musicpal: Use ptimer_free() in the finalize function to avoid memleaks
48
exynos4210_mct: Use ptimer_free() in the finalize function to avoid memleaks
49
52
50
Peter Maydell (9):
53
MAINTAINERS | 1 +
51
hw/intc/armv7m_nvic: Correct handling of CCR.BFHFNMIGN
54
include/exec/cpu-defs.h | 6 +
52
target/arm: Correct store of FPSCR value via FPCXT_S
55
include/hw/arm/allwinner-a10.h | 2 -
53
target/arm: Implement FPCXT_NS fp system register
56
include/hw/arm/armsse.h | 6 +-
54
target/arm: Implement Cortex-M55 model
57
include/hw/arm/bcm2835_peripherals.h | 2 +-
55
hw/arm/highbank: Drop dead KVM support code
58
include/hw/arm/exynos4210.h | 4 +-
56
util/qemu-timer: Make timer_free() imply timer_del()
59
include/hw/arm/stm32f205_soc.h | 2 +-
57
scripts/coccinelle: New script to remove unnecessary timer_del() calls
60
include/hw/arm/stm32f405_soc.h | 2 +-
58
Remove superfluous timer_del() calls
61
include/hw/arm/xlnx-versal.h | 6 +-
59
target/arm: Remove timer_del()/timer_deinit() before timer_free()
62
include/hw/arm/xlnx-zynqmp.h | 2 +-
63
include/hw/char/cmsdk-apb-uart.h | 34 ---
64
include/hw/char/pl011.h | 36 +--
65
include/hw/char/xilinx_uartlite.h | 22 +-
66
include/hw/or-irq.h | 5 +-
67
include/hw/timer/cmsdk-apb-timer.h | 1 -
68
target/arm/internals.h | 23 +-
69
target/arm/{ => tcg}/translate-a64.h | 0
70
target/arm/{ => tcg}/translate.h | 0
71
target/arm/{ => tcg}/vec_internal.h | 0
72
target/arm/{ => tcg}/a32-uncond.decode | 0
73
target/arm/{ => tcg}/a32.decode | 0
74
target/arm/{ => tcg}/m-nocp.decode | 0
75
target/arm/{ => tcg}/mve.decode | 0
76
target/arm/{ => tcg}/neon-dp.decode | 0
77
target/arm/{ => tcg}/neon-ls.decode | 0
78
target/arm/{ => tcg}/neon-shared.decode | 0
79
target/arm/{ => tcg}/sme-fa64.decode | 0
80
target/arm/{ => tcg}/sme.decode | 0
81
target/arm/{ => tcg}/sve.decode | 0
82
target/arm/{ => tcg}/t16.decode | 0
83
target/arm/{ => tcg}/t32.decode | 0
84
target/arm/{ => tcg}/vfp-uncond.decode | 0
85
target/arm/{ => tcg}/vfp.decode | 0
86
hw/arm/allwinner-a10.c | 1 +
87
hw/arm/boot.c | 6 +-
88
hw/arm/exynos4210.c | 4 +-
89
hw/arm/mps2-tz.c | 2 +-
90
hw/arm/mps2.c | 41 ++-
91
hw/arm/musicpal.c | 4 -
92
hw/arm/stellaris.c | 11 +-
93
hw/char/pl011.c | 17 ++
94
hw/char/xilinx_uartlite.c | 4 +-
95
hw/core/irq.c | 9 +-
96
hw/core/or-irq.c | 18 +-
97
hw/gpio/max7310.c | 5 +-
98
hw/intc/armv7m_nvic.c | 26 +-
99
hw/microblaze/petalogix_s3adsp1800_mmu.c | 7 +-
100
hw/pci-host/raven.c | 2 +-
101
iothread.c | 4 -
102
target/arm/arm-powerctl.c | 7 +-
103
target/arm/cpu.c | 9 +-
104
target/arm/debug_helper.c | 490 ++++++++++++++++---------------
105
target/arm/helper.c | 411 +-------------------------
106
target/arm/machine.c | 12 +-
107
target/arm/ptw.c | 4 +
108
target/arm/tcg-stubs.c | 27 ++
109
target/arm/{ => tcg}/crypto_helper.c | 0
110
target/arm/{ => tcg}/helper-a64.c | 0
111
target/arm/tcg/hflags.c | 403 +++++++++++++++++++++++++
112
target/arm/{ => tcg}/iwmmxt_helper.c | 0
113
target/arm/{ => tcg}/m_helper.c | 0
114
target/arm/{ => tcg}/mte_helper.c | 0
115
target/arm/{ => tcg}/mve_helper.c | 0
116
target/arm/{ => tcg}/neon_helper.c | 0
117
target/arm/{ => tcg}/op_helper.c | 0
118
target/arm/{ => tcg}/pauth_helper.c | 0
119
target/arm/{ => tcg}/psci.c | 0
120
target/arm/{ => tcg}/sme_helper.c | 0
121
target/arm/{ => tcg}/sve_helper.c | 0
122
target/arm/{ => tcg}/tlb_helper.c | 18 --
123
target/arm/{ => tcg}/translate-a64.c | 0
124
target/arm/{ => tcg}/translate-m-nocp.c | 0
125
target/arm/{ => tcg}/translate-mve.c | 0
126
target/arm/{ => tcg}/translate-neon.c | 0
127
target/arm/{ => tcg}/translate-sme.c | 0
128
target/arm/{ => tcg}/translate-sve.c | 0
129
target/arm/{ => tcg}/translate-vfp.c | 0
130
target/arm/{ => tcg}/translate.c | 0
131
target/arm/{ => tcg}/vec_helper.c | 0
132
target/arm/meson.build | 46 +--
133
target/arm/tcg/meson.build | 50 ++++
134
tests/avocado/version.py | 1 +
135
82 files changed, 918 insertions(+), 875 deletions(-)
136
rename target/arm/{ => tcg}/translate-a64.h (100%)
137
rename target/arm/{ => tcg}/translate.h (100%)
138
rename target/arm/{ => tcg}/vec_internal.h (100%)
139
rename target/arm/{ => tcg}/a32-uncond.decode (100%)
140
rename target/arm/{ => tcg}/a32.decode (100%)
141
rename target/arm/{ => tcg}/m-nocp.decode (100%)
142
rename target/arm/{ => tcg}/mve.decode (100%)
143
rename target/arm/{ => tcg}/neon-dp.decode (100%)
144
rename target/arm/{ => tcg}/neon-ls.decode (100%)
145
rename target/arm/{ => tcg}/neon-shared.decode (100%)
146
rename target/arm/{ => tcg}/sme-fa64.decode (100%)
147
rename target/arm/{ => tcg}/sme.decode (100%)
148
rename target/arm/{ => tcg}/sve.decode (100%)
149
rename target/arm/{ => tcg}/t16.decode (100%)
150
rename target/arm/{ => tcg}/t32.decode (100%)
151
rename target/arm/{ => tcg}/vfp-uncond.decode (100%)
152
rename target/arm/{ => tcg}/vfp.decode (100%)
153
create mode 100644 target/arm/tcg-stubs.c
154
rename target/arm/{ => tcg}/crypto_helper.c (100%)
155
rename target/arm/{ => tcg}/helper-a64.c (100%)
156
create mode 100644 target/arm/tcg/hflags.c
157
rename target/arm/{ => tcg}/iwmmxt_helper.c (100%)
158
rename target/arm/{ => tcg}/m_helper.c (100%)
159
rename target/arm/{ => tcg}/mte_helper.c (100%)
160
rename target/arm/{ => tcg}/mve_helper.c (100%)
161
rename target/arm/{ => tcg}/neon_helper.c (100%)
162
rename target/arm/{ => tcg}/op_helper.c (100%)
163
rename target/arm/{ => tcg}/pauth_helper.c (100%)
164
rename target/arm/{ => tcg}/psci.c (100%)
165
rename target/arm/{ => tcg}/sme_helper.c (100%)
166
rename target/arm/{ => tcg}/sve_helper.c (100%)
167
rename target/arm/{ => tcg}/tlb_helper.c (94%)
168
rename target/arm/{ => tcg}/translate-a64.c (100%)
169
rename target/arm/{ => tcg}/translate-m-nocp.c (100%)
170
rename target/arm/{ => tcg}/translate-mve.c (100%)
171
rename target/arm/{ => tcg}/translate-neon.c (100%)
172
rename target/arm/{ => tcg}/translate-sme.c (100%)
173
rename target/arm/{ => tcg}/translate-sve.c (100%)
174
rename target/arm/{ => tcg}/translate-vfp.c (100%)
175
rename target/arm/{ => tcg}/translate.c (100%)
176
rename target/arm/{ => tcg}/vec_helper.c (100%)
177
create mode 100644 target/arm/tcg/meson.build
60
178
61
Richard Henderson (1):
62
target/arm: Fix MTE0_ACTIVE
63
64
docs/system/arm/sabrelite.rst | 119 ++++++++++++++++++++++++++
65
docs/system/target-arm.rst | 1 +
66
scripts/coccinelle/timer-del-timer-free.cocci | 18 ++++
67
include/hw/arm/virt.h | 3 +-
68
include/qemu/timer.h | 24 +++---
69
block/iscsi.c | 2 -
70
block/nbd.c | 1 -
71
block/qcow2.c | 1 -
72
hw/arm/highbank.c | 14 +--
73
hw/arm/musicpal.c | 12 +++
74
hw/arm/sabrelite.c | 4 +
75
hw/arm/virt-acpi-build.c | 9 +-
76
hw/arm/virt.c | 21 +++--
77
hw/block/nvme.c | 2 -
78
hw/char/serial.c | 2 -
79
hw/char/virtio-serial-bus.c | 2 -
80
hw/ide/core.c | 1 -
81
hw/input/hid.c | 1 -
82
hw/intc/apic.c | 1 -
83
hw/intc/arm_gic.c | 4 +-
84
hw/intc/armv7m_nvic.c | 15 ++++
85
hw/intc/ioapic.c | 1 -
86
hw/ipmi/ipmi_bmc_extern.c | 1 -
87
hw/misc/imx6_ccm.c | 4 +-
88
hw/net/e1000.c | 3 -
89
hw/net/e1000e_core.c | 8 --
90
hw/net/pcnet-pci.c | 1 -
91
hw/net/rtl8139.c | 1 -
92
hw/net/spapr_llan.c | 1 -
93
hw/net/virtio-net.c | 2 -
94
hw/rtc/exynos4210_rtc.c | 9 ++
95
hw/s390x/s390-pci-inst.c | 1 -
96
hw/sd/sd.c | 1 -
97
hw/sd/sdhci.c | 2 -
98
hw/timer/allwinner-a10-pit.c | 11 +++
99
hw/timer/digic-timer.c | 8 ++
100
hw/timer/exynos4210_mct.c | 14 +++
101
hw/timer/exynos4210_pwm.c | 11 +++
102
hw/timer/mss-timer.c | 13 +++
103
hw/usb/dev-hub.c | 1 -
104
hw/usb/hcd-ehci.c | 1 -
105
hw/usb/hcd-ohci-pci.c | 1 -
106
hw/usb/hcd-uhci.c | 1 -
107
hw/usb/hcd-xhci.c | 1 -
108
hw/usb/redirect.c | 1 -
109
hw/vfio/display.c | 1 -
110
hw/virtio/vhost-vsock-common.c | 1 -
111
hw/virtio/virtio-balloon.c | 1 -
112
hw/virtio/virtio-rng.c | 1 -
113
hw/watchdog/wdt_diag288.c | 1 -
114
hw/watchdog/wdt_i6300esb.c | 1 -
115
migration/colo.c | 1 -
116
monitor/hmp-cmds.c | 1 -
117
net/announce.c | 1 -
118
net/colo-compare.c | 1 -
119
net/slirp.c | 1 -
120
replay/replay-debugging.c | 1 -
121
target/arm/cpu.c | 2 -
122
target/arm/cpu_tcg.c | 42 +++++++++
123
target/arm/helper.c | 2 +-
124
target/s390x/cpu.c | 2 -
125
ui/console.c | 1 -
126
ui/spice-core.c | 1 -
127
util/throttle.c | 1 -
128
target/arm/translate-vfp.c.inc | 114 ++++++++++++++++++++++--
129
65 files changed, 421 insertions(+), 111 deletions(-)
130
create mode 100644 docs/system/arm/sabrelite.rst
131
create mode 100644 scripts/coccinelle/timer-del-timer-free.cocci
132
diff view generated by jsdifflib
New patch
1
From: Thomas Huth <thuth@redhat.com>
1
2
3
pci_device.h is not needed at all in allwinner-a10.h, and serial.h
4
is only needed by the corresponding .c file.
5
6
Signed-off-by: Thomas Huth <thuth@redhat.com>
7
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
8
Message-id: 20230215152233.210024-1-thuth@redhat.com
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
include/hw/arm/allwinner-a10.h | 2 --
12
hw/arm/allwinner-a10.c | 1 +
13
2 files changed, 1 insertion(+), 2 deletions(-)
14
15
diff --git a/include/hw/arm/allwinner-a10.h b/include/hw/arm/allwinner-a10.h
16
index XXXXXXX..XXXXXXX 100644
17
--- a/include/hw/arm/allwinner-a10.h
18
+++ b/include/hw/arm/allwinner-a10.h
19
@@ -XXX,XX +XXX,XX @@
20
#ifndef HW_ARM_ALLWINNER_A10_H
21
#define HW_ARM_ALLWINNER_A10_H
22
23
-#include "hw/char/serial.h"
24
#include "hw/arm/boot.h"
25
-#include "hw/pci/pci_device.h"
26
#include "hw/timer/allwinner-a10-pit.h"
27
#include "hw/intc/allwinner-a10-pic.h"
28
#include "hw/net/allwinner_emac.h"
29
diff --git a/hw/arm/allwinner-a10.c b/hw/arm/allwinner-a10.c
30
index XXXXXXX..XXXXXXX 100644
31
--- a/hw/arm/allwinner-a10.c
32
+++ b/hw/arm/allwinner-a10.c
33
@@ -XXX,XX +XXX,XX @@
34
#include "qemu/osdep.h"
35
#include "qapi/error.h"
36
#include "qemu/module.h"
37
+#include "hw/char/serial.h"
38
#include "hw/sysbus.h"
39
#include "hw/arm/allwinner-a10.h"
40
#include "hw/misc/unimp.h"
41
--
42
2.34.1
43
44
diff view generated by jsdifflib
1
The Arm CPU finalize function uses a sequence of timer_del(), timer_deinit(),
1
From: Fabiano Rosas <farosas@suse.de>
2
timer_free() to free the timer. The timer_deinit() step in this was always
3
unnecessary, and now the timer_del() is implied by timer_free(), so we can
4
collapse this down to simply calling timer_free().
5
2
3
This is in preparation for restricting compilation of some parts of
4
debug_helper.c to TCG only.
5
6
Signed-off-by: Fabiano Rosas <farosas@suse.de>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20201215154107.3255-5-peter.maydell@linaro.org
10
---
9
---
11
target/arm/cpu.c | 2 --
10
target/arm/cpu.c | 6 ++++--
12
1 file changed, 2 deletions(-)
11
target/arm/debug_helper.c | 16 ++++++++++++----
12
target/arm/machine.c | 7 +++++--
13
3 files changed, 21 insertions(+), 8 deletions(-)
13
14
14
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
15
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
15
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/cpu.c
17
--- a/target/arm/cpu.c
17
+++ b/target/arm/cpu.c
18
+++ b/target/arm/cpu.c
18
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_finalizefn(Object *obj)
19
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset_hold(Object *obj)
19
}
20
#ifndef CONFIG_USER_ONLY
21
if (cpu->pmu_timer) {
22
- timer_del(cpu->pmu_timer);
23
- timer_deinit(cpu->pmu_timer);
24
timer_free(cpu->pmu_timer);
25
}
20
}
26
#endif
21
#endif
22
23
- hw_breakpoint_update_all(cpu);
24
- hw_watchpoint_update_all(cpu);
25
+ if (tcg_enabled()) {
26
+ hw_breakpoint_update_all(cpu);
27
+ hw_watchpoint_update_all(cpu);
28
+ }
29
arm_rebuild_hflags(env);
30
}
31
32
diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c
33
index XXXXXXX..XXXXXXX 100644
34
--- a/target/arm/debug_helper.c
35
+++ b/target/arm/debug_helper.c
36
@@ -XXX,XX +XXX,XX @@ static void dbgwvr_write(CPUARMState *env, const ARMCPRegInfo *ri,
37
value &= ~3ULL;
38
39
raw_write(env, ri, value);
40
- hw_watchpoint_update(cpu, i);
41
+ if (tcg_enabled()) {
42
+ hw_watchpoint_update(cpu, i);
43
+ }
44
}
45
46
static void dbgwcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
47
@@ -XXX,XX +XXX,XX @@ static void dbgwcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
48
int i = ri->crm;
49
50
raw_write(env, ri, value);
51
- hw_watchpoint_update(cpu, i);
52
+ if (tcg_enabled()) {
53
+ hw_watchpoint_update(cpu, i);
54
+ }
55
}
56
57
void hw_breakpoint_update(ARMCPU *cpu, int n)
58
@@ -XXX,XX +XXX,XX @@ static void dbgbvr_write(CPUARMState *env, const ARMCPRegInfo *ri,
59
int i = ri->crm;
60
61
raw_write(env, ri, value);
62
- hw_breakpoint_update(cpu, i);
63
+ if (tcg_enabled()) {
64
+ hw_breakpoint_update(cpu, i);
65
+ }
66
}
67
68
static void dbgbcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
69
@@ -XXX,XX +XXX,XX @@ static void dbgbcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
70
value = deposit64(value, 8, 1, extract64(value, 7, 1));
71
72
raw_write(env, ri, value);
73
- hw_breakpoint_update(cpu, i);
74
+ if (tcg_enabled()) {
75
+ hw_breakpoint_update(cpu, i);
76
+ }
77
}
78
79
void define_debug_regs(ARMCPU *cpu)
80
diff --git a/target/arm/machine.c b/target/arm/machine.c
81
index XXXXXXX..XXXXXXX 100644
82
--- a/target/arm/machine.c
83
+++ b/target/arm/machine.c
84
@@ -XXX,XX +XXX,XX @@
85
#include "cpu.h"
86
#include "qemu/error-report.h"
87
#include "sysemu/kvm.h"
88
+#include "sysemu/tcg.h"
89
#include "kvm_arm.h"
90
#include "internals.h"
91
#include "migration/cpu.h"
92
@@ -XXX,XX +XXX,XX @@ static int cpu_post_load(void *opaque, int version_id)
93
return -1;
94
}
95
96
- hw_breakpoint_update_all(cpu);
97
- hw_watchpoint_update_all(cpu);
98
+ if (tcg_enabled()) {
99
+ hw_breakpoint_update_all(cpu);
100
+ hw_watchpoint_update_all(cpu);
101
+ }
102
103
/*
104
* TCG gen_update_fp_context() relies on the invariant that
27
--
105
--
28
2.20.1
106
2.34.1
29
30
diff view generated by jsdifflib
1
From: Gan Qixin <ganqixin@huawei.com>
1
From: Fabiano Rosas <farosas@suse.de>
2
2
3
When running device-introspect-test, a memory leak occurred in the
3
The next few patches will move helpers under CONFIG_TCG. We'd prefer
4
mss_timer_init function, so use ptimer_free() in the finalize function to avoid
4
to keep the debug helpers and debug registers close together, so
5
it.
5
rearrange the file a bit to be able to wrap the helpers with a TCG
6
ifdef.
6
7
7
ASAN shows memory leak stack:
8
Signed-off-by: Fabiano Rosas <farosas@suse.de>
8
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Indirect leak of 192 byte(s) in 2 object(s) allocated from:
10
#0 0xffffab97e1f0 in __interceptor_calloc (/lib64/libasan.so.5+0xee1f0)
11
#1 0xffffab256800 in g_malloc0 (/lib64/libglib-2.0.so.0+0x56800)
12
#2 0xaaabf555db78 in ptimer_init /qemu/hw/core/ptimer.c:432
13
#3 0xaaabf58a0010 in mss_timer_init /qemu/hw/timer/mss-timer.c:235
14
#4 0xaaabf6339f6c in object_initialize_with_type /qemu/qom/object.c:515
15
#5 0xaaabf633ca04 in object_initialize_child_with_propsv /qemu/qom/object.c:564
16
#6 0xaaabf633cc08 in object_initialize_child_with_props /qemu/qom/object.c:547
17
#7 0xaaabf5b8316c in m2sxxx_soc_initfn /qemu/hw/arm/msf2-soc.c:70
18
#8 0xaaabf6339f6c in object_initialize_with_type /qemu/qom/object.c:515
19
#9 0xaaabf633a1e0 in object_new_with_type /qemu/qom/object.c:729
20
#10 0xaaabf6375e40 in qmp_device_list_properties /qemu/qom/qom-qmp-cmds.c:153
21
#11 0xaaabf653d8ec in qmp_marshal_device_list_properties /qemu/qapi/qapi-commands-qdev.c:59
22
#12 0xaaabf6587d08 in do_qmp_dispatch_bh /qemu/qapi/qmp-dispatch.c:110
23
24
Reported-by: Euler Robot <euler.robot@huawei.com>
25
Signed-off-by: Gan Qixin <ganqixin@huawei.com>
26
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
27
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
28
---
11
---
29
hw/timer/mss-timer.c | 13 +++++++++++++
12
target/arm/debug_helper.c | 476 +++++++++++++++++++-------------------
30
1 file changed, 13 insertions(+)
13
1 file changed, 239 insertions(+), 237 deletions(-)
31
14
32
diff --git a/hw/timer/mss-timer.c b/hw/timer/mss-timer.c
15
diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c
33
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
34
--- a/hw/timer/mss-timer.c
17
--- a/target/arm/debug_helper.c
35
+++ b/hw/timer/mss-timer.c
18
+++ b/target/arm/debug_helper.c
36
@@ -XXX,XX +XXX,XX @@ static void mss_timer_init(Object *obj)
19
@@ -XXX,XX +XXX,XX @@
37
sysbus_init_mmio(SYS_BUS_DEVICE(obj), &t->mmio);
20
#include "cpregs.h"
21
#include "exec/exec-all.h"
22
#include "exec/helper-proto.h"
23
+#include "sysemu/tcg.h"
24
25
-
26
+#ifdef CONFIG_TCG
27
/* Return the Exception Level targeted by debug exceptions. */
28
static int arm_debug_target_el(CPUARMState *env)
29
{
30
@@ -XXX,XX +XXX,XX @@ void HELPER(exception_swstep)(CPUARMState *env, uint32_t syndrome)
31
raise_exception_debug(env, EXCP_UDEF, syndrome);
38
}
32
}
39
33
40
+static void mss_timer_finalize(Object *obj)
34
+void hw_watchpoint_update(ARMCPU *cpu, int n)
41
+{
35
+{
42
+ MSSTimerState *t = MSS_TIMER(obj);
36
+ CPUARMState *env = &cpu->env;
37
+ vaddr len = 0;
38
+ vaddr wvr = env->cp15.dbgwvr[n];
39
+ uint64_t wcr = env->cp15.dbgwcr[n];
40
+ int mask;
41
+ int flags = BP_CPU | BP_STOP_BEFORE_ACCESS;
42
+
43
+ if (env->cpu_watchpoint[n]) {
44
+ cpu_watchpoint_remove_by_ref(CPU(cpu), env->cpu_watchpoint[n]);
45
+ env->cpu_watchpoint[n] = NULL;
46
+ }
47
+
48
+ if (!FIELD_EX64(wcr, DBGWCR, E)) {
49
+ /* E bit clear : watchpoint disabled */
50
+ return;
51
+ }
52
+
53
+ switch (FIELD_EX64(wcr, DBGWCR, LSC)) {
54
+ case 0:
55
+ /* LSC 00 is reserved and must behave as if the wp is disabled */
56
+ return;
57
+ case 1:
58
+ flags |= BP_MEM_READ;
59
+ break;
60
+ case 2:
61
+ flags |= BP_MEM_WRITE;
62
+ break;
63
+ case 3:
64
+ flags |= BP_MEM_ACCESS;
65
+ break;
66
+ }
67
+
68
+ /*
69
+ * Attempts to use both MASK and BAS fields simultaneously are
70
+ * CONSTRAINED UNPREDICTABLE; we opt to ignore BAS in this case,
71
+ * thus generating a watchpoint for every byte in the masked region.
72
+ */
73
+ mask = FIELD_EX64(wcr, DBGWCR, MASK);
74
+ if (mask == 1 || mask == 2) {
75
+ /*
76
+ * Reserved values of MASK; we must act as if the mask value was
77
+ * some non-reserved value, or as if the watchpoint were disabled.
78
+ * We choose the latter.
79
+ */
80
+ return;
81
+ } else if (mask) {
82
+ /* Watchpoint covers an aligned area up to 2GB in size */
83
+ len = 1ULL << mask;
84
+ /*
85
+ * If masked bits in WVR are not zero it's CONSTRAINED UNPREDICTABLE
86
+ * whether the watchpoint fires when the unmasked bits match; we opt
87
+ * to generate the exceptions.
88
+ */
89
+ wvr &= ~(len - 1);
90
+ } else {
91
+ /* Watchpoint covers bytes defined by the byte address select bits */
92
+ int bas = FIELD_EX64(wcr, DBGWCR, BAS);
93
+ int basstart;
94
+
95
+ if (extract64(wvr, 2, 1)) {
96
+ /*
97
+ * Deprecated case of an only 4-aligned address. BAS[7:4] are
98
+ * ignored, and BAS[3:0] define which bytes to watch.
99
+ */
100
+ bas &= 0xf;
101
+ }
102
+
103
+ if (bas == 0) {
104
+ /* This must act as if the watchpoint is disabled */
105
+ return;
106
+ }
107
+
108
+ /*
109
+ * The BAS bits are supposed to be programmed to indicate a contiguous
110
+ * range of bytes. Otherwise it is CONSTRAINED UNPREDICTABLE whether
111
+ * we fire for each byte in the word/doubleword addressed by the WVR.
112
+ * We choose to ignore any non-zero bits after the first range of 1s.
113
+ */
114
+ basstart = ctz32(bas);
115
+ len = cto32(bas >> basstart);
116
+ wvr += basstart;
117
+ }
118
+
119
+ cpu_watchpoint_insert(CPU(cpu), wvr, len, flags,
120
+ &env->cpu_watchpoint[n]);
121
+}
122
+
123
+void hw_watchpoint_update_all(ARMCPU *cpu)
124
+{
43
+ int i;
125
+ int i;
44
+
126
+ CPUARMState *env = &cpu->env;
45
+ for (i = 0; i < NUM_TIMERS; i++) {
127
+
46
+ struct Msf2Timer *st = &t->timers[i];
128
+ /*
47
+
129
+ * Completely clear out existing QEMU watchpoints and our array, to
48
+ ptimer_free(st->ptimer);
130
+ * avoid possible stale entries following migration load.
131
+ */
132
+ cpu_watchpoint_remove_all(CPU(cpu), BP_CPU);
133
+ memset(env->cpu_watchpoint, 0, sizeof(env->cpu_watchpoint));
134
+
135
+ for (i = 0; i < ARRAY_SIZE(cpu->env.cpu_watchpoint); i++) {
136
+ hw_watchpoint_update(cpu, i);
49
+ }
137
+ }
50
+}
138
+}
51
+
139
+
52
static const VMStateDescription vmstate_timers = {
140
+void hw_breakpoint_update(ARMCPU *cpu, int n)
53
.name = "mss-timer-block",
141
+{
54
.version_id = 1,
142
+ CPUARMState *env = &cpu->env;
55
@@ -XXX,XX +XXX,XX @@ static const TypeInfo mss_timer_info = {
143
+ uint64_t bvr = env->cp15.dbgbvr[n];
56
.parent = TYPE_SYS_BUS_DEVICE,
144
+ uint64_t bcr = env->cp15.dbgbcr[n];
57
.instance_size = sizeof(MSSTimerState),
145
+ vaddr addr;
58
.instance_init = mss_timer_init,
146
+ int bt;
59
+ .instance_finalize = mss_timer_finalize,
147
+ int flags = BP_CPU;
60
.class_init = mss_timer_class_init,
148
+
149
+ if (env->cpu_breakpoint[n]) {
150
+ cpu_breakpoint_remove_by_ref(CPU(cpu), env->cpu_breakpoint[n]);
151
+ env->cpu_breakpoint[n] = NULL;
152
+ }
153
+
154
+ if (!extract64(bcr, 0, 1)) {
155
+ /* E bit clear : watchpoint disabled */
156
+ return;
157
+ }
158
+
159
+ bt = extract64(bcr, 20, 4);
160
+
161
+ switch (bt) {
162
+ case 4: /* unlinked address mismatch (reserved if AArch64) */
163
+ case 5: /* linked address mismatch (reserved if AArch64) */
164
+ qemu_log_mask(LOG_UNIMP,
165
+ "arm: address mismatch breakpoint types not implemented\n");
166
+ return;
167
+ case 0: /* unlinked address match */
168
+ case 1: /* linked address match */
169
+ {
170
+ /*
171
+ * Bits [1:0] are RES0.
172
+ *
173
+ * It is IMPLEMENTATION DEFINED whether bits [63:49]
174
+ * ([63:53] for FEAT_LVA) are hardwired to a copy of the sign bit
175
+ * of the VA field ([48] or [52] for FEAT_LVA), or whether the
176
+ * value is read as written. It is CONSTRAINED UNPREDICTABLE
177
+ * whether the RESS bits are ignored when comparing an address.
178
+ * Therefore we are allowed to compare the entire register, which
179
+ * lets us avoid considering whether FEAT_LVA is actually enabled.
180
+ *
181
+ * The BAS field is used to allow setting breakpoints on 16-bit
182
+ * wide instructions; it is CONSTRAINED UNPREDICTABLE whether
183
+ * a bp will fire if the addresses covered by the bp and the addresses
184
+ * covered by the insn overlap but the insn doesn't start at the
185
+ * start of the bp address range. We choose to require the insn and
186
+ * the bp to have the same address. The constraints on writing to
187
+ * BAS enforced in dbgbcr_write mean we have only four cases:
188
+ * 0b0000 => no breakpoint
189
+ * 0b0011 => breakpoint on addr
190
+ * 0b1100 => breakpoint on addr + 2
191
+ * 0b1111 => breakpoint on addr
192
+ * See also figure D2-3 in the v8 ARM ARM (DDI0487A.c).
193
+ */
194
+ int bas = extract64(bcr, 5, 4);
195
+ addr = bvr & ~3ULL;
196
+ if (bas == 0) {
197
+ return;
198
+ }
199
+ if (bas == 0xc) {
200
+ addr += 2;
201
+ }
202
+ break;
203
+ }
204
+ case 2: /* unlinked context ID match */
205
+ case 8: /* unlinked VMID match (reserved if no EL2) */
206
+ case 10: /* unlinked context ID and VMID match (reserved if no EL2) */
207
+ qemu_log_mask(LOG_UNIMP,
208
+ "arm: unlinked context breakpoint types not implemented\n");
209
+ return;
210
+ case 9: /* linked VMID match (reserved if no EL2) */
211
+ case 11: /* linked context ID and VMID match (reserved if no EL2) */
212
+ case 3: /* linked context ID match */
213
+ default:
214
+ /*
215
+ * We must generate no events for Linked context matches (unless
216
+ * they are linked to by some other bp/wp, which is handled in
217
+ * updates for the linking bp/wp). We choose to also generate no events
218
+ * for reserved values.
219
+ */
220
+ return;
221
+ }
222
+
223
+ cpu_breakpoint_insert(CPU(cpu), addr, flags, &env->cpu_breakpoint[n]);
224
+}
225
+
226
+void hw_breakpoint_update_all(ARMCPU *cpu)
227
+{
228
+ int i;
229
+ CPUARMState *env = &cpu->env;
230
+
231
+ /*
232
+ * Completely clear out existing QEMU breakpoints and our array, to
233
+ * avoid possible stale entries following migration load.
234
+ */
235
+ cpu_breakpoint_remove_all(CPU(cpu), BP_CPU);
236
+ memset(env->cpu_breakpoint, 0, sizeof(env->cpu_breakpoint));
237
+
238
+ for (i = 0; i < ARRAY_SIZE(cpu->env.cpu_breakpoint); i++) {
239
+ hw_breakpoint_update(cpu, i);
240
+ }
241
+}
242
+
243
+#if !defined(CONFIG_USER_ONLY)
244
+
245
+vaddr arm_adjust_watchpoint_address(CPUState *cs, vaddr addr, int len)
246
+{
247
+ ARMCPU *cpu = ARM_CPU(cs);
248
+ CPUARMState *env = &cpu->env;
249
+
250
+ /*
251
+ * In BE32 system mode, target memory is stored byteswapped (on a
252
+ * little-endian host system), and by the time we reach here (via an
253
+ * opcode helper) the addresses of subword accesses have been adjusted
254
+ * to account for that, which means that watchpoints will not match.
255
+ * Undo the adjustment here.
256
+ */
257
+ if (arm_sctlr_b(env)) {
258
+ if (len == 1) {
259
+ addr ^= 3;
260
+ } else if (len == 2) {
261
+ addr ^= 2;
262
+ }
263
+ }
264
+
265
+ return addr;
266
+}
267
+
268
+#endif /* !CONFIG_USER_ONLY */
269
+#endif /* CONFIG_TCG */
270
+
271
/*
272
* Check for traps to "powerdown debug" registers, which are controlled
273
* by MDCR.TDOSA
274
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo debug_lpae_cp_reginfo[] = {
275
.access = PL0_R, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
61
};
276
};
62
277
278
-void hw_watchpoint_update(ARMCPU *cpu, int n)
279
-{
280
- CPUARMState *env = &cpu->env;
281
- vaddr len = 0;
282
- vaddr wvr = env->cp15.dbgwvr[n];
283
- uint64_t wcr = env->cp15.dbgwcr[n];
284
- int mask;
285
- int flags = BP_CPU | BP_STOP_BEFORE_ACCESS;
286
-
287
- if (env->cpu_watchpoint[n]) {
288
- cpu_watchpoint_remove_by_ref(CPU(cpu), env->cpu_watchpoint[n]);
289
- env->cpu_watchpoint[n] = NULL;
290
- }
291
-
292
- if (!FIELD_EX64(wcr, DBGWCR, E)) {
293
- /* E bit clear : watchpoint disabled */
294
- return;
295
- }
296
-
297
- switch (FIELD_EX64(wcr, DBGWCR, LSC)) {
298
- case 0:
299
- /* LSC 00 is reserved and must behave as if the wp is disabled */
300
- return;
301
- case 1:
302
- flags |= BP_MEM_READ;
303
- break;
304
- case 2:
305
- flags |= BP_MEM_WRITE;
306
- break;
307
- case 3:
308
- flags |= BP_MEM_ACCESS;
309
- break;
310
- }
311
-
312
- /*
313
- * Attempts to use both MASK and BAS fields simultaneously are
314
- * CONSTRAINED UNPREDICTABLE; we opt to ignore BAS in this case,
315
- * thus generating a watchpoint for every byte in the masked region.
316
- */
317
- mask = FIELD_EX64(wcr, DBGWCR, MASK);
318
- if (mask == 1 || mask == 2) {
319
- /*
320
- * Reserved values of MASK; we must act as if the mask value was
321
- * some non-reserved value, or as if the watchpoint were disabled.
322
- * We choose the latter.
323
- */
324
- return;
325
- } else if (mask) {
326
- /* Watchpoint covers an aligned area up to 2GB in size */
327
- len = 1ULL << mask;
328
- /*
329
- * If masked bits in WVR are not zero it's CONSTRAINED UNPREDICTABLE
330
- * whether the watchpoint fires when the unmasked bits match; we opt
331
- * to generate the exceptions.
332
- */
333
- wvr &= ~(len - 1);
334
- } else {
335
- /* Watchpoint covers bytes defined by the byte address select bits */
336
- int bas = FIELD_EX64(wcr, DBGWCR, BAS);
337
- int basstart;
338
-
339
- if (extract64(wvr, 2, 1)) {
340
- /*
341
- * Deprecated case of an only 4-aligned address. BAS[7:4] are
342
- * ignored, and BAS[3:0] define which bytes to watch.
343
- */
344
- bas &= 0xf;
345
- }
346
-
347
- if (bas == 0) {
348
- /* This must act as if the watchpoint is disabled */
349
- return;
350
- }
351
-
352
- /*
353
- * The BAS bits are supposed to be programmed to indicate a contiguous
354
- * range of bytes. Otherwise it is CONSTRAINED UNPREDICTABLE whether
355
- * we fire for each byte in the word/doubleword addressed by the WVR.
356
- * We choose to ignore any non-zero bits after the first range of 1s.
357
- */
358
- basstart = ctz32(bas);
359
- len = cto32(bas >> basstart);
360
- wvr += basstart;
361
- }
362
-
363
- cpu_watchpoint_insert(CPU(cpu), wvr, len, flags,
364
- &env->cpu_watchpoint[n]);
365
-}
366
-
367
-void hw_watchpoint_update_all(ARMCPU *cpu)
368
-{
369
- int i;
370
- CPUARMState *env = &cpu->env;
371
-
372
- /*
373
- * Completely clear out existing QEMU watchpoints and our array, to
374
- * avoid possible stale entries following migration load.
375
- */
376
- cpu_watchpoint_remove_all(CPU(cpu), BP_CPU);
377
- memset(env->cpu_watchpoint, 0, sizeof(env->cpu_watchpoint));
378
-
379
- for (i = 0; i < ARRAY_SIZE(cpu->env.cpu_watchpoint); i++) {
380
- hw_watchpoint_update(cpu, i);
381
- }
382
-}
383
-
384
static void dbgwvr_write(CPUARMState *env, const ARMCPRegInfo *ri,
385
uint64_t value)
386
{
387
@@ -XXX,XX +XXX,XX @@ static void dbgwcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
388
}
389
}
390
391
-void hw_breakpoint_update(ARMCPU *cpu, int n)
392
-{
393
- CPUARMState *env = &cpu->env;
394
- uint64_t bvr = env->cp15.dbgbvr[n];
395
- uint64_t bcr = env->cp15.dbgbcr[n];
396
- vaddr addr;
397
- int bt;
398
- int flags = BP_CPU;
399
-
400
- if (env->cpu_breakpoint[n]) {
401
- cpu_breakpoint_remove_by_ref(CPU(cpu), env->cpu_breakpoint[n]);
402
- env->cpu_breakpoint[n] = NULL;
403
- }
404
-
405
- if (!extract64(bcr, 0, 1)) {
406
- /* E bit clear : watchpoint disabled */
407
- return;
408
- }
409
-
410
- bt = extract64(bcr, 20, 4);
411
-
412
- switch (bt) {
413
- case 4: /* unlinked address mismatch (reserved if AArch64) */
414
- case 5: /* linked address mismatch (reserved if AArch64) */
415
- qemu_log_mask(LOG_UNIMP,
416
- "arm: address mismatch breakpoint types not implemented\n");
417
- return;
418
- case 0: /* unlinked address match */
419
- case 1: /* linked address match */
420
- {
421
- /*
422
- * Bits [1:0] are RES0.
423
- *
424
- * It is IMPLEMENTATION DEFINED whether bits [63:49]
425
- * ([63:53] for FEAT_LVA) are hardwired to a copy of the sign bit
426
- * of the VA field ([48] or [52] for FEAT_LVA), or whether the
427
- * value is read as written. It is CONSTRAINED UNPREDICTABLE
428
- * whether the RESS bits are ignored when comparing an address.
429
- * Therefore we are allowed to compare the entire register, which
430
- * lets us avoid considering whether FEAT_LVA is actually enabled.
431
- *
432
- * The BAS field is used to allow setting breakpoints on 16-bit
433
- * wide instructions; it is CONSTRAINED UNPREDICTABLE whether
434
- * a bp will fire if the addresses covered by the bp and the addresses
435
- * covered by the insn overlap but the insn doesn't start at the
436
- * start of the bp address range. We choose to require the insn and
437
- * the bp to have the same address. The constraints on writing to
438
- * BAS enforced in dbgbcr_write mean we have only four cases:
439
- * 0b0000 => no breakpoint
440
- * 0b0011 => breakpoint on addr
441
- * 0b1100 => breakpoint on addr + 2
442
- * 0b1111 => breakpoint on addr
443
- * See also figure D2-3 in the v8 ARM ARM (DDI0487A.c).
444
- */
445
- int bas = extract64(bcr, 5, 4);
446
- addr = bvr & ~3ULL;
447
- if (bas == 0) {
448
- return;
449
- }
450
- if (bas == 0xc) {
451
- addr += 2;
452
- }
453
- break;
454
- }
455
- case 2: /* unlinked context ID match */
456
- case 8: /* unlinked VMID match (reserved if no EL2) */
457
- case 10: /* unlinked context ID and VMID match (reserved if no EL2) */
458
- qemu_log_mask(LOG_UNIMP,
459
- "arm: unlinked context breakpoint types not implemented\n");
460
- return;
461
- case 9: /* linked VMID match (reserved if no EL2) */
462
- case 11: /* linked context ID and VMID match (reserved if no EL2) */
463
- case 3: /* linked context ID match */
464
- default:
465
- /*
466
- * We must generate no events for Linked context matches (unless
467
- * they are linked to by some other bp/wp, which is handled in
468
- * updates for the linking bp/wp). We choose to also generate no events
469
- * for reserved values.
470
- */
471
- return;
472
- }
473
-
474
- cpu_breakpoint_insert(CPU(cpu), addr, flags, &env->cpu_breakpoint[n]);
475
-}
476
-
477
-void hw_breakpoint_update_all(ARMCPU *cpu)
478
-{
479
- int i;
480
- CPUARMState *env = &cpu->env;
481
-
482
- /*
483
- * Completely clear out existing QEMU breakpoints and our array, to
484
- * avoid possible stale entries following migration load.
485
- */
486
- cpu_breakpoint_remove_all(CPU(cpu), BP_CPU);
487
- memset(env->cpu_breakpoint, 0, sizeof(env->cpu_breakpoint));
488
-
489
- for (i = 0; i < ARRAY_SIZE(cpu->env.cpu_breakpoint); i++) {
490
- hw_breakpoint_update(cpu, i);
491
- }
492
-}
493
-
494
static void dbgbvr_write(CPUARMState *env, const ARMCPRegInfo *ri,
495
uint64_t value)
496
{
497
@@ -XXX,XX +XXX,XX @@ void define_debug_regs(ARMCPU *cpu)
498
g_free(dbgwcr_el1_name);
499
}
500
}
501
-
502
-#if !defined(CONFIG_USER_ONLY)
503
-
504
-vaddr arm_adjust_watchpoint_address(CPUState *cs, vaddr addr, int len)
505
-{
506
- ARMCPU *cpu = ARM_CPU(cs);
507
- CPUARMState *env = &cpu->env;
508
-
509
- /*
510
- * In BE32 system mode, target memory is stored byteswapped (on a
511
- * little-endian host system), and by the time we reach here (via an
512
- * opcode helper) the addresses of subword accesses have been adjusted
513
- * to account for that, which means that watchpoints will not match.
514
- * Undo the adjustment here.
515
- */
516
- if (arm_sctlr_b(env)) {
517
- if (len == 1) {
518
- addr ^= 3;
519
- } else if (len == 2) {
520
- addr ^= 2;
521
- }
522
- }
523
-
524
- return addr;
525
-}
526
-
527
-#endif
63
--
528
--
64
2.20.1
529
2.34.1
65
66
diff view generated by jsdifflib
New patch
1
1
From: Fabiano Rosas <farosas@suse.de>
2
3
Introduce the target/arm/tcg directory. Its purpose is to hold the TCG
4
code that is selected by CONFIG_TCG.
5
6
Signed-off-by: Claudio Fontana <cfontana@suse.de>
7
Signed-off-by: Fabiano Rosas <farosas@suse.de>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
10
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
11
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
14
MAINTAINERS | 1 +
15
target/arm/{ => tcg}/translate-a64.h | 0
16
target/arm/{ => tcg}/translate.h | 0
17
target/arm/{ => tcg}/a32-uncond.decode | 0
18
target/arm/{ => tcg}/a32.decode | 0
19
target/arm/{ => tcg}/m-nocp.decode | 0
20
target/arm/{ => tcg}/mve.decode | 0
21
target/arm/{ => tcg}/neon-dp.decode | 0
22
target/arm/{ => tcg}/neon-ls.decode | 0
23
target/arm/{ => tcg}/neon-shared.decode | 0
24
target/arm/{ => tcg}/sme-fa64.decode | 0
25
target/arm/{ => tcg}/sme.decode | 0
26
target/arm/{ => tcg}/sve.decode | 0
27
target/arm/{ => tcg}/t16.decode | 0
28
target/arm/{ => tcg}/t32.decode | 0
29
target/arm/{ => tcg}/vfp-uncond.decode | 0
30
target/arm/{ => tcg}/vfp.decode | 0
31
target/arm/{ => tcg}/translate-a64.c | 0
32
target/arm/{ => tcg}/translate-m-nocp.c | 0
33
target/arm/{ => tcg}/translate-mve.c | 0
34
target/arm/{ => tcg}/translate-neon.c | 0
35
target/arm/{ => tcg}/translate-sme.c | 0
36
target/arm/{ => tcg}/translate-sve.c | 0
37
target/arm/{ => tcg}/translate-vfp.c | 0
38
target/arm/{ => tcg}/translate.c | 0
39
target/arm/meson.build | 30 +++---------------
40
target/arm/{ => tcg}/meson.build | 41 +------------------------
41
27 files changed, 6 insertions(+), 66 deletions(-)
42
rename target/arm/{ => tcg}/translate-a64.h (100%)
43
rename target/arm/{ => tcg}/translate.h (100%)
44
rename target/arm/{ => tcg}/a32-uncond.decode (100%)
45
rename target/arm/{ => tcg}/a32.decode (100%)
46
rename target/arm/{ => tcg}/m-nocp.decode (100%)
47
rename target/arm/{ => tcg}/mve.decode (100%)
48
rename target/arm/{ => tcg}/neon-dp.decode (100%)
49
rename target/arm/{ => tcg}/neon-ls.decode (100%)
50
rename target/arm/{ => tcg}/neon-shared.decode (100%)
51
rename target/arm/{ => tcg}/sme-fa64.decode (100%)
52
rename target/arm/{ => tcg}/sme.decode (100%)
53
rename target/arm/{ => tcg}/sve.decode (100%)
54
rename target/arm/{ => tcg}/t16.decode (100%)
55
rename target/arm/{ => tcg}/t32.decode (100%)
56
rename target/arm/{ => tcg}/vfp-uncond.decode (100%)
57
rename target/arm/{ => tcg}/vfp.decode (100%)
58
rename target/arm/{ => tcg}/translate-a64.c (100%)
59
rename target/arm/{ => tcg}/translate-m-nocp.c (100%)
60
rename target/arm/{ => tcg}/translate-mve.c (100%)
61
rename target/arm/{ => tcg}/translate-neon.c (100%)
62
rename target/arm/{ => tcg}/translate-sme.c (100%)
63
rename target/arm/{ => tcg}/translate-sve.c (100%)
64
rename target/arm/{ => tcg}/translate-vfp.c (100%)
65
rename target/arm/{ => tcg}/translate.c (100%)
66
copy target/arm/{ => tcg}/meson.build (64%)
67
68
diff --git a/MAINTAINERS b/MAINTAINERS
69
index XXXXXXX..XXXXXXX 100644
70
--- a/MAINTAINERS
71
+++ b/MAINTAINERS
72
@@ -XXX,XX +XXX,XX @@ M: Peter Maydell <peter.maydell@linaro.org>
73
L: qemu-arm@nongnu.org
74
S: Maintained
75
F: target/arm/
76
+F: target/arm/tcg/
77
F: tests/tcg/arm/
78
F: tests/tcg/aarch64/
79
F: tests/qtest/arm-cpu-features.c
80
diff --git a/target/arm/translate-a64.h b/target/arm/tcg/translate-a64.h
81
similarity index 100%
82
rename from target/arm/translate-a64.h
83
rename to target/arm/tcg/translate-a64.h
84
diff --git a/target/arm/translate.h b/target/arm/tcg/translate.h
85
similarity index 100%
86
rename from target/arm/translate.h
87
rename to target/arm/tcg/translate.h
88
diff --git a/target/arm/a32-uncond.decode b/target/arm/tcg/a32-uncond.decode
89
similarity index 100%
90
rename from target/arm/a32-uncond.decode
91
rename to target/arm/tcg/a32-uncond.decode
92
diff --git a/target/arm/a32.decode b/target/arm/tcg/a32.decode
93
similarity index 100%
94
rename from target/arm/a32.decode
95
rename to target/arm/tcg/a32.decode
96
diff --git a/target/arm/m-nocp.decode b/target/arm/tcg/m-nocp.decode
97
similarity index 100%
98
rename from target/arm/m-nocp.decode
99
rename to target/arm/tcg/m-nocp.decode
100
diff --git a/target/arm/mve.decode b/target/arm/tcg/mve.decode
101
similarity index 100%
102
rename from target/arm/mve.decode
103
rename to target/arm/tcg/mve.decode
104
diff --git a/target/arm/neon-dp.decode b/target/arm/tcg/neon-dp.decode
105
similarity index 100%
106
rename from target/arm/neon-dp.decode
107
rename to target/arm/tcg/neon-dp.decode
108
diff --git a/target/arm/neon-ls.decode b/target/arm/tcg/neon-ls.decode
109
similarity index 100%
110
rename from target/arm/neon-ls.decode
111
rename to target/arm/tcg/neon-ls.decode
112
diff --git a/target/arm/neon-shared.decode b/target/arm/tcg/neon-shared.decode
113
similarity index 100%
114
rename from target/arm/neon-shared.decode
115
rename to target/arm/tcg/neon-shared.decode
116
diff --git a/target/arm/sme-fa64.decode b/target/arm/tcg/sme-fa64.decode
117
similarity index 100%
118
rename from target/arm/sme-fa64.decode
119
rename to target/arm/tcg/sme-fa64.decode
120
diff --git a/target/arm/sme.decode b/target/arm/tcg/sme.decode
121
similarity index 100%
122
rename from target/arm/sme.decode
123
rename to target/arm/tcg/sme.decode
124
diff --git a/target/arm/sve.decode b/target/arm/tcg/sve.decode
125
similarity index 100%
126
rename from target/arm/sve.decode
127
rename to target/arm/tcg/sve.decode
128
diff --git a/target/arm/t16.decode b/target/arm/tcg/t16.decode
129
similarity index 100%
130
rename from target/arm/t16.decode
131
rename to target/arm/tcg/t16.decode
132
diff --git a/target/arm/t32.decode b/target/arm/tcg/t32.decode
133
similarity index 100%
134
rename from target/arm/t32.decode
135
rename to target/arm/tcg/t32.decode
136
diff --git a/target/arm/vfp-uncond.decode b/target/arm/tcg/vfp-uncond.decode
137
similarity index 100%
138
rename from target/arm/vfp-uncond.decode
139
rename to target/arm/tcg/vfp-uncond.decode
140
diff --git a/target/arm/vfp.decode b/target/arm/tcg/vfp.decode
141
similarity index 100%
142
rename from target/arm/vfp.decode
143
rename to target/arm/tcg/vfp.decode
144
diff --git a/target/arm/translate-a64.c b/target/arm/tcg/translate-a64.c
145
similarity index 100%
146
rename from target/arm/translate-a64.c
147
rename to target/arm/tcg/translate-a64.c
148
diff --git a/target/arm/translate-m-nocp.c b/target/arm/tcg/translate-m-nocp.c
149
similarity index 100%
150
rename from target/arm/translate-m-nocp.c
151
rename to target/arm/tcg/translate-m-nocp.c
152
diff --git a/target/arm/translate-mve.c b/target/arm/tcg/translate-mve.c
153
similarity index 100%
154
rename from target/arm/translate-mve.c
155
rename to target/arm/tcg/translate-mve.c
156
diff --git a/target/arm/translate-neon.c b/target/arm/tcg/translate-neon.c
157
similarity index 100%
158
rename from target/arm/translate-neon.c
159
rename to target/arm/tcg/translate-neon.c
160
diff --git a/target/arm/translate-sme.c b/target/arm/tcg/translate-sme.c
161
similarity index 100%
162
rename from target/arm/translate-sme.c
163
rename to target/arm/tcg/translate-sme.c
164
diff --git a/target/arm/translate-sve.c b/target/arm/tcg/translate-sve.c
165
similarity index 100%
166
rename from target/arm/translate-sve.c
167
rename to target/arm/tcg/translate-sve.c
168
diff --git a/target/arm/translate-vfp.c b/target/arm/tcg/translate-vfp.c
169
similarity index 100%
170
rename from target/arm/translate-vfp.c
171
rename to target/arm/tcg/translate-vfp.c
172
diff --git a/target/arm/translate.c b/target/arm/tcg/translate.c
173
similarity index 100%
174
rename from target/arm/translate.c
175
rename to target/arm/tcg/translate.c
176
diff --git a/target/arm/meson.build b/target/arm/meson.build
177
index XXXXXXX..XXXXXXX 100644
178
--- a/target/arm/meson.build
179
+++ b/target/arm/meson.build
180
@@ -XXX,XX +XXX,XX @@
181
-gen = [
182
- decodetree.process('sve.decode', extra_args: '--decode=disas_sve'),
183
- decodetree.process('sme.decode', extra_args: '--decode=disas_sme'),
184
- decodetree.process('sme-fa64.decode', extra_args: '--static-decode=disas_sme_fa64'),
185
- decodetree.process('neon-shared.decode', extra_args: '--decode=disas_neon_shared'),
186
- decodetree.process('neon-dp.decode', extra_args: '--decode=disas_neon_dp'),
187
- decodetree.process('neon-ls.decode', extra_args: '--decode=disas_neon_ls'),
188
- decodetree.process('vfp.decode', extra_args: '--decode=disas_vfp'),
189
- decodetree.process('vfp-uncond.decode', extra_args: '--decode=disas_vfp_uncond'),
190
- decodetree.process('m-nocp.decode', extra_args: '--decode=disas_m_nocp'),
191
- decodetree.process('mve.decode', extra_args: '--decode=disas_mve'),
192
- decodetree.process('a32.decode', extra_args: '--static-decode=disas_a32'),
193
- decodetree.process('a32-uncond.decode', extra_args: '--static-decode=disas_a32_uncond'),
194
- decodetree.process('t32.decode', extra_args: '--static-decode=disas_t32'),
195
- decodetree.process('t16.decode', extra_args: ['-w', '16', '--static-decode=disas_t16']),
196
-]
197
-
198
arm_ss = ss.source_set()
199
-arm_ss.add(gen)
200
arm_ss.add(files(
201
'cpu.c',
202
'crypto_helper.c',
203
@@ -XXX,XX +XXX,XX @@ arm_ss.add(files(
204
'neon_helper.c',
205
'op_helper.c',
206
'tlb_helper.c',
207
- 'translate.c',
208
- 'translate-m-nocp.c',
209
- 'translate-mve.c',
210
- 'translate-neon.c',
211
- 'translate-vfp.c',
212
'vec_helper.c',
213
'vfp_helper.c',
214
'cpu_tcg.c',
215
@@ -XXX,XX +XXX,XX @@ arm_ss.add(when: 'TARGET_AARCH64', if_true: files(
216
'pauth_helper.c',
217
'sve_helper.c',
218
'sme_helper.c',
219
- 'translate-a64.c',
220
- 'translate-sve.c',
221
- 'translate-sme.c',
222
))
223
224
arm_softmmu_ss = ss.source_set()
225
@@ -XXX,XX +XXX,XX @@ arm_softmmu_ss.add(files(
226
227
subdir('hvf')
228
229
+if 'CONFIG_TCG' in config_all
230
+ subdir('tcg')
231
+endif
232
+
233
target_arch += {'arm': arm_ss}
234
target_softmmu_arch += {'arm': arm_softmmu_ss}
235
diff --git a/target/arm/meson.build b/target/arm/tcg/meson.build
236
similarity index 64%
237
copy from target/arm/meson.build
238
copy to target/arm/tcg/meson.build
239
index XXXXXXX..XXXXXXX 100644
240
--- a/target/arm/meson.build
241
+++ b/target/arm/tcg/meson.build
242
@@ -XXX,XX +XXX,XX @@ gen = [
243
decodetree.process('t16.decode', extra_args: ['-w', '16', '--static-decode=disas_t16']),
244
]
245
246
-arm_ss = ss.source_set()
247
arm_ss.add(gen)
248
+
249
arm_ss.add(files(
250
- 'cpu.c',
251
- 'crypto_helper.c',
252
- 'debug_helper.c',
253
- 'gdbstub.c',
254
- 'helper.c',
255
- 'iwmmxt_helper.c',
256
- 'm_helper.c',
257
- 'mve_helper.c',
258
- 'neon_helper.c',
259
- 'op_helper.c',
260
- 'tlb_helper.c',
261
'translate.c',
262
'translate-m-nocp.c',
263
'translate-mve.c',
264
'translate-neon.c',
265
'translate-vfp.c',
266
- 'vec_helper.c',
267
- 'vfp_helper.c',
268
- 'cpu_tcg.c',
269
))
270
-arm_ss.add(zlib)
271
-
272
-arm_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c', 'kvm64.c'), if_false: files('kvm-stub.c'))
273
274
arm_ss.add(when: 'TARGET_AARCH64', if_true: files(
275
- 'cpu64.c',
276
- 'gdbstub64.c',
277
- 'helper-a64.c',
278
- 'mte_helper.c',
279
- 'pauth_helper.c',
280
- 'sve_helper.c',
281
- 'sme_helper.c',
282
'translate-a64.c',
283
'translate-sve.c',
284
'translate-sme.c',
285
))
286
-
287
-arm_softmmu_ss = ss.source_set()
288
-arm_softmmu_ss.add(files(
289
- 'arch_dump.c',
290
- 'arm-powerctl.c',
291
- 'machine.c',
292
- 'monitor.c',
293
- 'psci.c',
294
- 'ptw.c',
295
-))
296
-
297
-subdir('hvf')
298
-
299
-target_arch += {'arm': arm_ss}
300
-target_softmmu_arch += {'arm': arm_softmmu_ss}
301
--
302
2.34.1
303
304
diff view generated by jsdifflib
1
From: Bin Meng <bin.meng@windriver.com>
1
From: Claudio Fontana <cfontana@suse.de>
2
2
3
This adds the target guide for SABRE Lite board, and documents how
3
Signed-off-by: Claudio Fontana <cfontana@suse.de>
4
to boot a Linux kernel and U-Boot bootloader.
4
Signed-off-by: Fabiano Rosas <farosas@suse.de>
5
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Signed-off-by: Bin Meng <bin.meng@windriver.com>
6
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
7
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
7
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
8
Message-id: 20210106063504.10841-5-bmeng.cn@gmail.com
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
9
---
11
docs/system/arm/sabrelite.rst | 119 ++++++++++++++++++++++++++++++++++
10
target/arm/{ => tcg}/vec_internal.h | 0
12
docs/system/target-arm.rst | 1 +
11
target/arm/tcg-stubs.c | 23 +++++++++++++++++++++++
13
2 files changed, 120 insertions(+)
12
target/arm/{ => tcg}/crypto_helper.c | 0
14
create mode 100644 docs/system/arm/sabrelite.rst
13
target/arm/{ => tcg}/helper-a64.c | 0
15
14
target/arm/{ => tcg}/iwmmxt_helper.c | 0
16
diff --git a/docs/system/arm/sabrelite.rst b/docs/system/arm/sabrelite.rst
15
target/arm/{ => tcg}/m_helper.c | 0
16
target/arm/{ => tcg}/mte_helper.c | 0
17
target/arm/{ => tcg}/mve_helper.c | 0
18
target/arm/{ => tcg}/neon_helper.c | 0
19
target/arm/{ => tcg}/op_helper.c | 0
20
target/arm/{ => tcg}/pauth_helper.c | 0
21
target/arm/{ => tcg}/sme_helper.c | 0
22
target/arm/{ => tcg}/sve_helper.c | 0
23
target/arm/{ => tcg}/tlb_helper.c | 0
24
target/arm/{ => tcg}/vec_helper.c | 0
25
target/arm/meson.build | 15 ++-------------
26
target/arm/tcg/meson.build | 13 +++++++++++++
27
17 files changed, 38 insertions(+), 13 deletions(-)
28
rename target/arm/{ => tcg}/vec_internal.h (100%)
29
create mode 100644 target/arm/tcg-stubs.c
30
rename target/arm/{ => tcg}/crypto_helper.c (100%)
31
rename target/arm/{ => tcg}/helper-a64.c (100%)
32
rename target/arm/{ => tcg}/iwmmxt_helper.c (100%)
33
rename target/arm/{ => tcg}/m_helper.c (100%)
34
rename target/arm/{ => tcg}/mte_helper.c (100%)
35
rename target/arm/{ => tcg}/mve_helper.c (100%)
36
rename target/arm/{ => tcg}/neon_helper.c (100%)
37
rename target/arm/{ => tcg}/op_helper.c (100%)
38
rename target/arm/{ => tcg}/pauth_helper.c (100%)
39
rename target/arm/{ => tcg}/sme_helper.c (100%)
40
rename target/arm/{ => tcg}/sve_helper.c (100%)
41
rename target/arm/{ => tcg}/tlb_helper.c (100%)
42
rename target/arm/{ => tcg}/vec_helper.c (100%)
43
44
diff --git a/target/arm/vec_internal.h b/target/arm/tcg/vec_internal.h
45
similarity index 100%
46
rename from target/arm/vec_internal.h
47
rename to target/arm/tcg/vec_internal.h
48
diff --git a/target/arm/tcg-stubs.c b/target/arm/tcg-stubs.c
17
new file mode 100644
49
new file mode 100644
18
index XXXXXXX..XXXXXXX
50
index XXXXXXX..XXXXXXX
19
--- /dev/null
51
--- /dev/null
20
+++ b/docs/system/arm/sabrelite.rst
52
+++ b/target/arm/tcg-stubs.c
21
@@ -XXX,XX +XXX,XX @@
53
@@ -XXX,XX +XXX,XX @@
22
+Boundary Devices SABRE Lite (``sabrelite``)
54
+/*
23
+===========================================
55
+ * QEMU ARM stubs for some TCG helper functions
56
+ *
57
+ * Copyright 2021 SUSE LLC
58
+ *
59
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
60
+ * See the COPYING file in the top-level directory.
61
+ */
24
+
62
+
25
+Boundary Devices SABRE Lite i.MX6 Development Board is a low-cost development
63
+#include "qemu/osdep.h"
26
+platform featuring the powerful Freescale / NXP Semiconductor's i.MX 6 Quad
64
+#include "cpu.h"
27
+Applications Processor.
65
+#include "internals.h"
28
+
66
+
29
+Supported devices
67
+void write_v7m_exception(CPUARMState *env, uint32_t new_exc)
30
+-----------------
68
+{
69
+ g_assert_not_reached();
70
+}
31
+
71
+
32
+The SABRE Lite machine supports the following devices:
72
+void raise_exception_ra(CPUARMState *env, uint32_t excp, uint32_t syndrome,
33
+
73
+ uint32_t target_el, uintptr_t ra)
34
+ * Up to 4 Cortex A9 cores
74
+{
35
+ * Generic Interrupt Controller
75
+ g_assert_not_reached();
36
+ * 1 Clock Controller Module
76
+}
37
+ * 1 System Reset Controller
77
diff --git a/target/arm/crypto_helper.c b/target/arm/tcg/crypto_helper.c
38
+ * 5 UARTs
78
similarity index 100%
39
+ * 2 EPIC timers
79
rename from target/arm/crypto_helper.c
40
+ * 1 GPT timer
80
rename to target/arm/tcg/crypto_helper.c
41
+ * 2 Watchdog timers
81
diff --git a/target/arm/helper-a64.c b/target/arm/tcg/helper-a64.c
42
+ * 1 FEC Ethernet controller
82
similarity index 100%
43
+ * 3 I2C controllers
83
rename from target/arm/helper-a64.c
44
+ * 7 GPIO controllers
84
rename to target/arm/tcg/helper-a64.c
45
+ * 4 SDHC storage controllers
85
diff --git a/target/arm/iwmmxt_helper.c b/target/arm/tcg/iwmmxt_helper.c
46
+ * 4 USB 2.0 host controllers
86
similarity index 100%
47
+ * 5 ECSPI controllers
87
rename from target/arm/iwmmxt_helper.c
48
+ * 1 SST 25VF016B flash
88
rename to target/arm/tcg/iwmmxt_helper.c
49
+
89
diff --git a/target/arm/m_helper.c b/target/arm/tcg/m_helper.c
50
+Please note above list is a complete superset the QEMU SABRE Lite machine can
90
similarity index 100%
51
+support. For a normal use case, a device tree blob that represents a real world
91
rename from target/arm/m_helper.c
52
+SABRE Lite board, only exposes a subset of devices to the guest software.
92
rename to target/arm/tcg/m_helper.c
53
+
93
diff --git a/target/arm/mte_helper.c b/target/arm/tcg/mte_helper.c
54
+Boot options
94
similarity index 100%
55
+------------
95
rename from target/arm/mte_helper.c
56
+
96
rename to target/arm/tcg/mte_helper.c
57
+The SABRE Lite machine can start using the standard -kernel functionality
97
diff --git a/target/arm/mve_helper.c b/target/arm/tcg/mve_helper.c
58
+for loading a Linux kernel, U-Boot bootloader or ELF executable.
98
similarity index 100%
59
+
99
rename from target/arm/mve_helper.c
60
+Running Linux kernel
100
rename to target/arm/tcg/mve_helper.c
61
+--------------------
101
diff --git a/target/arm/neon_helper.c b/target/arm/tcg/neon_helper.c
62
+
102
similarity index 100%
63
+Linux mainline v5.10 release is tested at the time of writing. To build a Linux
103
rename from target/arm/neon_helper.c
64
+mainline kernel that can be booted by the SABRE Lite machine, simply configure
104
rename to target/arm/tcg/neon_helper.c
65
+the kernel using the imx_v6_v7_defconfig configuration:
105
diff --git a/target/arm/op_helper.c b/target/arm/tcg/op_helper.c
66
+
106
similarity index 100%
67
+.. code-block:: bash
107
rename from target/arm/op_helper.c
68
+
108
rename to target/arm/tcg/op_helper.c
69
+ $ export ARCH=arm
109
diff --git a/target/arm/pauth_helper.c b/target/arm/tcg/pauth_helper.c
70
+ $ export CROSS_COMPILE=arm-linux-gnueabihf-
110
similarity index 100%
71
+ $ make imx_v6_v7_defconfig
111
rename from target/arm/pauth_helper.c
72
+ $ make
112
rename to target/arm/tcg/pauth_helper.c
73
+
113
diff --git a/target/arm/sme_helper.c b/target/arm/tcg/sme_helper.c
74
+To boot the newly built Linux kernel in QEMU with the SABRE Lite machine, use:
114
similarity index 100%
75
+
115
rename from target/arm/sme_helper.c
76
+.. code-block:: bash
116
rename to target/arm/tcg/sme_helper.c
77
+
117
diff --git a/target/arm/sve_helper.c b/target/arm/tcg/sve_helper.c
78
+ $ qemu-system-arm -M sabrelite -smp 4 -m 1G \
118
similarity index 100%
79
+ -display none -serial null -serial stdio \
119
rename from target/arm/sve_helper.c
80
+ -kernel arch/arm/boot/zImage \
120
rename to target/arm/tcg/sve_helper.c
81
+ -dtb arch/arm/boot/dts/imx6q-sabrelite.dtb \
121
diff --git a/target/arm/tlb_helper.c b/target/arm/tcg/tlb_helper.c
82
+ -initrd /path/to/rootfs.ext4 \
122
similarity index 100%
83
+ -append "root=/dev/ram"
123
rename from target/arm/tlb_helper.c
84
+
124
rename to target/arm/tcg/tlb_helper.c
85
+Running U-Boot
125
diff --git a/target/arm/vec_helper.c b/target/arm/tcg/vec_helper.c
86
+--------------
126
similarity index 100%
87
+
127
rename from target/arm/vec_helper.c
88
+U-Boot mainline v2020.10 release is tested at the time of writing. To build a
128
rename to target/arm/tcg/vec_helper.c
89
+U-Boot mainline bootloader that can be booted by the SABRE Lite machine, use
129
diff --git a/target/arm/meson.build b/target/arm/meson.build
90
+the mx6qsabrelite_defconfig with similar commands as described above for Linux:
91
+
92
+.. code-block:: bash
93
+
94
+ $ export CROSS_COMPILE=arm-linux-gnueabihf-
95
+ $ make mx6qsabrelite_defconfig
96
+
97
+Note we need to adjust settings by:
98
+
99
+.. code-block:: bash
100
+
101
+ $ make menuconfig
102
+
103
+then manually select the following configuration in U-Boot:
104
+
105
+ Device Tree Control > Provider of DTB for DT Control > Embedded DTB
106
+
107
+To start U-Boot using the SABRE Lite machine, provide the u-boot binary to
108
+the -kernel argument, along with an SD card image with rootfs:
109
+
110
+.. code-block:: bash
111
+
112
+ $ qemu-system-arm -M sabrelite -smp 4 -m 1G \
113
+ -display none -serial null -serial stdio \
114
+ -kernel u-boot
115
+
116
+The following example shows booting Linux kernel from dhcp, and uses the
117
+rootfs on an SD card. This requires some additional command line parameters
118
+for QEMU:
119
+
120
+.. code-block:: none
121
+
122
+ -nic user,tftp=/path/to/kernel/zImage \
123
+ -drive file=sdcard.img,id=rootfs -device sd-card,drive=rootfs
124
+
125
+The directory for the built-in TFTP server should also contain the device tree
126
+blob of the SABRE Lite board. The sample SD card image was populated with the
127
+root file system with one single partition. You may adjust the kernel "root="
128
+boot parameter accordingly.
129
+
130
+After U-Boot boots, type the following commands in the U-Boot command shell to
131
+boot the Linux kernel:
132
+
133
+.. code-block:: none
134
+
135
+ => setenv ethaddr 00:11:22:33:44:55
136
+ => setenv bootfile zImage
137
+ => dhcp
138
+ => tftpboot 14000000 imx6q-sabrelite.dtb
139
+ => setenv bootargs root=/dev/mmcblk3p1
140
+ => bootz 12000000 - 14000000
141
diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst
142
index XXXXXXX..XXXXXXX 100644
130
index XXXXXXX..XXXXXXX 100644
143
--- a/docs/system/target-arm.rst
131
--- a/target/arm/meson.build
144
+++ b/docs/system/target-arm.rst
132
+++ b/target/arm/meson.build
145
@@ -XXX,XX +XXX,XX @@ undocumented; you can get a complete list by running
133
@@ -XXX,XX +XXX,XX @@
146
arm/versatile
134
arm_ss = ss.source_set()
147
arm/vexpress
135
arm_ss.add(files(
148
arm/aspeed
136
'cpu.c',
149
+ arm/sabrelite
137
- 'crypto_helper.c',
150
arm/digic
138
'debug_helper.c',
151
arm/musicpal
139
'gdbstub.c',
152
arm/gumstix
140
'helper.c',
141
- 'iwmmxt_helper.c',
142
- 'm_helper.c',
143
- 'mve_helper.c',
144
- 'neon_helper.c',
145
- 'op_helper.c',
146
- 'tlb_helper.c',
147
- 'vec_helper.c',
148
'vfp_helper.c',
149
'cpu_tcg.c',
150
))
151
@@ -XXX,XX +XXX,XX @@ arm_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c', 'kvm64.c'), if_false: fil
152
arm_ss.add(when: 'TARGET_AARCH64', if_true: files(
153
'cpu64.c',
154
'gdbstub64.c',
155
- 'helper-a64.c',
156
- 'mte_helper.c',
157
- 'pauth_helper.c',
158
- 'sve_helper.c',
159
- 'sme_helper.c',
160
))
161
162
arm_softmmu_ss = ss.source_set()
163
@@ -XXX,XX +XXX,XX @@ subdir('hvf')
164
165
if 'CONFIG_TCG' in config_all
166
subdir('tcg')
167
+else
168
+ arm_ss.add(files('tcg-stubs.c'))
169
endif
170
171
target_arch += {'arm': arm_ss}
172
diff --git a/target/arm/tcg/meson.build b/target/arm/tcg/meson.build
173
index XXXXXXX..XXXXXXX 100644
174
--- a/target/arm/tcg/meson.build
175
+++ b/target/arm/tcg/meson.build
176
@@ -XXX,XX +XXX,XX @@ arm_ss.add(files(
177
'translate-mve.c',
178
'translate-neon.c',
179
'translate-vfp.c',
180
+ 'crypto_helper.c',
181
+ 'iwmmxt_helper.c',
182
+ 'm_helper.c',
183
+ 'mve_helper.c',
184
+ 'neon_helper.c',
185
+ 'op_helper.c',
186
+ 'tlb_helper.c',
187
+ 'vec_helper.c',
188
))
189
190
arm_ss.add(when: 'TARGET_AARCH64', if_true: files(
191
'translate-a64.c',
192
'translate-sve.c',
193
'translate-sme.c',
194
+ 'helper-a64.c',
195
+ 'mte_helper.c',
196
+ 'pauth_helper.c',
197
+ 'sme_helper.c',
198
+ 'sve_helper.c',
199
))
153
--
200
--
154
2.20.1
201
2.34.1
155
202
156
203
diff view generated by jsdifflib
1
From: Bin Meng <bin.meng@windriver.com>
1
From: Claudio Fontana <cfontana@suse.de>
2
2
3
Currently when U-Boot boots, it prints "??" for i.MX processor:
3
Signed-off-by: Claudio Fontana <cfontana@suse.de>
4
4
Signed-off-by: Fabiano Rosas <farosas@suse.de>
5
CPU: Freescale i.MX?? rev1.0 at 792 MHz
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
7
The register that was used to determine the silicon type is
8
undocumented in the latest IMX6DQRM (Rev. 6, 05/2020), but we
9
can refer to get_cpu_rev() in arch/arm/mach-imx/mx6/soc.c in
10
the U-Boot source codes that USB_ANALOG_DIGPROG is used.
11
12
Update its reset value to indicate i.MX6Q.
13
14
Signed-off-by: Bin Meng <bin.meng@windriver.com>
15
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
6
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
16
Message-id: 20210106063504.10841-3-bmeng.cn@gmail.com
7
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
---
9
---
19
hw/misc/imx6_ccm.c | 2 +-
10
target/arm/{ => tcg}/psci.c | 0
20
1 file changed, 1 insertion(+), 1 deletion(-)
11
target/arm/meson.build | 1 -
12
target/arm/tcg/meson.build | 4 ++++
13
3 files changed, 4 insertions(+), 1 deletion(-)
14
rename target/arm/{ => tcg}/psci.c (100%)
21
15
22
diff --git a/hw/misc/imx6_ccm.c b/hw/misc/imx6_ccm.c
16
diff --git a/target/arm/psci.c b/target/arm/tcg/psci.c
17
similarity index 100%
18
rename from target/arm/psci.c
19
rename to target/arm/tcg/psci.c
20
diff --git a/target/arm/meson.build b/target/arm/meson.build
23
index XXXXXXX..XXXXXXX 100644
21
index XXXXXXX..XXXXXXX 100644
24
--- a/hw/misc/imx6_ccm.c
22
--- a/target/arm/meson.build
25
+++ b/hw/misc/imx6_ccm.c
23
+++ b/target/arm/meson.build
26
@@ -XXX,XX +XXX,XX @@ static void imx6_ccm_reset(DeviceState *dev)
24
@@ -XXX,XX +XXX,XX @@ arm_softmmu_ss.add(files(
27
s->analog[USB_ANALOG_USB2_VBUS_DETECT] = 0x00000004;
25
'arm-powerctl.c',
28
s->analog[USB_ANALOG_USB2_CHRG_DETECT] = 0x00000000;
26
'machine.c',
29
s->analog[USB_ANALOG_USB2_MISC] = 0x00000002;
27
'monitor.c',
30
- s->analog[USB_ANALOG_DIGPROG] = 0x00000000;
28
- 'psci.c',
31
+ s->analog[USB_ANALOG_DIGPROG] = 0x00630000;
29
'ptw.c',
32
30
))
33
/* all PLLs need to be locked */
31
34
s->analog[CCM_ANALOG_PLL_ARM] |= CCM_ANALOG_PLL_LOCK;
32
diff --git a/target/arm/tcg/meson.build b/target/arm/tcg/meson.build
33
index XXXXXXX..XXXXXXX 100644
34
--- a/target/arm/tcg/meson.build
35
+++ b/target/arm/tcg/meson.build
36
@@ -XXX,XX +XXX,XX @@ arm_ss.add(when: 'TARGET_AARCH64', if_true: files(
37
'sme_helper.c',
38
'sve_helper.c',
39
))
40
+
41
+arm_softmmu_ss.add(files(
42
+ 'psci.c',
43
+))
35
--
44
--
36
2.20.1
45
2.34.1
37
46
38
47
diff view generated by jsdifflib
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Fabiano Rosas <farosas@suse.de>
2
2
3
In 50244cc76abc we updated mte_check_fail to match the ARM
3
This is in preparation to moving the hflags code into its own file
4
pseudocode, using the correct EL to select the TCF field.
4
under the tcg/ directory.
5
But we failed to update MTE0_ACTIVE the same way, which led
5
6
to g_assert_not_reached().
6
Signed-off-by: Fabiano Rosas <farosas@suse.de>
7
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Cc: qemu-stable@nongnu.org
8
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
9
Buglink: https://bugs.launchpad.net/bugs/1907137
10
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
11
Message-id: 20201221204426.88514-1-richard.henderson@linaro.org
12
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
10
---
15
target/arm/helper.c | 2 +-
11
hw/arm/boot.c | 6 +++++-
16
1 file changed, 1 insertion(+), 1 deletion(-)
12
hw/intc/armv7m_nvic.c | 20 +++++++++++++-------
17
13
target/arm/arm-powerctl.c | 7 +++++--
14
target/arm/cpu.c | 3 ++-
15
target/arm/helper.c | 18 +++++++++++++-----
16
target/arm/machine.c | 5 ++++-
17
6 files changed, 42 insertions(+), 17 deletions(-)
18
19
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
20
index XXXXXXX..XXXXXXX 100644
21
--- a/hw/arm/boot.c
22
+++ b/hw/arm/boot.c
23
@@ -XXX,XX +XXX,XX @@
24
#include "hw/arm/boot.h"
25
#include "hw/arm/linux-boot-if.h"
26
#include "sysemu/kvm.h"
27
+#include "sysemu/tcg.h"
28
#include "sysemu/sysemu.h"
29
#include "sysemu/numa.h"
30
#include "hw/boards.h"
31
@@ -XXX,XX +XXX,XX @@ static void do_cpu_reset(void *opaque)
32
info->secondary_cpu_reset_hook(cpu, info);
33
}
34
}
35
- arm_rebuild_hflags(env);
36
+
37
+ if (tcg_enabled()) {
38
+ arm_rebuild_hflags(env);
39
+ }
40
}
41
}
42
43
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
44
index XXXXXXX..XXXXXXX 100644
45
--- a/hw/intc/armv7m_nvic.c
46
+++ b/hw/intc/armv7m_nvic.c
47
@@ -XXX,XX +XXX,XX @@
48
#include "hw/intc/armv7m_nvic.h"
49
#include "hw/irq.h"
50
#include "hw/qdev-properties.h"
51
+#include "sysemu/tcg.h"
52
#include "sysemu/runstate.h"
53
#include "target/arm/cpu.h"
54
#include "exec/exec-all.h"
55
@@ -XXX,XX +XXX,XX @@ static MemTxResult nvic_sysreg_write(void *opaque, hwaddr addr,
56
/* This is UNPREDICTABLE; treat as RAZ/WI */
57
58
exit_ok:
59
- /* Ensure any changes made are reflected in the cached hflags. */
60
- arm_rebuild_hflags(&s->cpu->env);
61
+ if (tcg_enabled()) {
62
+ /* Ensure any changes made are reflected in the cached hflags. */
63
+ arm_rebuild_hflags(&s->cpu->env);
64
+ }
65
return MEMTX_OK;
66
}
67
68
@@ -XXX,XX +XXX,XX @@ static void armv7m_nvic_reset(DeviceState *dev)
69
}
70
}
71
72
- /*
73
- * We updated state that affects the CPU's MMUidx and thus its hflags;
74
- * and we can't guarantee that we run before the CPU reset function.
75
- */
76
- arm_rebuild_hflags(&s->cpu->env);
77
+ if (tcg_enabled()) {
78
+ /*
79
+ * We updated state that affects the CPU's MMUidx and thus its
80
+ * hflags; and we can't guarantee that we run before the CPU
81
+ * reset function.
82
+ */
83
+ arm_rebuild_hflags(&s->cpu->env);
84
+ }
85
}
86
87
static void nvic_systick_trigger(void *opaque, int n, int level)
88
diff --git a/target/arm/arm-powerctl.c b/target/arm/arm-powerctl.c
89
index XXXXXXX..XXXXXXX 100644
90
--- a/target/arm/arm-powerctl.c
91
+++ b/target/arm/arm-powerctl.c
92
@@ -XXX,XX +XXX,XX @@
93
#include "arm-powerctl.h"
94
#include "qemu/log.h"
95
#include "qemu/main-loop.h"
96
+#include "sysemu/tcg.h"
97
98
#ifndef DEBUG_ARM_POWERCTL
99
#define DEBUG_ARM_POWERCTL 0
100
@@ -XXX,XX +XXX,XX @@ static void arm_set_cpu_on_async_work(CPUState *target_cpu_state,
101
target_cpu->env.regs[0] = info->context_id;
102
}
103
104
- /* CP15 update requires rebuilding hflags */
105
- arm_rebuild_hflags(&target_cpu->env);
106
+ if (tcg_enabled()) {
107
+ /* CP15 update requires rebuilding hflags */
108
+ arm_rebuild_hflags(&target_cpu->env);
109
+ }
110
111
/* Start the new CPU at the requested address */
112
cpu_set_pc(target_cpu_state, info->entry);
113
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
114
index XXXXXXX..XXXXXXX 100644
115
--- a/target/arm/cpu.c
116
+++ b/target/arm/cpu.c
117
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset_hold(Object *obj)
118
if (tcg_enabled()) {
119
hw_breakpoint_update_all(cpu);
120
hw_watchpoint_update_all(cpu);
121
+
122
+ arm_rebuild_hflags(env);
123
}
124
- arm_rebuild_hflags(env);
125
}
126
127
#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
18
diff --git a/target/arm/helper.c b/target/arm/helper.c
128
diff --git a/target/arm/helper.c b/target/arm/helper.c
19
index XXXXXXX..XXXXXXX 100644
129
index XXXXXXX..XXXXXXX 100644
20
--- a/target/arm/helper.c
130
--- a/target/arm/helper.c
21
+++ b/target/arm/helper.c
131
+++ b/target/arm/helper.c
22
@@ -XXX,XX +XXX,XX @@ static uint32_t rebuild_hflags_a64(CPUARMState *env, int el, int fp_el,
132
@@ -XXX,XX +XXX,XX @@ static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri,
23
if (FIELD_EX32(flags, TBFLAG_A64, UNPRIV)
133
/* This may enable/disable the MMU, so do a TLB flush. */
24
&& tbid
134
tlb_flush(CPU(cpu));
25
&& !(env->pstate & PSTATE_TCO)
135
26
- && (sctlr & SCTLR_TCF0)
136
- if (ri->type & ARM_CP_SUPPRESS_TB_END) {
27
+ && (sctlr & SCTLR_TCF)
137
+ if (tcg_enabled() && ri->type & ARM_CP_SUPPRESS_TB_END) {
28
&& allocation_tag_access_enabled(env, 0, sctlr)) {
138
/*
29
flags = FIELD_DP32(flags, TBFLAG_A64, MTE0_ACTIVE, 1);
139
* Normally we would always end the TB on an SCTLR write; see the
30
}
140
* comment in ARMCPRegInfo sctlr initialization below for why Xscale
141
@@ -XXX,XX +XXX,XX @@ void aarch64_set_svcr(CPUARMState *env, uint64_t new, uint64_t mask)
142
memset(env->zarray, 0, sizeof(env->zarray));
143
}
144
145
- arm_rebuild_hflags(env);
146
+ if (tcg_enabled()) {
147
+ arm_rebuild_hflags(env);
148
+ }
149
}
150
151
static void svcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
152
@@ -XXX,XX +XXX,XX @@ void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask,
153
}
154
mask &= ~CACHED_CPSR_BITS;
155
env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask);
156
- if (rebuild_hflags) {
157
+ if (tcg_enabled() && rebuild_hflags) {
158
arm_rebuild_hflags(env);
159
}
160
}
161
@@ -XXX,XX +XXX,XX @@ static void take_aarch32_exception(CPUARMState *env, int new_mode,
162
env->regs[14] = env->regs[15] + offset;
163
}
164
env->regs[15] = newpc;
165
- arm_rebuild_hflags(env);
166
+
167
+ if (tcg_enabled()) {
168
+ arm_rebuild_hflags(env);
169
+ }
170
}
171
172
static void arm_cpu_do_interrupt_aarch32_hyp(CPUState *cs)
173
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs)
174
pstate_write(env, PSTATE_DAIF | new_mode);
175
env->aarch64 = true;
176
aarch64_restore_sp(env, new_el);
177
- helper_rebuild_hflags_a64(env, new_el);
178
+
179
+ if (tcg_enabled()) {
180
+ helper_rebuild_hflags_a64(env, new_el);
181
+ }
182
183
env->pc = addr;
184
185
diff --git a/target/arm/machine.c b/target/arm/machine.c
186
index XXXXXXX..XXXXXXX 100644
187
--- a/target/arm/machine.c
188
+++ b/target/arm/machine.c
189
@@ -XXX,XX +XXX,XX @@ static int cpu_post_load(void *opaque, int version_id)
190
if (!kvm_enabled()) {
191
pmu_op_finish(&cpu->env);
192
}
193
- arm_rebuild_hflags(&cpu->env);
194
+
195
+ if (tcg_enabled()) {
196
+ arm_rebuild_hflags(&cpu->env);
197
+ }
198
199
return 0;
200
}
31
--
201
--
32
2.20.1
202
2.34.1
33
203
34
204
diff view generated by jsdifflib
1
Now that timer_free() implicitly calls timer_del(), sequences
1
From: Fabiano Rosas <farosas@suse.de>
2
timer_del(mytimer);
3
timer_free(mytimer);
4
2
5
can be simplified to just
3
The hflags are used only for TCG code, so introduce a new file
6
timer_free(mytimer);
4
hflags.c to keep that code.
7
5
8
Add a Coccinelle script to do this transformation.
6
Signed-off-by: Fabiano Rosas <farosas@suse.de>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/internals.h | 2 +
12
target/arm/helper.c | 393 +-----------------------------------
13
target/arm/tcg-stubs.c | 4 +
14
target/arm/tcg/hflags.c | 403 +++++++++++++++++++++++++++++++++++++
15
target/arm/tcg/meson.build | 1 +
16
5 files changed, 411 insertions(+), 392 deletions(-)
17
create mode 100644 target/arm/tcg/hflags.c
9
18
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
diff --git a/target/arm/internals.h b/target/arm/internals.h
11
Acked-by: Paolo Bonzini <pbonzini@redhat.com>
20
index XXXXXXX..XXXXXXX 100644
12
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
21
--- a/target/arm/internals.h
13
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
22
+++ b/target/arm/internals.h
14
Message-id: 20201215154107.3255-3-peter.maydell@linaro.org
23
@@ -XXX,XX +XXX,XX @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
15
---
24
16
scripts/coccinelle/timer-del-timer-free.cocci | 18 ++++++++++++++++++
25
int aa64_va_parameter_tbi(uint64_t tcr, ARMMMUIdx mmu_idx);
17
1 file changed, 18 insertions(+)
26
int aa64_va_parameter_tbid(uint64_t tcr, ARMMMUIdx mmu_idx);
18
create mode 100644 scripts/coccinelle/timer-del-timer-free.cocci
27
+int aa64_va_parameter_tcma(uint64_t tcr, ARMMMUIdx mmu_idx);
19
28
20
diff --git a/scripts/coccinelle/timer-del-timer-free.cocci b/scripts/coccinelle/timer-del-timer-free.cocci
29
/* Determine if allocation tags are available. */
30
static inline bool allocation_tag_access_enabled(CPUARMState *env, int el,
31
@@ -XXX,XX +XXX,XX @@ static inline bool arm_fgt_active(CPUARMState *env, int el)
32
(!arm_feature(env, ARM_FEATURE_EL3) || (env->cp15.scr_el3 & SCR_FGTEN));
33
}
34
35
+void assert_hflags_rebuild_correctly(CPUARMState *env);
36
#endif
37
diff --git a/target/arm/helper.c b/target/arm/helper.c
38
index XXXXXXX..XXXXXXX 100644
39
--- a/target/arm/helper.c
40
+++ b/target/arm/helper.c
41
@@ -XXX,XX +XXX,XX @@ int sme_exception_el(CPUARMState *env, int el)
42
return 0;
43
}
44
45
-/* This corresponds to the ARM pseudocode function IsFullA64Enabled(). */
46
-static bool sme_fa64(CPUARMState *env, int el)
47
-{
48
- if (!cpu_isar_feature(aa64_sme_fa64, env_archcpu(env))) {
49
- return false;
50
- }
51
-
52
- if (el <= 1 && !el_is_in_host(env, el)) {
53
- if (!FIELD_EX64(env->vfp.smcr_el[1], SMCR, FA64)) {
54
- return false;
55
- }
56
- }
57
- if (el <= 2 && arm_is_el2_enabled(env)) {
58
- if (!FIELD_EX64(env->vfp.smcr_el[2], SMCR, FA64)) {
59
- return false;
60
- }
61
- }
62
- if (arm_feature(env, ARM_FEATURE_EL3)) {
63
- if (!FIELD_EX64(env->vfp.smcr_el[3], SMCR, FA64)) {
64
- return false;
65
- }
66
- }
67
-
68
- return true;
69
-}
70
-
71
/*
72
* Given that SVE is enabled, return the vector length for EL.
73
*/
74
@@ -XXX,XX +XXX,XX @@ int aa64_va_parameter_tbid(uint64_t tcr, ARMMMUIdx mmu_idx)
75
}
76
}
77
78
-static int aa64_va_parameter_tcma(uint64_t tcr, ARMMMUIdx mmu_idx)
79
+int aa64_va_parameter_tcma(uint64_t tcr, ARMMMUIdx mmu_idx)
80
{
81
if (regime_has_2_ranges(mmu_idx)) {
82
return extract64(tcr, 57, 2);
83
@@ -XXX,XX +XXX,XX @@ ARMMMUIdx arm_mmu_idx(CPUARMState *env)
84
return arm_mmu_idx_el(env, arm_current_el(env));
85
}
86
87
-static inline bool fgt_svc(CPUARMState *env, int el)
88
-{
89
- /*
90
- * Assuming fine-grained-traps are active, return true if we
91
- * should be trapping on SVC instructions. Only AArch64 can
92
- * trap on an SVC at EL1, but we don't need to special-case this
93
- * because if this is AArch32 EL1 then arm_fgt_active() is false.
94
- * We also know el is 0 or 1.
95
- */
96
- return el == 0 ?
97
- FIELD_EX64(env->cp15.fgt_exec[FGTREG_HFGITR], HFGITR_EL2, SVC_EL0) :
98
- FIELD_EX64(env->cp15.fgt_exec[FGTREG_HFGITR], HFGITR_EL2, SVC_EL1);
99
-}
100
-
101
-static CPUARMTBFlags rebuild_hflags_common(CPUARMState *env, int fp_el,
102
- ARMMMUIdx mmu_idx,
103
- CPUARMTBFlags flags)
104
-{
105
- DP_TBFLAG_ANY(flags, FPEXC_EL, fp_el);
106
- DP_TBFLAG_ANY(flags, MMUIDX, arm_to_core_mmu_idx(mmu_idx));
107
-
108
- if (arm_singlestep_active(env)) {
109
- DP_TBFLAG_ANY(flags, SS_ACTIVE, 1);
110
- }
111
-
112
- return flags;
113
-}
114
-
115
-static CPUARMTBFlags rebuild_hflags_common_32(CPUARMState *env, int fp_el,
116
- ARMMMUIdx mmu_idx,
117
- CPUARMTBFlags flags)
118
-{
119
- bool sctlr_b = arm_sctlr_b(env);
120
-
121
- if (sctlr_b) {
122
- DP_TBFLAG_A32(flags, SCTLR__B, 1);
123
- }
124
- if (arm_cpu_data_is_big_endian_a32(env, sctlr_b)) {
125
- DP_TBFLAG_ANY(flags, BE_DATA, 1);
126
- }
127
- DP_TBFLAG_A32(flags, NS, !access_secure_reg(env));
128
-
129
- return rebuild_hflags_common(env, fp_el, mmu_idx, flags);
130
-}
131
-
132
-static CPUARMTBFlags rebuild_hflags_m32(CPUARMState *env, int fp_el,
133
- ARMMMUIdx mmu_idx)
134
-{
135
- CPUARMTBFlags flags = {};
136
- uint32_t ccr = env->v7m.ccr[env->v7m.secure];
137
-
138
- /* Without HaveMainExt, CCR.UNALIGN_TRP is RES1. */
139
- if (ccr & R_V7M_CCR_UNALIGN_TRP_MASK) {
140
- DP_TBFLAG_ANY(flags, ALIGN_MEM, 1);
141
- }
142
-
143
- if (arm_v7m_is_handler_mode(env)) {
144
- DP_TBFLAG_M32(flags, HANDLER, 1);
145
- }
146
-
147
- /*
148
- * v8M always applies stack limit checks unless CCR.STKOFHFNMIGN
149
- * is suppressing them because the requested execution priority
150
- * is less than 0.
151
- */
152
- if (arm_feature(env, ARM_FEATURE_V8) &&
153
- !((mmu_idx & ARM_MMU_IDX_M_NEGPRI) &&
154
- (ccr & R_V7M_CCR_STKOFHFNMIGN_MASK))) {
155
- DP_TBFLAG_M32(flags, STACKCHECK, 1);
156
- }
157
-
158
- if (arm_feature(env, ARM_FEATURE_M_SECURITY) && env->v7m.secure) {
159
- DP_TBFLAG_M32(flags, SECURE, 1);
160
- }
161
-
162
- return rebuild_hflags_common_32(env, fp_el, mmu_idx, flags);
163
-}
164
-
165
-static CPUARMTBFlags rebuild_hflags_a32(CPUARMState *env, int fp_el,
166
- ARMMMUIdx mmu_idx)
167
-{
168
- CPUARMTBFlags flags = {};
169
- int el = arm_current_el(env);
170
-
171
- if (arm_sctlr(env, el) & SCTLR_A) {
172
- DP_TBFLAG_ANY(flags, ALIGN_MEM, 1);
173
- }
174
-
175
- if (arm_el_is_aa64(env, 1)) {
176
- DP_TBFLAG_A32(flags, VFPEN, 1);
177
- }
178
-
179
- if (el < 2 && env->cp15.hstr_el2 && arm_is_el2_enabled(env) &&
180
- (arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) {
181
- DP_TBFLAG_A32(flags, HSTR_ACTIVE, 1);
182
- }
183
-
184
- if (arm_fgt_active(env, el)) {
185
- DP_TBFLAG_ANY(flags, FGT_ACTIVE, 1);
186
- if (fgt_svc(env, el)) {
187
- DP_TBFLAG_ANY(flags, FGT_SVC, 1);
188
- }
189
- }
190
-
191
- if (env->uncached_cpsr & CPSR_IL) {
192
- DP_TBFLAG_ANY(flags, PSTATE__IL, 1);
193
- }
194
-
195
- /*
196
- * The SME exception we are testing for is raised via
197
- * AArch64.CheckFPAdvSIMDEnabled(), as called from
198
- * AArch32.CheckAdvSIMDOrFPEnabled().
199
- */
200
- if (el == 0
201
- && FIELD_EX64(env->svcr, SVCR, SM)
202
- && (!arm_is_el2_enabled(env)
203
- || (arm_el_is_aa64(env, 2) && !(env->cp15.hcr_el2 & HCR_TGE)))
204
- && arm_el_is_aa64(env, 1)
205
- && !sme_fa64(env, el)) {
206
- DP_TBFLAG_A32(flags, SME_TRAP_NONSTREAMING, 1);
207
- }
208
-
209
- return rebuild_hflags_common_32(env, fp_el, mmu_idx, flags);
210
-}
211
-
212
-static CPUARMTBFlags rebuild_hflags_a64(CPUARMState *env, int el, int fp_el,
213
- ARMMMUIdx mmu_idx)
214
-{
215
- CPUARMTBFlags flags = {};
216
- ARMMMUIdx stage1 = stage_1_mmu_idx(mmu_idx);
217
- uint64_t tcr = regime_tcr(env, mmu_idx);
218
- uint64_t sctlr;
219
- int tbii, tbid;
220
-
221
- DP_TBFLAG_ANY(flags, AARCH64_STATE, 1);
222
-
223
- /* Get control bits for tagged addresses. */
224
- tbid = aa64_va_parameter_tbi(tcr, mmu_idx);
225
- tbii = tbid & ~aa64_va_parameter_tbid(tcr, mmu_idx);
226
-
227
- DP_TBFLAG_A64(flags, TBII, tbii);
228
- DP_TBFLAG_A64(flags, TBID, tbid);
229
-
230
- if (cpu_isar_feature(aa64_sve, env_archcpu(env))) {
231
- int sve_el = sve_exception_el(env, el);
232
-
233
- /*
234
- * If either FP or SVE are disabled, translator does not need len.
235
- * If SVE EL > FP EL, FP exception has precedence, and translator
236
- * does not need SVE EL. Save potential re-translations by forcing
237
- * the unneeded data to zero.
238
- */
239
- if (fp_el != 0) {
240
- if (sve_el > fp_el) {
241
- sve_el = 0;
242
- }
243
- } else if (sve_el == 0) {
244
- DP_TBFLAG_A64(flags, VL, sve_vqm1_for_el(env, el));
245
- }
246
- DP_TBFLAG_A64(flags, SVEEXC_EL, sve_el);
247
- }
248
- if (cpu_isar_feature(aa64_sme, env_archcpu(env))) {
249
- int sme_el = sme_exception_el(env, el);
250
- bool sm = FIELD_EX64(env->svcr, SVCR, SM);
251
-
252
- DP_TBFLAG_A64(flags, SMEEXC_EL, sme_el);
253
- if (sme_el == 0) {
254
- /* Similarly, do not compute SVL if SME is disabled. */
255
- int svl = sve_vqm1_for_el_sm(env, el, true);
256
- DP_TBFLAG_A64(flags, SVL, svl);
257
- if (sm) {
258
- /* If SVE is disabled, we will not have set VL above. */
259
- DP_TBFLAG_A64(flags, VL, svl);
260
- }
261
- }
262
- if (sm) {
263
- DP_TBFLAG_A64(flags, PSTATE_SM, 1);
264
- DP_TBFLAG_A64(flags, SME_TRAP_NONSTREAMING, !sme_fa64(env, el));
265
- }
266
- DP_TBFLAG_A64(flags, PSTATE_ZA, FIELD_EX64(env->svcr, SVCR, ZA));
267
- }
268
-
269
- sctlr = regime_sctlr(env, stage1);
270
-
271
- if (sctlr & SCTLR_A) {
272
- DP_TBFLAG_ANY(flags, ALIGN_MEM, 1);
273
- }
274
-
275
- if (arm_cpu_data_is_big_endian_a64(el, sctlr)) {
276
- DP_TBFLAG_ANY(flags, BE_DATA, 1);
277
- }
278
-
279
- if (cpu_isar_feature(aa64_pauth, env_archcpu(env))) {
280
- /*
281
- * In order to save space in flags, we record only whether
282
- * pauth is "inactive", meaning all insns are implemented as
283
- * a nop, or "active" when some action must be performed.
284
- * The decision of which action to take is left to a helper.
285
- */
286
- if (sctlr & (SCTLR_EnIA | SCTLR_EnIB | SCTLR_EnDA | SCTLR_EnDB)) {
287
- DP_TBFLAG_A64(flags, PAUTH_ACTIVE, 1);
288
- }
289
- }
290
-
291
- if (cpu_isar_feature(aa64_bti, env_archcpu(env))) {
292
- /* Note that SCTLR_EL[23].BT == SCTLR_BT1. */
293
- if (sctlr & (el == 0 ? SCTLR_BT0 : SCTLR_BT1)) {
294
- DP_TBFLAG_A64(flags, BT, 1);
295
- }
296
- }
297
-
298
- /* Compute the condition for using AccType_UNPRIV for LDTR et al. */
299
- if (!(env->pstate & PSTATE_UAO)) {
300
- switch (mmu_idx) {
301
- case ARMMMUIdx_E10_1:
302
- case ARMMMUIdx_E10_1_PAN:
303
- /* TODO: ARMv8.3-NV */
304
- DP_TBFLAG_A64(flags, UNPRIV, 1);
305
- break;
306
- case ARMMMUIdx_E20_2:
307
- case ARMMMUIdx_E20_2_PAN:
308
- /*
309
- * Note that EL20_2 is gated by HCR_EL2.E2H == 1, but EL20_0 is
310
- * gated by HCR_EL2.<E2H,TGE> == '11', and so is LDTR.
311
- */
312
- if (env->cp15.hcr_el2 & HCR_TGE) {
313
- DP_TBFLAG_A64(flags, UNPRIV, 1);
314
- }
315
- break;
316
- default:
317
- break;
318
- }
319
- }
320
-
321
- if (env->pstate & PSTATE_IL) {
322
- DP_TBFLAG_ANY(flags, PSTATE__IL, 1);
323
- }
324
-
325
- if (arm_fgt_active(env, el)) {
326
- DP_TBFLAG_ANY(flags, FGT_ACTIVE, 1);
327
- if (FIELD_EX64(env->cp15.fgt_exec[FGTREG_HFGITR], HFGITR_EL2, ERET)) {
328
- DP_TBFLAG_A64(flags, FGT_ERET, 1);
329
- }
330
- if (fgt_svc(env, el)) {
331
- DP_TBFLAG_ANY(flags, FGT_SVC, 1);
332
- }
333
- }
334
-
335
- if (cpu_isar_feature(aa64_mte, env_archcpu(env))) {
336
- /*
337
- * Set MTE_ACTIVE if any access may be Checked, and leave clear
338
- * if all accesses must be Unchecked:
339
- * 1) If no TBI, then there are no tags in the address to check,
340
- * 2) If Tag Check Override, then all accesses are Unchecked,
341
- * 3) If Tag Check Fail == 0, then Checked access have no effect,
342
- * 4) If no Allocation Tag Access, then all accesses are Unchecked.
343
- */
344
- if (allocation_tag_access_enabled(env, el, sctlr)) {
345
- DP_TBFLAG_A64(flags, ATA, 1);
346
- if (tbid
347
- && !(env->pstate & PSTATE_TCO)
348
- && (sctlr & (el == 0 ? SCTLR_TCF0 : SCTLR_TCF))) {
349
- DP_TBFLAG_A64(flags, MTE_ACTIVE, 1);
350
- }
351
- }
352
- /* And again for unprivileged accesses, if required. */
353
- if (EX_TBFLAG_A64(flags, UNPRIV)
354
- && tbid
355
- && !(env->pstate & PSTATE_TCO)
356
- && (sctlr & SCTLR_TCF0)
357
- && allocation_tag_access_enabled(env, 0, sctlr)) {
358
- DP_TBFLAG_A64(flags, MTE0_ACTIVE, 1);
359
- }
360
- /* Cache TCMA as well as TBI. */
361
- DP_TBFLAG_A64(flags, TCMA, aa64_va_parameter_tcma(tcr, mmu_idx));
362
- }
363
-
364
- return rebuild_hflags_common(env, fp_el, mmu_idx, flags);
365
-}
366
-
367
-static CPUARMTBFlags rebuild_hflags_internal(CPUARMState *env)
368
-{
369
- int el = arm_current_el(env);
370
- int fp_el = fp_exception_el(env, el);
371
- ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el);
372
-
373
- if (is_a64(env)) {
374
- return rebuild_hflags_a64(env, el, fp_el, mmu_idx);
375
- } else if (arm_feature(env, ARM_FEATURE_M)) {
376
- return rebuild_hflags_m32(env, fp_el, mmu_idx);
377
- } else {
378
- return rebuild_hflags_a32(env, fp_el, mmu_idx);
379
- }
380
-}
381
-
382
-void arm_rebuild_hflags(CPUARMState *env)
383
-{
384
- env->hflags = rebuild_hflags_internal(env);
385
-}
386
-
387
-/*
388
- * If we have triggered a EL state change we can't rely on the
389
- * translator having passed it to us, we need to recompute.
390
- */
391
-void HELPER(rebuild_hflags_m32_newel)(CPUARMState *env)
392
-{
393
- int el = arm_current_el(env);
394
- int fp_el = fp_exception_el(env, el);
395
- ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el);
396
-
397
- env->hflags = rebuild_hflags_m32(env, fp_el, mmu_idx);
398
-}
399
-
400
-void HELPER(rebuild_hflags_m32)(CPUARMState *env, int el)
401
-{
402
- int fp_el = fp_exception_el(env, el);
403
- ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el);
404
-
405
- env->hflags = rebuild_hflags_m32(env, fp_el, mmu_idx);
406
-}
407
-
408
-/*
409
- * If we have triggered a EL state change we can't rely on the
410
- * translator having passed it to us, we need to recompute.
411
- */
412
-void HELPER(rebuild_hflags_a32_newel)(CPUARMState *env)
413
-{
414
- int el = arm_current_el(env);
415
- int fp_el = fp_exception_el(env, el);
416
- ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el);
417
- env->hflags = rebuild_hflags_a32(env, fp_el, mmu_idx);
418
-}
419
-
420
-void HELPER(rebuild_hflags_a32)(CPUARMState *env, int el)
421
-{
422
- int fp_el = fp_exception_el(env, el);
423
- ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el);
424
-
425
- env->hflags = rebuild_hflags_a32(env, fp_el, mmu_idx);
426
-}
427
-
428
-void HELPER(rebuild_hflags_a64)(CPUARMState *env, int el)
429
-{
430
- int fp_el = fp_exception_el(env, el);
431
- ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el);
432
-
433
- env->hflags = rebuild_hflags_a64(env, el, fp_el, mmu_idx);
434
-}
435
-
436
-static inline void assert_hflags_rebuild_correctly(CPUARMState *env)
437
-{
438
-#ifdef CONFIG_DEBUG_TCG
439
- CPUARMTBFlags c = env->hflags;
440
- CPUARMTBFlags r = rebuild_hflags_internal(env);
441
-
442
- if (unlikely(c.flags != r.flags || c.flags2 != r.flags2)) {
443
- fprintf(stderr, "TCG hflags mismatch "
444
- "(current:(0x%08x,0x" TARGET_FMT_lx ")"
445
- " rebuilt:(0x%08x,0x" TARGET_FMT_lx ")\n",
446
- c.flags, c.flags2, r.flags, r.flags2);
447
- abort();
448
- }
449
-#endif
450
-}
451
-
452
static bool mve_no_pred(CPUARMState *env)
453
{
454
/*
455
diff --git a/target/arm/tcg-stubs.c b/target/arm/tcg-stubs.c
456
index XXXXXXX..XXXXXXX 100644
457
--- a/target/arm/tcg-stubs.c
458
+++ b/target/arm/tcg-stubs.c
459
@@ -XXX,XX +XXX,XX @@ void raise_exception_ra(CPUARMState *env, uint32_t excp, uint32_t syndrome,
460
{
461
g_assert_not_reached();
462
}
463
+/* Temporarily while cpu_get_tb_cpu_state() is still in common code */
464
+void assert_hflags_rebuild_correctly(CPUARMState *env)
465
+{
466
+}
467
diff --git a/target/arm/tcg/hflags.c b/target/arm/tcg/hflags.c
21
new file mode 100644
468
new file mode 100644
22
index XXXXXXX..XXXXXXX
469
index XXXXXXX..XXXXXXX
23
--- /dev/null
470
--- /dev/null
24
+++ b/scripts/coccinelle/timer-del-timer-free.cocci
471
+++ b/target/arm/tcg/hflags.c
25
@@ -XXX,XX +XXX,XX @@
472
@@ -XXX,XX +XXX,XX @@
26
+// Remove superfluous timer_del() calls
473
+/*
27
+//
474
+ * ARM hflags
28
+// Copyright Linaro Limited 2020
475
+ *
29
+// This work is licensed under the terms of the GNU GPLv2 or later.
476
+ * This code is licensed under the GNU GPL v2 or later.
30
+//
477
+ *
31
+// spatch --macro-file scripts/cocci-macro-file.h \
478
+ * SPDX-License-Identifier: GPL-2.0-or-later
32
+// --sp-file scripts/coccinelle/timer-del-timer-free.cocci \
479
+ */
33
+// --in-place --dir .
480
+#include "qemu/osdep.h"
34
+//
481
+#include "cpu.h"
35
+// The timer_free() function now implicitly calls timer_del()
482
+#include "internals.h"
36
+// for you, so calls to timer_del() immediately before the
483
+#include "exec/helper-proto.h"
37
+// timer_free() of the same timer can be deleted.
484
+#include "cpregs.h"
38
+
485
+
39
+@@
486
+static inline bool fgt_svc(CPUARMState *env, int el)
40
+expression T;
487
+{
41
+@@
488
+ /*
42
+-timer_del(T);
489
+ * Assuming fine-grained-traps are active, return true if we
43
+ timer_free(T);
490
+ * should be trapping on SVC instructions. Only AArch64 can
491
+ * trap on an SVC at EL1, but we don't need to special-case this
492
+ * because if this is AArch32 EL1 then arm_fgt_active() is false.
493
+ * We also know el is 0 or 1.
494
+ */
495
+ return el == 0 ?
496
+ FIELD_EX64(env->cp15.fgt_exec[FGTREG_HFGITR], HFGITR_EL2, SVC_EL0) :
497
+ FIELD_EX64(env->cp15.fgt_exec[FGTREG_HFGITR], HFGITR_EL2, SVC_EL1);
498
+}
499
+
500
+static CPUARMTBFlags rebuild_hflags_common(CPUARMState *env, int fp_el,
501
+ ARMMMUIdx mmu_idx,
502
+ CPUARMTBFlags flags)
503
+{
504
+ DP_TBFLAG_ANY(flags, FPEXC_EL, fp_el);
505
+ DP_TBFLAG_ANY(flags, MMUIDX, arm_to_core_mmu_idx(mmu_idx));
506
+
507
+ if (arm_singlestep_active(env)) {
508
+ DP_TBFLAG_ANY(flags, SS_ACTIVE, 1);
509
+ }
510
+
511
+ return flags;
512
+}
513
+
514
+static CPUARMTBFlags rebuild_hflags_common_32(CPUARMState *env, int fp_el,
515
+ ARMMMUIdx mmu_idx,
516
+ CPUARMTBFlags flags)
517
+{
518
+ bool sctlr_b = arm_sctlr_b(env);
519
+
520
+ if (sctlr_b) {
521
+ DP_TBFLAG_A32(flags, SCTLR__B, 1);
522
+ }
523
+ if (arm_cpu_data_is_big_endian_a32(env, sctlr_b)) {
524
+ DP_TBFLAG_ANY(flags, BE_DATA, 1);
525
+ }
526
+ DP_TBFLAG_A32(flags, NS, !access_secure_reg(env));
527
+
528
+ return rebuild_hflags_common(env, fp_el, mmu_idx, flags);
529
+}
530
+
531
+static CPUARMTBFlags rebuild_hflags_m32(CPUARMState *env, int fp_el,
532
+ ARMMMUIdx mmu_idx)
533
+{
534
+ CPUARMTBFlags flags = {};
535
+ uint32_t ccr = env->v7m.ccr[env->v7m.secure];
536
+
537
+ /* Without HaveMainExt, CCR.UNALIGN_TRP is RES1. */
538
+ if (ccr & R_V7M_CCR_UNALIGN_TRP_MASK) {
539
+ DP_TBFLAG_ANY(flags, ALIGN_MEM, 1);
540
+ }
541
+
542
+ if (arm_v7m_is_handler_mode(env)) {
543
+ DP_TBFLAG_M32(flags, HANDLER, 1);
544
+ }
545
+
546
+ /*
547
+ * v8M always applies stack limit checks unless CCR.STKOFHFNMIGN
548
+ * is suppressing them because the requested execution priority
549
+ * is less than 0.
550
+ */
551
+ if (arm_feature(env, ARM_FEATURE_V8) &&
552
+ !((mmu_idx & ARM_MMU_IDX_M_NEGPRI) &&
553
+ (ccr & R_V7M_CCR_STKOFHFNMIGN_MASK))) {
554
+ DP_TBFLAG_M32(flags, STACKCHECK, 1);
555
+ }
556
+
557
+ if (arm_feature(env, ARM_FEATURE_M_SECURITY) && env->v7m.secure) {
558
+ DP_TBFLAG_M32(flags, SECURE, 1);
559
+ }
560
+
561
+ return rebuild_hflags_common_32(env, fp_el, mmu_idx, flags);
562
+}
563
+
564
+/* This corresponds to the ARM pseudocode function IsFullA64Enabled(). */
565
+static bool sme_fa64(CPUARMState *env, int el)
566
+{
567
+ if (!cpu_isar_feature(aa64_sme_fa64, env_archcpu(env))) {
568
+ return false;
569
+ }
570
+
571
+ if (el <= 1 && !el_is_in_host(env, el)) {
572
+ if (!FIELD_EX64(env->vfp.smcr_el[1], SMCR, FA64)) {
573
+ return false;
574
+ }
575
+ }
576
+ if (el <= 2 && arm_is_el2_enabled(env)) {
577
+ if (!FIELD_EX64(env->vfp.smcr_el[2], SMCR, FA64)) {
578
+ return false;
579
+ }
580
+ }
581
+ if (arm_feature(env, ARM_FEATURE_EL3)) {
582
+ if (!FIELD_EX64(env->vfp.smcr_el[3], SMCR, FA64)) {
583
+ return false;
584
+ }
585
+ }
586
+
587
+ return true;
588
+}
589
+
590
+static CPUARMTBFlags rebuild_hflags_a32(CPUARMState *env, int fp_el,
591
+ ARMMMUIdx mmu_idx)
592
+{
593
+ CPUARMTBFlags flags = {};
594
+ int el = arm_current_el(env);
595
+
596
+ if (arm_sctlr(env, el) & SCTLR_A) {
597
+ DP_TBFLAG_ANY(flags, ALIGN_MEM, 1);
598
+ }
599
+
600
+ if (arm_el_is_aa64(env, 1)) {
601
+ DP_TBFLAG_A32(flags, VFPEN, 1);
602
+ }
603
+
604
+ if (el < 2 && env->cp15.hstr_el2 && arm_is_el2_enabled(env) &&
605
+ (arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) {
606
+ DP_TBFLAG_A32(flags, HSTR_ACTIVE, 1);
607
+ }
608
+
609
+ if (arm_fgt_active(env, el)) {
610
+ DP_TBFLAG_ANY(flags, FGT_ACTIVE, 1);
611
+ if (fgt_svc(env, el)) {
612
+ DP_TBFLAG_ANY(flags, FGT_SVC, 1);
613
+ }
614
+ }
615
+
616
+ if (env->uncached_cpsr & CPSR_IL) {
617
+ DP_TBFLAG_ANY(flags, PSTATE__IL, 1);
618
+ }
619
+
620
+ /*
621
+ * The SME exception we are testing for is raised via
622
+ * AArch64.CheckFPAdvSIMDEnabled(), as called from
623
+ * AArch32.CheckAdvSIMDOrFPEnabled().
624
+ */
625
+ if (el == 0
626
+ && FIELD_EX64(env->svcr, SVCR, SM)
627
+ && (!arm_is_el2_enabled(env)
628
+ || (arm_el_is_aa64(env, 2) && !(env->cp15.hcr_el2 & HCR_TGE)))
629
+ && arm_el_is_aa64(env, 1)
630
+ && !sme_fa64(env, el)) {
631
+ DP_TBFLAG_A32(flags, SME_TRAP_NONSTREAMING, 1);
632
+ }
633
+
634
+ return rebuild_hflags_common_32(env, fp_el, mmu_idx, flags);
635
+}
636
+
637
+static CPUARMTBFlags rebuild_hflags_a64(CPUARMState *env, int el, int fp_el,
638
+ ARMMMUIdx mmu_idx)
639
+{
640
+ CPUARMTBFlags flags = {};
641
+ ARMMMUIdx stage1 = stage_1_mmu_idx(mmu_idx);
642
+ uint64_t tcr = regime_tcr(env, mmu_idx);
643
+ uint64_t sctlr;
644
+ int tbii, tbid;
645
+
646
+ DP_TBFLAG_ANY(flags, AARCH64_STATE, 1);
647
+
648
+ /* Get control bits for tagged addresses. */
649
+ tbid = aa64_va_parameter_tbi(tcr, mmu_idx);
650
+ tbii = tbid & ~aa64_va_parameter_tbid(tcr, mmu_idx);
651
+
652
+ DP_TBFLAG_A64(flags, TBII, tbii);
653
+ DP_TBFLAG_A64(flags, TBID, tbid);
654
+
655
+ if (cpu_isar_feature(aa64_sve, env_archcpu(env))) {
656
+ int sve_el = sve_exception_el(env, el);
657
+
658
+ /*
659
+ * If either FP or SVE are disabled, translator does not need len.
660
+ * If SVE EL > FP EL, FP exception has precedence, and translator
661
+ * does not need SVE EL. Save potential re-translations by forcing
662
+ * the unneeded data to zero.
663
+ */
664
+ if (fp_el != 0) {
665
+ if (sve_el > fp_el) {
666
+ sve_el = 0;
667
+ }
668
+ } else if (sve_el == 0) {
669
+ DP_TBFLAG_A64(flags, VL, sve_vqm1_for_el(env, el));
670
+ }
671
+ DP_TBFLAG_A64(flags, SVEEXC_EL, sve_el);
672
+ }
673
+ if (cpu_isar_feature(aa64_sme, env_archcpu(env))) {
674
+ int sme_el = sme_exception_el(env, el);
675
+ bool sm = FIELD_EX64(env->svcr, SVCR, SM);
676
+
677
+ DP_TBFLAG_A64(flags, SMEEXC_EL, sme_el);
678
+ if (sme_el == 0) {
679
+ /* Similarly, do not compute SVL if SME is disabled. */
680
+ int svl = sve_vqm1_for_el_sm(env, el, true);
681
+ DP_TBFLAG_A64(flags, SVL, svl);
682
+ if (sm) {
683
+ /* If SVE is disabled, we will not have set VL above. */
684
+ DP_TBFLAG_A64(flags, VL, svl);
685
+ }
686
+ }
687
+ if (sm) {
688
+ DP_TBFLAG_A64(flags, PSTATE_SM, 1);
689
+ DP_TBFLAG_A64(flags, SME_TRAP_NONSTREAMING, !sme_fa64(env, el));
690
+ }
691
+ DP_TBFLAG_A64(flags, PSTATE_ZA, FIELD_EX64(env->svcr, SVCR, ZA));
692
+ }
693
+
694
+ sctlr = regime_sctlr(env, stage1);
695
+
696
+ if (sctlr & SCTLR_A) {
697
+ DP_TBFLAG_ANY(flags, ALIGN_MEM, 1);
698
+ }
699
+
700
+ if (arm_cpu_data_is_big_endian_a64(el, sctlr)) {
701
+ DP_TBFLAG_ANY(flags, BE_DATA, 1);
702
+ }
703
+
704
+ if (cpu_isar_feature(aa64_pauth, env_archcpu(env))) {
705
+ /*
706
+ * In order to save space in flags, we record only whether
707
+ * pauth is "inactive", meaning all insns are implemented as
708
+ * a nop, or "active" when some action must be performed.
709
+ * The decision of which action to take is left to a helper.
710
+ */
711
+ if (sctlr & (SCTLR_EnIA | SCTLR_EnIB | SCTLR_EnDA | SCTLR_EnDB)) {
712
+ DP_TBFLAG_A64(flags, PAUTH_ACTIVE, 1);
713
+ }
714
+ }
715
+
716
+ if (cpu_isar_feature(aa64_bti, env_archcpu(env))) {
717
+ /* Note that SCTLR_EL[23].BT == SCTLR_BT1. */
718
+ if (sctlr & (el == 0 ? SCTLR_BT0 : SCTLR_BT1)) {
719
+ DP_TBFLAG_A64(flags, BT, 1);
720
+ }
721
+ }
722
+
723
+ /* Compute the condition for using AccType_UNPRIV for LDTR et al. */
724
+ if (!(env->pstate & PSTATE_UAO)) {
725
+ switch (mmu_idx) {
726
+ case ARMMMUIdx_E10_1:
727
+ case ARMMMUIdx_E10_1_PAN:
728
+ /* TODO: ARMv8.3-NV */
729
+ DP_TBFLAG_A64(flags, UNPRIV, 1);
730
+ break;
731
+ case ARMMMUIdx_E20_2:
732
+ case ARMMMUIdx_E20_2_PAN:
733
+ /*
734
+ * Note that EL20_2 is gated by HCR_EL2.E2H == 1, but EL20_0 is
735
+ * gated by HCR_EL2.<E2H,TGE> == '11', and so is LDTR.
736
+ */
737
+ if (env->cp15.hcr_el2 & HCR_TGE) {
738
+ DP_TBFLAG_A64(flags, UNPRIV, 1);
739
+ }
740
+ break;
741
+ default:
742
+ break;
743
+ }
744
+ }
745
+
746
+ if (env->pstate & PSTATE_IL) {
747
+ DP_TBFLAG_ANY(flags, PSTATE__IL, 1);
748
+ }
749
+
750
+ if (arm_fgt_active(env, el)) {
751
+ DP_TBFLAG_ANY(flags, FGT_ACTIVE, 1);
752
+ if (FIELD_EX64(env->cp15.fgt_exec[FGTREG_HFGITR], HFGITR_EL2, ERET)) {
753
+ DP_TBFLAG_A64(flags, FGT_ERET, 1);
754
+ }
755
+ if (fgt_svc(env, el)) {
756
+ DP_TBFLAG_ANY(flags, FGT_SVC, 1);
757
+ }
758
+ }
759
+
760
+ if (cpu_isar_feature(aa64_mte, env_archcpu(env))) {
761
+ /*
762
+ * Set MTE_ACTIVE if any access may be Checked, and leave clear
763
+ * if all accesses must be Unchecked:
764
+ * 1) If no TBI, then there are no tags in the address to check,
765
+ * 2) If Tag Check Override, then all accesses are Unchecked,
766
+ * 3) If Tag Check Fail == 0, then Checked access have no effect,
767
+ * 4) If no Allocation Tag Access, then all accesses are Unchecked.
768
+ */
769
+ if (allocation_tag_access_enabled(env, el, sctlr)) {
770
+ DP_TBFLAG_A64(flags, ATA, 1);
771
+ if (tbid
772
+ && !(env->pstate & PSTATE_TCO)
773
+ && (sctlr & (el == 0 ? SCTLR_TCF0 : SCTLR_TCF))) {
774
+ DP_TBFLAG_A64(flags, MTE_ACTIVE, 1);
775
+ }
776
+ }
777
+ /* And again for unprivileged accesses, if required. */
778
+ if (EX_TBFLAG_A64(flags, UNPRIV)
779
+ && tbid
780
+ && !(env->pstate & PSTATE_TCO)
781
+ && (sctlr & SCTLR_TCF0)
782
+ && allocation_tag_access_enabled(env, 0, sctlr)) {
783
+ DP_TBFLAG_A64(flags, MTE0_ACTIVE, 1);
784
+ }
785
+ /* Cache TCMA as well as TBI. */
786
+ DP_TBFLAG_A64(flags, TCMA, aa64_va_parameter_tcma(tcr, mmu_idx));
787
+ }
788
+
789
+ return rebuild_hflags_common(env, fp_el, mmu_idx, flags);
790
+}
791
+
792
+static CPUARMTBFlags rebuild_hflags_internal(CPUARMState *env)
793
+{
794
+ int el = arm_current_el(env);
795
+ int fp_el = fp_exception_el(env, el);
796
+ ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el);
797
+
798
+ if (is_a64(env)) {
799
+ return rebuild_hflags_a64(env, el, fp_el, mmu_idx);
800
+ } else if (arm_feature(env, ARM_FEATURE_M)) {
801
+ return rebuild_hflags_m32(env, fp_el, mmu_idx);
802
+ } else {
803
+ return rebuild_hflags_a32(env, fp_el, mmu_idx);
804
+ }
805
+}
806
+
807
+void arm_rebuild_hflags(CPUARMState *env)
808
+{
809
+ env->hflags = rebuild_hflags_internal(env);
810
+}
811
+
812
+/*
813
+ * If we have triggered a EL state change we can't rely on the
814
+ * translator having passed it to us, we need to recompute.
815
+ */
816
+void HELPER(rebuild_hflags_m32_newel)(CPUARMState *env)
817
+{
818
+ int el = arm_current_el(env);
819
+ int fp_el = fp_exception_el(env, el);
820
+ ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el);
821
+
822
+ env->hflags = rebuild_hflags_m32(env, fp_el, mmu_idx);
823
+}
824
+
825
+void HELPER(rebuild_hflags_m32)(CPUARMState *env, int el)
826
+{
827
+ int fp_el = fp_exception_el(env, el);
828
+ ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el);
829
+
830
+ env->hflags = rebuild_hflags_m32(env, fp_el, mmu_idx);
831
+}
832
+
833
+/*
834
+ * If we have triggered a EL state change we can't rely on the
835
+ * translator having passed it to us, we need to recompute.
836
+ */
837
+void HELPER(rebuild_hflags_a32_newel)(CPUARMState *env)
838
+{
839
+ int el = arm_current_el(env);
840
+ int fp_el = fp_exception_el(env, el);
841
+ ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el);
842
+ env->hflags = rebuild_hflags_a32(env, fp_el, mmu_idx);
843
+}
844
+
845
+void HELPER(rebuild_hflags_a32)(CPUARMState *env, int el)
846
+{
847
+ int fp_el = fp_exception_el(env, el);
848
+ ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el);
849
+
850
+ env->hflags = rebuild_hflags_a32(env, fp_el, mmu_idx);
851
+}
852
+
853
+void HELPER(rebuild_hflags_a64)(CPUARMState *env, int el)
854
+{
855
+ int fp_el = fp_exception_el(env, el);
856
+ ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el);
857
+
858
+ env->hflags = rebuild_hflags_a64(env, el, fp_el, mmu_idx);
859
+}
860
+
861
+void assert_hflags_rebuild_correctly(CPUARMState *env)
862
+{
863
+#ifdef CONFIG_DEBUG_TCG
864
+ CPUARMTBFlags c = env->hflags;
865
+ CPUARMTBFlags r = rebuild_hflags_internal(env);
866
+
867
+ if (unlikely(c.flags != r.flags || c.flags2 != r.flags2)) {
868
+ fprintf(stderr, "TCG hflags mismatch "
869
+ "(current:(0x%08x,0x" TARGET_FMT_lx ")"
870
+ " rebuilt:(0x%08x,0x" TARGET_FMT_lx ")\n",
871
+ c.flags, c.flags2, r.flags, r.flags2);
872
+ abort();
873
+ }
874
+#endif
875
+}
876
diff --git a/target/arm/tcg/meson.build b/target/arm/tcg/meson.build
877
index XXXXXXX..XXXXXXX 100644
878
--- a/target/arm/tcg/meson.build
879
+++ b/target/arm/tcg/meson.build
880
@@ -XXX,XX +XXX,XX @@ arm_ss.add(files(
881
'translate-neon.c',
882
'translate-vfp.c',
883
'crypto_helper.c',
884
+ 'hflags.c',
885
'iwmmxt_helper.c',
886
'm_helper.c',
887
'mve_helper.c',
44
--
888
--
45
2.20.1
889
2.34.1
46
890
47
891
diff view generated by jsdifflib
1
From: Gan Qixin <ganqixin@huawei.com>
1
From: Fabiano Rosas <farosas@suse.de>
2
2
3
When running device-introspect-test, a memory leak occurred in the
3
This function is needed by common code (ptw.c), so move it along with
4
exynos4210_mct_init function, so use ptimer_free() in the finalize function to
4
the other regime_* functions in internal.h. When we enable the build
5
avoid it.
5
without TCG, the tlb_helper.c file will not be present.
6
6
7
ASAN shows memory leak stack:
7
Signed-off-by: Fabiano Rosas <farosas@suse.de>
8
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Indirect leak of 96 byte(s) in 1 object(s) allocated from:
9
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
10
#0 0xffffab97e1f0 in __interceptor_calloc (/lib64/libasan.so.5+0xee1f0)
11
#1 0xffffab256800 in g_malloc0 (/lib64/libglib-2.0.so.0+0x56800)
12
#2 0xaaabf555db78 in ptimer_init /qemu/hw/core/ptimer.c:432
13
#3 0xaaabf56b01a0 in exynos4210_mct_init /qemu/hw/timer/exynos4210_mct.c:1505
14
#4 0xaaabf6339f6c in object_initialize_with_type /qemu/qom/object.c:515
15
#5 0xaaabf633a1e0 in object_new_with_type /qemu/qom/object.c:729
16
#6 0xaaabf6375e40 in qmp_device_list_properties /qemu/qom/qom-qmp-cmds.c:153
17
#7 0xaaabf653d8ec in qmp_marshal_device_list_properties /qemu/qapi/qapi-commands-qdev.c:59
18
#8 0xaaabf6587d08 in do_qmp_dispatch_bh /qemu/qapi/qmp-dispatch.c:110
19
#9 0xaaabf6552708 in aio_bh_call /qemu/util/async.c:136
20
#10 0xaaabf6552708 in aio_bh_poll /qemu/util/async.c:164
21
#11 0xaaabf655f19c in aio_dispatch /qemu/util/aio-posix.c:381
22
#12 0xaaabf65523f4 in aio_ctx_dispatch /qemu/util/async.c:306
23
24
Reported-by: Euler Robot <euler.robot@huawei.com>
25
Signed-off-by: Gan Qixin <ganqixin@huawei.com>
26
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
27
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
28
---
11
---
29
hw/timer/exynos4210_mct.c | 14 ++++++++++++++
12
target/arm/internals.h | 21 ++++++++++++++++++---
30
1 file changed, 14 insertions(+)
13
target/arm/tcg/tlb_helper.c | 18 ------------------
14
2 files changed, 18 insertions(+), 21 deletions(-)
31
15
32
diff --git a/hw/timer/exynos4210_mct.c b/hw/timer/exynos4210_mct.c
16
diff --git a/target/arm/internals.h b/target/arm/internals.h
33
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
34
--- a/hw/timer/exynos4210_mct.c
18
--- a/target/arm/internals.h
35
+++ b/hw/timer/exynos4210_mct.c
19
+++ b/target/arm/internals.h
36
@@ -XXX,XX +XXX,XX @@ static void exynos4210_mct_init(Object *obj)
20
@@ -XXX,XX +XXX,XX @@ int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx);
37
sysbus_init_mmio(dev, &s->iomem);
21
/* Return the MMU index for a v7M CPU in the specified security state */
22
ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate);
23
24
-/* Return true if the translation regime is using LPAE format page tables */
25
-bool regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx);
26
-
27
/*
28
* Return true if the stage 1 translation regime is using LPAE
29
* format page tables
30
@@ -XXX,XX +XXX,XX @@ static inline uint64_t regime_tcr(CPUARMState *env, ARMMMUIdx mmu_idx)
31
return env->cp15.tcr_el[regime_el(env, mmu_idx)];
38
}
32
}
39
33
40
+static void exynos4210_mct_finalize(Object *obj)
34
+/* Return true if the translation regime is using LPAE format page tables */
35
+static inline bool regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx)
41
+{
36
+{
42
+ int i;
37
+ int el = regime_el(env, mmu_idx);
43
+ Exynos4210MCTState *s = EXYNOS4210_MCT(obj);
38
+ if (el == 2 || arm_el_is_aa64(env, el)) {
44
+
39
+ return true;
45
+ ptimer_free(s->g_timer.ptimer_frc);
46
+
47
+ for (i = 0; i < 2; i++) {
48
+ ptimer_free(s->l_timer[i].tick_timer.ptimer_tick);
49
+ ptimer_free(s->l_timer[i].ptimer_frc);
50
+ }
40
+ }
41
+ if (arm_feature(env, ARM_FEATURE_PMSA) &&
42
+ arm_feature(env, ARM_FEATURE_V8)) {
43
+ return true;
44
+ }
45
+ if (arm_feature(env, ARM_FEATURE_LPAE)
46
+ && (regime_tcr(env, mmu_idx) & TTBCR_EAE)) {
47
+ return true;
48
+ }
49
+ return false;
51
+}
50
+}
52
+
51
+
53
static void exynos4210_mct_class_init(ObjectClass *klass, void *data)
52
/**
54
{
53
* arm_num_brps: Return number of implemented breakpoints.
55
DeviceClass *dc = DEVICE_CLASS(klass);
54
* Note that the ID register BRPS field is "number of bps - 1",
56
@@ -XXX,XX +XXX,XX @@ static const TypeInfo exynos4210_mct_info = {
55
diff --git a/target/arm/tcg/tlb_helper.c b/target/arm/tcg/tlb_helper.c
57
.parent = TYPE_SYS_BUS_DEVICE,
56
index XXXXXXX..XXXXXXX 100644
58
.instance_size = sizeof(Exynos4210MCTState),
57
--- a/target/arm/tcg/tlb_helper.c
59
.instance_init = exynos4210_mct_init,
58
+++ b/target/arm/tcg/tlb_helper.c
60
+ .instance_finalize = exynos4210_mct_finalize,
59
@@ -XXX,XX +XXX,XX @@
61
.class_init = exynos4210_mct_class_init,
60
#include "exec/helper-proto.h"
62
};
61
63
62
63
-/* Return true if the translation regime is using LPAE format page tables */
64
-bool regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx)
65
-{
66
- int el = regime_el(env, mmu_idx);
67
- if (el == 2 || arm_el_is_aa64(env, el)) {
68
- return true;
69
- }
70
- if (arm_feature(env, ARM_FEATURE_PMSA) &&
71
- arm_feature(env, ARM_FEATURE_V8)) {
72
- return true;
73
- }
74
- if (arm_feature(env, ARM_FEATURE_LPAE)
75
- && (regime_tcr(env, mmu_idx) & TTBCR_EAE)) {
76
- return true;
77
- }
78
- return false;
79
-}
80
-
81
/*
82
* Returns true if the stage 1 translation regime is using LPAE format page
83
* tables. Used when raising alignment exceptions, whose FSR changes depending
64
--
84
--
65
2.20.1
85
2.34.1
66
86
67
87
diff view generated by jsdifflib
1
From: Bin Meng <bin.meng@windriver.com>
1
From: Fabiano Rosas <farosas@suse.de>
2
2
3
At present, when booting U-Boot on QEMU sabrelite, we see:
3
When TCG is disabled this part of the code should not be reachable, so
4
wrap it with an ifdef for now.
4
5
5
Net: Board Net Initialization Failed
6
Signed-off-by: Fabiano Rosas <farosas@suse.de>
6
No ethernet found.
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
8
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
8
U-Boot scans PHY at address 4/5/6/7 (see board_eth_init() in the
9
U-Boot source: board/boundary/nitrogen6x/nitrogen6x.c). On the real
10
board, the Ethernet PHY is at address 6. Adjust this by updating the
11
"fec-phy-num" property of the fsl_imx6 SoC object.
12
13
With this change, U-Boot sees the PHY but complains MAC address:
14
15
Net: using phy at 6
16
FEC [PRIME]
17
Error: FEC address not set.
18
19
This is due to U-Boot tries to read the MAC address from the fuse,
20
which QEMU does not have any valid content filled in. However this
21
does not prevent the Ethernet from working in QEMU. We just need to
22
set up the MAC address later in the U-Boot command shell, by:
23
24
=> setenv ethaddr 00:11:22:33:44:55
25
26
Signed-off-by: Bin Meng <bin.meng@windriver.com>
27
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
28
Message-id: 20210106063504.10841-4-bmeng.cn@gmail.com
29
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
30
---
10
---
31
hw/arm/sabrelite.c | 4 ++++
11
target/arm/ptw.c | 4 ++++
32
1 file changed, 4 insertions(+)
12
1 file changed, 4 insertions(+)
33
13
34
diff --git a/hw/arm/sabrelite.c b/hw/arm/sabrelite.c
14
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
35
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
36
--- a/hw/arm/sabrelite.c
16
--- a/target/arm/ptw.c
37
+++ b/hw/arm/sabrelite.c
17
+++ b/target/arm/ptw.c
38
@@ -XXX,XX +XXX,XX @@ static void sabrelite_init(MachineState *machine)
18
@@ -XXX,XX +XXX,XX @@ static bool S1_ptw_translate(CPUARMState *env, S1Translate *ptw,
39
19
ptw->out_host = NULL;
40
s = FSL_IMX6(object_new(TYPE_FSL_IMX6));
20
ptw->out_rw = false;
41
object_property_add_child(OBJECT(machine), "soc", OBJECT(s));
21
} else {
42
+
22
+#ifdef CONFIG_TCG
43
+ /* Ethernet PHY address is 6 */
23
CPUTLBEntryFull *full;
44
+ object_property_set_int(OBJECT(s), "fec-phy-num", 6, &error_fatal);
24
int flags;
45
+
25
46
qdev_realize(DEVICE(s), NULL, &error_fatal);
26
@@ -XXX,XX +XXX,XX @@ static bool S1_ptw_translate(CPUARMState *env, S1Translate *ptw,
47
27
ptw->out_rw = full->prot & PAGE_WRITE;
48
memory_region_add_subregion(get_system_memory(), FSL_IMX6_MMDC_ADDR,
28
pte_attrs = full->pte_attrs;
29
pte_secure = full->attrs.secure;
30
+#else
31
+ g_assert_not_reached();
32
+#endif
33
}
34
35
if (regime_is_stage2(s2_mmu_idx)) {
49
--
36
--
50
2.20.1
37
2.34.1
51
38
52
39
diff view generated by jsdifflib
1
From: Bin Meng <bin.meng@windriver.com>
1
From: Fabiano Rosas <farosas@suse.de>
2
2
3
U-Boot expects PMU_MISC0 register bit 7 is set (see init_bandgap()
3
This struct has no dependencies on TCG code and it is being used in
4
in arch/arm/mach-imx/mx6/soc.c) during boot. This bit indicates the
4
target/arm/ptw.c to simplify the passing around of page table walk
5
bandgap has stabilized.
5
results. Those routines can be reached by KVM code via the gdbstub
6
breakpoint code, so take the structure out of CONFIG_TCG to make it
7
visible when building with --disable-tcg.
6
8
7
With this change, the latest upstream U-Boot (v2021.01-rc3) for imx6
9
Signed-off-by: Fabiano Rosas <farosas@suse.de>
8
sabrelite board (mx6qsabrelite_defconfig), with a slight change made
10
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
by switching CONFIG_OF_SEPARATE to CONFIG_OF_EMBED, boots to U-Boot
11
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
10
shell on QEMU with the following command:
12
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
11
12
$ qemu-system-arm -M sabrelite -smp 4 -m 1G -kernel u-boot \
13
-display none -serial null -serial stdio
14
15
Boot log below:
16
17
U-Boot 2021.01-rc3 (Dec 12 2020 - 17:40:02 +0800)
18
19
CPU: Freescale i.MX?? rev1.0 at 792 MHz
20
Reset cause: POR
21
Model: Freescale i.MX6 Quad SABRE Lite Board
22
Board: SABRE Lite
23
I2C: ready
24
DRAM: 1 GiB
25
force_idle_bus: sda=0 scl=0 sda.gp=0x5c scl.gp=0x55
26
force_idle_bus: failed to clear bus, sda=0 scl=0
27
force_idle_bus: sda=0 scl=0 sda.gp=0x6d scl.gp=0x6c
28
force_idle_bus: failed to clear bus, sda=0 scl=0
29
force_idle_bus: sda=0 scl=0 sda.gp=0xcb scl.gp=0x5
30
force_idle_bus: failed to clear bus, sda=0 scl=0
31
MMC: FSL_SDHC: 0, FSL_SDHC: 1
32
Loading Environment from MMC... *** Warning - No block device, using default environment
33
34
In: serial
35
Out: serial
36
Err: serial
37
Net: Board Net Initialization Failed
38
No ethernet found.
39
starting USB...
40
Bus usb@2184000: usb dr_mode not found
41
USB EHCI 1.00
42
Bus usb@2184200: USB EHCI 1.00
43
scanning bus usb@2184000 for devices... 1 USB Device(s) found
44
scanning bus usb@2184200 for devices... 1 USB Device(s) found
45
scanning usb for storage devices... 0 Storage Device(s) found
46
scanning usb for ethernet devices... 0 Ethernet Device(s) found
47
Hit any key to stop autoboot: 0
48
=>
49
50
Signed-off-by: Bin Meng <bin.meng@windriver.com>
51
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
52
Message-id: 20210106063504.10841-2-bmeng.cn@gmail.com
53
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
54
---
14
---
55
hw/misc/imx6_ccm.c | 2 +-
15
include/exec/cpu-defs.h | 6 ++++++
56
1 file changed, 1 insertion(+), 1 deletion(-)
16
1 file changed, 6 insertions(+)
57
17
58
diff --git a/hw/misc/imx6_ccm.c b/hw/misc/imx6_ccm.c
18
diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h
59
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
60
--- a/hw/misc/imx6_ccm.c
20
--- a/include/exec/cpu-defs.h
61
+++ b/hw/misc/imx6_ccm.c
21
+++ b/include/exec/cpu-defs.h
62
@@ -XXX,XX +XXX,XX @@ static void imx6_ccm_reset(DeviceState *dev)
22
@@ -XXX,XX +XXX,XX @@ typedef struct CPUTLBEntry {
63
s->analog[PMU_REG_3P0] = 0x00000F74;
23
64
s->analog[PMU_REG_2P5] = 0x00005071;
24
QEMU_BUILD_BUG_ON(sizeof(CPUTLBEntry) != (1 << CPU_TLB_ENTRY_BITS));
65
s->analog[PMU_REG_CORE] = 0x00402010;
25
66
- s->analog[PMU_MISC0] = 0x04000000;
26
+
67
+ s->analog[PMU_MISC0] = 0x04000080;
27
+#endif /* !CONFIG_USER_ONLY && CONFIG_TCG */
68
s->analog[PMU_MISC1] = 0x00000000;
28
+
69
s->analog[PMU_MISC2] = 0x00272727;
29
+#if !defined(CONFIG_USER_ONLY)
70
30
/*
31
* The full TLB entry, which is not accessed by generated TCG code,
32
* so the layout is not as critical as that of CPUTLBEntry. This is
33
@@ -XXX,XX +XXX,XX @@ typedef struct CPUTLBEntryFull {
34
TARGET_PAGE_ENTRY_EXTRA
35
#endif
36
} CPUTLBEntryFull;
37
+#endif /* !CONFIG_USER_ONLY */
38
39
+#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG)
40
/*
41
* Data elements that are per MMU mode, minus the bits accessed by
42
* the TCG fast path.
71
--
43
--
72
2.20.1
44
2.34.1
73
45
74
46
diff view generated by jsdifflib
1
From: Gan Qixin <ganqixin@huawei.com>
1
From: Fabiano Rosas <farosas@suse.de>
2
2
3
When running device-introspect-test, a memory leak occurred in the
3
This test currently fails when run on a host for which the QEMU target
4
exynos4210_pwm_init function, so use ptimer_free() in the finalize function to
4
has no default machine set:
5
avoid it.
6
5
7
ASAN shows memory leak stack:
6
ERROR| Output: qemu-system-aarch64: No machine specified, and there is
7
no default
8
8
9
Indirect leak of 240 byte(s) in 5 object(s) allocated from:
9
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
10
#0 0xffffab97e1f0 in __interceptor_calloc (/lib64/libasan.so.5+0xee1f0)
10
Signed-off-by: Fabiano Rosas <farosas@suse.de>
11
#1 0xffffab256800 in g_malloc0 (/lib64/libglib-2.0.so.0+0x56800)
12
#2 0xaaabf555db84 in timer_new_full /qemu/include/qemu/timer.h:523
13
#3 0xaaabf555db84 in timer_new /qemu/include/qemu/timer.h:544
14
#4 0xaaabf555db84 in timer_new_ns /qemu/include/qemu/timer.h:562
15
#5 0xaaabf555db84 in ptimer_init /qemu/hw/core/ptimer.c:433
16
#6 0xaaabf56a36cc in exynos4210_pwm_init /qemu/hw/timer/exynos4210_pwm.c:401
17
#7 0xaaabf6339f6c in object_initialize_with_type /qemu/qom/object.c:515
18
#8 0xaaabf633a1e0 in object_new_with_type /qemu/qom/object.c:729
19
#9 0xaaabf6375e40 in qmp_device_list_properties /qemu/qom/qom-qmp-cmds.c:153
20
#10 0xaaabf653d8ec in qmp_marshal_device_list_properties /qemu/qapi/qapi-commands-qdev.c:59
21
#11 0xaaabf6587d08 in do_qmp_dispatch_bh /qemu/qapi/qmp-dispatch.c:110
22
#12 0xaaabf6552708 in aio_bh_call /qemu/util/async.c:136
23
24
Reported-by: Euler Robot <euler.robot@huawei.com>
25
Signed-off-by: Gan Qixin <ganqixin@huawei.com>
26
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
27
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
28
---
12
---
29
hw/timer/exynos4210_pwm.c | 11 +++++++++++
13
tests/avocado/version.py | 1 +
30
1 file changed, 11 insertions(+)
14
1 file changed, 1 insertion(+)
31
15
32
diff --git a/hw/timer/exynos4210_pwm.c b/hw/timer/exynos4210_pwm.c
16
diff --git a/tests/avocado/version.py b/tests/avocado/version.py
33
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
34
--- a/hw/timer/exynos4210_pwm.c
18
--- a/tests/avocado/version.py
35
+++ b/hw/timer/exynos4210_pwm.c
19
+++ b/tests/avocado/version.py
36
@@ -XXX,XX +XXX,XX @@ static void exynos4210_pwm_init(Object *obj)
20
@@ -XXX,XX +XXX,XX @@
37
sysbus_init_mmio(dev, &s->iomem);
21
class Version(QemuSystemTest):
38
}
22
"""
39
23
:avocado: tags=quick
40
+static void exynos4210_pwm_finalize(Object *obj)
24
+ :avocado: tags=machine:none
41
+{
25
"""
42
+ Exynos4210PWMState *s = EXYNOS4210_PWM(obj);
26
def test_qmp_human_info_version(self):
43
+ int i;
27
self.vm.add_args('-nodefaults')
44
+
45
+ for (i = 0; i < EXYNOS4210_PWM_TIMERS_NUM; i++) {
46
+ ptimer_free(s->timer[i].ptimer);
47
+ }
48
+}
49
+
50
static void exynos4210_pwm_class_init(ObjectClass *klass, void *data)
51
{
52
DeviceClass *dc = DEVICE_CLASS(klass);
53
@@ -XXX,XX +XXX,XX @@ static const TypeInfo exynos4210_pwm_info = {
54
.parent = TYPE_SYS_BUS_DEVICE,
55
.instance_size = sizeof(Exynos4210PWMState),
56
.instance_init = exynos4210_pwm_init,
57
+ .instance_finalize = exynos4210_pwm_finalize,
58
.class_init = exynos4210_pwm_class_init,
59
};
60
61
--
28
--
62
2.20.1
29
2.34.1
63
30
64
31
diff view generated by jsdifflib
1
Now that we have implemented all the features needed by the v8.1M
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
2
architecture, we can add the model of the Cortex-M55. This is the
3
configuration without MVE support; we'll add MVE later.
4
2
3
Since &I2C_SLAVE(dev)->qdev == dev, no need to go back and
4
forth with QOM type casting. Directly use 'dev'.
5
6
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20230220115114.25237-2-philmd@linaro.org
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20201210201433.26262-5-peter.maydell@linaro.org
8
---
10
---
9
target/arm/cpu_tcg.c | 42 ++++++++++++++++++++++++++++++++++++++++++
11
hw/gpio/max7310.c | 5 ++---
10
1 file changed, 42 insertions(+)
12
1 file changed, 2 insertions(+), 3 deletions(-)
11
13
12
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
14
diff --git a/hw/gpio/max7310.c b/hw/gpio/max7310.c
13
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
14
--- a/target/arm/cpu_tcg.c
16
--- a/hw/gpio/max7310.c
15
+++ b/target/arm/cpu_tcg.c
17
+++ b/hw/gpio/max7310.c
16
@@ -XXX,XX +XXX,XX @@ static void cortex_m33_initfn(Object *obj)
18
@@ -XXX,XX +XXX,XX @@ static void max7310_gpio_set(void *opaque, int line, int level)
17
cpu->ctr = 0x8000c000;
19
* but also accepts sequences that are not SMBus so return an I2C device. */
20
static void max7310_realize(DeviceState *dev, Error **errp)
21
{
22
- I2CSlave *i2c = I2C_SLAVE(dev);
23
MAX7310State *s = MAX7310(dev);
24
25
- qdev_init_gpio_in(&i2c->qdev, max7310_gpio_set, 8);
26
- qdev_init_gpio_out(&i2c->qdev, s->handler, 8);
27
+ qdev_init_gpio_in(dev, max7310_gpio_set, ARRAY_SIZE(s->handler));
28
+ qdev_init_gpio_out(dev, s->handler, ARRAY_SIZE(s->handler));
18
}
29
}
19
30
20
+static void cortex_m55_initfn(Object *obj)
31
static void max7310_class_init(ObjectClass *klass, void *data)
21
+{
22
+ ARMCPU *cpu = ARM_CPU(obj);
23
+
24
+ set_feature(&cpu->env, ARM_FEATURE_V8);
25
+ set_feature(&cpu->env, ARM_FEATURE_V8_1M);
26
+ set_feature(&cpu->env, ARM_FEATURE_M);
27
+ set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
28
+ set_feature(&cpu->env, ARM_FEATURE_M_SECURITY);
29
+ set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
30
+ cpu->midr = 0x410fd221; /* r0p1 */
31
+ cpu->revidr = 0;
32
+ cpu->pmsav7_dregion = 16;
33
+ cpu->sau_sregion = 8;
34
+ /*
35
+ * These are the MVFR* values for the FPU, no MVE configuration;
36
+ * we will update them later when we implement MVE
37
+ */
38
+ cpu->isar.mvfr0 = 0x10110221;
39
+ cpu->isar.mvfr1 = 0x12100011;
40
+ cpu->isar.mvfr2 = 0x00000040;
41
+ cpu->isar.id_pfr0 = 0x20000030;
42
+ cpu->isar.id_pfr1 = 0x00000230;
43
+ cpu->isar.id_dfr0 = 0x10200000;
44
+ cpu->id_afr0 = 0x00000000;
45
+ cpu->isar.id_mmfr0 = 0x00111040;
46
+ cpu->isar.id_mmfr1 = 0x00000000;
47
+ cpu->isar.id_mmfr2 = 0x01000000;
48
+ cpu->isar.id_mmfr3 = 0x00000011;
49
+ cpu->isar.id_isar0 = 0x01103110;
50
+ cpu->isar.id_isar1 = 0x02212000;
51
+ cpu->isar.id_isar2 = 0x20232232;
52
+ cpu->isar.id_isar3 = 0x01111131;
53
+ cpu->isar.id_isar4 = 0x01310132;
54
+ cpu->isar.id_isar5 = 0x00000000;
55
+ cpu->isar.id_isar6 = 0x00000000;
56
+ cpu->clidr = 0x00000000; /* caches not implemented */
57
+ cpu->ctr = 0x8303c003;
58
+}
59
+
60
static const ARMCPRegInfo cortexr5_cp_reginfo[] = {
61
/* Dummy the TCM region regs for the moment */
62
{ .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0,
63
@@ -XXX,XX +XXX,XX @@ static const ARMCPUInfo arm_tcg_cpus[] = {
64
.class_init = arm_v7m_class_init },
65
{ .name = "cortex-m33", .initfn = cortex_m33_initfn,
66
.class_init = arm_v7m_class_init },
67
+ { .name = "cortex-m55", .initfn = cortex_m55_initfn,
68
+ .class_init = arm_v7m_class_init },
69
{ .name = "cortex-r5", .initfn = cortex_r5_initfn },
70
{ .name = "cortex-r5f", .initfn = cortex_r5f_initfn },
71
{ .name = "ti925t", .initfn = ti925t_initfn },
72
--
32
--
73
2.20.1
33
2.34.1
74
34
75
35
diff view generated by jsdifflib
1
From: Gan Qixin <ganqixin@huawei.com>
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
2
2
3
When running device-introspect-test, a memory leak occurred in the
3
pl011_create() is only used in DeviceRealize handlers,
4
exynos4210_rtc_init function, so use ptimer_free() in the finalize function to
4
not a hot-path. Inlining is not justified.
5
avoid it.
6
5
7
ASAN shows memory leak stack:
6
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
8
7
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
9
Indirect leak of 96 byte(s) in 1 object(s) allocated from:
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
#0 0xffffab97e1f0 in __interceptor_calloc (/lib64/libasan.so.5+0xee1f0)
9
Message-id: 20230220115114.25237-3-philmd@linaro.org
11
#1 0xffffab256800 in g_malloc0 (/lib64/libglib-2.0.so.0+0x56800)
12
#2 0xaaabf555db78 in ptimer_init /qemu/hw/core/ptimer.c:432
13
#3 0xaaabf57b3934 in exynos4210_rtc_init /qemu/hw/rtc/exynos4210_rtc.c:567
14
#4 0xaaabf6339f6c in object_initialize_with_type /qemu/qom/object.c:515
15
#5 0xaaabf633a1e0 in object_new_with_type /qemu/qom/object.c:729
16
#6 0xaaabf6375e40 in qmp_device_list_properties /qemu/qom/qom-qmp-cmds.c:153
17
#7 0xaaabf653d8ec in qmp_marshal_device_list_properties /qemu/qapi/qapi-commands-qdev.c:59
18
#8 0xaaabf6587d08 in do_qmp_dispatch_bh /qemu/qapi/qmp-dispatch.c:110
19
#9 0xaaabf6552708 in aio_bh_call /qemu/util/async.c:136
20
#10 0xaaabf6552708 in aio_bh_poll /qemu/util/async.c:164
21
#11 0xaaabf655f19c in aio_dispatch /qemu/util/aio-posix.c:381
22
#12 0xaaabf65523f4 in aio_ctx_dispatch /qemu/util/async.c:306
23
24
Reported-by: Euler Robot <euler.robot@huawei.com>
25
Signed-off-by: Gan Qixin <ganqixin@huawei.com>
26
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
27
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
28
---
11
---
29
hw/rtc/exynos4210_rtc.c | 9 +++++++++
12
include/hw/char/pl011.h | 19 +------------------
30
1 file changed, 9 insertions(+)
13
hw/char/pl011.c | 17 +++++++++++++++++
14
2 files changed, 18 insertions(+), 18 deletions(-)
31
15
32
diff --git a/hw/rtc/exynos4210_rtc.c b/hw/rtc/exynos4210_rtc.c
16
diff --git a/include/hw/char/pl011.h b/include/hw/char/pl011.h
33
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
34
--- a/hw/rtc/exynos4210_rtc.c
18
--- a/include/hw/char/pl011.h
35
+++ b/hw/rtc/exynos4210_rtc.c
19
+++ b/include/hw/char/pl011.h
36
@@ -XXX,XX +XXX,XX @@ static void exynos4210_rtc_init(Object *obj)
20
@@ -XXX,XX +XXX,XX @@
37
sysbus_init_mmio(dev, &s->iomem);
21
#ifndef HW_PL011_H
38
}
22
#define HW_PL011_H
39
23
40
+static void exynos4210_rtc_finalize(Object *obj)
24
-#include "hw/qdev-properties.h"
25
#include "hw/sysbus.h"
26
#include "chardev/char-fe.h"
27
-#include "qapi/error.h"
28
#include "qom/object.h"
29
30
#define TYPE_PL011 "pl011"
31
@@ -XXX,XX +XXX,XX @@ struct PL011State {
32
const unsigned char *id;
33
};
34
35
-static inline DeviceState *pl011_create(hwaddr addr,
36
- qemu_irq irq,
37
- Chardev *chr)
38
-{
39
- DeviceState *dev;
40
- SysBusDevice *s;
41
-
42
- dev = qdev_new("pl011");
43
- s = SYS_BUS_DEVICE(dev);
44
- qdev_prop_set_chr(dev, "chardev", chr);
45
- sysbus_realize_and_unref(s, &error_fatal);
46
- sysbus_mmio_map(s, 0, addr);
47
- sysbus_connect_irq(s, 0, irq);
48
-
49
- return dev;
50
-}
51
+DeviceState *pl011_create(hwaddr addr, qemu_irq irq, Chardev *chr);
52
53
static inline DeviceState *pl011_luminary_create(hwaddr addr,
54
qemu_irq irq,
55
diff --git a/hw/char/pl011.c b/hw/char/pl011.c
56
index XXXXXXX..XXXXXXX 100644
57
--- a/hw/char/pl011.c
58
+++ b/hw/char/pl011.c
59
@@ -XXX,XX +XXX,XX @@
60
*/
61
62
#include "qemu/osdep.h"
63
+#include "qapi/error.h"
64
#include "hw/char/pl011.h"
65
#include "hw/irq.h"
66
#include "hw/sysbus.h"
67
#include "hw/qdev-clock.h"
68
+#include "hw/qdev-properties.h"
69
#include "hw/qdev-properties-system.h"
70
#include "migration/vmstate.h"
71
#include "chardev/char-fe.h"
72
@@ -XXX,XX +XXX,XX @@
73
#include "qemu/module.h"
74
#include "trace.h"
75
76
+DeviceState *pl011_create(hwaddr addr, qemu_irq irq, Chardev *chr)
41
+{
77
+{
42
+ Exynos4210RTCState *s = EXYNOS4210_RTC(obj);
78
+ DeviceState *dev;
79
+ SysBusDevice *s;
43
+
80
+
44
+ ptimer_free(s->ptimer);
81
+ dev = qdev_new("pl011");
45
+ ptimer_free(s->ptimer_1Hz);
82
+ s = SYS_BUS_DEVICE(dev);
83
+ qdev_prop_set_chr(dev, "chardev", chr);
84
+ sysbus_realize_and_unref(s, &error_fatal);
85
+ sysbus_mmio_map(s, 0, addr);
86
+ sysbus_connect_irq(s, 0, irq);
87
+
88
+ return dev;
46
+}
89
+}
47
+
90
+
48
static void exynos4210_rtc_class_init(ObjectClass *klass, void *data)
91
#define PL011_INT_TX 0x20
49
{
92
#define PL011_INT_RX 0x10
50
DeviceClass *dc = DEVICE_CLASS(klass);
51
@@ -XXX,XX +XXX,XX @@ static const TypeInfo exynos4210_rtc_info = {
52
.parent = TYPE_SYS_BUS_DEVICE,
53
.instance_size = sizeof(Exynos4210RTCState),
54
.instance_init = exynos4210_rtc_init,
55
+ .instance_finalize = exynos4210_rtc_finalize,
56
.class_init = exynos4210_rtc_class_init,
57
};
58
93
59
--
94
--
60
2.20.1
95
2.34.1
61
96
62
97
diff view generated by jsdifflib
1
This commit is the result of running the timer-del-timer-free.cocci
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
2
script on the whole source tree.
3
2
3
pl011_luminary_create() is only used for the Stellaris board,
4
open-code it.
5
6
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
7
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20230220115114.25237-4-philmd@linaro.org
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Acked-by: Corey Minyard <cminyard@mvista.com>
6
Acked-by: Paolo Bonzini <pbonzini@redhat.com>
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20201215154107.3255-4-peter.maydell@linaro.org
10
---
11
---
11
block/iscsi.c | 2 --
12
include/hw/char/pl011.h | 17 -----------------
12
block/nbd.c | 1 -
13
hw/arm/stellaris.c | 11 ++++++++---
13
block/qcow2.c | 1 -
14
2 files changed, 8 insertions(+), 20 deletions(-)
14
hw/block/nvme.c | 2 --
15
hw/char/serial.c | 2 --
16
hw/char/virtio-serial-bus.c | 2 --
17
hw/ide/core.c | 1 -
18
hw/input/hid.c | 1 -
19
hw/intc/apic.c | 1 -
20
hw/intc/ioapic.c | 1 -
21
hw/ipmi/ipmi_bmc_extern.c | 1 -
22
hw/net/e1000.c | 3 ---
23
hw/net/e1000e_core.c | 8 --------
24
hw/net/pcnet-pci.c | 1 -
25
hw/net/rtl8139.c | 1 -
26
hw/net/spapr_llan.c | 1 -
27
hw/net/virtio-net.c | 2 --
28
hw/s390x/s390-pci-inst.c | 1 -
29
hw/sd/sd.c | 1 -
30
hw/sd/sdhci.c | 2 --
31
hw/usb/dev-hub.c | 1 -
32
hw/usb/hcd-ehci.c | 1 -
33
hw/usb/hcd-ohci-pci.c | 1 -
34
hw/usb/hcd-uhci.c | 1 -
35
hw/usb/hcd-xhci.c | 1 -
36
hw/usb/redirect.c | 1 -
37
hw/vfio/display.c | 1 -
38
hw/virtio/vhost-vsock-common.c | 1 -
39
hw/virtio/virtio-balloon.c | 1 -
40
hw/virtio/virtio-rng.c | 1 -
41
hw/watchdog/wdt_diag288.c | 1 -
42
hw/watchdog/wdt_i6300esb.c | 1 -
43
migration/colo.c | 1 -
44
monitor/hmp-cmds.c | 1 -
45
net/announce.c | 1 -
46
net/colo-compare.c | 1 -
47
net/slirp.c | 1 -
48
replay/replay-debugging.c | 1 -
49
target/s390x/cpu.c | 2 --
50
ui/console.c | 1 -
51
ui/spice-core.c | 1 -
52
util/throttle.c | 1 -
53
42 files changed, 58 deletions(-)
54
15
55
diff --git a/block/iscsi.c b/block/iscsi.c
16
diff --git a/include/hw/char/pl011.h b/include/hw/char/pl011.h
56
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
57
--- a/block/iscsi.c
18
--- a/include/hw/char/pl011.h
58
+++ b/block/iscsi.c
19
+++ b/include/hw/char/pl011.h
59
@@ -XXX,XX +XXX,XX @@ static void iscsi_detach_aio_context(BlockDriverState *bs)
20
@@ -XXX,XX +XXX,XX @@ struct PL011State {
60
iscsilun->events = 0;
21
61
22
DeviceState *pl011_create(hwaddr addr, qemu_irq irq, Chardev *chr);
62
if (iscsilun->nop_timer) {
23
63
- timer_del(iscsilun->nop_timer);
24
-static inline DeviceState *pl011_luminary_create(hwaddr addr,
64
timer_free(iscsilun->nop_timer);
25
- qemu_irq irq,
65
iscsilun->nop_timer = NULL;
26
- Chardev *chr)
66
}
27
-{
67
if (iscsilun->event_timer) {
28
- DeviceState *dev;
68
- timer_del(iscsilun->event_timer);
29
- SysBusDevice *s;
69
timer_free(iscsilun->event_timer);
30
-
70
iscsilun->event_timer = NULL;
31
- dev = qdev_new("pl011_luminary");
71
}
32
- s = SYS_BUS_DEVICE(dev);
72
diff --git a/block/nbd.c b/block/nbd.c
33
- qdev_prop_set_chr(dev, "chardev", chr);
34
- sysbus_realize_and_unref(s, &error_fatal);
35
- sysbus_mmio_map(s, 0, addr);
36
- sysbus_connect_irq(s, 0, irq);
37
-
38
- return dev;
39
-}
40
-
41
#endif
42
diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
73
index XXXXXXX..XXXXXXX 100644
43
index XXXXXXX..XXXXXXX 100644
74
--- a/block/nbd.c
44
--- a/hw/arm/stellaris.c
75
+++ b/block/nbd.c
45
+++ b/hw/arm/stellaris.c
76
@@ -XXX,XX +XXX,XX @@ static void nbd_recv_coroutines_wake_all(BDRVNBDState *s)
46
@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
77
static void reconnect_delay_timer_del(BDRVNBDState *s)
47
78
{
48
for (i = 0; i < 4; i++) {
79
if (s->reconnect_delay_timer) {
49
if (board->dc2 & (1 << i)) {
80
- timer_del(s->reconnect_delay_timer);
50
- pl011_luminary_create(0x4000c000 + i * 0x1000,
81
timer_free(s->reconnect_delay_timer);
51
- qdev_get_gpio_in(nvic, uart_irq[i]),
82
s->reconnect_delay_timer = NULL;
52
- serial_hd(i));
83
}
53
+ SysBusDevice *sbd;
84
diff --git a/block/qcow2.c b/block/qcow2.c
54
+
85
index XXXXXXX..XXXXXXX 100644
55
+ dev = qdev_new("pl011_luminary");
86
--- a/block/qcow2.c
56
+ sbd = SYS_BUS_DEVICE(dev);
87
+++ b/block/qcow2.c
57
+ qdev_prop_set_chr(dev, "chardev", serial_hd(i));
88
@@ -XXX,XX +XXX,XX @@ static void cache_clean_timer_del(BlockDriverState *bs)
58
+ sysbus_realize_and_unref(sbd, &error_fatal);
89
{
59
+ sysbus_mmio_map(sbd, 0, 0x4000c000 + i * 0x1000);
90
BDRVQcow2State *s = bs->opaque;
60
+ sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(nvic, uart_irq[i]));
91
if (s->cache_clean_timer) {
92
- timer_del(s->cache_clean_timer);
93
timer_free(s->cache_clean_timer);
94
s->cache_clean_timer = NULL;
95
}
96
diff --git a/hw/block/nvme.c b/hw/block/nvme.c
97
index XXXXXXX..XXXXXXX 100644
98
--- a/hw/block/nvme.c
99
+++ b/hw/block/nvme.c
100
@@ -XXX,XX +XXX,XX @@ static uint16_t nvme_io_cmd(NvmeCtrl *n, NvmeRequest *req)
101
static void nvme_free_sq(NvmeSQueue *sq, NvmeCtrl *n)
102
{
103
n->sq[sq->sqid] = NULL;
104
- timer_del(sq->timer);
105
timer_free(sq->timer);
106
g_free(sq->io_req);
107
if (sq->sqid) {
108
@@ -XXX,XX +XXX,XX @@ static uint16_t nvme_get_log(NvmeCtrl *n, NvmeRequest *req)
109
static void nvme_free_cq(NvmeCQueue *cq, NvmeCtrl *n)
110
{
111
n->cq[cq->cqid] = NULL;
112
- timer_del(cq->timer);
113
timer_free(cq->timer);
114
msix_vector_unuse(&n->parent_obj, cq->vector);
115
if (cq->cqid) {
116
diff --git a/hw/char/serial.c b/hw/char/serial.c
117
index XXXXXXX..XXXXXXX 100644
118
--- a/hw/char/serial.c
119
+++ b/hw/char/serial.c
120
@@ -XXX,XX +XXX,XX @@ static void serial_unrealize(DeviceState *dev)
121
122
qemu_chr_fe_deinit(&s->chr, false);
123
124
- timer_del(s->modem_status_poll);
125
timer_free(s->modem_status_poll);
126
127
- timer_del(s->fifo_timeout_timer);
128
timer_free(s->fifo_timeout_timer);
129
130
fifo8_destroy(&s->recv_fifo);
131
diff --git a/hw/char/virtio-serial-bus.c b/hw/char/virtio-serial-bus.c
132
index XXXXXXX..XXXXXXX 100644
133
--- a/hw/char/virtio-serial-bus.c
134
+++ b/hw/char/virtio-serial-bus.c
135
@@ -XXX,XX +XXX,XX @@ static void virtio_serial_post_load_timer_cb(void *opaque)
136
}
61
}
137
}
62
}
138
g_free(s->post_load->connected);
63
if (board->dc2 & (1 << 4)) {
139
- timer_del(s->post_load->timer);
140
timer_free(s->post_load->timer);
141
g_free(s->post_load);
142
s->post_load = NULL;
143
@@ -XXX,XX +XXX,XX @@ static void virtio_serial_device_unrealize(DeviceState *dev)
144
g_free(vser->ports_map);
145
if (vser->post_load) {
146
g_free(vser->post_load->connected);
147
- timer_del(vser->post_load->timer);
148
timer_free(vser->post_load->timer);
149
g_free(vser->post_load);
150
}
151
diff --git a/hw/ide/core.c b/hw/ide/core.c
152
index XXXXXXX..XXXXXXX 100644
153
--- a/hw/ide/core.c
154
+++ b/hw/ide/core.c
155
@@ -XXX,XX +XXX,XX @@ void ide_init2(IDEBus *bus, qemu_irq irq)
156
157
void ide_exit(IDEState *s)
158
{
159
- timer_del(s->sector_write_timer);
160
timer_free(s->sector_write_timer);
161
qemu_vfree(s->smart_selftest_data);
162
qemu_vfree(s->io_buffer);
163
diff --git a/hw/input/hid.c b/hw/input/hid.c
164
index XXXXXXX..XXXXXXX 100644
165
--- a/hw/input/hid.c
166
+++ b/hw/input/hid.c
167
@@ -XXX,XX +XXX,XX @@ static void hid_idle_timer(void *opaque)
168
static void hid_del_idle_timer(HIDState *hs)
169
{
170
if (hs->idle_timer) {
171
- timer_del(hs->idle_timer);
172
timer_free(hs->idle_timer);
173
hs->idle_timer = NULL;
174
}
175
diff --git a/hw/intc/apic.c b/hw/intc/apic.c
176
index XXXXXXX..XXXXXXX 100644
177
--- a/hw/intc/apic.c
178
+++ b/hw/intc/apic.c
179
@@ -XXX,XX +XXX,XX @@ static void apic_unrealize(DeviceState *dev)
180
{
181
APICCommonState *s = APIC(dev);
182
183
- timer_del(s->timer);
184
timer_free(s->timer);
185
local_apics[s->id] = NULL;
186
}
187
diff --git a/hw/intc/ioapic.c b/hw/intc/ioapic.c
188
index XXXXXXX..XXXXXXX 100644
189
--- a/hw/intc/ioapic.c
190
+++ b/hw/intc/ioapic.c
191
@@ -XXX,XX +XXX,XX @@ static void ioapic_unrealize(DeviceState *dev)
192
{
193
IOAPICCommonState *s = IOAPIC_COMMON(dev);
194
195
- timer_del(s->delayed_ioapic_service_timer);
196
timer_free(s->delayed_ioapic_service_timer);
197
}
198
199
diff --git a/hw/ipmi/ipmi_bmc_extern.c b/hw/ipmi/ipmi_bmc_extern.c
200
index XXXXXXX..XXXXXXX 100644
201
--- a/hw/ipmi/ipmi_bmc_extern.c
202
+++ b/hw/ipmi/ipmi_bmc_extern.c
203
@@ -XXX,XX +XXX,XX @@ static void ipmi_bmc_extern_finalize(Object *obj)
204
{
205
IPMIBmcExtern *ibe = IPMI_BMC_EXTERN(obj);
206
207
- timer_del(ibe->extern_timer);
208
timer_free(ibe->extern_timer);
209
}
210
211
diff --git a/hw/net/e1000.c b/hw/net/e1000.c
212
index XXXXXXX..XXXXXXX 100644
213
--- a/hw/net/e1000.c
214
+++ b/hw/net/e1000.c
215
@@ -XXX,XX +XXX,XX @@ pci_e1000_uninit(PCIDevice *dev)
216
{
217
E1000State *d = E1000(dev);
218
219
- timer_del(d->autoneg_timer);
220
timer_free(d->autoneg_timer);
221
- timer_del(d->mit_timer);
222
timer_free(d->mit_timer);
223
- timer_del(d->flush_queue_timer);
224
timer_free(d->flush_queue_timer);
225
qemu_del_nic(d->nic);
226
}
227
diff --git a/hw/net/e1000e_core.c b/hw/net/e1000e_core.c
228
index XXXXXXX..XXXXXXX 100644
229
--- a/hw/net/e1000e_core.c
230
+++ b/hw/net/e1000e_core.c
231
@@ -XXX,XX +XXX,XX @@ e1000e_intrmgr_pci_unint(E1000ECore *core)
232
{
233
int i;
234
235
- timer_del(core->radv.timer);
236
timer_free(core->radv.timer);
237
- timer_del(core->rdtr.timer);
238
timer_free(core->rdtr.timer);
239
- timer_del(core->raid.timer);
240
timer_free(core->raid.timer);
241
242
- timer_del(core->tadv.timer);
243
timer_free(core->tadv.timer);
244
- timer_del(core->tidv.timer);
245
timer_free(core->tidv.timer);
246
247
- timer_del(core->itr.timer);
248
timer_free(core->itr.timer);
249
250
for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) {
251
- timer_del(core->eitr[i].timer);
252
timer_free(core->eitr[i].timer);
253
}
254
}
255
@@ -XXX,XX +XXX,XX @@ e1000e_core_pci_uninit(E1000ECore *core)
256
{
257
int i;
258
259
- timer_del(core->autoneg_timer);
260
timer_free(core->autoneg_timer);
261
262
e1000e_intrmgr_pci_unint(core);
263
diff --git a/hw/net/pcnet-pci.c b/hw/net/pcnet-pci.c
264
index XXXXXXX..XXXXXXX 100644
265
--- a/hw/net/pcnet-pci.c
266
+++ b/hw/net/pcnet-pci.c
267
@@ -XXX,XX +XXX,XX @@ static void pci_pcnet_uninit(PCIDevice *dev)
268
PCIPCNetState *d = PCI_PCNET(dev);
269
270
qemu_free_irq(d->state.irq);
271
- timer_del(d->state.poll_timer);
272
timer_free(d->state.poll_timer);
273
qemu_del_nic(d->state.nic);
274
}
275
diff --git a/hw/net/rtl8139.c b/hw/net/rtl8139.c
276
index XXXXXXX..XXXXXXX 100644
277
--- a/hw/net/rtl8139.c
278
+++ b/hw/net/rtl8139.c
279
@@ -XXX,XX +XXX,XX @@ static void pci_rtl8139_uninit(PCIDevice *dev)
280
281
g_free(s->cplus_txbuffer);
282
s->cplus_txbuffer = NULL;
283
- timer_del(s->timer);
284
timer_free(s->timer);
285
qemu_del_nic(s->nic);
286
}
287
diff --git a/hw/net/spapr_llan.c b/hw/net/spapr_llan.c
288
index XXXXXXX..XXXXXXX 100644
289
--- a/hw/net/spapr_llan.c
290
+++ b/hw/net/spapr_llan.c
291
@@ -XXX,XX +XXX,XX @@ static void spapr_vlan_instance_finalize(Object *obj)
292
}
293
294
if (dev->rxp_timer) {
295
- timer_del(dev->rxp_timer);
296
timer_free(dev->rxp_timer);
297
}
298
}
299
diff --git a/hw/net/virtio-net.c b/hw/net/virtio-net.c
300
index XXXXXXX..XXXXXXX 100644
301
--- a/hw/net/virtio-net.c
302
+++ b/hw/net/virtio-net.c
303
@@ -XXX,XX +XXX,XX @@ static void virtio_net_rsc_cleanup(VirtIONet *n)
304
g_free(seg);
305
}
306
307
- timer_del(chain->drain_timer);
308
timer_free(chain->drain_timer);
309
QTAILQ_REMOVE(&n->rsc_chains, chain, next);
310
g_free(chain);
311
@@ -XXX,XX +XXX,XX @@ static void virtio_net_del_queue(VirtIONet *n, int index)
312
313
virtio_del_queue(vdev, index * 2);
314
if (q->tx_timer) {
315
- timer_del(q->tx_timer);
316
timer_free(q->tx_timer);
317
q->tx_timer = NULL;
318
} else {
319
diff --git a/hw/s390x/s390-pci-inst.c b/hw/s390x/s390-pci-inst.c
320
index XXXXXXX..XXXXXXX 100644
321
--- a/hw/s390x/s390-pci-inst.c
322
+++ b/hw/s390x/s390-pci-inst.c
323
@@ -XXX,XX +XXX,XX @@ void pci_dereg_ioat(S390PCIIOMMU *iommu)
324
void fmb_timer_free(S390PCIBusDevice *pbdev)
325
{
326
if (pbdev->fmb_timer) {
327
- timer_del(pbdev->fmb_timer);
328
timer_free(pbdev->fmb_timer);
329
pbdev->fmb_timer = NULL;
330
}
331
diff --git a/hw/sd/sd.c b/hw/sd/sd.c
332
index XXXXXXX..XXXXXXX 100644
333
--- a/hw/sd/sd.c
334
+++ b/hw/sd/sd.c
335
@@ -XXX,XX +XXX,XX @@ static void sd_instance_finalize(Object *obj)
336
{
337
SDState *sd = SD_CARD(obj);
338
339
- timer_del(sd->ocr_power_timer);
340
timer_free(sd->ocr_power_timer);
341
}
342
343
diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
344
index XXXXXXX..XXXXXXX 100644
345
--- a/hw/sd/sdhci.c
346
+++ b/hw/sd/sdhci.c
347
@@ -XXX,XX +XXX,XX @@ void sdhci_initfn(SDHCIState *s)
348
349
void sdhci_uninitfn(SDHCIState *s)
350
{
351
- timer_del(s->insert_timer);
352
timer_free(s->insert_timer);
353
- timer_del(s->transfer_timer);
354
timer_free(s->transfer_timer);
355
356
g_free(s->fifo_buffer);
357
diff --git a/hw/usb/dev-hub.c b/hw/usb/dev-hub.c
358
index XXXXXXX..XXXXXXX 100644
359
--- a/hw/usb/dev-hub.c
360
+++ b/hw/usb/dev-hub.c
361
@@ -XXX,XX +XXX,XX @@ static void usb_hub_unrealize(USBDevice *dev)
362
&s->ports[i].port);
363
}
364
365
- timer_del(s->port_timer);
366
timer_free(s->port_timer);
367
}
368
369
diff --git a/hw/usb/hcd-ehci.c b/hw/usb/hcd-ehci.c
370
index XXXXXXX..XXXXXXX 100644
371
--- a/hw/usb/hcd-ehci.c
372
+++ b/hw/usb/hcd-ehci.c
373
@@ -XXX,XX +XXX,XX @@ void usb_ehci_unrealize(EHCIState *s, DeviceState *dev)
374
trace_usb_ehci_unrealize();
375
376
if (s->frame_timer) {
377
- timer_del(s->frame_timer);
378
timer_free(s->frame_timer);
379
s->frame_timer = NULL;
380
}
381
diff --git a/hw/usb/hcd-ohci-pci.c b/hw/usb/hcd-ohci-pci.c
382
index XXXXXXX..XXXXXXX 100644
383
--- a/hw/usb/hcd-ohci-pci.c
384
+++ b/hw/usb/hcd-ohci-pci.c
385
@@ -XXX,XX +XXX,XX @@ static void usb_ohci_exit(PCIDevice *dev)
386
usb_bus_release(&s->bus);
387
}
388
389
- timer_del(s->eof_timer);
390
timer_free(s->eof_timer);
391
}
392
393
diff --git a/hw/usb/hcd-uhci.c b/hw/usb/hcd-uhci.c
394
index XXXXXXX..XXXXXXX 100644
395
--- a/hw/usb/hcd-uhci.c
396
+++ b/hw/usb/hcd-uhci.c
397
@@ -XXX,XX +XXX,XX @@ static void usb_uhci_exit(PCIDevice *dev)
398
trace_usb_uhci_exit();
399
400
if (s->frame_timer) {
401
- timer_del(s->frame_timer);
402
timer_free(s->frame_timer);
403
s->frame_timer = NULL;
404
}
405
diff --git a/hw/usb/hcd-xhci.c b/hw/usb/hcd-xhci.c
406
index XXXXXXX..XXXXXXX 100644
407
--- a/hw/usb/hcd-xhci.c
408
+++ b/hw/usb/hcd-xhci.c
409
@@ -XXX,XX +XXX,XX @@ static void usb_xhci_unrealize(DeviceState *dev)
410
}
411
412
if (xhci->mfwrap_timer) {
413
- timer_del(xhci->mfwrap_timer);
414
timer_free(xhci->mfwrap_timer);
415
xhci->mfwrap_timer = NULL;
416
}
417
diff --git a/hw/usb/redirect.c b/hw/usb/redirect.c
418
index XXXXXXX..XXXXXXX 100644
419
--- a/hw/usb/redirect.c
420
+++ b/hw/usb/redirect.c
421
@@ -XXX,XX +XXX,XX @@ static void usbredir_unrealize(USBDevice *udev)
422
qemu_bh_delete(dev->chardev_close_bh);
423
qemu_bh_delete(dev->device_reject_bh);
424
425
- timer_del(dev->attach_timer);
426
timer_free(dev->attach_timer);
427
428
usbredir_cleanup_device_queues(dev);
429
diff --git a/hw/vfio/display.c b/hw/vfio/display.c
430
index XXXXXXX..XXXXXXX 100644
431
--- a/hw/vfio/display.c
432
+++ b/hw/vfio/display.c
433
@@ -XXX,XX +XXX,XX @@ static void vfio_display_edid_exit(VFIODisplay *dpy)
434
435
g_free(dpy->edid_regs);
436
g_free(dpy->edid_blob);
437
- timer_del(dpy->edid_link_timer);
438
timer_free(dpy->edid_link_timer);
439
}
440
441
diff --git a/hw/virtio/vhost-vsock-common.c b/hw/virtio/vhost-vsock-common.c
442
index XXXXXXX..XXXXXXX 100644
443
--- a/hw/virtio/vhost-vsock-common.c
444
+++ b/hw/virtio/vhost-vsock-common.c
445
@@ -XXX,XX +XXX,XX @@ static void vhost_vsock_common_post_load_timer_cleanup(VHostVSockCommon *vvc)
446
return;
447
}
448
449
- timer_del(vvc->post_load_timer);
450
timer_free(vvc->post_load_timer);
451
vvc->post_load_timer = NULL;
452
}
453
diff --git a/hw/virtio/virtio-balloon.c b/hw/virtio/virtio-balloon.c
454
index XXXXXXX..XXXXXXX 100644
455
--- a/hw/virtio/virtio-balloon.c
456
+++ b/hw/virtio/virtio-balloon.c
457
@@ -XXX,XX +XXX,XX @@ static bool balloon_stats_enabled(const VirtIOBalloon *s)
458
static void balloon_stats_destroy_timer(VirtIOBalloon *s)
459
{
460
if (balloon_stats_enabled(s)) {
461
- timer_del(s->stats_timer);
462
timer_free(s->stats_timer);
463
s->stats_timer = NULL;
464
s->stats_poll_interval = 0;
465
diff --git a/hw/virtio/virtio-rng.c b/hw/virtio/virtio-rng.c
466
index XXXXXXX..XXXXXXX 100644
467
--- a/hw/virtio/virtio-rng.c
468
+++ b/hw/virtio/virtio-rng.c
469
@@ -XXX,XX +XXX,XX @@ static void virtio_rng_device_unrealize(DeviceState *dev)
470
VirtIORNG *vrng = VIRTIO_RNG(dev);
471
472
qemu_del_vm_change_state_handler(vrng->vmstate);
473
- timer_del(vrng->rate_limit_timer);
474
timer_free(vrng->rate_limit_timer);
475
virtio_del_queue(vdev, 0);
476
virtio_cleanup(vdev);
477
diff --git a/hw/watchdog/wdt_diag288.c b/hw/watchdog/wdt_diag288.c
478
index XXXXXXX..XXXXXXX 100644
479
--- a/hw/watchdog/wdt_diag288.c
480
+++ b/hw/watchdog/wdt_diag288.c
481
@@ -XXX,XX +XXX,XX @@ static void wdt_diag288_unrealize(DeviceState *dev)
482
{
483
DIAG288State *diag288 = DIAG288(dev);
484
485
- timer_del(diag288->timer);
486
timer_free(diag288->timer);
487
}
488
489
diff --git a/hw/watchdog/wdt_i6300esb.c b/hw/watchdog/wdt_i6300esb.c
490
index XXXXXXX..XXXXXXX 100644
491
--- a/hw/watchdog/wdt_i6300esb.c
492
+++ b/hw/watchdog/wdt_i6300esb.c
493
@@ -XXX,XX +XXX,XX @@ static void i6300esb_exit(PCIDevice *dev)
494
{
495
I6300State *d = WATCHDOG_I6300ESB_DEVICE(dev);
496
497
- timer_del(d->timer);
498
timer_free(d->timer);
499
}
500
501
diff --git a/migration/colo.c b/migration/colo.c
502
index XXXXXXX..XXXXXXX 100644
503
--- a/migration/colo.c
504
+++ b/migration/colo.c
505
@@ -XXX,XX +XXX,XX @@ out:
506
* error.
507
*/
508
colo_compare_unregister_notifier(&packets_compare_notifier);
509
- timer_del(s->colo_delay_timer);
510
timer_free(s->colo_delay_timer);
511
qemu_event_destroy(&s->colo_checkpoint_event);
512
513
diff --git a/monitor/hmp-cmds.c b/monitor/hmp-cmds.c
514
index XXXXXXX..XXXXXXX 100644
515
--- a/monitor/hmp-cmds.c
516
+++ b/monitor/hmp-cmds.c
517
@@ -XXX,XX +XXX,XX @@ static void hmp_migrate_status_cb(void *opaque)
518
error_report("%s", info->error_desc);
519
}
520
monitor_resume(status->mon);
521
- timer_del(status->timer);
522
timer_free(status->timer);
523
g_free(status);
524
}
525
diff --git a/net/announce.c b/net/announce.c
526
index XXXXXXX..XXXXXXX 100644
527
--- a/net/announce.c
528
+++ b/net/announce.c
529
@@ -XXX,XX +XXX,XX @@ void qemu_announce_timer_del(AnnounceTimer *timer, bool free_named)
530
{
531
bool free_timer = false;
532
if (timer->tm) {
533
- timer_del(timer->tm);
534
timer_free(timer->tm);
535
timer->tm = NULL;
536
}
537
diff --git a/net/colo-compare.c b/net/colo-compare.c
538
index XXXXXXX..XXXXXXX 100644
539
--- a/net/colo-compare.c
540
+++ b/net/colo-compare.c
541
@@ -XXX,XX +XXX,XX @@ static void colo_compare_timer_init(CompareState *s)
542
static void colo_compare_timer_del(CompareState *s)
543
{
544
if (s->packet_check_timer) {
545
- timer_del(s->packet_check_timer);
546
timer_free(s->packet_check_timer);
547
s->packet_check_timer = NULL;
548
}
549
diff --git a/net/slirp.c b/net/slirp.c
550
index XXXXXXX..XXXXXXX 100644
551
--- a/net/slirp.c
552
+++ b/net/slirp.c
553
@@ -XXX,XX +XXX,XX @@ static void *net_slirp_timer_new(SlirpTimerCb cb,
554
555
static void net_slirp_timer_free(void *timer, void *opaque)
556
{
557
- timer_del(timer);
558
timer_free(timer);
559
}
560
561
diff --git a/replay/replay-debugging.c b/replay/replay-debugging.c
562
index XXXXXXX..XXXXXXX 100644
563
--- a/replay/replay-debugging.c
564
+++ b/replay/replay-debugging.c
565
@@ -XXX,XX +XXX,XX @@ static void replay_delete_break(void)
566
assert(replay_mutex_locked());
567
568
if (replay_break_timer) {
569
- timer_del(replay_break_timer);
570
timer_free(replay_break_timer);
571
replay_break_timer = NULL;
572
}
573
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
574
index XXXXXXX..XXXXXXX 100644
575
--- a/target/s390x/cpu.c
576
+++ b/target/s390x/cpu.c
577
@@ -XXX,XX +XXX,XX @@ static void s390_cpu_finalize(Object *obj)
578
#if !defined(CONFIG_USER_ONLY)
579
S390CPU *cpu = S390_CPU(obj);
580
581
- timer_del(cpu->env.tod_timer);
582
timer_free(cpu->env.tod_timer);
583
- timer_del(cpu->env.cpu_timer);
584
timer_free(cpu->env.cpu_timer);
585
586
qemu_unregister_reset(s390_cpu_machine_reset_cb, cpu);
587
diff --git a/ui/console.c b/ui/console.c
588
index XXXXXXX..XXXXXXX 100644
589
--- a/ui/console.c
590
+++ b/ui/console.c
591
@@ -XXX,XX +XXX,XX @@ static void gui_setup_refresh(DisplayState *ds)
592
timer_mod(ds->gui_timer, qemu_clock_get_ms(QEMU_CLOCK_REALTIME));
593
}
594
if (!need_timer && ds->gui_timer != NULL) {
595
- timer_del(ds->gui_timer);
596
timer_free(ds->gui_timer);
597
ds->gui_timer = NULL;
598
}
599
diff --git a/ui/spice-core.c b/ui/spice-core.c
600
index XXXXXXX..XXXXXXX 100644
601
--- a/ui/spice-core.c
602
+++ b/ui/spice-core.c
603
@@ -XXX,XX +XXX,XX @@ static void timer_cancel(SpiceTimer *timer)
604
605
static void timer_remove(SpiceTimer *timer)
606
{
607
- timer_del(timer->timer);
608
timer_free(timer->timer);
609
g_free(timer);
610
}
611
diff --git a/util/throttle.c b/util/throttle.c
612
index XXXXXXX..XXXXXXX 100644
613
--- a/util/throttle.c
614
+++ b/util/throttle.c
615
@@ -XXX,XX +XXX,XX @@ static void throttle_timer_destroy(QEMUTimer **timer)
616
{
617
assert(*timer != NULL);
618
619
- timer_del(*timer);
620
timer_free(*timer);
621
*timer = NULL;
622
}
623
--
64
--
624
2.20.1
65
2.34.1
625
66
626
67
diff view generated by jsdifflib
1
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
2
2
3
Correct the indexing into s->cpu_ctlr for vCPUs.
3
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
4
4
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
5
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
6
Message-id: 20230220115114.25237-5-philmd@linaro.org
7
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
8
Message-id: 20201214222154.3480243-2-edgar.iglesias@gmail.com
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
8
---
11
hw/intc/arm_gic.c | 4 +++-
9
include/hw/char/xilinx_uartlite.h | 6 +++++-
12
1 file changed, 3 insertions(+), 1 deletion(-)
10
hw/char/xilinx_uartlite.c | 4 +---
11
2 files changed, 6 insertions(+), 4 deletions(-)
13
12
14
diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c
13
diff --git a/include/hw/char/xilinx_uartlite.h b/include/hw/char/xilinx_uartlite.h
15
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/intc/arm_gic.c
15
--- a/include/hw/char/xilinx_uartlite.h
17
+++ b/hw/intc/arm_gic.c
16
+++ b/include/hw/char/xilinx_uartlite.h
18
@@ -XXX,XX +XXX,XX @@ static inline void gic_get_best_virq(GICState *s, int cpu,
17
@@ -XXX,XX +XXX,XX @@
19
static inline bool gic_irq_signaling_enabled(GICState *s, int cpu, bool virt,
18
#include "hw/qdev-properties.h"
20
int group_mask)
19
#include "hw/sysbus.h"
21
{
20
#include "qapi/error.h"
22
+ int cpu_iface = virt ? (cpu + GIC_NCPU) : cpu;
21
+#include "qom/object.h"
23
+
22
+
24
if (!virt && !(s->ctlr & group_mask)) {
23
+#define TYPE_XILINX_UARTLITE "xlnx.xps-uartlite"
25
return false;
24
+OBJECT_DECLARE_SIMPLE_TYPE(XilinxUARTLite, XILINX_UARTLITE)
26
}
25
27
@@ -XXX,XX +XXX,XX @@ static inline bool gic_irq_signaling_enabled(GICState *s, int cpu, bool virt,
26
static inline DeviceState *xilinx_uartlite_create(hwaddr addr,
28
return false;
27
qemu_irq irq,
29
}
28
@@ -XXX,XX +XXX,XX @@ static inline DeviceState *xilinx_uartlite_create(hwaddr addr,
30
29
DeviceState *dev;
31
- if (!(s->cpu_ctlr[cpu] & group_mask)) {
30
SysBusDevice *s;
32
+ if (!(s->cpu_ctlr[cpu_iface] & group_mask)) {
31
33
return false;
32
- dev = qdev_new("xlnx.xps-uartlite");
34
}
33
+ dev = qdev_new(TYPE_XILINX_UARTLITE);
34
s = SYS_BUS_DEVICE(dev);
35
qdev_prop_set_chr(dev, "chardev", chr);
36
sysbus_realize_and_unref(s, &error_fatal);
37
diff --git a/hw/char/xilinx_uartlite.c b/hw/char/xilinx_uartlite.c
38
index XXXXXXX..XXXXXXX 100644
39
--- a/hw/char/xilinx_uartlite.c
40
+++ b/hw/char/xilinx_uartlite.c
41
@@ -XXX,XX +XXX,XX @@
42
43
#include "qemu/osdep.h"
44
#include "qemu/log.h"
45
+#include "hw/char/xilinx_uartlite.h"
46
#include "hw/irq.h"
47
#include "hw/qdev-properties.h"
48
#include "hw/qdev-properties-system.h"
49
@@ -XXX,XX +XXX,XX @@
50
#define CONTROL_RST_RX 0x02
51
#define CONTROL_IE 0x10
52
53
-#define TYPE_XILINX_UARTLITE "xlnx.xps-uartlite"
54
-OBJECT_DECLARE_SIMPLE_TYPE(XilinxUARTLite, XILINX_UARTLITE)
55
-
56
struct XilinxUARTLite {
57
SysBusDevice parent_obj;
35
58
36
--
59
--
37
2.20.1
60
2.34.1
38
61
39
62
diff view generated by jsdifflib
1
Currently timer_free() is a simple wrapper for g_free(). This means
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
2
that the timer being freed must not be currently active, as otherwise
3
QEMU might crash later when the active list is processed and still
4
has a pointer to freed memory on it. As a result almost all calls to
5
timer_free() are preceded by a timer_del() call, as can be seen in
6
the output of
7
git grep -B1 '\<timer_free\>'
8
2
9
This is unfortunate API design as it makes it easy to accidentally
3
Open-code the single use of xilinx_uartlite_create().
10
misuse (by forgetting the timer_del()), and the correct use is
11
annoyingly verbose.
12
4
13
Make timer_free() imply a timer_del().
5
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
6
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20230220115114.25237-6-philmd@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
include/hw/char/xilinx_uartlite.h | 20 --------------------
12
hw/microblaze/petalogix_s3adsp1800_mmu.c | 7 +++++--
13
2 files changed, 5 insertions(+), 22 deletions(-)
14
14
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
diff --git a/include/hw/char/xilinx_uartlite.h b/include/hw/char/xilinx_uartlite.h
16
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
17
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
18
Message-id: 20201215154107.3255-2-peter.maydell@linaro.org
19
---
20
include/qemu/timer.h | 24 +++++++++++++-----------
21
1 file changed, 13 insertions(+), 11 deletions(-)
22
23
diff --git a/include/qemu/timer.h b/include/qemu/timer.h
24
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
25
--- a/include/qemu/timer.h
17
--- a/include/hw/char/xilinx_uartlite.h
26
+++ b/include/qemu/timer.h
18
+++ b/include/hw/char/xilinx_uartlite.h
27
@@ -XXX,XX +XXX,XX @@ static inline QEMUTimer *timer_new_ms(QEMUClockType type, QEMUTimerCB *cb,
19
@@ -XXX,XX +XXX,XX @@
28
*/
20
#ifndef XILINX_UARTLITE_H
29
void timer_deinit(QEMUTimer *ts);
21
#define XILINX_UARTLITE_H
30
22
31
-/**
23
-#include "hw/qdev-properties.h"
32
- * timer_free:
24
-#include "hw/sysbus.h"
33
- * @ts: the timer
25
-#include "qapi/error.h"
34
- *
26
#include "qom/object.h"
35
- * Free a timer (it must not be on the active list)
27
36
- */
28
#define TYPE_XILINX_UARTLITE "xlnx.xps-uartlite"
37
-static inline void timer_free(QEMUTimer *ts)
29
OBJECT_DECLARE_SIMPLE_TYPE(XilinxUARTLite, XILINX_UARTLITE)
30
31
-static inline DeviceState *xilinx_uartlite_create(hwaddr addr,
32
- qemu_irq irq,
33
- Chardev *chr)
38
-{
34
-{
39
- g_free(ts);
35
- DeviceState *dev;
36
- SysBusDevice *s;
37
-
38
- dev = qdev_new(TYPE_XILINX_UARTLITE);
39
- s = SYS_BUS_DEVICE(dev);
40
- qdev_prop_set_chr(dev, "chardev", chr);
41
- sysbus_realize_and_unref(s, &error_fatal);
42
- sysbus_mmio_map(s, 0, addr);
43
- sysbus_connect_irq(s, 0, irq);
44
-
45
- return dev;
40
-}
46
-}
41
-
47
-
42
/**
48
#endif
43
* timer_del:
49
diff --git a/hw/microblaze/petalogix_s3adsp1800_mmu.c b/hw/microblaze/petalogix_s3adsp1800_mmu.c
44
* @ts: the timer
50
index XXXXXXX..XXXXXXX 100644
45
@@ -XXX,XX +XXX,XX @@ static inline void timer_free(QEMUTimer *ts)
51
--- a/hw/microblaze/petalogix_s3adsp1800_mmu.c
46
*/
52
+++ b/hw/microblaze/petalogix_s3adsp1800_mmu.c
47
void timer_del(QEMUTimer *ts);
53
@@ -XXX,XX +XXX,XX @@ petalogix_s3adsp1800_init(MachineState *machine)
48
54
irq[i] = qdev_get_gpio_in(dev, i);
49
+/**
55
}
50
+ * timer_free:
56
51
+ * @ts: the timer
57
- xilinx_uartlite_create(UARTLITE_BASEADDR, irq[UARTLITE_IRQ],
52
+ *
58
- serial_hd(0));
53
+ * Free a timer. This will call timer_del() for you to remove
59
+ dev = qdev_new(TYPE_XILINX_UARTLITE);
54
+ * the timer from the active list if it was still active.
60
+ qdev_prop_set_chr(dev, "chardev", serial_hd(0));
55
+ */
61
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
56
+static inline void timer_free(QEMUTimer *ts)
62
+ sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, UARTLITE_BASEADDR);
57
+{
63
+ sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[UARTLITE_IRQ]);
58
+ timer_del(ts);
64
59
+ g_free(ts);
65
/* 2 timers at irq 2 @ 62 Mhz. */
60
+}
66
dev = qdev_new("xlnx.xps-timer");
61
+
62
/**
63
* timer_mod_ns:
64
* @ts: the timer
65
--
67
--
66
2.20.1
68
2.34.1
67
69
68
70
diff view generated by jsdifflib
1
Implement the v8.1M FPCXT_NS floating-point system register. This is
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
2
a little more complicated than FPCXT_S, because it has specific
3
handling for "current FP state is inactive", and it only wants to do
4
PreserveFPState(), not the full set of actions done by
5
ExecuteFPCheck() which vfp_access_check() implements.
6
2
3
cmsdk_apb_uart_create() is only used twice in the same
4
file. Open-code it.
5
6
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Message-id: 20230220115114.25237-7-philmd@linaro.org
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20201210201433.26262-4-peter.maydell@linaro.org
10
---
10
---
11
target/arm/translate-vfp.c.inc | 102 ++++++++++++++++++++++++++++++++-
11
include/hw/char/cmsdk-apb-uart.h | 34 --------------------------
12
1 file changed, 99 insertions(+), 3 deletions(-)
12
hw/arm/mps2.c | 41 +++++++++++++++++++++-----------
13
2 files changed, 27 insertions(+), 48 deletions(-)
13
14
14
diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc
15
diff --git a/include/hw/char/cmsdk-apb-uart.h b/include/hw/char/cmsdk-apb-uart.h
15
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/translate-vfp.c.inc
17
--- a/include/hw/char/cmsdk-apb-uart.h
17
+++ b/target/arm/translate-vfp.c.inc
18
+++ b/include/hw/char/cmsdk-apb-uart.h
18
@@ -XXX,XX +XXX,XX @@ static FPSysRegCheckResult fp_sysreg_checks(DisasContext *s, int regno)
19
@@ -XXX,XX +XXX,XX @@
20
#ifndef CMSDK_APB_UART_H
21
#define CMSDK_APB_UART_H
22
23
-#include "hw/qdev-properties.h"
24
#include "hw/sysbus.h"
25
#include "chardev/char-fe.h"
26
-#include "qapi/error.h"
27
#include "qom/object.h"
28
29
#define TYPE_CMSDK_APB_UART "cmsdk-apb-uart"
30
@@ -XXX,XX +XXX,XX @@ struct CMSDKAPBUART {
31
uint8_t rxbuf;
32
};
33
34
-/**
35
- * cmsdk_apb_uart_create - convenience function to create TYPE_CMSDK_APB_UART
36
- * @addr: location in system memory to map registers
37
- * @chr: Chardev backend to connect UART to, or NULL if no backend
38
- * @pclk_frq: frequency in Hz of the PCLK clock (used for calculating baud rate)
39
- */
40
-static inline DeviceState *cmsdk_apb_uart_create(hwaddr addr,
41
- qemu_irq txint,
42
- qemu_irq rxint,
43
- qemu_irq txovrint,
44
- qemu_irq rxovrint,
45
- qemu_irq uartint,
46
- Chardev *chr,
47
- uint32_t pclk_frq)
48
-{
49
- DeviceState *dev;
50
- SysBusDevice *s;
51
-
52
- dev = qdev_new(TYPE_CMSDK_APB_UART);
53
- s = SYS_BUS_DEVICE(dev);
54
- qdev_prop_set_chr(dev, "chardev", chr);
55
- qdev_prop_set_uint32(dev, "pclk-frq", pclk_frq);
56
- sysbus_realize_and_unref(s, &error_fatal);
57
- sysbus_mmio_map(s, 0, addr);
58
- sysbus_connect_irq(s, 0, txint);
59
- sysbus_connect_irq(s, 1, rxint);
60
- sysbus_connect_irq(s, 2, txovrint);
61
- sysbus_connect_irq(s, 3, rxovrint);
62
- sysbus_connect_irq(s, 4, uartint);
63
- return dev;
64
-}
65
-
66
#endif
67
diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c
68
index XXXXXXX..XXXXXXX 100644
69
--- a/hw/arm/mps2.c
70
+++ b/hw/arm/mps2.c
71
@@ -XXX,XX +XXX,XX @@
72
#include "hw/boards.h"
73
#include "exec/address-spaces.h"
74
#include "sysemu/sysemu.h"
75
+#include "hw/qdev-properties.h"
76
#include "hw/misc/unimp.h"
77
#include "hw/char/cmsdk-apb-uart.h"
78
#include "hw/timer/cmsdk-apb-timer.h"
79
@@ -XXX,XX +XXX,XX @@ static void mps2_common_init(MachineState *machine)
80
qdev_connect_gpio_out(orgate_dev, 0, qdev_get_gpio_in(armv7m, 12));
81
82
for (i = 0; i < 5; i++) {
83
+ DeviceState *dev;
84
+ SysBusDevice *s;
85
+
86
static const hwaddr uartbase[] = {0x40004000, 0x40005000,
87
0x40006000, 0x40007000,
88
0x40009000};
89
@@ -XXX,XX +XXX,XX @@ static void mps2_common_init(MachineState *machine)
90
rxovrint = qdev_get_gpio_in(orgate_dev, i * 2 + 1);
91
}
92
93
- cmsdk_apb_uart_create(uartbase[i],
94
- qdev_get_gpio_in(armv7m, uartirq[i] + 1),
95
- qdev_get_gpio_in(armv7m, uartirq[i]),
96
- txovrint, rxovrint,
97
- NULL,
98
- serial_hd(i), SYSCLK_FRQ);
99
+ dev = qdev_new(TYPE_CMSDK_APB_UART);
100
+ s = SYS_BUS_DEVICE(dev);
101
+ qdev_prop_set_chr(dev, "chardev", serial_hd(i));
102
+ qdev_prop_set_uint32(dev, "pclk-frq", SYSCLK_FRQ);
103
+ sysbus_realize_and_unref(s, &error_fatal);
104
+ sysbus_mmio_map(s, 0, uartbase[i]);
105
+ sysbus_connect_irq(s, 0, qdev_get_gpio_in(armv7m, uartirq[i] + 1));
106
+ sysbus_connect_irq(s, 1, qdev_get_gpio_in(armv7m, uartirq[i]));
107
+ sysbus_connect_irq(s, 2, txovrint);
108
+ sysbus_connect_irq(s, 3, rxovrint);
19
}
109
}
20
break;
110
break;
21
case ARM_VFP_FPCXT_S:
111
}
22
+ case ARM_VFP_FPCXT_NS:
112
@@ -XXX,XX +XXX,XX @@ static void mps2_common_init(MachineState *machine)
23
if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) {
113
0x4002c000, 0x4002d000,
24
return false;
114
0x4002e000};
115
Object *txrx_orgate;
116
- DeviceState *txrx_orgate_dev;
117
+ DeviceState *txrx_orgate_dev, *dev;
118
+ SysBusDevice *s;
119
120
txrx_orgate = object_new(TYPE_OR_IRQ);
121
object_property_set_int(txrx_orgate, "num-lines", 2, &error_fatal);
122
@@ -XXX,XX +XXX,XX @@ static void mps2_common_init(MachineState *machine)
123
txrx_orgate_dev = DEVICE(txrx_orgate);
124
qdev_connect_gpio_out(txrx_orgate_dev, 0,
125
qdev_get_gpio_in(armv7m, uart_txrx_irqno[i]));
126
- cmsdk_apb_uart_create(uartbase[i],
127
- qdev_get_gpio_in(txrx_orgate_dev, 0),
128
- qdev_get_gpio_in(txrx_orgate_dev, 1),
129
- qdev_get_gpio_in(orgate_dev, i * 2),
130
- qdev_get_gpio_in(orgate_dev, i * 2 + 1),
131
- NULL,
132
- serial_hd(i), SYSCLK_FRQ);
133
+
134
+ dev = qdev_new(TYPE_CMSDK_APB_UART);
135
+ s = SYS_BUS_DEVICE(dev);
136
+ qdev_prop_set_chr(dev, "chardev", serial_hd(i));
137
+ qdev_prop_set_uint32(dev, "pclk-frq", SYSCLK_FRQ);
138
+ sysbus_realize_and_unref(s, &error_fatal);
139
+ sysbus_mmio_map(s, 0, uartbase[i]);
140
+ sysbus_connect_irq(s, 0, qdev_get_gpio_in(txrx_orgate_dev, 0));
141
+ sysbus_connect_irq(s, 1, qdev_get_gpio_in(txrx_orgate_dev, 1));
142
+ sysbus_connect_irq(s, 2, qdev_get_gpio_in(orgate_dev, i * 2));
143
+ sysbus_connect_irq(s, 3, qdev_get_gpio_in(orgate_dev, i * 2 + 1));
25
}
144
}
26
@@ -XXX,XX +XXX,XX @@ static FPSysRegCheckResult fp_sysreg_checks(DisasContext *s, int regno)
27
return FPSysRegCheckFailed;
28
}
29
30
- if (!vfp_access_check(s)) {
31
+ /*
32
+ * FPCXT_NS is a special case: it has specific handling for
33
+ * "current FP state is inactive", and must do the PreserveFPState()
34
+ * but not the usual full set of actions done by ExecuteFPCheck().
35
+ * So we don't call vfp_access_check() and the callers must handle this.
36
+ */
37
+ if (regno != ARM_VFP_FPCXT_NS && !vfp_access_check(s)) {
38
return FPSysRegCheckDone;
39
}
40
-
41
return FPSysRegCheckContinue;
42
}
43
44
+static void gen_branch_fpInactive(DisasContext *s, TCGCond cond,
45
+ TCGLabel *label)
46
+{
47
+ /*
48
+ * FPCXT_NS is a special case: it has specific handling for
49
+ * "current FP state is inactive", and must do the PreserveFPState()
50
+ * but not the usual full set of actions done by ExecuteFPCheck().
51
+ * We don't have a TB flag that matches the fpInactive check, so we
52
+ * do it at runtime as we don't expect FPCXT_NS accesses to be frequent.
53
+ *
54
+ * Emit code that checks fpInactive and does a conditional
55
+ * branch to label based on it:
56
+ * if cond is TCG_COND_NE then branch if fpInactive != 0 (ie if inactive)
57
+ * if cond is TCG_COND_EQ then branch if fpInactive == 0 (ie if active)
58
+ */
59
+ assert(cond == TCG_COND_EQ || cond == TCG_COND_NE);
60
+
61
+ /* fpInactive = FPCCR_NS.ASPEN == 1 && CONTROL.FPCA == 0 */
62
+ TCGv_i32 aspen, fpca;
63
+ aspen = load_cpu_field(v7m.fpccr[M_REG_NS]);
64
+ fpca = load_cpu_field(v7m.control[M_REG_S]);
65
+ tcg_gen_andi_i32(aspen, aspen, R_V7M_FPCCR_ASPEN_MASK);
66
+ tcg_gen_xori_i32(aspen, aspen, R_V7M_FPCCR_ASPEN_MASK);
67
+ tcg_gen_andi_i32(fpca, fpca, R_V7M_CONTROL_FPCA_MASK);
68
+ tcg_gen_or_i32(fpca, fpca, aspen);
69
+ tcg_gen_brcondi_i32(tcg_invert_cond(cond), fpca, 0, label);
70
+ tcg_temp_free_i32(aspen);
71
+ tcg_temp_free_i32(fpca);
72
+}
73
+
74
static bool gen_M_fp_sysreg_write(DisasContext *s, int regno,
75
76
fp_sysreg_loadfn *loadfn,
77
@@ -XXX,XX +XXX,XX @@ static bool gen_M_fp_sysreg_write(DisasContext *s, int regno,
78
{
79
/* Do a write to an M-profile floating point system register */
80
TCGv_i32 tmp;
81
+ TCGLabel *lab_end = NULL;
82
83
switch (fp_sysreg_checks(s, regno)) {
84
case FPSysRegCheckFailed:
85
@@ -XXX,XX +XXX,XX @@ static bool gen_M_fp_sysreg_write(DisasContext *s, int regno,
86
tcg_temp_free_i32(tmp);
87
break;
145
break;
88
}
146
}
89
+ case ARM_VFP_FPCXT_NS:
90
+ lab_end = gen_new_label();
91
+ /* fpInactive case: write is a NOP, so branch to end */
92
+ gen_branch_fpInactive(s, TCG_COND_NE, lab_end);
93
+ /* !fpInactive: PreserveFPState(), and reads same as FPCXT_S */
94
+ gen_preserve_fp_state(s);
95
+ /* fall through */
96
case ARM_VFP_FPCXT_S:
97
{
98
TCGv_i32 sfpa, control;
99
@@ -XXX,XX +XXX,XX @@ static bool gen_M_fp_sysreg_write(DisasContext *s, int regno,
100
default:
101
g_assert_not_reached();
102
}
103
+ if (lab_end) {
104
+ gen_set_label(lab_end);
105
+ }
106
return true;
107
}
108
109
@@ -XXX,XX +XXX,XX @@ static bool gen_M_fp_sysreg_read(DisasContext *s, int regno,
110
{
111
/* Do a read from an M-profile floating point system register */
112
TCGv_i32 tmp;
113
+ TCGLabel *lab_end = NULL;
114
+ bool lookup_tb = false;
115
116
switch (fp_sysreg_checks(s, regno)) {
117
case FPSysRegCheckFailed:
118
@@ -XXX,XX +XXX,XX @@ static bool gen_M_fp_sysreg_read(DisasContext *s, int regno,
119
fpscr = load_cpu_field(v7m.fpdscr[M_REG_NS]);
120
gen_helper_vfp_set_fpscr(cpu_env, fpscr);
121
tcg_temp_free_i32(fpscr);
122
- gen_lookup_tb(s);
123
+ lookup_tb = true;
124
+ break;
125
+ }
126
+ case ARM_VFP_FPCXT_NS:
127
+ {
128
+ TCGv_i32 control, sfpa, fpscr, fpdscr, zero;
129
+ TCGLabel *lab_active = gen_new_label();
130
+
131
+ lookup_tb = true;
132
+
133
+ gen_branch_fpInactive(s, TCG_COND_EQ, lab_active);
134
+ /* fpInactive case: reads as FPDSCR_NS */
135
+ TCGv_i32 tmp = load_cpu_field(v7m.fpdscr[M_REG_NS]);
136
+ storefn(s, opaque, tmp);
137
+ lab_end = gen_new_label();
138
+ tcg_gen_br(lab_end);
139
+
140
+ gen_set_label(lab_active);
141
+ /* !fpInactive: Reads the same as FPCXT_S, but side effects differ */
142
+ gen_preserve_fp_state(s);
143
+ tmp = tcg_temp_new_i32();
144
+ sfpa = tcg_temp_new_i32();
145
+ fpscr = tcg_temp_new_i32();
146
+ gen_helper_vfp_get_fpscr(fpscr, cpu_env);
147
+ tcg_gen_andi_i32(tmp, fpscr, ~FPCR_NZCV_MASK);
148
+ control = load_cpu_field(v7m.control[M_REG_S]);
149
+ tcg_gen_andi_i32(sfpa, control, R_V7M_CONTROL_SFPA_MASK);
150
+ tcg_gen_shli_i32(sfpa, sfpa, 31 - R_V7M_CONTROL_SFPA_SHIFT);
151
+ tcg_gen_or_i32(tmp, tmp, sfpa);
152
+ tcg_temp_free_i32(control);
153
+ /* Store result before updating FPSCR, in case it faults */
154
+ storefn(s, opaque, tmp);
155
+ /* If SFPA is zero then set FPSCR from FPDSCR_NS */
156
+ fpdscr = load_cpu_field(v7m.fpdscr[M_REG_NS]);
157
+ zero = tcg_const_i32(0);
158
+ tcg_gen_movcond_i32(TCG_COND_EQ, fpscr, sfpa, zero, fpdscr, fpscr);
159
+ gen_helper_vfp_set_fpscr(cpu_env, fpscr);
160
+ tcg_temp_free_i32(zero);
161
+ tcg_temp_free_i32(sfpa);
162
+ tcg_temp_free_i32(fpdscr);
163
+ tcg_temp_free_i32(fpscr);
164
break;
165
}
166
default:
167
g_assert_not_reached();
168
}
169
+
170
+ if (lab_end) {
171
+ gen_set_label(lab_end);
172
+ }
173
+ if (lookup_tb) {
174
+ gen_lookup_tb(s);
175
+ }
176
return true;
177
}
178
179
--
147
--
180
2.20.1
148
2.34.1
181
149
182
150
diff view generated by jsdifflib
1
Support for running KVM on 32-bit Arm hosts was removed in commit
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
2
82bf7ae84ce739e. You can still run a 32-bit guest on a 64-bit Arm
3
host CPU, but because Arm KVM requires the host and guest CPU types
4
to match, it is not possible to run a guest that requires a Cortex-A9
5
or Cortex-A15 CPU there. That means that the code in the
6
highbank/midway board models to support KVM is no longer used, and we
7
can delete it.
8
2
3
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
4
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
5
Message-id: 20230220115114.25237-8-philmd@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
11
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
12
Message-id: 20201215144215.28482-1-peter.maydell@linaro.org
13
---
7
---
14
hw/arm/highbank.c | 14 ++++----------
8
include/hw/timer/cmsdk-apb-timer.h | 1 -
15
1 file changed, 4 insertions(+), 10 deletions(-)
9
1 file changed, 1 deletion(-)
16
10
17
diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c
11
diff --git a/include/hw/timer/cmsdk-apb-timer.h b/include/hw/timer/cmsdk-apb-timer.h
18
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/arm/highbank.c
13
--- a/include/hw/timer/cmsdk-apb-timer.h
20
+++ b/hw/arm/highbank.c
14
+++ b/include/hw/timer/cmsdk-apb-timer.h
21
@@ -XXX,XX +XXX,XX @@
15
@@ -XXX,XX +XXX,XX @@
22
#include "hw/arm/boot.h"
16
#ifndef CMSDK_APB_TIMER_H
23
#include "hw/loader.h"
17
#define CMSDK_APB_TIMER_H
24
#include "net/net.h"
18
25
-#include "sysemu/kvm.h"
19
-#include "hw/qdev-properties.h"
26
#include "sysemu/runstate.h"
20
#include "hw/sysbus.h"
27
#include "sysemu/sysemu.h"
21
#include "hw/ptimer.h"
28
#include "hw/boards.h"
22
#include "hw/clock.h"
29
@@ -XXX,XX +XXX,XX @@
30
#include "hw/cpu/a15mpcore.h"
31
#include "qemu/log.h"
32
#include "qom/object.h"
33
+#include "cpu.h"
34
35
#define SMP_BOOT_ADDR 0x100
36
#define SMP_BOOT_REG 0x40
37
@@ -XXX,XX +XXX,XX @@ static void calxeda_init(MachineState *machine, enum cxmachines machine_id)
38
highbank_binfo.loader_start = 0;
39
highbank_binfo.write_secondary_boot = hb_write_secondary;
40
highbank_binfo.secondary_cpu_reset_hook = hb_reset_secondary;
41
- if (!kvm_enabled()) {
42
- highbank_binfo.board_setup_addr = BOARD_SETUP_ADDR;
43
- highbank_binfo.write_board_setup = hb_write_board_setup;
44
- highbank_binfo.secure_board_setup = true;
45
- } else {
46
- warn_report("cannot load built-in Monitor support "
47
- "if KVM is enabled. Some guests (such as Linux) "
48
- "may not boot.");
49
- }
50
+ highbank_binfo.board_setup_addr = BOARD_SETUP_ADDR;
51
+ highbank_binfo.write_board_setup = hb_write_board_setup;
52
+ highbank_binfo.secure_board_setup = true;
53
54
arm_load_kernel(ARM_CPU(first_cpu), machine, &highbank_binfo);
55
}
56
--
23
--
57
2.20.1
24
2.34.1
58
25
59
26
diff view generated by jsdifflib
1
The CCR is a register most of whose bits are banked between security
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
2
states but where BFHFNMIGN is not, and we keep it in the non-secure
3
entry of the v7m.ccr[] array. The logic which tries to handle this
4
bit fails to implement the "RAZ/WI from Nonsecure if AIRCR.BFHFNMINS
5
is zero" requirement; correct the omission.
6
2
3
Avoid accessing 'parent_obj' directly.
4
5
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
6
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
7
Message-id: 20230220115114.25237-9-philmd@linaro.org
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20201210201433.26262-2-peter.maydell@linaro.org
10
---
9
---
11
hw/intc/armv7m_nvic.c | 15 +++++++++++++++
10
hw/intc/armv7m_nvic.c | 6 +++---
12
1 file changed, 15 insertions(+)
11
1 file changed, 3 insertions(+), 3 deletions(-)
13
12
14
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
13
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
15
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/intc/armv7m_nvic.c
15
--- a/hw/intc/armv7m_nvic.c
17
+++ b/hw/intc/armv7m_nvic.c
16
+++ b/hw/intc/armv7m_nvic.c
18
@@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
17
@@ -XXX,XX +XXX,XX @@ static void do_armv7m_nvic_set_pending(void *opaque, int irq, bool secure,
19
*/
18
* which saves having to have an extra argument is_terminal
20
val = cpu->env.v7m.ccr[attrs.secure];
19
* that we'd only use in one place.
21
val |= cpu->env.v7m.ccr[M_REG_NS] & R_V7M_CCR_BFHFNMIGN_MASK;
20
*/
22
+ /* BFHFNMIGN is RAZ/WI from NS if AIRCR.BFHFNMINS is 0 */
21
- cpu_abort(&s->cpu->parent_obj,
23
+ if (!attrs.secure) {
22
+ cpu_abort(CPU(s->cpu),
24
+ if (!(cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK)) {
23
"Lockup: can't take terminal derived exception "
25
+ val &= ~R_V7M_CCR_BFHFNMIGN_MASK;
24
"(original exception priority %d)\n",
26
+ }
25
s->vectpending_prio);
27
+ }
26
@@ -XXX,XX +XXX,XX @@ static void do_armv7m_nvic_set_pending(void *opaque, int irq, bool secure,
28
return val;
27
* Lockup condition due to a guest bug. We don't model
29
case 0xd24: /* System Handler Control and State (SHCSR) */
28
* Lockup, so report via cpu_abort() instead.
30
if (!arm_feature(&cpu->env, ARM_FEATURE_V7)) {
29
*/
31
@@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
30
- cpu_abort(&s->cpu->parent_obj,
32
(cpu->env.v7m.ccr[M_REG_NS] & ~R_V7M_CCR_BFHFNMIGN_MASK)
31
+ cpu_abort(CPU(s->cpu),
33
| (value & R_V7M_CCR_BFHFNMIGN_MASK);
32
"Lockup: can't escalate %d to HardFault "
34
value &= ~R_V7M_CCR_BFHFNMIGN_MASK;
33
"(current priority %d)\n", irq, running);
35
+ } else {
34
}
36
+ /*
35
@@ -XXX,XX +XXX,XX @@ void armv7m_nvic_set_pending_lazyfp(NVICState *s, int irq, bool secure)
37
+ * BFHFNMIGN is RAZ/WI from NS if AIRCR.BFHFNMINS is 0, so
36
* We want to escalate to HardFault but the context the
38
+ * preserve the state currently in the NS element of the array
37
* FP state belongs to prevents the exception pre-empting.
39
+ */
38
*/
40
+ if (!(cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK)) {
39
- cpu_abort(&s->cpu->parent_obj,
41
+ value &= ~R_V7M_CCR_BFHFNMIGN_MASK;
40
+ cpu_abort(CPU(s->cpu),
42
+ value |= cpu->env.v7m.ccr[M_REG_NS] & R_V7M_CCR_BFHFNMIGN_MASK;
41
"Lockup: can't escalate to HardFault during "
43
+ }
42
"lazy FP register stacking\n");
44
}
43
}
45
46
cpu->env.v7m.ccr[attrs.secure] = value;
47
--
44
--
48
2.20.1
45
2.34.1
49
46
50
47
diff view generated by jsdifflib
1
From: Gan Qixin <ganqixin@huawei.com>
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
2
2
3
When running device-introspect-test, a memory leak occurred in the
3
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
4
mv88w8618_pit_init function, so use ptimer_free() in the finalize function to
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
avoid it.
6
7
ASAN shows memory leak stack:
8
9
Indirect leak of 192 byte(s) in 4 object(s) allocated from:
10
#0 0xffffab97e1f0 in __interceptor_calloc (/lib64/libasan.so.5+0xee1f0)
11
#1 0xffffab256800 in g_malloc0 (/lib64/libglib-2.0.so.0+0x56800)
12
#2 0xaaabf555db84 in timer_new_full /qemu/include/qemu/timer.h:523
13
#3 0xaaabf555db84 in timer_new /qemu/include/qemu/timer.h:544
14
#4 0xaaabf555db84 in timer_new_ns /qemu/include/qemu/timer.h:562
15
#5 0xaaabf555db84 in ptimer_init /qemu/hw/core/ptimer.c:433
16
#6 0xaaabf5bb2290 in mv88w8618_timer_init /qemu/hw/arm/musicpal.c:862
17
#7 0xaaabf5bb2290 in mv88w8618_pit_init /qemu/hw/arm/musicpal.c:954
18
#8 0xaaabf6339f6c in object_initialize_with_type /qemu/qom/object.c:515
19
#9 0xaaabf633a1e0 in object_new_with_type /qemu/qom/object.c:729
20
#10 0xaaabf6375e40 in qmp_device_list_properties /qemu/qom/qom-qmp-cmds.c:153
21
#11 0xaaabf5a95540 in qdev_device_help /qemu/softmmu/qdev-monitor.c:283
22
#12 0xaaabf5a96940 in qmp_device_add /qemu/softmmu/qdev-monitor.c:801
23
24
Reported-by: Euler Robot <euler.robot@huawei.com>
25
Signed-off-by: Gan Qixin <ganqixin@huawei.com>
26
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
27
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
28
---
6
---
29
hw/arm/musicpal.c | 12 ++++++++++++
7
hw/arm/musicpal.c | 4 ----
30
1 file changed, 12 insertions(+)
8
1 file changed, 4 deletions(-)
31
9
32
diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c
10
diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c
33
index XXXXXXX..XXXXXXX 100644
11
index XXXXXXX..XXXXXXX 100644
34
--- a/hw/arm/musicpal.c
12
--- a/hw/arm/musicpal.c
35
+++ b/hw/arm/musicpal.c
13
+++ b/hw/arm/musicpal.c
36
@@ -XXX,XX +XXX,XX @@ static void mv88w8618_pit_init(Object *obj)
14
@@ -XXX,XX +XXX,XX @@ struct musicpal_key_state {
37
sysbus_init_mmio(dev, &s->iomem);
15
SysBusDevice parent_obj;
38
}
16
/*< public >*/
39
17
40
+static void mv88w8618_pit_finalize(Object *obj)
18
- MemoryRegion iomem;
41
+{
19
uint32_t kbd_extended;
42
+ SysBusDevice *dev = SYS_BUS_DEVICE(obj);
20
uint32_t pressed_keys;
43
+ mv88w8618_pit_state *s = MV88W8618_PIT(dev);
21
qemu_irq out[8];
44
+ int i;
22
@@ -XXX,XX +XXX,XX @@ static void musicpal_key_init(Object *obj)
45
+
23
DeviceState *dev = DEVICE(sbd);
46
+ for (i = 0; i < 4; i++) {
24
musicpal_key_state *s = MUSICPAL_KEY(dev);
47
+ ptimer_free(s->timer[i].ptimer);
25
48
+ }
26
- memory_region_init(&s->iomem, obj, "dummy", 0);
49
+}
27
- sysbus_init_mmio(sbd, &s->iomem);
50
+
28
-
51
static const VMStateDescription mv88w8618_timer_vmsd = {
29
s->kbd_extended = 0;
52
.name = "timer",
30
s->pressed_keys = 0;
53
.version_id = 1,
54
@@ -XXX,XX +XXX,XX @@ static const TypeInfo mv88w8618_pit_info = {
55
.parent = TYPE_SYS_BUS_DEVICE,
56
.instance_size = sizeof(mv88w8618_pit_state),
57
.instance_init = mv88w8618_pit_init,
58
+ .instance_finalize = mv88w8618_pit_finalize,
59
.class_init = mv88w8618_pit_class_init,
60
};
61
31
62
--
32
--
63
2.20.1
33
2.34.1
64
34
65
35
diff view generated by jsdifflib
1
In commit 64f863baeedc8659 we implemented the v8.1M FPCXT_S register,
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
2
but we got the write behaviour wrong. On read, this register reads
3
bits [27:0] of FPSCR plus the CONTROL.SFPA bit. On write, it doesn't
4
just write back those bits -- it writes a value to the whole FPSCR,
5
whose upper 4 bits are zeroes.
6
2
7
We also incorrectly implemented the write-to-FPSCR as a simple store
3
Since commit be8d853766 ("iothread: add I/O thread object") we
8
to vfp.xregs; this skips the "update the softfloat flags" part of
4
never used IOThreadClass / IOTHREAD_CLASS() / IOTHREAD_GET_CLASS(),
9
the vfp_set_fpscr helper so the value would read back correctly but
5
remove these definitions.
10
not actually take effect.
11
6
12
Fix both of these things by doing a complete write to the FPSCR
7
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
13
using the helper function.
8
Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
9
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
10
Message-id: 20230113200138.52869-2-philmd@linaro.org
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
iothread.c | 4 ----
14
1 file changed, 4 deletions(-)
14
15
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
diff --git a/iothread.c b/iothread.c
16
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
17
Message-id: 20201210201433.26262-3-peter.maydell@linaro.org
18
---
19
target/arm/translate-vfp.c.inc | 12 ++++++------
20
1 file changed, 6 insertions(+), 6 deletions(-)
21
22
diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc
23
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
24
--- a/target/arm/translate-vfp.c.inc
18
--- a/iothread.c
25
+++ b/target/arm/translate-vfp.c.inc
19
+++ b/iothread.c
26
@@ -XXX,XX +XXX,XX @@ static bool gen_M_fp_sysreg_write(DisasContext *s, int regno,
20
@@ -XXX,XX +XXX,XX @@
27
}
21
#include "qemu/rcu.h"
28
case ARM_VFP_FPCXT_S:
22
#include "qemu/main-loop.h"
29
{
23
30
- TCGv_i32 sfpa, control, fpscr;
24
-typedef ObjectClass IOThreadClass;
31
- /* Set FPSCR[27:0] and CONTROL.SFPA from value */
25
-
32
+ TCGv_i32 sfpa, control;
26
-DECLARE_CLASS_CHECKERS(IOThreadClass, IOTHREAD,
33
+ /*
27
- TYPE_IOTHREAD)
34
+ * Set FPSCR and CONTROL.SFPA from value; the new FPSCR takes
28
35
+ * bits [27:0] from value and zeroes bits [31:28].
29
#ifdef CONFIG_POSIX
36
+ */
30
/* Benchmark results from 2016 on NVMe SSD drives show max polling times around
37
tmp = loadfn(s, opaque);
38
sfpa = tcg_temp_new_i32();
39
tcg_gen_shri_i32(sfpa, tmp, 31);
40
@@ -XXX,XX +XXX,XX @@ static bool gen_M_fp_sysreg_write(DisasContext *s, int regno,
41
tcg_gen_deposit_i32(control, control, sfpa,
42
R_V7M_CONTROL_SFPA_SHIFT, 1);
43
store_cpu_field(control, v7m.control[M_REG_S]);
44
- fpscr = load_cpu_field(vfp.xregs[ARM_VFP_FPSCR]);
45
- tcg_gen_andi_i32(fpscr, fpscr, FPCR_NZCV_MASK);
46
tcg_gen_andi_i32(tmp, tmp, ~FPCR_NZCV_MASK);
47
- tcg_gen_or_i32(fpscr, fpscr, tmp);
48
- store_cpu_field(fpscr, vfp.xregs[ARM_VFP_FPSCR]);
49
+ gen_helper_vfp_set_fpscr(cpu_env, tmp);
50
tcg_temp_free_i32(tmp);
51
tcg_temp_free_i32(sfpa);
52
break;
53
--
31
--
54
2.20.1
32
2.34.1
55
33
56
34
diff view generated by jsdifflib
1
From: Gan Qixin <ganqixin@huawei.com>
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
2
2
3
When running device-introspect-test, a memory leak occurred in the a10_pit_init
3
QOM *DECLARE* macros expect a typedef as first argument,
4
function, so use ptimer_free() in the finalize function to avoid it.
4
not a structure. Replace 'struct IRQState' by 'IRQState'
5
to avoid when modifying the macros:
5
6
6
ASAN shows memory leak stack:
7
../hw/core/irq.c:29:1: error: declaration of anonymous struct must be a definition
8
DECLARE_INSTANCE_CHECKER(struct IRQState, IRQ,
9
^
7
10
8
Indirect leak of 288 byte(s) in 6 object(s) allocated from:
11
Use OBJECT_DECLARE_SIMPLE_TYPE instead of DECLARE_INSTANCE_CHECKER.
9
#0 0xffffab97e1f0 in __interceptor_calloc (/lib64/libasan.so.5+0xee1f0)
10
#1 0xffffab256800 in g_malloc0 (/lib64/libglib-2.0.so.0+0x56800)
11
#2 0xaaabf555db84 in timer_new_full /qemu/include/qemu/timer.h:523
12
#3 0xaaabf555db84 in timer_new /qemu/include/qemu/timer.h:544
13
#4 0xaaabf555db84 in timer_new_ns /qemu/include/qemu/timer.h:562
14
#5 0xaaabf555db84 in ptimer_init /qemu/hw/core/ptimer.c:433
15
#6 0xaaabf57415e8 in a10_pit_init /qemu/hw/timer/allwinner-a10-pit.c:278
16
#7 0xaaabf6339f6c in object_initialize_with_type /qemu/qom/object.c:515
17
#8 0xaaabf633ca04 in object_initialize_child_with_propsv /qemu/qom/object.c:564
18
#9 0xaaabf633cc08 in object_initialize_child_with_props /qemu/qom/object.c:547
19
#10 0xaaabf5b94680 in aw_a10_init /qemu/hw/arm/allwinner-a10.c:49
20
#11 0xaaabf6339f6c in object_initialize_with_type /qemu/qom/object.c:515
21
#12 0xaaabf633a1e0 in object_new_with_type /qemu/qom/object.c:729
22
12
23
Reported-by: Euler Robot <euler.robot@huawei.com>
13
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
24
Signed-off-by: Gan Qixin <ganqixin@huawei.com>
14
Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
25
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
15
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
16
Message-id: 20230113200138.52869-3-philmd@linaro.org
26
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
27
---
18
---
28
hw/timer/allwinner-a10-pit.c | 11 +++++++++++
19
hw/core/irq.c | 9 ++++-----
29
1 file changed, 11 insertions(+)
20
1 file changed, 4 insertions(+), 5 deletions(-)
30
21
31
diff --git a/hw/timer/allwinner-a10-pit.c b/hw/timer/allwinner-a10-pit.c
22
diff --git a/hw/core/irq.c b/hw/core/irq.c
32
index XXXXXXX..XXXXXXX 100644
23
index XXXXXXX..XXXXXXX 100644
33
--- a/hw/timer/allwinner-a10-pit.c
24
--- a/hw/core/irq.c
34
+++ b/hw/timer/allwinner-a10-pit.c
25
+++ b/hw/core/irq.c
35
@@ -XXX,XX +XXX,XX @@ static void a10_pit_init(Object *obj)
26
@@ -XXX,XX +XXX,XX @@
36
}
27
#include "hw/irq.h"
28
#include "qom/object.h"
29
30
-DECLARE_INSTANCE_CHECKER(struct IRQState, IRQ,
31
- TYPE_IRQ)
32
+OBJECT_DECLARE_SIMPLE_TYPE(IRQState, IRQ)
33
34
struct IRQState {
35
Object parent_obj;
36
@@ -XXX,XX +XXX,XX @@ qemu_irq *qemu_allocate_irqs(qemu_irq_handler handler, void *opaque, int n)
37
38
qemu_irq qemu_allocate_irq(qemu_irq_handler handler, void *opaque, int n)
39
{
40
- struct IRQState *irq;
41
+ IRQState *irq;
42
43
irq = IRQ(object_new(TYPE_IRQ));
44
irq->handler = handler;
45
@@ -XXX,XX +XXX,XX @@ void qemu_free_irq(qemu_irq irq)
46
47
static void qemu_notirq(void *opaque, int line, int level)
48
{
49
- struct IRQState *irq = opaque;
50
+ IRQState *irq = opaque;
51
52
irq->handler(irq->opaque, irq->n, !level);
37
}
53
}
38
54
@@ -XXX,XX +XXX,XX @@ void qemu_irq_intercept_in(qemu_irq *gpio_in, qemu_irq_handler handler, int n)
39
+static void a10_pit_finalize(Object *obj)
55
static const TypeInfo irq_type_info = {
40
+{
56
.name = TYPE_IRQ,
41
+ AwA10PITState *s = AW_A10_PIT(obj);
57
.parent = TYPE_OBJECT,
42
+ int i;
58
- .instance_size = sizeof(struct IRQState),
43
+
59
+ .instance_size = sizeof(IRQState),
44
+ for (i = 0; i < AW_A10_PIT_TIMER_NR; i++) {
45
+ ptimer_free(s->timer[i]);
46
+ }
47
+}
48
+
49
static void a10_pit_class_init(ObjectClass *klass, void *data)
50
{
51
DeviceClass *dc = DEVICE_CLASS(klass);
52
@@ -XXX,XX +XXX,XX @@ static const TypeInfo a10_pit_info = {
53
.parent = TYPE_SYS_BUS_DEVICE,
54
.instance_size = sizeof(AwA10PITState),
55
.instance_init = a10_pit_init,
56
+ .instance_finalize = a10_pit_finalize,
57
.class_init = a10_pit_class_init,
58
};
60
};
59
61
62
static void irq_register_types(void)
60
--
63
--
61
2.20.1
64
2.34.1
62
65
63
66
diff view generated by jsdifflib
1
From: Andrew Jones <drjones@redhat.com>
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
2
2
3
virt machine's 'smp_cpus' and machine->smp.cpus must always have the
3
Missed during automatic conversion from commit 8063396bf3
4
same value. And, anywhere we have virt machine state we have machine
4
("Use OBJECT_DECLARE_SIMPLE_TYPE when possible").
5
state. So let's remove the redundancy. Also, to make it easier to see
6
that machine->smp is the true source for "smp_cpus" and "max_cpus",
7
avoid passing them in function parameters, preferring instead to get
8
them from the state.
9
5
10
No functional change intended.
6
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
11
7
Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
12
Signed-off-by: Andrew Jones <drjones@redhat.com>
8
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
13
Reviewed-by: David Edmondson <david.edmondson@oracle.com>
9
Message-id: 20230113200138.52869-4-philmd@linaro.org
14
Reviewed-by: Ying Fang <fangying1@huawei.com>
15
Message-id: 20201215174815.51520-1-drjones@redhat.com
16
[PMM: minor formatting tweak to smp_cpus variable declaration]
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
---
11
---
19
include/hw/arm/virt.h | 3 +--
12
include/hw/or-irq.h | 3 +--
20
hw/arm/virt-acpi-build.c | 9 +++++----
13
1 file changed, 1 insertion(+), 2 deletions(-)
21
hw/arm/virt.c | 21 ++++++++++-----------
22
3 files changed, 16 insertions(+), 17 deletions(-)
23
14
24
diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
15
diff --git a/include/hw/or-irq.h b/include/hw/or-irq.h
25
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
26
--- a/include/hw/arm/virt.h
17
--- a/include/hw/or-irq.h
27
+++ b/include/hw/arm/virt.h
18
+++ b/include/hw/or-irq.h
28
@@ -XXX,XX +XXX,XX @@ struct VirtMachineState {
29
MemMapEntry *memmap;
30
char *pciehb_nodename;
31
const int *irqmap;
32
- int smp_cpus;
33
void *fdt;
34
int fdt_size;
35
uint32_t clock_phandle;
36
@@ -XXX,XX +XXX,XX @@ static inline int virt_gicv3_redist_region_count(VirtMachineState *vms)
37
38
assert(vms->gic_version == VIRT_GIC_VERSION_3);
39
40
- return vms->smp_cpus > redist0_capacity ? 2 : 1;
41
+ return MACHINE(vms)->smp.cpus > redist0_capacity ? 2 : 1;
42
}
43
44
#endif /* QEMU_ARM_VIRT_H */
45
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
46
index XXXXXXX..XXXXXXX 100644
47
--- a/hw/arm/virt-acpi-build.c
48
+++ b/hw/arm/virt-acpi-build.c
49
@@ -XXX,XX +XXX,XX @@
19
@@ -XXX,XX +XXX,XX @@
50
20
51
#define ACPI_BUILD_TABLE_SIZE 0x20000
21
typedef struct OrIRQState qemu_or_irq;
52
22
53
-static void acpi_dsdt_add_cpus(Aml *scope, int smp_cpus)
23
-DECLARE_INSTANCE_CHECKER(qemu_or_irq, OR_IRQ,
54
+static void acpi_dsdt_add_cpus(Aml *scope, VirtMachineState *vms)
24
- TYPE_OR_IRQ)
55
{
25
+OBJECT_DECLARE_SIMPLE_TYPE(OrIRQState, OR_IRQ)
56
+ MachineState *ms = MACHINE(vms);
26
57
uint16_t i;
27
struct OrIRQState {
58
28
DeviceState parent_obj;
59
- for (i = 0; i < smp_cpus; i++) {
60
+ for (i = 0; i < ms->smp.cpus; i++) {
61
Aml *dev = aml_device("C%.03X", i);
62
aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0007")));
63
aml_append(dev, aml_name_decl("_UID", aml_int(i)));
64
@@ -XXX,XX +XXX,XX @@ build_madt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
65
gicd->base_address = cpu_to_le64(memmap[VIRT_GIC_DIST].base);
66
gicd->version = vms->gic_version;
67
68
- for (i = 0; i < vms->smp_cpus; i++) {
69
+ for (i = 0; i < MACHINE(vms)->smp.cpus; i++) {
70
AcpiMadtGenericCpuInterface *gicc = acpi_data_push(table_data,
71
sizeof(*gicc));
72
ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(i));
73
@@ -XXX,XX +XXX,XX @@ build_dsdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
74
* the RTC ACPI device at all when using UEFI.
75
*/
76
scope = aml_scope("\\_SB");
77
- acpi_dsdt_add_cpus(scope, vms->smp_cpus);
78
+ acpi_dsdt_add_cpus(scope, vms);
79
acpi_dsdt_add_uart(scope, &memmap[VIRT_UART],
80
(irqmap[VIRT_UART] + ARM_SPI_BASE));
81
if (vmc->acpi_expose_flash) {
82
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
83
index XXXXXXX..XXXXXXX 100644
84
--- a/hw/arm/virt.c
85
+++ b/hw/arm/virt.c
86
@@ -XXX,XX +XXX,XX @@ static void fdt_add_timer_nodes(const VirtMachineState *vms)
87
if (vms->gic_version == VIRT_GIC_VERSION_2) {
88
irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START,
89
GIC_FDT_IRQ_PPI_CPU_WIDTH,
90
- (1 << vms->smp_cpus) - 1);
91
+ (1 << MACHINE(vms)->smp.cpus) - 1);
92
}
93
94
qemu_fdt_add_subnode(vms->fdt, "/timer");
95
@@ -XXX,XX +XXX,XX @@ static void fdt_add_cpu_nodes(const VirtMachineState *vms)
96
int cpu;
97
int addr_cells = 1;
98
const MachineState *ms = MACHINE(vms);
99
+ int smp_cpus = ms->smp.cpus;
100
101
/*
102
* From Documentation/devicetree/bindings/arm/cpus.txt
103
@@ -XXX,XX +XXX,XX @@ static void fdt_add_cpu_nodes(const VirtMachineState *vms)
104
* The simplest way to go is to examine affinity IDs of all our CPUs. If
105
* at least one of them has Aff3 populated, we set #address-cells to 2.
106
*/
107
- for (cpu = 0; cpu < vms->smp_cpus; cpu++) {
108
+ for (cpu = 0; cpu < smp_cpus; cpu++) {
109
ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu));
110
111
if (armcpu->mp_affinity & ARM_AFF3_MASK) {
112
@@ -XXX,XX +XXX,XX @@ static void fdt_add_cpu_nodes(const VirtMachineState *vms)
113
qemu_fdt_setprop_cell(vms->fdt, "/cpus", "#address-cells", addr_cells);
114
qemu_fdt_setprop_cell(vms->fdt, "/cpus", "#size-cells", 0x0);
115
116
- for (cpu = vms->smp_cpus - 1; cpu >= 0; cpu--) {
117
+ for (cpu = smp_cpus - 1; cpu >= 0; cpu--) {
118
char *nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
119
ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu));
120
CPUState *cs = CPU(armcpu);
121
@@ -XXX,XX +XXX,XX @@ static void fdt_add_cpu_nodes(const VirtMachineState *vms)
122
qemu_fdt_setprop_string(vms->fdt, nodename, "compatible",
123
armcpu->dtb_compatible);
124
125
- if (vms->psci_conduit != QEMU_PSCI_CONDUIT_DISABLED
126
- && vms->smp_cpus > 1) {
127
+ if (vms->psci_conduit != QEMU_PSCI_CONDUIT_DISABLED && smp_cpus > 1) {
128
qemu_fdt_setprop_string(vms->fdt, nodename,
129
"enable-method", "psci");
130
}
131
@@ -XXX,XX +XXX,XX @@ static void fdt_add_pmu_nodes(const VirtMachineState *vms)
132
if (vms->gic_version == VIRT_GIC_VERSION_2) {
133
irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START,
134
GIC_FDT_IRQ_PPI_CPU_WIDTH,
135
- (1 << vms->smp_cpus) - 1);
136
+ (1 << MACHINE(vms)->smp.cpus) - 1);
137
}
138
139
qemu_fdt_add_subnode(vms->fdt, "/pmu");
140
@@ -XXX,XX +XXX,XX @@ static void finalize_gic_version(VirtMachineState *vms)
141
* virt_cpu_post_init() must be called after the CPUs have
142
* been realized and the GIC has been created.
143
*/
144
-static void virt_cpu_post_init(VirtMachineState *vms, int max_cpus,
145
- MemoryRegion *sysmem)
146
+static void virt_cpu_post_init(VirtMachineState *vms, MemoryRegion *sysmem)
147
{
148
+ int max_cpus = MACHINE(vms)->smp.max_cpus;
149
bool aarch64, pmu, steal_time;
150
CPUState *cpu;
151
152
@@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine)
153
exit(1);
154
}
155
156
- vms->smp_cpus = smp_cpus;
157
-
158
if (vms->virt && kvm_enabled()) {
159
error_report("mach-virt: KVM does not support providing "
160
"Virtualization extensions to the guest CPU");
161
@@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine)
162
create_fdt(vms);
163
164
possible_cpus = mc->possible_cpu_arch_ids(machine);
165
+ assert(possible_cpus->len == max_cpus);
166
for (n = 0; n < possible_cpus->len; n++) {
167
Object *cpuobj;
168
CPUState *cs;
169
@@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine)
170
171
create_gic(vms);
172
173
- virt_cpu_post_init(vms, possible_cpus->len, sysmem);
174
+ virt_cpu_post_init(vms, sysmem);
175
176
fdt_add_pmu_nodes(vms);
177
178
--
29
--
179
2.20.1
30
2.34.1
180
31
181
32
diff view generated by jsdifflib
1
From: Gan Qixin <ganqixin@huawei.com>
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
2
2
3
When running device-introspect-test, a memory leak occurred in the
3
OBJECT_DECLARE_SIMPLE_TYPE() macro provides the OrIRQState
4
digic_timer_init function, so use ptimer_free() in the finalize function to
4
declaration for free. Besides, the QOM code style is to use
5
avoid it.
5
the structure name as typedef, and QEMU style is to use Camel
6
6
Case, so rename qemu_or_irq as OrIRQState.
7
ASAN shows memory leak stack:
7
8
8
Mechanical change using:
9
Indirect leak of 288 byte(s) in 3 object(s) allocated from:
9
10
#0 0xffffab97e1f0 in __interceptor_calloc (/lib64/libasan.so.5+0xee1f0)
10
$ sed -i -e 's/qemu_or_irq/OrIRQState/g' $(git grep -l qemu_or_irq)
11
#1 0xffffab256800 in g_malloc0 (/lib64/libglib-2.0.so.0+0x56800)
11
12
#2 0xaaabf555db78 in ptimer_init /qemu/hw/core/ptimer.c:432
12
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
13
#3 0xaaabf5b04084 in digic_timer_init /qemu/hw/timer/digic-timer.c:142
13
Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
14
#4 0xaaabf6339f6c in object_initialize_with_type /qemu/qom/object.c:515
14
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
15
#5 0xaaabf633ca04 in object_initialize_child_with_propsv /qemu/qom/object.c:564
15
Message-id: 20230113200138.52869-5-philmd@linaro.org
16
#6 0xaaabf633cc08 in object_initialize_child_with_props /qemu/qom/object.c:547
17
#7 0xaaabf5b40e84 in digic_init /qemu/hw/arm/digic.c:46
18
#8 0xaaabf6339f6c in object_initialize_with_type /qemu/qom/object.c:515
19
#9 0xaaabf633a1e0 in object_new_with_type /qemu/qom/object.c:729
20
#10 0xaaabf6375e40 in qmp_device_list_properties /qemu/qom/qom-qmp-cmds.c:153
21
#11 0xaaabf653d8ec in qmp_marshal_device_list_properties /qemu/qapi/qapi-commands-qdev.c:59
22
#12 0xaaabf6587d08 in do_qmp_dispatch_bh /qemu/qapi/qmp-dispatch.c:110
23
24
Reported-by: Euler Robot <euler.robot@huawei.com>
25
Signed-off-by: Gan Qixin <ganqixin@huawei.com>
26
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
27
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
28
---
17
---
29
hw/timer/digic-timer.c | 8 ++++++++
18
include/hw/arm/armsse.h | 6 +++---
30
1 file changed, 8 insertions(+)
19
include/hw/arm/bcm2835_peripherals.h | 2 +-
31
20
include/hw/arm/exynos4210.h | 4 ++--
32
diff --git a/hw/timer/digic-timer.c b/hw/timer/digic-timer.c
21
include/hw/arm/stm32f205_soc.h | 2 +-
33
index XXXXXXX..XXXXXXX 100644
22
include/hw/arm/stm32f405_soc.h | 2 +-
34
--- a/hw/timer/digic-timer.c
23
include/hw/arm/xlnx-versal.h | 6 +++---
35
+++ b/hw/timer/digic-timer.c
24
include/hw/arm/xlnx-zynqmp.h | 2 +-
36
@@ -XXX,XX +XXX,XX @@ static void digic_timer_init(Object *obj)
25
include/hw/or-irq.h | 2 --
37
sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->iomem);
26
hw/arm/exynos4210.c | 4 ++--
27
hw/arm/mps2-tz.c | 2 +-
28
hw/core/or-irq.c | 18 +++++++++---------
29
hw/pci-host/raven.c | 2 +-
30
12 files changed, 25 insertions(+), 27 deletions(-)
31
32
diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h
33
index XXXXXXX..XXXXXXX 100644
34
--- a/include/hw/arm/armsse.h
35
+++ b/include/hw/arm/armsse.h
36
@@ -XXX,XX +XXX,XX @@ struct ARMSSE {
37
TZPPC apb_ppc[NUM_INTERNAL_PPCS];
38
TZMPC mpc[IOTS_NUM_MPC];
39
CMSDKAPBTimer timer[3];
40
- qemu_or_irq ppc_irq_orgate;
41
+ OrIRQState ppc_irq_orgate;
42
SplitIRQ sec_resp_splitter;
43
SplitIRQ ppc_irq_splitter[NUM_PPCS];
44
SplitIRQ mpc_irq_splitter[IOTS_NUM_EXP_MPC + IOTS_NUM_MPC];
45
- qemu_or_irq mpc_irq_orgate;
46
- qemu_or_irq nmi_orgate;
47
+ OrIRQState mpc_irq_orgate;
48
+ OrIRQState nmi_orgate;
49
50
SplitIRQ cpu_irq_splitter[NUM_SSE_IRQS];
51
52
diff --git a/include/hw/arm/bcm2835_peripherals.h b/include/hw/arm/bcm2835_peripherals.h
53
index XXXXXXX..XXXXXXX 100644
54
--- a/include/hw/arm/bcm2835_peripherals.h
55
+++ b/include/hw/arm/bcm2835_peripherals.h
56
@@ -XXX,XX +XXX,XX @@ struct BCM2835PeripheralState {
57
BCM2835AuxState aux;
58
BCM2835FBState fb;
59
BCM2835DMAState dma;
60
- qemu_or_irq orgated_dma_irq;
61
+ OrIRQState orgated_dma_irq;
62
BCM2835ICState ic;
63
BCM2835PropertyState property;
64
BCM2835RngState rng;
65
diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h
66
index XXXXXXX..XXXXXXX 100644
67
--- a/include/hw/arm/exynos4210.h
68
+++ b/include/hw/arm/exynos4210.h
69
@@ -XXX,XX +XXX,XX @@ struct Exynos4210State {
70
MemoryRegion boot_secondary;
71
MemoryRegion bootreg_mem;
72
I2CBus *i2c_if[EXYNOS4210_I2C_NUMBER];
73
- qemu_or_irq pl330_irq_orgate[EXYNOS4210_NUM_DMA];
74
- qemu_or_irq cpu_irq_orgate[EXYNOS4210_NCPUS];
75
+ OrIRQState pl330_irq_orgate[EXYNOS4210_NUM_DMA];
76
+ OrIRQState cpu_irq_orgate[EXYNOS4210_NCPUS];
77
A9MPPrivState a9mpcore;
78
Exynos4210GicState ext_gic;
79
Exynos4210CombinerState int_combiner;
80
diff --git a/include/hw/arm/stm32f205_soc.h b/include/hw/arm/stm32f205_soc.h
81
index XXXXXXX..XXXXXXX 100644
82
--- a/include/hw/arm/stm32f205_soc.h
83
+++ b/include/hw/arm/stm32f205_soc.h
84
@@ -XXX,XX +XXX,XX @@ struct STM32F205State {
85
STM32F2XXADCState adc[STM_NUM_ADCS];
86
STM32F2XXSPIState spi[STM_NUM_SPIS];
87
88
- qemu_or_irq *adc_irqs;
89
+ OrIRQState *adc_irqs;
90
91
MemoryRegion sram;
92
MemoryRegion flash;
93
diff --git a/include/hw/arm/stm32f405_soc.h b/include/hw/arm/stm32f405_soc.h
94
index XXXXXXX..XXXXXXX 100644
95
--- a/include/hw/arm/stm32f405_soc.h
96
+++ b/include/hw/arm/stm32f405_soc.h
97
@@ -XXX,XX +XXX,XX @@ struct STM32F405State {
98
STM32F4xxExtiState exti;
99
STM32F2XXUsartState usart[STM_NUM_USARTS];
100
STM32F2XXTimerState timer[STM_NUM_TIMERS];
101
- qemu_or_irq adc_irqs;
102
+ OrIRQState adc_irqs;
103
STM32F2XXADCState adc[STM_NUM_ADCS];
104
STM32F2XXSPIState spi[STM_NUM_SPIS];
105
106
diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h
107
index XXXXXXX..XXXXXXX 100644
108
--- a/include/hw/arm/xlnx-versal.h
109
+++ b/include/hw/arm/xlnx-versal.h
110
@@ -XXX,XX +XXX,XX @@ struct Versal {
111
} rpu;
112
113
struct {
114
- qemu_or_irq irq_orgate;
115
+ OrIRQState irq_orgate;
116
XlnxXramCtrl ctrl[XLNX_VERSAL_NR_XRAM];
117
} xram;
118
119
@@ -XXX,XX +XXX,XX @@ struct Versal {
120
XlnxCSUDMA dma_src;
121
XlnxCSUDMA dma_dst;
122
MemoryRegion linear_mr;
123
- qemu_or_irq irq_orgate;
124
+ OrIRQState irq_orgate;
125
} ospi;
126
} iou;
127
128
@@ -XXX,XX +XXX,XX @@ struct Versal {
129
XlnxVersalEFuseCtrl efuse_ctrl;
130
XlnxVersalEFuseCache efuse_cache;
131
132
- qemu_or_irq apb_irq_orgate;
133
+ OrIRQState apb_irq_orgate;
134
} pmc;
135
136
struct {
137
diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h
138
index XXXXXXX..XXXXXXX 100644
139
--- a/include/hw/arm/xlnx-zynqmp.h
140
+++ b/include/hw/arm/xlnx-zynqmp.h
141
@@ -XXX,XX +XXX,XX @@ struct XlnxZynqMPState {
142
XlnxZDMA gdma[XLNX_ZYNQMP_NUM_GDMA_CH];
143
XlnxZDMA adma[XLNX_ZYNQMP_NUM_ADMA_CH];
144
XlnxCSUDMA qspi_dma;
145
- qemu_or_irq qspi_irq_orgate;
146
+ OrIRQState qspi_irq_orgate;
147
XlnxZynqMPAPUCtrl apu_ctrl;
148
XlnxZynqMPCRF crf;
149
CadenceTTCState ttc[XLNX_ZYNQMP_NUM_TTC];
150
diff --git a/include/hw/or-irq.h b/include/hw/or-irq.h
151
index XXXXXXX..XXXXXXX 100644
152
--- a/include/hw/or-irq.h
153
+++ b/include/hw/or-irq.h
154
@@ -XXX,XX +XXX,XX @@
155
*/
156
#define MAX_OR_LINES 48
157
158
-typedef struct OrIRQState qemu_or_irq;
159
-
160
OBJECT_DECLARE_SIMPLE_TYPE(OrIRQState, OR_IRQ)
161
162
struct OrIRQState {
163
diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
164
index XXXXXXX..XXXXXXX 100644
165
--- a/hw/arm/exynos4210.c
166
+++ b/hw/arm/exynos4210.c
167
@@ -XXX,XX +XXX,XX @@ static uint64_t exynos4210_calc_affinity(int cpu)
168
return (0x9 << ARM_AFF1_SHIFT) | cpu;
38
}
169
}
39
170
40
+static void digic_timer_finalize(Object *obj)
171
-static DeviceState *pl330_create(uint32_t base, qemu_or_irq *orgate,
41
+{
172
+static DeviceState *pl330_create(uint32_t base, OrIRQState *orgate,
42
+ DigicTimerState *s = DIGIC_TIMER(obj);
173
qemu_irq irq, int nreq, int nevents, int width)
43
+
174
{
44
+ ptimer_free(s->ptimer);
175
SysBusDevice *busdev;
45
+}
176
@@ -XXX,XX +XXX,XX @@ static void exynos4210_init(Object *obj)
46
+
177
47
static void digic_timer_class_init(ObjectClass *klass, void *class_data)
178
for (i = 0; i < ARRAY_SIZE(s->pl330_irq_orgate); i++) {
48
{
179
char *name = g_strdup_printf("pl330-irq-orgate%d", i);
49
DeviceClass *dc = DEVICE_CLASS(klass);
180
- qemu_or_irq *orgate = &s->pl330_irq_orgate[i];
50
@@ -XXX,XX +XXX,XX @@ static const TypeInfo digic_timer_info = {
181
+ OrIRQState *orgate = &s->pl330_irq_orgate[i];
51
.parent = TYPE_SYS_BUS_DEVICE,
182
52
.instance_size = sizeof(DigicTimerState),
183
object_initialize_child(obj, name, orgate, TYPE_OR_IRQ);
53
.instance_init = digic_timer_init,
184
g_free(name);
54
+ .instance_finalize = digic_timer_finalize,
185
diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c
55
.class_init = digic_timer_class_init,
186
index XXXXXXX..XXXXXXX 100644
187
--- a/hw/arm/mps2-tz.c
188
+++ b/hw/arm/mps2-tz.c
189
@@ -XXX,XX +XXX,XX @@ struct MPS2TZMachineState {
190
TZMSC msc[4];
191
CMSDKAPBUART uart[6];
192
SplitIRQ sec_resp_splitter;
193
- qemu_or_irq uart_irq_orgate;
194
+ OrIRQState uart_irq_orgate;
195
DeviceState *lan9118;
196
SplitIRQ cpu_irq_splitter[MPS2TZ_NUMIRQ_MAX];
197
Clock *sysclk;
198
diff --git a/hw/core/or-irq.c b/hw/core/or-irq.c
199
index XXXXXXX..XXXXXXX 100644
200
--- a/hw/core/or-irq.c
201
+++ b/hw/core/or-irq.c
202
@@ -XXX,XX +XXX,XX @@
203
204
static void or_irq_handler(void *opaque, int n, int level)
205
{
206
- qemu_or_irq *s = OR_IRQ(opaque);
207
+ OrIRQState *s = OR_IRQ(opaque);
208
int or_level = 0;
209
int i;
210
211
@@ -XXX,XX +XXX,XX @@ static void or_irq_handler(void *opaque, int n, int level)
212
213
static void or_irq_reset(DeviceState *dev)
214
{
215
- qemu_or_irq *s = OR_IRQ(dev);
216
+ OrIRQState *s = OR_IRQ(dev);
217
int i;
218
219
for (i = 0; i < MAX_OR_LINES; i++) {
220
@@ -XXX,XX +XXX,XX @@ static void or_irq_reset(DeviceState *dev)
221
222
static void or_irq_realize(DeviceState *dev, Error **errp)
223
{
224
- qemu_or_irq *s = OR_IRQ(dev);
225
+ OrIRQState *s = OR_IRQ(dev);
226
227
assert(s->num_lines <= MAX_OR_LINES);
228
229
@@ -XXX,XX +XXX,XX @@ static void or_irq_realize(DeviceState *dev, Error **errp)
230
231
static void or_irq_init(Object *obj)
232
{
233
- qemu_or_irq *s = OR_IRQ(obj);
234
+ OrIRQState *s = OR_IRQ(obj);
235
236
qdev_init_gpio_out(DEVICE(obj), &s->out_irq, 1);
237
}
238
@@ -XXX,XX +XXX,XX @@ static void or_irq_init(Object *obj)
239
240
static bool vmstate_extras_needed(void *opaque)
241
{
242
- qemu_or_irq *s = OR_IRQ(opaque);
243
+ OrIRQState *s = OR_IRQ(opaque);
244
245
return s->num_lines >= OLD_MAX_OR_LINES;
246
}
247
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_or_irq_extras = {
248
.minimum_version_id = 1,
249
.needed = vmstate_extras_needed,
250
.fields = (VMStateField[]) {
251
- VMSTATE_VARRAY_UINT16_UNSAFE(levels, qemu_or_irq, num_lines, 0,
252
+ VMSTATE_VARRAY_UINT16_UNSAFE(levels, OrIRQState, num_lines, 0,
253
vmstate_info_bool, bool),
254
VMSTATE_END_OF_LIST(),
255
},
256
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_or_irq = {
257
.version_id = 1,
258
.minimum_version_id = 1,
259
.fields = (VMStateField[]) {
260
- VMSTATE_BOOL_SUB_ARRAY(levels, qemu_or_irq, 0, OLD_MAX_OR_LINES),
261
+ VMSTATE_BOOL_SUB_ARRAY(levels, OrIRQState, 0, OLD_MAX_OR_LINES),
262
VMSTATE_END_OF_LIST(),
263
},
264
.subsections = (const VMStateDescription*[]) {
265
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_or_irq = {
56
};
266
};
57
267
268
static Property or_irq_properties[] = {
269
- DEFINE_PROP_UINT16("num-lines", qemu_or_irq, num_lines, 1),
270
+ DEFINE_PROP_UINT16("num-lines", OrIRQState, num_lines, 1),
271
DEFINE_PROP_END_OF_LIST(),
272
};
273
274
@@ -XXX,XX +XXX,XX @@ static void or_irq_class_init(ObjectClass *klass, void *data)
275
static const TypeInfo or_irq_type_info = {
276
.name = TYPE_OR_IRQ,
277
.parent = TYPE_DEVICE,
278
- .instance_size = sizeof(qemu_or_irq),
279
+ .instance_size = sizeof(OrIRQState),
280
.instance_init = or_irq_init,
281
.class_init = or_irq_class_init,
282
};
283
diff --git a/hw/pci-host/raven.c b/hw/pci-host/raven.c
284
index XXXXXXX..XXXXXXX 100644
285
--- a/hw/pci-host/raven.c
286
+++ b/hw/pci-host/raven.c
287
@@ -XXX,XX +XXX,XX @@ DECLARE_INSTANCE_CHECKER(PREPPCIState, RAVEN_PCI_HOST_BRIDGE,
288
struct PRePPCIState {
289
PCIHostState parent_obj;
290
291
- qemu_or_irq *or_irq;
292
+ OrIRQState *or_irq;
293
qemu_irq pci_irqs[PCI_NUM_PINS];
294
PCIBus pci_bus;
295
AddressSpace pci_io_as;
58
--
296
--
59
2.20.1
297
2.34.1
60
298
61
299
diff view generated by jsdifflib