Nothing too exciting, but does include the last bits of v8.1M support work.

The following changes since commit e79de63ab1bd1f6550e7b915e433bec1ad1a870a:

Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-tcg-20210107' into staging (2021-01-07 20:34:05 +0000)

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210108

for you to fetch changes up to c9f8511ea8d2b80723af0fea1f716d752c1b5208:

docs/system: arm: Add sabrelite board description (2021-01-08 15:13:39 +0000)

* intc/arm_gic: Fix gic_irq_signaling_enabled() for vCPUs

* target/arm: Fix MTE0_ACTIVE

* target/arm: Implement v8.1M and Cortex-M55 model

* hw/arm/highbank: Drop dead KVM support code

* util/qemu-timer: Make timer_free() imply timer_del()

* various devices: Use ptimer_free() in finalize function

* docs/system: arm: Add sabrelite board description

* sabrelite: Minor fixes to allow booting U-Boot

Andrew Jones (1):

hw/arm/virt: Remove virt machine state 'smp_cpus'

Bin Meng (4):

hw/misc: imx6_ccm: Update PMU_MISC0 reset value

hw/msic: imx6_ccm: Correct register value for silicon type

hw/arm: sabrelite: Connect the Ethernet PHY at address 6

docs/system: arm: Add sabrelite board description

Edgar E. Iglesias (1):

intc/arm_gic: Fix gic_irq_signaling_enabled() for vCPUs

Gan Qixin (7):

digic-timer: Use ptimer_free() in the finalize function to avoid memleaks

allwinner-a10-pit: Use ptimer_free() in the finalize function to avoid memleaks

exynos4210_rtc: Use ptimer_free() in the finalize function to avoid memleaks

exynos4210_pwm: Use ptimer_free() in the finalize function to avoid memleaks

mss-timer: Use ptimer_free() in the finalize function to avoid memleaks

musicpal: Use ptimer_free() in the finalize function to avoid memleaks

exynos4210_mct: Use ptimer_free() in the finalize function to avoid memleaks

Peter Maydell (9):

hw/intc/armv7m_nvic: Correct handling of CCR.BFHFNMIGN

target/arm: Correct store of FPSCR value via FPCXT_S

target/arm: Implement FPCXT_NS fp system register

target/arm: Implement Cortex-M55 model

hw/arm/highbank: Drop dead KVM support code

util/qemu-timer: Make timer_free() imply timer_del()

scripts/coccinelle: New script to remove unnecessary timer_del() calls

Remove superfluous timer_del() calls

target/arm: Remove timer_del()/timer_deinit() before timer_free()

Richard Henderson (1):

target/arm: Fix MTE0_ACTIVE

docs/system/arm/sabrelite.rst | 119 ++++++++++++++++++++++++++

docs/system/target-arm.rst | 1 +

scripts/coccinelle/timer-del-timer-free.cocci | 18 ++++

include/hw/arm/virt.h | 3 +-

include/qemu/timer.h | 24 +++---

block/iscsi.c | 2 -

block/nbd.c | 1 -

block/qcow2.c | 1 -

hw/arm/highbank.c | 14 +--

hw/arm/musicpal.c | 12 +++

hw/arm/sabrelite.c | 4 +

hw/arm/virt-acpi-build.c | 9 +-

hw/arm/virt.c | 21 +++--

hw/block/nvme.c | 2 -

hw/char/serial.c | 2 -

hw/char/virtio-serial-bus.c | 2 -

hw/ide/core.c | 1 -

hw/input/hid.c | 1 -

hw/intc/apic.c | 1 -

hw/intc/arm_gic.c | 4 +-

hw/intc/armv7m_nvic.c | 15 ++++

hw/intc/ioapic.c | 1 -

hw/ipmi/ipmi_bmc_extern.c | 1 -

hw/misc/imx6_ccm.c | 4 +-

hw/net/e1000.c | 3 -

hw/net/e1000e_core.c | 8 --

hw/net/pcnet-pci.c | 1 -

hw/net/rtl8139.c | 1 -

hw/net/spapr_llan.c | 1 -

hw/net/virtio-net.c | 2 -

hw/rtc/exynos4210_rtc.c | 9 ++

hw/s390x/s390-pci-inst.c | 1 -

hw/sd/sd.c | 1 -

hw/sd/sdhci.c | 2 -

hw/timer/allwinner-a10-pit.c | 11 +++

hw/timer/digic-timer.c | 8 ++

hw/timer/exynos4210_mct.c | 14 +++

hw/timer/exynos4210_pwm.c | 11 +++

hw/timer/mss-timer.c | 13 +++

hw/usb/dev-hub.c | 1 -

hw/usb/hcd-ehci.c | 1 -

hw/usb/hcd-ohci-pci.c | 1 -

hw/usb/hcd-uhci.c | 1 -

hw/usb/hcd-xhci.c | 1 -

hw/usb/redirect.c | 1 -

hw/vfio/display.c | 1 -

hw/virtio/vhost-vsock-common.c | 1 -

hw/virtio/virtio-balloon.c | 1 -

hw/virtio/virtio-rng.c | 1 -

hw/watchdog/wdt_diag288.c | 1 -

hw/watchdog/wdt_i6300esb.c | 1 -

migration/colo.c | 1 -

monitor/hmp-cmds.c | 1 -

net/announce.c | 1 -

net/colo-compare.c | 1 -

net/slirp.c | 1 -

replay/replay-debugging.c | 1 -

target/arm/cpu.c | 2 -

target/arm/cpu_tcg.c | 42 +++++++++

target/arm/helper.c | 2 +-

target/s390x/cpu.c | 2 -

ui/console.c | 1 -

ui/spice-core.c | 1 -

util/throttle.c | 1 -

target/arm/translate-vfp.c.inc | 114 ++++++++++++++++++++++--

65 files changed, 421 insertions(+), 111 deletions(-)

create mode 100644 docs/system/arm/sabrelite.rst

create mode 100644 scripts/coccinelle/timer-del-timer-free.cocci

From: Andrew Jones <drjones@redhat.com>

virt machine's 'smp_cpus' and machine->smp.cpus must always have the

same value. And, anywhere we have virt machine state we have machine

state. So let's remove the redundancy. Also, to make it easier to see

that machine->smp is the true source for "smp_cpus" and "max_cpus",

avoid passing them in function parameters, preferring instead to get

them from the state.

No functional change intended.

Signed-off-by: Andrew Jones <drjones@redhat.com>

Reviewed-by: David Edmondson <david.edmondson@oracle.com>

Reviewed-by: Ying Fang <fangying1@huawei.com>

Message-id: 20201215174815.51520-1-drjones@redhat.com

[PMM: minor formatting tweak to smp_cpus variable declaration]

include/hw/arm/virt.h | 3 +--

hw/arm/virt-acpi-build.c | 9 +++++----

hw/arm/virt.c | 21 ++++++++++-----------

3 files changed, 16 insertions(+), 17 deletions(-)

MemMapEntry *memmap;

char *pciehb_nodename;

const int *irqmap;

- int smp_cpus;

void *fdt;

int fdt_size;

uint32_t clock_phandle;

@@ -XXX,XX +XXX,XX @@ static inline int virt_gicv3_redist_region_count(VirtMachineState *vms)

assert(vms->gic_version == VIRT_GIC_VERSION_3);

- return vms->smp_cpus > redist0_capacity ? 2 : 1;

+ return MACHINE(vms)->smp.cpus > redist0_capacity ? 2 : 1;

}

#endif /* QEMU_ARM_VIRT_H */

diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/arm/virt-acpi-build.c

+++ b/hw/arm/virt-acpi-build.c

@@ -XXX,XX +XXX,XX @@

#define ACPI_BUILD_TABLE_SIZE 0x20000

-static void acpi_dsdt_add_cpus(Aml *scope, int smp_cpus)

+static void acpi_dsdt_add_cpus(Aml *scope, VirtMachineState *vms)

{

+ MachineState *ms = MACHINE(vms);

uint16_t i;

- for (i = 0; i < smp_cpus; i++) {

+ for (i = 0; i < ms->smp.cpus; i++) {

Aml *dev = aml_device("C%.03X", i);

aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0007")));

aml_append(dev, aml_name_decl("_UID", aml_int(i)));

@@ -XXX,XX +XXX,XX @@ build_madt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)

gicd->base_address = cpu_to_le64(memmap[VIRT_GIC_DIST].base);

gicd->version = vms->gic_version;

- for (i = 0; i < vms->smp_cpus; i++) {

+ for (i = 0; i < MACHINE(vms)->smp.cpus; i++) {

AcpiMadtGenericCpuInterface *gicc = acpi_data_push(table_data,

sizeof(*gicc));

ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(i));

@@ -XXX,XX +XXX,XX @@ build_dsdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)

* the RTC ACPI device at all when using UEFI.

*/

scope = aml_scope("\\_SB");

- acpi_dsdt_add_cpus(scope, vms->smp_cpus);

+ acpi_dsdt_add_cpus(scope, vms);

acpi_dsdt_add_uart(scope, &memmap[VIRT_UART],

(irqmap[VIRT_UART] + ARM_SPI_BASE));

if (vmc->acpi_expose_flash) {

@@ -XXX,XX +XXX,XX @@ static void fdt_add_timer_nodes(const VirtMachineState *vms)

if (vms->gic_version == VIRT_GIC_VERSION_2) {

irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START,

GIC_FDT_IRQ_PPI_CPU_WIDTH,

- (1 << vms->smp_cpus) - 1);

+ (1 << MACHINE(vms)->smp.cpus) - 1);

qemu_fdt_add_subnode(vms->fdt, "/timer");

@@ -XXX,XX +XXX,XX @@ static void fdt_add_cpu_nodes(const VirtMachineState *vms)

int cpu;

int addr_cells = 1;

const MachineState *ms = MACHINE(vms);

+ int smp_cpus = ms->smp.cpus;

/*

* From Documentation/devicetree/bindings/arm/cpus.txt

@@ -XXX,XX +XXX,XX @@ static void fdt_add_cpu_nodes(const VirtMachineState *vms)

* The simplest way to go is to examine affinity IDs of all our CPUs. If

* at least one of them has Aff3 populated, we set #address-cells to 2.

*/

- for (cpu = 0; cpu < vms->smp_cpus; cpu++) {

+ for (cpu = 0; cpu < smp_cpus; cpu++) {

ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu));

if (armcpu->mp_affinity & ARM_AFF3_MASK) {

@@ -XXX,XX +XXX,XX @@ static void fdt_add_cpu_nodes(const VirtMachineState *vms)

qemu_fdt_setprop_cell(vms->fdt, "/cpus", "#address-cells", addr_cells);

qemu_fdt_setprop_cell(vms->fdt, "/cpus", "#size-cells", 0x0);

- for (cpu = vms->smp_cpus - 1; cpu >= 0; cpu--) {

+ for (cpu = smp_cpus - 1; cpu >= 0; cpu--) {

char *nodename = g_strdup_printf("/cpus/cpu@%d", cpu);

ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu));

CPUState *cs = CPU(armcpu);

@@ -XXX,XX +XXX,XX @@ static void fdt_add_cpu_nodes(const VirtMachineState *vms)

qemu_fdt_setprop_string(vms->fdt, nodename, "compatible",

armcpu->dtb_compatible);

- if (vms->psci_conduit != QEMU_PSCI_CONDUIT_DISABLED

- && vms->smp_cpus > 1) {

+ if (vms->psci_conduit != QEMU_PSCI_CONDUIT_DISABLED && smp_cpus > 1) {

qemu_fdt_setprop_string(vms->fdt, nodename,

"enable-method", "psci");

qemu_fdt_add_subnode(vms->fdt, "/pmu");

@@ -XXX,XX +XXX,XX @@ static void finalize_gic_version(VirtMachineState *vms)

* virt_cpu_post_init() must be called after the CPUs have

* been realized and the GIC has been created.

*/

-static void virt_cpu_post_init(VirtMachineState *vms, int max_cpus,

- MemoryRegion *sysmem)

+static void virt_cpu_post_init(VirtMachineState *vms, MemoryRegion *sysmem)

+ int max_cpus = MACHINE(vms)->smp.max_cpus;

bool aarch64, pmu, steal_time;

CPUState *cpu;

@@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine)

exit(1);

}

- vms->smp_cpus = smp_cpus;

-

if (vms->virt && kvm_enabled()) {

error_report("mach-virt: KVM does not support providing "

"Virtualization extensions to the guest CPU");

@@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine)

create_fdt(vms);

possible_cpus = mc->possible_cpu_arch_ids(machine);

+ assert(possible_cpus->len == max_cpus);

for (n = 0; n < possible_cpus->len; n++) {

Object *cpuobj;

CPUState *cs;

@@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine)

create_gic(vms);

- virt_cpu_post_init(vms, possible_cpus->len, sysmem);

+ virt_cpu_post_init(vms, sysmem);

fdt_add_pmu_nodes(vms);

2.20.1

From: Bin Meng <bin.meng@windriver.com>

U-Boot expects PMU_MISC0 register bit 7 is set (see init_bandgap()

in arch/arm/mach-imx/mx6/soc.c) during boot. This bit indicates the

bandgap has stabilized.

With this change, the latest upstream U-Boot (v2021.01-rc3) for imx6

sabrelite board (mx6qsabrelite_defconfig), with a slight change made

by switching CONFIG_OF_SEPARATE to CONFIG_OF_EMBED, boots to U-Boot

shell on QEMU with the following command:

$ qemu-system-arm -M sabrelite -smp 4 -m 1G -kernel u-boot \

-display none -serial null -serial stdio

Boot log below:

U-Boot 2021.01-rc3 (Dec 12 2020 - 17:40:02 +0800)

CPU: Freescale i.MX?? rev1.0 at 792 MHz

Reset cause: POR

Model: Freescale i.MX6 Quad SABRE Lite Board

Board: SABRE Lite

I2C: ready

DRAM: 1 GiB

force_idle_bus: sda=0 scl=0 sda.gp=0x5c scl.gp=0x55

force_idle_bus: failed to clear bus, sda=0 scl=0

force_idle_bus: sda=0 scl=0 sda.gp=0x6d scl.gp=0x6c

force_idle_bus: failed to clear bus, sda=0 scl=0

force_idle_bus: sda=0 scl=0 sda.gp=0xcb scl.gp=0x5

force_idle_bus: failed to clear bus, sda=0 scl=0

MMC: FSL_SDHC: 0, FSL_SDHC: 1

Loading Environment from MMC... *** Warning - No block device, using default environment

In: serial

Out: serial

Err: serial

Net: Board Net Initialization Failed

No ethernet found.

starting USB...

Bus usb@2184000: usb dr_mode not found

USB EHCI 1.00

Bus usb@2184200: USB EHCI 1.00

scanning bus usb@2184000 for devices... 1 USB Device(s) found

scanning bus usb@2184200 for devices... 1 USB Device(s) found

scanning usb for storage devices... 0 Storage Device(s) found

scanning usb for ethernet devices... 0 Ethernet Device(s) found

Hit any key to stop autoboot: 0

=>

Signed-off-by: Bin Meng <bin.meng@windriver.com>

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>

Message-id: 20210106063504.10841-2-bmeng.cn@gmail.com

hw/misc/imx6_ccm.c | 2 +-

diff --git a/hw/misc/imx6_ccm.c b/hw/misc/imx6_ccm.c

--- a/hw/misc/imx6_ccm.c

+++ b/hw/misc/imx6_ccm.c

@@ -XXX,XX +XXX,XX @@ static void imx6_ccm_reset(DeviceState *dev)

s->analog[PMU_REG_3P0] = 0x00000F74;

s->analog[PMU_REG_2P5] = 0x00005071;

s->analog[PMU_REG_CORE] = 0x00402010;

- s->analog[PMU_MISC0] = 0x04000000;

+ s->analog[PMU_MISC0] = 0x04000080;

s->analog[PMU_MISC1] = 0x00000000;

s->analog[PMU_MISC2] = 0x00272727;

2.20.1

In 50244cc76abc we updated mte_check_fail to match the ARM

pseudocode, using the correct EL to select the TCF field.

But we failed to update MTE0_ACTIVE the same way, which led

to g_assert_not_reached().

target/arm/helper.c | 2 +-

1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c

--- a/target/arm/helper.c

+++ b/target/arm/helper.c

@@ -XXX,XX +XXX,XX @@ static uint32_t rebuild_hflags_a64(CPUARMState *env, int el, int fp_el,

if (FIELD_EX32(flags, TBFLAG_A64, UNPRIV)

&& tbid

&& !(env->pstate & PSTATE_TCO)

- && (sctlr & SCTLR_TCF0)

+ && (sctlr & SCTLR_TCF)

&& allocation_tag_access_enabled(env, 0, sctlr)) {

flags = FIELD_DP32(flags, TBFLAG_A64, MTE0_ACTIVE, 1);

}

2.20.1

The CCR is a register most of whose bits are banked between security

states but where BFHFNMIGN is not, and we keep it in the non-secure

entry of the v7m.ccr[] array. The logic which tries to handle this

bit fails to implement the "RAZ/WI from Nonsecure if AIRCR.BFHFNMINS

is zero" requirement; correct the omission.

Message-id: 20201210201433.26262-2-peter.maydell@linaro.org

hw/intc/armv7m_nvic.c | 15 +++++++++++++++

1 file changed, 15 insertions(+)

diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c

--- a/hw/intc/armv7m_nvic.c

+++ b/hw/intc/armv7m_nvic.c

@@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)

val = cpu->env.v7m.ccr[attrs.secure];

val |= cpu->env.v7m.ccr[M_REG_NS] & R_V7M_CCR_BFHFNMIGN_MASK;

+ /* BFHFNMIGN is RAZ/WI from NS if AIRCR.BFHFNMINS is 0 */

+ if (!attrs.secure) {

+ if (!(cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK)) {

+ val &= ~R_V7M_CCR_BFHFNMIGN_MASK;

+ }

+ }

return val;

case 0xd24: /* System Handler Control and State (SHCSR) */

if (!arm_feature(&cpu->env, ARM_FEATURE_V7)) {

@@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,

(cpu->env.v7m.ccr[M_REG_NS] & ~R_V7M_CCR_BFHFNMIGN_MASK)

| (value & R_V7M_CCR_BFHFNMIGN_MASK);

value &= ~R_V7M_CCR_BFHFNMIGN_MASK;

+ } else {

+ * BFHFNMIGN is RAZ/WI from NS if AIRCR.BFHFNMINS is 0, so

+ * preserve the state currently in the NS element of the array

+ */

+ if (!(cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK)) {

+ value &= ~R_V7M_CCR_BFHFNMIGN_MASK;

+ value |= cpu->env.v7m.ccr[M_REG_NS] & R_V7M_CCR_BFHFNMIGN_MASK;

+ }

cpu->env.v7m.ccr[attrs.secure] = value;

2.20.1

Implement the v8.1M FPCXT_NS floating-point system register. This is

a little more complicated than FPCXT_S, because it has specific

handling for "current FP state is inactive", and it only wants to do

PreserveFPState(), not the full set of actions done by

ExecuteFPCheck() which vfp_access_check() implements.

Message-id: 20201210201433.26262-4-peter.maydell@linaro.org

target/arm/translate-vfp.c.inc | 102 ++++++++++++++++++++++++++++++++-

1 file changed, 99 insertions(+), 3 deletions(-)

diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc

--- a/target/arm/translate-vfp.c.inc

+++ b/target/arm/translate-vfp.c.inc

@@ -XXX,XX +XXX,XX @@ static FPSysRegCheckResult fp_sysreg_checks(DisasContext *s, int regno)

}

break;

case ARM_VFP_FPCXT_S:

+ case ARM_VFP_FPCXT_NS:

if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) {

return false;

}

@@ -XXX,XX +XXX,XX @@ static FPSysRegCheckResult fp_sysreg_checks(DisasContext *s, int regno)

return FPSysRegCheckFailed;