Nothing too exciting, but does include the last bits of v8.1M support work.

The following changes since commit e79de63ab1bd1f6550e7b915e433bec1ad1a870a:

Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-tcg-20210107' into staging (2021-01-07 20:34:05 +0000)

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210108

for you to fetch changes up to c9f8511ea8d2b80723af0fea1f716d752c1b5208:

docs/system: arm: Add sabrelite board description (2021-01-08 15:13:39 +0000)

* intc/arm_gic: Fix gic_irq_signaling_enabled() for vCPUs

* target/arm: Fix MTE0_ACTIVE

* target/arm: Implement v8.1M and Cortex-M55 model

* hw/arm/highbank: Drop dead KVM support code

* util/qemu-timer: Make timer_free() imply timer_del()

* various devices: Use ptimer_free() in finalize function

* docs/system: arm: Add sabrelite board description

* sabrelite: Minor fixes to allow booting U-Boot

Andrew Jones (1):

hw/arm/virt: Remove virt machine state 'smp_cpus'

Bin Meng (4):

hw/misc: imx6_ccm: Update PMU_MISC0 reset value

hw/msic: imx6_ccm: Correct register value for silicon type

hw/arm: sabrelite: Connect the Ethernet PHY at address 6

docs/system: arm: Add sabrelite board description

Edgar E. Iglesias (1):

intc/arm_gic: Fix gic_irq_signaling_enabled() for vCPUs

Gan Qixin (7):

digic-timer: Use ptimer_free() in the finalize function to avoid memleaks

allwinner-a10-pit: Use ptimer_free() in the finalize function to avoid memleaks

exynos4210_rtc: Use ptimer_free() in the finalize function to avoid memleaks

exynos4210_pwm: Use ptimer_free() in the finalize function to avoid memleaks

mss-timer: Use ptimer_free() in the finalize function to avoid memleaks

musicpal: Use ptimer_free() in the finalize function to avoid memleaks

exynos4210_mct: Use ptimer_free() in the finalize function to avoid memleaks

From: Andrew Jones <drjones@redhat.com>

virt machine's 'smp_cpus' and machine->smp.cpus must always have the

same value. And, anywhere we have virt machine state we have machine

state. So let's remove the redundancy. Also, to make it easier to see

that machine->smp is the true source for "smp_cpus" and "max_cpus",

avoid passing them in function parameters, preferring instead to get

them from the state.

No functional change intended.

Signed-off-by: Andrew Jones <drjones@redhat.com>

Reviewed-by: David Edmondson <david.edmondson@oracle.com>

Reviewed-by: Ying Fang <fangying1@huawei.com>

Message-id: 20201215174815.51520-1-drjones@redhat.com

[PMM: minor formatting tweak to smp_cpus variable declaration]

include/hw/arm/virt.h | 3 +--

hw/arm/virt-acpi-build.c | 9 +++++----

hw/arm/virt.c | 21 ++++++++++-----------

3 files changed, 16 insertions(+), 17 deletions(-)

@@ -XXX,XX +XXX,XX @@ static void fdt_add_timer_nodes(const VirtMachineState *vms)

if (vms->gic_version == VIRT_GIC_VERSION_2) {

irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START,

GIC_FDT_IRQ_PPI_CPU_WIDTH,

- (1 << vms->smp_cpus) - 1);

+ (1 << MACHINE(vms)->smp.cpus) - 1);

}

qemu_fdt_add_subnode(vms->fdt, "/timer");

@@ -XXX,XX +XXX,XX @@ static void fdt_add_cpu_nodes(const VirtMachineState *vms)

int cpu;

int addr_cells = 1;

const MachineState *ms = MACHINE(vms);

+ int smp_cpus = ms->smp.cpus;

/*

* From Documentation/devicetree/bindings/arm/cpus.txt

@@ -XXX,XX +XXX,XX @@ static void fdt_add_cpu_nodes(const VirtMachineState *vms)

* The simplest way to go is to examine affinity IDs of all our CPUs. If

* at least one of them has Aff3 populated, we set #address-cells to 2.

*/

- for (cpu = 0; cpu < vms->smp_cpus; cpu++) {

+ for (cpu = 0; cpu < smp_cpus; cpu++) {

ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu));

if (armcpu->mp_affinity & ARM_AFF3_MASK) {

@@ -XXX,XX +XXX,XX @@ static void fdt_add_cpu_nodes(const VirtMachineState *vms)

qemu_fdt_setprop_cell(vms->fdt, "/cpus", "#address-cells", addr_cells);

qemu_fdt_setprop_cell(vms->fdt, "/cpus", "#size-cells", 0x0);

- for (cpu = vms->smp_cpus - 1; cpu >= 0; cpu--) {

+ for (cpu = smp_cpus - 1; cpu >= 0; cpu--) {

char *nodename = g_strdup_printf("/cpus/cpu@%d", cpu);

ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu));

CPUState *cs = CPU(armcpu);

@@ -XXX,XX +XXX,XX @@ static void fdt_add_cpu_nodes(const VirtMachineState *vms)

qemu_fdt_setprop_string(vms->fdt, nodename, "compatible",

armcpu->dtb_compatible);

- if (vms->psci_conduit != QEMU_PSCI_CONDUIT_DISABLED

- && vms->smp_cpus > 1) {

+ if (vms->psci_conduit != QEMU_PSCI_CONDUIT_DISABLED && smp_cpus > 1) {

qemu_fdt_setprop_string(vms->fdt, nodename,

"enable-method", "psci");

}

@@ -XXX,XX +XXX,XX @@ static void fdt_add_pmu_nodes(const VirtMachineState *vms)

if (vms->gic_version == VIRT_GIC_VERSION_2) {

irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START,

GIC_FDT_IRQ_PPI_CPU_WIDTH,

- (1 << vms->smp_cpus) - 1);

+ (1 << MACHINE(vms)->smp.cpus) - 1);

}

qemu_fdt_add_subnode(vms->fdt, "/pmu");

@@ -XXX,XX +XXX,XX @@ static void finalize_gic_version(VirtMachineState *vms)

* virt_cpu_post_init() must be called after the CPUs have

* been realized and the GIC has been created.

*/

-static void virt_cpu_post_init(VirtMachineState *vms, int max_cpus,

- MemoryRegion *sysmem)

+static void virt_cpu_post_init(VirtMachineState *vms, MemoryRegion *sysmem)

{

+ int max_cpus = MACHINE(vms)->smp.max_cpus;

bool aarch64, pmu, steal_time;

CPUState *cpu;

- vms->smp_cpus = smp_cpus;

-

if (vms->virt && kvm_enabled()) {

error_report("mach-virt: KVM does not support providing "

"Virtualization extensions to the guest CPU");

@@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine)

create_fdt(vms);

possible_cpus = mc->possible_cpu_arch_ids(machine);

+ assert(possible_cpus->len == max_cpus);

for (n = 0; n < possible_cpus->len; n++) {

Object *cpuobj;

CPUState *cs;

@@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine)

create_gic(vms);

- virt_cpu_post_init(vms, possible_cpus->len, sysmem);

+ virt_cpu_post_init(vms, sysmem);

fdt_add_pmu_nodes(vms);

2.20.1

From: Bin Meng <bin.meng@windriver.com>

This adds the target guide for SABRE Lite board, and documents how

to boot a Linux kernel and U-Boot bootloader.

Signed-off-by: Bin Meng <bin.meng@windriver.com>

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>

Message-id: 20210106063504.10841-5-bmeng.cn@gmail.com

docs/system/arm/sabrelite.rst | 119 ++++++++++++++++++++++++++++++++++

docs/system/target-arm.rst | 1 +

2 files changed, 120 insertions(+)

create mode 100644 docs/system/arm/sabrelite.rst

diff --git a/docs/system/arm/sabrelite.rst b/docs/system/arm/sabrelite.rst

new file mode 100644

index XXXXXXX..XXXXXXX

--- /dev/null

+++ b/docs/system/arm/sabrelite.rst

@@ -XXX,XX +XXX,XX @@

+Boundary Devices SABRE Lite (``sabrelite``)

+===========================================

+

+Boundary Devices SABRE Lite i.MX6 Development Board is a low-cost development

+platform featuring the powerful Freescale / NXP Semiconductor's i.MX 6 Quad

+Applications Processor.

+

+Supported devices

+-----------------

+

+The SABRE Lite machine supports the following devices:

+

+ * Up to 4 Cortex A9 cores

+ * Generic Interrupt Controller

+ * 1 Clock Controller Module

+ * 1 System Reset Controller

+ * 5 UARTs

+ * 2 EPIC timers

+ * 1 GPT timer

+ * 2 Watchdog timers

+ * 1 FEC Ethernet controller

+ * 3 I2C controllers

+ * 7 GPIO controllers

+ * 4 SDHC storage controllers

+ * 4 USB 2.0 host controllers

+ * 5 ECSPI controllers

+ * 1 SST 25VF016B flash

+

+Please note above list is a complete superset the QEMU SABRE Lite machine can

+support. For a normal use case, a device tree blob that represents a real world

+SABRE Lite board, only exposes a subset of devices to the guest software.

+

+Boot options

+------------

+

+The SABRE Lite machine can start using the standard -kernel functionality

+for loading a Linux kernel, U-Boot bootloader or ELF executable.

+

+Running Linux kernel

+--------------------

+

+Linux mainline v5.10 release is tested at the time of writing. To build a Linux

+mainline kernel that can be booted by the SABRE Lite machine, simply configure

+the kernel using the imx_v6_v7_defconfig configuration:

+

+.. code-block:: bash

+

+ $ export ARCH=arm

+ $ export CROSS_COMPILE=arm-linux-gnueabihf-

+ $ make imx_v6_v7_defconfig

+ $ make

+

+To boot the newly built Linux kernel in QEMU with the SABRE Lite machine, use:

+

+.. code-block:: bash

+

+ $ qemu-system-arm -M sabrelite -smp 4 -m 1G \

+ -display none -serial null -serial stdio \

+ -kernel arch/arm/boot/zImage \

+ -dtb arch/arm/boot/dts/imx6q-sabrelite.dtb \

+ -initrd /path/to/rootfs.ext4 \

+ -append "root=/dev/ram"

+

+Running U-Boot

+--------------

+

+U-Boot mainline v2020.10 release is tested at the time of writing. To build a

+U-Boot mainline bootloader that can be booted by the SABRE Lite machine, use

+the mx6qsabrelite_defconfig with similar commands as described above for Linux:

+

+.. code-block:: bash

+

+ $ export CROSS_COMPILE=arm-linux-gnueabihf-

+ $ make mx6qsabrelite_defconfig

+

+Note we need to adjust settings by:

+

+.. code-block:: bash

+

+ $ make menuconfig

+

+then manually select the following configuration in U-Boot:

+

+ Device Tree Control > Provider of DTB for DT Control > Embedded DTB

+

+To start U-Boot using the SABRE Lite machine, provide the u-boot binary to

+the -kernel argument, along with an SD card image with rootfs:

+

+.. code-block:: bash

+

+ $ qemu-system-arm -M sabrelite -smp 4 -m 1G \

+ -display none -serial null -serial stdio \

+ -kernel u-boot

+

+The following example shows booting Linux kernel from dhcp, and uses the

+rootfs on an SD card. This requires some additional command line parameters

+for QEMU:

+

+.. code-block:: none

+

+ -nic user,tftp=/path/to/kernel/zImage \

+ -drive file=sdcard.img,id=rootfs -device sd-card,drive=rootfs

+

+The directory for the built-in TFTP server should also contain the device tree

+blob of the SABRE Lite board. The sample SD card image was populated with the

+root file system with one single partition. You may adjust the kernel "root="

+boot parameter accordingly.

+

+After U-Boot boots, type the following commands in the U-Boot command shell to

+boot the Linux kernel:

+

+.. code-block:: none

+

+ => setenv ethaddr 00:11:22:33:44:55

+ => setenv bootfile zImage

+ => dhcp

+ => tftpboot 14000000 imx6q-sabrelite.dtb

+ => setenv bootargs root=/dev/mmcblk3p1

+ => bootz 12000000 - 14000000

diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst

--- a/docs/system/target-arm.rst

+++ b/docs/system/target-arm.rst

@@ -XXX,XX +XXX,XX @@ undocumented; you can get a complete list by running

arm/versatile

arm/vexpress

arm/aspeed

+ arm/sabrelite

arm/digic

arm/musicpal

arm/gumstix

2.20.1

Implement the v8.1M FPCXT_NS floating-point system register. This is

a little more complicated than FPCXT_S, because it has specific

handling for "current FP state is inactive", and it only wants to do

PreserveFPState(), not the full set of actions done by

ExecuteFPCheck() which vfp_access_check() implements.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Message-id: 20201210201433.26262-4-peter.maydell@linaro.org

target/arm/translate-vfp.c.inc | 102 ++++++++++++++++++++++++++++++++-

1 file changed, 99 insertions(+), 3 deletions(-)

diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc

--- a/target/arm/translate-vfp.c.inc

+++ b/target/arm/translate-vfp.c.inc

@@ -XXX,XX +XXX,XX @@ static FPSysRegCheckResult fp_sysreg_checks(DisasContext *s, int regno)

break;

case ARM_VFP_FPCXT_S:

+ case ARM_VFP_FPCXT_NS:

if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) {

return false;

}

@@ -XXX,XX +XXX,XX @@ static FPSysRegCheckResult fp_sysreg_checks(DisasContext *s, int regno)

return FPSysRegCheckFailed;

- if (!vfp_access_check(s)) {

+ /*

+ * FPCXT_NS is a special case: it has specific handling for

+ * "current FP state is inactive", and must do the PreserveFPState()

+ * but not the usual full set of actions done by ExecuteFPCheck().

+ * So we don't call vfp_access_check() and the callers must handle this.

+ */

+ if (regno != ARM_VFP_FPCXT_NS && !vfp_access_check(s)) {

return FPSysRegCheckDone;

+static void gen_branch_fpInactive(DisasContext *s, TCGCond cond,

+ TCGLabel *label)

+ /*

+ * FPCXT_NS is a special case: it has specific handling for

+ * "current FP state is inactive", and must do the PreserveFPState()

+ * but not the usual full set of actions done by ExecuteFPCheck().

+ * We don't have a TB flag that matches the fpInactive check, so we

+ * do it at runtime as we don't expect FPCXT_NS accesses to be frequent.

+ *

+ * Emit code that checks fpInactive and does a conditional

+ * branch to label based on it:

+ * if cond is TCG_COND_NE then branch if fpInactive != 0 (ie if inactive)

+ * if cond is TCG_COND_EQ then branch if fpInactive == 0 (ie if active)

+ */

+ assert(cond == TCG_COND_EQ || cond == TCG_COND_NE);

+

+ /* fpInactive = FPCCR_NS.ASPEN == 1 && CONTROL.FPCA == 0 */

+ TCGv_i32 aspen, fpca;

+ aspen = load_cpu_field(v7m.fpccr[M_REG_NS]);

+ fpca = load_cpu_field(v7m.control[M_REG_S]);

+ tcg_gen_andi_i32(aspen, aspen, R_V7M_FPCCR_ASPEN_MASK);

+ tcg_gen_xori_i32(aspen, aspen, R_V7M_FPCCR_ASPEN_MASK);

+ tcg_gen_andi_i32(fpca, fpca, R_V7M_CONTROL_FPCA_MASK);

+ tcg_gen_or_i32(fpca, fpca, aspen);

+ tcg_gen_brcondi_i32(tcg_invert_cond(cond), fpca, 0, label);

+ tcg_temp_free_i32(aspen);

+ tcg_temp_free_i32(fpca);

static bool gen_M_fp_sysreg_write(DisasContext *s, int regno,

fp_sysreg_loadfn *loadfn,

@@ -XXX,XX +XXX,XX @@ static bool gen_M_fp_sysreg_write(DisasContext *s, int regno,

/* Do a write to an M-profile floating point system register */

TCGv_i32 tmp;

+ TCGLabel *lab_end = NULL;

switch (fp_sysreg_checks(s, regno)) {

case FPSysRegCheckFailed:

@@ -XXX,XX +XXX,XX @@ static bool gen_M_fp_sysreg_write(DisasContext *s, int regno,

tcg_temp_free_i32(tmp);

break;

}

+ case ARM_VFP_FPCXT_NS:

+ lab_end = gen_new_label();

+ /* fpInactive case: write is a NOP, so branch to end */

+ gen_branch_fpInactive(s, TCG_COND_NE, lab_end);

+ /* !fpInactive: PreserveFPState(), and reads same as FPCXT_S */

+ gen_preserve_fp_state(s);

+ /* fall through */

case ARM_VFP_FPCXT_S:

{

TCGv_i32 sfpa, control;

@@ -XXX,XX +XXX,XX @@ static bool gen_M_fp_sysreg_write(DisasContext *s, int regno,

default:

g_assert_not_reached();

}

+ if (lab_end) {

+ gen_set_label(lab_end);

+ }

return true;

@@ -XXX,XX +XXX,XX @@ static bool gen_M_fp_sysreg_read(DisasContext *s, int regno,

{

/* Do a read from an M-profile floating point system register */

TCGv_i32 tmp;

+ TCGLabel *lab_end = NULL;

+ bool lookup_tb = false;

switch (fp_sysreg_checks(s, regno)) {

case FPSysRegCheckFailed:

@@ -XXX,XX +XXX,XX @@ static bool gen_M_fp_sysreg_read(DisasContext *s, int regno,

fpscr = load_cpu_field(v7m.fpdscr[M_REG_NS]);

gen_helper_vfp_set_fpscr(cpu_env, fpscr);

tcg_temp_free_i32(fpscr);

- gen_lookup_tb(s);

+ lookup_tb = true;

+ break;

+ }

+ case ARM_VFP_FPCXT_NS:

+ {

+ TCGv_i32 control, sfpa, fpscr, fpdscr, zero;

+ TCGLabel *lab_active = gen_new_label();

+

+ lookup_tb = true;

+

+ gen_branch_fpInactive(s, TCG_COND_EQ, lab_active);

+ /* fpInactive case: reads as FPDSCR_NS */

+ TCGv_i32 tmp = load_cpu_field(v7m.fpdscr[M_REG_NS]);

+ storefn(s, opaque, tmp);

+ lab_end = gen_new_label();

+ tcg_gen_br(lab_end);

+

+ gen_set_label(lab_active);

+ /* !fpInactive: Reads the same as FPCXT_S, but side effects differ */

+ gen_preserve_fp_state(s);

+ tmp = tcg_temp_new_i32();

+ sfpa = tcg_temp_new_i32();

+ fpscr = tcg_temp_new_i32();

+ gen_helper_vfp_get_fpscr(fpscr, cpu_env);

+ tcg_gen_andi_i32(tmp, fpscr, ~FPCR_NZCV_MASK);

+ control = load_cpu_field(v7m.control[M_REG_S]);

+ tcg_gen_andi_i32(sfpa, control, R_V7M_CONTROL_SFPA_MASK);

+ tcg_gen_shli_i32(sfpa, sfpa, 31 - R_V7M_CONTROL_SFPA_SHIFT);

+ tcg_gen_or_i32(tmp, tmp, sfpa);

+ tcg_temp_free_i32(control);

+ /* Store result before updating FPSCR, in case it faults */

+ storefn(s, opaque, tmp);

+ /* If SFPA is zero then set FPSCR from FPDSCR_NS */

+ fpdscr = load_cpu_field(v7m.fpdscr[M_REG_NS]);

+ zero = tcg_const_i32(0);

+ tcg_gen_movcond_i32(TCG_COND_EQ, fpscr, sfpa, zero, fpdscr, fpscr);

+ gen_helper_vfp_set_fpscr(cpu_env, fpscr);

+ tcg_temp_free_i32(zero);

+ tcg_temp_free_i32(sfpa);

+ tcg_temp_free_i32(fpdscr);

+ tcg_temp_free_i32(fpscr);

break;

}

default:

g_assert_not_reached();

}

+

+ if (lab_end) {

+ gen_set_label(lab_end);

+ }

+ if (lookup_tb) {

+ gen_lookup_tb(s);

+ }

return true;

}

2.20.1

Currently timer_free() is a simple wrapper for g_free(). This means

that the timer being freed must not be currently active, as otherwise

QEMU might crash later when the active list is processed and still

has a pointer to freed memory on it. As a result almost all calls to

timer_free() are preceded by a timer_del() call, as can be seen in

the output of

git grep -B1 '\<timer_free\>'

This is unfortunate API design as it makes it easy to accidentally

misuse (by forgetting the timer_del()), and the correct use is

annoyingly verbose.

Make timer_free() imply a timer_del().

Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Message-id: 20201215154107.3255-2-peter.maydell@linaro.org

include/qemu/timer.h | 24 +++++++++++++-----------

1 file changed, 13 insertions(+), 11 deletions(-)

diff --git a/include/qemu/timer.h b/include/qemu/timer.h

--- a/include/qemu/timer.h

+++ b/include/qemu/timer.h

@@ -XXX,XX +XXX,XX @@ static inline QEMUTimer *timer_new_ms(QEMUClockType type, QEMUTimerCB *cb,

*/

void timer_deinit(QEMUTimer *ts);

-/**

- * timer_free:

- * @ts: the timer

- *

- * Free a timer (it must not be on the active list)

- */

-static inline void timer_free(QEMUTimer *ts)

-{

- g_free(ts);

-}

-

/**

* timer_del:

* @ts: the timer

@@ -XXX,XX +XXX,XX @@ static inline void timer_free(QEMUTimer *ts)

*/

void timer_del(QEMUTimer *ts);

+ * timer_free:

+ * @ts: the timer

+ * Free a timer. This will call timer_del() for you to remove

+ * the timer from the active list if it was still active.

+static inline void timer_free(QEMUTimer *ts)

+ timer_del(ts);

+ g_free(ts);

* timer_mod_ns:

* @ts: the timer

2.20.1

This commit is the result of running the timer-del-timer-free.cocci

script on the whole source tree.