[PULL 0/3] tcg patch queue
[PULL v3 00/28] tcg patch queue
1
The following changes since commit 41192db338588051f21501abc13743e62b0a5605:
1
v3: One more try to fix macos issues.
2
2
3
Merge remote-tracking branch 'remotes/ehabkost-gl/tags/machine-next-pull-request' into staging (2021-01-01 22:57:15 +0000)
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4
r~
5
6
7
8
The following changes since commit e0209297cddd5e10a07e15fac5cca7aa1a8e0e59:
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10
Merge tag 'pull-ufs-20250217' of https://gitlab.com/jeuk20.kim/qemu into staging (2025-02-18 10:58:48 +0800)
4
11
5
are available in the Git repository at:
12
are available in the Git repository at:
6
13
7
https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20210104
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https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20250215-3
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15
9
for you to fetch changes up to a66424ba17d661007dc13d78c9e3014ccbaf0efb:
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for you to fetch changes up to e726f65867087d86436de05e9f372a86ec1381a6:
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tcg: Add tcg_gen_bswap_tl alias (2021-01-04 06:32:58 -1000)
18
tcg: Remove TCG_TARGET_HAS_{br,set}cond2 from riscv and loongarch64 (2025-02-18 08:29:03 -0800)
12
19
13
----------------------------------------------------------------
20
----------------------------------------------------------------
14
Fix vector clear issue.
21
tcg: Remove last traces of TCG_TARGET_NEED_POOL_LABELS
15
Fix riscv host shift issue.
22
tcg: Cleanups after disallowing 64-on-32
16
Add tcg_gen_bswap_tl.
23
tcg: Introduce constraint for zero register
24
tcg: Remove TCG_TARGET_HAS_{br,set}cond2 from riscv and loongarch64
25
tcg/i386: Use tcg_{high,unsigned}_cond in tcg_out_brcond2
26
linux-user: Move TARGET_SA_RESTORER out of generic/signal.h
27
linux-user: Fix alignment when unmapping excess reservation
28
target/sparc: Fix register selection for all F*TOx and FxTO* instructions
29
target/sparc: Fix gdbstub incorrectly handling registers f32-f62
30
target/sparc: fake UltraSPARC T1 PCR and PIC registers
17
31
18
----------------------------------------------------------------
32
----------------------------------------------------------------
19
Richard Henderson (2):
33
Andreas Schwab (1):
20
tcg: Use memset for large vector byte replication
34
linux-user: Move TARGET_SA_RESTORER out of generic/signal.h
21
tcg: Add tcg_gen_bswap_tl alias
22
35
23
Zihao Yu (1):
36
Artyom Tarasenko (1):
24
tcg/riscv: Fix illegal shift instructions
37
target/sparc: fake UltraSPARC T1 PCR and PIC registers
25
38
26
accel/tcg/tcg-runtime.h | 11 +++++++++++
39
Fabiano Rosas (1):
27
include/exec/helper-proto.h | 4 ++++
40
elfload: Fix alignment when unmapping excess reservation
28
include/tcg/tcg-op.h | 2 ++
29
tcg/tcg-op-gvec.c | 32 ++++++++++++++++++++++++++++++++
30
tcg/riscv/tcg-target.c.inc | 12 ++++++------
31
5 files changed, 55 insertions(+), 6 deletions(-)
32
41
42
Mikael Szreder (2):
43
target/sparc: Fix register selection for all F*TOx and FxTO* instructions
44
target/sparc: Fix gdbstub incorrectly handling registers f32-f62
45
46
Richard Henderson (23):
47
tcg: Remove last traces of TCG_TARGET_NEED_POOL_LABELS
48
tcg: Remove TCG_OVERSIZED_GUEST
49
tcg: Drop support for two address registers in gen_ldst
50
tcg: Merge INDEX_op_qemu_*_{a32,a64}_*
51
tcg/arm: Drop addrhi from prepare_host_addr
52
tcg/i386: Drop addrhi from prepare_host_addr
53
tcg/mips: Drop addrhi from prepare_host_addr
54
tcg/ppc: Drop addrhi from prepare_host_addr
55
tcg: Replace addr{lo,hi}_reg with addr_reg in TCGLabelQemuLdst
56
plugins: Fix qemu_plugin_read_memory_vaddr parameters
57
accel/tcg: Fix tlb_set_page_with_attrs, tlb_set_page
58
target/loongarch: Use VADDR_PRIx for logging pc_next
59
target/mips: Use VADDR_PRIx for logging pc_next
60
include/exec: Change vaddr to uintptr_t
61
include/exec: Use uintptr_t in CPUTLBEntry
62
tcg: Introduce the 'z' constraint for a hardware zero register
63
tcg/aarch64: Use 'z' constraint
64
tcg/loongarch64: Use 'z' constraint
65
tcg/mips: Use 'z' constraint
66
tcg/riscv: Use 'z' constraint
67
tcg/sparc64: Use 'z' constraint
68
tcg/i386: Use tcg_{high,unsigned}_cond in tcg_out_brcond2
69
tcg: Remove TCG_TARGET_HAS_{br,set}cond2 from riscv and loongarch64
70
71
include/exec/tlb-common.h | 10 +-
72
include/exec/vaddr.h | 16 +-
73
include/qemu/atomic.h | 18 +-
74
include/tcg/oversized-guest.h | 23 ---
75
include/tcg/tcg-opc.h | 28 +--
76
include/tcg/tcg.h | 3 +-
77
linux-user/aarch64/target_signal.h | 2 +
78
linux-user/arm/target_signal.h | 2 +
79
linux-user/generic/signal.h | 1 -
80
linux-user/i386/target_signal.h | 2 +
81
linux-user/m68k/target_signal.h | 1 +
82
linux-user/microblaze/target_signal.h | 2 +
83
linux-user/ppc/target_signal.h | 2 +
84
linux-user/s390x/target_signal.h | 2 +
85
linux-user/sh4/target_signal.h | 2 +
86
linux-user/x86_64/target_signal.h | 2 +
87
linux-user/xtensa/target_signal.h | 2 +
88
tcg/aarch64/tcg-target-con-set.h | 12 +-
89
tcg/aarch64/tcg-target.h | 2 +
90
tcg/loongarch64/tcg-target-con-set.h | 15 +-
91
tcg/loongarch64/tcg-target-con-str.h | 1 -
92
tcg/loongarch64/tcg-target-has.h | 2 -
93
tcg/loongarch64/tcg-target.h | 2 +
94
tcg/mips/tcg-target-con-set.h | 26 +--
95
tcg/mips/tcg-target-con-str.h | 1 -
96
tcg/mips/tcg-target.h | 2 +
97
tcg/riscv/tcg-target-con-set.h | 10 +-
98
tcg/riscv/tcg-target-con-str.h | 1 -
99
tcg/riscv/tcg-target-has.h | 2 -
100
tcg/riscv/tcg-target.h | 2 +
101
tcg/sparc64/tcg-target-con-set.h | 12 +-
102
tcg/sparc64/tcg-target-con-str.h | 1 -
103
tcg/sparc64/tcg-target.h | 3 +-
104
tcg/tci/tcg-target.h | 1 -
105
accel/tcg/cputlb.c | 32 +---
106
accel/tcg/tcg-all.c | 9 +-
107
linux-user/elfload.c | 4 +-
108
plugins/api.c | 2 +-
109
target/arm/ptw.c | 34 ----
110
target/loongarch/tcg/translate.c | 2 +-
111
target/mips/tcg/octeon_translate.c | 4 +-
112
target/riscv/cpu_helper.c | 13 +-
113
target/sparc/gdbstub.c | 18 +-
114
target/sparc/translate.c | 19 +++
115
tcg/optimize.c | 21 +--
116
tcg/tcg-op-ldst.c | 103 +++--------
117
tcg/tcg.c | 97 +++++------
118
tcg/tci.c | 119 +++----------
119
docs/devel/multi-thread-tcg.rst | 1 -
120
docs/devel/tcg-ops.rst | 4 +-
121
target/loongarch/tcg/insn_trans/trans_atomic.c.inc | 2 +-
122
target/sparc/insns.decode | 19 ++-
123
tcg/aarch64/tcg-target.c.inc | 86 ++++------
124
tcg/arm/tcg-target.c.inc | 114 ++++---------
125
tcg/i386/tcg-target.c.inc | 190 +++++----------------
126
tcg/loongarch64/tcg-target.c.inc | 72 +++-----
127
tcg/mips/tcg-target.c.inc | 169 ++++++------------
128
tcg/ppc/tcg-target.c.inc | 164 +++++-------------
129
tcg/riscv/tcg-target.c.inc | 56 +++---
130
tcg/s390x/tcg-target.c.inc | 40 ++---
131
tcg/sparc64/tcg-target.c.inc | 45 ++---
132
tcg/tci/tcg-target.c.inc | 60 ++-----
133
62 files changed, 550 insertions(+), 1162 deletions(-)
134
delete mode 100644 include/tcg/oversized-guest.h
diff view generated by jsdifflib
[PULL 1/3] tcg: Use memset for large vector byte replication
Deleted patch
1
In f47db80cc07, we handled odd-sized tail clearing for
2
the case of hosts that have vector operations, but did
3
not handle the case of hosts that do not have vector ops.
4
1
5
This was ok until e2e7168a214b, which changed the encoding
6
of simd_desc such that the odd sizes are impossible.
7
8
Add memset as a tcg helper, and use that for all out-of-line
9
byte stores to vectors. This includes, but is not limited to,
10
the tail clearing operation in question.
11
12
Cc: qemu-stable@nongnu.org
13
Buglink: https://bugs.launchpad.net/bugs/1907817
14
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
15
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
16
---
17
accel/tcg/tcg-runtime.h | 11 +++++++++++
18
include/exec/helper-proto.h | 4 ++++
19
tcg/tcg-op-gvec.c | 32 ++++++++++++++++++++++++++++++++
20
3 files changed, 47 insertions(+)
21
22
diff --git a/accel/tcg/tcg-runtime.h b/accel/tcg/tcg-runtime.h
23
index XXXXXXX..XXXXXXX 100644
24
--- a/accel/tcg/tcg-runtime.h
25
+++ b/accel/tcg/tcg-runtime.h
26
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_1(lookup_tb_ptr, TCG_CALL_NO_WG_SE, ptr, env)
27
28
DEF_HELPER_FLAGS_1(exit_atomic, TCG_CALL_NO_WG, noreturn, env)
29
30
+#ifndef IN_HELPER_PROTO
31
+/*
32
+ * Pass calls to memset directly to libc, without a thunk in qemu.
33
+ * Do not re-declare memset, especially since we fudge the type here;
34
+ * we assume sizeof(void *) == sizeof(size_t), which is true for
35
+ * all supported hosts.
36
+ */
37
+#define helper_memset memset
38
+DEF_HELPER_FLAGS_3(memset, TCG_CALL_NO_RWG, ptr, ptr, int, ptr)
39
+#endif /* IN_HELPER_PROTO */
40
+
41
#ifdef CONFIG_SOFTMMU
42
43
DEF_HELPER_FLAGS_5(atomic_cmpxchgb, TCG_CALL_NO_WG,
44
diff --git a/include/exec/helper-proto.h b/include/exec/helper-proto.h
45
index XXXXXXX..XXXXXXX 100644
46
--- a/include/exec/helper-proto.h
47
+++ b/include/exec/helper-proto.h
48
@@ -XXX,XX +XXX,XX @@ dh_ctype(ret) HELPER(name) (dh_ctype(t1), dh_ctype(t2), dh_ctype(t3), \
49
dh_ctype(t4), dh_ctype(t5), dh_ctype(t6), \
50
dh_ctype(t7));
51
52
+#define IN_HELPER_PROTO
53
+
54
#include "helper.h"
55
#include "trace/generated-helpers.h"
56
#include "tcg-runtime.h"
57
#include "plugin-helpers.h"
58
59
+#undef IN_HELPER_PROTO
60
+
61
#undef DEF_HELPER_FLAGS_0
62
#undef DEF_HELPER_FLAGS_1
63
#undef DEF_HELPER_FLAGS_2
64
diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c
65
index XXXXXXX..XXXXXXX 100644
66
--- a/tcg/tcg-op-gvec.c
67
+++ b/tcg/tcg-op-gvec.c
68
@@ -XXX,XX +XXX,XX @@ static void do_dup(unsigned vece, uint32_t dofs, uint32_t oprsz,
69
in_c = dup_const(vece, in_c);
70
if (in_c == 0) {
71
oprsz = maxsz;
72
+ vece = MO_8;
73
+ } else if (in_c == dup_const(MO_8, in_c)) {
74
+ vece = MO_8;
75
}
76
}
77
78
@@ -XXX,XX +XXX,XX @@ static void do_dup(unsigned vece, uint32_t dofs, uint32_t oprsz,
79
/* Otherwise implement out of line. */
80
t_ptr = tcg_temp_new_ptr();
81
tcg_gen_addi_ptr(t_ptr, cpu_env, dofs);
82
+
83
+ /*
84
+ * This may be expand_clr for the tail of an operation, e.g.
85
+ * oprsz == 8 && maxsz == 64. The size of the clear is misaligned
86
+ * wrt simd_desc and will assert. Simply pass all replicated byte
87
+ * stores through to memset.
88
+ */
89
+ if (oprsz == maxsz && vece == MO_8) {
90
+ TCGv_ptr t_size = tcg_const_ptr(oprsz);
91
+ TCGv_i32 t_val;
92
+
93
+ if (in_32) {
94
+ t_val = in_32;
95
+ } else if (in_64) {
96
+ t_val = tcg_temp_new_i32();
97
+ tcg_gen_extrl_i64_i32(t_val, in_64);
98
+ } else {
99
+ t_val = tcg_const_i32(in_c);
100
+ }
101
+ gen_helper_memset(t_ptr, t_ptr, t_val, t_size);
102
+
103
+ if (!in_32) {
104
+ tcg_temp_free_i32(t_val);
105
+ }
106
+ tcg_temp_free_ptr(t_size);
107
+ tcg_temp_free_ptr(t_ptr);
108
+ return;
109
+ }
110
+
111
t_desc = tcg_const_i32(simd_desc(oprsz, maxsz, 0));
112
113
if (vece == MO_64) {
114
--
115
2.25.1
116
117
diff view generated by jsdifflib
[PULL 2/3] tcg/riscv: Fix illegal shift instructions
Deleted patch
1
From: Zihao Yu <yuzihao@ict.ac.cn>
2
1
3
Out-of-range shifts have undefined results, but must not trap.
4
Mask off immediate shift counts to solve this problem.
5
6
This bug can be reproduced by running the following guest instructions:
7
8
xor %ecx,%ecx
9
sar %cl,%eax
10
cmovne %edi,%eax
11
12
After optimization, the tcg opcodes of the sar are
13
14
movi_i32 tmp3,$0xffffffffffffffff pref=all
15
sar_i32 tmp3,eax,tmp3 dead: 2 pref=all
16
mov_i32 cc_dst,eax sync: 0 dead: 1 pref=0xffc0300
17
mov_i32 cc_src,tmp3 sync: 0 dead: 0 1 pref=all
18
movi_i32 cc_op,$0x31 sync: 0 dead: 0 pref=all
19
20
The sar_i32 opcode is a shift by -1, which unmasked generates
21
22
0x200808d618: fffa5b9b illegal
23
24
Signed-off-by: Zihao Yu <yuzihao@ict.ac.cn>
25
Message-Id: <20201216081206.9628-1-yuzihao@ict.ac.cn>
26
[rth: Reworded the patch description.]
27
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
28
---
29
tcg/riscv/tcg-target.c.inc | 12 ++++++------
30
1 file changed, 6 insertions(+), 6 deletions(-)
31
32
diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
33
index XXXXXXX..XXXXXXX 100644
34
--- a/tcg/riscv/tcg-target.c.inc
35
+++ b/tcg/riscv/tcg-target.c.inc
36
@@ -XXX,XX +XXX,XX @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
37
38
case INDEX_op_shl_i32:
39
if (c2) {
40
- tcg_out_opc_imm(s, OPC_SLLIW, a0, a1, a2);
41
+ tcg_out_opc_imm(s, OPC_SLLIW, a0, a1, a2 & 0x1f);
42
} else {
43
tcg_out_opc_reg(s, OPC_SLLW, a0, a1, a2);
44
}
45
break;
46
case INDEX_op_shl_i64:
47
if (c2) {
48
- tcg_out_opc_imm(s, OPC_SLLI, a0, a1, a2);
49
+ tcg_out_opc_imm(s, OPC_SLLI, a0, a1, a2 & 0x3f);
50
} else {
51
tcg_out_opc_reg(s, OPC_SLL, a0, a1, a2);
52
}
53
@@ -XXX,XX +XXX,XX @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
54
55
case INDEX_op_shr_i32:
56
if (c2) {
57
- tcg_out_opc_imm(s, OPC_SRLIW, a0, a1, a2);
58
+ tcg_out_opc_imm(s, OPC_SRLIW, a0, a1, a2 & 0x1f);
59
} else {
60
tcg_out_opc_reg(s, OPC_SRLW, a0, a1, a2);
61
}
62
break;
63
case INDEX_op_shr_i64:
64
if (c2) {
65
- tcg_out_opc_imm(s, OPC_SRLI, a0, a1, a2);
66
+ tcg_out_opc_imm(s, OPC_SRLI, a0, a1, a2 & 0x3f);
67
} else {
68
tcg_out_opc_reg(s, OPC_SRL, a0, a1, a2);
69
}
70
@@ -XXX,XX +XXX,XX @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
71
72
case INDEX_op_sar_i32:
73
if (c2) {
74
- tcg_out_opc_imm(s, OPC_SRAIW, a0, a1, a2);
75
+ tcg_out_opc_imm(s, OPC_SRAIW, a0, a1, a2 & 0x1f);
76
} else {
77
tcg_out_opc_reg(s, OPC_SRAW, a0, a1, a2);
78
}
79
break;
80
case INDEX_op_sar_i64:
81
if (c2) {
82
- tcg_out_opc_imm(s, OPC_SRAI, a0, a1, a2);
83
+ tcg_out_opc_imm(s, OPC_SRAI, a0, a1, a2 & 0x3f);
84
} else {
85
tcg_out_opc_reg(s, OPC_SRA, a0, a1, a2);
86
}
87
--
88
2.25.1
89
90
diff view generated by jsdifflib
[PULL 3/3] tcg: Add tcg_gen_bswap_tl alias
[PULL v3 13/28] target/mips: Use VADDR_PRIx for logging pc_next
1
The alias is intended to indicate that the bswap is for the
1
DisasContextBase.pc_next has type vaddr; use the correct log format.
2
entire target_long. This should avoid ifdefs on some targets.
3
2
4
Reviewed-by: Frank Chang <frank.chang@sifive.com>
3
Fixes: 85c19af63e7 ("include/exec: Use vaddr in DisasContextBase for virtual addresses")
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
---
5
---
7
include/tcg/tcg-op.h | 2 ++
6
target/mips/tcg/octeon_translate.c | 4 ++--
8
1 file changed, 2 insertions(+)
7
1 file changed, 2 insertions(+), 2 deletions(-)
9
8
10
diff --git a/include/tcg/tcg-op.h b/include/tcg/tcg-op.h
9
diff --git a/target/mips/tcg/octeon_translate.c b/target/mips/tcg/octeon_translate.c
11
index XXXXXXX..XXXXXXX 100644
10
index XXXXXXX..XXXXXXX 100644
12
--- a/include/tcg/tcg-op.h
11
--- a/target/mips/tcg/octeon_translate.c
13
+++ b/include/tcg/tcg-op.h
12
+++ b/target/mips/tcg/octeon_translate.c
14
@@ -XXX,XX +XXX,XX @@ void tcg_gen_stl_vec(TCGv_vec r, TCGv_ptr base, TCGArg offset, TCGType t);
13
@@ -XXX,XX +XXX,XX @@ static bool trans_BBIT(DisasContext *ctx, arg_BBIT *a)
15
#define tcg_gen_bswap16_tl tcg_gen_bswap16_i64
14
TCGv p;
16
#define tcg_gen_bswap32_tl tcg_gen_bswap32_i64
15
17
#define tcg_gen_bswap64_tl tcg_gen_bswap64_i64
16
if (ctx->hflags & MIPS_HFLAG_BMASK) {
18
+#define tcg_gen_bswap_tl tcg_gen_bswap64_i64
17
- LOG_DISAS("Branch in delay / forbidden slot at PC 0x"
19
#define tcg_gen_concat_tl_i64 tcg_gen_concat32_i64
18
- TARGET_FMT_lx "\n", ctx->base.pc_next);
20
#define tcg_gen_extr_i64_tl tcg_gen_extr32_i64
19
+ LOG_DISAS("Branch in delay / forbidden slot at PC 0x%" VADDR_PRIx "\n",
21
#define tcg_gen_andc_tl tcg_gen_andc_i64
20
+ ctx->base.pc_next);
22
@@ -XXX,XX +XXX,XX @@ void tcg_gen_stl_vec(TCGv_vec r, TCGv_ptr base, TCGArg offset, TCGType t);
21
generate_exception_end(ctx, EXCP_RI);
23
#define tcg_gen_ext32s_tl tcg_gen_mov_i32
22
return true;
24
#define tcg_gen_bswap16_tl tcg_gen_bswap16_i32
23
}
25
#define tcg_gen_bswap32_tl tcg_gen_bswap32_i32
26
+#define tcg_gen_bswap_tl tcg_gen_bswap32_i32
27
#define tcg_gen_concat_tl_i64 tcg_gen_concat_i32_i64
28
#define tcg_gen_extr_i64_tl tcg_gen_extr_i64_i32
29
#define tcg_gen_andc_tl tcg_gen_andc_i32
30
--
24
--
31
2.25.1
25
2.43.0
32
33
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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