From: Klaus Jensen <k.jensen@samsung.com>

This is a resend of "hw/block/nvme: allow cmb and pmr to coexist" with some
more PMR work added (PMR RDS/WDS support).

This includes a resurrection of Andrzej's series[1] from back July.

Andrzej's main patch basically moved the the CMB from BAR 2 into an
offset in BAR 4 (located after the MSI-X table and PBA). Having an
offset on the CMB causes a bunch of calculations related to address
mapping to change.

So, since I couldn't get the patch to apply cleanly I took a stab at
implementing the suggestion I originally came up with: simply move the
MSI-X table and PBA from BAR 4 into BAR 0 (up-aligned to a 4 KiB
boundary, after the main NVMe controller registers). This way we can
keep the CMB at offset zero in its own BAR and free up BAR 4 for use by
PMR. This makes the patch simpler and does not impact any of the
existing address mapping code.

Andrzej, I would prefer an Ack from you, since I pretty much voided your
main patch.

  [1]: https://lore.kernel.org/qemu-devel/20200729220107.37758-1-andrzej.jakowski@linux.intel.com/

CC: Andrzej Jakowski <andrzej.jakowski@linux.intel.com>

Andrzej Jakowski (1):
  hw/block/nvme: indicate CMB support through controller capabilities
    register

Klaus Jensen (6):
  hw/block/nvme: move msix table and pba to BAR 0
  hw/block/nvme: allow cmb and pmr to coexist
  hw/block/nvme: fix controller reset/shutdown logic
  hw/block/nvme: rename CAP_PMR_{SHIFT,MASK} to CAP_PMRS_{SHIFT,MASK}
  hw/block/nvme: remove redundant zeroing of PMR registers
  hw/block/nvme: disable PMR at boot up

Naveen Nagar (1):
  hw/block/nvme: add PMR RDS/WDS support

 hw/block/nvme.h      |   2 +
 include/block/nvme.h |  15 ++-
 hw/block/nvme.c      | 216 ++++++++++++++++++++++++++++++-------------
 3 files changed, 164 insertions(+), 69 deletions(-)

-- 
2.29.2