[PULL 00/23] riscv-to-apply queue
[PULL 00/28] riscv-to-apply queue
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The following changes since commit 75ee62ac606bfc9eb59310b9446df3434bf6e8c2:
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The following changes since commit ad10b4badc1dd5b28305f9b9f1168cf0aa3ae946:
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Merge remote-tracking branch 'remotes/ehabkost-gl/tags/x86-next-pull-request' into staging (2020-12-17 18:53:36 +0000)
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Merge tag 'pull-error-2024-05-27' of https://repo.or.cz/qemu/armbru into staging (2024-05-27 06:40:42 -0700)
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are available in the Git repository at:
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are available in the Git repository at:
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git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20201217-1
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https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20240528
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for you to fetch changes up to d31e970a01e7399b9cd43ec0dc00c857d968987e:
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for you to fetch changes up to 1806da76cb81088ea026ca3441551782b850e393:
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riscv/opentitan: Update the OpenTitan memory layout (2020-12-17 21:56:44 -0800)
11
target/riscv: raise an exception when CSRRS/CSRRC writes a read-only CSR (2024-05-28 12:20:27 +1000)
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----------------------------------------------------------------
13
----------------------------------------------------------------
14
A collection of RISC-V improvements:
14
RISC-V PR for 9.1
15
- Improve the sifive_u DTB generation
15
16
- Add QSPI NOR flash to Microchip PFSoC
16
* APLICs add child earlier than realize
17
- Fix a bug in the Hypervisor HLVX/HLV/HSV instructions
17
* Fix exposure of Zkr
18
- Fix some mstatus mask defines
18
* Raise exceptions on wrs.nto
19
- Ibex PLIC improvements
19
* Implement SBI debug console (DBCN) calls for KVM
20
- OpenTitan memory layout update
20
* Support 64-bit addresses for initrd
21
- Initial steps towards support for 32-bit CPUs on 64-bit builds
21
* Change RISCV_EXCP_SEMIHOST exception number to 63
22
* Tolerate KVM disable ext errors
23
* Set tval in breakpoints
24
* Add support for Zve32x extension
25
* Add support for Zve64x extension
26
* Relax vector register check in RISCV gdbstub
27
* Fix the element agnostic Vector function problem
28
* Fix Zvkb extension config
29
* Implement dynamic establishment of custom decoder
30
* Add th.sxstatus CSR emulation
31
* Fix Zvfhmin checking for vfwcvt.f.f.v and vfncvt.f.f.w instructions
32
* Check single width operator for vector fp widen instructions
33
* Check single width operator for vfncvt.rod.f.f.w
34
* Remove redudant SEW checking for vector fp narrow/widen instructions
35
* Prioritize pmp errors in raise_mmu_exception()
36
* Do not set mtval2 for non guest-page faults
37
* Remove experimental prefix from "B" extension
38
* Fixup CBO extension register calculation
39
* Fix the hart bit setting of AIA
40
* Fix reg_width in ricsv_gen_dynamic_vector_feature()
41
* Decode all of the pmpcfg and pmpaddr CSRs
42
* Raise an exception when CSRRS/CSRRC writes a read-only CSR
22
43
23
----------------------------------------------------------------
44
----------------------------------------------------------------
24
Alex Richardson (1):
45
Alexei Filippov (1):
25
target/riscv: Fix definition of MSTATUS_TW and MSTATUS_TSR
46
target/riscv: do not set mtval2 for non guest-page faults
26
47
27
Alistair Francis (18):
48
Alistair Francis (2):
28
intc/ibex_plic: Clear interrupts that occur during claim process
49
target/riscv: rvzicbo: Fixup CBO extension register calculation
29
hw/riscv: Expand the is 32-bit check to support more CPUs
50
disas/riscv: Decode all of the pmpcfg and pmpaddr CSRs
30
target/riscv: Add a TYPE_RISCV_CPU_BASE CPU
31
riscv: spike: Remove target macro conditionals
32
riscv: virt: Remove target macro conditionals
33
hw/riscv: boot: Remove compile time XLEN checks
34
hw/riscv: virt: Remove compile time XLEN checks
35
hw/riscv: spike: Remove compile time XLEN checks
36
hw/riscv: sifive_u: Remove compile time XLEN checks
37
target/riscv: fpu_helper: Match function defs in HELPER macros
38
target/riscv: Add a riscv_cpu_is_32bit() helper function
39
target/riscv: Specify the XLEN for CPUs
40
target/riscv: cpu: Remove compile time XLEN checks
41
target/riscv: cpu_helper: Remove compile time XLEN checks
42
target/riscv: csr: Remove compile time XLEN checks
43
target/riscv: cpu: Set XLEN independently from target
44
hw/riscv: Use the CPU to determine if 32-bit
45
riscv/opentitan: Update the OpenTitan memory layout
46
51
47
Anup Patel (1):
52
Andrew Jones (2):
48
hw/riscv: sifive_u: Add UART1 DT node in the generated DTB
53
target/riscv/kvm: Fix exposure of Zkr
54
target/riscv: Raise exceptions on wrs.nto
49
55
50
Vitaly Wool (1):
56
Cheng Yang (1):
51
hw/riscv: microchip_pfsoc: add QSPI NOR flash
57
hw/riscv/boot.c: Support 64-bit address for initrd
52
58
53
Xinhao Zhang (1):
59
Christoph Müllner (1):
54
hw/core/register.c: Don't use '#' flag of printf format
60
riscv: thead: Add th.sxstatus CSR emulation
55
61
56
Yifei Jiang (1):
62
Clément Léger (1):
57
target/riscv: Fix the bug of HLVX/HLV/HSV
63
target/riscv: change RISCV_EXCP_SEMIHOST exception number to 63
58
64
59
include/hw/riscv/boot.h | 14 +--
65
Daniel Henrique Barboza (6):
60
include/hw/riscv/microchip_pfsoc.h | 3 +
66
target/riscv/kvm: implement SBI debug console (DBCN) calls
61
include/hw/riscv/opentitan.h | 23 +++--
67
target/riscv/kvm: tolerate KVM disable ext errors
62
include/hw/riscv/spike.h | 6 --
68
target/riscv/debug: set tval=pc in breakpoint exceptions
63
include/hw/riscv/virt.h | 6 --
69
trans_privileged.c.inc: set (m|s)tval on ebreak breakpoint
64
target/riscv/cpu.h | 8 ++
70
target/riscv: prioritize pmp errors in raise_mmu_exception()
65
target/riscv/cpu_bits.h | 8 +-
71
riscv, gdbstub.c: fix reg_width in ricsv_gen_dynamic_vector_feature()
66
target/riscv/helper.h | 24 ++---
67
hw/core/register.c | 16 ++--
68
hw/intc/ibex_plic.c | 13 ++-
69
hw/riscv/boot.c | 70 ++++++++-------
70
hw/riscv/microchip_pfsoc.c | 21 +++++
71
hw/riscv/opentitan.c | 81 ++++++++++++-----
72
hw/riscv/sifive_u.c | 74 ++++++++++------
73
hw/riscv/spike.c | 52 ++++++-----
74
hw/riscv/virt.c | 39 ++++----
75
target/riscv/cpu.c | 84 ++++++++++++------
76
target/riscv/cpu_helper.c | 15 ++--
77
target/riscv/csr.c | 176 +++++++++++++++++++------------------
78
target/riscv/fpu_helper.c | 8 --
79
20 files changed, 434 insertions(+), 307 deletions(-)
80
72
73
Huang Tao (2):
74
target/riscv: Fix the element agnostic function problem
75
target/riscv: Implement dynamic establishment of custom decoder
76
77
Jason Chien (3):
78
target/riscv: Add support for Zve32x extension
79
target/riscv: Add support for Zve64x extension
80
target/riscv: Relax vector register check in RISCV gdbstub
81
82
Max Chou (4):
83
target/riscv: rvv: Fix Zvfhmin checking for vfwcvt.f.f.v and vfncvt.f.f.w instructions
84
target/riscv: rvv: Check single width operator for vector fp widen instructions
85
target/riscv: rvv: Check single width operator for vfncvt.rod.f.f.w
86
target/riscv: rvv: Remove redudant SEW checking for vector fp narrow/widen instructions
87
88
Rob Bradford (1):
89
target/riscv: Remove experimental prefix from "B" extension
90
91
Yangyu Chen (1):
92
target/riscv/cpu.c: fix Zvkb extension config
93
94
Yong-Xuan Wang (1):
95
target/riscv/kvm.c: Fix the hart bit setting of AIA
96
97
Yu-Ming Chang (1):
98
target/riscv: raise an exception when CSRRS/CSRRC writes a read-only CSR
99
100
yang.zhang (1):
101
hw/intc/riscv_aplic: APLICs should add child earlier than realize
102
103
MAINTAINERS | 1 +
104
target/riscv/cpu.h | 11 ++
105
target/riscv/cpu_bits.h | 2 +-
106
target/riscv/cpu_cfg.h | 2 +
107
target/riscv/helper.h | 1 +
108
target/riscv/sbi_ecall_interface.h | 17 +++
109
target/riscv/tcg/tcg-cpu.h | 15 +++
110
disas/riscv.c | 65 +++++++++-
111
hw/intc/riscv_aplic.c | 8 +-
112
hw/riscv/boot.c | 4 +-
113
target/riscv/cpu.c | 10 +-
114
target/riscv/cpu_helper.c | 37 +++---
115
target/riscv/csr.c | 71 +++++++++--
116
target/riscv/debug.c | 3 +
117
target/riscv/gdbstub.c | 8 +-
118
target/riscv/kvm/kvm-cpu.c | 157 ++++++++++++++++++++++++-
119
target/riscv/op_helper.c | 17 ++-
120
target/riscv/tcg/tcg-cpu.c | 50 +++++---
121
target/riscv/th_csr.c | 79 +++++++++++++
122
target/riscv/translate.c | 31 +++--
123
target/riscv/vector_internals.c | 22 ++++
124
target/riscv/insn_trans/trans_privileged.c.inc | 2 +
125
target/riscv/insn_trans/trans_rvv.c.inc | 46 +++++---
126
target/riscv/insn_trans/trans_rvzawrs.c.inc | 29 +++--
127
target/riscv/insn_trans/trans_rvzicbo.c.inc | 16 ++-
128
target/riscv/meson.build | 1 +
129
26 files changed, 596 insertions(+), 109 deletions(-)
130
create mode 100644 target/riscv/th_csr.c
131
diff view generated by jsdifflib
[PULL 06/23] intc/ibex_plic: Clear interrupts that occur during claim process
[PULL 01/28] hw/intc/riscv_aplic: APLICs should add child earlier than realize
1
Previously if an interrupt occured during the claim process (after the
1
From: "yang.zhang" <yang.zhang@hexintek.com>
2
interrupt is claimed but before it's completed) it would never be
3
cleared.
4
This patch ensures that we also clear the hidden_pending bits as well.
5
2
3
Since only root APLICs can have hw IRQ lines, aplic->parent should
4
be initialized first.
5
6
Fixes: e8f79343cf ("hw/intc: Add RISC-V AIA APLIC device emulation")
7
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
8
Signed-off-by: yang.zhang <yang.zhang@hexintek.com>
9
Cc: qemu-stable <qemu-stable@nongnu.org>
10
Message-ID: <20240409014445.278-1-gaoshanliukou@163.com>
6
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
11
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
7
Tested-by: Jackie Ke <jackieke724@hotmail.com>
8
Message-id: 4e9786084a86f220689123cc8a7837af8fa071cf.1607100423.git.alistair.francis@wdc.com
9
---
12
---
10
hw/intc/ibex_plic.c | 13 ++++++++++---
13
hw/intc/riscv_aplic.c | 8 ++++----
11
1 file changed, 10 insertions(+), 3 deletions(-)
14
1 file changed, 4 insertions(+), 4 deletions(-)
12
15
13
diff --git a/hw/intc/ibex_plic.c b/hw/intc/ibex_plic.c
16
diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c
14
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
15
--- a/hw/intc/ibex_plic.c
18
--- a/hw/intc/riscv_aplic.c
16
+++ b/hw/intc/ibex_plic.c
19
+++ b/hw/intc/riscv_aplic.c
17
@@ -XXX,XX +XXX,XX @@ static void ibex_plic_irqs_set_pending(IbexPlicState *s, int irq, bool level)
20
@@ -XXX,XX +XXX,XX @@ DeviceState *riscv_aplic_create(hwaddr addr, hwaddr size,
18
{
21
qdev_prop_set_bit(dev, "msimode", msimode);
19
int pending_num = irq / 32;
22
qdev_prop_set_bit(dev, "mmode", mmode);
20
23
21
+ if (!level) {
24
+ if (parent) {
22
+ /*
25
+ riscv_aplic_add_child(parent, dev);
23
+ * If the level is low make sure we clear the hidden_pending.
24
+ */
25
+ s->hidden_pending[pending_num] &= ~(1 << (irq % 32));
26
+ }
26
+ }
27
+
27
+
28
if (s->claimed[pending_num] & 1 << (irq % 32)) {
28
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
29
/*
29
30
* The interrupt has been claimed, but not completed.
30
if (!is_kvm_aia(msimode)) {
31
* The pending bit can't be set.
31
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
32
+ * Save the pending level for after the interrupt is completed.
33
*/
34
s->hidden_pending[pending_num] |= level << (irq % 32);
35
- return;
36
+ } else {
37
+ s->pending[pending_num] |= level << (irq % 32);
38
}
32
}
33
34
- if (parent) {
35
- riscv_aplic_add_child(parent, dev);
36
- }
39
-
37
-
40
- s->pending[pending_num] |= level << (irq % 32);
38
if (!msimode) {
41
}
39
for (i = 0; i < num_harts; i++) {
42
40
CPUState *cpu = cpu_by_arch_id(hartid_base + i);
43
static bool ibex_plic_irqs_pending(IbexPlicState *s, uint32_t context)
44
--
41
--
45
2.29.2
42
2.45.1
46
47
diff view generated by jsdifflib
[PULL 08/23] target/riscv: Add a TYPE_RISCV_CPU_BASE CPU
[PULL 02/28] target/riscv/kvm: Fix exposure of Zkr
1
From: Andrew Jones <ajones@ventanamicro.com>
2
3
The Zkr extension may only be exposed to KVM guests if the VMM
4
implements the SEED CSR. Use the same implementation as TCG.
5
6
Without this patch, running with a KVM which does not forward the
7
SEED CSR access to QEMU will result in an ILL exception being
8
injected into the guest (this results in Linux guests crashing on
9
boot). And, when running with a KVM which does forward the access,
10
QEMU will crash, since QEMU doesn't know what to do with the exit.
11
12
Fixes: 3108e2f1c69d ("target/riscv/kvm: update KVM exts to Linux 6.8")
13
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
14
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
15
Cc: qemu-stable <qemu-stable@nongnu.org>
16
Message-ID: <20240422134605.534207-2-ajones@ventanamicro.com>
1
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
17
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2
Reviewed-by: Bin Meng <bin.meng@windriver.com>
3
Tested-by: Bin Meng <bin.meng@windriver.com>
4
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
5
Acked-by: Palmer Dabbelt <palmerdabbelt@google.com>
6
Message-id: 86e5ccd9eae2f5d8c2257679c6ccf6078a5d51af.1608142916.git.alistair.francis@wdc.com
7
---
18
---
8
target/riscv/cpu.h | 6 ++++++
19
target/riscv/cpu.h | 3 +++
9
1 file changed, 6 insertions(+)
20
target/riscv/csr.c | 18 ++++++++++++++----
21
target/riscv/kvm/kvm-cpu.c | 25 +++++++++++++++++++++++++
22
3 files changed, 42 insertions(+), 4 deletions(-)
10
23
11
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
24
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
12
index XXXXXXX..XXXXXXX 100644
25
index XXXXXXX..XXXXXXX 100644
13
--- a/target/riscv/cpu.h
26
--- a/target/riscv/cpu.h
14
+++ b/target/riscv/cpu.h
27
+++ b/target/riscv/cpu.h
15
@@ -XXX,XX +XXX,XX @@
28
@@ -XXX,XX +XXX,XX @@ void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops);
16
#define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34")
29
17
#define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54")
30
void riscv_cpu_register_gdb_regs_for_features(CPUState *cs);
18
31
19
+#if defined(TARGET_RISCV32)
32
+target_ulong riscv_new_csr_seed(target_ulong new_value,
20
+# define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE32
33
+ target_ulong write_mask);
21
+#elif defined(TARGET_RISCV64)
22
+# define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE64
23
+#endif
24
+
34
+
25
#define RV32 ((target_ulong)1 << (TARGET_LONG_BITS - 2))
35
uint8_t satp_mode_max_from_map(uint32_t map);
26
#define RV64 ((target_ulong)2 << (TARGET_LONG_BITS - 2))
36
const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit);
27
37
38
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
39
index XXXXXXX..XXXXXXX 100644
40
--- a/target/riscv/csr.c
41
+++ b/target/riscv/csr.c
42
@@ -XXX,XX +XXX,XX @@ static RISCVException write_upmbase(CPURISCVState *env, int csrno,
43
#endif
44
45
/* Crypto Extension */
46
-static RISCVException rmw_seed(CPURISCVState *env, int csrno,
47
- target_ulong *ret_value,
48
- target_ulong new_value,
49
- target_ulong write_mask)
50
+target_ulong riscv_new_csr_seed(target_ulong new_value,
51
+ target_ulong write_mask)
52
{
53
uint16_t random_v;
54
Error *random_e = NULL;
55
@@ -XXX,XX +XXX,XX @@ static RISCVException rmw_seed(CPURISCVState *env, int csrno,
56
rval = random_v | SEED_OPST_ES16;
57
}
58
59
+ return rval;
60
+}
61
+
62
+static RISCVException rmw_seed(CPURISCVState *env, int csrno,
63
+ target_ulong *ret_value,
64
+ target_ulong new_value,
65
+ target_ulong write_mask)
66
+{
67
+ target_ulong rval;
68
+
69
+ rval = riscv_new_csr_seed(new_value, write_mask);
70
+
71
if (ret_value) {
72
*ret_value = rval;
73
}
74
diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
75
index XXXXXXX..XXXXXXX 100644
76
--- a/target/riscv/kvm/kvm-cpu.c
77
+++ b/target/riscv/kvm/kvm-cpu.c
78
@@ -XXX,XX +XXX,XX @@ static int kvm_riscv_handle_sbi(CPUState *cs, struct kvm_run *run)
79
return ret;
80
}
81
82
+static int kvm_riscv_handle_csr(CPUState *cs, struct kvm_run *run)
83
+{
84
+ target_ulong csr_num = run->riscv_csr.csr_num;
85
+ target_ulong new_value = run->riscv_csr.new_value;
86
+ target_ulong write_mask = run->riscv_csr.write_mask;
87
+ int ret = 0;
88
+
89
+ switch (csr_num) {
90
+ case CSR_SEED:
91
+ run->riscv_csr.ret_value = riscv_new_csr_seed(new_value, write_mask);
92
+ break;
93
+ default:
94
+ qemu_log_mask(LOG_UNIMP,
95
+ "%s: un-handled CSR EXIT for CSR %lx\n",
96
+ __func__, csr_num);
97
+ ret = -1;
98
+ break;
99
+ }
100
+
101
+ return ret;
102
+}
103
+
104
int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
105
{
106
int ret = 0;
107
@@ -XXX,XX +XXX,XX @@ int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
108
case KVM_EXIT_RISCV_SBI:
109
ret = kvm_riscv_handle_sbi(cs, run);
110
break;
111
+ case KVM_EXIT_RISCV_CSR:
112
+ ret = kvm_riscv_handle_csr(cs, run);
113
+ break;
114
default:
115
qemu_log_mask(LOG_UNIMP, "%s: un-handled exit reason %d\n",
116
__func__, run->exit_reason);
28
--
117
--
29
2.29.2
118
2.45.1
30
31
diff view generated by jsdifflib
[PULL 15/23] target/riscv: fpu_helper: Match function defs in HELPER macros
[PULL 03/28] target/riscv: Raise exceptions on wrs.nto
1
Update the function definitions generated in helper.h to match the
1
From: Andrew Jones <ajones@ventanamicro.com>
2
actual function implementations.
3
2
4
Also remove all compile time XLEN checks when building.
3
Implementing wrs.nto to always just return is consistent with the
4
specification, as the instruction is permitted to terminate the
5
stall for any reason, but it's not useful for virtualization, where
6
we'd like the guest to trap to the hypervisor in order to allow
7
scheduling of the lock holding VCPU. Change to always immediately
8
raise exceptions when the appropriate conditions are present,
9
otherwise continue to just return. Note, immediately raising
10
exceptions is also consistent with the specification since the
11
time limit that should expire prior to the exception is
12
implementation-specific.
5
13
14
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
15
Reviewed-by: Christoph Müllner <christoph.muellner@vrull.eu>
16
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
17
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
18
Message-ID: <20240424142808.62936-2-ajones@ventanamicro.com>
6
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
19
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
7
Message-id: 614c369cb0000d070873a647b8aac7e023cba145.1608142916.git.alistair.francis@wdc.com
8
---
20
---
9
target/riscv/helper.h | 24 ++++++++----------------
21
target/riscv/helper.h | 1 +
10
target/riscv/fpu_helper.c | 8 --------
22
target/riscv/op_helper.c | 11 ++++++++
11
2 files changed, 8 insertions(+), 24 deletions(-)
23
target/riscv/insn_trans/trans_rvzawrs.c.inc | 29 ++++++++++++++-------
24
3 files changed, 32 insertions(+), 9 deletions(-)
12
25
13
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
26
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
14
index XXXXXXX..XXXXXXX 100644
27
index XXXXXXX..XXXXXXX 100644
15
--- a/target/riscv/helper.h
28
--- a/target/riscv/helper.h
16
+++ b/target/riscv/helper.h
29
+++ b/target/riscv/helper.h
17
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(flt_s, TCG_CALL_NO_RWG, tl, env, i64, i64)
30
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_6(csrrw_i128, tl, env, int, tl, tl, tl, tl)
18
DEF_HELPER_FLAGS_3(feq_s, TCG_CALL_NO_RWG, tl, env, i64, i64)
31
DEF_HELPER_1(sret, tl, env)
19
DEF_HELPER_FLAGS_2(fcvt_w_s, TCG_CALL_NO_RWG, tl, env, i64)
32
DEF_HELPER_1(mret, tl, env)
20
DEF_HELPER_FLAGS_2(fcvt_wu_s, TCG_CALL_NO_RWG, tl, env, i64)
33
DEF_HELPER_1(wfi, void, env)
21
-#if defined(TARGET_RISCV64)
34
+DEF_HELPER_1(wrs_nto, void, env)
22
-DEF_HELPER_FLAGS_2(fcvt_l_s, TCG_CALL_NO_RWG, tl, env, i64)
35
DEF_HELPER_1(tlb_flush, void, env)
23
-DEF_HELPER_FLAGS_2(fcvt_lu_s, TCG_CALL_NO_RWG, tl, env, i64)
36
DEF_HELPER_1(tlb_flush_all, void, env)
24
-#endif
37
/* Native Debug */
25
+DEF_HELPER_FLAGS_2(fcvt_l_s, TCG_CALL_NO_RWG, i64, env, i64)
38
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
26
+DEF_HELPER_FLAGS_2(fcvt_lu_s, TCG_CALL_NO_RWG, i64, env, i64)
27
DEF_HELPER_FLAGS_2(fcvt_s_w, TCG_CALL_NO_RWG, i64, env, tl)
28
DEF_HELPER_FLAGS_2(fcvt_s_wu, TCG_CALL_NO_RWG, i64, env, tl)
29
-#if defined(TARGET_RISCV64)
30
-DEF_HELPER_FLAGS_2(fcvt_s_l, TCG_CALL_NO_RWG, i64, env, tl)
31
-DEF_HELPER_FLAGS_2(fcvt_s_lu, TCG_CALL_NO_RWG, i64, env, tl)
32
-#endif
33
+DEF_HELPER_FLAGS_2(fcvt_s_l, TCG_CALL_NO_RWG, i64, env, i64)
34
+DEF_HELPER_FLAGS_2(fcvt_s_lu, TCG_CALL_NO_RWG, i64, env, i64)
35
DEF_HELPER_FLAGS_1(fclass_s, TCG_CALL_NO_RWG_SE, tl, i64)
36
37
/* Floating Point - Double Precision */
38
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(flt_d, TCG_CALL_NO_RWG, tl, env, i64, i64)
39
DEF_HELPER_FLAGS_3(feq_d, TCG_CALL_NO_RWG, tl, env, i64, i64)
40
DEF_HELPER_FLAGS_2(fcvt_w_d, TCG_CALL_NO_RWG, tl, env, i64)
41
DEF_HELPER_FLAGS_2(fcvt_wu_d, TCG_CALL_NO_RWG, tl, env, i64)
42
-#if defined(TARGET_RISCV64)
43
-DEF_HELPER_FLAGS_2(fcvt_l_d, TCG_CALL_NO_RWG, tl, env, i64)
44
-DEF_HELPER_FLAGS_2(fcvt_lu_d, TCG_CALL_NO_RWG, tl, env, i64)
45
-#endif
46
+DEF_HELPER_FLAGS_2(fcvt_l_d, TCG_CALL_NO_RWG, i64, env, i64)
47
+DEF_HELPER_FLAGS_2(fcvt_lu_d, TCG_CALL_NO_RWG, i64, env, i64)
48
DEF_HELPER_FLAGS_2(fcvt_d_w, TCG_CALL_NO_RWG, i64, env, tl)
49
DEF_HELPER_FLAGS_2(fcvt_d_wu, TCG_CALL_NO_RWG, i64, env, tl)
50
-#if defined(TARGET_RISCV64)
51
-DEF_HELPER_FLAGS_2(fcvt_d_l, TCG_CALL_NO_RWG, i64, env, tl)
52
-DEF_HELPER_FLAGS_2(fcvt_d_lu, TCG_CALL_NO_RWG, i64, env, tl)
53
-#endif
54
+DEF_HELPER_FLAGS_2(fcvt_d_l, TCG_CALL_NO_RWG, i64, env, i64)
55
+DEF_HELPER_FLAGS_2(fcvt_d_lu, TCG_CALL_NO_RWG, i64, env, i64)
56
DEF_HELPER_FLAGS_1(fclass_d, TCG_CALL_NO_RWG_SE, tl, i64)
57
58
/* Special functions */
59
diff --git a/target/riscv/fpu_helper.c b/target/riscv/fpu_helper.c
60
index XXXXXXX..XXXXXXX 100644
39
index XXXXXXX..XXXXXXX 100644
61
--- a/target/riscv/fpu_helper.c
40
--- a/target/riscv/op_helper.c
62
+++ b/target/riscv/fpu_helper.c
41
+++ b/target/riscv/op_helper.c
63
@@ -XXX,XX +XXX,XX @@ target_ulong helper_fcvt_wu_s(CPURISCVState *env, uint64_t rs1)
42
@@ -XXX,XX +XXX,XX @@ void helper_wfi(CPURISCVState *env)
64
return (int32_t)float32_to_uint32(frs1, &env->fp_status);
43
}
65
}
44
}
66
45
67
-#if defined(TARGET_RISCV64)
46
+void helper_wrs_nto(CPURISCVState *env)
68
uint64_t helper_fcvt_l_s(CPURISCVState *env, uint64_t rs1)
47
+{
48
+ if (env->virt_enabled && (env->priv == PRV_S || env->priv == PRV_U) &&
49
+ get_field(env->hstatus, HSTATUS_VTW) &&
50
+ !get_field(env->mstatus, MSTATUS_TW)) {
51
+ riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETPC());
52
+ } else if (env->priv != PRV_M && get_field(env->mstatus, MSTATUS_TW)) {
53
+ riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
54
+ }
55
+}
56
+
57
void helper_tlb_flush(CPURISCVState *env)
69
{
58
{
70
float32 frs1 = check_nanbox_s(rs1);
59
CPUState *cs = env_cpu(env);
71
@@ -XXX,XX +XXX,XX @@ uint64_t helper_fcvt_lu_s(CPURISCVState *env, uint64_t rs1)
60
diff --git a/target/riscv/insn_trans/trans_rvzawrs.c.inc b/target/riscv/insn_trans/trans_rvzawrs.c.inc
72
float32 frs1 = check_nanbox_s(rs1);
61
index XXXXXXX..XXXXXXX 100644
73
return float32_to_uint64(frs1, &env->fp_status);
62
--- a/target/riscv/insn_trans/trans_rvzawrs.c.inc
63
+++ b/target/riscv/insn_trans/trans_rvzawrs.c.inc
64
@@ -XXX,XX +XXX,XX @@
65
* this program. If not, see <http://www.gnu.org/licenses/>.
66
*/
67
68
-static bool trans_wrs(DisasContext *ctx)
69
+static bool trans_wrs_sto(DisasContext *ctx, arg_wrs_sto *a)
70
{
71
if (!ctx->cfg_ptr->ext_zawrs) {
72
return false;
73
@@ -XXX,XX +XXX,XX @@ static bool trans_wrs(DisasContext *ctx)
74
return true;
74
}
75
}
75
-#endif
76
76
77
-#define GEN_TRANS_WRS(insn) \
77
uint64_t helper_fcvt_s_w(CPURISCVState *env, target_ulong rs1)
78
-static bool trans_ ## insn(DisasContext *ctx, arg_ ## insn *a) \
78
{
79
-{ \
79
@@ -XXX,XX +XXX,XX @@ uint64_t helper_fcvt_s_wu(CPURISCVState *env, target_ulong rs1)
80
- (void)a; \
80
return nanbox_s(uint32_to_float32((uint32_t)rs1, &env->fp_status));
81
- return trans_wrs(ctx); \
81
}
82
-}
82
83
+static bool trans_wrs_nto(DisasContext *ctx, arg_wrs_nto *a)
83
-#if defined(TARGET_RISCV64)
84
+{
84
uint64_t helper_fcvt_s_l(CPURISCVState *env, uint64_t rs1)
85
+ if (!ctx->cfg_ptr->ext_zawrs) {
85
{
86
+ return false;
86
return nanbox_s(int64_to_float32(rs1, &env->fp_status));
87
+ }
87
@@ -XXX,XX +XXX,XX @@ uint64_t helper_fcvt_s_lu(CPURISCVState *env, uint64_t rs1)
88
88
{
89
-GEN_TRANS_WRS(wrs_nto)
89
return nanbox_s(uint64_to_float32(rs1, &env->fp_status));
90
-GEN_TRANS_WRS(wrs_sto)
90
}
91
+ /*
91
-#endif
92
+ * Depending on the mode of execution, mstatus.TW and hstatus.VTW, wrs.nto
92
93
+ * should raise an exception when the implementation-specific bounded time
93
target_ulong helper_fclass_s(uint64_t rs1)
94
+ * limit has expired. Our time limit is zero, so we either return
94
{
95
+ * immediately, as does our implementation of wrs.sto, or raise an
95
@@ -XXX,XX +XXX,XX @@ target_ulong helper_fcvt_wu_d(CPURISCVState *env, uint64_t frs1)
96
+ * exception, as handled by the wrs.nto helper.
96
return (int32_t)float64_to_uint32(frs1, &env->fp_status);
97
+ */
97
}
98
+#ifndef CONFIG_USER_ONLY
98
99
+ gen_helper_wrs_nto(tcg_env);
99
-#if defined(TARGET_RISCV64)
100
+#endif
100
uint64_t helper_fcvt_l_d(CPURISCVState *env, uint64_t frs1)
101
+
101
{
102
+ /* We only get here when helper_wrs_nto() doesn't raise an exception. */
102
return float64_to_int64(frs1, &env->fp_status);
103
+ return trans_wrs_sto(ctx, NULL);
103
@@ -XXX,XX +XXX,XX @@ uint64_t helper_fcvt_lu_d(CPURISCVState *env, uint64_t frs1)
104
+}
104
{
105
return float64_to_uint64(frs1, &env->fp_status);
106
}
107
-#endif
108
109
uint64_t helper_fcvt_d_w(CPURISCVState *env, target_ulong rs1)
110
{
111
@@ -XXX,XX +XXX,XX @@ uint64_t helper_fcvt_d_wu(CPURISCVState *env, target_ulong rs1)
112
return uint32_to_float64((uint32_t)rs1, &env->fp_status);
113
}
114
115
-#if defined(TARGET_RISCV64)
116
uint64_t helper_fcvt_d_l(CPURISCVState *env, uint64_t rs1)
117
{
118
return int64_to_float64(rs1, &env->fp_status);
119
@@ -XXX,XX +XXX,XX @@ uint64_t helper_fcvt_d_lu(CPURISCVState *env, uint64_t rs1)
120
{
121
return uint64_to_float64(rs1, &env->fp_status);
122
}
123
-#endif
124
125
target_ulong helper_fclass_d(uint64_t frs1)
126
{
127
--
105
--
128
2.29.2
106
2.45.1
129
107
130
108
diff view generated by jsdifflib
[PULL 09/23] riscv: spike: Remove target macro conditionals
[PULL 04/28] target/riscv/kvm: implement SBI debug console (DBCN) calls
1
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
2
3
SBI defines a Debug Console extension "DBCN" that will, in time, replace
4
the legacy console putchar and getchar SBI extensions.
5
6
The appeal of the DBCN extension is that it allows multiple bytes to be
7
read/written in the SBI console in a single SBI call.
8
9
As far as KVM goes, the DBCN calls are forwarded by an in-kernel KVM
10
module to userspace. But this will only happens if the KVM module
11
actually supports this SBI extension and we activate it.
12
13
We'll check for DBCN support during init time, checking if get-reg-list
14
is advertising KVM_RISCV_SBI_EXT_DBCN. In that case, we'll enable it via
15
kvm_set_one_reg() during kvm_arch_init_vcpu().
16
17
Finally, change kvm_riscv_handle_sbi() to handle the incoming calls for
18
SBI_EXT_DBCN, reading and writing as required.
19
20
A simple KVM guest with 'earlycon=sbi', running in an emulated RISC-V
21
host, takes around 20 seconds to boot without using DBCN. With this
22
patch we're taking around 14 seconds to boot due to the speed-up in the
23
terminal output. There's no change in boot time if the guest isn't
24
using earlycon.
25
26
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
27
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
28
Message-ID: <20240425155012.581366-1-dbarboza@ventanamicro.com>
1
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
29
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2
Reviewed-by: Bin Meng <bin.meng@windriver.com>
3
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
4
Acked-by: Palmer Dabbelt <palmerdabbelt@google.com>
5
Message-id: 04ac7fba2348c92f296a5e6a9959ac72b77ae4c6.1608142916.git.alistair.francis@wdc.com
6
---
30
---
7
include/hw/riscv/spike.h | 6 ------
31
target/riscv/sbi_ecall_interface.h | 17 +++++
8
hw/riscv/spike.c | 2 +-
32
target/riscv/kvm/kvm-cpu.c | 111 +++++++++++++++++++++++++++++
9
2 files changed, 1 insertion(+), 7 deletions(-)
33
2 files changed, 128 insertions(+)
10
34
11
diff --git a/include/hw/riscv/spike.h b/include/hw/riscv/spike.h
35
diff --git a/target/riscv/sbi_ecall_interface.h b/target/riscv/sbi_ecall_interface.h
12
index XXXXXXX..XXXXXXX 100644
36
index XXXXXXX..XXXXXXX 100644
13
--- a/include/hw/riscv/spike.h
37
--- a/target/riscv/sbi_ecall_interface.h
14
+++ b/include/hw/riscv/spike.h
38
+++ b/target/riscv/sbi_ecall_interface.h
15
@@ -XXX,XX +XXX,XX @@ enum {
39
@@ -XXX,XX +XXX,XX @@
16
SPIKE_DRAM
40
41
/* clang-format off */
42
43
+#define SBI_SUCCESS 0
44
+#define SBI_ERR_FAILED -1
45
+#define SBI_ERR_NOT_SUPPORTED -2
46
+#define SBI_ERR_INVALID_PARAM -3
47
+#define SBI_ERR_DENIED -4
48
+#define SBI_ERR_INVALID_ADDRESS -5
49
+#define SBI_ERR_ALREADY_AVAILABLE -6
50
+#define SBI_ERR_ALREADY_STARTED -7
51
+#define SBI_ERR_ALREADY_STOPPED -8
52
+#define SBI_ERR_NO_SHMEM -9
53
+
54
/* SBI Extension IDs */
55
#define SBI_EXT_0_1_SET_TIMER 0x0
56
#define SBI_EXT_0_1_CONSOLE_PUTCHAR 0x1
57
@@ -XXX,XX +XXX,XX @@
58
#define SBI_EXT_IPI 0x735049
59
#define SBI_EXT_RFENCE 0x52464E43
60
#define SBI_EXT_HSM 0x48534D
61
+#define SBI_EXT_DBCN 0x4442434E
62
63
/* SBI function IDs for BASE extension */
64
#define SBI_EXT_BASE_GET_SPEC_VERSION 0x0
65
@@ -XXX,XX +XXX,XX @@
66
#define SBI_EXT_HSM_HART_STOP 0x1
67
#define SBI_EXT_HSM_HART_GET_STATUS 0x2
68
69
+/* SBI function IDs for DBCN extension */
70
+#define SBI_EXT_DBCN_CONSOLE_WRITE 0x0
71
+#define SBI_EXT_DBCN_CONSOLE_READ 0x1
72
+#define SBI_EXT_DBCN_CONSOLE_WRITE_BYTE 0x2
73
+
74
#define SBI_HSM_HART_STATUS_STARTED 0x0
75
#define SBI_HSM_HART_STATUS_STOPPED 0x1
76
#define SBI_HSM_HART_STATUS_START_PENDING 0x2
77
diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
78
index XXXXXXX..XXXXXXX 100644
79
--- a/target/riscv/kvm/kvm-cpu.c
80
+++ b/target/riscv/kvm/kvm-cpu.c
81
@@ -XXX,XX +XXX,XX @@ static KVMCPUConfig kvm_v_vlenb = {
82
KVM_REG_RISCV_VECTOR_CSR_REG(vlenb)
17
};
83
};
18
84
19
-#if defined(TARGET_RISCV32)
85
+static KVMCPUConfig kvm_sbi_dbcn = {
20
-#define SPIKE_V1_10_0_CPU TYPE_RISCV_CPU_BASE32
86
+ .name = "sbi_dbcn",
21
-#elif defined(TARGET_RISCV64)
87
+ .kvm_reg_id = KVM_REG_RISCV | KVM_REG_SIZE_U64 |
22
-#define SPIKE_V1_10_0_CPU TYPE_RISCV_CPU_BASE64
88
+ KVM_REG_RISCV_SBI_EXT | KVM_RISCV_SBI_EXT_DBCN
23
-#endif
89
+};
24
-
90
+
25
#endif
91
static void kvm_riscv_update_cpu_cfg_isa_ext(RISCVCPU *cpu, CPUState *cs)
26
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
92
{
27
index XXXXXXX..XXXXXXX 100644
93
CPURISCVState *env = &cpu->env;
28
--- a/hw/riscv/spike.c
94
@@ -XXX,XX +XXX,XX @@ static int uint64_cmp(const void *a, const void *b)
29
+++ b/hw/riscv/spike.c
95
return 0;
30
@@ -XXX,XX +XXX,XX @@ static void spike_machine_class_init(ObjectClass *oc, void *data)
96
}
31
mc->init = spike_board_init;
97
32
mc->max_cpus = SPIKE_CPUS_MAX;
98
+static void kvm_riscv_check_sbi_dbcn_support(RISCVCPU *cpu,
33
mc->is_default = true;
99
+ KVMScratchCPU *kvmcpu,
34
- mc->default_cpu_type = SPIKE_V1_10_0_CPU;
100
+ struct kvm_reg_list *reglist)
35
+ mc->default_cpu_type = TYPE_RISCV_CPU_BASE;
101
+{
36
mc->possible_cpu_arch_ids = riscv_numa_possible_cpu_arch_ids;
102
+ struct kvm_reg_list *reg_search;
37
mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props;
103
+
38
mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id;
104
+ reg_search = bsearch(&kvm_sbi_dbcn.kvm_reg_id, reglist->reg, reglist->n,
105
+ sizeof(uint64_t), uint64_cmp);
106
+
107
+ if (reg_search) {
108
+ kvm_sbi_dbcn.supported = true;
109
+ }
110
+}
111
+
112
static void kvm_riscv_read_vlenb(RISCVCPU *cpu, KVMScratchCPU *kvmcpu,
113
struct kvm_reg_list *reglist)
114
{
115
@@ -XXX,XX +XXX,XX @@ static void kvm_riscv_init_multiext_cfg(RISCVCPU *cpu, KVMScratchCPU *kvmcpu)
116
if (riscv_has_ext(&cpu->env, RVV)) {
117
kvm_riscv_read_vlenb(cpu, kvmcpu, reglist);
118
}
119
+
120
+ kvm_riscv_check_sbi_dbcn_support(cpu, kvmcpu, reglist);
121
}
122
123
static void riscv_init_kvm_registers(Object *cpu_obj)
124
@@ -XXX,XX +XXX,XX @@ static int kvm_vcpu_set_machine_ids(RISCVCPU *cpu, CPUState *cs)
125
return ret;
126
}
127
128
+static int kvm_vcpu_enable_sbi_dbcn(RISCVCPU *cpu, CPUState *cs)
129
+{
130
+ target_ulong reg = 1;
131
+
132
+ if (!kvm_sbi_dbcn.supported) {
133
+ return 0;
134
+ }
135
+
136
+ return kvm_set_one_reg(cs, kvm_sbi_dbcn.kvm_reg_id, &reg);
137
+}
138
+
139
int kvm_arch_init_vcpu(CPUState *cs)
140
{
141
int ret = 0;
142
@@ -XXX,XX +XXX,XX @@ int kvm_arch_init_vcpu(CPUState *cs)
143
kvm_riscv_update_cpu_misa_ext(cpu, cs);
144
kvm_riscv_update_cpu_cfg_isa_ext(cpu, cs);
145
146
+ ret = kvm_vcpu_enable_sbi_dbcn(cpu, cs);
147
+
148
return ret;
149
}
150
151
@@ -XXX,XX +XXX,XX @@ bool kvm_arch_stop_on_emulation_error(CPUState *cs)
152
return true;
153
}
154
155
+static void kvm_riscv_handle_sbi_dbcn(CPUState *cs, struct kvm_run *run)
156
+{
157
+ g_autofree uint8_t *buf = NULL;
158
+ RISCVCPU *cpu = RISCV_CPU(cs);
159
+ target_ulong num_bytes;
160
+ uint64_t addr;
161
+ unsigned char ch;
162
+ int ret;
163
+
164
+ switch (run->riscv_sbi.function_id) {
165
+ case SBI_EXT_DBCN_CONSOLE_READ:
166
+ case SBI_EXT_DBCN_CONSOLE_WRITE:
167
+ num_bytes = run->riscv_sbi.args[0];
168
+
169
+ if (num_bytes == 0) {
170
+ run->riscv_sbi.ret[0] = SBI_SUCCESS;
171
+ run->riscv_sbi.ret[1] = 0;
172
+ break;
173
+ }
174
+
175
+ addr = run->riscv_sbi.args[1];
176
+
177
+ /*
178
+ * Handle the case where a 32 bit CPU is running in a
179
+ * 64 bit addressing env.
180
+ */
181
+ if (riscv_cpu_mxl(&cpu->env) == MXL_RV32) {
182
+ addr |= (uint64_t)run->riscv_sbi.args[2] << 32;
183
+ }
184
+
185
+ buf = g_malloc0(num_bytes);
186
+
187
+ if (run->riscv_sbi.function_id == SBI_EXT_DBCN_CONSOLE_READ) {
188
+ ret = qemu_chr_fe_read_all(serial_hd(0)->be, buf, num_bytes);
189
+ if (ret < 0) {
190
+ error_report("SBI_EXT_DBCN_CONSOLE_READ: error when "
191
+ "reading chardev");
192
+ exit(1);
193
+ }
194
+
195
+ cpu_physical_memory_write(addr, buf, ret);
196
+ } else {
197
+ cpu_physical_memory_read(addr, buf, num_bytes);
198
+
199
+ ret = qemu_chr_fe_write_all(serial_hd(0)->be, buf, num_bytes);
200
+ if (ret < 0) {
201
+ error_report("SBI_EXT_DBCN_CONSOLE_WRITE: error when "
202
+ "writing chardev");
203
+ exit(1);
204
+ }
205
+ }
206
+
207
+ run->riscv_sbi.ret[0] = SBI_SUCCESS;
208
+ run->riscv_sbi.ret[1] = ret;
209
+ break;
210
+ case SBI_EXT_DBCN_CONSOLE_WRITE_BYTE:
211
+ ch = run->riscv_sbi.args[0];
212
+ ret = qemu_chr_fe_write(serial_hd(0)->be, &ch, sizeof(ch));
213
+
214
+ if (ret < 0) {
215
+ error_report("SBI_EXT_DBCN_CONSOLE_WRITE_BYTE: error when "
216
+ "writing chardev");
217
+ exit(1);
218
+ }
219
+
220
+ run->riscv_sbi.ret[0] = SBI_SUCCESS;
221
+ run->riscv_sbi.ret[1] = 0;
222
+ break;
223
+ default:
224
+ run->riscv_sbi.ret[0] = SBI_ERR_NOT_SUPPORTED;
225
+ }
226
+}
227
+
228
static int kvm_riscv_handle_sbi(CPUState *cs, struct kvm_run *run)
229
{
230
int ret = 0;
231
@@ -XXX,XX +XXX,XX @@ static int kvm_riscv_handle_sbi(CPUState *cs, struct kvm_run *run)
232
}
233
ret = 0;
234
break;
235
+ case SBI_EXT_DBCN:
236
+ kvm_riscv_handle_sbi_dbcn(cs, run);
237
+ break;
238
default:
239
qemu_log_mask(LOG_UNIMP,
240
"%s: un-handled SBI EXIT, specific reasons is %lu\n",
39
--
241
--
40
2.29.2
242
2.45.1
41
42
diff view generated by jsdifflib
[PULL 07/23] hw/riscv: Expand the is 32-bit check to support more CPUs
[PULL 05/28] hw/riscv/boot.c: Support 64-bit address for initrd
1
Currently the riscv_is_32_bit() function only supports the generic rv32
1
From: Cheng Yang <yangcheng.work@foxmail.com>
2
CPUs. Extend the function to support the SiFive and LowRISC CPUs as
3
well.
4
2
3
Use qemu_fdt_setprop_u64() instead of qemu_fdt_setprop_cell()
4
to set the address of initrd in FDT to support 64-bit address.
5
6
Signed-off-by: Cheng Yang <yangcheng.work@foxmail.com>
7
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
8
Message-ID: <tencent_A4482251DD0890F312758FA6B33F60815609@qq.com>
5
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
9
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
6
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
7
Acked-by: Palmer Dabbelt <palmerdabbelt@google.com>
8
Message-id: 9a13764115ba78688ba61b56526c6de65fc3ef42.1608142916.git.alistair.francis@wdc.com
9
---
10
---
10
hw/riscv/boot.c | 12 +++++++++++-
11
hw/riscv/boot.c | 4 ++--
11
1 file changed, 11 insertions(+), 1 deletion(-)
12
1 file changed, 2 insertions(+), 2 deletions(-)
12
13
13
diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
14
diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
14
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
15
--- a/hw/riscv/boot.c
16
--- a/hw/riscv/boot.c
16
+++ b/hw/riscv/boot.c
17
+++ b/hw/riscv/boot.c
17
@@ -XXX,XX +XXX,XX @@
18
@@ -XXX,XX +XXX,XX @@ static void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry)
18
19
/* Some RISC-V machines (e.g. opentitan) don't have a fdt. */
19
bool riscv_is_32_bit(MachineState *machine)
20
if (fdt) {
20
{
21
end = start + size;
21
- if (!strncmp(machine->cpu_type, "rv32", 4)) {
22
- qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", start);
22
+ /*
23
- qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", end);
23
+ * To determine if the CPU is 32-bit we need to check a few different CPUs.
24
+ qemu_fdt_setprop_u64(fdt, "/chosen", "linux,initrd-start", start);
24
+ *
25
+ qemu_fdt_setprop_u64(fdt, "/chosen", "linux,initrd-end", end);
25
+ * If the CPU starts with rv32
26
}
26
+ * If the CPU is a sifive 3 seriries CPU (E31, U34)
27
}
27
+ * If it's the Ibex CPU
28
28
+ */
29
+ if (!strncmp(machine->cpu_type, "rv32", 4) ||
30
+ (!strncmp(machine->cpu_type, "sifive", 6) &&
31
+ machine->cpu_type[8] == '3') ||
32
+ !strncmp(machine->cpu_type, "lowrisc-ibex", 12)) {
33
return true;
34
} else {
35
return false;
36
--
29
--
37
2.29.2
30
2.45.1
38
39
diff view generated by jsdifflib
[PULL 05/23] target/riscv: Fix definition of MSTATUS_TW and MSTATUS_TSR
[PULL 06/28] target/riscv: change RISCV_EXCP_SEMIHOST exception number to 63
1
From: Alex Richardson <Alexander.Richardson@cl.cam.ac.uk>
1
From: Clément Léger <cleger@rivosinc.com>
2
2
3
The TW and TSR fields should be bits 21 and 22 and not 30/29.
3
The current semihost exception number (16) is a reserved number (range
4
This was found while comparing QEMU behaviour against the sail formal
4
[16-17]). The upcoming double trap specification uses that number for
5
model (https://github.com/rems-project/sail-riscv/).
5
the double trap exception. Since the privileged spec (Table 22) defines
6
ranges for custom uses change the semihosting exception number to 63
7
which belongs to the range [48-63] in order to avoid any future
8
collisions with reserved exception.
6
9
7
Signed-off-by: Alex Richardson <Alexander.Richardson@cl.cam.ac.uk>
10
Signed-off-by: Clément Léger <cleger@rivosinc.com>
11
8
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
12
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
9
Message-id: 20201130170117.71281-1-Alexander.Richardson@cl.cam.ac.uk
13
Message-ID: <20240422135840.1959967-1-cleger@rivosinc.com>
10
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
14
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
11
---
15
---
12
target/riscv/cpu_bits.h | 4 ++--
16
target/riscv/cpu_bits.h | 2 +-
13
1 file changed, 2 insertions(+), 2 deletions(-)
17
1 file changed, 1 insertion(+), 1 deletion(-)
14
18
15
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
19
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
16
index XXXXXXX..XXXXXXX 100644
20
index XXXXXXX..XXXXXXX 100644
17
--- a/target/riscv/cpu_bits.h
21
--- a/target/riscv/cpu_bits.h
18
+++ b/target/riscv/cpu_bits.h
22
+++ b/target/riscv/cpu_bits.h
19
@@ -XXX,XX +XXX,XX @@
23
@@ -XXX,XX +XXX,XX @@ typedef enum RISCVException {
20
#define MSTATUS_MXR 0x00080000
24
RISCV_EXCP_INST_PAGE_FAULT = 0xc, /* since: priv-1.10.0 */
21
#define MSTATUS_VM 0x1F000000 /* until: priv-1.9.1 */
25
RISCV_EXCP_LOAD_PAGE_FAULT = 0xd, /* since: priv-1.10.0 */
22
#define MSTATUS_TVM 0x00100000 /* since: priv-1.10 */
26
RISCV_EXCP_STORE_PAGE_FAULT = 0xf, /* since: priv-1.10.0 */
23
-#define MSTATUS_TW 0x20000000 /* since: priv-1.10 */
27
- RISCV_EXCP_SEMIHOST = 0x10,
24
-#define MSTATUS_TSR 0x40000000 /* since: priv-1.10 */
28
RISCV_EXCP_INST_GUEST_PAGE_FAULT = 0x14,
25
+#define MSTATUS_TW 0x00200000 /* since: priv-1.10 */
29
RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT = 0x15,
26
+#define MSTATUS_TSR 0x00400000 /* since: priv-1.10 */
30
RISCV_EXCP_VIRT_INSTRUCTION_FAULT = 0x16,
27
#define MSTATUS_GVA 0x4000000000ULL
31
RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT = 0x17,
28
#define MSTATUS_MPV 0x8000000000ULL
32
+ RISCV_EXCP_SEMIHOST = 0x3f,
29
33
} RISCVException;
34
35
#define RISCV_EXCP_INT_FLAG 0x80000000
30
--
36
--
31
2.29.2
37
2.45.1
32
38
33
39
diff view generated by jsdifflib
New patch
[PULL 07/28] target/riscv/kvm: tolerate KVM disable ext errors
1
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
1
2
3
Running a KVM guest using a 6.9-rc3 kernel, in a 6.8 host that has zkr
4
enabled, will fail with a kernel oops SIGILL right at the start. The
5
reason is that we can't expose zkr without implementing the SEED CSR.
6
Disabling zkr in the guest would be a workaround, but if the KVM doesn't
7
allow it we'll error out and never boot.
8
9
In hindsight this is too strict. If we keep proceeding, despite not
10
disabling the extension in the KVM vcpu, we'll not add the extension in
11
the riscv,isa. The guest kernel will be unaware of the extension, i.e.
12
it doesn't matter if the KVM vcpu has it enabled underneath or not. So
13
it's ok to keep booting in this case.
14
15
Change our current logic to not error out if we fail to disable an
16
extension in kvm_set_one_reg(), but show a warning and keep booting. It
17
is important to throw a warning because we must make the user aware that
18
the extension is still available in the vcpu, meaning that an
19
ill-behaved guest can ignore the riscv,isa settings and use the
20
extension.
21
22
The case we're handling happens with an EINVAL error code. If we fail to
23
disable the extension in KVM for any other reason, error out.
24
25
We'll also keep erroring out when we fail to enable an extension in KVM,
26
since adding the extension in riscv,isa at this point will cause a guest
27
malfunction because the extension isn't enabled in the vcpu.
28
29
Suggested-by: Andrew Jones <ajones@ventanamicro.com>
30
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
31
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
32
Cc: qemu-stable <qemu-stable@nongnu.org>
33
Message-ID: <20240422171425.333037-2-dbarboza@ventanamicro.com>
34
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
35
---
36
target/riscv/kvm/kvm-cpu.c | 12 ++++++++----
37
1 file changed, 8 insertions(+), 4 deletions(-)
38
39
diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
40
index XXXXXXX..XXXXXXX 100644
41
--- a/target/riscv/kvm/kvm-cpu.c
42
+++ b/target/riscv/kvm/kvm-cpu.c
43
@@ -XXX,XX +XXX,XX @@ static void kvm_riscv_update_cpu_cfg_isa_ext(RISCVCPU *cpu, CPUState *cs)
44
reg = kvm_cpu_cfg_get(cpu, multi_ext_cfg);
45
ret = kvm_set_one_reg(cs, id, &reg);
46
if (ret != 0) {
47
- error_report("Unable to %s extension %s in KVM, error %d",
48
- reg ? "enable" : "disable",
49
- multi_ext_cfg->name, ret);
50
- exit(EXIT_FAILURE);
51
+ if (!reg && ret == -EINVAL) {
52
+ warn_report("KVM cannot disable extension %s",
53
+ multi_ext_cfg->name);
54
+ } else {
55
+ error_report("Unable to enable extension %s in KVM, error %d",
56
+ multi_ext_cfg->name, ret);
57
+ exit(EXIT_FAILURE);
58
+ }
59
}
60
}
61
}
62
--
63
2.45.1
diff view generated by jsdifflib
New patch
[PULL 08/28] target/riscv/debug: set tval=pc in breakpoint exceptions
1
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
1
2
3
We're not setting (s/m)tval when triggering breakpoints of type 2
4
(mcontrol) and 6 (mcontrol6). According to the debug spec section
5
5.7.12, "Match Control Type 6":
6
7
"The Privileged Spec says that breakpoint exceptions that occur on
8
instruction fetches, loads, or stores update the tval CSR with either
9
zero or the faulting virtual address. The faulting virtual address for
10
an mcontrol6 trigger with action = 0 is the address being accessed and
11
which caused that trigger to fire."
12
13
A similar text is also found in the Debug spec section 5.7.11 w.r.t.
14
mcontrol.
15
16
Note that what we're doing ATM is not violating the spec, but it's
17
simple enough to set mtval/stval and it makes life easier for any
18
software that relies on this info.
19
20
Given that we always use action = 0, save the faulting address for the
21
mcontrol and mcontrol6 trigger breakpoints into env->badaddr, which is
22
used as as scratch area for traps with address information. 'tval' is
23
then set during riscv_cpu_do_interrupt().
24
25
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
26
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
27
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
28
Message-ID: <20240416230437.1869024-2-dbarboza@ventanamicro.com>
29
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
30
---
31
target/riscv/cpu_helper.c | 1 +
32
target/riscv/debug.c | 3 +++
33
2 files changed, 4 insertions(+)
34
35
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
36
index XXXXXXX..XXXXXXX 100644
37
--- a/target/riscv/cpu_helper.c
38
+++ b/target/riscv/cpu_helper.c
39
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
40
tval = env->bins;
41
break;
42
case RISCV_EXCP_BREAKPOINT:
43
+ tval = env->badaddr;
44
if (cs->watchpoint_hit) {
45
tval = cs->watchpoint_hit->hitaddr;
46
cs->watchpoint_hit = NULL;
47
diff --git a/target/riscv/debug.c b/target/riscv/debug.c
48
index XXXXXXX..XXXXXXX 100644
49
--- a/target/riscv/debug.c
50
+++ b/target/riscv/debug.c
51
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_debug_check_breakpoint(CPUState *cs)
52
if ((ctrl & TYPE2_EXEC) && (bp->pc == pc)) {
53
/* check U/S/M bit against current privilege level */
54
if ((ctrl >> 3) & BIT(env->priv)) {
55
+ env->badaddr = pc;
56
return true;
57
}
58
}
59
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_debug_check_breakpoint(CPUState *cs)
60
if (env->virt_enabled) {
61
/* check VU/VS bit against current privilege level */
62
if ((ctrl >> 23) & BIT(env->priv)) {
63
+ env->badaddr = pc;
64
return true;
65
}
66
} else {
67
/* check U/S/M bit against current privilege level */
68
if ((ctrl >> 3) & BIT(env->priv)) {
69
+ env->badaddr = pc;
70
return true;
71
}
72
}
73
--
74
2.45.1
diff view generated by jsdifflib
New patch
[PULL 09/28] trans_privileged.c.inc: set (m|s)tval on ebreak breakpoint
1
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
1
2
3
Privileged spec section 4.1.9 mentions:
4
5
"When a trap is taken into S-mode, stval is written with
6
exception-specific information to assist software in handling the trap.
7
(...)
8
9
If stval is written with a nonzero value when a breakpoint,
10
address-misaligned, access-fault, or page-fault exception occurs on an
11
instruction fetch, load, or store, then stval will contain the faulting
12
virtual address."
13
14
A similar text is found for mtval in section 3.1.16.
15
16
Setting mtval/stval in this scenario is optional, but some softwares read
17
these regs when handling ebreaks.
18
19
Write 'badaddr' in all ebreak breakpoints to write the appropriate
20
'tval' during riscv_do_cpu_interrrupt().
21
22
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
23
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
24
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
25
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
26
Message-ID: <20240416230437.1869024-3-dbarboza@ventanamicro.com>
27
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
28
---
29
target/riscv/insn_trans/trans_privileged.c.inc | 2 ++
30
1 file changed, 2 insertions(+)
31
32
diff --git a/target/riscv/insn_trans/trans_privileged.c.inc b/target/riscv/insn_trans/trans_privileged.c.inc
33
index XXXXXXX..XXXXXXX 100644
34
--- a/target/riscv/insn_trans/trans_privileged.c.inc
35
+++ b/target/riscv/insn_trans/trans_privileged.c.inc
36
@@ -XXX,XX +XXX,XX @@ static bool trans_ebreak(DisasContext *ctx, arg_ebreak *a)
37
if (pre == 0x01f01013 && ebreak == 0x00100073 && post == 0x40705013) {
38
generate_exception(ctx, RISCV_EXCP_SEMIHOST);
39
} else {
40
+ tcg_gen_st_tl(tcg_constant_tl(ebreak_addr), tcg_env,
41
+ offsetof(CPURISCVState, badaddr));
42
generate_exception(ctx, RISCV_EXCP_BREAKPOINT);
43
}
44
return true;
45
--
46
2.45.1
diff view generated by jsdifflib
[PULL 03/23] hw/core/register.c: Don't use '#' flag of printf format
[PULL 10/28] target/riscv: Add support for Zve32x extension
1
From: Xinhao Zhang <zhangxinhao1@huawei.com>
1
From: Jason Chien <jason.chien@sifive.com>
2
2
3
Fix code style. Don't use '#' flag of printf format ('%#') in
3
Add support for Zve32x extension and replace some checks for Zve32f with
4
format strings, use '0x' prefix instead
4
Zve32x, since Zve32f depends on Zve32x.
5
5
6
Signed-off-by: Xinhao Zhang <zhangxinhao1@huawei.com>
6
Signed-off-by: Jason Chien <jason.chien@sifive.com>
7
Signed-off-by: Kai Deng <dengkai1@huawei.com>
7
Reviewed-by: Frank Chang <frank.chang@sifive.com>
8
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
8
Reviewed-by: Max Chou <max.chou@sifive.com>
9
Message-id: 20201116140148.2850128-1-zhangxinhao1@huawei.com
9
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
10
Message-ID: <20240328022343.6871-2-jason.chien@sifive.com>
10
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
11
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
11
---
12
---
12
hw/core/register.c | 16 ++++++++--------
13
target/riscv/cpu_cfg.h | 1 +
13
1 file changed, 8 insertions(+), 8 deletions(-)
14
target/riscv/cpu.c | 2 ++
15
target/riscv/cpu_helper.c | 2 +-
16
target/riscv/csr.c | 2 +-
17
target/riscv/tcg/tcg-cpu.c | 16 ++++++++--------
18
target/riscv/insn_trans/trans_rvv.c.inc | 4 ++--
19
6 files changed, 15 insertions(+), 12 deletions(-)
14
20
15
diff --git a/hw/core/register.c b/hw/core/register.c
21
diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
16
index XXXXXXX..XXXXXXX 100644
22
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/core/register.c
23
--- a/target/riscv/cpu_cfg.h
18
+++ b/hw/core/register.c
24
+++ b/target/riscv/cpu_cfg.h
19
@@ -XXX,XX +XXX,XX @@ void register_write(RegisterInfo *reg, uint64_t val, uint64_t we,
25
@@ -XXX,XX +XXX,XX @@ struct RISCVCPUConfig {
20
26
bool ext_zhinx;
21
if (!ac || !ac->name) {
27
bool ext_zhinxmin;
22
qemu_log_mask(LOG_GUEST_ERROR, "%s: write to undefined device state "
28
bool ext_zve32f;
23
- "(written value: %#" PRIx64 ")\n", prefix, val);
29
+ bool ext_zve32x;
24
+ "(written value: 0x%" PRIx64 ")\n", prefix, val);
30
bool ext_zve64f;
31
bool ext_zve64d;
32
bool ext_zvbb;
33
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
34
index XXXXXXX..XXXXXXX 100644
35
--- a/target/riscv/cpu.c
36
+++ b/target/riscv/cpu.c
37
@@ -XXX,XX +XXX,XX @@ const RISCVIsaExtData isa_edata_arr[] = {
38
ISA_EXT_DATA_ENTRY(zvbb, PRIV_VERSION_1_12_0, ext_zvbb),
39
ISA_EXT_DATA_ENTRY(zvbc, PRIV_VERSION_1_12_0, ext_zvbc),
40
ISA_EXT_DATA_ENTRY(zve32f, PRIV_VERSION_1_10_0, ext_zve32f),
41
+ ISA_EXT_DATA_ENTRY(zve32x, PRIV_VERSION_1_10_0, ext_zve32x),
42
ISA_EXT_DATA_ENTRY(zve64f, PRIV_VERSION_1_10_0, ext_zve64f),
43
ISA_EXT_DATA_ENTRY(zve64d, PRIV_VERSION_1_10_0, ext_zve64d),
44
ISA_EXT_DATA_ENTRY(zvfbfmin, PRIV_VERSION_1_12_0, ext_zvfbfmin),
45
@@ -XXX,XX +XXX,XX @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
46
MULTI_EXT_CFG_BOOL("zfh", ext_zfh, false),
47
MULTI_EXT_CFG_BOOL("zfhmin", ext_zfhmin, false),
48
MULTI_EXT_CFG_BOOL("zve32f", ext_zve32f, false),
49
+ MULTI_EXT_CFG_BOOL("zve32x", ext_zve32x, false),
50
MULTI_EXT_CFG_BOOL("zve64f", ext_zve64f, false),
51
MULTI_EXT_CFG_BOOL("zve64d", ext_zve64d, false),
52
MULTI_EXT_CFG_BOOL("zvfbfmin", ext_zvfbfmin, false),
53
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
54
index XXXXXXX..XXXXXXX 100644
55
--- a/target/riscv/cpu_helper.c
56
+++ b/target/riscv/cpu_helper.c
57
@@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc,
58
*pc = env->xl == MXL_RV32 ? env->pc & UINT32_MAX : env->pc;
59
*cs_base = 0;
60
61
- if (cpu->cfg.ext_zve32f) {
62
+ if (cpu->cfg.ext_zve32x) {
63
/*
64
* If env->vl equals to VLMAX, we can use generic vector operation
65
* expanders (GVEC) to accerlate the vector operations.
66
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
67
index XXXXXXX..XXXXXXX 100644
68
--- a/target/riscv/csr.c
69
+++ b/target/riscv/csr.c
70
@@ -XXX,XX +XXX,XX @@ static RISCVException fs(CPURISCVState *env, int csrno)
71
72
static RISCVException vs(CPURISCVState *env, int csrno)
73
{
74
- if (riscv_cpu_cfg(env)->ext_zve32f) {
75
+ if (riscv_cpu_cfg(env)->ext_zve32x) {
76
#if !defined(CONFIG_USER_ONLY)
77
if (!env->debugger && !riscv_cpu_vector_enabled(env)) {
78
return RISCV_EXCP_ILLEGAL_INST;
79
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
80
index XXXXXXX..XXXXXXX 100644
81
--- a/target/riscv/tcg/tcg-cpu.c
82
+++ b/target/riscv/tcg/tcg-cpu.c
83
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
25
return;
84
return;
26
}
85
}
27
86
28
@@ -XXX,XX +XXX,XX @@ void register_write(RegisterInfo *reg, uint64_t val, uint64_t we,
87
- if (cpu->cfg.ext_zve32f && !riscv_has_ext(env, RVF)) {
29
test = (old_val ^ val) & ac->rsvd;
88
- error_setg(errp, "Zve32f/Zve64f extensions require F extension");
30
if (test) {
89
- return;
31
qemu_log_mask(LOG_GUEST_ERROR, "%s: change of value in reserved bit"
90
+ /* The Zve32f extension depends on the Zve32x extension */
32
- "fields: %#" PRIx64 ")\n", prefix, test);
91
+ if (cpu->cfg.ext_zve32f) {
33
+ "fields: 0x%" PRIx64 ")\n", prefix, test);
92
+ if (!riscv_has_ext(env, RVF)) {
93
+ error_setg(errp, "Zve32f/Zve64f extensions require F extension");
94
+ return;
95
+ }
96
+ cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve32x), true);
34
}
97
}
35
98
36
test = val & ac->unimp;
99
if (cpu->cfg.ext_zvfh) {
37
if (test) {
100
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
38
qemu_log_mask(LOG_UNIMP,
101
cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvbc), true);
39
- "%s:%s writing %#" PRIx64 " to unimplemented bits:" \
40
- " %#" PRIx64 "\n",
41
+ "%s:%s writing 0x%" PRIx64 " to unimplemented bits:" \
42
+ " 0x%" PRIx64 "\n",
43
prefix, reg->access->name, val, ac->unimp);
44
}
102
}
45
103
46
@@ -XXX,XX +XXX,XX @@ void register_write(RegisterInfo *reg, uint64_t val, uint64_t we,
104
- /*
105
- * In principle Zve*x would also suffice here, were they supported
106
- * in qemu
107
- */
108
if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkb || cpu->cfg.ext_zvkg ||
109
cpu->cfg.ext_zvkned || cpu->cfg.ext_zvknha || cpu->cfg.ext_zvksed ||
110
- cpu->cfg.ext_zvksh) && !cpu->cfg.ext_zve32f) {
111
+ cpu->cfg.ext_zvksh) && !cpu->cfg.ext_zve32x) {
112
error_setg(errp,
113
"Vector crypto extensions require V or Zve* extensions");
114
return;
115
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
116
index XXXXXXX..XXXXXXX 100644
117
--- a/target/riscv/insn_trans/trans_rvv.c.inc
118
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
119
@@ -XXX,XX +XXX,XX @@ static bool do_vsetvl(DisasContext *s, int rd, int rs1, TCGv s2)
120
{
121
TCGv s1, dst;
122
123
- if (!require_rvv(s) || !s->cfg_ptr->ext_zve32f) {
124
+ if (!require_rvv(s) || !s->cfg_ptr->ext_zve32x) {
125
return false;
47
}
126
}
48
127
49
if (debug) {
128
@@ -XXX,XX +XXX,XX @@ static bool do_vsetivli(DisasContext *s, int rd, TCGv s1, TCGv s2)
50
- qemu_log("%s:%s: write of value %#" PRIx64 "\n", prefix, ac->name,
129
{
51
+ qemu_log("%s:%s: write of value 0x%" PRIx64 "\n", prefix, ac->name,
130
TCGv dst;
52
new_val);
131
132
- if (!require_rvv(s) || !s->cfg_ptr->ext_zve32f) {
133
+ if (!require_rvv(s) || !s->cfg_ptr->ext_zve32x) {
134
return false;
53
}
135
}
54
136
55
@@ -XXX,XX +XXX,XX @@ uint64_t register_read(RegisterInfo *reg, uint64_t re, const char* prefix,
56
}
57
58
if (debug) {
59
- qemu_log("%s:%s: read of value %#" PRIx64 "\n", prefix,
60
+ qemu_log("%s:%s: read of value 0x%" PRIx64 "\n", prefix,
61
ac->name, ret);
62
}
63
64
@@ -XXX,XX +XXX,XX @@ void register_write_memory(void *opaque, hwaddr addr,
65
66
if (!reg) {
67
qemu_log_mask(LOG_GUEST_ERROR, "%s: write to unimplemented register " \
68
- "at address: %#" PRIx64 "\n", reg_array->prefix, addr);
69
+ "at address: 0x%" PRIx64 "\n", reg_array->prefix, addr);
70
return;
71
}
72
73
@@ -XXX,XX +XXX,XX @@ uint64_t register_read_memory(void *opaque, hwaddr addr,
74
75
if (!reg) {
76
qemu_log_mask(LOG_GUEST_ERROR, "%s: read to unimplemented register " \
77
- "at address: %#" PRIx64 "\n", reg_array->prefix, addr);
78
+ "at address: 0x%" PRIx64 "\n", reg_array->prefix, addr);
79
return 0;
80
}
81
82
--
137
--
83
2.29.2
138
2.45.1
84
85
diff view generated by jsdifflib
[PULL 22/23] hw/riscv: Use the CPU to determine if 32-bit
[PULL 11/28] target/riscv: Add support for Zve64x extension
1
Instead of using string compares to determine if a RISC-V machine is
1
From: Jason Chien <jason.chien@sifive.com>
2
using 32-bit or 64-bit CPUs we can use the initalised CPUs. This avoids
3
us having to maintain a list of CPU names to compare against.
4
2
5
This commit also fixes the name of the function to match the
3
Add support for Zve64x extension. Enabling Zve64f enables Zve64x and
6
riscv_cpu_is_32bit() function.
4
enabling Zve64x enables Zve32x according to their dependency.
7
5
6
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2107
7
Signed-off-by: Jason Chien <jason.chien@sifive.com>
8
Reviewed-by: Frank Chang <frank.chang@sifive.com>
9
Reviewed-by: Max Chou <max.chou@sifive.com>
10
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
11
Message-ID: <20240328022343.6871-3-jason.chien@sifive.com>
8
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
12
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 8ab7614e5df93ab5267788b73dcd75f9f5615e82.1608142916.git.alistair.francis@wdc.com
11
---
13
---
12
include/hw/riscv/boot.h | 8 +++++---
14
target/riscv/cpu_cfg.h | 1 +
13
hw/riscv/boot.c | 31 ++++++++++---------------------
15
target/riscv/cpu.c | 2 ++
14
hw/riscv/sifive_u.c | 10 +++++-----
16
target/riscv/tcg/tcg-cpu.c | 17 +++++++++++------
15
hw/riscv/spike.c | 8 ++++----
17
3 files changed, 14 insertions(+), 6 deletions(-)
16
hw/riscv/virt.c | 9 +++++----
17
5 files changed, 29 insertions(+), 37 deletions(-)
18
18
19
diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h
19
diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
20
index XXXXXXX..XXXXXXX 100644
20
index XXXXXXX..XXXXXXX 100644
21
--- a/include/hw/riscv/boot.h
21
--- a/target/riscv/cpu_cfg.h
22
+++ b/include/hw/riscv/boot.h
22
+++ b/target/riscv/cpu_cfg.h
23
@@ -XXX,XX +XXX,XX @@
23
@@ -XXX,XX +XXX,XX @@ struct RISCVCPUConfig {
24
24
bool ext_zve32x;
25
#include "exec/cpu-defs.h"
25
bool ext_zve64f;
26
#include "hw/loader.h"
26
bool ext_zve64d;
27
+#include "hw/riscv/riscv_hart.h"
27
+ bool ext_zve64x;
28
28
bool ext_zvbb;
29
-bool riscv_is_32_bit(MachineState *machine);
29
bool ext_zvbc;
30
+bool riscv_is_32bit(RISCVHartArrayState harts);
30
bool ext_zvkb;
31
31
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
32
-target_ulong riscv_calc_kernel_start_addr(MachineState *machine,
33
+target_ulong riscv_calc_kernel_start_addr(RISCVHartArrayState harts,
34
target_ulong firmware_end_addr);
35
target_ulong riscv_find_and_load_firmware(MachineState *machine,
36
const char *default_machine_firmware,
37
@@ -XXX,XX +XXX,XX @@ target_ulong riscv_load_kernel(const char *kernel_filename,
38
hwaddr riscv_load_initrd(const char *filename, uint64_t mem_size,
39
uint64_t kernel_entry, hwaddr *start);
40
uint32_t riscv_load_fdt(hwaddr dram_start, uint64_t dram_size, void *fdt);
41
-void riscv_setup_rom_reset_vec(MachineState *machine, hwaddr saddr,
42
+void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState harts,
43
+ hwaddr saddr,
44
hwaddr rom_base, hwaddr rom_size,
45
uint64_t kernel_entry,
46
uint32_t fdt_load_addr, void *fdt);
47
diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
48
index XXXXXXX..XXXXXXX 100644
32
index XXXXXXX..XXXXXXX 100644
49
--- a/hw/riscv/boot.c
33
--- a/target/riscv/cpu.c
50
+++ b/hw/riscv/boot.c
34
+++ b/target/riscv/cpu.c
51
@@ -XXX,XX +XXX,XX @@
35
@@ -XXX,XX +XXX,XX @@ const RISCVIsaExtData isa_edata_arr[] = {
52
36
ISA_EXT_DATA_ENTRY(zve32x, PRIV_VERSION_1_10_0, ext_zve32x),
53
#include <libfdt.h>
37
ISA_EXT_DATA_ENTRY(zve64f, PRIV_VERSION_1_10_0, ext_zve64f),
54
38
ISA_EXT_DATA_ENTRY(zve64d, PRIV_VERSION_1_10_0, ext_zve64d),
55
-bool riscv_is_32_bit(MachineState *machine)
39
+ ISA_EXT_DATA_ENTRY(zve64x, PRIV_VERSION_1_10_0, ext_zve64x),
56
+bool riscv_is_32bit(RISCVHartArrayState harts)
40
ISA_EXT_DATA_ENTRY(zvfbfmin, PRIV_VERSION_1_12_0, ext_zvfbfmin),
57
{
41
ISA_EXT_DATA_ENTRY(zvfbfwma, PRIV_VERSION_1_12_0, ext_zvfbfwma),
58
- /*
42
ISA_EXT_DATA_ENTRY(zvfh, PRIV_VERSION_1_12_0, ext_zvfh),
59
- * To determine if the CPU is 32-bit we need to check a few different CPUs.
43
@@ -XXX,XX +XXX,XX @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
60
- *
44
MULTI_EXT_CFG_BOOL("zve32x", ext_zve32x, false),
61
- * If the CPU starts with rv32
45
MULTI_EXT_CFG_BOOL("zve64f", ext_zve64f, false),
62
- * If the CPU is a sifive 3 seriries CPU (E31, U34)
46
MULTI_EXT_CFG_BOOL("zve64d", ext_zve64d, false),
63
- * If it's the Ibex CPU
47
+ MULTI_EXT_CFG_BOOL("zve64x", ext_zve64x, false),
64
- */
48
MULTI_EXT_CFG_BOOL("zvfbfmin", ext_zvfbfmin, false),
65
- if (!strncmp(machine->cpu_type, "rv32", 4) ||
49
MULTI_EXT_CFG_BOOL("zvfbfwma", ext_zvfbfwma, false),
66
- (!strncmp(machine->cpu_type, "sifive", 6) &&
50
MULTI_EXT_CFG_BOOL("zvfh", ext_zvfh, false),
67
- machine->cpu_type[8] == '3') ||
51
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
68
- !strncmp(machine->cpu_type, "lowrisc-ibex", 12)) {
52
index XXXXXXX..XXXXXXX 100644
69
- return true;
53
--- a/target/riscv/tcg/tcg-cpu.c
70
- } else {
54
+++ b/target/riscv/tcg/tcg-cpu.c
71
- return false;
55
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
72
- }
56
73
+ RISCVCPU hart = harts.harts[0];
57
/* The Zve64d extension depends on the Zve64f extension */
74
+
58
if (cpu->cfg.ext_zve64d) {
75
+ return riscv_cpu_is_32bit(&hart.env);
59
+ if (!riscv_has_ext(env, RVD)) {
76
}
60
+ error_setg(errp, "Zve64d/V extensions require D extension");
77
61
+ return;
78
-target_ulong riscv_calc_kernel_start_addr(MachineState *machine,
62
+ }
79
+target_ulong riscv_calc_kernel_start_addr(RISCVHartArrayState harts,
63
cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve64f), true);
80
target_ulong firmware_end_addr) {
81
- if (riscv_is_32_bit(machine)) {
82
+ if (riscv_is_32bit(harts)) {
83
return QEMU_ALIGN_UP(firmware_end_addr, 4 * MiB);
84
} else {
85
return QEMU_ALIGN_UP(firmware_end_addr, 2 * MiB);
86
@@ -XXX,XX +XXX,XX @@ void riscv_rom_copy_firmware_info(MachineState *machine, hwaddr rom_base,
87
&address_space_memory);
88
}
89
90
-void riscv_setup_rom_reset_vec(MachineState *machine, hwaddr start_addr,
91
+void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState harts,
92
+ hwaddr start_addr,
93
hwaddr rom_base, hwaddr rom_size,
94
uint64_t kernel_entry,
95
uint32_t fdt_load_addr, void *fdt)
96
@@ -XXX,XX +XXX,XX @@ void riscv_setup_rom_reset_vec(MachineState *machine, hwaddr start_addr,
97
int i;
98
uint32_t start_addr_hi32 = 0x00000000;
99
100
- if (!riscv_is_32_bit(machine)) {
101
+ if (!riscv_is_32bit(harts)) {
102
start_addr_hi32 = start_addr >> 32;
103
}
64
}
104
/* reset vector */
65
105
@@ -XXX,XX +XXX,XX @@ void riscv_setup_rom_reset_vec(MachineState *machine, hwaddr start_addr,
66
- /* The Zve64f extension depends on the Zve32f extension */
106
0x00000000,
67
+ /* The Zve64f extension depends on the Zve64x and Zve32f extensions */
107
/* fw_dyn: */
68
if (cpu->cfg.ext_zve64f) {
108
};
69
+ cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve64x), true);
109
- if (riscv_is_32_bit(machine)) {
70
cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve32f), true);
110
+ if (riscv_is_32bit(harts)) {
111
reset_vec[3] = 0x0202a583; /* lw a1, 32(t0) */
112
reset_vec[4] = 0x0182a283; /* lw t0, 24(t0) */
113
} else {
114
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
115
index XXXXXXX..XXXXXXX 100644
116
--- a/hw/riscv/sifive_u.c
117
+++ b/hw/riscv/sifive_u.c
118
@@ -XXX,XX +XXX,XX @@ static void sifive_u_machine_init(MachineState *machine)
119
120
/* create device tree */
121
create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline,
122
- riscv_is_32_bit(machine));
123
+ riscv_is_32bit(s->soc.u_cpus));
124
125
if (s->start_in_flash) {
126
/*
127
@@ -XXX,XX +XXX,XX @@ static void sifive_u_machine_init(MachineState *machine)
128
break;
129
}
71
}
130
72
131
- if (riscv_is_32_bit(machine)) {
73
- if (cpu->cfg.ext_zve64d && !riscv_has_ext(env, RVD)) {
132
+ if (riscv_is_32bit(s->soc.u_cpus)) {
74
- error_setg(errp, "Zve64d/V extensions require D extension");
133
firmware_end_addr = riscv_find_and_load_firmware(machine,
75
- return;
134
"opensbi-riscv32-generic-fw_dynamic.bin",
76
+ /* The Zve64x extension depends on the Zve32x extension */
135
start_addr, NULL);
77
+ if (cpu->cfg.ext_zve64x) {
136
@@ -XXX,XX +XXX,XX @@ static void sifive_u_machine_init(MachineState *machine)
78
+ cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve32x), true);
137
}
79
}
138
80
139
if (machine->kernel_filename) {
81
/* The Zve32f extension depends on the Zve32x extension */
140
- kernel_start_addr = riscv_calc_kernel_start_addr(machine,
82
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
141
+ kernel_start_addr = riscv_calc_kernel_start_addr(s->soc.u_cpus,
83
return;
142
firmware_end_addr);
143
144
kernel_entry = riscv_load_kernel(machine->kernel_filename,
145
@@ -XXX,XX +XXX,XX @@ static void sifive_u_machine_init(MachineState *machine)
146
/* Compute the fdt load address in dram */
147
fdt_load_addr = riscv_load_fdt(memmap[SIFIVE_U_DEV_DRAM].base,
148
machine->ram_size, s->fdt);
149
- if (!riscv_is_32_bit(machine)) {
150
+ if (!riscv_is_32bit(s->soc.u_cpus)) {
151
start_addr_hi32 = (uint64_t)start_addr >> 32;
152
}
84
}
153
85
154
@@ -XXX,XX +XXX,XX @@ static void sifive_u_machine_init(MachineState *machine)
86
- if ((cpu->cfg.ext_zvbc || cpu->cfg.ext_zvknhb) && !cpu->cfg.ext_zve64f) {
155
0x00000000,
87
+ if ((cpu->cfg.ext_zvbc || cpu->cfg.ext_zvknhb) && !cpu->cfg.ext_zve64x) {
156
/* fw_dyn: */
88
error_setg(
157
};
89
errp,
158
- if (riscv_is_32_bit(machine)) {
90
- "Zvbc and Zvknhb extensions require V or Zve64{f,d} extensions");
159
+ if (riscv_is_32bit(s->soc.u_cpus)) {
91
+ "Zvbc and Zvknhb extensions require V or Zve64x extensions");
160
reset_vec[4] = 0x0202a583; /* lw a1, 32(t0) */
92
return;
161
reset_vec[5] = 0x0182a283; /* lw t0, 24(t0) */
162
} else {
163
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
164
index XXXXXXX..XXXXXXX 100644
165
--- a/hw/riscv/spike.c
166
+++ b/hw/riscv/spike.c
167
@@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine)
168
169
/* create device tree */
170
create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline,
171
- riscv_is_32_bit(machine));
172
+ riscv_is_32bit(s->soc[0]));
173
174
/* boot rom */
175
memory_region_init_rom(mask_rom, NULL, "riscv.spike.mrom",
176
@@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine)
177
* keeping ELF files here was intentional because BIN files don't work
178
* for the Spike machine as HTIF emulation depends on ELF parsing.
179
*/
180
- if (riscv_is_32_bit(machine)) {
181
+ if (riscv_is_32bit(s->soc[0])) {
182
firmware_end_addr = riscv_find_and_load_firmware(machine,
183
"opensbi-riscv32-generic-fw_dynamic.elf",
184
memmap[SPIKE_DRAM].base,
185
@@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine)
186
}
93
}
187
94
188
if (machine->kernel_filename) {
189
- kernel_start_addr = riscv_calc_kernel_start_addr(machine,
190
+ kernel_start_addr = riscv_calc_kernel_start_addr(s->soc[0],
191
firmware_end_addr);
192
193
kernel_entry = riscv_load_kernel(machine->kernel_filename,
194
@@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine)
195
fdt_load_addr = riscv_load_fdt(memmap[SPIKE_DRAM].base,
196
machine->ram_size, s->fdt);
197
/* load the reset vector */
198
- riscv_setup_rom_reset_vec(machine, memmap[SPIKE_DRAM].base,
199
+ riscv_setup_rom_reset_vec(machine, s->soc[0], memmap[SPIKE_DRAM].base,
200
memmap[SPIKE_MROM].base,
201
memmap[SPIKE_MROM].size, kernel_entry,
202
fdt_load_addr, s->fdt);
203
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
204
index XXXXXXX..XXXXXXX 100644
205
--- a/hw/riscv/virt.c
206
+++ b/hw/riscv/virt.c
207
@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
208
209
/* create device tree */
210
create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline,
211
- riscv_is_32_bit(machine));
212
+ riscv_is_32bit(s->soc[0]));
213
214
/* boot rom */
215
memory_region_init_rom(mask_rom, NULL, "riscv_virt_board.mrom",
216
@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
217
memory_region_add_subregion(system_memory, memmap[VIRT_MROM].base,
218
mask_rom);
219
220
- if (riscv_is_32_bit(machine)) {
221
+ if (riscv_is_32bit(s->soc[0])) {
222
firmware_end_addr = riscv_find_and_load_firmware(machine,
223
"opensbi-riscv32-generic-fw_dynamic.bin",
224
start_addr, NULL);
225
@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
226
}
227
228
if (machine->kernel_filename) {
229
- kernel_start_addr = riscv_calc_kernel_start_addr(machine,
230
+ kernel_start_addr = riscv_calc_kernel_start_addr(s->soc[0],
231
firmware_end_addr);
232
233
kernel_entry = riscv_load_kernel(machine->kernel_filename,
234
@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
235
fdt_load_addr = riscv_load_fdt(memmap[VIRT_DRAM].base,
236
machine->ram_size, s->fdt);
237
/* load the reset vector */
238
- riscv_setup_rom_reset_vec(machine, start_addr, virt_memmap[VIRT_MROM].base,
239
+ riscv_setup_rom_reset_vec(machine, s->soc[0], start_addr,
240
+ virt_memmap[VIRT_MROM].base,
241
virt_memmap[VIRT_MROM].size, kernel_entry,
242
fdt_load_addr, s->fdt);
243
244
--
95
--
245
2.29.2
96
2.45.1
246
247
diff view generated by jsdifflib
New patch
[PULL 12/28] target/riscv: Relax vector register check in RISCV gdbstub
1
From: Jason Chien <jason.chien@sifive.com>
1
2
3
In current implementation, the gdbstub allows reading vector registers
4
only if V extension is supported. However, all vector extensions and
5
vector crypto extensions have the vector registers and they all depend
6
on Zve32x. The gdbstub should check for Zve32x instead.
7
8
Signed-off-by: Jason Chien <jason.chien@sifive.com>
9
Reviewed-by: Frank Chang <frank.chang@sifive.com>
10
Reviewed-by: Max Chou <max.chou@sifive.com>
11
Message-ID: <20240328022343.6871-4-jason.chien@sifive.com>
12
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
13
---
14
target/riscv/gdbstub.c | 2 +-
15
1 file changed, 1 insertion(+), 1 deletion(-)
16
17
diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
18
index XXXXXXX..XXXXXXX 100644
19
--- a/target/riscv/gdbstub.c
20
+++ b/target/riscv/gdbstub.c
21
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs)
22
gdb_find_static_feature("riscv-32bit-fpu.xml"),
23
0);
24
}
25
- if (env->misa_ext & RVV) {
26
+ if (cpu->cfg.ext_zve32x) {
27
gdb_register_coprocessor(cs, riscv_gdb_get_vector,
28
riscv_gdb_set_vector,
29
ricsv_gen_dynamic_vector_feature(cs, cs->gdb_num_regs),
30
--
31
2.45.1
diff view generated by jsdifflib
[PULL 02/23] hw/riscv: microchip_pfsoc: add QSPI NOR flash
[PULL 13/28] target/riscv: Fix the element agnostic function problem
1
From: Vitaly Wool <vitaly.wool@konsulko.com>
1
From: Huang Tao <eric.huang@linux.alibaba.com>
2
2
3
Add QSPI NOR flash definition for Microchip PolarFire SoC.
3
In RVV and vcrypto instructions, the masked and tail elements are set to 1s
4
using vext_set_elems_1s function if the vma/vta bit is set. It is the element
5
agnostic policy.
4
6
5
Signed-off-by: Vitaly Wool <vitaly.wool@konsulko.com>
7
However, this function can't deal the big endian situation. This patch fixes
6
Acked-by: Alistair Francis <alistair.francis@wdc.com>
8
the problem by adding handling of such case.
7
Reviewed-by: Bin Meng <bin.meng@windriver.com>
9
8
Message-id: 20201112074950.33283-1-vitaly.wool@konsulko.com
10
Signed-off-by: Huang Tao <eric.huang@linux.alibaba.com>
11
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
12
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
13
Cc: qemu-stable <qemu-stable@nongnu.org>
14
Message-ID: <20240325021654.6594-1-eric.huang@linux.alibaba.com>
9
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
15
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
10
---
16
---
11
include/hw/riscv/microchip_pfsoc.h | 3 +++
17
target/riscv/vector_internals.c | 22 ++++++++++++++++++++++
12
hw/riscv/microchip_pfsoc.c | 21 +++++++++++++++++++++
18
1 file changed, 22 insertions(+)
13
2 files changed, 24 insertions(+)
14
19
15
diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h
20
diff --git a/target/riscv/vector_internals.c b/target/riscv/vector_internals.c
16
index XXXXXXX..XXXXXXX 100644
21
index XXXXXXX..XXXXXXX 100644
17
--- a/include/hw/riscv/microchip_pfsoc.h
22
--- a/target/riscv/vector_internals.c
18
+++ b/include/hw/riscv/microchip_pfsoc.h
23
+++ b/target/riscv/vector_internals.c
19
@@ -XXX,XX +XXX,XX @@ enum {
24
@@ -XXX,XX +XXX,XX @@ void vext_set_elems_1s(void *base, uint32_t is_agnostic, uint32_t cnt,
20
MICROCHIP_PFSOC_MMUART2,
25
if (tot - cnt == 0) {
21
MICROCHIP_PFSOC_MMUART3,
26
return ;
22
MICROCHIP_PFSOC_MMUART4,
27
}
23
+ MICROCHIP_PFSOC_SPI0,
24
+ MICROCHIP_PFSOC_SPI1,
25
MICROCHIP_PFSOC_I2C1,
26
MICROCHIP_PFSOC_GEM0,
27
MICROCHIP_PFSOC_GEM1,
28
@@ -XXX,XX +XXX,XX @@ enum {
29
MICROCHIP_PFSOC_GPIO2,
30
MICROCHIP_PFSOC_ENVM_CFG,
31
MICROCHIP_PFSOC_ENVM_DATA,
32
+ MICROCHIP_PFSOC_QSPI_XIP,
33
MICROCHIP_PFSOC_IOSCB,
34
MICROCHIP_PFSOC_DRAM_LO,
35
MICROCHIP_PFSOC_DRAM_LO_ALIAS,
36
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
37
index XXXXXXX..XXXXXXX 100644
38
--- a/hw/riscv/microchip_pfsoc.c
39
+++ b/hw/riscv/microchip_pfsoc.c
40
@@ -XXX,XX +XXX,XX @@ static const struct MemmapEntry {
41
[MICROCHIP_PFSOC_MMUART2] = { 0x20102000, 0x1000 },
42
[MICROCHIP_PFSOC_MMUART3] = { 0x20104000, 0x1000 },
43
[MICROCHIP_PFSOC_MMUART4] = { 0x20106000, 0x1000 },
44
+ [MICROCHIP_PFSOC_SPI0] = { 0x20108000, 0x1000 },
45
+ [MICROCHIP_PFSOC_SPI1] = { 0x20109000, 0x1000 },
46
[MICROCHIP_PFSOC_I2C1] = { 0x2010b000, 0x1000 },
47
[MICROCHIP_PFSOC_GEM0] = { 0x20110000, 0x2000 },
48
[MICROCHIP_PFSOC_GEM1] = { 0x20112000, 0x2000 },
49
@@ -XXX,XX +XXX,XX @@ static const struct MemmapEntry {
50
[MICROCHIP_PFSOC_GPIO2] = { 0x20122000, 0x1000 },
51
[MICROCHIP_PFSOC_ENVM_CFG] = { 0x20200000, 0x1000 },
52
[MICROCHIP_PFSOC_ENVM_DATA] = { 0x20220000, 0x20000 },
53
+ [MICROCHIP_PFSOC_QSPI_XIP] = { 0x21000000, 0x1000000 },
54
[MICROCHIP_PFSOC_IOSCB] = { 0x30000000, 0x10000000 },
55
[MICROCHIP_PFSOC_DRAM_LO] = { 0x80000000, 0x40000000 },
56
[MICROCHIP_PFSOC_DRAM_LO_ALIAS] = { 0xc0000000, 0x40000000 },
57
@@ -XXX,XX +XXX,XX @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
58
MemoryRegion *e51_dtim_mem = g_new(MemoryRegion, 1);
59
MemoryRegion *l2lim_mem = g_new(MemoryRegion, 1);
60
MemoryRegion *envm_data = g_new(MemoryRegion, 1);
61
+ MemoryRegion *qspi_xip_mem = g_new(MemoryRegion, 1);
62
char *plic_hart_config;
63
size_t plic_hart_config_len;
64
NICInfo *nd;
65
@@ -XXX,XX +XXX,XX @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
66
qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART4_IRQ),
67
serial_hd(4));
68
69
+ /* SPI */
70
+ create_unimplemented_device("microchip.pfsoc.spi0",
71
+ memmap[MICROCHIP_PFSOC_SPI0].base,
72
+ memmap[MICROCHIP_PFSOC_SPI0].size);
73
+ create_unimplemented_device("microchip.pfsoc.spi1",
74
+ memmap[MICROCHIP_PFSOC_SPI1].base,
75
+ memmap[MICROCHIP_PFSOC_SPI1].size);
76
+
28
+
77
/* I2C1 */
29
+ if (HOST_BIG_ENDIAN) {
78
create_unimplemented_device("microchip.pfsoc.i2c1",
30
+ /*
79
memmap[MICROCHIP_PFSOC_I2C1].base,
31
+ * Deal the situation when the elements are insdie
80
@@ -XXX,XX +XXX,XX @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
32
+ * only one uint64 block including setting the
81
sysbus_realize(SYS_BUS_DEVICE(&s->ioscb), errp);
33
+ * masked-off element.
82
sysbus_mmio_map(SYS_BUS_DEVICE(&s->ioscb), 0,
34
+ */
83
memmap[MICROCHIP_PFSOC_IOSCB].base);
35
+ if (((tot - 1) ^ cnt) < 8) {
84
+
36
+ memset(base + H1(tot - 1), -1, tot - cnt);
85
+ /* QSPI Flash */
37
+ return;
86
+ memory_region_init_rom(qspi_xip_mem, OBJECT(dev),
38
+ }
87
+ "microchip.pfsoc.qspi_xip",
39
+ /*
88
+ memmap[MICROCHIP_PFSOC_QSPI_XIP].size,
40
+ * Otherwise, at least cross two uint64_t blocks.
89
+ &error_fatal);
41
+ * Set first unaligned block.
90
+ memory_region_add_subregion(system_memory,
42
+ */
91
+ memmap[MICROCHIP_PFSOC_QSPI_XIP].base,
43
+ if (cnt % 8 != 0) {
92
+ qspi_xip_mem);
44
+ uint32_t j = ROUND_UP(cnt, 8);
45
+ memset(base + H1(j - 1), -1, j - cnt);
46
+ cnt = j;
47
+ }
48
+ /* Set other 64bit aligend blocks */
49
+ }
50
memset(base + cnt, -1, tot - cnt);
93
}
51
}
94
52
95
static void microchip_pfsoc_soc_class_init(ObjectClass *oc, void *data)
96
--
53
--
97
2.29.2
54
2.45.1
98
99
diff view generated by jsdifflib
[PULL 18/23] target/riscv: cpu: Remove compile time XLEN checks
[PULL 14/28] target/riscv/cpu.c: fix Zvkb extension config
1
From: Yangyu Chen <cyy@cyyself.name>
2
3
This code has a typo that writes zvkb to zvkg, causing users can't
4
enable zvkb through the config. This patch gets this fixed.
5
6
Signed-off-by: Yangyu Chen <cyy@cyyself.name>
7
Fixes: ea61ef7097d0 ("target/riscv: Move vector crypto extensions to riscv_cpu_extensions")
8
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
9
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
10
Reviewed-by: Max Chou <max.chou@sifive.com>
11
Reviewed-by:  Weiwei Li <liwei1518@gmail.com>
12
Message-ID: <tencent_7E34EEF0F90B9A68BF38BEE09EC6D4877C0A@qq.com>
13
Cc: qemu-stable <qemu-stable@nongnu.org>
1
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
14
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2
Reviewed-by: Bin Meng <bin.meng@windriver.com>
3
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
5
Acked-by: Palmer Dabbelt <palmerdabbelt@google.com>
6
Tested-by: Bin Meng <bin.meng@windriver.com>
7
Message-id: a426ead44db5065a0790066d43e91245683509d7.1608142916.git.alistair.francis@wdc.com
8
---
15
---
9
target/riscv/cpu.c | 19 ++++++++++---------
16
target/riscv/cpu.c | 2 +-
10
1 file changed, 10 insertions(+), 9 deletions(-)
17
1 file changed, 1 insertion(+), 1 deletion(-)
11
18
12
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
19
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
13
index XXXXXXX..XXXXXXX 100644
20
index XXXXXXX..XXXXXXX 100644
14
--- a/target/riscv/cpu.c
21
--- a/target/riscv/cpu.c
15
+++ b/target/riscv/cpu.c
22
+++ b/target/riscv/cpu.c
16
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
23
@@ -XXX,XX +XXX,XX @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
17
#ifndef CONFIG_USER_ONLY
24
/* Vector cryptography extensions */
18
qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mhartid ", env->mhartid);
25
MULTI_EXT_CFG_BOOL("zvbb", ext_zvbb, false),
19
qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatus ", (target_ulong)env->mstatus);
26
MULTI_EXT_CFG_BOOL("zvbc", ext_zvbc, false),
20
-#ifdef TARGET_RISCV32
27
- MULTI_EXT_CFG_BOOL("zvkb", ext_zvkg, false),
21
- qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatush ",
28
+ MULTI_EXT_CFG_BOOL("zvkb", ext_zvkb, false),
22
- (target_ulong)(env->mstatus >> 32));
29
MULTI_EXT_CFG_BOOL("zvkg", ext_zvkg, false),
23
-#endif
30
MULTI_EXT_CFG_BOOL("zvkned", ext_zvkned, false),
24
+ if (riscv_cpu_is_32bit(env)) {
31
MULTI_EXT_CFG_BOOL("zvknha", ext_zvknha, false),
25
+ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatush ",
26
+ (target_ulong)(env->mstatus >> 32));
27
+ }
28
if (riscv_has_ext(env, RVH)) {
29
qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hstatus ", env->hstatus);
30
qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vsstatus ",
31
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_reset(DeviceState *dev)
32
33
static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info)
34
{
35
-#if defined(TARGET_RISCV32)
36
- info->print_insn = print_insn_riscv32;
37
-#elif defined(TARGET_RISCV64)
38
- info->print_insn = print_insn_riscv64;
39
-#endif
40
+ RISCVCPU *cpu = RISCV_CPU(s);
41
+ if (riscv_cpu_is_32bit(&cpu->env)) {
42
+ info->print_insn = print_insn_riscv32;
43
+ } else {
44
+ info->print_insn = print_insn_riscv64;
45
+ }
46
}
47
48
static void riscv_cpu_realize(DeviceState *dev, Error **errp)
49
--
32
--
50
2.29.2
33
2.45.1
51
34
52
35
diff view generated by jsdifflib
[PULL 16/23] target/riscv: Add a riscv_cpu_is_32bit() helper function
[PULL 15/28] target/riscv: Implement dynamic establishment of custom decoder
1
From: Huang Tao <eric.huang@linux.alibaba.com>
2
3
In this patch, we modify the decoder to be a freely composable data
4
structure instead of a hardcoded one. It can be dynamically builded up
5
according to the extensions.
6
This approach has several benefits:
7
1. Provides support for heterogeneous cpu architectures. As we add decoder in
8
RISCVCPU, each cpu can have their own decoder, and the decoders can be
9
different due to cpu's features.
10
2. Improve the decoding efficiency. We run the guard_func to see if the decoder
11
can be added to the dynamic_decoder when building up the decoder. Therefore,
12
there is no need to run the guard_func when decoding each instruction. It can
13
improve the decoding efficiency
14
3. For vendor or dynamic cpus, it allows them to customize their own decoder
15
functions to improve decoding efficiency, especially when vendor-defined
16
instruction sets increase. Because of dynamic building up, it can skip the other
17
decoder guard functions when decoding.
18
4. Pre patch for allowing adding a vendor decoder before decode_insn32() with minimal
19
overhead for users that don't need this particular vendor decoder.
20
21
Signed-off-by: Huang Tao <eric.huang@linux.alibaba.com>
22
Suggested-by: Christoph Muellner <christoph.muellner@vrull.eu>
23
Co-authored-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
24
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
25
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
26
Message-ID: <20240506023607.29544-1-eric.huang@linux.alibaba.com>
1
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
27
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2
Reviewed-by: Bin Meng <bin.meng@windriver.com>
3
Tested-by: Bin Meng <bin.meng@windriver.com>
4
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
5
Acked-by: Palmer Dabbelt <palmerdabbelt@google.com>
6
Message-id: ebd37b237a8cbe457335b948bd57f487b6b31869.1608142916.git.alistair.francis@wdc.com
7
---
28
---
8
target/riscv/cpu.h | 2 ++
29
target/riscv/cpu.h | 1 +
9
target/riscv/cpu.c | 9 +++++++++
30
target/riscv/tcg/tcg-cpu.h | 15 +++++++++++++++
10
2 files changed, 11 insertions(+)
31
target/riscv/cpu.c | 1 +
32
target/riscv/tcg/tcg-cpu.c | 15 +++++++++++++++
33
target/riscv/translate.c | 31 +++++++++++++++----------------
34
5 files changed, 47 insertions(+), 16 deletions(-)
11
35
12
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
36
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
13
index XXXXXXX..XXXXXXX 100644
37
index XXXXXXX..XXXXXXX 100644
14
--- a/target/riscv/cpu.h
38
--- a/target/riscv/cpu.h
15
+++ b/target/riscv/cpu.h
39
+++ b/target/riscv/cpu.h
16
@@ -XXX,XX +XXX,XX @@ FIELD(TB_FLAGS, VILL, 8, 1)
40
@@ -XXX,XX +XXX,XX @@ struct ArchCPU {
17
/* Is a Hypervisor instruction load/store allowed? */
41
uint32_t pmu_avail_ctrs;
18
FIELD(TB_FLAGS, HLSX, 9, 1)
42
/* Mapping of events to counters */
19
43
GHashTable *pmu_event_ctr_map;
20
+bool riscv_cpu_is_32bit(CPURISCVState *env);
44
+ const GPtrArray *decoders;
45
};
46
47
/**
48
diff --git a/target/riscv/tcg/tcg-cpu.h b/target/riscv/tcg/tcg-cpu.h
49
index XXXXXXX..XXXXXXX 100644
50
--- a/target/riscv/tcg/tcg-cpu.h
51
+++ b/target/riscv/tcg/tcg-cpu.h
52
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp);
53
void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error **errp);
54
bool riscv_cpu_tcg_compatible(RISCVCPU *cpu);
55
56
+struct DisasContext;
57
+struct RISCVCPUConfig;
58
+typedef struct RISCVDecoder {
59
+ bool (*guard_func)(const struct RISCVCPUConfig *);
60
+ bool (*riscv_cpu_decode_fn)(struct DisasContext *, uint32_t);
61
+} RISCVDecoder;
21
+
62
+
22
/*
63
+typedef bool (*riscv_cpu_decode_fn)(struct DisasContext *, uint32_t);
23
* A simplification for VLMAX
64
+
24
* = (1 << LMUL) * VLEN / (8 * (1 << SEW))
65
+extern const size_t decoder_table_size;
66
+
67
+extern const RISCVDecoder decoder_table[];
68
+
69
+void riscv_tcg_cpu_finalize_dynamic_decoder(RISCVCPU *cpu);
70
+
71
#endif
25
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
72
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
26
index XXXXXXX..XXXXXXX 100644
73
index XXXXXXX..XXXXXXX 100644
27
--- a/target/riscv/cpu.c
74
--- a/target/riscv/cpu.c
28
+++ b/target/riscv/cpu.c
75
+++ b/target/riscv/cpu.c
29
@@ -XXX,XX +XXX,XX @@ const char *riscv_cpu_get_trap_name(target_ulong cause, bool async)
76
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_finalize_features(RISCVCPU *cpu, Error **errp)
77
error_propagate(errp, local_err);
78
return;
79
}
80
+ riscv_tcg_cpu_finalize_dynamic_decoder(cpu);
81
} else if (kvm_enabled()) {
82
riscv_kvm_cpu_finalize_features(cpu, &local_err);
83
if (local_err != NULL) {
84
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
85
index XXXXXXX..XXXXXXX 100644
86
--- a/target/riscv/tcg/tcg-cpu.c
87
+++ b/target/riscv/tcg/tcg-cpu.c
88
@@ -XXX,XX +XXX,XX @@ void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error **errp)
30
}
89
}
31
}
90
}
32
91
33
+bool riscv_cpu_is_32bit(CPURISCVState *env)
92
+void riscv_tcg_cpu_finalize_dynamic_decoder(RISCVCPU *cpu)
34
+{
93
+{
35
+ if (env->misa & RV64) {
94
+ GPtrArray *dynamic_decoders;
36
+ return false;
95
+ dynamic_decoders = g_ptr_array_sized_new(decoder_table_size);
96
+ for (size_t i = 0; i < decoder_table_size; ++i) {
97
+ if (decoder_table[i].guard_func &&
98
+ decoder_table[i].guard_func(&cpu->cfg)) {
99
+ g_ptr_array_add(dynamic_decoders,
100
+ (gpointer)decoder_table[i].riscv_cpu_decode_fn);
101
+ }
37
+ }
102
+ }
38
+
103
+
39
+ return true;
104
+ cpu->decoders = dynamic_decoders;
40
+}
105
+}
41
+
106
+
42
static void set_misa(CPURISCVState *env, target_ulong misa)
107
bool riscv_cpu_tcg_compatible(RISCVCPU *cpu)
43
{
108
{
44
env->misa_mask = env->misa = misa;
109
return object_dynamic_cast(OBJECT(cpu), TYPE_RISCV_CPU_HOST) == NULL;
110
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
111
index XXXXXXX..XXXXXXX 100644
112
--- a/target/riscv/translate.c
113
+++ b/target/riscv/translate.c
114
@@ -XXX,XX +XXX,XX @@
115
#include "exec/helper-info.c.inc"
116
#undef HELPER_H
117
118
+#include "tcg/tcg-cpu.h"
119
+
120
/* global register indices */
121
static TCGv cpu_gpr[32], cpu_gprh[32], cpu_pc, cpu_vl, cpu_vstart;
122
static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */
123
@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
124
/* FRM is known to contain a valid value. */
125
bool frm_valid;
126
bool insn_start_updated;
127
+ const GPtrArray *decoders;
128
} DisasContext;
129
130
static inline bool has_ext(DisasContext *ctx, uint32_t ext)
131
@@ -XXX,XX +XXX,XX @@ static inline int insn_len(uint16_t first_word)
132
return (first_word & 3) == 3 ? 4 : 2;
133
}
134
135
+const RISCVDecoder decoder_table[] = {
136
+ { always_true_p, decode_insn32 },
137
+ { has_xthead_p, decode_xthead},
138
+ { has_XVentanaCondOps_p, decode_XVentanaCodeOps},
139
+};
140
+
141
+const size_t decoder_table_size = ARRAY_SIZE(decoder_table);
142
+
143
static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
144
{
145
- /*
146
- * A table with predicate (i.e., guard) functions and decoder functions
147
- * that are tested in-order until a decoder matches onto the opcode.
148
- */
149
- static const struct {
150
- bool (*guard_func)(const RISCVCPUConfig *);
151
- bool (*decode_func)(DisasContext *, uint32_t);
152
- } decoders[] = {
153
- { always_true_p, decode_insn32 },
154
- { has_xthead_p, decode_xthead },
155
- { has_XVentanaCondOps_p, decode_XVentanaCodeOps },
156
- };
157
-
158
ctx->virt_inst_excp = false;
159
ctx->cur_insn_len = insn_len(opcode);
160
/* Check for compressed insn */
161
@@ -XXX,XX +XXX,XX @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
162
ctx->base.pc_next + 2));
163
ctx->opcode = opcode32;
164
165
- for (size_t i = 0; i < ARRAY_SIZE(decoders); ++i) {
166
- if (decoders[i].guard_func(ctx->cfg_ptr) &&
167
- decoders[i].decode_func(ctx, opcode32)) {
168
+ for (guint i = 0; i < ctx->decoders->len; ++i) {
169
+ riscv_cpu_decode_fn func = g_ptr_array_index(ctx->decoders, i);
170
+ if (func(ctx, opcode32)) {
171
return;
172
}
173
}
174
@@ -XXX,XX +XXX,XX @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
175
ctx->itrigger = FIELD_EX32(tb_flags, TB_FLAGS, ITRIGGER);
176
ctx->zero = tcg_constant_tl(0);
177
ctx->virt_inst_excp = false;
178
+ ctx->decoders = cpu->decoders;
179
}
180
181
static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu)
45
--
182
--
46
2.29.2
183
2.45.1
47
48
diff view generated by jsdifflib
[PULL 21/23] target/riscv: cpu: Set XLEN independently from target
[PULL 16/28] riscv: thead: Add th.sxstatus CSR emulation
1
From: Christoph Müllner <christoph.muellner@vrull.eu>
2
3
The th.sxstatus CSR can be used to identify available custom extension
4
on T-Head CPUs. The CSR is documented here:
5
https://github.com/T-head-Semi/thead-extension-spec/blob/master/xtheadsxstatus.adoc
6
7
An important property of this patch is, that the th.sxstatus MAEE field
8
is not set (indicating that XTheadMae is not available).
9
XTheadMae is a memory attribute extension (similar to Svpbmt) which is
10
implemented in many T-Head CPUs (C906, C910, etc.) and utilizes bits
11
in PTEs that are marked as reserved. QEMU maintainers prefer to not
12
implement XTheadMae, so we need give kernels a mechanism to identify
13
if XTheadMae is available in a system or not. And this patch introduces
14
this mechanism in QEMU in a way that's compatible with real HW
15
(i.e., probing the th.sxstatus.MAEE bit).
16
17
Further context can be found on the list:
18
https://lists.gnu.org/archive/html/qemu-devel/2024-02/msg00775.html
19
20
Reviewed-by: LIU Zhiwei <zhiwe_liu@linux.alibaba.com>
21
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
22
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
23
Message-ID: <20240429073656.2486732-1-christoph.muellner@vrull.eu>
1
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
24
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2
Reviewed-by: Bin Meng <bin.meng@windriver.com>
3
Tested-by: Bin Meng <bin.meng@windriver.com>
4
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
5
Acked-by: Palmer Dabbelt <palmerdabbelt@google.com>
6
Message-id: 7eddba45b5d223321c031431849fdd42eceb514b.1608142916.git.alistair.francis@wdc.com
7
---
25
---
8
target/riscv/cpu.c | 25 ++++++++++++++++---------
26
MAINTAINERS | 1 +
9
1 file changed, 16 insertions(+), 9 deletions(-)
27
target/riscv/cpu.h | 3 ++
28
target/riscv/cpu.c | 1 +
29
target/riscv/th_csr.c | 79 ++++++++++++++++++++++++++++++++++++++++
30
target/riscv/meson.build | 1 +
31
5 files changed, 85 insertions(+)
32
create mode 100644 target/riscv/th_csr.c
10
33
34
diff --git a/MAINTAINERS b/MAINTAINERS
35
index XXXXXXX..XXXXXXX 100644
36
--- a/MAINTAINERS
37
+++ b/MAINTAINERS
38
@@ -XXX,XX +XXX,XX @@ L: qemu-riscv@nongnu.org
39
S: Supported
40
F: target/riscv/insn_trans/trans_xthead.c.inc
41
F: target/riscv/xthead*.decode
42
+F: target/riscv/th_*
43
F: disas/riscv-xthead*
44
45
RISC-V XVentanaCondOps extension
46
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
47
index XXXXXXX..XXXXXXX 100644
48
--- a/target/riscv/cpu.h
49
+++ b/target/riscv/cpu.h
50
@@ -XXX,XX +XXX,XX @@ target_ulong riscv_new_csr_seed(target_ulong new_value,
51
uint8_t satp_mode_max_from_map(uint32_t map);
52
const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit);
53
54
+/* Implemented in th_csr.c */
55
+void th_register_custom_csrs(RISCVCPU *cpu);
56
+
57
#endif /* RISCV_CPU_H */
11
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
58
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
12
index XXXXXXX..XXXXXXX 100644
59
index XXXXXXX..XXXXXXX 100644
13
--- a/target/riscv/cpu.c
60
--- a/target/riscv/cpu.c
14
+++ b/target/riscv/cpu.c
61
+++ b/target/riscv/cpu.c
15
@@ -XXX,XX +XXX,XX @@ static void riscv_any_cpu_init(Object *obj)
62
@@ -XXX,XX +XXX,XX @@ static void rv64_thead_c906_cpu_init(Object *obj)
16
set_priv_version(env, PRIV_VERSION_1_11_0);
63
cpu->cfg.mvendorid = THEAD_VENDOR_ID;
17
}
64
#ifndef CONFIG_USER_ONLY
18
65
set_satp_mode_max_supported(cpu, VM_1_10_SV39);
19
-static void riscv_base_cpu_init(Object *obj)
66
+ th_register_custom_csrs(cpu);
20
+#if defined(TARGET_RISCV64)
67
#endif
21
+static void rv64_base_cpu_init(Object *obj)
68
22
{
69
/* inherited from parent obj via riscv_cpu_init() */
23
CPURISCVState *env = &RISCV_CPU(obj)->env;
70
diff --git a/target/riscv/th_csr.c b/target/riscv/th_csr.c
24
/* We set this in the realise function */
71
new file mode 100644
25
- set_misa(env, 0);
72
index XXXXXXX..XXXXXXX
26
+ set_misa(env, RV64);
73
--- /dev/null
27
}
74
+++ b/target/riscv/th_csr.c
28
75
@@ -XXX,XX +XXX,XX @@
29
-#ifdef TARGET_RISCV64
76
+/*
30
static void rv64_sifive_u_cpu_init(Object *obj)
77
+ * T-Head-specific CSRs.
31
{
78
+ *
32
CPURISCVState *env = &RISCV_CPU(obj)->env;
79
+ * Copyright (c) 2024 VRULL GmbH
33
@@ -XXX,XX +XXX,XX @@ static void rv64_sifive_e_cpu_init(Object *obj)
80
+ *
34
qdev_prop_set_bit(DEVICE(obj), "mmu", false);
81
+ * This program is free software; you can redistribute it and/or modify it
35
}
82
+ * under the terms and conditions of the GNU General Public License,
36
#else
83
+ * version 2 or later, as published by the Free Software Foundation.
37
+static void rv32_base_cpu_init(Object *obj)
84
+ *
85
+ * This program is distributed in the hope it will be useful, but WITHOUT
86
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
87
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
88
+ * more details.
89
+ *
90
+ * You should have received a copy of the GNU General Public License along with
91
+ * this program. If not, see <http://www.gnu.org/licenses/>.
92
+ */
93
+
94
+#include "qemu/osdep.h"
95
+#include "cpu.h"
96
+#include "cpu_vendorid.h"
97
+
98
+#define CSR_TH_SXSTATUS 0x5c0
99
+
100
+/* TH_SXSTATUS bits */
101
+#define TH_SXSTATUS_UCME BIT(16)
102
+#define TH_SXSTATUS_MAEE BIT(21)
103
+#define TH_SXSTATUS_THEADISAEE BIT(22)
104
+
105
+typedef struct {
106
+ int csrno;
107
+ int (*insertion_test)(RISCVCPU *cpu);
108
+ riscv_csr_operations csr_ops;
109
+} riscv_csr;
110
+
111
+static RISCVException smode(CPURISCVState *env, int csrno)
38
+{
112
+{
39
+ CPURISCVState *env = &RISCV_CPU(obj)->env;
113
+ if (riscv_has_ext(env, RVS)) {
40
+ /* We set this in the realise function */
114
+ return RISCV_EXCP_NONE;
41
+ set_misa(env, RV32);
115
+ }
116
+
117
+ return RISCV_EXCP_ILLEGAL_INST;
42
+}
118
+}
43
+
119
+
44
static void rv32_sifive_u_cpu_init(Object *obj)
120
+static int test_thead_mvendorid(RISCVCPU *cpu)
45
{
121
+{
46
CPURISCVState *env = &RISCV_CPU(obj)->env;
122
+ if (cpu->cfg.mvendorid != THEAD_VENDOR_ID) {
47
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
123
+ return -1;
48
RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev);
124
+ }
49
int priv_version = PRIV_VERSION_1_11_0;
125
+
50
int vext_version = VEXT_VERSION_0_07_1;
126
+ return 0;
51
- target_ulong target_misa = 0;
127
+}
52
+ target_ulong target_misa = env->misa;
128
+
53
Error *local_err = NULL;
129
+static RISCVException read_th_sxstatus(CPURISCVState *env, int csrno,
54
130
+ target_ulong *val)
55
cpu_exec_realizefn(cs, &local_err);
131
+{
56
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
132
+ /* We don't set MAEE here, because QEMU does not implement MAEE. */
57
133
+ *val = TH_SXSTATUS_UCME | TH_SXSTATUS_THEADISAEE;
58
set_resetvec(env, cpu->cfg.resetvec);
134
+ return RISCV_EXCP_NONE;
59
135
+}
60
- /* If misa isn't set (rv32 and rv64 machines) set it here */
136
+
61
- if (!env->misa) {
137
+static riscv_csr th_csr_list[] = {
62
+ /* If only XLEN is set for misa, then set misa from properties */
138
+ {
63
+ if (env->misa == RV32 || env->misa == RV64) {
139
+ .csrno = CSR_TH_SXSTATUS,
64
/* Do some ISA extension error checking */
140
+ .insertion_test = test_thead_mvendorid,
65
if (cpu->cfg.ext_i && cpu->cfg.ext_e) {
141
+ .csr_ops = { "th.sxstatus", smode, read_th_sxstatus }
66
error_setg(errp,
142
+ }
67
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
143
+};
68
set_vext_version(env, vext_version);
144
+
69
}
145
+void th_register_custom_csrs(RISCVCPU *cpu)
70
146
+{
71
- set_misa(env, RVXLEN | target_misa);
147
+ for (size_t i = 0; i < ARRAY_SIZE(th_csr_list); i++) {
72
+ set_misa(env, target_misa);
148
+ int csrno = th_csr_list[i].csrno;
73
}
149
+ riscv_csr_operations *csr_ops = &th_csr_list[i].csr_ops;
74
150
+ if (!th_csr_list[i].insertion_test(cpu)) {
75
riscv_cpu_register_gdb_regs_for_features(cs);
151
+ riscv_set_csr_ops(csrno, csr_ops);
76
@@ -XXX,XX +XXX,XX @@ static const TypeInfo riscv_cpu_type_infos[] = {
152
+ }
77
},
153
+ }
78
DEFINE_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init),
154
+}
79
#if defined(TARGET_RISCV32)
155
diff --git a/target/riscv/meson.build b/target/riscv/meson.build
80
- DEFINE_CPU(TYPE_RISCV_CPU_BASE32, riscv_base_cpu_init),
156
index XXXXXXX..XXXXXXX 100644
81
+ DEFINE_CPU(TYPE_RISCV_CPU_BASE32, rv32_base_cpu_init),
157
--- a/target/riscv/meson.build
82
DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32_ibex_cpu_init),
158
+++ b/target/riscv/meson.build
83
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32_sifive_e_cpu_init),
159
@@ -XXX,XX +XXX,XX @@ riscv_system_ss.add(files(
84
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32_imafcu_nommu_cpu_init),
160
'monitor.c',
85
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32_sifive_u_cpu_init),
161
'machine.c',
86
#elif defined(TARGET_RISCV64)
162
'pmu.c',
87
- DEFINE_CPU(TYPE_RISCV_CPU_BASE64, riscv_base_cpu_init),
163
+ 'th_csr.c',
88
+ DEFINE_CPU(TYPE_RISCV_CPU_BASE64, rv64_base_cpu_init),
164
'time_helper.c',
89
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64_sifive_e_cpu_init),
165
'riscv-qmp-cmds.c',
90
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64_sifive_u_cpu_init),
166
))
91
#endif
92
--
167
--
93
2.29.2
168
2.45.1
94
169
95
170
diff view generated by jsdifflib
[PULL 12/23] hw/riscv: virt: Remove compile time XLEN checks
[PULL 17/28] target/riscv: rvv: Fix Zvfhmin checking for vfwcvt.f.f.v and vfncvt.f.f.w instructions
1
From: Max Chou <max.chou@sifive.com>
2
3
According v spec 18.4, only the vfwcvt.f.f.v and vfncvt.f.f.w
4
instructions will be affected by Zvfhmin extension.
5
And the vfwcvt.f.f.v and vfncvt.f.f.w instructions only support the
6
conversions of
7
8
* From 1*SEW(16/32) to 2*SEW(32/64)
9
* From 2*SEW(32/64) to 1*SEW(16/32)
10
11
Signed-off-by: Max Chou <max.chou@sifive.com>
12
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
13
Cc: qemu-stable <qemu-stable@nongnu.org>
14
Message-ID: <20240322092600.1198921-2-max.chou@sifive.com>
1
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
15
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2
Reviewed-by: Bin Meng <bin.meng@windriver.com>
3
Tested-by: Bin Meng <bin.meng@windriver.com>
4
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
5
Acked-by: Palmer Dabbelt <palmerdabbelt@google.com>
6
Message-id: d7ca1aca672515e6a4aa0d41716238b055f3f25c.1608142916.git.alistair.francis@wdc.com
7
---
16
---
8
hw/riscv/virt.c | 32 +++++++++++++++++---------------
17
target/riscv/insn_trans/trans_rvv.c.inc | 20 ++++++++++++++++++--
9
1 file changed, 17 insertions(+), 15 deletions(-)
18
1 file changed, 18 insertions(+), 2 deletions(-)
10
19
11
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
20
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
12
index XXXXXXX..XXXXXXX 100644
21
index XXXXXXX..XXXXXXX 100644
13
--- a/hw/riscv/virt.c
22
--- a/target/riscv/insn_trans/trans_rvv.c.inc
14
+++ b/hw/riscv/virt.c
23
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
15
@@ -XXX,XX +XXX,XX @@
24
@@ -XXX,XX +XXX,XX @@ static bool require_rvf(DisasContext *s)
16
#include "hw/pci/pci.h"
25
}
17
#include "hw/pci-host/gpex.h"
18
19
-#if defined(TARGET_RISCV32)
20
-# define BIOS_FILENAME "opensbi-riscv32-generic-fw_dynamic.bin"
21
-#else
22
-# define BIOS_FILENAME "opensbi-riscv64-generic-fw_dynamic.bin"
23
-#endif
24
-
25
static const struct MemmapEntry {
26
hwaddr base;
27
hwaddr size;
28
@@ -XXX,XX +XXX,XX @@ static void create_pcie_irq_map(void *fdt, char *nodename,
29
}
26
}
30
27
31
static void create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap,
28
+static bool require_rvfmin(DisasContext *s)
32
- uint64_t mem_size, const char *cmdline)
29
+{
33
+ uint64_t mem_size, const char *cmdline, bool is_32_bit)
30
+ if (s->mstatus_fs == EXT_STATUS_DISABLED) {
31
+ return false;
32
+ }
33
+
34
+ switch (s->sew) {
35
+ case MO_16:
36
+ return s->cfg_ptr->ext_zvfhmin;
37
+ case MO_32:
38
+ return s->cfg_ptr->ext_zve32f;
39
+ default:
40
+ return false;
41
+ }
42
+}
43
+
44
static bool require_scale_rvf(DisasContext *s)
34
{
45
{
35
void *fdt;
46
if (s->mstatus_fs == EXT_STATUS_DISABLED) {
36
int i, cpu, socket;
47
@@ -XXX,XX +XXX,XX @@ static bool require_scale_rvfmin(DisasContext *s)
37
@@ -XXX,XX +XXX,XX @@ static void create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap,
48
}
38
cpu_name = g_strdup_printf("/cpus/cpu@%d",
49
39
s->soc[socket].hartid_base + cpu);
50
switch (s->sew) {
40
qemu_fdt_add_subnode(fdt, cpu_name);
51
- case MO_8:
41
-#if defined(TARGET_RISCV32)
52
- return s->cfg_ptr->ext_zvfhmin;
42
- qemu_fdt_setprop_string(fdt, cpu_name, "mmu-type", "riscv,sv32");
53
case MO_16:
43
-#else
54
return s->cfg_ptr->ext_zve32f;
44
- qemu_fdt_setprop_string(fdt, cpu_name, "mmu-type", "riscv,sv48");
55
case MO_32:
45
-#endif
56
@@ -XXX,XX +XXX,XX @@ static bool opxfv_widen_check(DisasContext *s, arg_rmr *a)
46
+ if (is_32_bit) {
57
static bool opffv_widen_check(DisasContext *s, arg_rmr *a)
47
+ qemu_fdt_setprop_string(fdt, cpu_name, "mmu-type", "riscv,sv32");
58
{
48
+ } else {
59
return opfv_widen_check(s, a) &&
49
+ qemu_fdt_setprop_string(fdt, cpu_name, "mmu-type", "riscv,sv48");
60
+ require_rvfmin(s) &&
50
+ }
61
require_scale_rvfmin(s) &&
51
name = riscv_isa_string(&s->soc[socket].harts[cpu]);
62
(s->sew != MO_8);
52
qemu_fdt_setprop_string(fdt, cpu_name, "riscv,isa", name);
63
}
53
g_free(name);
64
@@ -XXX,XX +XXX,XX @@ static bool opfxv_narrow_check(DisasContext *s, arg_rmr *a)
54
@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
65
static bool opffv_narrow_check(DisasContext *s, arg_rmr *a)
55
main_mem);
66
{
56
67
return opfv_narrow_check(s, a) &&
57
/* create device tree */
68
+ require_rvfmin(s) &&
58
- create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline);
69
require_scale_rvfmin(s) &&
59
+ create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline,
70
(s->sew != MO_8);
60
+ riscv_is_32_bit(machine));
71
}
61
62
/* boot rom */
63
memory_region_init_rom(mask_rom, NULL, "riscv_virt_board.mrom",
64
@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
65
memory_region_add_subregion(system_memory, memmap[VIRT_MROM].base,
66
mask_rom);
67
68
- firmware_end_addr = riscv_find_and_load_firmware(machine, BIOS_FILENAME,
69
- start_addr, NULL);
70
+ if (riscv_is_32_bit(machine)) {
71
+ firmware_end_addr = riscv_find_and_load_firmware(machine,
72
+ "opensbi-riscv32-generic-fw_dynamic.bin",
73
+ start_addr, NULL);
74
+ } else {
75
+ firmware_end_addr = riscv_find_and_load_firmware(machine,
76
+ "opensbi-riscv64-generic-fw_dynamic.bin",
77
+ start_addr, NULL);
78
+ }
79
80
if (machine->kernel_filename) {
81
kernel_start_addr = riscv_calc_kernel_start_addr(machine,
82
--
72
--
83
2.29.2
73
2.45.1
84
85
diff view generated by jsdifflib
[PULL 13/23] hw/riscv: spike: Remove compile time XLEN checks
[PULL 18/28] target/riscv: rvv: Check single width operator for vector fp widen instructions
1
From: Max Chou <max.chou@sifive.com>
2
3
The require_scale_rvf function only checks the double width operator for
4
the vector floating point widen instructions, so most of the widen
5
checking functions need to add require_rvf for single width operator.
6
7
The vfwcvt.f.x.v and vfwcvt.f.xu.v instructions convert single width
8
integer to double width float, so the opfxv_widen_check function doesn’t
9
need require_rvf for the single width operator(integer).
10
11
Signed-off-by: Max Chou <max.chou@sifive.com>
12
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
13
Cc: qemu-stable <qemu-stable@nongnu.org>
14
Message-ID: <20240322092600.1198921-3-max.chou@sifive.com>
1
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
15
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2
Reviewed-by: Bin Meng <bin.meng@windriver.com>
3
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
4
Acked-by: Palmer Dabbelt <palmerdabbelt@google.com>
5
Message-id: ac75037dd58061486de421a0fcd9ac8a92014607.1608142916.git.alistair.francis@wdc.com
6
---
16
---
7
hw/riscv/spike.c | 45 ++++++++++++++++++++++++---------------------
17
target/riscv/insn_trans/trans_rvv.c.inc | 5 +++++
8
1 file changed, 24 insertions(+), 21 deletions(-)
18
1 file changed, 5 insertions(+)
9
19
10
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
20
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
11
index XXXXXXX..XXXXXXX 100644
21
index XXXXXXX..XXXXXXX 100644
12
--- a/hw/riscv/spike.c
22
--- a/target/riscv/insn_trans/trans_rvv.c.inc
13
+++ b/hw/riscv/spike.c
23
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
14
@@ -XXX,XX +XXX,XX @@
24
@@ -XXX,XX +XXX,XX @@ GEN_OPFVF_TRANS(vfrsub_vf, opfvf_check)
15
#include "sysemu/qtest.h"
25
static bool opfvv_widen_check(DisasContext *s, arg_rmrr *a)
16
#include "sysemu/sysemu.h"
17
18
-/*
19
- * Not like other RISC-V machines that use plain binary bios images,
20
- * keeping ELF files here was intentional because BIN files don't work
21
- * for the Spike machine as HTIF emulation depends on ELF parsing.
22
- */
23
-#if defined(TARGET_RISCV32)
24
-# define BIOS_FILENAME "opensbi-riscv32-generic-fw_dynamic.elf"
25
-#else
26
-# define BIOS_FILENAME "opensbi-riscv64-generic-fw_dynamic.elf"
27
-#endif
28
-
29
static const struct MemmapEntry {
30
hwaddr base;
31
hwaddr size;
32
@@ -XXX,XX +XXX,XX @@ static const struct MemmapEntry {
33
};
34
35
static void create_fdt(SpikeState *s, const struct MemmapEntry *memmap,
36
- uint64_t mem_size, const char *cmdline)
37
+ uint64_t mem_size, const char *cmdline, bool is_32_bit)
38
{
26
{
39
void *fdt;
27
return require_rvv(s) &&
40
uint64_t addr, size;
28
+ require_rvf(s) &&
41
@@ -XXX,XX +XXX,XX @@ static void create_fdt(SpikeState *s, const struct MemmapEntry *memmap,
29
require_scale_rvf(s) &&
42
cpu_name = g_strdup_printf("/cpus/cpu@%d",
30
(s->sew != MO_8) &&
43
s->soc[socket].hartid_base + cpu);
31
vext_check_isa_ill(s) &&
44
qemu_fdt_add_subnode(fdt, cpu_name);
32
@@ -XXX,XX +XXX,XX @@ GEN_OPFVV_WIDEN_TRANS(vfwsub_vv, opfvv_widen_check)
45
-#if defined(TARGET_RISCV32)
33
static bool opfvf_widen_check(DisasContext *s, arg_rmrr *a)
46
- qemu_fdt_setprop_string(fdt, cpu_name, "mmu-type", "riscv,sv32");
34
{
47
-#else
35
return require_rvv(s) &&
48
- qemu_fdt_setprop_string(fdt, cpu_name, "mmu-type", "riscv,sv48");
36
+ require_rvf(s) &&
49
-#endif
37
require_scale_rvf(s) &&
50
+ if (is_32_bit) {
38
(s->sew != MO_8) &&
51
+ qemu_fdt_setprop_string(fdt, cpu_name, "mmu-type", "riscv,sv32");
39
vext_check_isa_ill(s) &&
52
+ } else {
40
@@ -XXX,XX +XXX,XX @@ GEN_OPFVF_WIDEN_TRANS(vfwsub_vf)
53
+ qemu_fdt_setprop_string(fdt, cpu_name, "mmu-type", "riscv,sv48");
41
static bool opfwv_widen_check(DisasContext *s, arg_rmrr *a)
54
+ }
42
{
55
name = riscv_isa_string(&s->soc[socket].harts[cpu]);
43
return require_rvv(s) &&
56
qemu_fdt_setprop_string(fdt, cpu_name, "riscv,isa", name);
44
+ require_rvf(s) &&
57
g_free(name);
45
require_scale_rvf(s) &&
58
@@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine)
46
(s->sew != MO_8) &&
59
main_mem);
47
vext_check_isa_ill(s) &&
60
48
@@ -XXX,XX +XXX,XX @@ GEN_OPFWV_WIDEN_TRANS(vfwsub_wv)
61
/* create device tree */
49
static bool opfwf_widen_check(DisasContext *s, arg_rmrr *a)
62
- create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline);
50
{
63
+ create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline,
51
return require_rvv(s) &&
64
+ riscv_is_32_bit(machine));
52
+ require_rvf(s) &&
65
53
require_scale_rvf(s) &&
66
/* boot rom */
54
(s->sew != MO_8) &&
67
memory_region_init_rom(mask_rom, NULL, "riscv.spike.mrom",
55
vext_check_isa_ill(s) &&
68
@@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine)
56
@@ -XXX,XX +XXX,XX @@ GEN_OPFVV_TRANS(vfredmin_vs, freduction_check)
69
memory_region_add_subregion(system_memory, memmap[SPIKE_MROM].base,
57
static bool freduction_widen_check(DisasContext *s, arg_rmrr *a)
70
mask_rom);
58
{
71
59
return reduction_widen_check(s, a) &&
72
- firmware_end_addr = riscv_find_and_load_firmware(machine, BIOS_FILENAME,
60
+ require_rvf(s) &&
73
- memmap[SPIKE_DRAM].base,
61
require_scale_rvf(s) &&
74
- htif_symbol_callback);
62
(s->sew != MO_8);
75
+ /*
63
}
76
+ * Not like other RISC-V machines that use plain binary bios images,
77
+ * keeping ELF files here was intentional because BIN files don't work
78
+ * for the Spike machine as HTIF emulation depends on ELF parsing.
79
+ */
80
+ if (riscv_is_32_bit(machine)) {
81
+ firmware_end_addr = riscv_find_and_load_firmware(machine,
82
+ "opensbi-riscv32-generic-fw_dynamic.elf",
83
+ memmap[SPIKE_DRAM].base,
84
+ htif_symbol_callback);
85
+ } else {
86
+ firmware_end_addr = riscv_find_and_load_firmware(machine,
87
+ "opensbi-riscv64-generic-fw_dynamic.elf",
88
+ memmap[SPIKE_DRAM].base,
89
+ htif_symbol_callback);
90
+ }
91
92
if (machine->kernel_filename) {
93
kernel_start_addr = riscv_calc_kernel_start_addr(machine,
94
--
64
--
95
2.29.2
65
2.45.1
96
66
97
67
diff view generated by jsdifflib
New patch
[PULL 19/28] target/riscv: rvv: Check single width operator for vfncvt.rod.f.f.w
1
From: Max Chou <max.chou@sifive.com>
1
2
3
The opfv_narrow_check needs to check the single width float operator by
4
require_rvf.
5
6
Signed-off-by: Max Chou <max.chou@sifive.com>
7
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
8
Cc: qemu-stable <qemu-stable@nongnu.org>
9
Message-ID: <20240322092600.1198921-4-max.chou@sifive.com>
10
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
11
---
12
target/riscv/insn_trans/trans_rvv.c.inc | 1 +
13
1 file changed, 1 insertion(+)
14
15
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
16
index XXXXXXX..XXXXXXX 100644
17
--- a/target/riscv/insn_trans/trans_rvv.c.inc
18
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
19
@@ -XXX,XX +XXX,XX @@ static bool opffv_narrow_check(DisasContext *s, arg_rmr *a)
20
static bool opffv_rod_narrow_check(DisasContext *s, arg_rmr *a)
21
{
22
return opfv_narrow_check(s, a) &&
23
+ require_rvf(s) &&
24
require_scale_rvf(s) &&
25
(s->sew != MO_8);
26
}
27
--
28
2.45.1
diff view generated by jsdifflib
[PULL 11/23] hw/riscv: boot: Remove compile time XLEN checks
[PULL 20/28] target/riscv: rvv: Remove redudant SEW checking for vector fp narrow/widen instructions
1
From: Max Chou <max.chou@sifive.com>
2
3
If the checking functions check both the single and double width
4
operators at the same time, then the single width operator checking
5
functions (require_rvf[min]) will check whether the SEW is 8.
6
7
Signed-off-by: Max Chou <max.chou@sifive.com>
8
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
9
Cc: qemu-stable <qemu-stable@nongnu.org>
10
Message-ID: <20240322092600.1198921-5-max.chou@sifive.com>
1
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
11
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2
Reviewed-by: Bin Meng <bin.meng@windriver.com>
3
Tested-by: Bin Meng <bin.meng@windriver.com>
4
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
5
Acked-by: Palmer Dabbelt <palmerdabbelt@google.com>
6
Message-id: 51e9842dbed1acceebad7f97bd3aae69aa1ac19e.1608142916.git.alistair.francis@wdc.com
7
---
12
---
8
include/hw/riscv/boot.h | 8 +++---
13
target/riscv/insn_trans/trans_rvv.c.inc | 16 ++++------------
9
hw/riscv/boot.c | 55 ++++++++++++++++++++++-------------------
14
1 file changed, 4 insertions(+), 12 deletions(-)
10
hw/riscv/sifive_u.c | 2 +-
11
hw/riscv/spike.c | 3 ++-
12
hw/riscv/virt.c | 2 +-
13
5 files changed, 39 insertions(+), 31 deletions(-)
14
15
15
diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h
16
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
16
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
17
--- a/include/hw/riscv/boot.h
18
--- a/target/riscv/insn_trans/trans_rvv.c.inc
18
+++ b/include/hw/riscv/boot.h
19
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
19
@@ -XXX,XX +XXX,XX @@ target_ulong riscv_load_kernel(const char *kernel_filename,
20
@@ -XXX,XX +XXX,XX @@ static bool opfvv_widen_check(DisasContext *s, arg_rmrr *a)
20
hwaddr riscv_load_initrd(const char *filename, uint64_t mem_size,
21
return require_rvv(s) &&
21
uint64_t kernel_entry, hwaddr *start);
22
require_rvf(s) &&
22
uint32_t riscv_load_fdt(hwaddr dram_start, uint64_t dram_size, void *fdt);
23
require_scale_rvf(s) &&
23
-void riscv_setup_rom_reset_vec(hwaddr saddr, hwaddr rom_base,
24
- (s->sew != MO_8) &&
24
- hwaddr rom_size, uint64_t kernel_entry,
25
vext_check_isa_ill(s) &&
25
+void riscv_setup_rom_reset_vec(MachineState *machine, hwaddr saddr,
26
vext_check_dss(s, a->rd, a->rs1, a->rs2, a->vm);
26
+ hwaddr rom_base, hwaddr rom_size,
27
}
27
+ uint64_t kernel_entry,
28
@@ -XXX,XX +XXX,XX @@ static bool opfvf_widen_check(DisasContext *s, arg_rmrr *a)
28
uint32_t fdt_load_addr, void *fdt);
29
return require_rvv(s) &&
29
-void riscv_rom_copy_firmware_info(hwaddr rom_base, hwaddr rom_size,
30
require_rvf(s) &&
30
+void riscv_rom_copy_firmware_info(MachineState *machine, hwaddr rom_base,
31
require_scale_rvf(s) &&
31
+ hwaddr rom_size,
32
- (s->sew != MO_8) &&
32
uint32_t reset_vec_size,
33
vext_check_isa_ill(s) &&
33
uint64_t kernel_entry);
34
vext_check_ds(s, a->rd, a->rs2, a->vm);
34
35
}
35
diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
36
@@ -XXX,XX +XXX,XX @@ static bool opfwv_widen_check(DisasContext *s, arg_rmrr *a)
36
index XXXXXXX..XXXXXXX 100644
37
return require_rvv(s) &&
37
--- a/hw/riscv/boot.c
38
require_rvf(s) &&
38
+++ b/hw/riscv/boot.c
39
require_scale_rvf(s) &&
39
@@ -XXX,XX +XXX,XX @@
40
- (s->sew != MO_8) &&
40
41
vext_check_isa_ill(s) &&
41
#include <libfdt.h>
42
vext_check_dds(s, a->rd, a->rs1, a->rs2, a->vm);
42
43
}
43
-#if defined(TARGET_RISCV32)
44
@@ -XXX,XX +XXX,XX @@ static bool opfwf_widen_check(DisasContext *s, arg_rmrr *a)
44
-#define fw_dynamic_info_data(__val) cpu_to_le32(__val)
45
return require_rvv(s) &&
45
-#else
46
require_rvf(s) &&
46
-#define fw_dynamic_info_data(__val) cpu_to_le64(__val)
47
require_scale_rvf(s) &&
47
-#endif
48
- (s->sew != MO_8) &&
48
-
49
vext_check_isa_ill(s) &&
49
bool riscv_is_32_bit(MachineState *machine)
50
vext_check_dd(s, a->rd, a->rs2, a->vm);
51
}
52
@@ -XXX,XX +XXX,XX @@ static bool opffv_widen_check(DisasContext *s, arg_rmr *a)
50
{
53
{
51
/*
54
return opfv_widen_check(s, a) &&
52
@@ -XXX,XX +XXX,XX @@ uint32_t riscv_load_fdt(hwaddr dram_base, uint64_t mem_size, void *fdt)
55
require_rvfmin(s) &&
53
return fdt_addr;
56
- require_scale_rvfmin(s) &&
57
- (s->sew != MO_8);
58
+ require_scale_rvfmin(s);
54
}
59
}
55
60
56
-void riscv_rom_copy_firmware_info(hwaddr rom_base, hwaddr rom_size,
61
#define GEN_OPFV_WIDEN_TRANS(NAME, CHECK, HELPER, FRM) \
57
- uint32_t reset_vec_size, uint64_t kernel_entry)
62
@@ -XXX,XX +XXX,XX @@ static bool opffv_narrow_check(DisasContext *s, arg_rmr *a)
58
+void riscv_rom_copy_firmware_info(MachineState *machine, hwaddr rom_base,
59
+ hwaddr rom_size, uint32_t reset_vec_size,
60
+ uint64_t kernel_entry)
61
{
63
{
62
struct fw_dynamic_info dinfo;
64
return opfv_narrow_check(s, a) &&
63
size_t dinfo_len;
65
require_rvfmin(s) &&
64
66
- require_scale_rvfmin(s) &&
65
- dinfo.magic = fw_dynamic_info_data(FW_DYNAMIC_INFO_MAGIC_VALUE);
67
- (s->sew != MO_8);
66
- dinfo.version = fw_dynamic_info_data(FW_DYNAMIC_INFO_VERSION);
68
+ require_scale_rvfmin(s);
67
- dinfo.next_mode = fw_dynamic_info_data(FW_DYNAMIC_INFO_NEXT_MODE_S);
68
- dinfo.next_addr = fw_dynamic_info_data(kernel_entry);
69
+ if (sizeof(dinfo.magic) == 4) {
70
+ dinfo.magic = cpu_to_le32(FW_DYNAMIC_INFO_MAGIC_VALUE);
71
+ dinfo.version = cpu_to_le32(FW_DYNAMIC_INFO_VERSION);
72
+ dinfo.next_mode = cpu_to_le32(FW_DYNAMIC_INFO_NEXT_MODE_S);
73
+ dinfo.next_addr = cpu_to_le32(kernel_entry);
74
+ } else {
75
+ dinfo.magic = cpu_to_le64(FW_DYNAMIC_INFO_MAGIC_VALUE);
76
+ dinfo.version = cpu_to_le64(FW_DYNAMIC_INFO_VERSION);
77
+ dinfo.next_mode = cpu_to_le64(FW_DYNAMIC_INFO_NEXT_MODE_S);
78
+ dinfo.next_addr = cpu_to_le64(kernel_entry);
79
+ }
80
dinfo.options = 0;
81
dinfo.boot_hart = 0;
82
dinfo_len = sizeof(dinfo);
83
@@ -XXX,XX +XXX,XX @@ void riscv_rom_copy_firmware_info(hwaddr rom_base, hwaddr rom_size,
84
&address_space_memory);
85
}
69
}
86
70
87
-void riscv_setup_rom_reset_vec(hwaddr start_addr, hwaddr rom_base,
71
static bool opffv_rod_narrow_check(DisasContext *s, arg_rmr *a)
88
- hwaddr rom_size, uint64_t kernel_entry,
89
+void riscv_setup_rom_reset_vec(MachineState *machine, hwaddr start_addr,
90
+ hwaddr rom_base, hwaddr rom_size,
91
+ uint64_t kernel_entry,
92
uint32_t fdt_load_addr, void *fdt)
93
{
72
{
94
int i;
73
return opfv_narrow_check(s, a) &&
95
uint32_t start_addr_hi32 = 0x00000000;
74
require_rvf(s) &&
96
75
- require_scale_rvf(s) &&
97
- #if defined(TARGET_RISCV64)
76
- (s->sew != MO_8);
98
- start_addr_hi32 = start_addr >> 32;
77
+ require_scale_rvf(s);
99
- #endif
100
+ if (!riscv_is_32_bit(machine)) {
101
+ start_addr_hi32 = start_addr >> 32;
102
+ }
103
/* reset vector */
104
uint32_t reset_vec[10] = {
105
0x00000297, /* 1: auipc t0, %pcrel_hi(fw_dyn) */
106
0x02828613, /* addi a2, t0, %pcrel_lo(1b) */
107
0xf1402573, /* csrr a0, mhartid */
108
-#if defined(TARGET_RISCV32)
109
- 0x0202a583, /* lw a1, 32(t0) */
110
- 0x0182a283, /* lw t0, 24(t0) */
111
-#elif defined(TARGET_RISCV64)
112
- 0x0202b583, /* ld a1, 32(t0) */
113
- 0x0182b283, /* ld t0, 24(t0) */
114
-#endif
115
+ 0,
116
+ 0,
117
0x00028067, /* jr t0 */
118
start_addr, /* start: .dword */
119
start_addr_hi32,
120
@@ -XXX,XX +XXX,XX @@ void riscv_setup_rom_reset_vec(hwaddr start_addr, hwaddr rom_base,
121
0x00000000,
122
/* fw_dyn: */
123
};
124
+ if (riscv_is_32_bit(machine)) {
125
+ reset_vec[3] = 0x0202a583; /* lw a1, 32(t0) */
126
+ reset_vec[4] = 0x0182a283; /* lw t0, 24(t0) */
127
+ } else {
128
+ reset_vec[3] = 0x0202b583; /* ld a1, 32(t0) */
129
+ reset_vec[4] = 0x0182b283; /* ld t0, 24(t0) */
130
+ }
131
132
/* copy in the reset vector in little_endian byte order */
133
for (i = 0; i < ARRAY_SIZE(reset_vec); i++) {
134
@@ -XXX,XX +XXX,XX @@ void riscv_setup_rom_reset_vec(hwaddr start_addr, hwaddr rom_base,
135
}
136
rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
137
rom_base, &address_space_memory);
138
- riscv_rom_copy_firmware_info(rom_base, rom_size, sizeof(reset_vec),
139
+ riscv_rom_copy_firmware_info(machine, rom_base, rom_size, sizeof(reset_vec),
140
kernel_entry);
141
142
return;
143
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
144
index XXXXXXX..XXXXXXX 100644
145
--- a/hw/riscv/sifive_u.c
146
+++ b/hw/riscv/sifive_u.c
147
@@ -XXX,XX +XXX,XX @@ static void sifive_u_machine_init(MachineState *machine)
148
rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
149
memmap[SIFIVE_U_DEV_MROM].base, &address_space_memory);
150
151
- riscv_rom_copy_firmware_info(memmap[SIFIVE_U_DEV_MROM].base,
152
+ riscv_rom_copy_firmware_info(machine, memmap[SIFIVE_U_DEV_MROM].base,
153
memmap[SIFIVE_U_DEV_MROM].size,
154
sizeof(reset_vec), kernel_entry);
155
}
78
}
156
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
79
157
index XXXXXXX..XXXXXXX 100644
80
#define GEN_OPFV_NARROW_TRANS(NAME, CHECK, HELPER, FRM) \
158
--- a/hw/riscv/spike.c
81
@@ -XXX,XX +XXX,XX @@ static bool freduction_widen_check(DisasContext *s, arg_rmrr *a)
159
+++ b/hw/riscv/spike.c
82
{
160
@@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine)
83
return reduction_widen_check(s, a) &&
161
fdt_load_addr = riscv_load_fdt(memmap[SPIKE_DRAM].base,
84
require_rvf(s) &&
162
machine->ram_size, s->fdt);
85
- require_scale_rvf(s) &&
163
/* load the reset vector */
86
- (s->sew != MO_8);
164
- riscv_setup_rom_reset_vec(memmap[SPIKE_DRAM].base, memmap[SPIKE_MROM].base,
87
+ require_scale_rvf(s);
165
+ riscv_setup_rom_reset_vec(machine, memmap[SPIKE_DRAM].base,
88
}
166
+ memmap[SPIKE_MROM].base,
89
167
memmap[SPIKE_MROM].size, kernel_entry,
90
GEN_OPFVV_WIDEN_TRANS(vfwredusum_vs, freduction_widen_check)
168
fdt_load_addr, s->fdt);
169
170
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
171
index XXXXXXX..XXXXXXX 100644
172
--- a/hw/riscv/virt.c
173
+++ b/hw/riscv/virt.c
174
@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
175
fdt_load_addr = riscv_load_fdt(memmap[VIRT_DRAM].base,
176
machine->ram_size, s->fdt);
177
/* load the reset vector */
178
- riscv_setup_rom_reset_vec(start_addr, virt_memmap[VIRT_MROM].base,
179
+ riscv_setup_rom_reset_vec(machine, start_addr, virt_memmap[VIRT_MROM].base,
180
virt_memmap[VIRT_MROM].size, kernel_entry,
181
fdt_load_addr, s->fdt);
182
183
--
91
--
184
2.29.2
92
2.45.1
185
186
diff view generated by jsdifflib
[PULL 19/23] target/riscv: cpu_helper: Remove compile time XLEN checks
[PULL 21/28] target/riscv: prioritize pmp errors in raise_mmu_exception()
1
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
2
3
raise_mmu_exception(), as is today, is prioritizing guest page faults by
4
checking first if virt_enabled && !first_stage, and then considering the
5
regular inst/load/store faults.
6
7
There's no mention in the spec about guest page fault being a higher
8
priority that PMP faults. In fact, privileged spec section 3.7.1 says:
9
10
"Attempting to fetch an instruction from a PMP region that does not have
11
execute permissions raises an instruction access-fault exception.
12
Attempting to execute a load or load-reserved instruction which accesses
13
a physical address within a PMP region without read permissions raises a
14
load access-fault exception. Attempting to execute a store,
15
store-conditional, or AMO instruction which accesses a physical address
16
within a PMP region without write permissions raises a store
17
access-fault exception."
18
19
So, in fact, we're doing it wrong - PMP faults should always be thrown,
20
regardless of also being a first or second stage fault.
21
22
The way riscv_cpu_tlb_fill() and get_physical_address() work is
23
adequate: a TRANSLATE_PMP_FAIL error is immediately reported and
24
reflected in the 'pmp_violation' flag. What we need is to change
25
raise_mmu_exception() to prioritize it.
26
27
Reported-by: Joseph Chan <jchan@ventanamicro.com>
28
Fixes: 82d53adfbb ("target/riscv/cpu_helper.c: Invalid exception on MMU translation stage")
29
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
30
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
31
Message-ID: <20240413105929.7030-1-alexei.filippov@syntacore.com>
32
Cc: qemu-stable <qemu-stable@nongnu.org>
1
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
33
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
3
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
4
Acked-by: Palmer Dabbelt <palmerdabbelt@google.com>
5
Reviewed-by: Bin Meng <bin.meng@windriver.com>
6
Tested-by: Bin Meng <bin.meng@windriver.com>
7
Message-id: 872d2dfcd1c7c3914655d677e911b9432eb8f340.1608142916.git.alistair.francis@wdc.com
8
---
34
---
9
target/riscv/cpu_helper.c | 12 +++++++-----
35
target/riscv/cpu_helper.c | 22 ++++++++++++----------
10
1 file changed, 7 insertions(+), 5 deletions(-)
36
1 file changed, 12 insertions(+), 10 deletions(-)
11
37
12
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
38
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
13
index XXXXXXX..XXXXXXX 100644
39
index XXXXXXX..XXXXXXX 100644
14
--- a/target/riscv/cpu_helper.c
40
--- a/target/riscv/cpu_helper.c
15
+++ b/target/riscv/cpu_helper.c
41
+++ b/target/riscv/cpu_helper.c
16
@@ -XXX,XX +XXX,XX @@ restart:
42
@@ -XXX,XX +XXX,XX @@ static void raise_mmu_exception(CPURISCVState *env, target_ulong address,
17
return TRANSLATE_PMP_FAIL;
43
44
switch (access_type) {
45
case MMU_INST_FETCH:
46
- if (env->virt_enabled && !first_stage) {
47
+ if (pmp_violation) {
48
+ cs->exception_index = RISCV_EXCP_INST_ACCESS_FAULT;
49
+ } else if (env->virt_enabled && !first_stage) {
50
cs->exception_index = RISCV_EXCP_INST_GUEST_PAGE_FAULT;
51
} else {
52
- cs->exception_index = pmp_violation ?
53
- RISCV_EXCP_INST_ACCESS_FAULT : RISCV_EXCP_INST_PAGE_FAULT;
54
+ cs->exception_index = RISCV_EXCP_INST_PAGE_FAULT;
18
}
55
}
19
56
break;
20
-#if defined(TARGET_RISCV32)
57
case MMU_DATA_LOAD:
21
- target_ulong pte = address_space_ldl(cs->as, pte_addr, attrs, &res);
58
- if (two_stage && !first_stage) {
22
-#elif defined(TARGET_RISCV64)
59
+ if (pmp_violation) {
23
- target_ulong pte = address_space_ldq(cs->as, pte_addr, attrs, &res);
60
+ cs->exception_index = RISCV_EXCP_LOAD_ACCESS_FAULT;
24
-#endif
61
+ } else if (two_stage && !first_stage) {
25
+ target_ulong pte;
62
cs->exception_index = RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT;
26
+ if (riscv_cpu_is_32bit(env)) {
63
} else {
27
+ pte = address_space_ldl(cs->as, pte_addr, attrs, &res);
64
- cs->exception_index = pmp_violation ?
28
+ } else {
65
- RISCV_EXCP_LOAD_ACCESS_FAULT : RISCV_EXCP_LOAD_PAGE_FAULT;
29
+ pte = address_space_ldq(cs->as, pte_addr, attrs, &res);
66
+ cs->exception_index = RISCV_EXCP_LOAD_PAGE_FAULT;
30
+ }
31
+
32
if (res != MEMTX_OK) {
33
return TRANSLATE_FAIL;
34
}
67
}
68
break;
69
case MMU_DATA_STORE:
70
- if (two_stage && !first_stage) {
71
+ if (pmp_violation) {
72
+ cs->exception_index = RISCV_EXCP_STORE_AMO_ACCESS_FAULT;
73
+ } else if (two_stage && !first_stage) {
74
cs->exception_index = RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT;
75
} else {
76
- cs->exception_index = pmp_violation ?
77
- RISCV_EXCP_STORE_AMO_ACCESS_FAULT :
78
- RISCV_EXCP_STORE_PAGE_FAULT;
79
+ cs->exception_index = RISCV_EXCP_STORE_PAGE_FAULT;
80
}
81
break;
82
default:
35
--
83
--
36
2.29.2
84
2.45.1
37
38
diff view generated by jsdifflib
[PULL 04/23] target/riscv: Fix the bug of HLVX/HLV/HSV
[PULL 22/28] target/riscv: do not set mtval2 for non guest-page faults
1
From: Yifei Jiang <jiangyifei@huawei.com>
1
From: Alexei Filippov <alexei.filippov@syntacore.com>
2
2
3
We found that the hypervisor virtual-machine load and store instructions,
3
Previous patch fixed the PMP priority in raise_mmu_exception() but we're still
4
included HLVX/HLV/HSV, couldn't access guest userspace memory.
4
setting mtval2 incorrectly. In riscv_cpu_tlb_fill(), after pmp check in 2 stage
5
translation part, mtval2 will be set in case of successes 2 stage translation but
6
failed pmp check.
5
7
6
In the riscv-privileged spec, HLVX/HLV/HSV is defined as follow:
8
In this case we gonna set mtval2 via env->guest_phys_fault_addr in context of
7
"As usual when V=1, two-stage address translation is applied, and
9
riscv_cpu_tlb_fill(), as this was a guest-page-fault, but it didn't and mtval2
8
the HS-level sstatus.SUM is ignored."
10
should be zero, according to RISCV privileged spec sect. 9.4.4: When a guest
11
page-fault is taken into M-mode, mtval2 is written with either zero or guest
12
physical address that faulted, shifted by 2 bits. *For other traps, mtval2
13
is set to zero...*
9
14
10
But get_physical_address() doesn't ignore sstatus.SUM, when HLVX/HLV/HSV
15
Signed-off-by: Alexei Filippov <alexei.filippov@syntacore.com>
11
accesses guest userspace memory. So this patch fixes it.
16
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
12
13
Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
14
Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com>
15
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
17
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
16
Message-id: 20201130012810.899-1-jiangyifei@huawei.com
18
Message-ID: <20240503103052.6819-1-alexei.filippov@syntacore.com>
19
Cc: qemu-stable <qemu-stable@nongnu.org>
17
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
20
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
18
---
21
---
19
target/riscv/cpu_helper.c | 3 ++-
22
target/riscv/cpu_helper.c | 12 ++++++------
20
1 file changed, 2 insertions(+), 1 deletion(-)
23
1 file changed, 6 insertions(+), 6 deletions(-)
21
24
22
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
25
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
23
index XXXXXXX..XXXXXXX 100644
26
index XXXXXXX..XXXXXXX 100644
24
--- a/target/riscv/cpu_helper.c
27
--- a/target/riscv/cpu_helper.c
25
+++ b/target/riscv/cpu_helper.c
28
+++ b/target/riscv/cpu_helper.c
26
@@ -XXX,XX +XXX,XX @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
29
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
27
vm = get_field(env->hgatp, HGATP_MODE);
30
__func__, pa, ret, prot_pmp, tlb_size);
28
widened = 2;
31
29
}
32
prot &= prot_pmp;
30
- sum = get_field(env->mstatus, MSTATUS_SUM);
33
- }
31
+ /* status.SUM will be ignored if execute on background */
34
-
32
+ sum = get_field(env->mstatus, MSTATUS_SUM) || use_background;
35
- if (ret != TRANSLATE_SUCCESS) {
33
switch (vm) {
36
+ } else {
34
case VM_1_10_SV32:
37
/*
35
levels = 2; ptidxbits = 10; ptesize = 4; break;
38
* Guest physical address translation failed, this is a HS
39
* level exception
40
*/
41
first_stage_error = false;
42
- env->guest_phys_fault_addr = (im_address |
43
- (address &
44
- (TARGET_PAGE_SIZE - 1))) >> 2;
45
+ if (ret != TRANSLATE_PMP_FAIL) {
46
+ env->guest_phys_fault_addr = (im_address |
47
+ (address &
48
+ (TARGET_PAGE_SIZE - 1))) >> 2;
49
+ }
50
}
51
}
52
} else {
36
--
53
--
37
2.29.2
54
2.45.1
38
39
diff view generated by jsdifflib
[PULL 17/23] target/riscv: Specify the XLEN for CPUs
[PULL 23/28] target/riscv: Remove experimental prefix from "B" extension
1
From: Rob Bradford <rbradford@rivosinc.com>
2
3
This extension has now been ratified:
4
https://jira.riscv.org/browse/RVS-2006 so the "x-" prefix can be
5
removed.
6
7
Since this is now a ratified extension add it to the list of extensions
8
included in the "max" CPU variant.
9
10
Signed-off-by: Rob Bradford <rbradford@rivosinc.com>
11
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
12
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
13
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
14
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
15
Message-ID: <20240514110217.22516-1-rbradford@rivosinc.com>
1
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
16
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2
Reviewed-by: Bin Meng <bin.meng@windriver.com>
3
Tested-by: Bin Meng <bin.meng@windriver.com>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
6
Acked-by: Palmer Dabbelt <palmerdabbelt@google.com>
7
Message-id: c1da66affbb83ec4a2fbeb0194293bd24d65f5dc.1608142916.git.alistair.francis@wdc.com
8
---
17
---
9
target/riscv/cpu.c | 33 +++++++++++++++++++++++----------
18
target/riscv/cpu.c | 2 +-
10
1 file changed, 23 insertions(+), 10 deletions(-)
19
target/riscv/tcg/tcg-cpu.c | 2 +-
20
2 files changed, 2 insertions(+), 2 deletions(-)
11
21
12
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
22
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
13
index XXXXXXX..XXXXXXX 100644
23
index XXXXXXX..XXXXXXX 100644
14
--- a/target/riscv/cpu.c
24
--- a/target/riscv/cpu.c
15
+++ b/target/riscv/cpu.c
25
+++ b/target/riscv/cpu.c
16
@@ -XXX,XX +XXX,XX @@ static void riscv_base_cpu_init(Object *obj)
26
@@ -XXX,XX +XXX,XX @@ static const MISAExtInfo misa_ext_info_arr[] = {
17
set_misa(env, 0);
27
MISA_EXT_INFO(RVJ, "x-j", "Dynamic translated languages"),
18
}
28
MISA_EXT_INFO(RVV, "v", "Vector operations"),
19
29
MISA_EXT_INFO(RVG, "g", "General purpose (IMAFD_Zicsr_Zifencei)"),
20
-static void rvxx_sifive_u_cpu_init(Object *obj)
30
- MISA_EXT_INFO(RVB, "x-b", "Bit manipulation (Zba_Zbb_Zbs)")
21
+#ifdef TARGET_RISCV64
31
+ MISA_EXT_INFO(RVB, "b", "Bit manipulation (Zba_Zbb_Zbs)")
22
+static void rv64_sifive_u_cpu_init(Object *obj)
23
{
24
CPURISCVState *env = &RISCV_CPU(obj)->env;
25
- set_misa(env, RVXLEN | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
26
+ set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
27
set_priv_version(env, PRIV_VERSION_1_10_0);
28
}
29
30
-static void rvxx_sifive_e_cpu_init(Object *obj)
31
+static void rv64_sifive_e_cpu_init(Object *obj)
32
{
33
CPURISCVState *env = &RISCV_CPU(obj)->env;
34
- set_misa(env, RVXLEN | RVI | RVM | RVA | RVC | RVU);
35
+ set_misa(env, RV64 | RVI | RVM | RVA | RVC | RVU);
36
set_priv_version(env, PRIV_VERSION_1_10_0);
37
qdev_prop_set_bit(DEVICE(obj), "mmu", false);
38
}
39
+#else
40
+static void rv32_sifive_u_cpu_init(Object *obj)
41
+{
42
+ CPURISCVState *env = &RISCV_CPU(obj)->env;
43
+ set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
44
+ set_priv_version(env, PRIV_VERSION_1_10_0);
45
+}
46
47
-#if defined(TARGET_RISCV32)
48
+static void rv32_sifive_e_cpu_init(Object *obj)
49
+{
50
+ CPURISCVState *env = &RISCV_CPU(obj)->env;
51
+ set_misa(env, RV32 | RVI | RVM | RVA | RVC | RVU);
52
+ set_priv_version(env, PRIV_VERSION_1_10_0);
53
+ qdev_prop_set_bit(DEVICE(obj), "mmu", false);
54
+}
55
56
static void rv32_ibex_cpu_init(Object *obj)
57
{
58
@@ -XXX,XX +XXX,XX @@ static void rv32_imafcu_nommu_cpu_init(Object *obj)
59
set_resetvec(env, DEFAULT_RSTVEC);
60
qdev_prop_set_bit(DEVICE(obj), "mmu", false);
61
}
62
-
63
#endif
64
65
static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model)
66
@@ -XXX,XX +XXX,XX @@ static const TypeInfo riscv_cpu_type_infos[] = {
67
#if defined(TARGET_RISCV32)
68
DEFINE_CPU(TYPE_RISCV_CPU_BASE32, riscv_base_cpu_init),
69
DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32_ibex_cpu_init),
70
- DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rvxx_sifive_e_cpu_init),
71
+ DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32_sifive_e_cpu_init),
72
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32_imafcu_nommu_cpu_init),
73
- DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rvxx_sifive_u_cpu_init),
74
+ DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32_sifive_u_cpu_init),
75
#elif defined(TARGET_RISCV64)
76
DEFINE_CPU(TYPE_RISCV_CPU_BASE64, riscv_base_cpu_init),
77
- DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rvxx_sifive_e_cpu_init),
78
- DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rvxx_sifive_u_cpu_init),
79
+ DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64_sifive_e_cpu_init),
80
+ DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64_sifive_u_cpu_init),
81
#endif
82
};
32
};
83
33
34
static void riscv_cpu_validate_misa_mxl(RISCVCPUClass *mcc)
35
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
36
index XXXXXXX..XXXXXXX 100644
37
--- a/target/riscv/tcg/tcg-cpu.c
38
+++ b/target/riscv/tcg/tcg-cpu.c
39
@@ -XXX,XX +XXX,XX @@ static void riscv_init_max_cpu_extensions(Object *obj)
40
const RISCVCPUMultiExtConfig *prop;
41
42
/* Enable RVG, RVJ and RVV that are disabled by default */
43
- riscv_cpu_set_misa_ext(env, env->misa_ext | RVG | RVJ | RVV);
44
+ riscv_cpu_set_misa_ext(env, env->misa_ext | RVB | RVG | RVJ | RVV);
45
46
for (prop = riscv_cpu_extensions; prop && prop->name; prop++) {
47
isa_ext_update_enabled(cpu, prop->offset, true);
84
--
48
--
85
2.29.2
49
2.45.1
86
87
diff view generated by jsdifflib
[PULL 23/23] riscv/opentitan: Update the OpenTitan memory layout
[PULL 24/28] target/riscv: rvzicbo: Fixup CBO extension register calculation
1
OpenTitan is currently only avalible on an FPGA platform and the memory
1
From: Alistair Francis <alistair23@gmail.com>
2
addresses have changed. Update to use the new memory addresses.
2
3
When running the instruction
4
5
```
6
cbo.flush 0(x0)
7
```
8
9
QEMU would segfault.
10
11
The issue was in cpu_gpr[a->rs1] as QEMU does not have cpu_gpr[0]
12
allocated.
13
14
In order to fix this let's use the existing get_address()
15
helper. This also has the benefit of performing pointer mask
16
calculations on the address specified in rs1.
17
18
The pointer masking specificiation specifically states:
19
20
"""
21
Cache Management Operations: All instructions in Zicbom, Zicbop and Zicboz
22
"""
23
24
So this is the correct behaviour and we previously have been incorrectly
25
not masking the address.
3
26
4
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
27
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
5
Message-id: 8eb65314830a75d0fea3fccf77bc45b8ddd01c42.1607982831.git.alistair.francis@wdc.com
28
Reported-by: Fabian Thomas <fabian.thomas@cispa.de>
29
Fixes: e05da09b7cfd ("target/riscv: implement Zicbom extension")
30
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
31
Cc: qemu-stable <qemu-stable@nongnu.org>
32
Message-ID: <20240514023910.301766-1-alistair.francis@wdc.com>
33
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
6
---
34
---
7
include/hw/riscv/opentitan.h | 23 +++++++---
35
target/riscv/insn_trans/trans_rvzicbo.c.inc | 16 ++++++++++++----
8
hw/riscv/opentitan.c | 81 +++++++++++++++++++++++++-----------
36
1 file changed, 12 insertions(+), 4 deletions(-)
9
2 files changed, 74 insertions(+), 30 deletions(-)
10
37
11
diff --git a/include/hw/riscv/opentitan.h b/include/hw/riscv/opentitan.h
38
diff --git a/target/riscv/insn_trans/trans_rvzicbo.c.inc b/target/riscv/insn_trans/trans_rvzicbo.c.inc
12
index XXXXXXX..XXXXXXX 100644
39
index XXXXXXX..XXXXXXX 100644
13
--- a/include/hw/riscv/opentitan.h
40
--- a/target/riscv/insn_trans/trans_rvzicbo.c.inc
14
+++ b/include/hw/riscv/opentitan.h
41
+++ b/target/riscv/insn_trans/trans_rvzicbo.c.inc
15
@@ -XXX,XX +XXX,XX @@ enum {
42
@@ -XXX,XX +XXX,XX @@
16
IBEX_DEV_UART,
43
static bool trans_cbo_clean(DisasContext *ctx, arg_cbo_clean *a)
17
IBEX_DEV_GPIO,
44
{
18
IBEX_DEV_SPI,
45
REQUIRE_ZICBOM(ctx);
19
- IBEX_DEV_FLASH_CTRL,
46
- gen_helper_cbo_clean_flush(tcg_env, cpu_gpr[a->rs1]);
20
+ IBEX_DEV_I2C,
47
+ TCGv src = get_address(ctx, a->rs1, 0);
21
+ IBEX_DEV_PATTGEN,
48
+
22
IBEX_DEV_RV_TIMER,
49
+ gen_helper_cbo_clean_flush(tcg_env, src);
23
- IBEX_DEV_AES,
50
return true;
24
- IBEX_DEV_HMAC,
25
- IBEX_DEV_PLIC,
26
+ IBEX_DEV_SENSOR_CTRL,
27
+ IBEX_DEV_OTP_CTRL,
28
IBEX_DEV_PWRMGR,
29
IBEX_DEV_RSTMGR,
30
IBEX_DEV_CLKMGR,
31
IBEX_DEV_PINMUX,
32
+ IBEX_DEV_PADCTRL,
33
+ IBEX_DEV_USBDEV,
34
+ IBEX_DEV_FLASH_CTRL,
35
+ IBEX_DEV_PLIC,
36
+ IBEX_DEV_AES,
37
+ IBEX_DEV_HMAC,
38
+ IBEX_DEV_KMAC,
39
+ IBEX_DEV_KEYMGR,
40
+ IBEX_DEV_CSRNG,
41
+ IBEX_DEV_ENTROPY,
42
+ IBEX_DEV_EDNO,
43
+ IBEX_DEV_EDN1,
44
IBEX_DEV_ALERT_HANDLER,
45
IBEX_DEV_NMI_GEN,
46
- IBEX_DEV_USBDEV,
47
- IBEX_DEV_PADCTRL,
48
+ IBEX_DEV_OTBN,
49
};
50
51
enum {
52
diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
53
index XXXXXXX..XXXXXXX 100644
54
--- a/hw/riscv/opentitan.c
55
+++ b/hw/riscv/opentitan.c
56
@@ -XXX,XX +XXX,XX @@ static const struct MemmapEntry {
57
[IBEX_DEV_ROM] = { 0x00008000, 16 * KiB },
58
[IBEX_DEV_RAM] = { 0x10000000, 0x10000 },
59
[IBEX_DEV_FLASH] = { 0x20000000, 0x80000 },
60
- [IBEX_DEV_UART] = { 0x40000000, 0x10000 },
61
- [IBEX_DEV_GPIO] = { 0x40010000, 0x10000 },
62
- [IBEX_DEV_SPI] = { 0x40020000, 0x10000 },
63
- [IBEX_DEV_FLASH_CTRL] = { 0x40030000, 0x10000 },
64
- [IBEX_DEV_PINMUX] = { 0x40070000, 0x10000 },
65
- [IBEX_DEV_RV_TIMER] = { 0x40080000, 0x10000 },
66
- [IBEX_DEV_PLIC] = { 0x40090000, 0x10000 },
67
- [IBEX_DEV_PWRMGR] = { 0x400A0000, 0x10000 },
68
- [IBEX_DEV_RSTMGR] = { 0x400B0000, 0x10000 },
69
- [IBEX_DEV_CLKMGR] = { 0x400C0000, 0x10000 },
70
- [IBEX_DEV_AES] = { 0x40110000, 0x10000 },
71
- [IBEX_DEV_HMAC] = { 0x40120000, 0x10000 },
72
- [IBEX_DEV_ALERT_HANDLER] = { 0x40130000, 0x10000 },
73
- [IBEX_DEV_NMI_GEN] = { 0x40140000, 0x10000 },
74
- [IBEX_DEV_USBDEV] = { 0x40150000, 0x10000 },
75
- [IBEX_DEV_PADCTRL] = { 0x40160000, 0x10000 }
76
+ [IBEX_DEV_UART] = { 0x40000000, 0x1000 },
77
+ [IBEX_DEV_GPIO] = { 0x40040000, 0x1000 },
78
+ [IBEX_DEV_SPI] = { 0x40050000, 0x1000 },
79
+ [IBEX_DEV_I2C] = { 0x40080000, 0x1000 },
80
+ [IBEX_DEV_PATTGEN] = { 0x400e0000, 0x1000 },
81
+ [IBEX_DEV_RV_TIMER] = { 0x40100000, 0x1000 },
82
+ [IBEX_DEV_SENSOR_CTRL] = { 0x40110000, 0x1000 },
83
+ [IBEX_DEV_OTP_CTRL] = { 0x40130000, 0x4000 },
84
+ [IBEX_DEV_PWRMGR] = { 0x40400000, 0x1000 },
85
+ [IBEX_DEV_RSTMGR] = { 0x40410000, 0x1000 },
86
+ [IBEX_DEV_CLKMGR] = { 0x40420000, 0x1000 },
87
+ [IBEX_DEV_PINMUX] = { 0x40460000, 0x1000 },
88
+ [IBEX_DEV_PADCTRL] = { 0x40470000, 0x1000 },
89
+ [IBEX_DEV_USBDEV] = { 0x40500000, 0x1000 },
90
+ [IBEX_DEV_FLASH_CTRL] = { 0x41000000, 0x1000 },
91
+ [IBEX_DEV_PLIC] = { 0x41010000, 0x1000 },
92
+ [IBEX_DEV_AES] = { 0x41100000, 0x1000 },
93
+ [IBEX_DEV_HMAC] = { 0x41110000, 0x1000 },
94
+ [IBEX_DEV_KMAC] = { 0x41120000, 0x1000 },
95
+ [IBEX_DEV_KEYMGR] = { 0x41130000, 0x1000 },
96
+ [IBEX_DEV_CSRNG] = { 0x41150000, 0x1000 },
97
+ [IBEX_DEV_ENTROPY] = { 0x41160000, 0x1000 },
98
+ [IBEX_DEV_EDNO] = { 0x41170000, 0x1000 },
99
+ [IBEX_DEV_EDN1] = { 0x41180000, 0x1000 },
100
+ [IBEX_DEV_ALERT_HANDLER] = { 0x411b0000, 0x1000 },
101
+ [IBEX_DEV_NMI_GEN] = { 0x411c0000, 0x1000 },
102
+ [IBEX_DEV_OTBN] = { 0x411d0000, 0x10000 },
103
};
104
105
static void opentitan_board_init(MachineState *machine)
106
@@ -XXX,XX +XXX,XX @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
107
memmap[IBEX_DEV_GPIO].base, memmap[IBEX_DEV_GPIO].size);
108
create_unimplemented_device("riscv.lowrisc.ibex.spi",
109
memmap[IBEX_DEV_SPI].base, memmap[IBEX_DEV_SPI].size);
110
- create_unimplemented_device("riscv.lowrisc.ibex.flash_ctrl",
111
- memmap[IBEX_DEV_FLASH_CTRL].base, memmap[IBEX_DEV_FLASH_CTRL].size);
112
+ create_unimplemented_device("riscv.lowrisc.ibex.i2c",
113
+ memmap[IBEX_DEV_I2C].base, memmap[IBEX_DEV_I2C].size);
114
+ create_unimplemented_device("riscv.lowrisc.ibex.pattgen",
115
+ memmap[IBEX_DEV_PATTGEN].base, memmap[IBEX_DEV_PATTGEN].size);
116
create_unimplemented_device("riscv.lowrisc.ibex.rv_timer",
117
memmap[IBEX_DEV_RV_TIMER].base, memmap[IBEX_DEV_RV_TIMER].size);
118
+ create_unimplemented_device("riscv.lowrisc.ibex.sensor_ctrl",
119
+ memmap[IBEX_DEV_SENSOR_CTRL].base, memmap[IBEX_DEV_SENSOR_CTRL].size);
120
+ create_unimplemented_device("riscv.lowrisc.ibex.otp_ctrl",
121
+ memmap[IBEX_DEV_OTP_CTRL].base, memmap[IBEX_DEV_OTP_CTRL].size);
122
create_unimplemented_device("riscv.lowrisc.ibex.pwrmgr",
123
memmap[IBEX_DEV_PWRMGR].base, memmap[IBEX_DEV_PWRMGR].size);
124
create_unimplemented_device("riscv.lowrisc.ibex.rstmgr",
125
memmap[IBEX_DEV_RSTMGR].base, memmap[IBEX_DEV_RSTMGR].size);
126
create_unimplemented_device("riscv.lowrisc.ibex.clkmgr",
127
memmap[IBEX_DEV_CLKMGR].base, memmap[IBEX_DEV_CLKMGR].size);
128
+ create_unimplemented_device("riscv.lowrisc.ibex.pinmux",
129
+ memmap[IBEX_DEV_PINMUX].base, memmap[IBEX_DEV_PINMUX].size);
130
+ create_unimplemented_device("riscv.lowrisc.ibex.padctrl",
131
+ memmap[IBEX_DEV_PADCTRL].base, memmap[IBEX_DEV_PADCTRL].size);
132
+ create_unimplemented_device("riscv.lowrisc.ibex.usbdev",
133
+ memmap[IBEX_DEV_USBDEV].base, memmap[IBEX_DEV_USBDEV].size);
134
+ create_unimplemented_device("riscv.lowrisc.ibex.flash_ctrl",
135
+ memmap[IBEX_DEV_FLASH_CTRL].base, memmap[IBEX_DEV_FLASH_CTRL].size);
136
create_unimplemented_device("riscv.lowrisc.ibex.aes",
137
memmap[IBEX_DEV_AES].base, memmap[IBEX_DEV_AES].size);
138
create_unimplemented_device("riscv.lowrisc.ibex.hmac",
139
memmap[IBEX_DEV_HMAC].base, memmap[IBEX_DEV_HMAC].size);
140
- create_unimplemented_device("riscv.lowrisc.ibex.pinmux",
141
- memmap[IBEX_DEV_PINMUX].base, memmap[IBEX_DEV_PINMUX].size);
142
+ create_unimplemented_device("riscv.lowrisc.ibex.kmac",
143
+ memmap[IBEX_DEV_KMAC].base, memmap[IBEX_DEV_KMAC].size);
144
+ create_unimplemented_device("riscv.lowrisc.ibex.keymgr",
145
+ memmap[IBEX_DEV_KEYMGR].base, memmap[IBEX_DEV_KEYMGR].size);
146
+ create_unimplemented_device("riscv.lowrisc.ibex.csrng",
147
+ memmap[IBEX_DEV_CSRNG].base, memmap[IBEX_DEV_CSRNG].size);
148
+ create_unimplemented_device("riscv.lowrisc.ibex.entropy",
149
+ memmap[IBEX_DEV_ENTROPY].base, memmap[IBEX_DEV_ENTROPY].size);
150
+ create_unimplemented_device("riscv.lowrisc.ibex.edn0",
151
+ memmap[IBEX_DEV_EDNO].base, memmap[IBEX_DEV_EDNO].size);
152
+ create_unimplemented_device("riscv.lowrisc.ibex.edn1",
153
+ memmap[IBEX_DEV_EDN1].base, memmap[IBEX_DEV_EDN1].size);
154
create_unimplemented_device("riscv.lowrisc.ibex.alert_handler",
155
memmap[IBEX_DEV_ALERT_HANDLER].base, memmap[IBEX_DEV_ALERT_HANDLER].size);
156
create_unimplemented_device("riscv.lowrisc.ibex.nmi_gen",
157
memmap[IBEX_DEV_NMI_GEN].base, memmap[IBEX_DEV_NMI_GEN].size);
158
- create_unimplemented_device("riscv.lowrisc.ibex.usbdev",
159
- memmap[IBEX_DEV_USBDEV].base, memmap[IBEX_DEV_USBDEV].size);
160
- create_unimplemented_device("riscv.lowrisc.ibex.padctrl",
161
- memmap[IBEX_DEV_PADCTRL].base, memmap[IBEX_DEV_PADCTRL].size);
162
+ create_unimplemented_device("riscv.lowrisc.ibex.otbn",
163
+ memmap[IBEX_DEV_OTBN].base, memmap[IBEX_DEV_OTBN].size);
164
}
51
}
165
52
166
static void lowrisc_ibex_soc_class_init(ObjectClass *oc, void *data)
53
static bool trans_cbo_flush(DisasContext *ctx, arg_cbo_flush *a)
54
{
55
REQUIRE_ZICBOM(ctx);
56
- gen_helper_cbo_clean_flush(tcg_env, cpu_gpr[a->rs1]);
57
+ TCGv src = get_address(ctx, a->rs1, 0);
58
+
59
+ gen_helper_cbo_clean_flush(tcg_env, src);
60
return true;
61
}
62
63
static bool trans_cbo_inval(DisasContext *ctx, arg_cbo_inval *a)
64
{
65
REQUIRE_ZICBOM(ctx);
66
- gen_helper_cbo_inval(tcg_env, cpu_gpr[a->rs1]);
67
+ TCGv src = get_address(ctx, a->rs1, 0);
68
+
69
+ gen_helper_cbo_inval(tcg_env, src);
70
return true;
71
}
72
73
static bool trans_cbo_zero(DisasContext *ctx, arg_cbo_zero *a)
74
{
75
REQUIRE_ZICBOZ(ctx);
76
- gen_helper_cbo_zero(tcg_env, cpu_gpr[a->rs1]);
77
+ TCGv src = get_address(ctx, a->rs1, 0);
78
+
79
+ gen_helper_cbo_zero(tcg_env, src);
80
return true;
81
}
167
--
82
--
168
2.29.2
83
2.45.1
169
170
diff view generated by jsdifflib
[PULL 14/23] hw/riscv: sifive_u: Remove compile time XLEN checks
[PULL 25/28] target/riscv/kvm.c: Fix the hart bit setting of AIA
1
From: Yong-Xuan Wang <yongxuan.wang@sifive.com>
2
3
In AIA spec, each hart (or each hart within a group) has a unique hart
4
number to locate the memory pages of interrupt files in the address
5
space. The number of bits required to represent any hart number is equal
6
to ceil(log2(hmax + 1)), where hmax is the largest hart number among
7
groups.
8
9
However, if the largest hart number among groups is a power of 2, QEMU
10
will pass an inaccurate hart-index-bit setting to Linux. For example, when
11
the guest OS has 4 harts, only ceil(log2(3 + 1)) = 2 bits are sufficient
12
to represent 4 harts, but we passes 3 to Linux. The code needs to be
13
updated to ensure accurate hart-index-bit settings.
14
15
Additionally, a Linux patch[1] is necessary to correctly recover the hart
16
index when the guest OS has only 1 hart, where the hart-index-bit is 0.
17
18
[1] https://lore.kernel.org/lkml/20240415064905.25184-1-yongxuan.wang@sifive.com/t/
19
20
Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com>
21
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
22
Cc: qemu-stable <qemu-stable@nongnu.org>
23
Message-ID: <20240515091129.28116-1-yongxuan.wang@sifive.com>
1
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
24
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
3
Acked-by: Palmer Dabbelt <palmerdabbelt@google.com>
4
Reviewed-by: Bin Meng <bin.meng@windriver.com>
5
Tested-by: Bin Meng <bin.meng@windriver.com>
6
Message-id: 40d6df4dd05302c566e419be3a1fef7799e57c2e.1608142916.git.alistair.francis@wdc.com
7
---
25
---
8
hw/riscv/sifive_u.c | 55 ++++++++++++++++++++++++---------------------
26
target/riscv/kvm/kvm-cpu.c | 9 ++++++++-
9
1 file changed, 30 insertions(+), 25 deletions(-)
27
1 file changed, 8 insertions(+), 1 deletion(-)
10
28
11
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
29
diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
12
index XXXXXXX..XXXXXXX 100644
30
index XXXXXXX..XXXXXXX 100644
13
--- a/hw/riscv/sifive_u.c
31
--- a/target/riscv/kvm/kvm-cpu.c
14
+++ b/hw/riscv/sifive_u.c
32
+++ b/target/riscv/kvm/kvm-cpu.c
15
@@ -XXX,XX +XXX,XX @@
33
@@ -XXX,XX +XXX,XX @@ void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift,
16
34
}
17
#include <libfdt.h>
18
19
-#if defined(TARGET_RISCV32)
20
-# define BIOS_FILENAME "opensbi-riscv32-generic-fw_dynamic.bin"
21
-#else
22
-# define BIOS_FILENAME "opensbi-riscv64-generic-fw_dynamic.bin"
23
-#endif
24
-
25
static const struct MemmapEntry {
26
hwaddr base;
27
hwaddr size;
28
@@ -XXX,XX +XXX,XX @@ static const struct MemmapEntry {
29
#define GEM_REVISION 0x10070109
30
31
static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
32
- uint64_t mem_size, const char *cmdline)
33
+ uint64_t mem_size, const char *cmdline, bool is_32_bit)
34
{
35
MachineState *ms = MACHINE(qdev_get_machine());
36
void *fdt;
37
@@ -XXX,XX +XXX,XX @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
38
qemu_fdt_add_subnode(fdt, nodename);
39
/* cpu 0 is the management hart that does not have mmu */
40
if (cpu != 0) {
41
-#if defined(TARGET_RISCV32)
42
- qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv32");
43
-#else
44
- qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48");
45
-#endif
46
+ if (is_32_bit) {
47
+ qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv32");
48
+ } else {
49
+ qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48");
50
+ }
51
isa = riscv_isa_string(&s->soc.u_cpus.harts[cpu - 1]);
52
} else {
53
isa = riscv_isa_string(&s->soc.e_cpus.harts[0]);
54
@@ -XXX,XX +XXX,XX @@ static void sifive_u_machine_init(MachineState *machine)
55
qemu_allocate_irq(sifive_u_machine_reset, NULL, 0));
56
57
/* create device tree */
58
- create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline);
59
+ create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline,
60
+ riscv_is_32_bit(machine));
61
62
if (s->start_in_flash) {
63
/*
64
@@ -XXX,XX +XXX,XX @@ static void sifive_u_machine_init(MachineState *machine)
65
break;
66
}
35
}
67
36
68
- firmware_end_addr = riscv_find_and_load_firmware(machine, BIOS_FILENAME,
37
- hart_bits = find_last_bit(&max_hart_per_socket, BITS_PER_LONG) + 1;
69
- start_addr, NULL);
38
+
70
+ if (riscv_is_32_bit(machine)) {
39
+ if (max_hart_per_socket > 1) {
71
+ firmware_end_addr = riscv_find_and_load_firmware(machine,
40
+ max_hart_per_socket--;
72
+ "opensbi-riscv32-generic-fw_dynamic.bin",
41
+ hart_bits = find_last_bit(&max_hart_per_socket, BITS_PER_LONG) + 1;
73
+ start_addr, NULL);
74
+ } else {
42
+ } else {
75
+ firmware_end_addr = riscv_find_and_load_firmware(machine,
43
+ hart_bits = 0;
76
+ "opensbi-riscv64-generic-fw_dynamic.bin",
77
+ start_addr, NULL);
78
+ }
79
80
if (machine->kernel_filename) {
81
kernel_start_addr = riscv_calc_kernel_start_addr(machine,
82
@@ -XXX,XX +XXX,XX @@ static void sifive_u_machine_init(MachineState *machine)
83
/* Compute the fdt load address in dram */
84
fdt_load_addr = riscv_load_fdt(memmap[SIFIVE_U_DEV_DRAM].base,
85
machine->ram_size, s->fdt);
86
- #if defined(TARGET_RISCV64)
87
- start_addr_hi32 = start_addr >> 32;
88
- #endif
89
+ if (!riscv_is_32_bit(machine)) {
90
+ start_addr_hi32 = (uint64_t)start_addr >> 32;
91
+ }
92
93
/* reset vector */
94
uint32_t reset_vec[11] = {
95
@@ -XXX,XX +XXX,XX @@ static void sifive_u_machine_init(MachineState *machine)
96
0x00000297, /* 1: auipc t0, %pcrel_hi(fw_dyn) */
97
0x02828613, /* addi a2, t0, %pcrel_lo(1b) */
98
0xf1402573, /* csrr a0, mhartid */
99
-#if defined(TARGET_RISCV32)
100
- 0x0202a583, /* lw a1, 32(t0) */
101
- 0x0182a283, /* lw t0, 24(t0) */
102
-#elif defined(TARGET_RISCV64)
103
- 0x0202b583, /* ld a1, 32(t0) */
104
- 0x0182b283, /* ld t0, 24(t0) */
105
-#endif
106
+ 0,
107
+ 0,
108
0x00028067, /* jr t0 */
109
start_addr, /* start: .dword */
110
start_addr_hi32,
111
@@ -XXX,XX +XXX,XX @@ static void sifive_u_machine_init(MachineState *machine)
112
0x00000000,
113
/* fw_dyn: */
114
};
115
+ if (riscv_is_32_bit(machine)) {
116
+ reset_vec[4] = 0x0202a583; /* lw a1, 32(t0) */
117
+ reset_vec[5] = 0x0182a283; /* lw t0, 24(t0) */
118
+ } else {
119
+ reset_vec[4] = 0x0202b583; /* ld a1, 32(t0) */
120
+ reset_vec[5] = 0x0182b283; /* ld t0, 24(t0) */
121
+ }
44
+ }
122
+
45
+
123
46
ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG,
124
/* copy in the reset vector in little_endian byte order */
47
KVM_DEV_RISCV_AIA_CONFIG_HART_BITS,
125
for (i = 0; i < ARRAY_SIZE(reset_vec); i++) {
48
&hart_bits, true, NULL);
126
--
49
--
127
2.29.2
50
2.45.1
128
129
diff view generated by jsdifflib
[PULL 10/23] riscv: virt: Remove target macro conditionals
[PULL 26/28] riscv, gdbstub.c: fix reg_width in ricsv_gen_dynamic_vector_feature()
1
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
2
3
Commit 33a24910ae changed 'reg_width' to use 'vlenb', i.e. vector length
4
in bytes, when in this context we want 'reg_width' as the length in
5
bits.
6
7
Fix 'reg_width' back to the value in bits like 7cb59921c05a
8
("target/riscv/gdbstub.c: use 'vlenb' instead of shifting 'vlen'") set
9
beforehand.
10
11
While we're at it, rename 'reg_width' to 'bitsize' to provide a bit more
12
clarity about what the variable represents. 'bitsize' is also used in
13
riscv_gen_dynamic_csr_feature() with the same purpose, i.e. as an input to
14
gdb_feature_builder_append_reg().
15
16
Cc: Akihiko Odaki <akihiko.odaki@daynix.com>
17
Cc: Alex Bennée <alex.bennee@linaro.org>
18
Reported-by: Robin Dapp <rdapp.gcc@gmail.com>
19
Fixes: 33a24910ae ("target/riscv: Use GDBFeature for dynamic XML")
20
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
21
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
22
Acked-by: Alex Bennée <alex.bennee@linaro.org>
23
Reviewed-by: Akihiko Odaki <akihiko.odaki@daynix.com>
24
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
25
Cc: qemu-stable <qemu-stable@nongnu.org>
26
Message-ID: <20240517203054.880861-2-dbarboza@ventanamicro.com>
1
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
27
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2
Reviewed-by: Bin Meng <bin.meng@windriver.com>
3
Tested-by: Bin Meng <bin.meng@windriver.com>
4
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
5
Acked-by: Palmer Dabbelt <palmerdabbelt@google.com>
6
Message-id: aed1174c2efd2f050fa5bd8f524d68795b12c0e4.1608142916.git.alistair.francis@wdc.com
7
---
28
---
8
include/hw/riscv/virt.h | 6 ------
29
target/riscv/gdbstub.c | 6 +++---
9
hw/riscv/virt.c | 2 +-
30
1 file changed, 3 insertions(+), 3 deletions(-)
10
2 files changed, 1 insertion(+), 7 deletions(-)
11
31
12
diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
32
diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
13
index XXXXXXX..XXXXXXX 100644
33
index XXXXXXX..XXXXXXX 100644
14
--- a/include/hw/riscv/virt.h
34
--- a/target/riscv/gdbstub.c
15
+++ b/include/hw/riscv/virt.h
35
+++ b/target/riscv/gdbstub.c
16
@@ -XXX,XX +XXX,XX @@ enum {
36
@@ -XXX,XX +XXX,XX @@ static GDBFeature *riscv_gen_dynamic_csr_feature(CPUState *cs, int base_reg)
17
#define FDT_INT_MAP_WIDTH (FDT_PCI_ADDR_CELLS + FDT_PCI_INT_CELLS + 1 + \
37
static GDBFeature *ricsv_gen_dynamic_vector_feature(CPUState *cs, int base_reg)
18
FDT_PLIC_ADDR_CELLS + FDT_PLIC_INT_CELLS)
38
{
19
39
RISCVCPU *cpu = RISCV_CPU(cs);
20
-#if defined(TARGET_RISCV32)
40
- int reg_width = cpu->cfg.vlenb;
21
-#define VIRT_CPU TYPE_RISCV_CPU_BASE32
41
+ int bitsize = cpu->cfg.vlenb << 3;
22
-#elif defined(TARGET_RISCV64)
42
GDBFeatureBuilder builder;
23
-#define VIRT_CPU TYPE_RISCV_CPU_BASE64
43
int i;
24
-#endif
44
25
-
45
@@ -XXX,XX +XXX,XX @@ static GDBFeature *ricsv_gen_dynamic_vector_feature(CPUState *cs, int base_reg)
26
#endif
46
27
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
47
/* First define types and totals in a whole VL */
28
index XXXXXXX..XXXXXXX 100644
48
for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) {
29
--- a/hw/riscv/virt.c
49
- int count = reg_width / vec_lanes[i].size;
30
+++ b/hw/riscv/virt.c
50
+ int count = bitsize / vec_lanes[i].size;
31
@@ -XXX,XX +XXX,XX @@ static void virt_machine_class_init(ObjectClass *oc, void *data)
51
gdb_feature_builder_append_tag(
32
mc->desc = "RISC-V VirtIO board";
52
&builder, "<vector id=\"%s\" type=\"%s\" count=\"%d\"/>",
33
mc->init = virt_machine_init;
53
vec_lanes[i].id, vec_lanes[i].gdb_type, count);
34
mc->max_cpus = VIRT_CPUS_MAX;
54
@@ -XXX,XX +XXX,XX @@ static GDBFeature *ricsv_gen_dynamic_vector_feature(CPUState *cs, int base_reg)
35
- mc->default_cpu_type = VIRT_CPU;
55
/* Define vector registers */
36
+ mc->default_cpu_type = TYPE_RISCV_CPU_BASE;
56
for (i = 0; i < 32; i++) {
37
mc->pci_allow_0_address = true;
57
gdb_feature_builder_append_reg(&builder, g_strdup_printf("v%d", i),
38
mc->possible_cpu_arch_ids = riscv_numa_possible_cpu_arch_ids;
58
- reg_width, i, "riscv_vector", "vector");
39
mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props;
59
+ bitsize, i, "riscv_vector", "vector");
60
}
61
62
gdb_feature_builder_end(&builder);
40
--
63
--
41
2.29.2
64
2.45.1
42
65
43
66
diff view generated by jsdifflib
[PULL 01/23] hw/riscv: sifive_u: Add UART1 DT node in the generated DTB
[PULL 27/28] disas/riscv: Decode all of the pmpcfg and pmpaddr CSRs
1
From: Anup Patel <anup.patel@wdc.com>
1
From: Alistair Francis <alistair23@gmail.com>
2
2
3
The sifive_u machine emulates two UARTs but we have only UART0 DT
3
Previously we only listed a single pmpcfg CSR and the first 16 pmpaddr
4
node in the generated DTB so this patch adds UART1 DT node in the
4
CSRs. This patch fixes this to list all 16 pmpcfg and all 64 pmpaddr
5
generated DTB.
5
CSRs are part of the disassembly.
6
6
7
Signed-off-by: Anup Patel <anup.patel@wdc.com>
7
Reported-by: Eric DeVolder <eric_devolder@yahoo.com>
8
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
8
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
9
Message-id: 20201111094725.3768755-1-anup.patel@wdc.com
9
Fixes: ea10325917 ("RISC-V Disassembler")
10
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
11
Cc: qemu-stable <qemu-stable@nongnu.org>
12
Message-ID: <20240514051615.330979-1-alistair.francis@wdc.com>
10
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
13
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
11
---
14
---
12
hw/riscv/sifive_u.c | 15 +++++++++++++++
15
disas/riscv.c | 65 ++++++++++++++++++++++++++++++++++++++++++++++++++-
13
1 file changed, 15 insertions(+)
16
1 file changed, 64 insertions(+), 1 deletion(-)
14
17
15
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
18
diff --git a/disas/riscv.c b/disas/riscv.c
16
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/riscv/sifive_u.c
20
--- a/disas/riscv.c
18
+++ b/hw/riscv/sifive_u.c
21
+++ b/disas/riscv.c
19
@@ -XXX,XX +XXX,XX @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
22
@@ -XXX,XX +XXX,XX @@ static const char *csr_name(int csrno)
20
qemu_fdt_setprop_cell(fdt, nodename, "reg", 0x0);
23
case 0x0383: return "mibound";
21
g_free(nodename);
24
case 0x0384: return "mdbase";
22
25
case 0x0385: return "mdbound";
23
+ nodename = g_strdup_printf("/soc/serial@%lx",
26
- case 0x03a0: return "pmpcfg3";
24
+ (long)memmap[SIFIVE_U_DEV_UART1].base);
27
+ case 0x03a0: return "pmpcfg0";
25
+ qemu_fdt_add_subnode(fdt, nodename);
28
+ case 0x03a1: return "pmpcfg1";
26
+ qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,uart0");
29
+ case 0x03a2: return "pmpcfg2";
27
+ qemu_fdt_setprop_cells(fdt, nodename, "reg",
30
+ case 0x03a3: return "pmpcfg3";
28
+ 0x0, memmap[SIFIVE_U_DEV_UART1].base,
31
+ case 0x03a4: return "pmpcfg4";
29
+ 0x0, memmap[SIFIVE_U_DEV_UART1].size);
32
+ case 0x03a5: return "pmpcfg5";
30
+ qemu_fdt_setprop_cells(fdt, nodename, "clocks",
33
+ case 0x03a6: return "pmpcfg6";
31
+ prci_phandle, PRCI_CLK_TLCLK);
34
+ case 0x03a7: return "pmpcfg7";
32
+ qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
35
+ case 0x03a8: return "pmpcfg8";
33
+ qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_UART1_IRQ);
36
+ case 0x03a9: return "pmpcfg9";
34
+
37
+ case 0x03aa: return "pmpcfg10";
35
+ qemu_fdt_setprop_string(fdt, "/aliases", "serial1", nodename);
38
+ case 0x03ab: return "pmpcfg11";
36
+ g_free(nodename);
39
+ case 0x03ac: return "pmpcfg12";
37
+
40
+ case 0x03ad: return "pmpcfg13";
38
nodename = g_strdup_printf("/soc/serial@%lx",
41
+ case 0x03ae: return "pmpcfg14";
39
(long)memmap[SIFIVE_U_DEV_UART0].base);
42
+ case 0x03af: return "pmpcfg15";
40
qemu_fdt_add_subnode(fdt, nodename);
43
case 0x03b0: return "pmpaddr0";
44
case 0x03b1: return "pmpaddr1";
45
case 0x03b2: return "pmpaddr2";
46
@@ -XXX,XX +XXX,XX @@ static const char *csr_name(int csrno)
47
case 0x03bd: return "pmpaddr13";
48
case 0x03be: return "pmpaddr14";
49
case 0x03bf: return "pmpaddr15";
50
+ case 0x03c0: return "pmpaddr16";
51
+ case 0x03c1: return "pmpaddr17";
52
+ case 0x03c2: return "pmpaddr18";
53
+ case 0x03c3: return "pmpaddr19";
54
+ case 0x03c4: return "pmpaddr20";
55
+ case 0x03c5: return "pmpaddr21";
56
+ case 0x03c6: return "pmpaddr22";
57
+ case 0x03c7: return "pmpaddr23";
58
+ case 0x03c8: return "pmpaddr24";
59
+ case 0x03c9: return "pmpaddr25";
60
+ case 0x03ca: return "pmpaddr26";
61
+ case 0x03cb: return "pmpaddr27";
62
+ case 0x03cc: return "pmpaddr28";
63
+ case 0x03cd: return "pmpaddr29";
64
+ case 0x03ce: return "pmpaddr30";
65
+ case 0x03cf: return "pmpaddr31";
66
+ case 0x03d0: return "pmpaddr32";
67
+ case 0x03d1: return "pmpaddr33";
68
+ case 0x03d2: return "pmpaddr34";
69
+ case 0x03d3: return "pmpaddr35";
70
+ case 0x03d4: return "pmpaddr36";
71
+ case 0x03d5: return "pmpaddr37";
72
+ case 0x03d6: return "pmpaddr38";
73
+ case 0x03d7: return "pmpaddr39";
74
+ case 0x03d8: return "pmpaddr40";
75
+ case 0x03d9: return "pmpaddr41";
76
+ case 0x03da: return "pmpaddr42";
77
+ case 0x03db: return "pmpaddr43";
78
+ case 0x03dc: return "pmpaddr44";
79
+ case 0x03dd: return "pmpaddr45";
80
+ case 0x03de: return "pmpaddr46";
81
+ case 0x03df: return "pmpaddr47";
82
+ case 0x03e0: return "pmpaddr48";
83
+ case 0x03e1: return "pmpaddr49";
84
+ case 0x03e2: return "pmpaddr50";
85
+ case 0x03e3: return "pmpaddr51";
86
+ case 0x03e4: return "pmpaddr52";
87
+ case 0x03e5: return "pmpaddr53";
88
+ case 0x03e6: return "pmpaddr54";
89
+ case 0x03e7: return "pmpaddr55";
90
+ case 0x03e8: return "pmpaddr56";
91
+ case 0x03e9: return "pmpaddr57";
92
+ case 0x03ea: return "pmpaddr58";
93
+ case 0x03eb: return "pmpaddr59";
94
+ case 0x03ec: return "pmpaddr60";
95
+ case 0x03ed: return "pmpaddr61";
96
+ case 0x03ee: return "pmpaddr62";
97
+ case 0x03ef: return "pmpaddr63";
98
case 0x0780: return "mtohost";
99
case 0x0781: return "mfromhost";
100
case 0x0782: return "mreset";
41
--
101
--
42
2.29.2
102
2.45.1
43
44
diff view generated by jsdifflib
[PULL 20/23] target/riscv: csr: Remove compile time XLEN checks
[PULL 28/28] target/riscv: raise an exception when CSRRS/CSRRC writes a read-only CSR
1
From: Yu-Ming Chang <yumin686@andestech.com>
2
3
Both CSRRS and CSRRC always read the addressed CSR and cause any read side
4
effects regardless of rs1 and rd fields. Note that if rs1 specifies a register
5
holding a zero value other than x0, the instruction will still attempt to write
6
the unmodified value back to the CSR and will cause any attendant side effects.
7
8
So if CSRRS or CSRRC tries to write a read-only CSR with rs1 which specifies
9
a register holding a zero value, an illegal instruction exception should be
10
raised.
11
12
Signed-off-by: Yu-Ming Chang <yumin686@andestech.com>
13
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
14
Message-ID: <20240403070823.80897-1-yumin686@andestech.com>
1
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
15
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2
Reviewed-by: Bin Meng <bin.meng@windriver.com>
3
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
4
Acked-by: Palmer Dabbelt <palmerdabbelt@google.com>
5
Tested-by: Bin Meng <bin.meng@windriver.com>
6
Message-id: 7371180970b7db310d3a1da21d03d33499c2beb0.1608142916.git.alistair.francis@wdc.com
7
---
16
---
8
target/riscv/cpu_bits.h | 4 +-
17
target/riscv/cpu.h | 4 ++++
9
target/riscv/csr.c | 176 +++++++++++++++++++++-------------------
18
target/riscv/csr.c | 51 ++++++++++++++++++++++++++++++++++++----
10
2 files changed, 92 insertions(+), 88 deletions(-)
19
target/riscv/op_helper.c | 6 ++---
20
3 files changed, 53 insertions(+), 8 deletions(-)
11
21
12
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
22
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
13
index XXXXXXX..XXXXXXX 100644
23
index XXXXXXX..XXXXXXX 100644
14
--- a/target/riscv/cpu_bits.h
24
--- a/target/riscv/cpu.h
15
+++ b/target/riscv/cpu_bits.h
25
+++ b/target/riscv/cpu.h
16
@@ -XXX,XX +XXX,XX @@
26
@@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc,
17
#define HSTATUS_VGEIN 0x0003F000
27
void riscv_cpu_update_mask(CPURISCVState *env);
18
#define HSTATUS_VTVM 0x00100000
28
bool riscv_cpu_is_32bit(RISCVCPU *cpu);
19
#define HSTATUS_VTSR 0x00400000
29
20
-#if defined(TARGET_RISCV64)
30
+RISCVException riscv_csrr(CPURISCVState *env, int csrno,
21
-#define HSTATUS_VSXL 0x300000000
31
+ target_ulong *ret_value);
22
-#endif
32
RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
23
+#define HSTATUS_VSXL 0x300000000
33
target_ulong *ret_value,
24
34
target_ulong new_value, target_ulong write_mask);
25
#define HSTATUS32_WPRI 0xFF8FF87E
35
@@ -XXX,XX +XXX,XX @@ typedef RISCVException (*riscv_csr_op_fn)(CPURISCVState *env, int csrno,
26
#define HSTATUS64_WPRI 0xFFFFFFFFFF8FF87EULL
36
target_ulong new_value,
37
target_ulong write_mask);
38
39
+RISCVException riscv_csrr_i128(CPURISCVState *env, int csrno,
40
+ Int128 *ret_value);
41
RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno,
42
Int128 *ret_value,
43
Int128 new_value, Int128 write_mask);
27
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
44
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
28
index XXXXXXX..XXXXXXX 100644
45
index XXXXXXX..XXXXXXX 100644
29
--- a/target/riscv/csr.c
46
--- a/target/riscv/csr.c
30
+++ b/target/riscv/csr.c
47
+++ b/target/riscv/csr.c
31
@@ -XXX,XX +XXX,XX @@ static int ctr(CPURISCVState *env, int csrno)
48
@@ -XXX,XX +XXX,XX @@ static RISCVException rmw_seed(CPURISCVState *env, int csrno,
32
return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
49
33
}
50
static inline RISCVException riscv_csrrw_check(CPURISCVState *env,
34
break;
51
int csrno,
35
-#if defined(TARGET_RISCV32)
52
- bool write_mask)
36
- case CSR_CYCLEH:
53
+ bool write)
37
- if (!get_field(env->hcounteren, HCOUNTEREN_CY) &&
54
{
38
- get_field(env->mcounteren, HCOUNTEREN_CY)) {
55
/* check privileges and return RISCV_EXCP_ILLEGAL_INST if check fails */
39
- return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
56
bool read_only = get_field(csrno, 0xC00) == 3;
40
- }
57
@@ -XXX,XX +XXX,XX @@ static inline RISCVException riscv_csrrw_check(CPURISCVState *env,
41
- break;
42
- case CSR_TIMEH:
43
- if (!get_field(env->hcounteren, HCOUNTEREN_TM) &&
44
- get_field(env->mcounteren, HCOUNTEREN_TM)) {
45
- return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
46
- }
47
- break;
48
- case CSR_INSTRETH:
49
- if (!get_field(env->hcounteren, HCOUNTEREN_IR) &&
50
- get_field(env->mcounteren, HCOUNTEREN_IR)) {
51
- return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
52
- }
53
- break;
54
- case CSR_HPMCOUNTER3H...CSR_HPMCOUNTER31H:
55
- if (!get_field(env->hcounteren, 1 << (csrno - CSR_HPMCOUNTER3H)) &&
56
- get_field(env->mcounteren, 1 << (csrno - CSR_HPMCOUNTER3H))) {
57
- return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
58
+ }
59
+ if (riscv_cpu_is_32bit(env)) {
60
+ switch (csrno) {
61
+ case CSR_CYCLEH:
62
+ if (!get_field(env->hcounteren, HCOUNTEREN_CY) &&
63
+ get_field(env->mcounteren, HCOUNTEREN_CY)) {
64
+ return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
65
+ }
66
+ break;
67
+ case CSR_TIMEH:
68
+ if (!get_field(env->hcounteren, HCOUNTEREN_TM) &&
69
+ get_field(env->mcounteren, HCOUNTEREN_TM)) {
70
+ return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
71
+ }
72
+ break;
73
+ case CSR_INSTRETH:
74
+ if (!get_field(env->hcounteren, HCOUNTEREN_IR) &&
75
+ get_field(env->mcounteren, HCOUNTEREN_IR)) {
76
+ return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
77
+ }
78
+ break;
79
+ case CSR_HPMCOUNTER3H...CSR_HPMCOUNTER31H:
80
+ if (!get_field(env->hcounteren, 1 << (csrno - CSR_HPMCOUNTER3H)) &&
81
+ get_field(env->mcounteren, 1 << (csrno - CSR_HPMCOUNTER3H))) {
82
+ return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
83
+ }
84
+ break;
85
}
86
- break;
87
-#endif
88
}
89
}
58
}
90
#endif
59
91
return 0;
60
/* read / write check */
61
- if (write_mask && read_only) {
62
+ if (write && read_only) {
63
return RISCV_EXCP_ILLEGAL_INST;
64
}
65
66
@@ -XXX,XX +XXX,XX @@ static RISCVException riscv_csrrw_do64(CPURISCVState *env, int csrno,
67
return RISCV_EXCP_NONE;
92
}
68
}
93
69
94
+static int ctr32(CPURISCVState *env, int csrno)
70
+RISCVException riscv_csrr(CPURISCVState *env, int csrno,
71
+ target_ulong *ret_value)
95
+{
72
+{
96
+ if (!riscv_cpu_is_32bit(env)) {
73
+ RISCVException ret = riscv_csrrw_check(env, csrno, false);
97
+ return -RISCV_EXCP_ILLEGAL_INST;
74
+ if (ret != RISCV_EXCP_NONE) {
75
+ return ret;
98
+ }
76
+ }
99
+
77
+
100
+ return ctr(env, csrno);
78
+ return riscv_csrrw_do64(env, csrno, ret_value, 0, 0);
101
+}
79
+}
102
+
80
+
103
#if !defined(CONFIG_USER_ONLY)
81
RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
104
static int any(CPURISCVState *env, int csrno)
82
target_ulong *ret_value,
83
target_ulong new_value, target_ulong write_mask)
105
{
84
{
106
return 0;
85
- RISCVException ret = riscv_csrrw_check(env, csrno, write_mask);
86
+ RISCVException ret = riscv_csrrw_check(env, csrno, true);
87
if (ret != RISCV_EXCP_NONE) {
88
return ret;
89
}
90
@@ -XXX,XX +XXX,XX @@ static RISCVException riscv_csrrw_do128(CPURISCVState *env, int csrno,
91
return RISCV_EXCP_NONE;
107
}
92
}
108
93
109
+static int any32(CPURISCVState *env, int csrno)
94
+RISCVException riscv_csrr_i128(CPURISCVState *env, int csrno,
95
+ Int128 *ret_value)
110
+{
96
+{
111
+ if (!riscv_cpu_is_32bit(env)) {
97
+ RISCVException ret;
112
+ return -RISCV_EXCP_ILLEGAL_INST;
98
+
99
+ ret = riscv_csrrw_check(env, csrno, false);
100
+ if (ret != RISCV_EXCP_NONE) {
101
+ return ret;
113
+ }
102
+ }
114
+
103
+
115
+ return any(env, csrno);
104
+ if (csr_ops[csrno].read128) {
105
+ return riscv_csrrw_do128(env, csrno, ret_value,
106
+ int128_zero(), int128_zero());
107
+ }
116
+
108
+
109
+ /*
110
+ * Fall back to 64-bit version for now, if the 128-bit alternative isn't
111
+ * at all defined.
112
+ * Note, some CSRs don't need to extend to MXLEN (64 upper bits non
113
+ * significant), for those, this fallback is correctly handling the
114
+ * accesses
115
+ */
116
+ target_ulong old_value;
117
+ ret = riscv_csrrw_do64(env, csrno, &old_value,
118
+ (target_ulong)0,
119
+ (target_ulong)0);
120
+ if (ret == RISCV_EXCP_NONE && ret_value) {
121
+ *ret_value = int128_make64(old_value);
122
+ }
123
+ return ret;
117
+}
124
+}
118
+
125
+
119
static int smode(CPURISCVState *env, int csrno)
126
RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno,
127
Int128 *ret_value,
128
Int128 new_value, Int128 write_mask)
120
{
129
{
121
return -!riscv_has_ext(env, RVS);
130
RISCVException ret;
122
@@ -XXX,XX +XXX,XX @@ static int hmode(CPURISCVState *env, int csrno)
131
123
return -RISCV_EXCP_ILLEGAL_INST;
132
- ret = riscv_csrrw_check(env, csrno, int128_nz(write_mask));
124
}
133
+ ret = riscv_csrrw_check(env, csrno, true);
125
134
if (ret != RISCV_EXCP_NONE) {
126
+static int hmode32(CPURISCVState *env, int csrno)
135
return ret;
127
+{
136
}
128
+ if (!riscv_cpu_is_32bit(env)) {
137
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
129
+ return 0;
138
index XXXXXXX..XXXXXXX 100644
130
+ }
139
--- a/target/riscv/op_helper.c
131
+
140
+++ b/target/riscv/op_helper.c
132
+ return hmode(env, csrno);
141
@@ -XXX,XX +XXX,XX @@ target_ulong helper_csrr(CPURISCVState *env, int csr)
133
+
142
}
134
+}
143
135
+
144
target_ulong val = 0;
136
static int pmp(CPURISCVState *env, int csrno)
145
- RISCVException ret = riscv_csrrw(env, csr, &val, 0, 0);
146
+ RISCVException ret = riscv_csrr(env, csr, &val);
147
148
if (ret != RISCV_EXCP_NONE) {
149
riscv_raise_exception(env, ret, GETPC());
150
@@ -XXX,XX +XXX,XX @@ target_ulong helper_csrrw(CPURISCVState *env, int csr,
151
target_ulong helper_csrr_i128(CPURISCVState *env, int csr)
137
{
152
{
138
return -!riscv_feature(env, RISCV_FEATURE_PMP);
153
Int128 rv = int128_zero();
139
@@ -XXX,XX +XXX,XX @@ static int read_instret(CPURISCVState *env, int csrno, target_ulong *val)
154
- RISCVException ret = riscv_csrrw_i128(env, csr, &rv,
140
return 0;
155
- int128_zero(),
141
}
156
- int128_zero());
142
157
+ RISCVException ret = riscv_csrr_i128(env, csr, &rv);
143
-#if defined(TARGET_RISCV32)
158
144
static int read_instreth(CPURISCVState *env, int csrno, target_ulong *val)
159
if (ret != RISCV_EXCP_NONE) {
145
{
160
riscv_raise_exception(env, ret, GETPC());
146
#if !defined(CONFIG_USER_ONLY)
147
@@ -XXX,XX +XXX,XX @@ static int read_instreth(CPURISCVState *env, int csrno, target_ulong *val)
148
#endif
149
return 0;
150
}
151
-#endif /* TARGET_RISCV32 */
152
153
#if defined(CONFIG_USER_ONLY)
154
static int read_time(CPURISCVState *env, int csrno, target_ulong *val)
155
@@ -XXX,XX +XXX,XX @@ static int read_time(CPURISCVState *env, int csrno, target_ulong *val)
156
return 0;
157
}
158
159
-#if defined(TARGET_RISCV32)
160
static int read_timeh(CPURISCVState *env, int csrno, target_ulong *val)
161
{
162
*val = cpu_get_host_ticks() >> 32;
163
return 0;
164
}
165
-#endif
166
167
#else /* CONFIG_USER_ONLY */
168
169
@@ -XXX,XX +XXX,XX @@ static int read_time(CPURISCVState *env, int csrno, target_ulong *val)
170
return 0;
171
}
172
173
-#if defined(TARGET_RISCV32)
174
static int read_timeh(CPURISCVState *env, int csrno, target_ulong *val)
175
{
176
uint64_t delta = riscv_cpu_virt_enabled(env) ? env->htimedelta : 0;
177
@@ -XXX,XX +XXX,XX @@ static int read_timeh(CPURISCVState *env, int csrno, target_ulong *val)
178
*val = (env->rdtime_fn(env->rdtime_fn_arg) + delta) >> 32;
179
return 0;
180
}
181
-#endif
182
183
/* Machine constants */
184
185
@@ -XXX,XX +XXX,XX @@ static const target_ulong sip_writable_mask = SIP_SSIP | MIP_USIP | MIP_UEIP;
186
static const target_ulong hip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP;
187
static const target_ulong vsip_writable_mask = MIP_VSSIP;
188
189
-#if defined(TARGET_RISCV32)
190
-static const char valid_vm_1_10[16] = {
191
+static const char valid_vm_1_10_32[16] = {
192
[VM_1_10_MBARE] = 1,
193
[VM_1_10_SV32] = 1
194
};
195
-#elif defined(TARGET_RISCV64)
196
-static const char valid_vm_1_10[16] = {
197
+
198
+static const char valid_vm_1_10_64[16] = {
199
[VM_1_10_MBARE] = 1,
200
[VM_1_10_SV39] = 1,
201
[VM_1_10_SV48] = 1,
202
[VM_1_10_SV57] = 1
203
};
204
-#endif /* CONFIG_USER_ONLY */
205
206
/* Machine Information Registers */
207
static int read_zero(CPURISCVState *env, int csrno, target_ulong *val)
208
@@ -XXX,XX +XXX,XX @@ static int read_mstatus(CPURISCVState *env, int csrno, target_ulong *val)
209
210
static int validate_vm(CPURISCVState *env, target_ulong vm)
211
{
212
- return valid_vm_1_10[vm & 0xf];
213
+ if (riscv_cpu_is_32bit(env)) {
214
+ return valid_vm_1_10_32[vm & 0xf];
215
+ } else {
216
+ return valid_vm_1_10_64[vm & 0xf];
217
+ }
218
}
219
220
static int write_mstatus(CPURISCVState *env, int csrno, target_ulong val)
221
@@ -XXX,XX +XXX,XX @@ static int write_mstatus(CPURISCVState *env, int csrno, target_ulong val)
222
MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM |
223
MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TVM | MSTATUS_TSR |
224
MSTATUS_TW;
225
-#if defined(TARGET_RISCV64)
226
- /*
227
- * RV32: MPV and GVA are not in mstatus. The current plan is to
228
- * add them to mstatush. For now, we just don't support it.
229
- */
230
- mask |= MSTATUS_MPV | MSTATUS_GVA;
231
-#endif
232
+
233
+ if (!riscv_cpu_is_32bit(env)) {
234
+ /*
235
+ * RV32: MPV and GVA are not in mstatus. The current plan is to
236
+ * add them to mstatush. For now, we just don't support it.
237
+ */
238
+ mask |= MSTATUS_MPV | MSTATUS_GVA;
239
+ }
240
241
mstatus = (mstatus & ~mask) | (val & mask);
242
243
@@ -XXX,XX +XXX,XX @@ static int write_mstatus(CPURISCVState *env, int csrno, target_ulong val)
244
return 0;
245
}
246
247
-#ifdef TARGET_RISCV32
248
static int read_mstatush(CPURISCVState *env, int csrno, target_ulong *val)
249
{
250
*val = env->mstatus >> 32;
251
@@ -XXX,XX +XXX,XX @@ static int write_mstatush(CPURISCVState *env, int csrno, target_ulong val)
252
253
return 0;
254
}
255
-#endif
256
257
static int read_misa(CPURISCVState *env, int csrno, target_ulong *val)
258
{
259
@@ -XXX,XX +XXX,XX @@ static int write_satp(CPURISCVState *env, int csrno, target_ulong val)
260
static int read_hstatus(CPURISCVState *env, int csrno, target_ulong *val)
261
{
262
*val = env->hstatus;
263
-#ifdef TARGET_RISCV64
264
- /* We only support 64-bit VSXL */
265
- *val = set_field(*val, HSTATUS_VSXL, 2);
266
-#endif
267
+ if (!riscv_cpu_is_32bit(env)) {
268
+ /* We only support 64-bit VSXL */
269
+ *val = set_field(*val, HSTATUS_VSXL, 2);
270
+ }
271
/* We only support little endian */
272
*val = set_field(*val, HSTATUS_VSBE, 0);
273
return 0;
274
@@ -XXX,XX +XXX,XX @@ static int read_hstatus(CPURISCVState *env, int csrno, target_ulong *val)
275
static int write_hstatus(CPURISCVState *env, int csrno, target_ulong val)
276
{
277
env->hstatus = val;
278
-#ifdef TARGET_RISCV64
279
- if (get_field(val, HSTATUS_VSXL) != 2) {
280
+ if (!riscv_cpu_is_32bit(env) && get_field(val, HSTATUS_VSXL) != 2) {
281
qemu_log_mask(LOG_UNIMP, "QEMU does not support mixed HSXLEN options.");
282
}
283
-#endif
284
if (get_field(val, HSTATUS_VSBE) != 0) {
285
qemu_log_mask(LOG_UNIMP, "QEMU does not support big endian guests.");
286
}
287
@@ -XXX,XX +XXX,XX @@ static int read_htimedelta(CPURISCVState *env, int csrno, target_ulong *val)
288
return -RISCV_EXCP_ILLEGAL_INST;
289
}
290
291
-#if defined(TARGET_RISCV32)
292
- *val = env->htimedelta & 0xffffffff;
293
-#else
294
*val = env->htimedelta;
295
-#endif
296
return 0;
297
}
298
299
@@ -XXX,XX +XXX,XX @@ static int write_htimedelta(CPURISCVState *env, int csrno, target_ulong val)
300
return -RISCV_EXCP_ILLEGAL_INST;
301
}
302
303
-#if defined(TARGET_RISCV32)
304
- env->htimedelta = deposit64(env->htimedelta, 0, 32, (uint64_t)val);
305
-#else
306
- env->htimedelta = val;
307
-#endif
308
+ if (riscv_cpu_is_32bit(env)) {
309
+ env->htimedelta = deposit64(env->htimedelta, 0, 32, (uint64_t)val);
310
+ } else {
311
+ env->htimedelta = val;
312
+ }
313
return 0;
314
}
315
316
-#if defined(TARGET_RISCV32)
317
static int read_htimedeltah(CPURISCVState *env, int csrno, target_ulong *val)
318
{
319
if (!env->rdtime_fn) {
320
@@ -XXX,XX +XXX,XX @@ static int write_htimedeltah(CPURISCVState *env, int csrno, target_ulong val)
321
env->htimedelta = deposit64(env->htimedelta, 32, 32, (uint64_t)val);
322
return 0;
323
}
324
-#endif
325
326
/* Virtual CSR Registers */
327
static int read_vsstatus(CPURISCVState *env, int csrno, target_ulong *val)
328
@@ -XXX,XX +XXX,XX @@ static riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
329
/* User Timers and Counters */
330
[CSR_CYCLE] = { ctr, read_instret },
331
[CSR_INSTRET] = { ctr, read_instret },
332
-#if defined(TARGET_RISCV32)
333
- [CSR_CYCLEH] = { ctr, read_instreth },
334
- [CSR_INSTRETH] = { ctr, read_instreth },
335
-#endif
336
+ [CSR_CYCLEH] = { ctr32, read_instreth },
337
+ [CSR_INSTRETH] = { ctr32, read_instreth },
338
339
/* In privileged mode, the monitor will have to emulate TIME CSRs only if
340
* rdtime callback is not provided by machine/platform emulation */
341
[CSR_TIME] = { ctr, read_time },
342
-#if defined(TARGET_RISCV32)
343
- [CSR_TIMEH] = { ctr, read_timeh },
344
-#endif
345
+ [CSR_TIMEH] = { ctr32, read_timeh },
346
347
#if !defined(CONFIG_USER_ONLY)
348
/* Machine Timers and Counters */
349
[CSR_MCYCLE] = { any, read_instret },
350
[CSR_MINSTRET] = { any, read_instret },
351
-#if defined(TARGET_RISCV32)
352
- [CSR_MCYCLEH] = { any, read_instreth },
353
- [CSR_MINSTRETH] = { any, read_instreth },
354
-#endif
355
+ [CSR_MCYCLEH] = { any32, read_instreth },
356
+ [CSR_MINSTRETH] = { any32, read_instreth },
357
358
/* Machine Information Registers */
359
[CSR_MVENDORID] = { any, read_zero },
360
@@ -XXX,XX +XXX,XX @@ static riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
361
[CSR_MTVEC] = { any, read_mtvec, write_mtvec },
362
[CSR_MCOUNTEREN] = { any, read_mcounteren, write_mcounteren },
363
364
-#if defined(TARGET_RISCV32)
365
- [CSR_MSTATUSH] = { any, read_mstatush, write_mstatush },
366
-#endif
367
+ [CSR_MSTATUSH] = { any32, read_mstatush, write_mstatush },
368
369
[CSR_MSCOUNTEREN] = { any, read_mscounteren, write_mscounteren },
370
371
@@ -XXX,XX +XXX,XX @@ static riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
372
[CSR_HGEIP] = { hmode, read_hgeip, write_hgeip },
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[CSR_HGATP] = { hmode, read_hgatp, write_hgatp },
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[CSR_HTIMEDELTA] = { hmode, read_htimedelta, write_htimedelta },
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-#if defined(TARGET_RISCV32)
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- [CSR_HTIMEDELTAH] = { hmode, read_htimedeltah, write_htimedeltah},
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-#endif
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+ [CSR_HTIMEDELTAH] = { hmode32, read_htimedeltah, write_htimedeltah},
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[CSR_VSSTATUS] = { hmode, read_vsstatus, write_vsstatus },
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[CSR_VSIP] = { hmode, NULL, NULL, rmw_vsip },
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@@ -XXX,XX +XXX,XX @@ static riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
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[CSR_HPMCOUNTER3 ... CSR_HPMCOUNTER31] = { ctr, read_zero },
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[CSR_MHPMCOUNTER3 ... CSR_MHPMCOUNTER31] = { any, read_zero },
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[CSR_MHPMEVENT3 ... CSR_MHPMEVENT31] = { any, read_zero },
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-#if defined(TARGET_RISCV32)
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- [CSR_HPMCOUNTER3H ... CSR_HPMCOUNTER31H] = { ctr, read_zero },
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- [CSR_MHPMCOUNTER3H ... CSR_MHPMCOUNTER31H] = { any, read_zero },
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-#endif
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+ [CSR_HPMCOUNTER3H ... CSR_HPMCOUNTER31H] = { ctr32, read_zero },
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+ [CSR_MHPMCOUNTER3H ... CSR_MHPMCOUNTER31H] = { any32, read_zero },
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#endif /* !CONFIG_USER_ONLY */
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};
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--
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--
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2.29.2
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2.45.1
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Patchew 2.1-devel-b67e4c2

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