[PULL 00/23] riscv-to-apply queue
[PULL 0/2] riscv-to-apply queue
1
The following changes since commit 75ee62ac606bfc9eb59310b9446df3434bf6e8c2:
1
From: Alistair Francis <alistair.francis@wdc.com>
2
2
3
Merge remote-tracking branch 'remotes/ehabkost-gl/tags/x86-next-pull-request' into staging (2020-12-17 18:53:36 +0000)
3
The following changes since commit c5fbdd60cf1fb52f01bdfe342b6fa65d5343e1b1:
4
5
Merge tag 'qemu-sparc-20211121' of git://github.com/mcayland/qemu into staging (2021-11-21 14:12:25 +0100)
4
6
5
are available in the Git repository at:
7
are available in the Git repository at:
6
8
7
git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20201217-1
9
git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20211122
8
10
9
for you to fetch changes up to d31e970a01e7399b9cd43ec0dc00c857d968987e:
11
for you to fetch changes up to 526e7443027c71fe7b04c29df529e1f9f425f9e3:
10
12
11
riscv/opentitan: Update the OpenTitan memory layout (2020-12-17 21:56:44 -0800)
13
hw/misc/sifive_u_otp: Do not reset OTP content on hardware reset (2021-11-22 10:46:22 +1000)
12
14
13
----------------------------------------------------------------
15
----------------------------------------------------------------
14
A collection of RISC-V improvements:
16
Seventh RISC-V PR for QEMU 6.2
15
- Improve the sifive_u DTB generation
17
16
- Add QSPI NOR flash to Microchip PFSoC
18
- Deprecate IF_NONE for SiFive OTP
17
- Fix a bug in the Hypervisor HLVX/HLV/HSV instructions
19
- Don't reset SiFive OTP content
18
- Fix some mstatus mask defines
19
- Ibex PLIC improvements
20
- OpenTitan memory layout update
21
- Initial steps towards support for 32-bit CPUs on 64-bit builds
22
20
23
----------------------------------------------------------------
21
----------------------------------------------------------------
24
Alex Richardson (1):
22
Philippe Mathieu-Daudé (1):
25
target/riscv: Fix definition of MSTATUS_TW and MSTATUS_TSR
23
hw/misc/sifive_u_otp: Do not reset OTP content on hardware reset
26
24
27
Alistair Francis (18):
25
Thomas Huth (1):
28
intc/ibex_plic: Clear interrupts that occur during claim process
26
hw/misc/sifive_u_otp: Use IF_PFLASH for the OTP device instead of IF_NONE
29
hw/riscv: Expand the is 32-bit check to support more CPUs
30
target/riscv: Add a TYPE_RISCV_CPU_BASE CPU
31
riscv: spike: Remove target macro conditionals
32
riscv: virt: Remove target macro conditionals
33
hw/riscv: boot: Remove compile time XLEN checks
34
hw/riscv: virt: Remove compile time XLEN checks
35
hw/riscv: spike: Remove compile time XLEN checks
36
hw/riscv: sifive_u: Remove compile time XLEN checks
37
target/riscv: fpu_helper: Match function defs in HELPER macros
38
target/riscv: Add a riscv_cpu_is_32bit() helper function
39
target/riscv: Specify the XLEN for CPUs
40
target/riscv: cpu: Remove compile time XLEN checks
41
target/riscv: cpu_helper: Remove compile time XLEN checks
42
target/riscv: csr: Remove compile time XLEN checks
43
target/riscv: cpu: Set XLEN independently from target
44
hw/riscv: Use the CPU to determine if 32-bit
45
riscv/opentitan: Update the OpenTitan memory layout
46
27
47
Anup Patel (1):
28
docs/about/deprecated.rst | 6 ++++++
48
hw/riscv: sifive_u: Add UART1 DT node in the generated DTB
29
hw/misc/sifive_u_otp.c | 22 +++++++++++++---------
30
2 files changed, 19 insertions(+), 9 deletions(-)
49
31
50
Vitaly Wool (1):
51
hw/riscv: microchip_pfsoc: add QSPI NOR flash
52
53
Xinhao Zhang (1):
54
hw/core/register.c: Don't use '#' flag of printf format
55
56
Yifei Jiang (1):
57
target/riscv: Fix the bug of HLVX/HLV/HSV
58
59
include/hw/riscv/boot.h | 14 +--
60
include/hw/riscv/microchip_pfsoc.h | 3 +
61
include/hw/riscv/opentitan.h | 23 +++--
62
include/hw/riscv/spike.h | 6 --
63
include/hw/riscv/virt.h | 6 --
64
target/riscv/cpu.h | 8 ++
65
target/riscv/cpu_bits.h | 8 +-
66
target/riscv/helper.h | 24 ++---
67
hw/core/register.c | 16 ++--
68
hw/intc/ibex_plic.c | 13 ++-
69
hw/riscv/boot.c | 70 ++++++++-------
70
hw/riscv/microchip_pfsoc.c | 21 +++++
71
hw/riscv/opentitan.c | 81 ++++++++++++-----
72
hw/riscv/sifive_u.c | 74 ++++++++++------
73
hw/riscv/spike.c | 52 ++++++-----
74
hw/riscv/virt.c | 39 ++++----
75
target/riscv/cpu.c | 84 ++++++++++++------
76
target/riscv/cpu_helper.c | 15 ++--
77
target/riscv/csr.c | 176 +++++++++++++++++++------------------
78
target/riscv/fpu_helper.c | 8 --
79
20 files changed, 434 insertions(+), 307 deletions(-)
80
diff view generated by jsdifflib
[PULL 01/23] hw/riscv: sifive_u: Add UART1 DT node in the generated DTB
[PULL 1/2] hw/misc/sifive_u_otp: Use IF_PFLASH for the OTP device instead of IF_NONE
1
From: Anup Patel <anup.patel@wdc.com>
1
From: Thomas Huth <thuth@redhat.com>
2
2
3
The sifive_u machine emulates two UARTs but we have only UART0 DT
3
Configuring a drive with "if=none" is meant for creation of a backend
4
node in the generated DTB so this patch adds UART1 DT node in the
4
only, it should not get automatically assigned to a device frontend.
5
generated DTB.
5
Use "if=pflash" for the One-Time-Programmable device instead (like
6
it is e.g. also done for the efuse device in hw/arm/xlnx-zcu102.c).
6
7
7
Signed-off-by: Anup Patel <anup.patel@wdc.com>
8
Since the old way of configuring the device has already been published
9
with the previous QEMU versions, we cannot remove this immediately, but
10
have to deprecate it and support it for at least two more releases.
11
12
Signed-off-by: Thomas Huth <thuth@redhat.com>
13
Acked-by: Philippe Mathieu-Daudé <philmd@redhat.com>
14
Reviewed-by: Markus Armbruster <armbru@redhat.com>
8
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
15
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
9
Message-id: 20201111094725.3768755-1-anup.patel@wdc.com
16
Message-id: 20211119102549.217755-1-thuth@redhat.com
10
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
17
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
11
---
18
---
12
hw/riscv/sifive_u.c | 15 +++++++++++++++
19
docs/about/deprecated.rst | 6 ++++++
13
1 file changed, 15 insertions(+)
20
hw/misc/sifive_u_otp.c | 9 ++++++++-
21
2 files changed, 14 insertions(+), 1 deletion(-)
14
22
15
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
23
diff --git a/docs/about/deprecated.rst b/docs/about/deprecated.rst
16
index XXXXXXX..XXXXXXX 100644
24
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/riscv/sifive_u.c
25
--- a/docs/about/deprecated.rst
18
+++ b/hw/riscv/sifive_u.c
26
+++ b/docs/about/deprecated.rst
19
@@ -XXX,XX +XXX,XX @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
27
@@ -XXX,XX +XXX,XX @@ as short-form boolean values, and passed to plugins as ``arg_name=on``.
20
qemu_fdt_setprop_cell(fdt, nodename, "reg", 0x0);
28
However, short-form booleans are deprecated and full explicit ``arg_name=on``
21
g_free(nodename);
29
form is preferred.
22
30
23
+ nodename = g_strdup_printf("/soc/serial@%lx",
31
+``-drive if=none`` for the sifive_u OTP device (since 6.2)
24
+ (long)memmap[SIFIVE_U_DEV_UART1].base);
32
+''''''''''''''''''''''''''''''''''''''''''''''''''''''''''
25
+ qemu_fdt_add_subnode(fdt, nodename);
26
+ qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,uart0");
27
+ qemu_fdt_setprop_cells(fdt, nodename, "reg",
28
+ 0x0, memmap[SIFIVE_U_DEV_UART1].base,
29
+ 0x0, memmap[SIFIVE_U_DEV_UART1].size);
30
+ qemu_fdt_setprop_cells(fdt, nodename, "clocks",
31
+ prci_phandle, PRCI_CLK_TLCLK);
32
+ qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
33
+ qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_UART1_IRQ);
34
+
33
+
35
+ qemu_fdt_setprop_string(fdt, "/aliases", "serial1", nodename);
34
+Using ``-drive if=none`` to configure the OTP device of the sifive_u
36
+ g_free(nodename);
35
+RISC-V machine is deprecated. Use ``-drive if=pflash`` instead.
37
+
36
+
38
nodename = g_strdup_printf("/soc/serial@%lx",
37
39
(long)memmap[SIFIVE_U_DEV_UART0].base);
38
QEMU Machine Protocol (QMP) commands
40
qemu_fdt_add_subnode(fdt, nodename);
39
------------------------------------
40
diff --git a/hw/misc/sifive_u_otp.c b/hw/misc/sifive_u_otp.c
41
index XXXXXXX..XXXXXXX 100644
42
--- a/hw/misc/sifive_u_otp.c
43
+++ b/hw/misc/sifive_u_otp.c
44
@@ -XXX,XX +XXX,XX @@ static void sifive_u_otp_realize(DeviceState *dev, Error **errp)
45
TYPE_SIFIVE_U_OTP, SIFIVE_U_OTP_REG_SIZE);
46
sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->mmio);
47
48
- dinfo = drive_get_next(IF_NONE);
49
+ dinfo = drive_get_next(IF_PFLASH);
50
+ if (!dinfo) {
51
+ dinfo = drive_get_next(IF_NONE);
52
+ if (dinfo) {
53
+ warn_report("using \"-drive if=none\" for the OTP is deprecated, "
54
+ "use \"-drive if=pflash\" instead.");
55
+ }
56
+ }
57
if (dinfo) {
58
int ret;
59
uint64_t perm;
41
--
60
--
42
2.29.2
61
2.31.1
43
62
44
63
diff view generated by jsdifflib
[PULL 02/23] hw/riscv: microchip_pfsoc: add QSPI NOR flash
[PULL 2/2] hw/misc/sifive_u_otp: Do not reset OTP content on hardware reset
1
From: Vitaly Wool <vitaly.wool@konsulko.com>
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
2
3
Add QSPI NOR flash definition for Microchip PolarFire SoC.
3
Once a "One Time Programmable" is programmed, it shouldn't be reset.
4
4
5
Signed-off-by: Vitaly Wool <vitaly.wool@konsulko.com>
5
Do not re-initialize the OTP content in the DeviceReset handler,
6
Acked-by: Alistair Francis <alistair.francis@wdc.com>
6
initialize it once in the DeviceRealize one.
7
Reviewed-by: Bin Meng <bin.meng@windriver.com>
7
8
Message-id: 20201112074950.33283-1-vitaly.wool@konsulko.com
8
Fixes: 9fb45c62ae8 ("riscv: sifive: Implement a model for SiFive FU540 OTP")
9
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
10
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
11
Message-Id: <20211119104757.331579-1-f4bug@amsat.org>
9
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
12
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
10
---
13
---
11
include/hw/riscv/microchip_pfsoc.h | 3 +++
14
hw/misc/sifive_u_otp.c | 13 +++++--------
12
hw/riscv/microchip_pfsoc.c | 21 +++++++++++++++++++++
15
1 file changed, 5 insertions(+), 8 deletions(-)
13
2 files changed, 24 insertions(+)
14
16
15
diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h
17
diff --git a/hw/misc/sifive_u_otp.c b/hw/misc/sifive_u_otp.c
16
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
17
--- a/include/hw/riscv/microchip_pfsoc.h
19
--- a/hw/misc/sifive_u_otp.c
18
+++ b/include/hw/riscv/microchip_pfsoc.h
20
+++ b/hw/misc/sifive_u_otp.c
19
@@ -XXX,XX +XXX,XX @@ enum {
21
@@ -XXX,XX +XXX,XX @@ static void sifive_u_otp_realize(DeviceState *dev, Error **errp)
20
MICROCHIP_PFSOC_MMUART2,
22
21
MICROCHIP_PFSOC_MMUART3,
23
if (blk_pread(s->blk, 0, s->fuse, filesize) != filesize) {
22
MICROCHIP_PFSOC_MMUART4,
24
error_setg(errp, "failed to read the initial flash content");
23
+ MICROCHIP_PFSOC_SPI0,
25
+ return;
24
+ MICROCHIP_PFSOC_SPI1,
26
}
25
MICROCHIP_PFSOC_I2C1,
27
}
26
MICROCHIP_PFSOC_GEM0,
28
}
27
MICROCHIP_PFSOC_GEM1,
29
-}
28
@@ -XXX,XX +XXX,XX @@ enum {
30
-
29
MICROCHIP_PFSOC_GPIO2,
31
-static void sifive_u_otp_reset(DeviceState *dev)
30
MICROCHIP_PFSOC_ENVM_CFG,
32
-{
31
MICROCHIP_PFSOC_ENVM_DATA,
33
- SiFiveUOTPState *s = SIFIVE_U_OTP(dev);
32
+ MICROCHIP_PFSOC_QSPI_XIP,
34
33
MICROCHIP_PFSOC_IOSCB,
35
/* Initialize all fuses' initial value to 0xFFs */
34
MICROCHIP_PFSOC_DRAM_LO,
36
memset(s->fuse, 0xff, sizeof(s->fuse));
35
MICROCHIP_PFSOC_DRAM_LO_ALIAS,
37
@@ -XXX,XX +XXX,XX @@ static void sifive_u_otp_reset(DeviceState *dev)
36
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
38
serial_data = s->serial;
37
index XXXXXXX..XXXXXXX 100644
39
if (blk_pwrite(s->blk, index * SIFIVE_U_OTP_FUSE_WORD,
38
--- a/hw/riscv/microchip_pfsoc.c
40
&serial_data, SIFIVE_U_OTP_FUSE_WORD, 0) < 0) {
39
+++ b/hw/riscv/microchip_pfsoc.c
41
- error_report("write error index<%d>", index);
40
@@ -XXX,XX +XXX,XX @@ static const struct MemmapEntry {
42
+ error_setg(errp, "failed to write index<%d>", index);
41
[MICROCHIP_PFSOC_MMUART2] = { 0x20102000, 0x1000 },
43
+ return;
42
[MICROCHIP_PFSOC_MMUART3] = { 0x20104000, 0x1000 },
44
}
43
[MICROCHIP_PFSOC_MMUART4] = { 0x20106000, 0x1000 },
45
44
+ [MICROCHIP_PFSOC_SPI0] = { 0x20108000, 0x1000 },
46
serial_data = ~(s->serial);
45
+ [MICROCHIP_PFSOC_SPI1] = { 0x20109000, 0x1000 },
47
if (blk_pwrite(s->blk, (index + 1) * SIFIVE_U_OTP_FUSE_WORD,
46
[MICROCHIP_PFSOC_I2C1] = { 0x2010b000, 0x1000 },
48
&serial_data, SIFIVE_U_OTP_FUSE_WORD, 0) < 0) {
47
[MICROCHIP_PFSOC_GEM0] = { 0x20110000, 0x2000 },
49
- error_report("write error index<%d>", index + 1);
48
[MICROCHIP_PFSOC_GEM1] = { 0x20112000, 0x2000 },
50
+ error_setg(errp, "failed to write index<%d>", index + 1);
49
@@ -XXX,XX +XXX,XX @@ static const struct MemmapEntry {
51
+ return;
50
[MICROCHIP_PFSOC_GPIO2] = { 0x20122000, 0x1000 },
52
}
51
[MICROCHIP_PFSOC_ENVM_CFG] = { 0x20200000, 0x1000 },
53
}
52
[MICROCHIP_PFSOC_ENVM_DATA] = { 0x20220000, 0x20000 },
54
53
+ [MICROCHIP_PFSOC_QSPI_XIP] = { 0x21000000, 0x1000000 },
55
@@ -XXX,XX +XXX,XX @@ static void sifive_u_otp_class_init(ObjectClass *klass, void *data)
54
[MICROCHIP_PFSOC_IOSCB] = { 0x30000000, 0x10000000 },
56
55
[MICROCHIP_PFSOC_DRAM_LO] = { 0x80000000, 0x40000000 },
57
device_class_set_props(dc, sifive_u_otp_properties);
56
[MICROCHIP_PFSOC_DRAM_LO_ALIAS] = { 0xc0000000, 0x40000000 },
58
dc->realize = sifive_u_otp_realize;
57
@@ -XXX,XX +XXX,XX @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
59
- dc->reset = sifive_u_otp_reset;
58
MemoryRegion *e51_dtim_mem = g_new(MemoryRegion, 1);
59
MemoryRegion *l2lim_mem = g_new(MemoryRegion, 1);
60
MemoryRegion *envm_data = g_new(MemoryRegion, 1);
61
+ MemoryRegion *qspi_xip_mem = g_new(MemoryRegion, 1);
62
char *plic_hart_config;
63
size_t plic_hart_config_len;
64
NICInfo *nd;
65
@@ -XXX,XX +XXX,XX @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
66
qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART4_IRQ),
67
serial_hd(4));
68
69
+ /* SPI */
70
+ create_unimplemented_device("microchip.pfsoc.spi0",
71
+ memmap[MICROCHIP_PFSOC_SPI0].base,
72
+ memmap[MICROCHIP_PFSOC_SPI0].size);
73
+ create_unimplemented_device("microchip.pfsoc.spi1",
74
+ memmap[MICROCHIP_PFSOC_SPI1].base,
75
+ memmap[MICROCHIP_PFSOC_SPI1].size);
76
+
77
/* I2C1 */
78
create_unimplemented_device("microchip.pfsoc.i2c1",
79
memmap[MICROCHIP_PFSOC_I2C1].base,
80
@@ -XXX,XX +XXX,XX @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
81
sysbus_realize(SYS_BUS_DEVICE(&s->ioscb), errp);
82
sysbus_mmio_map(SYS_BUS_DEVICE(&s->ioscb), 0,
83
memmap[MICROCHIP_PFSOC_IOSCB].base);
84
+
85
+ /* QSPI Flash */
86
+ memory_region_init_rom(qspi_xip_mem, OBJECT(dev),
87
+ "microchip.pfsoc.qspi_xip",
88
+ memmap[MICROCHIP_PFSOC_QSPI_XIP].size,
89
+ &error_fatal);
90
+ memory_region_add_subregion(system_memory,
91
+ memmap[MICROCHIP_PFSOC_QSPI_XIP].base,
92
+ qspi_xip_mem);
93
}
60
}
94
61
95
static void microchip_pfsoc_soc_class_init(ObjectClass *oc, void *data)
62
static const TypeInfo sifive_u_otp_info = {
96
--
63
--
97
2.29.2
64
2.31.1
98
65
99
66
diff view generated by jsdifflib
[PULL 03/23] hw/core/register.c: Don't use '#' flag of printf format
Deleted patch
1
From: Xinhao Zhang <zhangxinhao1@huawei.com>
2
1
3
Fix code style. Don't use '#' flag of printf format ('%#') in
4
format strings, use '0x' prefix instead
5
6
Signed-off-by: Xinhao Zhang <zhangxinhao1@huawei.com>
7
Signed-off-by: Kai Deng <dengkai1@huawei.com>
8
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
9
Message-id: 20201116140148.2850128-1-zhangxinhao1@huawei.com
10
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
11
---
12
hw/core/register.c | 16 ++++++++--------
13
1 file changed, 8 insertions(+), 8 deletions(-)
14
15
diff --git a/hw/core/register.c b/hw/core/register.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/core/register.c
18
+++ b/hw/core/register.c
19
@@ -XXX,XX +XXX,XX @@ void register_write(RegisterInfo *reg, uint64_t val, uint64_t we,
20
21
if (!ac || !ac->name) {
22
qemu_log_mask(LOG_GUEST_ERROR, "%s: write to undefined device state "
23
- "(written value: %#" PRIx64 ")\n", prefix, val);
24
+ "(written value: 0x%" PRIx64 ")\n", prefix, val);
25
return;
26
}
27
28
@@ -XXX,XX +XXX,XX @@ void register_write(RegisterInfo *reg, uint64_t val, uint64_t we,
29
test = (old_val ^ val) & ac->rsvd;
30
if (test) {
31
qemu_log_mask(LOG_GUEST_ERROR, "%s: change of value in reserved bit"
32
- "fields: %#" PRIx64 ")\n", prefix, test);
33
+ "fields: 0x%" PRIx64 ")\n", prefix, test);
34
}
35
36
test = val & ac->unimp;
37
if (test) {
38
qemu_log_mask(LOG_UNIMP,
39
- "%s:%s writing %#" PRIx64 " to unimplemented bits:" \
40
- " %#" PRIx64 "\n",
41
+ "%s:%s writing 0x%" PRIx64 " to unimplemented bits:" \
42
+ " 0x%" PRIx64 "\n",
43
prefix, reg->access->name, val, ac->unimp);
44
}
45
46
@@ -XXX,XX +XXX,XX @@ void register_write(RegisterInfo *reg, uint64_t val, uint64_t we,
47
}
48
49
if (debug) {
50
- qemu_log("%s:%s: write of value %#" PRIx64 "\n", prefix, ac->name,
51
+ qemu_log("%s:%s: write of value 0x%" PRIx64 "\n", prefix, ac->name,
52
new_val);
53
}
54
55
@@ -XXX,XX +XXX,XX @@ uint64_t register_read(RegisterInfo *reg, uint64_t re, const char* prefix,
56
}
57
58
if (debug) {
59
- qemu_log("%s:%s: read of value %#" PRIx64 "\n", prefix,
60
+ qemu_log("%s:%s: read of value 0x%" PRIx64 "\n", prefix,
61
ac->name, ret);
62
}
63
64
@@ -XXX,XX +XXX,XX @@ void register_write_memory(void *opaque, hwaddr addr,
65
66
if (!reg) {
67
qemu_log_mask(LOG_GUEST_ERROR, "%s: write to unimplemented register " \
68
- "at address: %#" PRIx64 "\n", reg_array->prefix, addr);
69
+ "at address: 0x%" PRIx64 "\n", reg_array->prefix, addr);
70
return;
71
}
72
73
@@ -XXX,XX +XXX,XX @@ uint64_t register_read_memory(void *opaque, hwaddr addr,
74
75
if (!reg) {
76
qemu_log_mask(LOG_GUEST_ERROR, "%s: read to unimplemented register " \
77
- "at address: %#" PRIx64 "\n", reg_array->prefix, addr);
78
+ "at address: 0x%" PRIx64 "\n", reg_array->prefix, addr);
79
return 0;
80
}
81
82
--
83
2.29.2
84
85
diff view generated by jsdifflib
[PULL 04/23] target/riscv: Fix the bug of HLVX/HLV/HSV
Deleted patch
1
From: Yifei Jiang <jiangyifei@huawei.com>
2
1
3
We found that the hypervisor virtual-machine load and store instructions,
4
included HLVX/HLV/HSV, couldn't access guest userspace memory.
5
6
In the riscv-privileged spec, HLVX/HLV/HSV is defined as follow:
7
"As usual when V=1, two-stage address translation is applied, and
8
the HS-level sstatus.SUM is ignored."
9
10
But get_physical_address() doesn't ignore sstatus.SUM, when HLVX/HLV/HSV
11
accesses guest userspace memory. So this patch fixes it.
12
13
Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
14
Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com>
15
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
16
Message-id: 20201130012810.899-1-jiangyifei@huawei.com
17
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
18
---
19
target/riscv/cpu_helper.c | 3 ++-
20
1 file changed, 2 insertions(+), 1 deletion(-)
21
22
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
23
index XXXXXXX..XXXXXXX 100644
24
--- a/target/riscv/cpu_helper.c
25
+++ b/target/riscv/cpu_helper.c
26
@@ -XXX,XX +XXX,XX @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
27
vm = get_field(env->hgatp, HGATP_MODE);
28
widened = 2;
29
}
30
- sum = get_field(env->mstatus, MSTATUS_SUM);
31
+ /* status.SUM will be ignored if execute on background */
32
+ sum = get_field(env->mstatus, MSTATUS_SUM) || use_background;
33
switch (vm) {
34
case VM_1_10_SV32:
35
levels = 2; ptidxbits = 10; ptesize = 4; break;
36
--
37
2.29.2
38
39
diff view generated by jsdifflib
[PULL 05/23] target/riscv: Fix definition of MSTATUS_TW and MSTATUS_TSR
Deleted patch
1
From: Alex Richardson <Alexander.Richardson@cl.cam.ac.uk>
2
1
3
The TW and TSR fields should be bits 21 and 22 and not 30/29.
4
This was found while comparing QEMU behaviour against the sail formal
5
model (https://github.com/rems-project/sail-riscv/).
6
7
Signed-off-by: Alex Richardson <Alexander.Richardson@cl.cam.ac.uk>
8
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
9
Message-id: 20201130170117.71281-1-Alexander.Richardson@cl.cam.ac.uk
10
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
11
---
12
target/riscv/cpu_bits.h | 4 ++--
13
1 file changed, 2 insertions(+), 2 deletions(-)
14
15
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
16
index XXXXXXX..XXXXXXX 100644
17
--- a/target/riscv/cpu_bits.h
18
+++ b/target/riscv/cpu_bits.h
19
@@ -XXX,XX +XXX,XX @@
20
#define MSTATUS_MXR 0x00080000
21
#define MSTATUS_VM 0x1F000000 /* until: priv-1.9.1 */
22
#define MSTATUS_TVM 0x00100000 /* since: priv-1.10 */
23
-#define MSTATUS_TW 0x20000000 /* since: priv-1.10 */
24
-#define MSTATUS_TSR 0x40000000 /* since: priv-1.10 */
25
+#define MSTATUS_TW 0x00200000 /* since: priv-1.10 */
26
+#define MSTATUS_TSR 0x00400000 /* since: priv-1.10 */
27
#define MSTATUS_GVA 0x4000000000ULL
28
#define MSTATUS_MPV 0x8000000000ULL
29
30
--
31
2.29.2
32
33
diff view generated by jsdifflib
[PULL 06/23] intc/ibex_plic: Clear interrupts that occur during claim process
Deleted patch
1
Previously if an interrupt occured during the claim process (after the
2
interrupt is claimed but before it's completed) it would never be
3
cleared.
4
This patch ensures that we also clear the hidden_pending bits as well.
5
1
6
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
7
Tested-by: Jackie Ke <jackieke724@hotmail.com>
8
Message-id: 4e9786084a86f220689123cc8a7837af8fa071cf.1607100423.git.alistair.francis@wdc.com
9
---
10
hw/intc/ibex_plic.c | 13 ++++++++++---
11
1 file changed, 10 insertions(+), 3 deletions(-)
12
13
diff --git a/hw/intc/ibex_plic.c b/hw/intc/ibex_plic.c
14
index XXXXXXX..XXXXXXX 100644
15
--- a/hw/intc/ibex_plic.c
16
+++ b/hw/intc/ibex_plic.c
17
@@ -XXX,XX +XXX,XX @@ static void ibex_plic_irqs_set_pending(IbexPlicState *s, int irq, bool level)
18
{
19
int pending_num = irq / 32;
20
21
+ if (!level) {
22
+ /*
23
+ * If the level is low make sure we clear the hidden_pending.
24
+ */
25
+ s->hidden_pending[pending_num] &= ~(1 << (irq % 32));
26
+ }
27
+
28
if (s->claimed[pending_num] & 1 << (irq % 32)) {
29
/*
30
* The interrupt has been claimed, but not completed.
31
* The pending bit can't be set.
32
+ * Save the pending level for after the interrupt is completed.
33
*/
34
s->hidden_pending[pending_num] |= level << (irq % 32);
35
- return;
36
+ } else {
37
+ s->pending[pending_num] |= level << (irq % 32);
38
}
39
-
40
- s->pending[pending_num] |= level << (irq % 32);
41
}
42
43
static bool ibex_plic_irqs_pending(IbexPlicState *s, uint32_t context)
44
--
45
2.29.2
46
47
diff view generated by jsdifflib
[PULL 07/23] hw/riscv: Expand the is 32-bit check to support more CPUs
Deleted patch
1
Currently the riscv_is_32_bit() function only supports the generic rv32
2
CPUs. Extend the function to support the SiFive and LowRISC CPUs as
3
well.
4
1
5
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
6
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
7
Acked-by: Palmer Dabbelt <palmerdabbelt@google.com>
8
Message-id: 9a13764115ba78688ba61b56526c6de65fc3ef42.1608142916.git.alistair.francis@wdc.com
9
---
10
hw/riscv/boot.c | 12 +++++++++++-
11
1 file changed, 11 insertions(+), 1 deletion(-)
12
13
diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
14
index XXXXXXX..XXXXXXX 100644
15
--- a/hw/riscv/boot.c
16
+++ b/hw/riscv/boot.c
17
@@ -XXX,XX +XXX,XX @@
18
19
bool riscv_is_32_bit(MachineState *machine)
20
{
21
- if (!strncmp(machine->cpu_type, "rv32", 4)) {
22
+ /*
23
+ * To determine if the CPU is 32-bit we need to check a few different CPUs.
24
+ *
25
+ * If the CPU starts with rv32
26
+ * If the CPU is a sifive 3 seriries CPU (E31, U34)
27
+ * If it's the Ibex CPU
28
+ */
29
+ if (!strncmp(machine->cpu_type, "rv32", 4) ||
30
+ (!strncmp(machine->cpu_type, "sifive", 6) &&
31
+ machine->cpu_type[8] == '3') ||
32
+ !strncmp(machine->cpu_type, "lowrisc-ibex", 12)) {
33
return true;
34
} else {
35
return false;
36
--
37
2.29.2
38
39
diff view generated by jsdifflib
[PULL 08/23] target/riscv: Add a TYPE_RISCV_CPU_BASE CPU
Deleted patch
1
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2
Reviewed-by: Bin Meng <bin.meng@windriver.com>
3
Tested-by: Bin Meng <bin.meng@windriver.com>
4
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
5
Acked-by: Palmer Dabbelt <palmerdabbelt@google.com>
6
Message-id: 86e5ccd9eae2f5d8c2257679c6ccf6078a5d51af.1608142916.git.alistair.francis@wdc.com
7
---
8
target/riscv/cpu.h | 6 ++++++
9
1 file changed, 6 insertions(+)
10
1
11
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/riscv/cpu.h
14
+++ b/target/riscv/cpu.h
15
@@ -XXX,XX +XXX,XX @@
16
#define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34")
17
#define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54")
18
19
+#if defined(TARGET_RISCV32)
20
+# define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE32
21
+#elif defined(TARGET_RISCV64)
22
+# define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE64
23
+#endif
24
+
25
#define RV32 ((target_ulong)1 << (TARGET_LONG_BITS - 2))
26
#define RV64 ((target_ulong)2 << (TARGET_LONG_BITS - 2))
27
28
--
29
2.29.2
30
31
diff view generated by jsdifflib
[PULL 09/23] riscv: spike: Remove target macro conditionals
Deleted patch
1
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2
Reviewed-by: Bin Meng <bin.meng@windriver.com>
3
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
4
Acked-by: Palmer Dabbelt <palmerdabbelt@google.com>
5
Message-id: 04ac7fba2348c92f296a5e6a9959ac72b77ae4c6.1608142916.git.alistair.francis@wdc.com
6
---
7
include/hw/riscv/spike.h | 6 ------
8
hw/riscv/spike.c | 2 +-
9
2 files changed, 1 insertion(+), 7 deletions(-)
10
1
11
diff --git a/include/hw/riscv/spike.h b/include/hw/riscv/spike.h
12
index XXXXXXX..XXXXXXX 100644
13
--- a/include/hw/riscv/spike.h
14
+++ b/include/hw/riscv/spike.h
15
@@ -XXX,XX +XXX,XX @@ enum {
16
SPIKE_DRAM
17
};
18
19
-#if defined(TARGET_RISCV32)
20
-#define SPIKE_V1_10_0_CPU TYPE_RISCV_CPU_BASE32
21
-#elif defined(TARGET_RISCV64)
22
-#define SPIKE_V1_10_0_CPU TYPE_RISCV_CPU_BASE64
23
-#endif
24
-
25
#endif
26
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
27
index XXXXXXX..XXXXXXX 100644
28
--- a/hw/riscv/spike.c
29
+++ b/hw/riscv/spike.c
30
@@ -XXX,XX +XXX,XX @@ static void spike_machine_class_init(ObjectClass *oc, void *data)
31
mc->init = spike_board_init;
32
mc->max_cpus = SPIKE_CPUS_MAX;
33
mc->is_default = true;
34
- mc->default_cpu_type = SPIKE_V1_10_0_CPU;
35
+ mc->default_cpu_type = TYPE_RISCV_CPU_BASE;
36
mc->possible_cpu_arch_ids = riscv_numa_possible_cpu_arch_ids;
37
mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props;
38
mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id;
39
--
40
2.29.2
41
42
diff view generated by jsdifflib
[PULL 10/23] riscv: virt: Remove target macro conditionals
Deleted patch
1
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2
Reviewed-by: Bin Meng <bin.meng@windriver.com>
3
Tested-by: Bin Meng <bin.meng@windriver.com>
4
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
5
Acked-by: Palmer Dabbelt <palmerdabbelt@google.com>
6
Message-id: aed1174c2efd2f050fa5bd8f524d68795b12c0e4.1608142916.git.alistair.francis@wdc.com
7
---
8
include/hw/riscv/virt.h | 6 ------
9
hw/riscv/virt.c | 2 +-
10
2 files changed, 1 insertion(+), 7 deletions(-)
11
1
12
diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
13
index XXXXXXX..XXXXXXX 100644
14
--- a/include/hw/riscv/virt.h
15
+++ b/include/hw/riscv/virt.h
16
@@ -XXX,XX +XXX,XX @@ enum {
17
#define FDT_INT_MAP_WIDTH (FDT_PCI_ADDR_CELLS + FDT_PCI_INT_CELLS + 1 + \
18
FDT_PLIC_ADDR_CELLS + FDT_PLIC_INT_CELLS)
19
20
-#if defined(TARGET_RISCV32)
21
-#define VIRT_CPU TYPE_RISCV_CPU_BASE32
22
-#elif defined(TARGET_RISCV64)
23
-#define VIRT_CPU TYPE_RISCV_CPU_BASE64
24
-#endif
25
-
26
#endif
27
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
28
index XXXXXXX..XXXXXXX 100644
29
--- a/hw/riscv/virt.c
30
+++ b/hw/riscv/virt.c
31
@@ -XXX,XX +XXX,XX @@ static void virt_machine_class_init(ObjectClass *oc, void *data)
32
mc->desc = "RISC-V VirtIO board";
33
mc->init = virt_machine_init;
34
mc->max_cpus = VIRT_CPUS_MAX;
35
- mc->default_cpu_type = VIRT_CPU;
36
+ mc->default_cpu_type = TYPE_RISCV_CPU_BASE;
37
mc->pci_allow_0_address = true;
38
mc->possible_cpu_arch_ids = riscv_numa_possible_cpu_arch_ids;
39
mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props;
40
--
41
2.29.2
42
43
diff view generated by jsdifflib
[PULL 11/23] hw/riscv: boot: Remove compile time XLEN checks
Deleted patch
1
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2
Reviewed-by: Bin Meng <bin.meng@windriver.com>
3
Tested-by: Bin Meng <bin.meng@windriver.com>
4
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
5
Acked-by: Palmer Dabbelt <palmerdabbelt@google.com>
6
Message-id: 51e9842dbed1acceebad7f97bd3aae69aa1ac19e.1608142916.git.alistair.francis@wdc.com
7
---
8
include/hw/riscv/boot.h | 8 +++---
9
hw/riscv/boot.c | 55 ++++++++++++++++++++++-------------------
10
hw/riscv/sifive_u.c | 2 +-
11
hw/riscv/spike.c | 3 ++-
12
hw/riscv/virt.c | 2 +-
13
5 files changed, 39 insertions(+), 31 deletions(-)
14
1
15
diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h
16
index XXXXXXX..XXXXXXX 100644
17
--- a/include/hw/riscv/boot.h
18
+++ b/include/hw/riscv/boot.h
19
@@ -XXX,XX +XXX,XX @@ target_ulong riscv_load_kernel(const char *kernel_filename,
20
hwaddr riscv_load_initrd(const char *filename, uint64_t mem_size,
21
uint64_t kernel_entry, hwaddr *start);
22
uint32_t riscv_load_fdt(hwaddr dram_start, uint64_t dram_size, void *fdt);
23
-void riscv_setup_rom_reset_vec(hwaddr saddr, hwaddr rom_base,
24
- hwaddr rom_size, uint64_t kernel_entry,
25
+void riscv_setup_rom_reset_vec(MachineState *machine, hwaddr saddr,
26
+ hwaddr rom_base, hwaddr rom_size,
27
+ uint64_t kernel_entry,
28
uint32_t fdt_load_addr, void *fdt);
29
-void riscv_rom_copy_firmware_info(hwaddr rom_base, hwaddr rom_size,
30
+void riscv_rom_copy_firmware_info(MachineState *machine, hwaddr rom_base,
31
+ hwaddr rom_size,
32
uint32_t reset_vec_size,
33
uint64_t kernel_entry);
34
35
diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
36
index XXXXXXX..XXXXXXX 100644
37
--- a/hw/riscv/boot.c
38
+++ b/hw/riscv/boot.c
39
@@ -XXX,XX +XXX,XX @@
40
41
#include <libfdt.h>
42
43
-#if defined(TARGET_RISCV32)
44
-#define fw_dynamic_info_data(__val) cpu_to_le32(__val)
45
-#else
46
-#define fw_dynamic_info_data(__val) cpu_to_le64(__val)
47
-#endif
48
-
49
bool riscv_is_32_bit(MachineState *machine)
50
{
51
/*
52
@@ -XXX,XX +XXX,XX @@ uint32_t riscv_load_fdt(hwaddr dram_base, uint64_t mem_size, void *fdt)
53
return fdt_addr;
54
}
55
56
-void riscv_rom_copy_firmware_info(hwaddr rom_base, hwaddr rom_size,
57
- uint32_t reset_vec_size, uint64_t kernel_entry)
58
+void riscv_rom_copy_firmware_info(MachineState *machine, hwaddr rom_base,
59
+ hwaddr rom_size, uint32_t reset_vec_size,
60
+ uint64_t kernel_entry)
61
{
62
struct fw_dynamic_info dinfo;
63
size_t dinfo_len;
64
65
- dinfo.magic = fw_dynamic_info_data(FW_DYNAMIC_INFO_MAGIC_VALUE);
66
- dinfo.version = fw_dynamic_info_data(FW_DYNAMIC_INFO_VERSION);
67
- dinfo.next_mode = fw_dynamic_info_data(FW_DYNAMIC_INFO_NEXT_MODE_S);
68
- dinfo.next_addr = fw_dynamic_info_data(kernel_entry);
69
+ if (sizeof(dinfo.magic) == 4) {
70
+ dinfo.magic = cpu_to_le32(FW_DYNAMIC_INFO_MAGIC_VALUE);
71
+ dinfo.version = cpu_to_le32(FW_DYNAMIC_INFO_VERSION);
72
+ dinfo.next_mode = cpu_to_le32(FW_DYNAMIC_INFO_NEXT_MODE_S);
73
+ dinfo.next_addr = cpu_to_le32(kernel_entry);
74
+ } else {
75
+ dinfo.magic = cpu_to_le64(FW_DYNAMIC_INFO_MAGIC_VALUE);
76
+ dinfo.version = cpu_to_le64(FW_DYNAMIC_INFO_VERSION);
77
+ dinfo.next_mode = cpu_to_le64(FW_DYNAMIC_INFO_NEXT_MODE_S);
78
+ dinfo.next_addr = cpu_to_le64(kernel_entry);
79
+ }
80
dinfo.options = 0;
81
dinfo.boot_hart = 0;
82
dinfo_len = sizeof(dinfo);
83
@@ -XXX,XX +XXX,XX @@ void riscv_rom_copy_firmware_info(hwaddr rom_base, hwaddr rom_size,
84
&address_space_memory);
85
}
86
87
-void riscv_setup_rom_reset_vec(hwaddr start_addr, hwaddr rom_base,
88
- hwaddr rom_size, uint64_t kernel_entry,
89
+void riscv_setup_rom_reset_vec(MachineState *machine, hwaddr start_addr,
90
+ hwaddr rom_base, hwaddr rom_size,
91
+ uint64_t kernel_entry,
92
uint32_t fdt_load_addr, void *fdt)
93
{
94
int i;
95
uint32_t start_addr_hi32 = 0x00000000;
96
97
- #if defined(TARGET_RISCV64)
98
- start_addr_hi32 = start_addr >> 32;
99
- #endif
100
+ if (!riscv_is_32_bit(machine)) {
101
+ start_addr_hi32 = start_addr >> 32;
102
+ }
103
/* reset vector */
104
uint32_t reset_vec[10] = {
105
0x00000297, /* 1: auipc t0, %pcrel_hi(fw_dyn) */
106
0x02828613, /* addi a2, t0, %pcrel_lo(1b) */
107
0xf1402573, /* csrr a0, mhartid */
108
-#if defined(TARGET_RISCV32)
109
- 0x0202a583, /* lw a1, 32(t0) */
110
- 0x0182a283, /* lw t0, 24(t0) */
111
-#elif defined(TARGET_RISCV64)
112
- 0x0202b583, /* ld a1, 32(t0) */
113
- 0x0182b283, /* ld t0, 24(t0) */
114
-#endif
115
+ 0,
116
+ 0,
117
0x00028067, /* jr t0 */
118
start_addr, /* start: .dword */
119
start_addr_hi32,
120
@@ -XXX,XX +XXX,XX @@ void riscv_setup_rom_reset_vec(hwaddr start_addr, hwaddr rom_base,
121
0x00000000,
122
/* fw_dyn: */
123
};
124
+ if (riscv_is_32_bit(machine)) {
125
+ reset_vec[3] = 0x0202a583; /* lw a1, 32(t0) */
126
+ reset_vec[4] = 0x0182a283; /* lw t0, 24(t0) */
127
+ } else {
128
+ reset_vec[3] = 0x0202b583; /* ld a1, 32(t0) */
129
+ reset_vec[4] = 0x0182b283; /* ld t0, 24(t0) */
130
+ }
131
132
/* copy in the reset vector in little_endian byte order */
133
for (i = 0; i < ARRAY_SIZE(reset_vec); i++) {
134
@@ -XXX,XX +XXX,XX @@ void riscv_setup_rom_reset_vec(hwaddr start_addr, hwaddr rom_base,
135
}
136
rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
137
rom_base, &address_space_memory);
138
- riscv_rom_copy_firmware_info(rom_base, rom_size, sizeof(reset_vec),
139
+ riscv_rom_copy_firmware_info(machine, rom_base, rom_size, sizeof(reset_vec),
140
kernel_entry);
141
142
return;
143
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
144
index XXXXXXX..XXXXXXX 100644
145
--- a/hw/riscv/sifive_u.c
146
+++ b/hw/riscv/sifive_u.c
147
@@ -XXX,XX +XXX,XX @@ static void sifive_u_machine_init(MachineState *machine)
148
rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
149
memmap[SIFIVE_U_DEV_MROM].base, &address_space_memory);
150
151
- riscv_rom_copy_firmware_info(memmap[SIFIVE_U_DEV_MROM].base,
152
+ riscv_rom_copy_firmware_info(machine, memmap[SIFIVE_U_DEV_MROM].base,
153
memmap[SIFIVE_U_DEV_MROM].size,
154
sizeof(reset_vec), kernel_entry);
155
}
156
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
157
index XXXXXXX..XXXXXXX 100644
158
--- a/hw/riscv/spike.c
159
+++ b/hw/riscv/spike.c
160
@@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine)
161
fdt_load_addr = riscv_load_fdt(memmap[SPIKE_DRAM].base,
162
machine->ram_size, s->fdt);
163
/* load the reset vector */
164
- riscv_setup_rom_reset_vec(memmap[SPIKE_DRAM].base, memmap[SPIKE_MROM].base,
165
+ riscv_setup_rom_reset_vec(machine, memmap[SPIKE_DRAM].base,
166
+ memmap[SPIKE_MROM].base,
167
memmap[SPIKE_MROM].size, kernel_entry,
168
fdt_load_addr, s->fdt);
169
170
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
171
index XXXXXXX..XXXXXXX 100644
172
--- a/hw/riscv/virt.c
173
+++ b/hw/riscv/virt.c
174
@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
175
fdt_load_addr = riscv_load_fdt(memmap[VIRT_DRAM].base,
176
machine->ram_size, s->fdt);
177
/* load the reset vector */
178
- riscv_setup_rom_reset_vec(start_addr, virt_memmap[VIRT_MROM].base,
179
+ riscv_setup_rom_reset_vec(machine, start_addr, virt_memmap[VIRT_MROM].base,
180
virt_memmap[VIRT_MROM].size, kernel_entry,
181
fdt_load_addr, s->fdt);
182
183
--
184
2.29.2
185
186
diff view generated by jsdifflib
[PULL 12/23] hw/riscv: virt: Remove compile time XLEN checks
Deleted patch
1
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2
Reviewed-by: Bin Meng <bin.meng@windriver.com>
3
Tested-by: Bin Meng <bin.meng@windriver.com>
4
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
5
Acked-by: Palmer Dabbelt <palmerdabbelt@google.com>
6
Message-id: d7ca1aca672515e6a4aa0d41716238b055f3f25c.1608142916.git.alistair.francis@wdc.com
7
---
8
hw/riscv/virt.c | 32 +++++++++++++++++---------------
9
1 file changed, 17 insertions(+), 15 deletions(-)
10
1
11
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/hw/riscv/virt.c
14
+++ b/hw/riscv/virt.c
15
@@ -XXX,XX +XXX,XX @@
16
#include "hw/pci/pci.h"
17
#include "hw/pci-host/gpex.h"
18
19
-#if defined(TARGET_RISCV32)
20
-# define BIOS_FILENAME "opensbi-riscv32-generic-fw_dynamic.bin"
21
-#else
22
-# define BIOS_FILENAME "opensbi-riscv64-generic-fw_dynamic.bin"
23
-#endif
24
-
25
static const struct MemmapEntry {
26
hwaddr base;
27
hwaddr size;
28
@@ -XXX,XX +XXX,XX @@ static void create_pcie_irq_map(void *fdt, char *nodename,
29
}
30
31
static void create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap,
32
- uint64_t mem_size, const char *cmdline)
33
+ uint64_t mem_size, const char *cmdline, bool is_32_bit)
34
{
35
void *fdt;
36
int i, cpu, socket;
37
@@ -XXX,XX +XXX,XX @@ static void create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap,
38
cpu_name = g_strdup_printf("/cpus/cpu@%d",
39
s->soc[socket].hartid_base + cpu);
40
qemu_fdt_add_subnode(fdt, cpu_name);
41
-#if defined(TARGET_RISCV32)
42
- qemu_fdt_setprop_string(fdt, cpu_name, "mmu-type", "riscv,sv32");
43
-#else
44
- qemu_fdt_setprop_string(fdt, cpu_name, "mmu-type", "riscv,sv48");
45
-#endif
46
+ if (is_32_bit) {
47
+ qemu_fdt_setprop_string(fdt, cpu_name, "mmu-type", "riscv,sv32");
48
+ } else {
49
+ qemu_fdt_setprop_string(fdt, cpu_name, "mmu-type", "riscv,sv48");
50
+ }
51
name = riscv_isa_string(&s->soc[socket].harts[cpu]);
52
qemu_fdt_setprop_string(fdt, cpu_name, "riscv,isa", name);
53
g_free(name);
54
@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
55
main_mem);
56
57
/* create device tree */
58
- create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline);
59
+ create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline,
60
+ riscv_is_32_bit(machine));
61
62
/* boot rom */
63
memory_region_init_rom(mask_rom, NULL, "riscv_virt_board.mrom",
64
@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
65
memory_region_add_subregion(system_memory, memmap[VIRT_MROM].base,
66
mask_rom);
67
68
- firmware_end_addr = riscv_find_and_load_firmware(machine, BIOS_FILENAME,
69
- start_addr, NULL);
70
+ if (riscv_is_32_bit(machine)) {
71
+ firmware_end_addr = riscv_find_and_load_firmware(machine,
72
+ "opensbi-riscv32-generic-fw_dynamic.bin",
73
+ start_addr, NULL);
74
+ } else {
75
+ firmware_end_addr = riscv_find_and_load_firmware(machine,
76
+ "opensbi-riscv64-generic-fw_dynamic.bin",
77
+ start_addr, NULL);
78
+ }
79
80
if (machine->kernel_filename) {
81
kernel_start_addr = riscv_calc_kernel_start_addr(machine,
82
--
83
2.29.2
84
85
diff view generated by jsdifflib
[PULL 13/23] hw/riscv: spike: Remove compile time XLEN checks
Deleted patch
1
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2
Reviewed-by: Bin Meng <bin.meng@windriver.com>
3
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
4
Acked-by: Palmer Dabbelt <palmerdabbelt@google.com>
5
Message-id: ac75037dd58061486de421a0fcd9ac8a92014607.1608142916.git.alistair.francis@wdc.com
6
---
7
hw/riscv/spike.c | 45 ++++++++++++++++++++++++---------------------
8
1 file changed, 24 insertions(+), 21 deletions(-)
9
1
10
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
11
index XXXXXXX..XXXXXXX 100644
12
--- a/hw/riscv/spike.c
13
+++ b/hw/riscv/spike.c
14
@@ -XXX,XX +XXX,XX @@
15
#include "sysemu/qtest.h"
16
#include "sysemu/sysemu.h"
17
18
-/*
19
- * Not like other RISC-V machines that use plain binary bios images,
20
- * keeping ELF files here was intentional because BIN files don't work
21
- * for the Spike machine as HTIF emulation depends on ELF parsing.
22
- */
23
-#if defined(TARGET_RISCV32)
24
-# define BIOS_FILENAME "opensbi-riscv32-generic-fw_dynamic.elf"
25
-#else
26
-# define BIOS_FILENAME "opensbi-riscv64-generic-fw_dynamic.elf"
27
-#endif
28
-
29
static const struct MemmapEntry {
30
hwaddr base;
31
hwaddr size;
32
@@ -XXX,XX +XXX,XX @@ static const struct MemmapEntry {
33
};
34
35
static void create_fdt(SpikeState *s, const struct MemmapEntry *memmap,
36
- uint64_t mem_size, const char *cmdline)
37
+ uint64_t mem_size, const char *cmdline, bool is_32_bit)
38
{
39
void *fdt;
40
uint64_t addr, size;
41
@@ -XXX,XX +XXX,XX @@ static void create_fdt(SpikeState *s, const struct MemmapEntry *memmap,
42
cpu_name = g_strdup_printf("/cpus/cpu@%d",
43
s->soc[socket].hartid_base + cpu);
44
qemu_fdt_add_subnode(fdt, cpu_name);
45
-#if defined(TARGET_RISCV32)
46
- qemu_fdt_setprop_string(fdt, cpu_name, "mmu-type", "riscv,sv32");
47
-#else
48
- qemu_fdt_setprop_string(fdt, cpu_name, "mmu-type", "riscv,sv48");
49
-#endif
50
+ if (is_32_bit) {
51
+ qemu_fdt_setprop_string(fdt, cpu_name, "mmu-type", "riscv,sv32");
52
+ } else {
53
+ qemu_fdt_setprop_string(fdt, cpu_name, "mmu-type", "riscv,sv48");
54
+ }
55
name = riscv_isa_string(&s->soc[socket].harts[cpu]);
56
qemu_fdt_setprop_string(fdt, cpu_name, "riscv,isa", name);
57
g_free(name);
58
@@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine)
59
main_mem);
60
61
/* create device tree */
62
- create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline);
63
+ create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline,
64
+ riscv_is_32_bit(machine));
65
66
/* boot rom */
67
memory_region_init_rom(mask_rom, NULL, "riscv.spike.mrom",
68
@@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine)
69
memory_region_add_subregion(system_memory, memmap[SPIKE_MROM].base,
70
mask_rom);
71
72
- firmware_end_addr = riscv_find_and_load_firmware(machine, BIOS_FILENAME,
73
- memmap[SPIKE_DRAM].base,
74
- htif_symbol_callback);
75
+ /*
76
+ * Not like other RISC-V machines that use plain binary bios images,
77
+ * keeping ELF files here was intentional because BIN files don't work
78
+ * for the Spike machine as HTIF emulation depends on ELF parsing.
79
+ */
80
+ if (riscv_is_32_bit(machine)) {
81
+ firmware_end_addr = riscv_find_and_load_firmware(machine,
82
+ "opensbi-riscv32-generic-fw_dynamic.elf",
83
+ memmap[SPIKE_DRAM].base,
84
+ htif_symbol_callback);
85
+ } else {
86
+ firmware_end_addr = riscv_find_and_load_firmware(machine,
87
+ "opensbi-riscv64-generic-fw_dynamic.elf",
88
+ memmap[SPIKE_DRAM].base,
89
+ htif_symbol_callback);
90
+ }
91
92
if (machine->kernel_filename) {
93
kernel_start_addr = riscv_calc_kernel_start_addr(machine,
94
--
95
2.29.2
96
97
diff view generated by jsdifflib
[PULL 14/23] hw/riscv: sifive_u: Remove compile time XLEN checks
Deleted patch
1
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
3
Acked-by: Palmer Dabbelt <palmerdabbelt@google.com>
4
Reviewed-by: Bin Meng <bin.meng@windriver.com>
5
Tested-by: Bin Meng <bin.meng@windriver.com>
6
Message-id: 40d6df4dd05302c566e419be3a1fef7799e57c2e.1608142916.git.alistair.francis@wdc.com
7
---
8
hw/riscv/sifive_u.c | 55 ++++++++++++++++++++++++---------------------
9
1 file changed, 30 insertions(+), 25 deletions(-)
10
1
11
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/hw/riscv/sifive_u.c
14
+++ b/hw/riscv/sifive_u.c
15
@@ -XXX,XX +XXX,XX @@
16
17
#include <libfdt.h>
18
19
-#if defined(TARGET_RISCV32)
20
-# define BIOS_FILENAME "opensbi-riscv32-generic-fw_dynamic.bin"
21
-#else
22
-# define BIOS_FILENAME "opensbi-riscv64-generic-fw_dynamic.bin"
23
-#endif
24
-
25
static const struct MemmapEntry {
26
hwaddr base;
27
hwaddr size;
28
@@ -XXX,XX +XXX,XX @@ static const struct MemmapEntry {
29
#define GEM_REVISION 0x10070109
30
31
static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
32
- uint64_t mem_size, const char *cmdline)
33
+ uint64_t mem_size, const char *cmdline, bool is_32_bit)
34
{
35
MachineState *ms = MACHINE(qdev_get_machine());
36
void *fdt;
37
@@ -XXX,XX +XXX,XX @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
38
qemu_fdt_add_subnode(fdt, nodename);
39
/* cpu 0 is the management hart that does not have mmu */
40
if (cpu != 0) {
41
-#if defined(TARGET_RISCV32)
42
- qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv32");
43
-#else
44
- qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48");
45
-#endif
46
+ if (is_32_bit) {
47
+ qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv32");
48
+ } else {
49
+ qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48");
50
+ }
51
isa = riscv_isa_string(&s->soc.u_cpus.harts[cpu - 1]);
52
} else {
53
isa = riscv_isa_string(&s->soc.e_cpus.harts[0]);
54
@@ -XXX,XX +XXX,XX @@ static void sifive_u_machine_init(MachineState *machine)
55
qemu_allocate_irq(sifive_u_machine_reset, NULL, 0));
56
57
/* create device tree */
58
- create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline);
59
+ create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline,
60
+ riscv_is_32_bit(machine));
61
62
if (s->start_in_flash) {
63
/*
64
@@ -XXX,XX +XXX,XX @@ static void sifive_u_machine_init(MachineState *machine)
65
break;
66
}
67
68
- firmware_end_addr = riscv_find_and_load_firmware(machine, BIOS_FILENAME,
69
- start_addr, NULL);
70
+ if (riscv_is_32_bit(machine)) {
71
+ firmware_end_addr = riscv_find_and_load_firmware(machine,
72
+ "opensbi-riscv32-generic-fw_dynamic.bin",
73
+ start_addr, NULL);
74
+ } else {
75
+ firmware_end_addr = riscv_find_and_load_firmware(machine,
76
+ "opensbi-riscv64-generic-fw_dynamic.bin",
77
+ start_addr, NULL);
78
+ }
79
80
if (machine->kernel_filename) {
81
kernel_start_addr = riscv_calc_kernel_start_addr(machine,
82
@@ -XXX,XX +XXX,XX @@ static void sifive_u_machine_init(MachineState *machine)
83
/* Compute the fdt load address in dram */
84
fdt_load_addr = riscv_load_fdt(memmap[SIFIVE_U_DEV_DRAM].base,
85
machine->ram_size, s->fdt);
86
- #if defined(TARGET_RISCV64)
87
- start_addr_hi32 = start_addr >> 32;
88
- #endif
89
+ if (!riscv_is_32_bit(machine)) {
90
+ start_addr_hi32 = (uint64_t)start_addr >> 32;
91
+ }
92
93
/* reset vector */
94
uint32_t reset_vec[11] = {
95
@@ -XXX,XX +XXX,XX @@ static void sifive_u_machine_init(MachineState *machine)
96
0x00000297, /* 1: auipc t0, %pcrel_hi(fw_dyn) */
97
0x02828613, /* addi a2, t0, %pcrel_lo(1b) */
98
0xf1402573, /* csrr a0, mhartid */
99
-#if defined(TARGET_RISCV32)
100
- 0x0202a583, /* lw a1, 32(t0) */
101
- 0x0182a283, /* lw t0, 24(t0) */
102
-#elif defined(TARGET_RISCV64)
103
- 0x0202b583, /* ld a1, 32(t0) */
104
- 0x0182b283, /* ld t0, 24(t0) */
105
-#endif
106
+ 0,
107
+ 0,
108
0x00028067, /* jr t0 */
109
start_addr, /* start: .dword */
110
start_addr_hi32,
111
@@ -XXX,XX +XXX,XX @@ static void sifive_u_machine_init(MachineState *machine)
112
0x00000000,
113
/* fw_dyn: */
114
};
115
+ if (riscv_is_32_bit(machine)) {
116
+ reset_vec[4] = 0x0202a583; /* lw a1, 32(t0) */
117
+ reset_vec[5] = 0x0182a283; /* lw t0, 24(t0) */
118
+ } else {
119
+ reset_vec[4] = 0x0202b583; /* ld a1, 32(t0) */
120
+ reset_vec[5] = 0x0182b283; /* ld t0, 24(t0) */
121
+ }
122
+
123
124
/* copy in the reset vector in little_endian byte order */
125
for (i = 0; i < ARRAY_SIZE(reset_vec); i++) {
126
--
127
2.29.2
128
129
diff view generated by jsdifflib
[PULL 15/23] target/riscv: fpu_helper: Match function defs in HELPER macros
Deleted patch
1
Update the function definitions generated in helper.h to match the
2
actual function implementations.
3
1
4
Also remove all compile time XLEN checks when building.
5
6
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
7
Message-id: 614c369cb0000d070873a647b8aac7e023cba145.1608142916.git.alistair.francis@wdc.com
8
---
9
target/riscv/helper.h | 24 ++++++++----------------
10
target/riscv/fpu_helper.c | 8 --------
11
2 files changed, 8 insertions(+), 24 deletions(-)
12
13
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
14
index XXXXXXX..XXXXXXX 100644
15
--- a/target/riscv/helper.h
16
+++ b/target/riscv/helper.h
17
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(flt_s, TCG_CALL_NO_RWG, tl, env, i64, i64)
18
DEF_HELPER_FLAGS_3(feq_s, TCG_CALL_NO_RWG, tl, env, i64, i64)
19
DEF_HELPER_FLAGS_2(fcvt_w_s, TCG_CALL_NO_RWG, tl, env, i64)
20
DEF_HELPER_FLAGS_2(fcvt_wu_s, TCG_CALL_NO_RWG, tl, env, i64)
21
-#if defined(TARGET_RISCV64)
22
-DEF_HELPER_FLAGS_2(fcvt_l_s, TCG_CALL_NO_RWG, tl, env, i64)
23
-DEF_HELPER_FLAGS_2(fcvt_lu_s, TCG_CALL_NO_RWG, tl, env, i64)
24
-#endif
25
+DEF_HELPER_FLAGS_2(fcvt_l_s, TCG_CALL_NO_RWG, i64, env, i64)
26
+DEF_HELPER_FLAGS_2(fcvt_lu_s, TCG_CALL_NO_RWG, i64, env, i64)
27
DEF_HELPER_FLAGS_2(fcvt_s_w, TCG_CALL_NO_RWG, i64, env, tl)
28
DEF_HELPER_FLAGS_2(fcvt_s_wu, TCG_CALL_NO_RWG, i64, env, tl)
29
-#if defined(TARGET_RISCV64)
30
-DEF_HELPER_FLAGS_2(fcvt_s_l, TCG_CALL_NO_RWG, i64, env, tl)
31
-DEF_HELPER_FLAGS_2(fcvt_s_lu, TCG_CALL_NO_RWG, i64, env, tl)
32
-#endif
33
+DEF_HELPER_FLAGS_2(fcvt_s_l, TCG_CALL_NO_RWG, i64, env, i64)
34
+DEF_HELPER_FLAGS_2(fcvt_s_lu, TCG_CALL_NO_RWG, i64, env, i64)
35
DEF_HELPER_FLAGS_1(fclass_s, TCG_CALL_NO_RWG_SE, tl, i64)
36
37
/* Floating Point - Double Precision */
38
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(flt_d, TCG_CALL_NO_RWG, tl, env, i64, i64)
39
DEF_HELPER_FLAGS_3(feq_d, TCG_CALL_NO_RWG, tl, env, i64, i64)
40
DEF_HELPER_FLAGS_2(fcvt_w_d, TCG_CALL_NO_RWG, tl, env, i64)
41
DEF_HELPER_FLAGS_2(fcvt_wu_d, TCG_CALL_NO_RWG, tl, env, i64)
42
-#if defined(TARGET_RISCV64)
43
-DEF_HELPER_FLAGS_2(fcvt_l_d, TCG_CALL_NO_RWG, tl, env, i64)
44
-DEF_HELPER_FLAGS_2(fcvt_lu_d, TCG_CALL_NO_RWG, tl, env, i64)
45
-#endif
46
+DEF_HELPER_FLAGS_2(fcvt_l_d, TCG_CALL_NO_RWG, i64, env, i64)
47
+DEF_HELPER_FLAGS_2(fcvt_lu_d, TCG_CALL_NO_RWG, i64, env, i64)
48
DEF_HELPER_FLAGS_2(fcvt_d_w, TCG_CALL_NO_RWG, i64, env, tl)
49
DEF_HELPER_FLAGS_2(fcvt_d_wu, TCG_CALL_NO_RWG, i64, env, tl)
50
-#if defined(TARGET_RISCV64)
51
-DEF_HELPER_FLAGS_2(fcvt_d_l, TCG_CALL_NO_RWG, i64, env, tl)
52
-DEF_HELPER_FLAGS_2(fcvt_d_lu, TCG_CALL_NO_RWG, i64, env, tl)
53
-#endif
54
+DEF_HELPER_FLAGS_2(fcvt_d_l, TCG_CALL_NO_RWG, i64, env, i64)
55
+DEF_HELPER_FLAGS_2(fcvt_d_lu, TCG_CALL_NO_RWG, i64, env, i64)
56
DEF_HELPER_FLAGS_1(fclass_d, TCG_CALL_NO_RWG_SE, tl, i64)
57
58
/* Special functions */
59
diff --git a/target/riscv/fpu_helper.c b/target/riscv/fpu_helper.c
60
index XXXXXXX..XXXXXXX 100644
61
--- a/target/riscv/fpu_helper.c
62
+++ b/target/riscv/fpu_helper.c
63
@@ -XXX,XX +XXX,XX @@ target_ulong helper_fcvt_wu_s(CPURISCVState *env, uint64_t rs1)
64
return (int32_t)float32_to_uint32(frs1, &env->fp_status);
65
}
66
67
-#if defined(TARGET_RISCV64)
68
uint64_t helper_fcvt_l_s(CPURISCVState *env, uint64_t rs1)
69
{
70
float32 frs1 = check_nanbox_s(rs1);
71
@@ -XXX,XX +XXX,XX @@ uint64_t helper_fcvt_lu_s(CPURISCVState *env, uint64_t rs1)
72
float32 frs1 = check_nanbox_s(rs1);
73
return float32_to_uint64(frs1, &env->fp_status);
74
}
75
-#endif
76
77
uint64_t helper_fcvt_s_w(CPURISCVState *env, target_ulong rs1)
78
{
79
@@ -XXX,XX +XXX,XX @@ uint64_t helper_fcvt_s_wu(CPURISCVState *env, target_ulong rs1)
80
return nanbox_s(uint32_to_float32((uint32_t)rs1, &env->fp_status));
81
}
82
83
-#if defined(TARGET_RISCV64)
84
uint64_t helper_fcvt_s_l(CPURISCVState *env, uint64_t rs1)
85
{
86
return nanbox_s(int64_to_float32(rs1, &env->fp_status));
87
@@ -XXX,XX +XXX,XX @@ uint64_t helper_fcvt_s_lu(CPURISCVState *env, uint64_t rs1)
88
{
89
return nanbox_s(uint64_to_float32(rs1, &env->fp_status));
90
}
91
-#endif
92
93
target_ulong helper_fclass_s(uint64_t rs1)
94
{
95
@@ -XXX,XX +XXX,XX @@ target_ulong helper_fcvt_wu_d(CPURISCVState *env, uint64_t frs1)
96
return (int32_t)float64_to_uint32(frs1, &env->fp_status);
97
}
98
99
-#if defined(TARGET_RISCV64)
100
uint64_t helper_fcvt_l_d(CPURISCVState *env, uint64_t frs1)
101
{
102
return float64_to_int64(frs1, &env->fp_status);
103
@@ -XXX,XX +XXX,XX @@ uint64_t helper_fcvt_lu_d(CPURISCVState *env, uint64_t frs1)
104
{
105
return float64_to_uint64(frs1, &env->fp_status);
106
}
107
-#endif
108
109
uint64_t helper_fcvt_d_w(CPURISCVState *env, target_ulong rs1)
110
{
111
@@ -XXX,XX +XXX,XX @@ uint64_t helper_fcvt_d_wu(CPURISCVState *env, target_ulong rs1)
112
return uint32_to_float64((uint32_t)rs1, &env->fp_status);
113
}
114
115
-#if defined(TARGET_RISCV64)
116
uint64_t helper_fcvt_d_l(CPURISCVState *env, uint64_t rs1)
117
{
118
return int64_to_float64(rs1, &env->fp_status);
119
@@ -XXX,XX +XXX,XX @@ uint64_t helper_fcvt_d_lu(CPURISCVState *env, uint64_t rs1)
120
{
121
return uint64_to_float64(rs1, &env->fp_status);
122
}
123
-#endif
124
125
target_ulong helper_fclass_d(uint64_t frs1)
126
{
127
--
128
2.29.2
129
130
diff view generated by jsdifflib
[PULL 16/23] target/riscv: Add a riscv_cpu_is_32bit() helper function
Deleted patch
1
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2
Reviewed-by: Bin Meng <bin.meng@windriver.com>
3
Tested-by: Bin Meng <bin.meng@windriver.com>
4
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
5
Acked-by: Palmer Dabbelt <palmerdabbelt@google.com>
6
Message-id: ebd37b237a8cbe457335b948bd57f487b6b31869.1608142916.git.alistair.francis@wdc.com
7
---
8
target/riscv/cpu.h | 2 ++
9
target/riscv/cpu.c | 9 +++++++++
10
2 files changed, 11 insertions(+)
11
1
12
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/riscv/cpu.h
15
+++ b/target/riscv/cpu.h
16
@@ -XXX,XX +XXX,XX @@ FIELD(TB_FLAGS, VILL, 8, 1)
17
/* Is a Hypervisor instruction load/store allowed? */
18
FIELD(TB_FLAGS, HLSX, 9, 1)
19
20
+bool riscv_cpu_is_32bit(CPURISCVState *env);
21
+
22
/*
23
* A simplification for VLMAX
24
* = (1 << LMUL) * VLEN / (8 * (1 << SEW))
25
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
26
index XXXXXXX..XXXXXXX 100644
27
--- a/target/riscv/cpu.c
28
+++ b/target/riscv/cpu.c
29
@@ -XXX,XX +XXX,XX @@ const char *riscv_cpu_get_trap_name(target_ulong cause, bool async)
30
}
31
}
32
33
+bool riscv_cpu_is_32bit(CPURISCVState *env)
34
+{
35
+ if (env->misa & RV64) {
36
+ return false;
37
+ }
38
+
39
+ return true;
40
+}
41
+
42
static void set_misa(CPURISCVState *env, target_ulong misa)
43
{
44
env->misa_mask = env->misa = misa;
45
--
46
2.29.2
47
48
diff view generated by jsdifflib
[PULL 17/23] target/riscv: Specify the XLEN for CPUs
Deleted patch
1
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2
Reviewed-by: Bin Meng <bin.meng@windriver.com>
3
Tested-by: Bin Meng <bin.meng@windriver.com>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
6
Acked-by: Palmer Dabbelt <palmerdabbelt@google.com>
7
Message-id: c1da66affbb83ec4a2fbeb0194293bd24d65f5dc.1608142916.git.alistair.francis@wdc.com
8
---
9
target/riscv/cpu.c | 33 +++++++++++++++++++++++----------
10
1 file changed, 23 insertions(+), 10 deletions(-)
11
1
12
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/riscv/cpu.c
15
+++ b/target/riscv/cpu.c
16
@@ -XXX,XX +XXX,XX @@ static void riscv_base_cpu_init(Object *obj)
17
set_misa(env, 0);
18
}
19
20
-static void rvxx_sifive_u_cpu_init(Object *obj)
21
+#ifdef TARGET_RISCV64
22
+static void rv64_sifive_u_cpu_init(Object *obj)
23
{
24
CPURISCVState *env = &RISCV_CPU(obj)->env;
25
- set_misa(env, RVXLEN | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
26
+ set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
27
set_priv_version(env, PRIV_VERSION_1_10_0);
28
}
29
30
-static void rvxx_sifive_e_cpu_init(Object *obj)
31
+static void rv64_sifive_e_cpu_init(Object *obj)
32
{
33
CPURISCVState *env = &RISCV_CPU(obj)->env;
34
- set_misa(env, RVXLEN | RVI | RVM | RVA | RVC | RVU);
35
+ set_misa(env, RV64 | RVI | RVM | RVA | RVC | RVU);
36
set_priv_version(env, PRIV_VERSION_1_10_0);
37
qdev_prop_set_bit(DEVICE(obj), "mmu", false);
38
}
39
+#else
40
+static void rv32_sifive_u_cpu_init(Object *obj)
41
+{
42
+ CPURISCVState *env = &RISCV_CPU(obj)->env;
43
+ set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
44
+ set_priv_version(env, PRIV_VERSION_1_10_0);
45
+}
46
47
-#if defined(TARGET_RISCV32)
48
+static void rv32_sifive_e_cpu_init(Object *obj)
49
+{
50
+ CPURISCVState *env = &RISCV_CPU(obj)->env;
51
+ set_misa(env, RV32 | RVI | RVM | RVA | RVC | RVU);
52
+ set_priv_version(env, PRIV_VERSION_1_10_0);
53
+ qdev_prop_set_bit(DEVICE(obj), "mmu", false);
54
+}
55
56
static void rv32_ibex_cpu_init(Object *obj)
57
{
58
@@ -XXX,XX +XXX,XX @@ static void rv32_imafcu_nommu_cpu_init(Object *obj)
59
set_resetvec(env, DEFAULT_RSTVEC);
60
qdev_prop_set_bit(DEVICE(obj), "mmu", false);
61
}
62
-
63
#endif
64
65
static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model)
66
@@ -XXX,XX +XXX,XX @@ static const TypeInfo riscv_cpu_type_infos[] = {
67
#if defined(TARGET_RISCV32)
68
DEFINE_CPU(TYPE_RISCV_CPU_BASE32, riscv_base_cpu_init),
69
DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32_ibex_cpu_init),
70
- DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rvxx_sifive_e_cpu_init),
71
+ DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32_sifive_e_cpu_init),
72
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32_imafcu_nommu_cpu_init),
73
- DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rvxx_sifive_u_cpu_init),
74
+ DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32_sifive_u_cpu_init),
75
#elif defined(TARGET_RISCV64)
76
DEFINE_CPU(TYPE_RISCV_CPU_BASE64, riscv_base_cpu_init),
77
- DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rvxx_sifive_e_cpu_init),
78
- DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rvxx_sifive_u_cpu_init),
79
+ DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64_sifive_e_cpu_init),
80
+ DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64_sifive_u_cpu_init),
81
#endif
82
};
83
84
--
85
2.29.2
86
87
diff view generated by jsdifflib
[PULL 18/23] target/riscv: cpu: Remove compile time XLEN checks
Deleted patch
1
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2
Reviewed-by: Bin Meng <bin.meng@windriver.com>
3
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
5
Acked-by: Palmer Dabbelt <palmerdabbelt@google.com>
6
Tested-by: Bin Meng <bin.meng@windriver.com>
7
Message-id: a426ead44db5065a0790066d43e91245683509d7.1608142916.git.alistair.francis@wdc.com
8
---
9
target/riscv/cpu.c | 19 ++++++++++---------
10
1 file changed, 10 insertions(+), 9 deletions(-)
11
1
12
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/riscv/cpu.c
15
+++ b/target/riscv/cpu.c
16
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
17
#ifndef CONFIG_USER_ONLY
18
qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mhartid ", env->mhartid);
19
qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatus ", (target_ulong)env->mstatus);
20
-#ifdef TARGET_RISCV32
21
- qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatush ",
22
- (target_ulong)(env->mstatus >> 32));
23
-#endif
24
+ if (riscv_cpu_is_32bit(env)) {
25
+ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatush ",
26
+ (target_ulong)(env->mstatus >> 32));
27
+ }
28
if (riscv_has_ext(env, RVH)) {
29
qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hstatus ", env->hstatus);
30
qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vsstatus ",
31
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_reset(DeviceState *dev)
32
33
static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info)
34
{
35
-#if defined(TARGET_RISCV32)
36
- info->print_insn = print_insn_riscv32;
37
-#elif defined(TARGET_RISCV64)
38
- info->print_insn = print_insn_riscv64;
39
-#endif
40
+ RISCVCPU *cpu = RISCV_CPU(s);
41
+ if (riscv_cpu_is_32bit(&cpu->env)) {
42
+ info->print_insn = print_insn_riscv32;
43
+ } else {
44
+ info->print_insn = print_insn_riscv64;
45
+ }
46
}
47
48
static void riscv_cpu_realize(DeviceState *dev, Error **errp)
49
--
50
2.29.2
51
52
diff view generated by jsdifflib
[PULL 19/23] target/riscv: cpu_helper: Remove compile time XLEN checks
Deleted patch
1
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
3
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
4
Acked-by: Palmer Dabbelt <palmerdabbelt@google.com>
5
Reviewed-by: Bin Meng <bin.meng@windriver.com>
6
Tested-by: Bin Meng <bin.meng@windriver.com>
7
Message-id: 872d2dfcd1c7c3914655d677e911b9432eb8f340.1608142916.git.alistair.francis@wdc.com
8
---
9
target/riscv/cpu_helper.c | 12 +++++++-----
10
1 file changed, 7 insertions(+), 5 deletions(-)
11
1
12
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/riscv/cpu_helper.c
15
+++ b/target/riscv/cpu_helper.c
16
@@ -XXX,XX +XXX,XX @@ restart:
17
return TRANSLATE_PMP_FAIL;
18
}
19
20
-#if defined(TARGET_RISCV32)
21
- target_ulong pte = address_space_ldl(cs->as, pte_addr, attrs, &res);
22
-#elif defined(TARGET_RISCV64)
23
- target_ulong pte = address_space_ldq(cs->as, pte_addr, attrs, &res);
24
-#endif
25
+ target_ulong pte;
26
+ if (riscv_cpu_is_32bit(env)) {
27
+ pte = address_space_ldl(cs->as, pte_addr, attrs, &res);
28
+ } else {
29
+ pte = address_space_ldq(cs->as, pte_addr, attrs, &res);
30
+ }
31
+
32
if (res != MEMTX_OK) {
33
return TRANSLATE_FAIL;
34
}
35
--
36
2.29.2
37
38
diff view generated by jsdifflib
[PULL 20/23] target/riscv: csr: Remove compile time XLEN checks
Deleted patch
1
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2
Reviewed-by: Bin Meng <bin.meng@windriver.com>
3
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
4
Acked-by: Palmer Dabbelt <palmerdabbelt@google.com>
5
Tested-by: Bin Meng <bin.meng@windriver.com>
6
Message-id: 7371180970b7db310d3a1da21d03d33499c2beb0.1608142916.git.alistair.francis@wdc.com
7
---
8
target/riscv/cpu_bits.h | 4 +-
9
target/riscv/csr.c | 176 +++++++++++++++++++++-------------------
10
2 files changed, 92 insertions(+), 88 deletions(-)
11
1
12
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/riscv/cpu_bits.h
15
+++ b/target/riscv/cpu_bits.h
16
@@ -XXX,XX +XXX,XX @@
17
#define HSTATUS_VGEIN 0x0003F000
18
#define HSTATUS_VTVM 0x00100000
19
#define HSTATUS_VTSR 0x00400000
20
-#if defined(TARGET_RISCV64)
21
-#define HSTATUS_VSXL 0x300000000
22
-#endif
23
+#define HSTATUS_VSXL 0x300000000
24
25
#define HSTATUS32_WPRI 0xFF8FF87E
26
#define HSTATUS64_WPRI 0xFFFFFFFFFF8FF87EULL
27
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
28
index XXXXXXX..XXXXXXX 100644
29
--- a/target/riscv/csr.c
30
+++ b/target/riscv/csr.c
31
@@ -XXX,XX +XXX,XX @@ static int ctr(CPURISCVState *env, int csrno)
32
return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
33
}
34
break;
35
-#if defined(TARGET_RISCV32)
36
- case CSR_CYCLEH:
37
- if (!get_field(env->hcounteren, HCOUNTEREN_CY) &&
38
- get_field(env->mcounteren, HCOUNTEREN_CY)) {
39
- return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
40
- }
41
- break;
42
- case CSR_TIMEH:
43
- if (!get_field(env->hcounteren, HCOUNTEREN_TM) &&
44
- get_field(env->mcounteren, HCOUNTEREN_TM)) {
45
- return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
46
- }
47
- break;
48
- case CSR_INSTRETH:
49
- if (!get_field(env->hcounteren, HCOUNTEREN_IR) &&
50
- get_field(env->mcounteren, HCOUNTEREN_IR)) {
51
- return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
52
- }
53
- break;
54
- case CSR_HPMCOUNTER3H...CSR_HPMCOUNTER31H:
55
- if (!get_field(env->hcounteren, 1 << (csrno - CSR_HPMCOUNTER3H)) &&
56
- get_field(env->mcounteren, 1 << (csrno - CSR_HPMCOUNTER3H))) {
57
- return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
58
+ }
59
+ if (riscv_cpu_is_32bit(env)) {
60
+ switch (csrno) {
61
+ case CSR_CYCLEH:
62
+ if (!get_field(env->hcounteren, HCOUNTEREN_CY) &&
63
+ get_field(env->mcounteren, HCOUNTEREN_CY)) {
64
+ return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
65
+ }
66
+ break;
67
+ case CSR_TIMEH:
68
+ if (!get_field(env->hcounteren, HCOUNTEREN_TM) &&
69
+ get_field(env->mcounteren, HCOUNTEREN_TM)) {
70
+ return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
71
+ }
72
+ break;
73
+ case CSR_INSTRETH:
74
+ if (!get_field(env->hcounteren, HCOUNTEREN_IR) &&
75
+ get_field(env->mcounteren, HCOUNTEREN_IR)) {
76
+ return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
77
+ }
78
+ break;
79
+ case CSR_HPMCOUNTER3H...CSR_HPMCOUNTER31H:
80
+ if (!get_field(env->hcounteren, 1 << (csrno - CSR_HPMCOUNTER3H)) &&
81
+ get_field(env->mcounteren, 1 << (csrno - CSR_HPMCOUNTER3H))) {
82
+ return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
83
+ }
84
+ break;
85
}
86
- break;
87
-#endif
88
}
89
}
90
#endif
91
return 0;
92
}
93
94
+static int ctr32(CPURISCVState *env, int csrno)
95
+{
96
+ if (!riscv_cpu_is_32bit(env)) {
97
+ return -RISCV_EXCP_ILLEGAL_INST;
98
+ }
99
+
100
+ return ctr(env, csrno);
101
+}
102
+
103
#if !defined(CONFIG_USER_ONLY)
104
static int any(CPURISCVState *env, int csrno)
105
{
106
return 0;
107
}
108
109
+static int any32(CPURISCVState *env, int csrno)
110
+{
111
+ if (!riscv_cpu_is_32bit(env)) {
112
+ return -RISCV_EXCP_ILLEGAL_INST;
113
+ }
114
+
115
+ return any(env, csrno);
116
+
117
+}
118
+
119
static int smode(CPURISCVState *env, int csrno)
120
{
121
return -!riscv_has_ext(env, RVS);
122
@@ -XXX,XX +XXX,XX @@ static int hmode(CPURISCVState *env, int csrno)
123
return -RISCV_EXCP_ILLEGAL_INST;
124
}
125
126
+static int hmode32(CPURISCVState *env, int csrno)
127
+{
128
+ if (!riscv_cpu_is_32bit(env)) {
129
+ return 0;
130
+ }
131
+
132
+ return hmode(env, csrno);
133
+
134
+}
135
+
136
static int pmp(CPURISCVState *env, int csrno)
137
{
138
return -!riscv_feature(env, RISCV_FEATURE_PMP);
139
@@ -XXX,XX +XXX,XX @@ static int read_instret(CPURISCVState *env, int csrno, target_ulong *val)
140
return 0;
141
}
142
143
-#if defined(TARGET_RISCV32)
144
static int read_instreth(CPURISCVState *env, int csrno, target_ulong *val)
145
{
146
#if !defined(CONFIG_USER_ONLY)
147
@@ -XXX,XX +XXX,XX @@ static int read_instreth(CPURISCVState *env, int csrno, target_ulong *val)
148
#endif
149
return 0;
150
}
151
-#endif /* TARGET_RISCV32 */
152
153
#if defined(CONFIG_USER_ONLY)
154
static int read_time(CPURISCVState *env, int csrno, target_ulong *val)
155
@@ -XXX,XX +XXX,XX @@ static int read_time(CPURISCVState *env, int csrno, target_ulong *val)
156
return 0;
157
}
158
159
-#if defined(TARGET_RISCV32)
160
static int read_timeh(CPURISCVState *env, int csrno, target_ulong *val)
161
{
162
*val = cpu_get_host_ticks() >> 32;
163
return 0;
164
}
165
-#endif
166
167
#else /* CONFIG_USER_ONLY */
168
169
@@ -XXX,XX +XXX,XX @@ static int read_time(CPURISCVState *env, int csrno, target_ulong *val)
170
return 0;
171
}
172
173
-#if defined(TARGET_RISCV32)
174
static int read_timeh(CPURISCVState *env, int csrno, target_ulong *val)
175
{
176
uint64_t delta = riscv_cpu_virt_enabled(env) ? env->htimedelta : 0;
177
@@ -XXX,XX +XXX,XX @@ static int read_timeh(CPURISCVState *env, int csrno, target_ulong *val)
178
*val = (env->rdtime_fn(env->rdtime_fn_arg) + delta) >> 32;
179
return 0;
180
}
181
-#endif
182
183
/* Machine constants */
184
185
@@ -XXX,XX +XXX,XX @@ static const target_ulong sip_writable_mask = SIP_SSIP | MIP_USIP | MIP_UEIP;
186
static const target_ulong hip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP;
187
static const target_ulong vsip_writable_mask = MIP_VSSIP;
188
189
-#if defined(TARGET_RISCV32)
190
-static const char valid_vm_1_10[16] = {
191
+static const char valid_vm_1_10_32[16] = {
192
[VM_1_10_MBARE] = 1,
193
[VM_1_10_SV32] = 1
194
};
195
-#elif defined(TARGET_RISCV64)
196
-static const char valid_vm_1_10[16] = {
197
+
198
+static const char valid_vm_1_10_64[16] = {
199
[VM_1_10_MBARE] = 1,
200
[VM_1_10_SV39] = 1,
201
[VM_1_10_SV48] = 1,
202
[VM_1_10_SV57] = 1
203
};
204
-#endif /* CONFIG_USER_ONLY */
205
206
/* Machine Information Registers */
207
static int read_zero(CPURISCVState *env, int csrno, target_ulong *val)
208
@@ -XXX,XX +XXX,XX @@ static int read_mstatus(CPURISCVState *env, int csrno, target_ulong *val)
209
210
static int validate_vm(CPURISCVState *env, target_ulong vm)
211
{
212
- return valid_vm_1_10[vm & 0xf];
213
+ if (riscv_cpu_is_32bit(env)) {
214
+ return valid_vm_1_10_32[vm & 0xf];
215
+ } else {
216
+ return valid_vm_1_10_64[vm & 0xf];
217
+ }
218
}
219
220
static int write_mstatus(CPURISCVState *env, int csrno, target_ulong val)
221
@@ -XXX,XX +XXX,XX @@ static int write_mstatus(CPURISCVState *env, int csrno, target_ulong val)
222
MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM |
223
MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TVM | MSTATUS_TSR |
224
MSTATUS_TW;
225
-#if defined(TARGET_RISCV64)
226
- /*
227
- * RV32: MPV and GVA are not in mstatus. The current plan is to
228
- * add them to mstatush. For now, we just don't support it.
229
- */
230
- mask |= MSTATUS_MPV | MSTATUS_GVA;
231
-#endif
232
+
233
+ if (!riscv_cpu_is_32bit(env)) {
234
+ /*
235
+ * RV32: MPV and GVA are not in mstatus. The current plan is to
236
+ * add them to mstatush. For now, we just don't support it.
237
+ */
238
+ mask |= MSTATUS_MPV | MSTATUS_GVA;
239
+ }
240
241
mstatus = (mstatus & ~mask) | (val & mask);
242
243
@@ -XXX,XX +XXX,XX @@ static int write_mstatus(CPURISCVState *env, int csrno, target_ulong val)
244
return 0;
245
}
246
247
-#ifdef TARGET_RISCV32
248
static int read_mstatush(CPURISCVState *env, int csrno, target_ulong *val)
249
{
250
*val = env->mstatus >> 32;
251
@@ -XXX,XX +XXX,XX @@ static int write_mstatush(CPURISCVState *env, int csrno, target_ulong val)
252
253
return 0;
254
}
255
-#endif
256
257
static int read_misa(CPURISCVState *env, int csrno, target_ulong *val)
258
{
259
@@ -XXX,XX +XXX,XX @@ static int write_satp(CPURISCVState *env, int csrno, target_ulong val)
260
static int read_hstatus(CPURISCVState *env, int csrno, target_ulong *val)
261
{
262
*val = env->hstatus;
263
-#ifdef TARGET_RISCV64
264
- /* We only support 64-bit VSXL */
265
- *val = set_field(*val, HSTATUS_VSXL, 2);
266
-#endif
267
+ if (!riscv_cpu_is_32bit(env)) {
268
+ /* We only support 64-bit VSXL */
269
+ *val = set_field(*val, HSTATUS_VSXL, 2);
270
+ }
271
/* We only support little endian */
272
*val = set_field(*val, HSTATUS_VSBE, 0);
273
return 0;
274
@@ -XXX,XX +XXX,XX @@ static int read_hstatus(CPURISCVState *env, int csrno, target_ulong *val)
275
static int write_hstatus(CPURISCVState *env, int csrno, target_ulong val)
276
{
277
env->hstatus = val;
278
-#ifdef TARGET_RISCV64
279
- if (get_field(val, HSTATUS_VSXL) != 2) {
280
+ if (!riscv_cpu_is_32bit(env) && get_field(val, HSTATUS_VSXL) != 2) {
281
qemu_log_mask(LOG_UNIMP, "QEMU does not support mixed HSXLEN options.");
282
}
283
-#endif
284
if (get_field(val, HSTATUS_VSBE) != 0) {
285
qemu_log_mask(LOG_UNIMP, "QEMU does not support big endian guests.");
286
}
287
@@ -XXX,XX +XXX,XX @@ static int read_htimedelta(CPURISCVState *env, int csrno, target_ulong *val)
288
return -RISCV_EXCP_ILLEGAL_INST;
289
}
290
291
-#if defined(TARGET_RISCV32)
292
- *val = env->htimedelta & 0xffffffff;
293
-#else
294
*val = env->htimedelta;
295
-#endif
296
return 0;
297
}
298
299
@@ -XXX,XX +XXX,XX @@ static int write_htimedelta(CPURISCVState *env, int csrno, target_ulong val)
300
return -RISCV_EXCP_ILLEGAL_INST;
301
}
302
303
-#if defined(TARGET_RISCV32)
304
- env->htimedelta = deposit64(env->htimedelta, 0, 32, (uint64_t)val);
305
-#else
306
- env->htimedelta = val;
307
-#endif
308
+ if (riscv_cpu_is_32bit(env)) {
309
+ env->htimedelta = deposit64(env->htimedelta, 0, 32, (uint64_t)val);
310
+ } else {
311
+ env->htimedelta = val;
312
+ }
313
return 0;
314
}
315
316
-#if defined(TARGET_RISCV32)
317
static int read_htimedeltah(CPURISCVState *env, int csrno, target_ulong *val)
318
{
319
if (!env->rdtime_fn) {
320
@@ -XXX,XX +XXX,XX @@ static int write_htimedeltah(CPURISCVState *env, int csrno, target_ulong val)
321
env->htimedelta = deposit64(env->htimedelta, 32, 32, (uint64_t)val);
322
return 0;
323
}
324
-#endif
325
326
/* Virtual CSR Registers */
327
static int read_vsstatus(CPURISCVState *env, int csrno, target_ulong *val)
328
@@ -XXX,XX +XXX,XX @@ static riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
329
/* User Timers and Counters */
330
[CSR_CYCLE] = { ctr, read_instret },
331
[CSR_INSTRET] = { ctr, read_instret },
332
-#if defined(TARGET_RISCV32)
333
- [CSR_CYCLEH] = { ctr, read_instreth },
334
- [CSR_INSTRETH] = { ctr, read_instreth },
335
-#endif
336
+ [CSR_CYCLEH] = { ctr32, read_instreth },
337
+ [CSR_INSTRETH] = { ctr32, read_instreth },
338
339
/* In privileged mode, the monitor will have to emulate TIME CSRs only if
340
* rdtime callback is not provided by machine/platform emulation */
341
[CSR_TIME] = { ctr, read_time },
342
-#if defined(TARGET_RISCV32)
343
- [CSR_TIMEH] = { ctr, read_timeh },
344
-#endif
345
+ [CSR_TIMEH] = { ctr32, read_timeh },
346
347
#if !defined(CONFIG_USER_ONLY)
348
/* Machine Timers and Counters */
349
[CSR_MCYCLE] = { any, read_instret },
350
[CSR_MINSTRET] = { any, read_instret },
351
-#if defined(TARGET_RISCV32)
352
- [CSR_MCYCLEH] = { any, read_instreth },
353
- [CSR_MINSTRETH] = { any, read_instreth },
354
-#endif
355
+ [CSR_MCYCLEH] = { any32, read_instreth },
356
+ [CSR_MINSTRETH] = { any32, read_instreth },
357
358
/* Machine Information Registers */
359
[CSR_MVENDORID] = { any, read_zero },
360
@@ -XXX,XX +XXX,XX @@ static riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
361
[CSR_MTVEC] = { any, read_mtvec, write_mtvec },
362
[CSR_MCOUNTEREN] = { any, read_mcounteren, write_mcounteren },
363
364
-#if defined(TARGET_RISCV32)
365
- [CSR_MSTATUSH] = { any, read_mstatush, write_mstatush },
366
-#endif
367
+ [CSR_MSTATUSH] = { any32, read_mstatush, write_mstatush },
368
369
[CSR_MSCOUNTEREN] = { any, read_mscounteren, write_mscounteren },
370
371
@@ -XXX,XX +XXX,XX @@ static riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
372
[CSR_HGEIP] = { hmode, read_hgeip, write_hgeip },
373
[CSR_HGATP] = { hmode, read_hgatp, write_hgatp },
374
[CSR_HTIMEDELTA] = { hmode, read_htimedelta, write_htimedelta },
375
-#if defined(TARGET_RISCV32)
376
- [CSR_HTIMEDELTAH] = { hmode, read_htimedeltah, write_htimedeltah},
377
-#endif
378
+ [CSR_HTIMEDELTAH] = { hmode32, read_htimedeltah, write_htimedeltah},
379
380
[CSR_VSSTATUS] = { hmode, read_vsstatus, write_vsstatus },
381
[CSR_VSIP] = { hmode, NULL, NULL, rmw_vsip },
382
@@ -XXX,XX +XXX,XX @@ static riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
383
[CSR_HPMCOUNTER3 ... CSR_HPMCOUNTER31] = { ctr, read_zero },
384
[CSR_MHPMCOUNTER3 ... CSR_MHPMCOUNTER31] = { any, read_zero },
385
[CSR_MHPMEVENT3 ... CSR_MHPMEVENT31] = { any, read_zero },
386
-#if defined(TARGET_RISCV32)
387
- [CSR_HPMCOUNTER3H ... CSR_HPMCOUNTER31H] = { ctr, read_zero },
388
- [CSR_MHPMCOUNTER3H ... CSR_MHPMCOUNTER31H] = { any, read_zero },
389
-#endif
390
+ [CSR_HPMCOUNTER3H ... CSR_HPMCOUNTER31H] = { ctr32, read_zero },
391
+ [CSR_MHPMCOUNTER3H ... CSR_MHPMCOUNTER31H] = { any32, read_zero },
392
#endif /* !CONFIG_USER_ONLY */
393
};
394
--
395
2.29.2
396
397
diff view generated by jsdifflib
[PULL 21/23] target/riscv: cpu: Set XLEN independently from target
Deleted patch
1
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2
Reviewed-by: Bin Meng <bin.meng@windriver.com>
3
Tested-by: Bin Meng <bin.meng@windriver.com>
4
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
5
Acked-by: Palmer Dabbelt <palmerdabbelt@google.com>
6
Message-id: 7eddba45b5d223321c031431849fdd42eceb514b.1608142916.git.alistair.francis@wdc.com
7
---
8
target/riscv/cpu.c | 25 ++++++++++++++++---------
9
1 file changed, 16 insertions(+), 9 deletions(-)
10
1
11
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/riscv/cpu.c
14
+++ b/target/riscv/cpu.c
15
@@ -XXX,XX +XXX,XX @@ static void riscv_any_cpu_init(Object *obj)
16
set_priv_version(env, PRIV_VERSION_1_11_0);
17
}
18
19
-static void riscv_base_cpu_init(Object *obj)
20
+#if defined(TARGET_RISCV64)
21
+static void rv64_base_cpu_init(Object *obj)
22
{
23
CPURISCVState *env = &RISCV_CPU(obj)->env;
24
/* We set this in the realise function */
25
- set_misa(env, 0);
26
+ set_misa(env, RV64);
27
}
28
29
-#ifdef TARGET_RISCV64
30
static void rv64_sifive_u_cpu_init(Object *obj)
31
{
32
CPURISCVState *env = &RISCV_CPU(obj)->env;
33
@@ -XXX,XX +XXX,XX @@ static void rv64_sifive_e_cpu_init(Object *obj)
34
qdev_prop_set_bit(DEVICE(obj), "mmu", false);
35
}
36
#else
37
+static void rv32_base_cpu_init(Object *obj)
38
+{
39
+ CPURISCVState *env = &RISCV_CPU(obj)->env;
40
+ /* We set this in the realise function */
41
+ set_misa(env, RV32);
42
+}
43
+
44
static void rv32_sifive_u_cpu_init(Object *obj)
45
{
46
CPURISCVState *env = &RISCV_CPU(obj)->env;
47
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
48
RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev);
49
int priv_version = PRIV_VERSION_1_11_0;
50
int vext_version = VEXT_VERSION_0_07_1;
51
- target_ulong target_misa = 0;
52
+ target_ulong target_misa = env->misa;
53
Error *local_err = NULL;
54
55
cpu_exec_realizefn(cs, &local_err);
56
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
57
58
set_resetvec(env, cpu->cfg.resetvec);
59
60
- /* If misa isn't set (rv32 and rv64 machines) set it here */
61
- if (!env->misa) {
62
+ /* If only XLEN is set for misa, then set misa from properties */
63
+ if (env->misa == RV32 || env->misa == RV64) {
64
/* Do some ISA extension error checking */
65
if (cpu->cfg.ext_i && cpu->cfg.ext_e) {
66
error_setg(errp,
67
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
68
set_vext_version(env, vext_version);
69
}
70
71
- set_misa(env, RVXLEN | target_misa);
72
+ set_misa(env, target_misa);
73
}
74
75
riscv_cpu_register_gdb_regs_for_features(cs);
76
@@ -XXX,XX +XXX,XX @@ static const TypeInfo riscv_cpu_type_infos[] = {
77
},
78
DEFINE_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init),
79
#if defined(TARGET_RISCV32)
80
- DEFINE_CPU(TYPE_RISCV_CPU_BASE32, riscv_base_cpu_init),
81
+ DEFINE_CPU(TYPE_RISCV_CPU_BASE32, rv32_base_cpu_init),
82
DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32_ibex_cpu_init),
83
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32_sifive_e_cpu_init),
84
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32_imafcu_nommu_cpu_init),
85
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32_sifive_u_cpu_init),
86
#elif defined(TARGET_RISCV64)
87
- DEFINE_CPU(TYPE_RISCV_CPU_BASE64, riscv_base_cpu_init),
88
+ DEFINE_CPU(TYPE_RISCV_CPU_BASE64, rv64_base_cpu_init),
89
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64_sifive_e_cpu_init),
90
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64_sifive_u_cpu_init),
91
#endif
92
--
93
2.29.2
94
95
diff view generated by jsdifflib
[PULL 22/23] hw/riscv: Use the CPU to determine if 32-bit
Deleted patch
1
Instead of using string compares to determine if a RISC-V machine is
2
using 32-bit or 64-bit CPUs we can use the initalised CPUs. This avoids
3
us having to maintain a list of CPU names to compare against.
4
1
5
This commit also fixes the name of the function to match the
6
riscv_cpu_is_32bit() function.
7
8
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 8ab7614e5df93ab5267788b73dcd75f9f5615e82.1608142916.git.alistair.francis@wdc.com
11
---
12
include/hw/riscv/boot.h | 8 +++++---
13
hw/riscv/boot.c | 31 ++++++++++---------------------
14
hw/riscv/sifive_u.c | 10 +++++-----
15
hw/riscv/spike.c | 8 ++++----
16
hw/riscv/virt.c | 9 +++++----
17
5 files changed, 29 insertions(+), 37 deletions(-)
18
19
diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h
20
index XXXXXXX..XXXXXXX 100644
21
--- a/include/hw/riscv/boot.h
22
+++ b/include/hw/riscv/boot.h
23
@@ -XXX,XX +XXX,XX @@
24
25
#include "exec/cpu-defs.h"
26
#include "hw/loader.h"
27
+#include "hw/riscv/riscv_hart.h"
28
29
-bool riscv_is_32_bit(MachineState *machine);
30
+bool riscv_is_32bit(RISCVHartArrayState harts);
31
32
-target_ulong riscv_calc_kernel_start_addr(MachineState *machine,
33
+target_ulong riscv_calc_kernel_start_addr(RISCVHartArrayState harts,
34
target_ulong firmware_end_addr);
35
target_ulong riscv_find_and_load_firmware(MachineState *machine,
36
const char *default_machine_firmware,
37
@@ -XXX,XX +XXX,XX @@ target_ulong riscv_load_kernel(const char *kernel_filename,
38
hwaddr riscv_load_initrd(const char *filename, uint64_t mem_size,
39
uint64_t kernel_entry, hwaddr *start);
40
uint32_t riscv_load_fdt(hwaddr dram_start, uint64_t dram_size, void *fdt);
41
-void riscv_setup_rom_reset_vec(MachineState *machine, hwaddr saddr,
42
+void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState harts,
43
+ hwaddr saddr,
44
hwaddr rom_base, hwaddr rom_size,
45
uint64_t kernel_entry,
46
uint32_t fdt_load_addr, void *fdt);
47
diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
48
index XXXXXXX..XXXXXXX 100644
49
--- a/hw/riscv/boot.c
50
+++ b/hw/riscv/boot.c
51
@@ -XXX,XX +XXX,XX @@
52
53
#include <libfdt.h>
54
55
-bool riscv_is_32_bit(MachineState *machine)
56
+bool riscv_is_32bit(RISCVHartArrayState harts)
57
{
58
- /*
59
- * To determine if the CPU is 32-bit we need to check a few different CPUs.
60
- *
61
- * If the CPU starts with rv32
62
- * If the CPU is a sifive 3 seriries CPU (E31, U34)
63
- * If it's the Ibex CPU
64
- */
65
- if (!strncmp(machine->cpu_type, "rv32", 4) ||
66
- (!strncmp(machine->cpu_type, "sifive", 6) &&
67
- machine->cpu_type[8] == '3') ||
68
- !strncmp(machine->cpu_type, "lowrisc-ibex", 12)) {
69
- return true;
70
- } else {
71
- return false;
72
- }
73
+ RISCVCPU hart = harts.harts[0];
74
+
75
+ return riscv_cpu_is_32bit(&hart.env);
76
}
77
78
-target_ulong riscv_calc_kernel_start_addr(MachineState *machine,
79
+target_ulong riscv_calc_kernel_start_addr(RISCVHartArrayState harts,
80
target_ulong firmware_end_addr) {
81
- if (riscv_is_32_bit(machine)) {
82
+ if (riscv_is_32bit(harts)) {
83
return QEMU_ALIGN_UP(firmware_end_addr, 4 * MiB);
84
} else {
85
return QEMU_ALIGN_UP(firmware_end_addr, 2 * MiB);
86
@@ -XXX,XX +XXX,XX @@ void riscv_rom_copy_firmware_info(MachineState *machine, hwaddr rom_base,
87
&address_space_memory);
88
}
89
90
-void riscv_setup_rom_reset_vec(MachineState *machine, hwaddr start_addr,
91
+void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState harts,
92
+ hwaddr start_addr,
93
hwaddr rom_base, hwaddr rom_size,
94
uint64_t kernel_entry,
95
uint32_t fdt_load_addr, void *fdt)
96
@@ -XXX,XX +XXX,XX @@ void riscv_setup_rom_reset_vec(MachineState *machine, hwaddr start_addr,
97
int i;
98
uint32_t start_addr_hi32 = 0x00000000;
99
100
- if (!riscv_is_32_bit(machine)) {
101
+ if (!riscv_is_32bit(harts)) {
102
start_addr_hi32 = start_addr >> 32;
103
}
104
/* reset vector */
105
@@ -XXX,XX +XXX,XX @@ void riscv_setup_rom_reset_vec(MachineState *machine, hwaddr start_addr,
106
0x00000000,
107
/* fw_dyn: */
108
};
109
- if (riscv_is_32_bit(machine)) {
110
+ if (riscv_is_32bit(harts)) {
111
reset_vec[3] = 0x0202a583; /* lw a1, 32(t0) */
112
reset_vec[4] = 0x0182a283; /* lw t0, 24(t0) */
113
} else {
114
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
115
index XXXXXXX..XXXXXXX 100644
116
--- a/hw/riscv/sifive_u.c
117
+++ b/hw/riscv/sifive_u.c
118
@@ -XXX,XX +XXX,XX @@ static void sifive_u_machine_init(MachineState *machine)
119
120
/* create device tree */
121
create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline,
122
- riscv_is_32_bit(machine));
123
+ riscv_is_32bit(s->soc.u_cpus));
124
125
if (s->start_in_flash) {
126
/*
127
@@ -XXX,XX +XXX,XX @@ static void sifive_u_machine_init(MachineState *machine)
128
break;
129
}
130
131
- if (riscv_is_32_bit(machine)) {
132
+ if (riscv_is_32bit(s->soc.u_cpus)) {
133
firmware_end_addr = riscv_find_and_load_firmware(machine,
134
"opensbi-riscv32-generic-fw_dynamic.bin",
135
start_addr, NULL);
136
@@ -XXX,XX +XXX,XX @@ static void sifive_u_machine_init(MachineState *machine)
137
}
138
139
if (machine->kernel_filename) {
140
- kernel_start_addr = riscv_calc_kernel_start_addr(machine,
141
+ kernel_start_addr = riscv_calc_kernel_start_addr(s->soc.u_cpus,
142
firmware_end_addr);
143
144
kernel_entry = riscv_load_kernel(machine->kernel_filename,
145
@@ -XXX,XX +XXX,XX @@ static void sifive_u_machine_init(MachineState *machine)
146
/* Compute the fdt load address in dram */
147
fdt_load_addr = riscv_load_fdt(memmap[SIFIVE_U_DEV_DRAM].base,
148
machine->ram_size, s->fdt);
149
- if (!riscv_is_32_bit(machine)) {
150
+ if (!riscv_is_32bit(s->soc.u_cpus)) {
151
start_addr_hi32 = (uint64_t)start_addr >> 32;
152
}
153
154
@@ -XXX,XX +XXX,XX @@ static void sifive_u_machine_init(MachineState *machine)
155
0x00000000,
156
/* fw_dyn: */
157
};
158
- if (riscv_is_32_bit(machine)) {
159
+ if (riscv_is_32bit(s->soc.u_cpus)) {
160
reset_vec[4] = 0x0202a583; /* lw a1, 32(t0) */
161
reset_vec[5] = 0x0182a283; /* lw t0, 24(t0) */
162
} else {
163
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
164
index XXXXXXX..XXXXXXX 100644
165
--- a/hw/riscv/spike.c
166
+++ b/hw/riscv/spike.c
167
@@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine)
168
169
/* create device tree */
170
create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline,
171
- riscv_is_32_bit(machine));
172
+ riscv_is_32bit(s->soc[0]));
173
174
/* boot rom */
175
memory_region_init_rom(mask_rom, NULL, "riscv.spike.mrom",
176
@@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine)
177
* keeping ELF files here was intentional because BIN files don't work
178
* for the Spike machine as HTIF emulation depends on ELF parsing.
179
*/
180
- if (riscv_is_32_bit(machine)) {
181
+ if (riscv_is_32bit(s->soc[0])) {
182
firmware_end_addr = riscv_find_and_load_firmware(machine,
183
"opensbi-riscv32-generic-fw_dynamic.elf",
184
memmap[SPIKE_DRAM].base,
185
@@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine)
186
}
187
188
if (machine->kernel_filename) {
189
- kernel_start_addr = riscv_calc_kernel_start_addr(machine,
190
+ kernel_start_addr = riscv_calc_kernel_start_addr(s->soc[0],
191
firmware_end_addr);
192
193
kernel_entry = riscv_load_kernel(machine->kernel_filename,
194
@@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine)
195
fdt_load_addr = riscv_load_fdt(memmap[SPIKE_DRAM].base,
196
machine->ram_size, s->fdt);
197
/* load the reset vector */
198
- riscv_setup_rom_reset_vec(machine, memmap[SPIKE_DRAM].base,
199
+ riscv_setup_rom_reset_vec(machine, s->soc[0], memmap[SPIKE_DRAM].base,
200
memmap[SPIKE_MROM].base,
201
memmap[SPIKE_MROM].size, kernel_entry,
202
fdt_load_addr, s->fdt);
203
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
204
index XXXXXXX..XXXXXXX 100644
205
--- a/hw/riscv/virt.c
206
+++ b/hw/riscv/virt.c
207
@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
208
209
/* create device tree */
210
create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline,
211
- riscv_is_32_bit(machine));
212
+ riscv_is_32bit(s->soc[0]));
213
214
/* boot rom */
215
memory_region_init_rom(mask_rom, NULL, "riscv_virt_board.mrom",
216
@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
217
memory_region_add_subregion(system_memory, memmap[VIRT_MROM].base,
218
mask_rom);
219
220
- if (riscv_is_32_bit(machine)) {
221
+ if (riscv_is_32bit(s->soc[0])) {
222
firmware_end_addr = riscv_find_and_load_firmware(machine,
223
"opensbi-riscv32-generic-fw_dynamic.bin",
224
start_addr, NULL);
225
@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
226
}
227
228
if (machine->kernel_filename) {
229
- kernel_start_addr = riscv_calc_kernel_start_addr(machine,
230
+ kernel_start_addr = riscv_calc_kernel_start_addr(s->soc[0],
231
firmware_end_addr);
232
233
kernel_entry = riscv_load_kernel(machine->kernel_filename,
234
@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
235
fdt_load_addr = riscv_load_fdt(memmap[VIRT_DRAM].base,
236
machine->ram_size, s->fdt);
237
/* load the reset vector */
238
- riscv_setup_rom_reset_vec(machine, start_addr, virt_memmap[VIRT_MROM].base,
239
+ riscv_setup_rom_reset_vec(machine, s->soc[0], start_addr,
240
+ virt_memmap[VIRT_MROM].base,
241
virt_memmap[VIRT_MROM].size, kernel_entry,
242
fdt_load_addr, s->fdt);
243
244
--
245
2.29.2
246
247
diff view generated by jsdifflib
[PULL 23/23] riscv/opentitan: Update the OpenTitan memory layout
Deleted patch
1
OpenTitan is currently only avalible on an FPGA platform and the memory
2
addresses have changed. Update to use the new memory addresses.
3
1
4
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
5
Message-id: 8eb65314830a75d0fea3fccf77bc45b8ddd01c42.1607982831.git.alistair.francis@wdc.com
6
---
7
include/hw/riscv/opentitan.h | 23 +++++++---
8
hw/riscv/opentitan.c | 81 +++++++++++++++++++++++++-----------
9
2 files changed, 74 insertions(+), 30 deletions(-)
10
11
diff --git a/include/hw/riscv/opentitan.h b/include/hw/riscv/opentitan.h
12
index XXXXXXX..XXXXXXX 100644
13
--- a/include/hw/riscv/opentitan.h
14
+++ b/include/hw/riscv/opentitan.h
15
@@ -XXX,XX +XXX,XX @@ enum {
16
IBEX_DEV_UART,
17
IBEX_DEV_GPIO,
18
IBEX_DEV_SPI,
19
- IBEX_DEV_FLASH_CTRL,
20
+ IBEX_DEV_I2C,
21
+ IBEX_DEV_PATTGEN,
22
IBEX_DEV_RV_TIMER,
23
- IBEX_DEV_AES,
24
- IBEX_DEV_HMAC,
25
- IBEX_DEV_PLIC,
26
+ IBEX_DEV_SENSOR_CTRL,
27
+ IBEX_DEV_OTP_CTRL,
28
IBEX_DEV_PWRMGR,
29
IBEX_DEV_RSTMGR,
30
IBEX_DEV_CLKMGR,
31
IBEX_DEV_PINMUX,
32
+ IBEX_DEV_PADCTRL,
33
+ IBEX_DEV_USBDEV,
34
+ IBEX_DEV_FLASH_CTRL,
35
+ IBEX_DEV_PLIC,
36
+ IBEX_DEV_AES,
37
+ IBEX_DEV_HMAC,
38
+ IBEX_DEV_KMAC,
39
+ IBEX_DEV_KEYMGR,
40
+ IBEX_DEV_CSRNG,
41
+ IBEX_DEV_ENTROPY,
42
+ IBEX_DEV_EDNO,
43
+ IBEX_DEV_EDN1,
44
IBEX_DEV_ALERT_HANDLER,
45
IBEX_DEV_NMI_GEN,
46
- IBEX_DEV_USBDEV,
47
- IBEX_DEV_PADCTRL,
48
+ IBEX_DEV_OTBN,
49
};
50
51
enum {
52
diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
53
index XXXXXXX..XXXXXXX 100644
54
--- a/hw/riscv/opentitan.c
55
+++ b/hw/riscv/opentitan.c
56
@@ -XXX,XX +XXX,XX @@ static const struct MemmapEntry {
57
[IBEX_DEV_ROM] = { 0x00008000, 16 * KiB },
58
[IBEX_DEV_RAM] = { 0x10000000, 0x10000 },
59
[IBEX_DEV_FLASH] = { 0x20000000, 0x80000 },
60
- [IBEX_DEV_UART] = { 0x40000000, 0x10000 },
61
- [IBEX_DEV_GPIO] = { 0x40010000, 0x10000 },
62
- [IBEX_DEV_SPI] = { 0x40020000, 0x10000 },
63
- [IBEX_DEV_FLASH_CTRL] = { 0x40030000, 0x10000 },
64
- [IBEX_DEV_PINMUX] = { 0x40070000, 0x10000 },
65
- [IBEX_DEV_RV_TIMER] = { 0x40080000, 0x10000 },
66
- [IBEX_DEV_PLIC] = { 0x40090000, 0x10000 },
67
- [IBEX_DEV_PWRMGR] = { 0x400A0000, 0x10000 },
68
- [IBEX_DEV_RSTMGR] = { 0x400B0000, 0x10000 },
69
- [IBEX_DEV_CLKMGR] = { 0x400C0000, 0x10000 },
70
- [IBEX_DEV_AES] = { 0x40110000, 0x10000 },
71
- [IBEX_DEV_HMAC] = { 0x40120000, 0x10000 },
72
- [IBEX_DEV_ALERT_HANDLER] = { 0x40130000, 0x10000 },
73
- [IBEX_DEV_NMI_GEN] = { 0x40140000, 0x10000 },
74
- [IBEX_DEV_USBDEV] = { 0x40150000, 0x10000 },
75
- [IBEX_DEV_PADCTRL] = { 0x40160000, 0x10000 }
76
+ [IBEX_DEV_UART] = { 0x40000000, 0x1000 },
77
+ [IBEX_DEV_GPIO] = { 0x40040000, 0x1000 },
78
+ [IBEX_DEV_SPI] = { 0x40050000, 0x1000 },
79
+ [IBEX_DEV_I2C] = { 0x40080000, 0x1000 },
80
+ [IBEX_DEV_PATTGEN] = { 0x400e0000, 0x1000 },
81
+ [IBEX_DEV_RV_TIMER] = { 0x40100000, 0x1000 },
82
+ [IBEX_DEV_SENSOR_CTRL] = { 0x40110000, 0x1000 },
83
+ [IBEX_DEV_OTP_CTRL] = { 0x40130000, 0x4000 },
84
+ [IBEX_DEV_PWRMGR] = { 0x40400000, 0x1000 },
85
+ [IBEX_DEV_RSTMGR] = { 0x40410000, 0x1000 },
86
+ [IBEX_DEV_CLKMGR] = { 0x40420000, 0x1000 },
87
+ [IBEX_DEV_PINMUX] = { 0x40460000, 0x1000 },
88
+ [IBEX_DEV_PADCTRL] = { 0x40470000, 0x1000 },
89
+ [IBEX_DEV_USBDEV] = { 0x40500000, 0x1000 },
90
+ [IBEX_DEV_FLASH_CTRL] = { 0x41000000, 0x1000 },
91
+ [IBEX_DEV_PLIC] = { 0x41010000, 0x1000 },
92
+ [IBEX_DEV_AES] = { 0x41100000, 0x1000 },
93
+ [IBEX_DEV_HMAC] = { 0x41110000, 0x1000 },
94
+ [IBEX_DEV_KMAC] = { 0x41120000, 0x1000 },
95
+ [IBEX_DEV_KEYMGR] = { 0x41130000, 0x1000 },
96
+ [IBEX_DEV_CSRNG] = { 0x41150000, 0x1000 },
97
+ [IBEX_DEV_ENTROPY] = { 0x41160000, 0x1000 },
98
+ [IBEX_DEV_EDNO] = { 0x41170000, 0x1000 },
99
+ [IBEX_DEV_EDN1] = { 0x41180000, 0x1000 },
100
+ [IBEX_DEV_ALERT_HANDLER] = { 0x411b0000, 0x1000 },
101
+ [IBEX_DEV_NMI_GEN] = { 0x411c0000, 0x1000 },
102
+ [IBEX_DEV_OTBN] = { 0x411d0000, 0x10000 },
103
};
104
105
static void opentitan_board_init(MachineState *machine)
106
@@ -XXX,XX +XXX,XX @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
107
memmap[IBEX_DEV_GPIO].base, memmap[IBEX_DEV_GPIO].size);
108
create_unimplemented_device("riscv.lowrisc.ibex.spi",
109
memmap[IBEX_DEV_SPI].base, memmap[IBEX_DEV_SPI].size);
110
- create_unimplemented_device("riscv.lowrisc.ibex.flash_ctrl",
111
- memmap[IBEX_DEV_FLASH_CTRL].base, memmap[IBEX_DEV_FLASH_CTRL].size);
112
+ create_unimplemented_device("riscv.lowrisc.ibex.i2c",
113
+ memmap[IBEX_DEV_I2C].base, memmap[IBEX_DEV_I2C].size);
114
+ create_unimplemented_device("riscv.lowrisc.ibex.pattgen",
115
+ memmap[IBEX_DEV_PATTGEN].base, memmap[IBEX_DEV_PATTGEN].size);
116
create_unimplemented_device("riscv.lowrisc.ibex.rv_timer",
117
memmap[IBEX_DEV_RV_TIMER].base, memmap[IBEX_DEV_RV_TIMER].size);
118
+ create_unimplemented_device("riscv.lowrisc.ibex.sensor_ctrl",
119
+ memmap[IBEX_DEV_SENSOR_CTRL].base, memmap[IBEX_DEV_SENSOR_CTRL].size);
120
+ create_unimplemented_device("riscv.lowrisc.ibex.otp_ctrl",
121
+ memmap[IBEX_DEV_OTP_CTRL].base, memmap[IBEX_DEV_OTP_CTRL].size);
122
create_unimplemented_device("riscv.lowrisc.ibex.pwrmgr",
123
memmap[IBEX_DEV_PWRMGR].base, memmap[IBEX_DEV_PWRMGR].size);
124
create_unimplemented_device("riscv.lowrisc.ibex.rstmgr",
125
memmap[IBEX_DEV_RSTMGR].base, memmap[IBEX_DEV_RSTMGR].size);
126
create_unimplemented_device("riscv.lowrisc.ibex.clkmgr",
127
memmap[IBEX_DEV_CLKMGR].base, memmap[IBEX_DEV_CLKMGR].size);
128
+ create_unimplemented_device("riscv.lowrisc.ibex.pinmux",
129
+ memmap[IBEX_DEV_PINMUX].base, memmap[IBEX_DEV_PINMUX].size);
130
+ create_unimplemented_device("riscv.lowrisc.ibex.padctrl",
131
+ memmap[IBEX_DEV_PADCTRL].base, memmap[IBEX_DEV_PADCTRL].size);
132
+ create_unimplemented_device("riscv.lowrisc.ibex.usbdev",
133
+ memmap[IBEX_DEV_USBDEV].base, memmap[IBEX_DEV_USBDEV].size);
134
+ create_unimplemented_device("riscv.lowrisc.ibex.flash_ctrl",
135
+ memmap[IBEX_DEV_FLASH_CTRL].base, memmap[IBEX_DEV_FLASH_CTRL].size);
136
create_unimplemented_device("riscv.lowrisc.ibex.aes",
137
memmap[IBEX_DEV_AES].base, memmap[IBEX_DEV_AES].size);
138
create_unimplemented_device("riscv.lowrisc.ibex.hmac",
139
memmap[IBEX_DEV_HMAC].base, memmap[IBEX_DEV_HMAC].size);
140
- create_unimplemented_device("riscv.lowrisc.ibex.pinmux",
141
- memmap[IBEX_DEV_PINMUX].base, memmap[IBEX_DEV_PINMUX].size);
142
+ create_unimplemented_device("riscv.lowrisc.ibex.kmac",
143
+ memmap[IBEX_DEV_KMAC].base, memmap[IBEX_DEV_KMAC].size);
144
+ create_unimplemented_device("riscv.lowrisc.ibex.keymgr",
145
+ memmap[IBEX_DEV_KEYMGR].base, memmap[IBEX_DEV_KEYMGR].size);
146
+ create_unimplemented_device("riscv.lowrisc.ibex.csrng",
147
+ memmap[IBEX_DEV_CSRNG].base, memmap[IBEX_DEV_CSRNG].size);
148
+ create_unimplemented_device("riscv.lowrisc.ibex.entropy",
149
+ memmap[IBEX_DEV_ENTROPY].base, memmap[IBEX_DEV_ENTROPY].size);
150
+ create_unimplemented_device("riscv.lowrisc.ibex.edn0",
151
+ memmap[IBEX_DEV_EDNO].base, memmap[IBEX_DEV_EDNO].size);
152
+ create_unimplemented_device("riscv.lowrisc.ibex.edn1",
153
+ memmap[IBEX_DEV_EDN1].base, memmap[IBEX_DEV_EDN1].size);
154
create_unimplemented_device("riscv.lowrisc.ibex.alert_handler",
155
memmap[IBEX_DEV_ALERT_HANDLER].base, memmap[IBEX_DEV_ALERT_HANDLER].size);
156
create_unimplemented_device("riscv.lowrisc.ibex.nmi_gen",
157
memmap[IBEX_DEV_NMI_GEN].base, memmap[IBEX_DEV_NMI_GEN].size);
158
- create_unimplemented_device("riscv.lowrisc.ibex.usbdev",
159
- memmap[IBEX_DEV_USBDEV].base, memmap[IBEX_DEV_USBDEV].size);
160
- create_unimplemented_device("riscv.lowrisc.ibex.padctrl",
161
- memmap[IBEX_DEV_PADCTRL].base, memmap[IBEX_DEV_PADCTRL].size);
162
+ create_unimplemented_device("riscv.lowrisc.ibex.otbn",
163
+ memmap[IBEX_DEV_OTBN].base, memmap[IBEX_DEV_OTBN].size);
164
}
165
166
static void lowrisc_ibex_soc_class_init(ObjectClass *oc, void *data)
167
--
168
2.29.2
169
170
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

© 2016 - 2025 Red Hat, Inc.