[PULL 00/20] target-arm queue
[PULL 00/35] target-arm queue
1
A grab-bag of minor stuff for the end of the year. My to-review
1
The following changes since commit 5767815218efd3cbfd409505ed824d5f356044ae:
2
queue is not empty, but it it at least in single figures...
3
2
4
-- PMM
3
Merge tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu into staging (2024-02-14 15:45:52 +0000)
5
6
The following changes since commit 5bfbd8170ce7acb98a1834ff49ed7340b0837144:
7
8
Merge remote-tracking branch 'remotes/vivier2/tags/trivial-branch-for-6.0-pull-request' into staging (2020-12-14 20:32:38 +0000)
9
4
10
are available in the Git repository at:
5
are available in the Git repository at:
11
6
12
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20201215
7
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20240215
13
8
14
for you to fetch changes up to 23af268566069183285bebbdf95b1b37cb7c0942:
9
for you to fetch changes up to f780e63fe731b058fe52d43653600d8729a1b5f2:
15
10
16
hw/block/m25p80: Fix Numonyx fast read dummy cycle count (2020-12-15 13:39:30 +0000)
11
docs: Add documentation for the mps3-an536 board (2024-02-15 14:32:39 +0000)
17
12
18
----------------------------------------------------------------
13
----------------------------------------------------------------
19
target-arm queue:
14
target-arm queue:
20
* gdbstub: Correct misparsing of vCont C/S requests
15
* hw/arm/xilinx_zynq: Wire FIQ between CPU <> GIC
21
* openrisc: Move pic_cpu code into CPU object proper
16
* linux-user/aarch64: Choose SYNC as the preferred MTE mode
22
* nios2: Move IIC code into CPU object proper
17
* Fix some errors in SVE/SME handling of MTE tags
23
* Improve reporting of ROM overlap errors
18
* hw/pci-host/raven.c: Mark raven_io_ops as implementing unaligned accesses
24
* xlnx-versal: Add USB support
19
* hw/block/tc58128: Don't emit deprecation warning under qtest
25
* hw/misc/zynq_slcr: Avoid #DIV/0! error
20
* tests/qtest: Fix handling of npcm7xx and GMAC tests
26
* Numonyx: Fix dummy cycles and check for SPI mode on cmds
21
* hw/arm/virt: Wire up non-secure EL2 virtual timer IRQ
22
* tests/qtest/npcm7xx_emc-test: Connect all NICs to a backend
23
* Don't assert on vmload/vmsave of M-profile CPUs
24
* hw/arm/smmuv3: add support for stage 1 access fault
25
* hw/arm/stellaris: QOM cleanups
26
* Use new CBAR encoding for all v8 CPUs, not all aarch64 CPUs
27
* Improve Cortex_R52 IMPDEF sysreg modelling
28
* Allow access to SPSR_hyp from hyp mode
29
* New board model mps3-an536 (Cortex-R52)
27
30
28
----------------------------------------------------------------
31
----------------------------------------------------------------
29
Joe Komlodi (4):
32
Luc Michel (1):
30
hw/block/m25p80: Make Numonyx config field names more accurate
33
hw/arm/smmuv3: add support for stage 1 access fault
31
hw/block/m25p80: Fix when VCFG XIP bit is set for Numonyx
32
hw/block/m25p80: Check SPI mode before running some Numonyx commands
33
hw/block/m25p80: Fix Numonyx fast read dummy cycle count
34
34
35
Peter Maydell (11):
35
Nabih Estefan (1):
36
gdbstub: Correct misparsing of vCont C/S requests
36
tests/qtest: Fix GMAC test to run on a machine in upstream QEMU
37
hw/openrisc/openrisc_sim: Use IRQ splitter when connecting IRQ to multiple CPUs
38
hw/openrisc/openrisc_sim: Abstract out "get IRQ x of CPU y"
39
target/openrisc: Move pic_cpu code into CPU object proper
40
target/nios2: Move IIC code into CPU object proper
41
target/nios2: Move nios2_check_interrupts() into target/nios2
42
target/nios2: Use deposit32() to update ipending register
43
hw/core/loader.c: Track last-seen ROM in rom_check_and_register_reset()
44
hw/core/loader.c: Improve reporting of ROM overlap errors
45
elf_ops.h: Don't truncate name of the ROM blobs we create
46
elf_ops.h: Be more verbose with ROM blob names
47
37
48
Philippe Mathieu-Daudé (1):
38
Peter Maydell (22):
49
hw/misc/zynq_slcr: Avoid #DIV/0! error
39
hw/pci-host/raven.c: Mark raven_io_ops as implementing unaligned accesses
40
hw/block/tc58128: Don't emit deprecation warning under qtest
41
tests/qtest/meson.build: Don't include qtests_npcm7xx in qtests_aarch64
42
tests/qtest/bios-tables-test: Allow changes to virt GTDT
43
hw/arm/virt: Wire up non-secure EL2 virtual timer IRQ
44
tests/qtest/bios-tables-tests: Update virt golden reference
45
hw/arm/npcm7xx: Call qemu_configure_nic_device() for GMAC modules
46
tests/qtest/npcm7xx_emc-test: Connect all NICs to a backend
47
target/arm: Don't get MDCR_EL2 in pmu_counter_enabled() before checking ARM_FEATURE_PMU
48
target/arm: Use new CBAR encoding for all v8 CPUs, not all aarch64 CPUs
49
target/arm: The Cortex-R52 has a read-only CBAR
50
target/arm: Add Cortex-R52 IMPDEF sysregs
51
target/arm: Allow access to SPSR_hyp from hyp mode
52
hw/misc/mps2-scc: Fix condition for CFG3 register
53
hw/misc/mps2-scc: Factor out which-board conditionals
54
hw/misc/mps2-scc: Make changes needed for AN536 FPGA image
55
hw/arm/mps3r: Initial skeleton for mps3-an536 board
56
hw/arm/mps3r: Add CPUs, GIC, and per-CPU RAM
57
hw/arm/mps3r: Add UARTs
58
hw/arm/mps3r: Add GPIO, watchdog, dual-timer, I2C devices
59
hw/arm/mps3r: Add remaining devices
60
docs: Add documentation for the mps3-an536 board
50
61
51
Sai Pavan Boddu (2):
62
Philippe Mathieu-Daudé (5):
52
usb: Add versal-usb2-ctrl-regs module
63
hw/arm/xilinx_zynq: Wire FIQ between CPU <> GIC
53
usb: xlnx-usb-subsystem: Add xilinx usb subsystem
64
hw/arm/stellaris: Convert ADC controller to Resettable interface
65
hw/arm/stellaris: Convert I2C controller to Resettable interface
66
hw/arm/stellaris: Add missing QOM 'machine' parent
67
hw/arm/stellaris: Add missing QOM 'SoC' parent
54
68
55
Vikram Garhwal (2):
69
Richard Henderson (6):
56
usb: Add DWC3 model
70
linux-user/aarch64: Choose SYNC as the preferred MTE mode
57
arm: xlnx-versal: Connect usb to virt-versal
71
target/arm: Fix nregs computation in do_{ld,st}_zpa
72
target/arm: Adjust and validate mtedesc sizem1
73
target/arm: Split out make_svemte_desc
74
target/arm: Handle mte in do_ldrq, do_ldro
75
target/arm: Fix SVE/SME gross MTE suppression checks
58
76
59
include/hw/arm/xlnx-versal.h | 9 +
77
MAINTAINERS | 3 +-
60
include/hw/elf_ops.h | 5 +-
78
docs/system/arm/mps2.rst | 37 +-
61
include/hw/usb/hcd-dwc3.h | 55 +++
79
configs/devices/arm-softmmu/default.mak | 1 +
62
include/hw/usb/xlnx-usb-subsystem.h | 45 ++
80
hw/arm/smmuv3-internal.h | 1 +
63
include/hw/usb/xlnx-versal-usb2-ctrl-regs.h | 45 ++
81
include/hw/arm/smmu-common.h | 1 +
64
target/nios2/cpu.h | 3 -
82
include/hw/arm/virt.h | 2 +
65
target/openrisc/cpu.h | 1 -
83
include/hw/misc/mps2-scc.h | 1 +
66
gdbstub.c | 2 +-
84
linux-user/aarch64/target_prctl.h | 29 +-
67
hw/arm/xlnx-versal-virt.c | 55 +++
85
target/arm/internals.h | 2 +-
68
hw/arm/xlnx-versal.c | 26 ++
86
target/arm/tcg/translate-a64.h | 2 +
69
hw/block/m25p80.c | 158 +++++--
87
hw/arm/mps3r.c | 640 ++++++++++++++++++++++++++++++++
70
hw/core/loader.c | 67 ++-
88
hw/arm/npcm7xx.c | 1 +
71
hw/intc/nios2_iic.c | 95 ----
89
hw/arm/smmu-common.c | 11 +
72
hw/misc/zynq_slcr.c | 5 +
90
hw/arm/smmuv3.c | 1 +
73
hw/nios2/10m50_devboard.c | 13 +-
91
hw/arm/stellaris.c | 47 ++-
74
hw/nios2/cpu_pic.c | 67 ---
92
hw/arm/virt-acpi-build.c | 20 +-
75
hw/openrisc/openrisc_sim.c | 46 +-
93
hw/arm/virt.c | 60 ++-
76
hw/openrisc/pic_cpu.c | 61 ---
94
hw/arm/xilinx_zynq.c | 2 +
77
hw/usb/hcd-dwc3.c | 689 ++++++++++++++++++++++++++++
95
hw/block/tc58128.c | 4 +-
78
hw/usb/xlnx-usb-subsystem.c | 94 ++++
96
hw/misc/mps2-scc.c | 138 ++++++-
79
hw/usb/xlnx-versal-usb2-ctrl-regs.c | 229 +++++++++
97
hw/pci-host/raven.c | 1 +
80
softmmu/vl.c | 1 -
98
target/arm/helper.c | 14 +-
81
target/nios2/cpu.c | 29 ++
99
target/arm/tcg/cpu32.c | 109 ++++++
82
target/nios2/op_helper.c | 9 +
100
target/arm/tcg/op_helper.c | 43 ++-
83
target/openrisc/cpu.c | 32 ++
101
target/arm/tcg/sme_helper.c | 8 +-
84
MAINTAINERS | 1 -
102
target/arm/tcg/sve_helper.c | 12 +-
85
hw/intc/meson.build | 1 -
103
target/arm/tcg/translate-sme.c | 15 +-
86
hw/nios2/meson.build | 2 +-
104
target/arm/tcg/translate-sve.c | 83 +++--
87
hw/openrisc/Kconfig | 1 +
105
target/arm/tcg/translate.c | 19 +-
88
hw/openrisc/meson.build | 2 +-
106
tests/qtest/npcm7xx_emc-test.c | 5 +-
89
hw/usb/Kconfig | 10 +
107
tests/qtest/npcm_gmac-test.c | 84 +----
90
hw/usb/meson.build | 3 +
108
hw/arm/Kconfig | 5 +
91
32 files changed, 1557 insertions(+), 304 deletions(-)
109
hw/arm/meson.build | 1 +
92
create mode 100644 include/hw/usb/hcd-dwc3.h
110
tests/data/acpi/virt/FACP | Bin 276 -> 276 bytes
93
create mode 100644 include/hw/usb/xlnx-usb-subsystem.h
111
tests/data/acpi/virt/GTDT | Bin 96 -> 104 bytes
94
create mode 100644 include/hw/usb/xlnx-versal-usb2-ctrl-regs.h
112
tests/qtest/meson.build | 4 +-
95
delete mode 100644 hw/intc/nios2_iic.c
113
36 files changed, 1184 insertions(+), 222 deletions(-)
96
delete mode 100644 hw/nios2/cpu_pic.c
114
create mode 100644 hw/arm/mps3r.c
97
delete mode 100644 hw/openrisc/pic_cpu.c
98
create mode 100644 hw/usb/hcd-dwc3.c
99
create mode 100644 hw/usb/xlnx-usb-subsystem.c
100
create mode 100644 hw/usb/xlnx-versal-usb2-ctrl-regs.c
101
115
diff view generated by jsdifflib
[PULL 19/20] hw/block/m25p80: Check SPI mode before running some Numonyx commands
[PULL 01/35] hw/arm/xilinx_zynq: Wire FIQ between CPU <> GIC
1
From: Joe Komlodi <joe.komlodi@xilinx.com>
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
2
2
3
Some Numonyx flash commands cannot be executed in DIO and QIO mode, such as
3
Similarly to commits dadbb58f59..5ae79fe825 for other ARM boards,
4
trying to do DPP or DOR when in QIO mode.
4
connect FIQ output of the GIC CPU interfaces to the CPU.
5
5
6
Signed-off-by: Joe Komlodi <komlodi@xilinx.com>
6
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
7
Reviewed-by: Francisco Iglesias <francisco.iglesias@xilinx.com>
7
Message-id: 20240130152548.17855-1-philmd@linaro.org
8
Message-id: 1605568264-26376-4-git-send-email-komlodi@xilinx.com
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
10
---
11
hw/block/m25p80.c | 114 ++++++++++++++++++++++++++++++++++++++--------
11
hw/arm/xilinx_zynq.c | 2 ++
12
1 file changed, 95 insertions(+), 19 deletions(-)
12
1 file changed, 2 insertions(+)
13
13
14
diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
14
diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c
15
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/block/m25p80.c
16
--- a/hw/arm/xilinx_zynq.c
17
+++ b/hw/block/m25p80.c
17
+++ b/hw/arm/xilinx_zynq.c
18
@@ -XXX,XX +XXX,XX @@ typedef enum {
18
@@ -XXX,XX +XXX,XX @@ static void zynq_init(MachineState *machine)
19
MAN_GENERIC,
19
sysbus_mmio_map(busdev, 0, MPCORE_PERIPHBASE);
20
} Manufacturer;
20
sysbus_connect_irq(busdev, 0,
21
21
qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ));
22
+typedef enum {
22
+ sysbus_connect_irq(busdev, 1,
23
+ MODE_STD = 0,
23
+ qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_FIQ));
24
+ MODE_DIO = 1,
24
25
+ MODE_QIO = 2
25
for (n = 0; n < 64; n++) {
26
+} SPIMode;
26
pic[n] = qdev_get_gpio_in(dev, n);
27
+
28
#define M25P80_INTERNAL_DATA_BUFFER_SZ 16
29
30
struct Flash {
31
@@ -XXX,XX +XXX,XX @@ static void reset_memory(Flash *s)
32
trace_m25p80_reset_done(s);
33
}
34
35
+static uint8_t numonyx_mode(Flash *s)
36
+{
37
+ if (!(s->enh_volatile_cfg & EVCFG_QUAD_IO_DISABLED)) {
38
+ return MODE_QIO;
39
+ } else if (!(s->enh_volatile_cfg & EVCFG_DUAL_IO_DISABLED)) {
40
+ return MODE_DIO;
41
+ } else {
42
+ return MODE_STD;
43
+ }
44
+}
45
+
46
static void decode_fast_read_cmd(Flash *s)
47
{
48
s->needed_bytes = get_addr_length(s);
49
@@ -XXX,XX +XXX,XX @@ static void decode_new_cmd(Flash *s, uint32_t value)
50
case ERASE4_32K:
51
case ERASE_SECTOR:
52
case ERASE4_SECTOR:
53
- case READ:
54
- case READ4:
55
- case DPP:
56
- case QPP:
57
- case QPP_4:
58
case PP:
59
case PP4:
60
- case PP4_4:
61
case DIE_ERASE:
62
case RDID_90:
63
case RDID_AB:
64
@@ -XXX,XX +XXX,XX @@ static void decode_new_cmd(Flash *s, uint32_t value)
65
s->len = 0;
66
s->state = STATE_COLLECTING_DATA;
67
break;
68
+ case READ:
69
+ case READ4:
70
+ if (get_man(s) != MAN_NUMONYX || numonyx_mode(s) == MODE_STD) {
71
+ s->needed_bytes = get_addr_length(s);
72
+ s->pos = 0;
73
+ s->len = 0;
74
+ s->state = STATE_COLLECTING_DATA;
75
+ } else {
76
+ qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute cmd %x in "
77
+ "DIO or QIO mode\n", s->cmd_in_progress);
78
+ }
79
+ break;
80
+ case DPP:
81
+ if (get_man(s) != MAN_NUMONYX || numonyx_mode(s) != MODE_QIO) {
82
+ s->needed_bytes = get_addr_length(s);
83
+ s->pos = 0;
84
+ s->len = 0;
85
+ s->state = STATE_COLLECTING_DATA;
86
+ } else {
87
+ qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute cmd %x in "
88
+ "QIO mode\n", s->cmd_in_progress);
89
+ }
90
+ break;
91
+ case QPP:
92
+ case QPP_4:
93
+ case PP4_4:
94
+ if (get_man(s) != MAN_NUMONYX || numonyx_mode(s) != MODE_DIO) {
95
+ s->needed_bytes = get_addr_length(s);
96
+ s->pos = 0;
97
+ s->len = 0;
98
+ s->state = STATE_COLLECTING_DATA;
99
+ } else {
100
+ qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute cmd %x in "
101
+ "DIO mode\n", s->cmd_in_progress);
102
+ }
103
+ break;
104
105
case FAST_READ:
106
case FAST_READ4:
107
+ decode_fast_read_cmd(s);
108
+ break;
109
case DOR:
110
case DOR4:
111
+ if (get_man(s) != MAN_NUMONYX || numonyx_mode(s) != MODE_QIO) {
112
+ decode_fast_read_cmd(s);
113
+ } else {
114
+ qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute cmd %x in "
115
+ "QIO mode\n", s->cmd_in_progress);
116
+ }
117
+ break;
118
case QOR:
119
case QOR4:
120
- decode_fast_read_cmd(s);
121
+ if (get_man(s) != MAN_NUMONYX || numonyx_mode(s) != MODE_DIO) {
122
+ decode_fast_read_cmd(s);
123
+ } else {
124
+ qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute cmd %x in "
125
+ "DIO mode\n", s->cmd_in_progress);
126
+ }
127
break;
128
129
case DIOR:
130
case DIOR4:
131
- decode_dio_read_cmd(s);
132
+ if (get_man(s) != MAN_NUMONYX || numonyx_mode(s) != MODE_QIO) {
133
+ decode_dio_read_cmd(s);
134
+ } else {
135
+ qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute cmd %x in "
136
+ "QIO mode\n", s->cmd_in_progress);
137
+ }
138
break;
139
140
case QIOR:
141
case QIOR4:
142
- decode_qio_read_cmd(s);
143
+ if (get_man(s) != MAN_NUMONYX || numonyx_mode(s) != MODE_DIO) {
144
+ decode_qio_read_cmd(s);
145
+ } else {
146
+ qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute cmd %x in "
147
+ "DIO mode\n", s->cmd_in_progress);
148
+ }
149
break;
150
151
case WRSR:
152
@@ -XXX,XX +XXX,XX @@ static void decode_new_cmd(Flash *s, uint32_t value)
153
break;
154
155
case JEDEC_READ:
156
- trace_m25p80_populated_jedec(s);
157
- for (i = 0; i < s->pi->id_len; i++) {
158
- s->data[i] = s->pi->id[i];
159
- }
160
- for (; i < SPI_NOR_MAX_ID_LEN; i++) {
161
- s->data[i] = 0;
162
- }
163
+ if (get_man(s) != MAN_NUMONYX || numonyx_mode(s) == MODE_STD) {
164
+ trace_m25p80_populated_jedec(s);
165
+ for (i = 0; i < s->pi->id_len; i++) {
166
+ s->data[i] = s->pi->id[i];
167
+ }
168
+ for (; i < SPI_NOR_MAX_ID_LEN; i++) {
169
+ s->data[i] = 0;
170
+ }
171
172
- s->len = SPI_NOR_MAX_ID_LEN;
173
- s->pos = 0;
174
- s->state = STATE_READING_DATA;
175
+ s->len = SPI_NOR_MAX_ID_LEN;
176
+ s->pos = 0;
177
+ s->state = STATE_READING_DATA;
178
+ } else {
179
+ qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute JEDEC read "
180
+ "in DIO or QIO mode\n");
181
+ }
182
break;
183
184
case RDCR:
185
--
27
--
186
2.20.1
28
2.34.1
187
29
188
30
diff view generated by jsdifflib
New patch
[PULL 02/35] linux-user/aarch64: Choose SYNC as the preferred MTE mode
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
The API does not generate an error for setting ASYNC | SYNC; that merely
4
constrains the selection vs the per-cpu default. For qemu linux-user,
5
choose SYNC as the default.
6
7
Cc: qemu-stable@nongnu.org
8
Reported-by: Gustavo Romero <gustavo.romero@linaro.org>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
Tested-by: Gustavo Romero <gustavo.romero@linaro.org>
11
Message-id: 20240207025210.8837-2-richard.henderson@linaro.org
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
14
linux-user/aarch64/target_prctl.h | 29 +++++++++++++++++------------
15
1 file changed, 17 insertions(+), 12 deletions(-)
16
17
diff --git a/linux-user/aarch64/target_prctl.h b/linux-user/aarch64/target_prctl.h
18
index XXXXXXX..XXXXXXX 100644
19
--- a/linux-user/aarch64/target_prctl.h
20
+++ b/linux-user/aarch64/target_prctl.h
21
@@ -XXX,XX +XXX,XX @@ static abi_long do_prctl_set_tagged_addr_ctrl(CPUArchState *env, abi_long arg2)
22
env->tagged_addr_enable = arg2 & PR_TAGGED_ADDR_ENABLE;
23
24
if (cpu_isar_feature(aa64_mte, cpu)) {
25
- switch (arg2 & PR_MTE_TCF_MASK) {
26
- case PR_MTE_TCF_NONE:
27
- case PR_MTE_TCF_SYNC:
28
- case PR_MTE_TCF_ASYNC:
29
- break;
30
- default:
31
- return -EINVAL;
32
- }
33
-
34
/*
35
* Write PR_MTE_TCF to SCTLR_EL1[TCF0].
36
- * Note that the syscall values are consistent with hw.
37
+ *
38
+ * The kernel has a per-cpu configuration for the sysadmin,
39
+ * /sys/devices/system/cpu/cpu<N>/mte_tcf_preferred,
40
+ * which qemu does not implement.
41
+ *
42
+ * Because there is no performance difference between the modes, and
43
+ * because SYNC is most useful for debugging MTE errors, choose SYNC
44
+ * as the preferred mode. With this preference, and the way the API
45
+ * uses only two bits, there is no way for the program to select
46
+ * ASYMM mode.
47
*/
48
- env->cp15.sctlr_el[1] =
49
- deposit64(env->cp15.sctlr_el[1], 38, 2, arg2 >> PR_MTE_TCF_SHIFT);
50
+ unsigned tcf = 0;
51
+ if (arg2 & PR_MTE_TCF_SYNC) {
52
+ tcf = 1;
53
+ } else if (arg2 & PR_MTE_TCF_ASYNC) {
54
+ tcf = 2;
55
+ }
56
+ env->cp15.sctlr_el[1] = deposit64(env->cp15.sctlr_el[1], 38, 2, tcf);
57
58
/*
59
* Write PR_MTE_TAG to GCR_EL1[Exclude].
60
--
61
2.34.1
diff view generated by jsdifflib
New patch
[PULL 03/35] target/arm: Fix nregs computation in do_{ld,st}_zpa
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
The field is encoded as [0-3], which is convenient for
4
indexing our array of function pointers, but the true
5
value is [1-4]. Adjust before calling do_mem_zpa.
6
7
Add an assert, and move the comment re passing ZT to
8
the helper back next to the relevant code.
9
10
Cc: qemu-stable@nongnu.org
11
Fixes: 206adacfb8d ("target/arm: Add mte helpers for sve scalar + int loads")
12
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
13
Tested-by: Gustavo Romero <gustavo.romero@linaro.org>
14
Message-id: 20240207025210.8837-3-richard.henderson@linaro.org
15
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
---
18
target/arm/tcg/translate-sve.c | 16 ++++++++--------
19
1 file changed, 8 insertions(+), 8 deletions(-)
20
21
diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c
22
index XXXXXXX..XXXXXXX 100644
23
--- a/target/arm/tcg/translate-sve.c
24
+++ b/target/arm/tcg/translate-sve.c
25
@@ -XXX,XX +XXX,XX @@ static void do_mem_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr,
26
TCGv_ptr t_pg;
27
int desc = 0;
28
29
- /*
30
- * For e.g. LD4, there are not enough arguments to pass all 4
31
- * registers as pointers, so encode the regno into the data field.
32
- * For consistency, do this even for LD1.
33
- */
34
+ assert(mte_n >= 1 && mte_n <= 4);
35
if (s->mte_active[0]) {
36
int msz = dtype_msz(dtype);
37
38
@@ -XXX,XX +XXX,XX @@ static void do_mem_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr,
39
addr = clean_data_tbi(s, addr);
40
}
41
42
+ /*
43
+ * For e.g. LD4, there are not enough arguments to pass all 4
44
+ * registers as pointers, so encode the regno into the data field.
45
+ * For consistency, do this even for LD1.
46
+ */
47
desc = simd_desc(vsz, vsz, zt | desc);
48
t_pg = tcg_temp_new_ptr();
49
50
@@ -XXX,XX +XXX,XX @@ static void do_ld_zpa(DisasContext *s, int zt, int pg,
51
* accessible via the instruction encoding.
52
*/
53
assert(fn != NULL);
54
- do_mem_zpa(s, zt, pg, addr, dtype, nreg, false, fn);
55
+ do_mem_zpa(s, zt, pg, addr, dtype, nreg + 1, false, fn);
56
}
57
58
static bool trans_LD_zprr(DisasContext *s, arg_rprr_load *a)
59
@@ -XXX,XX +XXX,XX @@ static void do_st_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr,
60
if (nreg == 0) {
61
/* ST1 */
62
fn = fn_single[s->mte_active[0]][be][msz][esz];
63
- nreg = 1;
64
} else {
65
/* ST2, ST3, ST4 -- msz == esz, enforced by encoding */
66
assert(msz == esz);
67
fn = fn_multiple[s->mte_active[0]][be][nreg - 1][msz];
68
}
69
assert(fn != NULL);
70
- do_mem_zpa(s, zt, pg, addr, msz_dtype(s, msz), nreg, true, fn);
71
+ do_mem_zpa(s, zt, pg, addr, msz_dtype(s, msz), nreg + 1, true, fn);
72
}
73
74
static bool trans_ST_zprr(DisasContext *s, arg_rprr_store *a)
75
--
76
2.34.1
diff view generated by jsdifflib
New patch
[PULL 04/35] target/arm: Adjust and validate mtedesc sizem1
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
When we added SVE_MTEDESC_SHIFT, we effectively limited the
4
maximum size of MTEDESC. Adjust SIZEM1 to consume the remaining
5
bits (32 - 10 - 5 - 12 == 5). Assert that the data to be stored
6
fits within the field (expecting 8 * 4 - 1 == 31, exact fit).
7
8
Cc: qemu-stable@nongnu.org
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
11
Tested-by: Gustavo Romero <gustavo.romero@linaro.org>
12
Message-id: 20240207025210.8837-4-richard.henderson@linaro.org
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
15
target/arm/internals.h | 2 +-
16
target/arm/tcg/translate-sve.c | 7 ++++---
17
2 files changed, 5 insertions(+), 4 deletions(-)
18
19
diff --git a/target/arm/internals.h b/target/arm/internals.h
20
index XXXXXXX..XXXXXXX 100644
21
--- a/target/arm/internals.h
22
+++ b/target/arm/internals.h
23
@@ -XXX,XX +XXX,XX @@ FIELD(MTEDESC, TBI, 4, 2)
24
FIELD(MTEDESC, TCMA, 6, 2)
25
FIELD(MTEDESC, WRITE, 8, 1)
26
FIELD(MTEDESC, ALIGN, 9, 3)
27
-FIELD(MTEDESC, SIZEM1, 12, SIMD_DATA_BITS - 12) /* size - 1 */
28
+FIELD(MTEDESC, SIZEM1, 12, SIMD_DATA_BITS - SVE_MTEDESC_SHIFT - 12) /* size - 1 */
29
30
bool mte_probe(CPUARMState *env, uint32_t desc, uint64_t ptr);
31
uint64_t mte_check(CPUARMState *env, uint32_t desc, uint64_t ptr, uintptr_t ra);
32
diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c
33
index XXXXXXX..XXXXXXX 100644
34
--- a/target/arm/tcg/translate-sve.c
35
+++ b/target/arm/tcg/translate-sve.c
36
@@ -XXX,XX +XXX,XX @@ static void do_mem_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr,
37
{
38
unsigned vsz = vec_full_reg_size(s);
39
TCGv_ptr t_pg;
40
+ uint32_t sizem1;
41
int desc = 0;
42
43
assert(mte_n >= 1 && mte_n <= 4);
44
+ sizem1 = (mte_n << dtype_msz(dtype)) - 1;
45
+ assert(sizem1 <= R_MTEDESC_SIZEM1_MASK >> R_MTEDESC_SIZEM1_SHIFT);
46
if (s->mte_active[0]) {
47
- int msz = dtype_msz(dtype);
48
-
49
desc = FIELD_DP32(desc, MTEDESC, MIDX, get_mem_index(s));
50
desc = FIELD_DP32(desc, MTEDESC, TBI, s->tbid);
51
desc = FIELD_DP32(desc, MTEDESC, TCMA, s->tcma);
52
desc = FIELD_DP32(desc, MTEDESC, WRITE, is_write);
53
- desc = FIELD_DP32(desc, MTEDESC, SIZEM1, (mte_n << msz) - 1);
54
+ desc = FIELD_DP32(desc, MTEDESC, SIZEM1, sizem1);
55
desc <<= SVE_MTEDESC_SHIFT;
56
} else {
57
addr = clean_data_tbi(s, addr);
58
--
59
2.34.1
diff view generated by jsdifflib
[PULL 15/20] arm: xlnx-versal: Connect usb to virt-versal
[PULL 05/35] target/arm: Split out make_svemte_desc
1
From: Vikram Garhwal <fnu.vikram@xilinx.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Connect VersalUsb2 subsystem to xlnx-versal SOC, its placed
3
Share code that creates mtedesc and embeds within simd_desc.
4
in iou of lpd domain and configure it as dual port host controller.
5
Add the respective guest dts nodes for "xlnx-versal-virt" machine.
6
4
7
Signed-off-by: Vikram Garhwal <fnu.vikram@xilinx.com>
5
Cc: qemu-stable@nongnu.org
8
Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 1607023357-5096-5-git-send-email-sai.pavan.boddu@xilinx.com
8
Tested-by: Gustavo Romero <gustavo.romero@linaro.org>
9
Message-id: 20240207025210.8837-5-richard.henderson@linaro.org
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
11
---
13
include/hw/arm/xlnx-versal.h | 9 ++++++
12
target/arm/tcg/translate-a64.h | 2 ++
14
hw/arm/xlnx-versal-virt.c | 55 ++++++++++++++++++++++++++++++++++++
13
target/arm/tcg/translate-sme.c | 15 +++--------
15
hw/arm/xlnx-versal.c | 26 +++++++++++++++++
14
target/arm/tcg/translate-sve.c | 47 ++++++++++++++++++----------------
16
3 files changed, 90 insertions(+)
15
3 files changed, 31 insertions(+), 33 deletions(-)
17
16
18
diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h
17
diff --git a/target/arm/tcg/translate-a64.h b/target/arm/tcg/translate-a64.h
19
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
20
--- a/include/hw/arm/xlnx-versal.h
19
--- a/target/arm/tcg/translate-a64.h
21
+++ b/include/hw/arm/xlnx-versal.h
20
+++ b/target/arm/tcg/translate-a64.h
22
@@ -XXX,XX +XXX,XX @@
21
@@ -XXX,XX +XXX,XX @@ bool logic_imm_decode_wmask(uint64_t *result, unsigned int immn,
23
#include "hw/net/cadence_gem.h"
22
bool sve_access_check(DisasContext *s);
24
#include "hw/rtc/xlnx-zynqmp-rtc.h"
23
bool sme_enabled_check(DisasContext *s);
25
#include "qom/object.h"
24
bool sme_enabled_check_with_svcr(DisasContext *s, unsigned);
26
+#include "hw/usb/xlnx-usb-subsystem.h"
25
+uint32_t make_svemte_desc(DisasContext *s, unsigned vsz, uint32_t nregs,
27
26
+ uint32_t msz, bool is_write, uint32_t data);
28
#define TYPE_XLNX_VERSAL "xlnx-versal"
27
29
OBJECT_DECLARE_SIMPLE_TYPE(Versal, XLNX_VERSAL)
28
/* This function corresponds to CheckStreamingSVEEnabled. */
30
@@ -XXX,XX +XXX,XX @@ struct Versal {
29
static inline bool sme_sm_enabled_check(DisasContext *s)
31
PL011State uart[XLNX_VERSAL_NR_UARTS];
30
diff --git a/target/arm/tcg/translate-sme.c b/target/arm/tcg/translate-sme.c
32
CadenceGEMState gem[XLNX_VERSAL_NR_GEMS];
31
index XXXXXXX..XXXXXXX 100644
33
XlnxZDMA adma[XLNX_VERSAL_NR_ADMAS];
32
--- a/target/arm/tcg/translate-sme.c
34
+ VersalUsb2 usb;
33
+++ b/target/arm/tcg/translate-sme.c
35
} iou;
34
@@ -XXX,XX +XXX,XX @@ static bool trans_LDST1(DisasContext *s, arg_LDST1 *a)
36
} lpd;
35
37
36
TCGv_ptr t_za, t_pg;
38
@@ -XXX,XX +XXX,XX @@ struct Versal {
37
TCGv_i64 addr;
39
38
- int svl, desc = 0;
40
#define VERSAL_UART0_IRQ_0 18
39
+ uint32_t desc;
41
#define VERSAL_UART1_IRQ_0 19
40
bool be = s->be_data == MO_BE;
42
+#define VERSAL_USB0_IRQ_0 22
41
bool mte = s->mte_active[0];
43
#define VERSAL_GEM0_IRQ_0 56
42
44
#define VERSAL_GEM0_WAKE_IRQ_0 57
43
@@ -XXX,XX +XXX,XX @@ static bool trans_LDST1(DisasContext *s, arg_LDST1 *a)
45
#define VERSAL_GEM1_IRQ_0 58
44
tcg_gen_shli_i64(addr, cpu_reg(s, a->rm), a->esz);
46
@@ -XXX,XX +XXX,XX @@ struct Versal {
45
tcg_gen_add_i64(addr, addr, cpu_reg_sp(s, a->rn));
47
#define MM_OCM 0xfffc0000U
46
48
#define MM_OCM_SIZE 0x40000
47
- if (mte) {
49
48
- desc = FIELD_DP32(desc, MTEDESC, MIDX, get_mem_index(s));
50
+#define MM_USB2_CTRL_REGS 0xFF9D0000
49
- desc = FIELD_DP32(desc, MTEDESC, TBI, s->tbid);
51
+#define MM_USB2_CTRL_REGS_SIZE 0x10000
50
- desc = FIELD_DP32(desc, MTEDESC, TCMA, s->tcma);
51
- desc = FIELD_DP32(desc, MTEDESC, WRITE, a->st);
52
- desc = FIELD_DP32(desc, MTEDESC, SIZEM1, (1 << a->esz) - 1);
53
- desc <<= SVE_MTEDESC_SHIFT;
54
- } else {
55
+ if (!mte) {
56
addr = clean_data_tbi(s, addr);
57
}
58
- svl = streaming_vec_reg_size(s);
59
- desc = simd_desc(svl, svl, desc);
52
+
60
+
53
+#define MM_USB_0 0xFE200000
61
+ desc = make_svemte_desc(s, streaming_vec_reg_size(s), 1, a->esz, a->st, 0);
54
+#define MM_USB_0_SIZE 0x10000
62
63
fns[a->esz][be][a->v][mte][a->st](tcg_env, t_za, t_pg, addr,
64
tcg_constant_i32(desc));
65
diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c
66
index XXXXXXX..XXXXXXX 100644
67
--- a/target/arm/tcg/translate-sve.c
68
+++ b/target/arm/tcg/translate-sve.c
69
@@ -XXX,XX +XXX,XX @@ static const uint8_t dtype_esz[16] = {
70
3, 2, 1, 3
71
};
72
73
-static void do_mem_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr,
74
- int dtype, uint32_t mte_n, bool is_write,
75
- gen_helper_gvec_mem *fn)
76
+uint32_t make_svemte_desc(DisasContext *s, unsigned vsz, uint32_t nregs,
77
+ uint32_t msz, bool is_write, uint32_t data)
78
{
79
- unsigned vsz = vec_full_reg_size(s);
80
- TCGv_ptr t_pg;
81
uint32_t sizem1;
82
- int desc = 0;
83
+ uint32_t desc = 0;
84
85
- assert(mte_n >= 1 && mte_n <= 4);
86
- sizem1 = (mte_n << dtype_msz(dtype)) - 1;
87
+ /* Assert all of the data fits, with or without MTE enabled. */
88
+ assert(nregs >= 1 && nregs <= 4);
89
+ sizem1 = (nregs << msz) - 1;
90
assert(sizem1 <= R_MTEDESC_SIZEM1_MASK >> R_MTEDESC_SIZEM1_SHIFT);
91
+ assert(data < 1u << SVE_MTEDESC_SHIFT);
55
+
92
+
56
#define MM_TOP_DDR 0x0
93
if (s->mte_active[0]) {
57
#define MM_TOP_DDR_SIZE 0x80000000U
94
desc = FIELD_DP32(desc, MTEDESC, MIDX, get_mem_index(s));
58
#define MM_TOP_DDR_2 0x800000000ULL
95
desc = FIELD_DP32(desc, MTEDESC, TBI, s->tbid);
59
diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c
96
@@ -XXX,XX +XXX,XX @@ static void do_mem_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr,
60
index XXXXXXX..XXXXXXX 100644
97
desc = FIELD_DP32(desc, MTEDESC, WRITE, is_write);
61
--- a/hw/arm/xlnx-versal-virt.c
98
desc = FIELD_DP32(desc, MTEDESC, SIZEM1, sizem1);
62
+++ b/hw/arm/xlnx-versal-virt.c
99
desc <<= SVE_MTEDESC_SHIFT;
63
@@ -XXX,XX +XXX,XX @@ struct VersalVirt {
100
- } else {
64
uint32_t ethernet_phy[2];
101
+ }
65
uint32_t clk_125Mhz;
102
+ return simd_desc(vsz, vsz, desc | data);
66
uint32_t clk_25Mhz;
67
+ uint32_t usb;
68
+ uint32_t dwc;
69
} phandle;
70
struct arm_boot_info binfo;
71
72
@@ -XXX,XX +XXX,XX @@ static void fdt_create(VersalVirt *s)
73
s->phandle.clk_25Mhz = qemu_fdt_alloc_phandle(s->fdt);
74
s->phandle.clk_125Mhz = qemu_fdt_alloc_phandle(s->fdt);
75
76
+ s->phandle.usb = qemu_fdt_alloc_phandle(s->fdt);
77
+ s->phandle.dwc = qemu_fdt_alloc_phandle(s->fdt);
78
/* Create /chosen node for load_dtb. */
79
qemu_fdt_add_subnode(s->fdt, "/chosen");
80
81
@@ -XXX,XX +XXX,XX @@ static void fdt_add_timer_nodes(VersalVirt *s)
82
compat, sizeof(compat));
83
}
84
85
+static void fdt_add_usb_xhci_nodes(VersalVirt *s)
86
+{
87
+ const char clocknames[] = "bus_clk\0ref_clk";
88
+ const char irq_name[] = "dwc_usb3";
89
+ const char compatVersalDWC3[] = "xlnx,versal-dwc3";
90
+ const char compatDWC3[] = "snps,dwc3";
91
+ char *name = g_strdup_printf("/usb@%" PRIx32, MM_USB2_CTRL_REGS);
92
+
93
+ qemu_fdt_add_subnode(s->fdt, name);
94
+ qemu_fdt_setprop(s->fdt, name, "compatible",
95
+ compatVersalDWC3, sizeof(compatVersalDWC3));
96
+ qemu_fdt_setprop_sized_cells(s->fdt, name, "reg",
97
+ 2, MM_USB2_CTRL_REGS,
98
+ 2, MM_USB2_CTRL_REGS_SIZE);
99
+ qemu_fdt_setprop(s->fdt, name, "clock-names",
100
+ clocknames, sizeof(clocknames));
101
+ qemu_fdt_setprop_cells(s->fdt, name, "clocks",
102
+ s->phandle.clk_25Mhz, s->phandle.clk_125Mhz);
103
+ qemu_fdt_setprop(s->fdt, name, "ranges", NULL, 0);
104
+ qemu_fdt_setprop_cell(s->fdt, name, "#address-cells", 2);
105
+ qemu_fdt_setprop_cell(s->fdt, name, "#size-cells", 2);
106
+ qemu_fdt_setprop_cell(s->fdt, name, "phandle", s->phandle.usb);
107
+ g_free(name);
108
+
109
+ name = g_strdup_printf("/usb@%" PRIx32 "/dwc3@%" PRIx32,
110
+ MM_USB2_CTRL_REGS, MM_USB_0);
111
+ qemu_fdt_add_subnode(s->fdt, name);
112
+ qemu_fdt_setprop(s->fdt, name, "compatible",
113
+ compatDWC3, sizeof(compatDWC3));
114
+ qemu_fdt_setprop_sized_cells(s->fdt, name, "reg",
115
+ 2, MM_USB_0, 2, MM_USB_0_SIZE);
116
+ qemu_fdt_setprop(s->fdt, name, "interrupt-names",
117
+ irq_name, sizeof(irq_name));
118
+ qemu_fdt_setprop_cells(s->fdt, name, "interrupts",
119
+ GIC_FDT_IRQ_TYPE_SPI, VERSAL_USB0_IRQ_0,
120
+ GIC_FDT_IRQ_FLAGS_LEVEL_HI);
121
+ qemu_fdt_setprop_cell(s->fdt, name,
122
+ "snps,quirk-frame-length-adjustment", 0x20);
123
+ qemu_fdt_setprop_cells(s->fdt, name, "#stream-id-cells", 1);
124
+ qemu_fdt_setprop_string(s->fdt, name, "dr_mode", "host");
125
+ qemu_fdt_setprop_string(s->fdt, name, "phy-names", "usb3-phy");
126
+ qemu_fdt_setprop(s->fdt, name, "snps,dis_u2_susphy_quirk", NULL, 0);
127
+ qemu_fdt_setprop(s->fdt, name, "snps,dis_u3_susphy_quirk", NULL, 0);
128
+ qemu_fdt_setprop(s->fdt, name, "snps,refclk_fladj", NULL, 0);
129
+ qemu_fdt_setprop(s->fdt, name, "snps,mask_phy_reset", NULL, 0);
130
+ qemu_fdt_setprop_cell(s->fdt, name, "phandle", s->phandle.dwc);
131
+ qemu_fdt_setprop_string(s->fdt, name, "maximum-speed", "high-speed");
132
+ g_free(name);
133
+}
103
+}
134
+
104
+
135
static void fdt_add_uart_nodes(VersalVirt *s)
105
+static void do_mem_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr,
106
+ int dtype, uint32_t nregs, bool is_write,
107
+ gen_helper_gvec_mem *fn)
108
+{
109
+ TCGv_ptr t_pg;
110
+ uint32_t desc;
111
+
112
+ if (!s->mte_active[0]) {
113
addr = clean_data_tbi(s, addr);
114
}
115
116
@@ -XXX,XX +XXX,XX @@ static void do_mem_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr,
117
* registers as pointers, so encode the regno into the data field.
118
* For consistency, do this even for LD1.
119
*/
120
- desc = simd_desc(vsz, vsz, zt | desc);
121
+ desc = make_svemte_desc(s, vec_full_reg_size(s), nregs,
122
+ dtype_msz(dtype), is_write, zt);
123
t_pg = tcg_temp_new_ptr();
124
125
tcg_gen_addi_ptr(t_pg, tcg_env, pred_full_reg_offset(s, pg));
126
@@ -XXX,XX +XXX,XX @@ static void do_mem_zpz(DisasContext *s, int zt, int pg, int zm,
127
int scale, TCGv_i64 scalar, int msz, bool is_write,
128
gen_helper_gvec_mem_scatter *fn)
136
{
129
{
137
uint64_t addrs[] = { MM_UART1, MM_UART0 };
130
- unsigned vsz = vec_full_reg_size(s);
138
@@ -XXX,XX +XXX,XX @@ static void versal_virt_init(MachineState *machine)
131
TCGv_ptr t_zm = tcg_temp_new_ptr();
139
fdt_add_gic_nodes(s);
132
TCGv_ptr t_pg = tcg_temp_new_ptr();
140
fdt_add_timer_nodes(s);
133
TCGv_ptr t_zt = tcg_temp_new_ptr();
141
fdt_add_zdma_nodes(s);
134
- int desc = 0;
142
+ fdt_add_usb_xhci_nodes(s);
135
-
143
fdt_add_sd_nodes(s);
136
- if (s->mte_active[0]) {
144
fdt_add_rtc_node(s);
137
- desc = FIELD_DP32(desc, MTEDESC, MIDX, get_mem_index(s));
145
fdt_add_cpu_nodes(s, psci_conduit);
138
- desc = FIELD_DP32(desc, MTEDESC, TBI, s->tbid);
146
diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c
139
- desc = FIELD_DP32(desc, MTEDESC, TCMA, s->tcma);
147
index XXXXXXX..XXXXXXX 100644
140
- desc = FIELD_DP32(desc, MTEDESC, WRITE, is_write);
148
--- a/hw/arm/xlnx-versal.c
141
- desc = FIELD_DP32(desc, MTEDESC, SIZEM1, (1 << msz) - 1);
149
+++ b/hw/arm/xlnx-versal.c
142
- desc <<= SVE_MTEDESC_SHIFT;
150
@@ -XXX,XX +XXX,XX @@ static void versal_create_uarts(Versal *s, qemu_irq *pic)
143
- }
151
}
144
- desc = simd_desc(vsz, vsz, desc | scale);
145
+ uint32_t desc;
146
147
tcg_gen_addi_ptr(t_pg, tcg_env, pred_full_reg_offset(s, pg));
148
tcg_gen_addi_ptr(t_zm, tcg_env, vec_full_reg_offset(s, zm));
149
tcg_gen_addi_ptr(t_zt, tcg_env, vec_full_reg_offset(s, zt));
150
+
151
+ desc = make_svemte_desc(s, vec_full_reg_size(s), 1, msz, is_write, scale);
152
fn(tcg_env, t_zt, t_pg, t_zm, scalar, tcg_constant_i32(desc));
152
}
153
}
153
154
154
+static void versal_create_usbs(Versal *s, qemu_irq *pic)
155
+{
156
+ DeviceState *dev;
157
+ MemoryRegion *mr;
158
+
159
+ object_initialize_child(OBJECT(s), "usb2", &s->lpd.iou.usb,
160
+ TYPE_XILINX_VERSAL_USB2);
161
+ dev = DEVICE(&s->lpd.iou.usb);
162
+
163
+ object_property_set_link(OBJECT(dev), "dma", OBJECT(&s->mr_ps),
164
+ &error_abort);
165
+ qdev_prop_set_uint32(dev, "intrs", 1);
166
+ qdev_prop_set_uint32(dev, "slots", 2);
167
+
168
+ sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal);
169
+
170
+ mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
171
+ memory_region_add_subregion(&s->mr_ps, MM_USB_0, mr);
172
+
173
+ sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[VERSAL_USB0_IRQ_0]);
174
+
175
+ mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1);
176
+ memory_region_add_subregion(&s->mr_ps, MM_USB2_CTRL_REGS, mr);
177
+}
178
+
179
static void versal_create_gems(Versal *s, qemu_irq *pic)
180
{
181
int i;
182
@@ -XXX,XX +XXX,XX @@ static void versal_realize(DeviceState *dev, Error **errp)
183
versal_create_apu_cpus(s);
184
versal_create_apu_gic(s, pic);
185
versal_create_uarts(s, pic);
186
+ versal_create_usbs(s, pic);
187
versal_create_gems(s, pic);
188
versal_create_admas(s, pic);
189
versal_create_sds(s, pic);
190
--
155
--
191
2.20.1
156
2.34.1
192
193
diff view generated by jsdifflib
New patch
[PULL 06/35] target/arm: Handle mte in do_ldrq, do_ldro
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
These functions "use the standard load helpers", but
4
fail to clean_data_tbi or populate mtedesc.
5
6
Cc: qemu-stable@nongnu.org
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Tested-by: Gustavo Romero <gustavo.romero@linaro.org>
10
Message-id: 20240207025210.8837-6-richard.henderson@linaro.org
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
target/arm/tcg/translate-sve.c | 15 +++++++++++++--
14
1 file changed, 13 insertions(+), 2 deletions(-)
15
16
diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/tcg/translate-sve.c
19
+++ b/target/arm/tcg/translate-sve.c
20
@@ -XXX,XX +XXX,XX @@ static void do_ldrq(DisasContext *s, int zt, int pg, TCGv_i64 addr, int dtype)
21
unsigned vsz = vec_full_reg_size(s);
22
TCGv_ptr t_pg;
23
int poff;
24
+ uint32_t desc;
25
26
/* Load the first quadword using the normal predicated load helpers. */
27
+ if (!s->mte_active[0]) {
28
+ addr = clean_data_tbi(s, addr);
29
+ }
30
+
31
poff = pred_full_reg_offset(s, pg);
32
if (vsz > 16) {
33
/*
34
@@ -XXX,XX +XXX,XX @@ static void do_ldrq(DisasContext *s, int zt, int pg, TCGv_i64 addr, int dtype)
35
36
gen_helper_gvec_mem *fn
37
= ldr_fns[s->mte_active[0]][s->be_data == MO_BE][dtype][0];
38
- fn(tcg_env, t_pg, addr, tcg_constant_i32(simd_desc(16, 16, zt)));
39
+ desc = make_svemte_desc(s, 16, 1, dtype_msz(dtype), false, zt);
40
+ fn(tcg_env, t_pg, addr, tcg_constant_i32(desc));
41
42
/* Replicate that first quadword. */
43
if (vsz > 16) {
44
@@ -XXX,XX +XXX,XX @@ static void do_ldro(DisasContext *s, int zt, int pg, TCGv_i64 addr, int dtype)
45
unsigned vsz_r32;
46
TCGv_ptr t_pg;
47
int poff, doff;
48
+ uint32_t desc;
49
50
if (vsz < 32) {
51
/*
52
@@ -XXX,XX +XXX,XX @@ static void do_ldro(DisasContext *s, int zt, int pg, TCGv_i64 addr, int dtype)
53
}
54
55
/* Load the first octaword using the normal predicated load helpers. */
56
+ if (!s->mte_active[0]) {
57
+ addr = clean_data_tbi(s, addr);
58
+ }
59
60
poff = pred_full_reg_offset(s, pg);
61
if (vsz > 32) {
62
@@ -XXX,XX +XXX,XX @@ static void do_ldro(DisasContext *s, int zt, int pg, TCGv_i64 addr, int dtype)
63
64
gen_helper_gvec_mem *fn
65
= ldr_fns[s->mte_active[0]][s->be_data == MO_BE][dtype][0];
66
- fn(tcg_env, t_pg, addr, tcg_constant_i32(simd_desc(32, 32, zt)));
67
+ desc = make_svemte_desc(s, 32, 1, dtype_msz(dtype), false, zt);
68
+ fn(tcg_env, t_pg, addr, tcg_constant_i32(desc));
69
70
/*
71
* Replicate that first octaword.
72
--
73
2.34.1
diff view generated by jsdifflib
New patch
[PULL 07/35] target/arm: Fix SVE/SME gross MTE suppression checks
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
The TBI and TCMA bits are located within mtedesc, not desc.
4
5
Cc: qemu-stable@nongnu.org
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Tested-by: Gustavo Romero <gustavo.romero@linaro.org>
9
Message-id: 20240207025210.8837-7-richard.henderson@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
target/arm/tcg/sme_helper.c | 8 ++++----
13
target/arm/tcg/sve_helper.c | 12 ++++++------
14
2 files changed, 10 insertions(+), 10 deletions(-)
15
16
diff --git a/target/arm/tcg/sme_helper.c b/target/arm/tcg/sme_helper.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/tcg/sme_helper.c
19
+++ b/target/arm/tcg/sme_helper.c
20
@@ -XXX,XX +XXX,XX @@ void sme_ld1_mte(CPUARMState *env, void *za, uint64_t *vg,
21
desc = extract32(desc, 0, SIMD_DATA_SHIFT + SVE_MTEDESC_SHIFT);
22
23
/* Perform gross MTE suppression early. */
24
- if (!tbi_check(desc, bit55) ||
25
- tcma_check(desc, bit55, allocation_tag_from_addr(addr))) {
26
+ if (!tbi_check(mtedesc, bit55) ||
27
+ tcma_check(mtedesc, bit55, allocation_tag_from_addr(addr))) {
28
mtedesc = 0;
29
}
30
31
@@ -XXX,XX +XXX,XX @@ void sme_st1_mte(CPUARMState *env, void *za, uint64_t *vg, target_ulong addr,
32
desc = extract32(desc, 0, SIMD_DATA_SHIFT + SVE_MTEDESC_SHIFT);
33
34
/* Perform gross MTE suppression early. */
35
- if (!tbi_check(desc, bit55) ||
36
- tcma_check(desc, bit55, allocation_tag_from_addr(addr))) {
37
+ if (!tbi_check(mtedesc, bit55) ||
38
+ tcma_check(mtedesc, bit55, allocation_tag_from_addr(addr))) {
39
mtedesc = 0;
40
}
41
42
diff --git a/target/arm/tcg/sve_helper.c b/target/arm/tcg/sve_helper.c
43
index XXXXXXX..XXXXXXX 100644
44
--- a/target/arm/tcg/sve_helper.c
45
+++ b/target/arm/tcg/sve_helper.c
46
@@ -XXX,XX +XXX,XX @@ void sve_ldN_r_mte(CPUARMState *env, uint64_t *vg, target_ulong addr,
47
desc = extract32(desc, 0, SIMD_DATA_SHIFT + SVE_MTEDESC_SHIFT);
48
49
/* Perform gross MTE suppression early. */
50
- if (!tbi_check(desc, bit55) ||
51
- tcma_check(desc, bit55, allocation_tag_from_addr(addr))) {
52
+ if (!tbi_check(mtedesc, bit55) ||
53
+ tcma_check(mtedesc, bit55, allocation_tag_from_addr(addr))) {
54
mtedesc = 0;
55
}
56
57
@@ -XXX,XX +XXX,XX @@ void sve_ldnfff1_r_mte(CPUARMState *env, void *vg, target_ulong addr,
58
desc = extract32(desc, 0, SIMD_DATA_SHIFT + SVE_MTEDESC_SHIFT);
59
60
/* Perform gross MTE suppression early. */
61
- if (!tbi_check(desc, bit55) ||
62
- tcma_check(desc, bit55, allocation_tag_from_addr(addr))) {
63
+ if (!tbi_check(mtedesc, bit55) ||
64
+ tcma_check(mtedesc, bit55, allocation_tag_from_addr(addr))) {
65
mtedesc = 0;
66
}
67
68
@@ -XXX,XX +XXX,XX @@ void sve_stN_r_mte(CPUARMState *env, uint64_t *vg, target_ulong addr,
69
desc = extract32(desc, 0, SIMD_DATA_SHIFT + SVE_MTEDESC_SHIFT);
70
71
/* Perform gross MTE suppression early. */
72
- if (!tbi_check(desc, bit55) ||
73
- tcma_check(desc, bit55, allocation_tag_from_addr(addr))) {
74
+ if (!tbi_check(mtedesc, bit55) ||
75
+ tcma_check(mtedesc, bit55, allocation_tag_from_addr(addr))) {
76
mtedesc = 0;
77
}
78
79
--
80
2.34.1
diff view generated by jsdifflib
[PULL 07/20] target/nios2: Use deposit32() to update ipending register
[PULL 08/35] hw/pci-host/raven.c: Mark raven_io_ops as implementing unaligned accesses
1
In nios2_cpu_set_irq(), use deposit32() rather than raw shift-and-mask
1
The raven_io_ops MemoryRegionOps is the only one in the source tree
2
operations to set the appropriate bit in the ipending register.
2
which sets .valid.unaligned to indicate that it should support
3
unaligned accesses and which does not also set .impl.unaligned to
4
indicate that its read and write functions can do the unaligned
5
handling themselves. This is a problem, because at the moment the
6
core memory system does not implement the support for handling
7
unaligned accesses by doing a series of aligned accesses and
8
combining them (system/memory.c:access_with_adjusted_size() has a
9
TODO comment noting this).
3
10
11
Fortunately raven_io_read() and raven_io_write() will correctly deal
12
with the case of being passed an unaligned address, so we can fix the
13
missing unaligned access support by setting .impl.unaligned in the
14
MemoryRegionOps struct.
15
16
Fixes: 9a1839164c9c8f06 ("raven: Implement non-contiguous I/O region")
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
18
Tested-by: Cédric Le Goater <clg@redhat.com>
6
Message-id: 20201129174022.26530-4-peter.maydell@linaro.org
19
Reviewed-by: Cédric Le Goater <clg@redhat.com>
20
Message-id: 20240112134640.1775041-1-peter.maydell@linaro.org
7
---
21
---
8
target/nios2/cpu.c | 3 +--
22
hw/pci-host/raven.c | 1 +
9
1 file changed, 1 insertion(+), 2 deletions(-)
23
1 file changed, 1 insertion(+)
10
24
11
diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c
25
diff --git a/hw/pci-host/raven.c b/hw/pci-host/raven.c
12
index XXXXXXX..XXXXXXX 100644
26
index XXXXXXX..XXXXXXX 100644
13
--- a/target/nios2/cpu.c
27
--- a/hw/pci-host/raven.c
14
+++ b/target/nios2/cpu.c
28
+++ b/hw/pci-host/raven.c
15
@@ -XXX,XX +XXX,XX @@ static void nios2_cpu_set_irq(void *opaque, int irq, int level)
29
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps raven_io_ops = {
16
CPUNios2State *env = &cpu->env;
30
.write = raven_io_write,
17
CPUState *cs = CPU(cpu);
31
.endianness = DEVICE_LITTLE_ENDIAN,
18
32
.impl.max_access_size = 4,
19
- env->regs[CR_IPENDING] &= ~(1 << irq);
33
+ .impl.unaligned = true,
20
- env->regs[CR_IPENDING] |= !!level << irq;
34
.valid.unaligned = true,
21
+ env->regs[CR_IPENDING] = deposit32(env->regs[CR_IPENDING], irq, 1, !!level);
35
};
22
23
env->irq_pending = env->regs[CR_IPENDING] & env->regs[CR_IENABLE];
24
36
25
--
37
--
26
2.20.1
38
2.34.1
27
39
28
40
diff view generated by jsdifflib
[PULL 11/20] elf_ops.h: Be more verbose with ROM blob names
[PULL 09/35] hw/block/tc58128: Don't emit deprecation warning under qtest
1
Instead of making the ROM blob name something like:
1
Suppress the deprecation warning when we're running under qtest,
2
phdr #0: /home/petmay01/linaro/qemu-misc-tests/ldmia-fault.axf
2
to avoid "make check" including warning messages in its output.
3
make it a little more self-explanatory for people who don't know
4
ELF format details:
5
/home/petmay01/linaro/qemu-misc-tests/ldmia-fault.axf ELF program header segment 0
6
3
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
9
Message-id: 20201129203923.10622-5-peter.maydell@linaro.org
6
Message-id: 20240206154151.155620-1-peter.maydell@linaro.org
10
---
7
---
11
include/hw/elf_ops.h | 3 ++-
8
hw/block/tc58128.c | 4 +++-
12
1 file changed, 2 insertions(+), 1 deletion(-)
9
1 file changed, 3 insertions(+), 1 deletion(-)
13
10
14
diff --git a/include/hw/elf_ops.h b/include/hw/elf_ops.h
11
diff --git a/hw/block/tc58128.c b/hw/block/tc58128.c
15
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
16
--- a/include/hw/elf_ops.h
13
--- a/hw/block/tc58128.c
17
+++ b/include/hw/elf_ops.h
14
+++ b/hw/block/tc58128.c
18
@@ -XXX,XX +XXX,XX @@ static int glue(load_elf, SZ)(const char *name, int fd,
15
@@ -XXX,XX +XXX,XX @@ static sh7750_io_device tc58128 = {
19
if (mem_size != 0) {
16
20
if (load_rom) {
17
int tc58128_init(struct SH7750State *s, const char *zone1, const char *zone2)
21
g_autofree char *label =
18
{
22
- g_strdup_printf("phdr #%d: %s", i, name);
19
- warn_report_once("The TC58128 flash device is deprecated");
23
+ g_strdup_printf("%s ELF program header segment %d",
20
+ if (!qtest_enabled()) {
24
+ name, i);
21
+ warn_report_once("The TC58128 flash device is deprecated");
25
22
+ }
26
/*
23
init_dev(&tc58128_devs[0], zone1);
27
* rom_add_elf_program() takes its own reference to
24
init_dev(&tc58128_devs[1], zone2);
25
return sh7750_register_io_device(s, &tc58128);
28
--
26
--
29
2.20.1
27
2.34.1
30
28
31
29
diff view generated by jsdifflib
New patch
[PULL 10/35] tests/qtest/meson.build: Don't include qtests_npcm7xx in qtests_aarch64
1
We deliberately don't include qtests_npcm7xx in qtests_aarch64,
2
because we already get the coverage of those tests via qtests_arm,
3
and we don't want to use extra CI minutes testing them twice.
1
4
5
In commit 327b680877b79c4b we added it to qtests_aarch64; revert
6
that change.
7
8
Fixes: 327b680877b79c4b ("tests/qtest: Creating qtest for GMAC Module")
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
11
Message-id: 20240206163043.315535-1-peter.maydell@linaro.org
12
---
13
tests/qtest/meson.build | 1 -
14
1 file changed, 1 deletion(-)
15
16
diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
17
index XXXXXXX..XXXXXXX 100644
18
--- a/tests/qtest/meson.build
19
+++ b/tests/qtest/meson.build
20
@@ -XXX,XX +XXX,XX @@ qtests_aarch64 = \
21
(config_all_devices.has_key('CONFIG_RASPI') ? ['bcm2835-dma-test'] : []) + \
22
(config_all_accel.has_key('CONFIG_TCG') and \
23
config_all_devices.has_key('CONFIG_TPM_TIS_I2C') ? ['tpm-tis-i2c-test'] : []) + \
24
- (config_all_devices.has_key('CONFIG_NPCM7XX') ? qtests_npcm7xx : []) + \
25
['arm-cpu-features',
26
'numa-test',
27
'boot-serial-test',
28
--
29
2.34.1
30
31
diff view generated by jsdifflib
New patch
[PULL 11/35] tests/qtest/bios-tables-test: Allow changes to virt GTDT
1
Allow changes to the virt GTDT -- we are going to add the IRQ
2
entry for a new timer to it.
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
6
Message-id: 20240122143537.233498-2-peter.maydell@linaro.org
7
---
8
tests/qtest/bios-tables-test-allowed-diff.h | 2 ++
9
1 file changed, 2 insertions(+)
10
11
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h
12
index XXXXXXX..XXXXXXX 100644
13
--- a/tests/qtest/bios-tables-test-allowed-diff.h
14
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
15
@@ -1 +1,3 @@
16
/* List of comma-separated changed AML files to ignore */
17
+"tests/data/acpi/virt/FACP",
18
+"tests/data/acpi/virt/GTDT",
19
--
20
2.34.1
diff view generated by jsdifflib
New patch
[PULL 12/35] hw/arm/virt: Wire up non-secure EL2 virtual timer IRQ
1
1
Armv8.1+ CPUs have the Virtual Host Extension (VHE) which adds a
2
non-secure EL2 virtual timer. We implemented the timer itself in the
3
CPU model, but never wired up its IRQ line to the GIC.
4
5
Wire up the IRQ line (this is always safe whether the CPU has the
6
interrupt or not, since it always creates the outbound IRQ line).
7
Report it to the guest via dtb and ACPI if the CPU has the feature.
8
9
The DTB binding is documented in the kernel's
10
Documentation/devicetree/bindings/timer/arm\,arch_timer.yaml
11
and the ACPI table entries are documented in the ACPI specification
12
version 6.3 or later.
13
14
Because the IRQ line ACPI binding is new in 6.3, we need to bump the
15
FADT table rev to show that we might be using 6.3 features.
16
17
Note that exposing this IRQ in the DTB will trigger a bug in EDK2
18
versions prior to edk2-stable202311, for users who use the virt board
19
with 'virtualization=on' to enable EL2 emulation and are booting an
20
EDK2 guest BIOS, if that EDK2 has assertions enabled. The effect is
21
that EDK2 will assert on bootup:
22
23
ASSERT [ArmTimerDxe] /home/kraxel/projects/qemu/roms/edk2/ArmVirtPkg/Library/ArmVirtTimerFdtClientLib/ArmVirtTimerFdtClientLib.c(72): PropSize == 36 || PropSize == 48
24
25
If you see that assertion you should do one of:
26
* update your EDK2 binaries to edk2-stable202311 or newer
27
* use the 'virt-8.2' versioned machine type
28
* not use 'virtualization=on'
29
30
(The versions shipped with QEMU itself have the fix.)
31
32
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
33
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
34
Message-id: 20240122143537.233498-3-peter.maydell@linaro.org
35
---
36
include/hw/arm/virt.h | 2 ++
37
hw/arm/virt-acpi-build.c | 20 ++++++++++----
38
hw/arm/virt.c | 60 ++++++++++++++++++++++++++++++++++------
39
3 files changed, 67 insertions(+), 15 deletions(-)
40
41
diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
42
index XXXXXXX..XXXXXXX 100644
43
--- a/include/hw/arm/virt.h
44
+++ b/include/hw/arm/virt.h
45
@@ -XXX,XX +XXX,XX @@ struct VirtMachineClass {
46
/* Machines < 6.2 have no support for describing cpu topology to guest */
47
bool no_cpu_topology;
48
bool no_tcg_lpa2;
49
+ bool no_ns_el2_virt_timer_irq;
50
};
51
52
struct VirtMachineState {
53
@@ -XXX,XX +XXX,XX @@ struct VirtMachineState {
54
PCIBus *bus;
55
char *oem_id;
56
char *oem_table_id;
57
+ bool ns_el2_virt_timer_irq;
58
};
59
60
#define VIRT_ECAM_ID(high) (high ? VIRT_HIGH_PCIE_ECAM : VIRT_PCIE_ECAM)
61
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
62
index XXXXXXX..XXXXXXX 100644
63
--- a/hw/arm/virt-acpi-build.c
64
+++ b/hw/arm/virt-acpi-build.c
65
@@ -XXX,XX +XXX,XX @@ build_srat(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
66
}
67
68
/*
69
- * ACPI spec, Revision 5.1
70
- * 5.2.24 Generic Timer Description Table (GTDT)
71
+ * ACPI spec, Revision 6.5
72
+ * 5.2.25 Generic Timer Description Table (GTDT)
73
*/
74
static void
75
build_gtdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
76
@@ -XXX,XX +XXX,XX @@ build_gtdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
77
uint32_t irqflags = vmc->claim_edge_triggered_timers ?
78
1 : /* Interrupt is Edge triggered */
79
0; /* Interrupt is Level triggered */
80
- AcpiTable table = { .sig = "GTDT", .rev = 2, .oem_id = vms->oem_id,
81
+ AcpiTable table = { .sig = "GTDT", .rev = 3, .oem_id = vms->oem_id,
82
.oem_table_id = vms->oem_table_id };
83
84
acpi_table_begin(&table, table_data);
85
@@ -XXX,XX +XXX,XX @@ build_gtdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
86
build_append_int_noprefix(table_data, 0, 4);
87
/* Platform Timer Offset */
88
build_append_int_noprefix(table_data, 0, 4);
89
-
90
+ if (vms->ns_el2_virt_timer_irq) {
91
+ /* Virtual EL2 Timer GSIV */
92
+ build_append_int_noprefix(table_data, ARCH_TIMER_NS_EL2_VIRT_IRQ, 4);
93
+ /* Virtual EL2 Timer Flags */
94
+ build_append_int_noprefix(table_data, irqflags, 4);
95
+ } else {
96
+ build_append_int_noprefix(table_data, 0, 4);
97
+ build_append_int_noprefix(table_data, 0, 4);
98
+ }
99
acpi_table_end(linker, &table);
100
}
101
102
@@ -XXX,XX +XXX,XX @@ build_madt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
103
static void build_fadt_rev6(GArray *table_data, BIOSLinker *linker,
104
VirtMachineState *vms, unsigned dsdt_tbl_offset)
105
{
106
- /* ACPI v6.0 */
107
+ /* ACPI v6.3 */
108
AcpiFadtData fadt = {
109
.rev = 6,
110
- .minor_ver = 0,
111
+ .minor_ver = 3,
112
.flags = 1 << ACPI_FADT_F_HW_REDUCED_ACPI,
113
.xdsdt_tbl_offset = &dsdt_tbl_offset,
114
};
115
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
116
index XXXXXXX..XXXXXXX 100644
117
--- a/hw/arm/virt.c
118
+++ b/hw/arm/virt.c
119
@@ -XXX,XX +XXX,XX @@ static void create_randomness(MachineState *ms, const char *node)
120
qemu_fdt_setprop(ms->fdt, node, "rng-seed", seed.rng, sizeof(seed.rng));
121
}
122
123
+/*
124
+ * The CPU object always exposes the NS EL2 virt timer IRQ line,
125
+ * but we don't want to advertise it to the guest in the dtb or ACPI
126
+ * table unless it's really going to do something.
127
+ */
128
+static bool ns_el2_virt_timer_present(void)
129
+{
130
+ ARMCPU *cpu = ARM_CPU(qemu_get_cpu(0));
131
+ CPUARMState *env = &cpu->env;
132
+
133
+ return arm_feature(env, ARM_FEATURE_AARCH64) &&
134
+ arm_feature(env, ARM_FEATURE_EL2) && cpu_isar_feature(aa64_vh, cpu);
135
+}
136
+
137
static void create_fdt(VirtMachineState *vms)
138
{
139
MachineState *ms = MACHINE(vms);
140
@@ -XXX,XX +XXX,XX @@ static void fdt_add_timer_nodes(const VirtMachineState *vms)
141
"arm,armv7-timer");
142
}
143
qemu_fdt_setprop(ms->fdt, "/timer", "always-on", NULL, 0);
144
- qemu_fdt_setprop_cells(ms->fdt, "/timer", "interrupts",
145
- GIC_FDT_IRQ_TYPE_PPI,
146
- INTID_TO_PPI(ARCH_TIMER_S_EL1_IRQ), irqflags,
147
- GIC_FDT_IRQ_TYPE_PPI,
148
- INTID_TO_PPI(ARCH_TIMER_NS_EL1_IRQ), irqflags,
149
- GIC_FDT_IRQ_TYPE_PPI,
150
- INTID_TO_PPI(ARCH_TIMER_VIRT_IRQ), irqflags,
151
- GIC_FDT_IRQ_TYPE_PPI,
152
- INTID_TO_PPI(ARCH_TIMER_NS_EL2_IRQ), irqflags);
153
+ if (vms->ns_el2_virt_timer_irq) {
154
+ qemu_fdt_setprop_cells(ms->fdt, "/timer", "interrupts",
155
+ GIC_FDT_IRQ_TYPE_PPI,
156
+ INTID_TO_PPI(ARCH_TIMER_S_EL1_IRQ), irqflags,
157
+ GIC_FDT_IRQ_TYPE_PPI,
158
+ INTID_TO_PPI(ARCH_TIMER_NS_EL1_IRQ), irqflags,
159
+ GIC_FDT_IRQ_TYPE_PPI,
160
+ INTID_TO_PPI(ARCH_TIMER_VIRT_IRQ), irqflags,
161
+ GIC_FDT_IRQ_TYPE_PPI,
162
+ INTID_TO_PPI(ARCH_TIMER_NS_EL2_IRQ), irqflags,
163
+ GIC_FDT_IRQ_TYPE_PPI,
164
+ INTID_TO_PPI(ARCH_TIMER_NS_EL2_VIRT_IRQ), irqflags);
165
+ } else {
166
+ qemu_fdt_setprop_cells(ms->fdt, "/timer", "interrupts",
167
+ GIC_FDT_IRQ_TYPE_PPI,
168
+ INTID_TO_PPI(ARCH_TIMER_S_EL1_IRQ), irqflags,
169
+ GIC_FDT_IRQ_TYPE_PPI,
170
+ INTID_TO_PPI(ARCH_TIMER_NS_EL1_IRQ), irqflags,
171
+ GIC_FDT_IRQ_TYPE_PPI,
172
+ INTID_TO_PPI(ARCH_TIMER_VIRT_IRQ), irqflags,
173
+ GIC_FDT_IRQ_TYPE_PPI,
174
+ INTID_TO_PPI(ARCH_TIMER_NS_EL2_IRQ), irqflags);
175
+ }
176
}
177
178
static void fdt_add_cpu_nodes(const VirtMachineState *vms)
179
@@ -XXX,XX +XXX,XX @@ static void create_gic(VirtMachineState *vms, MemoryRegion *mem)
180
[GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ,
181
[GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ,
182
[GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ,
183
+ [GTIMER_HYPVIRT] = ARCH_TIMER_NS_EL2_VIRT_IRQ,
184
};
185
186
for (unsigned irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) {
187
@@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine)
188
qdev_realize(DEVICE(cpuobj), NULL, &error_fatal);
189
object_unref(cpuobj);
190
}
191
+
192
+ /* Now we've created the CPUs we can see if they have the hypvirt timer */
193
+ vms->ns_el2_virt_timer_irq = ns_el2_virt_timer_present() &&
194
+ !vmc->no_ns_el2_virt_timer_irq;
195
+
196
fdt_add_timer_nodes(vms);
197
fdt_add_cpu_nodes(vms);
198
199
@@ -XXX,XX +XXX,XX @@ DEFINE_VIRT_MACHINE_AS_LATEST(9, 0)
200
201
static void virt_machine_8_2_options(MachineClass *mc)
202
{
203
+ VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
204
+
205
virt_machine_9_0_options(mc);
206
compat_props_add(mc->compat_props, hw_compat_8_2, hw_compat_8_2_len);
207
+ /*
208
+ * Don't expose NS_EL2_VIRT timer IRQ in DTB on ACPI on 8.2 and
209
+ * earlier machines. (Exposing it tickles a bug in older EDK2
210
+ * guest BIOS binaries.)
211
+ */
212
+ vmc->no_ns_el2_virt_timer_irq = true;
213
}
214
DEFINE_VIRT_MACHINE(8, 2)
215
216
--
217
2.34.1
diff view generated by jsdifflib
New patch
[PULL 13/35] tests/qtest/bios-tables-tests: Update virt golden reference
1
1
Update the virt golden reference files to say that the FACP is ACPI
2
v6.3, and the GTDT table is a revision 3 table with space for the
3
virtual EL2 timer.
4
5
Diffs from iasl:
6
7
@@ -XXX,XX +XXX,XX @@
8
/*
9
* Intel ACPI Component Architecture
10
* AML/ASL+ Disassembler version 20200925 (64-bit version)
11
* Copyright (c) 2000 - 2020 Intel Corporation
12
*
13
- * Disassembly of tests/data/acpi/virt/FACP, Mon Jan 22 13:48:40 2024
14
+ * Disassembly of /tmp/aml-W8RZH2, Mon Jan 22 13:48:40 2024
15
*
16
* ACPI Data Table [FACP]
17
*
18
* Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
19
*/
20
21
[000h 0000 4] Signature : "FACP" [Fixed ACPI Description Table (FADT)]
22
[004h 0004 4] Table Length : 00000114
23
[008h 0008 1] Revision : 06
24
-[009h 0009 1] Checksum : 15
25
+[009h 0009 1] Checksum : 12
26
[00Ah 0010 6] Oem ID : "BOCHS "
27
[010h 0016 8] Oem Table ID : "BXPC "
28
[018h 0024 4] Oem Revision : 00000001
29
[01Ch 0028 4] Asl Compiler ID : "BXPC"
30
[020h 0032 4] Asl Compiler Revision : 00000001
31
32
[024h 0036 4] FACS Address : 00000000
33
[028h 0040 4] DSDT Address : 00000000
34
[02Ch 0044 1] Model : 00
35
[02Dh 0045 1] PM Profile : 00 [Unspecified]
36
[02Eh 0046 2] SCI Interrupt : 0000
37
[030h 0048 4] SMI Command Port : 00000000
38
[034h 0052 1] ACPI Enable Value : 00
39
[035h 0053 1] ACPI Disable Value : 00
40
[036h 0054 1] S4BIOS Command : 00
41
[037h 0055 1] P-State Control : 00
42
@@ -XXX,XX +XXX,XX @@
43
Use APIC Physical Destination Mode (V4) : 0
44
Hardware Reduced (V5) : 1
45
Low Power S0 Idle (V5) : 0
46
47
[074h 0116 12] Reset Register : [Generic Address Structure]
48
[074h 0116 1] Space ID : 00 [SystemMemory]
49
[075h 0117 1] Bit Width : 00
50
[076h 0118 1] Bit Offset : 00
51
[077h 0119 1] Encoded Access Width : 00 [Undefined/Legacy]
52
[078h 0120 8] Address : 0000000000000000
53
54
[080h 0128 1] Value to cause reset : 00
55
[081h 0129 2] ARM Flags (decoded below) : 0003
56
PSCI Compliant : 1
57
Must use HVC for PSCI : 1
58
59
-[083h 0131 1] FADT Minor Revision : 00
60
+[083h 0131 1] FADT Minor Revision : 03
61
[084h 0132 8] FACS Address : 0000000000000000
62
[08Ch 0140 8] DSDT Address : 0000000000000000
63
[094h 0148 12] PM1A Event Block : [Generic Address Structure]
64
[094h 0148 1] Space ID : 00 [SystemMemory]
65
[095h 0149 1] Bit Width : 00
66
[096h 0150 1] Bit Offset : 00
67
[097h 0151 1] Encoded Access Width : 00 [Undefined/Legacy]
68
[098h 0152 8] Address : 0000000000000000
69
70
[0A0h 0160 12] PM1B Event Block : [Generic Address Structure]
71
[0A0h 0160 1] Space ID : 00 [SystemMemory]
72
[0A1h 0161 1] Bit Width : 00
73
[0A2h 0162 1] Bit Offset : 00
74
[0A3h 0163 1] Encoded Access Width : 00 [Undefined/Legacy]
75
[0A4h 0164 8] Address : 0000000000000000
76
77
@@ -XXX,XX +XXX,XX @@
78
[0F5h 0245 1] Bit Width : 00
79
[0F6h 0246 1] Bit Offset : 00
80
[0F7h 0247 1] Encoded Access Width : 00 [Undefined/Legacy]
81
[0F8h 0248 8] Address : 0000000000000000
82
83
[100h 0256 12] Sleep Status Register : [Generic Address Structure]
84
[100h 0256 1] Space ID : 00 [SystemMemory]
85
[101h 0257 1] Bit Width : 00
86
[102h 0258 1] Bit Offset : 00
87
[103h 0259 1] Encoded Access Width : 00 [Undefined/Legacy]
88
[104h 0260 8] Address : 0000000000000000
89
90
[10Ch 0268 8] Hypervisor ID : 00000000554D4551
91
92
Raw Table Data: Length 276 (0x114)
93
94
- 0000: 46 41 43 50 14 01 00 00 06 15 42 4F 43 48 53 20 // FACP......BOCHS
95
+ 0000: 46 41 43 50 14 01 00 00 06 12 42 4F 43 48 53 20 // FACP......BOCHS
96
0010: 42 58 50 43 20 20 20 20 01 00 00 00 42 58 50 43 // BXPC ....BXPC
97
0020: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
98
0030: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
99
0040: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
100
0050: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
101
0060: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
102
0070: 00 00 10 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
103
- 0080: 00 03 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
104
+ 0080: 00 03 00 03 00 00 00 00 00 00 00 00 00 00 00 00 // ................
105
0090: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
106
00A0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
107
00B0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
108
00C0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
109
00D0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
110
00E0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
111
00F0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
112
0100: 00 00 00 00 00 00 00 00 00 00 00 00 51 45 4D 55 // ............QEMU
113
0110: 00 00 00 00 // ....
114
115
@@ -XXX,XX +XXX,XX @@
116
/*
117
* Intel ACPI Component Architecture
118
* AML/ASL+ Disassembler version 20200925 (64-bit version)
119
* Copyright (c) 2000 - 2020 Intel Corporation
120
*
121
- * Disassembly of tests/data/acpi/virt/GTDT, Mon Jan 22 13:48:40 2024
122
+ * Disassembly of /tmp/aml-XDSZH2, Mon Jan 22 13:48:40 2024
123
*
124
* ACPI Data Table [GTDT]
125
*
126
* Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
127
*/
128
129
[000h 0000 4] Signature : "GTDT" [Generic Timer Description Table]
130
-[004h 0004 4] Table Length : 00000060
131
-[008h 0008 1] Revision : 02
132
-[009h 0009 1] Checksum : 9C
133
+[004h 0004 4] Table Length : 00000068
134
+[008h 0008 1] Revision : 03
135
+[009h 0009 1] Checksum : 93
136
[00Ah 0010 6] Oem ID : "BOCHS "
137
[010h 0016 8] Oem Table ID : "BXPC "
138
[018h 0024 4] Oem Revision : 00000001
139
[01Ch 0028 4] Asl Compiler ID : "BXPC"
140
[020h 0032 4] Asl Compiler Revision : 00000001
141
142
[024h 0036 8] Counter Block Address : FFFFFFFFFFFFFFFF
143
[02Ch 0044 4] Reserved : 00000000
144
145
[030h 0048 4] Secure EL1 Interrupt : 0000001D
146
[034h 0052 4] EL1 Flags (decoded below) : 00000000
147
Trigger Mode : 0
148
Polarity : 0
149
Always On : 0
150
151
[038h 0056 4] Non-Secure EL1 Interrupt : 0000001E
152
@@ -XXX,XX +XXX,XX @@
153
154
[040h 0064 4] Virtual Timer Interrupt : 0000001B
155
[044h 0068 4] VT Flags (decoded below) : 00000000
156
Trigger Mode : 0
157
Polarity : 0
158
Always On : 0
159
160
[048h 0072 4] Non-Secure EL2 Interrupt : 0000001A
161
[04Ch 0076 4] NEL2 Flags (decoded below) : 00000000
162
Trigger Mode : 0
163
Polarity : 0
164
Always On : 0
165
[050h 0080 8] Counter Read Block Address : FFFFFFFFFFFFFFFF
166
167
[058h 0088 4] Platform Timer Count : 00000000
168
[05Ch 0092 4] Platform Timer Offset : 00000000
169
+[060h 0096 4] Virtual EL2 Timer GSIV : 00000000
170
+[064h 0100 4] Virtual EL2 Timer Flags : 00000000
171
172
-Raw Table Data: Length 96 (0x60)
173
+Raw Table Data: Length 104 (0x68)
174
175
- 0000: 47 54 44 54 60 00 00 00 02 9C 42 4F 43 48 53 20 // GTDT`.....BOCHS
176
+ 0000: 47 54 44 54 68 00 00 00 03 93 42 4F 43 48 53 20 // GTDTh.....BOCHS
177
0010: 42 58 50 43 20 20 20 20 01 00 00 00 42 58 50 43 // BXPC ....BXPC
178
0020: 01 00 00 00 FF FF FF FF FF FF FF FF 00 00 00 00 // ................
179
0030: 1D 00 00 00 00 00 00 00 1E 00 00 00 04 00 00 00 // ................
180
0040: 1B 00 00 00 00 00 00 00 1A 00 00 00 00 00 00 00 // ................
181
0050: FF FF FF FF FF FF FF FF 00 00 00 00 00 00 00 00 // ................
182
+ 0060: 00 00 00 00 00 00 00 00 // ........
183
184
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
185
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
186
Message-id: 20240122143537.233498-4-peter.maydell@linaro.org
187
---
188
tests/qtest/bios-tables-test-allowed-diff.h | 2 --
189
tests/data/acpi/virt/FACP | Bin 276 -> 276 bytes
190
tests/data/acpi/virt/GTDT | Bin 96 -> 104 bytes
191
3 files changed, 2 deletions(-)
192
193
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h
194
index XXXXXXX..XXXXXXX 100644
195
--- a/tests/qtest/bios-tables-test-allowed-diff.h
196
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
197
@@ -1,3 +1 @@
198
/* List of comma-separated changed AML files to ignore */
199
-"tests/data/acpi/virt/FACP",
200
-"tests/data/acpi/virt/GTDT",
201
diff --git a/tests/data/acpi/virt/FACP b/tests/data/acpi/virt/FACP
202
index XXXXXXX..XXXXXXX 100644
203
GIT binary patch
204
delta 25
205
gcmbQjG=+)F&CxkPgpq-PO=u!l<;2F$$vli407<0<)c^nh
206
207
delta 28
208
kcmbQjG=+)F&CxkPgpq-PO>`nx<-|!<6Akz$^DuG%0AAS!ssI20
209
210
diff --git a/tests/data/acpi/virt/GTDT b/tests/data/acpi/virt/GTDT
211
index XXXXXXX..XXXXXXX 100644
212
GIT binary patch
213
delta 25
214
bcmYeu;BpUf3CUn!U|^m+kt>V?$N&QXMtB4L
215
216
delta 16
217
Xcmc~u;BpUf2}xjJU|^avkt+-UB60)u
218
219
--
220
2.34.1
diff view generated by jsdifflib
New patch
[PULL 14/35] hw/arm/npcm7xx: Call qemu_configure_nic_device() for GMAC modules
1
The patchset adding the GMAC ethernet to this SoC crossed in the
2
mail with the patchset cleaning up the NIC handling. When we
3
create the GMAC modules we must call qemu_configure_nic_device()
4
so that the user has the opportunity to use the -nic commandline
5
option to create a network backend and connect it to the GMACs.
1
6
7
Add the missing call.
8
9
Fixes: 21e5326a7c ("hw/arm: Add GMAC devices to NPCM7XX SoC")
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: David Woodhouse <dwmw@amazon.co.uk>
12
Message-id: 20240206171231.396392-2-peter.maydell@linaro.org
13
---
14
hw/arm/npcm7xx.c | 1 +
15
1 file changed, 1 insertion(+)
16
17
diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c
18
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/arm/npcm7xx.c
20
+++ b/hw/arm/npcm7xx.c
21
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_realize(DeviceState *dev, Error **errp)
22
for (i = 0; i < ARRAY_SIZE(s->gmac); i++) {
23
SysBusDevice *sbd = SYS_BUS_DEVICE(&s->gmac[i]);
24
25
+ qemu_configure_nic_device(DEVICE(sbd), false, NULL);
26
/*
27
* The device exists regardless of whether it's connected to a QEMU
28
* netdev backend. So always instantiate it even if there is no
29
--
30
2.34.1
diff view generated by jsdifflib
New patch
[PULL 15/35] tests/qtest/npcm7xx_emc-test: Connect all NICs to a backend
1
Currently QEMU will warn if there is a NIC on the board that
2
is not connected to a backend. By default the '-nic user' will
3
get used for all NICs, but if you manually connect a specific
4
NIC to a specific backend, then the other NICs on the board
5
have no backend and will be warned about:
1
6
7
qemu-system-arm: warning: nic npcm7xx-emc.1 has no peer
8
qemu-system-arm: warning: nic npcm-gmac.0 has no peer
9
qemu-system-arm: warning: nic npcm-gmac.1 has no peer
10
11
So suppress those warnings by manually connecting every NIC
12
on the board to some backend.
13
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
Reviewed-by: David Woodhouse <dwmw@amazon.co.uk>
16
Reviewed-by: Thomas Huth <thuth@redhat.com>
17
Message-id: 20240206171231.396392-3-peter.maydell@linaro.org
18
---
19
tests/qtest/npcm7xx_emc-test.c | 5 ++++-
20
1 file changed, 4 insertions(+), 1 deletion(-)
21
22
diff --git a/tests/qtest/npcm7xx_emc-test.c b/tests/qtest/npcm7xx_emc-test.c
23
index XXXXXXX..XXXXXXX 100644
24
--- a/tests/qtest/npcm7xx_emc-test.c
25
+++ b/tests/qtest/npcm7xx_emc-test.c
26
@@ -XXX,XX +XXX,XX @@ static int *packet_test_init(int module_num, GString *cmd_line)
27
* KISS and use -nic. The driver accepts 'emc0' and 'emc1' as aliases
28
* in the 'model' field to specify the device to match.
29
*/
30
- g_string_append_printf(cmd_line, " -nic socket,fd=%d,model=emc%d ",
31
+ g_string_append_printf(cmd_line, " -nic socket,fd=%d,model=emc%d "
32
+ "-nic user,model=npcm7xx-emc "
33
+ "-nic user,model=npcm-gmac "
34
+ "-nic user,model=npcm-gmac",
35
test_sockets[1], module_num);
36
37
g_test_queue_destroy(packet_test_clear, test_sockets);
38
--
39
2.34.1
diff view generated by jsdifflib
[PULL 16/20] hw/misc/zynq_slcr: Avoid #DIV/0! error
[PULL 16/35] target/arm: Don't get MDCR_EL2 in pmu_counter_enabled() before checking ARM_FEATURE_PMU
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
It doesn't make sense to read the value of MDCR_EL2 on a non-A-profile
2
CPU, and in fact if you try to do it we will assert:
2
3
3
Malicious user can set the feedback divisor for the PLLs
4
#6 0x00007ffff4b95e96 in __GI___assert_fail
4
to zero, triggering a floating-point exception (SIGFPE).
5
(assertion=0x5555565a8c70 "!arm_feature(env, ARM_FEATURE_M)", file=0x5555565a6e5c "../../target/arm/helper.c", line=12600, function=0x5555565a9560 <__PRETTY_FUNCTION__.0> "arm_security_space_below_el3") at ./assert/assert.c:101
6
#7 0x0000555555ebf412 in arm_security_space_below_el3 (env=0x555557bc8190) at ../../target/arm/helper.c:12600
7
#8 0x0000555555ea6f89 in arm_is_el2_enabled (env=0x555557bc8190) at ../../target/arm/cpu.h:2595
8
#9 0x0000555555ea942f in arm_mdcr_el2_eff (env=0x555557bc8190) at ../../target/arm/internals.h:1512
5
9
6
As the datasheet [*] is not clear how hardware behaves
10
We might call pmu_counter_enabled() on an M-profile CPU (for example
7
when these bits are zeroes, use the maximum divisor
11
from the migration pre/post hooks in machine.c); this should always
8
possible (128) to avoid the software FPE.
12
return false because these CPUs don't set ARM_FEATURE_PMU.
9
13
10
[*] Zynq-7000 TRM, UG585 (v1.12.2)
14
Avoid the assertion by not calling arm_mdcr_el2_eff() before we
11
B.28 System Level Control Registers (slcr)
15
have done the early return for "PMU not present".
12
-> "Register (slcr) ARM_PLL_CTRL"
13
25.10.4 PLLs
14
-> "Software-Controlled PLL Update"
15
16
16
Fixes: 38867cb7ec9 ("hw/misc/zynq_slcr: add clock generation for uarts")
17
This fixes an assertion failure if you try to do a loadvm or
17
Reported-by: Gaoning Pan <pgn@zju.edu.cn>
18
savevm for an M-profile board.
18
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
19
19
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
20
Cc: qemu-stable@nongnu.org
20
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
21
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2155
21
Reviewed-by: Damien Hedde <damien.hedde@greensocs.com>
22
Message-id: 20201210141610.884600-1-f4bug@amsat.org
23
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
22
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
23
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
24
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
25
Message-id: 20240208153346.970021-1-peter.maydell@linaro.org
24
---
26
---
25
hw/misc/zynq_slcr.c | 5 +++++
27
target/arm/helper.c | 12 ++++++++++--
26
1 file changed, 5 insertions(+)
28
1 file changed, 10 insertions(+), 2 deletions(-)
27
29
28
diff --git a/hw/misc/zynq_slcr.c b/hw/misc/zynq_slcr.c
30
diff --git a/target/arm/helper.c b/target/arm/helper.c
29
index XXXXXXX..XXXXXXX 100644
31
index XXXXXXX..XXXXXXX 100644
30
--- a/hw/misc/zynq_slcr.c
32
--- a/target/arm/helper.c
31
+++ b/hw/misc/zynq_slcr.c
33
+++ b/target/arm/helper.c
32
@@ -XXX,XX +XXX,XX @@ static uint64_t zynq_slcr_compute_pll(uint64_t input, uint32_t ctrl_reg)
34
@@ -XXX,XX +XXX,XX @@ static bool pmu_counter_enabled(CPUARMState *env, uint8_t counter)
33
return 0;
35
bool enabled, prohibited = false, filtered;
36
bool secure = arm_is_secure(env);
37
int el = arm_current_el(env);
38
- uint64_t mdcr_el2 = arm_mdcr_el2_eff(env);
39
- uint8_t hpmn = mdcr_el2 & MDCR_HPMN;
40
+ uint64_t mdcr_el2;
41
+ uint8_t hpmn;
42
43
+ /*
44
+ * We might be called for M-profile cores where MDCR_EL2 doesn't
45
+ * exist and arm_mdcr_el2_eff() will assert, so this early-exit check
46
+ * must be before we read that value.
47
+ */
48
if (!arm_feature(env, ARM_FEATURE_PMU)) {
49
return false;
34
}
50
}
35
51
36
+ /* Consider zero feedback as maximum divide ratio possible */
52
+ mdcr_el2 = arm_mdcr_el2_eff(env);
37
+ if (!mult) {
53
+ hpmn = mdcr_el2 & MDCR_HPMN;
38
+ mult = 1 << R_xxx_PLL_CTRL_PLL_FPDIV_LENGTH;
39
+ }
40
+
54
+
41
/* frequency multiplier -> period division */
55
if (!arm_feature(env, ARM_FEATURE_EL2) ||
42
return input / mult;
56
(counter < hpmn || counter == 31)) {
43
}
57
e = env->cp15.c9_pmcr & PMCRE;
44
--
58
--
45
2.20.1
59
2.34.1
46
60
47
61
diff view generated by jsdifflib
New patch
[PULL 17/35] tests/qtest: Fix GMAC test to run on a machine in upstream QEMU
1
From: Nabih Estefan <nabihestefan@google.com>
1
2
3
Fix the nocm_gmac-test.c file to run on a nuvoton 7xx machine instead
4
of 8xx. Also fix comments referencing this and values expecting 8xx.
5
6
Change-Id: Iabd0fba14910c3f1e883c4a9521350f3db9ffab8
7
Signed-Off-By: Nabih Estefan <nabihestefan@google.com>
8
Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
9
Message-id: 20240208194759.2858582-2-nabihestefan@google.com
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
[PMM: commit message tweaks]
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
14
tests/qtest/npcm_gmac-test.c | 84 +-----------------------------------
15
tests/qtest/meson.build | 3 +-
16
2 files changed, 4 insertions(+), 83 deletions(-)
17
18
diff --git a/tests/qtest/npcm_gmac-test.c b/tests/qtest/npcm_gmac-test.c
19
index XXXXXXX..XXXXXXX 100644
20
--- a/tests/qtest/npcm_gmac-test.c
21
+++ b/tests/qtest/npcm_gmac-test.c
22
@@ -XXX,XX +XXX,XX @@ typedef struct TestData {
23
const GMACModule *module;
24
} TestData;
25
26
-/* Values extracted from hw/arm/npcm8xx.c */
27
+/* Values extracted from hw/arm/npcm7xx.c */
28
static const GMACModule gmac_module_list[] = {
29
{
30
.irq = 14,
31
@@ -XXX,XX +XXX,XX @@ static const GMACModule gmac_module_list[] = {
32
.irq = 15,
33
.base_addr = 0xf0804000
34
},
35
- {
36
- .irq = 16,
37
- .base_addr = 0xf0806000
38
- },
39
- {
40
- .irq = 17,
41
- .base_addr = 0xf0808000
42
- }
43
};
44
45
/* Returns the index of the GMAC module. */
46
@@ -XXX,XX +XXX,XX @@ static uint32_t gmac_read(QTestState *qts, const GMACModule *mod,
47
return qtest_readl(qts, mod->base_addr + regno);
48
}
49
50
-static uint16_t pcs_read(QTestState *qts, const GMACModule *mod,
51
- NPCMRegister regno)
52
-{
53
- uint32_t write_value = (regno & 0x3ffe00) >> 9;
54
- qtest_writel(qts, PCS_BASE_ADDRESS + NPCM_PCS_IND_AC_BA, write_value);
55
- uint32_t read_offset = regno & 0x1ff;
56
- return qtest_readl(qts, PCS_BASE_ADDRESS + read_offset);
57
-}
58
-
59
/* Check that GMAC registers are reset to default value */
60
static void test_init(gconstpointer test_data)
61
{
62
const TestData *td = test_data;
63
const GMACModule *mod = td->module;
64
- QTestState *qts = qtest_init("-machine npcm845-evb");
65
+ QTestState *qts = qtest_init("-machine npcm750-evb");
66
67
#define CHECK_REG32(regno, value) \
68
do { \
69
g_assert_cmphex(gmac_read(qts, mod, (regno)), ==, (value)); \
70
} while (0)
71
72
-#define CHECK_REG_PCS(regno, value) \
73
- do { \
74
- g_assert_cmphex(pcs_read(qts, mod, (regno)), ==, (value)); \
75
- } while (0)
76
-
77
CHECK_REG32(NPCM_DMA_BUS_MODE, 0x00020100);
78
CHECK_REG32(NPCM_DMA_XMT_POLL_DEMAND, 0);
79
CHECK_REG32(NPCM_DMA_RCV_POLL_DEMAND, 0);
80
@@ -XXX,XX +XXX,XX @@ static void test_init(gconstpointer test_data)
81
CHECK_REG32(NPCM_GMAC_PTP_TAR, 0);
82
CHECK_REG32(NPCM_GMAC_PTP_TTSR, 0);
83
84
- /* TODO Add registers PCS */
85
- if (mod->base_addr == 0xf0802000) {
86
- CHECK_REG_PCS(NPCM_PCS_SR_CTL_ID1, 0x699e);
87
- CHECK_REG_PCS(NPCM_PCS_SR_CTL_ID2, 0);
88
- CHECK_REG_PCS(NPCM_PCS_SR_CTL_STS, 0x8000);
89
-
90
- CHECK_REG_PCS(NPCM_PCS_SR_MII_CTRL, 0x1140);
91
- CHECK_REG_PCS(NPCM_PCS_SR_MII_STS, 0x0109);
92
- CHECK_REG_PCS(NPCM_PCS_SR_MII_DEV_ID1, 0x699e);
93
- CHECK_REG_PCS(NPCM_PCS_SR_MII_DEV_ID2, 0x0ced0);
94
- CHECK_REG_PCS(NPCM_PCS_SR_MII_AN_ADV, 0x0020);
95
- CHECK_REG_PCS(NPCM_PCS_SR_MII_LP_BABL, 0);
96
- CHECK_REG_PCS(NPCM_PCS_SR_MII_AN_EXPN, 0);
97
- CHECK_REG_PCS(NPCM_PCS_SR_MII_EXT_STS, 0xc000);
98
-
99
- CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_ABL, 0x0003);
100
- CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_TX_MAX_DLY_LWR, 0x0038);
101
- CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_TX_MAX_DLY_UPR, 0);
102
- CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_TX_MIN_DLY_LWR, 0x0038);
103
- CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_TX_MIN_DLY_UPR, 0);
104
- CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_RX_MAX_DLY_LWR, 0x0058);
105
- CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_RX_MAX_DLY_UPR, 0);
106
- CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_RX_MIN_DLY_LWR, 0x0048);
107
- CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_RX_MIN_DLY_UPR, 0);
108
-
109
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MMD_DIG_CTRL1, 0x2400);
110
- CHECK_REG_PCS(NPCM_PCS_VR_MII_AN_CTRL, 0);
111
- CHECK_REG_PCS(NPCM_PCS_VR_MII_AN_INTR_STS, 0x000a);
112
- CHECK_REG_PCS(NPCM_PCS_VR_MII_TC, 0);
113
- CHECK_REG_PCS(NPCM_PCS_VR_MII_DBG_CTRL, 0);
114
- CHECK_REG_PCS(NPCM_PCS_VR_MII_EEE_MCTRL0, 0x899c);
115
- CHECK_REG_PCS(NPCM_PCS_VR_MII_EEE_TXTIMER, 0);
116
- CHECK_REG_PCS(NPCM_PCS_VR_MII_EEE_RXTIMER, 0);
117
- CHECK_REG_PCS(NPCM_PCS_VR_MII_LINK_TIMER_CTRL, 0);
118
- CHECK_REG_PCS(NPCM_PCS_VR_MII_EEE_MCTRL1, 0);
119
- CHECK_REG_PCS(NPCM_PCS_VR_MII_DIG_STS, 0x0010);
120
- CHECK_REG_PCS(NPCM_PCS_VR_MII_ICG_ERRCNT1, 0);
121
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MISC_STS, 0);
122
- CHECK_REG_PCS(NPCM_PCS_VR_MII_RX_LSTS, 0);
123
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_TX_BSTCTRL0, 0x00a);
124
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_TX_LVLCTRL0, 0x007f);
125
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_TX_GENCTRL0, 0x0001);
126
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_TX_GENCTRL1, 0);
127
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_TX_STS, 0);
128
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_RX_GENCTRL0, 0x0100);
129
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_RX_GENCTRL1, 0x1100);
130
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_RX_LOS_CTRL0, 0x000e);
131
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_MPLL_CTRL0, 0x0100);
132
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_MPLL_CTRL1, 0x0032);
133
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_MPLL_STS, 0x0001);
134
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_MISC_CTRL2, 0);
135
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_LVL_CTRL, 0x0019);
136
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_MISC_CTRL0, 0);
137
- CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_MISC_CTRL1, 0);
138
- CHECK_REG_PCS(NPCM_PCS_VR_MII_DIG_CTRL2, 0);
139
- CHECK_REG_PCS(NPCM_PCS_VR_MII_DIG_ERRCNT_SEL, 0);
140
- }
141
-
142
qtest_quit(qts);
143
}
144
145
diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
146
index XXXXXXX..XXXXXXX 100644
147
--- a/tests/qtest/meson.build
148
+++ b/tests/qtest/meson.build
149
@@ -XXX,XX +XXX,XX @@ qtests_npcm7xx = \
150
'npcm7xx_sdhci-test',
151
'npcm7xx_smbus-test',
152
'npcm7xx_timer-test',
153
- 'npcm7xx_watchdog_timer-test'] + \
154
+ 'npcm7xx_watchdog_timer-test',
155
+ 'npcm_gmac-test'] + \
156
(slirp.found() ? ['npcm7xx_emc-test'] : [])
157
qtests_aspeed = \
158
['aspeed_hace-test',
159
--
160
2.34.1
diff view generated by jsdifflib
New patch
[PULL 18/35] hw/arm/smmuv3: add support for stage 1 access fault
1
From: Luc Michel <luc.michel@amd.com>
1
2
3
An access fault is raised when the Access Flag is not set in the
4
looked-up PTE and the AFFD field is not set in the corresponding context
5
descriptor. This was already implemented for stage 2. Implement it for
6
stage 1 as well.
7
8
Signed-off-by: Luc Michel <luc.michel@amd.com>
9
Reviewed-by: Mostafa Saleh <smostafa@google.com>
10
Reviewed-by: Eric Auger <eric.auger@redhat.com>
11
Tested-by: Mostafa Saleh <smostafa@google.com>
12
Message-id: 20240213082211.3330400-1-luc.michel@amd.com
13
[PMM: tweaked comment text]
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
---
16
hw/arm/smmuv3-internal.h | 1 +
17
include/hw/arm/smmu-common.h | 1 +
18
hw/arm/smmu-common.c | 11 +++++++++++
19
hw/arm/smmuv3.c | 1 +
20
4 files changed, 14 insertions(+)
21
22
diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h
23
index XXXXXXX..XXXXXXX 100644
24
--- a/hw/arm/smmuv3-internal.h
25
+++ b/hw/arm/smmuv3-internal.h
26
@@ -XXX,XX +XXX,XX @@ static inline int pa_range(STE *ste)
27
#define CD_EPD(x, sel) extract32((x)->word[0], (16 * (sel)) + 14, 1)
28
#define CD_ENDI(x) extract32((x)->word[0], 15, 1)
29
#define CD_IPS(x) extract32((x)->word[1], 0 , 3)
30
+#define CD_AFFD(x) extract32((x)->word[1], 3 , 1)
31
#define CD_TBI(x) extract32((x)->word[1], 6 , 2)
32
#define CD_HD(x) extract32((x)->word[1], 10 , 1)
33
#define CD_HA(x) extract32((x)->word[1], 11 , 1)
34
diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h
35
index XXXXXXX..XXXXXXX 100644
36
--- a/include/hw/arm/smmu-common.h
37
+++ b/include/hw/arm/smmu-common.h
38
@@ -XXX,XX +XXX,XX @@ typedef struct SMMUTransCfg {
39
bool disabled; /* smmu is disabled */
40
bool bypassed; /* translation is bypassed */
41
bool aborted; /* translation is aborted */
42
+ bool affd; /* AF fault disable */
43
uint32_t iotlb_hits; /* counts IOTLB hits */
44
uint32_t iotlb_misses; /* counts IOTLB misses*/
45
/* Used by stage-1 only. */
46
diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c
47
index XXXXXXX..XXXXXXX 100644
48
--- a/hw/arm/smmu-common.c
49
+++ b/hw/arm/smmu-common.c
50
@@ -XXX,XX +XXX,XX @@ static int smmu_ptw_64_s1(SMMUTransCfg *cfg,
51
pte_addr, pte, iova, gpa,
52
block_size >> 20);
53
}
54
+
55
+ /*
56
+ * QEMU does not currently implement HTTU, so if AFFD and PTE.AF
57
+ * are 0 we take an Access flag fault. (5.4. Context Descriptor)
58
+ * An Access flag fault takes priority over a Permission fault.
59
+ */
60
+ if (!PTE_AF(pte) && !cfg->affd) {
61
+ info->type = SMMU_PTW_ERR_ACCESS;
62
+ goto error;
63
+ }
64
+
65
ap = PTE_AP(pte);
66
if (is_permission_fault(ap, perm)) {
67
info->type = SMMU_PTW_ERR_PERMISSION;
68
diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
69
index XXXXXXX..XXXXXXX 100644
70
--- a/hw/arm/smmuv3.c
71
+++ b/hw/arm/smmuv3.c
72
@@ -XXX,XX +XXX,XX @@ static int decode_cd(SMMUTransCfg *cfg, CD *cd, SMMUEventInfo *event)
73
cfg->oas = MIN(oas2bits(SMMU_IDR5_OAS), cfg->oas);
74
cfg->tbi = CD_TBI(cd);
75
cfg->asid = CD_ASID(cd);
76
+ cfg->affd = CD_AFFD(cd);
77
78
trace_smmuv3_decode_cd(cfg->oas);
79
80
--
81
2.34.1
diff view generated by jsdifflib
[PULL 20/20] hw/block/m25p80: Fix Numonyx fast read dummy cycle count
[PULL 19/35] hw/arm/stellaris: Convert ADC controller to Resettable interface
1
From: Joe Komlodi <joe.komlodi@xilinx.com>
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
2
2
3
Numonyx chips determine the number of cycles to wait based on bits 7:4
3
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
4
in the volatile configuration register.
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
5
Message-id: 20240213155214.13619-2-philmd@linaro.org
6
However, if these bits are 0x0 or 0xF, the number of dummy cycles to
7
wait is 10 for QIOR and QIOR4 commands or when in QIO mode, and otherwise 8 for
8
the currently supported fast read commands. [1]
9
10
[1]
11
https://www.micron.com/-/media/client/global/documents/products/data-sheet/nor-flash/serial-nor/mt25q/die-rev-b/mt25q_qlkt_u_02g_cbb_0.pdf?rev=9b167fbf2b3645efba6385949a72e453
12
13
Signed-off-by: Joe Komlodi <komlodi@xilinx.com>
14
Reviewed-by: Francisco Iglesias <francisco.iglesias@xilinx.com>
15
Message-id: 1605568264-26376-5-git-send-email-komlodi@xilinx.com
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
---
7
---
18
hw/block/m25p80.c | 30 +++++++++++++++++++++++++++---
8
hw/arm/stellaris.c | 6 ++++--
19
1 file changed, 27 insertions(+), 3 deletions(-)
9
1 file changed, 4 insertions(+), 2 deletions(-)
20
10
21
diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
11
diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
22
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
23
--- a/hw/block/m25p80.c
13
--- a/hw/arm/stellaris.c
24
+++ b/hw/block/m25p80.c
14
+++ b/hw/arm/stellaris.c
25
@@ -XXX,XX +XXX,XX @@ static uint8_t numonyx_mode(Flash *s)
15
@@ -XXX,XX +XXX,XX @@ static void stellaris_adc_trigger(void *opaque, int irq, int level)
26
}
16
}
27
}
17
}
28
18
29
+static uint8_t numonyx_extract_cfg_num_dummies(Flash *s)
19
-static void stellaris_adc_reset(StellarisADCState *s)
30
+{
20
+static void stellaris_adc_reset_hold(Object *obj)
31
+ uint8_t num_dummies;
32
+ uint8_t mode;
33
+ assert(get_man(s) == MAN_NUMONYX);
34
+
35
+ mode = numonyx_mode(s);
36
+ num_dummies = extract32(s->volatile_cfg, 4, 4);
37
+
38
+ if (num_dummies == 0x0 || num_dummies == 0xf) {
39
+ switch (s->cmd_in_progress) {
40
+ case QIOR:
41
+ case QIOR4:
42
+ num_dummies = 10;
43
+ break;
44
+ default:
45
+ num_dummies = (mode == MODE_QIO) ? 10 : 8;
46
+ break;
47
+ }
48
+ }
49
+
50
+ return num_dummies;
51
+}
52
+
53
static void decode_fast_read_cmd(Flash *s)
54
{
21
{
55
s->needed_bytes = get_addr_length(s);
22
+ StellarisADCState *s = STELLARIS_ADC(obj);
56
@@ -XXX,XX +XXX,XX @@ static void decode_fast_read_cmd(Flash *s)
23
int n;
57
s->needed_bytes += 8;
24
58
break;
25
for (n = 0; n < 4; n++) {
59
case MAN_NUMONYX:
26
@@ -XXX,XX +XXX,XX @@ static void stellaris_adc_init(Object *obj)
60
- s->needed_bytes += extract32(s->volatile_cfg, 4, 4);
27
memory_region_init_io(&s->iomem, obj, &stellaris_adc_ops, s,
61
+ s->needed_bytes += numonyx_extract_cfg_num_dummies(s);
28
"adc", 0x1000);
62
break;
29
sysbus_init_mmio(sbd, &s->iomem);
63
case MAN_MACRONIX:
30
- stellaris_adc_reset(s);
64
if (extract32(s->volatile_cfg, 6, 2) == 1) {
31
qdev_init_gpio_in(dev, stellaris_adc_trigger, 1);
65
@@ -XXX,XX +XXX,XX @@ static void decode_dio_read_cmd(Flash *s)
32
}
66
);
33
67
break;
34
@@ -XXX,XX +XXX,XX @@ static const TypeInfo stellaris_i2c_info = {
68
case MAN_NUMONYX:
35
static void stellaris_adc_class_init(ObjectClass *klass, void *data)
69
- s->needed_bytes += extract32(s->volatile_cfg, 4, 4);
36
{
70
+ s->needed_bytes += numonyx_extract_cfg_num_dummies(s);
37
DeviceClass *dc = DEVICE_CLASS(klass);
71
break;
38
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
72
case MAN_MACRONIX:
39
73
switch (extract32(s->volatile_cfg, 6, 2)) {
40
+ rc->phases.hold = stellaris_adc_reset_hold;
74
@@ -XXX,XX +XXX,XX @@ static void decode_qio_read_cmd(Flash *s)
41
dc->vmsd = &vmstate_stellaris_adc;
75
);
42
}
76
break;
43
77
case MAN_NUMONYX:
78
- s->needed_bytes += extract32(s->volatile_cfg, 4, 4);
79
+ s->needed_bytes += numonyx_extract_cfg_num_dummies(s);
80
break;
81
case MAN_MACRONIX:
82
switch (extract32(s->volatile_cfg, 6, 2)) {
83
--
44
--
84
2.20.1
45
2.34.1
85
46
86
47
diff view generated by jsdifflib
[PULL 14/20] usb: xlnx-usb-subsystem: Add xilinx usb subsystem
[PULL 20/35] hw/arm/stellaris: Convert I2C controller to Resettable interface
1
From: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
2
2
3
This model is a top level integration wrapper for hcd-dwc3 and
3
Suggested-by: Peter Maydell <peter.maydell@linaro.org>
4
versal-usb2-ctrl-regs modules, this is used by xilinx versal soc's and
4
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
5
future xilinx usb subsystems would also be part of it.
5
Message-id: 20240213155214.13619-3-philmd@linaro.org
6
7
Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
8
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Message-id: 1607023357-5096-4-git-send-email-sai.pavan.boddu@xilinx.com
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
8
---
13
include/hw/usb/xlnx-usb-subsystem.h | 45 ++++++++++++++
9
hw/arm/stellaris.c | 26 ++++++++++++++++++++++----
14
hw/usb/xlnx-usb-subsystem.c | 94 +++++++++++++++++++++++++++++
10
1 file changed, 22 insertions(+), 4 deletions(-)
15
hw/usb/Kconfig | 5 ++
16
hw/usb/meson.build | 1 +
17
4 files changed, 145 insertions(+)
18
create mode 100644 include/hw/usb/xlnx-usb-subsystem.h
19
create mode 100644 hw/usb/xlnx-usb-subsystem.c
20
11
21
diff --git a/include/hw/usb/xlnx-usb-subsystem.h b/include/hw/usb/xlnx-usb-subsystem.h
12
diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
22
new file mode 100644
13
index XXXXXXX..XXXXXXX 100644
23
index XXXXXXX..XXXXXXX
14
--- a/hw/arm/stellaris.c
24
--- /dev/null
15
+++ b/hw/arm/stellaris.c
25
+++ b/include/hw/usb/xlnx-usb-subsystem.h
16
@@ -XXX,XX +XXX,XX @@ static void stellaris_sys_instance_init(Object *obj)
26
@@ -XXX,XX +XXX,XX @@
17
s->sysclk = qdev_init_clock_out(DEVICE(s), "SYSCLK");
18
}
19
20
-/* I2C controller. */
27
+/*
21
+/*
28
+ * QEMU model of the Xilinx usb subsystem
22
+ * I2C controller.
29
+ *
23
+ * ??? For now we only implement the master interface.
30
+ * Copyright (c) 2020 Xilinx Inc. Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
31
+ *
32
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
33
+ * of this software and associated documentation files (the "Software"), to deal
34
+ * in the Software without restriction, including without limitation the rights
35
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
36
+ * copies of the Software, and to permit persons to whom the Software is
37
+ * furnished to do so, subject to the following conditions:
38
+ *
39
+ * The above copyright notice and this permission notice shall be included in
40
+ * all copies or substantial portions of the Software.
41
+ *
42
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
43
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
44
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
45
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
46
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
47
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
48
+ * THE SOFTWARE.
49
+ */
24
+ */
25
26
#define TYPE_STELLARIS_I2C "stellaris-i2c"
27
OBJECT_DECLARE_SIMPLE_TYPE(stellaris_i2c_state, STELLARIS_I2C)
28
@@ -XXX,XX +XXX,XX @@ static void stellaris_i2c_write(void *opaque, hwaddr offset,
29
stellaris_i2c_update(s);
30
}
31
32
-static void stellaris_i2c_reset(stellaris_i2c_state *s)
33
+static void stellaris_i2c_reset_enter(Object *obj, ResetType type)
34
{
35
+ stellaris_i2c_state *s = STELLARIS_I2C(obj);
50
+
36
+
51
+#ifndef _XLNX_VERSAL_USB_SUBSYSTEM_H_
37
if (s->mcs & STELLARIS_I2C_MCS_BUSBSY)
52
+#define _XLNX_VERSAL_USB_SUBSYSTEM_H_
38
i2c_end_transfer(s->bus);
53
+
54
+#include "hw/usb/xlnx-versal-usb2-ctrl-regs.h"
55
+#include "hw/usb/hcd-dwc3.h"
56
+
57
+#define TYPE_XILINX_VERSAL_USB2 "xlnx.versal-usb2"
58
+
59
+#define VERSAL_USB2(obj) \
60
+ OBJECT_CHECK(VersalUsb2, (obj), TYPE_XILINX_VERSAL_USB2)
61
+
62
+typedef struct VersalUsb2 {
63
+ SysBusDevice parent_obj;
64
+ MemoryRegion dwc3_mr;
65
+ MemoryRegion usb2Ctrl_mr;
66
+
67
+ VersalUsb2CtrlRegs usb2Ctrl;
68
+ USBDWC3 dwc3;
69
+} VersalUsb2;
70
+
71
+#endif
72
diff --git a/hw/usb/xlnx-usb-subsystem.c b/hw/usb/xlnx-usb-subsystem.c
73
new file mode 100644
74
index XXXXXXX..XXXXXXX
75
--- /dev/null
76
+++ b/hw/usb/xlnx-usb-subsystem.c
77
@@ -XXX,XX +XXX,XX @@
78
+/*
79
+ * QEMU model of the Xilinx usb subsystem
80
+ *
81
+ * Copyright (c) 2020 Xilinx Inc. Sai Pavan Boddu <sai.pava.boddu@xilinx.com>
82
+ *
83
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
84
+ * of this software and associated documentation files (the "Software"), to deal
85
+ * in the Software without restriction, including without limitation the rights
86
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
87
+ * copies of the Software, and to permit persons to whom the Software is
88
+ * furnished to do so, subject to the following conditions:
89
+ *
90
+ * The above copyright notice and this permission notice shall be included in
91
+ * all copies or substantial portions of the Software.
92
+ *
93
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
94
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
95
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
96
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
97
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
98
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
99
+ * THE SOFTWARE.
100
+ */
101
+
102
+#include "qemu/osdep.h"
103
+#include "hw/sysbus.h"
104
+#include "hw/irq.h"
105
+#include "hw/register.h"
106
+#include "qemu/bitops.h"
107
+#include "qemu/log.h"
108
+#include "qom/object.h"
109
+#include "qapi/error.h"
110
+#include "hw/qdev-properties.h"
111
+#include "hw/usb/xlnx-usb-subsystem.h"
112
+
113
+static void versal_usb2_realize(DeviceState *dev, Error **errp)
114
+{
115
+ VersalUsb2 *s = VERSAL_USB2(dev);
116
+ SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
117
+ Error *err = NULL;
118
+
119
+ sysbus_realize(SYS_BUS_DEVICE(&s->dwc3), &err);
120
+ if (err) {
121
+ error_propagate(errp, err);
122
+ return;
123
+ }
124
+ sysbus_realize(SYS_BUS_DEVICE(&s->usb2Ctrl), &err);
125
+ if (err) {
126
+ error_propagate(errp, err);
127
+ return;
128
+ }
129
+ sysbus_init_mmio(sbd, &s->dwc3_mr);
130
+ sysbus_init_mmio(sbd, &s->usb2Ctrl_mr);
131
+ qdev_pass_gpios(DEVICE(&s->dwc3.sysbus_xhci), dev, SYSBUS_DEVICE_GPIO_IRQ);
132
+}
39
+}
133
+
40
+
134
+static void versal_usb2_init(Object *obj)
41
+static void stellaris_i2c_reset_hold(Object *obj)
135
+{
42
+{
136
+ VersalUsb2 *s = VERSAL_USB2(obj);
43
+ stellaris_i2c_state *s = STELLARIS_I2C(obj);
137
+
44
138
+ object_initialize_child(obj, "versal.dwc3", &s->dwc3,
45
s->msa = 0;
139
+ TYPE_USB_DWC3);
46
s->mcs = 0;
140
+ object_initialize_child(obj, "versal.usb2-ctrl", &s->usb2Ctrl,
47
@@ -XXX,XX +XXX,XX @@ static void stellaris_i2c_reset(stellaris_i2c_state *s)
141
+ TYPE_XILINX_VERSAL_USB2_CTRL_REGS);
48
s->mimr = 0;
142
+ memory_region_init_alias(&s->dwc3_mr, obj, "versal.dwc3_alias",
49
s->mris = 0;
143
+ &s->dwc3.iomem, 0, DWC3_SIZE);
50
s->mcr = 0;
144
+ memory_region_init_alias(&s->usb2Ctrl_mr, obj, "versal.usb2Ctrl_alias",
145
+ &s->usb2Ctrl.iomem, 0, USB2_REGS_R_MAX * 4);
146
+ qdev_alias_all_properties(DEVICE(&s->dwc3), obj);
147
+ qdev_alias_all_properties(DEVICE(&s->dwc3.sysbus_xhci), obj);
148
+ object_property_add_alias(obj, "dma", OBJECT(&s->dwc3.sysbus_xhci), "dma");
149
+}
51
+}
150
+
52
+
151
+static void versal_usb2_class_init(ObjectClass *klass, void *data)
53
+static void stellaris_i2c_reset_exit(Object *obj)
152
+{
54
+{
153
+ DeviceClass *dc = DEVICE_CLASS(klass);
55
+ stellaris_i2c_state *s = STELLARIS_I2C(obj);
154
+
56
+
155
+ dc->realize = versal_usb2_realize;
57
stellaris_i2c_update(s);
156
+}
58
}
157
+
59
158
+static const TypeInfo versal_usb2_info = {
60
@@ -XXX,XX +XXX,XX @@ static void stellaris_i2c_init(Object *obj)
159
+ .name = TYPE_XILINX_VERSAL_USB2,
61
memory_region_init_io(&s->iomem, obj, &stellaris_i2c_ops, s,
160
+ .parent = TYPE_SYS_BUS_DEVICE,
62
"i2c", 0x1000);
161
+ .instance_size = sizeof(VersalUsb2),
63
sysbus_init_mmio(sbd, &s->iomem);
162
+ .class_init = versal_usb2_class_init,
64
- /* ??? For now we only implement the master interface. */
163
+ .instance_init = versal_usb2_init,
65
- stellaris_i2c_reset(s);
164
+};
66
}
165
+
67
166
+static void versal_usb_types(void)
68
/* Analogue to Digital Converter. This is only partially implemented,
167
+{
69
@@ -XXX,XX +XXX,XX @@ type_init(stellaris_machine_init)
168
+ type_register_static(&versal_usb2_info);
70
static void stellaris_i2c_class_init(ObjectClass *klass, void *data)
169
+}
71
{
170
+
72
DeviceClass *dc = DEVICE_CLASS(klass);
171
+type_init(versal_usb_types)
73
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
172
diff --git a/hw/usb/Kconfig b/hw/usb/Kconfig
74
173
index XXXXXXX..XXXXXXX 100644
75
+ rc->phases.enter = stellaris_i2c_reset_enter;
174
--- a/hw/usb/Kconfig
76
+ rc->phases.hold = stellaris_i2c_reset_hold;
175
+++ b/hw/usb/Kconfig
77
+ rc->phases.exit = stellaris_i2c_reset_exit;
176
@@ -XXX,XX +XXX,XX @@ config USB_DWC3
78
dc->vmsd = &vmstate_stellaris_i2c;
177
bool
79
}
178
select USB_XHCI_SYSBUS
80
179
select REGISTER
180
+
181
+config XLNX_USB_SUBSYS
182
+ bool
183
+ default y if XLNX_VERSAL
184
+ select USB_DWC3
185
diff --git a/hw/usb/meson.build b/hw/usb/meson.build
186
index XXXXXXX..XXXXXXX 100644
187
--- a/hw/usb/meson.build
188
+++ b/hw/usb/meson.build
189
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_TUSB6010', if_true: files('tusb6010.c'))
190
softmmu_ss.add(when: 'CONFIG_IMX', if_true: files('chipidea.c'))
191
softmmu_ss.add(when: 'CONFIG_IMX_USBPHY', if_true: files('imx-usb-phy.c'))
192
specific_ss.add(when: 'CONFIG_XLNX_VERSAL', if_true: files('xlnx-versal-usb2-ctrl-regs.c'))
193
+specific_ss.add(when: 'CONFIG_XLNX_USB_SUBSYS', if_true: files('xlnx-usb-subsystem.c'))
194
195
# emulated usb devices
196
softmmu_ss.add(when: 'CONFIG_USB', if_true: files('dev-hub.c'))
197
--
81
--
198
2.20.1
82
2.34.1
199
83
200
84
diff view generated by jsdifflib
[PULL 18/20] hw/block/m25p80: Fix when VCFG XIP bit is set for Numonyx
[PULL 21/35] hw/arm/stellaris: Add missing QOM 'machine' parent
1
From: Joe Komlodi <joe.komlodi@xilinx.com>
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
2
2
3
VCFG XIP is set (disabled) when the NVCFG XIP bits are all set (disabled).
3
QDev objects created with qdev_new() need to manually add
4
their parent relationship with object_property_add_child().
4
5
5
Signed-off-by: Joe Komlodi <komlodi@xilinx.com>
6
This commit plug the devices which aren't part of the SoC;
6
Reviewed-by: Francisco Iglesias <francisco.iglesias@xilinx.com>
7
they will be plugged into a SoC container in the next one.
7
Message-id: 1605568264-26376-3-git-send-email-komlodi@xilinx.com
8
9
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Message-id: 20240213155214.13619-4-philmd@linaro.org
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
13
---
10
hw/block/m25p80.c | 2 +-
14
hw/arm/stellaris.c | 4 ++++
11
1 file changed, 1 insertion(+), 1 deletion(-)
15
1 file changed, 4 insertions(+)
12
16
13
diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
17
diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
14
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
15
--- a/hw/block/m25p80.c
19
--- a/hw/arm/stellaris.c
16
+++ b/hw/block/m25p80.c
20
+++ b/hw/arm/stellaris.c
17
@@ -XXX,XX +XXX,XX @@ static void reset_memory(Flash *s)
21
@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
18
s->volatile_cfg |= VCFG_DUMMY;
22
&error_fatal);
19
s->volatile_cfg |= VCFG_WRAP_SEQUENTIAL;
23
20
if ((s->nonvolatile_cfg & NVCFG_XIP_MODE_MASK)
24
ssddev = qdev_new("ssd0323");
21
- != NVCFG_XIP_MODE_DISABLED) {
25
+ object_property_add_child(OBJECT(ms), "oled", OBJECT(ssddev));
22
+ == NVCFG_XIP_MODE_DISABLED) {
26
qdev_prop_set_uint8(ssddev, "cs", 1);
23
s->volatile_cfg |= VCFG_XIP_MODE_DISABLED;
27
qdev_realize_and_unref(ssddev, bus, &error_fatal);
28
29
gpio_d_splitter = qdev_new(TYPE_SPLIT_IRQ);
30
+ object_property_add_child(OBJECT(ms), "splitter",
31
+ OBJECT(gpio_d_splitter));
32
qdev_prop_set_uint32(gpio_d_splitter, "num-lines", 2);
33
qdev_realize_and_unref(gpio_d_splitter, NULL, &error_fatal);
34
qdev_connect_gpio_out(
35
@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
36
DeviceState *gpad;
37
38
gpad = qdev_new(TYPE_STELLARIS_GAMEPAD);
39
+ object_property_add_child(OBJECT(ms), "gamepad", OBJECT(gpad));
40
for (i = 0; i < ARRAY_SIZE(gpad_keycode); i++) {
41
qlist_append_int(gpad_keycode_list, gpad_keycode[i]);
24
}
42
}
25
s->volatile_cfg |= deposit32(s->volatile_cfg,
26
--
43
--
27
2.20.1
44
2.34.1
28
45
29
46
diff view generated by jsdifflib
[PULL 17/20] hw/block/m25p80: Make Numonyx config field names more accurate
[PULL 22/35] hw/arm/stellaris: Add missing QOM 'SoC' parent
1
From: Joe Komlodi <joe.komlodi@xilinx.com>
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
2
2
3
The previous naming of the configuration registers made it sound like that if
3
QDev objects created with qdev_new() need to manually add
4
the bits were set the settings would be enabled, while the opposite is true.
4
their parent relationship with object_property_add_child().
5
5
6
Signed-off-by: Joe Komlodi <komlodi@xilinx.com>
6
Since we don't model the SoC, just use a QOM container.
7
Reviewed-by: Francisco Iglesias <francisco.iglesias@xilinx.com>
7
8
Message-id: 1605568264-26376-2-git-send-email-komlodi@xilinx.com
8
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Message-id: 20240213155214.13619-5-philmd@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
12
---
11
hw/block/m25p80.c | 12 ++++++------
13
hw/arm/stellaris.c | 11 ++++++++++-
12
1 file changed, 6 insertions(+), 6 deletions(-)
14
1 file changed, 10 insertions(+), 1 deletion(-)
13
15
14
diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
16
diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
15
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/block/m25p80.c
18
--- a/hw/arm/stellaris.c
17
+++ b/hw/block/m25p80.c
19
+++ b/hw/arm/stellaris.c
18
@@ -XXX,XX +XXX,XX @@ typedef struct FlashPartInfo {
20
@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
19
#define VCFG_WRAP_SEQUENTIAL 0x2
21
* 400fe000 system control
20
#define NVCFG_XIP_MODE_DISABLED (7 << 9)
22
*/
21
#define NVCFG_XIP_MODE_MASK (7 << 9)
23
22
-#define VCFG_XIP_MODE_ENABLED (1 << 3)
24
+ Object *soc_container;
23
+#define VCFG_XIP_MODE_DISABLED (1 << 3)
25
DeviceState *gpio_dev[7], *nvic;
24
#define CFG_DUMMY_CLK_LEN 4
26
qemu_irq gpio_in[7][8];
25
#define NVCFG_DUMMY_CLK_POS 12
27
qemu_irq gpio_out[7][8];
26
#define VCFG_DUMMY_CLK_POS 4
28
@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
27
@@ -XXX,XX +XXX,XX @@ typedef struct FlashPartInfo {
29
flash_size = (((board->dc0 & 0xffff) + 1) << 1) * 1024;
28
#define EVCFG_VPP_ACCELERATOR (1 << 3)
30
sram_size = ((board->dc0 >> 18) + 1) * 1024;
29
#define EVCFG_RESET_HOLD_ENABLED (1 << 4)
31
30
#define NVCFG_DUAL_IO_MASK (1 << 2)
32
+ soc_container = object_new("container");
31
-#define EVCFG_DUAL_IO_ENABLED (1 << 6)
33
+ object_property_add_child(OBJECT(ms), "soc", soc_container);
32
+#define EVCFG_DUAL_IO_DISABLED (1 << 6)
34
+
33
#define NVCFG_QUAD_IO_MASK (1 << 3)
35
/* Flash programming is done via the SCU, so pretend it is ROM. */
34
-#define EVCFG_QUAD_IO_ENABLED (1 << 7)
36
memory_region_init_rom(flash, NULL, "stellaris.flash", flash_size,
35
+#define EVCFG_QUAD_IO_DISABLED (1 << 7)
37
&error_fatal);
36
#define NVCFG_4BYTE_ADDR_MASK (1 << 0)
38
@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
37
#define NVCFG_LOWER_SEGMENT_MASK (1 << 1)
39
* need its sysclk output.
38
40
*/
39
@@ -XXX,XX +XXX,XX @@ static void reset_memory(Flash *s)
41
ssys_dev = qdev_new(TYPE_STELLARIS_SYS);
40
s->volatile_cfg |= VCFG_WRAP_SEQUENTIAL;
42
+ object_property_add_child(soc_container, "sys", OBJECT(ssys_dev));
41
if ((s->nonvolatile_cfg & NVCFG_XIP_MODE_MASK)
43
42
!= NVCFG_XIP_MODE_DISABLED) {
44
/*
43
- s->volatile_cfg |= VCFG_XIP_MODE_ENABLED;
45
* Most devices come preprogrammed with a MAC address in the user data.
44
+ s->volatile_cfg |= VCFG_XIP_MODE_DISABLED;
46
@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
45
}
47
sysbus_realize_and_unref(SYS_BUS_DEVICE(ssys_dev), &error_fatal);
46
s->volatile_cfg |= deposit32(s->volatile_cfg,
48
47
VCFG_DUMMY_CLK_POS,
49
nvic = qdev_new(TYPE_ARMV7M);
48
@@ -XXX,XX +XXX,XX @@ static void reset_memory(Flash *s)
50
+ object_property_add_child(soc_container, "v7m", OBJECT(nvic));
49
s->enh_volatile_cfg |= EVCFG_VPP_ACCELERATOR;
51
qdev_prop_set_uint32(nvic, "num-irq", NUM_IRQ_LINES);
50
s->enh_volatile_cfg |= EVCFG_RESET_HOLD_ENABLED;
52
qdev_prop_set_uint8(nvic, "num-prio-bits", NUM_PRIO_BITS);
51
if (s->nonvolatile_cfg & NVCFG_DUAL_IO_MASK) {
53
qdev_prop_set_string(nvic, "cpu-type", ms->cpu_type);
52
- s->enh_volatile_cfg |= EVCFG_DUAL_IO_ENABLED;
54
@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
53
+ s->enh_volatile_cfg |= EVCFG_DUAL_IO_DISABLED;
55
54
}
56
dev = qdev_new(TYPE_STELLARIS_GPTM);
55
if (s->nonvolatile_cfg & NVCFG_QUAD_IO_MASK) {
57
sbd = SYS_BUS_DEVICE(dev);
56
- s->enh_volatile_cfg |= EVCFG_QUAD_IO_ENABLED;
58
+ object_property_add_child(soc_container, "gptm[*]", OBJECT(dev));
57
+ s->enh_volatile_cfg |= EVCFG_QUAD_IO_DISABLED;
59
qdev_connect_clock_in(dev, "clk",
58
}
60
qdev_get_clock_out(ssys_dev, "SYSCLK"));
59
if (!(s->nonvolatile_cfg & NVCFG_4BYTE_ADDR_MASK)) {
61
sysbus_realize_and_unref(sbd, &error_fatal);
60
s->four_bytes_address_mode = true;
62
@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
63
64
if (board->dc1 & (1 << 3)) { /* watchdog present */
65
dev = qdev_new(TYPE_LUMINARY_WATCHDOG);
66
-
67
+ object_property_add_child(soc_container, "wdg", OBJECT(dev));
68
qdev_connect_clock_in(dev, "WDOGCLK",
69
qdev_get_clock_out(ssys_dev, "SYSCLK"));
70
71
@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
72
SysBusDevice *sbd;
73
74
dev = qdev_new("pl011_luminary");
75
+ object_property_add_child(soc_container, "uart[*]", OBJECT(dev));
76
sbd = SYS_BUS_DEVICE(dev);
77
qdev_prop_set_chr(dev, "chardev", serial_hd(i));
78
sysbus_realize_and_unref(sbd, &error_fatal);
79
@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
80
DeviceState *enet;
81
82
enet = qdev_new("stellaris_enet");
83
+ object_property_add_child(soc_container, "enet", OBJECT(enet));
84
if (nd) {
85
qdev_set_nic_properties(enet, nd);
86
} else {
61
--
87
--
62
2.20.1
88
2.34.1
63
89
64
90
diff view generated by jsdifflib
New patch
[PULL 23/35] target/arm: Use new CBAR encoding for all v8 CPUs, not all aarch64 CPUs
1
We support two different encodings for the AArch32 IMPDEF
2
CBAR register -- older cores like the Cortex A9, A7, A15
3
have this at 4, c15, c0, 0; newer cores like the
4
Cortex A35, A53, A57 and A72 have it at 1 c15 c0 0.
1
5
6
When we implemented this we picked which encoding to
7
use based on whether the CPU set ARM_FEATURE_AARCH64.
8
However this isn't right for three cases:
9
* the qemu-system-arm 'max' CPU, which is supposed to be
10
a variant on a Cortex-A57; it ought to use the same
11
encoding the A57 does and which the AArch64 'max'
12
exposes to AArch32 guest code
13
* the Cortex-R52, which is AArch32-only but has the CBAR
14
at the newer encoding (and where we incorrectly are
15
not yet setting ARM_FEATURE_CBAR_RO anyway)
16
* any possible future support for other v8 AArch32
17
only CPUs, or for supporting "boot the CPU into
18
AArch32 mode" on our existing cores like the A57 etc
19
20
Make the decision of the encoding be based on whether
21
the CPU implements the ARM_FEATURE_V8 flag instead.
22
23
This changes the behaviour only for the qemu-system-arm
24
'-cpu max'. We don't expect anybody to be relying on the
25
old behaviour because:
26
* it's not what the real hardware Cortex-A57 does
27
(and that's what our ID register claims we are)
28
* we don't implement the memory-mapped GICv3 support
29
which is the only thing that exists at the peripheral
30
base address pointed to by the register
31
32
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
33
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
34
Message-id: 20240206132931.38376-2-peter.maydell@linaro.org
35
---
36
target/arm/helper.c | 2 +-
37
1 file changed, 1 insertion(+), 1 deletion(-)
38
39
diff --git a/target/arm/helper.c b/target/arm/helper.c
40
index XXXXXXX..XXXXXXX 100644
41
--- a/target/arm/helper.c
42
+++ b/target/arm/helper.c
43
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
44
* AArch64 cores we might need to add a specific feature flag
45
* to indicate cores with "flavour 2" CBAR.
46
*/
47
- if (arm_feature(env, ARM_FEATURE_AARCH64)) {
48
+ if (arm_feature(env, ARM_FEATURE_V8)) {
49
/* 32 bit view is [31:18] 0...0 [43:32]. */
50
uint32_t cbar32 = (extract64(cpu->reset_cbar, 18, 14) << 18)
51
| extract64(cpu->reset_cbar, 32, 12);
52
--
53
2.34.1
diff view generated by jsdifflib
New patch
[PULL 24/35] target/arm: The Cortex-R52 has a read-only CBAR
1
The Cortex-R52 implements the Configuration Base Address Register
2
(CBAR), as a read-only register. Add ARM_FEATURE_CBAR_RO to this CPU
3
type, so that our implementation provides the register and the
4
associated qdev property.
1
5
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20240206132931.38376-3-peter.maydell@linaro.org
9
---
10
target/arm/tcg/cpu32.c | 1 +
11
1 file changed, 1 insertion(+)
12
13
diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c
14
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/tcg/cpu32.c
16
+++ b/target/arm/tcg/cpu32.c
17
@@ -XXX,XX +XXX,XX @@ static void cortex_r52_initfn(Object *obj)
18
set_feature(&cpu->env, ARM_FEATURE_PMSA);
19
set_feature(&cpu->env, ARM_FEATURE_NEON);
20
set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
21
+ set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
22
cpu->midr = 0x411fd133; /* r1p3 */
23
cpu->revidr = 0x00000000;
24
cpu->reset_fpsid = 0x41034023;
25
--
26
2.34.1
diff view generated by jsdifflib
[PULL 03/20] hw/openrisc/openrisc_sim: Abstract out "get IRQ x of CPU y"
[PULL 25/35] target/arm: Add Cortex-R52 IMPDEF sysregs
1
We're about to refactor the OpenRISC pic_cpu code in a way that means
1
Add the Cortex-R52 IMPDEF sysregs, by defining them here and
2
that just grabbing the whole qemu_irq[] array of inbound IRQs for a
2
also by enabling the AUXCR feature which defines the ACTLR
3
CPU won't be possible any more. Abstract out a function for "return
3
and HACTLR registers. As is our usual practice, we make these
4
the qemu_irq for IRQ x input of CPU y" so we can more easily replace
4
simple reads-as-zero stubs for now.
5
the implementation.
6
5
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Stafford Horne <shorne@gmail.com>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20201127225127.14770-3-peter.maydell@linaro.org
8
Message-id: 20240206132931.38376-4-peter.maydell@linaro.org
10
---
9
---
11
hw/openrisc/openrisc_sim.c | 38 +++++++++++++++++++++-----------------
10
target/arm/tcg/cpu32.c | 108 +++++++++++++++++++++++++++++++++++++++++
12
1 file changed, 21 insertions(+), 17 deletions(-)
11
1 file changed, 108 insertions(+)
13
12
14
diff --git a/hw/openrisc/openrisc_sim.c b/hw/openrisc/openrisc_sim.c
13
diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c
15
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/openrisc/openrisc_sim.c
15
--- a/target/arm/tcg/cpu32.c
17
+++ b/hw/openrisc/openrisc_sim.c
16
+++ b/target/arm/tcg/cpu32.c
18
@@ -XXX,XX +XXX,XX @@ static void main_cpu_reset(void *opaque)
17
@@ -XXX,XX +XXX,XX @@ static void cortex_r5_initfn(Object *obj)
19
cpu_set_pc(cs, boot_info.bootstrap_pc);
18
define_arm_cp_regs(cpu, cortexr5_cp_reginfo);
20
}
19
}
21
20
22
+static qemu_irq get_cpu_irq(OpenRISCCPU *cpus[], int cpunum, int irq_pin)
21
+static const ARMCPRegInfo cortex_r52_cp_reginfo[] = {
23
+{
22
+ { .name = "CPUACTLR", .cp = 15, .opc1 = 0, .crm = 15,
24
+ return cpus[cpunum]->env.irq[irq_pin];
23
+ .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
25
+}
24
+ { .name = "IMP_ATCMREGIONR",
25
+ .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0,
26
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
27
+ { .name = "IMP_BTCMREGIONR",
28
+ .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1,
29
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
30
+ { .name = "IMP_CTCMREGIONR",
31
+ .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 2,
32
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
33
+ { .name = "IMP_CSCTLR",
34
+ .cp = 15, .opc1 = 1, .crn = 9, .crm = 1, .opc2 = 0,
35
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
36
+ { .name = "IMP_BPCTLR",
37
+ .cp = 15, .opc1 = 1, .crn = 9, .crm = 1, .opc2 = 1,
38
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
39
+ { .name = "IMP_MEMPROTCLR",
40
+ .cp = 15, .opc1 = 1, .crn = 9, .crm = 1, .opc2 = 2,
41
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
42
+ { .name = "IMP_SLAVEPCTLR",
43
+ .cp = 15, .opc1 = 0, .crn = 11, .crm = 0, .opc2 = 0,
44
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
45
+ { .name = "IMP_PERIPHREGIONR",
46
+ .cp = 15, .opc1 = 0, .crn = 15, .crm = 0, .opc2 = 0,
47
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
48
+ { .name = "IMP_FLASHIFREGIONR",
49
+ .cp = 15, .opc1 = 0, .crn = 15, .crm = 0, .opc2 = 1,
50
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
51
+ { .name = "IMP_BUILDOPTR",
52
+ .cp = 15, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 0,
53
+ .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
54
+ { .name = "IMP_PINOPTR",
55
+ .cp = 15, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 7,
56
+ .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
57
+ { .name = "IMP_QOSR",
58
+ .cp = 15, .opc1 = 1, .crn = 15, .crm = 3, .opc2 = 1,
59
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
60
+ { .name = "IMP_BUSTIMEOUTR",
61
+ .cp = 15, .opc1 = 1, .crn = 15, .crm = 3, .opc2 = 2,
62
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
63
+ { .name = "IMP_INTMONR",
64
+ .cp = 15, .opc1 = 1, .crn = 15, .crm = 3, .opc2 = 4,
65
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
66
+ { .name = "IMP_ICERR0",
67
+ .cp = 15, .opc1 = 2, .crn = 15, .crm = 0, .opc2 = 0,
68
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
69
+ { .name = "IMP_ICERR1",
70
+ .cp = 15, .opc1 = 2, .crn = 15, .crm = 0, .opc2 = 1,
71
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
72
+ { .name = "IMP_DCERR0",
73
+ .cp = 15, .opc1 = 2, .crn = 15, .crm = 1, .opc2 = 0,
74
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
75
+ { .name = "IMP_DCERR1",
76
+ .cp = 15, .opc1 = 2, .crn = 15, .crm = 1, .opc2 = 1,
77
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
78
+ { .name = "IMP_TCMERR0",
79
+ .cp = 15, .opc1 = 2, .crn = 15, .crm = 2, .opc2 = 0,
80
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
81
+ { .name = "IMP_TCMERR1",
82
+ .cp = 15, .opc1 = 2, .crn = 15, .crm = 2, .opc2 = 1,
83
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
84
+ { .name = "IMP_TCMSYNDR0",
85
+ .cp = 15, .opc1 = 2, .crn = 15, .crm = 2, .opc2 = 2,
86
+ .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
87
+ { .name = "IMP_TCMSYNDR1",
88
+ .cp = 15, .opc1 = 2, .crn = 15, .crm = 2, .opc2 = 3,
89
+ .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
90
+ { .name = "IMP_FLASHERR0",
91
+ .cp = 15, .opc1 = 2, .crn = 15, .crm = 3, .opc2 = 0,
92
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
93
+ { .name = "IMP_FLASHERR1",
94
+ .cp = 15, .opc1 = 2, .crn = 15, .crm = 3, .opc2 = 1,
95
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
96
+ { .name = "IMP_CDBGDR0",
97
+ .cp = 15, .opc1 = 3, .crn = 15, .crm = 0, .opc2 = 0,
98
+ .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
99
+ { .name = "IMP_CBDGBR1",
100
+ .cp = 15, .opc1 = 3, .crn = 15, .crm = 0, .opc2 = 1,
101
+ .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
102
+ { .name = "IMP_TESTR0",
103
+ .cp = 15, .opc1 = 4, .crn = 15, .crm = 0, .opc2 = 0,
104
+ .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
105
+ { .name = "IMP_TESTR1",
106
+ .cp = 15, .opc1 = 4, .crn = 15, .crm = 0, .opc2 = 1,
107
+ .access = PL1_W, .type = ARM_CP_NOP, .resetvalue = 0 },
108
+ { .name = "IMP_CDBGDCI",
109
+ .cp = 15, .opc1 = 0, .crn = 15, .crm = 15, .opc2 = 0,
110
+ .access = PL1_W, .type = ARM_CP_NOP, .resetvalue = 0 },
111
+ { .name = "IMP_CDBGDCT",
112
+ .cp = 15, .opc1 = 3, .crn = 15, .crm = 2, .opc2 = 0,
113
+ .access = PL1_W, .type = ARM_CP_NOP, .resetvalue = 0 },
114
+ { .name = "IMP_CDBGICT",
115
+ .cp = 15, .opc1 = 3, .crn = 15, .crm = 2, .opc2 = 1,
116
+ .access = PL1_W, .type = ARM_CP_NOP, .resetvalue = 0 },
117
+ { .name = "IMP_CDBGDCD",
118
+ .cp = 15, .opc1 = 3, .crn = 15, .crm = 4, .opc2 = 0,
119
+ .access = PL1_W, .type = ARM_CP_NOP, .resetvalue = 0 },
120
+ { .name = "IMP_CDBGICD",
121
+ .cp = 15, .opc1 = 3, .crn = 15, .crm = 4, .opc2 = 1,
122
+ .access = PL1_W, .type = ARM_CP_NOP, .resetvalue = 0 },
123
+};
26
+
124
+
27
static void openrisc_sim_net_init(hwaddr base, hwaddr descriptors,
125
+
28
- int num_cpus, qemu_irq **cpu_irqs,
126
static void cortex_r52_initfn(Object *obj)
29
+ int num_cpus, OpenRISCCPU *cpus[],
30
int irq_pin, NICInfo *nd)
31
{
127
{
32
DeviceState *dev;
128
ARMCPU *cpu = ARM_CPU(obj);
33
@@ -XXX,XX +XXX,XX @@ static void openrisc_sim_net_init(hwaddr base, hwaddr descriptors,
129
@@ -XXX,XX +XXX,XX @@ static void cortex_r52_initfn(Object *obj)
34
qdev_prop_set_uint32(splitter, "num-lines", num_cpus);
130
set_feature(&cpu->env, ARM_FEATURE_NEON);
35
qdev_realize_and_unref(splitter, NULL, &error_fatal);
131
set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
36
for (i = 0; i < num_cpus; i++) {
132
set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
37
- qdev_connect_gpio_out(splitter, i, cpu_irqs[i][irq_pin]);
133
+ set_feature(&cpu->env, ARM_FEATURE_AUXCR);
38
+ qdev_connect_gpio_out(splitter, i, get_cpu_irq(cpus, i, irq_pin));
134
cpu->midr = 0x411fd133; /* r1p3 */
39
}
135
cpu->revidr = 0x00000000;
40
sysbus_connect_irq(s, 0, qdev_get_gpio_in(splitter, 0));
136
cpu->reset_fpsid = 0x41034023;
41
} else {
137
@@ -XXX,XX +XXX,XX @@ static void cortex_r52_initfn(Object *obj)
42
- sysbus_connect_irq(s, 0, cpu_irqs[0][irq_pin]);
138
43
+ sysbus_connect_irq(s, 0, get_cpu_irq(cpus, 0, irq_pin));
139
cpu->pmsav7_dregion = 16;
44
}
140
cpu->pmsav8r_hdregion = 16;
45
sysbus_mmio_map(s, 0, base);
141
+
46
sysbus_mmio_map(s, 1, descriptors);
142
+ define_arm_cp_regs(cpu, cortex_r52_cp_reginfo);
47
}
143
}
48
144
49
static void openrisc_sim_ompic_init(hwaddr base, int num_cpus,
145
static void cortex_r5f_initfn(Object *obj)
50
- qemu_irq **cpu_irqs, int irq_pin)
51
+ OpenRISCCPU *cpus[], int irq_pin)
52
{
53
DeviceState *dev;
54
SysBusDevice *s;
55
@@ -XXX,XX +XXX,XX @@ static void openrisc_sim_ompic_init(hwaddr base, int num_cpus,
56
s = SYS_BUS_DEVICE(dev);
57
sysbus_realize_and_unref(s, &error_fatal);
58
for (i = 0; i < num_cpus; i++) {
59
- sysbus_connect_irq(s, i, cpu_irqs[i][irq_pin]);
60
+ sysbus_connect_irq(s, i, get_cpu_irq(cpus, i, irq_pin));
61
}
62
sysbus_mmio_map(s, 0, base);
63
}
64
@@ -XXX,XX +XXX,XX @@ static void openrisc_sim_init(MachineState *machine)
65
{
66
ram_addr_t ram_size = machine->ram_size;
67
const char *kernel_filename = machine->kernel_filename;
68
- OpenRISCCPU *cpu = NULL;
69
+ OpenRISCCPU *cpus[2] = {};
70
MemoryRegion *ram;
71
- qemu_irq *cpu_irqs[2];
72
qemu_irq serial_irq;
73
int n;
74
unsigned int smp_cpus = machine->smp.cpus;
75
76
assert(smp_cpus >= 1 && smp_cpus <= 2);
77
for (n = 0; n < smp_cpus; n++) {
78
- cpu = OPENRISC_CPU(cpu_create(machine->cpu_type));
79
- if (cpu == NULL) {
80
+ cpus[n] = OPENRISC_CPU(cpu_create(machine->cpu_type));
81
+ if (cpus[n] == NULL) {
82
fprintf(stderr, "Unable to find CPU definition!\n");
83
exit(1);
84
}
85
- cpu_openrisc_pic_init(cpu);
86
- cpu_irqs[n] = (qemu_irq *) cpu->env.irq;
87
+ cpu_openrisc_pic_init(cpus[n]);
88
89
- cpu_openrisc_clock_init(cpu);
90
+ cpu_openrisc_clock_init(cpus[n]);
91
92
- qemu_register_reset(main_cpu_reset, cpu);
93
+ qemu_register_reset(main_cpu_reset, cpus[n]);
94
}
95
96
ram = g_malloc(sizeof(*ram));
97
@@ -XXX,XX +XXX,XX @@ static void openrisc_sim_init(MachineState *machine)
98
99
if (nd_table[0].used) {
100
openrisc_sim_net_init(0x92000000, 0x92000400, smp_cpus,
101
- cpu_irqs, 4, nd_table);
102
+ cpus, 4, nd_table);
103
}
104
105
if (smp_cpus > 1) {
106
- openrisc_sim_ompic_init(0x98000000, smp_cpus, cpu_irqs, 1);
107
+ openrisc_sim_ompic_init(0x98000000, smp_cpus, cpus, 1);
108
109
- serial_irq = qemu_irq_split(cpu_irqs[0][2], cpu_irqs[1][2]);
110
+ serial_irq = qemu_irq_split(get_cpu_irq(cpus, 0, 2),
111
+ get_cpu_irq(cpus, 1, 2));
112
} else {
113
- serial_irq = cpu_irqs[0][2];
114
+ serial_irq = get_cpu_irq(cpus, 0, 2);
115
}
116
117
serial_mm_init(get_system_memory(), 0x90000000, 0, serial_irq,
118
--
146
--
119
2.20.1
147
2.34.1
120
121
diff view generated by jsdifflib
[PULL 10/20] elf_ops.h: Don't truncate name of the ROM blobs we create
[PULL 26/35] target/arm: Allow access to SPSR_hyp from hyp mode
1
Currently the load_elf code assembles the ROM blob name into a
1
Architecturally, the AArch32 MSR/MRS to/from banked register
2
local 128 byte fixed-size array. Use g_strdup_printf() instead so
2
instructions are UNPREDICTABLE for attempts to access a banked
3
that we don't truncate the pathname if it happens to be long.
3
register that the guest could access in a more direct way (e.g.
4
(This matters mostly for monitor 'info roms' output and for the
4
using this insn to access r8_fiq when already in FIQ mode). QEMU has
5
error messages if ROM blobs overlap.)
5
chosen to UNDEF on all of these.
6
7
However, for the case of accessing SPSR_hyp from hyp mode, it turns
8
out that real hardware permits this, with the same effect as if the
9
guest had directly written to SPSR. Further, there is some
10
guest code out there that assumes it can do this, because it
11
happens to work on hardware: an example Cortex-R52 startup code
12
fragment uses this, and it got copied into various other places,
13
including Zephyr. Zephyr was fixed to not use this:
14
https://github.com/zephyrproject-rtos/zephyr/issues/47330
15
but other examples are still out there, like the selftest
16
binary for the MPS3-AN536.
17
18
For convenience of being able to run guest code, permit
19
this UNPREDICTABLE access instead of UNDEFing it.
6
20
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
21
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
22
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20201129203923.10622-4-peter.maydell@linaro.org
23
Message-id: 20240206132931.38376-5-peter.maydell@linaro.org
10
---
24
---
11
include/hw/elf_ops.h | 4 ++--
25
target/arm/tcg/op_helper.c | 43 ++++++++++++++++++++++++++------------
12
1 file changed, 2 insertions(+), 2 deletions(-)
26
target/arm/tcg/translate.c | 19 +++++++++++------
27
2 files changed, 43 insertions(+), 19 deletions(-)
13
28
14
diff --git a/include/hw/elf_ops.h b/include/hw/elf_ops.h
29
diff --git a/target/arm/tcg/op_helper.c b/target/arm/tcg/op_helper.c
15
index XXXXXXX..XXXXXXX 100644
30
index XXXXXXX..XXXXXXX 100644
16
--- a/include/hw/elf_ops.h
31
--- a/target/arm/tcg/op_helper.c
17
+++ b/include/hw/elf_ops.h
32
+++ b/target/arm/tcg/op_helper.c
18
@@ -XXX,XX +XXX,XX @@ static int glue(load_elf, SZ)(const char *name, int fd,
33
@@ -XXX,XX +XXX,XX @@ static void msr_mrs_banked_exc_checks(CPUARMState *env, uint32_t tgtmode,
19
uint64_t addr, low = (uint64_t)-1, high = 0;
34
*/
20
GMappedFile *mapped_file = NULL;
35
int curmode = env->uncached_cpsr & CPSR_M;
21
uint8_t *data = NULL;
36
22
- char label[128];
37
- if (regno == 17) {
23
int ret = ELF_LOAD_FAILED;
38
- /* ELR_Hyp: a special case because access from tgtmode is OK */
24
39
- if (curmode != ARM_CPU_MODE_HYP && curmode != ARM_CPU_MODE_MON) {
25
if (read(fd, &ehdr, sizeof(ehdr)) != sizeof(ehdr))
40
- goto undef;
26
@@ -XXX,XX +XXX,XX @@ static int glue(load_elf, SZ)(const char *name, int fd,
41
+ if (tgtmode == ARM_CPU_MODE_HYP) {
27
*/
42
+ /*
28
if (mem_size != 0) {
43
+ * Handle Hyp target regs first because some are special cases
29
if (load_rom) {
44
+ * which don't want the usual "not accessible from tgtmode" check.
30
- snprintf(label, sizeof(label), "phdr #%d: %s", i, name);
45
+ */
31
+ g_autofree char *label =
46
+ switch (regno) {
32
+ g_strdup_printf("phdr #%d: %s", i, name);
47
+ case 16 ... 17: /* ELR_Hyp, SPSR_Hyp */
33
48
+ if (curmode != ARM_CPU_MODE_HYP && curmode != ARM_CPU_MODE_MON) {
34
/*
49
+ goto undef;
35
* rom_add_elf_program() takes its own reference to
50
+ }
51
+ break;
52
+ case 13:
53
+ if (curmode != ARM_CPU_MODE_MON) {
54
+ goto undef;
55
+ }
56
+ break;
57
+ default:
58
+ g_assert_not_reached();
59
}
60
return;
61
}
62
@@ -XXX,XX +XXX,XX @@ static void msr_mrs_banked_exc_checks(CPUARMState *env, uint32_t tgtmode,
63
}
64
}
65
66
- if (tgtmode == ARM_CPU_MODE_HYP) {
67
- /* SPSR_Hyp, r13_hyp: accessible from Monitor mode only */
68
- if (curmode != ARM_CPU_MODE_MON) {
69
- goto undef;
70
- }
71
- }
72
-
73
return;
74
75
undef:
76
@@ -XXX,XX +XXX,XX @@ void HELPER(msr_banked)(CPUARMState *env, uint32_t value, uint32_t tgtmode,
77
78
switch (regno) {
79
case 16: /* SPSRs */
80
- env->banked_spsr[bank_number(tgtmode)] = value;
81
+ if (tgtmode == (env->uncached_cpsr & CPSR_M)) {
82
+ /* Only happens for SPSR_Hyp access in Hyp mode */
83
+ env->spsr = value;
84
+ } else {
85
+ env->banked_spsr[bank_number(tgtmode)] = value;
86
+ }
87
break;
88
case 17: /* ELR_Hyp */
89
env->elr_el[2] = value;
90
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(mrs_banked)(CPUARMState *env, uint32_t tgtmode, uint32_t regno)
91
92
switch (regno) {
93
case 16: /* SPSRs */
94
- return env->banked_spsr[bank_number(tgtmode)];
95
+ if (tgtmode == (env->uncached_cpsr & CPSR_M)) {
96
+ /* Only happens for SPSR_Hyp access in Hyp mode */
97
+ return env->spsr;
98
+ } else {
99
+ return env->banked_spsr[bank_number(tgtmode)];
100
+ }
101
case 17: /* ELR_Hyp */
102
return env->elr_el[2];
103
case 13:
104
diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c
105
index XXXXXXX..XXXXXXX 100644
106
--- a/target/arm/tcg/translate.c
107
+++ b/target/arm/tcg/translate.c
108
@@ -XXX,XX +XXX,XX @@ static bool msr_banked_access_decode(DisasContext *s, int r, int sysm, int rn,
109
break;
110
case ARM_CPU_MODE_HYP:
111
/*
112
- * SPSR_hyp and r13_hyp can only be accessed from Monitor mode
113
- * (and so we can forbid accesses from EL2 or below). elr_hyp
114
- * can be accessed also from Hyp mode, so forbid accesses from
115
- * EL0 or EL1.
116
+ * r13_hyp can only be accessed from Monitor mode, and so we
117
+ * can forbid accesses from EL2 or below.
118
+ * elr_hyp can be accessed also from Hyp mode, so forbid
119
+ * accesses from EL0 or EL1.
120
+ * SPSR_hyp is supposed to be in the same category as r13_hyp
121
+ * and UNPREDICTABLE if accessed from anything except Monitor
122
+ * mode. However there is some real-world code that will do
123
+ * it because at least some hardware happens to permit the
124
+ * access. (Notably a standard Cortex-R52 startup code fragment
125
+ * does this.) So we permit SPSR_hyp from Hyp mode also, to allow
126
+ * this (incorrect) guest code to run.
127
*/
128
- if (!arm_dc_feature(s, ARM_FEATURE_EL2) || s->current_el < 2 ||
129
- (s->current_el < 3 && *regno != 17)) {
130
+ if (!arm_dc_feature(s, ARM_FEATURE_EL2) || s->current_el < 2
131
+ || (s->current_el < 3 && *regno != 16 && *regno != 17)) {
132
goto undef;
133
}
134
break;
36
--
135
--
37
2.20.1
136
2.34.1
38
39
diff view generated by jsdifflib
[PULL 01/20] gdbstub: Correct misparsing of vCont C/S requests
[PULL 27/35] hw/misc/mps2-scc: Fix condition for CFG3 register
1
In the vCont packet, two of the command actions (C and S) take an
1
We currently guard the CFG3 register read with
2
argument specifying the signal to be sent to the process/thread, which is
2
(scc_partno(s) == 0x524 && scc_partno(s) == 0x547)
3
sent as an ASCII string of two hex digits which immediately follow the
3
which is clearly wrong as it is never true.
4
'C' or 'S' character.
5
4
6
Our code for parsing this packet accidentally skipped the first of the
5
This register is present on all board types except AN524
7
two bytes of the signal value, because it started parsing the hex string
6
and AN527; correct the condition.
8
at 'p + 1' when the preceding code had already moved past the 'C' or
9
'S' with "cur_action = *p++".
10
7
11
This meant that we would only do the right thing for signals below
8
Fixes: 6ac80818941829c0 ("hw/misc/mps2-scc: Implement changes for AN547")
12
10, and would misinterpret the rest. For instance, when the debugger
13
wants to send the process a SIGPROF (27 on x86-64) we mangle this into
14
a SIGSEGV (11).
15
16
Remove the accidental double increment.
17
18
Fixes: https://bugs.launchpad.net/qemu/+bug/1773743
19
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
20
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
10
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
21
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
11
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
22
Message-id: 20201121210342.10089-1-peter.maydell@linaro.org
12
Message-id: 20240206132931.38376-6-peter.maydell@linaro.org
23
---
13
---
24
gdbstub.c | 2 +-
14
hw/misc/mps2-scc.c | 2 +-
25
1 file changed, 1 insertion(+), 1 deletion(-)
15
1 file changed, 1 insertion(+), 1 deletion(-)
26
16
27
diff --git a/gdbstub.c b/gdbstub.c
17
diff --git a/hw/misc/mps2-scc.c b/hw/misc/mps2-scc.c
28
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
29
--- a/gdbstub.c
19
--- a/hw/misc/mps2-scc.c
30
+++ b/gdbstub.c
20
+++ b/hw/misc/mps2-scc.c
31
@@ -XXX,XX +XXX,XX @@ static int gdb_handle_vcont(const char *p)
21
@@ -XXX,XX +XXX,XX @@ static uint64_t mps2_scc_read(void *opaque, hwaddr offset, unsigned size)
32
cur_action = *p++;
22
r = s->cfg2;
33
if (cur_action == 'C' || cur_action == 'S') {
23
break;
34
cur_action = qemu_tolower(cur_action);
24
case A_CFG3:
35
- res = qemu_strtoul(p + 1, &p, 16, &tmp);
25
- if (scc_partno(s) == 0x524 && scc_partno(s) == 0x547) {
36
+ res = qemu_strtoul(p, &p, 16, &tmp);
26
+ if (scc_partno(s) == 0x524 || scc_partno(s) == 0x547) {
37
if (res) {
27
/* CFG3 reserved on AN524 */
38
goto out;
28
goto bad_offset;
39
}
29
}
40
--
30
--
41
2.20.1
31
2.34.1
42
32
43
33
diff view generated by jsdifflib
[PULL 09/20] hw/core/loader.c: Improve reporting of ROM overlap errors
[PULL 28/35] hw/misc/mps2-scc: Factor out which-board conditionals
1
In rom_check_and_register_reset() we report to the user if there is
1
The MPS SCC device has a lot of different flavours for the various
2
a "ROM region overlap". This has a couple of problems:
2
different MPS FPGA images, which look mostly similar but have
3
* the reported information is not very easy to intepret
3
differences in how particular registers are handled. Currently we
4
* the function just prints the overlap to stderr (and relies on
4
deal with this with a lot of open-coded checks on scc_partno(), but
5
its single callsite in vl.c to do an error_report() and exit)
5
as we add more board types this is getting a bit hard to read.
6
* only the first overlap encountered is diagnosed
7
6
8
Make this function use error_report() and error_printf() and
7
Factor out the conditions into some functions which we can
9
report a more user-friendly report with all the overlaps
8
give more descriptive names to.
10
diagnosed.
11
12
Sample old output:
13
14
rom: requested regions overlap (rom dtb. free=0x0000000000008000, addr=0x0000000000000000)
15
qemu-system-aarch64: rom check and register reset failed
16
17
Sample new output:
18
19
qemu-system-aarch64: Some ROM regions are overlapping
20
These ROM regions might have been loaded by direct user request or by default.
21
They could be BIOS/firmware images, a guest kernel, initrd or some other file loaded into guest memory.
22
Check whether you intended to load all this guest code, and whether it has been built to load to the correct addresses.
23
24
The following two regions overlap (in the cpu-memory-0 address space):
25
phdr #0: /home/petmay01/linaro/qemu-misc-tests/ldmia-fault.axf (addresses 0x0000000000000000 - 0x0000000000008000)
26
dtb (addresses 0x0000000000000000 - 0x0000000000100000)
27
28
The following two regions overlap (in the cpu-memory-0 address space):
29
phdr #1: /home/petmay01/linaro/qemu-misc-tests/bad-psci-call.axf (addresses 0x0000000040000000 - 0x0000000040000010)
30
phdr #0: /home/petmay01/linaro/qemu-misc-tests/bp-test.elf (addresses 0x0000000040000000 - 0x0000000040000020)
31
9
32
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
33
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
12
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
34
Message-id: 20201129203923.10622-3-peter.maydell@linaro.org
13
Message-id: 20240206132931.38376-7-peter.maydell@linaro.org
35
---
14
---
36
hw/core/loader.c | 48 ++++++++++++++++++++++++++++++++++++++++++------
15
hw/misc/mps2-scc.c | 45 +++++++++++++++++++++++++++++++--------------
37
softmmu/vl.c | 1 -
16
1 file changed, 31 insertions(+), 14 deletions(-)
38
2 files changed, 42 insertions(+), 7 deletions(-)
39
17
40
diff --git a/hw/core/loader.c b/hw/core/loader.c
18
diff --git a/hw/misc/mps2-scc.c b/hw/misc/mps2-scc.c
41
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
42
--- a/hw/core/loader.c
20
--- a/hw/misc/mps2-scc.c
43
+++ b/hw/core/loader.c
21
+++ b/hw/misc/mps2-scc.c
44
@@ -XXX,XX +XXX,XX @@ static bool roms_overlap(Rom *last_rom, Rom *this_rom)
22
@@ -XXX,XX +XXX,XX @@ static int scc_partno(MPS2SCC *s)
45
last_rom->addr + last_rom->romsize > this_rom->addr;
23
return extract32(s->id, 4, 8);
46
}
24
}
47
25
48
+static const char *rom_as_name(Rom *rom)
26
+/* Is CFG_REG2 present? */
27
+static bool have_cfg2(MPS2SCC *s)
49
+{
28
+{
50
+ const char *name = rom->as ? rom->as->name : NULL;
29
+ return scc_partno(s) == 0x524 || scc_partno(s) == 0x547;
51
+ return name ?: "anonymous";
52
+}
30
+}
53
+
31
+
54
+static void rom_print_overlap_error_header(void)
32
+/* Is CFG_REG3 present? */
33
+static bool have_cfg3(MPS2SCC *s)
55
+{
34
+{
56
+ error_report("Some ROM regions are overlapping");
35
+ return scc_partno(s) != 0x524 && scc_partno(s) != 0x547;
57
+ error_printf(
58
+ "These ROM regions might have been loaded by "
59
+ "direct user request or by default.\n"
60
+ "They could be BIOS/firmware images, a guest kernel, "
61
+ "initrd or some other file loaded into guest memory.\n"
62
+ "Check whether you intended to load all this guest code, and "
63
+ "whether it has been built to load to the correct addresses.\n");
64
+}
36
+}
65
+
37
+
66
+static void rom_print_one_overlap_error(Rom *last_rom, Rom *rom)
38
+/* Is CFG_REG5 present? */
39
+static bool have_cfg5(MPS2SCC *s)
67
+{
40
+{
68
+ error_printf(
41
+ return scc_partno(s) == 0x524 || scc_partno(s) == 0x547;
69
+ "\nThe following two regions overlap (in the %s address space):\n",
70
+ rom_as_name(rom));
71
+ error_printf(
72
+ " %s (addresses 0x" TARGET_FMT_plx " - 0x" TARGET_FMT_plx ")\n",
73
+ last_rom->name, last_rom->addr, last_rom->addr + last_rom->romsize);
74
+ error_printf(
75
+ " %s (addresses 0x" TARGET_FMT_plx " - 0x" TARGET_FMT_plx ")\n",
76
+ rom->name, rom->addr, rom->addr + rom->romsize);
77
+}
42
+}
78
+
43
+
79
int rom_check_and_register_reset(void)
44
+/* Is CFG_REG6 present? */
80
{
45
+static bool have_cfg6(MPS2SCC *s)
81
MemoryRegionSection section;
46
+{
82
Rom *rom, *last_rom = NULL;
47
+ return scc_partno(s) == 0x524;
83
+ bool found_overlap = false;
48
+}
84
49
+
85
QTAILQ_FOREACH(rom, &roms, next) {
50
/* Handle a write via the SYS_CFG channel to the specified function/device.
86
if (rom->fw_file) {
51
* Return false on error (reported to guest via SYS_CFGCTRL ERROR bit).
87
@@ -XXX,XX +XXX,XX @@ int rom_check_and_register_reset(void)
52
*/
53
@@ -XXX,XX +XXX,XX @@ static uint64_t mps2_scc_read(void *opaque, hwaddr offset, unsigned size)
54
r = s->cfg1;
55
break;
56
case A_CFG2:
57
- if (scc_partno(s) != 0x524 && scc_partno(s) != 0x547) {
58
- /* CFG2 reserved on other boards */
59
+ if (!have_cfg2(s)) {
60
goto bad_offset;
88
}
61
}
89
if (!rom->mr) {
62
r = s->cfg2;
90
if (roms_overlap(last_rom, rom)) {
63
break;
91
- fprintf(stderr, "rom: requested regions overlap "
64
case A_CFG3:
92
- "(rom %s. free=0x" TARGET_FMT_plx
65
- if (scc_partno(s) == 0x524 || scc_partno(s) == 0x547) {
93
- ", addr=0x" TARGET_FMT_plx ")\n",
66
- /* CFG3 reserved on AN524 */
94
- rom->name, last_rom->addr + last_rom->romsize,
67
+ if (!have_cfg3(s)) {
95
- rom->addr);
68
goto bad_offset;
96
- return -1;
97
+ if (!found_overlap) {
98
+ found_overlap = true;
99
+ rom_print_overlap_error_header();
100
+ }
101
+ rom_print_one_overlap_error(last_rom, rom);
102
+ /* Keep going through the list so we report all overlaps */
103
}
104
last_rom = rom;
105
}
69
}
106
@@ -XXX,XX +XXX,XX @@ int rom_check_and_register_reset(void)
70
/* These are user-settable DIP switches on the board. We don't
107
rom->isrom = int128_nz(section.size) && memory_region_is_rom(section.mr);
71
@@ -XXX,XX +XXX,XX @@ static uint64_t mps2_scc_read(void *opaque, hwaddr offset, unsigned size)
108
memory_region_unref(section.mr);
72
r = s->cfg4;
109
}
73
break;
110
+ if (found_overlap) {
74
case A_CFG5:
111
+ return -1;
75
- if (scc_partno(s) != 0x524 && scc_partno(s) != 0x547) {
112
+ }
76
- /* CFG5 reserved on other boards */
113
+
77
+ if (!have_cfg5(s)) {
114
qemu_register_reset(rom_reset, NULL);
78
goto bad_offset;
115
roms_loaded = 1;
79
}
116
return 0;
80
r = s->cfg5;
117
diff --git a/softmmu/vl.c b/softmmu/vl.c
81
break;
118
index XXXXXXX..XXXXXXX 100644
82
case A_CFG6:
119
--- a/softmmu/vl.c
83
- if (scc_partno(s) != 0x524) {
120
+++ b/softmmu/vl.c
84
- /* CFG6 reserved on other boards */
121
@@ -XXX,XX +XXX,XX @@ static void qemu_machine_creation_done(void)
85
+ if (!have_cfg6(s)) {
122
qemu_run_machine_init_done_notifiers();
86
goto bad_offset;
123
87
}
124
if (rom_check_and_register_reset() != 0) {
88
r = s->cfg6;
125
- error_report("rom check and register reset failed");
89
@@ -XXX,XX +XXX,XX @@ static void mps2_scc_write(void *opaque, hwaddr offset, uint64_t value,
126
exit(1);
90
}
127
}
91
break;
128
92
case A_CFG2:
93
- if (scc_partno(s) != 0x524 && scc_partno(s) != 0x547) {
94
- /* CFG2 reserved on other boards */
95
+ if (!have_cfg2(s)) {
96
goto bad_offset;
97
}
98
/* AN524: QSPI Select signal */
99
s->cfg2 = value;
100
break;
101
case A_CFG5:
102
- if (scc_partno(s) != 0x524 && scc_partno(s) != 0x547) {
103
- /* CFG5 reserved on other boards */
104
+ if (!have_cfg5(s)) {
105
goto bad_offset;
106
}
107
/* AN524: ACLK frequency in Hz */
108
s->cfg5 = value;
109
break;
110
case A_CFG6:
111
- if (scc_partno(s) != 0x524) {
112
- /* CFG6 reserved on other boards */
113
+ if (!have_cfg6(s)) {
114
goto bad_offset;
115
}
116
/* AN524: Clock divider for BRAM */
129
--
117
--
130
2.20.1
118
2.34.1
131
119
132
120
diff view generated by jsdifflib
[PULL 13/20] usb: Add DWC3 model
[PULL 29/35] hw/misc/mps2-scc: Make changes needed for AN536 FPGA image
1
From: Vikram Garhwal <fnu.vikram@xilinx.com>
1
The MPS2 SCC device is broadly the same for all FPGA images, but has
2
2
minor differences in the behaviour of the CFG registers depending on
3
This patch adds skeleton model of dwc3 usb controller attached to
3
the image. In many cases we don't really care about the functionality
4
xhci-sysbus device. It defines global register space of DWC3 controller,
4
controlled by these registers and a reads-as-written or similar
5
global registers control the AXI/AHB interfaces properties, external FIFO
5
behaviour is sufficient for the moment.
6
support and event count support. All of which are unimplemented at
6
7
present,we are only supporting core reset and read of ID register.
7
For the AN536 the required behaviour is:
8
8
9
Signed-off-by: Vikram Garhwal <fnu.vikram@xilinx.com>
9
* A_CFG0 has CPU reset and halt bits
10
Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
10
- implement as reads-as-written for the moment
11
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
11
* A_CFG1 has flash or ATCM address 0 remap handling
12
Message-id: 1607023357-5096-3-git-send-email-sai.pavan.boddu@xilinx.com
12
- QEMU doesn't model this; implement as reads-as-written
13
* A_CFG2 has QSPI select (like AN524)
14
- implemented (no behaviour, as with AN524)
15
* A_CFG3 is MCC_MSB_ADDR "additional MCC addressing bits"
16
- QEMU doesn't care about these, so use the existing
17
RAZ behaviour for convenience
18
* A_CFG4 is board rev (like all other images)
19
- no change needed
20
* A_CFG5 is ACLK frq in hz (like AN524)
21
- implemented as reads-as-written, as for other boards
22
* A_CFG6 is core 0 vector table base address
23
- implemented as reads-as-written for the moment
24
* A_CFG7 is core 1 vector table base address
25
- implemented as reads-as-written for the moment
26
27
Make the changes necessary for this; leave TODO comments where
28
appropriate to indicate where we might want to come back and
29
implement things like CPU reset.
30
31
The other aspects of the device specific to this FPGA image (like the
32
values of the board ID and similar registers) will be set via the
33
device's qdev properties.
34
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
35
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
36
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
37
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
38
Message-id: 20240206132931.38376-8-peter.maydell@linaro.org
14
---
39
---
15
include/hw/usb/hcd-dwc3.h | 55 +++
40
include/hw/misc/mps2-scc.h | 1 +
16
hw/usb/hcd-dwc3.c | 689 ++++++++++++++++++++++++++++++++++++++
41
hw/misc/mps2-scc.c | 101 +++++++++++++++++++++++++++++++++----
17
hw/usb/Kconfig | 5 +
42
2 files changed, 92 insertions(+), 10 deletions(-)
18
hw/usb/meson.build | 1 +
43
19
4 files changed, 750 insertions(+)
44
diff --git a/include/hw/misc/mps2-scc.h b/include/hw/misc/mps2-scc.h
20
create mode 100644 include/hw/usb/hcd-dwc3.h
45
index XXXXXXX..XXXXXXX 100644
21
create mode 100644 hw/usb/hcd-dwc3.c
46
--- a/include/hw/misc/mps2-scc.h
22
47
+++ b/include/hw/misc/mps2-scc.h
23
diff --git a/include/hw/usb/hcd-dwc3.h b/include/hw/usb/hcd-dwc3.h
48
@@ -XXX,XX +XXX,XX @@ struct MPS2SCC {
24
new file mode 100644
49
uint32_t cfg4;
25
index XXXXXXX..XXXXXXX
50
uint32_t cfg5;
26
--- /dev/null
51
uint32_t cfg6;
27
+++ b/include/hw/usb/hcd-dwc3.h
52
+ uint32_t cfg7;
28
@@ -XXX,XX +XXX,XX @@
53
uint32_t cfgdata_rtn;
29
+/*
54
uint32_t cfgdata_out;
30
+ * QEMU model of the USB DWC3 host controller emulation.
55
uint32_t cfgctrl;
31
+ *
56
diff --git a/hw/misc/mps2-scc.c b/hw/misc/mps2-scc.c
32
+ * Copyright (c) 2020 Xilinx Inc.
57
index XXXXXXX..XXXXXXX 100644
33
+ *
58
--- a/hw/misc/mps2-scc.c
34
+ * Written by Vikram Garhwal<fnu.vikram@xilinx.com>
59
+++ b/hw/misc/mps2-scc.c
35
+ *
60
@@ -XXX,XX +XXX,XX @@ REG32(CFG3, 0xc)
36
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
61
REG32(CFG4, 0x10)
37
+ * of this software and associated documentation files (the "Software"), to deal
62
REG32(CFG5, 0x14)
38
+ * in the Software without restriction, including without limitation the rights
63
REG32(CFG6, 0x18)
39
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
64
+REG32(CFG7, 0x1c)
40
+ * copies of the Software, and to permit persons to whom the Software is
65
REG32(CFGDATA_RTN, 0xa0)
41
+ * furnished to do so, subject to the following conditions:
66
REG32(CFGDATA_OUT, 0xa4)
42
+ *
67
REG32(CFGCTRL, 0xa8)
43
+ * The above copyright notice and this permission notice shall be included in
68
@@ -XXX,XX +XXX,XX @@ static int scc_partno(MPS2SCC *s)
44
+ * all copies or substantial portions of the Software.
69
/* Is CFG_REG2 present? */
45
+ *
70
static bool have_cfg2(MPS2SCC *s)
46
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
71
{
47
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
72
- return scc_partno(s) == 0x524 || scc_partno(s) == 0x547;
48
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
73
+ return scc_partno(s) == 0x524 || scc_partno(s) == 0x547 ||
49
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
74
+ scc_partno(s) == 0x536;
50
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
75
}
51
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
76
52
+ * THE SOFTWARE.
77
/* Is CFG_REG3 present? */
53
+ */
78
static bool have_cfg3(MPS2SCC *s)
54
+#ifndef HCD_DWC3_H
79
{
55
+#define HCD_DWC3_H
80
- return scc_partno(s) != 0x524 && scc_partno(s) != 0x547;
56
+
81
+ return scc_partno(s) != 0x524 && scc_partno(s) != 0x547 &&
57
+#include "hw/usb/hcd-xhci.h"
82
+ scc_partno(s) != 0x536;
58
+#include "hw/usb/hcd-xhci-sysbus.h"
83
}
59
+
84
60
+#define TYPE_USB_DWC3 "usb_dwc3"
85
/* Is CFG_REG5 present? */
61
+
86
static bool have_cfg5(MPS2SCC *s)
62
+#define USB_DWC3(obj) \
87
{
63
+ OBJECT_CHECK(USBDWC3, (obj), TYPE_USB_DWC3)
88
- return scc_partno(s) == 0x524 || scc_partno(s) == 0x547;
64
+
89
+ return scc_partno(s) == 0x524 || scc_partno(s) == 0x547 ||
65
+#define USB_DWC3_R_MAX ((0x530 / 4) + 1)
90
+ scc_partno(s) == 0x536;
66
+#define DWC3_SIZE 0x10000
91
}
67
+
92
68
+typedef struct USBDWC3 {
93
/* Is CFG_REG6 present? */
69
+ SysBusDevice parent_obj;
94
static bool have_cfg6(MPS2SCC *s)
70
+ MemoryRegion iomem;
95
{
71
+ XHCISysbusState sysbus_xhci;
96
- return scc_partno(s) == 0x524;
72
+
97
+ return scc_partno(s) == 0x524 || scc_partno(s) == 0x536;
73
+ uint32_t regs[USB_DWC3_R_MAX];
98
+}
74
+ RegisterInfo regs_info[USB_DWC3_R_MAX];
99
+
75
+
100
+/* Is CFG_REG7 present? */
76
+ struct {
101
+static bool have_cfg7(MPS2SCC *s)
77
+ uint8_t mode;
102
+{
78
+ uint32_t dwc_usb3_user;
103
+ return scc_partno(s) == 0x536;
79
+ } cfg;
104
+}
80
+
105
+
81
+} USBDWC3;
106
+/* Does CFG_REG0 drive the 'remap' GPIO output? */
82
+
107
+static bool cfg0_is_remap(MPS2SCC *s)
83
+#endif
108
+{
84
diff --git a/hw/usb/hcd-dwc3.c b/hw/usb/hcd-dwc3.c
109
+ return scc_partno(s) != 0x536;
85
new file mode 100644
110
+}
86
index XXXXXXX..XXXXXXX
111
+
87
--- /dev/null
112
+/* Is CFG_REG1 driving a set of LEDs? */
88
+++ b/hw/usb/hcd-dwc3.c
113
+static bool cfg1_is_leds(MPS2SCC *s)
89
@@ -XXX,XX +XXX,XX @@
114
+{
90
+/*
115
+ return scc_partno(s) != 0x536;
91
+ * QEMU model of the USB DWC3 host controller emulation.
116
}
92
+ *
117
93
+ * This model defines global register space of DWC3 controller. Global
118
/* Handle a write via the SYS_CFG channel to the specified function/device.
94
+ * registers control the AXI/AHB interfaces properties, external FIFO support
119
@@ -XXX,XX +XXX,XX @@ static uint64_t mps2_scc_read(void *opaque, hwaddr offset, unsigned size)
95
+ * and event count support. All of which are unimplemented at present. We are
120
if (!have_cfg3(s)) {
96
+ * only supporting core reset and read of ID register.
121
goto bad_offset;
97
+ *
122
}
98
+ * Copyright (c) 2020 Xilinx Inc. Vikram Garhwal<fnu.vikram@xilinx.com>
123
- /* These are user-settable DIP switches on the board. We don't
99
+ *
124
+ /*
100
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
125
+ * These are user-settable DIP switches on the board. We don't
101
+ * of this software and associated documentation files (the "Software"), to deal
126
* model that, so just return zeroes.
102
+ * in the Software without restriction, including without limitation the rights
127
+ *
103
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
128
+ * TODO: for AN536 this is MCC_MSB_ADDR "additional MCC addressing
104
+ * copies of the Software, and to permit persons to whom the Software is
129
+ * bits". These change which part of the DDR4 the motherboard
105
+ * furnished to do so, subject to the following conditions:
130
+ * configuration controller can see in its memory map (see the
106
+ *
131
+ * appnote section 2.4). QEMU doesn't model the MCC at all, so these
107
+ * The above copyright notice and this permission notice shall be included in
132
+ * bits are not interesting to us; read-as-zero is as good as anything
108
+ * all copies or substantial portions of the Software.
133
+ * else.
109
+ *
134
*/
110
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
135
r = 0;
111
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
136
break;
112
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
137
@@ -XXX,XX +XXX,XX @@ static uint64_t mps2_scc_read(void *opaque, hwaddr offset, unsigned size)
113
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
138
}
114
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
139
r = s->cfg6;
115
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
140
break;
116
+ * THE SOFTWARE.
141
+ case A_CFG7:
117
+ */
142
+ if (!have_cfg7(s)) {
118
+
143
+ goto bad_offset;
119
+#include "qemu/osdep.h"
120
+#include "hw/sysbus.h"
121
+#include "hw/register.h"
122
+#include "qemu/bitops.h"
123
+#include "qemu/log.h"
124
+#include "qom/object.h"
125
+#include "migration/vmstate.h"
126
+#include "hw/qdev-properties.h"
127
+#include "hw/usb/hcd-dwc3.h"
128
+#include "qapi/error.h"
129
+
130
+#ifndef USB_DWC3_ERR_DEBUG
131
+#define USB_DWC3_ERR_DEBUG 0
132
+#endif
133
+
134
+#define HOST_MODE 1
135
+#define FIFO_LEN 0x1000
136
+
137
+REG32(GSBUSCFG0, 0x00)
138
+ FIELD(GSBUSCFG0, DATRDREQINFO, 28, 4)
139
+ FIELD(GSBUSCFG0, DESRDREQINFO, 24, 4)
140
+ FIELD(GSBUSCFG0, DATWRREQINFO, 20, 4)
141
+ FIELD(GSBUSCFG0, DESWRREQINFO, 16, 4)
142
+ FIELD(GSBUSCFG0, RESERVED_15_12, 12, 4)
143
+ FIELD(GSBUSCFG0, DATBIGEND, 11, 1)
144
+ FIELD(GSBUSCFG0, DESBIGEND, 10, 1)
145
+ FIELD(GSBUSCFG0, RESERVED_9_8, 8, 2)
146
+ FIELD(GSBUSCFG0, INCR256BRSTENA, 7, 1)
147
+ FIELD(GSBUSCFG0, INCR128BRSTENA, 6, 1)
148
+ FIELD(GSBUSCFG0, INCR64BRSTENA, 5, 1)
149
+ FIELD(GSBUSCFG0, INCR32BRSTENA, 4, 1)
150
+ FIELD(GSBUSCFG0, INCR16BRSTENA, 3, 1)
151
+ FIELD(GSBUSCFG0, INCR8BRSTENA, 2, 1)
152
+ FIELD(GSBUSCFG0, INCR4BRSTENA, 1, 1)
153
+ FIELD(GSBUSCFG0, INCRBRSTENA, 0, 1)
154
+REG32(GSBUSCFG1, 0x04)
155
+ FIELD(GSBUSCFG1, RESERVED_31_13, 13, 19)
156
+ FIELD(GSBUSCFG1, EN1KPAGE, 12, 1)
157
+ FIELD(GSBUSCFG1, PIPETRANSLIMIT, 8, 4)
158
+ FIELD(GSBUSCFG1, RESERVED_7_0, 0, 8)
159
+REG32(GTXTHRCFG, 0x08)
160
+ FIELD(GTXTHRCFG, RESERVED_31, 31, 1)
161
+ FIELD(GTXTHRCFG, RESERVED_30, 30, 1)
162
+ FIELD(GTXTHRCFG, USBTXPKTCNTSEL, 29, 1)
163
+ FIELD(GTXTHRCFG, RESERVED_28, 28, 1)
164
+ FIELD(GTXTHRCFG, USBTXPKTCNT, 24, 4)
165
+ FIELD(GTXTHRCFG, USBMAXTXBURSTSIZE, 16, 8)
166
+ FIELD(GTXTHRCFG, RESERVED_15, 15, 1)
167
+ FIELD(GTXTHRCFG, RESERVED_14, 14, 1)
168
+ FIELD(GTXTHRCFG, RESERVED_13_11, 11, 3)
169
+ FIELD(GTXTHRCFG, RESERVED_10_0, 0, 11)
170
+REG32(GRXTHRCFG, 0x0c)
171
+ FIELD(GRXTHRCFG, RESERVED_31_30, 30, 2)
172
+ FIELD(GRXTHRCFG, USBRXPKTCNTSEL, 29, 1)
173
+ FIELD(GRXTHRCFG, RESERVED_28, 28, 1)
174
+ FIELD(GRXTHRCFG, USBRXPKTCNT, 24, 4)
175
+ FIELD(GRXTHRCFG, USBMAXRXBURSTSIZE, 19, 5)
176
+ FIELD(GRXTHRCFG, RESERVED_18_16, 16, 3)
177
+ FIELD(GRXTHRCFG, RESERVED_15, 15, 1)
178
+ FIELD(GRXTHRCFG, RESERVED_14_13, 13, 2)
179
+ FIELD(GRXTHRCFG, RESVISOCOUTSPC, 0, 13)
180
+REG32(GCTL, 0x10)
181
+ FIELD(GCTL, PWRDNSCALE, 19, 13)
182
+ FIELD(GCTL, MASTERFILTBYPASS, 18, 1)
183
+ FIELD(GCTL, BYPSSETADDR, 17, 1)
184
+ FIELD(GCTL, U2RSTECN, 16, 1)
185
+ FIELD(GCTL, FRMSCLDWN, 14, 2)
186
+ FIELD(GCTL, PRTCAPDIR, 12, 2)
187
+ FIELD(GCTL, CORESOFTRESET, 11, 1)
188
+ FIELD(GCTL, U1U2TIMERSCALE, 9, 1)
189
+ FIELD(GCTL, DEBUGATTACH, 8, 1)
190
+ FIELD(GCTL, RAMCLKSEL, 6, 2)
191
+ FIELD(GCTL, SCALEDOWN, 4, 2)
192
+ FIELD(GCTL, DISSCRAMBLE, 3, 1)
193
+ FIELD(GCTL, U2EXIT_LFPS, 2, 1)
194
+ FIELD(GCTL, GBLHIBERNATIONEN, 1, 1)
195
+ FIELD(GCTL, DSBLCLKGTNG, 0, 1)
196
+REG32(GPMSTS, 0x14)
197
+REG32(GSTS, 0x18)
198
+ FIELD(GSTS, CBELT, 20, 12)
199
+ FIELD(GSTS, RESERVED_19_12, 12, 8)
200
+ FIELD(GSTS, SSIC_IP, 11, 1)
201
+ FIELD(GSTS, OTG_IP, 10, 1)
202
+ FIELD(GSTS, BC_IP, 9, 1)
203
+ FIELD(GSTS, ADP_IP, 8, 1)
204
+ FIELD(GSTS, HOST_IP, 7, 1)
205
+ FIELD(GSTS, DEVICE_IP, 6, 1)
206
+ FIELD(GSTS, CSRTIMEOUT, 5, 1)
207
+ FIELD(GSTS, BUSERRADDRVLD, 4, 1)
208
+ FIELD(GSTS, RESERVED_3_2, 2, 2)
209
+ FIELD(GSTS, CURMOD, 0, 2)
210
+REG32(GUCTL1, 0x1c)
211
+ FIELD(GUCTL1, RESUME_OPMODE_HS_HOST, 10, 1)
212
+REG32(GSNPSID, 0x20)
213
+REG32(GGPIO, 0x24)
214
+ FIELD(GGPIO, GPO, 16, 16)
215
+ FIELD(GGPIO, GPI, 0, 16)
216
+REG32(GUID, 0x28)
217
+REG32(GUCTL, 0x2c)
218
+ FIELD(GUCTL, REFCLKPER, 22, 10)
219
+ FIELD(GUCTL, NOEXTRDL, 21, 1)
220
+ FIELD(GUCTL, RESERVED_20_18, 18, 3)
221
+ FIELD(GUCTL, SPRSCTRLTRANSEN, 17, 1)
222
+ FIELD(GUCTL, RESBWHSEPS, 16, 1)
223
+ FIELD(GUCTL, RESERVED_15, 15, 1)
224
+ FIELD(GUCTL, USBHSTINAUTORETRYEN, 14, 1)
225
+ FIELD(GUCTL, ENOVERLAPCHK, 13, 1)
226
+ FIELD(GUCTL, EXTCAPSUPPTEN, 12, 1)
227
+ FIELD(GUCTL, INSRTEXTRFSBODI, 11, 1)
228
+ FIELD(GUCTL, DTCT, 9, 2)
229
+ FIELD(GUCTL, DTFT, 0, 9)
230
+REG32(GBUSERRADDRLO, 0x30)
231
+REG32(GBUSERRADDRHI, 0x34)
232
+REG32(GHWPARAMS0, 0x40)
233
+ FIELD(GHWPARAMS0, GHWPARAMS0_31_24, 24, 8)
234
+ FIELD(GHWPARAMS0, GHWPARAMS0_23_16, 16, 8)
235
+ FIELD(GHWPARAMS0, GHWPARAMS0_15_8, 8, 8)
236
+ FIELD(GHWPARAMS0, GHWPARAMS0_7_6, 6, 2)
237
+ FIELD(GHWPARAMS0, GHWPARAMS0_5_3, 3, 3)
238
+ FIELD(GHWPARAMS0, GHWPARAMS0_2_0, 0, 3)
239
+REG32(GHWPARAMS1, 0x44)
240
+ FIELD(GHWPARAMS1, GHWPARAMS1_31, 31, 1)
241
+ FIELD(GHWPARAMS1, GHWPARAMS1_30, 30, 1)
242
+ FIELD(GHWPARAMS1, GHWPARAMS1_29, 29, 1)
243
+ FIELD(GHWPARAMS1, GHWPARAMS1_28, 28, 1)
244
+ FIELD(GHWPARAMS1, GHWPARAMS1_27, 27, 1)
245
+ FIELD(GHWPARAMS1, GHWPARAMS1_26, 26, 1)
246
+ FIELD(GHWPARAMS1, GHWPARAMS1_25_24, 24, 2)
247
+ FIELD(GHWPARAMS1, GHWPARAMS1_23, 23, 1)
248
+ FIELD(GHWPARAMS1, GHWPARAMS1_22_21, 21, 2)
249
+ FIELD(GHWPARAMS1, GHWPARAMS1_20_15, 15, 6)
250
+ FIELD(GHWPARAMS1, GHWPARAMS1_14_12, 12, 3)
251
+ FIELD(GHWPARAMS1, GHWPARAMS1_11_9, 9, 3)
252
+ FIELD(GHWPARAMS1, GHWPARAMS1_8_6, 6, 3)
253
+ FIELD(GHWPARAMS1, GHWPARAMS1_5_3, 3, 3)
254
+ FIELD(GHWPARAMS1, GHWPARAMS1_2_0, 0, 3)
255
+REG32(GHWPARAMS2, 0x48)
256
+REG32(GHWPARAMS3, 0x4c)
257
+ FIELD(GHWPARAMS3, GHWPARAMS3_31, 31, 1)
258
+ FIELD(GHWPARAMS3, GHWPARAMS3_30_23, 23, 8)
259
+ FIELD(GHWPARAMS3, GHWPARAMS3_22_18, 18, 5)
260
+ FIELD(GHWPARAMS3, GHWPARAMS3_17_12, 12, 6)
261
+ FIELD(GHWPARAMS3, GHWPARAMS3_11, 11, 1)
262
+ FIELD(GHWPARAMS3, GHWPARAMS3_10, 10, 1)
263
+ FIELD(GHWPARAMS3, GHWPARAMS3_9_8, 8, 2)
264
+ FIELD(GHWPARAMS3, GHWPARAMS3_7_6, 6, 2)
265
+ FIELD(GHWPARAMS3, GHWPARAMS3_5_4, 4, 2)
266
+ FIELD(GHWPARAMS3, GHWPARAMS3_3_2, 2, 2)
267
+ FIELD(GHWPARAMS3, GHWPARAMS3_1_0, 0, 2)
268
+REG32(GHWPARAMS4, 0x50)
269
+ FIELD(GHWPARAMS4, GHWPARAMS4_31_28, 28, 4)
270
+ FIELD(GHWPARAMS4, GHWPARAMS4_27_24, 24, 4)
271
+ FIELD(GHWPARAMS4, GHWPARAMS4_23, 23, 1)
272
+ FIELD(GHWPARAMS4, GHWPARAMS4_22, 22, 1)
273
+ FIELD(GHWPARAMS4, GHWPARAMS4_21, 21, 1)
274
+ FIELD(GHWPARAMS4, GHWPARAMS4_20_17, 17, 4)
275
+ FIELD(GHWPARAMS4, GHWPARAMS4_16_13, 13, 4)
276
+ FIELD(GHWPARAMS4, GHWPARAMS4_12, 12, 1)
277
+ FIELD(GHWPARAMS4, GHWPARAMS4_11, 11, 1)
278
+ FIELD(GHWPARAMS4, GHWPARAMS4_10_9, 9, 2)
279
+ FIELD(GHWPARAMS4, GHWPARAMS4_8_7, 7, 2)
280
+ FIELD(GHWPARAMS4, GHWPARAMS4_6, 6, 1)
281
+ FIELD(GHWPARAMS4, GHWPARAMS4_5_0, 0, 6)
282
+REG32(GHWPARAMS5, 0x54)
283
+ FIELD(GHWPARAMS5, GHWPARAMS5_31_28, 28, 4)
284
+ FIELD(GHWPARAMS5, GHWPARAMS5_27_22, 22, 6)
285
+ FIELD(GHWPARAMS5, GHWPARAMS5_21_16, 16, 6)
286
+ FIELD(GHWPARAMS5, GHWPARAMS5_15_10, 10, 6)
287
+ FIELD(GHWPARAMS5, GHWPARAMS5_9_4, 4, 6)
288
+ FIELD(GHWPARAMS5, GHWPARAMS5_3_0, 0, 4)
289
+REG32(GHWPARAMS6, 0x58)
290
+ FIELD(GHWPARAMS6, GHWPARAMS6_31_16, 16, 16)
291
+ FIELD(GHWPARAMS6, BUSFLTRSSUPPORT, 15, 1)
292
+ FIELD(GHWPARAMS6, BCSUPPORT, 14, 1)
293
+ FIELD(GHWPARAMS6, OTG_SS_SUPPORT, 13, 1)
294
+ FIELD(GHWPARAMS6, ADPSUPPORT, 12, 1)
295
+ FIELD(GHWPARAMS6, HNPSUPPORT, 11, 1)
296
+ FIELD(GHWPARAMS6, SRPSUPPORT, 10, 1)
297
+ FIELD(GHWPARAMS6, GHWPARAMS6_9_8, 8, 2)
298
+ FIELD(GHWPARAMS6, GHWPARAMS6_7, 7, 1)
299
+ FIELD(GHWPARAMS6, GHWPARAMS6_6, 6, 1)
300
+ FIELD(GHWPARAMS6, GHWPARAMS6_5_0, 0, 6)
301
+REG32(GHWPARAMS7, 0x5c)
302
+ FIELD(GHWPARAMS7, GHWPARAMS7_31_16, 16, 16)
303
+ FIELD(GHWPARAMS7, GHWPARAMS7_15_0, 0, 16)
304
+REG32(GDBGFIFOSPACE, 0x60)
305
+ FIELD(GDBGFIFOSPACE, SPACE_AVAILABLE, 16, 16)
306
+ FIELD(GDBGFIFOSPACE, RESERVED_15_9, 9, 7)
307
+ FIELD(GDBGFIFOSPACE, FIFO_QUEUE_SELECT, 0, 9)
308
+REG32(GUCTL2, 0x9c)
309
+ FIELD(GUCTL2, RESERVED_31_26, 26, 6)
310
+ FIELD(GUCTL2, EN_HP_PM_TIMER, 19, 7)
311
+ FIELD(GUCTL2, NOLOWPWRDUR, 15, 4)
312
+ FIELD(GUCTL2, RST_ACTBITLATER, 14, 1)
313
+ FIELD(GUCTL2, RESERVED_13, 13, 1)
314
+ FIELD(GUCTL2, DISABLECFC, 11, 1)
315
+REG32(GUSB2PHYCFG, 0x100)
316
+ FIELD(GUSB2PHYCFG, U2_FREECLK_EXISTS, 30, 1)
317
+ FIELD(GUSB2PHYCFG, ULPI_LPM_WITH_OPMODE_CHK, 29, 1)
318
+ FIELD(GUSB2PHYCFG, RESERVED_25, 25, 1)
319
+ FIELD(GUSB2PHYCFG, LSTRD, 22, 3)
320
+ FIELD(GUSB2PHYCFG, LSIPD, 19, 3)
321
+ FIELD(GUSB2PHYCFG, ULPIEXTVBUSINDIACTOR, 18, 1)
322
+ FIELD(GUSB2PHYCFG, ULPIEXTVBUSDRV, 17, 1)
323
+ FIELD(GUSB2PHYCFG, RESERVED_16, 16, 1)
324
+ FIELD(GUSB2PHYCFG, ULPIAUTORES, 15, 1)
325
+ FIELD(GUSB2PHYCFG, RESERVED_14, 14, 1)
326
+ FIELD(GUSB2PHYCFG, USBTRDTIM, 10, 4)
327
+ FIELD(GUSB2PHYCFG, XCVRDLY, 9, 1)
328
+ FIELD(GUSB2PHYCFG, ENBLSLPM, 8, 1)
329
+ FIELD(GUSB2PHYCFG, PHYSEL, 7, 1)
330
+ FIELD(GUSB2PHYCFG, SUSPENDUSB20, 6, 1)
331
+ FIELD(GUSB2PHYCFG, FSINTF, 5, 1)
332
+ FIELD(GUSB2PHYCFG, ULPI_UTMI_SEL, 4, 1)
333
+ FIELD(GUSB2PHYCFG, PHYIF, 3, 1)
334
+ FIELD(GUSB2PHYCFG, TOUTCAL, 0, 3)
335
+REG32(GUSB2I2CCTL, 0x140)
336
+REG32(GUSB2PHYACC_ULPI, 0x180)
337
+ FIELD(GUSB2PHYACC_ULPI, RESERVED_31_27, 27, 5)
338
+ FIELD(GUSB2PHYACC_ULPI, DISUIPIDRVR, 26, 1)
339
+ FIELD(GUSB2PHYACC_ULPI, NEWREGREQ, 25, 1)
340
+ FIELD(GUSB2PHYACC_ULPI, VSTSDONE, 24, 1)
341
+ FIELD(GUSB2PHYACC_ULPI, VSTSBSY, 23, 1)
342
+ FIELD(GUSB2PHYACC_ULPI, REGWR, 22, 1)
343
+ FIELD(GUSB2PHYACC_ULPI, REGADDR, 16, 6)
344
+ FIELD(GUSB2PHYACC_ULPI, EXTREGADDR, 8, 8)
345
+ FIELD(GUSB2PHYACC_ULPI, REGDATA, 0, 8)
346
+REG32(GTXFIFOSIZ0, 0x200)
347
+ FIELD(GTXFIFOSIZ0, TXFSTADDR_N, 16, 16)
348
+ FIELD(GTXFIFOSIZ0, TXFDEP_N, 0, 16)
349
+REG32(GTXFIFOSIZ1, 0x204)
350
+ FIELD(GTXFIFOSIZ1, TXFSTADDR_N, 16, 16)
351
+ FIELD(GTXFIFOSIZ1, TXFDEP_N, 0, 16)
352
+REG32(GTXFIFOSIZ2, 0x208)
353
+ FIELD(GTXFIFOSIZ2, TXFSTADDR_N, 16, 16)
354
+ FIELD(GTXFIFOSIZ2, TXFDEP_N, 0, 16)
355
+REG32(GTXFIFOSIZ3, 0x20c)
356
+ FIELD(GTXFIFOSIZ3, TXFSTADDR_N, 16, 16)
357
+ FIELD(GTXFIFOSIZ3, TXFDEP_N, 0, 16)
358
+REG32(GTXFIFOSIZ4, 0x210)
359
+ FIELD(GTXFIFOSIZ4, TXFSTADDR_N, 16, 16)
360
+ FIELD(GTXFIFOSIZ4, TXFDEP_N, 0, 16)
361
+REG32(GTXFIFOSIZ5, 0x214)
362
+ FIELD(GTXFIFOSIZ5, TXFSTADDR_N, 16, 16)
363
+ FIELD(GTXFIFOSIZ5, TXFDEP_N, 0, 16)
364
+REG32(GRXFIFOSIZ0, 0x280)
365
+ FIELD(GRXFIFOSIZ0, RXFSTADDR_N, 16, 16)
366
+ FIELD(GRXFIFOSIZ0, RXFDEP_N, 0, 16)
367
+REG32(GRXFIFOSIZ1, 0x284)
368
+ FIELD(GRXFIFOSIZ1, RXFSTADDR_N, 16, 16)
369
+ FIELD(GRXFIFOSIZ1, RXFDEP_N, 0, 16)
370
+REG32(GRXFIFOSIZ2, 0x288)
371
+ FIELD(GRXFIFOSIZ2, RXFSTADDR_N, 16, 16)
372
+ FIELD(GRXFIFOSIZ2, RXFDEP_N, 0, 16)
373
+REG32(GEVNTADRLO_0, 0x300)
374
+REG32(GEVNTADRHI_0, 0x304)
375
+REG32(GEVNTSIZ_0, 0x308)
376
+ FIELD(GEVNTSIZ_0, EVNTINTRPTMASK, 31, 1)
377
+ FIELD(GEVNTSIZ_0, RESERVED_30_16, 16, 15)
378
+ FIELD(GEVNTSIZ_0, EVENTSIZ, 0, 16)
379
+REG32(GEVNTCOUNT_0, 0x30c)
380
+ FIELD(GEVNTCOUNT_0, EVNT_HANDLER_BUSY, 31, 1)
381
+ FIELD(GEVNTCOUNT_0, RESERVED_30_16, 16, 15)
382
+ FIELD(GEVNTCOUNT_0, EVNTCOUNT, 0, 16)
383
+REG32(GEVNTADRLO_1, 0x310)
384
+REG32(GEVNTADRHI_1, 0x314)
385
+REG32(GEVNTSIZ_1, 0x318)
386
+ FIELD(GEVNTSIZ_1, EVNTINTRPTMASK, 31, 1)
387
+ FIELD(GEVNTSIZ_1, RESERVED_30_16, 16, 15)
388
+ FIELD(GEVNTSIZ_1, EVENTSIZ, 0, 16)
389
+REG32(GEVNTCOUNT_1, 0x31c)
390
+ FIELD(GEVNTCOUNT_1, EVNT_HANDLER_BUSY, 31, 1)
391
+ FIELD(GEVNTCOUNT_1, RESERVED_30_16, 16, 15)
392
+ FIELD(GEVNTCOUNT_1, EVNTCOUNT, 0, 16)
393
+REG32(GEVNTADRLO_2, 0x320)
394
+REG32(GEVNTADRHI_2, 0x324)
395
+REG32(GEVNTSIZ_2, 0x328)
396
+ FIELD(GEVNTSIZ_2, EVNTINTRPTMASK, 31, 1)
397
+ FIELD(GEVNTSIZ_2, RESERVED_30_16, 16, 15)
398
+ FIELD(GEVNTSIZ_2, EVENTSIZ, 0, 16)
399
+REG32(GEVNTCOUNT_2, 0x32c)
400
+ FIELD(GEVNTCOUNT_2, EVNT_HANDLER_BUSY, 31, 1)
401
+ FIELD(GEVNTCOUNT_2, RESERVED_30_16, 16, 15)
402
+ FIELD(GEVNTCOUNT_2, EVNTCOUNT, 0, 16)
403
+REG32(GEVNTADRLO_3, 0x330)
404
+REG32(GEVNTADRHI_3, 0x334)
405
+REG32(GEVNTSIZ_3, 0x338)
406
+ FIELD(GEVNTSIZ_3, EVNTINTRPTMASK, 31, 1)
407
+ FIELD(GEVNTSIZ_3, RESERVED_30_16, 16, 15)
408
+ FIELD(GEVNTSIZ_3, EVENTSIZ, 0, 16)
409
+REG32(GEVNTCOUNT_3, 0x33c)
410
+ FIELD(GEVNTCOUNT_3, EVNT_HANDLER_BUSY, 31, 1)
411
+ FIELD(GEVNTCOUNT_3, RESERVED_30_16, 16, 15)
412
+ FIELD(GEVNTCOUNT_3, EVNTCOUNT, 0, 16)
413
+REG32(GHWPARAMS8, 0x500)
414
+REG32(GTXFIFOPRIDEV, 0x510)
415
+ FIELD(GTXFIFOPRIDEV, RESERVED_31_N, 6, 26)
416
+ FIELD(GTXFIFOPRIDEV, GTXFIFOPRIDEV, 0, 6)
417
+REG32(GTXFIFOPRIHST, 0x518)
418
+ FIELD(GTXFIFOPRIHST, RESERVED_31_16, 3, 29)
419
+ FIELD(GTXFIFOPRIHST, GTXFIFOPRIHST, 0, 3)
420
+REG32(GRXFIFOPRIHST, 0x51c)
421
+ FIELD(GRXFIFOPRIHST, RESERVED_31_16, 3, 29)
422
+ FIELD(GRXFIFOPRIHST, GRXFIFOPRIHST, 0, 3)
423
+REG32(GDMAHLRATIO, 0x524)
424
+ FIELD(GDMAHLRATIO, RESERVED_31_13, 13, 19)
425
+ FIELD(GDMAHLRATIO, HSTRXFIFO, 8, 5)
426
+ FIELD(GDMAHLRATIO, RESERVED_7_5, 5, 3)
427
+ FIELD(GDMAHLRATIO, HSTTXFIFO, 0, 5)
428
+REG32(GFLADJ, 0x530)
429
+ FIELD(GFLADJ, GFLADJ_REFCLK_240MHZDECR_PLS1, 31, 1)
430
+ FIELD(GFLADJ, GFLADJ_REFCLK_240MHZ_DECR, 24, 7)
431
+ FIELD(GFLADJ, GFLADJ_REFCLK_LPM_SEL, 23, 1)
432
+ FIELD(GFLADJ, RESERVED_22, 22, 1)
433
+ FIELD(GFLADJ, GFLADJ_REFCLK_FLADJ, 8, 14)
434
+ FIELD(GFLADJ, GFLADJ_30MHZ_SDBND_SEL, 7, 1)
435
+ FIELD(GFLADJ, GFLADJ_30MHZ, 0, 6)
436
+
437
+#define DWC3_GLOBAL_OFFSET 0xC100
438
+static void reset_csr(USBDWC3 * s)
439
+{
440
+ int i = 0;
441
+ /*
442
+ * We reset all CSR regs except GCTL, GUCTL, GSTS, GSNPSID, GGPIO, GUID,
443
+ * GUSB2PHYCFGn registers and GUSB3PIPECTLn registers. We will skip PHY
444
+ * register as we don't implement them.
445
+ */
446
+ for (i = 0; i < USB_DWC3_R_MAX; i++) {
447
+ switch (i) {
448
+ case R_GCTL:
449
+ break;
450
+ case R_GSTS:
451
+ break;
452
+ case R_GSNPSID:
453
+ break;
454
+ case R_GGPIO:
455
+ break;
456
+ case R_GUID:
457
+ break;
458
+ case R_GUCTL:
459
+ break;
460
+ case R_GHWPARAMS0...R_GHWPARAMS7:
461
+ break;
462
+ case R_GHWPARAMS8:
463
+ break;
464
+ default:
465
+ register_reset(&s->regs_info[i]);
466
+ break;
467
+ }
144
+ }
468
+ }
145
+ r = s->cfg7;
469
+
146
+ break;
470
+ xhci_sysbus_reset(DEVICE(&s->sysbus_xhci));
147
case A_CFGDATA_RTN:
471
+}
148
r = s->cfgdata_rtn;
472
+
149
break;
473
+static void usb_dwc3_gctl_postw(RegisterInfo *reg, uint64_t val64)
150
@@ -XXX,XX +XXX,XX @@ static void mps2_scc_write(void *opaque, hwaddr offset, uint64_t value,
474
+{
151
* we always reflect bit 0 in the 'remap' GPIO output line,
475
+ USBDWC3 *s = USB_DWC3(reg->opaque);
152
* and let the board wire it up or not as it chooses.
476
+
153
* TODO on some boards bit 1 is CPU_WAIT.
477
+ if (ARRAY_FIELD_EX32(s->regs, GCTL, CORESOFTRESET)) {
154
+ *
478
+ reset_csr(s);
155
+ * TODO: on the AN536 this register controls reset and halt
479
+ }
156
+ * for both CPUs. For the moment we don't implement this, so the
480
+}
157
+ * register just reads as written.
481
+
158
*/
482
+static void usb_dwc3_guid_postw(RegisterInfo *reg, uint64_t val64)
159
s->cfg0 = value;
483
+{
160
- qemu_set_irq(s->remap, s->cfg0 & 1);
484
+ USBDWC3 *s = USB_DWC3(reg->opaque);
161
+ if (cfg0_is_remap(s)) {
485
+
162
+ qemu_set_irq(s->remap, s->cfg0 & 1);
486
+ s->regs[R_GUID] = s->cfg.dwc_usb3_user;
163
+ }
487
+}
164
break;
488
+
165
case A_CFG1:
489
+static const RegisterAccessInfo usb_dwc3_regs_info[] = {
166
s->cfg1 = value;
490
+ { .name = "GSBUSCFG0", .addr = A_GSBUSCFG0,
167
- for (size_t i = 0; i < ARRAY_SIZE(s->led); i++) {
491
+ .ro = 0xf300,
168
- led_set_state(s->led[i], extract32(value, i, 1));
492
+ .unimp = 0xffffffff,
169
+ /*
493
+ },{ .name = "GSBUSCFG1", .addr = A_GSBUSCFG1,
170
+ * On most boards this register drives LEDs.
494
+ .reset = 0x300,
171
+ *
495
+ .ro = 0xffffe0ff,
172
+ * TODO: for AN536 this controls whether flash and ATCM are
496
+ .unimp = 0xffffffff,
173
+ * enabled or disabled on reset. QEMU doesn't model this, and
497
+ },{ .name = "GTXTHRCFG", .addr = A_GTXTHRCFG,
174
+ * always wires up RAM in the ATCM area and ROM in the flash area.
498
+ .ro = 0xd000ffff,
175
+ */
499
+ .unimp = 0xffffffff,
176
+ if (cfg1_is_leds(s)) {
500
+ },{ .name = "GRXTHRCFG", .addr = A_GRXTHRCFG,
177
+ for (size_t i = 0; i < ARRAY_SIZE(s->led); i++) {
501
+ .ro = 0xd007e000,
178
+ led_set_state(s->led[i], extract32(value, i, 1));
502
+ .unimp = 0xffffffff,
179
+ }
503
+ },{ .name = "GCTL", .addr = A_GCTL,
180
}
504
+ .reset = 0x30c13004, .post_write = usb_dwc3_gctl_postw,
181
break;
505
+ },{ .name = "GPMSTS", .addr = A_GPMSTS,
182
case A_CFG2:
506
+ .ro = 0xfffffff,
183
if (!have_cfg2(s)) {
507
+ .unimp = 0xffffffff,
184
goto bad_offset;
508
+ },{ .name = "GSTS", .addr = A_GSTS,
185
}
509
+ .reset = 0x7e800000,
186
- /* AN524: QSPI Select signal */
510
+ .ro = 0xffffffcf,
187
+ /* AN524, AN536: QSPI Select signal */
511
+ .w1c = 0x30,
188
s->cfg2 = value;
512
+ .unimp = 0xffffffff,
189
break;
513
+ },{ .name = "GUCTL1", .addr = A_GUCTL1,
190
case A_CFG5:
514
+ .reset = 0x198a,
191
if (!have_cfg5(s)) {
515
+ .ro = 0x7800,
192
goto bad_offset;
516
+ .unimp = 0xffffffff,
193
}
517
+ },{ .name = "GSNPSID", .addr = A_GSNPSID,
194
- /* AN524: ACLK frequency in Hz */
518
+ .reset = 0x5533330a,
195
+ /* AN524, AN536: ACLK frequency in Hz */
519
+ .ro = 0xffffffff,
196
s->cfg5 = value;
520
+ },{ .name = "GGPIO", .addr = A_GGPIO,
197
break;
521
+ .ro = 0xffff,
198
case A_CFG6:
522
+ .unimp = 0xffffffff,
199
@@ -XXX,XX +XXX,XX @@ static void mps2_scc_write(void *opaque, hwaddr offset, uint64_t value,
523
+ },{ .name = "GUID", .addr = A_GUID,
200
goto bad_offset;
524
+ .reset = 0x12345678, .post_write = usb_dwc3_guid_postw,
201
}
525
+ },{ .name = "GUCTL", .addr = A_GUCTL,
202
/* AN524: Clock divider for BRAM */
526
+ .reset = 0x0c808010,
203
+ /* AN536: Core 0 vector table base address */
527
+ .ro = 0x1c8000,
204
+ s->cfg6 = value;
528
+ .unimp = 0xffffffff,
205
+ break;
529
+ },{ .name = "GBUSERRADDRLO", .addr = A_GBUSERRADDRLO,
206
+ case A_CFG7:
530
+ .ro = 0xffffffff,
207
+ if (!have_cfg7(s)) {
531
+ },{ .name = "GBUSERRADDRHI", .addr = A_GBUSERRADDRHI,
208
+ goto bad_offset;
532
+ .ro = 0xffffffff,
209
+ }
533
+ },{ .name = "GHWPARAMS0", .addr = A_GHWPARAMS0,
210
+ /* AN536: Core 1 vector table base address */
534
+ .ro = 0xffffffff,
211
s->cfg6 = value;
535
+ },{ .name = "GHWPARAMS1", .addr = A_GHWPARAMS1,
212
break;
536
+ .ro = 0xffffffff,
213
case A_CFGDATA_OUT:
537
+ },{ .name = "GHWPARAMS2", .addr = A_GHWPARAMS2,
214
@@ -XXX,XX +XXX,XX @@ static void mps2_scc_finalize(Object *obj)
538
+ .ro = 0xffffffff,
215
g_free(s->oscclk_reset);
539
+ },{ .name = "GHWPARAMS3", .addr = A_GHWPARAMS3,
216
}
540
+ .ro = 0xffffffff,
217
541
+ },{ .name = "GHWPARAMS4", .addr = A_GHWPARAMS4,
218
+static bool cfg7_needed(void *opaque)
542
+ .ro = 0xffffffff,
219
+{
543
+ },{ .name = "GHWPARAMS5", .addr = A_GHWPARAMS5,
220
+ MPS2SCC *s = opaque;
544
+ .ro = 0xffffffff,
221
+
545
+ },{ .name = "GHWPARAMS6", .addr = A_GHWPARAMS6,
222
+ return have_cfg7(s);
546
+ .ro = 0xffffffff,
223
+}
547
+ },{ .name = "GHWPARAMS7", .addr = A_GHWPARAMS7,
224
+
548
+ .ro = 0xffffffff,
225
+static const VMStateDescription vmstate_cfg7 = {
549
+ },{ .name = "GDBGFIFOSPACE", .addr = A_GDBGFIFOSPACE,
226
+ .name = "mps2-scc/cfg7",
550
+ .reset = 0xa0000,
551
+ .ro = 0xfffffe00,
552
+ .unimp = 0xffffffff,
553
+ },{ .name = "GUCTL2", .addr = A_GUCTL2,
554
+ .reset = 0x40d,
555
+ .ro = 0x2000,
556
+ .unimp = 0xffffffff,
557
+ },{ .name = "GUSB2PHYCFG", .addr = A_GUSB2PHYCFG,
558
+ .reset = 0x40102410,
559
+ .ro = 0x1e014030,
560
+ .unimp = 0xffffffff,
561
+ },{ .name = "GUSB2I2CCTL", .addr = A_GUSB2I2CCTL,
562
+ .ro = 0xffffffff,
563
+ .unimp = 0xffffffff,
564
+ },{ .name = "GUSB2PHYACC_ULPI", .addr = A_GUSB2PHYACC_ULPI,
565
+ .ro = 0xfd000000,
566
+ .unimp = 0xffffffff,
567
+ },{ .name = "GTXFIFOSIZ0", .addr = A_GTXFIFOSIZ0,
568
+ .reset = 0x2c7000a,
569
+ .unimp = 0xffffffff,
570
+ },{ .name = "GTXFIFOSIZ1", .addr = A_GTXFIFOSIZ1,
571
+ .reset = 0x2d10103,
572
+ .unimp = 0xffffffff,
573
+ },{ .name = "GTXFIFOSIZ2", .addr = A_GTXFIFOSIZ2,
574
+ .reset = 0x3d40103,
575
+ .unimp = 0xffffffff,
576
+ },{ .name = "GTXFIFOSIZ3", .addr = A_GTXFIFOSIZ3,
577
+ .reset = 0x4d70083,
578
+ .unimp = 0xffffffff,
579
+ },{ .name = "GTXFIFOSIZ4", .addr = A_GTXFIFOSIZ4,
580
+ .reset = 0x55a0083,
581
+ .unimp = 0xffffffff,
582
+ },{ .name = "GTXFIFOSIZ5", .addr = A_GTXFIFOSIZ5,
583
+ .reset = 0x5dd0083,
584
+ .unimp = 0xffffffff,
585
+ },{ .name = "GRXFIFOSIZ0", .addr = A_GRXFIFOSIZ0,
586
+ .reset = 0x1c20105,
587
+ .unimp = 0xffffffff,
588
+ },{ .name = "GRXFIFOSIZ1", .addr = A_GRXFIFOSIZ1,
589
+ .reset = 0x2c70000,
590
+ .unimp = 0xffffffff,
591
+ },{ .name = "GRXFIFOSIZ2", .addr = A_GRXFIFOSIZ2,
592
+ .reset = 0x2c70000,
593
+ .unimp = 0xffffffff,
594
+ },{ .name = "GEVNTADRLO_0", .addr = A_GEVNTADRLO_0,
595
+ .unimp = 0xffffffff,
596
+ },{ .name = "GEVNTADRHI_0", .addr = A_GEVNTADRHI_0,
597
+ .unimp = 0xffffffff,
598
+ },{ .name = "GEVNTSIZ_0", .addr = A_GEVNTSIZ_0,
599
+ .ro = 0x7fff0000,
600
+ .unimp = 0xffffffff,
601
+ },{ .name = "GEVNTCOUNT_0", .addr = A_GEVNTCOUNT_0,
602
+ .ro = 0x7fff0000,
603
+ .unimp = 0xffffffff,
604
+ },{ .name = "GEVNTADRLO_1", .addr = A_GEVNTADRLO_1,
605
+ .unimp = 0xffffffff,
606
+ },{ .name = "GEVNTADRHI_1", .addr = A_GEVNTADRHI_1,
607
+ .unimp = 0xffffffff,
608
+ },{ .name = "GEVNTSIZ_1", .addr = A_GEVNTSIZ_1,
609
+ .ro = 0x7fff0000,
610
+ .unimp = 0xffffffff,
611
+ },{ .name = "GEVNTCOUNT_1", .addr = A_GEVNTCOUNT_1,
612
+ .ro = 0x7fff0000,
613
+ .unimp = 0xffffffff,
614
+ },{ .name = "GEVNTADRLO_2", .addr = A_GEVNTADRLO_2,
615
+ .unimp = 0xffffffff,
616
+ },{ .name = "GEVNTADRHI_2", .addr = A_GEVNTADRHI_2,
617
+ .unimp = 0xffffffff,
618
+ },{ .name = "GEVNTSIZ_2", .addr = A_GEVNTSIZ_2,
619
+ .ro = 0x7fff0000,
620
+ .unimp = 0xffffffff,
621
+ },{ .name = "GEVNTCOUNT_2", .addr = A_GEVNTCOUNT_2,
622
+ .ro = 0x7fff0000,
623
+ .unimp = 0xffffffff,
624
+ },{ .name = "GEVNTADRLO_3", .addr = A_GEVNTADRLO_3,
625
+ .unimp = 0xffffffff,
626
+ },{ .name = "GEVNTADRHI_3", .addr = A_GEVNTADRHI_3,
627
+ .unimp = 0xffffffff,
628
+ },{ .name = "GEVNTSIZ_3", .addr = A_GEVNTSIZ_3,
629
+ .ro = 0x7fff0000,
630
+ .unimp = 0xffffffff,
631
+ },{ .name = "GEVNTCOUNT_3", .addr = A_GEVNTCOUNT_3,
632
+ .ro = 0x7fff0000,
633
+ .unimp = 0xffffffff,
634
+ },{ .name = "GHWPARAMS8", .addr = A_GHWPARAMS8,
635
+ .ro = 0xffffffff,
636
+ },{ .name = "GTXFIFOPRIDEV", .addr = A_GTXFIFOPRIDEV,
637
+ .ro = 0xffffffc0,
638
+ .unimp = 0xffffffff,
639
+ },{ .name = "GTXFIFOPRIHST", .addr = A_GTXFIFOPRIHST,
640
+ .ro = 0xfffffff8,
641
+ .unimp = 0xffffffff,
642
+ },{ .name = "GRXFIFOPRIHST", .addr = A_GRXFIFOPRIHST,
643
+ .ro = 0xfffffff8,
644
+ .unimp = 0xffffffff,
645
+ },{ .name = "GDMAHLRATIO", .addr = A_GDMAHLRATIO,
646
+ .ro = 0xffffe0e0,
647
+ .unimp = 0xffffffff,
648
+ },{ .name = "GFLADJ", .addr = A_GFLADJ,
649
+ .reset = 0xc83f020,
650
+ .rsvd = 0x40,
651
+ .ro = 0x400040,
652
+ .unimp = 0xffffffff,
653
+ }
654
+};
655
+
656
+static void usb_dwc3_reset(DeviceState *dev)
657
+{
658
+ USBDWC3 *s = USB_DWC3(dev);
659
+ unsigned int i;
660
+
661
+ for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) {
662
+ switch (i) {
663
+ case R_GHWPARAMS0...R_GHWPARAMS7:
664
+ break;
665
+ case R_GHWPARAMS8:
666
+ break;
667
+ default:
668
+ register_reset(&s->regs_info[i]);
669
+ };
670
+ }
671
+
672
+ xhci_sysbus_reset(DEVICE(&s->sysbus_xhci));
673
+}
674
+
675
+static const MemoryRegionOps usb_dwc3_ops = {
676
+ .read = register_read_memory,
677
+ .write = register_write_memory,
678
+ .endianness = DEVICE_LITTLE_ENDIAN,
679
+ .valid = {
680
+ .min_access_size = 4,
681
+ .max_access_size = 4,
682
+ },
683
+};
684
+
685
+static void usb_dwc3_realize(DeviceState *dev, Error **errp)
686
+{
687
+ USBDWC3 *s = USB_DWC3(dev);
688
+ SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
689
+ Error *err = NULL;
690
+
691
+ sysbus_realize(SYS_BUS_DEVICE(&s->sysbus_xhci), &err);
692
+ if (err) {
693
+ error_propagate(errp, err);
694
+ return;
695
+ }
696
+
697
+ memory_region_add_subregion(&s->iomem, 0,
698
+ sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->sysbus_xhci), 0));
699
+ sysbus_init_mmio(sbd, &s->iomem);
700
+
701
+ /*
702
+ * Device Configuration
703
+ */
704
+ s->regs[R_GHWPARAMS0] = 0x40204048 | s->cfg.mode;
705
+ s->regs[R_GHWPARAMS1] = 0x222493b;
706
+ s->regs[R_GHWPARAMS2] = 0x12345678;
707
+ s->regs[R_GHWPARAMS3] = 0x618c088;
708
+ s->regs[R_GHWPARAMS4] = 0x47822004;
709
+ s->regs[R_GHWPARAMS5] = 0x4202088;
710
+ s->regs[R_GHWPARAMS6] = 0x7850c20;
711
+ s->regs[R_GHWPARAMS7] = 0x0;
712
+ s->regs[R_GHWPARAMS8] = 0x478;
713
+}
714
+
715
+static void usb_dwc3_init(Object *obj)
716
+{
717
+ USBDWC3 *s = USB_DWC3(obj);
718
+ RegisterInfoArray *reg_array;
719
+
720
+ memory_region_init(&s->iomem, obj, TYPE_USB_DWC3, DWC3_SIZE);
721
+ reg_array =
722
+ register_init_block32(DEVICE(obj), usb_dwc3_regs_info,
723
+ ARRAY_SIZE(usb_dwc3_regs_info),
724
+ s->regs_info, s->regs,
725
+ &usb_dwc3_ops,
726
+ USB_DWC3_ERR_DEBUG,
727
+ USB_DWC3_R_MAX * 4);
728
+ memory_region_add_subregion(&s->iomem,
729
+ DWC3_GLOBAL_OFFSET,
730
+ &reg_array->mem);
731
+ object_initialize_child(obj, "dwc3-xhci", &s->sysbus_xhci,
732
+ TYPE_XHCI_SYSBUS);
733
+ qdev_alias_all_properties(DEVICE(&s->sysbus_xhci), obj);
734
+
735
+ s->cfg.mode = HOST_MODE;
736
+}
737
+
738
+static const VMStateDescription vmstate_usb_dwc3 = {
739
+ .name = "usb-dwc3",
740
+ .version_id = 1,
227
+ .version_id = 1,
741
+ .fields = (VMStateField[]) {
228
+ .minimum_version_id = 1,
742
+ VMSTATE_UINT32_ARRAY(regs, USBDWC3, USB_DWC3_R_MAX),
229
+ .needed = cfg7_needed,
743
+ VMSTATE_UINT8(cfg.mode, USBDWC3),
230
+ .fields = (const VMStateField[]) {
744
+ VMSTATE_UINT32(cfg.dwc_usb3_user, USBDWC3),
231
+ VMSTATE_UINT32(cfg7, MPS2SCC),
745
+ VMSTATE_END_OF_LIST()
232
+ VMSTATE_END_OF_LIST()
746
+ }
233
+ }
747
+};
234
+};
748
+
235
+
749
+static Property usb_dwc3_properties[] = {
236
static const VMStateDescription mps2_scc_vmstate = {
750
+ DEFINE_PROP_UINT32("DWC_USB3_USERID", USBDWC3, cfg.dwc_usb3_user,
237
.name = "mps2-scc",
751
+ 0x12345678),
238
.version_id = 3,
752
+ DEFINE_PROP_END_OF_LIST(),
239
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription mps2_scc_vmstate = {
753
+};
240
VMSTATE_VARRAY_UINT32(oscclk, MPS2SCC, num_oscclk,
754
+
241
0, vmstate_info_uint32, uint32_t),
755
+static void usb_dwc3_class_init(ObjectClass *klass, void *data)
242
VMSTATE_END_OF_LIST()
756
+{
243
+ },
757
+ DeviceClass *dc = DEVICE_CLASS(klass);
244
+ .subsections = (const VMStateDescription * const []) {
758
+
245
+ &vmstate_cfg7,
759
+ dc->reset = usb_dwc3_reset;
246
+ NULL
760
+ dc->realize = usb_dwc3_realize;
247
}
761
+ dc->vmsd = &vmstate_usb_dwc3;
248
};
762
+ device_class_set_props(dc, usb_dwc3_properties);
249
763
+}
764
+
765
+static const TypeInfo usb_dwc3_info = {
766
+ .name = TYPE_USB_DWC3,
767
+ .parent = TYPE_SYS_BUS_DEVICE,
768
+ .instance_size = sizeof(USBDWC3),
769
+ .class_init = usb_dwc3_class_init,
770
+ .instance_init = usb_dwc3_init,
771
+};
772
+
773
+static void usb_dwc3_register_types(void)
774
+{
775
+ type_register_static(&usb_dwc3_info);
776
+}
777
+
778
+type_init(usb_dwc3_register_types)
779
diff --git a/hw/usb/Kconfig b/hw/usb/Kconfig
780
index XXXXXXX..XXXXXXX 100644
781
--- a/hw/usb/Kconfig
782
+++ b/hw/usb/Kconfig
783
@@ -XXX,XX +XXX,XX @@ config IMX_USBPHY
784
bool
785
default y
786
depends on USB
787
+
788
+config USB_DWC3
789
+ bool
790
+ select USB_XHCI_SYSBUS
791
+ select REGISTER
792
diff --git a/hw/usb/meson.build b/hw/usb/meson.build
793
index XXXXXXX..XXXXXXX 100644
794
--- a/hw/usb/meson.build
795
+++ b/hw/usb/meson.build
796
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_USB_XHCI_SYSBUS', if_true: files('hcd-xhci-sysbus.c
797
softmmu_ss.add(when: 'CONFIG_USB_XHCI_NEC', if_true: files('hcd-xhci-nec.c'))
798
softmmu_ss.add(when: 'CONFIG_USB_MUSB', if_true: files('hcd-musb.c'))
799
softmmu_ss.add(when: 'CONFIG_USB_DWC2', if_true: files('hcd-dwc2.c'))
800
+softmmu_ss.add(when: 'CONFIG_USB_DWC3', if_true: files('hcd-dwc3.c'))
801
802
softmmu_ss.add(when: 'CONFIG_TUSB6010', if_true: files('tusb6010.c'))
803
softmmu_ss.add(when: 'CONFIG_IMX', if_true: files('chipidea.c'))
804
--
250
--
805
2.20.1
251
2.34.1
806
252
807
253
diff view generated by jsdifflib
[PULL 12/20] usb: Add versal-usb2-ctrl-regs module
[PULL 30/35] hw/arm/mps3r: Initial skeleton for mps3-an536 board
1
From: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
1
The AN536 is another FPGA image for the MPS3 development board. Unlike
2
2
the existing FPGA images we already model, this board uses a Cortex-R
3
This module emulates control registers of versal usb2 controller, this is added
3
family CPU, and it does not use any equivalent to the M-profile
4
just to make guest happy. In general this module would control the phy-reset
4
"Subsystem for Embedded" SoC-equivalent that we model in hw/arm/armsse.c.
5
signal from usb controller, data coherency of the transactions, signals
5
It's therefore more convenient for us to model it as a completely
6
the host system errors received from controller.
6
separate C file.
7
7
8
Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
8
This commit adds the basic skeleton of the board model, and the
9
Signed-off-by: Vikram Garhwal <fnu.vikram@xilinx.com>
9
code to create all the RAM and ROM. We assume that we're probably
10
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
10
going to want to add more images in future, so use the same
11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
base class/subclass setup that mps2-tz.c uses, even though at
12
Message-id: 1607023357-5096-2-git-send-email-sai.pavan.boddu@xilinx.com
12
the moment there's only a single subclass.
13
14
Following commits will add the CPUs and the peripherals.
15
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
18
Message-id: 20240206132931.38376-9-peter.maydell@linaro.org
14
---
19
---
15
include/hw/usb/xlnx-versal-usb2-ctrl-regs.h | 45 ++++
20
MAINTAINERS | 3 +-
16
hw/usb/xlnx-versal-usb2-ctrl-regs.c | 229 ++++++++++++++++++++
21
configs/devices/arm-softmmu/default.mak | 1 +
17
hw/usb/meson.build | 1 +
22
hw/arm/mps3r.c | 239 ++++++++++++++++++++++++
18
3 files changed, 275 insertions(+)
23
hw/arm/Kconfig | 5 +
19
create mode 100644 include/hw/usb/xlnx-versal-usb2-ctrl-regs.h
24
hw/arm/meson.build | 1 +
20
create mode 100644 hw/usb/xlnx-versal-usb2-ctrl-regs.c
25
5 files changed, 248 insertions(+), 1 deletion(-)
21
26
create mode 100644 hw/arm/mps3r.c
22
diff --git a/include/hw/usb/xlnx-versal-usb2-ctrl-regs.h b/include/hw/usb/xlnx-versal-usb2-ctrl-regs.h
27
28
diff --git a/MAINTAINERS b/MAINTAINERS
29
index XXXXXXX..XXXXXXX 100644
30
--- a/MAINTAINERS
31
+++ b/MAINTAINERS
32
@@ -XXX,XX +XXX,XX @@ F: include/hw/misc/imx7_*.h
33
F: hw/pci-host/designware.c
34
F: include/hw/pci-host/designware.h
35
36
-MPS2
37
+MPS2 / MPS3
38
M: Peter Maydell <peter.maydell@linaro.org>
39
L: qemu-arm@nongnu.org
40
S: Maintained
41
F: hw/arm/mps2.c
42
F: hw/arm/mps2-tz.c
43
+F: hw/arm/mps3r.c
44
F: hw/misc/mps2-*.c
45
F: include/hw/misc/mps2-*.h
46
F: hw/arm/armsse.c
47
diff --git a/configs/devices/arm-softmmu/default.mak b/configs/devices/arm-softmmu/default.mak
48
index XXXXXXX..XXXXXXX 100644
49
--- a/configs/devices/arm-softmmu/default.mak
50
+++ b/configs/devices/arm-softmmu/default.mak
51
@@ -XXX,XX +XXX,XX @@ CONFIG_ARM_VIRT=y
52
# CONFIG_INTEGRATOR=n
53
# CONFIG_FSL_IMX31=n
54
# CONFIG_MUSICPAL=n
55
+# CONFIG_MPS3R=n
56
# CONFIG_MUSCA=n
57
# CONFIG_CHEETAH=n
58
# CONFIG_SX1=n
59
diff --git a/hw/arm/mps3r.c b/hw/arm/mps3r.c
23
new file mode 100644
60
new file mode 100644
24
index XXXXXXX..XXXXXXX
61
index XXXXXXX..XXXXXXX
25
--- /dev/null
62
--- /dev/null
26
+++ b/include/hw/usb/xlnx-versal-usb2-ctrl-regs.h
63
+++ b/hw/arm/mps3r.c
27
@@ -XXX,XX +XXX,XX @@
64
@@ -XXX,XX +XXX,XX @@
28
+/*
65
+/*
29
+ * QEMU model of the VersalUsb2CtrlRegs Register control/Status block for
66
+ * Arm MPS3 board emulation for Cortex-R-based FPGA images.
30
+ * USB2.0 controller
67
+ * (For M-profile images see mps2.c and mps2tz.c.)
31
+ *
68
+ *
32
+ * Copyright (c) 2020 Xilinx Inc. Vikram Garhwal <fnu.vikram@xilinx.com>
69
+ * Copyright (c) 2017 Linaro Limited
70
+ * Written by Peter Maydell
33
+ *
71
+ *
34
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
72
+ * This program is free software; you can redistribute it and/or modify
35
+ * of this software and associated documentation files (the "Software"), to deal
73
+ * it under the terms of the GNU General Public License version 2 or
36
+ * in the Software without restriction, including without limitation the rights
74
+ * (at your option) any later version.
37
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
75
+ */
38
+ * copies of the Software, and to permit persons to whom the Software is
76
+
39
+ * furnished to do so, subject to the following conditions:
77
+/*
78
+ * The MPS3 is an FPGA based dev board. This file handles FPGA images
79
+ * which use the Cortex-R CPUs. We model these separately from the
80
+ * M-profile images, because on M-profile the FPGA image is based on
81
+ * a "Subsystem for Embedded" which is similar to an SoC, whereas
82
+ * the R-profile FPGA images don't have that abstraction layer.
40
+ *
83
+ *
41
+ * The above copyright notice and this permission notice shall be included in
84
+ * We model the following FPGA images here:
42
+ * all copies or substantial portions of the Software.
85
+ * "mps3-an536" -- dual Cortex-R52 as documented in Arm Application Note AN536
43
+ *
86
+ *
44
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
87
+ * Application Note AN536:
45
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
88
+ * https://developer.arm.com/documentation/dai0536/latest/
46
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
47
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
48
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
49
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
50
+ * THE SOFTWARE.
51
+ */
89
+ */
52
+
90
+
53
+#ifndef _XLNX_USB2_REGS_H_
91
+#include "qemu/osdep.h"
54
+#define _XLNX_USB2_REGS_H_
92
+#include "qemu/units.h"
55
+
93
+#include "qapi/error.h"
56
+#define TYPE_XILINX_VERSAL_USB2_CTRL_REGS "xlnx.versal-usb2-ctrl-regs"
94
+#include "exec/address-spaces.h"
57
+
95
+#include "cpu.h"
58
+#define XILINX_VERSAL_USB2_CTRL_REGS(obj) \
96
+#include "hw/boards.h"
59
+ OBJECT_CHECK(VersalUsb2CtrlRegs, (obj), TYPE_XILINX_VERSAL_USB2_CTRL_REGS)
97
+#include "hw/arm/boot.h"
60
+
98
+
61
+#define USB2_REGS_R_MAX ((0x78 / 4) + 1)
99
+/* Define the layout of RAM and ROM in a board */
62
+
100
+typedef struct RAMInfo {
63
+typedef struct VersalUsb2CtrlRegs {
101
+ const char *name;
64
+ SysBusDevice parent_obj;
102
+ hwaddr base;
65
+ MemoryRegion iomem;
103
+ hwaddr size;
66
+ qemu_irq irq_ir;
104
+ int mrindex; /* index into rams[]; -1 for the system RAM block */
67
+
105
+ int flags;
68
+ uint32_t regs[USB2_REGS_R_MAX];
106
+} RAMInfo;
69
+ RegisterInfo regs_info[USB2_REGS_R_MAX];
107
+
70
+} VersalUsb2CtrlRegs;
108
+/*
71
+
109
+ * The MPS3 DDR is 3GiB, but on a 32-bit host QEMU doesn't permit
110
+ * emulation of that much guest RAM, so artificially make it smaller.
111
+ */
112
+#if HOST_LONG_BITS == 32
113
+#define MPS3_DDR_SIZE (1 * GiB)
114
+#else
115
+#define MPS3_DDR_SIZE (3 * GiB)
72
+#endif
116
+#endif
73
diff --git a/hw/usb/xlnx-versal-usb2-ctrl-regs.c b/hw/usb/xlnx-versal-usb2-ctrl-regs.c
117
+
74
new file mode 100644
75
index XXXXXXX..XXXXXXX
76
--- /dev/null
77
+++ b/hw/usb/xlnx-versal-usb2-ctrl-regs.c
78
@@ -XXX,XX +XXX,XX @@
79
+/*
118
+/*
80
+ * QEMU model of the VersalUsb2CtrlRegs Register control/Status block for
119
+ * Flag values:
81
+ * USB2.0 controller
120
+ * IS_MAIN: this is the main machine RAM
82
+ *
121
+ * IS_ROM: this area is read-only
83
+ * This module should control phy_reset, permanent device plugs, frame length
84
+ * time adjust & setting of coherency paths. None of which are emulated in
85
+ * present model.
86
+ *
87
+ * Copyright (c) 2020 Xilinx Inc. Vikram Garhwal <fnu.vikram@xilinx.com>
88
+ *
89
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
90
+ * of this software and associated documentation files (the "Software"), to deal
91
+ * in the Software without restriction, including without limitation the rights
92
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
93
+ * copies of the Software, and to permit persons to whom the Software is
94
+ * furnished to do so, subject to the following conditions:
95
+ *
96
+ * The above copyright notice and this permission notice shall be included in
97
+ * all copies or substantial portions of the Software.
98
+ *
99
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
100
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
101
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
102
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
103
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
104
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
105
+ * THE SOFTWARE.
106
+ */
122
+ */
107
+
123
+#define IS_MAIN 1
108
+#include "qemu/osdep.h"
124
+#define IS_ROM 2
109
+#include "hw/sysbus.h"
125
+
110
+#include "hw/irq.h"
126
+#define MPS3R_RAM_MAX 9
111
+#include "hw/register.h"
127
+
112
+#include "qemu/bitops.h"
128
+typedef enum MPS3RFPGAType {
113
+#include "qemu/log.h"
129
+ FPGA_AN536,
114
+#include "qom/object.h"
130
+} MPS3RFPGAType;
115
+#include "migration/vmstate.h"
131
+
116
+#include "hw/usb/xlnx-versal-usb2-ctrl-regs.h"
132
+struct MPS3RMachineClass {
117
+
133
+ MachineClass parent;
118
+#ifndef XILINX_VERSAL_USB2_CTRL_REGS_ERR_DEBUG
134
+ MPS3RFPGAType fpga_type;
119
+#define XILINX_VERSAL_USB2_CTRL_REGS_ERR_DEBUG 0
135
+ const RAMInfo *raminfo;
120
+#endif
136
+};
121
+
137
+
122
+REG32(BUS_FILTER, 0x30)
138
+struct MPS3RMachineState {
123
+ FIELD(BUS_FILTER, BYPASS, 0, 4)
139
+ MachineState parent;
124
+REG32(PORT, 0x34)
140
+ MemoryRegion ram[MPS3R_RAM_MAX];
125
+ FIELD(PORT, HOST_SMI_BAR_WR, 4, 1)
141
+};
126
+ FIELD(PORT, HOST_SMI_PCI_CMD_REG_WR, 3, 1)
142
+
127
+ FIELD(PORT, HOST_MSI_ENABLE, 2, 1)
143
+#define TYPE_MPS3R_MACHINE "mps3r"
128
+ FIELD(PORT, PWR_CTRL_PRSNT, 1, 1)
144
+#define TYPE_MPS3R_AN536_MACHINE MACHINE_TYPE_NAME("mps3-an536")
129
+ FIELD(PORT, HUB_PERM_ATTACH, 0, 1)
145
+
130
+REG32(JITTER_ADJUST, 0x38)
146
+OBJECT_DECLARE_TYPE(MPS3RMachineState, MPS3RMachineClass, MPS3R_MACHINE)
131
+ FIELD(JITTER_ADJUST, FLADJ, 0, 6)
147
+
132
+REG32(BIGENDIAN, 0x40)
148
+static const RAMInfo an536_raminfo[] = {
133
+ FIELD(BIGENDIAN, ENDIAN_GS, 0, 1)
149
+ {
134
+REG32(COHERENCY, 0x44)
150
+ .name = "ATCM",
135
+ FIELD(COHERENCY, USB_COHERENCY, 0, 1)
151
+ .base = 0x00000000,
136
+REG32(XHC_BME, 0x48)
152
+ .size = 0x00008000,
137
+ FIELD(XHC_BME, XHC_BME, 0, 1)
153
+ .mrindex = 0,
138
+REG32(REG_CTRL, 0x60)
154
+ }, {
139
+ FIELD(REG_CTRL, SLVERR_ENABLE, 0, 1)
155
+ /* We model the QSPI flash as simple ROM for now */
140
+REG32(IR_STATUS, 0x64)
156
+ .name = "QSPI",
141
+ FIELD(IR_STATUS, HOST_SYS_ERR, 1, 1)
157
+ .base = 0x08000000,
142
+ FIELD(IR_STATUS, ADDR_DEC_ERR, 0, 1)
158
+ .size = 0x00800000,
143
+REG32(IR_MASK, 0x68)
159
+ .flags = IS_ROM,
144
+ FIELD(IR_MASK, HOST_SYS_ERR, 1, 1)
160
+ .mrindex = 1,
145
+ FIELD(IR_MASK, ADDR_DEC_ERR, 0, 1)
161
+ }, {
146
+REG32(IR_ENABLE, 0x6c)
162
+ .name = "BRAM",
147
+ FIELD(IR_ENABLE, HOST_SYS_ERR, 1, 1)
163
+ .base = 0x10000000,
148
+ FIELD(IR_ENABLE, ADDR_DEC_ERR, 0, 1)
164
+ .size = 0x00080000,
149
+REG32(IR_DISABLE, 0x70)
165
+ .mrindex = 2,
150
+ FIELD(IR_DISABLE, HOST_SYS_ERR, 1, 1)
166
+ }, {
151
+ FIELD(IR_DISABLE, ADDR_DEC_ERR, 0, 1)
167
+ .name = "DDR",
152
+REG32(USB3, 0x78)
168
+ .base = 0x20000000,
153
+
169
+ .size = MPS3_DDR_SIZE,
154
+static void ir_update_irq(VersalUsb2CtrlRegs *s)
170
+ .mrindex = -1,
155
+{
171
+ }, {
156
+ bool pending = s->regs[R_IR_STATUS] & ~s->regs[R_IR_MASK];
172
+ .name = "ATCM0",
157
+ qemu_set_irq(s->irq_ir, pending);
173
+ .base = 0xee000000,
158
+}
174
+ .size = 0x00008000,
159
+
175
+ .mrindex = 3,
160
+static void ir_status_postw(RegisterInfo *reg, uint64_t val64)
176
+ }, {
161
+{
177
+ .name = "BTCM0",
162
+ VersalUsb2CtrlRegs *s = XILINX_VERSAL_USB2_CTRL_REGS(reg->opaque);
178
+ .base = 0xee100000,
179
+ .size = 0x00008000,
180
+ .mrindex = 4,
181
+ }, {
182
+ .name = "CTCM0",
183
+ .base = 0xee200000,
184
+ .size = 0x00008000,
185
+ .mrindex = 5,
186
+ }, {
187
+ .name = "ATCM1",
188
+ .base = 0xee400000,
189
+ .size = 0x00008000,
190
+ .mrindex = 6,
191
+ }, {
192
+ .name = "BTCM1",
193
+ .base = 0xee500000,
194
+ .size = 0x00008000,
195
+ .mrindex = 7,
196
+ }, {
197
+ .name = "CTCM1",
198
+ .base = 0xee600000,
199
+ .size = 0x00008000,
200
+ .mrindex = 8,
201
+ }, {
202
+ .name = NULL,
203
+ }
204
+};
205
+
206
+static MemoryRegion *mr_for_raminfo(MPS3RMachineState *mms,
207
+ const RAMInfo *raminfo)
208
+{
209
+ /* Return an initialized MemoryRegion for the RAMInfo. */
210
+ MemoryRegion *ram;
211
+
212
+ if (raminfo->mrindex < 0) {
213
+ /* Means this RAMInfo is for QEMU's "system memory" */
214
+ MachineState *machine = MACHINE(mms);
215
+ assert(!(raminfo->flags & IS_ROM));
216
+ return machine->ram;
217
+ }
218
+
219
+ assert(raminfo->mrindex < MPS3R_RAM_MAX);
220
+ ram = &mms->ram[raminfo->mrindex];
221
+
222
+ memory_region_init_ram(ram, NULL, raminfo->name,
223
+ raminfo->size, &error_fatal);
224
+ if (raminfo->flags & IS_ROM) {
225
+ memory_region_set_readonly(ram, true);
226
+ }
227
+ return ram;
228
+}
229
+
230
+static void mps3r_common_init(MachineState *machine)
231
+{
232
+ MPS3RMachineState *mms = MPS3R_MACHINE(machine);
233
+ MPS3RMachineClass *mmc = MPS3R_MACHINE_GET_CLASS(mms);
234
+ MemoryRegion *sysmem = get_system_memory();
235
+
236
+ for (const RAMInfo *ri = mmc->raminfo; ri->name; ri++) {
237
+ MemoryRegion *mr = mr_for_raminfo(mms, ri);
238
+ memory_region_add_subregion(sysmem, ri->base, mr);
239
+ }
240
+}
241
+
242
+static void mps3r_set_default_ram_info(MPS3RMachineClass *mmc)
243
+{
163
+ /*
244
+ /*
164
+ * TODO: This should also clear USBSTS.HSE field in USB XHCI register.
245
+ * Set mc->default_ram_size and default_ram_id from the
165
+ * May be combine both the modules.
246
+ * information in mmc->raminfo.
166
+ */
247
+ */
167
+ ir_update_irq(s);
248
+ MachineClass *mc = MACHINE_CLASS(mmc);
168
+}
249
+ const RAMInfo *p;
169
+
250
+
170
+static uint64_t ir_enable_prew(RegisterInfo *reg, uint64_t val64)
251
+ for (p = mmc->raminfo; p->name; p++) {
171
+{
252
+ if (p->mrindex < 0) {
172
+ VersalUsb2CtrlRegs *s = XILINX_VERSAL_USB2_CTRL_REGS(reg->opaque);
253
+ /* Found the entry for "system memory" */
173
+ uint32_t val = val64;
254
+ mc->default_ram_size = p->size;
174
+
255
+ mc->default_ram_id = p->name;
175
+ s->regs[R_IR_MASK] &= ~val;
256
+ return;
176
+ ir_update_irq(s);
257
+ }
177
+ return 0;
258
+ }
178
+}
259
+ g_assert_not_reached();
179
+
260
+}
180
+static uint64_t ir_disable_prew(RegisterInfo *reg, uint64_t val64)
261
+
181
+{
262
+static void mps3r_class_init(ObjectClass *oc, void *data)
182
+ VersalUsb2CtrlRegs *s = XILINX_VERSAL_USB2_CTRL_REGS(reg->opaque);
263
+{
183
+ uint32_t val = val64;
264
+ MachineClass *mc = MACHINE_CLASS(oc);
184
+
265
+
185
+ s->regs[R_IR_MASK] |= val;
266
+ mc->init = mps3r_common_init;
186
+ ir_update_irq(s);
267
+}
187
+ return 0;
268
+
188
+}
269
+static void mps3r_an536_class_init(ObjectClass *oc, void *data)
189
+
270
+{
190
+static const RegisterAccessInfo usb2_ctrl_regs_regs_info[] = {
271
+ MachineClass *mc = MACHINE_CLASS(oc);
191
+ { .name = "BUS_FILTER", .addr = A_BUS_FILTER,
272
+ MPS3RMachineClass *mmc = MPS3R_MACHINE_CLASS(oc);
192
+ .rsvd = 0xfffffff0,
273
+ static const char * const valid_cpu_types[] = {
193
+ },{ .name = "PORT", .addr = A_PORT,
274
+ ARM_CPU_TYPE_NAME("cortex-r52"),
194
+ .rsvd = 0xffffffe0,
275
+ NULL
195
+ },{ .name = "JITTER_ADJUST", .addr = A_JITTER_ADJUST,
276
+ };
196
+ .reset = 0x20,
277
+
197
+ .rsvd = 0xffffffc0,
278
+ mc->desc = "ARM MPS3 with AN536 FPGA image for Cortex-R52";
198
+ },{ .name = "BIGENDIAN", .addr = A_BIGENDIAN,
279
+ mc->default_cpus = 2;
199
+ .rsvd = 0xfffffffe,
280
+ mc->min_cpus = mc->default_cpus;
200
+ },{ .name = "COHERENCY", .addr = A_COHERENCY,
281
+ mc->max_cpus = mc->default_cpus;
201
+ .rsvd = 0xfffffffe,
282
+ mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-r52");
202
+ },{ .name = "XHC_BME", .addr = A_XHC_BME,
283
+ mc->valid_cpu_types = valid_cpu_types;
203
+ .reset = 0x1,
284
+ mmc->raminfo = an536_raminfo;
204
+ .rsvd = 0xfffffffe,
285
+ mps3r_set_default_ram_info(mmc);
205
+ },{ .name = "REG_CTRL", .addr = A_REG_CTRL,
286
+}
206
+ .rsvd = 0xfffffffe,
287
+
207
+ },{ .name = "IR_STATUS", .addr = A_IR_STATUS,
288
+static const TypeInfo mps3r_machine_types[] = {
208
+ .rsvd = 0xfffffffc,
289
+ {
209
+ .w1c = 0x3,
290
+ .name = TYPE_MPS3R_MACHINE,
210
+ .post_write = ir_status_postw,
291
+ .parent = TYPE_MACHINE,
211
+ },{ .name = "IR_MASK", .addr = A_IR_MASK,
292
+ .abstract = true,
212
+ .reset = 0x3,
293
+ .instance_size = sizeof(MPS3RMachineState),
213
+ .rsvd = 0xfffffffc,
294
+ .class_size = sizeof(MPS3RMachineClass),
214
+ .ro = 0x3,
295
+ .class_init = mps3r_class_init,
215
+ },{ .name = "IR_ENABLE", .addr = A_IR_ENABLE,
296
+ }, {
216
+ .rsvd = 0xfffffffc,
297
+ .name = TYPE_MPS3R_AN536_MACHINE,
217
+ .pre_write = ir_enable_prew,
298
+ .parent = TYPE_MPS3R_MACHINE,
218
+ },{ .name = "IR_DISABLE", .addr = A_IR_DISABLE,
299
+ .class_init = mps3r_an536_class_init,
219
+ .rsvd = 0xfffffffc,
220
+ .pre_write = ir_disable_prew,
221
+ },{ .name = "USB3", .addr = A_USB3,
222
+ }
223
+};
224
+
225
+static void usb2_ctrl_regs_reset_init(Object *obj, ResetType type)
226
+{
227
+ VersalUsb2CtrlRegs *s = XILINX_VERSAL_USB2_CTRL_REGS(obj);
228
+ unsigned int i;
229
+
230
+ for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) {
231
+ register_reset(&s->regs_info[i]);
232
+ }
233
+}
234
+
235
+static void usb2_ctrl_regs_reset_hold(Object *obj)
236
+{
237
+ VersalUsb2CtrlRegs *s = XILINX_VERSAL_USB2_CTRL_REGS(obj);
238
+
239
+ ir_update_irq(s);
240
+}
241
+
242
+static const MemoryRegionOps usb2_ctrl_regs_ops = {
243
+ .read = register_read_memory,
244
+ .write = register_write_memory,
245
+ .endianness = DEVICE_LITTLE_ENDIAN,
246
+ .valid = {
247
+ .min_access_size = 4,
248
+ .max_access_size = 4,
249
+ },
300
+ },
250
+};
301
+};
251
+
302
+
252
+static void usb2_ctrl_regs_init(Object *obj)
303
+DEFINE_TYPES(mps3r_machine_types);
253
+{
304
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
254
+ VersalUsb2CtrlRegs *s = XILINX_VERSAL_USB2_CTRL_REGS(obj);
255
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
256
+ RegisterInfoArray *reg_array;
257
+
258
+ memory_region_init(&s->iomem, obj, TYPE_XILINX_VERSAL_USB2_CTRL_REGS,
259
+ USB2_REGS_R_MAX * 4);
260
+ reg_array =
261
+ register_init_block32(DEVICE(obj), usb2_ctrl_regs_regs_info,
262
+ ARRAY_SIZE(usb2_ctrl_regs_regs_info),
263
+ s->regs_info, s->regs,
264
+ &usb2_ctrl_regs_ops,
265
+ XILINX_VERSAL_USB2_CTRL_REGS_ERR_DEBUG,
266
+ USB2_REGS_R_MAX * 4);
267
+ memory_region_add_subregion(&s->iomem,
268
+ 0x0,
269
+ &reg_array->mem);
270
+ sysbus_init_mmio(sbd, &s->iomem);
271
+ sysbus_init_irq(sbd, &s->irq_ir);
272
+}
273
+
274
+static const VMStateDescription vmstate_usb2_ctrl_regs = {
275
+ .name = TYPE_XILINX_VERSAL_USB2_CTRL_REGS,
276
+ .version_id = 1,
277
+ .minimum_version_id = 1,
278
+ .fields = (VMStateField[]) {
279
+ VMSTATE_UINT32_ARRAY(regs, VersalUsb2CtrlRegs, USB2_REGS_R_MAX),
280
+ VMSTATE_END_OF_LIST(),
281
+ }
282
+};
283
+
284
+static void usb2_ctrl_regs_class_init(ObjectClass *klass, void *data)
285
+{
286
+ DeviceClass *dc = DEVICE_CLASS(klass);
287
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
288
+
289
+ rc->phases.enter = usb2_ctrl_regs_reset_init;
290
+ rc->phases.hold = usb2_ctrl_regs_reset_hold;
291
+ dc->vmsd = &vmstate_usb2_ctrl_regs;
292
+}
293
+
294
+static const TypeInfo usb2_ctrl_regs_info = {
295
+ .name = TYPE_XILINX_VERSAL_USB2_CTRL_REGS,
296
+ .parent = TYPE_SYS_BUS_DEVICE,
297
+ .instance_size = sizeof(VersalUsb2CtrlRegs),
298
+ .class_init = usb2_ctrl_regs_class_init,
299
+ .instance_init = usb2_ctrl_regs_init,
300
+};
301
+
302
+static void usb2_ctrl_regs_register_types(void)
303
+{
304
+ type_register_static(&usb2_ctrl_regs_info);
305
+}
306
+
307
+type_init(usb2_ctrl_regs_register_types)
308
diff --git a/hw/usb/meson.build b/hw/usb/meson.build
309
index XXXXXXX..XXXXXXX 100644
305
index XXXXXXX..XXXXXXX 100644
310
--- a/hw/usb/meson.build
306
--- a/hw/arm/Kconfig
311
+++ b/hw/usb/meson.build
307
+++ b/hw/arm/Kconfig
312
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_USB_DWC2', if_true: files('hcd-dwc2.c'))
308
@@ -XXX,XX +XXX,XX @@ config MAINSTONE
313
softmmu_ss.add(when: 'CONFIG_TUSB6010', if_true: files('tusb6010.c'))
309
select PFLASH_CFI01
314
softmmu_ss.add(when: 'CONFIG_IMX', if_true: files('chipidea.c'))
310
select SMC91C111
315
softmmu_ss.add(when: 'CONFIG_IMX_USBPHY', if_true: files('imx-usb-phy.c'))
311
316
+specific_ss.add(when: 'CONFIG_XLNX_VERSAL', if_true: files('xlnx-versal-usb2-ctrl-regs.c'))
312
+config MPS3R
317
313
+ bool
318
# emulated usb devices
314
+ default y
319
softmmu_ss.add(when: 'CONFIG_USB', if_true: files('dev-hub.c'))
315
+ depends on TCG && ARM
316
+
317
config MUSCA
318
bool
319
default y
320
diff --git a/hw/arm/meson.build b/hw/arm/meson.build
321
index XXXXXXX..XXXXXXX 100644
322
--- a/hw/arm/meson.build
323
+++ b/hw/arm/meson.build
324
@@ -XXX,XX +XXX,XX @@ arm_ss.add(when: 'CONFIG_HIGHBANK', if_true: files('highbank.c'))
325
arm_ss.add(when: 'CONFIG_INTEGRATOR', if_true: files('integratorcp.c'))
326
arm_ss.add(when: 'CONFIG_MAINSTONE', if_true: files('mainstone.c'))
327
arm_ss.add(when: 'CONFIG_MICROBIT', if_true: files('microbit.c'))
328
+arm_ss.add(when: 'CONFIG_MPS3R', if_true: files('mps3r.c'))
329
arm_ss.add(when: 'CONFIG_MUSICPAL', if_true: files('musicpal.c'))
330
arm_ss.add(when: 'CONFIG_NETDUINOPLUS2', if_true: files('netduinoplus2.c'))
331
arm_ss.add(when: 'CONFIG_OLIMEX_STM32_H405', if_true: files('olimex-stm32-h405.c'))
320
--
332
--
321
2.20.1
333
2.34.1
322
334
323
335
diff view generated by jsdifflib
[PULL 06/20] target/nios2: Move nios2_check_interrupts() into target/nios2
[PULL 31/35] hw/arm/mps3r: Add CPUs, GIC, and per-CPU RAM
1
The function nios2_check_interrupts)() looks only at CPU-internal
1
Create the CPUs, the GIC, and the per-CPU RAM block for
2
state; it belongs in target/nios2, not hw/nios2. Move it into the
2
the mps3-an536 board.
3
same file as its only caller, so it can just be local to that file.
4
5
This removes the only remaining code from cpu_pic.c, so we can delete
6
that file entirely.
7
3
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
5
Message-id: 20240206132931.38376-10-peter.maydell@linaro.org
10
Message-id: 20201129174022.26530-3-peter.maydell@linaro.org
11
Reviewed-by: Wentong Wu <wentong.wu@intel.com>
12
Tested-by: Wentong Wu <wentong.wu@intel.com>
13
---
6
---
14
target/nios2/cpu.h | 2 --
7
hw/arm/mps3r.c | 180 ++++++++++++++++++++++++++++++++++++++++++++++++-
15
hw/nios2/cpu_pic.c | 36 ------------------------------------
8
1 file changed, 177 insertions(+), 3 deletions(-)
16
target/nios2/op_helper.c | 9 +++++++++
17
hw/nios2/meson.build | 2 +-
18
4 files changed, 10 insertions(+), 39 deletions(-)
19
delete mode 100644 hw/nios2/cpu_pic.c
20
9
21
diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h
10
diff --git a/hw/arm/mps3r.c b/hw/arm/mps3r.c
22
index XXXXXXX..XXXXXXX 100644
11
index XXXXXXX..XXXXXXX 100644
23
--- a/target/nios2/cpu.h
12
--- a/hw/arm/mps3r.c
24
+++ b/target/nios2/cpu.h
13
+++ b/hw/arm/mps3r.c
25
@@ -XXX,XX +XXX,XX @@ void nios2_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
26
MMUAccessType access_type,
27
int mmu_idx, uintptr_t retaddr);
28
29
-void nios2_check_interrupts(CPUNios2State *env);
30
-
31
void do_nios2_semihosting(CPUNios2State *env);
32
33
#define CPU_RESOLVING_TYPE TYPE_NIOS2_CPU
34
diff --git a/hw/nios2/cpu_pic.c b/hw/nios2/cpu_pic.c
35
deleted file mode 100644
36
index XXXXXXX..XXXXXXX
37
--- a/hw/nios2/cpu_pic.c
38
+++ /dev/null
39
@@ -XXX,XX +XXX,XX @@
14
@@ -XXX,XX +XXX,XX @@
40
-/*
15
#include "qemu/osdep.h"
41
- * Altera Nios2 CPU PIC
16
#include "qemu/units.h"
42
- *
17
#include "qapi/error.h"
43
- * Copyright (c) 2016 Marek Vasut <marek.vasut@gmail.com>
18
+#include "qapi/qmp/qlist.h"
44
- *
19
#include "exec/address-spaces.h"
45
- * This library is free software; you can redistribute it and/or
20
#include "cpu.h"
46
- * modify it under the terms of the GNU Lesser General Public
21
#include "hw/boards.h"
47
- * License as published by the Free Software Foundation; either
22
+#include "hw/qdev-properties.h"
48
- * version 2.1 of the License, or (at your option) any later version.
23
#include "hw/arm/boot.h"
49
- *
24
+#include "hw/arm/bsa.h"
50
- * This library is distributed in the hope that it will be useful,
25
+#include "hw/intc/arm_gicv3.h"
51
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
26
52
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
27
/* Define the layout of RAM and ROM in a board */
53
- * Lesser General Public License for more details.
28
typedef struct RAMInfo {
54
- *
29
@@ -XXX,XX +XXX,XX @@ typedef struct RAMInfo {
55
- * You should have received a copy of the GNU Lesser General Public
30
#define IS_ROM 2
56
- * License along with this library; if not, see
31
57
- * <http://www.gnu.org/licenses/lgpl-2.1.html>
32
#define MPS3R_RAM_MAX 9
58
- */
33
+#define MPS3R_CPU_MAX 2
59
-
34
+
60
-#include "qemu/osdep.h"
35
+#define PERIPHBASE 0xf0000000
61
-#include "cpu.h"
36
+#define NUM_SPIS 96
62
-#include "hw/irq.h"
37
63
-
38
typedef enum MPS3RFPGAType {
64
-#include "qemu/config-file.h"
39
FPGA_AN536,
65
-
40
@@ -XXX,XX +XXX,XX @@ struct MPS3RMachineClass {
66
-#include "boot.h"
41
MachineClass parent;
67
-
42
MPS3RFPGAType fpga_type;
68
-void nios2_check_interrupts(CPUNios2State *env)
43
const RAMInfo *raminfo;
69
-{
44
+ hwaddr loader_start;
70
- if (env->irq_pending &&
45
};
71
- (env->regs[CR_STATUS] & CR_STATUS_PIE)) {
46
72
- env->irq_pending = 0;
47
struct MPS3RMachineState {
73
- cpu_interrupt(env_cpu(env), CPU_INTERRUPT_HARD);
48
MachineState parent;
74
- }
49
+ struct arm_boot_info bootinfo;
75
-}
50
MemoryRegion ram[MPS3R_RAM_MAX];
76
diff --git a/target/nios2/op_helper.c b/target/nios2/op_helper.c
51
+ Object *cpu[MPS3R_CPU_MAX];
77
index XXXXXXX..XXXXXXX 100644
52
+ MemoryRegion cpu_sysmem[MPS3R_CPU_MAX];
78
--- a/target/nios2/op_helper.c
53
+ MemoryRegion sysmem_alias[MPS3R_CPU_MAX];
79
+++ b/target/nios2/op_helper.c
54
+ MemoryRegion cpu_ram[MPS3R_CPU_MAX];
80
@@ -XXX,XX +XXX,XX @@ void helper_mmu_write(CPUNios2State *env, uint32_t rn, uint32_t v)
55
+ GICv3State gic;
81
mmu_write(env, rn, v);
56
};
57
58
#define TYPE_MPS3R_MACHINE "mps3r"
59
@@ -XXX,XX +XXX,XX @@ static MemoryRegion *mr_for_raminfo(MPS3RMachineState *mms,
60
return ram;
82
}
61
}
83
62
84
+static void nios2_check_interrupts(CPUNios2State *env)
63
+/*
64
+ * There is no defined secondary boot protocol for Linux for the AN536,
65
+ * because real hardware has a restriction that atomic operations between
66
+ * the two CPUs do not function correctly, and so true SMP is not
67
+ * possible. Therefore for cases where the user is directly booting
68
+ * a kernel, we treat the system as essentially uniprocessor, and
69
+ * put the secondary CPU into power-off state (as if the user on the
70
+ * real hardware had configured the secondary to be halted via the
71
+ * SCC config registers).
72
+ *
73
+ * Note that the default secondary boot code would not work here anyway
74
+ * as it assumes a GICv2, and we have a GICv3.
75
+ */
76
+static void mps3r_write_secondary_boot(ARMCPU *cpu,
77
+ const struct arm_boot_info *info)
85
+{
78
+{
86
+ if (env->irq_pending &&
79
+ /*
87
+ (env->regs[CR_STATUS] & CR_STATUS_PIE)) {
80
+ * Power the secondary CPU off. This means we don't need to write any
88
+ env->irq_pending = 0;
81
+ * boot code into guest memory. Note that the 'cpu' argument to this
89
+ cpu_interrupt(env_cpu(env), CPU_INTERRUPT_HARD);
82
+ * function is the primary CPU we passed to arm_load_kernel(), not
83
+ * the secondary. Loop around all the other CPUs, as the boot.c
84
+ * code does for the "disable secondaries if PSCI is enabled" case.
85
+ */
86
+ for (CPUState *cs = first_cpu; cs; cs = CPU_NEXT(cs)) {
87
+ if (cs != first_cpu) {
88
+ object_property_set_bool(OBJECT(cs), "start-powered-off", true,
89
+ &error_abort);
90
+ }
90
+ }
91
+ }
91
+}
92
+}
92
+
93
+
93
void helper_check_interrupts(CPUNios2State *env)
94
+static void mps3r_secondary_cpu_reset(ARMCPU *cpu,
95
+ const struct arm_boot_info *info)
96
+{
97
+ /* We don't need to do anything here because the CPU will be off */
98
+}
99
+
100
+static void create_gic(MPS3RMachineState *mms, MemoryRegion *sysmem)
101
+{
102
+ MachineState *machine = MACHINE(mms);
103
+ DeviceState *gicdev;
104
+ QList *redist_region_count;
105
+
106
+ object_initialize_child(OBJECT(mms), "gic", &mms->gic, TYPE_ARM_GICV3);
107
+ gicdev = DEVICE(&mms->gic);
108
+ qdev_prop_set_uint32(gicdev, "num-cpu", machine->smp.cpus);
109
+ qdev_prop_set_uint32(gicdev, "num-irq", NUM_SPIS + GIC_INTERNAL);
110
+ redist_region_count = qlist_new();
111
+ qlist_append_int(redist_region_count, machine->smp.cpus);
112
+ qdev_prop_set_array(gicdev, "redist-region-count", redist_region_count);
113
+ object_property_set_link(OBJECT(&mms->gic), "sysmem",
114
+ OBJECT(sysmem), &error_fatal);
115
+ sysbus_realize(SYS_BUS_DEVICE(&mms->gic), &error_fatal);
116
+ sysbus_mmio_map(SYS_BUS_DEVICE(&mms->gic), 0, PERIPHBASE);
117
+ sysbus_mmio_map(SYS_BUS_DEVICE(&mms->gic), 1, PERIPHBASE + 0x100000);
118
+ /*
119
+ * Wire the outputs from each CPU's generic timer and the GICv3
120
+ * maintenance interrupt signal to the appropriate GIC PPI inputs,
121
+ * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs.
122
+ */
123
+ for (int i = 0; i < machine->smp.cpus; i++) {
124
+ DeviceState *cpudev = DEVICE(mms->cpu[i]);
125
+ SysBusDevice *gicsbd = SYS_BUS_DEVICE(&mms->gic);
126
+ int intidbase = NUM_SPIS + i * GIC_INTERNAL;
127
+ int irq;
128
+ /*
129
+ * Mapping from the output timer irq lines from the CPU to the
130
+ * GIC PPI inputs used for this board. This isn't a BSA board,
131
+ * but it uses the standard convention for the PPI numbers.
132
+ */
133
+ const int timer_irq[] = {
134
+ [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ,
135
+ [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ,
136
+ [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ,
137
+ };
138
+
139
+ for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) {
140
+ qdev_connect_gpio_out(cpudev, irq,
141
+ qdev_get_gpio_in(gicdev,
142
+ intidbase + timer_irq[irq]));
143
+ }
144
+
145
+ qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt", 0,
146
+ qdev_get_gpio_in(gicdev,
147
+ intidbase + ARCH_GIC_MAINT_IRQ));
148
+
149
+ qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0,
150
+ qdev_get_gpio_in(gicdev,
151
+ intidbase + VIRTUAL_PMU_IRQ));
152
+
153
+ sysbus_connect_irq(gicsbd, i,
154
+ qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));
155
+ sysbus_connect_irq(gicsbd, i + machine->smp.cpus,
156
+ qdev_get_gpio_in(cpudev, ARM_CPU_FIQ));
157
+ sysbus_connect_irq(gicsbd, i + 2 * machine->smp.cpus,
158
+ qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ));
159
+ sysbus_connect_irq(gicsbd, i + 3 * machine->smp.cpus,
160
+ qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ));
161
+ }
162
+}
163
+
164
static void mps3r_common_init(MachineState *machine)
94
{
165
{
95
qemu_mutex_lock_iothread();
166
MPS3RMachineState *mms = MPS3R_MACHINE(machine);
96
diff --git a/hw/nios2/meson.build b/hw/nios2/meson.build
167
@@ -XXX,XX +XXX,XX @@ static void mps3r_common_init(MachineState *machine)
97
index XXXXXXX..XXXXXXX 100644
168
MemoryRegion *mr = mr_for_raminfo(mms, ri);
98
--- a/hw/nios2/meson.build
169
memory_region_add_subregion(sysmem, ri->base, mr);
99
+++ b/hw/nios2/meson.build
170
}
100
@@ -XXX,XX +XXX,XX @@
171
+
101
nios2_ss = ss.source_set()
172
+ assert(machine->smp.cpus <= MPS3R_CPU_MAX);
102
-nios2_ss.add(files('boot.c', 'cpu_pic.c'))
173
+ for (int i = 0; i < machine->smp.cpus; i++) {
103
+nios2_ss.add(files('boot.c'))
174
+ g_autofree char *sysmem_name = g_strdup_printf("cpu-%d-memory", i);
104
nios2_ss.add(when: 'CONFIG_NIOS2_10M50', if_true: files('10m50_devboard.c'))
175
+ g_autofree char *ramname = g_strdup_printf("cpu-%d-memory", i);
105
nios2_ss.add(when: 'CONFIG_NIOS2_GENERIC_NOMMU', if_true: files('generic_nommu.c'))
176
+ g_autofree char *alias_name = g_strdup_printf("sysmem-alias-%d", i);
106
177
+
178
+ /*
179
+ * Each CPU has some private RAM/peripherals, so create the container
180
+ * which will house those, with the whole-machine system memory being
181
+ * used where there's no CPU-specific device. Note that we need the
182
+ * sysmem_alias aliases because we can't put one MR (the original
183
+ * 'sysmem') into more than one other MR.
184
+ */
185
+ memory_region_init(&mms->cpu_sysmem[i], OBJECT(machine),
186
+ sysmem_name, UINT64_MAX);
187
+ memory_region_init_alias(&mms->sysmem_alias[i], OBJECT(machine),
188
+ alias_name, sysmem, 0, UINT64_MAX);
189
+ memory_region_add_subregion_overlap(&mms->cpu_sysmem[i], 0,
190
+ &mms->sysmem_alias[i], -1);
191
+
192
+ mms->cpu[i] = object_new(machine->cpu_type);
193
+ object_property_set_link(mms->cpu[i], "memory",
194
+ OBJECT(&mms->cpu_sysmem[i]), &error_abort);
195
+ object_property_set_int(mms->cpu[i], "reset-cbar",
196
+ PERIPHBASE, &error_abort);
197
+ qdev_realize(DEVICE(mms->cpu[i]), NULL, &error_fatal);
198
+ object_unref(mms->cpu[i]);
199
+
200
+ /* Per-CPU RAM */
201
+ memory_region_init_ram(&mms->cpu_ram[i], NULL, ramname,
202
+ 0x1000, &error_fatal);
203
+ memory_region_add_subregion(&mms->cpu_sysmem[i], 0xe7c01000,
204
+ &mms->cpu_ram[i]);
205
+ }
206
+
207
+ create_gic(mms, sysmem);
208
+
209
+ mms->bootinfo.ram_size = machine->ram_size;
210
+ mms->bootinfo.board_id = -1;
211
+ mms->bootinfo.loader_start = mmc->loader_start;
212
+ mms->bootinfo.write_secondary_boot = mps3r_write_secondary_boot;
213
+ mms->bootinfo.secondary_cpu_reset_hook = mps3r_secondary_cpu_reset;
214
+ arm_load_kernel(ARM_CPU(mms->cpu[0]), machine, &mms->bootinfo);
215
}
216
217
static void mps3r_set_default_ram_info(MPS3RMachineClass *mmc)
218
@@ -XXX,XX +XXX,XX @@ static void mps3r_set_default_ram_info(MPS3RMachineClass *mmc)
219
/* Found the entry for "system memory" */
220
mc->default_ram_size = p->size;
221
mc->default_ram_id = p->name;
222
+ mmc->loader_start = p->base;
223
return;
224
}
225
}
226
@@ -XXX,XX +XXX,XX @@ static void mps3r_an536_class_init(ObjectClass *oc, void *data)
227
};
228
229
mc->desc = "ARM MPS3 with AN536 FPGA image for Cortex-R52";
230
- mc->default_cpus = 2;
231
- mc->min_cpus = mc->default_cpus;
232
- mc->max_cpus = mc->default_cpus;
233
+ /*
234
+ * In the real FPGA image there are always two cores, but the standard
235
+ * initial setting for the SCC SYSCON 0x000 register is 0x21, meaning
236
+ * that the second core is held in reset and halted. Many images built for
237
+ * the board do not expect the second core to run at startup (especially
238
+ * since on the real FPGA image it is not possible to use LDREX/STREX
239
+ * in RAM between the two cores, so a true SMP setup isn't supported).
240
+ *
241
+ * As QEMU's equivalent of this, we support both -smp 1 and -smp 2,
242
+ * with the default being -smp 1. This seems a more intuitive UI for
243
+ * QEMU users than, for instance, having a machine property to allow
244
+ * the user to set the initial value of the SYSCON 0x000 register.
245
+ */
246
+ mc->default_cpus = 1;
247
+ mc->min_cpus = 1;
248
+ mc->max_cpus = 2;
249
mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-r52");
250
mc->valid_cpu_types = valid_cpu_types;
251
mmc->raminfo = an536_raminfo;
107
--
252
--
108
2.20.1
253
2.34.1
109
110
diff view generated by jsdifflib
[PULL 08/20] hw/core/loader.c: Track last-seen ROM in rom_check_and_register_reset()
[PULL 32/35] hw/arm/mps3r: Add UARTs
1
In rom_check_and_register_reset() we detect overlaps by looking at
1
This board has a lot of UARTs: there is one UART per CPU in the
2
whether the ROM blob we're currently examining is in the same address
2
per-CPU peripheral part of the address map, whose interrupts are
3
space and starts before the previous ROM blob ends. (This works
3
connected as per-CPU interrupt lines. Then there are 4 UARTs in the
4
because the ROM list is kept sorted in order by AddressSpace and then
4
normal part of the peripheral space, whose interrupts are shared
5
by address.)
5
peripheral interrupts.
6
6
7
Instead of keeping the AddressSpace and last address of the previous ROM
7
Connect and wire them all up; this involves some OR gates where
8
blob in local variables, just keep a pointer to it.
8
multiple overflow interrupts are wired into one GIC input.
9
10
This will allow us to print more useful information when we do detect
11
an overlap.
12
9
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
11
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
15
Message-id: 20201129203923.10622-2-peter.maydell@linaro.org
12
Message-id: 20240206132931.38376-11-peter.maydell@linaro.org
16
---
13
---
17
hw/core/loader.c | 23 +++++++++++++++--------
14
hw/arm/mps3r.c | 94 ++++++++++++++++++++++++++++++++++++++++++++++++++
18
1 file changed, 15 insertions(+), 8 deletions(-)
15
1 file changed, 94 insertions(+)
19
16
20
diff --git a/hw/core/loader.c b/hw/core/loader.c
17
diff --git a/hw/arm/mps3r.c b/hw/arm/mps3r.c
21
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
22
--- a/hw/core/loader.c
19
--- a/hw/arm/mps3r.c
23
+++ b/hw/core/loader.c
20
+++ b/hw/arm/mps3r.c
24
@@ -XXX,XX +XXX,XX @@ static void rom_reset(void *unused)
21
@@ -XXX,XX +XXX,XX @@
22
#include "qapi/qmp/qlist.h"
23
#include "exec/address-spaces.h"
24
#include "cpu.h"
25
+#include "sysemu/sysemu.h"
26
#include "hw/boards.h"
27
+#include "hw/or-irq.h"
28
#include "hw/qdev-properties.h"
29
#include "hw/arm/boot.h"
30
#include "hw/arm/bsa.h"
31
+#include "hw/char/cmsdk-apb-uart.h"
32
#include "hw/intc/arm_gicv3.h"
33
34
/* Define the layout of RAM and ROM in a board */
35
@@ -XXX,XX +XXX,XX @@ typedef struct RAMInfo {
36
37
#define MPS3R_RAM_MAX 9
38
#define MPS3R_CPU_MAX 2
39
+#define MPS3R_UART_MAX 4 /* shared UART count */
40
41
#define PERIPHBASE 0xf0000000
42
#define NUM_SPIS 96
43
@@ -XXX,XX +XXX,XX @@ struct MPS3RMachineState {
44
MemoryRegion sysmem_alias[MPS3R_CPU_MAX];
45
MemoryRegion cpu_ram[MPS3R_CPU_MAX];
46
GICv3State gic;
47
+ /* per-CPU UARTs followed by the shared UARTs */
48
+ CMSDKAPBUART uart[MPS3R_CPU_MAX + MPS3R_UART_MAX];
49
+ OrIRQState cpu_uart_oflow[MPS3R_CPU_MAX];
50
+ OrIRQState uart_oflow;
51
};
52
53
#define TYPE_MPS3R_MACHINE "mps3r"
54
@@ -XXX,XX +XXX,XX @@ struct MPS3RMachineState {
55
56
OBJECT_DECLARE_TYPE(MPS3RMachineState, MPS3RMachineClass, MPS3R_MACHINE)
57
58
+/*
59
+ * Main clock frequency CLK in Hz (50MHz). In the image there are also
60
+ * ACLK, MCLK, GPUCLK and PERIPHCLK at the same frequency; for our
61
+ * model we just roll them all into one.
62
+ */
63
+#define CLK_FRQ 50000000
64
+
65
static const RAMInfo an536_raminfo[] = {
66
{
67
.name = "ATCM",
68
@@ -XXX,XX +XXX,XX @@ static void create_gic(MPS3RMachineState *mms, MemoryRegion *sysmem)
25
}
69
}
26
}
70
}
27
71
28
+/* Return true if two consecutive ROMs in the ROM list overlap */
72
+/*
29
+static bool roms_overlap(Rom *last_rom, Rom *this_rom)
73
+ * Create UART uartno, and map it into the MemoryRegion mem at address baseaddr.
74
+ * The qemu_irq arguments are where we connect the various IRQs from the UART.
75
+ */
76
+static void create_uart(MPS3RMachineState *mms, int uartno, MemoryRegion *mem,
77
+ hwaddr baseaddr, qemu_irq txirq, qemu_irq rxirq,
78
+ qemu_irq txoverirq, qemu_irq rxoverirq,
79
+ qemu_irq combirq)
30
+{
80
+{
31
+ if (!last_rom) {
81
+ g_autofree char *s = g_strdup_printf("uart%d", uartno);
32
+ return false;
82
+ SysBusDevice *sbd;
33
+ }
83
+
34
+ return last_rom->as == this_rom->as &&
84
+ assert(uartno < ARRAY_SIZE(mms->uart));
35
+ last_rom->addr + last_rom->romsize > this_rom->addr;
85
+ object_initialize_child(OBJECT(mms), s, &mms->uart[uartno],
86
+ TYPE_CMSDK_APB_UART);
87
+ qdev_prop_set_uint32(DEVICE(&mms->uart[uartno]), "pclk-frq", CLK_FRQ);
88
+ qdev_prop_set_chr(DEVICE(&mms->uart[uartno]), "chardev", serial_hd(uartno));
89
+ sbd = SYS_BUS_DEVICE(&mms->uart[uartno]);
90
+ sysbus_realize(sbd, &error_fatal);
91
+ memory_region_add_subregion(mem, baseaddr,
92
+ sysbus_mmio_get_region(sbd, 0));
93
+ sysbus_connect_irq(sbd, 0, txirq);
94
+ sysbus_connect_irq(sbd, 1, rxirq);
95
+ sysbus_connect_irq(sbd, 2, txoverirq);
96
+ sysbus_connect_irq(sbd, 3, rxoverirq);
97
+ sysbus_connect_irq(sbd, 4, combirq);
36
+}
98
+}
37
+
99
+
38
int rom_check_and_register_reset(void)
100
static void mps3r_common_init(MachineState *machine)
39
{
101
{
40
- hwaddr addr = 0;
102
MPS3RMachineState *mms = MPS3R_MACHINE(machine);
41
MemoryRegionSection section;
103
MPS3RMachineClass *mmc = MPS3R_MACHINE_GET_CLASS(mms);
42
- Rom *rom;
104
MemoryRegion *sysmem = get_system_memory();
43
- AddressSpace *as = NULL;
105
+ DeviceState *gicdev;
44
+ Rom *rom, *last_rom = NULL;
106
45
107
for (const RAMInfo *ri = mmc->raminfo; ri->name; ri++) {
46
QTAILQ_FOREACH(rom, &roms, next) {
108
MemoryRegion *mr = mr_for_raminfo(mms, ri);
47
if (rom->fw_file) {
109
@@ -XXX,XX +XXX,XX @@ static void mps3r_common_init(MachineState *machine)
48
continue;
110
}
49
}
111
50
if (!rom->mr) {
112
create_gic(mms, sysmem);
51
- if ((addr > rom->addr) && (as == rom->as)) {
113
+ gicdev = DEVICE(&mms->gic);
52
+ if (roms_overlap(last_rom, rom)) {
114
+
53
fprintf(stderr, "rom: requested regions overlap "
115
+ /*
54
"(rom %s. free=0x" TARGET_FMT_plx
116
+ * UARTs 0 and 1 are per-CPU; their interrupts are wired to
55
", addr=0x" TARGET_FMT_plx ")\n",
117
+ * the relevant CPU's PPI 0..3, aka INTID 16..19
56
- rom->name, addr, rom->addr);
118
+ */
57
+ rom->name, last_rom->addr + last_rom->romsize,
119
+ for (int i = 0; i < machine->smp.cpus; i++) {
58
+ rom->addr);
120
+ int intidbase = NUM_SPIS + i * GIC_INTERNAL;
59
return -1;
121
+ g_autofree char *s = g_strdup_printf("cpu-uart-oflow-orgate%d", i);
60
}
122
+ DeviceState *orgate;
61
- addr = rom->addr;
123
+
62
- addr += rom->romsize;
124
+ /* The two overflow IRQs from the UART are ORed together into PPI 3 */
63
- as = rom->as;
125
+ object_initialize_child(OBJECT(mms), s, &mms->cpu_uart_oflow[i],
64
+ last_rom = rom;
126
+ TYPE_OR_IRQ);
65
}
127
+ orgate = DEVICE(&mms->cpu_uart_oflow[i]);
66
section = memory_region_find(rom->mr ? rom->mr : get_system_memory(),
128
+ qdev_prop_set_uint32(orgate, "num-lines", 2);
67
rom->addr, 1);
129
+ qdev_realize(orgate, NULL, &error_fatal);
130
+ qdev_connect_gpio_out(orgate, 0,
131
+ qdev_get_gpio_in(gicdev, intidbase + 19));
132
+
133
+ create_uart(mms, i, &mms->cpu_sysmem[i], 0xe7c00000,
134
+ qdev_get_gpio_in(gicdev, intidbase + 17), /* tx */
135
+ qdev_get_gpio_in(gicdev, intidbase + 16), /* rx */
136
+ qdev_get_gpio_in(orgate, 0), /* txover */
137
+ qdev_get_gpio_in(orgate, 1), /* rxover */
138
+ qdev_get_gpio_in(gicdev, intidbase + 18) /* combined */);
139
+ }
140
+ /*
141
+ * UARTs 2 to 5 are whole-system; all overflow IRQs are ORed
142
+ * together into IRQ 17
143
+ */
144
+ object_initialize_child(OBJECT(mms), "uart-oflow-orgate",
145
+ &mms->uart_oflow, TYPE_OR_IRQ);
146
+ qdev_prop_set_uint32(DEVICE(&mms->uart_oflow), "num-lines",
147
+ MPS3R_UART_MAX * 2);
148
+ qdev_realize(DEVICE(&mms->uart_oflow), NULL, &error_fatal);
149
+ qdev_connect_gpio_out(DEVICE(&mms->uart_oflow), 0,
150
+ qdev_get_gpio_in(gicdev, 17));
151
+
152
+ for (int i = 0; i < MPS3R_UART_MAX; i++) {
153
+ hwaddr baseaddr = 0xe0205000 + i * 0x1000;
154
+ int rxirq = 5 + i * 2, txirq = 6 + i * 2, combirq = 13 + i;
155
+
156
+ create_uart(mms, i + MPS3R_CPU_MAX, sysmem, baseaddr,
157
+ qdev_get_gpio_in(gicdev, txirq),
158
+ qdev_get_gpio_in(gicdev, rxirq),
159
+ qdev_get_gpio_in(DEVICE(&mms->uart_oflow), i * 2),
160
+ qdev_get_gpio_in(DEVICE(&mms->uart_oflow), i * 2 + 1),
161
+ qdev_get_gpio_in(gicdev, combirq));
162
+ }
163
164
mms->bootinfo.ram_size = machine->ram_size;
165
mms->bootinfo.board_id = -1;
68
--
166
--
69
2.20.1
167
2.34.1
70
168
71
169
diff view generated by jsdifflib
[PULL 04/20] target/openrisc: Move pic_cpu code into CPU object proper
[PULL 33/35] hw/arm/mps3r: Add GPIO, watchdog, dual-timer, I2C devices
1
The openrisc code uses an old style of interrupt handling, where a
1
Add the GPIO, watchdog, dual-timer and I2C devices to the mps3-an536
2
separate standalone set of qemu_irqs invoke a function
2
board. These are all simple devices that just need to be created and
3
openrisc_pic_cpu_handler() which signals the interrupt to the CPU
3
wired up.
4
proper by directly calling cpu_interrupt() and cpu_reset_interrupt().
5
Because CPU objects now inherit (indirectly) from TYPE_DEVICE, they
6
can have GPIO input lines themselves, and the neater modern way to
7
implement this is to simply have the CPU object itself provide the
8
input IRQ lines.
9
4
10
Create GPIO inputs to the OpenRISC CPU object, and make the only user
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
of cpu_openrisc_pic_init() wire up directly to those instead.
6
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
7
Message-id: 20240206132931.38376-12-peter.maydell@linaro.org
8
---
9
hw/arm/mps3r.c | 59 ++++++++++++++++++++++++++++++++++++++++++++++++++
10
1 file changed, 59 insertions(+)
12
11
13
This allows us to delete the hw/openrisc/pic_cpu.c file entirely.
12
diff --git a/hw/arm/mps3r.c b/hw/arm/mps3r.c
14
15
This fixes a trivial memory leak reported by Coverity of the IRQs
16
allocated in cpu_openrisc_pic_init().
17
18
Fixes: Coverity CID 1421934
19
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
20
Reviewed-by: Stafford Horne <shorne@gmail.com>
21
Message-id: 20201127225127.14770-4-peter.maydell@linaro.org
22
---
23
target/openrisc/cpu.h | 1 -
24
hw/openrisc/openrisc_sim.c | 3 +-
25
hw/openrisc/pic_cpu.c | 61 --------------------------------------
26
target/openrisc/cpu.c | 32 ++++++++++++++++++++
27
hw/openrisc/meson.build | 2 +-
28
5 files changed, 34 insertions(+), 65 deletions(-)
29
delete mode 100644 hw/openrisc/pic_cpu.c
30
31
diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h
32
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
33
--- a/target/openrisc/cpu.h
14
--- a/hw/arm/mps3r.c
34
+++ b/target/openrisc/cpu.h
15
+++ b/hw/arm/mps3r.c
35
@@ -XXX,XX +XXX,XX @@ typedef struct CPUOpenRISCState {
36
uint32_t picmr; /* Interrupt mask register */
37
uint32_t picsr; /* Interrupt contrl register*/
38
#endif
39
- void *irq[32]; /* Interrupt irq input */
40
} CPUOpenRISCState;
41
42
/**
43
diff --git a/hw/openrisc/openrisc_sim.c b/hw/openrisc/openrisc_sim.c
44
index XXXXXXX..XXXXXXX 100644
45
--- a/hw/openrisc/openrisc_sim.c
46
+++ b/hw/openrisc/openrisc_sim.c
47
@@ -XXX,XX +XXX,XX @@ static void main_cpu_reset(void *opaque)
48
49
static qemu_irq get_cpu_irq(OpenRISCCPU *cpus[], int cpunum, int irq_pin)
50
{
51
- return cpus[cpunum]->env.irq[irq_pin];
52
+ return qdev_get_gpio_in_named(DEVICE(cpus[cpunum]), "IRQ", irq_pin);
53
}
54
55
static void openrisc_sim_net_init(hwaddr base, hwaddr descriptors,
56
@@ -XXX,XX +XXX,XX @@ static void openrisc_sim_init(MachineState *machine)
57
fprintf(stderr, "Unable to find CPU definition!\n");
58
exit(1);
59
}
60
- cpu_openrisc_pic_init(cpus[n]);
61
62
cpu_openrisc_clock_init(cpus[n]);
63
64
diff --git a/hw/openrisc/pic_cpu.c b/hw/openrisc/pic_cpu.c
65
deleted file mode 100644
66
index XXXXXXX..XXXXXXX
67
--- a/hw/openrisc/pic_cpu.c
68
+++ /dev/null
69
@@ -XXX,XX +XXX,XX @@
16
@@ -XXX,XX +XXX,XX @@
70
-/*
17
#include "sysemu/sysemu.h"
71
- * OpenRISC Programmable Interrupt Controller support.
18
#include "hw/boards.h"
72
- *
19
#include "hw/or-irq.h"
73
- * Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com>
20
+#include "hw/qdev-clock.h"
74
- * Feng Gao <gf91597@gmail.com>
21
#include "hw/qdev-properties.h"
75
- *
22
#include "hw/arm/boot.h"
76
- * This library is free software; you can redistribute it and/or
23
#include "hw/arm/bsa.h"
77
- * modify it under the terms of the GNU Lesser General Public
24
#include "hw/char/cmsdk-apb-uart.h"
78
- * License as published by the Free Software Foundation; either
25
+#include "hw/i2c/arm_sbcon_i2c.h"
79
- * version 2.1 of the License, or (at your option) any later version.
26
#include "hw/intc/arm_gicv3.h"
80
- *
27
+#include "hw/misc/unimp.h"
81
- * This library is distributed in the hope that it will be useful,
28
+#include "hw/timer/cmsdk-apb-dualtimer.h"
82
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
29
+#include "hw/watchdog/cmsdk-apb-watchdog.h"
83
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
30
84
- * Lesser General Public License for more details.
31
/* Define the layout of RAM and ROM in a board */
85
- *
32
typedef struct RAMInfo {
86
- * You should have received a copy of the GNU Lesser General Public
33
@@ -XXX,XX +XXX,XX @@ struct MPS3RMachineState {
87
- * License along with this library; if not, see <http://www.gnu.org/licenses/>.
34
CMSDKAPBUART uart[MPS3R_CPU_MAX + MPS3R_UART_MAX];
88
- */
35
OrIRQState cpu_uart_oflow[MPS3R_CPU_MAX];
89
-
36
OrIRQState uart_oflow;
90
-#include "qemu/osdep.h"
37
+ CMSDKAPBWatchdog watchdog;
91
-#include "hw/irq.h"
38
+ CMSDKAPBDualTimer dualtimer;
92
-#include "cpu.h"
39
+ ArmSbconI2CState i2c[5];
93
-
40
+ Clock *clk;
94
-/* OpenRISC pic handler */
41
};
95
-static void openrisc_pic_cpu_handler(void *opaque, int irq, int level)
42
96
-{
43
#define TYPE_MPS3R_MACHINE "mps3r"
97
- OpenRISCCPU *cpu = (OpenRISCCPU *)opaque;
44
@@ -XXX,XX +XXX,XX @@ static void mps3r_common_init(MachineState *machine)
98
- CPUState *cs = CPU(cpu);
45
MemoryRegion *sysmem = get_system_memory();
99
- uint32_t irq_bit;
46
DeviceState *gicdev;
100
-
47
101
- if (irq > 31 || irq < 0) {
48
+ mms->clk = clock_new(OBJECT(machine), "CLK");
102
- return;
49
+ clock_set_hz(mms->clk, CLK_FRQ);
103
- }
104
-
105
- irq_bit = 1U << irq;
106
-
107
- if (level) {
108
- cpu->env.picsr |= irq_bit;
109
- } else {
110
- cpu->env.picsr &= ~irq_bit;
111
- }
112
-
113
- if (cpu->env.picsr & cpu->env.picmr) {
114
- cpu_interrupt(cs, CPU_INTERRUPT_HARD);
115
- } else {
116
- cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
117
- cpu->env.picsr = 0;
118
- }
119
-}
120
-
121
-void cpu_openrisc_pic_init(OpenRISCCPU *cpu)
122
-{
123
- int i;
124
- qemu_irq *qi;
125
- qi = qemu_allocate_irqs(openrisc_pic_cpu_handler, cpu, NR_IRQS);
126
-
127
- for (i = 0; i < NR_IRQS; i++) {
128
- cpu->env.irq[i] = qi[i];
129
- }
130
-}
131
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
132
index XXXXXXX..XXXXXXX 100644
133
--- a/target/openrisc/cpu.c
134
+++ b/target/openrisc/cpu.c
135
@@ -XXX,XX +XXX,XX @@ static void openrisc_cpu_reset(DeviceState *dev)
136
#endif
137
}
138
139
+#ifndef CONFIG_USER_ONLY
140
+static void openrisc_cpu_set_irq(void *opaque, int irq, int level)
141
+{
142
+ OpenRISCCPU *cpu = (OpenRISCCPU *)opaque;
143
+ CPUState *cs = CPU(cpu);
144
+ uint32_t irq_bit;
145
+
50
+
146
+ if (irq > 31 || irq < 0) {
51
for (const RAMInfo *ri = mmc->raminfo; ri->name; ri++) {
147
+ return;
52
MemoryRegion *mr = mr_for_raminfo(mms, ri);
53
memory_region_add_subregion(sysmem, ri->base, mr);
54
@@ -XXX,XX +XXX,XX @@ static void mps3r_common_init(MachineState *machine)
55
qdev_get_gpio_in(gicdev, combirq));
56
}
57
58
+ for (int i = 0; i < 4; i++) {
59
+ /* CMSDK GPIO controllers */
60
+ g_autofree char *s = g_strdup_printf("gpio%d", i);
61
+ create_unimplemented_device(s, 0xe0000000 + i * 0x1000, 0x1000);
148
+ }
62
+ }
149
+
63
+
150
+ irq_bit = 1U << irq;
64
+ object_initialize_child(OBJECT(mms), "watchdog", &mms->watchdog,
65
+ TYPE_CMSDK_APB_WATCHDOG);
66
+ qdev_connect_clock_in(DEVICE(&mms->watchdog), "WDOGCLK", mms->clk);
67
+ sysbus_realize(SYS_BUS_DEVICE(&mms->watchdog), &error_fatal);
68
+ sysbus_connect_irq(SYS_BUS_DEVICE(&mms->watchdog), 0,
69
+ qdev_get_gpio_in(gicdev, 0));
70
+ sysbus_mmio_map(SYS_BUS_DEVICE(&mms->watchdog), 0, 0xe0100000);
151
+
71
+
152
+ if (level) {
72
+ object_initialize_child(OBJECT(mms), "dualtimer", &mms->dualtimer,
153
+ cpu->env.picsr |= irq_bit;
73
+ TYPE_CMSDK_APB_DUALTIMER);
154
+ } else {
74
+ qdev_connect_clock_in(DEVICE(&mms->dualtimer), "TIMCLK", mms->clk);
155
+ cpu->env.picsr &= ~irq_bit;
75
+ sysbus_realize(SYS_BUS_DEVICE(&mms->dualtimer), &error_fatal);
76
+ sysbus_connect_irq(SYS_BUS_DEVICE(&mms->dualtimer), 0,
77
+ qdev_get_gpio_in(gicdev, 3));
78
+ sysbus_connect_irq(SYS_BUS_DEVICE(&mms->dualtimer), 1,
79
+ qdev_get_gpio_in(gicdev, 1));
80
+ sysbus_connect_irq(SYS_BUS_DEVICE(&mms->dualtimer), 2,
81
+ qdev_get_gpio_in(gicdev, 2));
82
+ sysbus_mmio_map(SYS_BUS_DEVICE(&mms->dualtimer), 0, 0xe0101000);
83
+
84
+ for (int i = 0; i < ARRAY_SIZE(mms->i2c); i++) {
85
+ static const hwaddr i2cbase[] = {0xe0102000, /* Touch */
86
+ 0xe0103000, /* Audio */
87
+ 0xe0107000, /* Shield0 */
88
+ 0xe0108000, /* Shield1 */
89
+ 0xe0109000}; /* DDR4 EEPROM */
90
+ g_autofree char *s = g_strdup_printf("i2c%d", i);
91
+
92
+ object_initialize_child(OBJECT(mms), s, &mms->i2c[i],
93
+ TYPE_ARM_SBCON_I2C);
94
+ sysbus_realize(SYS_BUS_DEVICE(&mms->i2c[i]), &error_fatal);
95
+ sysbus_mmio_map(SYS_BUS_DEVICE(&mms->i2c[i]), 0, i2cbase[i]);
96
+ if (i != 2 && i != 3) {
97
+ /*
98
+ * internal-only bus: mark it full to avoid user-created
99
+ * i2c devices being plugged into it.
100
+ */
101
+ qbus_mark_full(qdev_get_child_bus(DEVICE(&mms->i2c[i]), "i2c"));
102
+ }
156
+ }
103
+ }
157
+
104
+
158
+ if (cpu->env.picsr & cpu->env.picmr) {
105
mms->bootinfo.ram_size = machine->ram_size;
159
+ cpu_interrupt(cs, CPU_INTERRUPT_HARD);
106
mms->bootinfo.board_id = -1;
160
+ } else {
107
mms->bootinfo.loader_start = mmc->loader_start;
161
+ cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
162
+ cpu->env.picsr = 0;
163
+ }
164
+}
165
+#endif
166
+
167
static void openrisc_cpu_realizefn(DeviceState *dev, Error **errp)
168
{
169
CPUState *cs = CPU(dev);
170
@@ -XXX,XX +XXX,XX @@ static void openrisc_cpu_initfn(Object *obj)
171
OpenRISCCPU *cpu = OPENRISC_CPU(obj);
172
173
cpu_set_cpustate_pointers(cpu);
174
+
175
+#ifndef CONFIG_USER_ONLY
176
+ qdev_init_gpio_in_named(DEVICE(cpu), openrisc_cpu_set_irq, "IRQ", NR_IRQS);
177
+#endif
178
}
179
180
/* CPU models */
181
diff --git a/hw/openrisc/meson.build b/hw/openrisc/meson.build
182
index XXXXXXX..XXXXXXX 100644
183
--- a/hw/openrisc/meson.build
184
+++ b/hw/openrisc/meson.build
185
@@ -XXX,XX +XXX,XX @@
186
openrisc_ss = ss.source_set()
187
-openrisc_ss.add(files('pic_cpu.c', 'cputimer.c'))
188
+openrisc_ss.add(files('cputimer.c'))
189
openrisc_ss.add(when: 'CONFIG_OR1K_SIM', if_true: files('openrisc_sim.c'))
190
191
hw_arch += {'openrisc': openrisc_ss}
192
--
108
--
193
2.20.1
109
2.34.1
194
110
195
111
diff view generated by jsdifflib
[PULL 05/20] target/nios2: Move IIC code into CPU object proper
[PULL 34/35] hw/arm/mps3r: Add remaining devices
1
The Nios2 architecture supports two different interrupt controller
1
Add the remaining devices (or unimplemented-device stubs) for
2
options:
2
this board: SPI controllers, SCC, FPGAIO, I2S, RTC, the
3
QSPI write-config block, and ethernet.
3
4
4
* The IIC (Internal Interrupt Controller) is part of the CPU itself;
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
it has 32 IRQ input lines and no NMI support. Interrupt status is
6
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
6
queried and controlled via the CPU's ipending and istatus
7
Message-id: 20240206132931.38376-13-peter.maydell@linaro.org
7
registers.
8
---
9
hw/arm/mps3r.c | 74 ++++++++++++++++++++++++++++++++++++++++++++++++++
10
1 file changed, 74 insertions(+)
8
11
9
* The EIC (External Interrupt Controller) interface allows the CPU
12
diff --git a/hw/arm/mps3r.c b/hw/arm/mps3r.c
10
to connect to an external interrupt controller. The interface
11
allows the interrupt controller to present a packet of information
12
containing:
13
- handler address
14
- interrupt level
15
- register set
16
- NMI mode
17
18
QEMU does not model an EIC currently. We do model the IIC, but its
19
implementation is split across code in hw/nios2/cpu_pic.c and
20
hw/intc/nios2_iic.c. The code in those two files has no state of its
21
own -- the IIC state is in the Nios2CPU state struct.
22
23
Because CPU objects now inherit (indirectly) from TYPE_DEVICE, they
24
can have GPIO input lines themselves, so we can implement the IIC
25
directly in the CPU object the same way that real hardware does.
26
27
Create named "IRQ" GPIO inputs to the Nios2 CPU object, and make the
28
only user of the IIC wire up directly to those instead.
29
30
Note that the old code had an "NMI" concept which was entirely unused
31
and also as far as I can see not architecturally correct, since only
32
the EIC has a concept of an NMI.
33
34
This fixes a Coverity-reported trivial memory leak of the IRQ array
35
allocated in nios2_cpu_pic_init().
36
37
Fixes: Coverity CID 1421916
38
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
39
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
40
Message-id: 20201129174022.26530-2-peter.maydell@linaro.org
41
Reviewed-by: Wentong Wu <wentong.wu@intel.com>
42
Tested-by: Wentong Wu <wentong.wu@intel.com>
43
---
44
target/nios2/cpu.h | 1 -
45
hw/intc/nios2_iic.c | 95 ---------------------------------------
46
hw/nios2/10m50_devboard.c | 13 +-----
47
hw/nios2/cpu_pic.c | 31 -------------
48
target/nios2/cpu.c | 30 +++++++++++++
49
MAINTAINERS | 1 -
50
hw/intc/meson.build | 1 -
51
7 files changed, 32 insertions(+), 140 deletions(-)
52
delete mode 100644 hw/intc/nios2_iic.c
53
54
diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h
55
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
56
--- a/target/nios2/cpu.h
14
--- a/hw/arm/mps3r.c
57
+++ b/target/nios2/cpu.h
15
+++ b/hw/arm/mps3r.c
58
@@ -XXX,XX +XXX,XX @@ void nios2_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
59
MMUAccessType access_type,
60
int mmu_idx, uintptr_t retaddr);
61
62
-qemu_irq *nios2_cpu_pic_init(Nios2CPU *cpu);
63
void nios2_check_interrupts(CPUNios2State *env);
64
65
void do_nios2_semihosting(CPUNios2State *env);
66
diff --git a/hw/intc/nios2_iic.c b/hw/intc/nios2_iic.c
67
deleted file mode 100644
68
index XXXXXXX..XXXXXXX
69
--- a/hw/intc/nios2_iic.c
70
+++ /dev/null
71
@@ -XXX,XX +XXX,XX @@
16
@@ -XXX,XX +XXX,XX @@
72
-/*
17
#include "hw/char/cmsdk-apb-uart.h"
73
- * QEMU Altera Internal Interrupt Controller.
18
#include "hw/i2c/arm_sbcon_i2c.h"
74
- *
19
#include "hw/intc/arm_gicv3.h"
75
- * Copyright (c) 2012 Chris Wulff <crwulff@gmail.com>
20
+#include "hw/misc/mps2-scc.h"
76
- *
21
+#include "hw/misc/mps2-fpgaio.h"
77
- * This library is free software; you can redistribute it and/or
22
#include "hw/misc/unimp.h"
78
- * modify it under the terms of the GNU Lesser General Public
23
+#include "hw/net/lan9118.h"
79
- * License as published by the Free Software Foundation; either
24
+#include "hw/rtc/pl031.h"
80
- * version 2.1 of the License, or (at your option) any later version.
25
+#include "hw/ssi/pl022.h"
81
- *
26
#include "hw/timer/cmsdk-apb-dualtimer.h"
82
- * This library is distributed in the hope that it will be useful,
27
#include "hw/watchdog/cmsdk-apb-watchdog.h"
83
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
28
84
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
29
@@ -XXX,XX +XXX,XX @@ struct MPS3RMachineState {
85
- * Lesser General Public License for more details.
30
CMSDKAPBWatchdog watchdog;
86
- *
31
CMSDKAPBDualTimer dualtimer;
87
- * You should have received a copy of the GNU Lesser General Public
32
ArmSbconI2CState i2c[5];
88
- * License along with this library; if not, see
33
+ PL022State spi[3];
89
- * <http://www.gnu.org/licenses/lgpl-2.1.html>
34
+ MPS2SCC scc;
90
- */
35
+ MPS2FPGAIO fpgaio;
91
-
36
+ UnimplementedDeviceState i2s_audio;
92
-#include "qemu/osdep.h"
37
+ PL031State rtc;
93
-#include "qemu/module.h"
38
Clock *clk;
94
-#include "qapi/error.h"
39
};
95
-
40
96
-#include "hw/irq.h"
41
@@ -XXX,XX +XXX,XX @@ static const RAMInfo an536_raminfo[] = {
97
-#include "hw/sysbus.h"
98
-#include "cpu.h"
99
-#include "qom/object.h"
100
-
101
-#define TYPE_ALTERA_IIC "altera,iic"
102
-OBJECT_DECLARE_SIMPLE_TYPE(AlteraIIC, ALTERA_IIC)
103
-
104
-struct AlteraIIC {
105
- SysBusDevice parent_obj;
106
- void *cpu;
107
- qemu_irq parent_irq;
108
-};
109
-
110
-static void update_irq(AlteraIIC *pv)
111
-{
112
- CPUNios2State *env = &((Nios2CPU *)(pv->cpu))->env;
113
-
114
- qemu_set_irq(pv->parent_irq,
115
- env->regs[CR_IPENDING] & env->regs[CR_IENABLE]);
116
-}
117
-
118
-static void irq_handler(void *opaque, int irq, int level)
119
-{
120
- AlteraIIC *pv = opaque;
121
- CPUNios2State *env = &((Nios2CPU *)(pv->cpu))->env;
122
-
123
- env->regs[CR_IPENDING] &= ~(1 << irq);
124
- env->regs[CR_IPENDING] |= !!level << irq;
125
-
126
- update_irq(pv);
127
-}
128
-
129
-static void altera_iic_init(Object *obj)
130
-{
131
- AlteraIIC *pv = ALTERA_IIC(obj);
132
-
133
- qdev_init_gpio_in(DEVICE(pv), irq_handler, 32);
134
- sysbus_init_irq(SYS_BUS_DEVICE(obj), &pv->parent_irq);
135
-}
136
-
137
-static void altera_iic_realize(DeviceState *dev, Error **errp)
138
-{
139
- struct AlteraIIC *pv = ALTERA_IIC(dev);
140
-
141
- pv->cpu = object_property_get_link(OBJECT(dev), "cpu", &error_abort);
142
-}
143
-
144
-static void altera_iic_class_init(ObjectClass *klass, void *data)
145
-{
146
- DeviceClass *dc = DEVICE_CLASS(klass);
147
-
148
- /* Reason: needs to be wired up, e.g. by nios2_10m50_ghrd_init() */
149
- dc->user_creatable = false;
150
- dc->realize = altera_iic_realize;
151
-}
152
-
153
-static TypeInfo altera_iic_info = {
154
- .name = TYPE_ALTERA_IIC,
155
- .parent = TYPE_SYS_BUS_DEVICE,
156
- .instance_size = sizeof(AlteraIIC),
157
- .instance_init = altera_iic_init,
158
- .class_init = altera_iic_class_init,
159
-};
160
-
161
-static void altera_iic_register(void)
162
-{
163
- type_register_static(&altera_iic_info);
164
-}
165
-
166
-type_init(altera_iic_register)
167
diff --git a/hw/nios2/10m50_devboard.c b/hw/nios2/10m50_devboard.c
168
index XXXXXXX..XXXXXXX 100644
169
--- a/hw/nios2/10m50_devboard.c
170
+++ b/hw/nios2/10m50_devboard.c
171
@@ -XXX,XX +XXX,XX @@ static void nios2_10m50_ghrd_init(MachineState *machine)
172
ram_addr_t tcm_size = 0x1000; /* 1 kiB, but QEMU limit is 4 kiB */
173
ram_addr_t ram_base = 0x08000000;
174
ram_addr_t ram_size = 0x08000000;
175
- qemu_irq *cpu_irq, irq[32];
176
+ qemu_irq irq[32];
177
int i;
178
179
/* Physical TCM (tb_ram_1k) with alias at 0xc0000000 */
180
@@ -XXX,XX +XXX,XX @@ static void nios2_10m50_ghrd_init(MachineState *machine)
181
182
/* Create CPU -- FIXME */
183
cpu = NIOS2_CPU(cpu_create(TYPE_NIOS2_CPU));
184
-
185
- /* Register: CPU interrupt controller (PIC) */
186
- cpu_irq = nios2_cpu_pic_init(cpu);
187
-
188
- /* Register: Internal Interrupt Controller (IIC) */
189
- dev = qdev_new("altera,iic");
190
- object_property_add_const_link(OBJECT(dev), "cpu", OBJECT(cpu));
191
- sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
192
- sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, cpu_irq[0]);
193
for (i = 0; i < 32; i++) {
194
- irq[i] = qdev_get_gpio_in(dev, i);
195
+ irq[i] = qdev_get_gpio_in_named(DEVICE(cpu), "IRQ", i);
196
}
42
}
197
43
};
198
/* Register: Altera 16550 UART */
44
199
diff --git a/hw/nios2/cpu_pic.c b/hw/nios2/cpu_pic.c
45
+static const int an536_oscclk[] = {
200
index XXXXXXX..XXXXXXX 100644
46
+ 24000000, /* 24MHz reference for RTC and timers */
201
--- a/hw/nios2/cpu_pic.c
47
+ 50000000, /* 50MHz ACLK */
202
+++ b/hw/nios2/cpu_pic.c
48
+ 50000000, /* 50MHz MCLK */
203
@@ -XXX,XX +XXX,XX @@
49
+ 50000000, /* 50MHz GPUCLK */
204
50
+ 24576000, /* 24.576MHz AUDCLK */
205
#include "boot.h"
51
+ 23750000, /* 23.75MHz HDLCDCLK */
206
52
+ 100000000, /* 100MHz DDR4_REF_CLK */
207
-static void nios2_pic_cpu_handler(void *opaque, int irq, int level)
53
+};
208
-{
54
+
209
- Nios2CPU *cpu = opaque;
55
static MemoryRegion *mr_for_raminfo(MPS3RMachineState *mms,
210
- CPUNios2State *env = &cpu->env;
56
const RAMInfo *raminfo)
211
- CPUState *cs = CPU(cpu);
212
- int type = irq ? CPU_INTERRUPT_NMI : CPU_INTERRUPT_HARD;
213
-
214
- if (type == CPU_INTERRUPT_HARD) {
215
- env->irq_pending = level;
216
-
217
- if (level && (env->regs[CR_STATUS] & CR_STATUS_PIE)) {
218
- env->irq_pending = 0;
219
- cpu_interrupt(cs, type);
220
- } else if (!level) {
221
- env->irq_pending = 0;
222
- cpu_reset_interrupt(cs, type);
223
- }
224
- } else {
225
- if (level) {
226
- cpu_interrupt(cs, type);
227
- } else {
228
- cpu_reset_interrupt(cs, type);
229
- }
230
- }
231
-}
232
-
233
void nios2_check_interrupts(CPUNios2State *env)
234
{
57
{
235
if (env->irq_pending &&
58
@@ -XXX,XX +XXX,XX @@ static void mps3r_common_init(MachineState *machine)
236
@@ -XXX,XX +XXX,XX @@ void nios2_check_interrupts(CPUNios2State *env)
59
MPS3RMachineClass *mmc = MPS3R_MACHINE_GET_CLASS(mms);
237
cpu_interrupt(env_cpu(env), CPU_INTERRUPT_HARD);
60
MemoryRegion *sysmem = get_system_memory();
61
DeviceState *gicdev;
62
+ QList *oscclk;
63
64
mms->clk = clock_new(OBJECT(machine), "CLK");
65
clock_set_hz(mms->clk, CLK_FRQ);
66
@@ -XXX,XX +XXX,XX @@ static void mps3r_common_init(MachineState *machine)
67
}
238
}
68
}
239
}
69
240
-
70
+ for (int i = 0; i < ARRAY_SIZE(mms->spi); i++) {
241
-qemu_irq *nios2_cpu_pic_init(Nios2CPU *cpu)
71
+ g_autofree char *s = g_strdup_printf("spi%d", i);
242
-{
72
+ hwaddr baseaddr = 0xe0104000 + i * 0x1000;
243
- return qemu_allocate_irqs(nios2_pic_cpu_handler, cpu, 2);
244
-}
245
diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c
246
index XXXXXXX..XXXXXXX 100644
247
--- a/target/nios2/cpu.c
248
+++ b/target/nios2/cpu.c
249
@@ -XXX,XX +XXX,XX @@ static void nios2_cpu_reset(DeviceState *dev)
250
#endif
251
}
252
253
+#ifndef CONFIG_USER_ONLY
254
+static void nios2_cpu_set_irq(void *opaque, int irq, int level)
255
+{
256
+ Nios2CPU *cpu = opaque;
257
+ CPUNios2State *env = &cpu->env;
258
+ CPUState *cs = CPU(cpu);
259
+
73
+
260
+ env->regs[CR_IPENDING] &= ~(1 << irq);
74
+ object_initialize_child(OBJECT(mms), s, &mms->spi[i], TYPE_PL022);
261
+ env->regs[CR_IPENDING] |= !!level << irq;
75
+ sysbus_realize(SYS_BUS_DEVICE(&mms->spi[i]), &error_fatal);
76
+ sysbus_mmio_map(SYS_BUS_DEVICE(&mms->spi[i]), 0, baseaddr);
77
+ sysbus_connect_irq(SYS_BUS_DEVICE(&mms->spi[i]), 0,
78
+ qdev_get_gpio_in(gicdev, 22 + i));
79
+ }
262
+
80
+
263
+ env->irq_pending = env->regs[CR_IPENDING] & env->regs[CR_IENABLE];
81
+ object_initialize_child(OBJECT(mms), "scc", &mms->scc, TYPE_MPS2_SCC);
82
+ qdev_prop_set_uint32(DEVICE(&mms->scc), "scc-cfg0", 0);
83
+ qdev_prop_set_uint32(DEVICE(&mms->scc), "scc-cfg4", 0x2);
84
+ qdev_prop_set_uint32(DEVICE(&mms->scc), "scc-aid", 0x00200008);
85
+ qdev_prop_set_uint32(DEVICE(&mms->scc), "scc-id", 0x41055360);
86
+ oscclk = qlist_new();
87
+ for (int i = 0; i < ARRAY_SIZE(an536_oscclk); i++) {
88
+ qlist_append_int(oscclk, an536_oscclk[i]);
89
+ }
90
+ qdev_prop_set_array(DEVICE(&mms->scc), "oscclk", oscclk);
91
+ sysbus_realize(SYS_BUS_DEVICE(&mms->scc), &error_fatal);
92
+ sysbus_mmio_map(SYS_BUS_DEVICE(&mms->scc), 0, 0xe0200000);
264
+
93
+
265
+ if (env->irq_pending && (env->regs[CR_STATUS] & CR_STATUS_PIE)) {
94
+ create_unimplemented_device("i2s-audio", 0xe0201000, 0x1000);
266
+ env->irq_pending = 0;
267
+ cpu_interrupt(cs, CPU_INTERRUPT_HARD);
268
+ } else if (!env->irq_pending) {
269
+ cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
270
+ }
271
+}
272
+#endif
273
+
95
+
274
static void nios2_cpu_initfn(Object *obj)
96
+ object_initialize_child(OBJECT(mms), "fpgaio", &mms->fpgaio,
275
{
97
+ TYPE_MPS2_FPGAIO);
276
Nios2CPU *cpu = NIOS2_CPU(obj);
98
+ qdev_prop_set_uint32(DEVICE(&mms->fpgaio), "prescale-clk", an536_oscclk[1]);
277
@@ -XXX,XX +XXX,XX @@ static void nios2_cpu_initfn(Object *obj)
99
+ qdev_prop_set_uint32(DEVICE(&mms->fpgaio), "num-leds", 10);
278
100
+ qdev_prop_set_bit(DEVICE(&mms->fpgaio), "has-switches", true);
279
#if !defined(CONFIG_USER_ONLY)
101
+ qdev_prop_set_bit(DEVICE(&mms->fpgaio), "has-dbgctrl", false);
280
mmu_init(&cpu->env);
102
+ sysbus_realize(SYS_BUS_DEVICE(&mms->fpgaio), &error_fatal);
103
+ sysbus_mmio_map(SYS_BUS_DEVICE(&mms->fpgaio), 0, 0xe0202000);
104
+
105
+ create_unimplemented_device("clcd", 0xe0209000, 0x1000);
106
+
107
+ object_initialize_child(OBJECT(mms), "rtc", &mms->rtc, TYPE_PL031);
108
+ sysbus_realize(SYS_BUS_DEVICE(&mms->rtc), &error_fatal);
109
+ sysbus_mmio_map(SYS_BUS_DEVICE(&mms->rtc), 0, 0xe020a000);
110
+ sysbus_connect_irq(SYS_BUS_DEVICE(&mms->rtc), 0,
111
+ qdev_get_gpio_in(gicdev, 4));
281
+
112
+
282
+ /*
113
+ /*
283
+ * These interrupt lines model the IIC (internal interrupt
114
+ * In hardware this is a LAN9220; the LAN9118 is software compatible
284
+ * controller). QEMU does not currently support the EIC
115
+ * except that it doesn't support the checksum-offload feature.
285
+ * (external interrupt controller) -- if we did it would be
286
+ * a separate device in hw/intc with a custom interface to
287
+ * the CPU, and boards using it would not wire up these IRQ lines.
288
+ */
116
+ */
289
+ qdev_init_gpio_in_named(DEVICE(cpu), nios2_cpu_set_irq, "IRQ", 32);
117
+ lan9118_init(0xe0300000,
290
#endif
118
+ qdev_get_gpio_in(gicdev, 18));
291
}
119
+
292
120
+ create_unimplemented_device("usb", 0xe0301000, 0x1000);
293
diff --git a/MAINTAINERS b/MAINTAINERS
121
+ create_unimplemented_device("qspi-write-config", 0xe0600000, 0x1000);
294
index XXXXXXX..XXXXXXX 100644
122
+
295
--- a/MAINTAINERS
123
mms->bootinfo.ram_size = machine->ram_size;
296
+++ b/MAINTAINERS
124
mms->bootinfo.board_id = -1;
297
@@ -XXX,XX +XXX,XX @@ M: Marek Vasut <marex@denx.de>
125
mms->bootinfo.loader_start = mmc->loader_start;
298
S: Maintained
299
F: target/nios2/
300
F: hw/nios2/
301
-F: hw/intc/nios2_iic.c
302
F: disas/nios2.c
303
F: default-configs/nios2-softmmu.mak
304
305
diff --git a/hw/intc/meson.build b/hw/intc/meson.build
306
index XXXXXXX..XXXXXXX 100644
307
--- a/hw/intc/meson.build
308
+++ b/hw/intc/meson.build
309
@@ -XXX,XX +XXX,XX @@ specific_ss.add(when: 'CONFIG_IBEX', if_true: files('ibex_plic.c'))
310
specific_ss.add(when: 'CONFIG_IOAPIC', if_true: files('ioapic.c'))
311
specific_ss.add(when: 'CONFIG_LOONGSON_LIOINTC', if_true: files('loongson_liointc.c'))
312
specific_ss.add(when: 'CONFIG_MIPS_CPS', if_true: files('mips_gic.c'))
313
-specific_ss.add(when: 'CONFIG_NIOS2', if_true: files('nios2_iic.c'))
314
specific_ss.add(when: 'CONFIG_OMAP', if_true: files('omap_intc.c'))
315
specific_ss.add(when: 'CONFIG_OMPIC', if_true: files('ompic.c'))
316
specific_ss.add(when: 'CONFIG_OPENPIC_KVM', if_true: files('openpic_kvm.c'))
317
--
126
--
318
2.20.1
127
2.34.1
319
128
320
129
diff view generated by jsdifflib
[PULL 02/20] hw/openrisc/openrisc_sim: Use IRQ splitter when connecting IRQ to multiple CPUs
[PULL 35/35] docs: Add documentation for the mps3-an536 board
1
openrisc_sim_net_init() attempts to connect the IRQ line from the
1
Add documentation for the mps3-an536 board type.
2
ethernet device to both CPUs in an SMP configuration by simply caling
3
sysbus_connect_irq() for it twice. This doesn't work, because the
4
second connection simply overrides the first.
5
6
Fix this by creating a TYPE_SPLIT_IRQ to split the IRQ in the SMP
7
case.
8
2
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Stafford Horne <shorne@gmail.com>
4
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
11
Message-id: 20201127225127.14770-2-peter.maydell@linaro.org
5
Message-id: 20240206132931.38376-14-peter.maydell@linaro.org
12
---
6
---
13
hw/openrisc/openrisc_sim.c | 13 +++++++++++--
7
docs/system/arm/mps2.rst | 37 ++++++++++++++++++++++++++++++++++---
14
hw/openrisc/Kconfig | 1 +
8
1 file changed, 34 insertions(+), 3 deletions(-)
15
2 files changed, 12 insertions(+), 2 deletions(-)
16
9
17
diff --git a/hw/openrisc/openrisc_sim.c b/hw/openrisc/openrisc_sim.c
10
diff --git a/docs/system/arm/mps2.rst b/docs/system/arm/mps2.rst
18
index XXXXXXX..XXXXXXX 100644
11
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/openrisc/openrisc_sim.c
12
--- a/docs/system/arm/mps2.rst
20
+++ b/hw/openrisc/openrisc_sim.c
13
+++ b/docs/system/arm/mps2.rst
21
@@ -XXX,XX +XXX,XX @@
14
@@ -XXX,XX +XXX,XX @@
22
#include "hw/sysbus.h"
15
-Arm MPS2 and MPS3 boards (``mps2-an385``, ``mps2-an386``, ``mps2-an500``, ``mps2-an505``, ``mps2-an511``, ``mps2-an521``, ``mps3-an524``, ``mps3-an547``)
23
#include "sysemu/qtest.h"
16
-=========================================================================================================================================================
24
#include "sysemu/reset.h"
17
+Arm MPS2 and MPS3 boards (``mps2-an385``, ``mps2-an386``, ``mps2-an500``, ``mps2-an505``, ``mps2-an511``, ``mps2-an521``, ``mps3-an524``, ``mps3-an536``, ``mps3-an547``)
25
+#include "hw/core/split-irq.h"
18
+=========================================================================================================================================================================
26
19
27
#define KERNEL_LOAD_ADDR 0x100
20
-These board models all use Arm M-profile CPUs.
28
21
+These board models use Arm M-profile or R-profile CPUs.
29
@@ -XXX,XX +XXX,XX @@ static void openrisc_sim_net_init(hwaddr base, hwaddr descriptors,
22
30
23
The Arm MPS2, MPS2+ and MPS3 dev boards are FPGA based (the 2+ has a
31
s = SYS_BUS_DEVICE(dev);
24
bigger FPGA but is otherwise the same as the 2; the 3 has a bigger
32
sysbus_realize_and_unref(s, &error_fatal);
25
@@ -XXX,XX +XXX,XX @@ FPGA image.
33
- for (i = 0; i < num_cpus; i++) {
26
34
- sysbus_connect_irq(s, 0, cpu_irqs[i][irq_pin]);
27
QEMU models the following FPGA images:
35
+ if (num_cpus > 1) {
28
36
+ DeviceState *splitter = qdev_new(TYPE_SPLIT_IRQ);
29
+FPGA images using M-profile CPUs:
37
+ qdev_prop_set_uint32(splitter, "num-lines", num_cpus);
30
+
38
+ qdev_realize_and_unref(splitter, NULL, &error_fatal);
31
``mps2-an385``
39
+ for (i = 0; i < num_cpus; i++) {
32
Cortex-M3 as documented in Arm Application Note AN385
40
+ qdev_connect_gpio_out(splitter, i, cpu_irqs[i][irq_pin]);
33
``mps2-an386``
41
+ }
34
@@ -XXX,XX +XXX,XX @@ QEMU models the following FPGA images:
42
+ sysbus_connect_irq(s, 0, qdev_get_gpio_in(splitter, 0));
35
``mps3-an547``
43
+ } else {
36
Cortex-M55 on an MPS3, as documented in Arm Application Note AN547
44
+ sysbus_connect_irq(s, 0, cpu_irqs[0][irq_pin]);
37
45
}
38
+FPGA images using R-profile CPUs:
46
sysbus_mmio_map(s, 0, base);
39
+
47
sysbus_mmio_map(s, 1, descriptors);
40
+``mps3-an536``
48
diff --git a/hw/openrisc/Kconfig b/hw/openrisc/Kconfig
41
+ Dual Cortex-R52 on an MPS3, as documented in Arm Application Note AN536
49
index XXXXXXX..XXXXXXX 100644
42
+
50
--- a/hw/openrisc/Kconfig
43
Differences between QEMU and real hardware:
51
+++ b/hw/openrisc/Kconfig
44
52
@@ -XXX,XX +XXX,XX @@ config OR1K_SIM
45
- AN385/AN386 remapping of low 16K of memory to either ZBT SSRAM1 or to
53
select SERIAL
46
@@ -XXX,XX +XXX,XX @@ Differences between QEMU and real hardware:
54
select OPENCORES_ETH
47
flash, but only as simple ROM, so attempting to rewrite the flash
55
select OMPIC
48
from the guest will fail
56
+ select SPLIT_IRQ
49
- QEMU does not model the USB controller in MPS3 boards
50
+- AN536 does not support runtime control of CPU reset and halt via
51
+ the SCC CFG_REG0 register.
52
+- AN536 does not support enabling or disabling the flash and ATCM
53
+ interfaces via the SCC CFG_REG1 register.
54
+- AN536 does not support setting of the initial vector table
55
+ base address via the SCC CFG_REG6 and CFG_REG7 register config,
56
+ and does not provide a mechanism for specifying these values at
57
+ startup, so all guest images must be built to start from TCM
58
+ (i.e. to expect the interrupt vector base at 0 from reset).
59
+- AN536 defaults to only creating a single CPU; this is the equivalent
60
+ of the way the real FPGA image usually runs with the second Cortex-R52
61
+ held in halt via the initial SCC CFG_REG0 register setting. You can
62
+ create the second CPU with ``-smp 2``; both CPUs will then start
63
+ execution immediately on startup.
64
+
65
+Note that for the AN536 the first UART is accessible only by
66
+CPU0, and the second UART is accessible only by CPU1. The
67
+first UART accessible shared between both CPUs is the third
68
+UART. Guest software might therefore be built to use either
69
+the first UART or the third UART; if you don't see any output
70
+from the UART you are looking at, try one of the others.
71
+(Even if the AN536 machine is started with a single CPU and so
72
+no "CPU1-only UART", the UART numbering remains the same,
73
+with the third UART being the first of the shared ones.)
74
75
Machine-specific options
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""""""""""""""""""""""""
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--
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--
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2.20.1
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2.34.1
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