A grab-bag of minor stuff for the end of the year. My to-review

queue is not empty, but it it at least in single figures...

The following changes since commit 5bfbd8170ce7acb98a1834ff49ed7340b0837144:

Merge remote-tracking branch 'remotes/vivier2/tags/trivial-branch-for-6.0-pull-request' into staging (2020-12-14 20:32:38 +0000)

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20201215

for you to fetch changes up to 23af268566069183285bebbdf95b1b37cb7c0942:

hw/block/m25p80: Fix Numonyx fast read dummy cycle count (2020-12-15 13:39:30 +0000)

* gdbstub: Correct misparsing of vCont C/S requests

* openrisc: Move pic_cpu code into CPU object proper

* nios2: Move IIC code into CPU object proper

* Improve reporting of ROM overlap errors

* xlnx-versal: Add USB support

* hw/misc/zynq_slcr: Avoid #DIV/0! error

* Numonyx: Fix dummy cycles and check for SPI mode on cmds

Joe Komlodi (4):

hw/block/m25p80: Make Numonyx config field names more accurate

hw/block/m25p80: Fix when VCFG XIP bit is set for Numonyx

hw/block/m25p80: Check SPI mode before running some Numonyx commands

hw/block/m25p80: Fix Numonyx fast read dummy cycle count

Peter Maydell (11):

gdbstub: Correct misparsing of vCont C/S requests

hw/openrisc/openrisc_sim: Use IRQ splitter when connecting IRQ to multiple CPUs

hw/openrisc/openrisc_sim: Abstract out "get IRQ x of CPU y"

target/openrisc: Move pic_cpu code into CPU object proper

target/nios2: Move IIC code into CPU object proper

target/nios2: Move nios2_check_interrupts() into target/nios2

target/nios2: Use deposit32() to update ipending register

hw/core/loader.c: Track last-seen ROM in rom_check_and_register_reset()

hw/core/loader.c: Improve reporting of ROM overlap errors

elf_ops.h: Don't truncate name of the ROM blobs we create

elf_ops.h: Be more verbose with ROM blob names

Philippe Mathieu-Daudé (1):

hw/misc/zynq_slcr: Avoid #DIV/0! error

Sai Pavan Boddu (2):

usb: Add versal-usb2-ctrl-regs module

usb: xlnx-usb-subsystem: Add xilinx usb subsystem

Vikram Garhwal (2):

usb: Add DWC3 model

arm: xlnx-versal: Connect usb to virt-versal

include/hw/arm/xlnx-versal.h | 9 +

include/hw/elf_ops.h | 5 +-

include/hw/usb/hcd-dwc3.h | 55 +++

include/hw/usb/xlnx-usb-subsystem.h | 45 ++

include/hw/usb/xlnx-versal-usb2-ctrl-regs.h | 45 ++

target/nios2/cpu.h | 3 -

target/openrisc/cpu.h | 1 -

gdbstub.c | 2 +-

hw/arm/xlnx-versal-virt.c | 55 +++

hw/arm/xlnx-versal.c | 26 ++

hw/block/m25p80.c | 158 +++++--

hw/core/loader.c | 67 ++-

hw/intc/nios2_iic.c | 95 ----

hw/misc/zynq_slcr.c | 5 +

hw/nios2/10m50_devboard.c | 13 +-

hw/nios2/cpu_pic.c | 67 ---

hw/openrisc/openrisc_sim.c | 46 +-

hw/openrisc/pic_cpu.c | 61 ---

hw/usb/hcd-dwc3.c | 689 ++++++++++++++++++++++++++++

hw/usb/xlnx-usb-subsystem.c | 94 ++++

hw/usb/xlnx-versal-usb2-ctrl-regs.c | 229 +++++++++

softmmu/vl.c | 1 -

target/nios2/cpu.c | 29 ++

target/nios2/op_helper.c | 9 +

target/openrisc/cpu.c | 32 ++

MAINTAINERS | 1 -

hw/intc/meson.build | 1 -

hw/nios2/meson.build | 2 +-

hw/openrisc/Kconfig | 1 +

hw/openrisc/meson.build | 2 +-

hw/usb/Kconfig | 10 +

hw/usb/meson.build | 3 +

32 files changed, 1557 insertions(+), 304 deletions(-)

create mode 100644 include/hw/usb/hcd-dwc3.h

create mode 100644 include/hw/usb/xlnx-usb-subsystem.h

create mode 100644 include/hw/usb/xlnx-versal-usb2-ctrl-regs.h

delete mode 100644 hw/intc/nios2_iic.c

delete mode 100644 hw/nios2/cpu_pic.c

delete mode 100644 hw/openrisc/pic_cpu.c

create mode 100644 hw/usb/hcd-dwc3.c

create mode 100644 hw/usb/xlnx-usb-subsystem.c

create mode 100644 hw/usb/xlnx-versal-usb2-ctrl-regs.c

From: Philippe Mathieu-Daudé <f4bug@amsat.org>

Malicious user can set the feedback divisor for the PLLs

to zero, triggering a floating-point exception (SIGFPE).

As the datasheet [*] is not clear how hardware behaves

when these bits are zeroes, use the maximum divisor

possible (128) to avoid the software FPE.

[*] Zynq-7000 TRM, UG585 (v1.12.2)

B.28 System Level Control Registers (slcr)

-> "Register (slcr) ARM_PLL_CTRL"

25.10.4 PLLs

-> "Software-Controlled PLL Update"

Fixes: 38867cb7ec9 ("hw/misc/zynq_slcr: add clock generation for uarts")

Reported-by: Gaoning Pan <pgn@zju.edu.cn>

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>

Reviewed-by: Damien Hedde <damien.hedde@greensocs.com>

Message-id: 20201210141610.884600-1-f4bug@amsat.org

hw/misc/zynq_slcr.c | 5 +++++

1 file changed, 5 insertions(+)

diff --git a/hw/misc/zynq_slcr.c b/hw/misc/zynq_slcr.c

--- a/hw/misc/zynq_slcr.c

+++ b/hw/misc/zynq_slcr.c

@@ -XXX,XX +XXX,XX @@ static uint64_t zynq_slcr_compute_pll(uint64_t input, uint32_t ctrl_reg)

return 0;

+ /* Consider zero feedback as maximum divide ratio possible */

+ if (!mult) {

+ mult = 1 << R_xxx_PLL_CTRL_PLL_FPDIV_LENGTH;

+ }

+

/* frequency multiplier -> period division */

return input / mult;

}

Instead of making the ROM blob name something like:

phdr #0: /home/petmay01/linaro/qemu-misc-tests/ldmia-fault.axf

make it a little more self-explanatory for people who don't know

ELF format details:

/home/petmay01/linaro/qemu-misc-tests/ldmia-fault.axf ELF program header segment 0

Message-id: 20201129203923.10622-5-peter.maydell@linaro.org

include/hw/elf_ops.h | 3 ++-

1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/include/hw/elf_ops.h b/include/hw/elf_ops.h

--- a/include/hw/elf_ops.h

+++ b/include/hw/elf_ops.h

@@ -XXX,XX +XXX,XX @@ static int glue(load_elf, SZ)(const char *name, int fd,

if (mem_size != 0) {

if (load_rom) {

g_autofree char *label =

- g_strdup_printf("phdr #%d: %s", i, name);

+ g_strdup_printf("%s ELF program header segment %d",

+ name, i);

/*

* rom_add_elf_program() takes its own reference to

We're about to refactor the OpenRISC pic_cpu code in a way that means

that just grabbing the whole qemu_irq[] array of inbound IRQs for a

CPU won't be possible any more. Abstract out a function for "return

the qemu_irq for IRQ x input of CPU y" so we can more easily replace

the implementation.

Reviewed-by: Stafford Horne <shorne@gmail.com>

Message-id: 20201127225127.14770-3-peter.maydell@linaro.org

hw/openrisc/openrisc_sim.c | 38 +++++++++++++++++++++-----------------

1 file changed, 21 insertions(+), 17 deletions(-)

diff --git a/hw/openrisc/openrisc_sim.c b/hw/openrisc/openrisc_sim.c

--- a/hw/openrisc/openrisc_sim.c

+++ b/hw/openrisc/openrisc_sim.c

@@ -XXX,XX +XXX,XX @@ static void main_cpu_reset(void *opaque)

cpu_set_pc(cs, boot_info.bootstrap_pc);

+static qemu_irq get_cpu_irq(OpenRISCCPU *cpus[], int cpunum, int irq_pin)

+ return cpus[cpunum]->env.irq[irq_pin];

static void openrisc_sim_net_init(hwaddr base, hwaddr descriptors,

- int num_cpus, qemu_irq **cpu_irqs,

+ int num_cpus, OpenRISCCPU *cpus[],

int irq_pin, NICInfo *nd)

DeviceState *dev;

@@ -XXX,XX +XXX,XX @@ static void openrisc_sim_net_init(hwaddr base, hwaddr descriptors,

qdev_prop_set_uint32(splitter, "num-lines", num_cpus);

qdev_realize_and_unref(splitter, NULL, &error_fatal);

for (i = 0; i < num_cpus; i++) {

- qdev_connect_gpio_out(splitter, i, cpu_irqs[i][irq_pin]);

+ qdev_connect_gpio_out(splitter, i, get_cpu_irq(cpus, i, irq_pin));

}

sysbus_connect_irq(s, 0, qdev_get_gpio_in(splitter, 0));

} else {

- sysbus_connect_irq(s, 0, cpu_irqs[0][irq_pin]);

+ sysbus_connect_irq(s, 0, get_cpu_irq(cpus, 0, irq_pin));

sysbus_mmio_map(s, 0, base);

sysbus_mmio_map(s, 1, descriptors);

static void openrisc_sim_ompic_init(hwaddr base, int num_cpus,

- qemu_irq **cpu_irqs, int irq_pin)

+ OpenRISCCPU *cpus[], int irq_pin)

DeviceState *dev;

SysBusDevice *s;

@@ -XXX,XX +XXX,XX @@ static void openrisc_sim_ompic_init(hwaddr base, int num_cpus,

s = SYS_BUS_DEVICE(dev);

sysbus_realize_and_unref(s, &error_fatal);

for (i = 0; i < num_cpus; i++) {

- sysbus_connect_irq(s, i, cpu_irqs[i][irq_pin]);

+ sysbus_connect_irq(s, i, get_cpu_irq(cpus, i, irq_pin));

sysbus_mmio_map(s, 0, base);

@@ -XXX,XX +XXX,XX @@ static void openrisc_sim_init(MachineState *machine)

{

ram_addr_t ram_size = machine->ram_size;

const char *kernel_filename = machine->kernel_filename;

- OpenRISCCPU *cpu = NULL;

+ OpenRISCCPU *cpus[2] = {};

MemoryRegion *ram;

- qemu_irq *cpu_irqs[2];

qemu_irq serial_irq;

int n;

unsigned int smp_cpus = machine->smp.cpus;

assert(smp_cpus >= 1 && smp_cpus <= 2);

for (n = 0; n < smp_cpus; n++) {

- cpu = OPENRISC_CPU(cpu_create(machine->cpu_type));

- if (cpu == NULL) {

+ cpus[n] = OPENRISC_CPU(cpu_create(machine->cpu_type));

+ if (cpus[n] == NULL) {

fprintf(stderr, "Unable to find CPU definition!\n");

exit(1);

}

- cpu_openrisc_pic_init(cpu);

- cpu_irqs[n] = (qemu_irq *) cpu->env.irq;

+ cpu_openrisc_pic_init(cpus[n]);

- cpu_openrisc_clock_init(cpu);

+ cpu_openrisc_clock_init(cpus[n]);

- qemu_register_reset(main_cpu_reset, cpu);

+ qemu_register_reset(main_cpu_reset, cpus[n]);

}

ram = g_malloc(sizeof(*ram));

@@ -XXX,XX +XXX,XX @@ static void openrisc_sim_init(MachineState *machine)

if (nd_table[0].used) {

openrisc_sim_net_init(0x92000000, 0x92000400, smp_cpus,

- cpu_irqs, 4, nd_table);

+ cpus, 4, nd_table);

}

if (smp_cpus > 1) {

- openrisc_sim_ompic_init(0x98000000, smp_cpus, cpu_irqs, 1);

+ openrisc_sim_ompic_init(0x98000000, smp_cpus, cpus, 1);

- serial_irq = qemu_irq_split(cpu_irqs[0][2], cpu_irqs[1][2]);

+ serial_irq = qemu_irq_split(get_cpu_irq(cpus, 0, 2),

+ get_cpu_irq(cpus, 1, 2));

} else {

- serial_irq = cpu_irqs[0][2];

+ serial_irq = get_cpu_irq(cpus, 0, 2);

}

serial_mm_init(get_system_memory(), 0x90000000, 0, serial_irq,

In rom_check_and_register_reset() we detect overlaps by looking at

whether the ROM blob we're currently examining is in the same address

space and starts before the previous ROM blob ends. (This works

because the ROM list is kept sorted in order by AddressSpace and then

by address.)

Instead of keeping the AddressSpace and last address of the previous ROM

blob in local variables, just keep a pointer to it.

This will allow us to print more useful information when we do detect

an overlap.

Message-id: 20201129203923.10622-2-peter.maydell@linaro.org

hw/core/loader.c | 23 +++++++++++++++--------

1 file changed, 15 insertions(+), 8 deletions(-)

diff --git a/hw/core/loader.c b/hw/core/loader.c

--- a/hw/core/loader.c

+++ b/hw/core/loader.c

@@ -XXX,XX +XXX,XX @@ static void rom_reset(void *unused)

}

+/* Return true if two consecutive ROMs in the ROM list overlap */

+static bool roms_overlap(Rom *last_rom, Rom *this_rom)

+ if (!last_rom) {

+ return false;

+ }

+ return last_rom->as == this_rom->as &&

+ last_rom->addr + last_rom->romsize > this_rom->addr;

int rom_check_and_register_reset(void)

{

- hwaddr addr = 0;

MemoryRegionSection section;

- Rom *rom;

- AddressSpace *as = NULL;

+ Rom *rom, *last_rom = NULL;

QTAILQ_FOREACH(rom, &roms, next) {

if (rom->fw_file) {

continue;

}

if (!rom->mr) {

- if ((addr > rom->addr) && (as == rom->as)) {

+ if (roms_overlap(last_rom, rom)) {

fprintf(stderr, "rom: requested regions overlap "

"(rom %s. free=0x" TARGET_FMT_plx

", addr=0x" TARGET_FMT_plx ")\n",

- rom->name, addr, rom->addr);

+ rom->name, last_rom->addr + last_rom->romsize,

+ rom->addr);

return -1;

}

- addr = rom->addr;

- addr += rom->romsize;

- as = rom->as;

+ last_rom = rom;

}

section = memory_region_find(rom->mr ? rom->mr : get_system_memory(),

rom->addr, 1);

Currently the load_elf code assembles the ROM blob name into a

local 128 byte fixed-size array. Use g_strdup_printf() instead so

that we don't truncate the pathname if it happens to be long.

(This matters mostly for monitor 'info roms' output and for the

error messages if ROM blobs overlap.)

Message-id: 20201129203923.10622-4-peter.maydell@linaro.org

include/hw/elf_ops.h | 4 ++--

1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/include/hw/elf_ops.h b/include/hw/elf_ops.h

--- a/include/hw/elf_ops.h

+++ b/include/hw/elf_ops.h

@@ -XXX,XX +XXX,XX @@ static int glue(load_elf, SZ)(const char *name, int fd,

uint64_t addr, low = (uint64_t)-1, high = 0;

GMappedFile *mapped_file = NULL;

uint8_t *data = NULL;

- char label[128];

int ret = ELF_LOAD_FAILED;

if (read(fd, &ehdr, sizeof(ehdr)) != sizeof(ehdr))

@@ -XXX,XX +XXX,XX @@ static int glue(load_elf, SZ)(const char *name, int fd,

*/

if (mem_size != 0) {

if (load_rom) {

- snprintf(label, sizeof(label), "phdr #%d: %s", i, name);

+ g_autofree char *label =

+ g_strdup_printf("phdr #%d: %s", i, name);

/*

* rom_add_elf_program() takes its own reference to

In nios2_cpu_set_irq(), use deposit32() rather than raw shift-and-mask

operations to set the appropriate bit in the ipending register.

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

Message-id: 20201129174022.26530-4-peter.maydell@linaro.org

target/nios2/cpu.c | 3 +--

1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c

--- a/target/nios2/cpu.c

+++ b/target/nios2/cpu.c

@@ -XXX,XX +XXX,XX @@ static void nios2_cpu_set_irq(void *opaque, int irq, int level)

CPUNios2State *env = &cpu->env;

CPUState *cs = CPU(cpu);

- env->regs[CR_IPENDING] &= ~(1 << irq);

- env->regs[CR_IPENDING] |= !!level << irq;

+ env->regs[CR_IPENDING] = deposit32(env->regs[CR_IPENDING], irq, 1, !!level);

env->irq_pending = env->regs[CR_IPENDING] & env->regs[CR_IENABLE];

From: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>

This model is a top level integration wrapper for hcd-dwc3 and

versal-usb2-ctrl-regs modules, this is used by xilinx versal soc's and

future xilinx usb subsystems would also be part of it.

Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>

Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

Message-id: 1607023357-5096-4-git-send-email-sai.pavan.boddu@xilinx.com

include/hw/usb/xlnx-usb-subsystem.h | 45 ++++++++++++++

hw/usb/xlnx-usb-subsystem.c | 94 +++++++++++++++++++++++++++++

hw/usb/Kconfig | 5 ++

hw/usb/meson.build | 1 +

4 files changed, 145 insertions(+)

create mode 100644 include/hw/usb/xlnx-usb-subsystem.h

create mode 100644 hw/usb/xlnx-usb-subsystem.c

diff --git a/include/hw/usb/xlnx-usb-subsystem.h b/include/hw/usb/xlnx-usb-subsystem.h

+++ b/include/hw/usb/xlnx-usb-subsystem.h

+/*

+ * QEMU model of the Xilinx usb subsystem

+ *

+ * Copyright (c) 2020 Xilinx Inc. Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>

+ *

+ * Permission is hereby granted, free of charge, to any person obtaining a copy

+ * of this software and associated documentation files (the "Software"), to deal

+ * in the Software without restriction, including without limitation the rights

+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell

+ * copies of the Software, and to permit persons to whom the Software is

+ * furnished to do so, subject to the following conditions:

+ *

+ * The above copyright notice and this permission notice shall be included in

+ * all copies or substantial portions of the Software.

+ *

+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL

+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER

+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,

+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN

+ * THE SOFTWARE.

+ */

+#ifndef _XLNX_VERSAL_USB_SUBSYSTEM_H_

+#define _XLNX_VERSAL_USB_SUBSYSTEM_H_

+

+#include "hw/usb/xlnx-versal-usb2-ctrl-regs.h"

+#include "hw/usb/hcd-dwc3.h"

+

+#define TYPE_XILINX_VERSAL_USB2 "xlnx.versal-usb2"

+

+#define VERSAL_USB2(obj) \

+ OBJECT_CHECK(VersalUsb2, (obj), TYPE_XILINX_VERSAL_USB2)

+

+typedef struct VersalUsb2 {

+ SysBusDevice parent_obj;

+ MemoryRegion dwc3_mr;

+ MemoryRegion usb2Ctrl_mr;

+

+ VersalUsb2CtrlRegs usb2Ctrl;

+ USBDWC3 dwc3;

+} VersalUsb2;

+

+#endif

diff --git a/hw/usb/xlnx-usb-subsystem.c b/hw/usb/xlnx-usb-subsystem.c

new file mode 100644

index XXXXXXX..XXXXXXX

--- /dev/null

+++ b/hw/usb/xlnx-usb-subsystem.c

@@ -XXX,XX +XXX,XX @@

+/*

+ * QEMU model of the Xilinx usb subsystem

+ *

+ * Copyright (c) 2020 Xilinx Inc. Sai Pavan Boddu <sai.pava.boddu@xilinx.com>

+ *

+ * Permission is hereby granted, free of charge, to any person obtaining a copy

+ * of this software and associated documentation files (the "Software"), to deal

+ * in the Software without restriction, including without limitation the rights

+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell

+ * copies of the Software, and to permit persons to whom the Software is

+ * furnished to do so, subject to the following conditions:

+ *

+ * The above copyright notice and this permission notice shall be included in

+ * all copies or substantial portions of the Software.

+ *

+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL

+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER

+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,

+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN

+ * THE SOFTWARE.

+ */

+

+#include "qemu/osdep.h"

+#include "hw/sysbus.h"

+#include "hw/irq.h"

+#include "hw/register.h"

+#include "qemu/bitops.h"

+#include "qemu/log.h"

+#include "qom/object.h"

+#include "qapi/error.h"

+#include "hw/qdev-properties.h"

+#include "hw/usb/xlnx-usb-subsystem.h"

+

+static void versal_usb2_realize(DeviceState *dev, Error **errp)

+{

+ VersalUsb2 *s = VERSAL_USB2(dev);

+ SysBusDevice *sbd = SYS_BUS_DEVICE(dev);

+ Error *err = NULL;

+

+ sysbus_realize(SYS_BUS_DEVICE(&s->dwc3), &err);

+ if (err) {

+ error_propagate(errp, err);

+ return;

+ }

+ sysbus_realize(SYS_BUS_DEVICE(&s->usb2Ctrl), &err);

+ if (err) {

+ error_propagate(errp, err);

+ return;

+ }

+ sysbus_init_mmio(sbd, &s->dwc3_mr);

+ sysbus_init_mmio(sbd, &s->usb2Ctrl_mr);

+ qdev_pass_gpios(DEVICE(&s->dwc3.sysbus_xhci), dev, SYSBUS_DEVICE_GPIO_IRQ);

+}

+

+static void versal_usb2_init(Object *obj)

+{

+ VersalUsb2 *s = VERSAL_USB2(obj);

+

+ object_initialize_child(obj, "versal.dwc3", &s->dwc3,

+ TYPE_USB_DWC3);

+ object_initialize_child(obj, "versal.usb2-ctrl", &s->usb2Ctrl,

+ TYPE_XILINX_VERSAL_USB2_CTRL_REGS);

+ memory_region_init_alias(&s->dwc3_mr, obj, "versal.dwc3_alias",

+ &s->dwc3.iomem, 0, DWC3_SIZE);

+ memory_region_init_alias(&s->usb2Ctrl_mr, obj, "versal.usb2Ctrl_alias",

+ &s->usb2Ctrl.iomem, 0, USB2_REGS_R_MAX * 4);

+ qdev_alias_all_properties(DEVICE(&s->dwc3), obj);

+ qdev_alias_all_properties(DEVICE(&s->dwc3.sysbus_xhci), obj);

+ object_property_add_alias(obj, "dma", OBJECT(&s->dwc3.sysbus_xhci), "dma");

+}

+

+static void versal_usb2_class_init(ObjectClass *klass, void *data)

+{

+ DeviceClass *dc = DEVICE_CLASS(klass);

+

+ dc->realize = versal_usb2_realize;

+}

+

+static const TypeInfo versal_usb2_info = {

+ .name = TYPE_XILINX_VERSAL_USB2,

+ .parent = TYPE_SYS_BUS_DEVICE,

+ .instance_size = sizeof(VersalUsb2),

+ .class_init = versal_usb2_class_init,

+ .instance_init = versal_usb2_init,

+};

+

+static void versal_usb_types(void)

+{

+ type_register_static(&versal_usb2_info);

+}

+

+type_init(versal_usb_types)

diff --git a/hw/usb/Kconfig b/hw/usb/Kconfig

index XXXXXXX..XXXXXXX 100644

--- a/hw/usb/Kconfig

+++ b/hw/usb/Kconfig

@@ -XXX,XX +XXX,XX @@ config USB_DWC3

bool

select USB_XHCI_SYSBUS

select REGISTER

+

+config XLNX_USB_SUBSYS

+ bool

+ default y if XLNX_VERSAL

+ select USB_DWC3

diff --git a/hw/usb/meson.build b/hw/usb/meson.build

index XXXXXXX..XXXXXXX 100644

--- a/hw/usb/meson.build

+++ b/hw/usb/meson.build

@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_TUSB6010', if_true: files('tusb6010.c'))

softmmu_ss.add(when: 'CONFIG_IMX', if_true: files('chipidea.c'))

softmmu_ss.add(when: 'CONFIG_IMX_USBPHY', if_true: files('imx-usb-phy.c'))

specific_ss.add(when: 'CONFIG_XLNX_VERSAL', if_true: files('xlnx-versal-usb2-ctrl-regs.c'))

+specific_ss.add(when: 'CONFIG_XLNX_USB_SUBSYS', if_true: files('xlnx-usb-subsystem.c'))

# emulated usb devices

softmmu_ss.add(when: 'CONFIG_USB', if_true: files('dev-hub.c'))

The Nios2 architecture supports two different interrupt controller

options:

* The IIC (Internal Interrupt Controller) is part of the CPU itself;

it has 32 IRQ input lines and no NMI support. Interrupt status is

queried and controlled via the CPU's ipending and istatus

registers.