Enable support for FEAT_TLBIOS and FEAT_TLBIRANGE by setting
ID_AA64ISAR0.TLB to 2 for the max AARCH64 CPU type.

Signed-off-by: Rebecca Cran <rebecca@nuviainc.com>
---
 target/arm/cpu64.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index 649213082ff9..4b9c5887cc1c 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -620,6 +620,7 @@ static void aarch64_max_initfn(Object *obj)
         t = FIELD_DP64(t, ID_AA64ISAR0, DP, 1);
         t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 1);
         t = FIELD_DP64(t, ID_AA64ISAR0, TS, 2); /* v8.5-CondM */
+        t = FIELD_DP64(t, ID_AA64ISAR0, TLB, 2);
         t = FIELD_DP64(t, ID_AA64ISAR0, RNDR, 1);
         cpu->isar.id_aa64isar0 = t;
 
-- 
2.26.2

On 12/14/20 2:23 PM, Rebecca Cran wrote:
> +++ b/target/arm/cpu64.c
> @@ -620,6 +620,7 @@ static void aarch64_max_initfn(Object *obj)
>          t = FIELD_DP64(t, ID_AA64ISAR0, DP, 1);
>          t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 1);
>          t = FIELD_DP64(t, ID_AA64ISAR0, TS, 2); /* v8.5-CondM */
> +        t = FIELD_DP64(t, ID_AA64ISAR0, TLB, 2);
>          t = FIELD_DP64(t, ID_AA64ISAR0, RNDR, 1);

When the value is not 1, we have generally added a comment to clarify exactly
which extensions this covers.  Though it's slightly annoying that F.c has
renamed all of the extensions.

With that added,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


r~

On Tue, 15 Dec 2020 at 21:53, Richard Henderson
<richard.henderson@linaro.org> wrote:
> Though it's slightly annoying that F.c has
> renamed all of the extensions.

It's in a good cause, which is to say it avoids the previous
irritating ambiguity where you had some duplication between
v8.x-Foo and v8.y-Foo that meant "Foo" alone wasn't a unique
identifier for the extension.

thanks
-- PMM