[PULL 0/3] tcg patch queue
[PULL 00/42] tcg patch queue
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The following changes since commit 2ecfc0657afa5d29a373271b342f704a1a3c6737:
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The following changes since commit a9fe9e191b4305b88c356a1ed9ac3baf89eb18aa:
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Merge remote-tracking branch 'remotes/armbru/tags/pull-misc-2020-12-10' into staging (2020-12-10 17:01:05 +0000)
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Merge tag 'pull-riscv-to-apply-20230505-1' of https://github.com/alistair23/qemu into staging (2023-05-05 09:25:13 +0100)
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are available in the Git repository at:
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are available in the Git repository at:
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https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20201210
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https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20230505
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for you to fetch changes up to 9e2658d62ebc23efe7df43fc0e306f129510d874:
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for you to fetch changes up to 35a0bd63b458f30389b6bc6b7471c1665fe7b9d8:
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accel/tcg: rename tcg-cpus functions to match module name (2020-12-10 17:44:10 -0600)
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tcg: Widen helper_*_st[bw]_mmu val arguments (2023-05-05 17:21:03 +0100)
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13
----------------------------------------------------------------
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----------------------------------------------------------------
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Split CpusAccel for tcg variants
14
softfloat: Fix the incorrect computation in float32_exp2
15
tcg: Remove compatability helpers for qemu ld/st
16
target/alpha: Remove TARGET_ALIGNED_ONLY
17
target/hppa: Remove TARGET_ALIGNED_ONLY
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target/sparc: Remove TARGET_ALIGNED_ONLY
19
tcg: Cleanups preparing to unify calls to qemu_ld/st helpers
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16
----------------------------------------------------------------
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----------------------------------------------------------------
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Claudio Fontana (3):
22
Richard Henderson (41):
18
accel/tcg: split CpusAccel into three TCG variants
23
target/avr: Finish conversion to tcg_gen_qemu_{ld,st}_*
19
accel/tcg: split tcg_start_vcpu_thread
24
target/cris: Finish conversion to tcg_gen_qemu_{ld,st}_*
20
accel/tcg: rename tcg-cpus functions to match module name
25
target/Hexagon: Finish conversion to tcg_gen_qemu_{ld, st}_*
26
target/m68k: Finish conversion to tcg_gen_qemu_{ld,st}_*
27
target/mips: Finish conversion to tcg_gen_qemu_{ld,st}_*
28
target/s390x: Finish conversion to tcg_gen_qemu_{ld, st}_*
29
target/sparc: Finish conversion to tcg_gen_qemu_{ld, st}_*
30
target/xtensa: Finish conversion to tcg_gen_qemu_{ld, st}_*
31
tcg: Remove compatability helpers for qemu ld/st
32
target/alpha: Use MO_ALIGN for system UNALIGN()
33
target/alpha: Use MO_ALIGN where required
34
target/alpha: Remove TARGET_ALIGNED_ONLY
35
target/hppa: Use MO_ALIGN for system UNALIGN()
36
target/hppa: Remove TARGET_ALIGNED_ONLY
37
target/sparc: Use MO_ALIGN where required
38
target/sparc: Use cpu_ld*_code_mmu
39
target/sparc: Remove TARGET_ALIGNED_ONLY
40
tcg/i386: Rationalize args to tcg_out_qemu_{ld,st}
41
tcg/i386: Generalize multi-part load overlap test
42
tcg/i386: Introduce HostAddress
43
tcg/i386: Drop r0+r1 local variables from tcg_out_tlb_load
44
tcg/i386: Introduce tcg_out_testi
45
tcg/aarch64: Rationalize args to tcg_out_qemu_{ld,st}
46
tcg/aarch64: Introduce HostAddress
47
tcg/arm: Rationalize args to tcg_out_qemu_{ld,st}
48
tcg/arm: Introduce HostAddress
49
tcg/loongarch64: Rationalize args to tcg_out_qemu_{ld,st}
50
tcg/loongarch64: Introduce HostAddress
51
tcg/mips: Rationalize args to tcg_out_qemu_{ld,st}
52
tcg/ppc: Rationalize args to tcg_out_qemu_{ld,st}
53
tcg/ppc: Introduce HostAddress
54
tcg/riscv: Require TCG_TARGET_REG_BITS == 64
55
tcg/riscv: Rationalize args to tcg_out_qemu_{ld,st}
56
tcg/s390x: Pass TCGType to tcg_out_qemu_{ld,st}
57
tcg/s390x: Introduce HostAddress
58
tcg/sparc64: Drop is_64 test from tcg_out_qemu_ld data return
59
tcg/sparc64: Pass TCGType to tcg_out_qemu_{ld,st}
60
tcg: Move TCGLabelQemuLdst to tcg.c
61
tcg: Replace REG_P with arg_loc_reg_p
62
tcg: Introduce arg_slot_stk_ofs
63
tcg: Widen helper_*_st[bw]_mmu val arguments
21
64
22
accel/tcg/tcg-cpus-icount.h | 17 ++
65
Shivaprasad G Bhat (1):
23
accel/tcg/tcg-cpus-rr.h | 21 ++
66
softfloat: Fix the incorrect computation in float32_exp2
24
accel/tcg/tcg-cpus.h | 12 +-
25
accel/tcg/tcg-all.c | 13 +-
26
accel/tcg/tcg-cpus-icount.c | 147 +++++++++++++
27
accel/tcg/tcg-cpus-mttcg.c | 140 ++++++++++++
28
accel/tcg/tcg-cpus-rr.c | 305 ++++++++++++++++++++++++++
29
accel/tcg/tcg-cpus.c | 506 +-------------------------------------------
30
softmmu/icount.c | 2 +-
31
accel/tcg/meson.build | 9 +-
32
10 files changed, 670 insertions(+), 502 deletions(-)
33
create mode 100644 accel/tcg/tcg-cpus-icount.h
34
create mode 100644 accel/tcg/tcg-cpus-rr.h
35
create mode 100644 accel/tcg/tcg-cpus-icount.c
36
create mode 100644 accel/tcg/tcg-cpus-mttcg.c
37
create mode 100644 accel/tcg/tcg-cpus-rr.c
38
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68
configs/targets/alpha-linux-user.mak | 1 -
69
configs/targets/alpha-softmmu.mak | 1 -
70
configs/targets/hppa-linux-user.mak | 1 -
71
configs/targets/hppa-softmmu.mak | 1 -
72
configs/targets/sparc-linux-user.mak | 1 -
73
configs/targets/sparc-softmmu.mak | 1 -
74
configs/targets/sparc32plus-linux-user.mak | 1 -
75
configs/targets/sparc64-linux-user.mak | 1 -
76
configs/targets/sparc64-softmmu.mak | 1 -
77
include/tcg/tcg-ldst.h | 10 +-
78
include/tcg/tcg-op.h | 55 -----
79
target/hexagon/macros.h | 14 +-
80
tcg/riscv/tcg-target-con-set.h | 8 -
81
tcg/riscv/tcg-target.h | 22 +-
82
tcg/tcg-internal.h | 4 -
83
accel/tcg/cputlb.c | 6 +-
84
fpu/softfloat.c | 2 +-
85
target/alpha/translate.c | 38 +--
86
target/avr/translate.c | 16 +-
87
target/hexagon/genptr.c | 8 +-
88
target/hexagon/idef-parser/parser-helpers.c | 28 +--
89
target/hexagon/translate.c | 32 +--
90
target/hppa/translate.c | 2 +-
91
target/m68k/translate.c | 76 ++----
92
target/mips/tcg/translate.c | 8 +-
93
target/s390x/tcg/translate.c | 152 ++++++------
94
target/sparc/ldst_helper.c | 10 +-
95
target/sparc/translate.c | 85 ++++---
96
target/xtensa/translate.c | 4 +-
97
tcg/tcg.c | 58 +++--
98
target/cris/translate_v10.c.inc | 18 +-
99
target/mips/tcg/nanomips_translate.c.inc | 2 +-
100
tcg/aarch64/tcg-target.c.inc | 108 ++++++---
101
tcg/arm/tcg-target.c.inc | 357 +++++++++++++---------------
102
tcg/i386/tcg-target.c.inc | 345 ++++++++++++++-------------
103
tcg/loongarch64/tcg-target.c.inc | 135 +++++------
104
tcg/mips/tcg-target.c.inc | 186 ++++++++-------
105
tcg/ppc/tcg-target.c.inc | 192 ++++++++-------
106
tcg/riscv/tcg-target.c.inc | 268 ++++++---------------
107
tcg/s390x/tcg-target.c.inc | 131 +++++-----
108
tcg/sparc64/tcg-target.c.inc | 8 +-
109
tcg/tcg-ldst.c.inc | 14 --
110
42 files changed, 1120 insertions(+), 1291 deletions(-)
diff view generated by jsdifflib
New patch
[PULL 01/42] softfloat: Fix the incorrect computation in float32_exp2
1
From: Shivaprasad G Bhat <sbhat@linux.ibm.com>
1
2
3
The float32_exp2 function is computing wrong exponent of 2.
4
5
For example, with the following set of values {0.1, 2.0, 2.0, -1.0},
6
the expected output would be {1.071773, 4.000000, 4.000000, 0.500000}.
7
Instead, the function is computing {1.119102, 3.382044, 3.382044, -0.191022}
8
9
Looking at the code, the float32_exp2() attempts to do this
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11
2 3 4 5 n
12
x x x x x x x
13
e = 1 + --- + --- + --- + --- + --- + ... + --- + ...
14
1! 2! 3! 4! 5! n!
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But because of the typo it ends up doing
17
18
x x x x x x x
19
e = 1 + --- + --- + --- + --- + --- + ... + --- + ...
20
1! 2! 3! 4! 5! n!
21
22
This is because instead of the xnp which holds the numerator, parts_muladd
23
is using the xp which is just 'x'. Commit '572c4d862ff2' refactored this
24
function, and mistakenly used xp instead of xnp.
25
26
Cc: qemu-stable@nongnu.org
27
Fixes: 572c4d862ff2 "softfloat: Convert float32_exp2 to FloatParts"
28
Partially-Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1623
29
Reported-By: Luca Barbato (https://gitlab.com/lu-zero)
30
Signed-off-by: Shivaprasad G Bhat <sbhat@linux.ibm.com>
31
Signed-off-by: Vaibhav Jain <vaibhav@linux.ibm.com>
32
Message-Id: <168304110865.537992.13059030916325018670.stgit@localhost.localdomain>
33
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
34
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
35
---
36
fpu/softfloat.c | 2 +-
37
1 file changed, 1 insertion(+), 1 deletion(-)
38
39
diff --git a/fpu/softfloat.c b/fpu/softfloat.c
40
index XXXXXXX..XXXXXXX 100644
41
--- a/fpu/softfloat.c
42
+++ b/fpu/softfloat.c
43
@@ -XXX,XX +XXX,XX @@ float32 float32_exp2(float32 a, float_status *status)
44
float64_unpack_canonical(&rp, float64_one, status);
45
for (i = 0 ; i < 15 ; i++) {
46
float64_unpack_canonical(&tp, float32_exp2_coefficients[i], status);
47
- rp = *parts_muladd(&tp, &xp, &rp, 0, status);
48
+ rp = *parts_muladd(&tp, &xnp, &rp, 0, status);
49
xnp = *parts_mul(&xnp, &xp, status);
50
}
51
52
--
53
2.34.1
diff view generated by jsdifflib
New patch
[PULL 02/42] target/avr: Finish conversion to tcg_gen_qemu_{ld,st}_*
1
Convert away from the old interface with the implicit
2
MemOp argument.
1
3
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
Reviewed-by: Anton Johansson <anjo@rev.ng>
6
Message-Id: <20230502135741.1158035-2-richard.henderson@linaro.org>
7
---
8
target/avr/translate.c | 16 ++++++++--------
9
1 file changed, 8 insertions(+), 8 deletions(-)
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diff --git a/target/avr/translate.c b/target/avr/translate.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/avr/translate.c
14
+++ b/target/avr/translate.c
15
@@ -XXX,XX +XXX,XX @@ static void gen_data_store(DisasContext *ctx, TCGv data, TCGv addr)
16
if (ctx->base.tb->flags & TB_FLAGS_FULL_ACCESS) {
17
gen_helper_fullwr(cpu_env, data, addr);
18
} else {
19
- tcg_gen_qemu_st8(data, addr, MMU_DATA_IDX); /* mem[addr] = data */
20
+ tcg_gen_qemu_st_tl(data, addr, MMU_DATA_IDX, MO_UB);
21
}
22
}
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@@ -XXX,XX +XXX,XX @@ static void gen_data_load(DisasContext *ctx, TCGv data, TCGv addr)
25
if (ctx->base.tb->flags & TB_FLAGS_FULL_ACCESS) {
26
gen_helper_fullrd(data, cpu_env, addr);
27
} else {
28
- tcg_gen_qemu_ld8u(data, addr, MMU_DATA_IDX); /* data = mem[addr] */
29
+ tcg_gen_qemu_ld_tl(data, addr, MMU_DATA_IDX, MO_UB);
30
}
31
}
32
33
@@ -XXX,XX +XXX,XX @@ static bool trans_LPM1(DisasContext *ctx, arg_LPM1 *a)
34
35
tcg_gen_shli_tl(addr, H, 8); /* addr = H:L */
36
tcg_gen_or_tl(addr, addr, L);
37
- tcg_gen_qemu_ld8u(Rd, addr, MMU_CODE_IDX); /* Rd = mem[addr] */
38
+ tcg_gen_qemu_ld_tl(Rd, addr, MMU_CODE_IDX, MO_UB);
39
return true;
40
}
41
42
@@ -XXX,XX +XXX,XX @@ static bool trans_LPM2(DisasContext *ctx, arg_LPM2 *a)
43
44
tcg_gen_shli_tl(addr, H, 8); /* addr = H:L */
45
tcg_gen_or_tl(addr, addr, L);
46
- tcg_gen_qemu_ld8u(Rd, addr, MMU_CODE_IDX); /* Rd = mem[addr] */
47
+ tcg_gen_qemu_ld_tl(Rd, addr, MMU_CODE_IDX, MO_UB);
48
return true;
49
}
50
51
@@ -XXX,XX +XXX,XX @@ static bool trans_LPMX(DisasContext *ctx, arg_LPMX *a)
52
53
tcg_gen_shli_tl(addr, H, 8); /* addr = H:L */
54
tcg_gen_or_tl(addr, addr, L);
55
- tcg_gen_qemu_ld8u(Rd, addr, MMU_CODE_IDX); /* Rd = mem[addr] */
56
+ tcg_gen_qemu_ld_tl(Rd, addr, MMU_CODE_IDX, MO_UB);
57
tcg_gen_addi_tl(addr, addr, 1); /* addr = addr + 1 */
58
tcg_gen_andi_tl(L, addr, 0xff);
59
tcg_gen_shri_tl(addr, addr, 8);
60
@@ -XXX,XX +XXX,XX @@ static bool trans_ELPM1(DisasContext *ctx, arg_ELPM1 *a)
61
TCGv Rd = cpu_r[0];
62
TCGv addr = gen_get_zaddr();
63
64
- tcg_gen_qemu_ld8u(Rd, addr, MMU_CODE_IDX); /* Rd = mem[addr] */
65
+ tcg_gen_qemu_ld_tl(Rd, addr, MMU_CODE_IDX, MO_UB);
66
return true;
67
}
68
69
@@ -XXX,XX +XXX,XX @@ static bool trans_ELPM2(DisasContext *ctx, arg_ELPM2 *a)
70
TCGv Rd = cpu_r[a->rd];
71
TCGv addr = gen_get_zaddr();
72
73
- tcg_gen_qemu_ld8u(Rd, addr, MMU_CODE_IDX); /* Rd = mem[addr] */
74
+ tcg_gen_qemu_ld_tl(Rd, addr, MMU_CODE_IDX, MO_UB);
75
return true;
76
}
77
78
@@ -XXX,XX +XXX,XX @@ static bool trans_ELPMX(DisasContext *ctx, arg_ELPMX *a)
79
TCGv Rd = cpu_r[a->rd];
80
TCGv addr = gen_get_zaddr();
81
82
- tcg_gen_qemu_ld8u(Rd, addr, MMU_CODE_IDX); /* Rd = mem[addr] */
83
+ tcg_gen_qemu_ld_tl(Rd, addr, MMU_CODE_IDX, MO_UB);
84
tcg_gen_addi_tl(addr, addr, 1); /* addr = addr + 1 */
85
gen_set_zaddr(addr);
86
return true;
87
--
88
2.34.1
diff view generated by jsdifflib
New patch
[PULL 03/42] target/cris: Finish conversion to tcg_gen_qemu_{ld, st}_*
1
Convert away from the old interface with the implicit
2
MemOp argument. In this case we can fold the calls
3
using the size bits of MemOp.
1
4
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Reviewed-by: Anton Johansson <anjo@rev.ng>
7
Message-Id: <20230502135741.1158035-3-richard.henderson@linaro.org>
8
---
9
target/cris/translate_v10.c.inc | 18 ++++--------------
10
1 file changed, 4 insertions(+), 14 deletions(-)
11
12
diff --git a/target/cris/translate_v10.c.inc b/target/cris/translate_v10.c.inc
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/cris/translate_v10.c.inc
15
+++ b/target/cris/translate_v10.c.inc
16
@@ -XXX,XX +XXX,XX @@ static void gen_store_v10_conditional(DisasContext *dc, TCGv addr, TCGv val,
17
/* Store only if F flag isn't set */
18
tcg_gen_andi_tl(t1, cpu_PR[PR_CCS], F_FLAG_V10);
19
tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1);
20
- if (size == 1) {
21
- tcg_gen_qemu_st8(tval, taddr, mem_index);
22
- } else if (size == 2) {
23
- tcg_gen_qemu_st16(tval, taddr, mem_index);
24
- } else {
25
- tcg_gen_qemu_st32(tval, taddr, mem_index);
26
- }
27
+
28
+ tcg_gen_qemu_st_tl(tval, taddr, mem_index, ctz32(size) | MO_TE);
29
+
30
gen_set_label(l1);
31
tcg_gen_shri_tl(t1, t1, 1); /* shift F to P position */
32
tcg_gen_or_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], t1); /*P=F*/
33
@@ -XXX,XX +XXX,XX @@ static void gen_store_v10(DisasContext *dc, TCGv addr, TCGv val,
34
return;
35
}
36
37
- if (size == 1) {
38
- tcg_gen_qemu_st8(val, addr, mem_index);
39
- } else if (size == 2) {
40
- tcg_gen_qemu_st16(val, addr, mem_index);
41
- } else {
42
- tcg_gen_qemu_st32(val, addr, mem_index);
43
- }
44
+ tcg_gen_qemu_st_tl(val, addr, mem_index, ctz32(size) | MO_TE);
45
}
46
47
48
--
49
2.34.1
diff view generated by jsdifflib
New patch
[PULL 04/42] target/Hexagon: Finish conversion to tcg_gen_qemu_{ld, st}_*
1
Convert away from the old interface with the implicit
2
MemOp argument. Importantly, this removes some incorrect
3
casts generated by idef-parser's gen_load().
1
4
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Tested-by: Taylor Simpson <tsimpson@quicinc.com>
7
Reviewed-by: Taylor Simpson <tsimpson@quicinc.com>
8
Reviewed-by: Anton Johansson <anjo@rev.ng>
9
Message-Id: <20230502135741.1158035-4-richard.henderson@linaro.org>
10
---
11
target/hexagon/macros.h | 14 ++++-----
12
target/hexagon/genptr.c | 8 +++---
13
target/hexagon/idef-parser/parser-helpers.c | 28 +++++++++---------
14
target/hexagon/translate.c | 32 ++++++++++-----------
15
4 files changed, 40 insertions(+), 42 deletions(-)
16
17
diff --git a/target/hexagon/macros.h b/target/hexagon/macros.h
18
index XXXXXXX..XXXXXXX 100644
19
--- a/target/hexagon/macros.h
20
+++ b/target/hexagon/macros.h
21
@@ -XXX,XX +XXX,XX @@
22
#define MEM_LOAD1s(DST, VA) \
23
do { \
24
CHECK_NOSHUF(VA, 1); \
25
- tcg_gen_qemu_ld8s(DST, VA, ctx->mem_idx); \
26
+ tcg_gen_qemu_ld_tl(DST, VA, ctx->mem_idx, MO_SB); \
27
} while (0)
28
#define MEM_LOAD1u(DST, VA) \
29
do { \
30
CHECK_NOSHUF(VA, 1); \
31
- tcg_gen_qemu_ld8u(DST, VA, ctx->mem_idx); \
32
+ tcg_gen_qemu_ld_tl(DST, VA, ctx->mem_idx, MO_UB); \
33
} while (0)
34
#define MEM_LOAD2s(DST, VA) \
35
do { \
36
CHECK_NOSHUF(VA, 2); \
37
- tcg_gen_qemu_ld16s(DST, VA, ctx->mem_idx); \
38
+ tcg_gen_qemu_ld_tl(DST, VA, ctx->mem_idx, MO_TESW); \
39
} while (0)
40
#define MEM_LOAD2u(DST, VA) \
41
do { \
42
CHECK_NOSHUF(VA, 2); \
43
- tcg_gen_qemu_ld16u(DST, VA, ctx->mem_idx); \
44
+ tcg_gen_qemu_ld_tl(DST, VA, ctx->mem_idx, MO_TEUW); \
45
} while (0)
46
#define MEM_LOAD4s(DST, VA) \
47
do { \
48
CHECK_NOSHUF(VA, 4); \
49
- tcg_gen_qemu_ld32s(DST, VA, ctx->mem_idx); \
50
+ tcg_gen_qemu_ld_tl(DST, VA, ctx->mem_idx, MO_TESL); \
51
} while (0)
52
#define MEM_LOAD4u(DST, VA) \
53
do { \
54
CHECK_NOSHUF(VA, 4); \
55
- tcg_gen_qemu_ld32s(DST, VA, ctx->mem_idx); \
56
+ tcg_gen_qemu_ld_tl(DST, VA, ctx->mem_idx, MO_TEUL); \
57
} while (0)
58
#define MEM_LOAD8u(DST, VA) \
59
do { \
60
CHECK_NOSHUF(VA, 8); \
61
- tcg_gen_qemu_ld64(DST, VA, ctx->mem_idx); \
62
+ tcg_gen_qemu_ld_i64(DST, VA, ctx->mem_idx, MO_TEUQ); \
63
} while (0)
64
65
#define MEM_STORE1_FUNC(X) \
66
diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c
67
index XXXXXXX..XXXXXXX 100644
68
--- a/target/hexagon/genptr.c
69
+++ b/target/hexagon/genptr.c
70
@@ -XXX,XX +XXX,XX @@ void gen_set_byte_i64(int N, TCGv_i64 result, TCGv src)
71
72
static inline void gen_load_locked4u(TCGv dest, TCGv vaddr, int mem_index)
73
{
74
- tcg_gen_qemu_ld32u(dest, vaddr, mem_index);
75
+ tcg_gen_qemu_ld_tl(dest, vaddr, mem_index, MO_TEUL);
76
tcg_gen_mov_tl(hex_llsc_addr, vaddr);
77
tcg_gen_mov_tl(hex_llsc_val, dest);
78
}
79
80
static inline void gen_load_locked8u(TCGv_i64 dest, TCGv vaddr, int mem_index)
81
{
82
- tcg_gen_qemu_ld64(dest, vaddr, mem_index);
83
+ tcg_gen_qemu_ld_i64(dest, vaddr, mem_index, MO_TEUQ);
84
tcg_gen_mov_tl(hex_llsc_addr, vaddr);
85
tcg_gen_mov_i64(hex_llsc_val_i64, dest);
86
}
87
@@ -XXX,XX +XXX,XX @@ static void gen_load_frame(DisasContext *ctx, TCGv_i64 frame, TCGv EA)
88
{
89
Insn *insn = ctx->insn; /* Needed for CHECK_NOSHUF */
90
CHECK_NOSHUF(EA, 8);
91
- tcg_gen_qemu_ld64(frame, EA, ctx->mem_idx);
92
+ tcg_gen_qemu_ld_i64(frame, EA, ctx->mem_idx, MO_TEUQ);
93
}
94
95
static void gen_return(DisasContext *ctx, TCGv_i64 dst, TCGv src)
96
@@ -XXX,XX +XXX,XX @@ static void gen_vreg_load(DisasContext *ctx, intptr_t dstoff, TCGv src,
97
tcg_gen_andi_tl(src, src, ~((int32_t)sizeof(MMVector) - 1));
98
}
99
for (int i = 0; i < sizeof(MMVector) / 8; i++) {
100
- tcg_gen_qemu_ld64(tmp, src, ctx->mem_idx);
101
+ tcg_gen_qemu_ld_i64(tmp, src, ctx->mem_idx, MO_TEUQ);
102
tcg_gen_addi_tl(src, src, 8);
103
tcg_gen_st_i64(tmp, cpu_env, dstoff + i * 8);
104
}
105
diff --git a/target/hexagon/idef-parser/parser-helpers.c b/target/hexagon/idef-parser/parser-helpers.c
106
index XXXXXXX..XXXXXXX 100644
107
--- a/target/hexagon/idef-parser/parser-helpers.c
108
+++ b/target/hexagon/idef-parser/parser-helpers.c
109
@@ -XXX,XX +XXX,XX @@ void gen_load_cancel(Context *c, YYLTYPE *locp)
110
void gen_load(Context *c, YYLTYPE *locp, HexValue *width,
111
HexSignedness signedness, HexValue *ea, HexValue *dst)
112
{
113
- char size_suffix[4] = {0};
114
- const char *sign_suffix;
115
+ unsigned dst_bit_width;
116
+ unsigned src_bit_width;
117
+
118
/* Memop width is specified in the load macro */
119
assert_signedness(c, locp, signedness);
120
- sign_suffix = (width->imm.value > 4)
121
- ? ""
122
- : ((signedness == UNSIGNED) ? "u" : "s");
123
+
124
/* If dst is a variable, assert that is declared and load the type info */
125
if (dst->type == VARID) {
126
find_variable(c, locp, dst, dst);
127
}
128
129
- snprintf(size_suffix, 4, "%" PRIu64, width->imm.value * 8);
130
+ src_bit_width = width->imm.value * 8;
131
+ dst_bit_width = MAX(dst->bit_width, 32);
132
+
133
/* Lookup the effective address EA */
134
find_variable(c, locp, ea, ea);
135
OUT(c, locp, "if (insn->slot == 0 && pkt->pkt_has_store_s1) {\n");
136
OUT(c, locp, "probe_noshuf_load(", ea, ", ", width, ", ctx->mem_idx);\n");
137
OUT(c, locp, "process_store(ctx, 1);\n");
138
OUT(c, locp, "}\n");
139
- OUT(c, locp, "tcg_gen_qemu_ld", size_suffix, sign_suffix);
140
+
141
+ OUT(c, locp, "tcg_gen_qemu_ld_i", &dst_bit_width);
142
OUT(c, locp, "(");
143
- if (dst->bit_width > width->imm.value * 8) {
144
- /*
145
- * Cast to the correct TCG type if necessary, to avoid implict cast
146
- * warnings. This is needed when the width of the destination var is
147
- * larger than the size of the requested load.
148
- */
149
- OUT(c, locp, "(TCGv) ");
150
+ OUT(c, locp, dst, ", ", ea, ", ctx->mem_idx, MO_", &src_bit_width);
151
+ if (signedness == SIGNED) {
152
+ OUT(c, locp, " | MO_SIGN");
153
}
154
- OUT(c, locp, dst, ", ", ea, ", ctx->mem_idx);\n");
155
+ OUT(c, locp, " | MO_TE);\n");
156
}
157
158
void gen_store(Context *c, YYLTYPE *locp, HexValue *width, HexValue *ea,
159
diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c
160
index XXXXXXX..XXXXXXX 100644
161
--- a/target/hexagon/translate.c
162
+++ b/target/hexagon/translate.c
163
@@ -XXX,XX +XXX,XX @@ void process_store(DisasContext *ctx, int slot_num)
164
switch (ctx->store_width[slot_num]) {
165
case 1:
166
gen_check_store_width(ctx, slot_num);
167
- tcg_gen_qemu_st8(hex_store_val32[slot_num],
168
- hex_store_addr[slot_num],
169
- ctx->mem_idx);
170
+ tcg_gen_qemu_st_tl(hex_store_val32[slot_num],
171
+ hex_store_addr[slot_num],
172
+ ctx->mem_idx, MO_UB);
173
break;
174
case 2:
175
gen_check_store_width(ctx, slot_num);
176
- tcg_gen_qemu_st16(hex_store_val32[slot_num],
177
- hex_store_addr[slot_num],
178
- ctx->mem_idx);
179
+ tcg_gen_qemu_st_tl(hex_store_val32[slot_num],
180
+ hex_store_addr[slot_num],
181
+ ctx->mem_idx, MO_TEUW);
182
break;
183
case 4:
184
gen_check_store_width(ctx, slot_num);
185
- tcg_gen_qemu_st32(hex_store_val32[slot_num],
186
- hex_store_addr[slot_num],
187
- ctx->mem_idx);
188
+ tcg_gen_qemu_st_tl(hex_store_val32[slot_num],
189
+ hex_store_addr[slot_num],
190
+ ctx->mem_idx, MO_TEUL);
191
break;
192
case 8:
193
gen_check_store_width(ctx, slot_num);
194
- tcg_gen_qemu_st64(hex_store_val64[slot_num],
195
- hex_store_addr[slot_num],
196
- ctx->mem_idx);
197
+ tcg_gen_qemu_st_i64(hex_store_val64[slot_num],
198
+ hex_store_addr[slot_num],
199
+ ctx->mem_idx, MO_TEUQ);
200
break;
201
default:
202
{
203
@@ -XXX,XX +XXX,XX @@ static void process_dczeroa(DisasContext *ctx)
204
TCGv_i64 zero = tcg_constant_i64(0);
205
206
tcg_gen_andi_tl(addr, hex_dczero_addr, ~0x1f);
207
- tcg_gen_qemu_st64(zero, addr, ctx->mem_idx);
208
+ tcg_gen_qemu_st_i64(zero, addr, ctx->mem_idx, MO_UQ);
209
tcg_gen_addi_tl(addr, addr, 8);
210
- tcg_gen_qemu_st64(zero, addr, ctx->mem_idx);
211
+ tcg_gen_qemu_st_i64(zero, addr, ctx->mem_idx, MO_UQ);
212
tcg_gen_addi_tl(addr, addr, 8);
213
- tcg_gen_qemu_st64(zero, addr, ctx->mem_idx);
214
+ tcg_gen_qemu_st_i64(zero, addr, ctx->mem_idx, MO_UQ);
215
tcg_gen_addi_tl(addr, addr, 8);
216
- tcg_gen_qemu_st64(zero, addr, ctx->mem_idx);
217
+ tcg_gen_qemu_st_i64(zero, addr, ctx->mem_idx, MO_UQ);
218
}
219
}
220
221
--
222
2.34.1
diff view generated by jsdifflib
New patch
[PULL 05/42] target/m68k: Finish conversion to tcg_gen_qemu_{ld, st}_*
1
Convert away from the old interface with the implicit
2
MemOp argument.
1
3
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
Reviewed-by: Anton Johansson <anjo@rev.ng>
6
Message-Id: <20230502135741.1158035-5-richard.henderson@linaro.org>
7
---
8
target/m68k/translate.c | 76 ++++++++++++++---------------------------
9
1 file changed, 25 insertions(+), 51 deletions(-)
10
11
diff --git a/target/m68k/translate.c b/target/m68k/translate.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/m68k/translate.c
14
+++ b/target/m68k/translate.c
15
@@ -XXX,XX +XXX,XX @@ static inline void gen_addr_fault(DisasContext *s)
16
static inline TCGv gen_load(DisasContext *s, int opsize, TCGv addr,
17
int sign, int index)
18
{
19
- TCGv tmp;
20
- tmp = tcg_temp_new_i32();
21
- switch(opsize) {
22
+ TCGv tmp = tcg_temp_new_i32();
23
+
24
+ switch (opsize) {
25
case OS_BYTE:
26
- if (sign)
27
- tcg_gen_qemu_ld8s(tmp, addr, index);
28
- else
29
- tcg_gen_qemu_ld8u(tmp, addr, index);
30
- break;
31
case OS_WORD:
32
- if (sign)
33
- tcg_gen_qemu_ld16s(tmp, addr, index);
34
- else
35
- tcg_gen_qemu_ld16u(tmp, addr, index);
36
- break;
37
case OS_LONG:
38
- tcg_gen_qemu_ld32u(tmp, addr, index);
39
+ tcg_gen_qemu_ld_tl(tmp, addr, index,
40
+ opsize | (sign ? MO_SIGN : 0) | MO_TE);
41
break;
42
default:
43
g_assert_not_reached();
44
@@ -XXX,XX +XXX,XX @@ static inline TCGv gen_load(DisasContext *s, int opsize, TCGv addr,
45
static inline void gen_store(DisasContext *s, int opsize, TCGv addr, TCGv val,
46
int index)
47
{
48
- switch(opsize) {
49
+ switch (opsize) {
50
case OS_BYTE:
51
- tcg_gen_qemu_st8(val, addr, index);
52
- break;
53
case OS_WORD:
54
- tcg_gen_qemu_st16(val, addr, index);
55
- break;
56
case OS_LONG:
57
- tcg_gen_qemu_st32(val, addr, index);
58
+ tcg_gen_qemu_st_tl(val, addr, index, opsize | MO_TE);
59
break;
60
default:
61
g_assert_not_reached();
62
@@ -XXX,XX +XXX,XX @@ static void gen_load_fp(DisasContext *s, int opsize, TCGv addr, TCGv_ptr fp,
63
tmp = tcg_temp_new();
64
switch (opsize) {
65
case OS_BYTE:
66
- tcg_gen_qemu_ld8s(tmp, addr, index);
67
- gen_helper_exts32(cpu_env, fp, tmp);
68
- break;
69
case OS_WORD:
70
- tcg_gen_qemu_ld16s(tmp, addr, index);
71
- gen_helper_exts32(cpu_env, fp, tmp);
72
- break;
73
- case OS_LONG:
74
- tcg_gen_qemu_ld32u(tmp, addr, index);
75
+ tcg_gen_qemu_ld_tl(tmp, addr, index, opsize | MO_SIGN | MO_TE);
76
gen_helper_exts32(cpu_env, fp, tmp);
77
break;
78
case OS_SINGLE:
79
- tcg_gen_qemu_ld32u(tmp, addr, index);
80
+ tcg_gen_qemu_ld_tl(tmp, addr, index, MO_TEUL);
81
gen_helper_extf32(cpu_env, fp, tmp);
82
break;
83
case OS_DOUBLE:
84
- tcg_gen_qemu_ld64(t64, addr, index);
85
+ tcg_gen_qemu_ld_i64(t64, addr, index, MO_TEUQ);
86
gen_helper_extf64(cpu_env, fp, t64);
87
break;
88
case OS_EXTENDED:
89
@@ -XXX,XX +XXX,XX @@ static void gen_load_fp(DisasContext *s, int opsize, TCGv addr, TCGv_ptr fp,
90
gen_exception(s, s->base.pc_next, EXCP_FP_UNIMP);
91
break;
92
}
93
- tcg_gen_qemu_ld32u(tmp, addr, index);
94
+ tcg_gen_qemu_ld_i32(tmp, addr, index, MO_TEUL);
95
tcg_gen_shri_i32(tmp, tmp, 16);
96
tcg_gen_st16_i32(tmp, fp, offsetof(FPReg, l.upper));
97
tcg_gen_addi_i32(tmp, addr, 4);
98
- tcg_gen_qemu_ld64(t64, tmp, index);
99
+ tcg_gen_qemu_ld_i64(t64, tmp, index, MO_TEUQ);
100
tcg_gen_st_i64(t64, fp, offsetof(FPReg, l.lower));
101
break;
102
case OS_PACKED:
103
@@ -XXX,XX +XXX,XX @@ static void gen_store_fp(DisasContext *s, int opsize, TCGv addr, TCGv_ptr fp,
104
tmp = tcg_temp_new();
105
switch (opsize) {
106
case OS_BYTE:
107
- gen_helper_reds32(tmp, cpu_env, fp);
108
- tcg_gen_qemu_st8(tmp, addr, index);
109
- break;
110
case OS_WORD:
111
- gen_helper_reds32(tmp, cpu_env, fp);
112
- tcg_gen_qemu_st16(tmp, addr, index);
113
- break;
114
case OS_LONG:
115
gen_helper_reds32(tmp, cpu_env, fp);
116
- tcg_gen_qemu_st32(tmp, addr, index);
117
+ tcg_gen_qemu_st_tl(tmp, addr, index, opsize | MO_TE);
118
break;
119
case OS_SINGLE:
120
gen_helper_redf32(tmp, cpu_env, fp);
121
- tcg_gen_qemu_st32(tmp, addr, index);
122
+ tcg_gen_qemu_st_tl(tmp, addr, index, MO_TEUL);
123
break;
124
case OS_DOUBLE:
125
gen_helper_redf64(t64, cpu_env, fp);
126
- tcg_gen_qemu_st64(t64, addr, index);
127
+ tcg_gen_qemu_st_i64(t64, addr, index, MO_TEUQ);
128
break;
129
case OS_EXTENDED:
130
if (m68k_feature(s->env, M68K_FEATURE_CF_FPU)) {
131
@@ -XXX,XX +XXX,XX @@ static void gen_store_fp(DisasContext *s, int opsize, TCGv addr, TCGv_ptr fp,
132
}
133
tcg_gen_ld16u_i32(tmp, fp, offsetof(FPReg, l.upper));
134
tcg_gen_shli_i32(tmp, tmp, 16);
135
- tcg_gen_qemu_st32(tmp, addr, index);
136
+ tcg_gen_qemu_st_i32(tmp, addr, index, MO_TEUL);
137
tcg_gen_addi_i32(tmp, addr, 4);
138
tcg_gen_ld_i64(t64, fp, offsetof(FPReg, l.lower));
139
- tcg_gen_qemu_st64(t64, tmp, index);
140
+ tcg_gen_qemu_st_i64(t64, tmp, index, MO_TEUQ);
141
break;
142
case OS_PACKED:
143
/*
144
@@ -XXX,XX +XXX,XX @@ DISAS_INSN(movep)
145
if (insn & 0x80) {
146
for ( ; i > 0 ; i--) {
147
tcg_gen_shri_i32(dbuf, reg, (i - 1) * 8);
148
- tcg_gen_qemu_st8(dbuf, abuf, IS_USER(s));
149
+ tcg_gen_qemu_st_i32(dbuf, abuf, IS_USER(s), MO_UB);
150
if (i > 1) {
151
tcg_gen_addi_i32(abuf, abuf, 2);
152
}
153
}
154
} else {
155
for ( ; i > 0 ; i--) {
156
- tcg_gen_qemu_ld8u(dbuf, abuf, IS_USER(s));
157
+ tcg_gen_qemu_ld_tl(dbuf, abuf, IS_USER(s), MO_UB);
158
tcg_gen_deposit_i32(reg, reg, dbuf, (i - 1) * 8, 8);
159
if (i > 1) {
160
tcg_gen_addi_i32(abuf, abuf, 2);
161
@@ -XXX,XX +XXX,XX @@ static void m68k_copy_line(TCGv dst, TCGv src, int index)
162
t1 = tcg_temp_new_i64();
163
164
tcg_gen_andi_i32(addr, src, ~15);
165
- tcg_gen_qemu_ld64(t0, addr, index);
166
+ tcg_gen_qemu_ld_i64(t0, addr, index, MO_TEUQ);
167
tcg_gen_addi_i32(addr, addr, 8);
168
- tcg_gen_qemu_ld64(t1, addr, index);
169
+ tcg_gen_qemu_ld_i64(t1, addr, index, MO_TEUQ);
170
171
tcg_gen_andi_i32(addr, dst, ~15);
172
- tcg_gen_qemu_st64(t0, addr, index);
173
+ tcg_gen_qemu_st_i64(t0, addr, index, MO_TEUQ);
174
tcg_gen_addi_i32(addr, addr, 8);
175
- tcg_gen_qemu_st64(t1, addr, index);
176
+ tcg_gen_qemu_st_i64(t1, addr, index, MO_TEUQ);
177
}
178
179
DISAS_INSN(move16_reg)
180
@@ -XXX,XX +XXX,XX @@ static void gen_qemu_store_fcr(DisasContext *s, TCGv addr, int reg)
181
182
tmp = tcg_temp_new();
183
gen_load_fcr(s, tmp, reg);
184
- tcg_gen_qemu_st32(tmp, addr, index);
185
+ tcg_gen_qemu_st_tl(tmp, addr, index, MO_TEUL);
186
}
187
188
static void gen_qemu_load_fcr(DisasContext *s, TCGv addr, int reg)
189
@@ -XXX,XX +XXX,XX @@ static void gen_qemu_load_fcr(DisasContext *s, TCGv addr, int reg)
190
TCGv tmp;
191
192
tmp = tcg_temp_new();
193
- tcg_gen_qemu_ld32u(tmp, addr, index);
194
+ tcg_gen_qemu_ld_tl(tmp, addr, index, MO_TEUL);
195
gen_store_fcr(s, tmp, reg);
196
}
197
198
--
199
2.34.1
diff view generated by jsdifflib
New patch
[PULL 06/42] target/mips: Finish conversion to tcg_gen_qemu_{ld, st}_*
1
Convert away from the old interface with the implicit
2
MemOp argument.
1
3
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
Reviewed-by: Anton Johansson <anjo@rev.ng>
6
Message-Id: <20230502135741.1158035-6-richard.henderson@linaro.org>
7
---
8
target/mips/tcg/translate.c | 8 ++++----
9
target/mips/tcg/nanomips_translate.c.inc | 2 +-
10
2 files changed, 5 insertions(+), 5 deletions(-)
11
12
diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/mips/tcg/translate.c
15
+++ b/target/mips/tcg/translate.c
16
@@ -XXX,XX +XXX,XX @@ FOP_CONDNS(s, FMT_S, 32, gen_store_fpr32(ctx, fp0, fd))
17
18
/* load/store instructions. */
19
#ifdef CONFIG_USER_ONLY
20
-#define OP_LD_ATOMIC(insn, fname) \
21
+#define OP_LD_ATOMIC(insn, memop) \
22
static inline void op_ld_##insn(TCGv ret, TCGv arg1, int mem_idx, \
23
DisasContext *ctx) \
24
{ \
25
TCGv t0 = tcg_temp_new(); \
26
tcg_gen_mov_tl(t0, arg1); \
27
- tcg_gen_qemu_##fname(ret, arg1, ctx->mem_idx); \
28
+ tcg_gen_qemu_ld_tl(ret, arg1, ctx->mem_idx, memop); \
29
tcg_gen_st_tl(t0, cpu_env, offsetof(CPUMIPSState, lladdr)); \
30
tcg_gen_st_tl(ret, cpu_env, offsetof(CPUMIPSState, llval)); \
31
}
32
@@ -XXX,XX +XXX,XX @@ static inline void op_ld_##insn(TCGv ret, TCGv arg1, int mem_idx, \
33
gen_helper_##insn(ret, cpu_env, arg1, tcg_constant_i32(mem_idx)); \
34
}
35
#endif
36
-OP_LD_ATOMIC(ll, ld32s);
37
+OP_LD_ATOMIC(ll, MO_TESL);
38
#if defined(TARGET_MIPS64)
39
-OP_LD_ATOMIC(lld, ld64);
40
+OP_LD_ATOMIC(lld, MO_TEUQ);
41
#endif
42
#undef OP_LD_ATOMIC
43
44
diff --git a/target/mips/tcg/nanomips_translate.c.inc b/target/mips/tcg/nanomips_translate.c.inc
45
index XXXXXXX..XXXXXXX 100644
46
--- a/target/mips/tcg/nanomips_translate.c.inc
47
+++ b/target/mips/tcg/nanomips_translate.c.inc
48
@@ -XXX,XX +XXX,XX @@ static void gen_llwp(DisasContext *ctx, uint32_t base, int16_t offset,
49
TCGv tmp2 = tcg_temp_new();
50
51
gen_base_offset_addr(ctx, taddr, base, offset);
52
- tcg_gen_qemu_ld64(tval, taddr, ctx->mem_idx);
53
+ tcg_gen_qemu_ld_i64(tval, taddr, ctx->mem_idx, MO_TEUQ);
54
if (cpu_is_bigendian(ctx)) {
55
tcg_gen_extr_i64_tl(tmp2, tmp1, tval);
56
} else {
57
--
58
2.34.1
diff view generated by jsdifflib
New patch
[PULL 07/42] target/s390x: Finish conversion to tcg_gen_qemu_{ld, st}_*
1
Convert away from the old interface with the implicit
2
MemOp argument.
1
3
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
Reviewed-by: David Hildenbrand <david@redhat.com>
6
Reviewed-by: Ilya Leoshkevich <iii@linux.ibm.com>
7
Message-Id: <20230502135741.1158035-7-richard.henderson@linaro.org>
8
---
9
target/s390x/tcg/translate.c | 152 ++++++++++++++++-------------------
10
1 file changed, 71 insertions(+), 81 deletions(-)
11
12
diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/s390x/tcg/translate.c
15
+++ b/target/s390x/tcg/translate.c
16
@@ -XXX,XX +XXX,XX @@ static DisasJumpType op_clc(DisasContext *s, DisasOps *o)
17
{
18
int l = get_field(s, l1);
19
TCGv_i32 vl;
20
+ MemOp mop;
21
22
switch (l + 1) {
23
case 1:
24
- tcg_gen_qemu_ld8u(cc_src, o->addr1, get_mem_index(s));
25
- tcg_gen_qemu_ld8u(cc_dst, o->in2, get_mem_index(s));
26
- break;
27
case 2:
28
- tcg_gen_qemu_ld16u(cc_src, o->addr1, get_mem_index(s));
29
- tcg_gen_qemu_ld16u(cc_dst, o->in2, get_mem_index(s));
30
- break;
31
case 4:
32
- tcg_gen_qemu_ld32u(cc_src, o->addr1, get_mem_index(s));
33
- tcg_gen_qemu_ld32u(cc_dst, o->in2, get_mem_index(s));
34
- break;
35
case 8:
36
- tcg_gen_qemu_ld64(cc_src, o->addr1, get_mem_index(s));
37
- tcg_gen_qemu_ld64(cc_dst, o->in2, get_mem_index(s));
38
- break;
39
+ mop = ctz32(l + 1) | MO_TE;
40
+ tcg_gen_qemu_ld_tl(cc_src, o->addr1, get_mem_index(s), mop);
41
+ tcg_gen_qemu_ld_tl(cc_dst, o->in2, get_mem_index(s), mop);
42
+ gen_op_update2_cc_i64(s, CC_OP_LTUGTU_64, cc_src, cc_dst);
43
+ return DISAS_NEXT;
44
default:
45
vl = tcg_constant_i32(l);
46
gen_helper_clc(cc_op, cpu_env, vl, o->addr1, o->in2);
47
set_cc_static(s);
48
return DISAS_NEXT;
49
}
50
- gen_op_update2_cc_i64(s, CC_OP_LTUGTU_64, cc_src, cc_dst);
51
- return DISAS_NEXT;
52
}
53
54
static DisasJumpType op_clcl(DisasContext *s, DisasOps *o)
55
@@ -XXX,XX +XXX,XX @@ static DisasJumpType op_cvd(DisasContext *s, DisasOps *o)
56
TCGv_i32 t2 = tcg_temp_new_i32();
57
tcg_gen_extrl_i64_i32(t2, o->in1);
58
gen_helper_cvd(t1, t2);
59
- tcg_gen_qemu_st64(t1, o->in2, get_mem_index(s));
60
+ tcg_gen_qemu_st_i64(t1, o->in2, get_mem_index(s), MO_TEUQ);
61
return DISAS_NEXT;
62
}
63
64
@@ -XXX,XX +XXX,XX @@ static DisasJumpType op_icm(DisasContext *s, DisasOps *o)
65
switch (m3) {
66
case 0xf:
67
/* Effectively a 32-bit load. */
68
- tcg_gen_qemu_ld32u(tmp, o->in2, get_mem_index(s));
69
+ tcg_gen_qemu_ld_i64(tmp, o->in2, get_mem_index(s), MO_TEUL);
70
len = 32;
71
goto one_insert;
72
73
@@ -XXX,XX +XXX,XX @@ static DisasJumpType op_icm(DisasContext *s, DisasOps *o)
74
case 0x6:
75
case 0x3:
76
/* Effectively a 16-bit load. */
77
- tcg_gen_qemu_ld16u(tmp, o->in2, get_mem_index(s));
78
+ tcg_gen_qemu_ld_i64(tmp, o->in2, get_mem_index(s), MO_TEUW);
79
len = 16;
80
goto one_insert;
81
82
@@ -XXX,XX +XXX,XX @@ static DisasJumpType op_icm(DisasContext *s, DisasOps *o)
83
case 0x2:
84
case 0x1:
85
/* Effectively an 8-bit load. */
86
- tcg_gen_qemu_ld8u(tmp, o->in2, get_mem_index(s));
87
+ tcg_gen_qemu_ld_i64(tmp, o->in2, get_mem_index(s), MO_UB);
88
len = 8;
89
goto one_insert;
90
91
@@ -XXX,XX +XXX,XX @@ static DisasJumpType op_icm(DisasContext *s, DisasOps *o)
92
ccm = 0;
93
while (m3) {
94
if (m3 & 0x8) {
95
- tcg_gen_qemu_ld8u(tmp, o->in2, get_mem_index(s));
96
+ tcg_gen_qemu_ld_i64(tmp, o->in2, get_mem_index(s), MO_UB);
97
tcg_gen_addi_i64(o->in2, o->in2, 1);
98
tcg_gen_deposit_i64(o->out, o->out, tmp, pos, 8);
99
ccm |= 0xffull << pos;
100
@@ -XXX,XX +XXX,XX @@ static DisasJumpType op_llgt(DisasContext *s, DisasOps *o)
101
102
static DisasJumpType op_ld8s(DisasContext *s, DisasOps *o)
103
{
104
- tcg_gen_qemu_ld8s(o->out, o->in2, get_mem_index(s));
105
+ tcg_gen_qemu_ld_i64(o->out, o->in2, get_mem_index(s), MO_SB);
106
return DISAS_NEXT;
107
}
108
109
static DisasJumpType op_ld8u(DisasContext *s, DisasOps *o)
110
{
111
- tcg_gen_qemu_ld8u(o->out, o->in2, get_mem_index(s));
112
+ tcg_gen_qemu_ld_i64(o->out, o->in2, get_mem_index(s), MO_UB);
113
return DISAS_NEXT;
114
}
115
116
static DisasJumpType op_ld16s(DisasContext *s, DisasOps *o)
117
{
118
- tcg_gen_qemu_ld16s(o->out, o->in2, get_mem_index(s));
119
+ tcg_gen_qemu_ld_i64(o->out, o->in2, get_mem_index(s), MO_TESW);
120
return DISAS_NEXT;
121
}
122
123
static DisasJumpType op_ld16u(DisasContext *s, DisasOps *o)
124
{
125
- tcg_gen_qemu_ld16u(o->out, o->in2, get_mem_index(s));
126
+ tcg_gen_qemu_ld_i64(o->out, o->in2, get_mem_index(s), MO_TEUW);
127
return DISAS_NEXT;
128
}
129
130
@@ -XXX,XX +XXX,XX @@ static DisasJumpType op_lat(DisasContext *s, DisasOps *o)
131
static DisasJumpType op_lgat(DisasContext *s, DisasOps *o)
132
{
133
TCGLabel *lab = gen_new_label();
134
- tcg_gen_qemu_ld64(o->out, o->in2, get_mem_index(s));
135
+ tcg_gen_qemu_ld_i64(o->out, o->in2, get_mem_index(s), MO_TEUQ);
136
/* The value is stored even in case of trap. */
137
tcg_gen_brcondi_i64(TCG_COND_NE, o->out, 0, lab);
138
gen_trap(s);
139
@@ -XXX,XX +XXX,XX @@ static DisasJumpType op_lfhat(DisasContext *s, DisasOps *o)
140
static DisasJumpType op_llgfat(DisasContext *s, DisasOps *o)
141
{
142
TCGLabel *lab = gen_new_label();
143
- tcg_gen_qemu_ld32u(o->out, o->in2, get_mem_index(s));
144
+
145
+ tcg_gen_qemu_ld_i64(o->out, o->in2, get_mem_index(s), MO_TEUL);
146
/* The value is stored even in case of trap. */
147
tcg_gen_brcondi_i64(TCG_COND_NE, o->out, 0, lab);
148
gen_trap(s);
149
@@ -XXX,XX +XXX,XX @@ static DisasJumpType op_lpswe(DisasContext *s, DisasOps *o)
150
tcg_gen_qemu_ld_i64(t1, o->in2, get_mem_index(s),
151
MO_TEUQ | MO_ALIGN_8);
152
tcg_gen_addi_i64(o->in2, o->in2, 8);
153
- tcg_gen_qemu_ld64(t2, o->in2, get_mem_index(s));
154
+ tcg_gen_qemu_ld_i64(t2, o->in2, get_mem_index(s), MO_TEUQ);
155
gen_helper_load_psw(cpu_env, t1, t2);
156
return DISAS_NORETURN;
157
}
158
@@ -XXX,XX +XXX,XX @@ static DisasJumpType op_lm32(DisasContext *s, DisasOps *o)
159
/* Only one register to read. */
160
t1 = tcg_temp_new_i64();
161
if (unlikely(r1 == r3)) {
162
- tcg_gen_qemu_ld32u(t1, o->in2, get_mem_index(s));
163
+ tcg_gen_qemu_ld_i64(t1, o->in2, get_mem_index(s), MO_TEUL);
164
store_reg32_i64(r1, t1);
165
return DISAS_NEXT;
166
}
167
@@ -XXX,XX +XXX,XX @@ static DisasJumpType op_lm32(DisasContext *s, DisasOps *o)
168
/* First load the values of the first and last registers to trigger
169
possible page faults. */
170
t2 = tcg_temp_new_i64();
171
- tcg_gen_qemu_ld32u(t1, o->in2, get_mem_index(s));
172
+ tcg_gen_qemu_ld_i64(t1, o->in2, get_mem_index(s), MO_TEUL);
173
tcg_gen_addi_i64(t2, o->in2, 4 * ((r3 - r1) & 15));
174
- tcg_gen_qemu_ld32u(t2, t2, get_mem_index(s));
175
+ tcg_gen_qemu_ld_i64(t2, t2, get_mem_index(s), MO_TEUL);
176
store_reg32_i64(r1, t1);
177
store_reg32_i64(r3, t2);
178
179
@@ -XXX,XX +XXX,XX @@ static DisasJumpType op_lm32(DisasContext *s, DisasOps *o)
180
while (r1 != r3) {
181
r1 = (r1 + 1) & 15;
182
tcg_gen_add_i64(o->in2, o->in2, t2);
183
- tcg_gen_qemu_ld32u(t1, o->in2, get_mem_index(s));
184
+ tcg_gen_qemu_ld_i64(t1, o->in2, get_mem_index(s), MO_TEUL);
185
store_reg32_i64(r1, t1);
186
}
187
return DISAS_NEXT;
188
@@ -XXX,XX +XXX,XX @@ static DisasJumpType op_lmh(DisasContext *s, DisasOps *o)
189
/* Only one register to read. */
190
t1 = tcg_temp_new_i64();
191
if (unlikely(r1 == r3)) {
192
- tcg_gen_qemu_ld32u(t1, o->in2, get_mem_index(s));
193
+ tcg_gen_qemu_ld_i64(t1, o->in2, get_mem_index(s), MO_TEUL);
194
store_reg32h_i64(r1, t1);
195
return DISAS_NEXT;
196
}
197
@@ -XXX,XX +XXX,XX @@ static DisasJumpType op_lmh(DisasContext *s, DisasOps *o)
198
/* First load the values of the first and last registers to trigger
199
possible page faults. */
200
t2 = tcg_temp_new_i64();
201
- tcg_gen_qemu_ld32u(t1, o->in2, get_mem_index(s));
202
+ tcg_gen_qemu_ld_i64(t1, o->in2, get_mem_index(s), MO_TEUL);
203
tcg_gen_addi_i64(t2, o->in2, 4 * ((r3 - r1) & 15));
204
- tcg_gen_qemu_ld32u(t2, t2, get_mem_index(s));
205
+ tcg_gen_qemu_ld_i64(t2, t2, get_mem_index(s), MO_TEUL);
206
store_reg32h_i64(r1, t1);
207
store_reg32h_i64(r3, t2);
208
209
@@ -XXX,XX +XXX,XX @@ static DisasJumpType op_lmh(DisasContext *s, DisasOps *o)
210
while (r1 != r3) {
211
r1 = (r1 + 1) & 15;
212
tcg_gen_add_i64(o->in2, o->in2, t2);
213
- tcg_gen_qemu_ld32u(t1, o->in2, get_mem_index(s));
214
+ tcg_gen_qemu_ld_i64(t1, o->in2, get_mem_index(s), MO_TEUL);
215
store_reg32h_i64(r1, t1);
216
}
217
return DISAS_NEXT;
218
@@ -XXX,XX +XXX,XX @@ static DisasJumpType op_lm64(DisasContext *s, DisasOps *o)
219
220
/* Only one register to read. */
221
if (unlikely(r1 == r3)) {
222
- tcg_gen_qemu_ld64(regs[r1], o->in2, get_mem_index(s));
223
+ tcg_gen_qemu_ld_i64(regs[r1], o->in2, get_mem_index(s), MO_TEUQ);
224
return DISAS_NEXT;
225
}
226
227
@@ -XXX,XX +XXX,XX @@ static DisasJumpType op_lm64(DisasContext *s, DisasOps *o)
228
possible page faults. */
229
t1 = tcg_temp_new_i64();
230
t2 = tcg_temp_new_i64();
231
- tcg_gen_qemu_ld64(t1, o->in2, get_mem_index(s));
232
+ tcg_gen_qemu_ld_i64(t1, o->in2, get_mem_index(s), MO_TEUQ);
233
tcg_gen_addi_i64(t2, o->in2, 8 * ((r3 - r1) & 15));
234
- tcg_gen_qemu_ld64(regs[r3], t2, get_mem_index(s));
235
+ tcg_gen_qemu_ld_i64(regs[r3], t2, get_mem_index(s), MO_TEUQ);
236
tcg_gen_mov_i64(regs[r1], t1);
237
238
/* Only two registers to read. */
239
@@ -XXX,XX +XXX,XX @@ static DisasJumpType op_lm64(DisasContext *s, DisasOps *o)
240
while (r1 != r3) {
241
r1 = (r1 + 1) & 15;
242
tcg_gen_add_i64(o->in2, o->in2, t1);
243
- tcg_gen_qemu_ld64(regs[r1], o->in2, get_mem_index(s));
244
+ tcg_gen_qemu_ld_i64(regs[r1], o->in2, get_mem_index(s), MO_TEUQ);
245
}
246
return DISAS_NEXT;
247
}
248
@@ -XXX,XX +XXX,XX @@ static DisasJumpType op_soc(DisasContext *s, DisasOps *o)
249
a = get_address(s, 0, get_field(s, b2), get_field(s, d2));
250
switch (s->insn->data) {
251
case 1: /* STOCG */
252
- tcg_gen_qemu_st64(regs[r1], a, get_mem_index(s));
253
+ tcg_gen_qemu_st_i64(regs[r1], a, get_mem_index(s), MO_TEUQ);
254
break;
255
case 0: /* STOC */
256
- tcg_gen_qemu_st32(regs[r1], a, get_mem_index(s));
257
+ tcg_gen_qemu_st_i64(regs[r1], a, get_mem_index(s), MO_TEUL);
258
break;
259
case 2: /* STOCFH */
260
h = tcg_temp_new_i64();
261
tcg_gen_shri_i64(h, regs[r1], 32);
262
- tcg_gen_qemu_st32(h, a, get_mem_index(s));
263
+ tcg_gen_qemu_st_i64(h, a, get_mem_index(s), MO_TEUL);
264
break;
265
default:
266
g_assert_not_reached();
267
@@ -XXX,XX +XXX,XX @@ static DisasJumpType op_ectg(DisasContext *s, DisasOps *o)
268
gen_addi_and_wrap_i64(s, o->addr1, regs[r3], 0);
269
270
/* load the third operand into r3 before modifying anything */
271
- tcg_gen_qemu_ld64(regs[r3], o->addr1, get_mem_index(s));
272
+ tcg_gen_qemu_ld_i64(regs[r3], o->addr1, get_mem_index(s), MO_TEUQ);
273
274
/* subtract CPU timer from first operand and store in GR0 */
275
gen_helper_stpt(tmp, cpu_env);
276
@@ -XXX,XX +XXX,XX @@ static DisasJumpType op_stcke(DisasContext *s, DisasOps *o)
277
tcg_gen_shri_i64(c1, c1, 8);
278
tcg_gen_ori_i64(c2, c2, 0x10000);
279
tcg_gen_or_i64(c2, c2, todpr);
280
- tcg_gen_qemu_st64(c1, o->in2, get_mem_index(s));
281
+ tcg_gen_qemu_st_i64(c1, o->in2, get_mem_index(s), MO_TEUQ);
282
tcg_gen_addi_i64(o->in2, o->in2, 8);
283
- tcg_gen_qemu_st64(c2, o->in2, get_mem_index(s));
284
+ tcg_gen_qemu_st_i64(c2, o->in2, get_mem_index(s), MO_TEUQ);
285
/* ??? We don't implement clock states. */
286
gen_op_movi_cc(s, 0);
287
return DISAS_NEXT;
288
@@ -XXX,XX +XXX,XX @@ static DisasJumpType op_stnosm(DisasContext *s, DisasOps *o)
289
restart, we'll have the wrong SYSTEM MASK in place. */
290
t = tcg_temp_new_i64();
291
tcg_gen_shri_i64(t, psw_mask, 56);
292
- tcg_gen_qemu_st8(t, o->addr1, get_mem_index(s));
293
+ tcg_gen_qemu_st_i64(t, o->addr1, get_mem_index(s), MO_UB);
294
295
if (s->fields.op == 0xac) {
296
tcg_gen_andi_i64(psw_mask, psw_mask,
297
@@ -XXX,XX +XXX,XX @@ static DisasJumpType op_stfle(DisasContext *s, DisasOps *o)
298
299
static DisasJumpType op_st8(DisasContext *s, DisasOps *o)
300
{
301
- tcg_gen_qemu_st8(o->in1, o->in2, get_mem_index(s));
302
+ tcg_gen_qemu_st_i64(o->in1, o->in2, get_mem_index(s), MO_UB);
303
return DISAS_NEXT;
304
}
305
306
static DisasJumpType op_st16(DisasContext *s, DisasOps *o)
307
{
308
- tcg_gen_qemu_st16(o->in1, o->in2, get_mem_index(s));
309
+ tcg_gen_qemu_st_i64(o->in1, o->in2, get_mem_index(s), MO_TEUW);
310
return DISAS_NEXT;
311
}
312
313
@@ -XXX,XX +XXX,XX @@ static DisasJumpType op_stcm(DisasContext *s, DisasOps *o)
314
case 0xf:
315
/* Effectively a 32-bit store. */
316
tcg_gen_shri_i64(tmp, o->in1, pos);
317
- tcg_gen_qemu_st32(tmp, o->in2, get_mem_index(s));
318
+ tcg_gen_qemu_st_i64(tmp, o->in2, get_mem_index(s), MO_TEUL);
319
break;
320
321
case 0xc:
322
@@ -XXX,XX +XXX,XX @@ static DisasJumpType op_stcm(DisasContext *s, DisasOps *o)
323
case 0x3:
324
/* Effectively a 16-bit store. */
325
tcg_gen_shri_i64(tmp, o->in1, pos);
326
- tcg_gen_qemu_st16(tmp, o->in2, get_mem_index(s));
327
+ tcg_gen_qemu_st_i64(tmp, o->in2, get_mem_index(s), MO_TEUW);
328
break;
329
330
case 0x8:
331
@@ -XXX,XX +XXX,XX @@ static DisasJumpType op_stcm(DisasContext *s, DisasOps *o)
332
case 0x1:
333
/* Effectively an 8-bit store. */
334
tcg_gen_shri_i64(tmp, o->in1, pos);
335
- tcg_gen_qemu_st8(tmp, o->in2, get_mem_index(s));
336
+ tcg_gen_qemu_st_i64(tmp, o->in2, get_mem_index(s), MO_UB);
337
break;
338
339
default:
340
@@ -XXX,XX +XXX,XX @@ static DisasJumpType op_stcm(DisasContext *s, DisasOps *o)
341
while (m3) {
342
if (m3 & 0x8) {
343
tcg_gen_shri_i64(tmp, o->in1, pos);
344
- tcg_gen_qemu_st8(tmp, o->in2, get_mem_index(s));
345
+ tcg_gen_qemu_st_i64(tmp, o->in2, get_mem_index(s), MO_UB);
346
tcg_gen_addi_i64(o->in2, o->in2, 1);
347
}
348
m3 = (m3 << 1) & 0xf;
349
@@ -XXX,XX +XXX,XX @@ static DisasJumpType op_stm(DisasContext *s, DisasOps *o)
350
TCGv_i64 tsize = tcg_constant_i64(size);
351
352
while (1) {
353
- if (size == 8) {
354
- tcg_gen_qemu_st64(regs[r1], o->in2, get_mem_index(s));
355
- } else {
356
- tcg_gen_qemu_st32(regs[r1], o->in2, get_mem_index(s));
357
- }
358
+ tcg_gen_qemu_st_i64(regs[r1], o->in2, get_mem_index(s),
359
+ size == 8 ? MO_TEUQ : MO_TEUL);
360
if (r1 == r3) {
361
break;
362
}
363
@@ -XXX,XX +XXX,XX @@ static DisasJumpType op_stmh(DisasContext *s, DisasOps *o)
364
365
while (1) {
366
tcg_gen_shl_i64(t, regs[r1], t32);
367
- tcg_gen_qemu_st32(t, o->in2, get_mem_index(s));
368
+ tcg_gen_qemu_st_i64(t, o->in2, get_mem_index(s), MO_TEUL);
369
if (r1 == r3) {
370
break;
371
}
372
@@ -XXX,XX +XXX,XX @@ static DisasJumpType op_xc(DisasContext *s, DisasOps *o)
373
374
l++;
375
while (l >= 8) {
376
- tcg_gen_qemu_st64(o->in2, o->addr1, get_mem_index(s));
377
+ tcg_gen_qemu_st_i64(o->in2, o->addr1, get_mem_index(s), MO_UQ);
378
l -= 8;
379
if (l > 0) {
380
tcg_gen_addi_i64(o->addr1, o->addr1, 8);
381
}
382
}
383
if (l >= 4) {
384
- tcg_gen_qemu_st32(o->in2, o->addr1, get_mem_index(s));
385
+ tcg_gen_qemu_st_i64(o->in2, o->addr1, get_mem_index(s), MO_UL);
386
l -= 4;
387
if (l > 0) {
388
tcg_gen_addi_i64(o->addr1, o->addr1, 4);
389
}
390
}
391
if (l >= 2) {
392
- tcg_gen_qemu_st16(o->in2, o->addr1, get_mem_index(s));
393
+ tcg_gen_qemu_st_i64(o->in2, o->addr1, get_mem_index(s), MO_UW);
394
l -= 2;
395
if (l > 0) {
396
tcg_gen_addi_i64(o->addr1, o->addr1, 2);
397
}
398
}
399
if (l) {
400
- tcg_gen_qemu_st8(o->in2, o->addr1, get_mem_index(s));
401
+ tcg_gen_qemu_st_i64(o->in2, o->addr1, get_mem_index(s), MO_UB);
402
}
403
gen_op_movi_cc(s, 0);
404
return DISAS_NEXT;
405
@@ -XXX,XX +XXX,XX @@ static void wout_cond_e1e2(DisasContext *s, DisasOps *o)
406
407
static void wout_m1_8(DisasContext *s, DisasOps *o)
408
{
409
- tcg_gen_qemu_st8(o->out, o->addr1, get_mem_index(s));
410
+ tcg_gen_qemu_st_i64(o->out, o->addr1, get_mem_index(s), MO_UB);
411
}
412
#define SPEC_wout_m1_8 0
413
414
static void wout_m1_16(DisasContext *s, DisasOps *o)
415
{
416
- tcg_gen_qemu_st16(o->out, o->addr1, get_mem_index(s));
417
+ tcg_gen_qemu_st_i64(o->out, o->addr1, get_mem_index(s), MO_TEUW);
418
}
419
#define SPEC_wout_m1_16 0
420
421
@@ -XXX,XX +XXX,XX @@ static void wout_m1_16a(DisasContext *s, DisasOps *o)
422
423
static void wout_m1_32(DisasContext *s, DisasOps *o)
424
{
425
- tcg_gen_qemu_st32(o->out, o->addr1, get_mem_index(s));
426
+ tcg_gen_qemu_st_i64(o->out, o->addr1, get_mem_index(s), MO_TEUL);
427
}
428
#define SPEC_wout_m1_32 0
429
430
@@ -XXX,XX +XXX,XX @@ static void wout_m1_32a(DisasContext *s, DisasOps *o)
431
432
static void wout_m1_64(DisasContext *s, DisasOps *o)
433
{
434
- tcg_gen_qemu_st64(o->out, o->addr1, get_mem_index(s));
435
+ tcg_gen_qemu_st_i64(o->out, o->addr1, get_mem_index(s), MO_TEUQ);
436
}
437
#define SPEC_wout_m1_64 0
438
439
@@ -XXX,XX +XXX,XX @@ static void wout_m1_64a(DisasContext *s, DisasOps *o)
440
441
static void wout_m2_32(DisasContext *s, DisasOps *o)
442
{
443
- tcg_gen_qemu_st32(o->out, o->in2, get_mem_index(s));
444
+ tcg_gen_qemu_st_i64(o->out, o->in2, get_mem_index(s), MO_TEUL);
445
}
446
#define SPEC_wout_m2_32 0
447
448
@@ -XXX,XX +XXX,XX @@ static void in1_m1_8u(DisasContext *s, DisasOps *o)
449
{
450
in1_la1(s, o);
451
o->in1 = tcg_temp_new_i64();
452
- tcg_gen_qemu_ld8u(o->in1, o->addr1, get_mem_index(s));
453
+ tcg_gen_qemu_ld_i64(o->in1, o->addr1, get_mem_index(s), MO_UB);
454
}
455
#define SPEC_in1_m1_8u 0
456
457
@@ -XXX,XX +XXX,XX @@ static void in1_m1_16s(DisasContext *s, DisasOps *o)
458
{
459
in1_la1(s, o);
460
o->in1 = tcg_temp_new_i64();
461
- tcg_gen_qemu_ld16s(o->in1, o->addr1, get_mem_index(s));
462
+ tcg_gen_qemu_ld_i64(o->in1, o->addr1, get_mem_index(s), MO_TESW);
463
}
464
#define SPEC_in1_m1_16s 0
465
466
@@ -XXX,XX +XXX,XX @@ static void in1_m1_16u(DisasContext *s, DisasOps *o)
467
{
468
in1_la1(s, o);
469
o->in1 = tcg_temp_new_i64();
470
- tcg_gen_qemu_ld16u(o->in1, o->addr1, get_mem_index(s));
471
+ tcg_gen_qemu_ld_i64(o->in1, o->addr1, get_mem_index(s), MO_TEUW);
472
}
473
#define SPEC_in1_m1_16u 0
474
475
@@ -XXX,XX +XXX,XX @@ static void in1_m1_32s(DisasContext *s, DisasOps *o)
476
{
477
in1_la1(s, o);
478
o->in1 = tcg_temp_new_i64();
479
- tcg_gen_qemu_ld32s(o->in1, o->addr1, get_mem_index(s));
480
+ tcg_gen_qemu_ld_i64(o->in1, o->addr1, get_mem_index(s), MO_TESL);
481
}
482
#define SPEC_in1_m1_32s 0
483
484
@@ -XXX,XX +XXX,XX @@ static void in1_m1_32u(DisasContext *s, DisasOps *o)
485
{
486
in1_la1(s, o);
487
o->in1 = tcg_temp_new_i64();
488
- tcg_gen_qemu_ld32u(o->in1, o->addr1, get_mem_index(s));
489
+ tcg_gen_qemu_ld_i64(o->in1, o->addr1, get_mem_index(s), MO_TEUL);
490
}
491
#define SPEC_in1_m1_32u 0
492
493
@@ -XXX,XX +XXX,XX @@ static void in1_m1_64(DisasContext *s, DisasOps *o)
494
{
495
in1_la1(s, o);
496
o->in1 = tcg_temp_new_i64();
497
- tcg_gen_qemu_ld64(o->in1, o->addr1, get_mem_index(s));
498
+ tcg_gen_qemu_ld_i64(o->in1, o->addr1, get_mem_index(s), MO_TEUQ);
499
}
500
#define SPEC_in1_m1_64 0
501
502
@@ -XXX,XX +XXX,XX @@ static void in2_sh(DisasContext *s, DisasOps *o)
503
static void in2_m2_8u(DisasContext *s, DisasOps *o)
504
{
505
in2_a2(s, o);
506
- tcg_gen_qemu_ld8u(o->in2, o->in2, get_mem_index(s));
507
+ tcg_gen_qemu_ld_i64(o->in2, o->in2, get_mem_index(s), MO_UB);
508
}
509
#define SPEC_in2_m2_8u 0
510
511
static void in2_m2_16s(DisasContext *s, DisasOps *o)
512
{
513
in2_a2(s, o);
514
- tcg_gen_qemu_ld16s(o->in2, o->in2, get_mem_index(s));
515
+ tcg_gen_qemu_ld_i64(o->in2, o->in2, get_mem_index(s), MO_TESW);
516
}
517
#define SPEC_in2_m2_16s 0
518
519
static void in2_m2_16u(DisasContext *s, DisasOps *o)
520
{
521
in2_a2(s, o);
522
- tcg_gen_qemu_ld16u(o->in2, o->in2, get_mem_index(s));
523
+ tcg_gen_qemu_ld_i64(o->in2, o->in2, get_mem_index(s), MO_TEUW);
524
}
525
#define SPEC_in2_m2_16u 0
526
527
static void in2_m2_32s(DisasContext *s, DisasOps *o)
528
{
529
in2_a2(s, o);
530
- tcg_gen_qemu_ld32s(o->in2, o->in2, get_mem_index(s));
531
+ tcg_gen_qemu_ld_i64(o->in2, o->in2, get_mem_index(s), MO_TESL);
532
}
533
#define SPEC_in2_m2_32s 0
534
535
static void in2_m2_32u(DisasContext *s, DisasOps *o)
536
{
537
in2_a2(s, o);
538
- tcg_gen_qemu_ld32u(o->in2, o->in2, get_mem_index(s));
539
+ tcg_gen_qemu_ld_i64(o->in2, o->in2, get_mem_index(s), MO_TEUL);
540
}
541
#define SPEC_in2_m2_32u 0
542
543
@@ -XXX,XX +XXX,XX @@ static void in2_m2_32ua(DisasContext *s, DisasOps *o)
544
static void in2_m2_64(DisasContext *s, DisasOps *o)
545
{
546
in2_a2(s, o);
547
- tcg_gen_qemu_ld64(o->in2, o->in2, get_mem_index(s));
548
+ tcg_gen_qemu_ld_i64(o->in2, o->in2, get_mem_index(s), MO_TEUQ);
549
}
550
#define SPEC_in2_m2_64 0
551
552
static void in2_m2_64w(DisasContext *s, DisasOps *o)
553
{
554
in2_a2(s, o);
555
- tcg_gen_qemu_ld64(o->in2, o->in2, get_mem_index(s));
556
+ tcg_gen_qemu_ld_i64(o->in2, o->in2, get_mem_index(s), MO_TEUQ);
557
gen_addi_and_wrap_i64(s, o->in2, o->in2, 0);
558
}
559
#define SPEC_in2_m2_64w 0
560
@@ -XXX,XX +XXX,XX @@ static void in2_m2_64a(DisasContext *s, DisasOps *o)
561
static void in2_mri2_16s(DisasContext *s, DisasOps *o)
562
{
563
o->in2 = tcg_temp_new_i64();
564
- tcg_gen_qemu_ld16s(o->in2, gen_ri2(s), get_mem_index(s));
565
+ tcg_gen_qemu_ld_i64(o->in2, gen_ri2(s), get_mem_index(s), MO_TESW);
566
}
567
#define SPEC_in2_mri2_16s 0
568
569
static void in2_mri2_16u(DisasContext *s, DisasOps *o)
570
{
571
o->in2 = tcg_temp_new_i64();
572
- tcg_gen_qemu_ld16u(o->in2, gen_ri2(s), get_mem_index(s));
573
+ tcg_gen_qemu_ld_i64(o->in2, gen_ri2(s), get_mem_index(s), MO_TEUW);
574
}
575
#define SPEC_in2_mri2_16u 0
576
577
--
578
2.34.1
diff view generated by jsdifflib
New patch
[PULL 08/42] target/sparc: Finish conversion to tcg_gen_qemu_{ld, st}_*
1
Convert away from the old interface with the implicit
2
MemOp argument.
1
3
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
Reviewed-by: Anton Johansson <anjo@rev.ng>
6
Message-Id: <20230502135741.1158035-8-richard.henderson@linaro.org>
7
---
8
target/sparc/translate.c | 43 ++++++++++++++++++++++++++--------------
9
1 file changed, 28 insertions(+), 15 deletions(-)
10
11
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/sparc/translate.c
14
+++ b/target/sparc/translate.c
15
@@ -XXX,XX +XXX,XX @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
16
switch (xop) {
17
case 0x0: /* ld, V9 lduw, load unsigned word */
18
gen_address_mask(dc, cpu_addr);
19
- tcg_gen_qemu_ld32u(cpu_val, cpu_addr, dc->mem_idx);
20
+ tcg_gen_qemu_ld_tl(cpu_val, cpu_addr,
21
+ dc->mem_idx, MO_TEUL);
22
break;
23
case 0x1: /* ldub, load unsigned byte */
24
gen_address_mask(dc, cpu_addr);
25
- tcg_gen_qemu_ld8u(cpu_val, cpu_addr, dc->mem_idx);
26
+ tcg_gen_qemu_ld_tl(cpu_val, cpu_addr,
27
+ dc->mem_idx, MO_UB);
28
break;
29
case 0x2: /* lduh, load unsigned halfword */
30
gen_address_mask(dc, cpu_addr);
31
- tcg_gen_qemu_ld16u(cpu_val, cpu_addr, dc->mem_idx);
32
+ tcg_gen_qemu_ld_tl(cpu_val, cpu_addr,
33
+ dc->mem_idx, MO_TEUW);
34
break;
35
case 0x3: /* ldd, load double word */
36
if (rd & 1)
37
@@ -XXX,XX +XXX,XX @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
38
39
gen_address_mask(dc, cpu_addr);
40
t64 = tcg_temp_new_i64();
41
- tcg_gen_qemu_ld64(t64, cpu_addr, dc->mem_idx);
42
+ tcg_gen_qemu_ld_i64(t64, cpu_addr,
43
+ dc->mem_idx, MO_TEUQ);
44
tcg_gen_trunc_i64_tl(cpu_val, t64);
45
tcg_gen_ext32u_tl(cpu_val, cpu_val);
46
gen_store_gpr(dc, rd + 1, cpu_val);
47
@@ -XXX,XX +XXX,XX @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
48
break;
49
case 0x9: /* ldsb, load signed byte */
50
gen_address_mask(dc, cpu_addr);
51
- tcg_gen_qemu_ld8s(cpu_val, cpu_addr, dc->mem_idx);
52
+ tcg_gen_qemu_ld_tl(cpu_val, cpu_addr, dc->mem_idx, MO_SB);
53
break;
54
case 0xa: /* ldsh, load signed halfword */
55
gen_address_mask(dc, cpu_addr);
56
- tcg_gen_qemu_ld16s(cpu_val, cpu_addr, dc->mem_idx);
57
+ tcg_gen_qemu_ld_tl(cpu_val, cpu_addr,
58
+ dc->mem_idx, MO_TESW);
59
break;
60
case 0xd: /* ldstub */
61
gen_ldstub(dc, cpu_val, cpu_addr, dc->mem_idx);
62
@@ -XXX,XX +XXX,XX @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
63
#ifdef TARGET_SPARC64
64
case 0x08: /* V9 ldsw */
65
gen_address_mask(dc, cpu_addr);
66
- tcg_gen_qemu_ld32s(cpu_val, cpu_addr, dc->mem_idx);
67
+ tcg_gen_qemu_ld_tl(cpu_val, cpu_addr,
68
+ dc->mem_idx, MO_TESL);
69
break;
70
case 0x0b: /* V9 ldx */
71
gen_address_mask(dc, cpu_addr);
72
- tcg_gen_qemu_ld64(cpu_val, cpu_addr, dc->mem_idx);
73
+ tcg_gen_qemu_ld_tl(cpu_val, cpu_addr,
74
+ dc->mem_idx, MO_TEUQ);
75
break;
76
case 0x18: /* V9 ldswa */
77
gen_ld_asi(dc, cpu_val, cpu_addr, insn, MO_TESL);
78
@@ -XXX,XX +XXX,XX @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
79
switch (xop) {
80
case 0x4: /* st, store word */
81
gen_address_mask(dc, cpu_addr);
82
- tcg_gen_qemu_st32(cpu_val, cpu_addr, dc->mem_idx);
83
+ tcg_gen_qemu_st_tl(cpu_val, cpu_addr,
84
+ dc->mem_idx, MO_TEUL);
85
break;
86
case 0x5: /* stb, store byte */
87
gen_address_mask(dc, cpu_addr);
88
- tcg_gen_qemu_st8(cpu_val, cpu_addr, dc->mem_idx);
89
+ tcg_gen_qemu_st_tl(cpu_val, cpu_addr, dc->mem_idx, MO_UB);
90
break;
91
case 0x6: /* sth, store halfword */
92
gen_address_mask(dc, cpu_addr);
93
- tcg_gen_qemu_st16(cpu_val, cpu_addr, dc->mem_idx);
94
+ tcg_gen_qemu_st_tl(cpu_val, cpu_addr,
95
+ dc->mem_idx, MO_TEUW);
96
break;
97
case 0x7: /* std, store double word */
98
if (rd & 1)
99
@@ -XXX,XX +XXX,XX @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
100
lo = gen_load_gpr(dc, rd + 1);
101
t64 = tcg_temp_new_i64();
102
tcg_gen_concat_tl_i64(t64, lo, cpu_val);
103
- tcg_gen_qemu_st64(t64, cpu_addr, dc->mem_idx);
104
+ tcg_gen_qemu_st_i64(t64, cpu_addr,
105
+ dc->mem_idx, MO_TEUQ);
106
}
107
break;
108
#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
109
@@ -XXX,XX +XXX,XX @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
110
#ifdef TARGET_SPARC64
111
case 0x0e: /* V9 stx */
112
gen_address_mask(dc, cpu_addr);
113
- tcg_gen_qemu_st64(cpu_val, cpu_addr, dc->mem_idx);
114
+ tcg_gen_qemu_st_tl(cpu_val, cpu_addr,
115
+ dc->mem_idx, MO_TEUQ);
116
break;
117
case 0x1e: /* V9 stxa */
118
gen_st_asi(dc, cpu_val, cpu_addr, insn, MO_TEUQ);
119
@@ -XXX,XX +XXX,XX @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
120
#ifdef TARGET_SPARC64
121
gen_address_mask(dc, cpu_addr);
122
if (rd == 1) {
123
- tcg_gen_qemu_st64(cpu_fsr, cpu_addr, dc->mem_idx);
124
+ tcg_gen_qemu_st_tl(cpu_fsr, cpu_addr,
125
+ dc->mem_idx, MO_TEUQ);
126
break;
127
}
128
#endif
129
- tcg_gen_qemu_st32(cpu_fsr, cpu_addr, dc->mem_idx);
130
+ tcg_gen_qemu_st_tl(cpu_fsr, cpu_addr,
131
+ dc->mem_idx, MO_TEUL);
132
}
133
break;
134
case 0x26:
135
--
136
2.34.1
diff view generated by jsdifflib
New patch
[PULL 09/42] target/xtensa: Finish conversion to tcg_gen_qemu_{ld, st}_*
1
Convert away from the old interface with the implicit
2
MemOp argument.
1
3
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
Reviewed-by: Max Filippov <jcmvbkbc@gmail.com>
6
Message-Id: <20230502135741.1158035-9-richard.henderson@linaro.org>
7
---
8
target/xtensa/translate.c | 4 ++--
9
1 file changed, 2 insertions(+), 2 deletions(-)
10
11
diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/xtensa/translate.c
14
+++ b/target/xtensa/translate.c
15
@@ -XXX,XX +XXX,XX @@ static void translate_dcache(DisasContext *dc, const OpcodeArg arg[],
16
TCGv_i32 res = tcg_temp_new_i32();
17
18
tcg_gen_addi_i32(addr, arg[0].in, arg[1].imm);
19
- tcg_gen_qemu_ld8u(res, addr, dc->cring);
20
+ tcg_gen_qemu_ld_i32(res, addr, dc->cring, MO_UB);
21
}
22
23
static void translate_depbits(DisasContext *dc, const OpcodeArg arg[],
24
@@ -XXX,XX +XXX,XX @@ static void translate_l32r(DisasContext *dc, const OpcodeArg arg[],
25
} else {
26
tmp = tcg_constant_i32(arg[1].imm);
27
}
28
- tcg_gen_qemu_ld32u(arg[0].out, tmp, dc->cring);
29
+ tcg_gen_qemu_ld_i32(arg[0].out, tmp, dc->cring, MO_TEUL);
30
}
31
32
static void translate_loop(DisasContext *dc, const OpcodeArg arg[],
33
--
34
2.34.1
diff view generated by jsdifflib
[PULL 1/3] accel/tcg: split CpusAccel into three TCG variants
[PULL 10/42] tcg: Remove compatability helpers for qemu ld/st
1
From: Claudio Fontana <cfontana@suse.de>
1
Remove the old interfaces with the implicit MemOp argument.
2
2
3
split up the CpusAccel tcg_cpus into three TCG variants:
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Acked-by: David Hildenbrand <david@redhat.com>
5
Message-Id: <20230502135741.1158035-10-richard.henderson@linaro.org>
6
---
7
include/tcg/tcg-op.h | 55 --------------------------------------------
8
1 file changed, 55 deletions(-)
4
9
5
tcg_cpus_rr (single threaded, round robin cpus)
10
diff --git a/include/tcg/tcg-op.h b/include/tcg/tcg-op.h
6
tcg_cpus_icount (same as rr, but with instruction counting enabled)
7
tcg_cpus_mttcg (multi-threaded cpus)
8
9
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
10
Signed-off-by: Claudio Fontana <cfontana@suse.de>
11
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
12
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
13
Message-Id: <20201015143217.29337-2-cfontana@suse.de>
14
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
15
---
16
accel/tcg/tcg-cpus-icount.h | 17 ++
17
accel/tcg/tcg-cpus-mttcg.h | 21 ++
18
accel/tcg/tcg-cpus-rr.h | 20 ++
19
accel/tcg/tcg-cpus.h | 13 +-
20
accel/tcg/tcg-all.c | 8 +-
21
accel/tcg/tcg-cpus-icount.c | 147 +++++++++++
22
accel/tcg/tcg-cpus-mttcg.c | 117 +++++++++
23
accel/tcg/tcg-cpus-rr.c | 270 ++++++++++++++++++++
24
accel/tcg/tcg-cpus.c | 484 ++----------------------------------
25
softmmu/icount.c | 2 +-
26
accel/tcg/meson.build | 9 +-
27
11 files changed, 646 insertions(+), 462 deletions(-)
28
create mode 100644 accel/tcg/tcg-cpus-icount.h
29
create mode 100644 accel/tcg/tcg-cpus-mttcg.h
30
create mode 100644 accel/tcg/tcg-cpus-rr.h
31
create mode 100644 accel/tcg/tcg-cpus-icount.c
32
create mode 100644 accel/tcg/tcg-cpus-mttcg.c
33
create mode 100644 accel/tcg/tcg-cpus-rr.c
34
35
diff --git a/accel/tcg/tcg-cpus-icount.h b/accel/tcg/tcg-cpus-icount.h
36
new file mode 100644
37
index XXXXXXX..XXXXXXX
38
--- /dev/null
39
+++ b/accel/tcg/tcg-cpus-icount.h
40
@@ -XXX,XX +XXX,XX @@
41
+/*
42
+ * QEMU TCG Single Threaded vCPUs implementation using instruction counting
43
+ *
44
+ * Copyright 2020 SUSE LLC
45
+ *
46
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
47
+ * See the COPYING file in the top-level directory.
48
+ */
49
+
50
+#ifndef TCG_CPUS_ICOUNT_H
51
+#define TCG_CPUS_ICOUNT_H
52
+
53
+void handle_icount_deadline(void);
54
+void prepare_icount_for_run(CPUState *cpu);
55
+void process_icount_data(CPUState *cpu);
56
+
57
+#endif /* TCG_CPUS_ICOUNT_H */
58
diff --git a/accel/tcg/tcg-cpus-mttcg.h b/accel/tcg/tcg-cpus-mttcg.h
59
new file mode 100644
60
index XXXXXXX..XXXXXXX
61
--- /dev/null
62
+++ b/accel/tcg/tcg-cpus-mttcg.h
63
@@ -XXX,XX +XXX,XX @@
64
+/*
65
+ * QEMU TCG Multi Threaded vCPUs implementation
66
+ *
67
+ * Copyright 2020 SUSE LLC
68
+ *
69
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
70
+ * See the COPYING file in the top-level directory.
71
+ */
72
+
73
+#ifndef TCG_CPUS_MTTCG_H
74
+#define TCG_CPUS_MTTCG_H
75
+
76
+/*
77
+ * In the multi-threaded case each vCPU has its own thread. The TLS
78
+ * variable current_cpu can be used deep in the code to find the
79
+ * current CPUState for a given thread.
80
+ */
81
+
82
+void *tcg_cpu_thread_fn(void *arg);
83
+
84
+#endif /* TCG_CPUS_MTTCG_H */
85
diff --git a/accel/tcg/tcg-cpus-rr.h b/accel/tcg/tcg-cpus-rr.h
86
new file mode 100644
87
index XXXXXXX..XXXXXXX
88
--- /dev/null
89
+++ b/accel/tcg/tcg-cpus-rr.h
90
@@ -XXX,XX +XXX,XX @@
91
+/*
92
+ * QEMU TCG Single Threaded vCPUs implementation
93
+ *
94
+ * Copyright 2020 SUSE LLC
95
+ *
96
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
97
+ * See the COPYING file in the top-level directory.
98
+ */
99
+
100
+#ifndef TCG_CPUS_RR_H
101
+#define TCG_CPUS_RR_H
102
+
103
+#define TCG_KICK_PERIOD (NANOSECONDS_PER_SECOND / 10)
104
+
105
+/* Kick all RR vCPUs. */
106
+void qemu_cpu_kick_rr_cpus(CPUState *unused);
107
+
108
+void *tcg_rr_cpu_thread_fn(void *arg);
109
+
110
+#endif /* TCG_CPUS_RR_H */
111
diff --git a/accel/tcg/tcg-cpus.h b/accel/tcg/tcg-cpus.h
112
index XXXXXXX..XXXXXXX 100644
11
index XXXXXXX..XXXXXXX 100644
113
--- a/accel/tcg/tcg-cpus.h
12
--- a/include/tcg/tcg-op.h
114
+++ b/accel/tcg/tcg-cpus.h
13
+++ b/include/tcg/tcg-op.h
115
@@ -XXX,XX +XXX,XX @@
14
@@ -XXX,XX +XXX,XX @@ void tcg_gen_qemu_st_i64(TCGv_i64, TCGv, TCGArg, MemOp);
116
/*
15
void tcg_gen_qemu_ld_i128(TCGv_i128, TCGv, TCGArg, MemOp);
117
- * Accelerator CPUS Interface
16
void tcg_gen_qemu_st_i128(TCGv_i128, TCGv, TCGArg, MemOp);
118
+ * QEMU TCG vCPU common functionality
17
119
+ *
18
-static inline void tcg_gen_qemu_ld8u(TCGv ret, TCGv addr, int mem_index)
120
+ * Functionality common to all TCG vcpu variants: mttcg, rr and icount.
121
*
122
* Copyright 2020 SUSE LLC
123
*
124
@@ -XXX,XX +XXX,XX @@
125
126
#include "sysemu/cpus.h"
127
128
-extern const CpusAccel tcg_cpus;
129
+extern const CpusAccel tcg_cpus_mttcg;
130
+extern const CpusAccel tcg_cpus_icount;
131
+extern const CpusAccel tcg_cpus_rr;
132
+
133
+void tcg_start_vcpu_thread(CPUState *cpu);
134
+void qemu_tcg_destroy_vcpu(CPUState *cpu);
135
+int tcg_cpu_exec(CPUState *cpu);
136
+void tcg_handle_interrupt(CPUState *cpu, int mask);
137
138
#endif /* TCG_CPUS_H */
139
diff --git a/accel/tcg/tcg-all.c b/accel/tcg/tcg-all.c
140
index XXXXXXX..XXXXXXX 100644
141
--- a/accel/tcg/tcg-all.c
142
+++ b/accel/tcg/tcg-all.c
143
@@ -XXX,XX +XXX,XX @@ static int tcg_init(MachineState *ms)
144
145
tcg_exec_init(s->tb_size * 1024 * 1024);
146
mttcg_enabled = s->mttcg_enabled;
147
- cpus_register_accel(&tcg_cpus);
148
149
+ if (mttcg_enabled) {
150
+ cpus_register_accel(&tcg_cpus_mttcg);
151
+ } else if (icount_enabled()) {
152
+ cpus_register_accel(&tcg_cpus_icount);
153
+ } else {
154
+ cpus_register_accel(&tcg_cpus_rr);
155
+ }
156
return 0;
157
}
158
159
diff --git a/accel/tcg/tcg-cpus-icount.c b/accel/tcg/tcg-cpus-icount.c
160
new file mode 100644
161
index XXXXXXX..XXXXXXX
162
--- /dev/null
163
+++ b/accel/tcg/tcg-cpus-icount.c
164
@@ -XXX,XX +XXX,XX @@
165
+/*
166
+ * QEMU TCG Single Threaded vCPUs implementation using instruction counting
167
+ *
168
+ * Copyright (c) 2003-2008 Fabrice Bellard
169
+ * Copyright (c) 2014 Red Hat Inc.
170
+ *
171
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
172
+ * of this software and associated documentation files (the "Software"), to deal
173
+ * in the Software without restriction, including without limitation the rights
174
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
175
+ * copies of the Software, and to permit persons to whom the Software is
176
+ * furnished to do so, subject to the following conditions:
177
+ *
178
+ * The above copyright notice and this permission notice shall be included in
179
+ * all copies or substantial portions of the Software.
180
+ *
181
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
182
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
183
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
184
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
185
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
186
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
187
+ * THE SOFTWARE.
188
+ */
189
+
190
+#include "qemu/osdep.h"
191
+#include "qemu-common.h"
192
+#include "sysemu/tcg.h"
193
+#include "sysemu/replay.h"
194
+#include "qemu/main-loop.h"
195
+#include "qemu/guest-random.h"
196
+#include "exec/exec-all.h"
197
+#include "hw/boards.h"
198
+
199
+#include "tcg-cpus.h"
200
+#include "tcg-cpus-icount.h"
201
+#include "tcg-cpus-rr.h"
202
+
203
+static int64_t tcg_get_icount_limit(void)
204
+{
205
+ int64_t deadline;
206
+
207
+ if (replay_mode != REPLAY_MODE_PLAY) {
208
+ /*
209
+ * Include all the timers, because they may need an attention.
210
+ * Too long CPU execution may create unnecessary delay in UI.
211
+ */
212
+ deadline = qemu_clock_deadline_ns_all(QEMU_CLOCK_VIRTUAL,
213
+ QEMU_TIMER_ATTR_ALL);
214
+ /* Check realtime timers, because they help with input processing */
215
+ deadline = qemu_soonest_timeout(deadline,
216
+ qemu_clock_deadline_ns_all(QEMU_CLOCK_REALTIME,
217
+ QEMU_TIMER_ATTR_ALL));
218
+
219
+ /*
220
+ * Maintain prior (possibly buggy) behaviour where if no deadline
221
+ * was set (as there is no QEMU_CLOCK_VIRTUAL timer) or it is more than
222
+ * INT32_MAX nanoseconds ahead, we still use INT32_MAX
223
+ * nanoseconds.
224
+ */
225
+ if ((deadline < 0) || (deadline > INT32_MAX)) {
226
+ deadline = INT32_MAX;
227
+ }
228
+
229
+ return icount_round(deadline);
230
+ } else {
231
+ return replay_get_instructions();
232
+ }
233
+}
234
+
235
+static void notify_aio_contexts(void)
236
+{
237
+ /* Wake up other AioContexts. */
238
+ qemu_clock_notify(QEMU_CLOCK_VIRTUAL);
239
+ qemu_clock_run_timers(QEMU_CLOCK_VIRTUAL);
240
+}
241
+
242
+void handle_icount_deadline(void)
243
+{
244
+ assert(qemu_in_vcpu_thread());
245
+ int64_t deadline = qemu_clock_deadline_ns_all(QEMU_CLOCK_VIRTUAL,
246
+ QEMU_TIMER_ATTR_ALL);
247
+
248
+ if (deadline == 0) {
249
+ notify_aio_contexts();
250
+ }
251
+}
252
+
253
+void prepare_icount_for_run(CPUState *cpu)
254
+{
255
+ int insns_left;
256
+
257
+ /*
258
+ * These should always be cleared by process_icount_data after
259
+ * each vCPU execution. However u16.high can be raised
260
+ * asynchronously by cpu_exit/cpu_interrupt/tcg_handle_interrupt
261
+ */
262
+ g_assert(cpu_neg(cpu)->icount_decr.u16.low == 0);
263
+ g_assert(cpu->icount_extra == 0);
264
+
265
+ cpu->icount_budget = tcg_get_icount_limit();
266
+ insns_left = MIN(0xffff, cpu->icount_budget);
267
+ cpu_neg(cpu)->icount_decr.u16.low = insns_left;
268
+ cpu->icount_extra = cpu->icount_budget - insns_left;
269
+
270
+ replay_mutex_lock();
271
+
272
+ if (cpu->icount_budget == 0 && replay_has_checkpoint()) {
273
+ notify_aio_contexts();
274
+ }
275
+}
276
+
277
+void process_icount_data(CPUState *cpu)
278
+{
279
+ /* Account for executed instructions */
280
+ icount_update(cpu);
281
+
282
+ /* Reset the counters */
283
+ cpu_neg(cpu)->icount_decr.u16.low = 0;
284
+ cpu->icount_extra = 0;
285
+ cpu->icount_budget = 0;
286
+
287
+ replay_account_executed_instructions();
288
+
289
+ replay_mutex_unlock();
290
+}
291
+
292
+static void icount_handle_interrupt(CPUState *cpu, int mask)
293
+{
294
+ int old_mask = cpu->interrupt_request;
295
+
296
+ tcg_handle_interrupt(cpu, mask);
297
+ if (qemu_cpu_is_self(cpu) &&
298
+ !cpu->can_do_io
299
+ && (mask & ~old_mask) != 0) {
300
+ cpu_abort(cpu, "Raised interrupt while not in I/O function");
301
+ }
302
+}
303
+
304
+const CpusAccel tcg_cpus_icount = {
305
+ .create_vcpu_thread = tcg_start_vcpu_thread,
306
+ .kick_vcpu_thread = qemu_cpu_kick_rr_cpus,
307
+
308
+ .handle_interrupt = icount_handle_interrupt,
309
+ .get_virtual_clock = icount_get,
310
+ .get_elapsed_ticks = icount_get,
311
+};
312
diff --git a/accel/tcg/tcg-cpus-mttcg.c b/accel/tcg/tcg-cpus-mttcg.c
313
new file mode 100644
314
index XXXXXXX..XXXXXXX
315
--- /dev/null
316
+++ b/accel/tcg/tcg-cpus-mttcg.c
317
@@ -XXX,XX +XXX,XX @@
318
+/*
319
+ * QEMU TCG Multi Threaded vCPUs implementation
320
+ *
321
+ * Copyright (c) 2003-2008 Fabrice Bellard
322
+ * Copyright (c) 2014 Red Hat Inc.
323
+ *
324
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
325
+ * of this software and associated documentation files (the "Software"), to deal
326
+ * in the Software without restriction, including without limitation the rights
327
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
328
+ * copies of the Software, and to permit persons to whom the Software is
329
+ * furnished to do so, subject to the following conditions:
330
+ *
331
+ * The above copyright notice and this permission notice shall be included in
332
+ * all copies or substantial portions of the Software.
333
+ *
334
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
335
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
336
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
337
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
338
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
339
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
340
+ * THE SOFTWARE.
341
+ */
342
+
343
+#include "qemu/osdep.h"
344
+#include "qemu-common.h"
345
+#include "sysemu/tcg.h"
346
+#include "sysemu/replay.h"
347
+#include "qemu/main-loop.h"
348
+#include "qemu/guest-random.h"
349
+#include "exec/exec-all.h"
350
+#include "hw/boards.h"
351
+
352
+#include "tcg-cpus.h"
353
+#include "tcg-cpus-mttcg.h"
354
+
355
+/*
356
+ * In the multi-threaded case each vCPU has its own thread. The TLS
357
+ * variable current_cpu can be used deep in the code to find the
358
+ * current CPUState for a given thread.
359
+ */
360
+
361
+void *tcg_cpu_thread_fn(void *arg)
362
+{
363
+ CPUState *cpu = arg;
364
+
365
+ assert(tcg_enabled());
366
+ g_assert(!icount_enabled());
367
+
368
+ rcu_register_thread();
369
+ tcg_register_thread();
370
+
371
+ qemu_mutex_lock_iothread();
372
+ qemu_thread_get_self(cpu->thread);
373
+
374
+ cpu->thread_id = qemu_get_thread_id();
375
+ cpu->can_do_io = 1;
376
+ current_cpu = cpu;
377
+ cpu_thread_signal_created(cpu);
378
+ qemu_guest_random_seed_thread_part2(cpu->random_seed);
379
+
380
+ /* process any pending work */
381
+ cpu->exit_request = 1;
382
+
383
+ do {
384
+ if (cpu_can_run(cpu)) {
385
+ int r;
386
+ qemu_mutex_unlock_iothread();
387
+ r = tcg_cpu_exec(cpu);
388
+ qemu_mutex_lock_iothread();
389
+ switch (r) {
390
+ case EXCP_DEBUG:
391
+ cpu_handle_guest_debug(cpu);
392
+ break;
393
+ case EXCP_HALTED:
394
+ /*
395
+ * during start-up the vCPU is reset and the thread is
396
+ * kicked several times. If we don't ensure we go back
397
+ * to sleep in the halted state we won't cleanly
398
+ * start-up when the vCPU is enabled.
399
+ *
400
+ * cpu->halted should ensure we sleep in wait_io_event
401
+ */
402
+ g_assert(cpu->halted);
403
+ break;
404
+ case EXCP_ATOMIC:
405
+ qemu_mutex_unlock_iothread();
406
+ cpu_exec_step_atomic(cpu);
407
+ qemu_mutex_lock_iothread();
408
+ default:
409
+ /* Ignore everything else? */
410
+ break;
411
+ }
412
+ }
413
+
414
+ qatomic_mb_set(&cpu->exit_request, 0);
415
+ qemu_wait_io_event(cpu);
416
+ } while (!cpu->unplug || cpu_can_run(cpu));
417
+
418
+ qemu_tcg_destroy_vcpu(cpu);
419
+ qemu_mutex_unlock_iothread();
420
+ rcu_unregister_thread();
421
+ return NULL;
422
+}
423
+
424
+static void mttcg_kick_vcpu_thread(CPUState *cpu)
425
+{
426
+ cpu_exit(cpu);
427
+}
428
+
429
+const CpusAccel tcg_cpus_mttcg = {
430
+ .create_vcpu_thread = tcg_start_vcpu_thread,
431
+ .kick_vcpu_thread = mttcg_kick_vcpu_thread,
432
+
433
+ .handle_interrupt = tcg_handle_interrupt,
434
+};
435
diff --git a/accel/tcg/tcg-cpus-rr.c b/accel/tcg/tcg-cpus-rr.c
436
new file mode 100644
437
index XXXXXXX..XXXXXXX
438
--- /dev/null
439
+++ b/accel/tcg/tcg-cpus-rr.c
440
@@ -XXX,XX +XXX,XX @@
441
+/*
442
+ * QEMU TCG Single Threaded vCPUs implementation
443
+ *
444
+ * Copyright (c) 2003-2008 Fabrice Bellard
445
+ * Copyright (c) 2014 Red Hat Inc.
446
+ *
447
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
448
+ * of this software and associated documentation files (the "Software"), to deal
449
+ * in the Software without restriction, including without limitation the rights
450
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
451
+ * copies of the Software, and to permit persons to whom the Software is
452
+ * furnished to do so, subject to the following conditions:
453
+ *
454
+ * The above copyright notice and this permission notice shall be included in
455
+ * all copies or substantial portions of the Software.
456
+ *
457
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
458
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
459
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
460
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
461
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
462
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
463
+ * THE SOFTWARE.
464
+ */
465
+
466
+#include "qemu/osdep.h"
467
+#include "qemu-common.h"
468
+#include "sysemu/tcg.h"
469
+#include "sysemu/replay.h"
470
+#include "qemu/main-loop.h"
471
+#include "qemu/guest-random.h"
472
+#include "exec/exec-all.h"
473
+#include "hw/boards.h"
474
+
475
+#include "tcg-cpus.h"
476
+#include "tcg-cpus-rr.h"
477
+#include "tcg-cpus-icount.h"
478
+
479
+/* Kick all RR vCPUs */
480
+void qemu_cpu_kick_rr_cpus(CPUState *unused)
481
+{
482
+ CPUState *cpu;
483
+
484
+ CPU_FOREACH(cpu) {
485
+ cpu_exit(cpu);
486
+ };
487
+}
488
+
489
+/*
490
+ * TCG vCPU kick timer
491
+ *
492
+ * The kick timer is responsible for moving single threaded vCPU
493
+ * emulation on to the next vCPU. If more than one vCPU is running a
494
+ * timer event with force a cpu->exit so the next vCPU can get
495
+ * scheduled.
496
+ *
497
+ * The timer is removed if all vCPUs are idle and restarted again once
498
+ * idleness is complete.
499
+ */
500
+
501
+static QEMUTimer *tcg_kick_vcpu_timer;
502
+static CPUState *tcg_current_rr_cpu;
503
+
504
+#define TCG_KICK_PERIOD (NANOSECONDS_PER_SECOND / 10)
505
+
506
+static inline int64_t qemu_tcg_next_kick(void)
507
+{
508
+ return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + TCG_KICK_PERIOD;
509
+}
510
+
511
+/* Kick the currently round-robin scheduled vCPU to next */
512
+static void qemu_cpu_kick_rr_next_cpu(void)
513
+{
514
+ CPUState *cpu;
515
+ do {
516
+ cpu = qatomic_mb_read(&tcg_current_rr_cpu);
517
+ if (cpu) {
518
+ cpu_exit(cpu);
519
+ }
520
+ } while (cpu != qatomic_mb_read(&tcg_current_rr_cpu));
521
+}
522
+
523
+static void kick_tcg_thread(void *opaque)
524
+{
525
+ timer_mod(tcg_kick_vcpu_timer, qemu_tcg_next_kick());
526
+ qemu_cpu_kick_rr_next_cpu();
527
+}
528
+
529
+static void start_tcg_kick_timer(void)
530
+{
531
+ if (!tcg_kick_vcpu_timer && CPU_NEXT(first_cpu)) {
532
+ tcg_kick_vcpu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
533
+ kick_tcg_thread, NULL);
534
+ }
535
+ if (tcg_kick_vcpu_timer && !timer_pending(tcg_kick_vcpu_timer)) {
536
+ timer_mod(tcg_kick_vcpu_timer, qemu_tcg_next_kick());
537
+ }
538
+}
539
+
540
+static void stop_tcg_kick_timer(void)
541
+{
542
+ if (tcg_kick_vcpu_timer && timer_pending(tcg_kick_vcpu_timer)) {
543
+ timer_del(tcg_kick_vcpu_timer);
544
+ }
545
+}
546
+
547
+static void qemu_tcg_rr_wait_io_event(void)
548
+{
549
+ CPUState *cpu;
550
+
551
+ while (all_cpu_threads_idle()) {
552
+ stop_tcg_kick_timer();
553
+ qemu_cond_wait_iothread(first_cpu->halt_cond);
554
+ }
555
+
556
+ start_tcg_kick_timer();
557
+
558
+ CPU_FOREACH(cpu) {
559
+ qemu_wait_io_event_common(cpu);
560
+ }
561
+}
562
+
563
+/*
564
+ * Destroy any remaining vCPUs which have been unplugged and have
565
+ * finished running
566
+ */
567
+static void deal_with_unplugged_cpus(void)
568
+{
569
+ CPUState *cpu;
570
+
571
+ CPU_FOREACH(cpu) {
572
+ if (cpu->unplug && !cpu_can_run(cpu)) {
573
+ qemu_tcg_destroy_vcpu(cpu);
574
+ break;
575
+ }
576
+ }
577
+}
578
+
579
+/*
580
+ * In the single-threaded case each vCPU is simulated in turn. If
581
+ * there is more than a single vCPU we create a simple timer to kick
582
+ * the vCPU and ensure we don't get stuck in a tight loop in one vCPU.
583
+ * This is done explicitly rather than relying on side-effects
584
+ * elsewhere.
585
+ */
586
+
587
+void *tcg_rr_cpu_thread_fn(void *arg)
588
+{
589
+ CPUState *cpu = arg;
590
+
591
+ assert(tcg_enabled());
592
+ rcu_register_thread();
593
+ tcg_register_thread();
594
+
595
+ qemu_mutex_lock_iothread();
596
+ qemu_thread_get_self(cpu->thread);
597
+
598
+ cpu->thread_id = qemu_get_thread_id();
599
+ cpu->can_do_io = 1;
600
+ cpu_thread_signal_created(cpu);
601
+ qemu_guest_random_seed_thread_part2(cpu->random_seed);
602
+
603
+ /* wait for initial kick-off after machine start */
604
+ while (first_cpu->stopped) {
605
+ qemu_cond_wait_iothread(first_cpu->halt_cond);
606
+
607
+ /* process any pending work */
608
+ CPU_FOREACH(cpu) {
609
+ current_cpu = cpu;
610
+ qemu_wait_io_event_common(cpu);
611
+ }
612
+ }
613
+
614
+ start_tcg_kick_timer();
615
+
616
+ cpu = first_cpu;
617
+
618
+ /* process any pending work */
619
+ cpu->exit_request = 1;
620
+
621
+ while (1) {
622
+ qemu_mutex_unlock_iothread();
623
+ replay_mutex_lock();
624
+ qemu_mutex_lock_iothread();
625
+
626
+ if (icount_enabled()) {
627
+ /* Account partial waits to QEMU_CLOCK_VIRTUAL. */
628
+ icount_account_warp_timer();
629
+ /*
630
+ * Run the timers here. This is much more efficient than
631
+ * waking up the I/O thread and waiting for completion.
632
+ */
633
+ handle_icount_deadline();
634
+ }
635
+
636
+ replay_mutex_unlock();
637
+
638
+ if (!cpu) {
639
+ cpu = first_cpu;
640
+ }
641
+
642
+ while (cpu && cpu_work_list_empty(cpu) && !cpu->exit_request) {
643
+
644
+ qatomic_mb_set(&tcg_current_rr_cpu, cpu);
645
+ current_cpu = cpu;
646
+
647
+ qemu_clock_enable(QEMU_CLOCK_VIRTUAL,
648
+ (cpu->singlestep_enabled & SSTEP_NOTIMER) == 0);
649
+
650
+ if (cpu_can_run(cpu)) {
651
+ int r;
652
+
653
+ qemu_mutex_unlock_iothread();
654
+ if (icount_enabled()) {
655
+ prepare_icount_for_run(cpu);
656
+ }
657
+ r = tcg_cpu_exec(cpu);
658
+ if (icount_enabled()) {
659
+ process_icount_data(cpu);
660
+ }
661
+ qemu_mutex_lock_iothread();
662
+
663
+ if (r == EXCP_DEBUG) {
664
+ cpu_handle_guest_debug(cpu);
665
+ break;
666
+ } else if (r == EXCP_ATOMIC) {
667
+ qemu_mutex_unlock_iothread();
668
+ cpu_exec_step_atomic(cpu);
669
+ qemu_mutex_lock_iothread();
670
+ break;
671
+ }
672
+ } else if (cpu->stop) {
673
+ if (cpu->unplug) {
674
+ cpu = CPU_NEXT(cpu);
675
+ }
676
+ break;
677
+ }
678
+
679
+ cpu = CPU_NEXT(cpu);
680
+ } /* while (cpu && !cpu->exit_request).. */
681
+
682
+ /* Does not need qatomic_mb_set because a spurious wakeup is okay. */
683
+ qatomic_set(&tcg_current_rr_cpu, NULL);
684
+
685
+ if (cpu && cpu->exit_request) {
686
+ qatomic_mb_set(&cpu->exit_request, 0);
687
+ }
688
+
689
+ if (icount_enabled() && all_cpu_threads_idle()) {
690
+ /*
691
+ * When all cpus are sleeping (e.g in WFI), to avoid a deadlock
692
+ * in the main_loop, wake it up in order to start the warp timer.
693
+ */
694
+ qemu_notify_event();
695
+ }
696
+
697
+ qemu_tcg_rr_wait_io_event();
698
+ deal_with_unplugged_cpus();
699
+ }
700
+
701
+ rcu_unregister_thread();
702
+ return NULL;
703
+}
704
+
705
+const CpusAccel tcg_cpus_rr = {
706
+ .create_vcpu_thread = tcg_start_vcpu_thread,
707
+ .kick_vcpu_thread = qemu_cpu_kick_rr_cpus,
708
+
709
+ .handle_interrupt = tcg_handle_interrupt,
710
+};
711
diff --git a/accel/tcg/tcg-cpus.c b/accel/tcg/tcg-cpus.c
712
index XXXXXXX..XXXXXXX 100644
713
--- a/accel/tcg/tcg-cpus.c
714
+++ b/accel/tcg/tcg-cpus.c
715
@@ -XXX,XX +XXX,XX @@
716
/*
717
- * QEMU System Emulator
718
+ * QEMU TCG vCPU common functionality
719
+ *
720
+ * Functionality common to all TCG vCPU variants: mttcg, rr and icount.
721
*
722
* Copyright (c) 2003-2008 Fabrice Bellard
723
* Copyright (c) 2014 Red Hat Inc.
724
@@ -XXX,XX +XXX,XX @@
725
#include "hw/boards.h"
726
727
#include "tcg-cpus.h"
728
+#include "tcg-cpus-mttcg.h"
729
+#include "tcg-cpus-rr.h"
730
731
-/* Kick all RR vCPUs */
732
-static void qemu_cpu_kick_rr_cpus(void)
733
-{
19
-{
734
- CPUState *cpu;
20
- tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_UB);
735
+/* common functionality among all TCG variants */
736
737
- CPU_FOREACH(cpu) {
738
- cpu_exit(cpu);
739
- };
740
-}
21
-}
741
-
22
-
742
-static void tcg_kick_vcpu_thread(CPUState *cpu)
23
-static inline void tcg_gen_qemu_ld8s(TCGv ret, TCGv addr, int mem_index)
743
-{
24
-{
744
- if (qemu_tcg_mttcg_enabled()) {
25
- tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_SB);
745
- cpu_exit(cpu);
746
- } else {
747
- qemu_cpu_kick_rr_cpus();
748
- }
749
-}
26
-}
750
-
27
-
751
-/*
28
-static inline void tcg_gen_qemu_ld16u(TCGv ret, TCGv addr, int mem_index)
752
- * TCG vCPU kick timer
753
- *
754
- * The kick timer is responsible for moving single threaded vCPU
755
- * emulation on to the next vCPU. If more than one vCPU is running a
756
- * timer event with force a cpu->exit so the next vCPU can get
757
- * scheduled.
758
- *
759
- * The timer is removed if all vCPUs are idle and restarted again once
760
- * idleness is complete.
761
- */
762
-
763
-static QEMUTimer *tcg_kick_vcpu_timer;
764
-static CPUState *tcg_current_rr_cpu;
765
-
766
-#define TCG_KICK_PERIOD (NANOSECONDS_PER_SECOND / 10)
767
-
768
-static inline int64_t qemu_tcg_next_kick(void)
769
-{
29
-{
770
- return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + TCG_KICK_PERIOD;
30
- tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_TEUW);
771
-}
31
-}
772
-
32
-
773
-/* Kick the currently round-robin scheduled vCPU to next */
33
-static inline void tcg_gen_qemu_ld16s(TCGv ret, TCGv addr, int mem_index)
774
-static void qemu_cpu_kick_rr_next_cpu(void)
775
-{
34
-{
776
- CPUState *cpu;
35
- tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_TESW);
777
- do {
778
- cpu = qatomic_mb_read(&tcg_current_rr_cpu);
779
- if (cpu) {
780
- cpu_exit(cpu);
781
- }
782
- } while (cpu != qatomic_mb_read(&tcg_current_rr_cpu));
783
-}
36
-}
784
-
37
-
785
-static void kick_tcg_thread(void *opaque)
38
-static inline void tcg_gen_qemu_ld32u(TCGv ret, TCGv addr, int mem_index)
786
-{
39
-{
787
- timer_mod(tcg_kick_vcpu_timer, qemu_tcg_next_kick());
40
- tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_TEUL);
788
- qemu_cpu_kick_rr_next_cpu();
789
-}
41
-}
790
-
42
-
791
-static void start_tcg_kick_timer(void)
43
-static inline void tcg_gen_qemu_ld32s(TCGv ret, TCGv addr, int mem_index)
792
-{
44
-{
793
- assert(!mttcg_enabled);
45
- tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_TESL);
794
- if (!tcg_kick_vcpu_timer && CPU_NEXT(first_cpu)) {
795
- tcg_kick_vcpu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
796
- kick_tcg_thread, NULL);
797
- }
798
- if (tcg_kick_vcpu_timer && !timer_pending(tcg_kick_vcpu_timer)) {
799
- timer_mod(tcg_kick_vcpu_timer, qemu_tcg_next_kick());
800
- }
801
-}
46
-}
802
-
47
-
803
-static void stop_tcg_kick_timer(void)
48
-static inline void tcg_gen_qemu_ld64(TCGv_i64 ret, TCGv addr, int mem_index)
804
-{
49
-{
805
- assert(!mttcg_enabled);
50
- tcg_gen_qemu_ld_i64(ret, addr, mem_index, MO_TEUQ);
806
- if (tcg_kick_vcpu_timer && timer_pending(tcg_kick_vcpu_timer)) {
807
- timer_del(tcg_kick_vcpu_timer);
808
- }
809
-}
51
-}
810
-
52
-
811
-static void qemu_tcg_destroy_vcpu(CPUState *cpu)
53
-static inline void tcg_gen_qemu_st8(TCGv arg, TCGv addr, int mem_index)
812
-{
54
-{
55
- tcg_gen_qemu_st_tl(arg, addr, mem_index, MO_UB);
813
-}
56
-}
814
-
57
-
815
-static void qemu_tcg_rr_wait_io_event(void)
58
-static inline void tcg_gen_qemu_st16(TCGv arg, TCGv addr, int mem_index)
816
-{
59
-{
817
- CPUState *cpu;
60
- tcg_gen_qemu_st_tl(arg, addr, mem_index, MO_TEUW);
818
-
819
- while (all_cpu_threads_idle()) {
820
- stop_tcg_kick_timer();
821
- qemu_cond_wait_iothread(first_cpu->halt_cond);
822
- }
823
-
824
- start_tcg_kick_timer();
825
-
826
- CPU_FOREACH(cpu) {
827
- qemu_wait_io_event_common(cpu);
828
- }
829
-}
61
-}
830
-
62
-
831
-static int64_t tcg_get_icount_limit(void)
63
-static inline void tcg_gen_qemu_st32(TCGv arg, TCGv addr, int mem_index)
832
-{
64
-{
833
- int64_t deadline;
65
- tcg_gen_qemu_st_tl(arg, addr, mem_index, MO_TEUL);
834
-
835
- if (replay_mode != REPLAY_MODE_PLAY) {
836
- /*
837
- * Include all the timers, because they may need an attention.
838
- * Too long CPU execution may create unnecessary delay in UI.
839
- */
840
- deadline = qemu_clock_deadline_ns_all(QEMU_CLOCK_VIRTUAL,
841
- QEMU_TIMER_ATTR_ALL);
842
- /* Check realtime timers, because they help with input processing */
843
- deadline = qemu_soonest_timeout(deadline,
844
- qemu_clock_deadline_ns_all(QEMU_CLOCK_REALTIME,
845
- QEMU_TIMER_ATTR_ALL));
846
-
847
- /*
848
- * Maintain prior (possibly buggy) behaviour where if no deadline
849
- * was set (as there is no QEMU_CLOCK_VIRTUAL timer) or it is more than
850
- * INT32_MAX nanoseconds ahead, we still use INT32_MAX
851
- * nanoseconds.
852
- */
853
- if ((deadline < 0) || (deadline > INT32_MAX)) {
854
- deadline = INT32_MAX;
855
- }
856
-
857
- return icount_round(deadline);
858
- } else {
859
- return replay_get_instructions();
860
- }
861
-}
66
-}
862
-
67
-
863
-static void notify_aio_contexts(void)
68
-static inline void tcg_gen_qemu_st64(TCGv_i64 arg, TCGv addr, int mem_index)
864
-{
69
-{
865
- /* Wake up other AioContexts. */
70
- tcg_gen_qemu_st_i64(arg, addr, mem_index, MO_TEUQ);
866
- qemu_clock_notify(QEMU_CLOCK_VIRTUAL);
867
- qemu_clock_run_timers(QEMU_CLOCK_VIRTUAL);
868
-}
71
-}
869
-
72
-
870
-static void handle_icount_deadline(void)
73
void tcg_gen_atomic_cmpxchg_i32(TCGv_i32, TCGv, TCGv_i32, TCGv_i32,
871
-{
74
TCGArg, MemOp);
872
- assert(qemu_in_vcpu_thread());
75
void tcg_gen_atomic_cmpxchg_i64(TCGv_i64, TCGv, TCGv_i64, TCGv_i64,
873
- if (icount_enabled()) {
874
- int64_t deadline = qemu_clock_deadline_ns_all(QEMU_CLOCK_VIRTUAL,
875
- QEMU_TIMER_ATTR_ALL);
876
-
877
- if (deadline == 0) {
878
- notify_aio_contexts();
879
- }
880
- }
881
-}
882
-
883
-static void prepare_icount_for_run(CPUState *cpu)
884
-{
885
- if (icount_enabled()) {
886
- int insns_left;
887
-
888
- /*
889
- * These should always be cleared by process_icount_data after
890
- * each vCPU execution. However u16.high can be raised
891
- * asynchronously by cpu_exit/cpu_interrupt/tcg_handle_interrupt
892
- */
893
- g_assert(cpu_neg(cpu)->icount_decr.u16.low == 0);
894
- g_assert(cpu->icount_extra == 0);
895
-
896
- cpu->icount_budget = tcg_get_icount_limit();
897
- insns_left = MIN(0xffff, cpu->icount_budget);
898
- cpu_neg(cpu)->icount_decr.u16.low = insns_left;
899
- cpu->icount_extra = cpu->icount_budget - insns_left;
900
-
901
- replay_mutex_lock();
902
-
903
- if (cpu->icount_budget == 0 && replay_has_checkpoint()) {
904
- notify_aio_contexts();
905
- }
906
- }
907
-}
908
-
909
-static void process_icount_data(CPUState *cpu)
910
-{
911
- if (icount_enabled()) {
912
- /* Account for executed instructions */
913
- icount_update(cpu);
914
-
915
- /* Reset the counters */
916
- cpu_neg(cpu)->icount_decr.u16.low = 0;
917
- cpu->icount_extra = 0;
918
- cpu->icount_budget = 0;
919
-
920
- replay_account_executed_instructions();
921
-
922
- replay_mutex_unlock();
923
- }
924
-}
925
-
926
-static int tcg_cpu_exec(CPUState *cpu)
927
-{
928
- int ret;
929
-#ifdef CONFIG_PROFILER
930
- int64_t ti;
931
-#endif
932
-
933
- assert(tcg_enabled());
934
-#ifdef CONFIG_PROFILER
935
- ti = profile_getclock();
936
-#endif
937
- cpu_exec_start(cpu);
938
- ret = cpu_exec(cpu);
939
- cpu_exec_end(cpu);
940
-#ifdef CONFIG_PROFILER
941
- qatomic_set(&tcg_ctx->prof.cpu_exec_time,
942
- tcg_ctx->prof.cpu_exec_time + profile_getclock() - ti);
943
-#endif
944
- return ret;
945
-}
946
-
947
-/*
948
- * Destroy any remaining vCPUs which have been unplugged and have
949
- * finished running
950
- */
951
-static void deal_with_unplugged_cpus(void)
952
-{
953
- CPUState *cpu;
954
-
955
- CPU_FOREACH(cpu) {
956
- if (cpu->unplug && !cpu_can_run(cpu)) {
957
- qemu_tcg_destroy_vcpu(cpu);
958
- cpu_thread_signal_destroyed(cpu);
959
- break;
960
- }
961
- }
962
-}
963
-
964
-/*
965
- * Single-threaded TCG
966
- *
967
- * In the single-threaded case each vCPU is simulated in turn. If
968
- * there is more than a single vCPU we create a simple timer to kick
969
- * the vCPU and ensure we don't get stuck in a tight loop in one vCPU.
970
- * This is done explicitly rather than relying on side-effects
971
- * elsewhere.
972
- */
973
-
974
-static void *tcg_rr_cpu_thread_fn(void *arg)
975
-{
976
- CPUState *cpu = arg;
977
-
978
- assert(tcg_enabled());
979
- rcu_register_thread();
980
- tcg_register_thread();
981
-
982
- qemu_mutex_lock_iothread();
983
- qemu_thread_get_self(cpu->thread);
984
-
985
- cpu->thread_id = qemu_get_thread_id();
986
- cpu->can_do_io = 1;
987
- cpu_thread_signal_created(cpu);
988
- qemu_guest_random_seed_thread_part2(cpu->random_seed);
989
-
990
- /* wait for initial kick-off after machine start */
991
- while (first_cpu->stopped) {
992
- qemu_cond_wait_iothread(first_cpu->halt_cond);
993
-
994
- /* process any pending work */
995
- CPU_FOREACH(cpu) {
996
- current_cpu = cpu;
997
- qemu_wait_io_event_common(cpu);
998
- }
999
- }
1000
-
1001
- start_tcg_kick_timer();
1002
-
1003
- cpu = first_cpu;
1004
-
1005
- /* process any pending work */
1006
- cpu->exit_request = 1;
1007
-
1008
- while (1) {
1009
- qemu_mutex_unlock_iothread();
1010
- replay_mutex_lock();
1011
- qemu_mutex_lock_iothread();
1012
- /* Account partial waits to QEMU_CLOCK_VIRTUAL. */
1013
- icount_account_warp_timer();
1014
-
1015
- /*
1016
- * Run the timers here. This is much more efficient than
1017
- * waking up the I/O thread and waiting for completion.
1018
- */
1019
- handle_icount_deadline();
1020
-
1021
- replay_mutex_unlock();
1022
-
1023
- if (!cpu) {
1024
- cpu = first_cpu;
1025
- }
1026
-
1027
- while (cpu && cpu_work_list_empty(cpu) && !cpu->exit_request) {
1028
-
1029
- qatomic_mb_set(&tcg_current_rr_cpu, cpu);
1030
- current_cpu = cpu;
1031
-
1032
- qemu_clock_enable(QEMU_CLOCK_VIRTUAL,
1033
- (cpu->singlestep_enabled & SSTEP_NOTIMER) == 0);
1034
-
1035
- if (cpu_can_run(cpu)) {
1036
- int r;
1037
-
1038
- qemu_mutex_unlock_iothread();
1039
- prepare_icount_for_run(cpu);
1040
-
1041
- r = tcg_cpu_exec(cpu);
1042
-
1043
- process_icount_data(cpu);
1044
- qemu_mutex_lock_iothread();
1045
-
1046
- if (r == EXCP_DEBUG) {
1047
- cpu_handle_guest_debug(cpu);
1048
- break;
1049
- } else if (r == EXCP_ATOMIC) {
1050
- qemu_mutex_unlock_iothread();
1051
- cpu_exec_step_atomic(cpu);
1052
- qemu_mutex_lock_iothread();
1053
- break;
1054
- }
1055
- } else if (cpu->stop) {
1056
- if (cpu->unplug) {
1057
- cpu = CPU_NEXT(cpu);
1058
- }
1059
- break;
1060
- }
1061
-
1062
- cpu = CPU_NEXT(cpu);
1063
- } /* while (cpu && !cpu->exit_request).. */
1064
-
1065
- /* Does not need qatomic_mb_set because a spurious wakeup is okay. */
1066
- qatomic_set(&tcg_current_rr_cpu, NULL);
1067
-
1068
- if (cpu && cpu->exit_request) {
1069
- qatomic_mb_set(&cpu->exit_request, 0);
1070
- }
1071
-
1072
- if (icount_enabled() && all_cpu_threads_idle()) {
1073
- /*
1074
- * When all cpus are sleeping (e.g in WFI), to avoid a deadlock
1075
- * in the main_loop, wake it up in order to start the warp timer.
1076
- */
1077
- qemu_notify_event();
1078
- }
1079
-
1080
- qemu_tcg_rr_wait_io_event();
1081
- deal_with_unplugged_cpus();
1082
- }
1083
-
1084
- rcu_unregister_thread();
1085
- return NULL;
1086
-}
1087
-
1088
-/*
1089
- * Multi-threaded TCG
1090
- *
1091
- * In the multi-threaded case each vCPU has its own thread. The TLS
1092
- * variable current_cpu can be used deep in the code to find the
1093
- * current CPUState for a given thread.
1094
- */
1095
-
1096
-static void *tcg_cpu_thread_fn(void *arg)
1097
-{
1098
- CPUState *cpu = arg;
1099
-
1100
- assert(tcg_enabled());
1101
- g_assert(!icount_enabled());
1102
-
1103
- rcu_register_thread();
1104
- tcg_register_thread();
1105
-
1106
- qemu_mutex_lock_iothread();
1107
- qemu_thread_get_self(cpu->thread);
1108
-
1109
- cpu->thread_id = qemu_get_thread_id();
1110
- cpu->can_do_io = 1;
1111
- current_cpu = cpu;
1112
- cpu_thread_signal_created(cpu);
1113
- qemu_guest_random_seed_thread_part2(cpu->random_seed);
1114
-
1115
- /* process any pending work */
1116
- cpu->exit_request = 1;
1117
-
1118
- do {
1119
- if (cpu_can_run(cpu)) {
1120
- int r;
1121
- qemu_mutex_unlock_iothread();
1122
- r = tcg_cpu_exec(cpu);
1123
- qemu_mutex_lock_iothread();
1124
- switch (r) {
1125
- case EXCP_DEBUG:
1126
- cpu_handle_guest_debug(cpu);
1127
- break;
1128
- case EXCP_HALTED:
1129
- /*
1130
- * during start-up the vCPU is reset and the thread is
1131
- * kicked several times. If we don't ensure we go back
1132
- * to sleep in the halted state we won't cleanly
1133
- * start-up when the vCPU is enabled.
1134
- *
1135
- * cpu->halted should ensure we sleep in wait_io_event
1136
- */
1137
- g_assert(cpu->halted);
1138
- break;
1139
- case EXCP_ATOMIC:
1140
- qemu_mutex_unlock_iothread();
1141
- cpu_exec_step_atomic(cpu);
1142
- qemu_mutex_lock_iothread();
1143
- default:
1144
- /* Ignore everything else? */
1145
- break;
1146
- }
1147
- }
1148
-
1149
- qatomic_mb_set(&cpu->exit_request, 0);
1150
- qemu_wait_io_event(cpu);
1151
- } while (!cpu->unplug || cpu_can_run(cpu));
1152
-
1153
- qemu_tcg_destroy_vcpu(cpu);
1154
- cpu_thread_signal_destroyed(cpu);
1155
- qemu_mutex_unlock_iothread();
1156
- rcu_unregister_thread();
1157
- return NULL;
1158
-}
1159
-
1160
-static void tcg_start_vcpu_thread(CPUState *cpu)
1161
+void tcg_start_vcpu_thread(CPUState *cpu)
1162
{
1163
char thread_name[VCPU_THREAD_NAME_SIZE];
1164
static QemuCond *single_tcg_halt_cond;
1165
@@ -XXX,XX +XXX,XX @@ static void tcg_start_vcpu_thread(CPUState *cpu)
1166
}
1167
}
1168
1169
-static int64_t tcg_get_virtual_clock(void)
1170
+void qemu_tcg_destroy_vcpu(CPUState *cpu)
1171
{
1172
- if (icount_enabled()) {
1173
- return icount_get();
1174
- }
1175
- return cpu_get_clock();
1176
+ cpu_thread_signal_destroyed(cpu);
1177
}
1178
1179
-static int64_t tcg_get_elapsed_ticks(void)
1180
+int tcg_cpu_exec(CPUState *cpu)
1181
{
1182
- if (icount_enabled()) {
1183
- return icount_get();
1184
- }
1185
- return cpu_get_ticks();
1186
+ int ret;
1187
+#ifdef CONFIG_PROFILER
1188
+ int64_t ti;
1189
+#endif
1190
+ assert(tcg_enabled());
1191
+#ifdef CONFIG_PROFILER
1192
+ ti = profile_getclock();
1193
+#endif
1194
+ cpu_exec_start(cpu);
1195
+ ret = cpu_exec(cpu);
1196
+ cpu_exec_end(cpu);
1197
+#ifdef CONFIG_PROFILER
1198
+ qatomic_set(&tcg_ctx->prof.cpu_exec_time,
1199
+ tcg_ctx->prof.cpu_exec_time + profile_getclock() - ti);
1200
+#endif
1201
+ return ret;
1202
}
1203
1204
/* mask must never be zero, except for A20 change call */
1205
-static void tcg_handle_interrupt(CPUState *cpu, int mask)
1206
+void tcg_handle_interrupt(CPUState *cpu, int mask)
1207
{
1208
- int old_mask;
1209
g_assert(qemu_mutex_iothread_locked());
1210
1211
- old_mask = cpu->interrupt_request;
1212
cpu->interrupt_request |= mask;
1213
1214
/*
1215
@@ -XXX,XX +XXX,XX @@ static void tcg_handle_interrupt(CPUState *cpu, int mask)
1216
qemu_cpu_kick(cpu);
1217
} else {
1218
qatomic_set(&cpu_neg(cpu)->icount_decr.u16.high, -1);
1219
- if (icount_enabled() &&
1220
- !cpu->can_do_io
1221
- && (mask & ~old_mask) != 0) {
1222
- cpu_abort(cpu, "Raised interrupt while not in I/O function");
1223
- }
1224
}
1225
}
1226
-
1227
-const CpusAccel tcg_cpus = {
1228
- .create_vcpu_thread = tcg_start_vcpu_thread,
1229
- .kick_vcpu_thread = tcg_kick_vcpu_thread,
1230
-
1231
- .handle_interrupt = tcg_handle_interrupt,
1232
-
1233
- .get_virtual_clock = tcg_get_virtual_clock,
1234
- .get_elapsed_ticks = tcg_get_elapsed_ticks,
1235
-};
1236
diff --git a/softmmu/icount.c b/softmmu/icount.c
1237
index XXXXXXX..XXXXXXX 100644
1238
--- a/softmmu/icount.c
1239
+++ b/softmmu/icount.c
1240
@@ -XXX,XX +XXX,XX @@ void icount_start_warp_timer(void)
1241
1242
void icount_account_warp_timer(void)
1243
{
1244
- if (!icount_enabled() || !icount_sleep) {
1245
+ if (!icount_sleep) {
1246
return;
1247
}
1248
1249
diff --git a/accel/tcg/meson.build b/accel/tcg/meson.build
1250
index XXXXXXX..XXXXXXX 100644
1251
--- a/accel/tcg/meson.build
1252
+++ b/accel/tcg/meson.build
1253
@@ -XXX,XX +XXX,XX @@ tcg_ss.add(when: 'CONFIG_SOFTMMU', if_false: files('user-exec-stub.c'))
1254
tcg_ss.add(when: 'CONFIG_PLUGIN', if_true: [files('plugin-gen.c'), libdl])
1255
specific_ss.add_all(when: 'CONFIG_TCG', if_true: tcg_ss)
1256
1257
-specific_ss.add(when: ['CONFIG_SOFTMMU', 'CONFIG_TCG'], if_true: files('tcg-all.c', 'cputlb.c', 'tcg-cpus.c'))
1258
+specific_ss.add(when: ['CONFIG_SOFTMMU', 'CONFIG_TCG'], if_true: files(
1259
+ 'tcg-all.c',
1260
+ 'cputlb.c',
1261
+ 'tcg-cpus.c',
1262
+ 'tcg-cpus-mttcg.c',
1263
+ 'tcg-cpus-icount.c',
1264
+ 'tcg-cpus-rr.c'
1265
+))
1266
--
76
--
1267
2.25.1
77
2.34.1
1268
1269
diff view generated by jsdifflib
New patch
[PULL 11/42] target/alpha: Use MO_ALIGN for system UNALIGN()
1
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2
---
3
target/alpha/translate.c | 2 +-
4
1 file changed, 1 insertion(+), 1 deletion(-)
1
5
6
diff --git a/target/alpha/translate.c b/target/alpha/translate.c
7
index XXXXXXX..XXXXXXX 100644
8
--- a/target/alpha/translate.c
9
+++ b/target/alpha/translate.c
10
@@ -XXX,XX +XXX,XX @@ struct DisasContext {
11
#ifdef CONFIG_USER_ONLY
12
#define UNALIGN(C) (C)->unalign
13
#else
14
-#define UNALIGN(C) 0
15
+#define UNALIGN(C) MO_ALIGN
16
#endif
17
18
/* Target-specific return values from translate_one, indicating the
19
--
20
2.34.1
diff view generated by jsdifflib
New patch
[PULL 12/42] target/alpha: Use MO_ALIGN where required
1
Mark all memory operations that are not already marked with UNALIGN.
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
---
5
target/alpha/translate.c | 36 ++++++++++++++++++++----------------
6
1 file changed, 20 insertions(+), 16 deletions(-)
7
8
diff --git a/target/alpha/translate.c b/target/alpha/translate.c
9
index XXXXXXX..XXXXXXX 100644
10
--- a/target/alpha/translate.c
11
+++ b/target/alpha/translate.c
12
@@ -XXX,XX +XXX,XX @@ static DisasJumpType translate_one(DisasContext *ctx, uint32_t insn)
13
switch ((insn >> 12) & 0xF) {
14
case 0x0:
15
/* Longword physical access (hw_ldl/p) */
16
- tcg_gen_qemu_ld_i64(va, addr, MMU_PHYS_IDX, MO_LESL);
17
+ tcg_gen_qemu_ld_i64(va, addr, MMU_PHYS_IDX, MO_LESL | MO_ALIGN);
18
break;
19
case 0x1:
20
/* Quadword physical access (hw_ldq/p) */
21
- tcg_gen_qemu_ld_i64(va, addr, MMU_PHYS_IDX, MO_LEUQ);
22
+ tcg_gen_qemu_ld_i64(va, addr, MMU_PHYS_IDX, MO_LEUQ | MO_ALIGN);
23
break;
24
case 0x2:
25
/* Longword physical access with lock (hw_ldl_l/p) */
26
- tcg_gen_qemu_ld_i64(va, addr, MMU_PHYS_IDX, MO_LESL);
27
+ tcg_gen_qemu_ld_i64(va, addr, MMU_PHYS_IDX, MO_LESL | MO_ALIGN);
28
tcg_gen_mov_i64(cpu_lock_addr, addr);
29
tcg_gen_mov_i64(cpu_lock_value, va);
30
break;
31
case 0x3:
32
/* Quadword physical access with lock (hw_ldq_l/p) */
33
- tcg_gen_qemu_ld_i64(va, addr, MMU_PHYS_IDX, MO_LEUQ);
34
+ tcg_gen_qemu_ld_i64(va, addr, MMU_PHYS_IDX, MO_LEUQ | MO_ALIGN);
35
tcg_gen_mov_i64(cpu_lock_addr, addr);
36
tcg_gen_mov_i64(cpu_lock_value, va);
37
break;
38
@@ -XXX,XX +XXX,XX @@ static DisasJumpType translate_one(DisasContext *ctx, uint32_t insn)
39
goto invalid_opc;
40
case 0xA:
41
/* Longword virtual access with protection check (hw_ldl/w) */
42
- tcg_gen_qemu_ld_i64(va, addr, MMU_KERNEL_IDX, MO_LESL);
43
+ tcg_gen_qemu_ld_i64(va, addr, MMU_KERNEL_IDX,
44
+ MO_LESL | MO_ALIGN);
45
break;
46
case 0xB:
47
/* Quadword virtual access with protection check (hw_ldq/w) */
48
- tcg_gen_qemu_ld_i64(va, addr, MMU_KERNEL_IDX, MO_LEUQ);
49
+ tcg_gen_qemu_ld_i64(va, addr, MMU_KERNEL_IDX,
50
+ MO_LEUQ | MO_ALIGN);
51
break;
52
case 0xC:
53
/* Longword virtual access with alt access mode (hw_ldl/a)*/
54
@@ -XXX,XX +XXX,XX @@ static DisasJumpType translate_one(DisasContext *ctx, uint32_t insn)
55
case 0xE:
56
/* Longword virtual access with alternate access mode and
57
protection checks (hw_ldl/wa) */
58
- tcg_gen_qemu_ld_i64(va, addr, MMU_USER_IDX, MO_LESL);
59
+ tcg_gen_qemu_ld_i64(va, addr, MMU_USER_IDX,
60
+ MO_LESL | MO_ALIGN);
61
break;
62
case 0xF:
63
/* Quadword virtual access with alternate access mode and
64
protection checks (hw_ldq/wa) */
65
- tcg_gen_qemu_ld_i64(va, addr, MMU_USER_IDX, MO_LEUQ);
66
+ tcg_gen_qemu_ld_i64(va, addr, MMU_USER_IDX,
67
+ MO_LEUQ | MO_ALIGN);
68
break;
69
}
70
break;
71
@@ -XXX,XX +XXX,XX @@ static DisasJumpType translate_one(DisasContext *ctx, uint32_t insn)
72
vb = load_gpr(ctx, rb);
73
tmp = tcg_temp_new();
74
tcg_gen_addi_i64(tmp, vb, disp12);
75
- tcg_gen_qemu_st_i64(va, tmp, MMU_PHYS_IDX, MO_LESL);
76
+ tcg_gen_qemu_st_i64(va, tmp, MMU_PHYS_IDX, MO_LESL | MO_ALIGN);
77
break;
78
case 0x1:
79
/* Quadword physical access */
80
@@ -XXX,XX +XXX,XX @@ static DisasJumpType translate_one(DisasContext *ctx, uint32_t insn)
81
vb = load_gpr(ctx, rb);
82
tmp = tcg_temp_new();
83
tcg_gen_addi_i64(tmp, vb, disp12);
84
- tcg_gen_qemu_st_i64(va, tmp, MMU_PHYS_IDX, MO_LEUQ);
85
+ tcg_gen_qemu_st_i64(va, tmp, MMU_PHYS_IDX, MO_LEUQ | MO_ALIGN);
86
break;
87
case 0x2:
88
/* Longword physical access with lock */
89
ret = gen_store_conditional(ctx, ra, rb, disp12,
90
- MMU_PHYS_IDX, MO_LESL);
91
+ MMU_PHYS_IDX, MO_LESL | MO_ALIGN);
92
break;
93
case 0x3:
94
/* Quadword physical access with lock */
95
ret = gen_store_conditional(ctx, ra, rb, disp12,
96
- MMU_PHYS_IDX, MO_LEUQ);
97
+ MMU_PHYS_IDX, MO_LEUQ | MO_ALIGN);
98
break;
99
case 0x4:
100
/* Longword virtual access */
101
@@ -XXX,XX +XXX,XX @@ static DisasJumpType translate_one(DisasContext *ctx, uint32_t insn)
102
break;
103
case 0x2A:
104
/* LDL_L */
105
- gen_load_int(ctx, ra, rb, disp16, MO_LESL, 0, 1);
106
+ gen_load_int(ctx, ra, rb, disp16, MO_LESL | MO_ALIGN, 0, 1);
107
break;
108
case 0x2B:
109
/* LDQ_L */
110
- gen_load_int(ctx, ra, rb, disp16, MO_LEUQ, 0, 1);
111
+ gen_load_int(ctx, ra, rb, disp16, MO_LEUQ | MO_ALIGN, 0, 1);
112
break;
113
case 0x2C:
114
/* STL */
115
@@ -XXX,XX +XXX,XX @@ static DisasJumpType translate_one(DisasContext *ctx, uint32_t insn)
116
case 0x2E:
117
/* STL_C */
118
ret = gen_store_conditional(ctx, ra, rb, disp16,
119
- ctx->mem_idx, MO_LESL);
120
+ ctx->mem_idx, MO_LESL | MO_ALIGN);
121
break;
122
case 0x2F:
123
/* STQ_C */
124
ret = gen_store_conditional(ctx, ra, rb, disp16,
125
- ctx->mem_idx, MO_LEUQ);
126
+ ctx->mem_idx, MO_LEUQ | MO_ALIGN);
127
break;
128
case 0x30:
129
/* BR */
130
--
131
2.34.1
diff view generated by jsdifflib
New patch
[PULL 13/42] target/alpha: Remove TARGET_ALIGNED_ONLY
1
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2
---
3
configs/targets/alpha-linux-user.mak | 1 -
4
configs/targets/alpha-softmmu.mak | 1 -
5
2 files changed, 2 deletions(-)
1
6
7
diff --git a/configs/targets/alpha-linux-user.mak b/configs/targets/alpha-linux-user.mak
8
index XXXXXXX..XXXXXXX 100644
9
--- a/configs/targets/alpha-linux-user.mak
10
+++ b/configs/targets/alpha-linux-user.mak
11
@@ -XXX,XX +XXX,XX @@
12
TARGET_ARCH=alpha
13
TARGET_SYSTBL_ABI=common
14
TARGET_SYSTBL=syscall.tbl
15
-TARGET_ALIGNED_ONLY=y
16
diff --git a/configs/targets/alpha-softmmu.mak b/configs/targets/alpha-softmmu.mak
17
index XXXXXXX..XXXXXXX 100644
18
--- a/configs/targets/alpha-softmmu.mak
19
+++ b/configs/targets/alpha-softmmu.mak
20
@@ -XXX,XX +XXX,XX @@
21
TARGET_ARCH=alpha
22
-TARGET_ALIGNED_ONLY=y
23
TARGET_SUPPORTS_MTTCG=y
24
--
25
2.34.1
diff view generated by jsdifflib
New patch
[PULL 14/42] target/hppa: Use MO_ALIGN for system UNALIGN()
1
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2
---
3
target/hppa/translate.c | 2 +-
4
1 file changed, 1 insertion(+), 1 deletion(-)
1
5
6
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
7
index XXXXXXX..XXXXXXX 100644
8
--- a/target/hppa/translate.c
9
+++ b/target/hppa/translate.c
10
@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
11
#ifdef CONFIG_USER_ONLY
12
#define UNALIGN(C) (C)->unalign
13
#else
14
-#define UNALIGN(C) 0
15
+#define UNALIGN(C) MO_ALIGN
16
#endif
17
18
/* Note that ssm/rsm instructions number PSW_W and PSW_E differently. */
19
--
20
2.34.1
diff view generated by jsdifflib
New patch
[PULL 15/42] target/hppa: Remove TARGET_ALIGNED_ONLY
1
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2
---
3
configs/targets/hppa-linux-user.mak | 1 -
4
configs/targets/hppa-softmmu.mak | 1 -
5
2 files changed, 2 deletions(-)
1
6
7
diff --git a/configs/targets/hppa-linux-user.mak b/configs/targets/hppa-linux-user.mak
8
index XXXXXXX..XXXXXXX 100644
9
--- a/configs/targets/hppa-linux-user.mak
10
+++ b/configs/targets/hppa-linux-user.mak
11
@@ -XXX,XX +XXX,XX @@
12
TARGET_ARCH=hppa
13
TARGET_SYSTBL_ABI=common,32
14
TARGET_SYSTBL=syscall.tbl
15
-TARGET_ALIGNED_ONLY=y
16
TARGET_BIG_ENDIAN=y
17
diff --git a/configs/targets/hppa-softmmu.mak b/configs/targets/hppa-softmmu.mak
18
index XXXXXXX..XXXXXXX 100644
19
--- a/configs/targets/hppa-softmmu.mak
20
+++ b/configs/targets/hppa-softmmu.mak
21
@@ -XXX,XX +XXX,XX @@
22
TARGET_ARCH=hppa
23
-TARGET_ALIGNED_ONLY=y
24
TARGET_BIG_ENDIAN=y
25
TARGET_SUPPORTS_MTTCG=y
26
--
27
2.34.1
diff view generated by jsdifflib
New patch
[PULL 16/42] target/sparc: Use MO_ALIGN where required
1
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
2
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
3
---
4
target/sparc/translate.c | 66 +++++++++++++++++++++-------------------
5
1 file changed, 34 insertions(+), 32 deletions(-)
1
6
7
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
8
index XXXXXXX..XXXXXXX 100644
9
--- a/target/sparc/translate.c
10
+++ b/target/sparc/translate.c
11
@@ -XXX,XX +XXX,XX @@ static void gen_swap(DisasContext *dc, TCGv dst, TCGv src,
12
TCGv addr, int mmu_idx, MemOp memop)
13
{
14
gen_address_mask(dc, addr);
15
- tcg_gen_atomic_xchg_tl(dst, addr, src, mmu_idx, memop);
16
+ tcg_gen_atomic_xchg_tl(dst, addr, src, mmu_idx, memop | MO_ALIGN);
17
}
18
19
static void gen_ldstub(DisasContext *dc, TCGv dst, TCGv addr, int mmu_idx)
20
@@ -XXX,XX +XXX,XX @@ static void gen_ld_asi(DisasContext *dc, TCGv dst, TCGv addr,
21
break;
22
case GET_ASI_DIRECT:
23
gen_address_mask(dc, addr);
24
- tcg_gen_qemu_ld_tl(dst, addr, da.mem_idx, da.memop);
25
+ tcg_gen_qemu_ld_tl(dst, addr, da.mem_idx, da.memop | MO_ALIGN);
26
break;
27
default:
28
{
29
TCGv_i32 r_asi = tcg_constant_i32(da.asi);
30
- TCGv_i32 r_mop = tcg_constant_i32(memop);
31
+ TCGv_i32 r_mop = tcg_constant_i32(memop | MO_ALIGN);
32
33
save_state(dc);
34
#ifdef TARGET_SPARC64
35
@@ -XXX,XX +XXX,XX @@ static void gen_st_asi(DisasContext *dc, TCGv src, TCGv addr,
36
/* fall through */
37
case GET_ASI_DIRECT:
38
gen_address_mask(dc, addr);
39
- tcg_gen_qemu_st_tl(src, addr, da.mem_idx, da.memop);
40
+ tcg_gen_qemu_st_tl(src, addr, da.mem_idx, da.memop | MO_ALIGN);
41
break;
42
#if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY)
43
case GET_ASI_BCOPY:
44
@@ -XXX,XX +XXX,XX @@ static void gen_st_asi(DisasContext *dc, TCGv src, TCGv addr,
45
default:
46
{
47
TCGv_i32 r_asi = tcg_constant_i32(da.asi);
48
- TCGv_i32 r_mop = tcg_constant_i32(memop & MO_SIZE);
49
+ TCGv_i32 r_mop = tcg_constant_i32(memop | MO_ALIGN);
50
51
save_state(dc);
52
#ifdef TARGET_SPARC64
53
@@ -XXX,XX +XXX,XX @@ static void gen_cas_asi(DisasContext *dc, TCGv addr, TCGv cmpv,
54
case GET_ASI_DIRECT:
55
oldv = tcg_temp_new();
56
tcg_gen_atomic_cmpxchg_tl(oldv, addr, cmpv, gen_load_gpr(dc, rd),
57
- da.mem_idx, da.memop);
58
+ da.mem_idx, da.memop | MO_ALIGN);
59
gen_store_gpr(dc, rd, oldv);
60
break;
61
default:
62
@@ -XXX,XX +XXX,XX @@ static void gen_ldf_asi(DisasContext *dc, TCGv addr,
63
switch (size) {
64
case 4:
65
d32 = gen_dest_fpr_F(dc);
66
- tcg_gen_qemu_ld_i32(d32, addr, da.mem_idx, da.memop);
67
+ tcg_gen_qemu_ld_i32(d32, addr, da.mem_idx, da.memop | MO_ALIGN);
68
gen_store_fpr_F(dc, rd, d32);
69
break;
70
case 8:
71
@@ -XXX,XX +XXX,XX @@ static void gen_ldf_asi(DisasContext *dc, TCGv addr,
72
/* Valid for lddfa only. */
73
if (size == 8) {
74
gen_address_mask(dc, addr);
75
- tcg_gen_qemu_ld_i64(cpu_fpr[rd / 2], addr, da.mem_idx, da.memop);
76
+ tcg_gen_qemu_ld_i64(cpu_fpr[rd / 2], addr, da.mem_idx,
77
+ da.memop | MO_ALIGN);
78
} else {
79
gen_exception(dc, TT_ILL_INSN);
80
}
81
@@ -XXX,XX +XXX,XX @@ static void gen_ldf_asi(DisasContext *dc, TCGv addr,
82
default:
83
{
84
TCGv_i32 r_asi = tcg_constant_i32(da.asi);
85
- TCGv_i32 r_mop = tcg_constant_i32(da.memop);
86
+ TCGv_i32 r_mop = tcg_constant_i32(da.memop | MO_ALIGN);
87
88
save_state(dc);
89
/* According to the table in the UA2011 manual, the only
90
@@ -XXX,XX +XXX,XX @@ static void gen_stf_asi(DisasContext *dc, TCGv addr,
91
switch (size) {
92
case 4:
93
d32 = gen_load_fpr_F(dc, rd);
94
- tcg_gen_qemu_st_i32(d32, addr, da.mem_idx, da.memop);
95
+ tcg_gen_qemu_st_i32(d32, addr, da.mem_idx, da.memop | MO_ALIGN);
96
break;
97
case 8:
98
tcg_gen_qemu_st_i64(cpu_fpr[rd / 2], addr, da.mem_idx,
99
@@ -XXX,XX +XXX,XX @@ static void gen_stf_asi(DisasContext *dc, TCGv addr,
100
/* Valid for stdfa only. */
101
if (size == 8) {
102
gen_address_mask(dc, addr);
103
- tcg_gen_qemu_st_i64(cpu_fpr[rd / 2], addr, da.mem_idx, da.memop);
104
+ tcg_gen_qemu_st_i64(cpu_fpr[rd / 2], addr, da.mem_idx,
105
+ da.memop | MO_ALIGN);
106
} else {
107
gen_exception(dc, TT_ILL_INSN);
108
}
109
@@ -XXX,XX +XXX,XX @@ static void gen_ldda_asi(DisasContext *dc, TCGv addr, int insn, int rd)
110
TCGv_i64 tmp = tcg_temp_new_i64();
111
112
gen_address_mask(dc, addr);
113
- tcg_gen_qemu_ld_i64(tmp, addr, da.mem_idx, da.memop);
114
+ tcg_gen_qemu_ld_i64(tmp, addr, da.mem_idx, da.memop | MO_ALIGN);
115
116
/* Note that LE ldda acts as if each 32-bit register
117
result is byte swapped. Having just performed one
118
@@ -XXX,XX +XXX,XX @@ static void gen_stda_asi(DisasContext *dc, TCGv hi, TCGv addr,
119
tcg_gen_concat32_i64(t64, hi, lo);
120
}
121
gen_address_mask(dc, addr);
122
- tcg_gen_qemu_st_i64(t64, addr, da.mem_idx, da.memop);
123
+ tcg_gen_qemu_st_i64(t64, addr, da.mem_idx, da.memop | MO_ALIGN);
124
}
125
break;
126
127
@@ -XXX,XX +XXX,XX @@ static void gen_casx_asi(DisasContext *dc, TCGv addr, TCGv cmpv,
128
case GET_ASI_DIRECT:
129
oldv = tcg_temp_new();
130
tcg_gen_atomic_cmpxchg_tl(oldv, addr, cmpv, gen_load_gpr(dc, rd),
131
- da.mem_idx, da.memop);
132
+ da.mem_idx, da.memop | MO_ALIGN);
133
gen_store_gpr(dc, rd, oldv);
134
break;
135
default:
136
@@ -XXX,XX +XXX,XX @@ static void gen_ldda_asi(DisasContext *dc, TCGv addr, int insn, int rd)
137
return;
138
case GET_ASI_DIRECT:
139
gen_address_mask(dc, addr);
140
- tcg_gen_qemu_ld_i64(t64, addr, da.mem_idx, da.memop);
141
+ tcg_gen_qemu_ld_i64(t64, addr, da.mem_idx, da.memop | MO_ALIGN);
142
break;
143
default:
144
{
145
@@ -XXX,XX +XXX,XX @@ static void gen_stda_asi(DisasContext *dc, TCGv hi, TCGv addr,
146
break;
147
case GET_ASI_DIRECT:
148
gen_address_mask(dc, addr);
149
- tcg_gen_qemu_st_i64(t64, addr, da.mem_idx, da.memop);
150
+ tcg_gen_qemu_st_i64(t64, addr, da.mem_idx, da.memop | MO_ALIGN);
151
break;
152
case GET_ASI_BFILL:
153
/* Store 32 bytes of T64 to ADDR. */
154
@@ -XXX,XX +XXX,XX @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
155
case 0x0: /* ld, V9 lduw, load unsigned word */
156
gen_address_mask(dc, cpu_addr);
157
tcg_gen_qemu_ld_tl(cpu_val, cpu_addr,
158
- dc->mem_idx, MO_TEUL);
159
+ dc->mem_idx, MO_TEUL | MO_ALIGN);
160
break;
161
case 0x1: /* ldub, load unsigned byte */
162
gen_address_mask(dc, cpu_addr);
163
@@ -XXX,XX +XXX,XX @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
164
case 0x2: /* lduh, load unsigned halfword */
165
gen_address_mask(dc, cpu_addr);
166
tcg_gen_qemu_ld_tl(cpu_val, cpu_addr,
167
- dc->mem_idx, MO_TEUW);
168
+ dc->mem_idx, MO_TEUW | MO_ALIGN);
169
break;
170
case 0x3: /* ldd, load double word */
171
if (rd & 1)
172
@@ -XXX,XX +XXX,XX @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
173
gen_address_mask(dc, cpu_addr);
174
t64 = tcg_temp_new_i64();
175
tcg_gen_qemu_ld_i64(t64, cpu_addr,
176
- dc->mem_idx, MO_TEUQ);
177
+ dc->mem_idx, MO_TEUQ | MO_ALIGN);
178
tcg_gen_trunc_i64_tl(cpu_val, t64);
179
tcg_gen_ext32u_tl(cpu_val, cpu_val);
180
gen_store_gpr(dc, rd + 1, cpu_val);
181
@@ -XXX,XX +XXX,XX @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
182
case 0xa: /* ldsh, load signed halfword */
183
gen_address_mask(dc, cpu_addr);
184
tcg_gen_qemu_ld_tl(cpu_val, cpu_addr,
185
- dc->mem_idx, MO_TESW);
186
+ dc->mem_idx, MO_TESW | MO_ALIGN);
187
break;
188
case 0xd: /* ldstub */
189
gen_ldstub(dc, cpu_val, cpu_addr, dc->mem_idx);
190
@@ -XXX,XX +XXX,XX @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
191
case 0x08: /* V9 ldsw */
192
gen_address_mask(dc, cpu_addr);
193
tcg_gen_qemu_ld_tl(cpu_val, cpu_addr,
194
- dc->mem_idx, MO_TESL);
195
+ dc->mem_idx, MO_TESL | MO_ALIGN);
196
break;
197
case 0x0b: /* V9 ldx */
198
gen_address_mask(dc, cpu_addr);
199
tcg_gen_qemu_ld_tl(cpu_val, cpu_addr,
200
- dc->mem_idx, MO_TEUQ);
201
+ dc->mem_idx, MO_TEUQ | MO_ALIGN);
202
break;
203
case 0x18: /* V9 ldswa */
204
gen_ld_asi(dc, cpu_val, cpu_addr, insn, MO_TESL);
205
@@ -XXX,XX +XXX,XX @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
206
gen_address_mask(dc, cpu_addr);
207
cpu_dst_32 = gen_dest_fpr_F(dc);
208
tcg_gen_qemu_ld_i32(cpu_dst_32, cpu_addr,
209
- dc->mem_idx, MO_TEUL);
210
+ dc->mem_idx, MO_TEUL | MO_ALIGN);
211
gen_store_fpr_F(dc, rd, cpu_dst_32);
212
break;
213
case 0x21: /* ldfsr, V9 ldxfsr */
214
@@ -XXX,XX +XXX,XX @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
215
if (rd == 1) {
216
TCGv_i64 t64 = tcg_temp_new_i64();
217
tcg_gen_qemu_ld_i64(t64, cpu_addr,
218
- dc->mem_idx, MO_TEUQ);
219
+ dc->mem_idx, MO_TEUQ | MO_ALIGN);
220
gen_helper_ldxfsr(cpu_fsr, cpu_env, cpu_fsr, t64);
221
break;
222
}
223
#endif
224
cpu_dst_32 = tcg_temp_new_i32();
225
tcg_gen_qemu_ld_i32(cpu_dst_32, cpu_addr,
226
- dc->mem_idx, MO_TEUL);
227
+ dc->mem_idx, MO_TEUL | MO_ALIGN);
228
gen_helper_ldfsr(cpu_fsr, cpu_env, cpu_fsr, cpu_dst_32);
229
break;
230
case 0x22: /* ldqf, load quad fpreg */
231
@@ -XXX,XX +XXX,XX @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
232
case 0x4: /* st, store word */
233
gen_address_mask(dc, cpu_addr);
234
tcg_gen_qemu_st_tl(cpu_val, cpu_addr,
235
- dc->mem_idx, MO_TEUL);
236
+ dc->mem_idx, MO_TEUL | MO_ALIGN);
237
break;
238
case 0x5: /* stb, store byte */
239
gen_address_mask(dc, cpu_addr);
240
@@ -XXX,XX +XXX,XX @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
241
case 0x6: /* sth, store halfword */
242
gen_address_mask(dc, cpu_addr);
243
tcg_gen_qemu_st_tl(cpu_val, cpu_addr,
244
- dc->mem_idx, MO_TEUW);
245
+ dc->mem_idx, MO_TEUW | MO_ALIGN);
246
break;
247
case 0x7: /* std, store double word */
248
if (rd & 1)
249
@@ -XXX,XX +XXX,XX @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
250
t64 = tcg_temp_new_i64();
251
tcg_gen_concat_tl_i64(t64, lo, cpu_val);
252
tcg_gen_qemu_st_i64(t64, cpu_addr,
253
- dc->mem_idx, MO_TEUQ);
254
+ dc->mem_idx, MO_TEUQ | MO_ALIGN);
255
}
256
break;
257
#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
258
@@ -XXX,XX +XXX,XX @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
259
case 0x0e: /* V9 stx */
260
gen_address_mask(dc, cpu_addr);
261
tcg_gen_qemu_st_tl(cpu_val, cpu_addr,
262
- dc->mem_idx, MO_TEUQ);
263
+ dc->mem_idx, MO_TEUQ | MO_ALIGN);
264
break;
265
case 0x1e: /* V9 stxa */
266
gen_st_asi(dc, cpu_val, cpu_addr, insn, MO_TEUQ);
267
@@ -XXX,XX +XXX,XX @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
268
gen_address_mask(dc, cpu_addr);
269
cpu_src1_32 = gen_load_fpr_F(dc, rd);
270
tcg_gen_qemu_st_i32(cpu_src1_32, cpu_addr,
271
- dc->mem_idx, MO_TEUL);
272
+ dc->mem_idx, MO_TEUL | MO_ALIGN);
273
break;
274
case 0x25: /* stfsr, V9 stxfsr */
275
{
276
@@ -XXX,XX +XXX,XX @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
277
gen_address_mask(dc, cpu_addr);
278
if (rd == 1) {
279
tcg_gen_qemu_st_tl(cpu_fsr, cpu_addr,
280
- dc->mem_idx, MO_TEUQ);
281
+ dc->mem_idx, MO_TEUQ | MO_ALIGN);
282
break;
283
}
284
#endif
285
tcg_gen_qemu_st_tl(cpu_fsr, cpu_addr,
286
- dc->mem_idx, MO_TEUL);
287
+ dc->mem_idx, MO_TEUL | MO_ALIGN);
288
}
289
break;
290
case 0x26:
291
--
292
2.34.1
diff view generated by jsdifflib
New patch
[PULL 17/42] target/sparc: Use cpu_ld*_code_mmu
1
This passes on the memop as given as argument to
2
helper_ld_asi to the ultimate load primitive.
1
3
4
Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
---
7
target/sparc/ldst_helper.c | 10 ++++++----
8
1 file changed, 6 insertions(+), 4 deletions(-)
9
10
diff --git a/target/sparc/ldst_helper.c b/target/sparc/ldst_helper.c
11
index XXXXXXX..XXXXXXX 100644
12
--- a/target/sparc/ldst_helper.c
13
+++ b/target/sparc/ldst_helper.c
14
@@ -XXX,XX +XXX,XX @@ uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr,
15
#if defined(DEBUG_MXCC) || defined(DEBUG_ASI)
16
uint32_t last_addr = addr;
17
#endif
18
+ MemOpIdx oi;
19
20
do_check_align(env, addr, size - 1, GETPC());
21
switch (asi) {
22
@@ -XXX,XX +XXX,XX @@ uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr,
23
case ASI_M_IODIAG: /* Turbosparc IOTLB Diagnostic */
24
break;
25
case ASI_KERNELTXT: /* Supervisor code access */
26
+ oi = make_memop_idx(memop, cpu_mmu_index(env, true));
27
switch (size) {
28
case 1:
29
- ret = cpu_ldub_code(env, addr);
30
+ ret = cpu_ldb_code_mmu(env, addr, oi, GETPC());
31
break;
32
case 2:
33
- ret = cpu_lduw_code(env, addr);
34
+ ret = cpu_ldw_code_mmu(env, addr, oi, GETPC());
35
break;
36
default:
37
case 4:
38
- ret = cpu_ldl_code(env, addr);
39
+ ret = cpu_ldl_code_mmu(env, addr, oi, GETPC());
40
break;
41
case 8:
42
- ret = cpu_ldq_code(env, addr);
43
+ ret = cpu_ldq_code_mmu(env, addr, oi, GETPC());
44
break;
45
}
46
break;
47
--
48
2.34.1
diff view generated by jsdifflib
New patch
[PULL 18/42] target/sparc: Remove TARGET_ALIGNED_ONLY
1
Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
2
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
3
---
4
configs/targets/sparc-linux-user.mak | 1 -
5
configs/targets/sparc-softmmu.mak | 1 -
6
configs/targets/sparc32plus-linux-user.mak | 1 -
7
configs/targets/sparc64-linux-user.mak | 1 -
8
configs/targets/sparc64-softmmu.mak | 1 -
9
5 files changed, 5 deletions(-)
1
10
11
diff --git a/configs/targets/sparc-linux-user.mak b/configs/targets/sparc-linux-user.mak
12
index XXXXXXX..XXXXXXX 100644
13
--- a/configs/targets/sparc-linux-user.mak
14
+++ b/configs/targets/sparc-linux-user.mak
15
@@ -XXX,XX +XXX,XX @@
16
TARGET_ARCH=sparc
17
TARGET_SYSTBL_ABI=common,32
18
TARGET_SYSTBL=syscall.tbl
19
-TARGET_ALIGNED_ONLY=y
20
TARGET_BIG_ENDIAN=y
21
diff --git a/configs/targets/sparc-softmmu.mak b/configs/targets/sparc-softmmu.mak
22
index XXXXXXX..XXXXXXX 100644
23
--- a/configs/targets/sparc-softmmu.mak
24
+++ b/configs/targets/sparc-softmmu.mak
25
@@ -XXX,XX +XXX,XX @@
26
TARGET_ARCH=sparc
27
-TARGET_ALIGNED_ONLY=y
28
TARGET_BIG_ENDIAN=y
29
diff --git a/configs/targets/sparc32plus-linux-user.mak b/configs/targets/sparc32plus-linux-user.mak
30
index XXXXXXX..XXXXXXX 100644
31
--- a/configs/targets/sparc32plus-linux-user.mak
32
+++ b/configs/targets/sparc32plus-linux-user.mak
33
@@ -XXX,XX +XXX,XX @@ TARGET_BASE_ARCH=sparc
34
TARGET_ABI_DIR=sparc
35
TARGET_SYSTBL_ABI=common,32
36
TARGET_SYSTBL=syscall.tbl
37
-TARGET_ALIGNED_ONLY=y
38
TARGET_BIG_ENDIAN=y
39
diff --git a/configs/targets/sparc64-linux-user.mak b/configs/targets/sparc64-linux-user.mak
40
index XXXXXXX..XXXXXXX 100644
41
--- a/configs/targets/sparc64-linux-user.mak
42
+++ b/configs/targets/sparc64-linux-user.mak
43
@@ -XXX,XX +XXX,XX @@ TARGET_BASE_ARCH=sparc
44
TARGET_ABI_DIR=sparc
45
TARGET_SYSTBL_ABI=common,64
46
TARGET_SYSTBL=syscall.tbl
47
-TARGET_ALIGNED_ONLY=y
48
TARGET_BIG_ENDIAN=y
49
diff --git a/configs/targets/sparc64-softmmu.mak b/configs/targets/sparc64-softmmu.mak
50
index XXXXXXX..XXXXXXX 100644
51
--- a/configs/targets/sparc64-softmmu.mak
52
+++ b/configs/targets/sparc64-softmmu.mak
53
@@ -XXX,XX +XXX,XX @@
54
TARGET_ARCH=sparc64
55
TARGET_BASE_ARCH=sparc
56
-TARGET_ALIGNED_ONLY=y
57
TARGET_BIG_ENDIAN=y
58
--
59
2.34.1
diff view generated by jsdifflib
New patch
[PULL 19/42] tcg/i386: Rationalize args to tcg_out_qemu_{ld,st}
1
1
Interpret the variable argument placement in the caller. Pass data_type
2
instead of is64 -- there are several places where we already convert back
3
from bool to type. Clean things up by using type throughout.
4
5
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
---
8
tcg/i386/tcg-target.c.inc | 111 +++++++++++++++++---------------------
9
1 file changed, 50 insertions(+), 61 deletions(-)
10
11
diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
12
index XXXXXXX..XXXXXXX 100644
13
--- a/tcg/i386/tcg-target.c.inc
14
+++ b/tcg/i386/tcg-target.c.inc
15
@@ -XXX,XX +XXX,XX @@ static inline void tcg_out_tlb_load(TCGContext *s, TCGReg addrlo, TCGReg addrhi,
16
* Record the context of a call to the out of line helper code for the slow path
17
* for a load or store, so that we can later generate the correct helper code
18
*/
19
-static void add_qemu_ldst_label(TCGContext *s, bool is_ld, bool is_64,
20
- MemOpIdx oi,
21
+static void add_qemu_ldst_label(TCGContext *s, bool is_ld,
22
+ TCGType type, MemOpIdx oi,
23
TCGReg datalo, TCGReg datahi,
24
TCGReg addrlo, TCGReg addrhi,
25
tcg_insn_unit *raddr,
26
@@ -XXX,XX +XXX,XX @@ static void add_qemu_ldst_label(TCGContext *s, bool is_ld, bool is_64,
27
28
label->is_ld = is_ld;
29
label->oi = oi;
30
- label->type = is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32;
31
+ label->type = type;
32
label->datalo_reg = datalo;
33
label->datahi_reg = datahi;
34
label->addrlo_reg = addrlo;
35
@@ -XXX,XX +XXX,XX @@ static inline int setup_guest_base_seg(void)
36
37
static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg datalo, TCGReg datahi,
38
TCGReg base, int index, intptr_t ofs,
39
- int seg, bool is64, MemOp memop)
40
+ int seg, TCGType type, MemOp memop)
41
{
42
- TCGType type = is64 ? TCG_TYPE_I64 : TCG_TYPE_I32;
43
bool use_movbe = false;
44
- int rexw = is64 * P_REXW;
45
+ int rexw = (type == TCG_TYPE_I32 ? 0 : P_REXW);
46
int movop = OPC_MOVL_GvEv;
47
48
/* Do big-endian loads with movbe. */
49
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg datalo, TCGReg datahi,
50
}
51
}
52
53
-/* XXX: qemu_ld and qemu_st could be modified to clobber only EDX and
54
- EAX. It will be useful once fixed registers globals are less
55
- common. */
56
-static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is64)
57
+static void tcg_out_qemu_ld(TCGContext *s, TCGReg datalo, TCGReg datahi,
58
+ TCGReg addrlo, TCGReg addrhi,
59
+ MemOpIdx oi, TCGType data_type)
60
{
61
- TCGReg datalo, datahi, addrlo;
62
- TCGReg addrhi __attribute__((unused));
63
- MemOpIdx oi;
64
- MemOp opc;
65
+ MemOp opc = get_memop(oi);
66
+
67
#if defined(CONFIG_SOFTMMU)
68
- int mem_index;
69
tcg_insn_unit *label_ptr[2];
70
-#else
71
- unsigned a_bits;
72
-#endif
73
74
- datalo = *args++;
75
- datahi = (TCG_TARGET_REG_BITS == 32 && is64 ? *args++ : 0);
76
- addrlo = *args++;
77
- addrhi = (TARGET_LONG_BITS > TCG_TARGET_REG_BITS ? *args++ : 0);
78
- oi = *args++;
79
- opc = get_memop(oi);
80
-
81
-#if defined(CONFIG_SOFTMMU)
82
- mem_index = get_mmuidx(oi);
83
-
84
- tcg_out_tlb_load(s, addrlo, addrhi, mem_index, opc,
85
+ tcg_out_tlb_load(s, addrlo, addrhi, get_mmuidx(oi), opc,
86
label_ptr, offsetof(CPUTLBEntry, addr_read));
87
88
/* TLB Hit. */
89
- tcg_out_qemu_ld_direct(s, datalo, datahi, TCG_REG_L1, -1, 0, 0, is64, opc);
90
+ tcg_out_qemu_ld_direct(s, datalo, datahi, TCG_REG_L1,
91
+ -1, 0, 0, data_type, opc);
92
93
/* Record the current context of a load into ldst label */
94
- add_qemu_ldst_label(s, true, is64, oi, datalo, datahi, addrlo, addrhi,
95
- s->code_ptr, label_ptr);
96
+ add_qemu_ldst_label(s, true, data_type, oi, datalo, datahi,
97
+ addrlo, addrhi, s->code_ptr, label_ptr);
98
#else
99
- a_bits = get_alignment_bits(opc);
100
+ unsigned a_bits = get_alignment_bits(opc);
101
if (a_bits) {
102
tcg_out_test_alignment(s, true, addrlo, addrhi, a_bits);
103
}
104
105
tcg_out_qemu_ld_direct(s, datalo, datahi, addrlo, x86_guest_base_index,
106
x86_guest_base_offset, x86_guest_base_seg,
107
- is64, opc);
108
+ data_type, opc);
109
#endif
110
}
111
112
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg datalo, TCGReg datahi,
113
}
114
}
115
116
-static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is64)
117
+static void tcg_out_qemu_st(TCGContext *s, TCGReg datalo, TCGReg datahi,
118
+ TCGReg addrlo, TCGReg addrhi,
119
+ MemOpIdx oi, TCGType data_type)
120
{
121
- TCGReg datalo, datahi, addrlo;
122
- TCGReg addrhi __attribute__((unused));
123
- MemOpIdx oi;
124
- MemOp opc;
125
+ MemOp opc = get_memop(oi);
126
+
127
#if defined(CONFIG_SOFTMMU)
128
- int mem_index;
129
tcg_insn_unit *label_ptr[2];
130
-#else
131
- unsigned a_bits;
132
-#endif
133
134
- datalo = *args++;
135
- datahi = (TCG_TARGET_REG_BITS == 32 && is64 ? *args++ : 0);
136
- addrlo = *args++;
137
- addrhi = (TARGET_LONG_BITS > TCG_TARGET_REG_BITS ? *args++ : 0);
138
- oi = *args++;
139
- opc = get_memop(oi);
140
-
141
-#if defined(CONFIG_SOFTMMU)
142
- mem_index = get_mmuidx(oi);
143
-
144
- tcg_out_tlb_load(s, addrlo, addrhi, mem_index, opc,
145
+ tcg_out_tlb_load(s, addrlo, addrhi, get_mmuidx(oi), opc,
146
label_ptr, offsetof(CPUTLBEntry, addr_write));
147
148
/* TLB Hit. */
149
tcg_out_qemu_st_direct(s, datalo, datahi, TCG_REG_L1, -1, 0, 0, opc);
150
151
/* Record the current context of a store into ldst label */
152
- add_qemu_ldst_label(s, false, is64, oi, datalo, datahi, addrlo, addrhi,
153
- s->code_ptr, label_ptr);
154
+ add_qemu_ldst_label(s, false, data_type, oi, datalo, datahi,
155
+ addrlo, addrhi, s->code_ptr, label_ptr);
156
#else
157
- a_bits = get_alignment_bits(opc);
158
+ unsigned a_bits = get_alignment_bits(opc);
159
if (a_bits) {
160
tcg_out_test_alignment(s, false, addrlo, addrhi, a_bits);
161
}
162
@@ -XXX,XX +XXX,XX @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
163
break;
164
165
case INDEX_op_qemu_ld_i32:
166
- tcg_out_qemu_ld(s, args, 0);
167
+ if (TCG_TARGET_REG_BITS >= TARGET_LONG_BITS) {
168
+ tcg_out_qemu_ld(s, a0, -1, a1, -1, a2, TCG_TYPE_I32);
169
+ } else {
170
+ tcg_out_qemu_ld(s, a0, -1, a1, a2, args[3], TCG_TYPE_I32);
171
+ }
172
break;
173
case INDEX_op_qemu_ld_i64:
174
- tcg_out_qemu_ld(s, args, 1);
175
+ if (TCG_TARGET_REG_BITS == 64) {
176
+ tcg_out_qemu_ld(s, a0, -1, a1, -1, a2, TCG_TYPE_I64);
177
+ } else if (TARGET_LONG_BITS == 32) {
178
+ tcg_out_qemu_ld(s, a0, a1, a2, -1, args[3], TCG_TYPE_I64);
179
+ } else {
180
+ tcg_out_qemu_ld(s, a0, a1, a2, args[3], args[4], TCG_TYPE_I64);
181
+ }
182
break;
183
case INDEX_op_qemu_st_i32:
184
case INDEX_op_qemu_st8_i32:
185
- tcg_out_qemu_st(s, args, 0);
186
+ if (TCG_TARGET_REG_BITS >= TARGET_LONG_BITS) {
187
+ tcg_out_qemu_st(s, a0, -1, a1, -1, a2, TCG_TYPE_I32);
188
+ } else {
189
+ tcg_out_qemu_st(s, a0, -1, a1, a2, args[3], TCG_TYPE_I32);
190
+ }
191
break;
192
case INDEX_op_qemu_st_i64:
193
- tcg_out_qemu_st(s, args, 1);
194
+ if (TCG_TARGET_REG_BITS == 64) {
195
+ tcg_out_qemu_st(s, a0, -1, a1, -1, a2, TCG_TYPE_I64);
196
+ } else if (TARGET_LONG_BITS == 32) {
197
+ tcg_out_qemu_st(s, a0, a1, a2, -1, args[3], TCG_TYPE_I64);
198
+ } else {
199
+ tcg_out_qemu_st(s, a0, a1, a2, args[3], args[4], TCG_TYPE_I64);
200
+ }
201
break;
202
203
OP_32_64(mulu2):
204
--
205
2.34.1
206
207
diff view generated by jsdifflib
New patch
[PULL 20/42] tcg/i386: Generalize multi-part load overlap test
1
Test for both base and index; use datahi as a temporary, overwritten
2
by the final load. Always perform the loads in ascending order, so
3
that any (user-only) fault sees the correct address.
1
4
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
---
7
tcg/i386/tcg-target.c.inc | 31 +++++++++++++++----------------
8
1 file changed, 15 insertions(+), 16 deletions(-)
9
10
diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
11
index XXXXXXX..XXXXXXX 100644
12
--- a/tcg/i386/tcg-target.c.inc
13
+++ b/tcg/i386/tcg-target.c.inc
14
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg datalo, TCGReg datahi,
15
if (TCG_TARGET_REG_BITS == 64) {
16
tcg_out_modrm_sib_offset(s, movop + P_REXW + seg, datalo,
17
base, index, 0, ofs);
18
+ break;
19
+ }
20
+ if (use_movbe) {
21
+ TCGReg t = datalo;
22
+ datalo = datahi;
23
+ datahi = t;
24
+ }
25
+ if (base == datalo || index == datalo) {
26
+ tcg_out_modrm_sib_offset(s, OPC_LEA, datahi, base, index, 0, ofs);
27
+ tcg_out_modrm_offset(s, movop + seg, datalo, datahi, 0);
28
+ tcg_out_modrm_offset(s, movop + seg, datahi, datahi, 4);
29
} else {
30
- if (use_movbe) {
31
- TCGReg t = datalo;
32
- datalo = datahi;
33
- datahi = t;
34
- }
35
- if (base != datalo) {
36
- tcg_out_modrm_sib_offset(s, movop + seg, datalo,
37
- base, index, 0, ofs);
38
- tcg_out_modrm_sib_offset(s, movop + seg, datahi,
39
- base, index, 0, ofs + 4);
40
- } else {
41
- tcg_out_modrm_sib_offset(s, movop + seg, datahi,
42
- base, index, 0, ofs + 4);
43
- tcg_out_modrm_sib_offset(s, movop + seg, datalo,
44
- base, index, 0, ofs);
45
- }
46
+ tcg_out_modrm_sib_offset(s, movop + seg, datalo,
47
+ base, index, 0, ofs);
48
+ tcg_out_modrm_sib_offset(s, movop + seg, datahi,
49
+ base, index, 0, ofs + 4);
50
}
51
break;
52
default:
53
--
54
2.34.1
diff view generated by jsdifflib
New patch
[PULL 21/42] tcg/i386: Introduce HostAddress
1
Collect the 4 potential parts of the host address into a struct.
2
Reorg tcg_out_qemu_{ld,st}_direct to use it.
3
Reorg guest_base handling to use it.
1
4
5
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
---
8
tcg/i386/tcg-target.c.inc | 165 +++++++++++++++++++++-----------------
9
1 file changed, 90 insertions(+), 75 deletions(-)
10
11
diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
12
index XXXXXXX..XXXXXXX 100644
13
--- a/tcg/i386/tcg-target.c.inc
14
+++ b/tcg/i386/tcg-target.c.inc
15
@@ -XXX,XX +XXX,XX @@ static void tcg_out_nopn(TCGContext *s, int n)
16
tcg_out8(s, 0x90);
17
}
18
19
+typedef struct {
20
+ TCGReg base;
21
+ int index;
22
+ int ofs;
23
+ int seg;
24
+} HostAddress;
25
+
26
#if defined(CONFIG_SOFTMMU)
27
/* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr,
28
* int mmu_idx, uintptr_t ra)
29
@@ -XXX,XX +XXX,XX @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
30
return tcg_out_fail_alignment(s, l);
31
}
32
33
-#if TCG_TARGET_REG_BITS == 32
34
-# define x86_guest_base_seg 0
35
-# define x86_guest_base_index -1
36
-# define x86_guest_base_offset guest_base
37
-#else
38
-static int x86_guest_base_seg;
39
-static int x86_guest_base_index = -1;
40
-static int32_t x86_guest_base_offset;
41
-# if defined(__x86_64__) && defined(__linux__)
42
-# include <asm/prctl.h>
43
-# include <sys/prctl.h>
44
+static HostAddress x86_guest_base = {
45
+ .index = -1
46
+};
47
+
48
+#if defined(__x86_64__) && defined(__linux__)
49
+# include <asm/prctl.h>
50
+# include <sys/prctl.h>
51
int arch_prctl(int code, unsigned long addr);
52
static inline int setup_guest_base_seg(void)
53
{
54
@@ -XXX,XX +XXX,XX @@ static inline int setup_guest_base_seg(void)
55
}
56
return 0;
57
}
58
-# elif defined (__FreeBSD__) || defined (__FreeBSD_kernel__)
59
-# include <machine/sysarch.h>
60
+#elif defined(__x86_64__) && \
61
+ (defined (__FreeBSD__) || defined (__FreeBSD_kernel__))
62
+# include <machine/sysarch.h>
63
static inline int setup_guest_base_seg(void)
64
{
65
if (sysarch(AMD64_SET_GSBASE, &guest_base) == 0) {
66
@@ -XXX,XX +XXX,XX @@ static inline int setup_guest_base_seg(void)
67
}
68
return 0;
69
}
70
-# else
71
+#else
72
static inline int setup_guest_base_seg(void)
73
{
74
return 0;
75
}
76
-# endif
77
-#endif
78
+#endif /* setup_guest_base_seg */
79
#endif /* SOFTMMU */
80
81
static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg datalo, TCGReg datahi,
82
- TCGReg base, int index, intptr_t ofs,
83
- int seg, TCGType type, MemOp memop)
84
+ HostAddress h, TCGType type, MemOp memop)
85
{
86
bool use_movbe = false;
87
int rexw = (type == TCG_TYPE_I32 ? 0 : P_REXW);
88
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg datalo, TCGReg datahi,
89
90
switch (memop & MO_SSIZE) {
91
case MO_UB:
92
- tcg_out_modrm_sib_offset(s, OPC_MOVZBL + seg, datalo,
93
- base, index, 0, ofs);
94
+ tcg_out_modrm_sib_offset(s, OPC_MOVZBL + h.seg, datalo,
95
+ h.base, h.index, 0, h.ofs);
96
break;
97
case MO_SB:
98
- tcg_out_modrm_sib_offset(s, OPC_MOVSBL + rexw + seg, datalo,
99
- base, index, 0, ofs);
100
+ tcg_out_modrm_sib_offset(s, OPC_MOVSBL + rexw + h.seg, datalo,
101
+ h.base, h.index, 0, h.ofs);
102
break;
103
case MO_UW:
104
if (use_movbe) {
105
/* There is no extending movbe; only low 16-bits are modified. */
106
- if (datalo != base && datalo != index) {
107
+ if (datalo != h.base && datalo != h.index) {
108
/* XOR breaks dependency chains. */
109
tgen_arithr(s, ARITH_XOR, datalo, datalo);
110
- tcg_out_modrm_sib_offset(s, OPC_MOVBE_GyMy + P_DATA16 + seg,
111
- datalo, base, index, 0, ofs);
112
+ tcg_out_modrm_sib_offset(s, OPC_MOVBE_GyMy + P_DATA16 + h.seg,
113
+ datalo, h.base, h.index, 0, h.ofs);
114
} else {
115
- tcg_out_modrm_sib_offset(s, OPC_MOVBE_GyMy + P_DATA16 + seg,
116
- datalo, base, index, 0, ofs);
117
+ tcg_out_modrm_sib_offset(s, OPC_MOVBE_GyMy + P_DATA16 + h.seg,
118
+ datalo, h.base, h.index, 0, h.ofs);
119
tcg_out_ext16u(s, datalo, datalo);
120
}
121
} else {
122
- tcg_out_modrm_sib_offset(s, OPC_MOVZWL + seg, datalo,
123
- base, index, 0, ofs);
124
+ tcg_out_modrm_sib_offset(s, OPC_MOVZWL + h.seg, datalo,
125
+ h.base, h.index, 0, h.ofs);
126
}
127
break;
128
case MO_SW:
129
if (use_movbe) {
130
- tcg_out_modrm_sib_offset(s, OPC_MOVBE_GyMy + P_DATA16 + seg,
131
- datalo, base, index, 0, ofs);
132
+ tcg_out_modrm_sib_offset(s, OPC_MOVBE_GyMy + P_DATA16 + h.seg,
133
+ datalo, h.base, h.index, 0, h.ofs);
134
tcg_out_ext16s(s, type, datalo, datalo);
135
} else {
136
- tcg_out_modrm_sib_offset(s, OPC_MOVSWL + rexw + seg,
137
- datalo, base, index, 0, ofs);
138
+ tcg_out_modrm_sib_offset(s, OPC_MOVSWL + rexw + h.seg,
139
+ datalo, h.base, h.index, 0, h.ofs);
140
}
141
break;
142
case MO_UL:
143
- tcg_out_modrm_sib_offset(s, movop + seg, datalo, base, index, 0, ofs);
144
+ tcg_out_modrm_sib_offset(s, movop + h.seg, datalo,
145
+ h.base, h.index, 0, h.ofs);
146
break;
147
#if TCG_TARGET_REG_BITS == 64
148
case MO_SL:
149
if (use_movbe) {
150
- tcg_out_modrm_sib_offset(s, OPC_MOVBE_GyMy + seg, datalo,
151
- base, index, 0, ofs);
152
+ tcg_out_modrm_sib_offset(s, OPC_MOVBE_GyMy + h.seg, datalo,
153
+ h.base, h.index, 0, h.ofs);
154
tcg_out_ext32s(s, datalo, datalo);
155
} else {
156
- tcg_out_modrm_sib_offset(s, OPC_MOVSLQ + seg, datalo,
157
- base, index, 0, ofs);
158
+ tcg_out_modrm_sib_offset(s, OPC_MOVSLQ + h.seg, datalo,
159
+ h.base, h.index, 0, h.ofs);
160
}
161
break;
162
#endif
163
case MO_UQ:
164
if (TCG_TARGET_REG_BITS == 64) {
165
- tcg_out_modrm_sib_offset(s, movop + P_REXW + seg, datalo,
166
- base, index, 0, ofs);
167
+ tcg_out_modrm_sib_offset(s, movop + P_REXW + h.seg, datalo,
168
+ h.base, h.index, 0, h.ofs);
169
break;
170
}
171
if (use_movbe) {
172
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg datalo, TCGReg datahi,
173
datalo = datahi;
174
datahi = t;
175
}
176
- if (base == datalo || index == datalo) {
177
- tcg_out_modrm_sib_offset(s, OPC_LEA, datahi, base, index, 0, ofs);
178
- tcg_out_modrm_offset(s, movop + seg, datalo, datahi, 0);
179
- tcg_out_modrm_offset(s, movop + seg, datahi, datahi, 4);
180
+ if (h.base == datalo || h.index == datalo) {
181
+ tcg_out_modrm_sib_offset(s, OPC_LEA, datahi,
182
+ h.base, h.index, 0, h.ofs);
183
+ tcg_out_modrm_offset(s, movop + h.seg, datalo, datahi, 0);
184
+ tcg_out_modrm_offset(s, movop + h.seg, datahi, datahi, 4);
185
} else {
186
- tcg_out_modrm_sib_offset(s, movop + seg, datalo,
187
- base, index, 0, ofs);
188
- tcg_out_modrm_sib_offset(s, movop + seg, datahi,
189
- base, index, 0, ofs + 4);
190
+ tcg_out_modrm_sib_offset(s, movop + h.seg, datalo,
191
+ h.base, h.index, 0, h.ofs);
192
+ tcg_out_modrm_sib_offset(s, movop + h.seg, datahi,
193
+ h.base, h.index, 0, h.ofs + 4);
194
}
195
break;
196
default:
197
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg datalo, TCGReg datahi,
198
MemOpIdx oi, TCGType data_type)
199
{
200
MemOp opc = get_memop(oi);
201
+ HostAddress h;
202
203
#if defined(CONFIG_SOFTMMU)
204
tcg_insn_unit *label_ptr[2];
205
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg datalo, TCGReg datahi,
206
label_ptr, offsetof(CPUTLBEntry, addr_read));
207
208
/* TLB Hit. */
209
- tcg_out_qemu_ld_direct(s, datalo, datahi, TCG_REG_L1,
210
- -1, 0, 0, data_type, opc);
211
+ h.base = TCG_REG_L1;
212
+ h.index = -1;
213
+ h.ofs = 0;
214
+ h.seg = 0;
215
+ tcg_out_qemu_ld_direct(s, datalo, datahi, h, data_type, opc);
216
217
/* Record the current context of a load into ldst label */
218
add_qemu_ldst_label(s, true, data_type, oi, datalo, datahi,
219
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg datalo, TCGReg datahi,
220
tcg_out_test_alignment(s, true, addrlo, addrhi, a_bits);
221
}
222
223
- tcg_out_qemu_ld_direct(s, datalo, datahi, addrlo, x86_guest_base_index,
224
- x86_guest_base_offset, x86_guest_base_seg,
225
- data_type, opc);
226
+ h = x86_guest_base;
227
+ h.base = addrlo;
228
+ tcg_out_qemu_ld_direct(s, datalo, datahi, h, data_type, opc);
229
#endif
230
}
231
232
static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg datalo, TCGReg datahi,
233
- TCGReg base, int index, intptr_t ofs,
234
- int seg, MemOp memop)
235
+ HostAddress h, MemOp memop)
236
{
237
bool use_movbe = false;
238
int movop = OPC_MOVL_EvGv;
239
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg datalo, TCGReg datahi,
240
case MO_8:
241
/* This is handled with constraints on INDEX_op_qemu_st8_i32. */
242
tcg_debug_assert(TCG_TARGET_REG_BITS == 64 || datalo < 4);
243
- tcg_out_modrm_sib_offset(s, OPC_MOVB_EvGv + P_REXB_R + seg,
244
- datalo, base, index, 0, ofs);
245
+ tcg_out_modrm_sib_offset(s, OPC_MOVB_EvGv + P_REXB_R + h.seg,
246
+ datalo, h.base, h.index, 0, h.ofs);
247
break;
248
case MO_16:
249
- tcg_out_modrm_sib_offset(s, movop + P_DATA16 + seg, datalo,
250
- base, index, 0, ofs);
251
+ tcg_out_modrm_sib_offset(s, movop + P_DATA16 + h.seg, datalo,
252
+ h.base, h.index, 0, h.ofs);
253
break;
254
case MO_32:
255
- tcg_out_modrm_sib_offset(s, movop + seg, datalo, base, index, 0, ofs);
256
+ tcg_out_modrm_sib_offset(s, movop + h.seg, datalo,
257
+ h.base, h.index, 0, h.ofs);
258
break;
259
case MO_64:
260
if (TCG_TARGET_REG_BITS == 64) {
261
- tcg_out_modrm_sib_offset(s, movop + P_REXW + seg, datalo,
262
- base, index, 0, ofs);
263
+ tcg_out_modrm_sib_offset(s, movop + P_REXW + h.seg, datalo,
264
+ h.base, h.index, 0, h.ofs);
265
} else {
266
if (use_movbe) {
267
TCGReg t = datalo;
268
datalo = datahi;
269
datahi = t;
270
}
271
- tcg_out_modrm_sib_offset(s, movop + seg, datalo,
272
- base, index, 0, ofs);
273
- tcg_out_modrm_sib_offset(s, movop + seg, datahi,
274
- base, index, 0, ofs + 4);
275
+ tcg_out_modrm_sib_offset(s, movop + h.seg, datalo,
276
+ h.base, h.index, 0, h.ofs);
277
+ tcg_out_modrm_sib_offset(s, movop + h.seg, datahi,
278
+ h.base, h.index, 0, h.ofs + 4);
279
}
280
break;
281
default:
282
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg datalo, TCGReg datahi,
283
MemOpIdx oi, TCGType data_type)
284
{
285
MemOp opc = get_memop(oi);
286
+ HostAddress h;
287
288
#if defined(CONFIG_SOFTMMU)
289
tcg_insn_unit *label_ptr[2];
290
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg datalo, TCGReg datahi,
291
label_ptr, offsetof(CPUTLBEntry, addr_write));
292
293
/* TLB Hit. */
294
- tcg_out_qemu_st_direct(s, datalo, datahi, TCG_REG_L1, -1, 0, 0, opc);
295
+ h.base = TCG_REG_L1;
296
+ h.index = -1;
297
+ h.ofs = 0;
298
+ h.seg = 0;
299
+ tcg_out_qemu_st_direct(s, datalo, datahi, h, opc);
300
301
/* Record the current context of a store into ldst label */
302
add_qemu_ldst_label(s, false, data_type, oi, datalo, datahi,
303
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg datalo, TCGReg datahi,
304
tcg_out_test_alignment(s, false, addrlo, addrhi, a_bits);
305
}
306
307
- tcg_out_qemu_st_direct(s, datalo, datahi, addrlo, x86_guest_base_index,
308
- x86_guest_base_offset, x86_guest_base_seg, opc);
309
+ h = x86_guest_base;
310
+ h.base = addrlo;
311
+
312
+ tcg_out_qemu_st_direct(s, datalo, datahi, h, opc);
313
#endif
314
}
315
316
@@ -XXX,XX +XXX,XX @@ static void tcg_target_qemu_prologue(TCGContext *s)
317
(ARRAY_SIZE(tcg_target_callee_save_regs) + 2) * 4
318
+ stack_addend);
319
#else
320
-# if !defined(CONFIG_SOFTMMU) && TCG_TARGET_REG_BITS == 64
321
+# if !defined(CONFIG_SOFTMMU)
322
if (guest_base) {
323
int seg = setup_guest_base_seg();
324
if (seg != 0) {
325
- x86_guest_base_seg = seg;
326
+ x86_guest_base.seg = seg;
327
} else if (guest_base == (int32_t)guest_base) {
328
- x86_guest_base_offset = guest_base;
329
+ x86_guest_base.ofs = guest_base;
330
} else {
331
/* Choose R12 because, as a base, it requires a SIB byte. */
332
- x86_guest_base_index = TCG_REG_R12;
333
- tcg_out_movi(s, TCG_TYPE_PTR, x86_guest_base_index, guest_base);
334
- tcg_regset_set_reg(s->reserved_regs, x86_guest_base_index);
335
+ x86_guest_base.index = TCG_REG_R12;
336
+ tcg_out_movi(s, TCG_TYPE_PTR, x86_guest_base.index, guest_base);
337
+ tcg_regset_set_reg(s->reserved_regs, x86_guest_base.index);
338
}
339
}
340
# endif
341
--
342
2.34.1
343
344
diff view generated by jsdifflib
New patch
[PULL 22/42] tcg/i386: Drop r0+r1 local variables from tcg_out_tlb_load
1
Use TCG_REG_L[01] constants directly.
1
2
3
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
---
6
tcg/i386/tcg-target.c.inc | 32 ++++++++++++++++----------------
7
1 file changed, 16 insertions(+), 16 deletions(-)
8
9
diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
10
index XXXXXXX..XXXXXXX 100644
11
--- a/tcg/i386/tcg-target.c.inc
12
+++ b/tcg/i386/tcg-target.c.inc
13
@@ -XXX,XX +XXX,XX @@ static inline void tcg_out_tlb_load(TCGContext *s, TCGReg addrlo, TCGReg addrhi,
14
int mem_index, MemOp opc,
15
tcg_insn_unit **label_ptr, int which)
16
{
17
- const TCGReg r0 = TCG_REG_L0;
18
- const TCGReg r1 = TCG_REG_L1;
19
TCGType ttype = TCG_TYPE_I32;
20
TCGType tlbtype = TCG_TYPE_I32;
21
int trexw = 0, hrexw = 0, tlbrexw = 0;
22
@@ -XXX,XX +XXX,XX @@ static inline void tcg_out_tlb_load(TCGContext *s, TCGReg addrlo, TCGReg addrhi,
23
}
24
}
25
26
- tcg_out_mov(s, tlbtype, r0, addrlo);
27
- tcg_out_shifti(s, SHIFT_SHR + tlbrexw, r0,
28
+ tcg_out_mov(s, tlbtype, TCG_REG_L0, addrlo);
29
+ tcg_out_shifti(s, SHIFT_SHR + tlbrexw, TCG_REG_L0,
30
TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS);
31
32
- tcg_out_modrm_offset(s, OPC_AND_GvEv + trexw, r0, TCG_AREG0,
33
+ tcg_out_modrm_offset(s, OPC_AND_GvEv + trexw, TCG_REG_L0, TCG_AREG0,
34
TLB_MASK_TABLE_OFS(mem_index) +
35
offsetof(CPUTLBDescFast, mask));
36
37
- tcg_out_modrm_offset(s, OPC_ADD_GvEv + hrexw, r0, TCG_AREG0,
38
+ tcg_out_modrm_offset(s, OPC_ADD_GvEv + hrexw, TCG_REG_L0, TCG_AREG0,
39
TLB_MASK_TABLE_OFS(mem_index) +
40
offsetof(CPUTLBDescFast, table));
41
42
@@ -XXX,XX +XXX,XX @@ static inline void tcg_out_tlb_load(TCGContext *s, TCGReg addrlo, TCGReg addrhi,
43
copy the address and mask. For lesser alignments, check that we don't
44
cross pages for the complete access. */
45
if (a_bits >= s_bits) {
46
- tcg_out_mov(s, ttype, r1, addrlo);
47
+ tcg_out_mov(s, ttype, TCG_REG_L1, addrlo);
48
} else {
49
- tcg_out_modrm_offset(s, OPC_LEA + trexw, r1, addrlo, s_mask - a_mask);
50
+ tcg_out_modrm_offset(s, OPC_LEA + trexw, TCG_REG_L1,
51
+ addrlo, s_mask - a_mask);
52
}
53
tlb_mask = (target_ulong)TARGET_PAGE_MASK | a_mask;
54
- tgen_arithi(s, ARITH_AND + trexw, r1, tlb_mask, 0);
55
+ tgen_arithi(s, ARITH_AND + trexw, TCG_REG_L1, tlb_mask, 0);
56
57
- /* cmp 0(r0), r1 */
58
- tcg_out_modrm_offset(s, OPC_CMP_GvEv + trexw, r1, r0, which);
59
+ /* cmp 0(TCG_REG_L0), TCG_REG_L1 */
60
+ tcg_out_modrm_offset(s, OPC_CMP_GvEv + trexw,
61
+ TCG_REG_L1, TCG_REG_L0, which);
62
63
/* Prepare for both the fast path add of the tlb addend, and the slow
64
path function argument setup. */
65
- tcg_out_mov(s, ttype, r1, addrlo);
66
+ tcg_out_mov(s, ttype, TCG_REG_L1, addrlo);
67
68
/* jne slow_path */
69
tcg_out_opc(s, OPC_JCC_long + JCC_JNE, 0, 0, 0);
70
@@ -XXX,XX +XXX,XX @@ static inline void tcg_out_tlb_load(TCGContext *s, TCGReg addrlo, TCGReg addrhi,
71
s->code_ptr += 4;
72
73
if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) {
74
- /* cmp 4(r0), addrhi */
75
- tcg_out_modrm_offset(s, OPC_CMP_GvEv, addrhi, r0, which + 4);
76
+ /* cmp 4(TCG_REG_L0), addrhi */
77
+ tcg_out_modrm_offset(s, OPC_CMP_GvEv, addrhi, TCG_REG_L0, which + 4);
78
79
/* jne slow_path */
80
tcg_out_opc(s, OPC_JCC_long + JCC_JNE, 0, 0, 0);
81
@@ -XXX,XX +XXX,XX @@ static inline void tcg_out_tlb_load(TCGContext *s, TCGReg addrlo, TCGReg addrhi,
82
83
/* TLB Hit. */
84
85
- /* add addend(r0), r1 */
86
- tcg_out_modrm_offset(s, OPC_ADD_GvEv + hrexw, r1, r0,
87
+ /* add addend(TCG_REG_L0), TCG_REG_L1 */
88
+ tcg_out_modrm_offset(s, OPC_ADD_GvEv + hrexw, TCG_REG_L1, TCG_REG_L0,
89
offsetof(CPUTLBEntry, addend));
90
}
91
92
--
93
2.34.1
94
95
diff view generated by jsdifflib
New patch
[PULL 23/42] tcg/i386: Introduce tcg_out_testi
1
Split out a helper for choosing testb vs testl.
1
2
3
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
---
6
tcg/i386/tcg-target.c.inc | 30 ++++++++++++++++++------------
7
1 file changed, 18 insertions(+), 12 deletions(-)
8
9
diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
10
index XXXXXXX..XXXXXXX 100644
11
--- a/tcg/i386/tcg-target.c.inc
12
+++ b/tcg/i386/tcg-target.c.inc
13
@@ -XXX,XX +XXX,XX @@ static void tcg_out_nopn(TCGContext *s, int n)
14
tcg_out8(s, 0x90);
15
}
16
17
+/* Test register R vs immediate bits I, setting Z flag for EQ/NE. */
18
+static void __attribute__((unused))
19
+tcg_out_testi(TCGContext *s, TCGReg r, uint32_t i)
20
+{
21
+ /*
22
+ * This is used for testing alignment, so we can usually use testb.
23
+ * For i686, we have to use testl for %esi/%edi.
24
+ */
25
+ if (i <= 0xff && (TCG_TARGET_REG_BITS == 64 || r < 4)) {
26
+ tcg_out_modrm(s, OPC_GRP3_Eb | P_REXB_RM, EXT3_TESTi, r);
27
+ tcg_out8(s, i);
28
+ } else {
29
+ tcg_out_modrm(s, OPC_GRP3_Ev, EXT3_TESTi, r);
30
+ tcg_out32(s, i);
31
+ }
32
+}
33
+
34
typedef struct {
35
TCGReg base;
36
int index;
37
@@ -XXX,XX +XXX,XX @@ static void tcg_out_test_alignment(TCGContext *s, bool is_ld, TCGReg addrlo,
38
unsigned a_mask = (1 << a_bits) - 1;
39
TCGLabelQemuLdst *label;
40
41
- /*
42
- * We are expecting a_bits to max out at 7, so we can usually use testb.
43
- * For i686, we have to use testl for %esi/%edi.
44
- */
45
- if (a_mask <= 0xff && (TCG_TARGET_REG_BITS == 64 || addrlo < 4)) {
46
- tcg_out_modrm(s, OPC_GRP3_Eb | P_REXB_RM, EXT3_TESTi, addrlo);
47
- tcg_out8(s, a_mask);
48
- } else {
49
- tcg_out_modrm(s, OPC_GRP3_Ev, EXT3_TESTi, addrlo);
50
- tcg_out32(s, a_mask);
51
- }
52
-
53
+ tcg_out_testi(s, addrlo, a_mask);
54
/* jne slow_path */
55
tcg_out_opc(s, OPC_JCC_long + JCC_JNE, 0, 0, 0);
56
57
--
58
2.34.1
59
60
diff view generated by jsdifflib
New patch
[PULL 24/42] tcg/aarch64: Rationalize args to tcg_out_qemu_{ld,st}
1
Rename the 'ext' parameter 'data_type' to make the use clearer;
2
pass it to tcg_out_qemu_st as well to even out the interfaces.
3
Rename the 'otype' local 'addr_type' to make the use clearer.
1
4
5
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
---
8
tcg/aarch64/tcg-target.c.inc | 36 +++++++++++++++++-------------------
9
1 file changed, 17 insertions(+), 19 deletions(-)
10
11
diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc
12
index XXXXXXX..XXXXXXX 100644
13
--- a/tcg/aarch64/tcg-target.c.inc
14
+++ b/tcg/aarch64/tcg-target.c.inc
15
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_st_direct(TCGContext *s, MemOp memop,
16
}
17
18
static void tcg_out_qemu_ld(TCGContext *s, TCGReg data_reg, TCGReg addr_reg,
19
- MemOpIdx oi, TCGType ext)
20
+ MemOpIdx oi, TCGType data_type)
21
{
22
MemOp memop = get_memop(oi);
23
- const TCGType otype = TARGET_LONG_BITS == 64 ? TCG_TYPE_I64 : TCG_TYPE_I32;
24
+ TCGType addr_type = TARGET_LONG_BITS == 64 ? TCG_TYPE_I64 : TCG_TYPE_I32;
25
26
/* Byte swapping is left to middle-end expansion. */
27
tcg_debug_assert((memop & MO_BSWAP) == 0);
28
29
#ifdef CONFIG_SOFTMMU
30
- unsigned mem_index = get_mmuidx(oi);
31
tcg_insn_unit *label_ptr;
32
33
- tcg_out_tlb_read(s, addr_reg, memop, &label_ptr, mem_index, 1);
34
- tcg_out_qemu_ld_direct(s, memop, ext, data_reg,
35
- TCG_REG_X1, otype, addr_reg);
36
- add_qemu_ldst_label(s, true, oi, ext, data_reg, addr_reg,
37
+ tcg_out_tlb_read(s, addr_reg, memop, &label_ptr, get_mmuidx(oi), 1);
38
+ tcg_out_qemu_ld_direct(s, memop, data_type, data_reg,
39
+ TCG_REG_X1, addr_type, addr_reg);
40
+ add_qemu_ldst_label(s, true, oi, data_type, data_reg, addr_reg,
41
s->code_ptr, label_ptr);
42
#else /* !CONFIG_SOFTMMU */
43
unsigned a_bits = get_alignment_bits(memop);
44
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg data_reg, TCGReg addr_reg,
45
tcg_out_test_alignment(s, true, addr_reg, a_bits);
46
}
47
if (USE_GUEST_BASE) {
48
- tcg_out_qemu_ld_direct(s, memop, ext, data_reg,
49
- TCG_REG_GUEST_BASE, otype, addr_reg);
50
+ tcg_out_qemu_ld_direct(s, memop, data_type, data_reg,
51
+ TCG_REG_GUEST_BASE, addr_type, addr_reg);
52
} else {
53
- tcg_out_qemu_ld_direct(s, memop, ext, data_reg,
54
+ tcg_out_qemu_ld_direct(s, memop, data_type, data_reg,
55
addr_reg, TCG_TYPE_I64, TCG_REG_XZR);
56
}
57
#endif /* CONFIG_SOFTMMU */
58
}
59
60
static void tcg_out_qemu_st(TCGContext *s, TCGReg data_reg, TCGReg addr_reg,
61
- MemOpIdx oi)
62
+ MemOpIdx oi, TCGType data_type)
63
{
64
MemOp memop = get_memop(oi);
65
- const TCGType otype = TARGET_LONG_BITS == 64 ? TCG_TYPE_I64 : TCG_TYPE_I32;
66
+ TCGType addr_type = TARGET_LONG_BITS == 64 ? TCG_TYPE_I64 : TCG_TYPE_I32;
67
68
/* Byte swapping is left to middle-end expansion. */
69
tcg_debug_assert((memop & MO_BSWAP) == 0);
70
71
#ifdef CONFIG_SOFTMMU
72
- unsigned mem_index = get_mmuidx(oi);
73
tcg_insn_unit *label_ptr;
74
75
- tcg_out_tlb_read(s, addr_reg, memop, &label_ptr, mem_index, 0);
76
+ tcg_out_tlb_read(s, addr_reg, memop, &label_ptr, get_mmuidx(oi), 0);
77
tcg_out_qemu_st_direct(s, memop, data_reg,
78
- TCG_REG_X1, otype, addr_reg);
79
- add_qemu_ldst_label(s, false, oi, (memop & MO_SIZE)== MO_64,
80
- data_reg, addr_reg, s->code_ptr, label_ptr);
81
+ TCG_REG_X1, addr_type, addr_reg);
82
+ add_qemu_ldst_label(s, false, oi, data_type, data_reg, addr_reg,
83
+ s->code_ptr, label_ptr);
84
#else /* !CONFIG_SOFTMMU */
85
unsigned a_bits = get_alignment_bits(memop);
86
if (a_bits) {
87
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg data_reg, TCGReg addr_reg,
88
}
89
if (USE_GUEST_BASE) {
90
tcg_out_qemu_st_direct(s, memop, data_reg,
91
- TCG_REG_GUEST_BASE, otype, addr_reg);
92
+ TCG_REG_GUEST_BASE, addr_type, addr_reg);
93
} else {
94
tcg_out_qemu_st_direct(s, memop, data_reg,
95
addr_reg, TCG_TYPE_I64, TCG_REG_XZR);
96
@@ -XXX,XX +XXX,XX @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
97
break;
98
case INDEX_op_qemu_st_i32:
99
case INDEX_op_qemu_st_i64:
100
- tcg_out_qemu_st(s, REG0(0), a1, a2);
101
+ tcg_out_qemu_st(s, REG0(0), a1, a2, ext);
102
break;
103
104
case INDEX_op_bswap64_i64:
105
--
106
2.34.1
107
108
diff view generated by jsdifflib
New patch
[PULL 25/42] tcg/aarch64: Introduce HostAddress
1
Collect the 3 potential parts of the host address into a struct.
2
Reorg tcg_out_qemu_{ld,st}_direct to use it.
1
3
4
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
---
7
tcg/aarch64/tcg-target.c.inc | 86 +++++++++++++++++++++++++-----------
8
1 file changed, 59 insertions(+), 27 deletions(-)
9
10
diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc
11
index XXXXXXX..XXXXXXX 100644
12
--- a/tcg/aarch64/tcg-target.c.inc
13
+++ b/tcg/aarch64/tcg-target.c.inc
14
@@ -XXX,XX +XXX,XX @@ static void tcg_out_adr(TCGContext *s, TCGReg rd, const void *target)
15
tcg_out_insn(s, 3406, ADR, rd, offset);
16
}
17
18
+typedef struct {
19
+ TCGReg base;
20
+ TCGReg index;
21
+ TCGType index_ext;
22
+} HostAddress;
23
+
24
#ifdef CONFIG_SOFTMMU
25
/* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr,
26
* MemOpIdx oi, uintptr_t ra)
27
@@ -XXX,XX +XXX,XX @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
28
#endif /* CONFIG_SOFTMMU */
29
30
static void tcg_out_qemu_ld_direct(TCGContext *s, MemOp memop, TCGType ext,
31
- TCGReg data_r, TCGReg addr_r,
32
- TCGType otype, TCGReg off_r)
33
+ TCGReg data_r, HostAddress h)
34
{
35
switch (memop & MO_SSIZE) {
36
case MO_UB:
37
- tcg_out_ldst_r(s, I3312_LDRB, data_r, addr_r, otype, off_r);
38
+ tcg_out_ldst_r(s, I3312_LDRB, data_r, h.base, h.index_ext, h.index);
39
break;
40
case MO_SB:
41
tcg_out_ldst_r(s, ext ? I3312_LDRSBX : I3312_LDRSBW,
42
- data_r, addr_r, otype, off_r);
43
+ data_r, h.base, h.index_ext, h.index);
44
break;
45
case MO_UW:
46
- tcg_out_ldst_r(s, I3312_LDRH, data_r, addr_r, otype, off_r);
47
+ tcg_out_ldst_r(s, I3312_LDRH, data_r, h.base, h.index_ext, h.index);
48
break;
49
case MO_SW:
50
tcg_out_ldst_r(s, (ext ? I3312_LDRSHX : I3312_LDRSHW),
51
- data_r, addr_r, otype, off_r);
52
+ data_r, h.base, h.index_ext, h.index);
53
break;
54
case MO_UL:
55
- tcg_out_ldst_r(s, I3312_LDRW, data_r, addr_r, otype, off_r);
56
+ tcg_out_ldst_r(s, I3312_LDRW, data_r, h.base, h.index_ext, h.index);
57
break;
58
case MO_SL:
59
- tcg_out_ldst_r(s, I3312_LDRSWX, data_r, addr_r, otype, off_r);
60
+ tcg_out_ldst_r(s, I3312_LDRSWX, data_r, h.base, h.index_ext, h.index);
61
break;
62
case MO_UQ:
63
- tcg_out_ldst_r(s, I3312_LDRX, data_r, addr_r, otype, off_r);
64
+ tcg_out_ldst_r(s, I3312_LDRX, data_r, h.base, h.index_ext, h.index);
65
break;
66
default:
67
g_assert_not_reached();
68
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_ld_direct(TCGContext *s, MemOp memop, TCGType ext,
69
}
70
71
static void tcg_out_qemu_st_direct(TCGContext *s, MemOp memop,
72
- TCGReg data_r, TCGReg addr_r,
73
- TCGType otype, TCGReg off_r)
74
+ TCGReg data_r, HostAddress h)
75
{
76
switch (memop & MO_SIZE) {
77
case MO_8:
78
- tcg_out_ldst_r(s, I3312_STRB, data_r, addr_r, otype, off_r);
79
+ tcg_out_ldst_r(s, I3312_STRB, data_r, h.base, h.index_ext, h.index);
80
break;
81
case MO_16:
82
- tcg_out_ldst_r(s, I3312_STRH, data_r, addr_r, otype, off_r);
83
+ tcg_out_ldst_r(s, I3312_STRH, data_r, h.base, h.index_ext, h.index);
84
break;
85
case MO_32:
86
- tcg_out_ldst_r(s, I3312_STRW, data_r, addr_r, otype, off_r);
87
+ tcg_out_ldst_r(s, I3312_STRW, data_r, h.base, h.index_ext, h.index);
88
break;
89
case MO_64:
90
- tcg_out_ldst_r(s, I3312_STRX, data_r, addr_r, otype, off_r);
91
+ tcg_out_ldst_r(s, I3312_STRX, data_r, h.base, h.index_ext, h.index);
92
break;
93
default:
94
g_assert_not_reached();
95
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg data_reg, TCGReg addr_reg,
96
{
97
MemOp memop = get_memop(oi);
98
TCGType addr_type = TARGET_LONG_BITS == 64 ? TCG_TYPE_I64 : TCG_TYPE_I32;
99
+ HostAddress h;
100
101
/* Byte swapping is left to middle-end expansion. */
102
tcg_debug_assert((memop & MO_BSWAP) == 0);
103
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg data_reg, TCGReg addr_reg,
104
tcg_insn_unit *label_ptr;
105
106
tcg_out_tlb_read(s, addr_reg, memop, &label_ptr, get_mmuidx(oi), 1);
107
- tcg_out_qemu_ld_direct(s, memop, data_type, data_reg,
108
- TCG_REG_X1, addr_type, addr_reg);
109
+
110
+ h = (HostAddress){
111
+ .base = TCG_REG_X1,
112
+ .index = addr_reg,
113
+ .index_ext = addr_type
114
+ };
115
+ tcg_out_qemu_ld_direct(s, memop, data_type, data_reg, h);
116
+
117
add_qemu_ldst_label(s, true, oi, data_type, data_reg, addr_reg,
118
s->code_ptr, label_ptr);
119
#else /* !CONFIG_SOFTMMU */
120
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg data_reg, TCGReg addr_reg,
121
tcg_out_test_alignment(s, true, addr_reg, a_bits);
122
}
123
if (USE_GUEST_BASE) {
124
- tcg_out_qemu_ld_direct(s, memop, data_type, data_reg,
125
- TCG_REG_GUEST_BASE, addr_type, addr_reg);
126
+ h = (HostAddress){
127
+ .base = TCG_REG_GUEST_BASE,
128
+ .index = addr_reg,
129
+ .index_ext = addr_type
130
+ };
131
} else {
132
- tcg_out_qemu_ld_direct(s, memop, data_type, data_reg,
133
- addr_reg, TCG_TYPE_I64, TCG_REG_XZR);
134
+ h = (HostAddress){
135
+ .base = addr_reg,
136
+ .index = TCG_REG_XZR,
137
+ .index_ext = TCG_TYPE_I64
138
+ };
139
}
140
+ tcg_out_qemu_ld_direct(s, memop, data_type, data_reg, h);
141
#endif /* CONFIG_SOFTMMU */
142
}
143
144
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg data_reg, TCGReg addr_reg,
145
{
146
MemOp memop = get_memop(oi);
147
TCGType addr_type = TARGET_LONG_BITS == 64 ? TCG_TYPE_I64 : TCG_TYPE_I32;
148
+ HostAddress h;
149
150
/* Byte swapping is left to middle-end expansion. */
151
tcg_debug_assert((memop & MO_BSWAP) == 0);
152
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg data_reg, TCGReg addr_reg,
153
tcg_insn_unit *label_ptr;
154
155
tcg_out_tlb_read(s, addr_reg, memop, &label_ptr, get_mmuidx(oi), 0);
156
- tcg_out_qemu_st_direct(s, memop, data_reg,
157
- TCG_REG_X1, addr_type, addr_reg);
158
+
159
+ h = (HostAddress){
160
+ .base = TCG_REG_X1,
161
+ .index = addr_reg,
162
+ .index_ext = addr_type
163
+ };
164
+ tcg_out_qemu_st_direct(s, memop, data_reg, h);
165
+
166
add_qemu_ldst_label(s, false, oi, data_type, data_reg, addr_reg,
167
s->code_ptr, label_ptr);
168
#else /* !CONFIG_SOFTMMU */
169
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg data_reg, TCGReg addr_reg,
170
tcg_out_test_alignment(s, false, addr_reg, a_bits);
171
}
172
if (USE_GUEST_BASE) {
173
- tcg_out_qemu_st_direct(s, memop, data_reg,
174
- TCG_REG_GUEST_BASE, addr_type, addr_reg);
175
+ h = (HostAddress){
176
+ .base = TCG_REG_GUEST_BASE,
177
+ .index = addr_reg,
178
+ .index_ext = addr_type
179
+ };
180
} else {
181
- tcg_out_qemu_st_direct(s, memop, data_reg,
182
- addr_reg, TCG_TYPE_I64, TCG_REG_XZR);
183
+ h = (HostAddress){
184
+ .base = addr_reg,
185
+ .index = TCG_REG_XZR,
186
+ .index_ext = TCG_TYPE_I64
187
+ };
188
}
189
+ tcg_out_qemu_st_direct(s, memop, data_reg, h);
190
#endif /* CONFIG_SOFTMMU */
191
}
192
193
--
194
2.34.1
195
196
diff view generated by jsdifflib
New patch
[PULL 26/42] tcg/arm: Rationalize args to tcg_out_qemu_{ld,st}
1
Interpret the variable argument placement in the caller.
2
Pass data_type instead of is_64. We need to set this in
3
TCGLabelQemuLdst, so plumb this all the way through from tcg_out_op.
1
4
5
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
---
8
tcg/arm/tcg-target.c.inc | 113 +++++++++++++++++++--------------------
9
1 file changed, 56 insertions(+), 57 deletions(-)
10
11
diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
12
index XXXXXXX..XXXXXXX 100644
13
--- a/tcg/arm/tcg-target.c.inc
14
+++ b/tcg/arm/tcg-target.c.inc
15
@@ -XXX,XX +XXX,XX @@ static TCGReg tcg_out_tlb_read(TCGContext *s, TCGReg addrlo, TCGReg addrhi,
16
/* Record the context of a call to the out of line helper code for the slow
17
path for a load or store, so that we can later generate the correct
18
helper code. */
19
-static void add_qemu_ldst_label(TCGContext *s, bool is_ld, MemOpIdx oi,
20
- TCGReg datalo, TCGReg datahi, TCGReg addrlo,
21
- TCGReg addrhi, tcg_insn_unit *raddr,
22
+static void add_qemu_ldst_label(TCGContext *s, bool is_ld,
23
+ MemOpIdx oi, TCGType type,
24
+ TCGReg datalo, TCGReg datahi,
25
+ TCGReg addrlo, TCGReg addrhi,
26
+ tcg_insn_unit *raddr,
27
tcg_insn_unit *label_ptr)
28
{
29
TCGLabelQemuLdst *label = new_ldst_label(s);
30
31
label->is_ld = is_ld;
32
label->oi = oi;
33
+ label->type = type;
34
label->datalo_reg = datalo;
35
label->datahi_reg = datahi;
36
label->addrlo_reg = addrlo;
37
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_ld_direct(TCGContext *s, MemOp opc, TCGReg datalo,
38
}
39
#endif
40
41
-static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is64)
42
+static void tcg_out_qemu_ld(TCGContext *s, TCGReg datalo, TCGReg datahi,
43
+ TCGReg addrlo, TCGReg addrhi,
44
+ MemOpIdx oi, TCGType data_type)
45
{
46
- TCGReg addrlo, datalo, datahi, addrhi __attribute__((unused));
47
- MemOpIdx oi;
48
- MemOp opc;
49
-#ifdef CONFIG_SOFTMMU
50
- int mem_index;
51
- TCGReg addend;
52
- tcg_insn_unit *label_ptr;
53
-#else
54
- unsigned a_bits;
55
-#endif
56
-
57
- datalo = *args++;
58
- datahi = (is64 ? *args++ : 0);
59
- addrlo = *args++;
60
- addrhi = (TARGET_LONG_BITS == 64 ? *args++ : 0);
61
- oi = *args++;
62
- opc = get_memop(oi);
63
+ MemOp opc = get_memop(oi);
64
65
#ifdef CONFIG_SOFTMMU
66
- mem_index = get_mmuidx(oi);
67
- addend = tcg_out_tlb_read(s, addrlo, addrhi, opc, mem_index, 1);
68
+ TCGReg addend= tcg_out_tlb_read(s, addrlo, addrhi, opc, get_mmuidx(oi), 1);
69
70
- /* This a conditional BL only to load a pointer within this opcode into LR
71
- for the slow path. We will not be using the value for a tail call. */
72
- label_ptr = s->code_ptr;
73
+ /*
74
+ * This a conditional BL only to load a pointer within this opcode into
75
+ * LR for the slow path. We will not be using the value for a tail call.
76
+ */
77
+ tcg_insn_unit *label_ptr = s->code_ptr;
78
tcg_out_bl_imm(s, COND_NE, 0);
79
80
tcg_out_qemu_ld_index(s, opc, datalo, datahi, addrlo, addend, true);
81
82
- add_qemu_ldst_label(s, true, oi, datalo, datahi, addrlo, addrhi,
83
- s->code_ptr, label_ptr);
84
+ add_qemu_ldst_label(s, true, oi, data_type, datalo, datahi,
85
+ addrlo, addrhi, s->code_ptr, label_ptr);
86
#else /* !CONFIG_SOFTMMU */
87
- a_bits = get_alignment_bits(opc);
88
+ unsigned a_bits = get_alignment_bits(opc);
89
if (a_bits) {
90
tcg_out_test_alignment(s, true, addrlo, addrhi, a_bits);
91
}
92
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_st_direct(TCGContext *s, MemOp opc, TCGReg datalo,
93
}
94
#endif
95
96
-static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is64)
97
+static void tcg_out_qemu_st(TCGContext *s, TCGReg datalo, TCGReg datahi,
98
+ TCGReg addrlo, TCGReg addrhi,
99
+ MemOpIdx oi, TCGType data_type)
100
{
101
- TCGReg addrlo, datalo, datahi, addrhi __attribute__((unused));
102
- MemOpIdx oi;
103
- MemOp opc;
104
-#ifdef CONFIG_SOFTMMU
105
- int mem_index;
106
- TCGReg addend;
107
- tcg_insn_unit *label_ptr;
108
-#else
109
- unsigned a_bits;
110
-#endif
111
-
112
- datalo = *args++;
113
- datahi = (is64 ? *args++ : 0);
114
- addrlo = *args++;
115
- addrhi = (TARGET_LONG_BITS == 64 ? *args++ : 0);
116
- oi = *args++;
117
- opc = get_memop(oi);
118
+ MemOp opc = get_memop(oi);
119
120
#ifdef CONFIG_SOFTMMU
121
- mem_index = get_mmuidx(oi);
122
- addend = tcg_out_tlb_read(s, addrlo, addrhi, opc, mem_index, 0);
123
+ TCGReg addend = tcg_out_tlb_read(s, addrlo, addrhi, opc, get_mmuidx(oi), 0);
124
125
tcg_out_qemu_st_index(s, COND_EQ, opc, datalo, datahi,
126
addrlo, addend, true);
127
128
/* The conditional call must come last, as we're going to return here. */
129
- label_ptr = s->code_ptr;
130
+ tcg_insn_unit *label_ptr = s->code_ptr;
131
tcg_out_bl_imm(s, COND_NE, 0);
132
133
- add_qemu_ldst_label(s, false, oi, datalo, datahi, addrlo, addrhi,
134
- s->code_ptr, label_ptr);
135
+ add_qemu_ldst_label(s, false, oi, data_type, datalo, datahi,
136
+ addrlo, addrhi, s->code_ptr, label_ptr);
137
#else /* !CONFIG_SOFTMMU */
138
- a_bits = get_alignment_bits(opc);
139
+ unsigned a_bits = get_alignment_bits(opc);
140
if (a_bits) {
141
tcg_out_test_alignment(s, false, addrlo, addrhi, a_bits);
142
}
143
@@ -XXX,XX +XXX,XX @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
144
break;
145
146
case INDEX_op_qemu_ld_i32:
147
- tcg_out_qemu_ld(s, args, 0);
148
+ if (TARGET_LONG_BITS == 32) {
149
+ tcg_out_qemu_ld(s, args[0], -1, args[1], -1,
150
+ args[2], TCG_TYPE_I32);
151
+ } else {
152
+ tcg_out_qemu_ld(s, args[0], -1, args[1], args[2],
153
+ args[3], TCG_TYPE_I32);
154
+ }
155
break;
156
case INDEX_op_qemu_ld_i64:
157
- tcg_out_qemu_ld(s, args, 1);
158
+ if (TARGET_LONG_BITS == 32) {
159
+ tcg_out_qemu_ld(s, args[0], args[1], args[2], -1,
160
+ args[3], TCG_TYPE_I64);
161
+ } else {
162
+ tcg_out_qemu_ld(s, args[0], args[1], args[2], args[3],
163
+ args[4], TCG_TYPE_I64);
164
+ }
165
break;
166
case INDEX_op_qemu_st_i32:
167
- tcg_out_qemu_st(s, args, 0);
168
+ if (TARGET_LONG_BITS == 32) {
169
+ tcg_out_qemu_st(s, args[0], -1, args[1], -1,
170
+ args[2], TCG_TYPE_I32);
171
+ } else {
172
+ tcg_out_qemu_st(s, args[0], -1, args[1], args[2],
173
+ args[3], TCG_TYPE_I32);
174
+ }
175
break;
176
case INDEX_op_qemu_st_i64:
177
- tcg_out_qemu_st(s, args, 1);
178
+ if (TARGET_LONG_BITS == 32) {
179
+ tcg_out_qemu_st(s, args[0], args[1], args[2], -1,
180
+ args[3], TCG_TYPE_I64);
181
+ } else {
182
+ tcg_out_qemu_st(s, args[0], args[1], args[2], args[3],
183
+ args[4], TCG_TYPE_I64);
184
+ }
185
break;
186
187
case INDEX_op_bswap16_i32:
188
--
189
2.34.1
190
191
diff view generated by jsdifflib
New patch
[PULL 27/42] tcg/arm: Introduce HostAddress
1
Collect the parts of the host address, and condition, into a struct.
2
Merge tcg_out_qemu_*_{index,direct} and use it.
1
3
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
---
6
tcg/arm/tcg-target.c.inc | 248 ++++++++++++++++++---------------------
7
1 file changed, 115 insertions(+), 133 deletions(-)
8
9
diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
10
index XXXXXXX..XXXXXXX 100644
11
--- a/tcg/arm/tcg-target.c.inc
12
+++ b/tcg/arm/tcg-target.c.inc
13
@@ -XXX,XX +XXX,XX @@ static void tcg_out_vldst(TCGContext *s, ARMInsn insn,
14
tcg_out32(s, insn | (rn << 16) | encode_vd(rd) | 0xf);
15
}
16
17
+typedef struct {
18
+ ARMCond cond;
19
+ TCGReg base;
20
+ int index;
21
+ bool index_scratch;
22
+} HostAddress;
23
+
24
#ifdef CONFIG_SOFTMMU
25
/* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr,
26
* int mmu_idx, uintptr_t ra)
27
@@ -XXX,XX +XXX,XX @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
28
}
29
#endif /* SOFTMMU */
30
31
-static void tcg_out_qemu_ld_index(TCGContext *s, MemOp opc,
32
- TCGReg datalo, TCGReg datahi,
33
- TCGReg addrlo, TCGReg addend,
34
- bool scratch_addend)
35
+static void tcg_out_qemu_ld_direct(TCGContext *s, MemOp opc, TCGReg datalo,
36
+ TCGReg datahi, HostAddress h)
37
{
38
+ TCGReg base;
39
+
40
/* Byte swapping is left to middle-end expansion. */
41
tcg_debug_assert((opc & MO_BSWAP) == 0);
42
43
switch (opc & MO_SSIZE) {
44
case MO_UB:
45
- tcg_out_ld8_r(s, COND_AL, datalo, addrlo, addend);
46
+ if (h.index < 0) {
47
+ tcg_out_ld8_12(s, h.cond, datalo, h.base, 0);
48
+ } else {
49
+ tcg_out_ld8_r(s, h.cond, datalo, h.base, h.index);
50
+ }
51
break;
52
case MO_SB:
53
- tcg_out_ld8s_r(s, COND_AL, datalo, addrlo, addend);
54
+ if (h.index < 0) {
55
+ tcg_out_ld8s_8(s, h.cond, datalo, h.base, 0);
56
+ } else {
57
+ tcg_out_ld8s_r(s, h.cond, datalo, h.base, h.index);
58
+ }
59
break;
60
case MO_UW:
61
- tcg_out_ld16u_r(s, COND_AL, datalo, addrlo, addend);
62
+ if (h.index < 0) {
63
+ tcg_out_ld16u_8(s, h.cond, datalo, h.base, 0);
64
+ } else {
65
+ tcg_out_ld16u_r(s, h.cond, datalo, h.base, h.index);
66
+ }
67
break;
68
case MO_SW:
69
- tcg_out_ld16s_r(s, COND_AL, datalo, addrlo, addend);
70
+ if (h.index < 0) {
71
+ tcg_out_ld16s_8(s, h.cond, datalo, h.base, 0);
72
+ } else {
73
+ tcg_out_ld16s_r(s, h.cond, datalo, h.base, h.index);
74
+ }
75
break;
76
case MO_UL:
77
- tcg_out_ld32_r(s, COND_AL, datalo, addrlo, addend);
78
+ if (h.index < 0) {
79
+ tcg_out_ld32_12(s, h.cond, datalo, h.base, 0);
80
+ } else {
81
+ tcg_out_ld32_r(s, h.cond, datalo, h.base, h.index);
82
+ }
83
break;
84
case MO_UQ:
85
/* We used pair allocation for datalo, so already should be aligned. */
86
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_ld_index(TCGContext *s, MemOp opc,
87
tcg_debug_assert(datahi == datalo + 1);
88
/* LDRD requires alignment; double-check that. */
89
if (get_alignment_bits(opc) >= MO_64) {
90
+ if (h.index < 0) {
91
+ tcg_out_ldrd_8(s, h.cond, datalo, h.base, 0);
92
+ break;
93
+ }
94
/*
95
* Rm (the second address op) must not overlap Rt or Rt + 1.
96
* Since datalo is aligned, we can simplify the test via alignment.
97
* Flip the two address arguments if that works.
98
*/
99
- if ((addend & ~1) != datalo) {
100
- tcg_out_ldrd_r(s, COND_AL, datalo, addrlo, addend);
101
+ if ((h.index & ~1) != datalo) {
102
+ tcg_out_ldrd_r(s, h.cond, datalo, h.base, h.index);
103
break;
104
}
105
- if ((addrlo & ~1) != datalo) {
106
- tcg_out_ldrd_r(s, COND_AL, datalo, addend, addrlo);
107
+ if ((h.base & ~1) != datalo) {
108
+ tcg_out_ldrd_r(s, h.cond, datalo, h.index, h.base);
109
break;
110
}
111
}
112
- if (scratch_addend) {
113
- tcg_out_ld32_rwb(s, COND_AL, datalo, addend, addrlo);
114
- tcg_out_ld32_12(s, COND_AL, datahi, addend, 4);
115
+ if (h.index < 0) {
116
+ base = h.base;
117
+ if (datalo == h.base) {
118
+ tcg_out_mov_reg(s, h.cond, TCG_REG_TMP, base);
119
+ base = TCG_REG_TMP;
120
+ }
121
+ } else if (h.index_scratch) {
122
+ tcg_out_ld32_rwb(s, h.cond, datalo, h.index, h.base);
123
+ tcg_out_ld32_12(s, h.cond, datahi, h.index, 4);
124
+ break;
125
} else {
126
- tcg_out_dat_reg(s, COND_AL, ARITH_ADD, TCG_REG_TMP,
127
- addend, addrlo, SHIFT_IMM_LSL(0));
128
- tcg_out_ld32_12(s, COND_AL, datalo, TCG_REG_TMP, 0);
129
- tcg_out_ld32_12(s, COND_AL, datahi, TCG_REG_TMP, 4);
130
+ tcg_out_dat_reg(s, h.cond, ARITH_ADD, TCG_REG_TMP,
131
+ h.base, h.index, SHIFT_IMM_LSL(0));
132
+ base = TCG_REG_TMP;
133
}
134
+ tcg_out_ld32_12(s, h.cond, datalo, base, 0);
135
+ tcg_out_ld32_12(s, h.cond, datahi, base, 4);
136
break;
137
default:
138
g_assert_not_reached();
139
}
140
}
141
142
-#ifndef CONFIG_SOFTMMU
143
-static void tcg_out_qemu_ld_direct(TCGContext *s, MemOp opc, TCGReg datalo,
144
- TCGReg datahi, TCGReg addrlo)
145
-{
146
- /* Byte swapping is left to middle-end expansion. */
147
- tcg_debug_assert((opc & MO_BSWAP) == 0);
148
-
149
- switch (opc & MO_SSIZE) {
150
- case MO_UB:
151
- tcg_out_ld8_12(s, COND_AL, datalo, addrlo, 0);
152
- break;
153
- case MO_SB:
154
- tcg_out_ld8s_8(s, COND_AL, datalo, addrlo, 0);
155
- break;
156
- case MO_UW:
157
- tcg_out_ld16u_8(s, COND_AL, datalo, addrlo, 0);
158
- break;
159
- case MO_SW:
160
- tcg_out_ld16s_8(s, COND_AL, datalo, addrlo, 0);
161
- break;
162
- case MO_UL:
163
- tcg_out_ld32_12(s, COND_AL, datalo, addrlo, 0);
164
- break;
165
- case MO_UQ:
166
- /* We used pair allocation for datalo, so already should be aligned. */
167
- tcg_debug_assert((datalo & 1) == 0);
168
- tcg_debug_assert(datahi == datalo + 1);
169
- /* LDRD requires alignment; double-check that. */
170
- if (get_alignment_bits(opc) >= MO_64) {
171
- tcg_out_ldrd_8(s, COND_AL, datalo, addrlo, 0);
172
- } else if (datalo == addrlo) {
173
- tcg_out_ld32_12(s, COND_AL, datahi, addrlo, 4);
174
- tcg_out_ld32_12(s, COND_AL, datalo, addrlo, 0);
175
- } else {
176
- tcg_out_ld32_12(s, COND_AL, datalo, addrlo, 0);
177
- tcg_out_ld32_12(s, COND_AL, datahi, addrlo, 4);
178
- }
179
- break;
180
- default:
181
- g_assert_not_reached();
182
- }
183
-}
184
-#endif
185
-
186
static void tcg_out_qemu_ld(TCGContext *s, TCGReg datalo, TCGReg datahi,
187
TCGReg addrlo, TCGReg addrhi,
188
MemOpIdx oi, TCGType data_type)
189
{
190
MemOp opc = get_memop(oi);
191
+ HostAddress h;
192
193
#ifdef CONFIG_SOFTMMU
194
- TCGReg addend= tcg_out_tlb_read(s, addrlo, addrhi, opc, get_mmuidx(oi), 1);
195
+ h.cond = COND_AL;
196
+ h.base = addrlo;
197
+ h.index_scratch = true;
198
+ h.index = tcg_out_tlb_read(s, addrlo, addrhi, opc, get_mmuidx(oi), 1);
199
200
/*
201
* This a conditional BL only to load a pointer within this opcode into
202
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg datalo, TCGReg datahi,
203
tcg_insn_unit *label_ptr = s->code_ptr;
204
tcg_out_bl_imm(s, COND_NE, 0);
205
206
- tcg_out_qemu_ld_index(s, opc, datalo, datahi, addrlo, addend, true);
207
+ tcg_out_qemu_ld_direct(s, opc, datalo, datahi, h);
208
209
add_qemu_ldst_label(s, true, oi, data_type, datalo, datahi,
210
addrlo, addrhi, s->code_ptr, label_ptr);
211
-#else /* !CONFIG_SOFTMMU */
212
+#else
213
unsigned a_bits = get_alignment_bits(opc);
214
if (a_bits) {
215
tcg_out_test_alignment(s, true, addrlo, addrhi, a_bits);
216
}
217
- if (guest_base) {
218
- tcg_out_qemu_ld_index(s, opc, datalo, datahi,
219
- addrlo, TCG_REG_GUEST_BASE, false);
220
- } else {
221
- tcg_out_qemu_ld_direct(s, opc, datalo, datahi, addrlo);
222
- }
223
+
224
+ h.cond = COND_AL;
225
+ h.base = addrlo;
226
+ h.index = guest_base ? TCG_REG_GUEST_BASE : -1;
227
+ h.index_scratch = false;
228
+ tcg_out_qemu_ld_direct(s, opc, datalo, datahi, h);
229
#endif
230
}
231
232
-static void tcg_out_qemu_st_index(TCGContext *s, ARMCond cond, MemOp opc,
233
- TCGReg datalo, TCGReg datahi,
234
- TCGReg addrlo, TCGReg addend,
235
- bool scratch_addend)
236
-{
237
- /* Byte swapping is left to middle-end expansion. */
238
- tcg_debug_assert((opc & MO_BSWAP) == 0);
239
-
240
- switch (opc & MO_SIZE) {
241
- case MO_8:
242
- tcg_out_st8_r(s, cond, datalo, addrlo, addend);
243
- break;
244
- case MO_16:
245
- tcg_out_st16_r(s, cond, datalo, addrlo, addend);
246
- break;
247
- case MO_32:
248
- tcg_out_st32_r(s, cond, datalo, addrlo, addend);
249
- break;
250
- case MO_64:
251
- /* We used pair allocation for datalo, so already should be aligned. */
252
- tcg_debug_assert((datalo & 1) == 0);
253
- tcg_debug_assert(datahi == datalo + 1);
254
- /* STRD requires alignment; double-check that. */
255
- if (get_alignment_bits(opc) >= MO_64) {
256
- tcg_out_strd_r(s, cond, datalo, addrlo, addend);
257
- } else if (scratch_addend) {
258
- tcg_out_st32_rwb(s, cond, datalo, addend, addrlo);
259
- tcg_out_st32_12(s, cond, datahi, addend, 4);
260
- } else {
261
- tcg_out_dat_reg(s, cond, ARITH_ADD, TCG_REG_TMP,
262
- addend, addrlo, SHIFT_IMM_LSL(0));
263
- tcg_out_st32_12(s, cond, datalo, TCG_REG_TMP, 0);
264
- tcg_out_st32_12(s, cond, datahi, TCG_REG_TMP, 4);
265
- }
266
- break;
267
- default:
268
- g_assert_not_reached();
269
- }
270
-}
271
-
272
-#ifndef CONFIG_SOFTMMU
273
static void tcg_out_qemu_st_direct(TCGContext *s, MemOp opc, TCGReg datalo,
274
- TCGReg datahi, TCGReg addrlo)
275
+ TCGReg datahi, HostAddress h)
276
{
277
/* Byte swapping is left to middle-end expansion. */
278
tcg_debug_assert((opc & MO_BSWAP) == 0);
279
280
switch (opc & MO_SIZE) {
281
case MO_8:
282
- tcg_out_st8_12(s, COND_AL, datalo, addrlo, 0);
283
+ if (h.index < 0) {
284
+ tcg_out_st8_12(s, h.cond, datalo, h.base, 0);
285
+ } else {
286
+ tcg_out_st8_r(s, h.cond, datalo, h.base, h.index);
287
+ }
288
break;
289
case MO_16:
290
- tcg_out_st16_8(s, COND_AL, datalo, addrlo, 0);
291
+ if (h.index < 0) {
292
+ tcg_out_st16_8(s, h.cond, datalo, h.base, 0);
293
+ } else {
294
+ tcg_out_st16_r(s, h.cond, datalo, h.base, h.index);
295
+ }
296
break;
297
case MO_32:
298
- tcg_out_st32_12(s, COND_AL, datalo, addrlo, 0);
299
+ if (h.index < 0) {
300
+ tcg_out_st32_12(s, h.cond, datalo, h.base, 0);
301
+ } else {
302
+ tcg_out_st32_r(s, h.cond, datalo, h.base, h.index);
303
+ }
304
break;
305
case MO_64:
306
/* We used pair allocation for datalo, so already should be aligned. */
307
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_st_direct(TCGContext *s, MemOp opc, TCGReg datalo,
308
tcg_debug_assert(datahi == datalo + 1);
309
/* STRD requires alignment; double-check that. */
310
if (get_alignment_bits(opc) >= MO_64) {
311
- tcg_out_strd_8(s, COND_AL, datalo, addrlo, 0);
312
+ if (h.index < 0) {
313
+ tcg_out_strd_8(s, h.cond, datalo, h.base, 0);
314
+ } else {
315
+ tcg_out_strd_r(s, h.cond, datalo, h.base, h.index);
316
+ }
317
+ } else if (h.index_scratch) {
318
+ tcg_out_st32_rwb(s, h.cond, datalo, h.index, h.base);
319
+ tcg_out_st32_12(s, h.cond, datahi, h.index, 4);
320
} else {
321
- tcg_out_st32_12(s, COND_AL, datalo, addrlo, 0);
322
- tcg_out_st32_12(s, COND_AL, datahi, addrlo, 4);
323
+ tcg_out_dat_reg(s, h.cond, ARITH_ADD, TCG_REG_TMP,
324
+ h.base, h.index, SHIFT_IMM_LSL(0));
325
+ tcg_out_st32_12(s, h.cond, datalo, TCG_REG_TMP, 0);
326
+ tcg_out_st32_12(s, h.cond, datahi, TCG_REG_TMP, 4);
327
}
328
break;
329
default:
330
g_assert_not_reached();
331
}
332
}
333
-#endif
334
335
static void tcg_out_qemu_st(TCGContext *s, TCGReg datalo, TCGReg datahi,
336
TCGReg addrlo, TCGReg addrhi,
337
MemOpIdx oi, TCGType data_type)
338
{
339
MemOp opc = get_memop(oi);
340
+ HostAddress h;
341
342
#ifdef CONFIG_SOFTMMU
343
- TCGReg addend = tcg_out_tlb_read(s, addrlo, addrhi, opc, get_mmuidx(oi), 0);
344
-
345
- tcg_out_qemu_st_index(s, COND_EQ, opc, datalo, datahi,
346
- addrlo, addend, true);
347
+ h.cond = COND_EQ;
348
+ h.base = addrlo;
349
+ h.index_scratch = true;
350
+ h.index = tcg_out_tlb_read(s, addrlo, addrhi, opc, get_mmuidx(oi), 0);
351
+ tcg_out_qemu_st_direct(s, opc, datalo, datahi, h);
352
353
/* The conditional call must come last, as we're going to return here. */
354
tcg_insn_unit *label_ptr = s->code_ptr;
355
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg datalo, TCGReg datahi,
356
357
add_qemu_ldst_label(s, false, oi, data_type, datalo, datahi,
358
addrlo, addrhi, s->code_ptr, label_ptr);
359
-#else /* !CONFIG_SOFTMMU */
360
+#else
361
unsigned a_bits = get_alignment_bits(opc);
362
+
363
+ h.cond = COND_AL;
364
if (a_bits) {
365
tcg_out_test_alignment(s, false, addrlo, addrhi, a_bits);
366
+ h.cond = COND_EQ;
367
}
368
- if (guest_base) {
369
- tcg_out_qemu_st_index(s, COND_AL, opc, datalo, datahi,
370
- addrlo, TCG_REG_GUEST_BASE, false);
371
- } else {
372
- tcg_out_qemu_st_direct(s, opc, datalo, datahi, addrlo);
373
- }
374
+
375
+ h.base = addrlo;
376
+ h.index = guest_base ? TCG_REG_GUEST_BASE : -1;
377
+ h.index_scratch = false;
378
+ tcg_out_qemu_st_direct(s, opc, datalo, datahi, h);
379
#endif
380
}
381
382
--
383
2.34.1
diff view generated by jsdifflib
New patch
[PULL 28/42] tcg/loongarch64: Rationalize args to tcg_out_qemu_{ld, st}
1
Interpret the variable argument placement in the caller. Shift some
2
code around slightly to share more between softmmu and user-only.
1
3
4
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
---
7
tcg/loongarch64/tcg-target.c.inc | 100 +++++++++++++------------------
8
1 file changed, 42 insertions(+), 58 deletions(-)
9
10
diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc
11
index XXXXXXX..XXXXXXX 100644
12
--- a/tcg/loongarch64/tcg-target.c.inc
13
+++ b/tcg/loongarch64/tcg-target.c.inc
14
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_ld_indexed(TCGContext *s, TCGReg rd, TCGReg rj,
15
}
16
}
17
18
-static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, TCGType type)
19
+static void tcg_out_qemu_ld(TCGContext *s, TCGReg data_reg, TCGReg addr_reg,
20
+ MemOpIdx oi, TCGType data_type)
21
{
22
- TCGReg addr_regl;
23
- TCGReg data_regl;
24
- MemOpIdx oi;
25
- MemOp opc;
26
-#if defined(CONFIG_SOFTMMU)
27
+ MemOp opc = get_memop(oi);
28
+ TCGReg base, index;
29
+
30
+#ifdef CONFIG_SOFTMMU
31
tcg_insn_unit *label_ptr[1];
32
-#else
33
- unsigned a_bits;
34
-#endif
35
- TCGReg base;
36
37
- data_regl = *args++;
38
- addr_regl = *args++;
39
- oi = *args++;
40
- opc = get_memop(oi);
41
-
42
-#if defined(CONFIG_SOFTMMU)
43
- tcg_out_tlb_load(s, addr_regl, oi, label_ptr, 1);
44
- base = tcg_out_zext_addr_if_32_bit(s, addr_regl, TCG_REG_TMP0);
45
- tcg_out_qemu_ld_indexed(s, data_regl, base, TCG_REG_TMP2, opc, type);
46
- add_qemu_ldst_label(s, 1, oi, type,
47
- data_regl, addr_regl,
48
- s->code_ptr, label_ptr);
49
+ tcg_out_tlb_load(s, addr_reg, oi, label_ptr, 1);
50
+ index = TCG_REG_TMP2;
51
#else
52
- a_bits = get_alignment_bits(opc);
53
+ unsigned a_bits = get_alignment_bits(opc);
54
if (a_bits) {
55
- tcg_out_test_alignment(s, true, addr_regl, a_bits);
56
+ tcg_out_test_alignment(s, true, addr_reg, a_bits);
57
}
58
- base = tcg_out_zext_addr_if_32_bit(s, addr_regl, TCG_REG_TMP0);
59
- TCGReg guest_base_reg = USE_GUEST_BASE ? TCG_GUEST_BASE_REG : TCG_REG_ZERO;
60
- tcg_out_qemu_ld_indexed(s, data_regl, base, guest_base_reg, opc, type);
61
+ index = USE_GUEST_BASE ? TCG_GUEST_BASE_REG : TCG_REG_ZERO;
62
+#endif
63
+
64
+ base = tcg_out_zext_addr_if_32_bit(s, addr_reg, TCG_REG_TMP0);
65
+ tcg_out_qemu_ld_indexed(s, data_reg, base, index, opc, data_type);
66
+
67
+#ifdef CONFIG_SOFTMMU
68
+ add_qemu_ldst_label(s, true, oi, data_type, data_reg, addr_reg,
69
+ s->code_ptr, label_ptr);
70
#endif
71
}
72
73
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_st_indexed(TCGContext *s, TCGReg data,
74
}
75
}
76
77
-static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, TCGType type)
78
+static void tcg_out_qemu_st(TCGContext *s, TCGReg data_reg, TCGReg addr_reg,
79
+ MemOpIdx oi, TCGType data_type)
80
{
81
- TCGReg addr_regl;
82
- TCGReg data_regl;
83
- MemOpIdx oi;
84
- MemOp opc;
85
-#if defined(CONFIG_SOFTMMU)
86
+ MemOp opc = get_memop(oi);
87
+ TCGReg base, index;
88
+
89
+#ifdef CONFIG_SOFTMMU
90
tcg_insn_unit *label_ptr[1];
91
-#else
92
- unsigned a_bits;
93
-#endif
94
- TCGReg base;
95
96
- data_regl = *args++;
97
- addr_regl = *args++;
98
- oi = *args++;
99
- opc = get_memop(oi);
100
-
101
-#if defined(CONFIG_SOFTMMU)
102
- tcg_out_tlb_load(s, addr_regl, oi, label_ptr, 0);
103
- base = tcg_out_zext_addr_if_32_bit(s, addr_regl, TCG_REG_TMP0);
104
- tcg_out_qemu_st_indexed(s, data_regl, base, TCG_REG_TMP2, opc);
105
- add_qemu_ldst_label(s, 0, oi, type,
106
- data_regl, addr_regl,
107
- s->code_ptr, label_ptr);
108
+ tcg_out_tlb_load(s, addr_reg, oi, label_ptr, 0);
109
+ index = TCG_REG_TMP2;
110
#else
111
- a_bits = get_alignment_bits(opc);
112
+ unsigned a_bits = get_alignment_bits(opc);
113
if (a_bits) {
114
- tcg_out_test_alignment(s, false, addr_regl, a_bits);
115
+ tcg_out_test_alignment(s, false, addr_reg, a_bits);
116
}
117
- base = tcg_out_zext_addr_if_32_bit(s, addr_regl, TCG_REG_TMP0);
118
- TCGReg guest_base_reg = USE_GUEST_BASE ? TCG_GUEST_BASE_REG : TCG_REG_ZERO;
119
- tcg_out_qemu_st_indexed(s, data_regl, base, guest_base_reg, opc);
120
+ index = USE_GUEST_BASE ? TCG_GUEST_BASE_REG : TCG_REG_ZERO;
121
+#endif
122
+
123
+ base = tcg_out_zext_addr_if_32_bit(s, addr_reg, TCG_REG_TMP0);
124
+ tcg_out_qemu_st_indexed(s, data_reg, base, index, opc);
125
+
126
+#ifdef CONFIG_SOFTMMU
127
+ add_qemu_ldst_label(s, false, oi, data_type, data_reg, addr_reg,
128
+ s->code_ptr, label_ptr);
129
#endif
130
}
131
132
@@ -XXX,XX +XXX,XX @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
133
break;
134
135
case INDEX_op_qemu_ld_i32:
136
- tcg_out_qemu_ld(s, args, TCG_TYPE_I32);
137
+ tcg_out_qemu_ld(s, a0, a1, a2, TCG_TYPE_I32);
138
break;
139
case INDEX_op_qemu_ld_i64:
140
- tcg_out_qemu_ld(s, args, TCG_TYPE_I64);
141
+ tcg_out_qemu_ld(s, a0, a1, a2, TCG_TYPE_I64);
142
break;
143
case INDEX_op_qemu_st_i32:
144
- tcg_out_qemu_st(s, args, TCG_TYPE_I32);
145
+ tcg_out_qemu_st(s, a0, a1, a2, TCG_TYPE_I32);
146
break;
147
case INDEX_op_qemu_st_i64:
148
- tcg_out_qemu_st(s, args, TCG_TYPE_I64);
149
+ tcg_out_qemu_st(s, a0, a1, a2, TCG_TYPE_I64);
150
break;
151
152
case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
153
--
154
2.34.1
155
156
diff view generated by jsdifflib
New patch
[PULL 29/42] tcg/loongarch64: Introduce HostAddress
1
Collect the 2 parts of the host address into a struct.
2
Reorg tcg_out_qemu_{ld,st}_direct to use it.
1
3
4
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
---
7
tcg/loongarch64/tcg-target.c.inc | 55 +++++++++++++++++---------------
8
1 file changed, 30 insertions(+), 25 deletions(-)
9
10
diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc
11
index XXXXXXX..XXXXXXX 100644
12
--- a/tcg/loongarch64/tcg-target.c.inc
13
+++ b/tcg/loongarch64/tcg-target.c.inc
14
@@ -XXX,XX +XXX,XX @@ static TCGReg tcg_out_zext_addr_if_32_bit(TCGContext *s,
15
return addr;
16
}
17
18
-static void tcg_out_qemu_ld_indexed(TCGContext *s, TCGReg rd, TCGReg rj,
19
- TCGReg rk, MemOp opc, TCGType type)
20
+typedef struct {
21
+ TCGReg base;
22
+ TCGReg index;
23
+} HostAddress;
24
+
25
+static void tcg_out_qemu_ld_indexed(TCGContext *s, MemOp opc, TCGType type,
26
+ TCGReg rd, HostAddress h)
27
{
28
/* Byte swapping is left to middle-end expansion. */
29
tcg_debug_assert((opc & MO_BSWAP) == 0);
30
31
switch (opc & MO_SSIZE) {
32
case MO_UB:
33
- tcg_out_opc_ldx_bu(s, rd, rj, rk);
34
+ tcg_out_opc_ldx_bu(s, rd, h.base, h.index);
35
break;
36
case MO_SB:
37
- tcg_out_opc_ldx_b(s, rd, rj, rk);
38
+ tcg_out_opc_ldx_b(s, rd, h.base, h.index);
39
break;
40
case MO_UW:
41
- tcg_out_opc_ldx_hu(s, rd, rj, rk);
42
+ tcg_out_opc_ldx_hu(s, rd, h.base, h.index);
43
break;
44
case MO_SW:
45
- tcg_out_opc_ldx_h(s, rd, rj, rk);
46
+ tcg_out_opc_ldx_h(s, rd, h.base, h.index);
47
break;
48
case MO_UL:
49
if (type == TCG_TYPE_I64) {
50
- tcg_out_opc_ldx_wu(s, rd, rj, rk);
51
+ tcg_out_opc_ldx_wu(s, rd, h.base, h.index);
52
break;
53
}
54
/* fallthrough */
55
case MO_SL:
56
- tcg_out_opc_ldx_w(s, rd, rj, rk);
57
+ tcg_out_opc_ldx_w(s, rd, h.base, h.index);
58
break;
59
case MO_UQ:
60
- tcg_out_opc_ldx_d(s, rd, rj, rk);
61
+ tcg_out_opc_ldx_d(s, rd, h.base, h.index);
62
break;
63
default:
64
g_assert_not_reached();
65
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg data_reg, TCGReg addr_reg,
66
MemOpIdx oi, TCGType data_type)
67
{
68
MemOp opc = get_memop(oi);
69
- TCGReg base, index;
70
+ HostAddress h;
71
72
#ifdef CONFIG_SOFTMMU
73
tcg_insn_unit *label_ptr[1];
74
75
tcg_out_tlb_load(s, addr_reg, oi, label_ptr, 1);
76
- index = TCG_REG_TMP2;
77
+ h.index = TCG_REG_TMP2;
78
#else
79
unsigned a_bits = get_alignment_bits(opc);
80
if (a_bits) {
81
tcg_out_test_alignment(s, true, addr_reg, a_bits);
82
}
83
- index = USE_GUEST_BASE ? TCG_GUEST_BASE_REG : TCG_REG_ZERO;
84
+ h.index = USE_GUEST_BASE ? TCG_GUEST_BASE_REG : TCG_REG_ZERO;
85
#endif
86
87
- base = tcg_out_zext_addr_if_32_bit(s, addr_reg, TCG_REG_TMP0);
88
- tcg_out_qemu_ld_indexed(s, data_reg, base, index, opc, data_type);
89
+ h.base = tcg_out_zext_addr_if_32_bit(s, addr_reg, TCG_REG_TMP0);
90
+ tcg_out_qemu_ld_indexed(s, opc, data_type, data_reg, h);
91
92
#ifdef CONFIG_SOFTMMU
93
add_qemu_ldst_label(s, true, oi, data_type, data_reg, addr_reg,
94
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg data_reg, TCGReg addr_reg,
95
#endif
96
}
97
98
-static void tcg_out_qemu_st_indexed(TCGContext *s, TCGReg data,
99
- TCGReg rj, TCGReg rk, MemOp opc)
100
+static void tcg_out_qemu_st_indexed(TCGContext *s, MemOp opc,
101
+ TCGReg rd, HostAddress h)
102
{
103
/* Byte swapping is left to middle-end expansion. */
104
tcg_debug_assert((opc & MO_BSWAP) == 0);
105
106
switch (opc & MO_SIZE) {
107
case MO_8:
108
- tcg_out_opc_stx_b(s, data, rj, rk);
109
+ tcg_out_opc_stx_b(s, rd, h.base, h.index);
110
break;
111
case MO_16:
112
- tcg_out_opc_stx_h(s, data, rj, rk);
113
+ tcg_out_opc_stx_h(s, rd, h.base, h.index);
114
break;
115
case MO_32:
116
- tcg_out_opc_stx_w(s, data, rj, rk);
117
+ tcg_out_opc_stx_w(s, rd, h.base, h.index);
118
break;
119
case MO_64:
120
- tcg_out_opc_stx_d(s, data, rj, rk);
121
+ tcg_out_opc_stx_d(s, rd, h.base, h.index);
122
break;
123
default:
124
g_assert_not_reached();
125
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg data_reg, TCGReg addr_reg,
126
MemOpIdx oi, TCGType data_type)
127
{
128
MemOp opc = get_memop(oi);
129
- TCGReg base, index;
130
+ HostAddress h;
131
132
#ifdef CONFIG_SOFTMMU
133
tcg_insn_unit *label_ptr[1];
134
135
tcg_out_tlb_load(s, addr_reg, oi, label_ptr, 0);
136
- index = TCG_REG_TMP2;
137
+ h.index = TCG_REG_TMP2;
138
#else
139
unsigned a_bits = get_alignment_bits(opc);
140
if (a_bits) {
141
tcg_out_test_alignment(s, false, addr_reg, a_bits);
142
}
143
- index = USE_GUEST_BASE ? TCG_GUEST_BASE_REG : TCG_REG_ZERO;
144
+ h.index = USE_GUEST_BASE ? TCG_GUEST_BASE_REG : TCG_REG_ZERO;
145
#endif
146
147
- base = tcg_out_zext_addr_if_32_bit(s, addr_reg, TCG_REG_TMP0);
148
- tcg_out_qemu_st_indexed(s, data_reg, base, index, opc);
149
+ h.base = tcg_out_zext_addr_if_32_bit(s, addr_reg, TCG_REG_TMP0);
150
+ tcg_out_qemu_st_indexed(s, opc, data_reg, h);
151
152
#ifdef CONFIG_SOFTMMU
153
add_qemu_ldst_label(s, false, oi, data_type, data_reg, addr_reg,
154
--
155
2.34.1
156
157
diff view generated by jsdifflib
New patch
[PULL 30/42] tcg/mips: Rationalize args to tcg_out_qemu_{ld,st}
1
Interpret the variable argument placement in the caller. There are
2
several places where we already convert back from bool to type.
3
Clean things up by using type throughout.
1
4
5
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
---
8
tcg/mips/tcg-target.c.inc | 186 +++++++++++++++++++-------------------
9
1 file changed, 95 insertions(+), 91 deletions(-)
10
11
diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc
12
index XXXXXXX..XXXXXXX 100644
13
--- a/tcg/mips/tcg-target.c.inc
14
+++ b/tcg/mips/tcg-target.c.inc
15
@@ -XXX,XX +XXX,XX @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
16
#endif /* SOFTMMU */
17
18
static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg lo, TCGReg hi,
19
- TCGReg base, MemOp opc, bool is_64)
20
+ TCGReg base, MemOp opc, TCGType type)
21
{
22
switch (opc & (MO_SSIZE | MO_BSWAP)) {
23
case MO_UB:
24
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg lo, TCGReg hi,
25
tcg_out_opc_imm(s, OPC_LH, lo, base, 0);
26
break;
27
case MO_UL | MO_BSWAP:
28
- if (TCG_TARGET_REG_BITS == 64 && is_64) {
29
+ if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I64) {
30
if (use_mips32r2_instructions) {
31
tcg_out_opc_imm(s, OPC_LWU, lo, base, 0);
32
tcg_out_bswap32(s, lo, lo, TCG_BSWAP_IZ | TCG_BSWAP_OZ);
33
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg lo, TCGReg hi,
34
}
35
break;
36
case MO_UL:
37
- if (TCG_TARGET_REG_BITS == 64 && is_64) {
38
+ if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I64) {
39
tcg_out_opc_imm(s, OPC_LWU, lo, base, 0);
40
break;
41
}
42
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg lo, TCGReg hi,
43
}
44
45
static void tcg_out_qemu_ld_unalign(TCGContext *s, TCGReg lo, TCGReg hi,
46
- TCGReg base, MemOp opc, bool is_64)
47
+ TCGReg base, MemOp opc, TCGType type)
48
{
49
const MIPSInsn lw1 = MIPS_BE ? OPC_LWL : OPC_LWR;
50
const MIPSInsn lw2 = MIPS_BE ? OPC_LWR : OPC_LWL;
51
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_ld_unalign(TCGContext *s, TCGReg lo, TCGReg hi,
52
case MO_UL:
53
tcg_out_opc_imm(s, lw1, lo, base, 0);
54
tcg_out_opc_imm(s, lw2, lo, base, 3);
55
- if (TCG_TARGET_REG_BITS == 64 && is_64 && !sgn) {
56
+ if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I64 && !sgn) {
57
tcg_out_ext32u(s, lo, lo);
58
}
59
break;
60
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_ld_unalign(TCGContext *s, TCGReg lo, TCGReg hi,
61
tcg_out_opc_imm(s, lw1, lo, base, 0);
62
tcg_out_opc_imm(s, lw2, lo, base, 3);
63
tcg_out_bswap32(s, lo, lo,
64
- TCG_TARGET_REG_BITS == 64 && is_64
65
+ TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I64
66
? (sgn ? TCG_BSWAP_OS : TCG_BSWAP_OZ) : 0);
67
} else {
68
const tcg_insn_unit *subr =
69
- (TCG_TARGET_REG_BITS == 64 && is_64 && !sgn
70
+ (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I64 && !sgn
71
? bswap32u_addr : bswap32_addr);
72
73
tcg_out_opc_imm(s, lw1, TCG_TMP0, base, 0);
74
tcg_out_bswap_subr(s, subr);
75
/* delay slot */
76
tcg_out_opc_imm(s, lw2, TCG_TMP0, base, 3);
77
- tcg_out_mov(s, is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32, lo, TCG_TMP3);
78
+ tcg_out_mov(s, type, lo, TCG_TMP3);
79
}
80
break;
81
82
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_ld_unalign(TCGContext *s, TCGReg lo, TCGReg hi,
83
}
84
}
85
86
-static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64)
87
+static void tcg_out_qemu_ld(TCGContext *s, TCGReg datalo, TCGReg datahi,
88
+ TCGReg addrlo, TCGReg addrhi,
89
+ MemOpIdx oi, TCGType data_type)
90
{
91
- TCGReg addr_regl, addr_regh __attribute__((unused));
92
- TCGReg data_regl, data_regh;
93
- MemOpIdx oi;
94
- MemOp opc;
95
-#if defined(CONFIG_SOFTMMU)
96
- tcg_insn_unit *label_ptr[2];
97
-#else
98
-#endif
99
- unsigned a_bits, s_bits;
100
- TCGReg base = TCG_REG_A0;
101
-
102
- data_regl = *args++;
103
- data_regh = (TCG_TARGET_REG_BITS == 32 && is_64 ? *args++ : 0);
104
- addr_regl = *args++;
105
- addr_regh = (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0);
106
- oi = *args++;
107
- opc = get_memop(oi);
108
- a_bits = get_alignment_bits(opc);
109
- s_bits = opc & MO_SIZE;
110
+ MemOp opc = get_memop(oi);
111
+ unsigned a_bits = get_alignment_bits(opc);
112
+ unsigned s_bits = opc & MO_SIZE;
113
+ TCGReg base;
114
115
/*
116
* R6 removes the left/right instructions but requires the
117
* system to support misaligned memory accesses.
118
*/
119
#if defined(CONFIG_SOFTMMU)
120
- tcg_out_tlb_load(s, base, addr_regl, addr_regh, oi, label_ptr, 1);
121
+ tcg_insn_unit *label_ptr[2];
122
+
123
+ base = TCG_REG_A0;
124
+ tcg_out_tlb_load(s, base, addrlo, addrhi, oi, label_ptr, 1);
125
if (use_mips32r6_instructions || a_bits >= s_bits) {
126
- tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_64);
127
+ tcg_out_qemu_ld_direct(s, datalo, datahi, base, opc, data_type);
128
} else {
129
- tcg_out_qemu_ld_unalign(s, data_regl, data_regh, base, opc, is_64);
130
+ tcg_out_qemu_ld_unalign(s, datalo, datahi, base, opc, data_type);
131
}
132
- add_qemu_ldst_label(s, 1, oi,
133
- (is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32),
134
- data_regl, data_regh, addr_regl, addr_regh,
135
- s->code_ptr, label_ptr);
136
+ add_qemu_ldst_label(s, true, oi, data_type, datalo, datahi,
137
+ addrlo, addrhi, s->code_ptr, label_ptr);
138
#else
139
+ base = addrlo;
140
if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
141
- tcg_out_ext32u(s, base, addr_regl);
142
- addr_regl = base;
143
+ tcg_out_ext32u(s, TCG_REG_A0, base);
144
+ base = TCG_REG_A0;
145
}
146
- if (guest_base == 0 && data_regl != addr_regl) {
147
- base = addr_regl;
148
- } else if (guest_base == (int16_t)guest_base) {
149
- tcg_out_opc_imm(s, ALIAS_PADDI, base, addr_regl, guest_base);
150
- } else {
151
- tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_GUEST_BASE_REG, addr_regl);
152
+ if (guest_base) {
153
+ if (guest_base == (int16_t)guest_base) {
154
+ tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_A0, base, guest_base);
155
+ } else {
156
+ tcg_out_opc_reg(s, ALIAS_PADD, TCG_REG_A0, base,
157
+ TCG_GUEST_BASE_REG);
158
+ }
159
+ base = TCG_REG_A0;
160
}
161
if (use_mips32r6_instructions) {
162
if (a_bits) {
163
- tcg_out_test_alignment(s, true, addr_regl, addr_regh, a_bits);
164
+ tcg_out_test_alignment(s, true, addrlo, addrhi, a_bits);
165
}
166
- tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_64);
167
+ tcg_out_qemu_ld_direct(s, datalo, datahi, base, opc, data_type);
168
} else {
169
if (a_bits && a_bits != s_bits) {
170
- tcg_out_test_alignment(s, true, addr_regl, addr_regh, a_bits);
171
+ tcg_out_test_alignment(s, true, addrlo, addrhi, a_bits);
172
}
173
if (a_bits >= s_bits) {
174
- tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_64);
175
+ tcg_out_qemu_ld_direct(s, datalo, datahi, base, opc, data_type);
176
} else {
177
- tcg_out_qemu_ld_unalign(s, data_regl, data_regh, base, opc, is_64);
178
+ tcg_out_qemu_ld_unalign(s, datalo, datahi, base, opc, data_type);
179
}
180
}
181
#endif
182
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_st_unalign(TCGContext *s, TCGReg lo, TCGReg hi,
183
g_assert_not_reached();
184
}
185
}
186
-static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64)
187
-{
188
- TCGReg addr_regl, addr_regh __attribute__((unused));
189
- TCGReg data_regl, data_regh;
190
- MemOpIdx oi;
191
- MemOp opc;
192
-#if defined(CONFIG_SOFTMMU)
193
- tcg_insn_unit *label_ptr[2];
194
-#endif
195
- unsigned a_bits, s_bits;
196
- TCGReg base = TCG_REG_A0;
197
198
- data_regl = *args++;
199
- data_regh = (TCG_TARGET_REG_BITS == 32 && is_64 ? *args++ : 0);
200
- addr_regl = *args++;
201
- addr_regh = (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0);
202
- oi = *args++;
203
- opc = get_memop(oi);
204
- a_bits = get_alignment_bits(opc);
205
- s_bits = opc & MO_SIZE;
206
+static void tcg_out_qemu_st(TCGContext *s, TCGReg datalo, TCGReg datahi,
207
+ TCGReg addrlo, TCGReg addrhi,
208
+ MemOpIdx oi, TCGType data_type)
209
+{
210
+ MemOp opc = get_memop(oi);
211
+ unsigned a_bits = get_alignment_bits(opc);
212
+ unsigned s_bits = opc & MO_SIZE;
213
+ TCGReg base;
214
215
/*
216
* R6 removes the left/right instructions but requires the
217
* system to support misaligned memory accesses.
218
*/
219
#if defined(CONFIG_SOFTMMU)
220
- tcg_out_tlb_load(s, base, addr_regl, addr_regh, oi, label_ptr, 0);
221
+ tcg_insn_unit *label_ptr[2];
222
+
223
+ base = TCG_REG_A0;
224
+ tcg_out_tlb_load(s, base, addrlo, addrhi, oi, label_ptr, 0);
225
if (use_mips32r6_instructions || a_bits >= s_bits) {
226
- tcg_out_qemu_st_direct(s, data_regl, data_regh, base, opc);
227
+ tcg_out_qemu_st_direct(s, datalo, datahi, base, opc);
228
} else {
229
- tcg_out_qemu_st_unalign(s, data_regl, data_regh, base, opc);
230
+ tcg_out_qemu_st_unalign(s, datalo, datahi, base, opc);
231
}
232
- add_qemu_ldst_label(s, 0, oi,
233
- (is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32),
234
- data_regl, data_regh, addr_regl, addr_regh,
235
- s->code_ptr, label_ptr);
236
+ add_qemu_ldst_label(s, false, oi, data_type, datalo, datahi,
237
+ addrlo, addrhi, s->code_ptr, label_ptr);
238
#else
239
+ base = addrlo;
240
if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
241
- tcg_out_ext32u(s, base, addr_regl);
242
- addr_regl = base;
243
+ tcg_out_ext32u(s, TCG_REG_A0, base);
244
+ base = TCG_REG_A0;
245
}
246
- if (guest_base == 0) {
247
- base = addr_regl;
248
- } else if (guest_base == (int16_t)guest_base) {
249
- tcg_out_opc_imm(s, ALIAS_PADDI, base, addr_regl, guest_base);
250
- } else {
251
- tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_GUEST_BASE_REG, addr_regl);
252
+ if (guest_base) {
253
+ if (guest_base == (int16_t)guest_base) {
254
+ tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_A0, base, guest_base);
255
+ } else {
256
+ tcg_out_opc_reg(s, ALIAS_PADD, TCG_REG_A0, base,
257
+ TCG_GUEST_BASE_REG);
258
+ }
259
+ base = TCG_REG_A0;
260
}
261
if (use_mips32r6_instructions) {
262
if (a_bits) {
263
- tcg_out_test_alignment(s, true, addr_regl, addr_regh, a_bits);
264
+ tcg_out_test_alignment(s, true, addrlo, addrhi, a_bits);
265
}
266
- tcg_out_qemu_st_direct(s, data_regl, data_regh, base, opc);
267
+ tcg_out_qemu_st_direct(s, datalo, datahi, base, opc);
268
} else {
269
if (a_bits && a_bits != s_bits) {
270
- tcg_out_test_alignment(s, true, addr_regl, addr_regh, a_bits);
271
+ tcg_out_test_alignment(s, true, addrlo, addrhi, a_bits);
272
}
273
if (a_bits >= s_bits) {
274
- tcg_out_qemu_st_direct(s, data_regl, data_regh, base, opc);
275
+ tcg_out_qemu_st_direct(s, datalo, datahi, base, opc);
276
} else {
277
- tcg_out_qemu_st_unalign(s, data_regl, data_regh, base, opc);
278
+ tcg_out_qemu_st_unalign(s, datalo, datahi, base, opc);
279
}
280
}
281
#endif
282
@@ -XXX,XX +XXX,XX @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
283
break;
284
285
case INDEX_op_qemu_ld_i32:
286
- tcg_out_qemu_ld(s, args, false);
287
+ if (TCG_TARGET_REG_BITS >= TARGET_LONG_BITS) {
288
+ tcg_out_qemu_ld(s, a0, 0, a1, 0, a2, TCG_TYPE_I32);
289
+ } else {
290
+ tcg_out_qemu_ld(s, a0, 0, a1, a2, args[3], TCG_TYPE_I32);
291
+ }
292
break;
293
case INDEX_op_qemu_ld_i64:
294
- tcg_out_qemu_ld(s, args, true);
295
+ if (TCG_TARGET_REG_BITS == 64) {
296
+ tcg_out_qemu_ld(s, a0, 0, a1, 0, a2, TCG_TYPE_I64);
297
+ } else if (TARGET_LONG_BITS == 32) {
298
+ tcg_out_qemu_ld(s, a0, a1, a2, 0, args[3], TCG_TYPE_I64);
299
+ } else {
300
+ tcg_out_qemu_ld(s, a0, a1, a2, args[3], args[4], TCG_TYPE_I64);
301
+ }
302
break;
303
case INDEX_op_qemu_st_i32:
304
- tcg_out_qemu_st(s, args, false);
305
+ if (TCG_TARGET_REG_BITS >= TARGET_LONG_BITS) {
306
+ tcg_out_qemu_st(s, a0, 0, a1, 0, a2, TCG_TYPE_I32);
307
+ } else {
308
+ tcg_out_qemu_st(s, a0, 0, a1, a2, args[3], TCG_TYPE_I32);
309
+ }
310
break;
311
case INDEX_op_qemu_st_i64:
312
- tcg_out_qemu_st(s, args, true);
313
+ if (TCG_TARGET_REG_BITS == 64) {
314
+ tcg_out_qemu_st(s, a0, 0, a1, 0, a2, TCG_TYPE_I64);
315
+ } else if (TARGET_LONG_BITS == 32) {
316
+ tcg_out_qemu_st(s, a0, a1, a2, 0, args[3], TCG_TYPE_I64);
317
+ } else {
318
+ tcg_out_qemu_st(s, a0, a1, a2, args[3], args[4], TCG_TYPE_I64);
319
+ }
320
break;
321
322
case INDEX_op_add2_i32:
323
--
324
2.34.1
325
326
diff view generated by jsdifflib
New patch
[PULL 31/42] tcg/ppc: Rationalize args to tcg_out_qemu_{ld,st}
1
1
Interpret the variable argument placement in the caller. Pass data_type
2
instead of is64 -- there are several places where we already convert back
3
from bool to type. Clean things up by using type throughout.
4
5
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
6
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
---
9
tcg/ppc/tcg-target.c.inc | 110 +++++++++++++++++++++------------------
10
1 file changed, 59 insertions(+), 51 deletions(-)
11
12
diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc
13
index XXXXXXX..XXXXXXX 100644
14
--- a/tcg/ppc/tcg-target.c.inc
15
+++ b/tcg/ppc/tcg-target.c.inc
16
@@ -XXX,XX +XXX,XX @@ static TCGReg tcg_out_tlb_read(TCGContext *s, MemOp opc,
17
/* Record the context of a call to the out of line helper code for the slow
18
path for a load or store, so that we can later generate the correct
19
helper code. */
20
-static void add_qemu_ldst_label(TCGContext *s, bool is_ld, MemOpIdx oi,
21
+static void add_qemu_ldst_label(TCGContext *s, bool is_ld,
22
+ TCGType type, MemOpIdx oi,
23
TCGReg datalo_reg, TCGReg datahi_reg,
24
TCGReg addrlo_reg, TCGReg addrhi_reg,
25
tcg_insn_unit *raddr, tcg_insn_unit *lptr)
26
@@ -XXX,XX +XXX,XX @@ static void add_qemu_ldst_label(TCGContext *s, bool is_ld, MemOpIdx oi,
27
TCGLabelQemuLdst *label = new_ldst_label(s);
28
29
label->is_ld = is_ld;
30
+ label->type = type;
31
label->oi = oi;
32
label->datalo_reg = datalo_reg;
33
label->datahi_reg = datahi_reg;
34
@@ -XXX,XX +XXX,XX @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
35
36
#endif /* SOFTMMU */
37
38
-static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64)
39
+static void tcg_out_qemu_ld(TCGContext *s, TCGReg datalo, TCGReg datahi,
40
+ TCGReg addrlo, TCGReg addrhi,
41
+ MemOpIdx oi, TCGType data_type)
42
{
43
- TCGReg datalo, datahi, addrlo, rbase;
44
- TCGReg addrhi __attribute__((unused));
45
- MemOpIdx oi;
46
- MemOp opc, s_bits;
47
+ MemOp opc = get_memop(oi);
48
+ MemOp s_bits = opc & MO_SIZE;
49
+ TCGReg rbase;
50
+
51
#ifdef CONFIG_SOFTMMU
52
- int mem_index;
53
tcg_insn_unit *label_ptr;
54
-#else
55
- unsigned a_bits;
56
-#endif
57
58
- datalo = *args++;
59
- datahi = (TCG_TARGET_REG_BITS == 32 && is_64 ? *args++ : 0);
60
- addrlo = *args++;
61
- addrhi = (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0);
62
- oi = *args++;
63
- opc = get_memop(oi);
64
- s_bits = opc & MO_SIZE;
65
-
66
-#ifdef CONFIG_SOFTMMU
67
- mem_index = get_mmuidx(oi);
68
- addrlo = tcg_out_tlb_read(s, opc, addrlo, addrhi, mem_index, true);
69
+ addrlo = tcg_out_tlb_read(s, opc, addrlo, addrhi, get_mmuidx(oi), true);
70
71
/* Load a pointer into the current opcode w/conditional branch-link. */
72
label_ptr = s->code_ptr;
73
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64)
74
75
rbase = TCG_REG_R3;
76
#else /* !CONFIG_SOFTMMU */
77
- a_bits = get_alignment_bits(opc);
78
+ unsigned a_bits = get_alignment_bits(opc);
79
if (a_bits) {
80
tcg_out_test_alignment(s, true, addrlo, addrhi, a_bits);
81
}
82
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64)
83
}
84
85
#ifdef CONFIG_SOFTMMU
86
- add_qemu_ldst_label(s, true, oi, datalo, datahi, addrlo, addrhi,
87
- s->code_ptr, label_ptr);
88
+ add_qemu_ldst_label(s, true, data_type, oi, datalo, datahi,
89
+ addrlo, addrhi, s->code_ptr, label_ptr);
90
#endif
91
}
92
93
-static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64)
94
+static void tcg_out_qemu_st(TCGContext *s, TCGReg datalo, TCGReg datahi,
95
+ TCGReg addrlo, TCGReg addrhi,
96
+ MemOpIdx oi, TCGType data_type)
97
{
98
- TCGReg datalo, datahi, addrlo, rbase;
99
- TCGReg addrhi __attribute__((unused));
100
- MemOpIdx oi;
101
- MemOp opc, s_bits;
102
+ MemOp opc = get_memop(oi);
103
+ MemOp s_bits = opc & MO_SIZE;
104
+ TCGReg rbase;
105
+
106
#ifdef CONFIG_SOFTMMU
107
- int mem_index;
108
tcg_insn_unit *label_ptr;
109
-#else
110
- unsigned a_bits;
111
-#endif
112
113
- datalo = *args++;
114
- datahi = (TCG_TARGET_REG_BITS == 32 && is_64 ? *args++ : 0);
115
- addrlo = *args++;
116
- addrhi = (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0);
117
- oi = *args++;
118
- opc = get_memop(oi);
119
- s_bits = opc & MO_SIZE;
120
-
121
-#ifdef CONFIG_SOFTMMU
122
- mem_index = get_mmuidx(oi);
123
- addrlo = tcg_out_tlb_read(s, opc, addrlo, addrhi, mem_index, false);
124
+ addrlo = tcg_out_tlb_read(s, opc, addrlo, addrhi, get_mmuidx(oi), false);
125
126
/* Load a pointer into the current opcode w/conditional branch-link. */
127
label_ptr = s->code_ptr;
128
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64)
129
130
rbase = TCG_REG_R3;
131
#else /* !CONFIG_SOFTMMU */
132
- a_bits = get_alignment_bits(opc);
133
+ unsigned a_bits = get_alignment_bits(opc);
134
if (a_bits) {
135
tcg_out_test_alignment(s, false, addrlo, addrhi, a_bits);
136
}
137
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64)
138
}
139
140
#ifdef CONFIG_SOFTMMU
141
- add_qemu_ldst_label(s, false, oi, datalo, datahi, addrlo, addrhi,
142
- s->code_ptr, label_ptr);
143
+ add_qemu_ldst_label(s, false, data_type, oi, datalo, datahi,
144
+ addrlo, addrhi, s->code_ptr, label_ptr);
145
#endif
146
}
147
148
@@ -XXX,XX +XXX,XX @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
149
break;
150
151
case INDEX_op_qemu_ld_i32:
152
- tcg_out_qemu_ld(s, args, false);
153
+ if (TCG_TARGET_REG_BITS >= TARGET_LONG_BITS) {
154
+ tcg_out_qemu_ld(s, args[0], -1, args[1], -1,
155
+ args[2], TCG_TYPE_I32);
156
+ } else {
157
+ tcg_out_qemu_ld(s, args[0], -1, args[1], args[2],
158
+ args[3], TCG_TYPE_I32);
159
+ }
160
break;
161
case INDEX_op_qemu_ld_i64:
162
- tcg_out_qemu_ld(s, args, true);
163
+ if (TCG_TARGET_REG_BITS == 64) {
164
+ tcg_out_qemu_ld(s, args[0], -1, args[1], -1,
165
+ args[2], TCG_TYPE_I64);
166
+ } else if (TARGET_LONG_BITS == 32) {
167
+ tcg_out_qemu_ld(s, args[0], args[1], args[2], -1,
168
+ args[3], TCG_TYPE_I64);
169
+ } else {
170
+ tcg_out_qemu_ld(s, args[0], args[1], args[2], args[3],
171
+ args[4], TCG_TYPE_I64);
172
+ }
173
break;
174
case INDEX_op_qemu_st_i32:
175
- tcg_out_qemu_st(s, args, false);
176
+ if (TCG_TARGET_REG_BITS >= TARGET_LONG_BITS) {
177
+ tcg_out_qemu_st(s, args[0], -1, args[1], -1,
178
+ args[2], TCG_TYPE_I32);
179
+ } else {
180
+ tcg_out_qemu_st(s, args[0], -1, args[1], args[2],
181
+ args[3], TCG_TYPE_I32);
182
+ }
183
break;
184
case INDEX_op_qemu_st_i64:
185
- tcg_out_qemu_st(s, args, true);
186
+ if (TCG_TARGET_REG_BITS == 64) {
187
+ tcg_out_qemu_st(s, args[0], -1, args[1], -1,
188
+ args[2], TCG_TYPE_I64);
189
+ } else if (TARGET_LONG_BITS == 32) {
190
+ tcg_out_qemu_st(s, args[0], args[1], args[2], -1,
191
+ args[3], TCG_TYPE_I64);
192
+ } else {
193
+ tcg_out_qemu_st(s, args[0], args[1], args[2], args[3],
194
+ args[4], TCG_TYPE_I64);
195
+ }
196
break;
197
198
case INDEX_op_setcond_i32:
199
--
200
2.34.1
201
202
diff view generated by jsdifflib
New patch
[PULL 32/42] tcg/ppc: Introduce HostAddress
1
Collect the parts of the host address into a struct.
2
Reorg tcg_out_qemu_{ld,st} to use it.
1
3
4
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
---
7
tcg/ppc/tcg-target.c.inc | 90 +++++++++++++++++++++-------------------
8
1 file changed, 47 insertions(+), 43 deletions(-)
9
10
diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc
11
index XXXXXXX..XXXXXXX 100644
12
--- a/tcg/ppc/tcg-target.c.inc
13
+++ b/tcg/ppc/tcg-target.c.inc
14
@@ -XXX,XX +XXX,XX @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
15
{
16
return tcg_out_fail_alignment(s, l);
17
}
18
-
19
#endif /* SOFTMMU */
20
21
+typedef struct {
22
+ TCGReg base;
23
+ TCGReg index;
24
+} HostAddress;
25
+
26
static void tcg_out_qemu_ld(TCGContext *s, TCGReg datalo, TCGReg datahi,
27
TCGReg addrlo, TCGReg addrhi,
28
MemOpIdx oi, TCGType data_type)
29
{
30
MemOp opc = get_memop(oi);
31
MemOp s_bits = opc & MO_SIZE;
32
- TCGReg rbase;
33
+ HostAddress h;
34
35
#ifdef CONFIG_SOFTMMU
36
tcg_insn_unit *label_ptr;
37
38
- addrlo = tcg_out_tlb_read(s, opc, addrlo, addrhi, get_mmuidx(oi), true);
39
+ h.index = tcg_out_tlb_read(s, opc, addrlo, addrhi, get_mmuidx(oi), true);
40
+ h.base = TCG_REG_R3;
41
42
/* Load a pointer into the current opcode w/conditional branch-link. */
43
label_ptr = s->code_ptr;
44
tcg_out32(s, BC | BI(7, CR_EQ) | BO_COND_FALSE | LK);
45
-
46
- rbase = TCG_REG_R3;
47
#else /* !CONFIG_SOFTMMU */
48
unsigned a_bits = get_alignment_bits(opc);
49
if (a_bits) {
50
tcg_out_test_alignment(s, true, addrlo, addrhi, a_bits);
51
}
52
- rbase = guest_base ? TCG_GUEST_BASE_REG : 0;
53
+ h.base = guest_base ? TCG_GUEST_BASE_REG : 0;
54
+ h.index = addrlo;
55
if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
56
tcg_out_ext32u(s, TCG_REG_TMP1, addrlo);
57
- addrlo = TCG_REG_TMP1;
58
+ h.index = TCG_REG_TMP1;
59
}
60
#endif
61
62
if (TCG_TARGET_REG_BITS == 32 && s_bits == MO_64) {
63
if (opc & MO_BSWAP) {
64
- tcg_out32(s, ADDI | TAI(TCG_REG_R0, addrlo, 4));
65
- tcg_out32(s, LWBRX | TAB(datalo, rbase, addrlo));
66
- tcg_out32(s, LWBRX | TAB(datahi, rbase, TCG_REG_R0));
67
- } else if (rbase != 0) {
68
- tcg_out32(s, ADDI | TAI(TCG_REG_R0, addrlo, 4));
69
- tcg_out32(s, LWZX | TAB(datahi, rbase, addrlo));
70
- tcg_out32(s, LWZX | TAB(datalo, rbase, TCG_REG_R0));
71
- } else if (addrlo == datahi) {
72
- tcg_out32(s, LWZ | TAI(datalo, addrlo, 4));
73
- tcg_out32(s, LWZ | TAI(datahi, addrlo, 0));
74
+ tcg_out32(s, ADDI | TAI(TCG_REG_R0, h.index, 4));
75
+ tcg_out32(s, LWBRX | TAB(datalo, h.base, h.index));
76
+ tcg_out32(s, LWBRX | TAB(datahi, h.base, TCG_REG_R0));
77
+ } else if (h.base != 0) {
78
+ tcg_out32(s, ADDI | TAI(TCG_REG_R0, h.index, 4));
79
+ tcg_out32(s, LWZX | TAB(datahi, h.base, h.index));
80
+ tcg_out32(s, LWZX | TAB(datalo, h.base, TCG_REG_R0));
81
+ } else if (h.index == datahi) {
82
+ tcg_out32(s, LWZ | TAI(datalo, h.index, 4));
83
+ tcg_out32(s, LWZ | TAI(datahi, h.index, 0));
84
} else {
85
- tcg_out32(s, LWZ | TAI(datahi, addrlo, 0));
86
- tcg_out32(s, LWZ | TAI(datalo, addrlo, 4));
87
+ tcg_out32(s, LWZ | TAI(datahi, h.index, 0));
88
+ tcg_out32(s, LWZ | TAI(datalo, h.index, 4));
89
}
90
} else {
91
uint32_t insn = qemu_ldx_opc[opc & (MO_BSWAP | MO_SSIZE)];
92
if (!have_isa_2_06 && insn == LDBRX) {
93
- tcg_out32(s, ADDI | TAI(TCG_REG_R0, addrlo, 4));
94
- tcg_out32(s, LWBRX | TAB(datalo, rbase, addrlo));
95
- tcg_out32(s, LWBRX | TAB(TCG_REG_R0, rbase, TCG_REG_R0));
96
+ tcg_out32(s, ADDI | TAI(TCG_REG_R0, h.index, 4));
97
+ tcg_out32(s, LWBRX | TAB(datalo, h.base, h.index));
98
+ tcg_out32(s, LWBRX | TAB(TCG_REG_R0, h.base, TCG_REG_R0));
99
tcg_out_rld(s, RLDIMI, datalo, TCG_REG_R0, 32, 0);
100
} else if (insn) {
101
- tcg_out32(s, insn | TAB(datalo, rbase, addrlo));
102
+ tcg_out32(s, insn | TAB(datalo, h.base, h.index));
103
} else {
104
insn = qemu_ldx_opc[opc & (MO_SIZE | MO_BSWAP)];
105
- tcg_out32(s, insn | TAB(datalo, rbase, addrlo));
106
+ tcg_out32(s, insn | TAB(datalo, h.base, h.index));
107
tcg_out_movext(s, TCG_TYPE_REG, datalo,
108
TCG_TYPE_REG, opc & MO_SSIZE, datalo);
109
}
110
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg datalo, TCGReg datahi,
111
{
112
MemOp opc = get_memop(oi);
113
MemOp s_bits = opc & MO_SIZE;
114
- TCGReg rbase;
115
+ HostAddress h;
116
117
#ifdef CONFIG_SOFTMMU
118
tcg_insn_unit *label_ptr;
119
120
- addrlo = tcg_out_tlb_read(s, opc, addrlo, addrhi, get_mmuidx(oi), false);
121
+ h.index = tcg_out_tlb_read(s, opc, addrlo, addrhi, get_mmuidx(oi), false);
122
+ h.base = TCG_REG_R3;
123
124
/* Load a pointer into the current opcode w/conditional branch-link. */
125
label_ptr = s->code_ptr;
126
tcg_out32(s, BC | BI(7, CR_EQ) | BO_COND_FALSE | LK);
127
-
128
- rbase = TCG_REG_R3;
129
#else /* !CONFIG_SOFTMMU */
130
unsigned a_bits = get_alignment_bits(opc);
131
if (a_bits) {
132
tcg_out_test_alignment(s, false, addrlo, addrhi, a_bits);
133
}
134
- rbase = guest_base ? TCG_GUEST_BASE_REG : 0;
135
+ h.base = guest_base ? TCG_GUEST_BASE_REG : 0;
136
+ h.index = addrlo;
137
if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
138
tcg_out_ext32u(s, TCG_REG_TMP1, addrlo);
139
- addrlo = TCG_REG_TMP1;
140
+ h.index = TCG_REG_TMP1;
141
}
142
#endif
143
144
if (TCG_TARGET_REG_BITS == 32 && s_bits == MO_64) {
145
if (opc & MO_BSWAP) {
146
- tcg_out32(s, ADDI | TAI(TCG_REG_R0, addrlo, 4));
147
- tcg_out32(s, STWBRX | SAB(datalo, rbase, addrlo));
148
- tcg_out32(s, STWBRX | SAB(datahi, rbase, TCG_REG_R0));
149
- } else if (rbase != 0) {
150
- tcg_out32(s, ADDI | TAI(TCG_REG_R0, addrlo, 4));
151
- tcg_out32(s, STWX | SAB(datahi, rbase, addrlo));
152
- tcg_out32(s, STWX | SAB(datalo, rbase, TCG_REG_R0));
153
+ tcg_out32(s, ADDI | TAI(TCG_REG_R0, h.index, 4));
154
+ tcg_out32(s, STWBRX | SAB(datalo, h.base, h.index));
155
+ tcg_out32(s, STWBRX | SAB(datahi, h.base, TCG_REG_R0));
156
+ } else if (h.base != 0) {
157
+ tcg_out32(s, ADDI | TAI(TCG_REG_R0, h.index, 4));
158
+ tcg_out32(s, STWX | SAB(datahi, h.base, h.index));
159
+ tcg_out32(s, STWX | SAB(datalo, h.base, TCG_REG_R0));
160
} else {
161
- tcg_out32(s, STW | TAI(datahi, addrlo, 0));
162
- tcg_out32(s, STW | TAI(datalo, addrlo, 4));
163
+ tcg_out32(s, STW | TAI(datahi, h.index, 0));
164
+ tcg_out32(s, STW | TAI(datalo, h.index, 4));
165
}
166
} else {
167
uint32_t insn = qemu_stx_opc[opc & (MO_BSWAP | MO_SIZE)];
168
if (!have_isa_2_06 && insn == STDBRX) {
169
- tcg_out32(s, STWBRX | SAB(datalo, rbase, addrlo));
170
- tcg_out32(s, ADDI | TAI(TCG_REG_TMP1, addrlo, 4));
171
+ tcg_out32(s, STWBRX | SAB(datalo, h.base, h.index));
172
+ tcg_out32(s, ADDI | TAI(TCG_REG_TMP1, h.index, 4));
173
tcg_out_shri64(s, TCG_REG_R0, datalo, 32);
174
- tcg_out32(s, STWBRX | SAB(TCG_REG_R0, rbase, TCG_REG_TMP1));
175
+ tcg_out32(s, STWBRX | SAB(TCG_REG_R0, h.base, TCG_REG_TMP1));
176
} else {
177
- tcg_out32(s, insn | SAB(datalo, rbase, addrlo));
178
+ tcg_out32(s, insn | SAB(datalo, h.base, h.index));
179
}
180
}
181
182
--
183
2.34.1
184
185
diff view generated by jsdifflib
New patch
[PULL 33/42] tcg/riscv: Require TCG_TARGET_REG_BITS == 64
1
The port currently does not support "oversize" guests, which
2
means riscv32 can only target 32-bit guests. We will soon be
3
building TCG once for all guests. This implies that we can
4
only support riscv64.
1
5
6
Since all Linux distributions target riscv64 not riscv32,
7
this is not much of a restriction and simplifies the code.
8
9
The brcond2 and setcond2 opcodes are exclusive to 32-bit hosts,
10
so we can and should remove the stubs.
11
12
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
13
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
14
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
15
---
16
tcg/riscv/tcg-target-con-set.h | 8 --
17
tcg/riscv/tcg-target.h | 22 ++--
18
tcg/riscv/tcg-target.c.inc | 232 +++++++++------------------------
19
3 files changed, 72 insertions(+), 190 deletions(-)
20
21
diff --git a/tcg/riscv/tcg-target-con-set.h b/tcg/riscv/tcg-target-con-set.h
22
index XXXXXXX..XXXXXXX 100644
23
--- a/tcg/riscv/tcg-target-con-set.h
24
+++ b/tcg/riscv/tcg-target-con-set.h
25
@@ -XXX,XX +XXX,XX @@ C_O0_I1(r)
26
C_O0_I2(LZ, L)
27
C_O0_I2(rZ, r)
28
C_O0_I2(rZ, rZ)
29
-C_O0_I3(LZ, L, L)
30
-C_O0_I3(LZ, LZ, L)
31
-C_O0_I4(LZ, LZ, L, L)
32
-C_O0_I4(rZ, rZ, rZ, rZ)
33
C_O1_I1(r, L)
34
C_O1_I1(r, r)
35
-C_O1_I2(r, L, L)
36
C_O1_I2(r, r, ri)
37
C_O1_I2(r, r, rI)
38
C_O1_I2(r, rZ, rN)
39
C_O1_I2(r, rZ, rZ)
40
-C_O1_I4(r, rZ, rZ, rZ, rZ)
41
-C_O2_I1(r, r, L)
42
-C_O2_I2(r, r, L, L)
43
C_O2_I4(r, r, rZ, rZ, rM, rM)
44
diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h
45
index XXXXXXX..XXXXXXX 100644
46
--- a/tcg/riscv/tcg-target.h
47
+++ b/tcg/riscv/tcg-target.h
48
@@ -XXX,XX +XXX,XX @@
49
#ifndef RISCV_TCG_TARGET_H
50
#define RISCV_TCG_TARGET_H
51
52
-#if __riscv_xlen == 32
53
-# define TCG_TARGET_REG_BITS 32
54
-#elif __riscv_xlen == 64
55
-# define TCG_TARGET_REG_BITS 64
56
+/*
57
+ * We don't support oversize guests.
58
+ * Since we will only build tcg once, this in turn requires a 64-bit host.
59
+ */
60
+#if __riscv_xlen != 64
61
+#error "unsupported code generation mode"
62
#endif
63
+#define TCG_TARGET_REG_BITS 64
64
65
#define TCG_TARGET_INSN_UNIT_SIZE 4
66
#define TCG_TARGET_TLB_DISPLACEMENT_BITS 20
67
@@ -XXX,XX +XXX,XX @@ typedef enum {
68
#define TCG_TARGET_STACK_ALIGN 16
69
#define TCG_TARGET_CALL_STACK_OFFSET 0
70
#define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_NORMAL
71
-#if TCG_TARGET_REG_BITS == 32
72
-#define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_EVEN
73
-#define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_EVEN
74
-#else
75
#define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_NORMAL
76
#define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_NORMAL
77
-#endif
78
#define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_NORMAL
79
80
/* optional instructions */
81
@@ -XXX,XX +XXX,XX @@ typedef enum {
82
#define TCG_TARGET_HAS_sub2_i32 1
83
#define TCG_TARGET_HAS_mulu2_i32 0
84
#define TCG_TARGET_HAS_muls2_i32 0
85
-#define TCG_TARGET_HAS_muluh_i32 (TCG_TARGET_REG_BITS == 32)
86
-#define TCG_TARGET_HAS_mulsh_i32 (TCG_TARGET_REG_BITS == 32)
87
+#define TCG_TARGET_HAS_muluh_i32 0
88
+#define TCG_TARGET_HAS_mulsh_i32 0
89
#define TCG_TARGET_HAS_ext8s_i32 1
90
#define TCG_TARGET_HAS_ext16s_i32 1
91
#define TCG_TARGET_HAS_ext8u_i32 1
92
@@ -XXX,XX +XXX,XX @@ typedef enum {
93
#define TCG_TARGET_HAS_setcond2 1
94
#define TCG_TARGET_HAS_qemu_st8_i32 0
95
96
-#if TCG_TARGET_REG_BITS == 64
97
#define TCG_TARGET_HAS_movcond_i64 0
98
#define TCG_TARGET_HAS_div_i64 1
99
#define TCG_TARGET_HAS_rem_i64 1
100
@@ -XXX,XX +XXX,XX @@ typedef enum {
101
#define TCG_TARGET_HAS_muls2_i64 0
102
#define TCG_TARGET_HAS_muluh_i64 1
103
#define TCG_TARGET_HAS_mulsh_i64 1
104
-#endif
105
106
#define TCG_TARGET_DEFAULT_MO (0)
107
108
diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
109
index XXXXXXX..XXXXXXX 100644
110
--- a/tcg/riscv/tcg-target.c.inc
111
+++ b/tcg/riscv/tcg-target.c.inc
112
@@ -XXX,XX +XXX,XX @@ static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot)
113
#define SOFTMMU_RESERVE_REGS 0
114
#endif
115
116
-
117
-static inline tcg_target_long sextreg(tcg_target_long val, int pos, int len)
118
-{
119
- if (TCG_TARGET_REG_BITS == 32) {
120
- return sextract32(val, pos, len);
121
- } else {
122
- return sextract64(val, pos, len);
123
- }
124
-}
125
+#define sextreg sextract64
126
127
/* test if a constant matches the constraint */
128
static bool tcg_target_const_match(int64_t val, TCGType type, int ct)
129
@@ -XXX,XX +XXX,XX @@ typedef enum {
130
OPC_XOR = 0x4033,
131
OPC_XORI = 0x4013,
132
133
-#if TCG_TARGET_REG_BITS == 64
134
OPC_ADDIW = 0x1b,
135
OPC_ADDW = 0x3b,
136
OPC_DIVUW = 0x200503b,
137
@@ -XXX,XX +XXX,XX @@ typedef enum {
138
OPC_SRLIW = 0x501b,
139
OPC_SRLW = 0x503b,
140
OPC_SUBW = 0x4000003b,
141
-#else
142
- /* Simplify code throughout by defining aliases for RV32. */
143
- OPC_ADDIW = OPC_ADDI,
144
- OPC_ADDW = OPC_ADD,
145
- OPC_DIVUW = OPC_DIVU,
146
- OPC_DIVW = OPC_DIV,
147
- OPC_MULW = OPC_MUL,
148
- OPC_REMUW = OPC_REMU,
149
- OPC_REMW = OPC_REM,
150
- OPC_SLLIW = OPC_SLLI,
151
- OPC_SLLW = OPC_SLL,
152
- OPC_SRAIW = OPC_SRAI,
153
- OPC_SRAW = OPC_SRA,
154
- OPC_SRLIW = OPC_SRLI,
155
- OPC_SRLW = OPC_SRL,
156
- OPC_SUBW = OPC_SUB,
157
-#endif
158
159
OPC_FENCE = 0x0000000f,
160
OPC_NOP = OPC_ADDI, /* nop = addi r0,r0,0 */
161
@@ -XXX,XX +XXX,XX @@ static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg rd,
162
tcg_target_long lo, hi, tmp;
163
int shift, ret;
164
165
- if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) {
166
+ if (type == TCG_TYPE_I32) {
167
val = (int32_t)val;
168
}
169
170
@@ -XXX,XX +XXX,XX @@ static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg rd,
171
}
172
173
hi = val - lo;
174
- if (TCG_TARGET_REG_BITS == 32 || val == (int32_t)val) {
175
+ if (val == (int32_t)val) {
176
tcg_out_opc_upper(s, OPC_LUI, rd, hi);
177
if (lo != 0) {
178
tcg_out_opc_imm(s, OPC_ADDIW, rd, rd, lo);
179
@@ -XXX,XX +XXX,XX @@ static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg rd,
180
return;
181
}
182
183
- /* We can only be here if TCG_TARGET_REG_BITS != 32 */
184
tmp = tcg_pcrel_diff(s, (void *)val);
185
if (tmp == (int32_t)tmp) {
186
tcg_out_opc_upper(s, OPC_AUIPC, rd, 0);
187
@@ -XXX,XX +XXX,XX @@ static void tcg_out_ldst(TCGContext *s, RISCVInsn opc, TCGReg data,
188
static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg,
189
TCGReg arg1, intptr_t arg2)
190
{
191
- bool is32bit = (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I32);
192
- tcg_out_ldst(s, is32bit ? OPC_LW : OPC_LD, arg, arg1, arg2);
193
+ RISCVInsn insn = type == TCG_TYPE_I32 ? OPC_LW : OPC_LD;
194
+ tcg_out_ldst(s, insn, arg, arg1, arg2);
195
}
196
197
static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg,
198
TCGReg arg1, intptr_t arg2)
199
{
200
- bool is32bit = (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I32);
201
- tcg_out_ldst(s, is32bit ? OPC_SW : OPC_SD, arg, arg1, arg2);
202
+ RISCVInsn insn = type == TCG_TYPE_I32 ? OPC_SW : OPC_SD;
203
+ tcg_out_ldst(s, insn, arg, arg1, arg2);
204
}
205
206
static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val,
207
@@ -XXX,XX +XXX,XX @@ static void tcg_out_setcond(TCGContext *s, TCGCond cond, TCGReg ret,
208
}
209
}
210
211
-static void tcg_out_brcond2(TCGContext *s, TCGCond cond, TCGReg al, TCGReg ah,
212
- TCGReg bl, TCGReg bh, TCGLabel *l)
213
-{
214
- /* todo */
215
- g_assert_not_reached();
216
-}
217
-
218
-static void tcg_out_setcond2(TCGContext *s, TCGCond cond, TCGReg ret,
219
- TCGReg al, TCGReg ah, TCGReg bl, TCGReg bh)
220
-{
221
- /* todo */
222
- g_assert_not_reached();
223
-}
224
-
225
static void tcg_out_call_int(TCGContext *s, const tcg_insn_unit *arg, bool tail)
226
{
227
TCGReg link = tail ? TCG_REG_ZERO : TCG_REG_RA;
228
@@ -XXX,XX +XXX,XX @@ static void tcg_out_call_int(TCGContext *s, const tcg_insn_unit *arg, bool tail)
229
if (offset == sextreg(offset, 0, 20)) {
230
/* short jump: -2097150 to 2097152 */
231
tcg_out_opc_jump(s, OPC_JAL, link, offset);
232
- } else if (TCG_TARGET_REG_BITS == 32 || offset == (int32_t)offset) {
233
+ } else if (offset == (int32_t)offset) {
234
/* long jump: -2147483646 to 2147483648 */
235
tcg_out_opc_upper(s, OPC_AUIPC, TCG_REG_TMP0, 0);
236
tcg_out_opc_imm(s, OPC_JALR, link, TCG_REG_TMP0, 0);
237
ret = reloc_call(s->code_ptr - 2, arg);
238
tcg_debug_assert(ret == true);
239
- } else if (TCG_TARGET_REG_BITS == 64) {
240
+ } else {
241
/* far jump: 64-bit */
242
tcg_target_long imm = sextreg((tcg_target_long)arg, 0, 12);
243
tcg_target_long base = (tcg_target_long)arg - imm;
244
tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP0, base);
245
tcg_out_opc_imm(s, OPC_JALR, link, TCG_REG_TMP0, imm);
246
- } else {
247
- g_assert_not_reached();
248
}
249
}
250
251
@@ -XXX,XX +XXX,XX @@ static void * const qemu_st_helpers[MO_SIZE + 1] = {
252
#endif
253
};
254
255
-/* We don't support oversize guests */
256
-QEMU_BUILD_BUG_ON(TCG_TARGET_REG_BITS < TARGET_LONG_BITS);
257
-
258
/* We expect to use a 12-bit negative offset from ENV. */
259
QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0);
260
QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -(1 << 11));
261
@@ -XXX,XX +XXX,XX @@ static void tcg_out_goto(TCGContext *s, const tcg_insn_unit *target)
262
tcg_debug_assert(ok);
263
}
264
265
-static TCGReg tcg_out_tlb_load(TCGContext *s, TCGReg addrl,
266
- TCGReg addrh, MemOpIdx oi,
267
+static TCGReg tcg_out_tlb_load(TCGContext *s, TCGReg addr, MemOpIdx oi,
268
tcg_insn_unit **label_ptr, bool is_load)
269
{
270
MemOp opc = get_memop(oi);
271
@@ -XXX,XX +XXX,XX @@ static TCGReg tcg_out_tlb_load(TCGContext *s, TCGReg addrl,
272
tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP0, mask_base, mask_ofs);
273
tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, table_base, table_ofs);
274
275
- tcg_out_opc_imm(s, OPC_SRLI, TCG_REG_TMP2, addrl,
276
+ tcg_out_opc_imm(s, OPC_SRLI, TCG_REG_TMP2, addr,
277
TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS);
278
tcg_out_opc_reg(s, OPC_AND, TCG_REG_TMP2, TCG_REG_TMP2, TCG_REG_TMP0);
279
tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP2, TCG_REG_TMP2, TCG_REG_TMP1);
280
@@ -XXX,XX +XXX,XX @@ static TCGReg tcg_out_tlb_load(TCGContext *s, TCGReg addrl,
281
/* Clear the non-page, non-alignment bits from the address. */
282
compare_mask = (tcg_target_long)TARGET_PAGE_MASK | ((1 << a_bits) - 1);
283
if (compare_mask == sextreg(compare_mask, 0, 12)) {
284
- tcg_out_opc_imm(s, OPC_ANDI, TCG_REG_TMP1, addrl, compare_mask);
285
+ tcg_out_opc_imm(s, OPC_ANDI, TCG_REG_TMP1, addr, compare_mask);
286
} else {
287
tcg_out_movi(s, TCG_TYPE_TL, TCG_REG_TMP1, compare_mask);
288
- tcg_out_opc_reg(s, OPC_AND, TCG_REG_TMP1, TCG_REG_TMP1, addrl);
289
+ tcg_out_opc_reg(s, OPC_AND, TCG_REG_TMP1, TCG_REG_TMP1, addr);
290
}
291
292
/* Compare masked address with the TLB entry. */
293
@@ -XXX,XX +XXX,XX @@ static TCGReg tcg_out_tlb_load(TCGContext *s, TCGReg addrl,
294
tcg_out_opc_branch(s, OPC_BNE, TCG_REG_TMP0, TCG_REG_TMP1, 0);
295
296
/* TLB Hit - translate address using addend. */
297
- if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
298
- tcg_out_ext32u(s, TCG_REG_TMP0, addrl);
299
- addrl = TCG_REG_TMP0;
300
+ if (TARGET_LONG_BITS == 32) {
301
+ tcg_out_ext32u(s, TCG_REG_TMP0, addr);
302
+ addr = TCG_REG_TMP0;
303
}
304
- tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP0, TCG_REG_TMP2, addrl);
305
+ tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP0, TCG_REG_TMP2, addr);
306
return TCG_REG_TMP0;
307
}
308
309
static void add_qemu_ldst_label(TCGContext *s, int is_ld, MemOpIdx oi,
310
- TCGType ext,
311
- TCGReg datalo, TCGReg datahi,
312
- TCGReg addrlo, TCGReg addrhi,
313
- void *raddr, tcg_insn_unit **label_ptr)
314
+ TCGType data_type, TCGReg data_reg,
315
+ TCGReg addr_reg, void *raddr,
316
+ tcg_insn_unit **label_ptr)
317
{
318
TCGLabelQemuLdst *label = new_ldst_label(s);
319
320
label->is_ld = is_ld;
321
label->oi = oi;
322
- label->type = ext;
323
- label->datalo_reg = datalo;
324
- label->datahi_reg = datahi;
325
- label->addrlo_reg = addrlo;
326
- label->addrhi_reg = addrhi;
327
+ label->type = data_type;
328
+ label->datalo_reg = data_reg;
329
+ label->addrlo_reg = addr_reg;
330
label->raddr = tcg_splitwx_to_rx(raddr);
331
label->label_ptr[0] = label_ptr[0];
332
}
333
@@ -XXX,XX +XXX,XX @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
334
TCGReg a2 = tcg_target_call_iarg_regs[2];
335
TCGReg a3 = tcg_target_call_iarg_regs[3];
336
337
- /* We don't support oversize guests */
338
- if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
339
- g_assert_not_reached();
340
- }
341
-
342
/* resolve label address */
343
if (!reloc_sbimm12(l->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) {
344
return false;
345
@@ -XXX,XX +XXX,XX @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
346
TCGReg a3 = tcg_target_call_iarg_regs[3];
347
TCGReg a4 = tcg_target_call_iarg_regs[4];
348
349
- /* We don't support oversize guests */
350
- if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
351
- g_assert_not_reached();
352
- }
353
-
354
/* resolve label address */
355
if (!reloc_sbimm12(l->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) {
356
return false;
357
@@ -XXX,XX +XXX,XX @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
358
359
#endif /* CONFIG_SOFTMMU */
360
361
-static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg lo, TCGReg hi,
362
+static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg val,
363
TCGReg base, MemOp opc, bool is_64)
364
{
365
/* Byte swapping is left to middle-end expansion. */
366
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg lo, TCGReg hi,
367
368
switch (opc & (MO_SSIZE)) {
369
case MO_UB:
370
- tcg_out_opc_imm(s, OPC_LBU, lo, base, 0);
371
+ tcg_out_opc_imm(s, OPC_LBU, val, base, 0);
372
break;
373
case MO_SB:
374
- tcg_out_opc_imm(s, OPC_LB, lo, base, 0);
375
+ tcg_out_opc_imm(s, OPC_LB, val, base, 0);
376
break;
377
case MO_UW:
378
- tcg_out_opc_imm(s, OPC_LHU, lo, base, 0);
379
+ tcg_out_opc_imm(s, OPC_LHU, val, base, 0);
380
break;
381
case MO_SW:
382
- tcg_out_opc_imm(s, OPC_LH, lo, base, 0);
383
+ tcg_out_opc_imm(s, OPC_LH, val, base, 0);
384
break;
385
case MO_UL:
386
- if (TCG_TARGET_REG_BITS == 64 && is_64) {
387
- tcg_out_opc_imm(s, OPC_LWU, lo, base, 0);
388
+ if (is_64) {
389
+ tcg_out_opc_imm(s, OPC_LWU, val, base, 0);
390
break;
391
}
392
/* FALLTHRU */
393
case MO_SL:
394
- tcg_out_opc_imm(s, OPC_LW, lo, base, 0);
395
+ tcg_out_opc_imm(s, OPC_LW, val, base, 0);
396
break;
397
case MO_UQ:
398
- /* Prefer to load from offset 0 first, but allow for overlap. */
399
- if (TCG_TARGET_REG_BITS == 64) {
400
- tcg_out_opc_imm(s, OPC_LD, lo, base, 0);
401
- } else if (lo != base) {
402
- tcg_out_opc_imm(s, OPC_LW, lo, base, 0);
403
- tcg_out_opc_imm(s, OPC_LW, hi, base, 4);
404
- } else {
405
- tcg_out_opc_imm(s, OPC_LW, hi, base, 4);
406
- tcg_out_opc_imm(s, OPC_LW, lo, base, 0);
407
- }
408
+ tcg_out_opc_imm(s, OPC_LD, val, base, 0);
409
break;
410
default:
411
g_assert_not_reached();
412
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg lo, TCGReg hi,
413
414
static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64)
415
{
416
- TCGReg addr_regl, addr_regh __attribute__((unused));
417
- TCGReg data_regl, data_regh;
418
+ TCGReg addr_reg, data_reg;
419
MemOpIdx oi;
420
MemOp opc;
421
#if defined(CONFIG_SOFTMMU)
422
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64)
423
#endif
424
TCGReg base;
425
426
- data_regl = *args++;
427
- data_regh = (TCG_TARGET_REG_BITS == 32 && is_64 ? *args++ : 0);
428
- addr_regl = *args++;
429
- addr_regh = (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0);
430
+ data_reg = *args++;
431
+ addr_reg = *args++;
432
oi = *args++;
433
opc = get_memop(oi);
434
435
#if defined(CONFIG_SOFTMMU)
436
- base = tcg_out_tlb_load(s, addr_regl, addr_regh, oi, label_ptr, 1);
437
- tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_64);
438
- add_qemu_ldst_label(s, 1, oi,
439
- (is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32),
440
- data_regl, data_regh, addr_regl, addr_regh,
441
- s->code_ptr, label_ptr);
442
+ base = tcg_out_tlb_load(s, addr_reg, oi, label_ptr, 1);
443
+ tcg_out_qemu_ld_direct(s, data_reg, base, opc, is_64);
444
+ add_qemu_ldst_label(s, 1, oi, (is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32),
445
+ data_reg, addr_reg, s->code_ptr, label_ptr);
446
#else
447
a_bits = get_alignment_bits(opc);
448
if (a_bits) {
449
- tcg_out_test_alignment(s, true, addr_regl, a_bits);
450
+ tcg_out_test_alignment(s, true, addr_reg, a_bits);
451
}
452
- base = addr_regl;
453
- if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
454
+ base = addr_reg;
455
+ if (TARGET_LONG_BITS == 32) {
456
tcg_out_ext32u(s, TCG_REG_TMP0, base);
457
base = TCG_REG_TMP0;
458
}
459
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64)
460
tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP0, TCG_GUEST_BASE_REG, base);
461
base = TCG_REG_TMP0;
462
}
463
- tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_64);
464
+ tcg_out_qemu_ld_direct(s, data_reg, base, opc, is_64);
465
#endif
466
}
467
468
-static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg lo, TCGReg hi,
469
+static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg val,
470
TCGReg base, MemOp opc)
471
{
472
/* Byte swapping is left to middle-end expansion. */
473
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg lo, TCGReg hi,
474
475
switch (opc & (MO_SSIZE)) {
476
case MO_8:
477
- tcg_out_opc_store(s, OPC_SB, base, lo, 0);
478
+ tcg_out_opc_store(s, OPC_SB, base, val, 0);
479
break;
480
case MO_16:
481
- tcg_out_opc_store(s, OPC_SH, base, lo, 0);
482
+ tcg_out_opc_store(s, OPC_SH, base, val, 0);
483
break;
484
case MO_32:
485
- tcg_out_opc_store(s, OPC_SW, base, lo, 0);
486
+ tcg_out_opc_store(s, OPC_SW, base, val, 0);
487
break;
488
case MO_64:
489
- if (TCG_TARGET_REG_BITS == 64) {
490
- tcg_out_opc_store(s, OPC_SD, base, lo, 0);
491
- } else {
492
- tcg_out_opc_store(s, OPC_SW, base, lo, 0);
493
- tcg_out_opc_store(s, OPC_SW, base, hi, 4);
494
- }
495
+ tcg_out_opc_store(s, OPC_SD, base, val, 0);
496
break;
497
default:
498
g_assert_not_reached();
499
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg lo, TCGReg hi,
500
501
static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64)
502
{
503
- TCGReg addr_regl, addr_regh __attribute__((unused));
504
- TCGReg data_regl, data_regh;
505
+ TCGReg addr_reg, data_reg;
506
MemOpIdx oi;
507
MemOp opc;
508
#if defined(CONFIG_SOFTMMU)
509
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64)
510
#endif
511
TCGReg base;
512
513
- data_regl = *args++;
514
- data_regh = (TCG_TARGET_REG_BITS == 32 && is_64 ? *args++ : 0);
515
- addr_regl = *args++;
516
- addr_regh = (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0);
517
+ data_reg = *args++;
518
+ addr_reg = *args++;
519
oi = *args++;
520
opc = get_memop(oi);
521
522
#if defined(CONFIG_SOFTMMU)
523
- base = tcg_out_tlb_load(s, addr_regl, addr_regh, oi, label_ptr, 0);
524
- tcg_out_qemu_st_direct(s, data_regl, data_regh, base, opc);
525
- add_qemu_ldst_label(s, 0, oi,
526
- (is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32),
527
- data_regl, data_regh, addr_regl, addr_regh,
528
- s->code_ptr, label_ptr);
529
+ base = tcg_out_tlb_load(s, addr_reg, oi, label_ptr, 0);
530
+ tcg_out_qemu_st_direct(s, data_reg, base, opc);
531
+ add_qemu_ldst_label(s, 0, oi, (is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32),
532
+ data_reg, addr_reg, s->code_ptr, label_ptr);
533
#else
534
a_bits = get_alignment_bits(opc);
535
if (a_bits) {
536
- tcg_out_test_alignment(s, false, addr_regl, a_bits);
537
+ tcg_out_test_alignment(s, false, addr_reg, a_bits);
538
}
539
- base = addr_regl;
540
- if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
541
+ base = addr_reg;
542
+ if (TARGET_LONG_BITS == 32) {
543
tcg_out_ext32u(s, TCG_REG_TMP0, base);
544
base = TCG_REG_TMP0;
545
}
546
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64)
547
tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP0, TCG_GUEST_BASE_REG, base);
548
base = TCG_REG_TMP0;
549
}
550
- tcg_out_qemu_st_direct(s, data_regl, data_regh, base, opc);
551
+ tcg_out_qemu_st_direct(s, data_reg, base, opc);
552
#endif
553
}
554
555
@@ -XXX,XX +XXX,XX @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
556
case INDEX_op_brcond_i64:
557
tcg_out_brcond(s, a2, a0, a1, arg_label(args[3]));
558
break;
559
- case INDEX_op_brcond2_i32:
560
- tcg_out_brcond2(s, args[4], a0, a1, a2, args[3], arg_label(args[5]));
561
- break;
562
563
case INDEX_op_setcond_i32:
564
case INDEX_op_setcond_i64:
565
tcg_out_setcond(s, args[3], a0, a1, a2);
566
break;
567
- case INDEX_op_setcond2_i32:
568
- tcg_out_setcond2(s, args[5], a0, a1, a2, args[3], args[4]);
569
- break;
570
571
case INDEX_op_qemu_ld_i32:
572
tcg_out_qemu_ld(s, args, false);
573
@@ -XXX,XX +XXX,XX @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
574
case INDEX_op_sub2_i64:
575
return C_O2_I4(r, r, rZ, rZ, rM, rM);
576
577
- case INDEX_op_brcond2_i32:
578
- return C_O0_I4(rZ, rZ, rZ, rZ);
579
-
580
- case INDEX_op_setcond2_i32:
581
- return C_O1_I4(r, rZ, rZ, rZ, rZ);
582
-
583
case INDEX_op_qemu_ld_i32:
584
- return (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS
585
- ? C_O1_I1(r, L) : C_O1_I2(r, L, L));
586
- case INDEX_op_qemu_st_i32:
587
- return (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS
588
- ? C_O0_I2(LZ, L) : C_O0_I3(LZ, L, L));
589
case INDEX_op_qemu_ld_i64:
590
- return (TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, L)
591
- : TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? C_O2_I1(r, r, L)
592
- : C_O2_I2(r, r, L, L));
593
+ return C_O1_I1(r, L);
594
+ case INDEX_op_qemu_st_i32:
595
case INDEX_op_qemu_st_i64:
596
- return (TCG_TARGET_REG_BITS == 64 ? C_O0_I2(LZ, L)
597
- : TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? C_O0_I3(LZ, LZ, L)
598
- : C_O0_I4(LZ, LZ, L, L));
599
+ return C_O0_I2(LZ, L);
600
601
default:
602
g_assert_not_reached();
603
@@ -XXX,XX +XXX,XX @@ static void tcg_target_qemu_prologue(TCGContext *s)
604
static void tcg_target_init(TCGContext *s)
605
{
606
tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffff;
607
- if (TCG_TARGET_REG_BITS == 64) {
608
- tcg_target_available_regs[TCG_TYPE_I64] = 0xffffffff;
609
- }
610
+ tcg_target_available_regs[TCG_TYPE_I64] = 0xffffffff;
611
612
tcg_target_call_clobber_regs = -1u;
613
tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S0);
614
--
615
2.34.1
616
617
diff view generated by jsdifflib
New patch
[PULL 34/42] tcg/riscv: Rationalize args to tcg_out_qemu_{ld,st}
1
Interpret the variable argument placement in the caller. Pass data_type
2
instead of is64 -- there are several places where we already convert back
3
from bool to type. Clean things up by using type throughout.
1
4
5
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
6
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
---
9
tcg/riscv/tcg-target.c.inc | 66 ++++++++++++++------------------------
10
1 file changed, 24 insertions(+), 42 deletions(-)
11
12
diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
13
index XXXXXXX..XXXXXXX 100644
14
--- a/tcg/riscv/tcg-target.c.inc
15
+++ b/tcg/riscv/tcg-target.c.inc
16
@@ -XXX,XX +XXX,XX @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
17
#endif /* CONFIG_SOFTMMU */
18
19
static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg val,
20
- TCGReg base, MemOp opc, bool is_64)
21
+ TCGReg base, MemOp opc, TCGType type)
22
{
23
/* Byte swapping is left to middle-end expansion. */
24
tcg_debug_assert((opc & MO_BSWAP) == 0);
25
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg val,
26
tcg_out_opc_imm(s, OPC_LH, val, base, 0);
27
break;
28
case MO_UL:
29
- if (is_64) {
30
+ if (type == TCG_TYPE_I64) {
31
tcg_out_opc_imm(s, OPC_LWU, val, base, 0);
32
break;
33
}
34
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg val,
35
}
36
}
37
38
-static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64)
39
+static void tcg_out_qemu_ld(TCGContext *s, TCGReg data_reg, TCGReg addr_reg,
40
+ MemOpIdx oi, TCGType data_type)
41
{
42
- TCGReg addr_reg, data_reg;
43
- MemOpIdx oi;
44
- MemOp opc;
45
-#if defined(CONFIG_SOFTMMU)
46
- tcg_insn_unit *label_ptr[1];
47
-#else
48
- unsigned a_bits;
49
-#endif
50
+ MemOp opc = get_memop(oi);
51
TCGReg base;
52
53
- data_reg = *args++;
54
- addr_reg = *args++;
55
- oi = *args++;
56
- opc = get_memop(oi);
57
-
58
#if defined(CONFIG_SOFTMMU)
59
+ tcg_insn_unit *label_ptr[1];
60
+
61
base = tcg_out_tlb_load(s, addr_reg, oi, label_ptr, 1);
62
- tcg_out_qemu_ld_direct(s, data_reg, base, opc, is_64);
63
- add_qemu_ldst_label(s, 1, oi, (is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32),
64
- data_reg, addr_reg, s->code_ptr, label_ptr);
65
+ tcg_out_qemu_ld_direct(s, data_reg, base, opc, data_type);
66
+ add_qemu_ldst_label(s, true, oi, data_type, data_reg, addr_reg,
67
+ s->code_ptr, label_ptr);
68
#else
69
- a_bits = get_alignment_bits(opc);
70
+ unsigned a_bits = get_alignment_bits(opc);
71
if (a_bits) {
72
tcg_out_test_alignment(s, true, addr_reg, a_bits);
73
}
74
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64)
75
tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP0, TCG_GUEST_BASE_REG, base);
76
base = TCG_REG_TMP0;
77
}
78
- tcg_out_qemu_ld_direct(s, data_reg, base, opc, is_64);
79
+ tcg_out_qemu_ld_direct(s, data_reg, base, opc, data_type);
80
#endif
81
}
82
83
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg val,
84
}
85
}
86
87
-static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64)
88
+static void tcg_out_qemu_st(TCGContext *s, TCGReg data_reg, TCGReg addr_reg,
89
+ MemOpIdx oi, TCGType data_type)
90
{
91
- TCGReg addr_reg, data_reg;
92
- MemOpIdx oi;
93
- MemOp opc;
94
-#if defined(CONFIG_SOFTMMU)
95
- tcg_insn_unit *label_ptr[1];
96
-#else
97
- unsigned a_bits;
98
-#endif
99
+ MemOp opc = get_memop(oi);
100
TCGReg base;
101
102
- data_reg = *args++;
103
- addr_reg = *args++;
104
- oi = *args++;
105
- opc = get_memop(oi);
106
-
107
#if defined(CONFIG_SOFTMMU)
108
+ tcg_insn_unit *label_ptr[1];
109
+
110
base = tcg_out_tlb_load(s, addr_reg, oi, label_ptr, 0);
111
tcg_out_qemu_st_direct(s, data_reg, base, opc);
112
- add_qemu_ldst_label(s, 0, oi, (is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32),
113
- data_reg, addr_reg, s->code_ptr, label_ptr);
114
+ add_qemu_ldst_label(s, false, oi, data_type, data_reg, addr_reg,
115
+ s->code_ptr, label_ptr);
116
#else
117
- a_bits = get_alignment_bits(opc);
118
+ unsigned a_bits = get_alignment_bits(opc);
119
if (a_bits) {
120
tcg_out_test_alignment(s, false, addr_reg, a_bits);
121
}
122
@@ -XXX,XX +XXX,XX @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
123
break;
124
125
case INDEX_op_qemu_ld_i32:
126
- tcg_out_qemu_ld(s, args, false);
127
+ tcg_out_qemu_ld(s, a0, a1, a2, TCG_TYPE_I32);
128
break;
129
case INDEX_op_qemu_ld_i64:
130
- tcg_out_qemu_ld(s, args, true);
131
+ tcg_out_qemu_ld(s, a0, a1, a2, TCG_TYPE_I64);
132
break;
133
case INDEX_op_qemu_st_i32:
134
- tcg_out_qemu_st(s, args, false);
135
+ tcg_out_qemu_st(s, a0, a1, a2, TCG_TYPE_I32);
136
break;
137
case INDEX_op_qemu_st_i64:
138
- tcg_out_qemu_st(s, args, true);
139
+ tcg_out_qemu_st(s, a0, a1, a2, TCG_TYPE_I64);
140
break;
141
142
case INDEX_op_extrh_i64_i32:
143
--
144
2.34.1
145
146
diff view generated by jsdifflib
New patch
[PULL 35/42] tcg/s390x: Pass TCGType to tcg_out_qemu_{ld,st}
1
We need to set this in TCGLabelQemuLdst, so plumb this
2
all the way through from tcg_out_op.
1
3
4
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
---
7
tcg/s390x/tcg-target.c.inc | 22 ++++++++++++++--------
8
1 file changed, 14 insertions(+), 8 deletions(-)
9
10
diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc
11
index XXXXXXX..XXXXXXX 100644
12
--- a/tcg/s390x/tcg-target.c.inc
13
+++ b/tcg/s390x/tcg-target.c.inc
14
@@ -XXX,XX +XXX,XX @@ static TCGReg tcg_out_tlb_read(TCGContext *s, TCGReg addr_reg, MemOp opc,
15
}
16
17
static void add_qemu_ldst_label(TCGContext *s, bool is_ld, MemOpIdx oi,
18
- TCGReg data, TCGReg addr,
19
+ TCGType type, TCGReg data, TCGReg addr,
20
tcg_insn_unit *raddr, tcg_insn_unit *label_ptr)
21
{
22
TCGLabelQemuLdst *label = new_ldst_label(s);
23
24
label->is_ld = is_ld;
25
label->oi = oi;
26
+ label->type = type;
27
label->datalo_reg = data;
28
label->addrlo_reg = addr;
29
label->raddr = tcg_splitwx_to_rx(raddr);
30
@@ -XXX,XX +XXX,XX @@ static void tcg_prepare_user_ldst(TCGContext *s, TCGReg *addr_reg,
31
#endif /* CONFIG_SOFTMMU */
32
33
static void tcg_out_qemu_ld(TCGContext* s, TCGReg data_reg, TCGReg addr_reg,
34
- MemOpIdx oi)
35
+ MemOpIdx oi, TCGType data_type)
36
{
37
MemOp opc = get_memop(oi);
38
#ifdef CONFIG_SOFTMMU
39
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_ld(TCGContext* s, TCGReg data_reg, TCGReg addr_reg,
40
41
tcg_out_qemu_ld_direct(s, opc, data_reg, base_reg, TCG_REG_R2, 0);
42
43
- add_qemu_ldst_label(s, 1, oi, data_reg, addr_reg, s->code_ptr, label_ptr);
44
+ add_qemu_ldst_label(s, true, oi, data_type, data_reg, addr_reg,
45
+ s->code_ptr, label_ptr);
46
#else
47
TCGReg index_reg;
48
tcg_target_long disp;
49
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_ld(TCGContext* s, TCGReg data_reg, TCGReg addr_reg,
50
}
51
52
static void tcg_out_qemu_st(TCGContext* s, TCGReg data_reg, TCGReg addr_reg,
53
- MemOpIdx oi)
54
+ MemOpIdx oi, TCGType data_type)
55
{
56
MemOp opc = get_memop(oi);
57
#ifdef CONFIG_SOFTMMU
58
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_st(TCGContext* s, TCGReg data_reg, TCGReg addr_reg,
59
60
tcg_out_qemu_st_direct(s, opc, data_reg, base_reg, TCG_REG_R2, 0);
61
62
- add_qemu_ldst_label(s, 0, oi, data_reg, addr_reg, s->code_ptr, label_ptr);
63
+ add_qemu_ldst_label(s, false, oi, data_type, data_reg, addr_reg,
64
+ s->code_ptr, label_ptr);
65
#else
66
TCGReg index_reg;
67
tcg_target_long disp;
68
@@ -XXX,XX +XXX,XX @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
69
break;
70
71
case INDEX_op_qemu_ld_i32:
72
- /* ??? Technically we can use a non-extending instruction. */
73
+ tcg_out_qemu_ld(s, args[0], args[1], args[2], TCG_TYPE_I32);
74
+ break;
75
case INDEX_op_qemu_ld_i64:
76
- tcg_out_qemu_ld(s, args[0], args[1], args[2]);
77
+ tcg_out_qemu_ld(s, args[0], args[1], args[2], TCG_TYPE_I64);
78
break;
79
case INDEX_op_qemu_st_i32:
80
+ tcg_out_qemu_st(s, args[0], args[1], args[2], TCG_TYPE_I32);
81
+ break;
82
case INDEX_op_qemu_st_i64:
83
- tcg_out_qemu_st(s, args[0], args[1], args[2]);
84
+ tcg_out_qemu_st(s, args[0], args[1], args[2], TCG_TYPE_I64);
85
break;
86
87
case INDEX_op_ld16s_i64:
88
--
89
2.34.1
90
91
diff view generated by jsdifflib
New patch
[PULL 36/42] tcg/s390x: Introduce HostAddress
1
1
Collect the 3 potential parts of the host address into a struct.
2
Reorg tcg_out_qemu_{ld,st}_direct to use it.
3
4
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
---
7
tcg/s390x/tcg-target.c.inc | 109 ++++++++++++++++++++-----------------
8
1 file changed, 60 insertions(+), 49 deletions(-)
9
10
diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc
11
index XXXXXXX..XXXXXXX 100644
12
--- a/tcg/s390x/tcg-target.c.inc
13
+++ b/tcg/s390x/tcg-target.c.inc
14
@@ -XXX,XX +XXX,XX @@ static void tcg_out_call(TCGContext *s, const tcg_insn_unit *dest,
15
tcg_out_call_int(s, dest);
16
}
17
18
+typedef struct {
19
+ TCGReg base;
20
+ TCGReg index;
21
+ int disp;
22
+} HostAddress;
23
+
24
static void tcg_out_qemu_ld_direct(TCGContext *s, MemOp opc, TCGReg data,
25
- TCGReg base, TCGReg index, int disp)
26
+ HostAddress h)
27
{
28
switch (opc & (MO_SSIZE | MO_BSWAP)) {
29
case MO_UB:
30
- tcg_out_insn(s, RXY, LLGC, data, base, index, disp);
31
+ tcg_out_insn(s, RXY, LLGC, data, h.base, h.index, h.disp);
32
break;
33
case MO_SB:
34
- tcg_out_insn(s, RXY, LGB, data, base, index, disp);
35
+ tcg_out_insn(s, RXY, LGB, data, h.base, h.index, h.disp);
36
break;
37
38
case MO_UW | MO_BSWAP:
39
/* swapped unsigned halfword load with upper bits zeroed */
40
- tcg_out_insn(s, RXY, LRVH, data, base, index, disp);
41
+ tcg_out_insn(s, RXY, LRVH, data, h.base, h.index, h.disp);
42
tcg_out_ext16u(s, data, data);
43
break;
44
case MO_UW:
45
- tcg_out_insn(s, RXY, LLGH, data, base, index, disp);
46
+ tcg_out_insn(s, RXY, LLGH, data, h.base, h.index, h.disp);
47
break;
48
49
case MO_SW | MO_BSWAP:
50
/* swapped sign-extended halfword load */
51
- tcg_out_insn(s, RXY, LRVH, data, base, index, disp);
52
+ tcg_out_insn(s, RXY, LRVH, data, h.base, h.index, h.disp);
53
tcg_out_ext16s(s, TCG_TYPE_REG, data, data);
54
break;
55
case MO_SW:
56
- tcg_out_insn(s, RXY, LGH, data, base, index, disp);
57
+ tcg_out_insn(s, RXY, LGH, data, h.base, h.index, h.disp);
58
break;
59
60
case MO_UL | MO_BSWAP:
61
/* swapped unsigned int load with upper bits zeroed */
62
- tcg_out_insn(s, RXY, LRV, data, base, index, disp);
63
+ tcg_out_insn(s, RXY, LRV, data, h.base, h.index, h.disp);
64
tcg_out_ext32u(s, data, data);
65
break;
66
case MO_UL:
67
- tcg_out_insn(s, RXY, LLGF, data, base, index, disp);
68
+ tcg_out_insn(s, RXY, LLGF, data, h.base, h.index, h.disp);
69
break;
70
71
case MO_SL | MO_BSWAP:
72
/* swapped sign-extended int load */
73
- tcg_out_insn(s, RXY, LRV, data, base, index, disp);
74
+ tcg_out_insn(s, RXY, LRV, data, h.base, h.index, h.disp);
75
tcg_out_ext32s(s, data, data);
76
break;
77
case MO_SL:
78
- tcg_out_insn(s, RXY, LGF, data, base, index, disp);
79
+ tcg_out_insn(s, RXY, LGF, data, h.base, h.index, h.disp);
80
break;
81
82
case MO_UQ | MO_BSWAP:
83
- tcg_out_insn(s, RXY, LRVG, data, base, index, disp);
84
+ tcg_out_insn(s, RXY, LRVG, data, h.base, h.index, h.disp);
85
break;
86
case MO_UQ:
87
- tcg_out_insn(s, RXY, LG, data, base, index, disp);
88
+ tcg_out_insn(s, RXY, LG, data, h.base, h.index, h.disp);
89
break;
90
91
default:
92
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_ld_direct(TCGContext *s, MemOp opc, TCGReg data,
93
}
94
95
static void tcg_out_qemu_st_direct(TCGContext *s, MemOp opc, TCGReg data,
96
- TCGReg base, TCGReg index, int disp)
97
+ HostAddress h)
98
{
99
switch (opc & (MO_SIZE | MO_BSWAP)) {
100
case MO_UB:
101
- if (disp >= 0 && disp < 0x1000) {
102
- tcg_out_insn(s, RX, STC, data, base, index, disp);
103
+ if (h.disp >= 0 && h.disp < 0x1000) {
104
+ tcg_out_insn(s, RX, STC, data, h.base, h.index, h.disp);
105
} else {
106
- tcg_out_insn(s, RXY, STCY, data, base, index, disp);
107
+ tcg_out_insn(s, RXY, STCY, data, h.base, h.index, h.disp);
108
}
109
break;
110
111
case MO_UW | MO_BSWAP:
112
- tcg_out_insn(s, RXY, STRVH, data, base, index, disp);
113
+ tcg_out_insn(s, RXY, STRVH, data, h.base, h.index, h.disp);
114
break;
115
case MO_UW:
116
- if (disp >= 0 && disp < 0x1000) {
117
- tcg_out_insn(s, RX, STH, data, base, index, disp);
118
+ if (h.disp >= 0 && h.disp < 0x1000) {
119
+ tcg_out_insn(s, RX, STH, data, h.base, h.index, h.disp);
120
} else {
121
- tcg_out_insn(s, RXY, STHY, data, base, index, disp);
122
+ tcg_out_insn(s, RXY, STHY, data, h.base, h.index, h.disp);
123
}
124
break;
125
126
case MO_UL | MO_BSWAP:
127
- tcg_out_insn(s, RXY, STRV, data, base, index, disp);
128
+ tcg_out_insn(s, RXY, STRV, data, h.base, h.index, h.disp);
129
break;
130
case MO_UL:
131
- if (disp >= 0 && disp < 0x1000) {
132
- tcg_out_insn(s, RX, ST, data, base, index, disp);
133
+ if (h.disp >= 0 && h.disp < 0x1000) {
134
+ tcg_out_insn(s, RX, ST, data, h.base, h.index, h.disp);
135
} else {
136
- tcg_out_insn(s, RXY, STY, data, base, index, disp);
137
+ tcg_out_insn(s, RXY, STY, data, h.base, h.index, h.disp);
138
}
139
break;
140
141
case MO_UQ | MO_BSWAP:
142
- tcg_out_insn(s, RXY, STRVG, data, base, index, disp);
143
+ tcg_out_insn(s, RXY, STRVG, data, h.base, h.index, h.disp);
144
break;
145
case MO_UQ:
146
- tcg_out_insn(s, RXY, STG, data, base, index, disp);
147
+ tcg_out_insn(s, RXY, STG, data, h.base, h.index, h.disp);
148
break;
149
150
default:
151
@@ -XXX,XX +XXX,XX @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
152
return tcg_out_fail_alignment(s, l);
153
}
154
155
-static void tcg_prepare_user_ldst(TCGContext *s, TCGReg *addr_reg,
156
- TCGReg *index_reg, tcg_target_long *disp)
157
+static HostAddress tcg_prepare_user_ldst(TCGContext *s, TCGReg addr_reg)
158
{
159
+ TCGReg index;
160
+ int disp;
161
+
162
if (TARGET_LONG_BITS == 32) {
163
- tcg_out_ext32u(s, TCG_TMP0, *addr_reg);
164
- *addr_reg = TCG_TMP0;
165
+ tcg_out_ext32u(s, TCG_TMP0, addr_reg);
166
+ addr_reg = TCG_TMP0;
167
}
168
if (guest_base < 0x80000) {
169
- *index_reg = TCG_REG_NONE;
170
- *disp = guest_base;
171
+ index = TCG_REG_NONE;
172
+ disp = guest_base;
173
} else {
174
- *index_reg = TCG_GUEST_BASE_REG;
175
- *disp = 0;
176
+ index = TCG_GUEST_BASE_REG;
177
+ disp = 0;
178
}
179
+ return (HostAddress){ .base = addr_reg, .index = index, .disp = disp };
180
}
181
#endif /* CONFIG_SOFTMMU */
182
183
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_ld(TCGContext* s, TCGReg data_reg, TCGReg addr_reg,
184
MemOpIdx oi, TCGType data_type)
185
{
186
MemOp opc = get_memop(oi);
187
+ HostAddress h;
188
+
189
#ifdef CONFIG_SOFTMMU
190
unsigned mem_index = get_mmuidx(oi);
191
tcg_insn_unit *label_ptr;
192
- TCGReg base_reg;
193
194
- base_reg = tcg_out_tlb_read(s, addr_reg, opc, mem_index, 1);
195
+ h.base = tcg_out_tlb_read(s, addr_reg, opc, mem_index, 1);
196
+ h.index = TCG_REG_R2;
197
+ h.disp = 0;
198
199
tcg_out16(s, RI_BRC | (S390_CC_NE << 4));
200
label_ptr = s->code_ptr;
201
s->code_ptr += 1;
202
203
- tcg_out_qemu_ld_direct(s, opc, data_reg, base_reg, TCG_REG_R2, 0);
204
+ tcg_out_qemu_ld_direct(s, opc, data_reg, h);
205
206
add_qemu_ldst_label(s, true, oi, data_type, data_reg, addr_reg,
207
s->code_ptr, label_ptr);
208
#else
209
- TCGReg index_reg;
210
- tcg_target_long disp;
211
unsigned a_bits = get_alignment_bits(opc);
212
213
if (a_bits) {
214
tcg_out_test_alignment(s, true, addr_reg, a_bits);
215
}
216
- tcg_prepare_user_ldst(s, &addr_reg, &index_reg, &disp);
217
- tcg_out_qemu_ld_direct(s, opc, data_reg, addr_reg, index_reg, disp);
218
+ h = tcg_prepare_user_ldst(s, addr_reg);
219
+ tcg_out_qemu_ld_direct(s, opc, data_reg, h);
220
#endif
221
}
222
223
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_st(TCGContext* s, TCGReg data_reg, TCGReg addr_reg,
224
MemOpIdx oi, TCGType data_type)
225
{
226
MemOp opc = get_memop(oi);
227
+ HostAddress h;
228
+
229
#ifdef CONFIG_SOFTMMU
230
unsigned mem_index = get_mmuidx(oi);
231
tcg_insn_unit *label_ptr;
232
- TCGReg base_reg;
233
234
- base_reg = tcg_out_tlb_read(s, addr_reg, opc, mem_index, 0);
235
+ h.base = tcg_out_tlb_read(s, addr_reg, opc, mem_index, 0);
236
+ h.index = TCG_REG_R2;
237
+ h.disp = 0;
238
239
tcg_out16(s, RI_BRC | (S390_CC_NE << 4));
240
label_ptr = s->code_ptr;
241
s->code_ptr += 1;
242
243
- tcg_out_qemu_st_direct(s, opc, data_reg, base_reg, TCG_REG_R2, 0);
244
+ tcg_out_qemu_st_direct(s, opc, data_reg, h);
245
246
add_qemu_ldst_label(s, false, oi, data_type, data_reg, addr_reg,
247
s->code_ptr, label_ptr);
248
#else
249
- TCGReg index_reg;
250
- tcg_target_long disp;
251
unsigned a_bits = get_alignment_bits(opc);
252
253
if (a_bits) {
254
tcg_out_test_alignment(s, false, addr_reg, a_bits);
255
}
256
- tcg_prepare_user_ldst(s, &addr_reg, &index_reg, &disp);
257
- tcg_out_qemu_st_direct(s, opc, data_reg, addr_reg, index_reg, disp);
258
+ h = tcg_prepare_user_ldst(s, addr_reg);
259
+ tcg_out_qemu_st_direct(s, opc, data_reg, h);
260
#endif
261
}
262
263
--
264
2.34.1
265
266
diff view generated by jsdifflib
New patch
[PULL 37/42] tcg/sparc64: Drop is_64 test from tcg_out_qemu_ld data return
1
In tcg_canonicalize_memop, we remove MO_SIGN from MO_32 operations
2
with TCG_TYPE_I32. Thus this is never set. We already have an
3
identical test just above which does not include is_64
1
4
5
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
---
8
tcg/sparc64/tcg-target.c.inc | 2 +-
9
1 file changed, 1 insertion(+), 1 deletion(-)
10
11
diff --git a/tcg/sparc64/tcg-target.c.inc b/tcg/sparc64/tcg-target.c.inc
12
index XXXXXXX..XXXXXXX 100644
13
--- a/tcg/sparc64/tcg-target.c.inc
14
+++ b/tcg/sparc64/tcg-target.c.inc
15
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg data, TCGReg addr,
16
tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_O2, oi);
17
18
/* We let the helper sign-extend SB and SW, but leave SL for here. */
19
- if (is_64 && (memop & MO_SSIZE) == MO_SL) {
20
+ if ((memop & MO_SSIZE) == MO_SL) {
21
tcg_out_ext32s(s, data, TCG_REG_O0);
22
} else {
23
tcg_out_mov(s, TCG_TYPE_REG, data, TCG_REG_O0);
24
--
25
2.34.1
26
27
diff view generated by jsdifflib
New patch
[PULL 38/42] tcg/sparc64: Pass TCGType to tcg_out_qemu_{ld,st}
1
We need to set this in TCGLabelQemuLdst, so plumb this
2
all the way through from tcg_out_op.
1
3
4
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
---
7
tcg/sparc64/tcg-target.c.inc | 6 +++---
8
1 file changed, 3 insertions(+), 3 deletions(-)
9
10
diff --git a/tcg/sparc64/tcg-target.c.inc b/tcg/sparc64/tcg-target.c.inc
11
index XXXXXXX..XXXXXXX 100644
12
--- a/tcg/sparc64/tcg-target.c.inc
13
+++ b/tcg/sparc64/tcg-target.c.inc
14
@@ -XXX,XX +XXX,XX @@ static const int qemu_st_opc[(MO_SIZE | MO_BSWAP) + 1] = {
15
};
16
17
static void tcg_out_qemu_ld(TCGContext *s, TCGReg data, TCGReg addr,
18
- MemOpIdx oi, bool is_64)
19
+ MemOpIdx oi, TCGType data_type)
20
{
21
MemOp memop = get_memop(oi);
22
tcg_insn_unit *label_ptr;
23
@@ -XXX,XX +XXX,XX @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
24
break;
25
26
case INDEX_op_qemu_ld_i32:
27
- tcg_out_qemu_ld(s, a0, a1, a2, false);
28
+ tcg_out_qemu_ld(s, a0, a1, a2, TCG_TYPE_I32);
29
break;
30
case INDEX_op_qemu_ld_i64:
31
- tcg_out_qemu_ld(s, a0, a1, a2, true);
32
+ tcg_out_qemu_ld(s, a0, a1, a2, TCG_TYPE_I64);
33
break;
34
case INDEX_op_qemu_st_i32:
35
tcg_out_qemu_st(s, a0, a1, a2, TCG_TYPE_I32);
36
--
37
2.34.1
38
39
diff view generated by jsdifflib
New patch
[PULL 39/42] tcg: Move TCGLabelQemuLdst to tcg.c
1
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
3
---
4
tcg/tcg.c | 13 +++++++++++++
5
tcg/tcg-ldst.c.inc | 14 --------------
6
2 files changed, 13 insertions(+), 14 deletions(-)
1
7
8
diff --git a/tcg/tcg.c b/tcg/tcg.c
9
index XXXXXXX..XXXXXXX 100644
10
--- a/tcg/tcg.c
11
+++ b/tcg/tcg.c
12
@@ -XXX,XX +XXX,XX @@ typedef struct QEMU_PACKED {
13
DebugFrameFDEHeader fde;
14
} DebugFrameHeader;
15
16
+typedef struct TCGLabelQemuLdst {
17
+ bool is_ld; /* qemu_ld: true, qemu_st: false */
18
+ MemOpIdx oi;
19
+ TCGType type; /* result type of a load */
20
+ TCGReg addrlo_reg; /* reg index for low word of guest virtual addr */
21
+ TCGReg addrhi_reg; /* reg index for high word of guest virtual addr */
22
+ TCGReg datalo_reg; /* reg index for low word to be loaded or stored */
23
+ TCGReg datahi_reg; /* reg index for high word to be loaded or stored */
24
+ const tcg_insn_unit *raddr; /* addr of the next IR of qemu_ld/st IR */
25
+ tcg_insn_unit *label_ptr[2]; /* label pointers to be updated */
26
+ QSIMPLEQ_ENTRY(TCGLabelQemuLdst) next;
27
+} TCGLabelQemuLdst;
28
+
29
static void tcg_register_jit_int(const void *buf, size_t size,
30
const void *debug_frame,
31
size_t debug_frame_size)
32
diff --git a/tcg/tcg-ldst.c.inc b/tcg/tcg-ldst.c.inc
33
index XXXXXXX..XXXXXXX 100644
34
--- a/tcg/tcg-ldst.c.inc
35
+++ b/tcg/tcg-ldst.c.inc
36
@@ -XXX,XX +XXX,XX @@
37
* THE SOFTWARE.
38
*/
39
40
-typedef struct TCGLabelQemuLdst {
41
- bool is_ld; /* qemu_ld: true, qemu_st: false */
42
- MemOpIdx oi;
43
- TCGType type; /* result type of a load */
44
- TCGReg addrlo_reg; /* reg index for low word of guest virtual addr */
45
- TCGReg addrhi_reg; /* reg index for high word of guest virtual addr */
46
- TCGReg datalo_reg; /* reg index for low word to be loaded or stored */
47
- TCGReg datahi_reg; /* reg index for high word to be loaded or stored */
48
- const tcg_insn_unit *raddr; /* addr of the next IR of qemu_ld/st IR */
49
- tcg_insn_unit *label_ptr[2]; /* label pointers to be updated */
50
- QSIMPLEQ_ENTRY(TCGLabelQemuLdst) next;
51
-} TCGLabelQemuLdst;
52
-
53
-
54
/*
55
* Generate TB finalization at the end of block
56
*/
57
--
58
2.34.1
59
60
diff view generated by jsdifflib
New patch
[PULL 40/42] tcg: Replace REG_P with arg_loc_reg_p
1
An inline function is safer than a macro, and REG_P
2
was rather too generic.
1
3
4
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
---
7
tcg/tcg-internal.h | 4 ----
8
tcg/tcg.c | 16 +++++++++++++---
9
2 files changed, 13 insertions(+), 7 deletions(-)
10
11
diff --git a/tcg/tcg-internal.h b/tcg/tcg-internal.h
12
index XXXXXXX..XXXXXXX 100644
13
--- a/tcg/tcg-internal.h
14
+++ b/tcg/tcg-internal.h
15
@@ -XXX,XX +XXX,XX @@ typedef struct TCGCallArgumentLoc {
16
unsigned tmp_subindex : 2;
17
} TCGCallArgumentLoc;
18
19
-/* Avoid "unsigned < 0 is always false" Werror, when iarg_regs is empty. */
20
-#define REG_P(L) \
21
- ((int)(L)->arg_slot < (int)ARRAY_SIZE(tcg_target_call_iarg_regs))
22
-
23
typedef struct TCGHelperInfo {
24
void *func;
25
const char *name;
26
diff --git a/tcg/tcg.c b/tcg/tcg.c
27
index XXXXXXX..XXXXXXX 100644
28
--- a/tcg/tcg.c
29
+++ b/tcg/tcg.c
30
@@ -XXX,XX +XXX,XX @@ static void init_ffi_layouts(void)
31
}
32
#endif /* CONFIG_TCG_INTERPRETER */
33
34
+static inline bool arg_slot_reg_p(unsigned arg_slot)
35
+{
36
+ /*
37
+ * Split the sizeof away from the comparison to avoid Werror from
38
+ * "unsigned < 0 is always false", when iarg_regs is empty.
39
+ */
40
+ unsigned nreg = ARRAY_SIZE(tcg_target_call_iarg_regs);
41
+ return arg_slot < nreg;
42
+}
43
+
44
typedef struct TCGCumulativeArgs {
45
int arg_idx; /* tcg_gen_callN args[] */
46
int info_in_idx; /* TCGHelperInfo in[] */
47
@@ -XXX,XX +XXX,XX @@ liveness_pass_1(TCGContext *s)
48
case TCG_CALL_ARG_NORMAL:
49
case TCG_CALL_ARG_EXTEND_U:
50
case TCG_CALL_ARG_EXTEND_S:
51
- if (REG_P(loc)) {
52
+ if (arg_slot_reg_p(loc->arg_slot)) {
53
*la_temp_pref(ts) = 0;
54
break;
55
}
56
@@ -XXX,XX +XXX,XX @@ liveness_pass_1(TCGContext *s)
57
case TCG_CALL_ARG_NORMAL:
58
case TCG_CALL_ARG_EXTEND_U:
59
case TCG_CALL_ARG_EXTEND_S:
60
- if (REG_P(loc)) {
61
+ if (arg_slot_reg_p(loc->arg_slot)) {
62
tcg_regset_set_reg(*la_temp_pref(ts),
63
tcg_target_call_iarg_regs[loc->arg_slot]);
64
}
65
@@ -XXX,XX +XXX,XX @@ static void load_arg_stk(TCGContext *s, int stk_slot, TCGTemp *ts,
66
static void load_arg_normal(TCGContext *s, const TCGCallArgumentLoc *l,
67
TCGTemp *ts, TCGRegSet *allocated_regs)
68
{
69
- if (REG_P(l)) {
70
+ if (arg_slot_reg_p(l->arg_slot)) {
71
TCGReg reg = tcg_target_call_iarg_regs[l->arg_slot];
72
load_arg_reg(s, reg, ts, *allocated_regs);
73
tcg_regset_set_reg(*allocated_regs, reg);
74
--
75
2.34.1
76
77
diff view generated by jsdifflib
[PULL 3/3] accel/tcg: rename tcg-cpus functions to match module name
[PULL 41/42] tcg: Introduce arg_slot_stk_ofs
1
From: Claudio Fontana <cfontana@suse.de>
1
Unify all computation of argument stack offset in one function.
2
This requires that we adjust ref_slot to be in the same units,
3
by adding max_reg_slots during init_call_layout.
2
4
3
Signed-off-by: Claudio Fontana <cfontana@suse.de>
5
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
4
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
5
Message-Id: <20201015143217.29337-4-cfontana@suse.de>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
---
7
---
8
accel/tcg/tcg-cpus-icount.h | 6 +--
8
tcg/tcg.c | 29 +++++++++++++++++------------
9
accel/tcg/tcg-cpus-rr.h | 2 +-
9
1 file changed, 17 insertions(+), 12 deletions(-)
10
accel/tcg/tcg-cpus.h | 6 +--
11
accel/tcg/tcg-cpus-icount.c | 24 ++++++------
12
accel/tcg/tcg-cpus-mttcg.c | 10 ++---
13
accel/tcg/tcg-cpus-rr.c | 74 ++++++++++++++++++-------------------
14
accel/tcg/tcg-cpus.c | 6 +--
15
7 files changed, 64 insertions(+), 64 deletions(-)
16
10
17
diff --git a/accel/tcg/tcg-cpus-icount.h b/accel/tcg/tcg-cpus-icount.h
11
diff --git a/tcg/tcg.c b/tcg/tcg.c
18
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
19
--- a/accel/tcg/tcg-cpus-icount.h
13
--- a/tcg/tcg.c
20
+++ b/accel/tcg/tcg-cpus-icount.h
14
+++ b/tcg/tcg.c
21
@@ -XXX,XX +XXX,XX @@
15
@@ -XXX,XX +XXX,XX @@ static inline bool arg_slot_reg_p(unsigned arg_slot)
22
#ifndef TCG_CPUS_ICOUNT_H
16
return arg_slot < nreg;
23
#define TCG_CPUS_ICOUNT_H
17
}
24
18
25
-void handle_icount_deadline(void);
19
+static inline int arg_slot_stk_ofs(unsigned arg_slot)
26
-void prepare_icount_for_run(CPUState *cpu);
20
+{
27
-void process_icount_data(CPUState *cpu);
21
+ unsigned max = TCG_STATIC_CALL_ARGS_SIZE / sizeof(tcg_target_long);
28
+void icount_handle_deadline(void);
22
+ unsigned stk_slot = arg_slot - ARRAY_SIZE(tcg_target_call_iarg_regs);
29
+void icount_prepare_for_run(CPUState *cpu);
23
+
30
+void icount_process_data(CPUState *cpu);
24
+ tcg_debug_assert(stk_slot < max);
31
25
+ return TCG_TARGET_CALL_STACK_OFFSET + stk_slot * sizeof(tcg_target_long);
32
#endif /* TCG_CPUS_ICOUNT_H */
26
+}
33
diff --git a/accel/tcg/tcg-cpus-rr.h b/accel/tcg/tcg-cpus-rr.h
27
+
34
index XXXXXXX..XXXXXXX 100644
28
typedef struct TCGCumulativeArgs {
35
--- a/accel/tcg/tcg-cpus-rr.h
29
int arg_idx; /* tcg_gen_callN args[] */
36
+++ b/accel/tcg/tcg-cpus-rr.h
30
int info_in_idx; /* TCGHelperInfo in[] */
37
@@ -XXX,XX +XXX,XX @@
31
@@ -XXX,XX +XXX,XX @@ static void init_call_layout(TCGHelperInfo *info)
38
#define TCG_KICK_PERIOD (NANOSECONDS_PER_SECOND / 10)
32
}
39
33
}
40
/* Kick all RR vCPUs. */
34
assert(ref_base + cum.ref_slot <= max_stk_slots);
41
-void qemu_cpu_kick_rr_cpus(CPUState *unused);
35
+ ref_base += max_reg_slots;
42
+void rr_kick_vcpu_thread(CPUState *unused);
36
43
37
if (ref_base != 0) {
44
/* start the round robin vcpu thread */
38
for (int i = cum.info_in_idx - 1; i >= 0; --i) {
45
void rr_start_vcpu_thread(CPUState *cpu);
39
@@ -XXX,XX +XXX,XX @@ static void load_arg_reg(TCGContext *s, TCGReg reg, TCGTemp *ts,
46
diff --git a/accel/tcg/tcg-cpus.h b/accel/tcg/tcg-cpus.h
47
index XXXXXXX..XXXXXXX 100644
48
--- a/accel/tcg/tcg-cpus.h
49
+++ b/accel/tcg/tcg-cpus.h
50
@@ -XXX,XX +XXX,XX @@ extern const CpusAccel tcg_cpus_mttcg;
51
extern const CpusAccel tcg_cpus_icount;
52
extern const CpusAccel tcg_cpus_rr;
53
54
-void qemu_tcg_destroy_vcpu(CPUState *cpu);
55
-int tcg_cpu_exec(CPUState *cpu);
56
-void tcg_handle_interrupt(CPUState *cpu, int mask);
57
+void tcg_cpus_destroy(CPUState *cpu);
58
+int tcg_cpus_exec(CPUState *cpu);
59
+void tcg_cpus_handle_interrupt(CPUState *cpu, int mask);
60
61
#endif /* TCG_CPUS_H */
62
diff --git a/accel/tcg/tcg-cpus-icount.c b/accel/tcg/tcg-cpus-icount.c
63
index XXXXXXX..XXXXXXX 100644
64
--- a/accel/tcg/tcg-cpus-icount.c
65
+++ b/accel/tcg/tcg-cpus-icount.c
66
@@ -XXX,XX +XXX,XX @@
67
#include "tcg-cpus-icount.h"
68
#include "tcg-cpus-rr.h"
69
70
-static int64_t tcg_get_icount_limit(void)
71
+static int64_t icount_get_limit(void)
72
{
73
int64_t deadline;
74
75
@@ -XXX,XX +XXX,XX @@ static int64_t tcg_get_icount_limit(void)
76
}
40
}
77
}
41
}
78
42
79
-static void notify_aio_contexts(void)
43
-static void load_arg_stk(TCGContext *s, int stk_slot, TCGTemp *ts,
80
+static void icount_notify_aio_contexts(void)
44
+static void load_arg_stk(TCGContext *s, unsigned arg_slot, TCGTemp *ts,
45
TCGRegSet allocated_regs)
81
{
46
{
82
/* Wake up other AioContexts. */
47
/*
83
qemu_clock_notify(QEMU_CLOCK_VIRTUAL);
48
@@ -XXX,XX +XXX,XX @@ static void load_arg_stk(TCGContext *s, int stk_slot, TCGTemp *ts,
84
qemu_clock_run_timers(QEMU_CLOCK_VIRTUAL);
49
*/
50
temp_load(s, ts, tcg_target_available_regs[ts->type], allocated_regs, 0);
51
tcg_out_st(s, ts->type, ts->reg, TCG_REG_CALL_STACK,
52
- TCG_TARGET_CALL_STACK_OFFSET +
53
- stk_slot * sizeof(tcg_target_long));
54
+ arg_slot_stk_ofs(arg_slot));
85
}
55
}
86
56
87
-void handle_icount_deadline(void)
57
static void load_arg_normal(TCGContext *s, const TCGCallArgumentLoc *l,
88
+void icount_handle_deadline(void)
58
@@ -XXX,XX +XXX,XX @@ static void load_arg_normal(TCGContext *s, const TCGCallArgumentLoc *l,
89
{
59
load_arg_reg(s, reg, ts, *allocated_regs);
90
assert(qemu_in_vcpu_thread());
60
tcg_regset_set_reg(*allocated_regs, reg);
91
int64_t deadline = qemu_clock_deadline_ns_all(QEMU_CLOCK_VIRTUAL,
61
} else {
92
QEMU_TIMER_ATTR_ALL);
62
- load_arg_stk(s, l->arg_slot - ARRAY_SIZE(tcg_target_call_iarg_regs),
93
63
- ts, *allocated_regs);
94
if (deadline == 0) {
64
+ load_arg_stk(s, l->arg_slot, ts, *allocated_regs);
95
- notify_aio_contexts();
96
+ icount_notify_aio_contexts();
97
}
65
}
98
}
66
}
99
67
100
-void prepare_icount_for_run(CPUState *cpu)
68
-static void load_arg_ref(TCGContext *s, int arg_slot, TCGReg ref_base,
101
+void icount_prepare_for_run(CPUState *cpu)
69
+static void load_arg_ref(TCGContext *s, unsigned arg_slot, TCGReg ref_base,
70
intptr_t ref_off, TCGRegSet *allocated_regs)
102
{
71
{
103
int insns_left;
72
TCGReg reg;
104
73
- int stk_slot = arg_slot - ARRAY_SIZE(tcg_target_call_iarg_regs);
105
/*
74
106
- * These should always be cleared by process_icount_data after
75
- if (stk_slot < 0) {
107
+ * These should always be cleared by icount_process_data after
76
+ if (arg_slot_reg_p(arg_slot)) {
108
* each vCPU execution. However u16.high can be raised
77
reg = tcg_target_call_iarg_regs[arg_slot];
109
- * asynchronously by cpu_exit/cpu_interrupt/tcg_handle_interrupt
78
tcg_reg_free(s, reg, *allocated_regs);
110
+ * asynchronously by cpu_exit/cpu_interrupt/tcg_cpus_handle_interrupt
79
tcg_out_addi_ptr(s, reg, ref_base, ref_off);
111
*/
80
@@ -XXX,XX +XXX,XX @@ static void load_arg_ref(TCGContext *s, int arg_slot, TCGReg ref_base,
112
g_assert(cpu_neg(cpu)->icount_decr.u16.low == 0);
81
*allocated_regs, 0, false);
113
g_assert(cpu->icount_extra == 0);
82
tcg_out_addi_ptr(s, reg, ref_base, ref_off);
114
83
tcg_out_st(s, TCG_TYPE_PTR, reg, TCG_REG_CALL_STACK,
115
- cpu->icount_budget = tcg_get_icount_limit();
84
- TCG_TARGET_CALL_STACK_OFFSET
116
+ cpu->icount_budget = icount_get_limit();
85
- + stk_slot * sizeof(tcg_target_long));
117
insns_left = MIN(0xffff, cpu->icount_budget);
86
+ arg_slot_stk_ofs(arg_slot));
118
cpu_neg(cpu)->icount_decr.u16.low = insns_left;
119
cpu->icount_extra = cpu->icount_budget - insns_left;
120
@@ -XXX,XX +XXX,XX @@ void prepare_icount_for_run(CPUState *cpu)
121
replay_mutex_lock();
122
123
if (cpu->icount_budget == 0 && replay_has_checkpoint()) {
124
- notify_aio_contexts();
125
+ icount_notify_aio_contexts();
126
}
87
}
127
}
88
}
128
89
129
-void process_icount_data(CPUState *cpu)
90
@@ -XXX,XX +XXX,XX @@ static void tcg_reg_alloc_call(TCGContext *s, TCGOp *op)
130
+void icount_process_data(CPUState *cpu)
91
case TCG_CALL_ARG_BY_REF:
131
{
92
load_arg_stk(s, loc->ref_slot, ts, allocated_regs);
132
/* Account for executed instructions */
93
load_arg_ref(s, loc->arg_slot, TCG_REG_CALL_STACK,
133
icount_update(cpu);
94
- TCG_TARGET_CALL_STACK_OFFSET
134
@@ -XXX,XX +XXX,XX @@ static void icount_handle_interrupt(CPUState *cpu, int mask)
95
- + loc->ref_slot * sizeof(tcg_target_long),
135
{
96
+ arg_slot_stk_ofs(loc->ref_slot),
136
int old_mask = cpu->interrupt_request;
97
&allocated_regs);
137
138
- tcg_handle_interrupt(cpu, mask);
139
+ tcg_cpus_handle_interrupt(cpu, mask);
140
if (qemu_cpu_is_self(cpu) &&
141
!cpu->can_do_io
142
&& (mask & ~old_mask) != 0) {
143
@@ -XXX,XX +XXX,XX @@ static void icount_handle_interrupt(CPUState *cpu, int mask)
144
145
const CpusAccel tcg_cpus_icount = {
146
.create_vcpu_thread = rr_start_vcpu_thread,
147
- .kick_vcpu_thread = qemu_cpu_kick_rr_cpus,
148
+ .kick_vcpu_thread = rr_kick_vcpu_thread,
149
150
.handle_interrupt = icount_handle_interrupt,
151
.get_virtual_clock = icount_get,
152
diff --git a/accel/tcg/tcg-cpus-mttcg.c b/accel/tcg/tcg-cpus-mttcg.c
153
index XXXXXXX..XXXXXXX 100644
154
--- a/accel/tcg/tcg-cpus-mttcg.c
155
+++ b/accel/tcg/tcg-cpus-mttcg.c
156
@@ -XXX,XX +XXX,XX @@
157
* current CPUState for a given thread.
158
*/
159
160
-static void *tcg_cpu_thread_fn(void *arg)
161
+static void *mttcg_cpu_thread_fn(void *arg)
162
{
163
CPUState *cpu = arg;
164
165
@@ -XXX,XX +XXX,XX @@ static void *tcg_cpu_thread_fn(void *arg)
166
if (cpu_can_run(cpu)) {
167
int r;
168
qemu_mutex_unlock_iothread();
169
- r = tcg_cpu_exec(cpu);
170
+ r = tcg_cpus_exec(cpu);
171
qemu_mutex_lock_iothread();
172
switch (r) {
173
case EXCP_DEBUG:
174
@@ -XXX,XX +XXX,XX @@ static void *tcg_cpu_thread_fn(void *arg)
175
qemu_wait_io_event(cpu);
176
} while (!cpu->unplug || cpu_can_run(cpu));
177
178
- qemu_tcg_destroy_vcpu(cpu);
179
+ tcg_cpus_destroy(cpu);
180
qemu_mutex_unlock_iothread();
181
rcu_unregister_thread();
182
return NULL;
183
@@ -XXX,XX +XXX,XX @@ static void mttcg_start_vcpu_thread(CPUState *cpu)
184
snprintf(thread_name, VCPU_THREAD_NAME_SIZE, "CPU %d/TCG",
185
cpu->cpu_index);
186
187
- qemu_thread_create(cpu->thread, thread_name, tcg_cpu_thread_fn,
188
+ qemu_thread_create(cpu->thread, thread_name, mttcg_cpu_thread_fn,
189
cpu, QEMU_THREAD_JOINABLE);
190
191
#ifdef _WIN32
192
@@ -XXX,XX +XXX,XX @@ const CpusAccel tcg_cpus_mttcg = {
193
.create_vcpu_thread = mttcg_start_vcpu_thread,
194
.kick_vcpu_thread = mttcg_kick_vcpu_thread,
195
196
- .handle_interrupt = tcg_handle_interrupt,
197
+ .handle_interrupt = tcg_cpus_handle_interrupt,
198
};
199
diff --git a/accel/tcg/tcg-cpus-rr.c b/accel/tcg/tcg-cpus-rr.c
200
index XXXXXXX..XXXXXXX 100644
201
--- a/accel/tcg/tcg-cpus-rr.c
202
+++ b/accel/tcg/tcg-cpus-rr.c
203
@@ -XXX,XX +XXX,XX @@
204
#include "tcg-cpus-icount.h"
205
206
/* Kick all RR vCPUs */
207
-void qemu_cpu_kick_rr_cpus(CPUState *unused)
208
+void rr_kick_vcpu_thread(CPUState *unused)
209
{
210
CPUState *cpu;
211
212
@@ -XXX,XX +XXX,XX @@ void qemu_cpu_kick_rr_cpus(CPUState *unused)
213
* idleness is complete.
214
*/
215
216
-static QEMUTimer *tcg_kick_vcpu_timer;
217
-static CPUState *tcg_current_rr_cpu;
218
+static QEMUTimer *rr_kick_vcpu_timer;
219
+static CPUState *rr_current_cpu;
220
221
#define TCG_KICK_PERIOD (NANOSECONDS_PER_SECOND / 10)
222
223
-static inline int64_t qemu_tcg_next_kick(void)
224
+static inline int64_t rr_next_kick_time(void)
225
{
226
return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + TCG_KICK_PERIOD;
227
}
228
229
/* Kick the currently round-robin scheduled vCPU to next */
230
-static void qemu_cpu_kick_rr_next_cpu(void)
231
+static void rr_kick_next_cpu(void)
232
{
233
CPUState *cpu;
234
do {
235
- cpu = qatomic_mb_read(&tcg_current_rr_cpu);
236
+ cpu = qatomic_mb_read(&rr_current_cpu);
237
if (cpu) {
238
cpu_exit(cpu);
239
}
240
- } while (cpu != qatomic_mb_read(&tcg_current_rr_cpu));
241
+ } while (cpu != qatomic_mb_read(&rr_current_cpu));
242
}
243
244
-static void kick_tcg_thread(void *opaque)
245
+static void rr_kick_thread(void *opaque)
246
{
247
- timer_mod(tcg_kick_vcpu_timer, qemu_tcg_next_kick());
248
- qemu_cpu_kick_rr_next_cpu();
249
+ timer_mod(rr_kick_vcpu_timer, rr_next_kick_time());
250
+ rr_kick_next_cpu();
251
}
252
253
-static void start_tcg_kick_timer(void)
254
+static void rr_start_kick_timer(void)
255
{
256
- if (!tcg_kick_vcpu_timer && CPU_NEXT(first_cpu)) {
257
- tcg_kick_vcpu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
258
- kick_tcg_thread, NULL);
259
+ if (!rr_kick_vcpu_timer && CPU_NEXT(first_cpu)) {
260
+ rr_kick_vcpu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
261
+ rr_kick_thread, NULL);
262
}
263
- if (tcg_kick_vcpu_timer && !timer_pending(tcg_kick_vcpu_timer)) {
264
- timer_mod(tcg_kick_vcpu_timer, qemu_tcg_next_kick());
265
+ if (rr_kick_vcpu_timer && !timer_pending(rr_kick_vcpu_timer)) {
266
+ timer_mod(rr_kick_vcpu_timer, rr_next_kick_time());
267
}
268
}
269
270
-static void stop_tcg_kick_timer(void)
271
+static void rr_stop_kick_timer(void)
272
{
273
- if (tcg_kick_vcpu_timer && timer_pending(tcg_kick_vcpu_timer)) {
274
- timer_del(tcg_kick_vcpu_timer);
275
+ if (rr_kick_vcpu_timer && timer_pending(rr_kick_vcpu_timer)) {
276
+ timer_del(rr_kick_vcpu_timer);
277
}
278
}
279
280
-static void qemu_tcg_rr_wait_io_event(void)
281
+static void rr_wait_io_event(void)
282
{
283
CPUState *cpu;
284
285
while (all_cpu_threads_idle()) {
286
- stop_tcg_kick_timer();
287
+ rr_stop_kick_timer();
288
qemu_cond_wait_iothread(first_cpu->halt_cond);
289
}
290
291
- start_tcg_kick_timer();
292
+ rr_start_kick_timer();
293
294
CPU_FOREACH(cpu) {
295
qemu_wait_io_event_common(cpu);
296
@@ -XXX,XX +XXX,XX @@ static void qemu_tcg_rr_wait_io_event(void)
297
* Destroy any remaining vCPUs which have been unplugged and have
298
* finished running
299
*/
300
-static void deal_with_unplugged_cpus(void)
301
+static void rr_deal_with_unplugged_cpus(void)
302
{
303
CPUState *cpu;
304
305
CPU_FOREACH(cpu) {
306
if (cpu->unplug && !cpu_can_run(cpu)) {
307
- qemu_tcg_destroy_vcpu(cpu);
308
+ tcg_cpus_destroy(cpu);
309
break;
98
break;
310
}
99
case TCG_CALL_ARG_BY_REF_N:
311
}
312
@@ -XXX,XX +XXX,XX @@ static void deal_with_unplugged_cpus(void)
313
* elsewhere.
314
*/
315
316
-static void *tcg_rr_cpu_thread_fn(void *arg)
317
+static void *rr_cpu_thread_fn(void *arg)
318
{
319
CPUState *cpu = arg;
320
321
@@ -XXX,XX +XXX,XX @@ static void *tcg_rr_cpu_thread_fn(void *arg)
322
}
323
}
324
325
- start_tcg_kick_timer();
326
+ rr_start_kick_timer();
327
328
cpu = first_cpu;
329
330
@@ -XXX,XX +XXX,XX @@ static void *tcg_rr_cpu_thread_fn(void *arg)
331
* Run the timers here. This is much more efficient than
332
* waking up the I/O thread and waiting for completion.
333
*/
334
- handle_icount_deadline();
335
+ icount_handle_deadline();
336
}
337
338
replay_mutex_unlock();
339
@@ -XXX,XX +XXX,XX @@ static void *tcg_rr_cpu_thread_fn(void *arg)
340
341
while (cpu && cpu_work_list_empty(cpu) && !cpu->exit_request) {
342
343
- qatomic_mb_set(&tcg_current_rr_cpu, cpu);
344
+ qatomic_mb_set(&rr_current_cpu, cpu);
345
current_cpu = cpu;
346
347
qemu_clock_enable(QEMU_CLOCK_VIRTUAL,
348
@@ -XXX,XX +XXX,XX @@ static void *tcg_rr_cpu_thread_fn(void *arg)
349
350
qemu_mutex_unlock_iothread();
351
if (icount_enabled()) {
352
- prepare_icount_for_run(cpu);
353
+ icount_prepare_for_run(cpu);
354
}
355
- r = tcg_cpu_exec(cpu);
356
+ r = tcg_cpus_exec(cpu);
357
if (icount_enabled()) {
358
- process_icount_data(cpu);
359
+ icount_process_data(cpu);
360
}
361
qemu_mutex_lock_iothread();
362
363
@@ -XXX,XX +XXX,XX @@ static void *tcg_rr_cpu_thread_fn(void *arg)
364
} /* while (cpu && !cpu->exit_request).. */
365
366
/* Does not need qatomic_mb_set because a spurious wakeup is okay. */
367
- qatomic_set(&tcg_current_rr_cpu, NULL);
368
+ qatomic_set(&rr_current_cpu, NULL);
369
370
if (cpu && cpu->exit_request) {
371
qatomic_mb_set(&cpu->exit_request, 0);
372
@@ -XXX,XX +XXX,XX @@ static void *tcg_rr_cpu_thread_fn(void *arg)
373
qemu_notify_event();
374
}
375
376
- qemu_tcg_rr_wait_io_event();
377
- deal_with_unplugged_cpus();
378
+ rr_wait_io_event();
379
+ rr_deal_with_unplugged_cpus();
380
}
381
382
rcu_unregister_thread();
383
@@ -XXX,XX +XXX,XX @@ void rr_start_vcpu_thread(CPUState *cpu)
384
/* share a single thread for all cpus with TCG */
385
snprintf(thread_name, VCPU_THREAD_NAME_SIZE, "ALL CPUs/TCG");
386
qemu_thread_create(cpu->thread, thread_name,
387
- tcg_rr_cpu_thread_fn,
388
+ rr_cpu_thread_fn,
389
cpu, QEMU_THREAD_JOINABLE);
390
391
single_tcg_halt_cond = cpu->halt_cond;
392
@@ -XXX,XX +XXX,XX @@ void rr_start_vcpu_thread(CPUState *cpu)
393
394
const CpusAccel tcg_cpus_rr = {
395
.create_vcpu_thread = rr_start_vcpu_thread,
396
- .kick_vcpu_thread = qemu_cpu_kick_rr_cpus,
397
+ .kick_vcpu_thread = rr_kick_vcpu_thread,
398
399
- .handle_interrupt = tcg_handle_interrupt,
400
+ .handle_interrupt = tcg_cpus_handle_interrupt,
401
};
402
diff --git a/accel/tcg/tcg-cpus.c b/accel/tcg/tcg-cpus.c
403
index XXXXXXX..XXXXXXX 100644
404
--- a/accel/tcg/tcg-cpus.c
405
+++ b/accel/tcg/tcg-cpus.c
406
@@ -XXX,XX +XXX,XX @@
407
408
/* common functionality among all TCG variants */
409
410
-void qemu_tcg_destroy_vcpu(CPUState *cpu)
411
+void tcg_cpus_destroy(CPUState *cpu)
412
{
413
cpu_thread_signal_destroyed(cpu);
414
}
415
416
-int tcg_cpu_exec(CPUState *cpu)
417
+int tcg_cpus_exec(CPUState *cpu)
418
{
419
int ret;
420
#ifdef CONFIG_PROFILER
421
@@ -XXX,XX +XXX,XX @@ int tcg_cpu_exec(CPUState *cpu)
422
}
423
424
/* mask must never be zero, except for A20 change call */
425
-void tcg_handle_interrupt(CPUState *cpu, int mask)
426
+void tcg_cpus_handle_interrupt(CPUState *cpu, int mask)
427
{
428
g_assert(qemu_mutex_iothread_locked());
429
430
--
100
--
431
2.25.1
101
2.34.1
432
102
433
103
diff view generated by jsdifflib
[PULL 2/3] accel/tcg: split tcg_start_vcpu_thread
[PULL 42/42] tcg: Widen helper_*_st[bw]_mmu val arguments
1
From: Claudio Fontana <cfontana@suse.de>
1
While the old type was correct in the ideal sense, some ABIs require
2
the argument to be zero-extended. Using uint32_t for all such values
3
is a decent compromise.
2
4
3
after the initial split into 3 tcg variants, we proceed to also
5
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
4
split tcg_start_vcpu_thread.
5
6
We actually split it in 2 this time, since the icount variant
7
just uses the round robin function.
8
9
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
10
Signed-off-by: Claudio Fontana <cfontana@suse.de>
11
Message-Id: <20201015143217.29337-3-cfontana@suse.de>
12
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
13
---
7
---
14
accel/tcg/tcg-cpus-mttcg.h | 21 --------------
8
include/tcg/tcg-ldst.h | 10 +++++++---
15
accel/tcg/tcg-cpus-rr.h | 3 +-
9
accel/tcg/cputlb.c | 6 +++---
16
accel/tcg/tcg-cpus.h | 1 -
10
2 files changed, 10 insertions(+), 6 deletions(-)
17
accel/tcg/tcg-all.c | 5 ++++
18
accel/tcg/tcg-cpus-icount.c | 2 +-
19
accel/tcg/tcg-cpus-mttcg.c | 29 +++++++++++++++++--
20
accel/tcg/tcg-cpus-rr.c | 39 +++++++++++++++++++++++--
21
accel/tcg/tcg-cpus.c | 58 -------------------------------------
22
8 files changed, 71 insertions(+), 87 deletions(-)
23
delete mode 100644 accel/tcg/tcg-cpus-mttcg.h
24
11
25
diff --git a/accel/tcg/tcg-cpus-mttcg.h b/accel/tcg/tcg-cpus-mttcg.h
12
diff --git a/include/tcg/tcg-ldst.h b/include/tcg/tcg-ldst.h
26
deleted file mode 100644
27
index XXXXXXX..XXXXXXX
28
--- a/accel/tcg/tcg-cpus-mttcg.h
29
+++ /dev/null
30
@@ -XXX,XX +XXX,XX @@
31
-/*
32
- * QEMU TCG Multi Threaded vCPUs implementation
33
- *
34
- * Copyright 2020 SUSE LLC
35
- *
36
- * This work is licensed under the terms of the GNU GPL, version 2 or later.
37
- * See the COPYING file in the top-level directory.
38
- */
39
-
40
-#ifndef TCG_CPUS_MTTCG_H
41
-#define TCG_CPUS_MTTCG_H
42
-
43
-/*
44
- * In the multi-threaded case each vCPU has its own thread. The TLS
45
- * variable current_cpu can be used deep in the code to find the
46
- * current CPUState for a given thread.
47
- */
48
-
49
-void *tcg_cpu_thread_fn(void *arg);
50
-
51
-#endif /* TCG_CPUS_MTTCG_H */
52
diff --git a/accel/tcg/tcg-cpus-rr.h b/accel/tcg/tcg-cpus-rr.h
53
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
54
--- a/accel/tcg/tcg-cpus-rr.h
14
--- a/include/tcg/tcg-ldst.h
55
+++ b/accel/tcg/tcg-cpus-rr.h
15
+++ b/include/tcg/tcg-ldst.h
56
@@ -XXX,XX +XXX,XX @@
16
@@ -XXX,XX +XXX,XX @@ tcg_target_ulong helper_be_ldsw_mmu(CPUArchState *env, target_ulong addr,
57
/* Kick all RR vCPUs. */
17
tcg_target_ulong helper_be_ldsl_mmu(CPUArchState *env, target_ulong addr,
58
void qemu_cpu_kick_rr_cpus(CPUState *unused);
18
MemOpIdx oi, uintptr_t retaddr);
59
19
60
-void *tcg_rr_cpu_thread_fn(void *arg);
20
-void helper_ret_stb_mmu(CPUArchState *env, target_ulong addr, uint8_t val,
61
+/* start the round robin vcpu thread */
21
+/*
62
+void rr_start_vcpu_thread(CPUState *cpu);
22
+ * Value extended to at least uint32_t, so that some ABIs do not require
63
23
+ * zero-extension from uint8_t or uint16_t.
64
#endif /* TCG_CPUS_RR_H */
24
+ */
65
diff --git a/accel/tcg/tcg-cpus.h b/accel/tcg/tcg-cpus.h
25
+void helper_ret_stb_mmu(CPUArchState *env, target_ulong addr, uint32_t val,
26
MemOpIdx oi, uintptr_t retaddr);
27
-void helper_le_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val,
28
+void helper_le_stw_mmu(CPUArchState *env, target_ulong addr, uint32_t val,
29
MemOpIdx oi, uintptr_t retaddr);
30
void helper_le_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val,
31
MemOpIdx oi, uintptr_t retaddr);
32
void helper_le_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val,
33
MemOpIdx oi, uintptr_t retaddr);
34
-void helper_be_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val,
35
+void helper_be_stw_mmu(CPUArchState *env, target_ulong addr, uint32_t val,
36
MemOpIdx oi, uintptr_t retaddr);
37
void helper_be_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val,
38
MemOpIdx oi, uintptr_t retaddr);
39
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
66
index XXXXXXX..XXXXXXX 100644
40
index XXXXXXX..XXXXXXX 100644
67
--- a/accel/tcg/tcg-cpus.h
41
--- a/accel/tcg/cputlb.c
68
+++ b/accel/tcg/tcg-cpus.h
42
+++ b/accel/tcg/cputlb.c
69
@@ -XXX,XX +XXX,XX @@ extern const CpusAccel tcg_cpus_mttcg;
43
@@ -XXX,XX +XXX,XX @@ full_stb_mmu(CPUArchState *env, target_ulong addr, uint64_t val,
70
extern const CpusAccel tcg_cpus_icount;
44
store_helper(env, addr, val, oi, retaddr, MO_UB);
71
extern const CpusAccel tcg_cpus_rr;
72
73
-void tcg_start_vcpu_thread(CPUState *cpu);
74
void qemu_tcg_destroy_vcpu(CPUState *cpu);
75
int tcg_cpu_exec(CPUState *cpu);
76
void tcg_handle_interrupt(CPUState *cpu, int mask);
77
diff --git a/accel/tcg/tcg-all.c b/accel/tcg/tcg-all.c
78
index XXXXXXX..XXXXXXX 100644
79
--- a/accel/tcg/tcg-all.c
80
+++ b/accel/tcg/tcg-all.c
81
@@ -XXX,XX +XXX,XX @@ static int tcg_init(MachineState *ms)
82
tcg_exec_init(s->tb_size * 1024 * 1024);
83
mttcg_enabled = s->mttcg_enabled;
84
85
+ /*
86
+ * Initialize TCG regions
87
+ */
88
+ tcg_region_init();
89
+
90
if (mttcg_enabled) {
91
cpus_register_accel(&tcg_cpus_mttcg);
92
} else if (icount_enabled()) {
93
diff --git a/accel/tcg/tcg-cpus-icount.c b/accel/tcg/tcg-cpus-icount.c
94
index XXXXXXX..XXXXXXX 100644
95
--- a/accel/tcg/tcg-cpus-icount.c
96
+++ b/accel/tcg/tcg-cpus-icount.c
97
@@ -XXX,XX +XXX,XX @@ static void icount_handle_interrupt(CPUState *cpu, int mask)
98
}
45
}
99
46
100
const CpusAccel tcg_cpus_icount = {
47
-void helper_ret_stb_mmu(CPUArchState *env, target_ulong addr, uint8_t val,
101
- .create_vcpu_thread = tcg_start_vcpu_thread,
48
+void helper_ret_stb_mmu(CPUArchState *env, target_ulong addr, uint32_t val,
102
+ .create_vcpu_thread = rr_start_vcpu_thread,
49
MemOpIdx oi, uintptr_t retaddr)
103
.kick_vcpu_thread = qemu_cpu_kick_rr_cpus,
104
105
.handle_interrupt = icount_handle_interrupt,
106
diff --git a/accel/tcg/tcg-cpus-mttcg.c b/accel/tcg/tcg-cpus-mttcg.c
107
index XXXXXXX..XXXXXXX 100644
108
--- a/accel/tcg/tcg-cpus-mttcg.c
109
+++ b/accel/tcg/tcg-cpus-mttcg.c
110
@@ -XXX,XX +XXX,XX @@
111
#include "hw/boards.h"
112
113
#include "tcg-cpus.h"
114
-#include "tcg-cpus-mttcg.h"
115
116
/*
117
* In the multi-threaded case each vCPU has its own thread. The TLS
118
@@ -XXX,XX +XXX,XX @@
119
* current CPUState for a given thread.
120
*/
121
122
-void *tcg_cpu_thread_fn(void *arg)
123
+static void *tcg_cpu_thread_fn(void *arg)
124
{
50
{
125
CPUState *cpu = arg;
51
full_stb_mmu(env, addr, val, oi, retaddr);
126
52
@@ -XXX,XX +XXX,XX @@ static void full_le_stw_mmu(CPUArchState *env, target_ulong addr, uint64_t val,
127
@@ -XXX,XX +XXX,XX @@ static void mttcg_kick_vcpu_thread(CPUState *cpu)
53
store_helper(env, addr, val, oi, retaddr, MO_LEUW);
128
cpu_exit(cpu);
129
}
54
}
130
55
131
+static void mttcg_start_vcpu_thread(CPUState *cpu)
56
-void helper_le_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val,
132
+{
57
+void helper_le_stw_mmu(CPUArchState *env, target_ulong addr, uint32_t val,
133
+ char thread_name[VCPU_THREAD_NAME_SIZE];
58
MemOpIdx oi, uintptr_t retaddr)
134
+
135
+ g_assert(tcg_enabled());
136
+
137
+ parallel_cpus = (current_machine->smp.max_cpus > 1);
138
+
139
+ cpu->thread = g_malloc0(sizeof(QemuThread));
140
+ cpu->halt_cond = g_malloc0(sizeof(QemuCond));
141
+ qemu_cond_init(cpu->halt_cond);
142
+
143
+ /* create a thread per vCPU with TCG (MTTCG) */
144
+ snprintf(thread_name, VCPU_THREAD_NAME_SIZE, "CPU %d/TCG",
145
+ cpu->cpu_index);
146
+
147
+ qemu_thread_create(cpu->thread, thread_name, tcg_cpu_thread_fn,
148
+ cpu, QEMU_THREAD_JOINABLE);
149
+
150
+#ifdef _WIN32
151
+ cpu->hThread = qemu_thread_get_handle(cpu->thread);
152
+#endif
153
+}
154
+
155
const CpusAccel tcg_cpus_mttcg = {
156
- .create_vcpu_thread = tcg_start_vcpu_thread,
157
+ .create_vcpu_thread = mttcg_start_vcpu_thread,
158
.kick_vcpu_thread = mttcg_kick_vcpu_thread,
159
160
.handle_interrupt = tcg_handle_interrupt,
161
diff --git a/accel/tcg/tcg-cpus-rr.c b/accel/tcg/tcg-cpus-rr.c
162
index XXXXXXX..XXXXXXX 100644
163
--- a/accel/tcg/tcg-cpus-rr.c
164
+++ b/accel/tcg/tcg-cpus-rr.c
165
@@ -XXX,XX +XXX,XX @@ static void deal_with_unplugged_cpus(void)
166
* elsewhere.
167
*/
168
169
-void *tcg_rr_cpu_thread_fn(void *arg)
170
+static void *tcg_rr_cpu_thread_fn(void *arg)
171
{
59
{
172
CPUState *cpu = arg;
60
full_le_stw_mmu(env, addr, val, oi, retaddr);
173
61
@@ -XXX,XX +XXX,XX @@ static void full_be_stw_mmu(CPUArchState *env, target_ulong addr, uint64_t val,
174
@@ -XXX,XX +XXX,XX @@ void *tcg_rr_cpu_thread_fn(void *arg)
62
store_helper(env, addr, val, oi, retaddr, MO_BEUW);
175
return NULL;
176
}
63
}
177
64
178
+void rr_start_vcpu_thread(CPUState *cpu)
65
-void helper_be_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val,
179
+{
66
+void helper_be_stw_mmu(CPUArchState *env, target_ulong addr, uint32_t val,
180
+ char thread_name[VCPU_THREAD_NAME_SIZE];
67
MemOpIdx oi, uintptr_t retaddr)
181
+ static QemuCond *single_tcg_halt_cond;
182
+ static QemuThread *single_tcg_cpu_thread;
183
+
184
+ g_assert(tcg_enabled());
185
+ parallel_cpus = false;
186
+
187
+ if (!single_tcg_cpu_thread) {
188
+ cpu->thread = g_malloc0(sizeof(QemuThread));
189
+ cpu->halt_cond = g_malloc0(sizeof(QemuCond));
190
+ qemu_cond_init(cpu->halt_cond);
191
+
192
+ /* share a single thread for all cpus with TCG */
193
+ snprintf(thread_name, VCPU_THREAD_NAME_SIZE, "ALL CPUs/TCG");
194
+ qemu_thread_create(cpu->thread, thread_name,
195
+ tcg_rr_cpu_thread_fn,
196
+ cpu, QEMU_THREAD_JOINABLE);
197
+
198
+ single_tcg_halt_cond = cpu->halt_cond;
199
+ single_tcg_cpu_thread = cpu->thread;
200
+#ifdef _WIN32
201
+ cpu->hThread = qemu_thread_get_handle(cpu->thread);
202
+#endif
203
+ } else {
204
+ /* we share the thread */
205
+ cpu->thread = single_tcg_cpu_thread;
206
+ cpu->halt_cond = single_tcg_halt_cond;
207
+ cpu->thread_id = first_cpu->thread_id;
208
+ cpu->can_do_io = 1;
209
+ cpu->created = true;
210
+ }
211
+}
212
+
213
const CpusAccel tcg_cpus_rr = {
214
- .create_vcpu_thread = tcg_start_vcpu_thread,
215
+ .create_vcpu_thread = rr_start_vcpu_thread,
216
.kick_vcpu_thread = qemu_cpu_kick_rr_cpus,
217
218
.handle_interrupt = tcg_handle_interrupt,
219
diff --git a/accel/tcg/tcg-cpus.c b/accel/tcg/tcg-cpus.c
220
index XXXXXXX..XXXXXXX 100644
221
--- a/accel/tcg/tcg-cpus.c
222
+++ b/accel/tcg/tcg-cpus.c
223
@@ -XXX,XX +XXX,XX @@
224
#include "hw/boards.h"
225
226
#include "tcg-cpus.h"
227
-#include "tcg-cpus-mttcg.h"
228
-#include "tcg-cpus-rr.h"
229
230
/* common functionality among all TCG variants */
231
232
-void tcg_start_vcpu_thread(CPUState *cpu)
233
-{
234
- char thread_name[VCPU_THREAD_NAME_SIZE];
235
- static QemuCond *single_tcg_halt_cond;
236
- static QemuThread *single_tcg_cpu_thread;
237
- static int tcg_region_inited;
238
-
239
- assert(tcg_enabled());
240
- /*
241
- * Initialize TCG regions--once. Now is a good time, because:
242
- * (1) TCG's init context, prologue and target globals have been set up.
243
- * (2) qemu_tcg_mttcg_enabled() works now (TCG init code runs before the
244
- * -accel flag is processed, so the check doesn't work then).
245
- */
246
- if (!tcg_region_inited) {
247
- tcg_region_inited = 1;
248
- tcg_region_init();
249
- parallel_cpus = qemu_tcg_mttcg_enabled() && current_machine->smp.max_cpus > 1;
250
- }
251
-
252
- if (qemu_tcg_mttcg_enabled() || !single_tcg_cpu_thread) {
253
- cpu->thread = g_malloc0(sizeof(QemuThread));
254
- cpu->halt_cond = g_malloc0(sizeof(QemuCond));
255
- qemu_cond_init(cpu->halt_cond);
256
-
257
- if (qemu_tcg_mttcg_enabled()) {
258
- /* create a thread per vCPU with TCG (MTTCG) */
259
- snprintf(thread_name, VCPU_THREAD_NAME_SIZE, "CPU %d/TCG",
260
- cpu->cpu_index);
261
-
262
- qemu_thread_create(cpu->thread, thread_name, tcg_cpu_thread_fn,
263
- cpu, QEMU_THREAD_JOINABLE);
264
-
265
- } else {
266
- /* share a single thread for all cpus with TCG */
267
- snprintf(thread_name, VCPU_THREAD_NAME_SIZE, "ALL CPUs/TCG");
268
- qemu_thread_create(cpu->thread, thread_name,
269
- tcg_rr_cpu_thread_fn,
270
- cpu, QEMU_THREAD_JOINABLE);
271
-
272
- single_tcg_halt_cond = cpu->halt_cond;
273
- single_tcg_cpu_thread = cpu->thread;
274
- }
275
-#ifdef _WIN32
276
- cpu->hThread = qemu_thread_get_handle(cpu->thread);
277
-#endif
278
- } else {
279
- /* For non-MTTCG cases we share the thread */
280
- cpu->thread = single_tcg_cpu_thread;
281
- cpu->halt_cond = single_tcg_halt_cond;
282
- cpu->thread_id = first_cpu->thread_id;
283
- cpu->can_do_io = 1;
284
- cpu->created = true;
285
- }
286
-}
287
-
288
void qemu_tcg_destroy_vcpu(CPUState *cpu)
289
{
68
{
290
cpu_thread_signal_destroyed(cpu);
69
full_be_stw_mmu(env, addr, val, oi, retaddr);
291
--
70
--
292
2.25.1
71
2.34.1
293
72
294
73
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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