1
The following changes since commit 2ecfc0657afa5d29a373271b342f704a1a3c6737:
1
Note that I've extended the expiration date of my gpg key
2
and have uploaded it to keyserver.ubuntu.com.
2
3
3
Merge remote-tracking branch 'remotes/armbru/tags/pull-misc-2020-12-10' into staging (2020-12-10 17:01:05 +0000)
4
5
r~
6
7
8
The following changes since commit 99c44988d5ba1866a411450c877ed818b1b70081:
9
10
Merge remote-tracking branch 'remotes/bsdimp/tags/pull-bsd-user-20210910' into staging (2021-09-11 14:00:39 +0100)
4
11
5
are available in the Git repository at:
12
are available in the Git repository at:
6
13
7
https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20201210
14
https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20210912
8
15
9
for you to fetch changes up to 9e2658d62ebc23efe7df43fc0e306f129510d874:
16
for you to fetch changes up to 267a3ec3e2a8fb3e06a9d46d09fcfc57dfefd118:
10
17
11
accel/tcg: rename tcg-cpus functions to match module name (2020-12-10 17:44:10 -0600)
18
tcg/arm: Fix tcg_out_vec_op function signature (2021-09-12 05:07:36 -0700)
12
19
13
----------------------------------------------------------------
20
----------------------------------------------------------------
14
Split CpusAccel for tcg variants
21
Fix translation race condition for user-only.
22
Fix tcg/i386 encoding for VPSLLVQ, VPSRLVQ.
23
Fix tcg/arm tcg_out_vec_op signature.
24
Fix tcg/ppc (32bit) build with clang.
25
Remove dupluate TCG_KICK_PERIOD definition.
26
Remove unused tcg_global_reg_new.
27
Use __builtin_bswap*.
15
28
16
----------------------------------------------------------------
29
----------------------------------------------------------------
17
Claudio Fontana (3):
30
Bin Meng (1):
18
accel/tcg: split CpusAccel into three TCG variants
31
tcg: Remove tcg_global_reg_new defines
19
accel/tcg: split tcg_start_vcpu_thread
20
accel/tcg: rename tcg-cpus functions to match module name
21
32
22
accel/tcg/tcg-cpus-icount.h | 17 ++
33
Ilya Leoshkevich (2):
23
accel/tcg/tcg-cpus-rr.h | 21 ++
34
accel/tcg: Add DisasContextBase argument to translator_ld*
24
accel/tcg/tcg-cpus.h | 12 +-
35
accel/tcg: Clear PAGE_WRITE before translation
25
accel/tcg/tcg-all.c | 13 +-
26
accel/tcg/tcg-cpus-icount.c | 147 +++++++++++++
27
accel/tcg/tcg-cpus-mttcg.c | 140 ++++++++++++
28
accel/tcg/tcg-cpus-rr.c | 305 ++++++++++++++++++++++++++
29
accel/tcg/tcg-cpus.c | 506 +-------------------------------------------
30
softmmu/icount.c | 2 +-
31
accel/tcg/meson.build | 9 +-
32
10 files changed, 670 insertions(+), 502 deletions(-)
33
create mode 100644 accel/tcg/tcg-cpus-icount.h
34
create mode 100644 accel/tcg/tcg-cpus-rr.h
35
create mode 100644 accel/tcg/tcg-cpus-icount.c
36
create mode 100644 accel/tcg/tcg-cpus-mttcg.c
37
create mode 100644 accel/tcg/tcg-cpus-rr.c
38
36
37
Jose R. Ziviani (1):
38
tcg/arm: Fix tcg_out_vec_op function signature
39
40
Luc Michel (1):
41
accel/tcg: remove redundant TCG_KICK_PERIOD define
42
43
Richard Henderson (4):
44
tcg/i386: Split P_VEXW from P_REXW
45
include/qemu: Use builtins for bswap
46
tcg/ppc: Replace TCG_TARGET_CALL_DARWIN with _CALL_DARWIN
47
tcg/ppc: Ensure _CALL_SYSV is set for 32-bit ELF
48
49
meson.build | 6 ----
50
include/exec/translate-all.h | 1 +
51
include/exec/translator.h | 44 +++++++++++++----------
52
include/qemu/bswap.h | 53 ++-------------------------
53
include/tcg/tcg-op.h | 2 --
54
target/arm/arm_ldst.h | 12 +++----
55
accel/tcg/tcg-accel-ops-rr.c | 2 --
56
accel/tcg/translate-all.c | 59 ++++++++++++++++++-------------
57
accel/tcg/translator.c | 39 ++++++++++++++++++++
58
target/alpha/translate.c | 2 +-
59
target/arm/translate-a64.c | 2 +-
60
target/arm/translate.c | 9 ++---
61
target/hexagon/translate.c | 3 +-
62
target/hppa/translate.c | 5 +--
63
target/i386/tcg/translate.c | 10 +++---
64
target/m68k/translate.c | 2 +-
65
target/mips/tcg/translate.c | 8 ++---
66
target/openrisc/translate.c | 2 +-
67
target/ppc/translate.c | 5 +--
68
target/riscv/translate.c | 5 +--
69
target/s390x/tcg/translate.c | 16 +++++----
70
target/sh4/translate.c | 4 +--
71
target/sparc/translate.c | 2 +-
72
target/xtensa/translate.c | 5 +--
73
target/mips/tcg/micromips_translate.c.inc | 2 +-
74
target/mips/tcg/mips16e_translate.c.inc | 4 +--
75
target/mips/tcg/nanomips_translate.c.inc | 4 +--
76
tcg/arm/tcg-target.c.inc | 3 +-
77
tcg/i386/tcg-target.c.inc | 13 +++----
78
tcg/ppc/tcg-target.c.inc | 25 ++++++++++---
79
30 files changed, 185 insertions(+), 164 deletions(-)
80
diff view generated by jsdifflib
New patch
1
From: Ilya Leoshkevich <iii@linux.ibm.com>
1
2
3
Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com>
4
[rth: Split out of a larger patch.]
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
---
7
include/exec/translator.h | 9 +++++----
8
target/arm/arm_ldst.h | 12 ++++++------
9
target/alpha/translate.c | 2 +-
10
target/arm/translate-a64.c | 2 +-
11
target/arm/translate.c | 9 +++++----
12
target/hexagon/translate.c | 3 ++-
13
target/hppa/translate.c | 2 +-
14
target/i386/tcg/translate.c | 10 +++++-----
15
target/m68k/translate.c | 2 +-
16
target/mips/tcg/translate.c | 8 ++++----
17
target/openrisc/translate.c | 2 +-
18
target/ppc/translate.c | 5 +++--
19
target/riscv/translate.c | 5 +++--
20
target/s390x/tcg/translate.c | 16 +++++++++-------
21
target/sh4/translate.c | 4 ++--
22
target/sparc/translate.c | 2 +-
23
target/xtensa/translate.c | 5 +++--
24
target/mips/tcg/micromips_translate.c.inc | 2 +-
25
target/mips/tcg/mips16e_translate.c.inc | 4 ++--
26
target/mips/tcg/nanomips_translate.c.inc | 4 ++--
27
20 files changed, 58 insertions(+), 50 deletions(-)
28
29
diff --git a/include/exec/translator.h b/include/exec/translator.h
30
index XXXXXXX..XXXXXXX 100644
31
--- a/include/exec/translator.h
32
+++ b/include/exec/translator.h
33
@@ -XXX,XX +XXX,XX @@ bool translator_use_goto_tb(DisasContextBase *db, target_ulong dest);
34
35
#define GEN_TRANSLATOR_LD(fullname, type, load_fn, swap_fn) \
36
static inline type \
37
- fullname ## _swap(CPUArchState *env, abi_ptr pc, bool do_swap) \
38
+ fullname ## _swap(CPUArchState *env, DisasContextBase *dcbase, \
39
+ abi_ptr pc, bool do_swap) \
40
{ \
41
type ret = load_fn(env, pc); \
42
if (do_swap) { \
43
@@ -XXX,XX +XXX,XX @@ bool translator_use_goto_tb(DisasContextBase *db, target_ulong dest);
44
plugin_insn_append(&ret, sizeof(ret)); \
45
return ret; \
46
} \
47
- \
48
- static inline type fullname(CPUArchState *env, abi_ptr pc) \
49
+ static inline type fullname(CPUArchState *env, \
50
+ DisasContextBase *dcbase, abi_ptr pc) \
51
{ \
52
- return fullname ## _swap(env, pc, false); \
53
+ return fullname ## _swap(env, dcbase, pc, false); \
54
}
55
56
GEN_TRANSLATOR_LD(translator_ldub, uint8_t, cpu_ldub_code, /* no swap */)
57
diff --git a/target/arm/arm_ldst.h b/target/arm/arm_ldst.h
58
index XXXXXXX..XXXXXXX 100644
59
--- a/target/arm/arm_ldst.h
60
+++ b/target/arm/arm_ldst.h
61
@@ -XXX,XX +XXX,XX @@
62
#include "qemu/bswap.h"
63
64
/* Load an instruction and return it in the standard little-endian order */
65
-static inline uint32_t arm_ldl_code(CPUARMState *env, target_ulong addr,
66
- bool sctlr_b)
67
+static inline uint32_t arm_ldl_code(CPUARMState *env, DisasContextBase *s,
68
+ target_ulong addr, bool sctlr_b)
69
{
70
- return translator_ldl_swap(env, addr, bswap_code(sctlr_b));
71
+ return translator_ldl_swap(env, s, addr, bswap_code(sctlr_b));
72
}
73
74
/* Ditto, for a halfword (Thumb) instruction */
75
-static inline uint16_t arm_lduw_code(CPUARMState *env, target_ulong addr,
76
- bool sctlr_b)
77
+static inline uint16_t arm_lduw_code(CPUARMState *env, DisasContextBase* s,
78
+ target_ulong addr, bool sctlr_b)
79
{
80
#ifndef CONFIG_USER_ONLY
81
/* In big-endian (BE32) mode, adjacent Thumb instructions have been swapped
82
@@ -XXX,XX +XXX,XX @@ static inline uint16_t arm_lduw_code(CPUARMState *env, target_ulong addr,
83
addr ^= 2;
84
}
85
#endif
86
- return translator_lduw_swap(env, addr, bswap_code(sctlr_b));
87
+ return translator_lduw_swap(env, s, addr, bswap_code(sctlr_b));
88
}
89
90
#endif
91
diff --git a/target/alpha/translate.c b/target/alpha/translate.c
92
index XXXXXXX..XXXXXXX 100644
93
--- a/target/alpha/translate.c
94
+++ b/target/alpha/translate.c
95
@@ -XXX,XX +XXX,XX @@ static void alpha_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
96
{
97
DisasContext *ctx = container_of(dcbase, DisasContext, base);
98
CPUAlphaState *env = cpu->env_ptr;
99
- uint32_t insn = translator_ldl(env, ctx->base.pc_next);
100
+ uint32_t insn = translator_ldl(env, &ctx->base, ctx->base.pc_next);
101
102
ctx->base.pc_next += 4;
103
ctx->base.is_jmp = translate_one(ctx, insn);
104
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
105
index XXXXXXX..XXXXXXX 100644
106
--- a/target/arm/translate-a64.c
107
+++ b/target/arm/translate-a64.c
108
@@ -XXX,XX +XXX,XX @@ static void disas_a64_insn(CPUARMState *env, DisasContext *s)
109
uint32_t insn;
110
111
s->pc_curr = s->base.pc_next;
112
- insn = arm_ldl_code(env, s->base.pc_next, s->sctlr_b);
113
+ insn = arm_ldl_code(env, &s->base, s->base.pc_next, s->sctlr_b);
114
s->insn = insn;
115
s->base.pc_next += 4;
116
117
diff --git a/target/arm/translate.c b/target/arm/translate.c
118
index XXXXXXX..XXXXXXX 100644
119
--- a/target/arm/translate.c
120
+++ b/target/arm/translate.c
121
@@ -XXX,XX +XXX,XX @@ static bool insn_crosses_page(CPUARMState *env, DisasContext *s)
122
* boundary, so we cross the page if the first 16 bits indicate
123
* that this is a 32 bit insn.
124
*/
125
- uint16_t insn = arm_lduw_code(env, s->base.pc_next, s->sctlr_b);
126
+ uint16_t insn = arm_lduw_code(env, &s->base, s->base.pc_next, s->sctlr_b);
127
128
return !thumb_insn_is_16bit(s, s->base.pc_next, insn);
129
}
130
@@ -XXX,XX +XXX,XX @@ static void arm_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
131
}
132
133
dc->pc_curr = dc->base.pc_next;
134
- insn = arm_ldl_code(env, dc->base.pc_next, dc->sctlr_b);
135
+ insn = arm_ldl_code(env, &dc->base, dc->base.pc_next, dc->sctlr_b);
136
dc->insn = insn;
137
dc->base.pc_next += 4;
138
disas_arm_insn(dc, insn);
139
@@ -XXX,XX +XXX,XX @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
140
}
141
142
dc->pc_curr = dc->base.pc_next;
143
- insn = arm_lduw_code(env, dc->base.pc_next, dc->sctlr_b);
144
+ insn = arm_lduw_code(env, &dc->base, dc->base.pc_next, dc->sctlr_b);
145
is_16bit = thumb_insn_is_16bit(dc, dc->base.pc_next, insn);
146
dc->base.pc_next += 2;
147
if (!is_16bit) {
148
- uint32_t insn2 = arm_lduw_code(env, dc->base.pc_next, dc->sctlr_b);
149
+ uint32_t insn2 = arm_lduw_code(env, &dc->base, dc->base.pc_next,
150
+ dc->sctlr_b);
151
152
insn = insn << 16 | insn2;
153
dc->base.pc_next += 2;
154
diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c
155
index XXXXXXX..XXXXXXX 100644
156
--- a/target/hexagon/translate.c
157
+++ b/target/hexagon/translate.c
158
@@ -XXX,XX +XXX,XX @@ static int read_packet_words(CPUHexagonState *env, DisasContext *ctx,
159
memset(words, 0, PACKET_WORDS_MAX * sizeof(uint32_t));
160
for (nwords = 0; !found_end && nwords < PACKET_WORDS_MAX; nwords++) {
161
words[nwords] =
162
- translator_ldl(env, ctx->base.pc_next + nwords * sizeof(uint32_t));
163
+ translator_ldl(env, &ctx->base,
164
+ ctx->base.pc_next + nwords * sizeof(uint32_t));
165
found_end = is_packet_end(words[nwords]);
166
}
167
if (!found_end) {
168
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
169
index XXXXXXX..XXXXXXX 100644
170
--- a/target/hppa/translate.c
171
+++ b/target/hppa/translate.c
172
@@ -XXX,XX +XXX,XX @@ static void hppa_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
173
{
174
/* Always fetch the insn, even if nullified, so that we check
175
the page permissions for execute. */
176
- uint32_t insn = translator_ldl(env, ctx->base.pc_next);
177
+ uint32_t insn = translator_ldl(env, &ctx->base, ctx->base.pc_next);
178
179
/* Set up the IA queue for the next insn.
180
This will be overwritten by a branch. */
181
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
182
index XXXXXXX..XXXXXXX 100644
183
--- a/target/i386/tcg/translate.c
184
+++ b/target/i386/tcg/translate.c
185
@@ -XXX,XX +XXX,XX @@ static uint64_t advance_pc(CPUX86State *env, DisasContext *s, int num_bytes)
186
187
static inline uint8_t x86_ldub_code(CPUX86State *env, DisasContext *s)
188
{
189
- return translator_ldub(env, advance_pc(env, s, 1));
190
+ return translator_ldub(env, &s->base, advance_pc(env, s, 1));
191
}
192
193
static inline int16_t x86_ldsw_code(CPUX86State *env, DisasContext *s)
194
{
195
- return translator_ldsw(env, advance_pc(env, s, 2));
196
+ return translator_ldsw(env, &s->base, advance_pc(env, s, 2));
197
}
198
199
static inline uint16_t x86_lduw_code(CPUX86State *env, DisasContext *s)
200
{
201
- return translator_lduw(env, advance_pc(env, s, 2));
202
+ return translator_lduw(env, &s->base, advance_pc(env, s, 2));
203
}
204
205
static inline uint32_t x86_ldl_code(CPUX86State *env, DisasContext *s)
206
{
207
- return translator_ldl(env, advance_pc(env, s, 4));
208
+ return translator_ldl(env, &s->base, advance_pc(env, s, 4));
209
}
210
211
#ifdef TARGET_X86_64
212
static inline uint64_t x86_ldq_code(CPUX86State *env, DisasContext *s)
213
{
214
- return translator_ldq(env, advance_pc(env, s, 8));
215
+ return translator_ldq(env, &s->base, advance_pc(env, s, 8));
216
}
217
#endif
218
219
diff --git a/target/m68k/translate.c b/target/m68k/translate.c
220
index XXXXXXX..XXXXXXX 100644
221
--- a/target/m68k/translate.c
222
+++ b/target/m68k/translate.c
223
@@ -XXX,XX +XXX,XX @@ static TCGv gen_ldst(DisasContext *s, int opsize, TCGv addr, TCGv val,
224
static inline uint16_t read_im16(CPUM68KState *env, DisasContext *s)
225
{
226
uint16_t im;
227
- im = translator_lduw(env, s->pc);
228
+ im = translator_lduw(env, &s->base, s->pc);
229
s->pc += 2;
230
return im;
231
}
232
diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
233
index XXXXXXX..XXXXXXX 100644
234
--- a/target/mips/tcg/translate.c
235
+++ b/target/mips/tcg/translate.c
236
@@ -XXX,XX +XXX,XX @@ static void mips_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
237
238
is_slot = ctx->hflags & MIPS_HFLAG_BMASK;
239
if (ctx->insn_flags & ISA_NANOMIPS32) {
240
- ctx->opcode = translator_lduw(env, ctx->base.pc_next);
241
+ ctx->opcode = translator_lduw(env, &ctx->base, ctx->base.pc_next);
242
insn_bytes = decode_isa_nanomips(env, ctx);
243
} else if (!(ctx->hflags & MIPS_HFLAG_M16)) {
244
- ctx->opcode = translator_ldl(env, ctx->base.pc_next);
245
+ ctx->opcode = translator_ldl(env, &ctx->base, ctx->base.pc_next);
246
insn_bytes = 4;
247
decode_opc(env, ctx);
248
} else if (ctx->insn_flags & ASE_MICROMIPS) {
249
- ctx->opcode = translator_lduw(env, ctx->base.pc_next);
250
+ ctx->opcode = translator_lduw(env, &ctx->base, ctx->base.pc_next);
251
insn_bytes = decode_isa_micromips(env, ctx);
252
} else if (ctx->insn_flags & ASE_MIPS16) {
253
- ctx->opcode = translator_lduw(env, ctx->base.pc_next);
254
+ ctx->opcode = translator_lduw(env, &ctx->base, ctx->base.pc_next);
255
insn_bytes = decode_ase_mips16e(env, ctx);
256
} else {
257
gen_reserved_instruction(ctx);
258
diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c
259
index XXXXXXX..XXXXXXX 100644
260
--- a/target/openrisc/translate.c
261
+++ b/target/openrisc/translate.c
262
@@ -XXX,XX +XXX,XX @@ static void openrisc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
263
{
264
DisasContext *dc = container_of(dcbase, DisasContext, base);
265
OpenRISCCPU *cpu = OPENRISC_CPU(cs);
266
- uint32_t insn = translator_ldl(&cpu->env, dc->base.pc_next);
267
+ uint32_t insn = translator_ldl(&cpu->env, &dc->base, dc->base.pc_next);
268
269
if (!decode(dc, insn)) {
270
gen_illegal_exception(dc);
271
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
272
index XXXXXXX..XXXXXXX 100644
273
--- a/target/ppc/translate.c
274
+++ b/target/ppc/translate.c
275
@@ -XXX,XX +XXX,XX @@ static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
276
ctx->base.pc_next, ctx->mem_idx, (int)msr_ir);
277
278
ctx->cia = pc = ctx->base.pc_next;
279
- insn = translator_ldl_swap(env, pc, need_byteswap(ctx));
280
+ insn = translator_ldl_swap(env, dcbase, pc, need_byteswap(ctx));
281
ctx->base.pc_next = pc += 4;
282
283
if (!is_prefix_insn(ctx, insn)) {
284
@@ -XXX,XX +XXX,XX @@ static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
285
gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_INSN);
286
ok = true;
287
} else {
288
- uint32_t insn2 = translator_ldl_swap(env, pc, need_byteswap(ctx));
289
+ uint32_t insn2 = translator_ldl_swap(env, dcbase, pc,
290
+ need_byteswap(ctx));
291
ctx->base.pc_next = pc += 4;
292
ok = decode_insn64(ctx, deposit64(insn2, 32, 32, insn));
293
}
294
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
295
index XXXXXXX..XXXXXXX 100644
296
--- a/target/riscv/translate.c
297
+++ b/target/riscv/translate.c
298
@@ -XXX,XX +XXX,XX @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
299
} else {
300
uint32_t opcode32 = opcode;
301
opcode32 = deposit32(opcode32, 16, 16,
302
- translator_lduw(env, ctx->base.pc_next + 2));
303
+ translator_lduw(env, &ctx->base,
304
+ ctx->base.pc_next + 2));
305
ctx->pc_succ_insn = ctx->base.pc_next + 4;
306
if (!decode_insn32(ctx, opcode32)) {
307
gen_exception_illegal(ctx);
308
@@ -XXX,XX +XXX,XX @@ static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
309
{
310
DisasContext *ctx = container_of(dcbase, DisasContext, base);
311
CPURISCVState *env = cpu->env_ptr;
312
- uint16_t opcode16 = translator_lduw(env, ctx->base.pc_next);
313
+ uint16_t opcode16 = translator_lduw(env, &ctx->base, ctx->base.pc_next);
314
315
decode_opc(env, ctx, opcode16);
316
ctx->base.pc_next = ctx->pc_succ_insn;
317
diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c
318
index XXXXXXX..XXXXXXX 100644
319
--- a/target/s390x/tcg/translate.c
320
+++ b/target/s390x/tcg/translate.c
321
@@ -XXX,XX +XXX,XX @@ static void update_cc_op(DisasContext *s)
322
}
323
}
324
325
-static inline uint64_t ld_code2(CPUS390XState *env, uint64_t pc)
326
+static inline uint64_t ld_code2(CPUS390XState *env, DisasContext *s,
327
+ uint64_t pc)
328
{
329
- return (uint64_t)cpu_lduw_code(env, pc);
330
+ return (uint64_t)translator_lduw(env, &s->base, pc);
331
}
332
333
-static inline uint64_t ld_code4(CPUS390XState *env, uint64_t pc)
334
+static inline uint64_t ld_code4(CPUS390XState *env, DisasContext *s,
335
+ uint64_t pc)
336
{
337
- return (uint64_t)(uint32_t)cpu_ldl_code(env, pc);
338
+ return (uint64_t)(uint32_t)translator_ldl(env, &s->base, pc);
339
}
340
341
static int get_mem_index(DisasContext *s)
342
@@ -XXX,XX +XXX,XX @@ static const DisasInsn *extract_insn(CPUS390XState *env, DisasContext *s)
343
ilen = s->ex_value & 0xf;
344
op = insn >> 56;
345
} else {
346
- insn = ld_code2(env, pc);
347
+ insn = ld_code2(env, s, pc);
348
op = (insn >> 8) & 0xff;
349
ilen = get_ilen(op);
350
switch (ilen) {
351
@@ -XXX,XX +XXX,XX @@ static const DisasInsn *extract_insn(CPUS390XState *env, DisasContext *s)
352
insn = insn << 48;
353
break;
354
case 4:
355
- insn = ld_code4(env, pc) << 32;
356
+ insn = ld_code4(env, s, pc) << 32;
357
break;
358
case 6:
359
- insn = (insn << 48) | (ld_code4(env, pc + 2) << 16);
360
+ insn = (insn << 48) | (ld_code4(env, s, pc + 2) << 16);
361
break;
362
default:
363
g_assert_not_reached();
364
diff --git a/target/sh4/translate.c b/target/sh4/translate.c
365
index XXXXXXX..XXXXXXX 100644
366
--- a/target/sh4/translate.c
367
+++ b/target/sh4/translate.c
368
@@ -XXX,XX +XXX,XX @@ static void decode_gusa(DisasContext *ctx, CPUSH4State *env)
369
370
/* Read all of the insns for the region. */
371
for (i = 0; i < max_insns; ++i) {
372
- insns[i] = translator_lduw(env, pc + i * 2);
373
+ insns[i] = translator_lduw(env, &ctx->base, pc + i * 2);
374
}
375
376
ld_adr = ld_dst = ld_mop = -1;
377
@@ -XXX,XX +XXX,XX @@ static void sh4_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
378
}
379
#endif
380
381
- ctx->opcode = translator_lduw(env, ctx->base.pc_next);
382
+ ctx->opcode = translator_lduw(env, &ctx->base, ctx->base.pc_next);
383
decode_opc(ctx);
384
ctx->base.pc_next += 2;
385
}
386
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
387
index XXXXXXX..XXXXXXX 100644
388
--- a/target/sparc/translate.c
389
+++ b/target/sparc/translate.c
390
@@ -XXX,XX +XXX,XX @@ static void sparc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
391
CPUSPARCState *env = cs->env_ptr;
392
unsigned int insn;
393
394
- insn = translator_ldl(env, dc->pc);
395
+ insn = translator_ldl(env, &dc->base, dc->pc);
396
dc->base.pc_next += 4;
397
disas_sparc_insn(dc, insn);
398
399
diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c
400
index XXXXXXX..XXXXXXX 100644
401
--- a/target/xtensa/translate.c
402
+++ b/target/xtensa/translate.c
403
@@ -XXX,XX +XXX,XX @@ static int arg_copy_compare(const void *a, const void *b)
404
static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc)
405
{
406
xtensa_isa isa = dc->config->isa;
407
- unsigned char b[MAX_INSN_LENGTH] = {translator_ldub(env, dc->pc)};
408
+ unsigned char b[MAX_INSN_LENGTH] = {translator_ldub(env, &dc->base,
409
+ dc->pc)};
410
unsigned len = xtensa_op0_insn_len(dc, b[0]);
411
xtensa_format fmt;
412
int slot, slots;
413
@@ -XXX,XX +XXX,XX @@ static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc)
414
415
dc->base.pc_next = dc->pc + len;
416
for (i = 1; i < len; ++i) {
417
- b[i] = translator_ldub(env, dc->pc + i);
418
+ b[i] = translator_ldub(env, &dc->base, dc->pc + i);
419
}
420
xtensa_insnbuf_from_chars(isa, dc->insnbuf, b, len);
421
fmt = xtensa_format_decode(isa, dc->insnbuf);
422
diff --git a/target/mips/tcg/micromips_translate.c.inc b/target/mips/tcg/micromips_translate.c.inc
423
index XXXXXXX..XXXXXXX 100644
424
--- a/target/mips/tcg/micromips_translate.c.inc
425
+++ b/target/mips/tcg/micromips_translate.c.inc
426
@@ -XXX,XX +XXX,XX @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
427
uint32_t op, minor, minor2, mips32_op;
428
uint32_t cond, fmt, cc;
429
430
- insn = translator_lduw(env, ctx->base.pc_next + 2);
431
+ insn = translator_lduw(env, &ctx->base, ctx->base.pc_next + 2);
432
ctx->opcode = (ctx->opcode << 16) | insn;
433
434
rt = (ctx->opcode >> 21) & 0x1f;
435
diff --git a/target/mips/tcg/mips16e_translate.c.inc b/target/mips/tcg/mips16e_translate.c.inc
436
index XXXXXXX..XXXXXXX 100644
437
--- a/target/mips/tcg/mips16e_translate.c.inc
438
+++ b/target/mips/tcg/mips16e_translate.c.inc
439
@@ -XXX,XX +XXX,XX @@ static void decode_i64_mips16(DisasContext *ctx,
440
441
static int decode_extended_mips16_opc(CPUMIPSState *env, DisasContext *ctx)
442
{
443
- int extend = translator_lduw(env, ctx->base.pc_next + 2);
444
+ int extend = translator_lduw(env, &ctx->base, ctx->base.pc_next + 2);
445
int op, rx, ry, funct, sa;
446
int16_t imm, offset;
447
448
@@ -XXX,XX +XXX,XX @@ static int decode_ase_mips16e(CPUMIPSState *env, DisasContext *ctx)
449
/* No delay slot, so just process as a normal instruction */
450
break;
451
case M16_OPC_JAL:
452
- offset = translator_lduw(env, ctx->base.pc_next + 2);
453
+ offset = translator_lduw(env, &ctx->base, ctx->base.pc_next + 2);
454
offset = (((ctx->opcode & 0x1f) << 21)
455
| ((ctx->opcode >> 5) & 0x1f) << 16
456
| offset) << 2;
457
diff --git a/target/mips/tcg/nanomips_translate.c.inc b/target/mips/tcg/nanomips_translate.c.inc
458
index XXXXXXX..XXXXXXX 100644
459
--- a/target/mips/tcg/nanomips_translate.c.inc
460
+++ b/target/mips/tcg/nanomips_translate.c.inc
461
@@ -XXX,XX +XXX,XX @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
462
int offset;
463
int imm;
464
465
- insn = translator_lduw(env, ctx->base.pc_next + 2);
466
+ insn = translator_lduw(env, &ctx->base, ctx->base.pc_next + 2);
467
ctx->opcode = (ctx->opcode << 16) | insn;
468
469
rt = extract32(ctx->opcode, 21, 5);
470
@@ -XXX,XX +XXX,XX @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
471
break;
472
case NM_P48I:
473
{
474
- insn = translator_lduw(env, ctx->base.pc_next + 4);
475
+ insn = translator_lduw(env, &ctx->base, ctx->base.pc_next + 4);
476
target_long addr_off = extract32(ctx->opcode, 0, 16) | insn << 16;
477
switch (extract32(ctx->opcode, 16, 5)) {
478
case NM_LI48:
479
--
480
2.25.1
481
482
diff view generated by jsdifflib
1
From: Claudio Fontana <cfontana@suse.de>
1
From: Ilya Leoshkevich <iii@linux.ibm.com>
2
2
3
after the initial split into 3 tcg variants, we proceed to also
3
translate_insn() implementations fetch instruction bytes piecemeal,
4
split tcg_start_vcpu_thread.
4
which can cause qemu-user to generate inconsistent translations if
5
5
another thread modifies them concurrently [1].
6
We actually split it in 2 this time, since the icount variant
6
7
just uses the round robin function.
7
Fix by making pages containing translated instruction non-writable
8
8
right before loading instruction bytes from them.
9
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
9
10
Signed-off-by: Claudio Fontana <cfontana@suse.de>
10
[1] https://lists.nongnu.org/archive/html/qemu-devel/2021-08/msg00644.html
11
Message-Id: <20201015143217.29337-3-cfontana@suse.de>
11
12
Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com>
13
Message-Id: <20210805204835.158918-1-iii@linux.ibm.com>
12
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
14
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
13
---
15
---
14
accel/tcg/tcg-cpus-mttcg.h | 21 --------------
16
include/exec/translate-all.h | 1 +
15
accel/tcg/tcg-cpus-rr.h | 3 +-
17
include/exec/translator.h | 39 ++++++++++++++----------
16
accel/tcg/tcg-cpus.h | 1 -
18
accel/tcg/translate-all.c | 59 +++++++++++++++++++++---------------
17
accel/tcg/tcg-all.c | 5 ++++
19
accel/tcg/translator.c | 39 ++++++++++++++++++++++++
18
accel/tcg/tcg-cpus-icount.c | 2 +-
20
4 files changed, 97 insertions(+), 41 deletions(-)
19
accel/tcg/tcg-cpus-mttcg.c | 29 +++++++++++++++++--
21
20
accel/tcg/tcg-cpus-rr.c | 39 +++++++++++++++++++++++--
22
diff --git a/include/exec/translate-all.h b/include/exec/translate-all.h
21
accel/tcg/tcg-cpus.c | 58 -------------------------------------
23
index XXXXXXX..XXXXXXX 100644
22
8 files changed, 71 insertions(+), 87 deletions(-)
24
--- a/include/exec/translate-all.h
23
delete mode 100644 accel/tcg/tcg-cpus-mttcg.h
25
+++ b/include/exec/translate-all.h
24
26
@@ -XXX,XX +XXX,XX @@ void tb_invalidate_phys_page_range(tb_page_addr_t start, tb_page_addr_t end);
25
diff --git a/accel/tcg/tcg-cpus-mttcg.h b/accel/tcg/tcg-cpus-mttcg.h
27
void tb_check_watchpoint(CPUState *cpu, uintptr_t retaddr);
26
deleted file mode 100644
28
27
index XXXXXXX..XXXXXXX
29
#ifdef CONFIG_USER_ONLY
28
--- a/accel/tcg/tcg-cpus-mttcg.h
30
+void page_protect(tb_page_addr_t page_addr);
29
+++ /dev/null
31
int page_unprotect(target_ulong address, uintptr_t pc);
32
#endif
33
34
diff --git a/include/exec/translator.h b/include/exec/translator.h
35
index XXXXXXX..XXXXXXX 100644
36
--- a/include/exec/translator.h
37
+++ b/include/exec/translator.h
30
@@ -XXX,XX +XXX,XX @@
38
@@ -XXX,XX +XXX,XX @@
31
-/*
39
#include "exec/exec-all.h"
32
- * QEMU TCG Multi Threaded vCPUs implementation
40
#include "exec/cpu_ldst.h"
33
- *
41
#include "exec/plugin-gen.h"
34
- * Copyright 2020 SUSE LLC
42
+#include "exec/translate-all.h"
35
- *
43
#include "tcg/tcg.h"
36
- * This work is licensed under the terms of the GNU GPL, version 2 or later.
44
37
- * See the COPYING file in the top-level directory.
45
38
- */
46
@@ -XXX,XX +XXX,XX @@ typedef struct DisasContextBase {
47
int num_insns;
48
int max_insns;
49
bool singlestep_enabled;
50
+#ifdef CONFIG_USER_ONLY
51
+ /*
52
+ * Guest address of the last byte of the last protected page.
53
+ *
54
+ * Pages containing the translated instructions are made non-writable in
55
+ * order to achieve consistency in case another thread is modifying the
56
+ * code while translate_insn() fetches the instruction bytes piecemeal.
57
+ * Such writer threads are blocked on mmap_lock() in page_unprotect().
58
+ */
59
+ target_ulong page_protect_end;
60
+#endif
61
} DisasContextBase;
62
63
/**
64
@@ -XXX,XX +XXX,XX @@ bool translator_use_goto_tb(DisasContextBase *db, target_ulong dest);
65
*/
66
67
#define GEN_TRANSLATOR_LD(fullname, type, load_fn, swap_fn) \
68
- static inline type \
69
- fullname ## _swap(CPUArchState *env, DisasContextBase *dcbase, \
70
- abi_ptr pc, bool do_swap) \
71
- { \
72
- type ret = load_fn(env, pc); \
73
- if (do_swap) { \
74
- ret = swap_fn(ret); \
75
- } \
76
- plugin_insn_append(&ret, sizeof(ret)); \
77
- return ret; \
78
- } \
79
+ type fullname ## _swap(CPUArchState *env, DisasContextBase *dcbase, \
80
+ abi_ptr pc, bool do_swap); \
81
static inline type fullname(CPUArchState *env, \
82
DisasContextBase *dcbase, abi_ptr pc) \
83
{ \
84
return fullname ## _swap(env, dcbase, pc, false); \
85
}
86
87
-GEN_TRANSLATOR_LD(translator_ldub, uint8_t, cpu_ldub_code, /* no swap */)
88
-GEN_TRANSLATOR_LD(translator_ldsw, int16_t, cpu_ldsw_code, bswap16)
89
-GEN_TRANSLATOR_LD(translator_lduw, uint16_t, cpu_lduw_code, bswap16)
90
-GEN_TRANSLATOR_LD(translator_ldl, uint32_t, cpu_ldl_code, bswap32)
91
-GEN_TRANSLATOR_LD(translator_ldq, uint64_t, cpu_ldq_code, bswap64)
92
+#define FOR_EACH_TRANSLATOR_LD(F) \
93
+ F(translator_ldub, uint8_t, cpu_ldub_code, /* no swap */) \
94
+ F(translator_ldsw, int16_t, cpu_ldsw_code, bswap16) \
95
+ F(translator_lduw, uint16_t, cpu_lduw_code, bswap16) \
96
+ F(translator_ldl, uint32_t, cpu_ldl_code, bswap32) \
97
+ F(translator_ldq, uint64_t, cpu_ldq_code, bswap64)
98
+
99
+FOR_EACH_TRANSLATOR_LD(GEN_TRANSLATOR_LD)
100
+
101
#undef GEN_TRANSLATOR_LD
102
103
#endif /* EXEC__TRANSLATOR_H */
104
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
105
index XXXXXXX..XXXXXXX 100644
106
--- a/accel/tcg/translate-all.c
107
+++ b/accel/tcg/translate-all.c
108
@@ -XXX,XX +XXX,XX @@ static inline void tb_page_add(PageDesc *p, TranslationBlock *tb,
109
invalidate_page_bitmap(p);
110
111
#if defined(CONFIG_USER_ONLY)
112
- if (p->flags & PAGE_WRITE) {
113
- target_ulong addr;
114
- PageDesc *p2;
115
- int prot;
39
-
116
-
40
-#ifndef TCG_CPUS_MTTCG_H
117
- /* force the host page as non writable (writes will have a
41
-#define TCG_CPUS_MTTCG_H
118
- page fault + mprotect overhead) */
119
- page_addr &= qemu_host_page_mask;
120
- prot = 0;
121
- for (addr = page_addr; addr < page_addr + qemu_host_page_size;
122
- addr += TARGET_PAGE_SIZE) {
42
-
123
-
43
-/*
124
- p2 = page_find(addr >> TARGET_PAGE_BITS);
44
- * In the multi-threaded case each vCPU has its own thread. The TLS
125
- if (!p2) {
45
- * variable current_cpu can be used deep in the code to find the
126
- continue;
46
- * current CPUState for a given thread.
127
- }
47
- */
128
- prot |= p2->flags;
48
-
129
- p2->flags &= ~PAGE_WRITE;
49
-void *tcg_cpu_thread_fn(void *arg);
130
- }
50
-
131
- mprotect(g2h_untagged(page_addr), qemu_host_page_size,
51
-#endif /* TCG_CPUS_MTTCG_H */
132
- (prot & PAGE_BITS) & ~PAGE_WRITE);
52
diff --git a/accel/tcg/tcg-cpus-rr.h b/accel/tcg/tcg-cpus-rr.h
133
- if (DEBUG_TB_INVALIDATE_GATE) {
53
index XXXXXXX..XXXXXXX 100644
134
- printf("protecting code page: 0x" TB_PAGE_ADDR_FMT "\n", page_addr);
54
--- a/accel/tcg/tcg-cpus-rr.h
135
- }
55
+++ b/accel/tcg/tcg-cpus-rr.h
136
- }
56
@@ -XXX,XX +XXX,XX @@
137
+ /* translator_loop() must have made all TB pages non-writable */
57
/* Kick all RR vCPUs. */
138
+ assert(!(p->flags & PAGE_WRITE));
58
void qemu_cpu_kick_rr_cpus(CPUState *unused);
139
#else
59
140
/* if some code is already present, then the pages are already
60
-void *tcg_rr_cpu_thread_fn(void *arg);
141
protected. So we handle the case where only the first TB is
61
+/* start the round robin vcpu thread */
142
@@ -XXX,XX +XXX,XX @@ int page_check_range(target_ulong start, target_ulong len, int flags)
62
+void rr_start_vcpu_thread(CPUState *cpu);
143
return 0;
63
64
#endif /* TCG_CPUS_RR_H */
65
diff --git a/accel/tcg/tcg-cpus.h b/accel/tcg/tcg-cpus.h
66
index XXXXXXX..XXXXXXX 100644
67
--- a/accel/tcg/tcg-cpus.h
68
+++ b/accel/tcg/tcg-cpus.h
69
@@ -XXX,XX +XXX,XX @@ extern const CpusAccel tcg_cpus_mttcg;
70
extern const CpusAccel tcg_cpus_icount;
71
extern const CpusAccel tcg_cpus_rr;
72
73
-void tcg_start_vcpu_thread(CPUState *cpu);
74
void qemu_tcg_destroy_vcpu(CPUState *cpu);
75
int tcg_cpu_exec(CPUState *cpu);
76
void tcg_handle_interrupt(CPUState *cpu, int mask);
77
diff --git a/accel/tcg/tcg-all.c b/accel/tcg/tcg-all.c
78
index XXXXXXX..XXXXXXX 100644
79
--- a/accel/tcg/tcg-all.c
80
+++ b/accel/tcg/tcg-all.c
81
@@ -XXX,XX +XXX,XX @@ static int tcg_init(MachineState *ms)
82
tcg_exec_init(s->tb_size * 1024 * 1024);
83
mttcg_enabled = s->mttcg_enabled;
84
85
+ /*
86
+ * Initialize TCG regions
87
+ */
88
+ tcg_region_init();
89
+
90
if (mttcg_enabled) {
91
cpus_register_accel(&tcg_cpus_mttcg);
92
} else if (icount_enabled()) {
93
diff --git a/accel/tcg/tcg-cpus-icount.c b/accel/tcg/tcg-cpus-icount.c
94
index XXXXXXX..XXXXXXX 100644
95
--- a/accel/tcg/tcg-cpus-icount.c
96
+++ b/accel/tcg/tcg-cpus-icount.c
97
@@ -XXX,XX +XXX,XX @@ static void icount_handle_interrupt(CPUState *cpu, int mask)
98
}
144
}
99
145
100
const CpusAccel tcg_cpus_icount = {
146
+void page_protect(tb_page_addr_t page_addr)
101
- .create_vcpu_thread = tcg_start_vcpu_thread,
147
+{
102
+ .create_vcpu_thread = rr_start_vcpu_thread,
148
+ target_ulong addr;
103
.kick_vcpu_thread = qemu_cpu_kick_rr_cpus,
149
+ PageDesc *p;
104
150
+ int prot;
105
.handle_interrupt = icount_handle_interrupt,
151
+
106
diff --git a/accel/tcg/tcg-cpus-mttcg.c b/accel/tcg/tcg-cpus-mttcg.c
152
+ p = page_find(page_addr >> TARGET_PAGE_BITS);
107
index XXXXXXX..XXXXXXX 100644
153
+ if (p && (p->flags & PAGE_WRITE)) {
108
--- a/accel/tcg/tcg-cpus-mttcg.c
154
+ /*
109
+++ b/accel/tcg/tcg-cpus-mttcg.c
155
+ * Force the host page as non writable (writes will have a page fault +
110
@@ -XXX,XX +XXX,XX @@
156
+ * mprotect overhead).
111
#include "hw/boards.h"
157
+ */
112
158
+ page_addr &= qemu_host_page_mask;
113
#include "tcg-cpus.h"
159
+ prot = 0;
114
-#include "tcg-cpus-mttcg.h"
160
+ for (addr = page_addr; addr < page_addr + qemu_host_page_size;
115
161
+ addr += TARGET_PAGE_SIZE) {
116
/*
162
+
117
* In the multi-threaded case each vCPU has its own thread. The TLS
163
+ p = page_find(addr >> TARGET_PAGE_BITS);
118
@@ -XXX,XX +XXX,XX @@
164
+ if (!p) {
119
* current CPUState for a given thread.
165
+ continue;
120
*/
166
+ }
121
167
+ prot |= p->flags;
122
-void *tcg_cpu_thread_fn(void *arg)
168
+ p->flags &= ~PAGE_WRITE;
123
+static void *tcg_cpu_thread_fn(void *arg)
169
+ }
124
{
170
+ mprotect(g2h_untagged(page_addr), qemu_host_page_size,
125
CPUState *cpu = arg;
171
+ (prot & PAGE_BITS) & ~PAGE_WRITE);
126
172
+ if (DEBUG_TB_INVALIDATE_GATE) {
127
@@ -XXX,XX +XXX,XX @@ static void mttcg_kick_vcpu_thread(CPUState *cpu)
173
+ printf("protecting code page: 0x" TB_PAGE_ADDR_FMT "\n", page_addr);
128
cpu_exit(cpu);
174
+ }
175
+ }
176
+}
177
+
178
/* called from signal handler: invalidate the code and unprotect the
179
* page. Return 0 if the fault was not handled, 1 if it was handled,
180
* and 2 if it was handled but the caller must cause the TB to be
181
diff --git a/accel/tcg/translator.c b/accel/tcg/translator.c
182
index XXXXXXX..XXXXXXX 100644
183
--- a/accel/tcg/translator.c
184
+++ b/accel/tcg/translator.c
185
@@ -XXX,XX +XXX,XX @@ bool translator_use_goto_tb(DisasContextBase *db, target_ulong dest)
186
return ((db->pc_first ^ dest) & TARGET_PAGE_MASK) == 0;
129
}
187
}
130
188
131
+static void mttcg_start_vcpu_thread(CPUState *cpu)
189
+static inline void translator_page_protect(DisasContextBase *dcbase,
190
+ target_ulong pc)
132
+{
191
+{
133
+ char thread_name[VCPU_THREAD_NAME_SIZE];
192
+#ifdef CONFIG_USER_ONLY
134
+
193
+ dcbase->page_protect_end = pc | ~TARGET_PAGE_MASK;
135
+ g_assert(tcg_enabled());
194
+ page_protect(pc);
136
+
137
+ parallel_cpus = (current_machine->smp.max_cpus > 1);
138
+
139
+ cpu->thread = g_malloc0(sizeof(QemuThread));
140
+ cpu->halt_cond = g_malloc0(sizeof(QemuCond));
141
+ qemu_cond_init(cpu->halt_cond);
142
+
143
+ /* create a thread per vCPU with TCG (MTTCG) */
144
+ snprintf(thread_name, VCPU_THREAD_NAME_SIZE, "CPU %d/TCG",
145
+ cpu->cpu_index);
146
+
147
+ qemu_thread_create(cpu->thread, thread_name, tcg_cpu_thread_fn,
148
+ cpu, QEMU_THREAD_JOINABLE);
149
+
150
+#ifdef _WIN32
151
+ cpu->hThread = qemu_thread_get_handle(cpu->thread);
152
+#endif
195
+#endif
153
+}
196
+}
154
+
197
+
155
const CpusAccel tcg_cpus_mttcg = {
198
void translator_loop(const TranslatorOps *ops, DisasContextBase *db,
156
- .create_vcpu_thread = tcg_start_vcpu_thread,
199
CPUState *cpu, TranslationBlock *tb, int max_insns)
157
+ .create_vcpu_thread = mttcg_start_vcpu_thread,
158
.kick_vcpu_thread = mttcg_kick_vcpu_thread,
159
160
.handle_interrupt = tcg_handle_interrupt,
161
diff --git a/accel/tcg/tcg-cpus-rr.c b/accel/tcg/tcg-cpus-rr.c
162
index XXXXXXX..XXXXXXX 100644
163
--- a/accel/tcg/tcg-cpus-rr.c
164
+++ b/accel/tcg/tcg-cpus-rr.c
165
@@ -XXX,XX +XXX,XX @@ static void deal_with_unplugged_cpus(void)
166
* elsewhere.
167
*/
168
169
-void *tcg_rr_cpu_thread_fn(void *arg)
170
+static void *tcg_rr_cpu_thread_fn(void *arg)
171
{
200
{
172
CPUState *cpu = arg;
201
@@ -XXX,XX +XXX,XX @@ void translator_loop(const TranslatorOps *ops, DisasContextBase *db,
173
202
db->num_insns = 0;
174
@@ -XXX,XX +XXX,XX @@ void *tcg_rr_cpu_thread_fn(void *arg)
203
db->max_insns = max_insns;
175
return NULL;
204
db->singlestep_enabled = cflags & CF_SINGLE_STEP;
205
+ translator_page_protect(db, db->pc_next);
206
207
ops->init_disas_context(db, cpu);
208
tcg_debug_assert(db->is_jmp == DISAS_NEXT); /* no early exit */
209
@@ -XXX,XX +XXX,XX @@ void translator_loop(const TranslatorOps *ops, DisasContextBase *db,
210
}
211
#endif
176
}
212
}
177
213
+
178
+void rr_start_vcpu_thread(CPUState *cpu)
214
+static inline void translator_maybe_page_protect(DisasContextBase *dcbase,
215
+ target_ulong pc, size_t len)
179
+{
216
+{
180
+ char thread_name[VCPU_THREAD_NAME_SIZE];
217
+#ifdef CONFIG_USER_ONLY
181
+ static QemuCond *single_tcg_halt_cond;
218
+ target_ulong end = pc + len - 1;
182
+ static QemuThread *single_tcg_cpu_thread;
219
+
183
+
220
+ if (end > dcbase->page_protect_end) {
184
+ g_assert(tcg_enabled());
221
+ translator_page_protect(dcbase, end);
185
+ parallel_cpus = false;
222
+ }
186
+
187
+ if (!single_tcg_cpu_thread) {
188
+ cpu->thread = g_malloc0(sizeof(QemuThread));
189
+ cpu->halt_cond = g_malloc0(sizeof(QemuCond));
190
+ qemu_cond_init(cpu->halt_cond);
191
+
192
+ /* share a single thread for all cpus with TCG */
193
+ snprintf(thread_name, VCPU_THREAD_NAME_SIZE, "ALL CPUs/TCG");
194
+ qemu_thread_create(cpu->thread, thread_name,
195
+ tcg_rr_cpu_thread_fn,
196
+ cpu, QEMU_THREAD_JOINABLE);
197
+
198
+ single_tcg_halt_cond = cpu->halt_cond;
199
+ single_tcg_cpu_thread = cpu->thread;
200
+#ifdef _WIN32
201
+ cpu->hThread = qemu_thread_get_handle(cpu->thread);
202
+#endif
223
+#endif
203
+ } else {
224
+}
204
+ /* we share the thread */
225
+
205
+ cpu->thread = single_tcg_cpu_thread;
226
+#define GEN_TRANSLATOR_LD(fullname, type, load_fn, swap_fn) \
206
+ cpu->halt_cond = single_tcg_halt_cond;
227
+ type fullname ## _swap(CPUArchState *env, DisasContextBase *dcbase, \
207
+ cpu->thread_id = first_cpu->thread_id;
228
+ abi_ptr pc, bool do_swap) \
208
+ cpu->can_do_io = 1;
229
+ { \
209
+ cpu->created = true;
230
+ translator_maybe_page_protect(dcbase, pc, sizeof(type)); \
231
+ type ret = load_fn(env, pc); \
232
+ if (do_swap) { \
233
+ ret = swap_fn(ret); \
234
+ } \
235
+ plugin_insn_append(&ret, sizeof(ret)); \
236
+ return ret; \
210
+ }
237
+ }
211
+}
238
+
212
+
239
+FOR_EACH_TRANSLATOR_LD(GEN_TRANSLATOR_LD)
213
const CpusAccel tcg_cpus_rr = {
240
+
214
- .create_vcpu_thread = tcg_start_vcpu_thread,
241
+#undef GEN_TRANSLATOR_LD
215
+ .create_vcpu_thread = rr_start_vcpu_thread,
216
.kick_vcpu_thread = qemu_cpu_kick_rr_cpus,
217
218
.handle_interrupt = tcg_handle_interrupt,
219
diff --git a/accel/tcg/tcg-cpus.c b/accel/tcg/tcg-cpus.c
220
index XXXXXXX..XXXXXXX 100644
221
--- a/accel/tcg/tcg-cpus.c
222
+++ b/accel/tcg/tcg-cpus.c
223
@@ -XXX,XX +XXX,XX @@
224
#include "hw/boards.h"
225
226
#include "tcg-cpus.h"
227
-#include "tcg-cpus-mttcg.h"
228
-#include "tcg-cpus-rr.h"
229
230
/* common functionality among all TCG variants */
231
232
-void tcg_start_vcpu_thread(CPUState *cpu)
233
-{
234
- char thread_name[VCPU_THREAD_NAME_SIZE];
235
- static QemuCond *single_tcg_halt_cond;
236
- static QemuThread *single_tcg_cpu_thread;
237
- static int tcg_region_inited;
238
-
239
- assert(tcg_enabled());
240
- /*
241
- * Initialize TCG regions--once. Now is a good time, because:
242
- * (1) TCG's init context, prologue and target globals have been set up.
243
- * (2) qemu_tcg_mttcg_enabled() works now (TCG init code runs before the
244
- * -accel flag is processed, so the check doesn't work then).
245
- */
246
- if (!tcg_region_inited) {
247
- tcg_region_inited = 1;
248
- tcg_region_init();
249
- parallel_cpus = qemu_tcg_mttcg_enabled() && current_machine->smp.max_cpus > 1;
250
- }
251
-
252
- if (qemu_tcg_mttcg_enabled() || !single_tcg_cpu_thread) {
253
- cpu->thread = g_malloc0(sizeof(QemuThread));
254
- cpu->halt_cond = g_malloc0(sizeof(QemuCond));
255
- qemu_cond_init(cpu->halt_cond);
256
-
257
- if (qemu_tcg_mttcg_enabled()) {
258
- /* create a thread per vCPU with TCG (MTTCG) */
259
- snprintf(thread_name, VCPU_THREAD_NAME_SIZE, "CPU %d/TCG",
260
- cpu->cpu_index);
261
-
262
- qemu_thread_create(cpu->thread, thread_name, tcg_cpu_thread_fn,
263
- cpu, QEMU_THREAD_JOINABLE);
264
-
265
- } else {
266
- /* share a single thread for all cpus with TCG */
267
- snprintf(thread_name, VCPU_THREAD_NAME_SIZE, "ALL CPUs/TCG");
268
- qemu_thread_create(cpu->thread, thread_name,
269
- tcg_rr_cpu_thread_fn,
270
- cpu, QEMU_THREAD_JOINABLE);
271
-
272
- single_tcg_halt_cond = cpu->halt_cond;
273
- single_tcg_cpu_thread = cpu->thread;
274
- }
275
-#ifdef _WIN32
276
- cpu->hThread = qemu_thread_get_handle(cpu->thread);
277
-#endif
278
- } else {
279
- /* For non-MTTCG cases we share the thread */
280
- cpu->thread = single_tcg_cpu_thread;
281
- cpu->halt_cond = single_tcg_halt_cond;
282
- cpu->thread_id = first_cpu->thread_id;
283
- cpu->can_do_io = 1;
284
- cpu->created = true;
285
- }
286
-}
287
-
288
void qemu_tcg_destroy_vcpu(CPUState *cpu)
289
{
290
cpu_thread_signal_destroyed(cpu);
291
--
242
--
292
2.25.1
243
2.25.1
293
244
294
245
diff view generated by jsdifflib
New patch
1
We need to be able to represent VEX.W on a 32-bit host, where REX.W
2
will always be zero. Fixes the encoding for VPSLLVQ and VPSRLVQ.
1
3
4
Fixes: a2ce146a068 ("tcg/i386: Support vector variable shift opcodes")
5
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/385
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
---
8
tcg/i386/tcg-target.c.inc | 13 +++++++------
9
1 file changed, 7 insertions(+), 6 deletions(-)
10
11
diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
12
index XXXXXXX..XXXXXXX 100644
13
--- a/tcg/i386/tcg-target.c.inc
14
+++ b/tcg/i386/tcg-target.c.inc
15
@@ -XXX,XX +XXX,XX @@ static bool tcg_target_const_match(int64_t val, TCGType type, int ct)
16
#define P_EXT        0x100        /* 0x0f opcode prefix */
17
#define P_EXT38 0x200 /* 0x0f 0x38 opcode prefix */
18
#define P_DATA16 0x400 /* 0x66 opcode prefix */
19
+#define P_VEXW 0x1000 /* Set VEX.W = 1 */
20
#if TCG_TARGET_REG_BITS == 64
21
-# define P_REXW 0x1000 /* Set REX.W = 1 */
22
+# define P_REXW P_VEXW /* Set REX.W = 1; match VEXW */
23
# define P_REXB_R 0x2000 /* REG field as byte register */
24
# define P_REXB_RM 0x4000 /* R/M field as byte register */
25
# define P_GS 0x8000 /* gs segment override */
26
@@ -XXX,XX +XXX,XX @@ static bool tcg_target_const_match(int64_t val, TCGType type, int ct)
27
#define OPC_VPBROADCASTW (0x79 | P_EXT38 | P_DATA16)
28
#define OPC_VPBROADCASTD (0x58 | P_EXT38 | P_DATA16)
29
#define OPC_VPBROADCASTQ (0x59 | P_EXT38 | P_DATA16)
30
-#define OPC_VPERMQ (0x00 | P_EXT3A | P_DATA16 | P_REXW)
31
+#define OPC_VPERMQ (0x00 | P_EXT3A | P_DATA16 | P_VEXW)
32
#define OPC_VPERM2I128 (0x46 | P_EXT3A | P_DATA16 | P_VEXL)
33
#define OPC_VPSLLVD (0x47 | P_EXT38 | P_DATA16)
34
-#define OPC_VPSLLVQ (0x47 | P_EXT38 | P_DATA16 | P_REXW)
35
+#define OPC_VPSLLVQ (0x47 | P_EXT38 | P_DATA16 | P_VEXW)
36
#define OPC_VPSRAVD (0x46 | P_EXT38 | P_DATA16)
37
#define OPC_VPSRLVD (0x45 | P_EXT38 | P_DATA16)
38
-#define OPC_VPSRLVQ (0x45 | P_EXT38 | P_DATA16 | P_REXW)
39
+#define OPC_VPSRLVQ (0x45 | P_EXT38 | P_DATA16 | P_VEXW)
40
#define OPC_VZEROUPPER (0x77 | P_EXT)
41
#define OPC_XCHG_ax_r32    (0x90)
42
43
@@ -XXX,XX +XXX,XX @@ static void tcg_out_vex_opc(TCGContext *s, int opc, int r, int v,
44
45
/* Use the two byte form if possible, which cannot encode
46
VEX.W, VEX.B, VEX.X, or an m-mmmm field other than P_EXT. */
47
- if ((opc & (P_EXT | P_EXT38 | P_EXT3A | P_REXW)) == P_EXT
48
+ if ((opc & (P_EXT | P_EXT38 | P_EXT3A | P_VEXW)) == P_EXT
49
&& ((rm | index) & 8) == 0) {
50
/* Two byte VEX prefix. */
51
tcg_out8(s, 0xc5);
52
@@ -XXX,XX +XXX,XX @@ static void tcg_out_vex_opc(TCGContext *s, int opc, int r, int v,
53
tmp |= (rm & 8 ? 0 : 0x20); /* VEX.B */
54
tcg_out8(s, tmp);
55
56
- tmp = (opc & P_REXW ? 0x80 : 0); /* VEX.W */
57
+ tmp = (opc & P_VEXW ? 0x80 : 0); /* VEX.W */
58
}
59
60
tmp |= (opc & P_VEXL ? 0x04 : 0); /* VEX.L */
61
--
62
2.25.1
63
64
diff view generated by jsdifflib
1
From: Claudio Fontana <cfontana@suse.de>
1
From: Luc Michel <lmichel@kalray.eu>
2
2
3
Signed-off-by: Claudio Fontana <cfontana@suse.de>
3
The TCG_KICK_PERIOD macro is already defined in tcg-accel-ops-rr.h.
4
Remove it from tcg-accel-ops-rr.c.
5
6
Signed-off-by: Luc Michel <lmichel@kalray.eu>
4
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
7
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
5
Message-Id: <20201015143217.29337-4-cfontana@suse.de>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-Id: <20210811141229.12470-1-lmichel@kalray.eu>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
---
11
---
8
accel/tcg/tcg-cpus-icount.h | 6 +--
12
accel/tcg/tcg-accel-ops-rr.c | 2 --
9
accel/tcg/tcg-cpus-rr.h | 2 +-
13
1 file changed, 2 deletions(-)
10
accel/tcg/tcg-cpus.h | 6 +--
11
accel/tcg/tcg-cpus-icount.c | 24 ++++++------
12
accel/tcg/tcg-cpus-mttcg.c | 10 ++---
13
accel/tcg/tcg-cpus-rr.c | 74 ++++++++++++++++++-------------------
14
accel/tcg/tcg-cpus.c | 6 +--
15
7 files changed, 64 insertions(+), 64 deletions(-)
16
14
17
diff --git a/accel/tcg/tcg-cpus-icount.h b/accel/tcg/tcg-cpus-icount.h
15
diff --git a/accel/tcg/tcg-accel-ops-rr.c b/accel/tcg/tcg-accel-ops-rr.c
18
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
19
--- a/accel/tcg/tcg-cpus-icount.h
17
--- a/accel/tcg/tcg-accel-ops-rr.c
20
+++ b/accel/tcg/tcg-cpus-icount.h
18
+++ b/accel/tcg/tcg-accel-ops-rr.c
21
@@ -XXX,XX +XXX,XX @@
19
@@ -XXX,XX +XXX,XX @@ void rr_kick_vcpu_thread(CPUState *unused)
22
#ifndef TCG_CPUS_ICOUNT_H
20
static QEMUTimer *rr_kick_vcpu_timer;
23
#define TCG_CPUS_ICOUNT_H
21
static CPUState *rr_current_cpu;
24
22
25
-void handle_icount_deadline(void);
23
-#define TCG_KICK_PERIOD (NANOSECONDS_PER_SECOND / 10)
26
-void prepare_icount_for_run(CPUState *cpu);
24
-
27
-void process_icount_data(CPUState *cpu);
25
static inline int64_t rr_next_kick_time(void)
28
+void icount_handle_deadline(void);
29
+void icount_prepare_for_run(CPUState *cpu);
30
+void icount_process_data(CPUState *cpu);
31
32
#endif /* TCG_CPUS_ICOUNT_H */
33
diff --git a/accel/tcg/tcg-cpus-rr.h b/accel/tcg/tcg-cpus-rr.h
34
index XXXXXXX..XXXXXXX 100644
35
--- a/accel/tcg/tcg-cpus-rr.h
36
+++ b/accel/tcg/tcg-cpus-rr.h
37
@@ -XXX,XX +XXX,XX @@
38
#define TCG_KICK_PERIOD (NANOSECONDS_PER_SECOND / 10)
39
40
/* Kick all RR vCPUs. */
41
-void qemu_cpu_kick_rr_cpus(CPUState *unused);
42
+void rr_kick_vcpu_thread(CPUState *unused);
43
44
/* start the round robin vcpu thread */
45
void rr_start_vcpu_thread(CPUState *cpu);
46
diff --git a/accel/tcg/tcg-cpus.h b/accel/tcg/tcg-cpus.h
47
index XXXXXXX..XXXXXXX 100644
48
--- a/accel/tcg/tcg-cpus.h
49
+++ b/accel/tcg/tcg-cpus.h
50
@@ -XXX,XX +XXX,XX @@ extern const CpusAccel tcg_cpus_mttcg;
51
extern const CpusAccel tcg_cpus_icount;
52
extern const CpusAccel tcg_cpus_rr;
53
54
-void qemu_tcg_destroy_vcpu(CPUState *cpu);
55
-int tcg_cpu_exec(CPUState *cpu);
56
-void tcg_handle_interrupt(CPUState *cpu, int mask);
57
+void tcg_cpus_destroy(CPUState *cpu);
58
+int tcg_cpus_exec(CPUState *cpu);
59
+void tcg_cpus_handle_interrupt(CPUState *cpu, int mask);
60
61
#endif /* TCG_CPUS_H */
62
diff --git a/accel/tcg/tcg-cpus-icount.c b/accel/tcg/tcg-cpus-icount.c
63
index XXXXXXX..XXXXXXX 100644
64
--- a/accel/tcg/tcg-cpus-icount.c
65
+++ b/accel/tcg/tcg-cpus-icount.c
66
@@ -XXX,XX +XXX,XX @@
67
#include "tcg-cpus-icount.h"
68
#include "tcg-cpus-rr.h"
69
70
-static int64_t tcg_get_icount_limit(void)
71
+static int64_t icount_get_limit(void)
72
{
73
int64_t deadline;
74
75
@@ -XXX,XX +XXX,XX @@ static int64_t tcg_get_icount_limit(void)
76
}
77
}
78
79
-static void notify_aio_contexts(void)
80
+static void icount_notify_aio_contexts(void)
81
{
82
/* Wake up other AioContexts. */
83
qemu_clock_notify(QEMU_CLOCK_VIRTUAL);
84
qemu_clock_run_timers(QEMU_CLOCK_VIRTUAL);
85
}
86
87
-void handle_icount_deadline(void)
88
+void icount_handle_deadline(void)
89
{
90
assert(qemu_in_vcpu_thread());
91
int64_t deadline = qemu_clock_deadline_ns_all(QEMU_CLOCK_VIRTUAL,
92
QEMU_TIMER_ATTR_ALL);
93
94
if (deadline == 0) {
95
- notify_aio_contexts();
96
+ icount_notify_aio_contexts();
97
}
98
}
99
100
-void prepare_icount_for_run(CPUState *cpu)
101
+void icount_prepare_for_run(CPUState *cpu)
102
{
103
int insns_left;
104
105
/*
106
- * These should always be cleared by process_icount_data after
107
+ * These should always be cleared by icount_process_data after
108
* each vCPU execution. However u16.high can be raised
109
- * asynchronously by cpu_exit/cpu_interrupt/tcg_handle_interrupt
110
+ * asynchronously by cpu_exit/cpu_interrupt/tcg_cpus_handle_interrupt
111
*/
112
g_assert(cpu_neg(cpu)->icount_decr.u16.low == 0);
113
g_assert(cpu->icount_extra == 0);
114
115
- cpu->icount_budget = tcg_get_icount_limit();
116
+ cpu->icount_budget = icount_get_limit();
117
insns_left = MIN(0xffff, cpu->icount_budget);
118
cpu_neg(cpu)->icount_decr.u16.low = insns_left;
119
cpu->icount_extra = cpu->icount_budget - insns_left;
120
@@ -XXX,XX +XXX,XX @@ void prepare_icount_for_run(CPUState *cpu)
121
replay_mutex_lock();
122
123
if (cpu->icount_budget == 0 && replay_has_checkpoint()) {
124
- notify_aio_contexts();
125
+ icount_notify_aio_contexts();
126
}
127
}
128
129
-void process_icount_data(CPUState *cpu)
130
+void icount_process_data(CPUState *cpu)
131
{
132
/* Account for executed instructions */
133
icount_update(cpu);
134
@@ -XXX,XX +XXX,XX @@ static void icount_handle_interrupt(CPUState *cpu, int mask)
135
{
136
int old_mask = cpu->interrupt_request;
137
138
- tcg_handle_interrupt(cpu, mask);
139
+ tcg_cpus_handle_interrupt(cpu, mask);
140
if (qemu_cpu_is_self(cpu) &&
141
!cpu->can_do_io
142
&& (mask & ~old_mask) != 0) {
143
@@ -XXX,XX +XXX,XX @@ static void icount_handle_interrupt(CPUState *cpu, int mask)
144
145
const CpusAccel tcg_cpus_icount = {
146
.create_vcpu_thread = rr_start_vcpu_thread,
147
- .kick_vcpu_thread = qemu_cpu_kick_rr_cpus,
148
+ .kick_vcpu_thread = rr_kick_vcpu_thread,
149
150
.handle_interrupt = icount_handle_interrupt,
151
.get_virtual_clock = icount_get,
152
diff --git a/accel/tcg/tcg-cpus-mttcg.c b/accel/tcg/tcg-cpus-mttcg.c
153
index XXXXXXX..XXXXXXX 100644
154
--- a/accel/tcg/tcg-cpus-mttcg.c
155
+++ b/accel/tcg/tcg-cpus-mttcg.c
156
@@ -XXX,XX +XXX,XX @@
157
* current CPUState for a given thread.
158
*/
159
160
-static void *tcg_cpu_thread_fn(void *arg)
161
+static void *mttcg_cpu_thread_fn(void *arg)
162
{
163
CPUState *cpu = arg;
164
165
@@ -XXX,XX +XXX,XX @@ static void *tcg_cpu_thread_fn(void *arg)
166
if (cpu_can_run(cpu)) {
167
int r;
168
qemu_mutex_unlock_iothread();
169
- r = tcg_cpu_exec(cpu);
170
+ r = tcg_cpus_exec(cpu);
171
qemu_mutex_lock_iothread();
172
switch (r) {
173
case EXCP_DEBUG:
174
@@ -XXX,XX +XXX,XX @@ static void *tcg_cpu_thread_fn(void *arg)
175
qemu_wait_io_event(cpu);
176
} while (!cpu->unplug || cpu_can_run(cpu));
177
178
- qemu_tcg_destroy_vcpu(cpu);
179
+ tcg_cpus_destroy(cpu);
180
qemu_mutex_unlock_iothread();
181
rcu_unregister_thread();
182
return NULL;
183
@@ -XXX,XX +XXX,XX @@ static void mttcg_start_vcpu_thread(CPUState *cpu)
184
snprintf(thread_name, VCPU_THREAD_NAME_SIZE, "CPU %d/TCG",
185
cpu->cpu_index);
186
187
- qemu_thread_create(cpu->thread, thread_name, tcg_cpu_thread_fn,
188
+ qemu_thread_create(cpu->thread, thread_name, mttcg_cpu_thread_fn,
189
cpu, QEMU_THREAD_JOINABLE);
190
191
#ifdef _WIN32
192
@@ -XXX,XX +XXX,XX @@ const CpusAccel tcg_cpus_mttcg = {
193
.create_vcpu_thread = mttcg_start_vcpu_thread,
194
.kick_vcpu_thread = mttcg_kick_vcpu_thread,
195
196
- .handle_interrupt = tcg_handle_interrupt,
197
+ .handle_interrupt = tcg_cpus_handle_interrupt,
198
};
199
diff --git a/accel/tcg/tcg-cpus-rr.c b/accel/tcg/tcg-cpus-rr.c
200
index XXXXXXX..XXXXXXX 100644
201
--- a/accel/tcg/tcg-cpus-rr.c
202
+++ b/accel/tcg/tcg-cpus-rr.c
203
@@ -XXX,XX +XXX,XX @@
204
#include "tcg-cpus-icount.h"
205
206
/* Kick all RR vCPUs */
207
-void qemu_cpu_kick_rr_cpus(CPUState *unused)
208
+void rr_kick_vcpu_thread(CPUState *unused)
209
{
210
CPUState *cpu;
211
212
@@ -XXX,XX +XXX,XX @@ void qemu_cpu_kick_rr_cpus(CPUState *unused)
213
* idleness is complete.
214
*/
215
216
-static QEMUTimer *tcg_kick_vcpu_timer;
217
-static CPUState *tcg_current_rr_cpu;
218
+static QEMUTimer *rr_kick_vcpu_timer;
219
+static CPUState *rr_current_cpu;
220
221
#define TCG_KICK_PERIOD (NANOSECONDS_PER_SECOND / 10)
222
223
-static inline int64_t qemu_tcg_next_kick(void)
224
+static inline int64_t rr_next_kick_time(void)
225
{
26
{
226
return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + TCG_KICK_PERIOD;
27
return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + TCG_KICK_PERIOD;
227
}
228
229
/* Kick the currently round-robin scheduled vCPU to next */
230
-static void qemu_cpu_kick_rr_next_cpu(void)
231
+static void rr_kick_next_cpu(void)
232
{
233
CPUState *cpu;
234
do {
235
- cpu = qatomic_mb_read(&tcg_current_rr_cpu);
236
+ cpu = qatomic_mb_read(&rr_current_cpu);
237
if (cpu) {
238
cpu_exit(cpu);
239
}
240
- } while (cpu != qatomic_mb_read(&tcg_current_rr_cpu));
241
+ } while (cpu != qatomic_mb_read(&rr_current_cpu));
242
}
243
244
-static void kick_tcg_thread(void *opaque)
245
+static void rr_kick_thread(void *opaque)
246
{
247
- timer_mod(tcg_kick_vcpu_timer, qemu_tcg_next_kick());
248
- qemu_cpu_kick_rr_next_cpu();
249
+ timer_mod(rr_kick_vcpu_timer, rr_next_kick_time());
250
+ rr_kick_next_cpu();
251
}
252
253
-static void start_tcg_kick_timer(void)
254
+static void rr_start_kick_timer(void)
255
{
256
- if (!tcg_kick_vcpu_timer && CPU_NEXT(first_cpu)) {
257
- tcg_kick_vcpu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
258
- kick_tcg_thread, NULL);
259
+ if (!rr_kick_vcpu_timer && CPU_NEXT(first_cpu)) {
260
+ rr_kick_vcpu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
261
+ rr_kick_thread, NULL);
262
}
263
- if (tcg_kick_vcpu_timer && !timer_pending(tcg_kick_vcpu_timer)) {
264
- timer_mod(tcg_kick_vcpu_timer, qemu_tcg_next_kick());
265
+ if (rr_kick_vcpu_timer && !timer_pending(rr_kick_vcpu_timer)) {
266
+ timer_mod(rr_kick_vcpu_timer, rr_next_kick_time());
267
}
268
}
269
270
-static void stop_tcg_kick_timer(void)
271
+static void rr_stop_kick_timer(void)
272
{
273
- if (tcg_kick_vcpu_timer && timer_pending(tcg_kick_vcpu_timer)) {
274
- timer_del(tcg_kick_vcpu_timer);
275
+ if (rr_kick_vcpu_timer && timer_pending(rr_kick_vcpu_timer)) {
276
+ timer_del(rr_kick_vcpu_timer);
277
}
278
}
279
280
-static void qemu_tcg_rr_wait_io_event(void)
281
+static void rr_wait_io_event(void)
282
{
283
CPUState *cpu;
284
285
while (all_cpu_threads_idle()) {
286
- stop_tcg_kick_timer();
287
+ rr_stop_kick_timer();
288
qemu_cond_wait_iothread(first_cpu->halt_cond);
289
}
290
291
- start_tcg_kick_timer();
292
+ rr_start_kick_timer();
293
294
CPU_FOREACH(cpu) {
295
qemu_wait_io_event_common(cpu);
296
@@ -XXX,XX +XXX,XX @@ static void qemu_tcg_rr_wait_io_event(void)
297
* Destroy any remaining vCPUs which have been unplugged and have
298
* finished running
299
*/
300
-static void deal_with_unplugged_cpus(void)
301
+static void rr_deal_with_unplugged_cpus(void)
302
{
303
CPUState *cpu;
304
305
CPU_FOREACH(cpu) {
306
if (cpu->unplug && !cpu_can_run(cpu)) {
307
- qemu_tcg_destroy_vcpu(cpu);
308
+ tcg_cpus_destroy(cpu);
309
break;
310
}
311
}
312
@@ -XXX,XX +XXX,XX @@ static void deal_with_unplugged_cpus(void)
313
* elsewhere.
314
*/
315
316
-static void *tcg_rr_cpu_thread_fn(void *arg)
317
+static void *rr_cpu_thread_fn(void *arg)
318
{
319
CPUState *cpu = arg;
320
321
@@ -XXX,XX +XXX,XX @@ static void *tcg_rr_cpu_thread_fn(void *arg)
322
}
323
}
324
325
- start_tcg_kick_timer();
326
+ rr_start_kick_timer();
327
328
cpu = first_cpu;
329
330
@@ -XXX,XX +XXX,XX @@ static void *tcg_rr_cpu_thread_fn(void *arg)
331
* Run the timers here. This is much more efficient than
332
* waking up the I/O thread and waiting for completion.
333
*/
334
- handle_icount_deadline();
335
+ icount_handle_deadline();
336
}
337
338
replay_mutex_unlock();
339
@@ -XXX,XX +XXX,XX @@ static void *tcg_rr_cpu_thread_fn(void *arg)
340
341
while (cpu && cpu_work_list_empty(cpu) && !cpu->exit_request) {
342
343
- qatomic_mb_set(&tcg_current_rr_cpu, cpu);
344
+ qatomic_mb_set(&rr_current_cpu, cpu);
345
current_cpu = cpu;
346
347
qemu_clock_enable(QEMU_CLOCK_VIRTUAL,
348
@@ -XXX,XX +XXX,XX @@ static void *tcg_rr_cpu_thread_fn(void *arg)
349
350
qemu_mutex_unlock_iothread();
351
if (icount_enabled()) {
352
- prepare_icount_for_run(cpu);
353
+ icount_prepare_for_run(cpu);
354
}
355
- r = tcg_cpu_exec(cpu);
356
+ r = tcg_cpus_exec(cpu);
357
if (icount_enabled()) {
358
- process_icount_data(cpu);
359
+ icount_process_data(cpu);
360
}
361
qemu_mutex_lock_iothread();
362
363
@@ -XXX,XX +XXX,XX @@ static void *tcg_rr_cpu_thread_fn(void *arg)
364
} /* while (cpu && !cpu->exit_request).. */
365
366
/* Does not need qatomic_mb_set because a spurious wakeup is okay. */
367
- qatomic_set(&tcg_current_rr_cpu, NULL);
368
+ qatomic_set(&rr_current_cpu, NULL);
369
370
if (cpu && cpu->exit_request) {
371
qatomic_mb_set(&cpu->exit_request, 0);
372
@@ -XXX,XX +XXX,XX @@ static void *tcg_rr_cpu_thread_fn(void *arg)
373
qemu_notify_event();
374
}
375
376
- qemu_tcg_rr_wait_io_event();
377
- deal_with_unplugged_cpus();
378
+ rr_wait_io_event();
379
+ rr_deal_with_unplugged_cpus();
380
}
381
382
rcu_unregister_thread();
383
@@ -XXX,XX +XXX,XX @@ void rr_start_vcpu_thread(CPUState *cpu)
384
/* share a single thread for all cpus with TCG */
385
snprintf(thread_name, VCPU_THREAD_NAME_SIZE, "ALL CPUs/TCG");
386
qemu_thread_create(cpu->thread, thread_name,
387
- tcg_rr_cpu_thread_fn,
388
+ rr_cpu_thread_fn,
389
cpu, QEMU_THREAD_JOINABLE);
390
391
single_tcg_halt_cond = cpu->halt_cond;
392
@@ -XXX,XX +XXX,XX @@ void rr_start_vcpu_thread(CPUState *cpu)
393
394
const CpusAccel tcg_cpus_rr = {
395
.create_vcpu_thread = rr_start_vcpu_thread,
396
- .kick_vcpu_thread = qemu_cpu_kick_rr_cpus,
397
+ .kick_vcpu_thread = rr_kick_vcpu_thread,
398
399
- .handle_interrupt = tcg_handle_interrupt,
400
+ .handle_interrupt = tcg_cpus_handle_interrupt,
401
};
402
diff --git a/accel/tcg/tcg-cpus.c b/accel/tcg/tcg-cpus.c
403
index XXXXXXX..XXXXXXX 100644
404
--- a/accel/tcg/tcg-cpus.c
405
+++ b/accel/tcg/tcg-cpus.c
406
@@ -XXX,XX +XXX,XX @@
407
408
/* common functionality among all TCG variants */
409
410
-void qemu_tcg_destroy_vcpu(CPUState *cpu)
411
+void tcg_cpus_destroy(CPUState *cpu)
412
{
413
cpu_thread_signal_destroyed(cpu);
414
}
415
416
-int tcg_cpu_exec(CPUState *cpu)
417
+int tcg_cpus_exec(CPUState *cpu)
418
{
419
int ret;
420
#ifdef CONFIG_PROFILER
421
@@ -XXX,XX +XXX,XX @@ int tcg_cpu_exec(CPUState *cpu)
422
}
423
424
/* mask must never be zero, except for A20 change call */
425
-void tcg_handle_interrupt(CPUState *cpu, int mask)
426
+void tcg_cpus_handle_interrupt(CPUState *cpu, int mask)
427
{
428
g_assert(qemu_mutex_iothread_locked());
429
430
--
28
--
431
2.25.1
29
2.25.1
432
30
433
31
diff view generated by jsdifflib
New patch
1
From: Bin Meng <bmeng.cn@gmail.com>
1
2
3
Since commit 1c2adb958fc0 ("tcg: Initialize cpu_env generically"),
4
these tcg_global_reg_new_ macros are not used anywhere.
5
6
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
7
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Message-Id: <20210816143507.11200-1-bmeng.cn@gmail.com>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
---
11
include/tcg/tcg-op.h | 2 --
12
target/hppa/translate.c | 3 ---
13
2 files changed, 5 deletions(-)
14
15
diff --git a/include/tcg/tcg-op.h b/include/tcg/tcg-op.h
16
index XXXXXXX..XXXXXXX 100644
17
--- a/include/tcg/tcg-op.h
18
+++ b/include/tcg/tcg-op.h
19
@@ -XXX,XX +XXX,XX @@ static inline void tcg_gen_plugin_cb_end(void)
20
21
#if TARGET_LONG_BITS == 32
22
#define tcg_temp_new() tcg_temp_new_i32()
23
-#define tcg_global_reg_new tcg_global_reg_new_i32
24
#define tcg_global_mem_new tcg_global_mem_new_i32
25
#define tcg_temp_local_new() tcg_temp_local_new_i32()
26
#define tcg_temp_free tcg_temp_free_i32
27
@@ -XXX,XX +XXX,XX @@ static inline void tcg_gen_plugin_cb_end(void)
28
#define tcg_gen_qemu_st_tl tcg_gen_qemu_st_i32
29
#else
30
#define tcg_temp_new() tcg_temp_new_i64()
31
-#define tcg_global_reg_new tcg_global_reg_new_i64
32
#define tcg_global_mem_new tcg_global_mem_new_i64
33
#define tcg_temp_local_new() tcg_temp_local_new_i64()
34
#define tcg_temp_free tcg_temp_free_i64
35
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
36
index XXXXXXX..XXXXXXX 100644
37
--- a/target/hppa/translate.c
38
+++ b/target/hppa/translate.c
39
@@ -XXX,XX +XXX,XX @@
40
41
#undef TCGv
42
#undef tcg_temp_new
43
-#undef tcg_global_reg_new
44
#undef tcg_global_mem_new
45
#undef tcg_temp_local_new
46
#undef tcg_temp_free
47
@@ -XXX,XX +XXX,XX @@
48
#define TCGv_reg TCGv_i64
49
50
#define tcg_temp_new tcg_temp_new_i64
51
-#define tcg_global_reg_new tcg_global_reg_new_i64
52
#define tcg_global_mem_new tcg_global_mem_new_i64
53
#define tcg_temp_local_new tcg_temp_local_new_i64
54
#define tcg_temp_free tcg_temp_free_i64
55
@@ -XXX,XX +XXX,XX @@
56
#else
57
#define TCGv_reg TCGv_i32
58
#define tcg_temp_new tcg_temp_new_i32
59
-#define tcg_global_reg_new tcg_global_reg_new_i32
60
#define tcg_global_mem_new tcg_global_mem_new_i32
61
#define tcg_temp_local_new tcg_temp_local_new_i32
62
#define tcg_temp_free tcg_temp_free_i32
63
--
64
2.25.1
65
66
diff view generated by jsdifflib
1
From: Claudio Fontana <cfontana@suse.de>
1
All supported compilers have builtins for this.
2
Drop all of the complicated system detection stuff.
2
3
3
split up the CpusAccel tcg_cpus into three TCG variants:
4
5
tcg_cpus_rr (single threaded, round robin cpus)
6
tcg_cpus_icount (same as rr, but with instruction counting enabled)
7
tcg_cpus_mttcg (multi-threaded cpus)
8
9
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
10
Signed-off-by: Claudio Fontana <cfontana@suse.de>
11
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
12
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
4
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
13
Message-Id: <20201015143217.29337-2-cfontana@suse.de>
5
Message-Id: <20210708181743.750220-1-richard.henderson@linaro.org>
14
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
15
---
7
---
16
accel/tcg/tcg-cpus-icount.h | 17 ++
8
meson.build | 6 -----
17
accel/tcg/tcg-cpus-mttcg.h | 21 ++
9
include/qemu/bswap.h | 53 +++-----------------------------------------
18
accel/tcg/tcg-cpus-rr.h | 20 ++
10
2 files changed, 3 insertions(+), 56 deletions(-)
19
accel/tcg/tcg-cpus.h | 13 +-
20
accel/tcg/tcg-all.c | 8 +-
21
accel/tcg/tcg-cpus-icount.c | 147 +++++++++++
22
accel/tcg/tcg-cpus-mttcg.c | 117 +++++++++
23
accel/tcg/tcg-cpus-rr.c | 270 ++++++++++++++++++++
24
accel/tcg/tcg-cpus.c | 484 ++----------------------------------
25
softmmu/icount.c | 2 +-
26
accel/tcg/meson.build | 9 +-
27
11 files changed, 646 insertions(+), 462 deletions(-)
28
create mode 100644 accel/tcg/tcg-cpus-icount.h
29
create mode 100644 accel/tcg/tcg-cpus-mttcg.h
30
create mode 100644 accel/tcg/tcg-cpus-rr.h
31
create mode 100644 accel/tcg/tcg-cpus-icount.c
32
create mode 100644 accel/tcg/tcg-cpus-mttcg.c
33
create mode 100644 accel/tcg/tcg-cpus-rr.c
34
11
35
diff --git a/accel/tcg/tcg-cpus-icount.h b/accel/tcg/tcg-cpus-icount.h
12
diff --git a/meson.build b/meson.build
36
new file mode 100644
13
index XXXXXXX..XXXXXXX 100644
37
index XXXXXXX..XXXXXXX
14
--- a/meson.build
38
--- /dev/null
15
+++ b/meson.build
39
+++ b/accel/tcg/tcg-cpus-icount.h
16
@@ -XXX,XX +XXX,XX @@ config_host_data.set('HAVE_STRCHRNUL', cc.has_function('strchrnul'))
17
config_host_data.set('HAVE_SYSTEM_FUNCTION', cc.has_function('system', prefix: '#include <stdlib.h>'))
18
19
# has_header_symbol
20
-config_host_data.set('CONFIG_BYTESWAP_H',
21
- cc.has_header_symbol('byteswap.h', 'bswap_32'))
22
config_host_data.set('CONFIG_EPOLL_CREATE1',
23
cc.has_header_symbol('sys/epoll.h', 'epoll_create1'))
24
config_host_data.set('CONFIG_HAS_ENVIRON',
25
@@ -XXX,XX +XXX,XX @@ config_host_data.set('CONFIG_INOTIFY',
26
cc.has_header_symbol('sys/inotify.h', 'inotify_init'))
27
config_host_data.set('CONFIG_INOTIFY1',
28
cc.has_header_symbol('sys/inotify.h', 'inotify_init1'))
29
-config_host_data.set('CONFIG_MACHINE_BSWAP_H',
30
- cc.has_header_symbol('machine/bswap.h', 'bswap32',
31
- prefix: '''#include <sys/endian.h>
32
- #include <sys/types.h>'''))
33
config_host_data.set('CONFIG_PRCTL_PR_SET_TIMERSLACK',
34
cc.has_header_symbol('sys/prctl.h', 'PR_SET_TIMERSLACK'))
35
config_host_data.set('CONFIG_RTNETLINK',
36
diff --git a/include/qemu/bswap.h b/include/qemu/bswap.h
37
index XXXXXXX..XXXXXXX 100644
38
--- a/include/qemu/bswap.h
39
+++ b/include/qemu/bswap.h
40
@@ -XXX,XX +XXX,XX @@
40
@@ -XXX,XX +XXX,XX @@
41
+/*
41
#ifndef BSWAP_H
42
+ * QEMU TCG Single Threaded vCPUs implementation using instruction counting
42
#define BSWAP_H
43
+ *
43
44
+ * Copyright 2020 SUSE LLC
44
-#ifdef CONFIG_MACHINE_BSWAP_H
45
+ *
45
-# include <sys/endian.h>
46
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
46
-# include <machine/bswap.h>
47
+ * See the COPYING file in the top-level directory.
47
-#elif defined(__FreeBSD__)
48
+ */
48
-# include <sys/endian.h>
49
+
49
-#elif defined(__HAIKU__)
50
+#ifndef TCG_CPUS_ICOUNT_H
50
-# include <endian.h>
51
+#define TCG_CPUS_ICOUNT_H
51
-#elif defined(CONFIG_BYTESWAP_H)
52
+
52
-# include <byteswap.h>
53
+void handle_icount_deadline(void);
53
-#define BSWAP_FROM_BYTESWAP
54
+void prepare_icount_for_run(CPUState *cpu);
54
-# else
55
+void process_icount_data(CPUState *cpu);
55
-#define BSWAP_FROM_FALLBACKS
56
+
56
-#endif /* ! CONFIG_MACHINE_BSWAP_H */
57
+#endif /* TCG_CPUS_ICOUNT_H */
57
-
58
diff --git a/accel/tcg/tcg-cpus-mttcg.h b/accel/tcg/tcg-cpus-mttcg.h
58
#ifdef __cplusplus
59
new file mode 100644
59
extern "C" {
60
index XXXXXXX..XXXXXXX
60
#endif
61
--- /dev/null
61
62
+++ b/accel/tcg/tcg-cpus-mttcg.h
62
#include "fpu/softfloat-types.h"
63
@@ -XXX,XX +XXX,XX @@
63
64
+/*
64
-#ifdef BSWAP_FROM_BYTESWAP
65
+ * QEMU TCG Multi Threaded vCPUs implementation
65
static inline uint16_t bswap16(uint16_t x)
66
+ *
66
{
67
+ * Copyright 2020 SUSE LLC
67
- return bswap_16(x);
68
+ *
68
+ return __builtin_bswap16(x);
69
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
70
+ * See the COPYING file in the top-level directory.
71
+ */
72
+
73
+#ifndef TCG_CPUS_MTTCG_H
74
+#define TCG_CPUS_MTTCG_H
75
+
76
+/*
77
+ * In the multi-threaded case each vCPU has its own thread. The TLS
78
+ * variable current_cpu can be used deep in the code to find the
79
+ * current CPUState for a given thread.
80
+ */
81
+
82
+void *tcg_cpu_thread_fn(void *arg);
83
+
84
+#endif /* TCG_CPUS_MTTCG_H */
85
diff --git a/accel/tcg/tcg-cpus-rr.h b/accel/tcg/tcg-cpus-rr.h
86
new file mode 100644
87
index XXXXXXX..XXXXXXX
88
--- /dev/null
89
+++ b/accel/tcg/tcg-cpus-rr.h
90
@@ -XXX,XX +XXX,XX @@
91
+/*
92
+ * QEMU TCG Single Threaded vCPUs implementation
93
+ *
94
+ * Copyright 2020 SUSE LLC
95
+ *
96
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
97
+ * See the COPYING file in the top-level directory.
98
+ */
99
+
100
+#ifndef TCG_CPUS_RR_H
101
+#define TCG_CPUS_RR_H
102
+
103
+#define TCG_KICK_PERIOD (NANOSECONDS_PER_SECOND / 10)
104
+
105
+/* Kick all RR vCPUs. */
106
+void qemu_cpu_kick_rr_cpus(CPUState *unused);
107
+
108
+void *tcg_rr_cpu_thread_fn(void *arg);
109
+
110
+#endif /* TCG_CPUS_RR_H */
111
diff --git a/accel/tcg/tcg-cpus.h b/accel/tcg/tcg-cpus.h
112
index XXXXXXX..XXXXXXX 100644
113
--- a/accel/tcg/tcg-cpus.h
114
+++ b/accel/tcg/tcg-cpus.h
115
@@ -XXX,XX +XXX,XX @@
116
/*
117
- * Accelerator CPUS Interface
118
+ * QEMU TCG vCPU common functionality
119
+ *
120
+ * Functionality common to all TCG vcpu variants: mttcg, rr and icount.
121
*
122
* Copyright 2020 SUSE LLC
123
*
124
@@ -XXX,XX +XXX,XX @@
125
126
#include "sysemu/cpus.h"
127
128
-extern const CpusAccel tcg_cpus;
129
+extern const CpusAccel tcg_cpus_mttcg;
130
+extern const CpusAccel tcg_cpus_icount;
131
+extern const CpusAccel tcg_cpus_rr;
132
+
133
+void tcg_start_vcpu_thread(CPUState *cpu);
134
+void qemu_tcg_destroy_vcpu(CPUState *cpu);
135
+int tcg_cpu_exec(CPUState *cpu);
136
+void tcg_handle_interrupt(CPUState *cpu, int mask);
137
138
#endif /* TCG_CPUS_H */
139
diff --git a/accel/tcg/tcg-all.c b/accel/tcg/tcg-all.c
140
index XXXXXXX..XXXXXXX 100644
141
--- a/accel/tcg/tcg-all.c
142
+++ b/accel/tcg/tcg-all.c
143
@@ -XXX,XX +XXX,XX @@ static int tcg_init(MachineState *ms)
144
145
tcg_exec_init(s->tb_size * 1024 * 1024);
146
mttcg_enabled = s->mttcg_enabled;
147
- cpus_register_accel(&tcg_cpus);
148
149
+ if (mttcg_enabled) {
150
+ cpus_register_accel(&tcg_cpus_mttcg);
151
+ } else if (icount_enabled()) {
152
+ cpus_register_accel(&tcg_cpus_icount);
153
+ } else {
154
+ cpus_register_accel(&tcg_cpus_rr);
155
+ }
156
return 0;
157
}
69
}
158
70
159
diff --git a/accel/tcg/tcg-cpus-icount.c b/accel/tcg/tcg-cpus-icount.c
71
static inline uint32_t bswap32(uint32_t x)
160
new file mode 100644
72
{
161
index XXXXXXX..XXXXXXX
73
- return bswap_32(x);
162
--- /dev/null
74
+ return __builtin_bswap32(x);
163
+++ b/accel/tcg/tcg-cpus-icount.c
75
}
164
@@ -XXX,XX +XXX,XX @@
76
165
+/*
77
static inline uint64_t bswap64(uint64_t x)
166
+ * QEMU TCG Single Threaded vCPUs implementation using instruction counting
78
{
167
+ *
79
- return bswap_64(x);
168
+ * Copyright (c) 2003-2008 Fabrice Bellard
80
+ return __builtin_bswap64(x);
169
+ * Copyright (c) 2014 Red Hat Inc.
81
}
170
+ *
82
-#endif
171
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
83
-
172
+ * of this software and associated documentation files (the "Software"), to deal
84
-#ifdef BSWAP_FROM_FALLBACKS
173
+ * in the Software without restriction, including without limitation the rights
85
-static inline uint16_t bswap16(uint16_t x)
174
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
175
+ * copies of the Software, and to permit persons to whom the Software is
176
+ * furnished to do so, subject to the following conditions:
177
+ *
178
+ * The above copyright notice and this permission notice shall be included in
179
+ * all copies or substantial portions of the Software.
180
+ *
181
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
182
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
183
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
184
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
185
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
186
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
187
+ * THE SOFTWARE.
188
+ */
189
+
190
+#include "qemu/osdep.h"
191
+#include "qemu-common.h"
192
+#include "sysemu/tcg.h"
193
+#include "sysemu/replay.h"
194
+#include "qemu/main-loop.h"
195
+#include "qemu/guest-random.h"
196
+#include "exec/exec-all.h"
197
+#include "hw/boards.h"
198
+
199
+#include "tcg-cpus.h"
200
+#include "tcg-cpus-icount.h"
201
+#include "tcg-cpus-rr.h"
202
+
203
+static int64_t tcg_get_icount_limit(void)
204
+{
205
+ int64_t deadline;
206
+
207
+ if (replay_mode != REPLAY_MODE_PLAY) {
208
+ /*
209
+ * Include all the timers, because they may need an attention.
210
+ * Too long CPU execution may create unnecessary delay in UI.
211
+ */
212
+ deadline = qemu_clock_deadline_ns_all(QEMU_CLOCK_VIRTUAL,
213
+ QEMU_TIMER_ATTR_ALL);
214
+ /* Check realtime timers, because they help with input processing */
215
+ deadline = qemu_soonest_timeout(deadline,
216
+ qemu_clock_deadline_ns_all(QEMU_CLOCK_REALTIME,
217
+ QEMU_TIMER_ATTR_ALL));
218
+
219
+ /*
220
+ * Maintain prior (possibly buggy) behaviour where if no deadline
221
+ * was set (as there is no QEMU_CLOCK_VIRTUAL timer) or it is more than
222
+ * INT32_MAX nanoseconds ahead, we still use INT32_MAX
223
+ * nanoseconds.
224
+ */
225
+ if ((deadline < 0) || (deadline > INT32_MAX)) {
226
+ deadline = INT32_MAX;
227
+ }
228
+
229
+ return icount_round(deadline);
230
+ } else {
231
+ return replay_get_instructions();
232
+ }
233
+}
234
+
235
+static void notify_aio_contexts(void)
236
+{
237
+ /* Wake up other AioContexts. */
238
+ qemu_clock_notify(QEMU_CLOCK_VIRTUAL);
239
+ qemu_clock_run_timers(QEMU_CLOCK_VIRTUAL);
240
+}
241
+
242
+void handle_icount_deadline(void)
243
+{
244
+ assert(qemu_in_vcpu_thread());
245
+ int64_t deadline = qemu_clock_deadline_ns_all(QEMU_CLOCK_VIRTUAL,
246
+ QEMU_TIMER_ATTR_ALL);
247
+
248
+ if (deadline == 0) {
249
+ notify_aio_contexts();
250
+ }
251
+}
252
+
253
+void prepare_icount_for_run(CPUState *cpu)
254
+{
255
+ int insns_left;
256
+
257
+ /*
258
+ * These should always be cleared by process_icount_data after
259
+ * each vCPU execution. However u16.high can be raised
260
+ * asynchronously by cpu_exit/cpu_interrupt/tcg_handle_interrupt
261
+ */
262
+ g_assert(cpu_neg(cpu)->icount_decr.u16.low == 0);
263
+ g_assert(cpu->icount_extra == 0);
264
+
265
+ cpu->icount_budget = tcg_get_icount_limit();
266
+ insns_left = MIN(0xffff, cpu->icount_budget);
267
+ cpu_neg(cpu)->icount_decr.u16.low = insns_left;
268
+ cpu->icount_extra = cpu->icount_budget - insns_left;
269
+
270
+ replay_mutex_lock();
271
+
272
+ if (cpu->icount_budget == 0 && replay_has_checkpoint()) {
273
+ notify_aio_contexts();
274
+ }
275
+}
276
+
277
+void process_icount_data(CPUState *cpu)
278
+{
279
+ /* Account for executed instructions */
280
+ icount_update(cpu);
281
+
282
+ /* Reset the counters */
283
+ cpu_neg(cpu)->icount_decr.u16.low = 0;
284
+ cpu->icount_extra = 0;
285
+ cpu->icount_budget = 0;
286
+
287
+ replay_account_executed_instructions();
288
+
289
+ replay_mutex_unlock();
290
+}
291
+
292
+static void icount_handle_interrupt(CPUState *cpu, int mask)
293
+{
294
+ int old_mask = cpu->interrupt_request;
295
+
296
+ tcg_handle_interrupt(cpu, mask);
297
+ if (qemu_cpu_is_self(cpu) &&
298
+ !cpu->can_do_io
299
+ && (mask & ~old_mask) != 0) {
300
+ cpu_abort(cpu, "Raised interrupt while not in I/O function");
301
+ }
302
+}
303
+
304
+const CpusAccel tcg_cpus_icount = {
305
+ .create_vcpu_thread = tcg_start_vcpu_thread,
306
+ .kick_vcpu_thread = qemu_cpu_kick_rr_cpus,
307
+
308
+ .handle_interrupt = icount_handle_interrupt,
309
+ .get_virtual_clock = icount_get,
310
+ .get_elapsed_ticks = icount_get,
311
+};
312
diff --git a/accel/tcg/tcg-cpus-mttcg.c b/accel/tcg/tcg-cpus-mttcg.c
313
new file mode 100644
314
index XXXXXXX..XXXXXXX
315
--- /dev/null
316
+++ b/accel/tcg/tcg-cpus-mttcg.c
317
@@ -XXX,XX +XXX,XX @@
318
+/*
319
+ * QEMU TCG Multi Threaded vCPUs implementation
320
+ *
321
+ * Copyright (c) 2003-2008 Fabrice Bellard
322
+ * Copyright (c) 2014 Red Hat Inc.
323
+ *
324
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
325
+ * of this software and associated documentation files (the "Software"), to deal
326
+ * in the Software without restriction, including without limitation the rights
327
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
328
+ * copies of the Software, and to permit persons to whom the Software is
329
+ * furnished to do so, subject to the following conditions:
330
+ *
331
+ * The above copyright notice and this permission notice shall be included in
332
+ * all copies or substantial portions of the Software.
333
+ *
334
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
335
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
336
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
337
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
338
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
339
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
340
+ * THE SOFTWARE.
341
+ */
342
+
343
+#include "qemu/osdep.h"
344
+#include "qemu-common.h"
345
+#include "sysemu/tcg.h"
346
+#include "sysemu/replay.h"
347
+#include "qemu/main-loop.h"
348
+#include "qemu/guest-random.h"
349
+#include "exec/exec-all.h"
350
+#include "hw/boards.h"
351
+
352
+#include "tcg-cpus.h"
353
+#include "tcg-cpus-mttcg.h"
354
+
355
+/*
356
+ * In the multi-threaded case each vCPU has its own thread. The TLS
357
+ * variable current_cpu can be used deep in the code to find the
358
+ * current CPUState for a given thread.
359
+ */
360
+
361
+void *tcg_cpu_thread_fn(void *arg)
362
+{
363
+ CPUState *cpu = arg;
364
+
365
+ assert(tcg_enabled());
366
+ g_assert(!icount_enabled());
367
+
368
+ rcu_register_thread();
369
+ tcg_register_thread();
370
+
371
+ qemu_mutex_lock_iothread();
372
+ qemu_thread_get_self(cpu->thread);
373
+
374
+ cpu->thread_id = qemu_get_thread_id();
375
+ cpu->can_do_io = 1;
376
+ current_cpu = cpu;
377
+ cpu_thread_signal_created(cpu);
378
+ qemu_guest_random_seed_thread_part2(cpu->random_seed);
379
+
380
+ /* process any pending work */
381
+ cpu->exit_request = 1;
382
+
383
+ do {
384
+ if (cpu_can_run(cpu)) {
385
+ int r;
386
+ qemu_mutex_unlock_iothread();
387
+ r = tcg_cpu_exec(cpu);
388
+ qemu_mutex_lock_iothread();
389
+ switch (r) {
390
+ case EXCP_DEBUG:
391
+ cpu_handle_guest_debug(cpu);
392
+ break;
393
+ case EXCP_HALTED:
394
+ /*
395
+ * during start-up the vCPU is reset and the thread is
396
+ * kicked several times. If we don't ensure we go back
397
+ * to sleep in the halted state we won't cleanly
398
+ * start-up when the vCPU is enabled.
399
+ *
400
+ * cpu->halted should ensure we sleep in wait_io_event
401
+ */
402
+ g_assert(cpu->halted);
403
+ break;
404
+ case EXCP_ATOMIC:
405
+ qemu_mutex_unlock_iothread();
406
+ cpu_exec_step_atomic(cpu);
407
+ qemu_mutex_lock_iothread();
408
+ default:
409
+ /* Ignore everything else? */
410
+ break;
411
+ }
412
+ }
413
+
414
+ qatomic_mb_set(&cpu->exit_request, 0);
415
+ qemu_wait_io_event(cpu);
416
+ } while (!cpu->unplug || cpu_can_run(cpu));
417
+
418
+ qemu_tcg_destroy_vcpu(cpu);
419
+ qemu_mutex_unlock_iothread();
420
+ rcu_unregister_thread();
421
+ return NULL;
422
+}
423
+
424
+static void mttcg_kick_vcpu_thread(CPUState *cpu)
425
+{
426
+ cpu_exit(cpu);
427
+}
428
+
429
+const CpusAccel tcg_cpus_mttcg = {
430
+ .create_vcpu_thread = tcg_start_vcpu_thread,
431
+ .kick_vcpu_thread = mttcg_kick_vcpu_thread,
432
+
433
+ .handle_interrupt = tcg_handle_interrupt,
434
+};
435
diff --git a/accel/tcg/tcg-cpus-rr.c b/accel/tcg/tcg-cpus-rr.c
436
new file mode 100644
437
index XXXXXXX..XXXXXXX
438
--- /dev/null
439
+++ b/accel/tcg/tcg-cpus-rr.c
440
@@ -XXX,XX +XXX,XX @@
441
+/*
442
+ * QEMU TCG Single Threaded vCPUs implementation
443
+ *
444
+ * Copyright (c) 2003-2008 Fabrice Bellard
445
+ * Copyright (c) 2014 Red Hat Inc.
446
+ *
447
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
448
+ * of this software and associated documentation files (the "Software"), to deal
449
+ * in the Software without restriction, including without limitation the rights
450
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
451
+ * copies of the Software, and to permit persons to whom the Software is
452
+ * furnished to do so, subject to the following conditions:
453
+ *
454
+ * The above copyright notice and this permission notice shall be included in
455
+ * all copies or substantial portions of the Software.
456
+ *
457
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
458
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
459
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
460
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
461
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
462
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
463
+ * THE SOFTWARE.
464
+ */
465
+
466
+#include "qemu/osdep.h"
467
+#include "qemu-common.h"
468
+#include "sysemu/tcg.h"
469
+#include "sysemu/replay.h"
470
+#include "qemu/main-loop.h"
471
+#include "qemu/guest-random.h"
472
+#include "exec/exec-all.h"
473
+#include "hw/boards.h"
474
+
475
+#include "tcg-cpus.h"
476
+#include "tcg-cpus-rr.h"
477
+#include "tcg-cpus-icount.h"
478
+
479
+/* Kick all RR vCPUs */
480
+void qemu_cpu_kick_rr_cpus(CPUState *unused)
481
+{
482
+ CPUState *cpu;
483
+
484
+ CPU_FOREACH(cpu) {
485
+ cpu_exit(cpu);
486
+ };
487
+}
488
+
489
+/*
490
+ * TCG vCPU kick timer
491
+ *
492
+ * The kick timer is responsible for moving single threaded vCPU
493
+ * emulation on to the next vCPU. If more than one vCPU is running a
494
+ * timer event with force a cpu->exit so the next vCPU can get
495
+ * scheduled.
496
+ *
497
+ * The timer is removed if all vCPUs are idle and restarted again once
498
+ * idleness is complete.
499
+ */
500
+
501
+static QEMUTimer *tcg_kick_vcpu_timer;
502
+static CPUState *tcg_current_rr_cpu;
503
+
504
+#define TCG_KICK_PERIOD (NANOSECONDS_PER_SECOND / 10)
505
+
506
+static inline int64_t qemu_tcg_next_kick(void)
507
+{
508
+ return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + TCG_KICK_PERIOD;
509
+}
510
+
511
+/* Kick the currently round-robin scheduled vCPU to next */
512
+static void qemu_cpu_kick_rr_next_cpu(void)
513
+{
514
+ CPUState *cpu;
515
+ do {
516
+ cpu = qatomic_mb_read(&tcg_current_rr_cpu);
517
+ if (cpu) {
518
+ cpu_exit(cpu);
519
+ }
520
+ } while (cpu != qatomic_mb_read(&tcg_current_rr_cpu));
521
+}
522
+
523
+static void kick_tcg_thread(void *opaque)
524
+{
525
+ timer_mod(tcg_kick_vcpu_timer, qemu_tcg_next_kick());
526
+ qemu_cpu_kick_rr_next_cpu();
527
+}
528
+
529
+static void start_tcg_kick_timer(void)
530
+{
531
+ if (!tcg_kick_vcpu_timer && CPU_NEXT(first_cpu)) {
532
+ tcg_kick_vcpu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
533
+ kick_tcg_thread, NULL);
534
+ }
535
+ if (tcg_kick_vcpu_timer && !timer_pending(tcg_kick_vcpu_timer)) {
536
+ timer_mod(tcg_kick_vcpu_timer, qemu_tcg_next_kick());
537
+ }
538
+}
539
+
540
+static void stop_tcg_kick_timer(void)
541
+{
542
+ if (tcg_kick_vcpu_timer && timer_pending(tcg_kick_vcpu_timer)) {
543
+ timer_del(tcg_kick_vcpu_timer);
544
+ }
545
+}
546
+
547
+static void qemu_tcg_rr_wait_io_event(void)
548
+{
549
+ CPUState *cpu;
550
+
551
+ while (all_cpu_threads_idle()) {
552
+ stop_tcg_kick_timer();
553
+ qemu_cond_wait_iothread(first_cpu->halt_cond);
554
+ }
555
+
556
+ start_tcg_kick_timer();
557
+
558
+ CPU_FOREACH(cpu) {
559
+ qemu_wait_io_event_common(cpu);
560
+ }
561
+}
562
+
563
+/*
564
+ * Destroy any remaining vCPUs which have been unplugged and have
565
+ * finished running
566
+ */
567
+static void deal_with_unplugged_cpus(void)
568
+{
569
+ CPUState *cpu;
570
+
571
+ CPU_FOREACH(cpu) {
572
+ if (cpu->unplug && !cpu_can_run(cpu)) {
573
+ qemu_tcg_destroy_vcpu(cpu);
574
+ break;
575
+ }
576
+ }
577
+}
578
+
579
+/*
580
+ * In the single-threaded case each vCPU is simulated in turn. If
581
+ * there is more than a single vCPU we create a simple timer to kick
582
+ * the vCPU and ensure we don't get stuck in a tight loop in one vCPU.
583
+ * This is done explicitly rather than relying on side-effects
584
+ * elsewhere.
585
+ */
586
+
587
+void *tcg_rr_cpu_thread_fn(void *arg)
588
+{
589
+ CPUState *cpu = arg;
590
+
591
+ assert(tcg_enabled());
592
+ rcu_register_thread();
593
+ tcg_register_thread();
594
+
595
+ qemu_mutex_lock_iothread();
596
+ qemu_thread_get_self(cpu->thread);
597
+
598
+ cpu->thread_id = qemu_get_thread_id();
599
+ cpu->can_do_io = 1;
600
+ cpu_thread_signal_created(cpu);
601
+ qemu_guest_random_seed_thread_part2(cpu->random_seed);
602
+
603
+ /* wait for initial kick-off after machine start */
604
+ while (first_cpu->stopped) {
605
+ qemu_cond_wait_iothread(first_cpu->halt_cond);
606
+
607
+ /* process any pending work */
608
+ CPU_FOREACH(cpu) {
609
+ current_cpu = cpu;
610
+ qemu_wait_io_event_common(cpu);
611
+ }
612
+ }
613
+
614
+ start_tcg_kick_timer();
615
+
616
+ cpu = first_cpu;
617
+
618
+ /* process any pending work */
619
+ cpu->exit_request = 1;
620
+
621
+ while (1) {
622
+ qemu_mutex_unlock_iothread();
623
+ replay_mutex_lock();
624
+ qemu_mutex_lock_iothread();
625
+
626
+ if (icount_enabled()) {
627
+ /* Account partial waits to QEMU_CLOCK_VIRTUAL. */
628
+ icount_account_warp_timer();
629
+ /*
630
+ * Run the timers here. This is much more efficient than
631
+ * waking up the I/O thread and waiting for completion.
632
+ */
633
+ handle_icount_deadline();
634
+ }
635
+
636
+ replay_mutex_unlock();
637
+
638
+ if (!cpu) {
639
+ cpu = first_cpu;
640
+ }
641
+
642
+ while (cpu && cpu_work_list_empty(cpu) && !cpu->exit_request) {
643
+
644
+ qatomic_mb_set(&tcg_current_rr_cpu, cpu);
645
+ current_cpu = cpu;
646
+
647
+ qemu_clock_enable(QEMU_CLOCK_VIRTUAL,
648
+ (cpu->singlestep_enabled & SSTEP_NOTIMER) == 0);
649
+
650
+ if (cpu_can_run(cpu)) {
651
+ int r;
652
+
653
+ qemu_mutex_unlock_iothread();
654
+ if (icount_enabled()) {
655
+ prepare_icount_for_run(cpu);
656
+ }
657
+ r = tcg_cpu_exec(cpu);
658
+ if (icount_enabled()) {
659
+ process_icount_data(cpu);
660
+ }
661
+ qemu_mutex_lock_iothread();
662
+
663
+ if (r == EXCP_DEBUG) {
664
+ cpu_handle_guest_debug(cpu);
665
+ break;
666
+ } else if (r == EXCP_ATOMIC) {
667
+ qemu_mutex_unlock_iothread();
668
+ cpu_exec_step_atomic(cpu);
669
+ qemu_mutex_lock_iothread();
670
+ break;
671
+ }
672
+ } else if (cpu->stop) {
673
+ if (cpu->unplug) {
674
+ cpu = CPU_NEXT(cpu);
675
+ }
676
+ break;
677
+ }
678
+
679
+ cpu = CPU_NEXT(cpu);
680
+ } /* while (cpu && !cpu->exit_request).. */
681
+
682
+ /* Does not need qatomic_mb_set because a spurious wakeup is okay. */
683
+ qatomic_set(&tcg_current_rr_cpu, NULL);
684
+
685
+ if (cpu && cpu->exit_request) {
686
+ qatomic_mb_set(&cpu->exit_request, 0);
687
+ }
688
+
689
+ if (icount_enabled() && all_cpu_threads_idle()) {
690
+ /*
691
+ * When all cpus are sleeping (e.g in WFI), to avoid a deadlock
692
+ * in the main_loop, wake it up in order to start the warp timer.
693
+ */
694
+ qemu_notify_event();
695
+ }
696
+
697
+ qemu_tcg_rr_wait_io_event();
698
+ deal_with_unplugged_cpus();
699
+ }
700
+
701
+ rcu_unregister_thread();
702
+ return NULL;
703
+}
704
+
705
+const CpusAccel tcg_cpus_rr = {
706
+ .create_vcpu_thread = tcg_start_vcpu_thread,
707
+ .kick_vcpu_thread = qemu_cpu_kick_rr_cpus,
708
+
709
+ .handle_interrupt = tcg_handle_interrupt,
710
+};
711
diff --git a/accel/tcg/tcg-cpus.c b/accel/tcg/tcg-cpus.c
712
index XXXXXXX..XXXXXXX 100644
713
--- a/accel/tcg/tcg-cpus.c
714
+++ b/accel/tcg/tcg-cpus.c
715
@@ -XXX,XX +XXX,XX @@
716
/*
717
- * QEMU System Emulator
718
+ * QEMU TCG vCPU common functionality
719
+ *
720
+ * Functionality common to all TCG vCPU variants: mttcg, rr and icount.
721
*
722
* Copyright (c) 2003-2008 Fabrice Bellard
723
* Copyright (c) 2014 Red Hat Inc.
724
@@ -XXX,XX +XXX,XX @@
725
#include "hw/boards.h"
726
727
#include "tcg-cpus.h"
728
+#include "tcg-cpus-mttcg.h"
729
+#include "tcg-cpus-rr.h"
730
731
-/* Kick all RR vCPUs */
732
-static void qemu_cpu_kick_rr_cpus(void)
733
-{
86
-{
734
- CPUState *cpu;
87
- return (((x & 0x00ff) << 8) |
735
+/* common functionality among all TCG variants */
88
- ((x & 0xff00) >> 8));
736
737
- CPU_FOREACH(cpu) {
738
- cpu_exit(cpu);
739
- };
740
-}
89
-}
741
-
90
-
742
-static void tcg_kick_vcpu_thread(CPUState *cpu)
91
-static inline uint32_t bswap32(uint32_t x)
743
-{
92
-{
744
- if (qemu_tcg_mttcg_enabled()) {
93
- return (((x & 0x000000ffU) << 24) |
745
- cpu_exit(cpu);
94
- ((x & 0x0000ff00U) << 8) |
746
- } else {
95
- ((x & 0x00ff0000U) >> 8) |
747
- qemu_cpu_kick_rr_cpus();
96
- ((x & 0xff000000U) >> 24));
748
- }
749
-}
97
-}
750
-
98
-
751
-/*
99
-static inline uint64_t bswap64(uint64_t x)
752
- * TCG vCPU kick timer
753
- *
754
- * The kick timer is responsible for moving single threaded vCPU
755
- * emulation on to the next vCPU. If more than one vCPU is running a
756
- * timer event with force a cpu->exit so the next vCPU can get
757
- * scheduled.
758
- *
759
- * The timer is removed if all vCPUs are idle and restarted again once
760
- * idleness is complete.
761
- */
762
-
763
-static QEMUTimer *tcg_kick_vcpu_timer;
764
-static CPUState *tcg_current_rr_cpu;
765
-
766
-#define TCG_KICK_PERIOD (NANOSECONDS_PER_SECOND / 10)
767
-
768
-static inline int64_t qemu_tcg_next_kick(void)
769
-{
100
-{
770
- return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + TCG_KICK_PERIOD;
101
- return (((x & 0x00000000000000ffULL) << 56) |
102
- ((x & 0x000000000000ff00ULL) << 40) |
103
- ((x & 0x0000000000ff0000ULL) << 24) |
104
- ((x & 0x00000000ff000000ULL) << 8) |
105
- ((x & 0x000000ff00000000ULL) >> 8) |
106
- ((x & 0x0000ff0000000000ULL) >> 24) |
107
- ((x & 0x00ff000000000000ULL) >> 40) |
108
- ((x & 0xff00000000000000ULL) >> 56));
771
-}
109
-}
772
-
773
-/* Kick the currently round-robin scheduled vCPU to next */
774
-static void qemu_cpu_kick_rr_next_cpu(void)
775
-{
776
- CPUState *cpu;
777
- do {
778
- cpu = qatomic_mb_read(&tcg_current_rr_cpu);
779
- if (cpu) {
780
- cpu_exit(cpu);
781
- }
782
- } while (cpu != qatomic_mb_read(&tcg_current_rr_cpu));
783
-}
784
-
785
-static void kick_tcg_thread(void *opaque)
786
-{
787
- timer_mod(tcg_kick_vcpu_timer, qemu_tcg_next_kick());
788
- qemu_cpu_kick_rr_next_cpu();
789
-}
790
-
791
-static void start_tcg_kick_timer(void)
792
-{
793
- assert(!mttcg_enabled);
794
- if (!tcg_kick_vcpu_timer && CPU_NEXT(first_cpu)) {
795
- tcg_kick_vcpu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
796
- kick_tcg_thread, NULL);
797
- }
798
- if (tcg_kick_vcpu_timer && !timer_pending(tcg_kick_vcpu_timer)) {
799
- timer_mod(tcg_kick_vcpu_timer, qemu_tcg_next_kick());
800
- }
801
-}
802
-
803
-static void stop_tcg_kick_timer(void)
804
-{
805
- assert(!mttcg_enabled);
806
- if (tcg_kick_vcpu_timer && timer_pending(tcg_kick_vcpu_timer)) {
807
- timer_del(tcg_kick_vcpu_timer);
808
- }
809
-}
810
-
811
-static void qemu_tcg_destroy_vcpu(CPUState *cpu)
812
-{
813
-}
814
-
815
-static void qemu_tcg_rr_wait_io_event(void)
816
-{
817
- CPUState *cpu;
818
-
819
- while (all_cpu_threads_idle()) {
820
- stop_tcg_kick_timer();
821
- qemu_cond_wait_iothread(first_cpu->halt_cond);
822
- }
823
-
824
- start_tcg_kick_timer();
825
-
826
- CPU_FOREACH(cpu) {
827
- qemu_wait_io_event_common(cpu);
828
- }
829
-}
830
-
831
-static int64_t tcg_get_icount_limit(void)
832
-{
833
- int64_t deadline;
834
-
835
- if (replay_mode != REPLAY_MODE_PLAY) {
836
- /*
837
- * Include all the timers, because they may need an attention.
838
- * Too long CPU execution may create unnecessary delay in UI.
839
- */
840
- deadline = qemu_clock_deadline_ns_all(QEMU_CLOCK_VIRTUAL,
841
- QEMU_TIMER_ATTR_ALL);
842
- /* Check realtime timers, because they help with input processing */
843
- deadline = qemu_soonest_timeout(deadline,
844
- qemu_clock_deadline_ns_all(QEMU_CLOCK_REALTIME,
845
- QEMU_TIMER_ATTR_ALL));
846
-
847
- /*
848
- * Maintain prior (possibly buggy) behaviour where if no deadline
849
- * was set (as there is no QEMU_CLOCK_VIRTUAL timer) or it is more than
850
- * INT32_MAX nanoseconds ahead, we still use INT32_MAX
851
- * nanoseconds.
852
- */
853
- if ((deadline < 0) || (deadline > INT32_MAX)) {
854
- deadline = INT32_MAX;
855
- }
856
-
857
- return icount_round(deadline);
858
- } else {
859
- return replay_get_instructions();
860
- }
861
-}
862
-
863
-static void notify_aio_contexts(void)
864
-{
865
- /* Wake up other AioContexts. */
866
- qemu_clock_notify(QEMU_CLOCK_VIRTUAL);
867
- qemu_clock_run_timers(QEMU_CLOCK_VIRTUAL);
868
-}
869
-
870
-static void handle_icount_deadline(void)
871
-{
872
- assert(qemu_in_vcpu_thread());
873
- if (icount_enabled()) {
874
- int64_t deadline = qemu_clock_deadline_ns_all(QEMU_CLOCK_VIRTUAL,
875
- QEMU_TIMER_ATTR_ALL);
876
-
877
- if (deadline == 0) {
878
- notify_aio_contexts();
879
- }
880
- }
881
-}
882
-
883
-static void prepare_icount_for_run(CPUState *cpu)
884
-{
885
- if (icount_enabled()) {
886
- int insns_left;
887
-
888
- /*
889
- * These should always be cleared by process_icount_data after
890
- * each vCPU execution. However u16.high can be raised
891
- * asynchronously by cpu_exit/cpu_interrupt/tcg_handle_interrupt
892
- */
893
- g_assert(cpu_neg(cpu)->icount_decr.u16.low == 0);
894
- g_assert(cpu->icount_extra == 0);
895
-
896
- cpu->icount_budget = tcg_get_icount_limit();
897
- insns_left = MIN(0xffff, cpu->icount_budget);
898
- cpu_neg(cpu)->icount_decr.u16.low = insns_left;
899
- cpu->icount_extra = cpu->icount_budget - insns_left;
900
-
901
- replay_mutex_lock();
902
-
903
- if (cpu->icount_budget == 0 && replay_has_checkpoint()) {
904
- notify_aio_contexts();
905
- }
906
- }
907
-}
908
-
909
-static void process_icount_data(CPUState *cpu)
910
-{
911
- if (icount_enabled()) {
912
- /* Account for executed instructions */
913
- icount_update(cpu);
914
-
915
- /* Reset the counters */
916
- cpu_neg(cpu)->icount_decr.u16.low = 0;
917
- cpu->icount_extra = 0;
918
- cpu->icount_budget = 0;
919
-
920
- replay_account_executed_instructions();
921
-
922
- replay_mutex_unlock();
923
- }
924
-}
925
-
926
-static int tcg_cpu_exec(CPUState *cpu)
927
-{
928
- int ret;
929
-#ifdef CONFIG_PROFILER
930
- int64_t ti;
931
-#endif
110
-#endif
932
-
111
-
933
- assert(tcg_enabled());
112
-#undef BSWAP_FROM_BYTESWAP
934
-#ifdef CONFIG_PROFILER
113
-#undef BSWAP_FROM_FALLBACKS
935
- ti = profile_getclock();
114
936
-#endif
115
static inline void bswap16s(uint16_t *s)
937
- cpu_exec_start(cpu);
938
- ret = cpu_exec(cpu);
939
- cpu_exec_end(cpu);
940
-#ifdef CONFIG_PROFILER
941
- qatomic_set(&tcg_ctx->prof.cpu_exec_time,
942
- tcg_ctx->prof.cpu_exec_time + profile_getclock() - ti);
943
-#endif
944
- return ret;
945
-}
946
-
947
-/*
948
- * Destroy any remaining vCPUs which have been unplugged and have
949
- * finished running
950
- */
951
-static void deal_with_unplugged_cpus(void)
952
-{
953
- CPUState *cpu;
954
-
955
- CPU_FOREACH(cpu) {
956
- if (cpu->unplug && !cpu_can_run(cpu)) {
957
- qemu_tcg_destroy_vcpu(cpu);
958
- cpu_thread_signal_destroyed(cpu);
959
- break;
960
- }
961
- }
962
-}
963
-
964
-/*
965
- * Single-threaded TCG
966
- *
967
- * In the single-threaded case each vCPU is simulated in turn. If
968
- * there is more than a single vCPU we create a simple timer to kick
969
- * the vCPU and ensure we don't get stuck in a tight loop in one vCPU.
970
- * This is done explicitly rather than relying on side-effects
971
- * elsewhere.
972
- */
973
-
974
-static void *tcg_rr_cpu_thread_fn(void *arg)
975
-{
976
- CPUState *cpu = arg;
977
-
978
- assert(tcg_enabled());
979
- rcu_register_thread();
980
- tcg_register_thread();
981
-
982
- qemu_mutex_lock_iothread();
983
- qemu_thread_get_self(cpu->thread);
984
-
985
- cpu->thread_id = qemu_get_thread_id();
986
- cpu->can_do_io = 1;
987
- cpu_thread_signal_created(cpu);
988
- qemu_guest_random_seed_thread_part2(cpu->random_seed);
989
-
990
- /* wait for initial kick-off after machine start */
991
- while (first_cpu->stopped) {
992
- qemu_cond_wait_iothread(first_cpu->halt_cond);
993
-
994
- /* process any pending work */
995
- CPU_FOREACH(cpu) {
996
- current_cpu = cpu;
997
- qemu_wait_io_event_common(cpu);
998
- }
999
- }
1000
-
1001
- start_tcg_kick_timer();
1002
-
1003
- cpu = first_cpu;
1004
-
1005
- /* process any pending work */
1006
- cpu->exit_request = 1;
1007
-
1008
- while (1) {
1009
- qemu_mutex_unlock_iothread();
1010
- replay_mutex_lock();
1011
- qemu_mutex_lock_iothread();
1012
- /* Account partial waits to QEMU_CLOCK_VIRTUAL. */
1013
- icount_account_warp_timer();
1014
-
1015
- /*
1016
- * Run the timers here. This is much more efficient than
1017
- * waking up the I/O thread and waiting for completion.
1018
- */
1019
- handle_icount_deadline();
1020
-
1021
- replay_mutex_unlock();
1022
-
1023
- if (!cpu) {
1024
- cpu = first_cpu;
1025
- }
1026
-
1027
- while (cpu && cpu_work_list_empty(cpu) && !cpu->exit_request) {
1028
-
1029
- qatomic_mb_set(&tcg_current_rr_cpu, cpu);
1030
- current_cpu = cpu;
1031
-
1032
- qemu_clock_enable(QEMU_CLOCK_VIRTUAL,
1033
- (cpu->singlestep_enabled & SSTEP_NOTIMER) == 0);
1034
-
1035
- if (cpu_can_run(cpu)) {
1036
- int r;
1037
-
1038
- qemu_mutex_unlock_iothread();
1039
- prepare_icount_for_run(cpu);
1040
-
1041
- r = tcg_cpu_exec(cpu);
1042
-
1043
- process_icount_data(cpu);
1044
- qemu_mutex_lock_iothread();
1045
-
1046
- if (r == EXCP_DEBUG) {
1047
- cpu_handle_guest_debug(cpu);
1048
- break;
1049
- } else if (r == EXCP_ATOMIC) {
1050
- qemu_mutex_unlock_iothread();
1051
- cpu_exec_step_atomic(cpu);
1052
- qemu_mutex_lock_iothread();
1053
- break;
1054
- }
1055
- } else if (cpu->stop) {
1056
- if (cpu->unplug) {
1057
- cpu = CPU_NEXT(cpu);
1058
- }
1059
- break;
1060
- }
1061
-
1062
- cpu = CPU_NEXT(cpu);
1063
- } /* while (cpu && !cpu->exit_request).. */
1064
-
1065
- /* Does not need qatomic_mb_set because a spurious wakeup is okay. */
1066
- qatomic_set(&tcg_current_rr_cpu, NULL);
1067
-
1068
- if (cpu && cpu->exit_request) {
1069
- qatomic_mb_set(&cpu->exit_request, 0);
1070
- }
1071
-
1072
- if (icount_enabled() && all_cpu_threads_idle()) {
1073
- /*
1074
- * When all cpus are sleeping (e.g in WFI), to avoid a deadlock
1075
- * in the main_loop, wake it up in order to start the warp timer.
1076
- */
1077
- qemu_notify_event();
1078
- }
1079
-
1080
- qemu_tcg_rr_wait_io_event();
1081
- deal_with_unplugged_cpus();
1082
- }
1083
-
1084
- rcu_unregister_thread();
1085
- return NULL;
1086
-}
1087
-
1088
-/*
1089
- * Multi-threaded TCG
1090
- *
1091
- * In the multi-threaded case each vCPU has its own thread. The TLS
1092
- * variable current_cpu can be used deep in the code to find the
1093
- * current CPUState for a given thread.
1094
- */
1095
-
1096
-static void *tcg_cpu_thread_fn(void *arg)
1097
-{
1098
- CPUState *cpu = arg;
1099
-
1100
- assert(tcg_enabled());
1101
- g_assert(!icount_enabled());
1102
-
1103
- rcu_register_thread();
1104
- tcg_register_thread();
1105
-
1106
- qemu_mutex_lock_iothread();
1107
- qemu_thread_get_self(cpu->thread);
1108
-
1109
- cpu->thread_id = qemu_get_thread_id();
1110
- cpu->can_do_io = 1;
1111
- current_cpu = cpu;
1112
- cpu_thread_signal_created(cpu);
1113
- qemu_guest_random_seed_thread_part2(cpu->random_seed);
1114
-
1115
- /* process any pending work */
1116
- cpu->exit_request = 1;
1117
-
1118
- do {
1119
- if (cpu_can_run(cpu)) {
1120
- int r;
1121
- qemu_mutex_unlock_iothread();
1122
- r = tcg_cpu_exec(cpu);
1123
- qemu_mutex_lock_iothread();
1124
- switch (r) {
1125
- case EXCP_DEBUG:
1126
- cpu_handle_guest_debug(cpu);
1127
- break;
1128
- case EXCP_HALTED:
1129
- /*
1130
- * during start-up the vCPU is reset and the thread is
1131
- * kicked several times. If we don't ensure we go back
1132
- * to sleep in the halted state we won't cleanly
1133
- * start-up when the vCPU is enabled.
1134
- *
1135
- * cpu->halted should ensure we sleep in wait_io_event
1136
- */
1137
- g_assert(cpu->halted);
1138
- break;
1139
- case EXCP_ATOMIC:
1140
- qemu_mutex_unlock_iothread();
1141
- cpu_exec_step_atomic(cpu);
1142
- qemu_mutex_lock_iothread();
1143
- default:
1144
- /* Ignore everything else? */
1145
- break;
1146
- }
1147
- }
1148
-
1149
- qatomic_mb_set(&cpu->exit_request, 0);
1150
- qemu_wait_io_event(cpu);
1151
- } while (!cpu->unplug || cpu_can_run(cpu));
1152
-
1153
- qemu_tcg_destroy_vcpu(cpu);
1154
- cpu_thread_signal_destroyed(cpu);
1155
- qemu_mutex_unlock_iothread();
1156
- rcu_unregister_thread();
1157
- return NULL;
1158
-}
1159
-
1160
-static void tcg_start_vcpu_thread(CPUState *cpu)
1161
+void tcg_start_vcpu_thread(CPUState *cpu)
1162
{
116
{
1163
char thread_name[VCPU_THREAD_NAME_SIZE];
1164
static QemuCond *single_tcg_halt_cond;
1165
@@ -XXX,XX +XXX,XX @@ static void tcg_start_vcpu_thread(CPUState *cpu)
1166
}
1167
}
1168
1169
-static int64_t tcg_get_virtual_clock(void)
1170
+void qemu_tcg_destroy_vcpu(CPUState *cpu)
1171
{
1172
- if (icount_enabled()) {
1173
- return icount_get();
1174
- }
1175
- return cpu_get_clock();
1176
+ cpu_thread_signal_destroyed(cpu);
1177
}
1178
1179
-static int64_t tcg_get_elapsed_ticks(void)
1180
+int tcg_cpu_exec(CPUState *cpu)
1181
{
1182
- if (icount_enabled()) {
1183
- return icount_get();
1184
- }
1185
- return cpu_get_ticks();
1186
+ int ret;
1187
+#ifdef CONFIG_PROFILER
1188
+ int64_t ti;
1189
+#endif
1190
+ assert(tcg_enabled());
1191
+#ifdef CONFIG_PROFILER
1192
+ ti = profile_getclock();
1193
+#endif
1194
+ cpu_exec_start(cpu);
1195
+ ret = cpu_exec(cpu);
1196
+ cpu_exec_end(cpu);
1197
+#ifdef CONFIG_PROFILER
1198
+ qatomic_set(&tcg_ctx->prof.cpu_exec_time,
1199
+ tcg_ctx->prof.cpu_exec_time + profile_getclock() - ti);
1200
+#endif
1201
+ return ret;
1202
}
1203
1204
/* mask must never be zero, except for A20 change call */
1205
-static void tcg_handle_interrupt(CPUState *cpu, int mask)
1206
+void tcg_handle_interrupt(CPUState *cpu, int mask)
1207
{
1208
- int old_mask;
1209
g_assert(qemu_mutex_iothread_locked());
1210
1211
- old_mask = cpu->interrupt_request;
1212
cpu->interrupt_request |= mask;
1213
1214
/*
1215
@@ -XXX,XX +XXX,XX @@ static void tcg_handle_interrupt(CPUState *cpu, int mask)
1216
qemu_cpu_kick(cpu);
1217
} else {
1218
qatomic_set(&cpu_neg(cpu)->icount_decr.u16.high, -1);
1219
- if (icount_enabled() &&
1220
- !cpu->can_do_io
1221
- && (mask & ~old_mask) != 0) {
1222
- cpu_abort(cpu, "Raised interrupt while not in I/O function");
1223
- }
1224
}
1225
}
1226
-
1227
-const CpusAccel tcg_cpus = {
1228
- .create_vcpu_thread = tcg_start_vcpu_thread,
1229
- .kick_vcpu_thread = tcg_kick_vcpu_thread,
1230
-
1231
- .handle_interrupt = tcg_handle_interrupt,
1232
-
1233
- .get_virtual_clock = tcg_get_virtual_clock,
1234
- .get_elapsed_ticks = tcg_get_elapsed_ticks,
1235
-};
1236
diff --git a/softmmu/icount.c b/softmmu/icount.c
1237
index XXXXXXX..XXXXXXX 100644
1238
--- a/softmmu/icount.c
1239
+++ b/softmmu/icount.c
1240
@@ -XXX,XX +XXX,XX @@ void icount_start_warp_timer(void)
1241
1242
void icount_account_warp_timer(void)
1243
{
1244
- if (!icount_enabled() || !icount_sleep) {
1245
+ if (!icount_sleep) {
1246
return;
1247
}
1248
1249
diff --git a/accel/tcg/meson.build b/accel/tcg/meson.build
1250
index XXXXXXX..XXXXXXX 100644
1251
--- a/accel/tcg/meson.build
1252
+++ b/accel/tcg/meson.build
1253
@@ -XXX,XX +XXX,XX @@ tcg_ss.add(when: 'CONFIG_SOFTMMU', if_false: files('user-exec-stub.c'))
1254
tcg_ss.add(when: 'CONFIG_PLUGIN', if_true: [files('plugin-gen.c'), libdl])
1255
specific_ss.add_all(when: 'CONFIG_TCG', if_true: tcg_ss)
1256
1257
-specific_ss.add(when: ['CONFIG_SOFTMMU', 'CONFIG_TCG'], if_true: files('tcg-all.c', 'cputlb.c', 'tcg-cpus.c'))
1258
+specific_ss.add(when: ['CONFIG_SOFTMMU', 'CONFIG_TCG'], if_true: files(
1259
+ 'tcg-all.c',
1260
+ 'cputlb.c',
1261
+ 'tcg-cpus.c',
1262
+ 'tcg-cpus-mttcg.c',
1263
+ 'tcg-cpus-icount.c',
1264
+ 'tcg-cpus-rr.c'
1265
+))
1266
--
117
--
1267
2.25.1
118
2.25.1
1268
119
1269
120
diff view generated by jsdifflib
New patch
1
If __APPLE__, ensure that _CALL_DARWIN is set, then remove
2
our local TCG_TARGET_CALL_DARWIN.
1
3
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
---
6
tcg/ppc/tcg-target.c.inc | 8 ++++----
7
1 file changed, 4 insertions(+), 4 deletions(-)
8
9
diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc
10
index XXXXXXX..XXXXXXX 100644
11
--- a/tcg/ppc/tcg-target.c.inc
12
+++ b/tcg/ppc/tcg-target.c.inc
13
@@ -XXX,XX +XXX,XX @@
14
#include "elf.h"
15
#include "../tcg-pool.c.inc"
16
17
-#if defined _CALL_DARWIN || defined __APPLE__
18
-#define TCG_TARGET_CALL_DARWIN
19
+#if !defined _CALL_DARWIN && defined __APPLE__
20
+#define _CALL_DARWIN 1
21
#endif
22
#ifdef _CALL_SYSV
23
# define TCG_TARGET_CALL_ALIGN_ARGS 1
24
@@ -XXX,XX +XXX,XX @@ static const int tcg_target_call_oarg_regs[] = {
25
};
26
27
static const int tcg_target_callee_save_regs[] = {
28
-#ifdef TCG_TARGET_CALL_DARWIN
29
+#ifdef _CALL_DARWIN
30
TCG_REG_R11,
31
#endif
32
TCG_REG_R14,
33
@@ -XXX,XX +XXX,XX @@ static void tcg_out_nop_fill(tcg_insn_unit *p, int count)
34
# define LINK_AREA_SIZE (6 * SZR)
35
# define LR_OFFSET (1 * SZR)
36
# define TCG_TARGET_CALL_STACK_OFFSET (LINK_AREA_SIZE + 8 * SZR)
37
-#elif defined(TCG_TARGET_CALL_DARWIN)
38
+#elif defined(_CALL_DARWIN)
39
# define LINK_AREA_SIZE (6 * SZR)
40
# define LR_OFFSET (2 * SZR)
41
#elif TCG_TARGET_REG_BITS == 64
42
--
43
2.25.1
44
45
diff view generated by jsdifflib
New patch
1
Clang only sets _CALL_ELF for ppc64, and nothing at all to specify
2
the ABI for ppc32. Make a good guess based on other symbols.
1
3
4
Reported-by: Brad Smith <brad@comstyle.com>
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
---
7
tcg/ppc/tcg-target.c.inc | 21 ++++++++++++++++++---
8
1 file changed, 18 insertions(+), 3 deletions(-)
9
10
diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc
11
index XXXXXXX..XXXXXXX 100644
12
--- a/tcg/ppc/tcg-target.c.inc
13
+++ b/tcg/ppc/tcg-target.c.inc
14
@@ -XXX,XX +XXX,XX @@
15
#include "elf.h"
16
#include "../tcg-pool.c.inc"
17
18
-#if !defined _CALL_DARWIN && defined __APPLE__
19
-#define _CALL_DARWIN 1
20
-#endif
21
+/*
22
+ * Standardize on the _CALL_FOO symbols used by GCC:
23
+ * Apple XCode does not define _CALL_DARWIN.
24
+ * Clang defines _CALL_ELF (64-bit) but not _CALL_SYSV (32-bit).
25
+ */
26
+#if !defined(_CALL_SYSV) && \
27
+ !defined(_CALL_DARWIN) && \
28
+ !defined(_CALL_AIX) && \
29
+ !defined(_CALL_ELF)
30
+# if defined(__APPLE__)
31
+# define _CALL_DARWIN
32
+# elif defined(__ELF__) && TCG_TARGET_REG_BITS == 32
33
+# define _CALL_SYSV
34
+# else
35
+# error "Unknown ABI"
36
+# endif
37
+#endif
38
+
39
#ifdef _CALL_SYSV
40
# define TCG_TARGET_CALL_ALIGN_ARGS 1
41
#endif
42
--
43
2.25.1
44
45
diff view generated by jsdifflib
New patch
1
From: "Jose R. Ziviani" <jziviani@suse.de>
1
2
3
Commit 5e8892db93 fixed several function signatures but tcg_out_vec_op
4
for arm is missing. It causes a build error on armv6 and armv7:
5
6
tcg-target.c.inc:2718:42: error: argument 5 of type 'const TCGArg *'
7
{aka 'const unsigned int *'} declared as a pointer [-Werror=array-parameter=]
8
const TCGArg *args, const int *const_args)
9
~~~~~~~~~~~~~~^~~~
10
../tcg/tcg.c:120:41: note: previously declared as an array 'const TCGArg[16]'
11
{aka 'const unsigned int[16]'}
12
const TCGArg args[TCG_MAX_OP_ARGS],
13
~~~~~~~~~~~~~~^~~~
14
15
Signed-off-by: Jose R. Ziviani <jziviani@suse.de>
16
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
17
Message-Id: <20210908185338.7927-1-jziviani@suse.de>
18
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
19
---
20
tcg/arm/tcg-target.c.inc | 3 ++-
21
1 file changed, 2 insertions(+), 1 deletion(-)
22
23
diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
24
index XXXXXXX..XXXXXXX 100644
25
--- a/tcg/arm/tcg-target.c.inc
26
+++ b/tcg/arm/tcg-target.c.inc
27
@@ -XXX,XX +XXX,XX @@ static const ARMInsn vec_cmp0_insn[16] = {
28
29
static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
30
unsigned vecl, unsigned vece,
31
- const TCGArg *args, const int *const_args)
32
+ const TCGArg args[TCG_MAX_OP_ARGS],
33
+ const int const_args[TCG_MAX_OP_ARGS])
34
{
35
TCGType type = vecl + TCG_TYPE_V64;
36
unsigned q = vecl;
37
--
38
2.25.1
39
40
diff view generated by jsdifflib