The following changes since commit ed734377ab3f3f3cc15d7aa301a87ab6370f2eed:

Merge tag 'linux-user-fix-gupnp-pull-request' of https://github.com/hdeller/qemu-hppa into staging (2025-01-24 14:43:07 -0500)

https://github.com/legoater/qemu/ tags/pull-aspeed-20250127

for you to fetch changes up to 8b7ccc6ad10cd4a107b4627e9a5606d757607ff2:

docs/system/arm/aspeed: Remove tacoma-bmc from the documentation (2025-01-27 09:38:15 +0100)

aspeed queue:

* Fixed serial definitions on the command line

* Fixed sdhci write protected pin on AST2600 EVB machine

* Added timer support on AST2700 SoC

* Updated buildroot and SDK images of functional tests

* Removed sd devices creation when -nodefaults is used

* Added software reset mode support on AST2600 SoC

Cédric Le Goater (3):

test/functional: Update the Aspeed aarch64 test

test/functional: Update buildroot images to 2024.11

aspeed: Create sd devices only when defaults are enabled

Jamin Lin (7):

hw/sd/sdhci: Introduce a new Write Protected pin inverted property

hw/arm/aspeed: Invert sdhci write protected pin for AST2600 EVB

hw/timer/aspeed: Refactor Timer Callbacks for SoC-Specific Implementations

hw/timer/aspeed: Add AST2700 Support

aspeed/soc: Support Timer for AST2700

aspeed/wdt: Fix coding style

aspeed/wdt: Support software reset mode for AST2600

Kenneth Jia (1):

hw/arm/aspeed: fix connect_serial_hds_to_uarts

Thomas Huth (1):

docs/system/arm/aspeed: Remove tacoma-bmc from the documentation

From: Kenneth Jia <kenneth_jia@asus.com>

In the loop, we need ignore the index increase when uart == uart_chosen

We should increase the index only after we allocate a serial.

Signed-off-by: Kenneth Jia <kenneth_jia@asus.com>

Fixes: d2b3eaefb4d7 ("aspeed: Refactor UART init for multi-SoC machines")

Reviewed-by: Cédric Le Goater <clg@redhat.com>

Link: https://lore.kernel.org/r/5f9b0c53f1644922ba85522046e92f4c@asus.com

Signed-off-by: Cédric Le Goater <clg@redhat.com>

hw/arm/aspeed.c | 4 ++--

1 file changed, 2 insertions(+), 2 deletions(-)

@@ -XXX,XX +XXX,XX @@ static void connect_serial_hds_to_uarts(AspeedMachineState *bmc)

int uart_chosen = bmc->uart_chosen ? bmc->uart_chosen : amc->uart_default;

aspeed_soc_uart_set_chr(s, uart_chosen, serial_hd(0));

- for (int i = 1, uart = sc->uarts_base; i < sc->uarts_num; i++, uart++) {

+ for (int i = 1, uart = sc->uarts_base; i < sc->uarts_num; uart++) {

if (uart == uart_chosen) {

continue;

}

- aspeed_soc_uart_set_chr(s, uart, serial_hd(i));

+ aspeed_soc_uart_set_chr(s, uart, serial_hd(i++));

}

2.48.1

From: Jamin Lin <jamin_lin@aspeedtech.com>

The register set have a significant change in AST2700. The TMC00-TMC3C

are used for TIMER0 and TMC40-TMC7C are used for TIMER1. In additional,

TMC20-TMC3C and TMC60-TMC7C are reserved registers for TIMER0 and TIMER1,

respectively.

Besides, each TIMER has their own control and interrupt status register.

In other words, users are able to set control and interrupt status for TIMER0

in one register. Both aspeed_timer_read and aspeed_timer_write callback

functions are not compatible AST2700.

Introduce common read and write functions for ASPEED timers.

Modify the aspeed_timer_read and aspeed_timer_write functions to delegate to

SoC-specific callbacks first.

Update the AST2400, AST2500, AST2600 and AST1030 specific read and write

functions to call the common implementations for common register accesses.

This refactoring improves the organization of call delegation and prepares the

codebase for future SoC-specific specializations, such as the AST2700.

Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>

Reviewed-by: Cédric Le Goater <clg@redhat.com>

Link: https://lore.kernel.org/r/20250113064455.1660564-2-jamin_lin@aspeedtech.com

Signed-off-by: Cédric Le Goater <clg@redhat.com>

---

hw/timer/aspeed_timer.c | 55 ++++++++++++++++++++++++++++++-----------

hw/timer/trace-events | 2 +-

2 files changed, 41 insertions(+), 16 deletions(-)

diff --git a/hw/timer/aspeed_timer.c b/hw/timer/aspeed_timer.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/timer/aspeed_timer.c

+++ b/hw/timer/aspeed_timer.c

@@ -XXX,XX +XXX,XX @@ static uint64_t aspeed_timer_get_value(AspeedTimer *t, int reg)

return value;

}

-static uint64_t aspeed_timer_read(void *opaque, hwaddr offset, unsigned size)

+static uint64_t aspeed_timer_read_common(AspeedTimerCtrlState *s, hwaddr offset)

{

- AspeedTimerCtrlState *s = opaque;

const int reg = (offset & 0xf) / 4;

uint64_t value;

@@ -XXX,XX +XXX,XX @@ static uint64_t aspeed_timer_read(void *opaque, hwaddr offset, unsigned size)

value = aspeed_timer_get_value(&s->timers[(offset >> 4) - 1], reg);

break;

default:

- value = ASPEED_TIMER_GET_CLASS(s)->read(s, offset);

+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n",

+ __func__, offset);

+ value = 0;

break;

}

- trace_aspeed_timer_read(offset, size, value);

return value;

}

@@ -XXX,XX +XXX,XX @@ static void aspeed_timer_set_ctrl2(AspeedTimerCtrlState *s, uint32_t value)

trace_aspeed_timer_set_ctrl2(value);

}

-static void aspeed_timer_write(void *opaque, hwaddr offset, uint64_t value,

- unsigned size)

+static void aspeed_timer_write_common(AspeedTimerCtrlState *s, hwaddr offset,

+ uint64_t value)

{

const uint32_t tv = (uint32_t)(value & 0xFFFFFFFF);

const int reg = (offset & 0xf) / 4;

- AspeedTimerCtrlState *s = opaque;

switch (offset) {

/* Control Registers */

@@ -XXX,XX +XXX,XX @@ static void aspeed_timer_write(void *opaque, hwaddr offset, uint64_t value,

aspeed_timer_set_value(s, (offset >> TIMER_NR_REGS) - 1, reg, tv);

break;

default:

- ASPEED_TIMER_GET_CLASS(s)->write(s, offset, value);

+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n",

+ __func__, offset);

break;

}

}

+static uint64_t aspeed_timer_read(void *opaque, hwaddr offset, unsigned size)

+{

+ AspeedTimerCtrlState *s = ASPEED_TIMER(opaque);

+ return ASPEED_TIMER_GET_CLASS(s)->read(s, offset);

+}

+

+static void aspeed_timer_write(void *opaque, hwaddr offset, uint64_t value,

+ unsigned size)

+{

+ AspeedTimerCtrlState *s = ASPEED_TIMER(opaque);

+ ASPEED_TIMER_GET_CLASS(s)->write(s, offset, value);

+}

+

static const MemoryRegionOps aspeed_timer_ops = {

.read = aspeed_timer_read,

.write = aspeed_timer_write,

@@ -XXX,XX +XXX,XX @@ static uint64_t aspeed_2400_timer_read(AspeedTimerCtrlState *s, hwaddr offset)

break;

case 0x38:

case 0x3C:

- default:

qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n",

__func__, offset);

value = 0;

break;

+ default:

+ value = aspeed_timer_read_common(s, offset);

+ break;

}

+ trace_aspeed_timer_read(offset, value);

return value;

}

@@ -XXX,XX +XXX,XX @@ static void aspeed_2400_timer_write(AspeedTimerCtrlState *s, hwaddr offset,

break;

case 0x38:

case 0x3C:

- default:

qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n",

__func__, offset);

break;

+ default:

+ aspeed_timer_write_common(s, offset, value);

+ break;

}

}

@@ -XXX,XX +XXX,XX @@ static uint64_t aspeed_2500_timer_read(AspeedTimerCtrlState *s, hwaddr offset)

value = s->ctrl3 & BIT(0);

break;

case 0x3C:

- default:

qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n",

__func__, offset);

value = 0;

break;

+ default:

+ value = aspeed_timer_read_common(s, offset);

+ break;

}

+ trace_aspeed_timer_read(offset, value);

return value;

}

@@ -XXX,XX +XXX,XX @@ static void aspeed_2500_timer_write(AspeedTimerCtrlState *s, hwaddr offset,

break;

default:

- qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n",

- __func__, offset);

+ aspeed_timer_write_common(s, offset, value);

break;

}

}

@@ -XXX,XX +XXX,XX @@ static uint64_t aspeed_2600_timer_read(AspeedTimerCtrlState *s, hwaddr offset)

break;

case 0x38:

case 0x3C:

- default:

qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n",

__func__, offset);

value = 0;

break;

+ default:

+ value = aspeed_timer_read_common(s, offset);

+ break;

}

+ trace_aspeed_timer_read(offset, value);

return value;

}

@@ -XXX,XX +XXX,XX @@ static void aspeed_2600_timer_write(AspeedTimerCtrlState *s, hwaddr offset,

aspeed_timer_set_ctrl(s, s->ctrl & ~tv);

break;

case 0x38:

- default:

qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n",

__func__, offset);

break;

+ default:

+ aspeed_timer_write_common(s, offset, value);

+ break;

}

}

diff --git a/hw/timer/trace-events b/hw/timer/trace-events

index XXXXXXX..XXXXXXX 100644

--- a/hw/timer/trace-events

+++ b/hw/timer/trace-events

@@ -XXX,XX +XXX,XX @@ aspeed_timer_ctrl_overflow_interrupt(uint8_t i, bool enable) "Timer %" PRIu8 ":

aspeed_timer_ctrl_pulse_enable(uint8_t i, bool enable) "Timer %" PRIu8 ": %d"

aspeed_timer_set_ctrl2(uint32_t value) "Value: 0x%" PRIx32

aspeed_timer_set_value(int timer, int reg, uint32_t value) "Timer %d register %d: 0x%" PRIx32

-aspeed_timer_read(uint64_t offset, unsigned size, uint64_t value) "From 0x%" PRIx64 ": of size %u: 0x%" PRIx64

+aspeed_timer_read(uint64_t offset, uint64_t value) "From 0x%" PRIx64 ": 0x%" PRIx64

# armv7m_systick.c

systick_reload(void) "systick reload"

--

2.48.1

From: Jamin Lin <jamin_lin@aspeedtech.com>

The timer controller include 8 sets of 32-bit decrement counters, based on

either PCLK or 1MHZ clock and the design of timer controller between AST2600

and AST2700 are almost the same.

TIMER0 – TIMER7 has their own individual control and interrupt status register.

In other words, users are able to set timer control in register TMC10 with

different TIMER base address and clear timer control and interrupt status in

register TMC14 with different TIMER base address.

Introduce new "aspeed_2700_timer_read" and "aspeed_2700_timer_write" callback

functions and a new ast2700 class to support AST2700.

The base address of TIMER0 to TIMER7 as following.

Base Address of Timer 0 = 0x12C1_0000

Base Address of Timer 1 = 0x12C1_0040

Base Address of Timer 2 = 0x12C1_0080

Base Address of Timer 3 = 0x12C1_00C0

Base Address of Timer 4 = 0x12C1_0100

Base Address of Timer 5 = 0x12C1_0140

Base Address of Timer 6 = 0x12C1_0180

Base Address of Timer 7 = 0x12C1_01C0

The register address space of each TIMER is "0x40" , and uses the following

formula to get the index and register of each TIMER.

timer_index = offset >> 6;

timer_offset = offset & 0x3f;

The TMC010 is a counter control set and interrupt status register. Write "1" to

TMC10[3:0] will set the specific bits to "1". Introduce a new

"aspeed_2700_timer_set_ctrl" function to handle this register behavior.

The TMC014 is a counter control clear and interrupt status register, to clear

the specific bits to "0", it should write "1" to TMC14[3:0] on the same bit

position. Introduce a new "aspeed_2700_timer_clear_ctrl" function to handle

this register behavior. TMC014 does not support read operation.

Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>

Acked-by: Cédric Le Goater <clg@redhat.com>

Link: https://lore.kernel.org/r/20250113064455.1660564-3-jamin_lin@aspeedtech.com

Signed-off-by: Cédric Le Goater <clg@redhat.com>

---

include/hw/timer/aspeed_timer.h | 1 +

hw/timer/aspeed_timer.c | 208 ++++++++++++++++++++++++++++++++

2 files changed, 209 insertions(+)

diff --git a/include/hw/timer/aspeed_timer.h b/include/hw/timer/aspeed_timer.h

index XXXXXXX..XXXXXXX 100644

--- a/include/hw/timer/aspeed_timer.h

+++ b/include/hw/timer/aspeed_timer.h

@@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_TYPE(AspeedTimerCtrlState, AspeedTimerClass, ASPEED_TIMER)

#define TYPE_ASPEED_2500_TIMER TYPE_ASPEED_TIMER "-ast2500"

#define TYPE_ASPEED_2600_TIMER TYPE_ASPEED_TIMER "-ast2600"

#define TYPE_ASPEED_1030_TIMER TYPE_ASPEED_TIMER "-ast1030"

+#define TYPE_ASPEED_2700_TIMER TYPE_ASPEED_TIMER "-ast2700"

#define ASPEED_TIMER_NR_TIMERS 8

diff --git a/hw/timer/aspeed_timer.c b/hw/timer/aspeed_timer.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/timer/aspeed_timer.c

+++ b/hw/timer/aspeed_timer.c

@@ -XXX,XX +XXX,XX @@ static void aspeed_2600_timer_write(AspeedTimerCtrlState *s, hwaddr offset,

}

}

+static void aspeed_2700_timer_set_ctrl(AspeedTimerCtrlState *s, int index,

+ uint32_t reg)

+{

+ const uint8_t overflow_interrupt_mask = BIT(op_overflow_interrupt);

+ const uint8_t external_clock_mask = BIT(op_external_clock);

+ const uint8_t pulse_enable_mask = BIT(op_pulse_enable);

+ const uint8_t enable_mask = BIT(op_enable);

+ AspeedTimer *t;

+ uint8_t t_old;

+ uint8_t t_new;

+ int shift;

+

+ /*

+ * Only 1 will set the specific bits to 1

+ * Handle a dependency between the 'enable' and remaining three

+ * configuration bits - i.e. if more than one bit in the control set has

+ * set, including the 'enable' bit, perform configuration and then

+ * enable the timer.

+ * Interrupt Status bit should not be set.

+ */

+

+ t = &s->timers[index];

+ shift = index * TIMER_CTRL_BITS;

+

+ t_old = (s->ctrl >> shift) & TIMER_CTRL_MASK;

+ t_new = reg & TIMER_CTRL_MASK;

+

+ if (!(t_old & external_clock_mask) &&

+ (t_new & external_clock_mask)) {

+ aspeed_timer_ctrl_external_clock(t, true);

+ s->ctrl = deposit32(s->ctrl, shift + op_external_clock, 1, 1);

+ }

+

+ if (!(t_old & overflow_interrupt_mask) &&

+ (t_new & overflow_interrupt_mask)) {

+ aspeed_timer_ctrl_overflow_interrupt(t, true);

+ s->ctrl = deposit32(s->ctrl, shift + op_overflow_interrupt, 1, 1);

+ }

+

+

+ if (!(t_old & pulse_enable_mask) &&

+ (t_new & pulse_enable_mask)) {

+ aspeed_timer_ctrl_pulse_enable(t, true);

+ s->ctrl = deposit32(s->ctrl, shift + op_pulse_enable, 1, 1);

+ }

+

+ /* If we are enabling, do so last */

+ if (!(t_old & enable_mask) &&

+ (t_new & enable_mask)) {

+ aspeed_timer_ctrl_enable(t, true);

+ s->ctrl = deposit32(s->ctrl, shift + op_enable, 1, 1);

+ }

+}

+

+static void aspeed_2700_timer_clear_ctrl(AspeedTimerCtrlState *s, int index,

+ uint32_t reg)

+{

+ const uint8_t overflow_interrupt_mask = BIT(op_overflow_interrupt);

+ const uint8_t external_clock_mask = BIT(op_external_clock);

+ const uint8_t pulse_enable_mask = BIT(op_pulse_enable);

+ const uint8_t enable_mask = BIT(op_enable);

+ AspeedTimer *t;

+ uint8_t t_old;

+ uint8_t t_new;

+ int shift;

+

+ /*

+ * Only 1 will clear the specific bits to 0

+ * Handle a dependency between the 'enable' and remaining three

+ * configuration bits - i.e. if more than one bit in the control set has

+ * clear, including the 'enable' bit, then disable the timer and perform

+ * configuration

+ */

+

+ t = &s->timers[index];

+ shift = index * TIMER_CTRL_BITS;

+

+ t_old = (s->ctrl >> shift) & TIMER_CTRL_MASK;

+ t_new = reg & TIMER_CTRL_MASK;

+

+ /* If we are disabling, do so first */

+ if ((t_old & enable_mask) &&

+ (t_new & enable_mask)) {

+ aspeed_timer_ctrl_enable(t, false);

+ s->ctrl = deposit32(s->ctrl, shift + op_enable, 1, 0);

+ }

+

+ if ((t_old & external_clock_mask) &&

+ (t_new & external_clock_mask)) {

+ aspeed_timer_ctrl_external_clock(t, false);

+ s->ctrl = deposit32(s->ctrl, shift + op_external_clock, 1, 0);

+ }

+

+ if ((t_old & overflow_interrupt_mask) &&

+ (t_new & overflow_interrupt_mask)) {

+ aspeed_timer_ctrl_overflow_interrupt(t, false);

+ s->ctrl = deposit32(s->ctrl, shift + op_overflow_interrupt, 1, 0);

+ }

+

+ if ((t_old & pulse_enable_mask) &&

+ (t_new & pulse_enable_mask)) {

+ aspeed_timer_ctrl_pulse_enable(t, false);

+ s->ctrl = deposit32(s->ctrl, shift + op_pulse_enable, 1, 0);

+ }

+

+ /* Clear interrupt status */

+ if (reg & 0x10000) {

+ s->irq_sts = deposit32(s->irq_sts, index, 1, 0);

+ }

+}

+

+static uint64_t aspeed_2700_timer_read(AspeedTimerCtrlState *s, hwaddr offset)

+{

+ uint32_t timer_offset = offset & 0x3f;

+ int timer_index = offset >> 6;

+ uint64_t value = 0;

+

+ if (timer_index >= ASPEED_TIMER_NR_TIMERS) {

+ qemu_log_mask(LOG_GUEST_ERROR,

+ "%s: offset 0x%" PRIx64 " out of bounds\n",

+ __func__, offset);

+ return 0;

+ }

+

+ switch (timer_offset) {

+ /*

+ * Counter Status

+ * Counter Reload

+ * Counter First Matching

+ * Counter Second Matching

+ */

+ case 0x00 ... 0x0C:

+ value = aspeed_timer_get_value(&s->timers[timer_index],

+ timer_offset >> 2);

+ break;

+ /* Counter Control and Interrupt Status */

+ case 0x10:

+ value = deposit64(value, 0, 4,

+ extract32(s->ctrl, timer_index * 4, 4));

+ value = deposit64(value, 16, 1,

+ extract32(s->irq_sts, timer_index, 1));

+ break;

+ default:

+ qemu_log_mask(LOG_GUEST_ERROR, "%s: no getter for offset 0x%"

+ PRIx64"\n", __func__, offset);

+ value = 0;

+ break;

+ }

+ trace_aspeed_timer_read(offset, value);

+ return value;

+}

+

+static void aspeed_2700_timer_write(AspeedTimerCtrlState *s, hwaddr offset,

+ uint64_t value)

+{

+ const uint32_t timer_value = (uint32_t)(value & 0xFFFFFFFF);

+ uint32_t timer_offset = offset & 0x3f;

+ int timer_index = offset >> 6;

+

+ if (timer_index >= ASPEED_TIMER_NR_TIMERS) {

+ qemu_log_mask(LOG_GUEST_ERROR,

+ "%s: offset 0x%" PRIx64 " out of bounds\n",

+ __func__, offset);

+ }

+

+ switch (timer_offset) {

+ /*

+ * Counter Status

+ * Counter Reload

+ * Counter First Matching

+ * Counter Second Matching

+ */

+ case 0x00 ... 0x0C:

+ aspeed_timer_set_value(s, timer_index, timer_offset >> 2,

+ timer_value);

+ break;

+ /* Counter Control Set and Interrupt Status */

+ case 0x10:

+ aspeed_2700_timer_set_ctrl(s, timer_index, timer_value);

+ break;

+ /* Counter Control Clear and Interrupr Status */

+ case 0x14:

+ aspeed_2700_timer_clear_ctrl(s, timer_index, timer_value);

+ break;

+ default:

+ qemu_log_mask(LOG_GUEST_ERROR, "%s: no setter for offset 0x%"

+ PRIx64"\n", __func__, offset);

+ break;

+ }

+}

+

static void aspeed_init_one_timer(AspeedTimerCtrlState *s, uint8_t id)

{

AspeedTimer *t = &s->timers[id];

@@ -XXX,XX +XXX,XX @@ static const TypeInfo aspeed_1030_timer_info = {

.class_init = aspeed_1030_timer_class_init,

};

+static void aspeed_2700_timer_class_init(ObjectClass *klass, void *data)

+{

+ DeviceClass *dc = DEVICE_CLASS(klass);

+ AspeedTimerClass *awc = ASPEED_TIMER_CLASS(klass);

+

+ dc->desc = "ASPEED 2700 Timer";

+ awc->read = aspeed_2700_timer_read;

+ awc->write = aspeed_2700_timer_write;

+}

+

+static const TypeInfo aspeed_2700_timer_info = {

+ .name = TYPE_ASPEED_2700_TIMER,

+ .parent = TYPE_ASPEED_TIMER,

+ .class_init = aspeed_2700_timer_class_init,

+};

+

static void aspeed_timer_register_types(void)

{

type_register_static(&aspeed_timer_info);

@@ -XXX,XX +XXX,XX @@ static void aspeed_timer_register_types(void)

type_register_static(&aspeed_2500_timer_info);

type_register_static(&aspeed_2600_timer_info);

type_register_static(&aspeed_1030_timer_info);

+ type_register_static(&aspeed_2700_timer_info);

}

type_init(aspeed_timer_register_types)

--

2.48.1

From: Jamin Lin <jamin_lin@aspeedtech.com>

Add Timer model for AST2700 Timer support. The Timer controller include 8 sets

of 32-bit decrement counters.

The base address of TIMER0 to TIMER7 as following.

Base Address of Timer 0 = 0x12C1_0000

Base Address of Timer 1 = 0x12C1_0040

Base Address of Timer 2 = 0x12C1_0080

Base Address of Timer 3 = 0x12C1_00C0

Base Address of Timer 4 = 0x12C1_0100

Base Address of Timer 5 = 0x12C1_0140

Base Address of Timer 6 = 0x12C1_0180

Base Address of Timer 7 = 0x12C1_01C0

The interrupt of TIMER0 to TIMER7 as following.

GICINT16 = TIMER 0 interrupt

GICINT17 = TIMER 1 interrupt

GICINT18 = TIMER 2 interrupt

GICINT19 = TIMER 3 interrupt

GICINT20 = TIMER 4 interrupt

GICINT21 = TIMER 5 interrupt

GICINT22 = TIMER 6 interrupt

GICINT23 = TIMER 7 interrupt

Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>

Reviewed-by: Cédric Le Goater <clg@redhat.com>

Link: https://lore.kernel.org/r/20250113064455.1660564-4-jamin_lin@aspeedtech.com

Signed-off-by: Cédric Le Goater <clg@redhat.com>

hw/arm/aspeed_ast27x0.c | 17 +++++++++++++++++

1 file changed, 17 insertions(+)

diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/arm/aspeed_ast27x0.c

+++ b/hw/arm/aspeed_ast27x0.c

@@ -XXX,XX +XXX,XX @@ static const hwaddr aspeed_soc_ast2700_memmap[] = {

[ASPEED_DEV_GPIO] = 0x14C0B000,

[ASPEED_DEV_RTC] = 0x12C0F000,

[ASPEED_DEV_SDHCI] = 0x14080000,

+ [ASPEED_DEV_TIMER1] = 0x12C10000,

};

#define AST2700_MAX_IRQ 256

@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2700_init(Object *obj)

object_initialize_child(obj, "emmc-controller.sdhci", &s->emmc.slots[0],

TYPE_SYSBUS_SDHCI);

+ snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname);

+ object_initialize_child(obj, "timerctrl", &s->timerctrl, typename);

}

/*

@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)

sysbus_connect_irq(SYS_BUS_DEVICE(&s->emmc), 0,

aspeed_soc_get_irq(s, ASPEED_DEV_EMMC));

+ /* Timer */

+ object_property_set_link(OBJECT(&s->timerctrl), "scu", OBJECT(&s->scu),

+ &error_abort);

+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->timerctrl), errp)) {

+ aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->timerctrl), 0,

+ sc->memmap[ASPEED_DEV_TIMER1]);

+ for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) {

+ irq = aspeed_soc_get_irq(s, ASPEED_DEV_TIMER1 + i);

+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq);

create_unimplemented_device("ast2700.dpmcu", 0x11000000, 0x40000);

create_unimplemented_device("ast2700.iomem0", 0x12000000, 0x01000000);

create_unimplemented_device("ast2700.iomem1", 0x14000000, 0x01000000);