1 | The following changes since commit 5e7b204dbfae9a562fc73684986f936b97f63877: | 1 | The following changes since commit a95260486aa7e78d7c7194eba65cf03311ad94ad: |
---|---|---|---|
2 | 2 | ||
3 | Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging (2020-12-09 20:08:54 +0000) | 3 | Merge tag 'pull-tcg-20231023' of https://gitlab.com/rth7680/qemu into staging (2023-10-23 14:45:46 -0700) |
4 | 4 | ||
5 | are available in the Git repository at: | 5 | are available in the Git repository at: |
6 | 6 | ||
7 | https://github.com/legoater/qemu/ tags/pull-aspeed-20201210 | 7 | https://github.com/legoater/qemu/ tags/pull-aspeed-20231025 |
8 | 8 | ||
9 | for you to fetch changes up to 6f5f6507e49df4820207a94f3aeaaeab08092d32: | 9 | for you to fetch changes up to dd41ce7a6f13ad4f45ebaf52b9fa91fe5fc961df: |
10 | 10 | ||
11 | aspeed: g220a-bmc: Add an FRU (2020-12-10 12:11:03 +0100) | 11 | hw/arm/aspeed: Move AspeedSoCState::cpu/vic to Aspeed2400SoCState (2023-10-25 09:52:44 +0200) |
12 | 12 | ||
13 | ---------------------------------------------------------------- | 13 | ---------------------------------------------------------------- |
14 | Aspeed patches : | 14 | aspeed queue: |
15 | 15 | ||
16 | * New device model for EMC1413/EMC1414 temperature sensors (I2C) | 16 | * Update of Andrew's email |
17 | * New g220a-bmc Aspeed machine | 17 | * Split of AspeedSoCState per 2400/2600/10x0 |
18 | * couple of Aspeed cleanups | ||
19 | 18 | ||
20 | ---------------------------------------------------------------- | 19 | ---------------------------------------------------------------- |
21 | Cédric Le Goater (1): | 20 | Andrew Jeffery (1): |
22 | aspeed/smc: Add support for address lane disablement | 21 | MAINTAINERS: aspeed: Update Andrew's email address |
23 | 22 | ||
24 | Joel Stanley (1): | 23 | Philippe Mathieu-Daudé (11): |
25 | ast2600: SRAM is 89KB | 24 | hw/arm/aspeed: Extract code common to all boards to a common file |
25 | hw/arm/aspeed: Rename aspeed_soc_init() as AST2400/2500 specific | ||
26 | hw/arm/aspeed: Rename aspeed_soc_realize() as AST2400/2500 specific | ||
27 | hw/arm/aspeed: Dynamically allocate AspeedMachineState::soc field | ||
28 | hw/arm/aspeed: Introduce TYPE_ASPEED10X0_SOC | ||
29 | hw/arm/aspeed: Introduce TYPE_ASPEED2600_SOC | ||
30 | hw/arm/aspeed: Introduce TYPE_ASPEED2400_SOC | ||
31 | hw/arm/aspeed: Check 'memory' link is set in common aspeed_soc_realize | ||
32 | hw/arm/aspeed: Move AspeedSoCState::armv7m to Aspeed10x0SoCState | ||
33 | hw/arm/aspeed: Move AspeedSoCState::a7mpcore to Aspeed2600SoCState | ||
34 | hw/arm/aspeed: Move AspeedSoCState::cpu/vic to Aspeed2400SoCState | ||
26 | 35 | ||
27 | John Wang (3): | 36 | MAINTAINERS | 2 +- |
28 | hw/misc: add an EMC141{3,4} device model | 37 | include/hw/arm/aspeed_soc.h | 35 +++++- |
29 | aspeed: Add support for the g220a-bmc board | 38 | hw/arm/aspeed.c | 101 +++++++-------- |
30 | aspeed: g220a-bmc: Add an FRU | 39 | hw/arm/aspeed_ast10x0.c | 53 ++++---- |
40 | hw/arm/{aspeed_soc.c => aspeed_ast2400.c} | 197 +++++++----------------------- | ||
41 | hw/arm/aspeed_ast2600.c | 75 ++++++------ | ||
42 | hw/arm/aspeed_soc_common.c | 154 +++++++++++++++++++++++ | ||
43 | hw/arm/fby35.c | 27 ++-- | ||
44 | hw/arm/meson.build | 3 +- | ||
45 | 9 files changed, 363 insertions(+), 284 deletions(-) | ||
46 | rename hw/arm/{aspeed_soc.c => aspeed_ast2400.c} (76%) | ||
47 | create mode 100644 hw/arm/aspeed_soc_common.c | ||
31 | 48 | ||
32 | include/hw/misc/emc141x_regs.h | 37 +++++ | ||
33 | hw/arm/aspeed.c | 72 +++++++++ | ||
34 | hw/arm/aspeed_ast2600.c | 2 +- | ||
35 | hw/misc/emc141x.c | 326 +++++++++++++++++++++++++++++++++++++++++ | ||
36 | hw/ssi/aspeed_smc.c | 25 +++- | ||
37 | tests/qtest/emc141x-test.c | 81 ++++++++++ | ||
38 | hw/arm/Kconfig | 1 + | ||
39 | hw/misc/Kconfig | 4 + | ||
40 | hw/misc/meson.build | 1 + | ||
41 | tests/qtest/meson.build | 1 + | ||
42 | 10 files changed, 542 insertions(+), 8 deletions(-) | ||
43 | create mode 100644 include/hw/misc/emc141x_regs.h | ||
44 | create mode 100644 hw/misc/emc141x.c | ||
45 | create mode 100644 tests/qtest/emc141x-test.c | ||
46 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Andrew Jeffery <andrew@codeconstruct.com.au> | ||
1 | 2 | ||
3 | I've changed employers, have company email that deals with patch-based | ||
4 | workflows without too much of a headache, and am trying to steer some | ||
5 | content out of my personal mail. | ||
6 | |||
7 | Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au> | ||
8 | Signed-off-by: Cédric Le Goater <clg@kaod.org> | ||
9 | --- | ||
10 | MAINTAINERS | 2 +- | ||
11 | 1 file changed, 1 insertion(+), 1 deletion(-) | ||
12 | |||
13 | diff --git a/MAINTAINERS b/MAINTAINERS | ||
14 | index XXXXXXX..XXXXXXX 100644 | ||
15 | --- a/MAINTAINERS | ||
16 | +++ b/MAINTAINERS | ||
17 | @@ -XXX,XX +XXX,XX @@ F: docs/system/arm/emcraft-sf2.rst | ||
18 | ASPEED BMCs | ||
19 | M: Cédric Le Goater <clg@kaod.org> | ||
20 | M: Peter Maydell <peter.maydell@linaro.org> | ||
21 | -R: Andrew Jeffery <andrew@aj.id.au> | ||
22 | +R: Andrew Jeffery <andrew@codeconstruct.com.au> | ||
23 | R: Joel Stanley <joel@jms.id.au> | ||
24 | L: qemu-arm@nongnu.org | ||
25 | S: Maintained | ||
26 | -- | ||
27 | 2.41.0 | ||
28 | |||
29 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | 1 | From: Philippe Mathieu-Daudé <philmd@linaro.org> | |
2 | |||
3 | aspeed_soc.c contains definitions specific to the AST2400 | ||
4 | and AST2500 SoCs, but also some definitions for other AST | ||
5 | SoCs: move them to a common file. | ||
6 | |||
7 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
8 | Reviewed-by: Cédric Le Goater <clg@kaod.org> | ||
9 | Signed-off-by: Cédric Le Goater <clg@kaod.org> | ||
10 | --- | ||
11 | hw/arm/aspeed_soc.c | 96 ------------------------------- | ||
12 | hw/arm/aspeed_soc_common.c | 114 +++++++++++++++++++++++++++++++++++++ | ||
13 | hw/arm/meson.build | 1 + | ||
14 | 3 files changed, 115 insertions(+), 96 deletions(-) | ||
15 | create mode 100644 hw/arm/aspeed_soc_common.c | ||
16 | |||
17 | diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c | ||
18 | index XXXXXXX..XXXXXXX 100644 | ||
19 | --- a/hw/arm/aspeed_soc.c | ||
20 | +++ b/hw/arm/aspeed_soc.c | ||
21 | @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_register_types(void) | ||
22 | }; | ||
23 | |||
24 | type_init(aspeed_soc_register_types); | ||
25 | - | ||
26 | -qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev) | ||
27 | -{ | ||
28 | - return ASPEED_SOC_GET_CLASS(s)->get_irq(s, dev); | ||
29 | -} | ||
30 | - | ||
31 | -bool aspeed_soc_uart_realize(AspeedSoCState *s, Error **errp) | ||
32 | -{ | ||
33 | - AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); | ||
34 | - SerialMM *smm; | ||
35 | - | ||
36 | - for (int i = 0, uart = ASPEED_DEV_UART1; i < sc->uarts_num; i++, uart++) { | ||
37 | - smm = &s->uart[i]; | ||
38 | - | ||
39 | - /* Chardev property is set by the machine. */ | ||
40 | - qdev_prop_set_uint8(DEVICE(smm), "regshift", 2); | ||
41 | - qdev_prop_set_uint32(DEVICE(smm), "baudbase", 38400); | ||
42 | - qdev_set_legacy_instance_id(DEVICE(smm), sc->memmap[uart], 2); | ||
43 | - qdev_prop_set_uint8(DEVICE(smm), "endianness", DEVICE_LITTLE_ENDIAN); | ||
44 | - if (!sysbus_realize(SYS_BUS_DEVICE(smm), errp)) { | ||
45 | - return false; | ||
46 | - } | ||
47 | - | ||
48 | - sysbus_connect_irq(SYS_BUS_DEVICE(smm), 0, aspeed_soc_get_irq(s, uart)); | ||
49 | - aspeed_mmio_map(s, SYS_BUS_DEVICE(smm), 0, sc->memmap[uart]); | ||
50 | - } | ||
51 | - | ||
52 | - return true; | ||
53 | -} | ||
54 | - | ||
55 | -void aspeed_soc_uart_set_chr(AspeedSoCState *s, int dev, Chardev *chr) | ||
56 | -{ | ||
57 | - AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); | ||
58 | - int i = dev - ASPEED_DEV_UART1; | ||
59 | - | ||
60 | - g_assert(0 <= i && i < ARRAY_SIZE(s->uart) && i < sc->uarts_num); | ||
61 | - qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", chr); | ||
62 | -} | ||
63 | - | ||
64 | -/* | ||
65 | - * SDMC should be realized first to get correct RAM size and max size | ||
66 | - * values | ||
67 | - */ | ||
68 | -bool aspeed_soc_dram_init(AspeedSoCState *s, Error **errp) | ||
69 | -{ | ||
70 | - AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); | ||
71 | - ram_addr_t ram_size, max_ram_size; | ||
72 | - | ||
73 | - ram_size = object_property_get_uint(OBJECT(&s->sdmc), "ram-size", | ||
74 | - &error_abort); | ||
75 | - max_ram_size = object_property_get_uint(OBJECT(&s->sdmc), "max-ram-size", | ||
76 | - &error_abort); | ||
77 | - | ||
78 | - memory_region_init(&s->dram_container, OBJECT(s), "ram-container", | ||
79 | - max_ram_size); | ||
80 | - memory_region_add_subregion(&s->dram_container, 0, s->dram_mr); | ||
81 | - | ||
82 | - /* | ||
83 | - * Add a memory region beyond the RAM region to let firmwares scan | ||
84 | - * the address space with load/store and guess how much RAM the | ||
85 | - * SoC has. | ||
86 | - */ | ||
87 | - if (ram_size < max_ram_size) { | ||
88 | - DeviceState *dev = qdev_new(TYPE_UNIMPLEMENTED_DEVICE); | ||
89 | - | ||
90 | - qdev_prop_set_string(dev, "name", "ram-empty"); | ||
91 | - qdev_prop_set_uint64(dev, "size", max_ram_size - ram_size); | ||
92 | - if (!sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), errp)) { | ||
93 | - return false; | ||
94 | - } | ||
95 | - | ||
96 | - memory_region_add_subregion_overlap(&s->dram_container, ram_size, | ||
97 | - sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0), -1000); | ||
98 | - } | ||
99 | - | ||
100 | - memory_region_add_subregion(s->memory, | ||
101 | - sc->memmap[ASPEED_DEV_SDRAM], &s->dram_container); | ||
102 | - return true; | ||
103 | -} | ||
104 | - | ||
105 | -void aspeed_mmio_map(AspeedSoCState *s, SysBusDevice *dev, int n, hwaddr addr) | ||
106 | -{ | ||
107 | - memory_region_add_subregion(s->memory, addr, | ||
108 | - sysbus_mmio_get_region(dev, n)); | ||
109 | -} | ||
110 | - | ||
111 | -void aspeed_mmio_map_unimplemented(AspeedSoCState *s, SysBusDevice *dev, | ||
112 | - const char *name, hwaddr addr, uint64_t size) | ||
113 | -{ | ||
114 | - qdev_prop_set_string(DEVICE(dev), "name", name); | ||
115 | - qdev_prop_set_uint64(DEVICE(dev), "size", size); | ||
116 | - sysbus_realize(dev, &error_abort); | ||
117 | - | ||
118 | - memory_region_add_subregion_overlap(s->memory, addr, | ||
119 | - sysbus_mmio_get_region(dev, 0), -1000); | ||
120 | -} | ||
121 | diff --git a/hw/arm/aspeed_soc_common.c b/hw/arm/aspeed_soc_common.c | ||
122 | new file mode 100644 | ||
123 | index XXXXXXX..XXXXXXX | ||
124 | --- /dev/null | ||
125 | +++ b/hw/arm/aspeed_soc_common.c | ||
126 | @@ -XXX,XX +XXX,XX @@ | ||
127 | +/* | ||
128 | + * ASPEED SoC family | ||
129 | + * | ||
130 | + * Andrew Jeffery <andrew@aj.id.au> | ||
131 | + * Jeremy Kerr <jk@ozlabs.org> | ||
132 | + * | ||
133 | + * Copyright 2016 IBM Corp. | ||
134 | + * | ||
135 | + * This code is licensed under the GPL version 2 or later. See | ||
136 | + * the COPYING file in the top-level directory. | ||
137 | + */ | ||
138 | + | ||
139 | +#include "qemu/osdep.h" | ||
140 | +#include "qapi/error.h" | ||
141 | +#include "hw/misc/unimp.h" | ||
142 | +#include "hw/arm/aspeed_soc.h" | ||
143 | +#include "hw/char/serial.h" | ||
144 | + | ||
145 | + | ||
146 | +qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev) | ||
147 | +{ | ||
148 | + return ASPEED_SOC_GET_CLASS(s)->get_irq(s, dev); | ||
149 | +} | ||
150 | + | ||
151 | +bool aspeed_soc_uart_realize(AspeedSoCState *s, Error **errp) | ||
152 | +{ | ||
153 | + AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); | ||
154 | + SerialMM *smm; | ||
155 | + | ||
156 | + for (int i = 0, uart = ASPEED_DEV_UART1; i < sc->uarts_num; i++, uart++) { | ||
157 | + smm = &s->uart[i]; | ||
158 | + | ||
159 | + /* Chardev property is set by the machine. */ | ||
160 | + qdev_prop_set_uint8(DEVICE(smm), "regshift", 2); | ||
161 | + qdev_prop_set_uint32(DEVICE(smm), "baudbase", 38400); | ||
162 | + qdev_set_legacy_instance_id(DEVICE(smm), sc->memmap[uart], 2); | ||
163 | + qdev_prop_set_uint8(DEVICE(smm), "endianness", DEVICE_LITTLE_ENDIAN); | ||
164 | + if (!sysbus_realize(SYS_BUS_DEVICE(smm), errp)) { | ||
165 | + return false; | ||
166 | + } | ||
167 | + | ||
168 | + sysbus_connect_irq(SYS_BUS_DEVICE(smm), 0, aspeed_soc_get_irq(s, uart)); | ||
169 | + aspeed_mmio_map(s, SYS_BUS_DEVICE(smm), 0, sc->memmap[uart]); | ||
170 | + } | ||
171 | + | ||
172 | + return true; | ||
173 | +} | ||
174 | + | ||
175 | +void aspeed_soc_uart_set_chr(AspeedSoCState *s, int dev, Chardev *chr) | ||
176 | +{ | ||
177 | + AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); | ||
178 | + int i = dev - ASPEED_DEV_UART1; | ||
179 | + | ||
180 | + g_assert(0 <= i && i < ARRAY_SIZE(s->uart) && i < sc->uarts_num); | ||
181 | + qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", chr); | ||
182 | +} | ||
183 | + | ||
184 | +/* | ||
185 | + * SDMC should be realized first to get correct RAM size and max size | ||
186 | + * values | ||
187 | + */ | ||
188 | +bool aspeed_soc_dram_init(AspeedSoCState *s, Error **errp) | ||
189 | +{ | ||
190 | + AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); | ||
191 | + ram_addr_t ram_size, max_ram_size; | ||
192 | + | ||
193 | + ram_size = object_property_get_uint(OBJECT(&s->sdmc), "ram-size", | ||
194 | + &error_abort); | ||
195 | + max_ram_size = object_property_get_uint(OBJECT(&s->sdmc), "max-ram-size", | ||
196 | + &error_abort); | ||
197 | + | ||
198 | + memory_region_init(&s->dram_container, OBJECT(s), "ram-container", | ||
199 | + max_ram_size); | ||
200 | + memory_region_add_subregion(&s->dram_container, 0, s->dram_mr); | ||
201 | + | ||
202 | + /* | ||
203 | + * Add a memory region beyond the RAM region to let firmwares scan | ||
204 | + * the address space with load/store and guess how much RAM the | ||
205 | + * SoC has. | ||
206 | + */ | ||
207 | + if (ram_size < max_ram_size) { | ||
208 | + DeviceState *dev = qdev_new(TYPE_UNIMPLEMENTED_DEVICE); | ||
209 | + | ||
210 | + qdev_prop_set_string(dev, "name", "ram-empty"); | ||
211 | + qdev_prop_set_uint64(dev, "size", max_ram_size - ram_size); | ||
212 | + if (!sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), errp)) { | ||
213 | + return false; | ||
214 | + } | ||
215 | + | ||
216 | + memory_region_add_subregion_overlap(&s->dram_container, ram_size, | ||
217 | + sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0), -1000); | ||
218 | + } | ||
219 | + | ||
220 | + memory_region_add_subregion(s->memory, | ||
221 | + sc->memmap[ASPEED_DEV_SDRAM], &s->dram_container); | ||
222 | + return true; | ||
223 | +} | ||
224 | + | ||
225 | +void aspeed_mmio_map(AspeedSoCState *s, SysBusDevice *dev, int n, hwaddr addr) | ||
226 | +{ | ||
227 | + memory_region_add_subregion(s->memory, addr, | ||
228 | + sysbus_mmio_get_region(dev, n)); | ||
229 | +} | ||
230 | + | ||
231 | +void aspeed_mmio_map_unimplemented(AspeedSoCState *s, SysBusDevice *dev, | ||
232 | + const char *name, hwaddr addr, uint64_t size) | ||
233 | +{ | ||
234 | + qdev_prop_set_string(DEVICE(dev), "name", name); | ||
235 | + qdev_prop_set_uint64(DEVICE(dev), "size", size); | ||
236 | + sysbus_realize(dev, &error_abort); | ||
237 | + | ||
238 | + memory_region_add_subregion_overlap(s->memory, addr, | ||
239 | + sysbus_mmio_get_region(dev, 0), -1000); | ||
240 | +} | ||
241 | diff --git a/hw/arm/meson.build b/hw/arm/meson.build | ||
242 | index XXXXXXX..XXXXXXX 100644 | ||
243 | --- a/hw/arm/meson.build | ||
244 | +++ b/hw/arm/meson.build | ||
245 | @@ -XXX,XX +XXX,XX @@ arm_ss.add(when: 'CONFIG_FSL_IMX6', if_true: files('fsl-imx6.c')) | ||
246 | arm_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files( | ||
247 | 'aspeed_soc.c', | ||
248 | 'aspeed.c', | ||
249 | + 'aspeed_soc_common.c', | ||
250 | 'aspeed_ast2600.c', | ||
251 | 'aspeed_ast10x0.c', | ||
252 | 'aspeed_eeprom.c', | ||
253 | -- | ||
254 | 2.41.0 | ||
255 | |||
256 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
1 | 2 | ||
3 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
4 | Reviewed-by: Cédric Le Goater <clg@kaod.org> | ||
5 | Signed-off-by: Cédric Le Goater <clg@kaod.org> | ||
6 | --- | ||
7 | hw/arm/aspeed_soc.c | 6 +++--- | ||
8 | 1 file changed, 3 insertions(+), 3 deletions(-) | ||
9 | |||
10 | diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c | ||
11 | index XXXXXXX..XXXXXXX 100644 | ||
12 | --- a/hw/arm/aspeed_soc.c | ||
13 | +++ b/hw/arm/aspeed_soc.c | ||
14 | @@ -XXX,XX +XXX,XX @@ static qemu_irq aspeed_soc_ast2400_get_irq(AspeedSoCState *s, int dev) | ||
15 | return qdev_get_gpio_in(DEVICE(&s->vic), sc->irqmap[dev]); | ||
16 | } | ||
17 | |||
18 | -static void aspeed_soc_init(Object *obj) | ||
19 | +static void aspeed_ast2400_soc_init(Object *obj) | ||
20 | { | ||
21 | AspeedSoCState *s = ASPEED_SOC(obj); | ||
22 | AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); | ||
23 | @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2400_class_init(ObjectClass *oc, void *data) | ||
24 | static const TypeInfo aspeed_soc_ast2400_type_info = { | ||
25 | .name = "ast2400-a1", | ||
26 | .parent = TYPE_ASPEED_SOC, | ||
27 | - .instance_init = aspeed_soc_init, | ||
28 | + .instance_init = aspeed_ast2400_soc_init, | ||
29 | .instance_size = sizeof(AspeedSoCState), | ||
30 | .class_init = aspeed_soc_ast2400_class_init, | ||
31 | }; | ||
32 | @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2500_class_init(ObjectClass *oc, void *data) | ||
33 | static const TypeInfo aspeed_soc_ast2500_type_info = { | ||
34 | .name = "ast2500-a1", | ||
35 | .parent = TYPE_ASPEED_SOC, | ||
36 | - .instance_init = aspeed_soc_init, | ||
37 | + .instance_init = aspeed_ast2400_soc_init, | ||
38 | .instance_size = sizeof(AspeedSoCState), | ||
39 | .class_init = aspeed_soc_ast2500_class_init, | ||
40 | }; | ||
41 | -- | ||
42 | 2.41.0 | ||
43 | |||
44 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
1 | 2 | ||
3 | Keep aspeed_soc_class_init() generic, set the realize handler | ||
4 | to aspeed_ast2400_soc_realize() in each 2400/2500 class_init. | ||
5 | |||
6 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
7 | Reviewed-by: Cédric Le Goater <clg@kaod.org> | ||
8 | Signed-off-by: Cédric Le Goater <clg@kaod.org> | ||
9 | --- | ||
10 | hw/arm/aspeed_soc.c | 15 +++++++++++---- | ||
11 | 1 file changed, 11 insertions(+), 4 deletions(-) | ||
12 | |||
13 | diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c | ||
14 | index XXXXXXX..XXXXXXX 100644 | ||
15 | --- a/hw/arm/aspeed_soc.c | ||
16 | +++ b/hw/arm/aspeed_soc.c | ||
17 | @@ -XXX,XX +XXX,XX @@ static void aspeed_ast2400_soc_init(Object *obj) | ||
18 | object_initialize_child(obj, "video", &s->video, TYPE_UNIMPLEMENTED_DEVICE); | ||
19 | } | ||
20 | |||
21 | -static void aspeed_soc_realize(DeviceState *dev, Error **errp) | ||
22 | +static void aspeed_ast2400_soc_realize(DeviceState *dev, Error **errp) | ||
23 | { | ||
24 | int i; | ||
25 | AspeedSoCState *s = ASPEED_SOC(dev); | ||
26 | @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_class_init(ObjectClass *oc, void *data) | ||
27 | { | ||
28 | DeviceClass *dc = DEVICE_CLASS(oc); | ||
29 | |||
30 | - dc->realize = aspeed_soc_realize; | ||
31 | - /* Reason: Uses serial_hds and nd_table in realize() directly */ | ||
32 | - dc->user_creatable = false; | ||
33 | device_class_set_props(dc, aspeed_soc_properties); | ||
34 | } | ||
35 | |||
36 | @@ -XXX,XX +XXX,XX @@ static const TypeInfo aspeed_soc_type_info = { | ||
37 | static void aspeed_soc_ast2400_class_init(ObjectClass *oc, void *data) | ||
38 | { | ||
39 | AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc); | ||
40 | + DeviceClass *dc = DEVICE_CLASS(oc); | ||
41 | + | ||
42 | + dc->realize = aspeed_ast2400_soc_realize; | ||
43 | + /* Reason: Uses serial_hds and nd_table in realize() directly */ | ||
44 | + dc->user_creatable = false; | ||
45 | |||
46 | sc->name = "ast2400-a1"; | ||
47 | sc->cpu_type = ARM_CPU_TYPE_NAME("arm926"); | ||
48 | @@ -XXX,XX +XXX,XX @@ static const TypeInfo aspeed_soc_ast2400_type_info = { | ||
49 | static void aspeed_soc_ast2500_class_init(ObjectClass *oc, void *data) | ||
50 | { | ||
51 | AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc); | ||
52 | + DeviceClass *dc = DEVICE_CLASS(oc); | ||
53 | + | ||
54 | + dc->realize = aspeed_ast2400_soc_realize; | ||
55 | + /* Reason: Uses serial_hds and nd_table in realize() directly */ | ||
56 | + dc->user_creatable = false; | ||
57 | |||
58 | sc->name = "ast2500-a1"; | ||
59 | sc->cpu_type = ARM_CPU_TYPE_NAME("arm1176"); | ||
60 | -- | ||
61 | 2.41.0 | ||
62 | |||
63 | diff view generated by jsdifflib |
1 | From: John Wang <wangzhiqiang.bj@bytedance.com> | 1 | From: Philippe Mathieu-Daudé <philmd@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | G220A is a 2 socket x86 motherboard supported by OpenBMC. | 3 | We want to derivate the big AspeedSoCState object in some more |
4 | Strapping configuration was obtained from hardware. | 4 | SoC-specific ones. Since the object size will vary, allocate it |
5 | 5 | dynamically. | |
6 | Signed-off-by: John Wang <wangzhiqiang.bj@bytedance.com> | 6 | |
7 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
7 | Reviewed-by: Cédric Le Goater <clg@kaod.org> | 8 | Reviewed-by: Cédric Le Goater <clg@kaod.org> |
8 | Reviewed-by: Joel Stanley <joel@jms.id.au> | ||
9 | Message-Id: <20201122105134.671-2-wangzhiqiang.bj@bytedance.com> | ||
10 | Signed-off-by: Cédric Le Goater <clg@kaod.org> | 9 | Signed-off-by: Cédric Le Goater <clg@kaod.org> |
11 | --- | 10 | --- |
12 | hw/arm/aspeed.c | 60 +++++++++++++++++++++++++++++++++++++++++++++++++ | 11 | hw/arm/aspeed.c | 101 +++++++++++++++++++++++++----------------------- |
13 | 1 file changed, 60 insertions(+) | 12 | 1 file changed, 52 insertions(+), 49 deletions(-) |
14 | 13 | ||
15 | diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c | 14 | diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c |
16 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/hw/arm/aspeed.c | 16 | --- a/hw/arm/aspeed.c |
18 | +++ b/hw/arm/aspeed.c | 17 | +++ b/hw/arm/aspeed.c |
19 | @@ -XXX,XX +XXX,XX @@ struct AspeedMachineState { | 18 | @@ -XXX,XX +XXX,XX @@ struct AspeedMachineState { |
20 | SCU_AST2500_HW_STRAP_ACPI_ENABLE | \ | 19 | MachineState parent_obj; |
21 | SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER)) | 20 | /* Public */ |
22 | 21 | ||
23 | +#define G220A_BMC_HW_STRAP1 ( \ | 22 | - AspeedSoCState soc; |
24 | + SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ | 23 | + AspeedSoCState *soc; |
25 | + SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ | 24 | MemoryRegion boot_rom; |
26 | + SCU_AST2500_HW_STRAP_UART_DEBUG | \ | 25 | bool mmio_exec; |
27 | + SCU_AST2500_HW_STRAP_RESERVED28 | \ | 26 | uint32_t uart_chosen; |
28 | + SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ | 27 | @@ -XXX,XX +XXX,XX @@ static void write_boot_rom(BlockBackend *blk, hwaddr addr, size_t rom_size, |
29 | + SCU_HW_STRAP_2ND_BOOT_WDT | \ | 28 | static void aspeed_install_boot_rom(AspeedMachineState *bmc, BlockBackend *blk, |
30 | + SCU_HW_STRAP_VGA_CLASS_CODE | \ | 29 | uint64_t rom_size) |
31 | + SCU_HW_STRAP_LPC_RESET_PIN | \ | 30 | { |
32 | + SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \ | 31 | - AspeedSoCState *soc = &bmc->soc; |
33 | + SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \ | 32 | + AspeedSoCState *soc = bmc->soc; |
34 | + SCU_HW_STRAP_VGA_SIZE_SET(VGA_64M_DRAM) | \ | 33 | |
35 | + SCU_AST2500_HW_STRAP_RESERVED1) | 34 | memory_region_init_rom(&bmc->boot_rom, NULL, "aspeed.boot_rom", rom_size, |
36 | + | 35 | &error_abort); |
37 | /* Witherspoon hardware value: 0xF10AD216 (but use romulus definition) */ | 36 | @@ -XXX,XX +XXX,XX @@ static void sdhci_attach_drive(SDHCIState *sdhci, DriveInfo *dinfo) |
38 | #define WITHERSPOON_BMC_HW_STRAP1 ROMULUS_BMC_HW_STRAP1 | 37 | static void connect_serial_hds_to_uarts(AspeedMachineState *bmc) |
39 | 38 | { | |
39 | AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(bmc); | ||
40 | - AspeedSoCState *s = &bmc->soc; | ||
41 | + AspeedSoCState *s = bmc->soc; | ||
42 | AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); | ||
43 | int uart_chosen = bmc->uart_chosen ? bmc->uart_chosen : amc->uart_default; | ||
44 | |||
45 | @@ -XXX,XX +XXX,XX @@ static void aspeed_machine_init(MachineState *machine) | ||
46 | int i; | ||
47 | NICInfo *nd = &nd_table[0]; | ||
48 | |||
49 | - object_initialize_child(OBJECT(machine), "soc", &bmc->soc, amc->soc_name); | ||
50 | - | ||
51 | - sc = ASPEED_SOC_GET_CLASS(&bmc->soc); | ||
52 | + bmc->soc = ASPEED_SOC(object_new(amc->soc_name)); | ||
53 | + object_property_add_child(OBJECT(machine), "soc", OBJECT(bmc->soc)); | ||
54 | + object_unref(OBJECT(bmc->soc)); | ||
55 | + sc = ASPEED_SOC_GET_CLASS(bmc->soc); | ||
56 | |||
57 | /* | ||
58 | * This will error out if the RAM size is not supported by the | ||
59 | * memory controller of the SoC. | ||
60 | */ | ||
61 | - object_property_set_uint(OBJECT(&bmc->soc), "ram-size", machine->ram_size, | ||
62 | + object_property_set_uint(OBJECT(bmc->soc), "ram-size", machine->ram_size, | ||
63 | &error_fatal); | ||
64 | |||
65 | for (i = 0; i < sc->macs_num; i++) { | ||
66 | if ((amc->macs_mask & (1 << i)) && nd->used) { | ||
67 | qemu_check_nic_model(nd, TYPE_FTGMAC100); | ||
68 | - qdev_set_nic_properties(DEVICE(&bmc->soc.ftgmac100[i]), nd); | ||
69 | + qdev_set_nic_properties(DEVICE(&bmc->soc->ftgmac100[i]), nd); | ||
70 | nd++; | ||
71 | } | ||
72 | } | ||
73 | |||
74 | - object_property_set_int(OBJECT(&bmc->soc), "hw-strap1", amc->hw_strap1, | ||
75 | + object_property_set_int(OBJECT(bmc->soc), "hw-strap1", amc->hw_strap1, | ||
76 | &error_abort); | ||
77 | - object_property_set_int(OBJECT(&bmc->soc), "hw-strap2", amc->hw_strap2, | ||
78 | + object_property_set_int(OBJECT(bmc->soc), "hw-strap2", amc->hw_strap2, | ||
79 | &error_abort); | ||
80 | - object_property_set_link(OBJECT(&bmc->soc), "memory", | ||
81 | + object_property_set_link(OBJECT(bmc->soc), "memory", | ||
82 | OBJECT(get_system_memory()), &error_abort); | ||
83 | - object_property_set_link(OBJECT(&bmc->soc), "dram", | ||
84 | + object_property_set_link(OBJECT(bmc->soc), "dram", | ||
85 | OBJECT(machine->ram), &error_abort); | ||
86 | if (machine->kernel_filename) { | ||
87 | /* | ||
88 | @@ -XXX,XX +XXX,XX @@ static void aspeed_machine_init(MachineState *machine) | ||
89 | * that runs to unlock the SCU. In this case set the default to | ||
90 | * be unlocked as the kernel expects | ||
91 | */ | ||
92 | - object_property_set_int(OBJECT(&bmc->soc), "hw-prot-key", | ||
93 | + object_property_set_int(OBJECT(bmc->soc), "hw-prot-key", | ||
94 | ASPEED_SCU_PROT_KEY, &error_abort); | ||
95 | } | ||
96 | connect_serial_hds_to_uarts(bmc); | ||
97 | - qdev_realize(DEVICE(&bmc->soc), NULL, &error_abort); | ||
98 | + qdev_realize(DEVICE(bmc->soc), NULL, &error_abort); | ||
99 | |||
100 | if (defaults_enabled()) { | ||
101 | - aspeed_board_init_flashes(&bmc->soc.fmc, | ||
102 | + aspeed_board_init_flashes(&bmc->soc->fmc, | ||
103 | bmc->fmc_model ? bmc->fmc_model : amc->fmc_model, | ||
104 | amc->num_cs, 0); | ||
105 | - aspeed_board_init_flashes(&bmc->soc.spi[0], | ||
106 | + aspeed_board_init_flashes(&bmc->soc->spi[0], | ||
107 | bmc->spi_model ? bmc->spi_model : amc->spi_model, | ||
108 | 1, amc->num_cs); | ||
109 | } | ||
110 | @@ -XXX,XX +XXX,XX @@ static void aspeed_machine_init(MachineState *machine) | ||
111 | amc->i2c_init(bmc); | ||
112 | } | ||
113 | |||
114 | - for (i = 0; i < bmc->soc.sdhci.num_slots; i++) { | ||
115 | - sdhci_attach_drive(&bmc->soc.sdhci.slots[i], | ||
116 | + for (i = 0; i < bmc->soc->sdhci.num_slots; i++) { | ||
117 | + sdhci_attach_drive(&bmc->soc->sdhci.slots[i], | ||
118 | drive_get(IF_SD, 0, i)); | ||
119 | } | ||
120 | |||
121 | - if (bmc->soc.emmc.num_slots) { | ||
122 | - sdhci_attach_drive(&bmc->soc.emmc.slots[0], | ||
123 | - drive_get(IF_SD, 0, bmc->soc.sdhci.num_slots)); | ||
124 | + if (bmc->soc->emmc.num_slots) { | ||
125 | + sdhci_attach_drive(&bmc->soc->emmc.slots[0], | ||
126 | + drive_get(IF_SD, 0, bmc->soc->sdhci.num_slots)); | ||
127 | } | ||
128 | |||
129 | if (!bmc->mmio_exec) { | ||
130 | - DeviceState *dev = ssi_get_cs(bmc->soc.fmc.spi, 0); | ||
131 | + DeviceState *dev = ssi_get_cs(bmc->soc->fmc.spi, 0); | ||
132 | BlockBackend *fmc0 = dev ? m25p80_get_blk(dev) : NULL; | ||
133 | |||
134 | if (fmc0) { | ||
135 | - uint64_t rom_size = memory_region_size(&bmc->soc.spi_boot); | ||
136 | + uint64_t rom_size = memory_region_size(&bmc->soc->spi_boot); | ||
137 | aspeed_install_boot_rom(bmc, fmc0, rom_size); | ||
138 | } | ||
139 | } | ||
140 | @@ -XXX,XX +XXX,XX @@ static void aspeed_machine_init(MachineState *machine) | ||
141 | |||
142 | static void palmetto_bmc_i2c_init(AspeedMachineState *bmc) | ||
143 | { | ||
144 | - AspeedSoCState *soc = &bmc->soc; | ||
145 | + AspeedSoCState *soc = bmc->soc; | ||
146 | DeviceState *dev; | ||
147 | uint8_t *eeprom_buf = g_malloc0(32 * 1024); | ||
148 | |||
149 | @@ -XXX,XX +XXX,XX @@ static void palmetto_bmc_i2c_init(AspeedMachineState *bmc) | ||
150 | |||
151 | static void quanta_q71l_bmc_i2c_init(AspeedMachineState *bmc) | ||
152 | { | ||
153 | - AspeedSoCState *soc = &bmc->soc; | ||
154 | + AspeedSoCState *soc = bmc->soc; | ||
155 | |||
156 | /* | ||
157 | * The quanta-q71l platform expects tmp75s which are compatible with | ||
158 | @@ -XXX,XX +XXX,XX @@ static void quanta_q71l_bmc_i2c_init(AspeedMachineState *bmc) | ||
159 | |||
160 | static void ast2500_evb_i2c_init(AspeedMachineState *bmc) | ||
161 | { | ||
162 | - AspeedSoCState *soc = &bmc->soc; | ||
163 | + AspeedSoCState *soc = bmc->soc; | ||
164 | uint8_t *eeprom_buf = g_malloc0(8 * 1024); | ||
165 | |||
166 | smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 3), 0x50, | ||
167 | @@ -XXX,XX +XXX,XX @@ static void ast2500_evb_i2c_init(AspeedMachineState *bmc) | ||
168 | |||
169 | static void ast2600_evb_i2c_init(AspeedMachineState *bmc) | ||
170 | { | ||
171 | - AspeedSoCState *soc = &bmc->soc; | ||
172 | + AspeedSoCState *soc = bmc->soc; | ||
173 | uint8_t *eeprom_buf = g_malloc0(8 * 1024); | ||
174 | |||
175 | smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 7), 0x50, | ||
176 | @@ -XXX,XX +XXX,XX @@ static void ast2600_evb_i2c_init(AspeedMachineState *bmc) | ||
177 | |||
178 | static void yosemitev2_bmc_i2c_init(AspeedMachineState *bmc) | ||
179 | { | ||
180 | - AspeedSoCState *soc = &bmc->soc; | ||
181 | + AspeedSoCState *soc = bmc->soc; | ||
182 | |||
183 | at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 4), 0x51, 128 * KiB); | ||
184 | at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 8), 0x51, 128 * KiB, | ||
185 | @@ -XXX,XX +XXX,XX @@ static void yosemitev2_bmc_i2c_init(AspeedMachineState *bmc) | ||
186 | |||
187 | static void romulus_bmc_i2c_init(AspeedMachineState *bmc) | ||
188 | { | ||
189 | - AspeedSoCState *soc = &bmc->soc; | ||
190 | + AspeedSoCState *soc = bmc->soc; | ||
191 | |||
192 | /* The romulus board expects Epson RX8900 I2C RTC but a ds1338 is | ||
193 | * good enough */ | ||
194 | @@ -XXX,XX +XXX,XX @@ static void romulus_bmc_i2c_init(AspeedMachineState *bmc) | ||
195 | |||
196 | static void tiogapass_bmc_i2c_init(AspeedMachineState *bmc) | ||
197 | { | ||
198 | - AspeedSoCState *soc = &bmc->soc; | ||
199 | + AspeedSoCState *soc = bmc->soc; | ||
200 | |||
201 | at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 4), 0x54, 128 * KiB); | ||
202 | at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 6), 0x54, 128 * KiB, | ||
203 | @@ -XXX,XX +XXX,XX @@ static void create_pca9552(AspeedSoCState *soc, int bus_id, int addr) | ||
204 | |||
205 | static void sonorapass_bmc_i2c_init(AspeedMachineState *bmc) | ||
206 | { | ||
207 | - AspeedSoCState *soc = &bmc->soc; | ||
208 | + AspeedSoCState *soc = bmc->soc; | ||
209 | |||
210 | /* bus 2 : */ | ||
211 | i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "tmp105", 0x48); | ||
40 | @@ -XXX,XX +XXX,XX @@ static void witherspoon_bmc_i2c_init(AspeedMachineState *bmc) | 212 | @@ -XXX,XX +XXX,XX @@ static void witherspoon_bmc_i2c_init(AspeedMachineState *bmc) |
41 | /* Bus 11: TODO ucd90160@64 */ | 213 | {14, LED_COLOR_GREEN, "front-power-3", GPIO_POLARITY_ACTIVE_LOW}, |
214 | {15, LED_COLOR_GREEN, "front-id-5", GPIO_POLARITY_ACTIVE_LOW}, | ||
215 | }; | ||
216 | - AspeedSoCState *soc = &bmc->soc; | ||
217 | + AspeedSoCState *soc = bmc->soc; | ||
218 | uint8_t *eeprom_buf = g_malloc0(8 * 1024); | ||
219 | DeviceState *dev; | ||
220 | LEDState *led; | ||
221 | @@ -XXX,XX +XXX,XX @@ static void witherspoon_bmc_i2c_init(AspeedMachineState *bmc) | ||
222 | |||
223 | static void g220a_bmc_i2c_init(AspeedMachineState *bmc) | ||
224 | { | ||
225 | - AspeedSoCState *soc = &bmc->soc; | ||
226 | + AspeedSoCState *soc = bmc->soc; | ||
227 | DeviceState *dev; | ||
228 | |||
229 | dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), | ||
230 | @@ -XXX,XX +XXX,XX @@ static void g220a_bmc_i2c_init(AspeedMachineState *bmc) | ||
231 | |||
232 | static void fp5280g2_bmc_i2c_init(AspeedMachineState *bmc) | ||
233 | { | ||
234 | - AspeedSoCState *soc = &bmc->soc; | ||
235 | + AspeedSoCState *soc = bmc->soc; | ||
236 | I2CSlave *i2c_mux; | ||
237 | |||
238 | /* The at24c256 */ | ||
239 | @@ -XXX,XX +XXX,XX @@ static void fp5280g2_bmc_i2c_init(AspeedMachineState *bmc) | ||
240 | |||
241 | static void rainier_bmc_i2c_init(AspeedMachineState *bmc) | ||
242 | { | ||
243 | - AspeedSoCState *soc = &bmc->soc; | ||
244 | + AspeedSoCState *soc = bmc->soc; | ||
245 | I2CSlave *i2c_mux; | ||
246 | |||
247 | at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 0), 0x51, 32 * KiB); | ||
248 | @@ -XXX,XX +XXX,XX @@ static void get_pca9548_channels(I2CBus *bus, uint8_t mux_addr, | ||
249 | |||
250 | static void fuji_bmc_i2c_init(AspeedMachineState *bmc) | ||
251 | { | ||
252 | - AspeedSoCState *soc = &bmc->soc; | ||
253 | + AspeedSoCState *soc = bmc->soc; | ||
254 | I2CBus *i2c[144] = {}; | ||
255 | |||
256 | for (int i = 0; i < 16; i++) { | ||
257 | @@ -XXX,XX +XXX,XX @@ static void fuji_bmc_i2c_init(AspeedMachineState *bmc) | ||
258 | |||
259 | static void bletchley_bmc_i2c_init(AspeedMachineState *bmc) | ||
260 | { | ||
261 | - AspeedSoCState *soc = &bmc->soc; | ||
262 | + AspeedSoCState *soc = bmc->soc; | ||
263 | I2CBus *i2c[13] = {}; | ||
264 | for (int i = 0; i < 13; i++) { | ||
265 | if ((i == 8) || (i == 11)) { | ||
266 | @@ -XXX,XX +XXX,XX @@ static void bletchley_bmc_i2c_init(AspeedMachineState *bmc) | ||
267 | |||
268 | static void fby35_i2c_init(AspeedMachineState *bmc) | ||
269 | { | ||
270 | - AspeedSoCState *soc = &bmc->soc; | ||
271 | + AspeedSoCState *soc = bmc->soc; | ||
272 | I2CBus *i2c[16]; | ||
273 | |||
274 | for (int i = 0; i < 16; i++) { | ||
275 | @@ -XXX,XX +XXX,XX @@ static void fby35_i2c_init(AspeedMachineState *bmc) | ||
276 | |||
277 | static void qcom_dc_scm_bmc_i2c_init(AspeedMachineState *bmc) | ||
278 | { | ||
279 | - AspeedSoCState *soc = &bmc->soc; | ||
280 | + AspeedSoCState *soc = bmc->soc; | ||
281 | |||
282 | i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 15), "tmp105", 0x4d); | ||
42 | } | 283 | } |
43 | 284 | ||
44 | +static void g220a_bmc_i2c_init(AspeedMachineState *bmc) | 285 | static void qcom_dc_scm_firework_i2c_init(AspeedMachineState *bmc) |
45 | +{ | 286 | { |
46 | + AspeedSoCState *soc = &bmc->soc; | 287 | - AspeedSoCState *soc = &bmc->soc; |
47 | + DeviceState *dev; | 288 | + AspeedSoCState *soc = bmc->soc; |
48 | + | 289 | I2CSlave *therm_mux, *cpuvr_mux; |
49 | + dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), | 290 | |
50 | + "emc1413", 0x4c)); | 291 | /* Create the generic DC-SCM hardware */ |
51 | + object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort); | 292 | @@ -XXX,XX +XXX,XX @@ static void aspeed_machine_bletchley_class_init(ObjectClass *oc, void *data) |
52 | + object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort); | 293 | static void fby35_reset(MachineState *state, ShutdownCause reason) |
53 | + object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort); | 294 | { |
54 | + | 295 | AspeedMachineState *bmc = ASPEED_MACHINE(state); |
55 | + dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 12), | 296 | - AspeedGPIOState *gpio = &bmc->soc.gpio; |
56 | + "emc1413", 0x4c)); | 297 | + AspeedGPIOState *gpio = &bmc->soc->gpio; |
57 | + object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort); | 298 | |
58 | + object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort); | 299 | qemu_devices_reset(reason); |
59 | + object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort); | 300 | |
60 | + | 301 | @@ -XXX,XX +XXX,XX @@ static void aspeed_minibmc_machine_init(MachineState *machine) |
61 | + dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 13), | 302 | sysclk = clock_new(OBJECT(machine), "SYSCLK"); |
62 | + "emc1413", 0x4c)); | 303 | clock_set_hz(sysclk, SYSCLK_FRQ); |
63 | + object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort); | 304 | |
64 | + object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort); | 305 | - object_initialize_child(OBJECT(machine), "soc", &bmc->soc, amc->soc_name); |
65 | + object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort); | 306 | - qdev_connect_clock_in(DEVICE(&bmc->soc), "sysclk", sysclk); |
66 | +} | 307 | + bmc->soc = ASPEED_SOC(object_new(amc->soc_name)); |
67 | + | 308 | + object_property_add_child(OBJECT(machine), "soc", OBJECT(bmc->soc)); |
68 | static bool aspeed_get_mmio_exec(Object *obj, Error **errp) | 309 | + object_unref(OBJECT(bmc->soc)); |
69 | { | 310 | + qdev_connect_clock_in(DEVICE(bmc->soc), "sysclk", sysclk); |
70 | return ASPEED_MACHINE(obj)->mmio_exec; | 311 | |
71 | @@ -XXX,XX +XXX,XX @@ static void aspeed_machine_tacoma_class_init(ObjectClass *oc, void *data) | 312 | - object_property_set_link(OBJECT(&bmc->soc), "memory", |
72 | aspeed_soc_num_cpus(amc->soc_name); | 313 | + object_property_set_link(OBJECT(bmc->soc), "memory", |
73 | }; | 314 | OBJECT(get_system_memory()), &error_abort); |
74 | 315 | connect_serial_hds_to_uarts(bmc); | |
75 | +static void aspeed_machine_g220a_class_init(ObjectClass *oc, void *data) | 316 | - qdev_realize(DEVICE(&bmc->soc), NULL, &error_abort); |
76 | +{ | 317 | + qdev_realize(DEVICE(bmc->soc), NULL, &error_abort); |
77 | + MachineClass *mc = MACHINE_CLASS(oc); | 318 | |
78 | + AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); | 319 | - aspeed_board_init_flashes(&bmc->soc.fmc, |
79 | + | 320 | + aspeed_board_init_flashes(&bmc->soc->fmc, |
80 | + mc->desc = "Bytedance G220A BMC (ARM1176)"; | 321 | bmc->fmc_model ? bmc->fmc_model : amc->fmc_model, |
81 | + amc->soc_name = "ast2500-a1"; | 322 | amc->num_cs, |
82 | + amc->hw_strap1 = G220A_BMC_HW_STRAP1; | 323 | 0); |
83 | + amc->fmc_model = "n25q512a"; | 324 | |
84 | + amc->spi_model = "mx25l25635e"; | 325 | - aspeed_board_init_flashes(&bmc->soc.spi[0], |
85 | + amc->num_cs = 2; | 326 | + aspeed_board_init_flashes(&bmc->soc->spi[0], |
86 | + amc->macs_mask = ASPEED_MAC1_ON | ASPEED_MAC2_ON; | 327 | bmc->spi_model ? bmc->spi_model : amc->spi_model, |
87 | + amc->i2c_init = g220a_bmc_i2c_init; | 328 | amc->num_cs, amc->num_cs); |
88 | + mc->default_ram_size = 1024 * MiB; | 329 | |
89 | + mc->default_cpus = mc->min_cpus = mc->max_cpus = | 330 | - aspeed_board_init_flashes(&bmc->soc.spi[1], |
90 | + aspeed_soc_num_cpus(amc->soc_name); | 331 | + aspeed_board_init_flashes(&bmc->soc->spi[1], |
91 | +}; | 332 | bmc->spi_model ? bmc->spi_model : amc->spi_model, |
92 | + | 333 | amc->num_cs, (amc->num_cs * 2)); |
93 | static const TypeInfo aspeed_machine_types[] = { | 334 | |
94 | { | 335 | @@ -XXX,XX +XXX,XX @@ static void aspeed_minibmc_machine_init(MachineState *machine) |
95 | .name = MACHINE_TYPE_NAME("palmetto-bmc"), | 336 | |
96 | @@ -XXX,XX +XXX,XX @@ static const TypeInfo aspeed_machine_types[] = { | 337 | static void ast1030_evb_i2c_init(AspeedMachineState *bmc) |
97 | .name = MACHINE_TYPE_NAME("tacoma-bmc"), | 338 | { |
98 | .parent = TYPE_ASPEED_MACHINE, | 339 | - AspeedSoCState *soc = &bmc->soc; |
99 | .class_init = aspeed_machine_tacoma_class_init, | 340 | + AspeedSoCState *soc = bmc->soc; |
100 | + }, { | 341 | |
101 | + .name = MACHINE_TYPE_NAME("g220a-bmc"), | 342 | /* U10 24C08 connects to SDA/SCL Group 1 by default */ |
102 | + .parent = TYPE_ASPEED_MACHINE, | 343 | uint8_t *eeprom_buf = g_malloc0(32 * 1024); |
103 | + .class_init = aspeed_machine_g220a_class_init, | ||
104 | }, { | ||
105 | .name = TYPE_ASPEED_MACHINE, | ||
106 | .parent = TYPE_MACHINE, | ||
107 | -- | 344 | -- |
108 | 2.26.2 | 345 | 2.41.0 |
109 | 346 | ||
110 | 347 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
1 | 2 | ||
3 | TYPE_ASPEED10X0_SOC inherits from TYPE_ASPEED_SOC. | ||
4 | In few commits we'll add more fields, but to keep | ||
5 | review process simple, don't add any yet. | ||
6 | |||
7 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
8 | Reviewed-by: Cédric Le Goater <clg@kaod.org> | ||
9 | Signed-off-by: Cédric Le Goater <clg@kaod.org> | ||
10 | --- | ||
11 | include/hw/arm/aspeed_soc.h | 7 +++++++ | ||
12 | hw/arm/aspeed_ast10x0.c | 26 +++++++++++++------------- | ||
13 | 2 files changed, 20 insertions(+), 13 deletions(-) | ||
14 | |||
15 | diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h | ||
16 | index XXXXXXX..XXXXXXX 100644 | ||
17 | --- a/include/hw/arm/aspeed_soc.h | ||
18 | +++ b/include/hw/arm/aspeed_soc.h | ||
19 | @@ -XXX,XX +XXX,XX @@ struct AspeedSoCState { | ||
20 | #define TYPE_ASPEED_SOC "aspeed-soc" | ||
21 | OBJECT_DECLARE_TYPE(AspeedSoCState, AspeedSoCClass, ASPEED_SOC) | ||
22 | |||
23 | +struct Aspeed10x0SoCState { | ||
24 | + AspeedSoCState parent; | ||
25 | +}; | ||
26 | + | ||
27 | +#define TYPE_ASPEED10X0_SOC "aspeed10x0-soc" | ||
28 | +OBJECT_DECLARE_SIMPLE_TYPE(Aspeed10x0SoCState, ASPEED10X0_SOC) | ||
29 | + | ||
30 | struct AspeedSoCClass { | ||
31 | DeviceClass parent_class; | ||
32 | |||
33 | diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c | ||
34 | index XXXXXXX..XXXXXXX 100644 | ||
35 | --- a/hw/arm/aspeed_ast10x0.c | ||
36 | +++ b/hw/arm/aspeed_ast10x0.c | ||
37 | @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast1030_class_init(ObjectClass *klass, void *data) | ||
38 | sc->get_irq = aspeed_soc_ast1030_get_irq; | ||
39 | } | ||
40 | |||
41 | -static const TypeInfo aspeed_soc_ast1030_type_info = { | ||
42 | - .name = "ast1030-a1", | ||
43 | - .parent = TYPE_ASPEED_SOC, | ||
44 | - .instance_size = sizeof(AspeedSoCState), | ||
45 | - .instance_init = aspeed_soc_ast1030_init, | ||
46 | - .class_init = aspeed_soc_ast1030_class_init, | ||
47 | - .class_size = sizeof(AspeedSoCClass), | ||
48 | +static const TypeInfo aspeed_soc_ast10x0_types[] = { | ||
49 | + { | ||
50 | + .name = TYPE_ASPEED10X0_SOC, | ||
51 | + .parent = TYPE_ASPEED_SOC, | ||
52 | + .instance_size = sizeof(Aspeed10x0SoCState), | ||
53 | + .abstract = true, | ||
54 | + }, { | ||
55 | + .name = "ast1030-a1", | ||
56 | + .parent = TYPE_ASPEED10X0_SOC, | ||
57 | + .instance_init = aspeed_soc_ast1030_init, | ||
58 | + .class_init = aspeed_soc_ast1030_class_init, | ||
59 | + }, | ||
60 | }; | ||
61 | |||
62 | -static void aspeed_soc_register_types(void) | ||
63 | -{ | ||
64 | - type_register_static(&aspeed_soc_ast1030_type_info); | ||
65 | -} | ||
66 | - | ||
67 | -type_init(aspeed_soc_register_types) | ||
68 | +DEFINE_TYPES(aspeed_soc_ast10x0_types) | ||
69 | -- | ||
70 | 2.41.0 | ||
71 | |||
72 | diff view generated by jsdifflib |
1 | From: Joel Stanley <joel@jms.id.au> | 1 | From: Philippe Mathieu-Daudé <philmd@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | On the AST2600A1, the SRAM size was increased to 89KB. | 3 | TYPE_ASPEED2600_SOC inherits from TYPE_ASPEED_SOC. |
4 | In few commits we'll add more fields, but to keep | ||
5 | review process simple, don't add any yet. | ||
4 | 6 | ||
5 | Fixes: 7582591ae745 ("aspeed: Support AST2600A1 silicon revision") | 7 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
6 | Signed-off-by: Joel Stanley <joel@jms.id.au> | ||
7 | Reviewed-by: Cédric Le Goater <clg@kaod.org> | 8 | Reviewed-by: Cédric Le Goater <clg@kaod.org> |
8 | Message-Id: <20201112012113.835858-1-joel@jms.id.au> | ||
9 | Signed-off-by: Cédric Le Goater <clg@kaod.org> | 9 | Signed-off-by: Cédric Le Goater <clg@kaod.org> |
10 | --- | 10 | --- |
11 | hw/arm/aspeed_ast2600.c | 2 +- | 11 | include/hw/arm/aspeed_soc.h | 7 +++++++ |
12 | 1 file changed, 1 insertion(+), 1 deletion(-) | 12 | hw/arm/aspeed_ast2600.c | 26 +++++++++++++------------- |
13 | 2 files changed, 20 insertions(+), 13 deletions(-) | ||
13 | 14 | ||
15 | diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h | ||
16 | index XXXXXXX..XXXXXXX 100644 | ||
17 | --- a/include/hw/arm/aspeed_soc.h | ||
18 | +++ b/include/hw/arm/aspeed_soc.h | ||
19 | @@ -XXX,XX +XXX,XX @@ struct AspeedSoCState { | ||
20 | #define TYPE_ASPEED_SOC "aspeed-soc" | ||
21 | OBJECT_DECLARE_TYPE(AspeedSoCState, AspeedSoCClass, ASPEED_SOC) | ||
22 | |||
23 | +struct Aspeed2600SoCState { | ||
24 | + AspeedSoCState parent; | ||
25 | +}; | ||
26 | + | ||
27 | +#define TYPE_ASPEED2600_SOC "aspeed2600-soc" | ||
28 | +OBJECT_DECLARE_SIMPLE_TYPE(Aspeed2600SoCState, ASPEED2600_SOC) | ||
29 | + | ||
30 | struct Aspeed10x0SoCState { | ||
31 | AspeedSoCState parent; | ||
32 | }; | ||
14 | diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c | 33 | diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c |
15 | index XXXXXXX..XXXXXXX 100644 | 34 | index XXXXXXX..XXXXXXX 100644 |
16 | --- a/hw/arm/aspeed_ast2600.c | 35 | --- a/hw/arm/aspeed_ast2600.c |
17 | +++ b/hw/arm/aspeed_ast2600.c | 36 | +++ b/hw/arm/aspeed_ast2600.c |
18 | @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data) | 37 | @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data) |
19 | sc->name = "ast2600-a1"; | 38 | sc->get_irq = aspeed_soc_ast2600_get_irq; |
20 | sc->cpu_type = ARM_CPU_TYPE_NAME("cortex-a7"); | 39 | } |
21 | sc->silicon_rev = AST2600_A1_SILICON_REV; | 40 | |
22 | - sc->sram_size = 0x10000; | 41 | -static const TypeInfo aspeed_soc_ast2600_type_info = { |
23 | + sc->sram_size = 0x16400; | 42 | - .name = "ast2600-a3", |
24 | sc->spis_num = 2; | 43 | - .parent = TYPE_ASPEED_SOC, |
25 | sc->ehcis_num = 2; | 44 | - .instance_size = sizeof(AspeedSoCState), |
26 | sc->wdts_num = 4; | 45 | - .instance_init = aspeed_soc_ast2600_init, |
46 | - .class_init = aspeed_soc_ast2600_class_init, | ||
47 | - .class_size = sizeof(AspeedSoCClass), | ||
48 | +static const TypeInfo aspeed_soc_ast2600_types[] = { | ||
49 | + { | ||
50 | + .name = TYPE_ASPEED2600_SOC, | ||
51 | + .parent = TYPE_ASPEED_SOC, | ||
52 | + .instance_size = sizeof(Aspeed2600SoCState), | ||
53 | + .abstract = true, | ||
54 | + }, { | ||
55 | + .name = "ast2600-a3", | ||
56 | + .parent = TYPE_ASPEED2600_SOC, | ||
57 | + .instance_init = aspeed_soc_ast2600_init, | ||
58 | + .class_init = aspeed_soc_ast2600_class_init, | ||
59 | + }, | ||
60 | }; | ||
61 | |||
62 | -static void aspeed_soc_register_types(void) | ||
63 | -{ | ||
64 | - type_register_static(&aspeed_soc_ast2600_type_info); | ||
65 | -}; | ||
66 | - | ||
67 | -type_init(aspeed_soc_register_types) | ||
68 | +DEFINE_TYPES(aspeed_soc_ast2600_types) | ||
27 | -- | 69 | -- |
28 | 2.26.2 | 70 | 2.41.0 |
29 | 71 | ||
30 | 72 | diff view generated by jsdifflib |
1 | From: John Wang <wangzhiqiang.bj@bytedance.com> | 1 | From: Philippe Mathieu-Daudé <philmd@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Largely inspired by the TMP421 temperature sensor, here is a model for | 3 | TYPE_ASPEED2400_SOC inherits from TYPE_ASPEED_SOC. |
4 | the EMC1413/EMC1414 temperature sensors. | 4 | In few commits we'll add more fields, but to keep |
5 | review process simple, don't add any yet. | ||
5 | 6 | ||
6 | Specs can be found here : | 7 | TYPE_ASPEED_SOC is common to various Aspeed SoCs, |
7 | http://ww1.microchip.com/downloads/en/DeviceDoc/20005274A.pdf | 8 | define it in aspeed_soc_common.c. |
8 | 9 | ||
9 | Cc: Philippe Mathieu-Daudé <philmd@redhat.com> | 10 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
10 | Signed-off-by: John Wang <wangzhiqiang.bj@bytedance.com> | ||
11 | Reviewed-by: Cédric Le Goater <clg@kaod.org> | 11 | Reviewed-by: Cédric Le Goater <clg@kaod.org> |
12 | Message-Id: <20201122105134.671-1-wangzhiqiang.bj@bytedance.com> | ||
13 | Signed-off-by: Cédric Le Goater <clg@kaod.org> | 12 | Signed-off-by: Cédric Le Goater <clg@kaod.org> |
14 | --- | 13 | --- |
15 | include/hw/misc/emc141x_regs.h | 37 ++++ | 14 | include/hw/arm/aspeed_soc.h | 7 +++++ |
16 | hw/misc/emc141x.c | 326 +++++++++++++++++++++++++++++++++ | 15 | hw/arm/aspeed_soc.c | 61 +++++++++++-------------------------- |
17 | tests/qtest/emc141x-test.c | 81 ++++++++ | 16 | hw/arm/aspeed_soc_common.c | 29 ++++++++++++++++++ |
18 | hw/arm/Kconfig | 1 + | 17 | 3 files changed, 53 insertions(+), 44 deletions(-) |
19 | hw/misc/Kconfig | 4 + | ||
20 | hw/misc/meson.build | 1 + | ||
21 | tests/qtest/meson.build | 1 + | ||
22 | 7 files changed, 451 insertions(+) | ||
23 | create mode 100644 include/hw/misc/emc141x_regs.h | ||
24 | create mode 100644 hw/misc/emc141x.c | ||
25 | create mode 100644 tests/qtest/emc141x-test.c | ||
26 | 18 | ||
27 | diff --git a/include/hw/misc/emc141x_regs.h b/include/hw/misc/emc141x_regs.h | 19 | diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h |
28 | new file mode 100644 | 20 | index XXXXXXX..XXXXXXX 100644 |
29 | index XXXXXXX..XXXXXXX | 21 | --- a/include/hw/arm/aspeed_soc.h |
30 | --- /dev/null | 22 | +++ b/include/hw/arm/aspeed_soc.h |
31 | +++ b/include/hw/misc/emc141x_regs.h | 23 | @@ -XXX,XX +XXX,XX @@ struct AspeedSoCState { |
32 | @@ -XXX,XX +XXX,XX @@ | 24 | #define TYPE_ASPEED_SOC "aspeed-soc" |
33 | +/* | 25 | OBJECT_DECLARE_TYPE(AspeedSoCState, AspeedSoCClass, ASPEED_SOC) |
34 | + * SMSC EMC141X temperature sensor. | 26 | |
35 | + * | 27 | +struct Aspeed2400SoCState { |
36 | + * Browse the data sheet: | 28 | + AspeedSoCState parent; |
37 | + * | ||
38 | + * http://ww1.microchip.com/downloads/en/DeviceDoc/20005274A.pdf | ||
39 | + * | ||
40 | + * This work is licensed under the terms of the GNU GPL, version 2 or | ||
41 | + * later. See the COPYING file in the top-level directory. | ||
42 | + */ | ||
43 | + | ||
44 | +#ifndef TMP105_REGS_H | ||
45 | +#define TMP105_REGS_H | ||
46 | + | ||
47 | +#define EMC1413_DEVICE_ID 0x21 | ||
48 | +#define EMC1414_DEVICE_ID 0x25 | ||
49 | +#define MANUFACTURER_ID 0x5d | ||
50 | +#define REVISION 0x04 | ||
51 | + | ||
52 | +/* the EMC141X registers */ | ||
53 | +#define EMC141X_TEMP_HIGH0 0x00 | ||
54 | +#define EMC141X_TEMP_HIGH1 0x01 | ||
55 | +#define EMC141X_TEMP_HIGH2 0x23 | ||
56 | +#define EMC141X_TEMP_HIGH3 0x2a | ||
57 | +#define EMC141X_TEMP_MAX_HIGH0 0x05 | ||
58 | +#define EMC141X_TEMP_MIN_HIGH0 0x06 | ||
59 | +#define EMC141X_TEMP_MAX_HIGH1 0x07 | ||
60 | +#define EMC141X_TEMP_MIN_HIGH1 0x08 | ||
61 | +#define EMC141X_TEMP_MAX_HIGH2 0x15 | ||
62 | +#define EMC141X_TEMP_MIN_HIGH2 0x16 | ||
63 | +#define EMC141X_TEMP_MAX_HIGH3 0x2c | ||
64 | +#define EMC141X_TEMP_MIN_HIGH3 0x2d | ||
65 | +#define EMC141X_DEVICE_ID 0xfd | ||
66 | +#define EMC141X_MANUFACTURER_ID 0xfe | ||
67 | +#define EMC141X_REVISION 0xff | ||
68 | + | ||
69 | +#endif | ||
70 | diff --git a/hw/misc/emc141x.c b/hw/misc/emc141x.c | ||
71 | new file mode 100644 | ||
72 | index XXXXXXX..XXXXXXX | ||
73 | --- /dev/null | ||
74 | +++ b/hw/misc/emc141x.c | ||
75 | @@ -XXX,XX +XXX,XX @@ | ||
76 | +/* | ||
77 | + * SMSC EMC141X temperature sensor. | ||
78 | + * | ||
79 | + * Copyright (c) 2020 Bytedance Corporation | ||
80 | + * Written by John Wang <wangzhiqiang.bj@bytedance.com> | ||
81 | + * | ||
82 | + * This program is free software; you can redistribute it and/or | ||
83 | + * modify it under the terms of the GNU General Public License as | ||
84 | + * published by the Free Software Foundation; either version 2 or | ||
85 | + * (at your option) version 3 of the License. | ||
86 | + * | ||
87 | + * This program is distributed in the hope that it will be useful, | ||
88 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
89 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
90 | + * GNU General Public License for more details. | ||
91 | + * | ||
92 | + * You should have received a copy of the GNU General Public License along | ||
93 | + * with this program; if not, see <http://www.gnu.org/licenses/>. | ||
94 | + */ | ||
95 | + | ||
96 | +#include "qemu/osdep.h" | ||
97 | +#include "hw/i2c/i2c.h" | ||
98 | +#include "migration/vmstate.h" | ||
99 | +#include "qapi/error.h" | ||
100 | +#include "qapi/visitor.h" | ||
101 | +#include "qemu/module.h" | ||
102 | +#include "qom/object.h" | ||
103 | +#include "hw/misc/emc141x_regs.h" | ||
104 | + | ||
105 | +#define SENSORS_COUNT_MAX 4 | ||
106 | + | ||
107 | +struct EMC141XState { | ||
108 | + I2CSlave parent_obj; | ||
109 | + struct { | ||
110 | + uint8_t raw_temp_min; | ||
111 | + uint8_t raw_temp_current; | ||
112 | + uint8_t raw_temp_max; | ||
113 | + } sensor[SENSORS_COUNT_MAX]; | ||
114 | + uint8_t len; | ||
115 | + uint8_t data; | ||
116 | + uint8_t pointer; | ||
117 | +}; | 29 | +}; |
118 | + | 30 | + |
119 | +struct EMC141XClass { | 31 | +#define TYPE_ASPEED2400_SOC "aspeed2400-soc" |
120 | + I2CSlaveClass parent_class; | 32 | +OBJECT_DECLARE_SIMPLE_TYPE(Aspeed2400SoCState, ASPEED2400_SOC) |
121 | + uint8_t model; | 33 | + |
122 | + unsigned sensors_count; | 34 | struct Aspeed2600SoCState { |
35 | AspeedSoCState parent; | ||
36 | }; | ||
37 | diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c | ||
38 | index XXXXXXX..XXXXXXX 100644 | ||
39 | --- a/hw/arm/aspeed_soc.c | ||
40 | +++ b/hw/arm/aspeed_soc.c | ||
41 | @@ -XXX,XX +XXX,XX @@ static void aspeed_ast2400_soc_realize(DeviceState *dev, Error **errp) | ||
42 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->hace), 0, | ||
43 | aspeed_soc_get_irq(s, ASPEED_DEV_HACE)); | ||
44 | } | ||
45 | -static Property aspeed_soc_properties[] = { | ||
46 | - DEFINE_PROP_LINK("memory", AspeedSoCState, memory, TYPE_MEMORY_REGION, | ||
47 | - MemoryRegion *), | ||
48 | - DEFINE_PROP_LINK("dram", AspeedSoCState, dram_mr, TYPE_MEMORY_REGION, | ||
49 | - MemoryRegion *), | ||
50 | - DEFINE_PROP_END_OF_LIST(), | ||
51 | -}; | ||
52 | - | ||
53 | -static void aspeed_soc_class_init(ObjectClass *oc, void *data) | ||
54 | -{ | ||
55 | - DeviceClass *dc = DEVICE_CLASS(oc); | ||
56 | - | ||
57 | - device_class_set_props(dc, aspeed_soc_properties); | ||
58 | -} | ||
59 | - | ||
60 | -static const TypeInfo aspeed_soc_type_info = { | ||
61 | - .name = TYPE_ASPEED_SOC, | ||
62 | - .parent = TYPE_DEVICE, | ||
63 | - .instance_size = sizeof(AspeedSoCState), | ||
64 | - .class_size = sizeof(AspeedSoCClass), | ||
65 | - .class_init = aspeed_soc_class_init, | ||
66 | - .abstract = true, | ||
67 | -}; | ||
68 | |||
69 | static void aspeed_soc_ast2400_class_init(ObjectClass *oc, void *data) | ||
70 | { | ||
71 | @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2400_class_init(ObjectClass *oc, void *data) | ||
72 | sc->get_irq = aspeed_soc_ast2400_get_irq; | ||
73 | } | ||
74 | |||
75 | -static const TypeInfo aspeed_soc_ast2400_type_info = { | ||
76 | - .name = "ast2400-a1", | ||
77 | - .parent = TYPE_ASPEED_SOC, | ||
78 | - .instance_init = aspeed_ast2400_soc_init, | ||
79 | - .instance_size = sizeof(AspeedSoCState), | ||
80 | - .class_init = aspeed_soc_ast2400_class_init, | ||
81 | -}; | ||
82 | - | ||
83 | static void aspeed_soc_ast2500_class_init(ObjectClass *oc, void *data) | ||
84 | { | ||
85 | AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc); | ||
86 | @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2500_class_init(ObjectClass *oc, void *data) | ||
87 | sc->get_irq = aspeed_soc_ast2400_get_irq; | ||
88 | } | ||
89 | |||
90 | -static const TypeInfo aspeed_soc_ast2500_type_info = { | ||
91 | - .name = "ast2500-a1", | ||
92 | - .parent = TYPE_ASPEED_SOC, | ||
93 | - .instance_init = aspeed_ast2400_soc_init, | ||
94 | - .instance_size = sizeof(AspeedSoCState), | ||
95 | - .class_init = aspeed_soc_ast2500_class_init, | ||
96 | -}; | ||
97 | -static void aspeed_soc_register_types(void) | ||
98 | -{ | ||
99 | - type_register_static(&aspeed_soc_type_info); | ||
100 | - type_register_static(&aspeed_soc_ast2400_type_info); | ||
101 | - type_register_static(&aspeed_soc_ast2500_type_info); | ||
102 | +static const TypeInfo aspeed_soc_ast2400_types[] = { | ||
103 | + { | ||
104 | + .name = TYPE_ASPEED2400_SOC, | ||
105 | + .parent = TYPE_ASPEED_SOC, | ||
106 | + .instance_init = aspeed_ast2400_soc_init, | ||
107 | + .instance_size = sizeof(Aspeed2400SoCState), | ||
108 | + .abstract = true, | ||
109 | + }, { | ||
110 | + .name = "ast2400-a1", | ||
111 | + .parent = TYPE_ASPEED2400_SOC, | ||
112 | + .class_init = aspeed_soc_ast2400_class_init, | ||
113 | + }, { | ||
114 | + .name = "ast2500-a1", | ||
115 | + .parent = TYPE_ASPEED2400_SOC, | ||
116 | + .class_init = aspeed_soc_ast2500_class_init, | ||
117 | + }, | ||
118 | }; | ||
119 | |||
120 | -type_init(aspeed_soc_register_types); | ||
121 | +DEFINE_TYPES(aspeed_soc_ast2400_types) | ||
122 | diff --git a/hw/arm/aspeed_soc_common.c b/hw/arm/aspeed_soc_common.c | ||
123 | index XXXXXXX..XXXXXXX 100644 | ||
124 | --- a/hw/arm/aspeed_soc_common.c | ||
125 | +++ b/hw/arm/aspeed_soc_common.c | ||
126 | @@ -XXX,XX +XXX,XX @@ | ||
127 | |||
128 | #include "qemu/osdep.h" | ||
129 | #include "qapi/error.h" | ||
130 | +#include "hw/qdev-properties.h" | ||
131 | #include "hw/misc/unimp.h" | ||
132 | #include "hw/arm/aspeed_soc.h" | ||
133 | #include "hw/char/serial.h" | ||
134 | @@ -XXX,XX +XXX,XX @@ void aspeed_mmio_map_unimplemented(AspeedSoCState *s, SysBusDevice *dev, | ||
135 | memory_region_add_subregion_overlap(s->memory, addr, | ||
136 | sysbus_mmio_get_region(dev, 0), -1000); | ||
137 | } | ||
138 | + | ||
139 | +static Property aspeed_soc_properties[] = { | ||
140 | + DEFINE_PROP_LINK("dram", AspeedSoCState, dram_mr, TYPE_MEMORY_REGION, | ||
141 | + MemoryRegion *), | ||
142 | + DEFINE_PROP_LINK("memory", AspeedSoCState, memory, TYPE_MEMORY_REGION, | ||
143 | + MemoryRegion *), | ||
144 | + DEFINE_PROP_END_OF_LIST(), | ||
123 | +}; | 145 | +}; |
124 | + | 146 | + |
125 | +#define TYPE_EMC141X "emc141x" | 147 | +static void aspeed_soc_class_init(ObjectClass *oc, void *data) |
126 | +OBJECT_DECLARE_TYPE(EMC141XState, EMC141XClass, EMC141X) | 148 | +{ |
149 | + DeviceClass *dc = DEVICE_CLASS(oc); | ||
127 | + | 150 | + |
128 | +static void emc141x_get_temperature(Object *obj, Visitor *v, const char *name, | 151 | + device_class_set_props(dc, aspeed_soc_properties); |
129 | + void *opaque, Error **errp) | ||
130 | +{ | ||
131 | + EMC141XState *s = EMC141X(obj); | ||
132 | + EMC141XClass *sc = EMC141X_GET_CLASS(s); | ||
133 | + int64_t value; | ||
134 | + unsigned tempid; | ||
135 | + | ||
136 | + if (sscanf(name, "temperature%u", &tempid) != 1) { | ||
137 | + error_setg(errp, "error reading %s: %s", name, g_strerror(errno)); | ||
138 | + return; | ||
139 | + } | ||
140 | + | ||
141 | + if (tempid >= sc->sensors_count) { | ||
142 | + error_setg(errp, "error reading %s", name); | ||
143 | + return; | ||
144 | + } | ||
145 | + | ||
146 | + value = s->sensor[tempid].raw_temp_current * 1000; | ||
147 | + | ||
148 | + visit_type_int(v, name, &value, errp); | ||
149 | +} | 152 | +} |
150 | + | 153 | + |
151 | +static void emc141x_set_temperature(Object *obj, Visitor *v, const char *name, | 154 | +static const TypeInfo aspeed_soc_types[] = { |
152 | + void *opaque, Error **errp) | 155 | + { |
153 | +{ | 156 | + .name = TYPE_ASPEED_SOC, |
154 | + EMC141XState *s = EMC141X(obj); | 157 | + .parent = TYPE_DEVICE, |
155 | + EMC141XClass *sc = EMC141X_GET_CLASS(s); | 158 | + .instance_size = sizeof(AspeedSoCState), |
156 | + int64_t temp; | 159 | + .class_size = sizeof(AspeedSoCClass), |
157 | + unsigned tempid; | 160 | + .class_init = aspeed_soc_class_init, |
158 | + | 161 | + .abstract = true, |
159 | + if (!visit_type_int(v, name, &temp, errp)) { | 162 | + }, |
160 | + return; | ||
161 | + } | ||
162 | + | ||
163 | + if (sscanf(name, "temperature%u", &tempid) != 1) { | ||
164 | + error_setg(errp, "error reading %s: %s", name, g_strerror(errno)); | ||
165 | + return; | ||
166 | + } | ||
167 | + | ||
168 | + if (tempid >= sc->sensors_count) { | ||
169 | + error_setg(errp, "error reading %s", name); | ||
170 | + return; | ||
171 | + } | ||
172 | + | ||
173 | + s->sensor[tempid].raw_temp_current = temp / 1000; | ||
174 | +} | ||
175 | + | ||
176 | +static void emc141x_read(EMC141XState *s) | ||
177 | +{ | ||
178 | + EMC141XClass *sc = EMC141X_GET_CLASS(s); | ||
179 | + switch (s->pointer) { | ||
180 | + case EMC141X_DEVICE_ID: | ||
181 | + s->data = sc->model; | ||
182 | + break; | ||
183 | + case EMC141X_MANUFACTURER_ID: | ||
184 | + s->data = MANUFACTURER_ID; | ||
185 | + break; | ||
186 | + case EMC141X_REVISION: | ||
187 | + s->data = REVISION; | ||
188 | + break; | ||
189 | + case EMC141X_TEMP_HIGH0: | ||
190 | + s->data = s->sensor[0].raw_temp_current; | ||
191 | + break; | ||
192 | + case EMC141X_TEMP_HIGH1: | ||
193 | + s->data = s->sensor[1].raw_temp_current; | ||
194 | + break; | ||
195 | + case EMC141X_TEMP_HIGH2: | ||
196 | + s->data = s->sensor[2].raw_temp_current; | ||
197 | + break; | ||
198 | + case EMC141X_TEMP_HIGH3: | ||
199 | + s->data = s->sensor[3].raw_temp_current; | ||
200 | + break; | ||
201 | + case EMC141X_TEMP_MAX_HIGH0: | ||
202 | + s->data = s->sensor[0].raw_temp_max; | ||
203 | + break; | ||
204 | + case EMC141X_TEMP_MAX_HIGH1: | ||
205 | + s->data = s->sensor[1].raw_temp_max; | ||
206 | + break; | ||
207 | + case EMC141X_TEMP_MAX_HIGH2: | ||
208 | + s->data = s->sensor[2].raw_temp_max; | ||
209 | + break; | ||
210 | + case EMC141X_TEMP_MAX_HIGH3: | ||
211 | + s->data = s->sensor[3].raw_temp_max; | ||
212 | + break; | ||
213 | + case EMC141X_TEMP_MIN_HIGH0: | ||
214 | + s->data = s->sensor[0].raw_temp_min; | ||
215 | + break; | ||
216 | + case EMC141X_TEMP_MIN_HIGH1: | ||
217 | + s->data = s->sensor[1].raw_temp_min; | ||
218 | + break; | ||
219 | + case EMC141X_TEMP_MIN_HIGH2: | ||
220 | + s->data = s->sensor[2].raw_temp_min; | ||
221 | + break; | ||
222 | + case EMC141X_TEMP_MIN_HIGH3: | ||
223 | + s->data = s->sensor[3].raw_temp_min; | ||
224 | + break; | ||
225 | + default: | ||
226 | + s->data = 0; | ||
227 | + } | ||
228 | +} | ||
229 | + | ||
230 | +static void emc141x_write(EMC141XState *s) | ||
231 | +{ | ||
232 | + switch (s->pointer) { | ||
233 | + case EMC141X_TEMP_MAX_HIGH0: | ||
234 | + s->sensor[0].raw_temp_max = s->data; | ||
235 | + break; | ||
236 | + case EMC141X_TEMP_MAX_HIGH1: | ||
237 | + s->sensor[1].raw_temp_max = s->data; | ||
238 | + break; | ||
239 | + case EMC141X_TEMP_MAX_HIGH2: | ||
240 | + s->sensor[2].raw_temp_max = s->data; | ||
241 | + break; | ||
242 | + case EMC141X_TEMP_MAX_HIGH3: | ||
243 | + s->sensor[3].raw_temp_max = s->data; | ||
244 | + break; | ||
245 | + case EMC141X_TEMP_MIN_HIGH0: | ||
246 | + s->sensor[0].raw_temp_min = s->data; | ||
247 | + break; | ||
248 | + case EMC141X_TEMP_MIN_HIGH1: | ||
249 | + s->sensor[1].raw_temp_min = s->data; | ||
250 | + break; | ||
251 | + case EMC141X_TEMP_MIN_HIGH2: | ||
252 | + s->sensor[2].raw_temp_min = s->data; | ||
253 | + break; | ||
254 | + case EMC141X_TEMP_MIN_HIGH3: | ||
255 | + s->sensor[3].raw_temp_min = s->data; | ||
256 | + break; | ||
257 | + default: | ||
258 | + s->data = 0; | ||
259 | + } | ||
260 | +} | ||
261 | + | ||
262 | +static uint8_t emc141x_rx(I2CSlave *i2c) | ||
263 | +{ | ||
264 | + EMC141XState *s = EMC141X(i2c); | ||
265 | + | ||
266 | + if (s->len == 0) { | ||
267 | + s->len++; | ||
268 | + return s->data; | ||
269 | + } else { | ||
270 | + return 0xff; | ||
271 | + } | ||
272 | +} | ||
273 | + | ||
274 | +static int emc141x_tx(I2CSlave *i2c, uint8_t data) | ||
275 | +{ | ||
276 | + EMC141XState *s = EMC141X(i2c); | ||
277 | + | ||
278 | + if (s->len == 0) { | ||
279 | + /* first byte is the reg pointer */ | ||
280 | + s->pointer = data; | ||
281 | + s->len++; | ||
282 | + } else if (s->len == 1) { | ||
283 | + s->data = data; | ||
284 | + emc141x_write(s); | ||
285 | + } | ||
286 | + | ||
287 | + return 0; | ||
288 | +} | ||
289 | + | ||
290 | +static int emc141x_event(I2CSlave *i2c, enum i2c_event event) | ||
291 | +{ | ||
292 | + EMC141XState *s = EMC141X(i2c); | ||
293 | + | ||
294 | + if (event == I2C_START_RECV) { | ||
295 | + emc141x_read(s); | ||
296 | + } | ||
297 | + | ||
298 | + s->len = 0; | ||
299 | + return 0; | ||
300 | +} | ||
301 | + | ||
302 | +static const VMStateDescription vmstate_emc141x = { | ||
303 | + .name = "EMC141X", | ||
304 | + .version_id = 0, | ||
305 | + .minimum_version_id = 0, | ||
306 | + .fields = (VMStateField[]) { | ||
307 | + VMSTATE_UINT8(len, EMC141XState), | ||
308 | + VMSTATE_UINT8(data, EMC141XState), | ||
309 | + VMSTATE_UINT8(pointer, EMC141XState), | ||
310 | + VMSTATE_I2C_SLAVE(parent_obj, EMC141XState), | ||
311 | + VMSTATE_END_OF_LIST() | ||
312 | + } | ||
313 | +}; | 163 | +}; |
314 | + | 164 | + |
315 | +static void emc141x_reset(DeviceState *dev) | 165 | +DEFINE_TYPES(aspeed_soc_types) |
316 | +{ | ||
317 | + EMC141XState *s = EMC141X(dev); | ||
318 | + int i; | ||
319 | + | ||
320 | + for (i = 0; i < SENSORS_COUNT_MAX; i++) { | ||
321 | + s->sensor[i].raw_temp_max = 0x55; | ||
322 | + } | ||
323 | + s->pointer = 0; | ||
324 | + s->len = 0; | ||
325 | +} | ||
326 | + | ||
327 | +static void emc141x_initfn(Object *obj) | ||
328 | +{ | ||
329 | + object_property_add(obj, "temperature0", "int", | ||
330 | + emc141x_get_temperature, | ||
331 | + emc141x_set_temperature, NULL, NULL); | ||
332 | + object_property_add(obj, "temperature1", "int", | ||
333 | + emc141x_get_temperature, | ||
334 | + emc141x_set_temperature, NULL, NULL); | ||
335 | + object_property_add(obj, "temperature2", "int", | ||
336 | + emc141x_get_temperature, | ||
337 | + emc141x_set_temperature, NULL, NULL); | ||
338 | + object_property_add(obj, "temperature3", "int", | ||
339 | + emc141x_get_temperature, | ||
340 | + emc141x_set_temperature, NULL, NULL); | ||
341 | +} | ||
342 | + | ||
343 | +static void emc141x_class_init(ObjectClass *klass, void *data) | ||
344 | +{ | ||
345 | + DeviceClass *dc = DEVICE_CLASS(klass); | ||
346 | + I2CSlaveClass *k = I2C_SLAVE_CLASS(klass); | ||
347 | + | ||
348 | + dc->reset = emc141x_reset; | ||
349 | + k->event = emc141x_event; | ||
350 | + k->recv = emc141x_rx; | ||
351 | + k->send = emc141x_tx; | ||
352 | + dc->vmsd = &vmstate_emc141x; | ||
353 | +} | ||
354 | + | ||
355 | +static void emc1413_class_init(ObjectClass *klass, void *data) | ||
356 | +{ | ||
357 | + EMC141XClass *ec = EMC141X_CLASS(klass); | ||
358 | + | ||
359 | + emc141x_class_init(klass, data); | ||
360 | + ec->model = EMC1413_DEVICE_ID; | ||
361 | + ec->sensors_count = 3; | ||
362 | +} | ||
363 | + | ||
364 | +static void emc1414_class_init(ObjectClass *klass, void *data) | ||
365 | +{ | ||
366 | + EMC141XClass *ec = EMC141X_CLASS(klass); | ||
367 | + | ||
368 | + emc141x_class_init(klass, data); | ||
369 | + ec->model = EMC1414_DEVICE_ID; | ||
370 | + ec->sensors_count = 4; | ||
371 | +} | ||
372 | + | ||
373 | +static const TypeInfo emc141x_info = { | ||
374 | + .name = TYPE_EMC141X, | ||
375 | + .parent = TYPE_I2C_SLAVE, | ||
376 | + .instance_size = sizeof(EMC141XState), | ||
377 | + .class_size = sizeof(EMC141XClass), | ||
378 | + .instance_init = emc141x_initfn, | ||
379 | + .abstract = true, | ||
380 | +}; | ||
381 | + | ||
382 | +static const TypeInfo emc1413_info = { | ||
383 | + .name = "emc1413", | ||
384 | + .parent = TYPE_EMC141X, | ||
385 | + .class_init = emc1413_class_init, | ||
386 | +}; | ||
387 | + | ||
388 | +static const TypeInfo emc1414_info = { | ||
389 | + .name = "emc1414", | ||
390 | + .parent = TYPE_EMC141X, | ||
391 | + .class_init = emc1414_class_init, | ||
392 | +}; | ||
393 | + | ||
394 | +static void emc141x_register_types(void) | ||
395 | +{ | ||
396 | + type_register_static(&emc141x_info); | ||
397 | + type_register_static(&emc1413_info); | ||
398 | + type_register_static(&emc1414_info); | ||
399 | +} | ||
400 | + | ||
401 | +type_init(emc141x_register_types) | ||
402 | diff --git a/tests/qtest/emc141x-test.c b/tests/qtest/emc141x-test.c | ||
403 | new file mode 100644 | ||
404 | index XXXXXXX..XXXXXXX | ||
405 | --- /dev/null | ||
406 | +++ b/tests/qtest/emc141x-test.c | ||
407 | @@ -XXX,XX +XXX,XX @@ | ||
408 | +/* | ||
409 | + * QTest testcase for the EMC141X temperature sensor | ||
410 | + * | ||
411 | + * This work is licensed under the terms of the GNU GPL, version 2 or later. | ||
412 | + * See the COPYING file in the top-level directory. | ||
413 | + */ | ||
414 | + | ||
415 | +#include "qemu/osdep.h" | ||
416 | + | ||
417 | +#include "libqtest-single.h" | ||
418 | +#include "libqos/qgraph.h" | ||
419 | +#include "libqos/i2c.h" | ||
420 | +#include "qapi/qmp/qdict.h" | ||
421 | +#include "hw/misc/emc141x_regs.h" | ||
422 | + | ||
423 | +#define EMC1414_TEST_ID "emc1414-test" | ||
424 | + | ||
425 | +static int qmp_emc1414_get_temperature(const char *id) | ||
426 | +{ | ||
427 | + QDict *response; | ||
428 | + int ret; | ||
429 | + | ||
430 | + response = qmp("{ 'execute': 'qom-get', 'arguments': { 'path': %s, " | ||
431 | + "'property': 'temperature0' } }", id); | ||
432 | + g_assert(qdict_haskey(response, "return")); | ||
433 | + ret = qdict_get_int(response, "return"); | ||
434 | + qobject_unref(response); | ||
435 | + return ret; | ||
436 | +} | ||
437 | + | ||
438 | +static void qmp_emc1414_set_temperature(const char *id, int value) | ||
439 | +{ | ||
440 | + QDict *response; | ||
441 | + | ||
442 | + response = qmp("{ 'execute': 'qom-set', 'arguments': { 'path': %s, " | ||
443 | + "'property': 'temperature0', 'value': %d } }", id, value); | ||
444 | + g_assert(qdict_haskey(response, "return")); | ||
445 | + qobject_unref(response); | ||
446 | +} | ||
447 | + | ||
448 | +static void send_and_receive(void *obj, void *data, QGuestAllocator *alloc) | ||
449 | +{ | ||
450 | + uint16_t value; | ||
451 | + QI2CDevice *i2cdev = (QI2CDevice *)obj; | ||
452 | + | ||
453 | + value = qmp_emc1414_get_temperature(EMC1414_TEST_ID); | ||
454 | + g_assert_cmpuint(value, ==, 0); | ||
455 | + | ||
456 | + value = i2c_get8(i2cdev, EMC141X_TEMP_HIGH0); | ||
457 | + g_assert_cmphex(value, ==, 0); | ||
458 | + | ||
459 | + /* The default max value is 85C, 0x55=85 */ | ||
460 | + value = i2c_get8(i2cdev, EMC141X_TEMP_MAX_HIGH0); | ||
461 | + g_assert_cmphex(value, ==, 0x55); | ||
462 | + | ||
463 | + value = i2c_get8(i2cdev, EMC141X_TEMP_MIN_HIGH0); | ||
464 | + g_assert_cmphex(value, ==, 0); | ||
465 | + | ||
466 | + /* 3000mc = 30C */ | ||
467 | + qmp_emc1414_set_temperature(EMC1414_TEST_ID, 30000); | ||
468 | + value = qmp_emc1414_get_temperature(EMC1414_TEST_ID); | ||
469 | + g_assert_cmpuint(value, ==, 30000); | ||
470 | + | ||
471 | + value = i2c_get8(i2cdev, EMC141X_TEMP_HIGH0); | ||
472 | + g_assert_cmphex(value, ==, 30); | ||
473 | + | ||
474 | +} | ||
475 | + | ||
476 | +static void emc1414_register_nodes(void) | ||
477 | +{ | ||
478 | + QOSGraphEdgeOptions opts = { | ||
479 | + .extra_device_opts = "id=" EMC1414_TEST_ID ",address=0x70" | ||
480 | + }; | ||
481 | + add_qi2c_address(&opts, &(QI2CAddress) { 0x70 }); | ||
482 | + | ||
483 | + qos_node_create_driver("emc1414", i2c_device_create); | ||
484 | + qos_node_consumes("emc1414", "i2c-bus", &opts); | ||
485 | + | ||
486 | + qos_add_test("tx-rx", "emc1414", send_and_receive, NULL); | ||
487 | +} | ||
488 | +libqos_init(emc1414_register_nodes); | ||
489 | diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig | ||
490 | index XXXXXXX..XXXXXXX 100644 | ||
491 | --- a/hw/arm/Kconfig | ||
492 | +++ b/hw/arm/Kconfig | ||
493 | @@ -XXX,XX +XXX,XX @@ config ASPEED_SOC | ||
494 | select SSI_M25P80 | ||
495 | select TMP105 | ||
496 | select TMP421 | ||
497 | + select EMC141X | ||
498 | select UNIMP | ||
499 | select LED | ||
500 | |||
501 | diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig | ||
502 | index XXXXXXX..XXXXXXX 100644 | ||
503 | --- a/hw/misc/Kconfig | ||
504 | +++ b/hw/misc/Kconfig | ||
505 | @@ -XXX,XX +XXX,XX @@ config TMP421 | ||
506 | bool | ||
507 | depends on I2C | ||
508 | |||
509 | +config EMC141X | ||
510 | + bool | ||
511 | + depends on I2C | ||
512 | + | ||
513 | config ISA_DEBUG | ||
514 | bool | ||
515 | depends on ISA_BUS | ||
516 | diff --git a/hw/misc/meson.build b/hw/misc/meson.build | ||
517 | index XXXXXXX..XXXXXXX 100644 | ||
518 | --- a/hw/misc/meson.build | ||
519 | +++ b/hw/misc/meson.build | ||
520 | @@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_PCI_TESTDEV', if_true: files('pci-testdev.c')) | ||
521 | softmmu_ss.add(when: 'CONFIG_SGA', if_true: files('sga.c')) | ||
522 | softmmu_ss.add(when: 'CONFIG_TMP105', if_true: files('tmp105.c')) | ||
523 | softmmu_ss.add(when: 'CONFIG_TMP421', if_true: files('tmp421.c')) | ||
524 | +softmmu_ss.add(when: 'CONFIG_EMC141X', if_true: files('emc141x.c')) | ||
525 | softmmu_ss.add(when: 'CONFIG_UNIMP', if_true: files('unimp.c')) | ||
526 | softmmu_ss.add(when: 'CONFIG_EMPTY_SLOT', if_true: files('empty_slot.c')) | ||
527 | softmmu_ss.add(when: 'CONFIG_LED', if_true: files('led.c')) | ||
528 | diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build | ||
529 | index XXXXXXX..XXXXXXX 100644 | ||
530 | --- a/tests/qtest/meson.build | ||
531 | +++ b/tests/qtest/meson.build | ||
532 | @@ -XXX,XX +XXX,XX @@ qos_test_ss.add( | ||
533 | 'sdhci-test.c', | ||
534 | 'spapr-phb-test.c', | ||
535 | 'tmp105-test.c', | ||
536 | + 'emc141x-test.c', | ||
537 | 'usb-hcd-ohci-test.c', | ||
538 | 'virtio-test.c', | ||
539 | 'virtio-blk-test.c', | ||
540 | -- | 166 | -- |
541 | 2.26.2 | 167 | 2.41.0 |
542 | 168 | ||
543 | 169 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
1 | 2 | ||
3 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
4 | Reviewed-by: Cédric Le Goater <clg@kaod.org> | ||
5 | Signed-off-by: Cédric Le Goater <clg@kaod.org> | ||
6 | --- | ||
7 | hw/arm/aspeed_soc_common.c | 11 +++++++++++ | ||
8 | 1 file changed, 11 insertions(+) | ||
9 | |||
10 | diff --git a/hw/arm/aspeed_soc_common.c b/hw/arm/aspeed_soc_common.c | ||
11 | index XXXXXXX..XXXXXXX 100644 | ||
12 | --- a/hw/arm/aspeed_soc_common.c | ||
13 | +++ b/hw/arm/aspeed_soc_common.c | ||
14 | @@ -XXX,XX +XXX,XX @@ void aspeed_mmio_map_unimplemented(AspeedSoCState *s, SysBusDevice *dev, | ||
15 | sysbus_mmio_get_region(dev, 0), -1000); | ||
16 | } | ||
17 | |||
18 | +static void aspeed_soc_realize(DeviceState *dev, Error **errp) | ||
19 | +{ | ||
20 | + AspeedSoCState *s = ASPEED_SOC(dev); | ||
21 | + | ||
22 | + if (!s->memory) { | ||
23 | + error_setg(errp, "'memory' link is not set"); | ||
24 | + return; | ||
25 | + } | ||
26 | +} | ||
27 | + | ||
28 | static Property aspeed_soc_properties[] = { | ||
29 | DEFINE_PROP_LINK("dram", AspeedSoCState, dram_mr, TYPE_MEMORY_REGION, | ||
30 | MemoryRegion *), | ||
31 | @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_class_init(ObjectClass *oc, void *data) | ||
32 | { | ||
33 | DeviceClass *dc = DEVICE_CLASS(oc); | ||
34 | |||
35 | + dc->realize = aspeed_soc_realize; | ||
36 | device_class_set_props(dc, aspeed_soc_properties); | ||
37 | } | ||
38 | |||
39 | -- | ||
40 | 2.41.0 | ||
41 | |||
42 | diff view generated by jsdifflib |
1 | From: John Wang <wangzhiqiang.bj@bytedance.com> | 1 | From: Philippe Mathieu-Daudé <philmd@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Add an eeprom device and fill it with fru | 3 | The v7-M core is specific to the Aspeed 10x0 series, |
4 | information | 4 | remove it from the common AspeedSoCState. |
5 | 5 | ||
6 | $ ipmitool fru print 0 | 6 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
7 | Product Manufacturer : Bytedance | ||
8 | Product Name : G220A | ||
9 | |||
10 | Signed-off-by: John Wang <wangzhiqiang.bj@bytedance.com> | ||
11 | Reviewed-by: Cédric Le Goater <clg@kaod.org> | 7 | Reviewed-by: Cédric Le Goater <clg@kaod.org> |
12 | Message-Id: <20201210103607.556-1-wangzhiqiang.bj@bytedance.com> | ||
13 | Signed-off-by: Cédric Le Goater <clg@kaod.org> | 8 | Signed-off-by: Cédric Le Goater <clg@kaod.org> |
14 | --- | 9 | --- |
15 | hw/arm/aspeed.c | 12 ++++++++++++ | 10 | include/hw/arm/aspeed_soc.h | 5 ++--- |
16 | 1 file changed, 12 insertions(+) | 11 | hw/arm/aspeed_ast10x0.c | 27 +++++++++++++++------------ |
12 | hw/arm/fby35.c | 13 ++++++++----- | ||
13 | 3 files changed, 25 insertions(+), 20 deletions(-) | ||
17 | 14 | ||
18 | diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c | 15 | diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h |
19 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
20 | --- a/hw/arm/aspeed.c | 17 | --- a/include/hw/arm/aspeed_soc.h |
21 | +++ b/hw/arm/aspeed.c | 18 | +++ b/include/hw/arm/aspeed_soc.h |
22 | @@ -XXX,XX +XXX,XX @@ static void g220a_bmc_i2c_init(AspeedMachineState *bmc) | 19 | @@ -XXX,XX +XXX,XX @@ |
23 | object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort); | 20 | #define ASPEED_JTAG_NUM 2 |
24 | object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort); | 21 | |
25 | object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort); | 22 | struct AspeedSoCState { |
23 | - /*< private >*/ | ||
24 | DeviceState parent; | ||
25 | |||
26 | - /*< public >*/ | ||
27 | ARMCPU cpu[ASPEED_CPUS_NUM]; | ||
28 | A15MPPrivState a7mpcore; | ||
29 | - ARMv7MState armv7m; | ||
30 | MemoryRegion *memory; | ||
31 | MemoryRegion *dram_mr; | ||
32 | MemoryRegion dram_container; | ||
33 | @@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_SIMPLE_TYPE(Aspeed2600SoCState, ASPEED2600_SOC) | ||
34 | |||
35 | struct Aspeed10x0SoCState { | ||
36 | AspeedSoCState parent; | ||
26 | + | 37 | + |
27 | + static uint8_t eeprom_buf[2 * 1024] = { | 38 | + ARMv7MState armv7m; |
28 | + 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0xfe, | 39 | }; |
29 | + 0x01, 0x06, 0x00, 0xc9, 0x42, 0x79, 0x74, 0x65, | 40 | |
30 | + 0x64, 0x61, 0x6e, 0x63, 0x65, 0xc5, 0x47, 0x32, | 41 | #define TYPE_ASPEED10X0_SOC "aspeed10x0-soc" |
31 | + 0x32, 0x30, 0x41, 0xc4, 0x41, 0x41, 0x42, 0x42, | 42 | diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c |
32 | + 0xc4, 0x43, 0x43, 0x44, 0x44, 0xc4, 0x45, 0x45, | 43 | index XXXXXXX..XXXXXXX 100644 |
33 | + 0x46, 0x46, 0xc4, 0x48, 0x48, 0x47, 0x47, 0xc1, | 44 | --- a/hw/arm/aspeed_ast10x0.c |
34 | + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa7, | 45 | +++ b/hw/arm/aspeed_ast10x0.c |
35 | + }; | 46 | @@ -XXX,XX +XXX,XX @@ static const int aspeed_soc_ast1030_irqmap[] = { |
36 | + smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 4), 0x57, | 47 | |
37 | + eeprom_buf); | 48 | static qemu_irq aspeed_soc_ast1030_get_irq(AspeedSoCState *s, int dev) |
49 | { | ||
50 | + Aspeed10x0SoCState *a = ASPEED10X0_SOC(s); | ||
51 | AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); | ||
52 | |||
53 | - return qdev_get_gpio_in(DEVICE(&s->armv7m), sc->irqmap[dev]); | ||
54 | + return qdev_get_gpio_in(DEVICE(&a->armv7m), sc->irqmap[dev]); | ||
38 | } | 55 | } |
39 | 56 | ||
40 | static bool aspeed_get_mmio_exec(Object *obj, Error **errp) | 57 | static void aspeed_soc_ast1030_init(Object *obj) |
58 | { | ||
59 | + Aspeed10x0SoCState *a = ASPEED10X0_SOC(obj); | ||
60 | AspeedSoCState *s = ASPEED_SOC(obj); | ||
61 | AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); | ||
62 | char socname[8]; | ||
63 | @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast1030_init(Object *obj) | ||
64 | g_assert_not_reached(); | ||
65 | } | ||
66 | |||
67 | - object_initialize_child(obj, "armv7m", &s->armv7m, TYPE_ARMV7M); | ||
68 | + object_initialize_child(obj, "armv7m", &a->armv7m, TYPE_ARMV7M); | ||
69 | |||
70 | s->sysclk = qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0); | ||
71 | |||
72 | @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast1030_init(Object *obj) | ||
73 | |||
74 | static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp) | ||
75 | { | ||
76 | + Aspeed10x0SoCState *a = ASPEED10X0_SOC(dev_soc); | ||
77 | AspeedSoCState *s = ASPEED_SOC(dev_soc); | ||
78 | AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); | ||
79 | DeviceState *armv7m; | ||
80 | @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp) | ||
81 | 0x40000); | ||
82 | |||
83 | /* AST1030 CPU Core */ | ||
84 | - armv7m = DEVICE(&s->armv7m); | ||
85 | + armv7m = DEVICE(&a->armv7m); | ||
86 | qdev_prop_set_uint32(armv7m, "num-irq", 256); | ||
87 | qdev_prop_set_string(armv7m, "cpu-type", sc->cpu_type); | ||
88 | qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk); | ||
89 | - object_property_set_link(OBJECT(&s->armv7m), "memory", | ||
90 | + object_property_set_link(OBJECT(&a->armv7m), "memory", | ||
91 | OBJECT(s->memory), &error_abort); | ||
92 | - sysbus_realize(SYS_BUS_DEVICE(&s->armv7m), &error_abort); | ||
93 | + sysbus_realize(SYS_BUS_DEVICE(&a->armv7m), &error_abort); | ||
94 | |||
95 | /* Internal SRAM */ | ||
96 | sram_name = g_strdup_printf("aspeed.sram.%d", | ||
97 | - CPU(s->armv7m.cpu)->cpu_index); | ||
98 | + CPU(a->armv7m.cpu)->cpu_index); | ||
99 | memory_region_init_ram(&s->sram, OBJECT(s), sram_name, sc->sram_size, &err); | ||
100 | if (err != NULL) { | ||
101 | error_propagate(errp, err); | ||
102 | @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp) | ||
103 | } | ||
104 | aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_DEV_I2C]); | ||
105 | for (i = 0; i < ASPEED_I2C_GET_CLASS(&s->i2c)->num_busses; i++) { | ||
106 | - qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->armv7m), | ||
107 | + qemu_irq irq = qdev_get_gpio_in(DEVICE(&a->armv7m), | ||
108 | sc->irqmap[ASPEED_DEV_I2C] + i); | ||
109 | /* The AST1030 I2C controller has one IRQ per bus. */ | ||
110 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c.busses[i]), 0, irq); | ||
111 | @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp) | ||
112 | } | ||
113 | aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i3c), 0, sc->memmap[ASPEED_DEV_I3C]); | ||
114 | for (i = 0; i < ASPEED_I3C_NR_DEVICES; i++) { | ||
115 | - qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->armv7m), | ||
116 | + qemu_irq irq = qdev_get_gpio_in(DEVICE(&a->armv7m), | ||
117 | sc->irqmap[ASPEED_DEV_I3C] + i); | ||
118 | /* The AST1030 I3C controller has one IRQ per bus. */ | ||
119 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->i3c.devices[i]), 0, irq); | ||
120 | @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp) | ||
121 | * On the AST1030 LPC subdevice IRQs are connected straight to the GIC. | ||
122 | */ | ||
123 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_1, | ||
124 | - qdev_get_gpio_in(DEVICE(&s->armv7m), | ||
125 | + qdev_get_gpio_in(DEVICE(&a->armv7m), | ||
126 | sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_1)); | ||
127 | |||
128 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_2, | ||
129 | - qdev_get_gpio_in(DEVICE(&s->armv7m), | ||
130 | + qdev_get_gpio_in(DEVICE(&a->armv7m), | ||
131 | sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_2)); | ||
132 | |||
133 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_3, | ||
134 | - qdev_get_gpio_in(DEVICE(&s->armv7m), | ||
135 | + qdev_get_gpio_in(DEVICE(&a->armv7m), | ||
136 | sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_3)); | ||
137 | |||
138 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_4, | ||
139 | - qdev_get_gpio_in(DEVICE(&s->armv7m), | ||
140 | + qdev_get_gpio_in(DEVICE(&a->armv7m), | ||
141 | sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_4)); | ||
142 | |||
143 | /* UART */ | ||
144 | diff --git a/hw/arm/fby35.c b/hw/arm/fby35.c | ||
145 | index XXXXXXX..XXXXXXX 100644 | ||
146 | --- a/hw/arm/fby35.c | ||
147 | +++ b/hw/arm/fby35.c | ||
148 | @@ -XXX,XX +XXX,XX @@ struct Fby35State { | ||
149 | Clock *bic_sysclk; | ||
150 | |||
151 | AspeedSoCState bmc; | ||
152 | - AspeedSoCState bic; | ||
153 | + Aspeed10x0SoCState bic; | ||
154 | |||
155 | bool mmio_exec; | ||
156 | }; | ||
157 | @@ -XXX,XX +XXX,XX @@ static void fby35_bmc_init(Fby35State *s) | ||
158 | |||
159 | static void fby35_bic_init(Fby35State *s) | ||
160 | { | ||
161 | + AspeedSoCState *soc; | ||
162 | + | ||
163 | s->bic_sysclk = clock_new(OBJECT(s), "SYSCLK"); | ||
164 | clock_set_hz(s->bic_sysclk, 200000000ULL); | ||
165 | |||
166 | object_initialize_child(OBJECT(s), "bic", &s->bic, "ast1030-a1"); | ||
167 | + soc = ASPEED_SOC(&s->bic); | ||
168 | |||
169 | memory_region_init(&s->bic_memory, OBJECT(&s->bic), "bic-memory", | ||
170 | UINT64_MAX); | ||
171 | @@ -XXX,XX +XXX,XX @@ static void fby35_bic_init(Fby35State *s) | ||
172 | qdev_connect_clock_in(DEVICE(&s->bic), "sysclk", s->bic_sysclk); | ||
173 | object_property_set_link(OBJECT(&s->bic), "memory", OBJECT(&s->bic_memory), | ||
174 | &error_abort); | ||
175 | - aspeed_soc_uart_set_chr(&s->bic, ASPEED_DEV_UART5, serial_hd(1)); | ||
176 | + aspeed_soc_uart_set_chr(soc, ASPEED_DEV_UART5, serial_hd(1)); | ||
177 | qdev_realize(DEVICE(&s->bic), NULL, &error_abort); | ||
178 | |||
179 | - aspeed_board_init_flashes(&s->bic.fmc, "sst25vf032b", 2, 2); | ||
180 | - aspeed_board_init_flashes(&s->bic.spi[0], "sst25vf032b", 2, 4); | ||
181 | - aspeed_board_init_flashes(&s->bic.spi[1], "sst25vf032b", 2, 6); | ||
182 | + aspeed_board_init_flashes(&soc->fmc, "sst25vf032b", 2, 2); | ||
183 | + aspeed_board_init_flashes(&soc->spi[0], "sst25vf032b", 2, 4); | ||
184 | + aspeed_board_init_flashes(&soc->spi[1], "sst25vf032b", 2, 6); | ||
185 | } | ||
186 | |||
187 | static void fby35_init(MachineState *machine) | ||
41 | -- | 188 | -- |
42 | 2.26.2 | 189 | 2.41.0 |
43 | 190 | ||
44 | 191 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | 1 | From: Philippe Mathieu-Daudé <philmd@linaro.org> | |
2 | |||
3 | The v7-A cluster is specific to the Aspeed 2600 series, | ||
4 | remove it from the common AspeedSoCState. | ||
5 | |||
6 | The ARM cores belong to the MP cluster, but the array | ||
7 | is currently used by TYPE_ASPEED2600_SOC. We'll clean | ||
8 | that soon, but for now keep it in Aspeed2600SoCState. | ||
9 | |||
10 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
11 | Reviewed-by: Cédric Le Goater <clg@kaod.org> | ||
12 | Signed-off-by: Cédric Le Goater <clg@kaod.org> | ||
13 | --- | ||
14 | include/hw/arm/aspeed_soc.h | 4 ++- | ||
15 | hw/arm/aspeed_ast2600.c | 49 ++++++++++++++++++++----------------- | ||
16 | hw/arm/fby35.c | 14 ++++++----- | ||
17 | 3 files changed, 37 insertions(+), 30 deletions(-) | ||
18 | |||
19 | diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h | ||
20 | index XXXXXXX..XXXXXXX 100644 | ||
21 | --- a/include/hw/arm/aspeed_soc.h | ||
22 | +++ b/include/hw/arm/aspeed_soc.h | ||
23 | @@ -XXX,XX +XXX,XX @@ struct AspeedSoCState { | ||
24 | DeviceState parent; | ||
25 | |||
26 | ARMCPU cpu[ASPEED_CPUS_NUM]; | ||
27 | - A15MPPrivState a7mpcore; | ||
28 | MemoryRegion *memory; | ||
29 | MemoryRegion *dram_mr; | ||
30 | MemoryRegion dram_container; | ||
31 | @@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_SIMPLE_TYPE(Aspeed2400SoCState, ASPEED2400_SOC) | ||
32 | |||
33 | struct Aspeed2600SoCState { | ||
34 | AspeedSoCState parent; | ||
35 | + | ||
36 | + A15MPPrivState a7mpcore; | ||
37 | + ARMCPU cpu[ASPEED_CPUS_NUM]; /* XXX belong to a7mpcore */ | ||
38 | }; | ||
39 | |||
40 | #define TYPE_ASPEED2600_SOC "aspeed2600-soc" | ||
41 | diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c | ||
42 | index XXXXXXX..XXXXXXX 100644 | ||
43 | --- a/hw/arm/aspeed_ast2600.c | ||
44 | +++ b/hw/arm/aspeed_ast2600.c | ||
45 | @@ -XXX,XX +XXX,XX @@ static const int aspeed_soc_ast2600_irqmap[] = { | ||
46 | |||
47 | static qemu_irq aspeed_soc_ast2600_get_irq(AspeedSoCState *s, int dev) | ||
48 | { | ||
49 | + Aspeed2600SoCState *a = ASPEED2600_SOC(s); | ||
50 | AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); | ||
51 | |||
52 | - return qdev_get_gpio_in(DEVICE(&s->a7mpcore), sc->irqmap[dev]); | ||
53 | + return qdev_get_gpio_in(DEVICE(&a->a7mpcore), sc->irqmap[dev]); | ||
54 | } | ||
55 | |||
56 | static void aspeed_soc_ast2600_init(Object *obj) | ||
57 | { | ||
58 | + Aspeed2600SoCState *a = ASPEED2600_SOC(obj); | ||
59 | AspeedSoCState *s = ASPEED_SOC(obj); | ||
60 | AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); | ||
61 | int i; | ||
62 | @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2600_init(Object *obj) | ||
63 | } | ||
64 | |||
65 | for (i = 0; i < sc->num_cpus; i++) { | ||
66 | - object_initialize_child(obj, "cpu[*]", &s->cpu[i], sc->cpu_type); | ||
67 | + object_initialize_child(obj, "cpu[*]", &a->cpu[i], sc->cpu_type); | ||
68 | } | ||
69 | |||
70 | snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname); | ||
71 | @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2600_init(Object *obj) | ||
72 | object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu), | ||
73 | "hw-prot-key"); | ||
74 | |||
75 | - object_initialize_child(obj, "a7mpcore", &s->a7mpcore, | ||
76 | + object_initialize_child(obj, "a7mpcore", &a->a7mpcore, | ||
77 | TYPE_A15MPCORE_PRIV); | ||
78 | |||
79 | object_initialize_child(obj, "rtc", &s->rtc, TYPE_ASPEED_RTC); | ||
80 | @@ -XXX,XX +XXX,XX @@ static uint64_t aspeed_calc_affinity(int cpu) | ||
81 | static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp) | ||
82 | { | ||
83 | int i; | ||
84 | + Aspeed2600SoCState *a = ASPEED2600_SOC(dev); | ||
85 | AspeedSoCState *s = ASPEED_SOC(dev); | ||
86 | AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); | ||
87 | Error *err = NULL; | ||
88 | @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp) | ||
89 | /* CPU */ | ||
90 | for (i = 0; i < sc->num_cpus; i++) { | ||
91 | if (sc->num_cpus > 1) { | ||
92 | - object_property_set_int(OBJECT(&s->cpu[i]), "reset-cbar", | ||
93 | + object_property_set_int(OBJECT(&a->cpu[i]), "reset-cbar", | ||
94 | ASPEED_A7MPCORE_ADDR, &error_abort); | ||
95 | } | ||
96 | - object_property_set_int(OBJECT(&s->cpu[i]), "mp-affinity", | ||
97 | + object_property_set_int(OBJECT(&a->cpu[i]), "mp-affinity", | ||
98 | aspeed_calc_affinity(i), &error_abort); | ||
99 | |||
100 | - object_property_set_int(OBJECT(&s->cpu[i]), "cntfrq", 1125000000, | ||
101 | + object_property_set_int(OBJECT(&a->cpu[i]), "cntfrq", 1125000000, | ||
102 | &error_abort); | ||
103 | - object_property_set_bool(OBJECT(&s->cpu[i]), "neon", false, | ||
104 | + object_property_set_bool(OBJECT(&a->cpu[i]), "neon", false, | ||
105 | &error_abort); | ||
106 | - object_property_set_bool(OBJECT(&s->cpu[i]), "vfp-d32", false, | ||
107 | + object_property_set_bool(OBJECT(&a->cpu[i]), "vfp-d32", false, | ||
108 | &error_abort); | ||
109 | - object_property_set_link(OBJECT(&s->cpu[i]), "memory", | ||
110 | + object_property_set_link(OBJECT(&a->cpu[i]), "memory", | ||
111 | OBJECT(s->memory), &error_abort); | ||
112 | |||
113 | - if (!qdev_realize(DEVICE(&s->cpu[i]), NULL, errp)) { | ||
114 | + if (!qdev_realize(DEVICE(&a->cpu[i]), NULL, errp)) { | ||
115 | return; | ||
116 | } | ||
117 | } | ||
118 | |||
119 | /* A7MPCORE */ | ||
120 | - object_property_set_int(OBJECT(&s->a7mpcore), "num-cpu", sc->num_cpus, | ||
121 | + object_property_set_int(OBJECT(&a->a7mpcore), "num-cpu", sc->num_cpus, | ||
122 | &error_abort); | ||
123 | - object_property_set_int(OBJECT(&s->a7mpcore), "num-irq", | ||
124 | + object_property_set_int(OBJECT(&a->a7mpcore), "num-irq", | ||
125 | ROUND_UP(AST2600_MAX_IRQ + GIC_INTERNAL, 32), | ||
126 | &error_abort); | ||
127 | |||
128 | - sysbus_realize(SYS_BUS_DEVICE(&s->a7mpcore), &error_abort); | ||
129 | - aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->a7mpcore), 0, ASPEED_A7MPCORE_ADDR); | ||
130 | + sysbus_realize(SYS_BUS_DEVICE(&a->a7mpcore), &error_abort); | ||
131 | + aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->a7mpcore), 0, ASPEED_A7MPCORE_ADDR); | ||
132 | |||
133 | for (i = 0; i < sc->num_cpus; i++) { | ||
134 | - SysBusDevice *sbd = SYS_BUS_DEVICE(&s->a7mpcore); | ||
135 | - DeviceState *d = DEVICE(&s->cpu[i]); | ||
136 | + SysBusDevice *sbd = SYS_BUS_DEVICE(&a->a7mpcore); | ||
137 | + DeviceState *d = DEVICE(&a->cpu[i]); | ||
138 | |||
139 | irq = qdev_get_gpio_in(d, ARM_CPU_IRQ); | ||
140 | sysbus_connect_irq(sbd, i, irq); | ||
141 | @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp) | ||
142 | } | ||
143 | |||
144 | /* SRAM */ | ||
145 | - sram_name = g_strdup_printf("aspeed.sram.%d", CPU(&s->cpu[0])->cpu_index); | ||
146 | + sram_name = g_strdup_printf("aspeed.sram.%d", CPU(&a->cpu[0])->cpu_index); | ||
147 | memory_region_init_ram(&s->sram, OBJECT(s), sram_name, sc->sram_size, &err); | ||
148 | if (err) { | ||
149 | error_propagate(errp, err); | ||
150 | @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp) | ||
151 | } | ||
152 | aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_DEV_I2C]); | ||
153 | for (i = 0; i < ASPEED_I2C_GET_CLASS(&s->i2c)->num_busses; i++) { | ||
154 | - irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), | ||
155 | + irq = qdev_get_gpio_in(DEVICE(&a->a7mpcore), | ||
156 | sc->irqmap[ASPEED_DEV_I2C] + i); | ||
157 | /* The AST2600 I2C controller has one IRQ per bus. */ | ||
158 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c.busses[i]), 0, irq); | ||
159 | @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp) | ||
160 | * offset 0. | ||
161 | */ | ||
162 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_1, | ||
163 | - qdev_get_gpio_in(DEVICE(&s->a7mpcore), | ||
164 | + qdev_get_gpio_in(DEVICE(&a->a7mpcore), | ||
165 | sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_1)); | ||
166 | |||
167 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_2, | ||
168 | - qdev_get_gpio_in(DEVICE(&s->a7mpcore), | ||
169 | + qdev_get_gpio_in(DEVICE(&a->a7mpcore), | ||
170 | sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_2)); | ||
171 | |||
172 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_3, | ||
173 | - qdev_get_gpio_in(DEVICE(&s->a7mpcore), | ||
174 | + qdev_get_gpio_in(DEVICE(&a->a7mpcore), | ||
175 | sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_3)); | ||
176 | |||
177 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_4, | ||
178 | - qdev_get_gpio_in(DEVICE(&s->a7mpcore), | ||
179 | + qdev_get_gpio_in(DEVICE(&a->a7mpcore), | ||
180 | sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_4)); | ||
181 | |||
182 | /* HACE */ | ||
183 | @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp) | ||
184 | } | ||
185 | aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i3c), 0, sc->memmap[ASPEED_DEV_I3C]); | ||
186 | for (i = 0; i < ASPEED_I3C_NR_DEVICES; i++) { | ||
187 | - irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), | ||
188 | + irq = qdev_get_gpio_in(DEVICE(&a->a7mpcore), | ||
189 | sc->irqmap[ASPEED_DEV_I3C] + i); | ||
190 | /* The AST2600 I3C controller has one IRQ per bus. */ | ||
191 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->i3c.devices[i]), 0, irq); | ||
192 | diff --git a/hw/arm/fby35.c b/hw/arm/fby35.c | ||
193 | index XXXXXXX..XXXXXXX 100644 | ||
194 | --- a/hw/arm/fby35.c | ||
195 | +++ b/hw/arm/fby35.c | ||
196 | @@ -XXX,XX +XXX,XX @@ struct Fby35State { | ||
197 | MemoryRegion bic_memory; | ||
198 | Clock *bic_sysclk; | ||
199 | |||
200 | - AspeedSoCState bmc; | ||
201 | + Aspeed2600SoCState bmc; | ||
202 | Aspeed10x0SoCState bic; | ||
203 | |||
204 | bool mmio_exec; | ||
205 | @@ -XXX,XX +XXX,XX @@ static void fby35_bmc_write_boot_rom(DriveInfo *dinfo, MemoryRegion *mr, | ||
206 | |||
207 | static void fby35_bmc_init(Fby35State *s) | ||
208 | { | ||
209 | + AspeedSoCState *soc; | ||
210 | + | ||
211 | object_initialize_child(OBJECT(s), "bmc", &s->bmc, "ast2600-a3"); | ||
212 | + soc = ASPEED_SOC(&s->bmc); | ||
213 | |||
214 | memory_region_init(&s->bmc_memory, OBJECT(&s->bmc), "bmc-memory", | ||
215 | UINT64_MAX); | ||
216 | @@ -XXX,XX +XXX,XX @@ static void fby35_bmc_init(Fby35State *s) | ||
217 | &error_abort); | ||
218 | object_property_set_int(OBJECT(&s->bmc), "hw-strap2", 0x00000003, | ||
219 | &error_abort); | ||
220 | - aspeed_soc_uart_set_chr(&s->bmc, ASPEED_DEV_UART5, serial_hd(0)); | ||
221 | + aspeed_soc_uart_set_chr(soc, ASPEED_DEV_UART5, serial_hd(0)); | ||
222 | qdev_realize(DEVICE(&s->bmc), NULL, &error_abort); | ||
223 | |||
224 | - aspeed_board_init_flashes(&s->bmc.fmc, "n25q00", 2, 0); | ||
225 | + aspeed_board_init_flashes(&soc->fmc, "n25q00", 2, 0); | ||
226 | |||
227 | /* Install first FMC flash content as a boot rom. */ | ||
228 | if (!s->mmio_exec) { | ||
229 | DriveInfo *mtd0 = drive_get(IF_MTD, 0, 0); | ||
230 | |||
231 | if (mtd0) { | ||
232 | - AspeedSoCState *bmc = &s->bmc; | ||
233 | - uint64_t rom_size = memory_region_size(&bmc->spi_boot); | ||
234 | + uint64_t rom_size = memory_region_size(&soc->spi_boot); | ||
235 | |||
236 | memory_region_init_rom(&s->bmc_boot_rom, NULL, "aspeed.boot_rom", | ||
237 | rom_size, &error_abort); | ||
238 | - memory_region_add_subregion_overlap(&bmc->spi_boot_container, 0, | ||
239 | + memory_region_add_subregion_overlap(&soc->spi_boot_container, 0, | ||
240 | &s->bmc_boot_rom, 1); | ||
241 | |||
242 | fby35_bmc_write_boot_rom(mtd0, &s->bmc_boot_rom, | ||
243 | -- | ||
244 | 2.41.0 | ||
245 | |||
246 | diff view generated by jsdifflib |
1 | The controller can be configured to disable or enable address and data | 1 | From: Philippe Mathieu-Daudé <philmd@linaro.org> |
---|---|---|---|
2 | byte lanes when issuing commands. This is useful in read command mode | ||
3 | to send SPI NOR commands that don't have an address space, such as | ||
4 | RDID. It's a good way to have a unified read operation for registers | ||
5 | and flash contents accesses. | ||
6 | 2 | ||
7 | A new SPI driver proposed by Aspeed makes use of this feature. Add | 3 | The ARM array and VIC peripheral are only used by the |
8 | support for address lanes to start with. We will do the same for the | 4 | 2400 series, remove them from the common AspeedSoCState. |
9 | data lanes if they are controlled one day. | ||
10 | 5 | ||
11 | Cc: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com> | 6 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
12 | Signed-off-by: Cédric Le Goater <clg@kaod.org> | 7 | Reviewed-by: Cédric Le Goater <clg@kaod.org> |
13 | Reviewed-by: Joel Stanley <joel@jms.id.au> | ||
14 | Message-Id: <20201120161547.740806-2-clg@kaod.org> | ||
15 | Signed-off-by: Cédric Le Goater <clg@kaod.org> | 8 | Signed-off-by: Cédric Le Goater <clg@kaod.org> |
16 | --- | 9 | --- |
17 | hw/ssi/aspeed_smc.c | 25 ++++++++++++++++++------- | 10 | include/hw/arm/aspeed_soc.h | 5 +++-- |
18 | 1 file changed, 18 insertions(+), 7 deletions(-) | 11 | hw/arm/{aspeed_soc.c => aspeed_ast2400.c} | 27 +++++++++++++---------- |
12 | hw/arm/meson.build | 2 +- | ||
13 | 3 files changed, 19 insertions(+), 15 deletions(-) | ||
14 | rename hw/arm/{aspeed_soc.c => aspeed_ast2400.c} (95%) | ||
19 | 15 | ||
20 | diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c | 16 | diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h |
21 | index XXXXXXX..XXXXXXX 100644 | 17 | index XXXXXXX..XXXXXXX 100644 |
22 | --- a/hw/ssi/aspeed_smc.c | 18 | --- a/include/hw/arm/aspeed_soc.h |
23 | +++ b/hw/ssi/aspeed_smc.c | 19 | +++ b/include/hw/arm/aspeed_soc.h |
24 | @@ -XXX,XX +XXX,XX @@ | 20 | @@ -XXX,XX +XXX,XX @@ |
25 | #define INTR_CTRL_CMD_ABORT_EN (1 << 2) | 21 | struct AspeedSoCState { |
26 | #define INTR_CTRL_WRITE_PROTECT_EN (1 << 1) | 22 | DeviceState parent; |
27 | 23 | ||
28 | +/* Command Control Register */ | 24 | - ARMCPU cpu[ASPEED_CPUS_NUM]; |
29 | +#define R_CE_CMD_CTRL (0x0C / 4) | 25 | MemoryRegion *memory; |
30 | +#define CTRL_ADDR_BYTE0_DISABLE_SHIFT 4 | 26 | MemoryRegion *dram_mr; |
31 | +#define CTRL_DATA_BYTE0_DISABLE_SHIFT 0 | 27 | MemoryRegion dram_container; |
28 | MemoryRegion sram; | ||
29 | MemoryRegion spi_boot_container; | ||
30 | MemoryRegion spi_boot; | ||
31 | - AspeedVICState vic; | ||
32 | AspeedRtcState rtc; | ||
33 | AspeedTimerCtrlState timerctrl; | ||
34 | AspeedI2CState i2c; | ||
35 | @@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_TYPE(AspeedSoCState, AspeedSoCClass, ASPEED_SOC) | ||
36 | |||
37 | struct Aspeed2400SoCState { | ||
38 | AspeedSoCState parent; | ||
32 | + | 39 | + |
33 | +#define aspeed_smc_addr_byte_enabled(s, i) \ | 40 | + ARMCPU cpu[ASPEED_CPUS_NUM]; |
34 | + (!((s)->regs[R_CE_CMD_CTRL] & (1 << (CTRL_ADDR_BYTE0_DISABLE_SHIFT + (i))))) | 41 | + AspeedVICState vic; |
35 | +#define aspeed_smc_data_byte_enabled(s, i) \ | 42 | }; |
36 | + (!((s)->regs[R_CE_CMD_CTRL] & (1 << (CTRL_DATA_BYTE0_DISABLE_SHIFT + (i))))) | 43 | |
37 | + | 44 | #define TYPE_ASPEED2400_SOC "aspeed2400-soc" |
38 | /* CEx Control Register */ | 45 | diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_ast2400.c |
39 | #define R_CTRL0 (0x10 / 4) | 46 | similarity index 95% |
40 | #define CTRL_IO_QPI (1 << 31) | 47 | rename from hw/arm/aspeed_soc.c |
41 | @@ -XXX,XX +XXX,XX @@ static void aspeed_smc_flash_setup(AspeedSMCFlash *fl, uint32_t addr) | 48 | rename to hw/arm/aspeed_ast2400.c |
49 | index XXXXXXX..XXXXXXX 100644 | ||
50 | --- a/hw/arm/aspeed_soc.c | ||
51 | +++ b/hw/arm/aspeed_ast2400.c | ||
52 | @@ -XXX,XX +XXX,XX @@ static const int aspeed_soc_ast2400_irqmap[] = { | ||
53 | |||
54 | static qemu_irq aspeed_soc_ast2400_get_irq(AspeedSoCState *s, int dev) | ||
42 | { | 55 | { |
43 | const AspeedSMCState *s = fl->controller; | 56 | + Aspeed2400SoCState *a = ASPEED2400_SOC(s); |
44 | uint8_t cmd = aspeed_smc_flash_cmd(fl); | 57 | AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); |
45 | - int i; | 58 | |
46 | + int i = aspeed_smc_flash_is_4byte(fl) ? 4 : 3; | 59 | - return qdev_get_gpio_in(DEVICE(&s->vic), sc->irqmap[dev]); |
47 | 60 | + return qdev_get_gpio_in(DEVICE(&a->vic), sc->irqmap[dev]); | |
48 | /* Flash access can not exceed CS segment */ | 61 | } |
49 | addr = aspeed_smc_check_segment_addr(fl, addr); | 62 | |
50 | 63 | static void aspeed_ast2400_soc_init(Object *obj) | |
51 | ssi_transfer(s->spi, cmd); | 64 | { |
52 | - | 65 | + Aspeed2400SoCState *a = ASPEED2400_SOC(obj); |
53 | - if (aspeed_smc_flash_is_4byte(fl)) { | 66 | AspeedSoCState *s = ASPEED_SOC(obj); |
54 | - ssi_transfer(s->spi, (addr >> 24) & 0xff); | 67 | AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); |
55 | + while (i--) { | 68 | int i; |
56 | + if (aspeed_smc_addr_byte_enabled(s, i)) { | 69 | @@ -XXX,XX +XXX,XX @@ static void aspeed_ast2400_soc_init(Object *obj) |
57 | + ssi_transfer(s->spi, (addr >> (i * 8)) & 0xff); | ||
58 | + } | ||
59 | } | 70 | } |
60 | - ssi_transfer(s->spi, (addr >> 16) & 0xff); | 71 | |
61 | - ssi_transfer(s->spi, (addr >> 8) & 0xff); | 72 | for (i = 0; i < sc->num_cpus; i++) { |
62 | - ssi_transfer(s->spi, (addr & 0xff)); | 73 | - object_initialize_child(obj, "cpu[*]", &s->cpu[i], sc->cpu_type); |
63 | 74 | + object_initialize_child(obj, "cpu[*]", &a->cpu[i], sc->cpu_type); | |
64 | /* | 75 | } |
65 | * Use fake transfers to model dummy bytes. The value should | 76 | |
66 | @@ -XXX,XX +XXX,XX @@ static uint64_t aspeed_smc_read(void *opaque, hwaddr addr, unsigned int size) | 77 | snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname); |
67 | (addr >= s->r_timings && | 78 | @@ -XXX,XX +XXX,XX @@ static void aspeed_ast2400_soc_init(Object *obj) |
68 | addr < s->r_timings + s->ctrl->nregs_timings) || | 79 | object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu), |
69 | addr == s->r_ce_ctrl || | 80 | "hw-prot-key"); |
70 | + addr == R_CE_CMD_CTRL || | 81 | |
71 | addr == R_INTR_CTRL || | 82 | - object_initialize_child(obj, "vic", &s->vic, TYPE_ASPEED_VIC); |
72 | addr == R_DUMMY_DATA || | 83 | + object_initialize_child(obj, "vic", &a->vic, TYPE_ASPEED_VIC); |
73 | (s->ctrl->has_dma && addr == R_DMA_CTRL) || | 84 | |
74 | @@ -XXX,XX +XXX,XX @@ static void aspeed_smc_write(void *opaque, hwaddr addr, uint64_t data, | 85 | object_initialize_child(obj, "rtc", &s->rtc, TYPE_ASPEED_RTC); |
75 | if (value != s->regs[R_SEG_ADDR0 + cs]) { | 86 | |
76 | aspeed_smc_flash_set_segment(s, cs, value); | 87 | @@ -XXX,XX +XXX,XX @@ static void aspeed_ast2400_soc_init(Object *obj) |
88 | static void aspeed_ast2400_soc_realize(DeviceState *dev, Error **errp) | ||
89 | { | ||
90 | int i; | ||
91 | + Aspeed2400SoCState *a = ASPEED2400_SOC(dev); | ||
92 | AspeedSoCState *s = ASPEED_SOC(dev); | ||
93 | AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); | ||
94 | Error *err = NULL; | ||
95 | @@ -XXX,XX +XXX,XX @@ static void aspeed_ast2400_soc_realize(DeviceState *dev, Error **errp) | ||
96 | |||
97 | /* CPU */ | ||
98 | for (i = 0; i < sc->num_cpus; i++) { | ||
99 | - object_property_set_link(OBJECT(&s->cpu[i]), "memory", | ||
100 | + object_property_set_link(OBJECT(&a->cpu[i]), "memory", | ||
101 | OBJECT(s->memory), &error_abort); | ||
102 | - if (!qdev_realize(DEVICE(&s->cpu[i]), NULL, errp)) { | ||
103 | + if (!qdev_realize(DEVICE(&a->cpu[i]), NULL, errp)) { | ||
104 | return; | ||
77 | } | 105 | } |
78 | + } else if (addr == R_CE_CMD_CTRL) { | 106 | } |
79 | + s->regs[addr] = value & 0xff; | 107 | |
80 | } else if (addr == R_DUMMY_DATA) { | 108 | /* SRAM */ |
81 | s->regs[addr] = value & 0xff; | 109 | - sram_name = g_strdup_printf("aspeed.sram.%d", CPU(&s->cpu[0])->cpu_index); |
82 | } else if (addr == R_INTR_CTRL) { | 110 | + sram_name = g_strdup_printf("aspeed.sram.%d", CPU(&a->cpu[0])->cpu_index); |
111 | memory_region_init_ram(&s->sram, OBJECT(s), sram_name, sc->sram_size, &err); | ||
112 | if (err) { | ||
113 | error_propagate(errp, err); | ||
114 | @@ -XXX,XX +XXX,XX @@ static void aspeed_ast2400_soc_realize(DeviceState *dev, Error **errp) | ||
115 | aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_DEV_SCU]); | ||
116 | |||
117 | /* VIC */ | ||
118 | - if (!sysbus_realize(SYS_BUS_DEVICE(&s->vic), errp)) { | ||
119 | + if (!sysbus_realize(SYS_BUS_DEVICE(&a->vic), errp)) { | ||
120 | return; | ||
121 | } | ||
122 | - aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->vic), 0, sc->memmap[ASPEED_DEV_VIC]); | ||
123 | - sysbus_connect_irq(SYS_BUS_DEVICE(&s->vic), 0, | ||
124 | - qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ)); | ||
125 | - sysbus_connect_irq(SYS_BUS_DEVICE(&s->vic), 1, | ||
126 | - qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ)); | ||
127 | + aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->vic), 0, sc->memmap[ASPEED_DEV_VIC]); | ||
128 | + sysbus_connect_irq(SYS_BUS_DEVICE(&a->vic), 0, | ||
129 | + qdev_get_gpio_in(DEVICE(&a->cpu), ARM_CPU_IRQ)); | ||
130 | + sysbus_connect_irq(SYS_BUS_DEVICE(&a->vic), 1, | ||
131 | + qdev_get_gpio_in(DEVICE(&a->cpu), ARM_CPU_FIQ)); | ||
132 | |||
133 | /* RTC */ | ||
134 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->rtc), errp)) { | ||
135 | diff --git a/hw/arm/meson.build b/hw/arm/meson.build | ||
136 | index XXXXXXX..XXXXXXX 100644 | ||
137 | --- a/hw/arm/meson.build | ||
138 | +++ b/hw/arm/meson.build | ||
139 | @@ -XXX,XX +XXX,XX @@ arm_ss.add(when: 'CONFIG_FSL_IMX25', if_true: files('fsl-imx25.c', 'imx25_pdk.c' | ||
140 | arm_ss.add(when: 'CONFIG_FSL_IMX31', if_true: files('fsl-imx31.c', 'kzm.c')) | ||
141 | arm_ss.add(when: 'CONFIG_FSL_IMX6', if_true: files('fsl-imx6.c')) | ||
142 | arm_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files( | ||
143 | - 'aspeed_soc.c', | ||
144 | 'aspeed.c', | ||
145 | 'aspeed_soc_common.c', | ||
146 | + 'aspeed_ast2400.c', | ||
147 | 'aspeed_ast2600.c', | ||
148 | 'aspeed_ast10x0.c', | ||
149 | 'aspeed_eeprom.c', | ||
83 | -- | 150 | -- |
84 | 2.26.2 | 151 | 2.41.0 |
85 | 152 | ||
86 | 153 | diff view generated by jsdifflib |