1 | First pullreq for 6.0: mostly my v8.1M work, plus some other | 1 | The following changes since commit 64ada298b98a51eb2512607f6e6180cb330c47b1: |
---|---|---|---|
2 | bits and pieces. (I still have a lot of stuff in my to-review | ||
3 | folder, which I may or may not get to before the Christmas break...) | ||
4 | 2 | ||
5 | thanks | 3 | Merge remote-tracking branch 'remotes/legoater/tags/pull-ppc-20220302' into staging (2022-03-02 12:38:46 +0000) |
6 | -- PMM | ||
7 | |||
8 | The following changes since commit 5e7b204dbfae9a562fc73684986f936b97f63877: | ||
9 | |||
10 | Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging (2020-12-09 20:08:54 +0000) | ||
11 | 4 | ||
12 | are available in the Git repository at: | 5 | are available in the Git repository at: |
13 | 6 | ||
14 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20201210 | 7 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220302 |
15 | 8 | ||
16 | for you to fetch changes up to 71f916be1c7e9ede0e37d9cabc781b5a9e8638ff: | 9 | for you to fetch changes up to 268c11984e67867c22f53beb3c7f8b98900d66b2: |
17 | 10 | ||
18 | hw/arm/armv7m: Correct typo in QOM object name (2020-12-10 11:44:56 +0000) | 11 | ui/cocoa.m: Remove unnecessary NSAutoreleasePools (2022-03-02 19:27:37 +0000) |
19 | 12 | ||
20 | ---------------------------------------------------------------- | 13 | ---------------------------------------------------------------- |
21 | target-arm queue: | 14 | target-arm queue: |
22 | * hw/arm/smmuv3: Fix up L1STD_SPAN decoding | 15 | * mps3-an547: Add missing user ahb interfaces |
23 | * xlnx-zynqmp: Support Xilinx ZynqMP CAN controllers | 16 | * hw/arm/mps2-tz.c: Update AN547 documentation URL |
24 | * sbsa-ref: allow to use Cortex-A53/57/72 cpus | 17 | * hw/input/tsc210x: Don't abort on bad SPI word widths |
25 | * Various minor code cleanups | 18 | * hw/i2c: flatten pca954x mux device |
26 | * hw/intc/armv7m_nvic: Make all of system PPB range be RAZWI/BusFault | 19 | * target/arm: Support PSCI 1.1 and SMCCC 1.0 |
27 | * Implement more pieces of ARMv8.1M support | 20 | * target/arm: Fix early free of TCG temp in handle_simd_shift_fpint_conv() |
21 | * tests/qtest: add qtests for npcm7xx sdhci | ||
22 | * Implement FEAT_LVA | ||
23 | * Implement FEAT_LPA | ||
24 | * Implement FEAT_LPA2 (but do not enable it yet) | ||
25 | * Report KVM's actual PSCI version to guest in dtb | ||
26 | * ui/cocoa.m: Fix updateUIInfo threading issues | ||
27 | * ui/cocoa.m: Remove unnecessary NSAutoreleasePools | ||
28 | 28 | ||
29 | ---------------------------------------------------------------- | 29 | ---------------------------------------------------------------- |
30 | Alex Chen (4): | 30 | Akihiko Odaki (1): |
31 | i.MX25: Fix bad printf format specifiers | 31 | target/arm: Support PSCI 1.1 and SMCCC 1.0 |
32 | i.MX31: Fix bad printf format specifiers | ||
33 | i.MX6: Fix bad printf format specifiers | ||
34 | i.MX6ul: Fix bad printf format specifiers | ||
35 | 32 | ||
36 | Havard Skinnemoen (1): | 33 | Jimmy Brisson (1): |
37 | tests/qtest/npcm7xx_rng-test: dump random data on failure | 34 | mps3-an547: Add missing user ahb interfaces |
38 | 35 | ||
39 | Kunkun Jiang (1): | 36 | Patrick Venture (1): |
40 | hw/arm/smmuv3: Fix up L1STD_SPAN decoding | 37 | hw/i2c: flatten pca954x mux device |
41 | 38 | ||
42 | Marcin Juszkiewicz (1): | 39 | Peter Maydell (5): |
43 | sbsa-ref: allow to use Cortex-A53/57/72 cpus | 40 | hw/arm/mps2-tz.c: Update AN547 documentation URL |
41 | hw/input/tsc210x: Don't abort on bad SPI word widths | ||
42 | target/arm: Report KVM's actual PSCI version to guest in dtb | ||
43 | ui/cocoa.m: Fix updateUIInfo threading issues | ||
44 | ui/cocoa.m: Remove unnecessary NSAutoreleasePools | ||
44 | 45 | ||
45 | Peter Maydell (25): | 46 | Richard Henderson (16): |
46 | hw/intc/armv7m_nvic: Make all of system PPB range be RAZWI/BusFault | 47 | hw/registerfields: Add FIELD_SEX<N> and FIELD_SDP<N> |
47 | target/arm: Implement v8.1M PXN extension | 48 | target/arm: Set TCR_EL1.TSZ for user-only |
48 | target/arm: Don't clobber ID_PFR1.Security on M-profile cores | 49 | target/arm: Fault on invalid TCR_ELx.TxSZ |
49 | target/arm: Implement VSCCLRM insn | 50 | target/arm: Move arm_pamax out of line |
50 | target/arm: Implement CLRM instruction | 51 | target/arm: Pass outputsize down to check_s2_mmu_setup |
51 | target/arm: Enforce M-profile VMRS/VMSR register restrictions | 52 | target/arm: Use MAKE_64BIT_MASK to compute indexmask |
52 | target/arm: Refactor M-profile VMSR/VMRS handling | 53 | target/arm: Honor TCR_ELx.{I}PS |
53 | target/arm: Move general-use constant expanders up in translate.c | 54 | target/arm: Prepare DBGBVR and DBGWVR for FEAT_LVA |
54 | target/arm: Implement VLDR/VSTR system register | 55 | target/arm: Implement FEAT_LVA |
55 | target/arm: Implement M-profile FPSCR_nzcvqc | 56 | target/arm: Implement FEAT_LPA |
56 | target/arm: Use new FPCR_NZCV_MASK constant | 57 | target/arm: Extend arm_fi_to_lfsc to level -1 |
57 | target/arm: Factor out preserve-fp-state from full_vfp_access_check() | 58 | target/arm: Introduce tlbi_aa64_get_range |
58 | target/arm: Implement FPCXT_S fp system register | 59 | target/arm: Fix TLBIRange.base for 16k and 64k pages |
59 | hw/intc/armv7m_nvic: Update FPDSCR masking for v8.1M | 60 | target/arm: Validate tlbi TG matches translation granule in use |
60 | target/arm: For v8.1M, always clear R0-R3, R12, APSR, EPSR on exception entry | 61 | target/arm: Advertise all page sizes for -cpu max |
61 | target/arm: In v8.1M, don't set HFSR.FORCED on vector table fetch failures | 62 | target/arm: Implement FEAT_LPA2 |
62 | target/arm: Implement v8.1M REVIDR register | ||
63 | target/arm: Implement new v8.1M NOCP check for exception return | ||
64 | target/arm: Implement new v8.1M VLLDM and VLSTM encodings | ||
65 | hw/intc/armv7m_nvic: Support v8.1M CCR.TRD bit | ||
66 | target/arm: Implement CCR_S.TRD behaviour for SG insns | ||
67 | hw/intc/armv7m_nvic: Fix "return from inactive handler" check | ||
68 | target/arm: Implement M-profile "minimal RAS implementation" | ||
69 | hw/intc/armv7m_nvic: Implement read/write for RAS register block | ||
70 | hw/arm/armv7m: Correct typo in QOM object name | ||
71 | 63 | ||
72 | Vikram Garhwal (4): | 64 | Shengtan Mao (1): |
73 | hw/net/can: Introduce Xilinx ZynqMP CAN controller | 65 | tests/qtest: add qtests for npcm7xx sdhci |
74 | xlnx-zynqmp: Connect Xilinx ZynqMP CAN controllers | ||
75 | tests/qtest: Introduce tests for Xilinx ZynqMP CAN controller | ||
76 | MAINTAINERS: Add maintainer entry for Xilinx ZynqMP CAN controller | ||
77 | 66 | ||
78 | meson.build | 1 + | 67 | Wentao_Liang (1): |
79 | hw/arm/smmuv3-internal.h | 2 +- | 68 | target/arm: Fix early free of TCG temp in handle_simd_shift_fpint_conv() |
80 | hw/net/can/trace.h | 1 + | ||
81 | include/hw/arm/xlnx-zynqmp.h | 8 + | ||
82 | include/hw/intc/armv7m_nvic.h | 2 + | ||
83 | include/hw/net/xlnx-zynqmp-can.h | 78 +++ | ||
84 | target/arm/cpu.h | 46 ++ | ||
85 | target/arm/m-nocp.decode | 10 +- | ||
86 | target/arm/t32.decode | 10 +- | ||
87 | target/arm/vfp.decode | 14 + | ||
88 | hw/arm/armv7m.c | 4 +- | ||
89 | hw/arm/sbsa-ref.c | 23 +- | ||
90 | hw/arm/xlnx-zcu102.c | 20 + | ||
91 | hw/arm/xlnx-zynqmp.c | 34 ++ | ||
92 | hw/intc/armv7m_nvic.c | 246 ++++++-- | ||
93 | hw/misc/imx25_ccm.c | 12 +- | ||
94 | hw/misc/imx31_ccm.c | 14 +- | ||
95 | hw/misc/imx6_ccm.c | 20 +- | ||
96 | hw/misc/imx6_src.c | 2 +- | ||
97 | hw/misc/imx6ul_ccm.c | 4 +- | ||
98 | hw/misc/imx_ccm.c | 4 +- | ||
99 | hw/net/can/xlnx-zynqmp-can.c | 1161 ++++++++++++++++++++++++++++++++++++++ | ||
100 | target/arm/cpu.c | 5 +- | ||
101 | target/arm/helper.c | 7 +- | ||
102 | target/arm/m_helper.c | 130 ++++- | ||
103 | target/arm/translate.c | 105 +++- | ||
104 | tests/qtest/npcm7xx_rng-test.c | 12 + | ||
105 | tests/qtest/xlnx-can-test.c | 360 ++++++++++++ | ||
106 | MAINTAINERS | 8 + | ||
107 | hw/Kconfig | 1 + | ||
108 | hw/net/can/meson.build | 1 + | ||
109 | hw/net/can/trace-events | 9 + | ||
110 | target/arm/translate-vfp.c.inc | 511 ++++++++++++++++- | ||
111 | tests/qtest/meson.build | 1 + | ||
112 | 34 files changed, 2713 insertions(+), 153 deletions(-) | ||
113 | create mode 100644 hw/net/can/trace.h | ||
114 | create mode 100644 include/hw/net/xlnx-zynqmp-can.h | ||
115 | create mode 100644 hw/net/can/xlnx-zynqmp-can.c | ||
116 | create mode 100644 tests/qtest/xlnx-can-test.c | ||
117 | create mode 100644 hw/net/can/trace-events | ||
118 | 69 | ||
70 | docs/system/arm/emulation.rst | 3 + | ||
71 | include/hw/registerfields.h | 48 +++++- | ||
72 | target/arm/cpu-param.h | 4 +- | ||
73 | target/arm/cpu.h | 27 ++++ | ||
74 | target/arm/internals.h | 58 ++++--- | ||
75 | target/arm/kvm-consts.h | 14 +- | ||
76 | hw/arm/boot.c | 11 +- | ||
77 | hw/arm/mps2-tz.c | 6 +- | ||
78 | hw/i2c/i2c_mux_pca954x.c | 77 ++------- | ||
79 | hw/input/tsc210x.c | 8 +- | ||
80 | target/arm/cpu.c | 8 +- | ||
81 | target/arm/cpu64.c | 7 +- | ||
82 | target/arm/helper.c | 332 ++++++++++++++++++++++++++++++--------- | ||
83 | target/arm/hvf/hvf.c | 27 +++- | ||
84 | target/arm/kvm64.c | 14 +- | ||
85 | target/arm/psci.c | 35 ++++- | ||
86 | target/arm/translate-a64.c | 2 +- | ||
87 | tests/qtest/npcm7xx_sdhci-test.c | 215 +++++++++++++++++++++++++ | ||
88 | tests/qtest/meson.build | 1 + | ||
89 | ui/cocoa.m | 31 ++-- | ||
90 | 20 files changed, 736 insertions(+), 192 deletions(-) | ||
91 | create mode 100644 tests/qtest/npcm7xx_sdhci-test.c | diff view generated by jsdifflib |
1 | For v8.1M the architecture mandates that CPUs must provide at | 1 | From: Jimmy Brisson <jimmy.brisson@linaro.org> |
---|---|---|---|
2 | least the "minimal RAS implementation" from the Reliability, | ||
3 | Availability and Serviceability extension. This consists of: | ||
4 | * an ESB instruction which is a NOP | ||
5 | -- since it is in the HINT space we need only add a comment | ||
6 | * an RFSR register which will RAZ/WI | ||
7 | * a RAZ/WI AIRCR.IESB bit | ||
8 | -- the code which handles writes to AIRCR does not allow setting | ||
9 | of RES0 bits, so we already treat this as RAZ/WI; add a comment | ||
10 | noting that this is deliberate | ||
11 | * minimal implementation of the RAS register block at 0xe0005000 | ||
12 | -- this will be in a subsequent commit | ||
13 | * setting the ID_PFR0.RAS field to 0b0010 | ||
14 | -- we will do this when we add the Cortex-M55 CPU model | ||
15 | 2 | ||
3 | With these interfaces missing, TFM would delegate peripherals 0, 1, | ||
4 | 2, 3 and 8, and qemu would ignore the delegation of interface 8, as | ||
5 | it thought interface 4 was eth & USB. | ||
6 | |||
7 | This patch corrects this behavior and allows TFM to delegate the | ||
8 | eth & USB peripheral to NS mode. | ||
9 | |||
10 | (The old QEMU behaviour was based on revision B of the AN547 | ||
11 | appnote; revision C corrects this error in the documentation, | ||
12 | and this commit brings QEMU in to line with how the FPGA | ||
13 | image really behaves.) | ||
14 | |||
15 | Signed-off-by: Jimmy Brisson <jimmy.brisson@linaro.org> | ||
16 | Message-id: 20220210210227.3203883-1-jimmy.brisson@linaro.org | ||
17 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
18 | [PMM: added commit message note clarifying that the old behaviour | ||
19 | was a docs issue, not because there were two different versions | ||
20 | of the FPGA image] | ||
16 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 21 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
17 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
18 | Message-id: 20201119215617.29887-26-peter.maydell@linaro.org | ||
19 | --- | 22 | --- |
20 | target/arm/cpu.h | 14 ++++++++++++++ | 23 | hw/arm/mps2-tz.c | 4 ++++ |
21 | target/arm/t32.decode | 4 ++++ | 24 | 1 file changed, 4 insertions(+) |
22 | hw/intc/armv7m_nvic.c | 13 +++++++++++++ | ||
23 | 3 files changed, 31 insertions(+) | ||
24 | 25 | ||
25 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | 26 | diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c |
26 | index XXXXXXX..XXXXXXX 100644 | 27 | index XXXXXXX..XXXXXXX 100644 |
27 | --- a/target/arm/cpu.h | 28 | --- a/hw/arm/mps2-tz.c |
28 | +++ b/target/arm/cpu.h | 29 | +++ b/hw/arm/mps2-tz.c |
29 | @@ -XXX,XX +XXX,XX @@ FIELD(ID_MMFR4, LSM, 20, 4) | 30 | @@ -XXX,XX +XXX,XX @@ static void mps2tz_common_init(MachineState *machine) |
30 | FIELD(ID_MMFR4, CCIDX, 24, 4) | 31 | { "gpio1", make_unimp_dev, &mms->gpio[1], 0x41101000, 0x1000 }, |
31 | FIELD(ID_MMFR4, EVT, 28, 4) | 32 | { "gpio2", make_unimp_dev, &mms->gpio[2], 0x41102000, 0x1000 }, |
32 | 33 | { "gpio3", make_unimp_dev, &mms->gpio[3], 0x41103000, 0x1000 }, | |
33 | +FIELD(ID_PFR0, STATE0, 0, 4) | 34 | + { /* port 4 USER AHB interface 0 */ }, |
34 | +FIELD(ID_PFR0, STATE1, 4, 4) | 35 | + { /* port 5 USER AHB interface 1 */ }, |
35 | +FIELD(ID_PFR0, STATE2, 8, 4) | 36 | + { /* port 6 USER AHB interface 2 */ }, |
36 | +FIELD(ID_PFR0, STATE3, 12, 4) | 37 | + { /* port 7 USER AHB interface 3 */ }, |
37 | +FIELD(ID_PFR0, CSV2, 16, 4) | 38 | { "eth-usb", make_eth_usb, NULL, 0x41400000, 0x200000, { 49 } }, |
38 | +FIELD(ID_PFR0, AMU, 20, 4) | 39 | }, |
39 | +FIELD(ID_PFR0, DIT, 24, 4) | 40 | }, |
40 | +FIELD(ID_PFR0, RAS, 28, 4) | ||
41 | + | ||
42 | FIELD(ID_PFR1, PROGMOD, 0, 4) | ||
43 | FIELD(ID_PFR1, SECURITY, 4, 4) | ||
44 | FIELD(ID_PFR1, MPROGMOD, 8, 4) | ||
45 | @@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa32_predinv(const ARMISARegisters *id) | ||
46 | return FIELD_EX32(id->id_isar6, ID_ISAR6, SPECRES) != 0; | ||
47 | } | ||
48 | |||
49 | +static inline bool isar_feature_aa32_ras(const ARMISARegisters *id) | ||
50 | +{ | ||
51 | + return FIELD_EX32(id->id_pfr0, ID_PFR0, RAS) != 0; | ||
52 | +} | ||
53 | + | ||
54 | static inline bool isar_feature_aa32_mprofile(const ARMISARegisters *id) | ||
55 | { | ||
56 | return FIELD_EX32(id->id_pfr1, ID_PFR1, MPROGMOD) != 0; | ||
57 | diff --git a/target/arm/t32.decode b/target/arm/t32.decode | ||
58 | index XXXXXXX..XXXXXXX 100644 | ||
59 | --- a/target/arm/t32.decode | ||
60 | +++ b/target/arm/t32.decode | ||
61 | @@ -XXX,XX +XXX,XX @@ CLZ 1111 1010 1011 ---- 1111 .... 1000 .... @rdm | ||
62 | # SEV 1111 0011 1010 1111 1000 0000 0000 0100 | ||
63 | # SEVL 1111 0011 1010 1111 1000 0000 0000 0101 | ||
64 | |||
65 | + # For M-profile minimal-RAS ESB can be a NOP, which is the | ||
66 | + # default behaviour since it is in the hint space. | ||
67 | + # ESB 1111 0011 1010 1111 1000 0000 0001 0000 | ||
68 | + | ||
69 | # The canonical nop ends in 0000 0000, but the whole rest | ||
70 | # of the space is "reserved hint, behaves as nop". | ||
71 | NOP 1111 0011 1010 1111 1000 0000 ---- ---- | ||
72 | diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c | ||
73 | index XXXXXXX..XXXXXXX 100644 | ||
74 | --- a/hw/intc/armv7m_nvic.c | ||
75 | +++ b/hw/intc/armv7m_nvic.c | ||
76 | @@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs) | ||
77 | return 0; | ||
78 | } | ||
79 | return cpu->env.v7m.sfar; | ||
80 | + case 0xf04: /* RFSR */ | ||
81 | + if (!cpu_isar_feature(aa32_ras, cpu)) { | ||
82 | + goto bad_offset; | ||
83 | + } | ||
84 | + /* We provide minimal-RAS only: RFSR is RAZ/WI */ | ||
85 | + return 0; | ||
86 | case 0xf34: /* FPCCR */ | ||
87 | if (!cpu_isar_feature(aa32_vfp_simd, cpu)) { | ||
88 | return 0; | ||
89 | @@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value, | ||
90 | R_V7M_AIRCR_PRIGROUP_SHIFT, | ||
91 | R_V7M_AIRCR_PRIGROUP_LENGTH); | ||
92 | } | ||
93 | + /* AIRCR.IESB is RAZ/WI because we implement only minimal RAS */ | ||
94 | if (attrs.secure) { | ||
95 | /* These bits are only writable by secure */ | ||
96 | cpu->env.v7m.aircr = value & | ||
97 | @@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value, | ||
98 | } | ||
99 | break; | ||
100 | } | ||
101 | + case 0xf04: /* RFSR */ | ||
102 | + if (!cpu_isar_feature(aa32_ras, cpu)) { | ||
103 | + goto bad_offset; | ||
104 | + } | ||
105 | + /* We provide minimal-RAS only: RFSR is RAZ/WI */ | ||
106 | + break; | ||
107 | case 0xf34: /* FPCCR */ | ||
108 | if (cpu_isar_feature(aa32_vfp_simd, cpu)) { | ||
109 | /* Not all bits here are banked. */ | ||
110 | -- | 41 | -- |
111 | 2.20.1 | 42 | 2.25.1 |
112 | |||
113 | diff view generated by jsdifflib |
1 | Correct a typo in the name we give the NVIC object. | 1 | The AN547 application note URL has changed: update our comment |
---|---|---|---|
2 | accordingly. (Rev B is still downloadable from the old URL, | ||
3 | but there is a new Rev C of the document now.) | ||
2 | 4 | ||
3 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
4 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 6 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> |
5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 7 | Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> |
6 | Message-id: 20201119215617.29887-28-peter.maydell@linaro.org | 8 | Message-id: 20220221094144.426191-1-peter.maydell@linaro.org |
7 | --- | 9 | --- |
8 | hw/arm/armv7m.c | 2 +- | 10 | hw/arm/mps2-tz.c | 2 +- |
9 | 1 file changed, 1 insertion(+), 1 deletion(-) | 11 | 1 file changed, 1 insertion(+), 1 deletion(-) |
10 | 12 | ||
11 | diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c | 13 | diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c |
12 | index XXXXXXX..XXXXXXX 100644 | 14 | index XXXXXXX..XXXXXXX 100644 |
13 | --- a/hw/arm/armv7m.c | 15 | --- a/hw/arm/mps2-tz.c |
14 | +++ b/hw/arm/armv7m.c | 16 | +++ b/hw/arm/mps2-tz.c |
15 | @@ -XXX,XX +XXX,XX @@ static void armv7m_instance_init(Object *obj) | 17 | @@ -XXX,XX +XXX,XX @@ |
16 | 18 | * Application Note AN524: | |
17 | memory_region_init(&s->container, obj, "armv7m-container", UINT64_MAX); | 19 | * https://developer.arm.com/documentation/dai0524/latest/ |
18 | 20 | * Application Note AN547: | |
19 | - object_initialize_child(obj, "nvnic", &s->nvic, TYPE_NVIC); | 21 | - * https://developer.arm.com/-/media/Arm%20Developer%20Community/PDF/DAI0547B_SSE300_PLUS_U55_FPGA_for_mps3.pdf |
20 | + object_initialize_child(obj, "nvic", &s->nvic, TYPE_NVIC); | 22 | + * https://developer.arm.com/documentation/dai0547/latest/ |
21 | object_property_add_alias(obj, "num-irq", | 23 | * |
22 | OBJECT(&s->nvic), "num-irq"); | 24 | * The AN505 defers to the Cortex-M33 processor ARMv8M IoT Kit FVP User Guide |
23 | 25 | * (ARM ECM0601256) for the details of some of the device layout: | |
24 | -- | 26 | -- |
25 | 2.20.1 | 27 | 2.25.1 |
26 | 28 | ||
27 | 29 | diff view generated by jsdifflib |
1 | v8.1M introduces a new TRD flag in the CCR register, which enables | 1 | The tsc210x doesn't support anything other than 16-bit reads on the |
---|---|---|---|
2 | checking for stack frame integrity signatures on SG instructions. | 2 | SPI bus, but the guest can program the SPI controller to attempt |
3 | This bit is not banked, and is always RAZ/WI to Non-secure code. | 3 | them anyway. If this happens, don't abort QEMU, just log this as |
4 | Adjust the code for handling CCR reads and writes to handle this. | 4 | a guest error. |
5 | 5 | ||
6 | This fixes our machine_arm_n8x0.py:N8x0Machine.test_n800 | ||
7 | acceptance test, which hits this assertion. | ||
8 | |||
9 | The reason we hit the assertion is because the guest kernel thinks | ||
10 | there is a TSC2005 on this SPI bus address, not a TSC210x. (The n810 | ||
11 | *does* have a TSC2005 at this address.) The TSC2005 supports the | ||
12 | 24-bit accesses which the guest driver makes, and the TSC210x does | ||
13 | not (that is, our TSC210x emulation is not missing support for a word | ||
14 | width the hardware can handle). It's not clear whether the problem | ||
15 | here is that the guest kernel incorrectly thinks the n800 has the | ||
16 | same device at this SPI bus address as the n810, or that QEMU's n810 | ||
17 | board model doesn't get the SPI devices right. At this late date | ||
18 | there no longer appears to be any reliable information on the web | ||
19 | about the hardware behaviour, but I am inclined to think this is a | ||
20 | guest kernel bug. In any case, we prefer not to abort QEMU for | ||
21 | guest-triggerable conditions, so logging the error is the right thing | ||
22 | to do. | ||
23 | |||
24 | Resolves: https://gitlab.com/qemu-project/qemu/-/issues/736 | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 25 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 26 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> |
8 | Message-id: 20201119215617.29887-23-peter.maydell@linaro.org | 27 | Message-id: 20220221140750.514557-1-peter.maydell@linaro.org |
9 | --- | 28 | --- |
10 | target/arm/cpu.h | 2 ++ | 29 | hw/input/tsc210x.c | 8 ++++++-- |
11 | hw/intc/armv7m_nvic.c | 26 ++++++++++++++++++-------- | 30 | 1 file changed, 6 insertions(+), 2 deletions(-) |
12 | 2 files changed, 20 insertions(+), 8 deletions(-) | ||
13 | 31 | ||
14 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | 32 | diff --git a/hw/input/tsc210x.c b/hw/input/tsc210x.c |
15 | index XXXXXXX..XXXXXXX 100644 | 33 | index XXXXXXX..XXXXXXX 100644 |
16 | --- a/target/arm/cpu.h | 34 | --- a/hw/input/tsc210x.c |
17 | +++ b/target/arm/cpu.h | 35 | +++ b/hw/input/tsc210x.c |
18 | @@ -XXX,XX +XXX,XX @@ FIELD(V7M_CCR, STKOFHFNMIGN, 10, 1) | 36 | @@ -XXX,XX +XXX,XX @@ |
19 | FIELD(V7M_CCR, DC, 16, 1) | 37 | #include "hw/hw.h" |
20 | FIELD(V7M_CCR, IC, 17, 1) | 38 | #include "audio/audio.h" |
21 | FIELD(V7M_CCR, BP, 18, 1) | 39 | #include "qemu/timer.h" |
22 | +FIELD(V7M_CCR, LOB, 19, 1) | 40 | +#include "qemu/log.h" |
23 | +FIELD(V7M_CCR, TRD, 20, 1) | 41 | #include "sysemu/reset.h" |
24 | 42 | #include "ui/console.h" | |
25 | /* V7M SCR bits */ | 43 | #include "hw/arm/omap.h" /* For I2SCodec */ |
26 | FIELD(V7M_SCR, SLEEPONEXIT, 1, 1) | 44 | @@ -XXX,XX +XXX,XX @@ uint32_t tsc210x_txrx(void *opaque, uint32_t value, int len) |
27 | diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c | 45 | TSC210xState *s = opaque; |
28 | index XXXXXXX..XXXXXXX 100644 | 46 | uint32_t ret = 0; |
29 | --- a/hw/intc/armv7m_nvic.c | 47 | |
30 | +++ b/hw/intc/armv7m_nvic.c | 48 | - if (len != 16) |
31 | @@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs) | 49 | - hw_error("%s: FIXME: bad SPI word width %i\n", __func__, len); |
32 | } | 50 | + if (len != 16) { |
33 | return cpu->env.v7m.scr[attrs.secure]; | 51 | + qemu_log_mask(LOG_GUEST_ERROR, |
34 | case 0xd14: /* Configuration Control. */ | 52 | + "%s: bad SPI word width %i\n", __func__, len); |
35 | - /* The BFHFNMIGN bit is the only non-banked bit; we | 53 | + return 0; |
36 | - * keep it in the non-secure copy of the register. | ||
37 | + /* | ||
38 | + * Non-banked bits: BFHFNMIGN (stored in the NS copy of the register) | ||
39 | + * and TRD (stored in the S copy of the register) | ||
40 | */ | ||
41 | val = cpu->env.v7m.ccr[attrs.secure]; | ||
42 | val |= cpu->env.v7m.ccr[M_REG_NS] & R_V7M_CCR_BFHFNMIGN_MASK; | ||
43 | @@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value, | ||
44 | cpu->env.v7m.scr[attrs.secure] = value; | ||
45 | break; | ||
46 | case 0xd14: /* Configuration Control. */ | ||
47 | + { | ||
48 | + uint32_t mask; | ||
49 | + | ||
50 | if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { | ||
51 | goto bad_offset; | ||
52 | } | ||
53 | |||
54 | /* Enforce RAZ/WI on reserved and must-RAZ/WI bits */ | ||
55 | - value &= (R_V7M_CCR_STKALIGN_MASK | | ||
56 | - R_V7M_CCR_BFHFNMIGN_MASK | | ||
57 | - R_V7M_CCR_DIV_0_TRP_MASK | | ||
58 | - R_V7M_CCR_UNALIGN_TRP_MASK | | ||
59 | - R_V7M_CCR_USERSETMPEND_MASK | | ||
60 | - R_V7M_CCR_NONBASETHRDENA_MASK); | ||
61 | + mask = R_V7M_CCR_STKALIGN_MASK | | ||
62 | + R_V7M_CCR_BFHFNMIGN_MASK | | ||
63 | + R_V7M_CCR_DIV_0_TRP_MASK | | ||
64 | + R_V7M_CCR_UNALIGN_TRP_MASK | | ||
65 | + R_V7M_CCR_USERSETMPEND_MASK | | ||
66 | + R_V7M_CCR_NONBASETHRDENA_MASK; | ||
67 | + if (arm_feature(&cpu->env, ARM_FEATURE_V8_1M) && attrs.secure) { | ||
68 | + /* TRD is always RAZ/WI from NS */ | ||
69 | + mask |= R_V7M_CCR_TRD_MASK; | ||
70 | + } | ||
71 | + value &= mask; | ||
72 | |||
73 | if (arm_feature(&cpu->env, ARM_FEATURE_V8)) { | ||
74 | /* v8M makes NONBASETHRDENA and STKALIGN be RES1 */ | ||
75 | @@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value, | ||
76 | |||
77 | cpu->env.v7m.ccr[attrs.secure] = value; | ||
78 | break; | ||
79 | + } | 54 | + } |
80 | case 0xd24: /* System Handler Control and State (SHCSR) */ | 55 | |
81 | if (!arm_feature(&cpu->env, ARM_FEATURE_V7)) { | 56 | /* TODO: sequential reads etc - how do we make sure the host doesn't |
82 | goto bad_offset; | 57 | * unintentionally read out a conversion result from a register while |
83 | -- | 58 | -- |
84 | 2.20.1 | 59 | 2.25.1 |
85 | 60 | ||
86 | 61 | diff view generated by jsdifflib |
1 | Implement the v8.1M VSCCLRM insn, which zeros floating point | 1 | From: Patrick Venture <venture@google.com> |
---|---|---|---|
2 | registers if there is an active floating point context. | ||
3 | This requires support in write_neon_element32() for the MO_32 | ||
4 | element size, so add it. | ||
5 | 2 | ||
6 | Because we want to use arm_gen_condlabel(), we need to move | 3 | Previously this device created N subdevices which each owned an i2c bus. |
7 | the definition of that function up in translate.c so it is | 4 | Now this device simply owns the N i2c busses directly. |
8 | before the #include of translate-vfp.c.inc. | ||
9 | 5 | ||
6 | Tested: Verified devices behind mux are still accessible via qmp and i2c | ||
7 | from within an arm32 SoC. | ||
8 | |||
9 | Reviewed-by: Hao Wu <wuhaotsh@google.com> | ||
10 | Signed-off-by: Patrick Venture <venture@google.com> | ||
11 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
12 | Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
13 | Message-id: 20220202164533.1283668-1-venture@google.com | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 14 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
11 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
12 | Message-id: 20201119215617.29887-5-peter.maydell@linaro.org | ||
13 | --- | 15 | --- |
14 | target/arm/cpu.h | 9 ++++ | 16 | hw/i2c/i2c_mux_pca954x.c | 77 +++++++--------------------------------- |
15 | target/arm/m-nocp.decode | 8 +++- | 17 | 1 file changed, 13 insertions(+), 64 deletions(-) |
16 | target/arm/translate.c | 21 +++++---- | ||
17 | target/arm/translate-vfp.c.inc | 84 ++++++++++++++++++++++++++++++++++ | ||
18 | 4 files changed, 111 insertions(+), 11 deletions(-) | ||
19 | 18 | ||
20 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | 19 | diff --git a/hw/i2c/i2c_mux_pca954x.c b/hw/i2c/i2c_mux_pca954x.c |
21 | index XXXXXXX..XXXXXXX 100644 | 20 | index XXXXXXX..XXXXXXX 100644 |
22 | --- a/target/arm/cpu.h | 21 | --- a/hw/i2c/i2c_mux_pca954x.c |
23 | +++ b/target/arm/cpu.h | 22 | +++ b/hw/i2c/i2c_mux_pca954x.c |
24 | @@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa32_mprofile(const ARMISARegisters *id) | 23 | @@ -XXX,XX +XXX,XX @@ |
25 | return FIELD_EX32(id->id_pfr1, ID_PFR1, MPROGMOD) != 0; | 24 | #define PCA9548_CHANNEL_COUNT 8 |
25 | #define PCA9546_CHANNEL_COUNT 4 | ||
26 | |||
27 | -/* | ||
28 | - * struct Pca954xChannel - The i2c mux device will have N of these states | ||
29 | - * that own the i2c channel bus. | ||
30 | - * @bus: The owned channel bus. | ||
31 | - * @enabled: Is this channel active? | ||
32 | - */ | ||
33 | -typedef struct Pca954xChannel { | ||
34 | - SysBusDevice parent; | ||
35 | - | ||
36 | - I2CBus *bus; | ||
37 | - | ||
38 | - bool enabled; | ||
39 | -} Pca954xChannel; | ||
40 | - | ||
41 | -#define TYPE_PCA954X_CHANNEL "pca954x-channel" | ||
42 | -#define PCA954X_CHANNEL(obj) \ | ||
43 | - OBJECT_CHECK(Pca954xChannel, (obj), TYPE_PCA954X_CHANNEL) | ||
44 | - | ||
45 | /* | ||
46 | * struct Pca954xState - The pca954x state object. | ||
47 | * @control: The value written to the mux control. | ||
48 | @@ -XXX,XX +XXX,XX @@ typedef struct Pca954xState { | ||
49 | |||
50 | uint8_t control; | ||
51 | |||
52 | - /* The channel i2c buses. */ | ||
53 | - Pca954xChannel channel[PCA9548_CHANNEL_COUNT]; | ||
54 | + bool enabled[PCA9548_CHANNEL_COUNT]; | ||
55 | + I2CBus *bus[PCA9548_CHANNEL_COUNT]; | ||
56 | } Pca954xState; | ||
57 | |||
58 | /* | ||
59 | @@ -XXX,XX +XXX,XX @@ static bool pca954x_match(I2CSlave *candidate, uint8_t address, | ||
60 | } | ||
61 | |||
62 | for (i = 0; i < mc->nchans; i++) { | ||
63 | - if (!mux->channel[i].enabled) { | ||
64 | + if (!mux->enabled[i]) { | ||
65 | continue; | ||
66 | } | ||
67 | |||
68 | - if (i2c_scan_bus(mux->channel[i].bus, address, broadcast, | ||
69 | + if (i2c_scan_bus(mux->bus[i], address, broadcast, | ||
70 | current_devs)) { | ||
71 | if (!broadcast) { | ||
72 | return true; | ||
73 | @@ -XXX,XX +XXX,XX @@ static void pca954x_enable_channel(Pca954xState *s, uint8_t enable_mask) | ||
74 | */ | ||
75 | for (i = 0; i < mc->nchans; i++) { | ||
76 | if (enable_mask & (1 << i)) { | ||
77 | - s->channel[i].enabled = true; | ||
78 | + s->enabled[i] = true; | ||
79 | } else { | ||
80 | - s->channel[i].enabled = false; | ||
81 | + s->enabled[i] = false; | ||
82 | } | ||
83 | } | ||
26 | } | 84 | } |
27 | 85 | @@ -XXX,XX +XXX,XX @@ I2CBus *pca954x_i2c_get_bus(I2CSlave *mux, uint8_t channel) | |
28 | +static inline bool isar_feature_aa32_m_sec_state(const ARMISARegisters *id) | 86 | Pca954xState *pca954x = PCA954X(mux); |
29 | +{ | 87 | |
30 | + /* | 88 | g_assert(channel < pc->nchans); |
31 | + * Return true if M-profile state handling insns | 89 | - return I2C_BUS(qdev_get_child_bus(DEVICE(&pca954x->channel[channel]), |
32 | + * (VSCCLRM, CLRM, FPCTX access insns) are implemented | 90 | - "i2c-bus")); |
33 | + */ | 91 | -} |
34 | + return FIELD_EX32(id->id_pfr1, ID_PFR1, SECURITY) >= 3; | 92 | - |
35 | +} | 93 | -static void pca954x_channel_init(Object *obj) |
36 | + | 94 | -{ |
37 | static inline bool isar_feature_aa32_fp16_arith(const ARMISARegisters *id) | 95 | - Pca954xChannel *s = PCA954X_CHANNEL(obj); |
38 | { | 96 | - s->bus = i2c_init_bus(DEVICE(s), "i2c-bus"); |
39 | /* Sadly this is encoded differently for A-profile and M-profile */ | 97 | - |
40 | diff --git a/target/arm/m-nocp.decode b/target/arm/m-nocp.decode | 98 | - /* Start all channels as disabled. */ |
41 | index XXXXXXX..XXXXXXX 100644 | 99 | - s->enabled = false; |
42 | --- a/target/arm/m-nocp.decode | 100 | -} |
43 | +++ b/target/arm/m-nocp.decode | 101 | - |
44 | @@ -XXX,XX +XXX,XX @@ | 102 | -static void pca954x_channel_class_init(ObjectClass *klass, void *data) |
45 | # If the coprocessor is not present or disabled then we will generate | 103 | -{ |
46 | # the NOCP exception; otherwise we let the insn through to the main decode. | 104 | - DeviceClass *dc = DEVICE_CLASS(klass); |
47 | 105 | - dc->desc = "Pca954x Channel"; | |
48 | +%vd_dp 22:1 12:4 | 106 | + return pca954x->bus[channel]; |
49 | +%vd_sp 12:4 22:1 | ||
50 | + | ||
51 | &nocp cp | ||
52 | |||
53 | { | ||
54 | # Special cases which do not take an early NOCP: VLLDM and VLSTM | ||
55 | VLLDM_VLSTM 1110 1100 001 l:1 rn:4 0000 1010 0000 0000 | ||
56 | - # TODO: VSCCLRM (new in v8.1M) is similar: | ||
57 | - #VSCCLRM 1110 1100 1-01 1111 ---- 1011 ---- ---0 | ||
58 | + # VSCCLRM (new in v8.1M) is similar: | ||
59 | + VSCCLRM 1110 1100 1.01 1111 .... 1011 imm:7 0 vd=%vd_dp size=3 | ||
60 | + VSCCLRM 1110 1100 1.01 1111 .... 1010 imm:8 vd=%vd_sp size=2 | ||
61 | |||
62 | NOCP 111- 1110 ---- ---- ---- cp:4 ---- ---- &nocp | ||
63 | NOCP 111- 110- ---- ---- ---- cp:4 ---- ---- &nocp | ||
64 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
65 | index XXXXXXX..XXXXXXX 100644 | ||
66 | --- a/target/arm/translate.c | ||
67 | +++ b/target/arm/translate.c | ||
68 | @@ -XXX,XX +XXX,XX @@ void arm_translate_init(void) | ||
69 | a64_translate_init(); | ||
70 | } | 107 | } |
71 | 108 | ||
72 | +/* Generate a label used for skipping this instruction */ | 109 | static void pca9546_class_init(ObjectClass *klass, void *data) |
73 | +static void arm_gen_condlabel(DisasContext *s) | 110 | @@ -XXX,XX +XXX,XX @@ static void pca9548_class_init(ObjectClass *klass, void *data) |
74 | +{ | 111 | s->nchans = PCA9548_CHANNEL_COUNT; |
75 | + if (!s->condjmp) { | ||
76 | + s->condlabel = gen_new_label(); | ||
77 | + s->condjmp = 1; | ||
78 | + } | ||
79 | +} | ||
80 | + | ||
81 | /* Flags for the disas_set_da_iss info argument: | ||
82 | * lower bits hold the Rt register number, higher bits are flags. | ||
83 | */ | ||
84 | @@ -XXX,XX +XXX,XX @@ static void write_neon_element64(TCGv_i64 src, int reg, int ele, MemOp memop) | ||
85 | long off = neon_element_offset(reg, ele, memop); | ||
86 | |||
87 | switch (memop) { | ||
88 | + case MO_32: | ||
89 | + tcg_gen_st32_i64(src, cpu_env, off); | ||
90 | + break; | ||
91 | case MO_64: | ||
92 | tcg_gen_st_i64(src, cpu_env, off); | ||
93 | break; | ||
94 | @@ -XXX,XX +XXX,XX @@ static void gen_srs(DisasContext *s, | ||
95 | s->base.is_jmp = DISAS_UPDATE_EXIT; | ||
96 | } | 112 | } |
97 | 113 | ||
98 | -/* Generate a label used for skipping this instruction */ | 114 | -static void pca954x_realize(DeviceState *dev, Error **errp) |
99 | -static void arm_gen_condlabel(DisasContext *s) | ||
100 | -{ | 115 | -{ |
101 | - if (!s->condjmp) { | 116 | - Pca954xState *s = PCA954X(dev); |
102 | - s->condlabel = gen_new_label(); | 117 | - Pca954xClass *c = PCA954X_GET_CLASS(s); |
103 | - s->condjmp = 1; | 118 | - int i; |
119 | - | ||
120 | - /* SMBus modules. Cannot fail. */ | ||
121 | - for (i = 0; i < c->nchans; i++) { | ||
122 | - sysbus_realize(SYS_BUS_DEVICE(&s->channel[i]), &error_abort); | ||
104 | - } | 123 | - } |
105 | -} | 124 | -} |
106 | - | 125 | - |
107 | /* Skip this instruction if the ARM condition is false */ | 126 | static void pca954x_init(Object *obj) |
108 | static void arm_skip_unless(DisasContext *s, uint32_t cond) | ||
109 | { | 127 | { |
110 | diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc | 128 | Pca954xState *s = PCA954X(obj); |
111 | index XXXXXXX..XXXXXXX 100644 | 129 | Pca954xClass *c = PCA954X_GET_CLASS(obj); |
112 | --- a/target/arm/translate-vfp.c.inc | 130 | int i; |
113 | +++ b/target/arm/translate-vfp.c.inc | 131 | |
114 | @@ -XXX,XX +XXX,XX @@ static bool trans_VLLDM_VLSTM(DisasContext *s, arg_VLLDM_VLSTM *a) | 132 | - /* Only initialize the children we expect. */ |
115 | return true; | 133 | + /* SMBus modules. Cannot fail. */ |
134 | for (i = 0; i < c->nchans; i++) { | ||
135 | - object_initialize_child(obj, "channel[*]", &s->channel[i], | ||
136 | - TYPE_PCA954X_CHANNEL); | ||
137 | + g_autofree gchar *bus_name = g_strdup_printf("i2c.%d", i); | ||
138 | + | ||
139 | + /* start all channels as disabled. */ | ||
140 | + s->enabled[i] = false; | ||
141 | + s->bus[i] = i2c_init_bus(DEVICE(s), bus_name); | ||
142 | } | ||
116 | } | 143 | } |
117 | 144 | ||
118 | +static bool trans_VSCCLRM(DisasContext *s, arg_VSCCLRM *a) | 145 | @@ -XXX,XX +XXX,XX @@ static void pca954x_class_init(ObjectClass *klass, void *data) |
119 | +{ | 146 | rc->phases.enter = pca954x_enter_reset; |
120 | + int btmreg, topreg; | 147 | |
121 | + TCGv_i64 zero; | 148 | dc->desc = "Pca954x i2c-mux"; |
122 | + TCGv_i32 aspen, sfpa; | 149 | - dc->realize = pca954x_realize; |
123 | + | 150 | |
124 | + if (!dc_isar_feature(aa32_m_sec_state, s)) { | 151 | k->write_data = pca954x_write_data; |
125 | + /* Before v8.1M, fall through in decode to NOCP check */ | 152 | k->receive_byte = pca954x_read_byte; |
126 | + return false; | 153 | @@ -XXX,XX +XXX,XX @@ static const TypeInfo pca954x_info[] = { |
127 | + } | 154 | .parent = TYPE_PCA954X, |
128 | + | 155 | .class_init = pca9548_class_init, |
129 | + /* Explicitly UNDEF because this takes precedence over NOCP */ | 156 | }, |
130 | + if (!arm_dc_feature(s, ARM_FEATURE_M_MAIN) || !s->v8m_secure) { | 157 | - { |
131 | + unallocated_encoding(s); | 158 | - .name = TYPE_PCA954X_CHANNEL, |
132 | + return true; | 159 | - .parent = TYPE_SYS_BUS_DEVICE, |
133 | + } | 160 | - .class_init = pca954x_channel_class_init, |
134 | + | 161 | - .instance_size = sizeof(Pca954xChannel), |
135 | + if (!dc_isar_feature(aa32_vfp_simd, s)) { | 162 | - .instance_init = pca954x_channel_init, |
136 | + /* NOP if we have neither FP nor MVE */ | 163 | - } |
137 | + return true; | 164 | }; |
138 | + } | 165 | |
139 | + | 166 | DEFINE_TYPES(pca954x_info) |
140 | + /* | ||
141 | + * If FPCCR.ASPEN != 0 && CONTROL_S.SFPA == 0 then there is no | ||
142 | + * active floating point context so we must NOP (without doing | ||
143 | + * any lazy state preservation or the NOCP check). | ||
144 | + */ | ||
145 | + aspen = load_cpu_field(v7m.fpccr[M_REG_S]); | ||
146 | + sfpa = load_cpu_field(v7m.control[M_REG_S]); | ||
147 | + tcg_gen_andi_i32(aspen, aspen, R_V7M_FPCCR_ASPEN_MASK); | ||
148 | + tcg_gen_xori_i32(aspen, aspen, R_V7M_FPCCR_ASPEN_MASK); | ||
149 | + tcg_gen_andi_i32(sfpa, sfpa, R_V7M_CONTROL_SFPA_MASK); | ||
150 | + tcg_gen_or_i32(sfpa, sfpa, aspen); | ||
151 | + arm_gen_condlabel(s); | ||
152 | + tcg_gen_brcondi_i32(TCG_COND_EQ, sfpa, 0, s->condlabel); | ||
153 | + | ||
154 | + if (s->fp_excp_el != 0) { | ||
155 | + gen_exception_insn(s, s->pc_curr, EXCP_NOCP, | ||
156 | + syn_uncategorized(), s->fp_excp_el); | ||
157 | + return true; | ||
158 | + } | ||
159 | + | ||
160 | + topreg = a->vd + a->imm - 1; | ||
161 | + btmreg = a->vd; | ||
162 | + | ||
163 | + /* Convert to Sreg numbers if the insn specified in Dregs */ | ||
164 | + if (a->size == 3) { | ||
165 | + topreg = topreg * 2 + 1; | ||
166 | + btmreg *= 2; | ||
167 | + } | ||
168 | + | ||
169 | + if (topreg > 63 || (topreg > 31 && !(topreg & 1))) { | ||
170 | + /* UNPREDICTABLE: we choose to undef */ | ||
171 | + unallocated_encoding(s); | ||
172 | + return true; | ||
173 | + } | ||
174 | + | ||
175 | + /* Silently ignore requests to clear D16-D31 if they don't exist */ | ||
176 | + if (topreg > 31 && !dc_isar_feature(aa32_simd_r32, s)) { | ||
177 | + topreg = 31; | ||
178 | + } | ||
179 | + | ||
180 | + if (!vfp_access_check(s)) { | ||
181 | + return true; | ||
182 | + } | ||
183 | + | ||
184 | + /* Zero the Sregs from btmreg to topreg inclusive. */ | ||
185 | + zero = tcg_const_i64(0); | ||
186 | + if (btmreg & 1) { | ||
187 | + write_neon_element64(zero, btmreg >> 1, 1, MO_32); | ||
188 | + btmreg++; | ||
189 | + } | ||
190 | + for (; btmreg + 1 <= topreg; btmreg += 2) { | ||
191 | + write_neon_element64(zero, btmreg >> 1, 0, MO_64); | ||
192 | + } | ||
193 | + if (btmreg == topreg) { | ||
194 | + write_neon_element64(zero, btmreg >> 1, 0, MO_32); | ||
195 | + btmreg++; | ||
196 | + } | ||
197 | + assert(btmreg == topreg + 1); | ||
198 | + /* TODO: when MVE is implemented, zero VPR here */ | ||
199 | + return true; | ||
200 | +} | ||
201 | + | ||
202 | static bool trans_NOCP(DisasContext *s, arg_nocp *a) | ||
203 | { | ||
204 | /* | ||
205 | -- | 167 | -- |
206 | 2.20.1 | 168 | 2.25.1 |
207 | 169 | ||
208 | 170 | diff view generated by jsdifflib |
1 | In arm_cpu_realizefn() we check whether the board code disabled EL3 | 1 | From: Akihiko Odaki <akihiko.odaki@gmail.com> |
---|---|---|---|
2 | via the has_el3 CPU object property, which we create if the CPU | ||
3 | starts with the ARM_FEATURE_EL3 feature bit. If it is disabled, then | ||
4 | we turn off ARM_FEATURE_EL3 and also zero out the relevant fields in | ||
5 | the ID_PFR1 and ID_AA64PFR0 registers. | ||
6 | 2 | ||
7 | This codepath was incorrectly being taken for M-profile CPUs, which | 3 | Support the latest PSCI on TCG and HVF. A 64-bit function called from |
8 | do not have an EL3 and don't set ARM_FEATURE_EL3, but which may have | 4 | AArch32 now returns NOT_SUPPORTED, which is necessary to adhere to SMC |
9 | the M-profile Security extension and so should have non-zero values | 5 | Calling Convention 1.0. It is still not compliant with SMCCC 1.3 since |
10 | in the ID_PFR1.Security field. | 6 | they do not implement mandatory functions. |
11 | 7 | ||
12 | Restrict the handling of the feature flag to A/R-profile cores. | 8 | Signed-off-by: Akihiko Odaki <akihiko.odaki@gmail.com> |
9 | Message-id: 20220213035753.34577-1-akihiko.odaki@gmail.com | ||
10 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
11 | [PMM: update MISMATCH_CHECK checks on PSCI_VERSION macros to match] | ||
12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
13 | --- | ||
14 | target/arm/kvm-consts.h | 13 +++++++++---- | ||
15 | hw/arm/boot.c | 12 +++++++++--- | ||
16 | target/arm/cpu.c | 5 +++-- | ||
17 | target/arm/hvf/hvf.c | 27 ++++++++++++++++++++++++++- | ||
18 | target/arm/kvm64.c | 2 +- | ||
19 | target/arm/psci.c | 35 ++++++++++++++++++++++++++++++++--- | ||
20 | 6 files changed, 80 insertions(+), 14 deletions(-) | ||
13 | 21 | ||
14 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 22 | diff --git a/target/arm/kvm-consts.h b/target/arm/kvm-consts.h |
15 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 23 | index XXXXXXX..XXXXXXX 100644 |
16 | Message-id: 20201119215617.29887-4-peter.maydell@linaro.org | 24 | --- a/target/arm/kvm-consts.h |
17 | --- | 25 | +++ b/target/arm/kvm-consts.h |
18 | target/arm/cpu.c | 2 +- | 26 | @@ -XXX,XX +XXX,XX @@ MISMATCH_CHECK(QEMU_PSCI_0_1_FN_MIGRATE, KVM_PSCI_FN_MIGRATE); |
19 | 1 file changed, 1 insertion(+), 1 deletion(-) | 27 | #define QEMU_PSCI_0_2_FN64_AFFINITY_INFO QEMU_PSCI_0_2_FN64(4) |
20 | 28 | #define QEMU_PSCI_0_2_FN64_MIGRATE QEMU_PSCI_0_2_FN64(5) | |
29 | |||
30 | +#define QEMU_PSCI_1_0_FN_PSCI_FEATURES QEMU_PSCI_0_2_FN(10) | ||
31 | + | ||
32 | MISMATCH_CHECK(QEMU_PSCI_0_2_FN_CPU_SUSPEND, PSCI_0_2_FN_CPU_SUSPEND); | ||
33 | MISMATCH_CHECK(QEMU_PSCI_0_2_FN_CPU_OFF, PSCI_0_2_FN_CPU_OFF); | ||
34 | MISMATCH_CHECK(QEMU_PSCI_0_2_FN_CPU_ON, PSCI_0_2_FN_CPU_ON); | ||
35 | @@ -XXX,XX +XXX,XX @@ MISMATCH_CHECK(QEMU_PSCI_0_2_FN_MIGRATE, PSCI_0_2_FN_MIGRATE); | ||
36 | MISMATCH_CHECK(QEMU_PSCI_0_2_FN64_CPU_SUSPEND, PSCI_0_2_FN64_CPU_SUSPEND); | ||
37 | MISMATCH_CHECK(QEMU_PSCI_0_2_FN64_CPU_ON, PSCI_0_2_FN64_CPU_ON); | ||
38 | MISMATCH_CHECK(QEMU_PSCI_0_2_FN64_MIGRATE, PSCI_0_2_FN64_MIGRATE); | ||
39 | +MISMATCH_CHECK(QEMU_PSCI_1_0_FN_PSCI_FEATURES, PSCI_1_0_FN_PSCI_FEATURES); | ||
40 | |||
41 | /* PSCI v0.2 return values used by TCG emulation of PSCI */ | ||
42 | |||
43 | /* No Trusted OS migration to worry about when offlining CPUs */ | ||
44 | #define QEMU_PSCI_0_2_RET_TOS_MIGRATION_NOT_REQUIRED 2 | ||
45 | |||
46 | -/* We implement version 0.2 only */ | ||
47 | -#define QEMU_PSCI_0_2_RET_VERSION_0_2 2 | ||
48 | +#define QEMU_PSCI_VERSION_0_1 0x00001 | ||
49 | +#define QEMU_PSCI_VERSION_0_2 0x00002 | ||
50 | +#define QEMU_PSCI_VERSION_1_1 0x10001 | ||
51 | |||
52 | MISMATCH_CHECK(QEMU_PSCI_0_2_RET_TOS_MIGRATION_NOT_REQUIRED, PSCI_0_2_TOS_MP); | ||
53 | -MISMATCH_CHECK(QEMU_PSCI_0_2_RET_VERSION_0_2, | ||
54 | - (PSCI_VERSION_MAJOR(0) | PSCI_VERSION_MINOR(2))); | ||
55 | +/* We don't bother to check every possible version value */ | ||
56 | +MISMATCH_CHECK(QEMU_PSCI_VERSION_0_2, PSCI_VERSION(0, 2)); | ||
57 | +MISMATCH_CHECK(QEMU_PSCI_VERSION_1_1, PSCI_VERSION(1, 1)); | ||
58 | |||
59 | /* PSCI return values (inclusive of all PSCI versions) */ | ||
60 | #define QEMU_PSCI_RET_SUCCESS 0 | ||
61 | diff --git a/hw/arm/boot.c b/hw/arm/boot.c | ||
62 | index XXXXXXX..XXXXXXX 100644 | ||
63 | --- a/hw/arm/boot.c | ||
64 | +++ b/hw/arm/boot.c | ||
65 | @@ -XXX,XX +XXX,XX @@ static void fdt_add_psci_node(void *fdt) | ||
66 | } | ||
67 | |||
68 | qemu_fdt_add_subnode(fdt, "/psci"); | ||
69 | - if (armcpu->psci_version == 2) { | ||
70 | - const char comp[] = "arm,psci-0.2\0arm,psci"; | ||
71 | - qemu_fdt_setprop(fdt, "/psci", "compatible", comp, sizeof(comp)); | ||
72 | + if (armcpu->psci_version == QEMU_PSCI_VERSION_0_2 || | ||
73 | + armcpu->psci_version == QEMU_PSCI_VERSION_1_1) { | ||
74 | + if (armcpu->psci_version == QEMU_PSCI_VERSION_0_2) { | ||
75 | + const char comp[] = "arm,psci-0.2\0arm,psci"; | ||
76 | + qemu_fdt_setprop(fdt, "/psci", "compatible", comp, sizeof(comp)); | ||
77 | + } else { | ||
78 | + const char comp[] = "arm,psci-1.0\0arm,psci-0.2\0arm,psci"; | ||
79 | + qemu_fdt_setprop(fdt, "/psci", "compatible", comp, sizeof(comp)); | ||
80 | + } | ||
81 | |||
82 | cpu_off_fn = QEMU_PSCI_0_2_FN_CPU_OFF; | ||
83 | if (arm_feature(&armcpu->env, ARM_FEATURE_AARCH64)) { | ||
21 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c | 84 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c |
22 | index XXXXXXX..XXXXXXX 100644 | 85 | index XXXXXXX..XXXXXXX 100644 |
23 | --- a/target/arm/cpu.c | 86 | --- a/target/arm/cpu.c |
24 | +++ b/target/arm/cpu.c | 87 | +++ b/target/arm/cpu.c |
25 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) | 88 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_initfn(Object *obj) |
89 | * picky DTB consumer will also provide a helpful error message. | ||
90 | */ | ||
91 | cpu->dtb_compatible = "qemu,unknown"; | ||
92 | - cpu->psci_version = 1; /* By default assume PSCI v0.1 */ | ||
93 | + cpu->psci_version = QEMU_PSCI_VERSION_0_1; /* By default assume PSCI v0.1 */ | ||
94 | cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE; | ||
95 | |||
96 | if (tcg_enabled() || hvf_enabled()) { | ||
97 | - cpu->psci_version = 2; /* TCG and HVF implement PSCI 0.2 */ | ||
98 | + /* TCG and HVF implement PSCI 1.1 */ | ||
99 | + cpu->psci_version = QEMU_PSCI_VERSION_1_1; | ||
100 | } | ||
101 | } | ||
102 | |||
103 | diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c | ||
104 | index XXXXXXX..XXXXXXX 100644 | ||
105 | --- a/target/arm/hvf/hvf.c | ||
106 | +++ b/target/arm/hvf/hvf.c | ||
107 | @@ -XXX,XX +XXX,XX @@ static bool hvf_handle_psci_call(CPUState *cpu) | ||
108 | |||
109 | switch (param[0]) { | ||
110 | case QEMU_PSCI_0_2_FN_PSCI_VERSION: | ||
111 | - ret = QEMU_PSCI_0_2_RET_VERSION_0_2; | ||
112 | + ret = QEMU_PSCI_VERSION_1_1; | ||
113 | break; | ||
114 | case QEMU_PSCI_0_2_FN_MIGRATE_INFO_TYPE: | ||
115 | ret = QEMU_PSCI_0_2_RET_TOS_MIGRATION_NOT_REQUIRED; /* No trusted OS */ | ||
116 | @@ -XXX,XX +XXX,XX @@ static bool hvf_handle_psci_call(CPUState *cpu) | ||
117 | case QEMU_PSCI_0_2_FN_MIGRATE: | ||
118 | ret = QEMU_PSCI_RET_NOT_SUPPORTED; | ||
119 | break; | ||
120 | + case QEMU_PSCI_1_0_FN_PSCI_FEATURES: | ||
121 | + switch (param[1]) { | ||
122 | + case QEMU_PSCI_0_2_FN_PSCI_VERSION: | ||
123 | + case QEMU_PSCI_0_2_FN_MIGRATE_INFO_TYPE: | ||
124 | + case QEMU_PSCI_0_2_FN_AFFINITY_INFO: | ||
125 | + case QEMU_PSCI_0_2_FN64_AFFINITY_INFO: | ||
126 | + case QEMU_PSCI_0_2_FN_SYSTEM_RESET: | ||
127 | + case QEMU_PSCI_0_2_FN_SYSTEM_OFF: | ||
128 | + case QEMU_PSCI_0_1_FN_CPU_ON: | ||
129 | + case QEMU_PSCI_0_2_FN_CPU_ON: | ||
130 | + case QEMU_PSCI_0_2_FN64_CPU_ON: | ||
131 | + case QEMU_PSCI_0_1_FN_CPU_OFF: | ||
132 | + case QEMU_PSCI_0_2_FN_CPU_OFF: | ||
133 | + case QEMU_PSCI_0_1_FN_CPU_SUSPEND: | ||
134 | + case QEMU_PSCI_0_2_FN_CPU_SUSPEND: | ||
135 | + case QEMU_PSCI_0_2_FN64_CPU_SUSPEND: | ||
136 | + case QEMU_PSCI_1_0_FN_PSCI_FEATURES: | ||
137 | + ret = 0; | ||
138 | + break; | ||
139 | + case QEMU_PSCI_0_1_FN_MIGRATE: | ||
140 | + case QEMU_PSCI_0_2_FN_MIGRATE: | ||
141 | + default: | ||
142 | + ret = QEMU_PSCI_RET_NOT_SUPPORTED; | ||
143 | + } | ||
144 | + break; | ||
145 | default: | ||
146 | return false; | ||
147 | } | ||
148 | diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c | ||
149 | index XXXXXXX..XXXXXXX 100644 | ||
150 | --- a/target/arm/kvm64.c | ||
151 | +++ b/target/arm/kvm64.c | ||
152 | @@ -XXX,XX +XXX,XX @@ int kvm_arch_init_vcpu(CPUState *cs) | ||
153 | cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_POWER_OFF; | ||
154 | } | ||
155 | if (kvm_check_extension(cs->kvm_state, KVM_CAP_ARM_PSCI_0_2)) { | ||
156 | - cpu->psci_version = 2; | ||
157 | + cpu->psci_version = QEMU_PSCI_VERSION_0_2; | ||
158 | cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_PSCI_0_2; | ||
159 | } | ||
160 | if (!arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { | ||
161 | diff --git a/target/arm/psci.c b/target/arm/psci.c | ||
162 | index XXXXXXX..XXXXXXX 100644 | ||
163 | --- a/target/arm/psci.c | ||
164 | +++ b/target/arm/psci.c | ||
165 | @@ -XXX,XX +XXX,XX @@ void arm_handle_psci_call(ARMCPU *cpu) | ||
166 | { | ||
167 | /* | ||
168 | * This function partially implements the logic for dispatching Power State | ||
169 | - * Coordination Interface (PSCI) calls (as described in ARM DEN 0022B.b), | ||
170 | + * Coordination Interface (PSCI) calls (as described in ARM DEN 0022D.b), | ||
171 | * to the extent required for bringing up and taking down secondary cores, | ||
172 | * and for handling reset and poweroff requests. | ||
173 | * Additional information about the calling convention used is available in | ||
174 | @@ -XXX,XX +XXX,XX @@ void arm_handle_psci_call(ARMCPU *cpu) | ||
175 | } | ||
176 | |||
177 | if ((param[0] & QEMU_PSCI_0_2_64BIT) && !is_a64(env)) { | ||
178 | - ret = QEMU_PSCI_RET_INVALID_PARAMS; | ||
179 | + ret = QEMU_PSCI_RET_NOT_SUPPORTED; | ||
180 | goto err; | ||
181 | } | ||
182 | |||
183 | @@ -XXX,XX +XXX,XX @@ void arm_handle_psci_call(ARMCPU *cpu) | ||
184 | ARMCPU *target_cpu; | ||
185 | |||
186 | case QEMU_PSCI_0_2_FN_PSCI_VERSION: | ||
187 | - ret = QEMU_PSCI_0_2_RET_VERSION_0_2; | ||
188 | + ret = QEMU_PSCI_VERSION_1_1; | ||
189 | break; | ||
190 | case QEMU_PSCI_0_2_FN_MIGRATE_INFO_TYPE: | ||
191 | ret = QEMU_PSCI_0_2_RET_TOS_MIGRATION_NOT_REQUIRED; /* No trusted OS */ | ||
192 | @@ -XXX,XX +XXX,XX @@ void arm_handle_psci_call(ARMCPU *cpu) | ||
26 | } | 193 | } |
27 | } | 194 | helper_wfi(env, 4); |
28 | 195 | break; | |
29 | - if (!cpu->has_el3) { | 196 | + case QEMU_PSCI_1_0_FN_PSCI_FEATURES: |
30 | + if (!arm_feature(env, ARM_FEATURE_M) && !cpu->has_el3) { | 197 | + switch (param[1]) { |
31 | /* If the has_el3 CPU property is disabled then we need to disable the | 198 | + case QEMU_PSCI_0_2_FN_PSCI_VERSION: |
32 | * feature. | 199 | + case QEMU_PSCI_0_2_FN_MIGRATE_INFO_TYPE: |
33 | */ | 200 | + case QEMU_PSCI_0_2_FN_AFFINITY_INFO: |
201 | + case QEMU_PSCI_0_2_FN64_AFFINITY_INFO: | ||
202 | + case QEMU_PSCI_0_2_FN_SYSTEM_RESET: | ||
203 | + case QEMU_PSCI_0_2_FN_SYSTEM_OFF: | ||
204 | + case QEMU_PSCI_0_1_FN_CPU_ON: | ||
205 | + case QEMU_PSCI_0_2_FN_CPU_ON: | ||
206 | + case QEMU_PSCI_0_2_FN64_CPU_ON: | ||
207 | + case QEMU_PSCI_0_1_FN_CPU_OFF: | ||
208 | + case QEMU_PSCI_0_2_FN_CPU_OFF: | ||
209 | + case QEMU_PSCI_0_1_FN_CPU_SUSPEND: | ||
210 | + case QEMU_PSCI_0_2_FN_CPU_SUSPEND: | ||
211 | + case QEMU_PSCI_0_2_FN64_CPU_SUSPEND: | ||
212 | + case QEMU_PSCI_1_0_FN_PSCI_FEATURES: | ||
213 | + if (!(param[1] & QEMU_PSCI_0_2_64BIT) || is_a64(env)) { | ||
214 | + ret = 0; | ||
215 | + break; | ||
216 | + } | ||
217 | + /* fallthrough */ | ||
218 | + case QEMU_PSCI_0_1_FN_MIGRATE: | ||
219 | + case QEMU_PSCI_0_2_FN_MIGRATE: | ||
220 | + default: | ||
221 | + ret = QEMU_PSCI_RET_NOT_SUPPORTED; | ||
222 | + break; | ||
223 | + } | ||
224 | + break; | ||
225 | case QEMU_PSCI_0_1_FN_MIGRATE: | ||
226 | case QEMU_PSCI_0_2_FN_MIGRATE: | ||
227 | default: | ||
34 | -- | 228 | -- |
35 | 2.20.1 | 229 | 2.25.1 |
36 | |||
37 | diff view generated by jsdifflib |
1 | The RAS feature has a block of memory-mapped registers at offset | 1 | From: Wentao_Liang <Wentao_Liang_g@163.com> |
---|---|---|---|
2 | 0x5000 within the PPB. For a "minimal RAS" implementation we provide | ||
3 | no error records and so the only registers that exist in the block | ||
4 | are ERRIIDR and ERRDEVID. | ||
5 | 2 | ||
6 | The "RAZ/WI for privileged, BusFault for nonprivileged" behaviour | 3 | handle_simd_shift_fpint_conv() was accidentally freeing the TCG |
7 | of the "nvic-default" region is actually valid for minimal-RAS, | 4 | temporary tcg_fpstatus too early, before the last use of it. Move |
8 | so the main benefit of providing an explicit implementation of | 5 | the free down to where it belongs. |
9 | the register block is more accurate LOG_UNIMP messages, and a | ||
10 | framework for where we could add a real RAS implementation later | ||
11 | if necessary. | ||
12 | 6 | ||
7 | Signed-off-by: Wentao_Liang <Wentao_Liang_g@163.com> | ||
8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
9 | [PMM: cleaned up commit message] | ||
13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
14 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
15 | Message-id: 20201119215617.29887-27-peter.maydell@linaro.org | ||
16 | --- | 11 | --- |
17 | include/hw/intc/armv7m_nvic.h | 1 + | 12 | target/arm/translate-a64.c | 2 +- |
18 | hw/intc/armv7m_nvic.c | 56 +++++++++++++++++++++++++++++++++++ | 13 | 1 file changed, 1 insertion(+), 1 deletion(-) |
19 | 2 files changed, 57 insertions(+) | ||
20 | 14 | ||
21 | diff --git a/include/hw/intc/armv7m_nvic.h b/include/hw/intc/armv7m_nvic.h | 15 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c |
22 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
23 | --- a/include/hw/intc/armv7m_nvic.h | 17 | --- a/target/arm/translate-a64.c |
24 | +++ b/include/hw/intc/armv7m_nvic.h | 18 | +++ b/target/arm/translate-a64.c |
25 | @@ -XXX,XX +XXX,XX @@ struct NVICState { | 19 | @@ -XXX,XX +XXX,XX @@ static void handle_simd_shift_fpint_conv(DisasContext *s, bool is_scalar, |
26 | MemoryRegion sysreg_ns_mem; | 20 | } |
27 | MemoryRegion systickmem; | ||
28 | MemoryRegion systick_ns_mem; | ||
29 | + MemoryRegion ras_mem; | ||
30 | MemoryRegion container; | ||
31 | MemoryRegion defaultmem; | ||
32 | |||
33 | diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c | ||
34 | index XXXXXXX..XXXXXXX 100644 | ||
35 | --- a/hw/intc/armv7m_nvic.c | ||
36 | +++ b/hw/intc/armv7m_nvic.c | ||
37 | @@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps nvic_systick_ops = { | ||
38 | .endianness = DEVICE_NATIVE_ENDIAN, | ||
39 | }; | ||
40 | |||
41 | + | ||
42 | +static MemTxResult ras_read(void *opaque, hwaddr addr, | ||
43 | + uint64_t *data, unsigned size, | ||
44 | + MemTxAttrs attrs) | ||
45 | +{ | ||
46 | + if (attrs.user) { | ||
47 | + return MEMTX_ERROR; | ||
48 | + } | ||
49 | + | ||
50 | + switch (addr) { | ||
51 | + case 0xe10: /* ERRIIDR */ | ||
52 | + /* architect field = Arm; product/variant/revision 0 */ | ||
53 | + *data = 0x43b; | ||
54 | + break; | ||
55 | + case 0xfc8: /* ERRDEVID */ | ||
56 | + /* Minimal RAS: we implement 0 error record indexes */ | ||
57 | + *data = 0; | ||
58 | + break; | ||
59 | + default: | ||
60 | + qemu_log_mask(LOG_UNIMP, "Read RAS register offset 0x%x\n", | ||
61 | + (uint32_t)addr); | ||
62 | + *data = 0; | ||
63 | + break; | ||
64 | + } | ||
65 | + return MEMTX_OK; | ||
66 | +} | ||
67 | + | ||
68 | +static MemTxResult ras_write(void *opaque, hwaddr addr, | ||
69 | + uint64_t value, unsigned size, | ||
70 | + MemTxAttrs attrs) | ||
71 | +{ | ||
72 | + if (attrs.user) { | ||
73 | + return MEMTX_ERROR; | ||
74 | + } | ||
75 | + | ||
76 | + switch (addr) { | ||
77 | + default: | ||
78 | + qemu_log_mask(LOG_UNIMP, "Write to RAS register offset 0x%x\n", | ||
79 | + (uint32_t)addr); | ||
80 | + break; | ||
81 | + } | ||
82 | + return MEMTX_OK; | ||
83 | +} | ||
84 | + | ||
85 | +static const MemoryRegionOps ras_ops = { | ||
86 | + .read_with_attrs = ras_read, | ||
87 | + .write_with_attrs = ras_write, | ||
88 | + .endianness = DEVICE_NATIVE_ENDIAN, | ||
89 | +}; | ||
90 | + | ||
91 | /* | ||
92 | * Unassigned portions of the PPB space are RAZ/WI for privileged | ||
93 | * accesses, and fault for non-privileged accesses. | ||
94 | @@ -XXX,XX +XXX,XX @@ static void armv7m_nvic_realize(DeviceState *dev, Error **errp) | ||
95 | &s->systick_ns_mem, 1); | ||
96 | } | 21 | } |
97 | 22 | ||
98 | + if (cpu_isar_feature(aa32_ras, s->cpu)) { | 23 | - tcg_temp_free_ptr(tcg_fpstatus); |
99 | + memory_region_init_io(&s->ras_mem, OBJECT(s), | 24 | tcg_temp_free_i32(tcg_shift); |
100 | + &ras_ops, s, "nvic_ras", 0x1000); | 25 | gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus); |
101 | + memory_region_add_subregion(&s->container, 0x5000, &s->ras_mem); | 26 | + tcg_temp_free_ptr(tcg_fpstatus); |
102 | + } | 27 | tcg_temp_free_i32(tcg_rmode); |
103 | + | ||
104 | sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->container); | ||
105 | } | 28 | } |
106 | 29 | ||
107 | -- | 30 | -- |
108 | 2.20.1 | 31 | 2.25.1 |
109 | |||
110 | diff view generated by jsdifflib |
1 | From: Vikram Garhwal <fnu.vikram@xilinx.com> | 1 | From: Shengtan Mao <stmao@google.com> |
---|---|---|---|
2 | 2 | ||
3 | The QTests perform five tests on the Xilinx ZynqMP CAN controller: | 3 | Reviewed-by: Hao Wu <wuhaotsh@google.com> |
4 | Tests the CAN controller in loopback, sleep and snoop mode. | 4 | Reviewed-by: Chris Rauer <crauer@google.com> |
5 | Tests filtering of incoming CAN messages. | 5 | Signed-off-by: Shengtan Mao <stmao@google.com> |
6 | 6 | Signed-off-by: Patrick Venture <venture@google.com> | |
7 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 7 | Message-id: 20220225174451.192304-1-wuhaotsh@google.com |
8 | Reviewed-by: Francisco Iglesias <francisco.iglesias@xilinx.com> | ||
9 | Signed-off-by: Vikram Garhwal <fnu.vikram@xilinx.com> | ||
10 | Message-id: 1605728926-352690-4-git-send-email-fnu.vikram@xilinx.com | ||
11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
12 | --- | 9 | --- |
13 | tests/qtest/xlnx-can-test.c | 360 ++++++++++++++++++++++++++++++++++++ | 10 | tests/qtest/npcm7xx_sdhci-test.c | 215 +++++++++++++++++++++++++++++++ |
14 | tests/qtest/meson.build | 1 + | 11 | tests/qtest/meson.build | 1 + |
15 | 2 files changed, 361 insertions(+) | 12 | 2 files changed, 216 insertions(+) |
16 | create mode 100644 tests/qtest/xlnx-can-test.c | 13 | create mode 100644 tests/qtest/npcm7xx_sdhci-test.c |
17 | 14 | ||
18 | diff --git a/tests/qtest/xlnx-can-test.c b/tests/qtest/xlnx-can-test.c | 15 | diff --git a/tests/qtest/npcm7xx_sdhci-test.c b/tests/qtest/npcm7xx_sdhci-test.c |
19 | new file mode 100644 | 16 | new file mode 100644 |
20 | index XXXXXXX..XXXXXXX | 17 | index XXXXXXX..XXXXXXX |
21 | --- /dev/null | 18 | --- /dev/null |
22 | +++ b/tests/qtest/xlnx-can-test.c | 19 | +++ b/tests/qtest/npcm7xx_sdhci-test.c |
23 | @@ -XXX,XX +XXX,XX @@ | 20 | @@ -XXX,XX +XXX,XX @@ |
24 | +/* | 21 | +/* |
25 | + * QTests for the Xilinx ZynqMP CAN controller. | 22 | + * QTests for NPCM7xx SD-3.0 / MMC-4.51 Host Controller |
26 | + * | 23 | + * |
27 | + * Copyright (c) 2020 Xilinx Inc. | 24 | + * Copyright (c) 2022 Google LLC |
28 | + * | 25 | + * |
29 | + * Written-by: Vikram Garhwal<fnu.vikram@xilinx.com> | 26 | + * This program is free software; you can redistribute it and/or modify it |
27 | + * under the terms of the GNU General Public License as published by the | ||
28 | + * Free Software Foundation; either version 2 of the License, or | ||
29 | + * (at your option) any later version. | ||
30 | + * | 30 | + * |
31 | + * Permission is hereby granted, free of charge, to any person obtaining a copy | 31 | + * This program is distributed in the hope that it will be useful, but WITHOUT |
32 | + * of this software and associated documentation files (the "Software"), to deal | 32 | + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
33 | + * in the Software without restriction, including without limitation the rights | 33 | + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
34 | + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | 34 | + * for more details. |
35 | + * copies of the Software, and to permit persons to whom the Software is | ||
36 | + * furnished to do so, subject to the following conditions: | ||
37 | + * | ||
38 | + * The above copyright notice and this permission notice shall be included in | ||
39 | + * all copies or substantial portions of the Software. | ||
40 | + * | ||
41 | + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
42 | + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
43 | + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
44 | + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
45 | + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | ||
46 | + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | ||
47 | + * THE SOFTWARE. | ||
48 | + */ | 35 | + */ |
49 | + | 36 | + |
50 | +#include "qemu/osdep.h" | 37 | +#include "qemu/osdep.h" |
38 | +#include "hw/sd/npcm7xx_sdhci.h" | ||
39 | + | ||
51 | +#include "libqos/libqtest.h" | 40 | +#include "libqos/libqtest.h" |
52 | + | 41 | +#include "libqtest-single.h" |
53 | +/* Base address. */ | 42 | +#include "libqos/sdhci-cmd.h" |
54 | +#define CAN0_BASE_ADDR 0xFF060000 | 43 | + |
55 | +#define CAN1_BASE_ADDR 0xFF070000 | 44 | +#define NPCM7XX_REG_SIZE 0x100 |
56 | + | 45 | +#define NPCM7XX_MMC_BA 0xF0842000 |
57 | +/* Register addresses. */ | 46 | +#define NPCM7XX_BLK_SIZE 512 |
58 | +#define R_SRR_OFFSET 0x00 | 47 | +#define NPCM7XX_TEST_IMAGE_SIZE (1 << 30) |
59 | +#define R_MSR_OFFSET 0x04 | 48 | + |
60 | +#define R_SR_OFFSET 0x18 | 49 | +char *sd_path; |
61 | +#define R_ISR_OFFSET 0x1C | 50 | + |
62 | +#define R_ICR_OFFSET 0x24 | 51 | +static QTestState *setup_sd_card(void) |
63 | +#define R_TXID_OFFSET 0x30 | 52 | +{ |
64 | +#define R_TXDLC_OFFSET 0x34 | 53 | + QTestState *qts = qtest_initf( |
65 | +#define R_TXDATA1_OFFSET 0x38 | 54 | + "-machine kudo-bmc " |
66 | +#define R_TXDATA2_OFFSET 0x3C | 55 | + "-device sd-card,drive=drive0 " |
67 | +#define R_RXID_OFFSET 0x50 | 56 | + "-drive id=drive0,if=none,file=%s,format=raw,auto-read-only=off", |
68 | +#define R_RXDLC_OFFSET 0x54 | 57 | + sd_path); |
69 | +#define R_RXDATA1_OFFSET 0x58 | 58 | + |
70 | +#define R_RXDATA2_OFFSET 0x5C | 59 | + qtest_writew(qts, NPCM7XX_MMC_BA + SDHC_SWRST, SDHC_RESET_ALL); |
71 | +#define R_AFR 0x60 | 60 | + qtest_writew(qts, NPCM7XX_MMC_BA + SDHC_CLKCON, |
72 | +#define R_AFMR1 0x64 | 61 | + SDHC_CLOCK_SDCLK_EN | SDHC_CLOCK_INT_STABLE | |
73 | +#define R_AFIR1 0x68 | 62 | + SDHC_CLOCK_INT_EN); |
74 | +#define R_AFMR2 0x6C | 63 | + sdhci_cmd_regs(qts, NPCM7XX_MMC_BA, 0, 0, 0, 0, SDHC_APP_CMD); |
75 | +#define R_AFIR2 0x70 | 64 | + sdhci_cmd_regs(qts, NPCM7XX_MMC_BA, 0, 0, 0x41200000, 0, (41 << 8)); |
76 | +#define R_AFMR3 0x74 | 65 | + sdhci_cmd_regs(qts, NPCM7XX_MMC_BA, 0, 0, 0, 0, SDHC_ALL_SEND_CID); |
77 | +#define R_AFIR3 0x78 | 66 | + sdhci_cmd_regs(qts, NPCM7XX_MMC_BA, 0, 0, 0, 0, SDHC_SEND_RELATIVE_ADDR); |
78 | +#define R_AFMR4 0x7C | 67 | + sdhci_cmd_regs(qts, NPCM7XX_MMC_BA, 0, 0, 0x45670000, 0, |
79 | +#define R_AFIR4 0x80 | 68 | + SDHC_SELECT_DESELECT_CARD); |
80 | + | 69 | + |
81 | +/* CAN modes. */ | 70 | + return qts; |
82 | +#define CONFIG_MODE 0x00 | 71 | +} |
83 | +#define NORMAL_MODE 0x00 | 72 | + |
84 | +#define LOOPBACK_MODE 0x02 | 73 | +static void write_sdread(QTestState *qts, const char *msg) |
85 | +#define SNOOP_MODE 0x04 | 74 | +{ |
86 | +#define SLEEP_MODE 0x01 | 75 | + int fd, ret; |
87 | +#define ENABLE_CAN (1 << 1) | 76 | + size_t len = strlen(msg); |
88 | +#define STATUS_NORMAL_MODE (1 << 3) | 77 | + char *rmsg = g_malloc(len); |
89 | +#define STATUS_LOOPBACK_MODE (1 << 1) | 78 | + |
90 | +#define STATUS_SNOOP_MODE (1 << 12) | 79 | + /* write message to sd */ |
91 | +#define STATUS_SLEEP_MODE (1 << 2) | 80 | + fd = open(sd_path, O_WRONLY); |
92 | +#define ISR_TXOK (1 << 1) | 81 | + g_assert(fd >= 0); |
93 | +#define ISR_RXOK (1 << 4) | 82 | + ret = write(fd, msg, len); |
94 | + | 83 | + close(fd); |
95 | +static void match_rx_tx_data(const uint32_t *buf_tx, const uint32_t *buf_rx, | 84 | + g_assert(ret == len); |
96 | + uint8_t can_timestamp) | 85 | + |
97 | +{ | 86 | + /* read message using sdhci */ |
98 | + uint16_t size = 0; | 87 | + ret = sdhci_read_cmd(qts, NPCM7XX_MMC_BA, rmsg, len); |
99 | + uint8_t len = 4; | 88 | + g_assert(ret == len); |
100 | + | 89 | + g_assert(!memcmp(rmsg, msg, len)); |
101 | + while (size < len) { | 90 | + |
102 | + if (R_RXID_OFFSET + 4 * size == R_RXDLC_OFFSET) { | 91 | + g_free(rmsg); |
103 | + g_assert_cmpint(buf_rx[size], ==, buf_tx[size] + can_timestamp); | 92 | +} |
104 | + } else { | 93 | + |
105 | + g_assert_cmpint(buf_rx[size], ==, buf_tx[size]); | 94 | +/* Check MMC can read values from sd */ |
95 | +static void test_read_sd(void) | ||
96 | +{ | ||
97 | + QTestState *qts = setup_sd_card(); | ||
98 | + | ||
99 | + write_sdread(qts, "hello world"); | ||
100 | + write_sdread(qts, "goodbye"); | ||
101 | + | ||
102 | + qtest_quit(qts); | ||
103 | +} | ||
104 | + | ||
105 | +static void sdwrite_read(QTestState *qts, const char *msg) | ||
106 | +{ | ||
107 | + int fd, ret; | ||
108 | + size_t len = strlen(msg); | ||
109 | + char *rmsg = g_malloc(len); | ||
110 | + | ||
111 | + /* write message using sdhci */ | ||
112 | + sdhci_write_cmd(qts, NPCM7XX_MMC_BA, msg, len, NPCM7XX_BLK_SIZE); | ||
113 | + | ||
114 | + /* read message from sd */ | ||
115 | + fd = open(sd_path, O_RDONLY); | ||
116 | + g_assert(fd >= 0); | ||
117 | + ret = read(fd, rmsg, len); | ||
118 | + close(fd); | ||
119 | + g_assert(ret == len); | ||
120 | + | ||
121 | + g_assert(!memcmp(rmsg, msg, len)); | ||
122 | + | ||
123 | + g_free(rmsg); | ||
124 | +} | ||
125 | + | ||
126 | +/* Check MMC can write values to sd */ | ||
127 | +static void test_write_sd(void) | ||
128 | +{ | ||
129 | + QTestState *qts = setup_sd_card(); | ||
130 | + | ||
131 | + sdwrite_read(qts, "hello world"); | ||
132 | + sdwrite_read(qts, "goodbye"); | ||
133 | + | ||
134 | + qtest_quit(qts); | ||
135 | +} | ||
136 | + | ||
137 | +/* Check SDHCI has correct default values. */ | ||
138 | +static void test_reset(void) | ||
139 | +{ | ||
140 | + QTestState *qts = qtest_init("-machine kudo-bmc"); | ||
141 | + uint64_t addr = NPCM7XX_MMC_BA; | ||
142 | + uint64_t end_addr = addr + NPCM7XX_REG_SIZE; | ||
143 | + uint16_t prstvals_resets[] = {NPCM7XX_PRSTVALS_0_RESET, | ||
144 | + NPCM7XX_PRSTVALS_1_RESET, | ||
145 | + 0, | ||
146 | + NPCM7XX_PRSTVALS_3_RESET, | ||
147 | + 0, | ||
148 | + 0}; | ||
149 | + int i; | ||
150 | + uint32_t mask; | ||
151 | + | ||
152 | + while (addr < end_addr) { | ||
153 | + switch (addr - NPCM7XX_MMC_BA) { | ||
154 | + case SDHC_PRNSTS: | ||
155 | + /* | ||
156 | + * ignores bits 20 to 24: they are changed when reading registers | ||
157 | + */ | ||
158 | + mask = 0x1f00000; | ||
159 | + g_assert_cmphex(qtest_readl(qts, addr) | mask, ==, | ||
160 | + NPCM7XX_PRSNTS_RESET | mask); | ||
161 | + addr += 4; | ||
162 | + break; | ||
163 | + case SDHC_BLKGAP: | ||
164 | + g_assert_cmphex(qtest_readb(qts, addr), ==, NPCM7XX_BLKGAP_RESET); | ||
165 | + addr += 1; | ||
166 | + break; | ||
167 | + case SDHC_CAPAB: | ||
168 | + g_assert_cmphex(qtest_readq(qts, addr), ==, NPCM7XX_CAPAB_RESET); | ||
169 | + addr += 8; | ||
170 | + break; | ||
171 | + case SDHC_MAXCURR: | ||
172 | + g_assert_cmphex(qtest_readq(qts, addr), ==, NPCM7XX_MAXCURR_RESET); | ||
173 | + addr += 8; | ||
174 | + break; | ||
175 | + case SDHC_HCVER: | ||
176 | + g_assert_cmphex(qtest_readw(qts, addr), ==, NPCM7XX_HCVER_RESET); | ||
177 | + addr += 2; | ||
178 | + break; | ||
179 | + case NPCM7XX_PRSTVALS: | ||
180 | + for (i = 0; i < NPCM7XX_PRSTVALS_SIZE; ++i) { | ||
181 | + g_assert_cmphex(qtest_readw(qts, addr + 2 * i), ==, | ||
182 | + prstvals_resets[i]); | ||
183 | + } | ||
184 | + addr += NPCM7XX_PRSTVALS_SIZE * 2; | ||
185 | + break; | ||
186 | + default: | ||
187 | + g_assert_cmphex(qtest_readb(qts, addr), ==, 0); | ||
188 | + addr += 1; | ||
106 | + } | 189 | + } |
107 | + | ||
108 | + size++; | ||
109 | + } | 190 | + } |
110 | +} | ||
111 | + | ||
112 | +static void read_data(QTestState *qts, uint64_t can_base_addr, uint32_t *buf_rx) | ||
113 | +{ | ||
114 | + uint32_t int_status; | ||
115 | + | ||
116 | + /* Read the interrupt on CAN rx. */ | ||
117 | + int_status = qtest_readl(qts, can_base_addr + R_ISR_OFFSET) & ISR_RXOK; | ||
118 | + | ||
119 | + g_assert_cmpint(int_status, ==, ISR_RXOK); | ||
120 | + | ||
121 | + /* Read the RX register data for CAN. */ | ||
122 | + buf_rx[0] = qtest_readl(qts, can_base_addr + R_RXID_OFFSET); | ||
123 | + buf_rx[1] = qtest_readl(qts, can_base_addr + R_RXDLC_OFFSET); | ||
124 | + buf_rx[2] = qtest_readl(qts, can_base_addr + R_RXDATA1_OFFSET); | ||
125 | + buf_rx[3] = qtest_readl(qts, can_base_addr + R_RXDATA2_OFFSET); | ||
126 | + | ||
127 | + /* Clear the RX interrupt. */ | ||
128 | + qtest_writel(qts, CAN1_BASE_ADDR + R_ICR_OFFSET, ISR_RXOK); | ||
129 | +} | ||
130 | + | ||
131 | +static void send_data(QTestState *qts, uint64_t can_base_addr, | ||
132 | + const uint32_t *buf_tx) | ||
133 | +{ | ||
134 | + uint32_t int_status; | ||
135 | + | ||
136 | + /* Write the TX register data for CAN. */ | ||
137 | + qtest_writel(qts, can_base_addr + R_TXID_OFFSET, buf_tx[0]); | ||
138 | + qtest_writel(qts, can_base_addr + R_TXDLC_OFFSET, buf_tx[1]); | ||
139 | + qtest_writel(qts, can_base_addr + R_TXDATA1_OFFSET, buf_tx[2]); | ||
140 | + qtest_writel(qts, can_base_addr + R_TXDATA2_OFFSET, buf_tx[3]); | ||
141 | + | ||
142 | + /* Read the interrupt on CAN for tx. */ | ||
143 | + int_status = qtest_readl(qts, can_base_addr + R_ISR_OFFSET) & ISR_TXOK; | ||
144 | + | ||
145 | + g_assert_cmpint(int_status, ==, ISR_TXOK); | ||
146 | + | ||
147 | + /* Clear the interrupt for tx. */ | ||
148 | + qtest_writel(qts, CAN0_BASE_ADDR + R_ICR_OFFSET, ISR_TXOK); | ||
149 | +} | ||
150 | + | ||
151 | +/* | ||
152 | + * This test will be transferring data from CAN0 and CAN1 through canbus. CAN0 | ||
153 | + * initiate the data transfer to can-bus, CAN1 receives the data. Test compares | ||
154 | + * the data sent from CAN0 with received on CAN1. | ||
155 | + */ | ||
156 | +static void test_can_bus(void) | ||
157 | +{ | ||
158 | + const uint32_t buf_tx[4] = { 0xFF, 0x80000000, 0x12345678, 0x87654321 }; | ||
159 | + uint32_t buf_rx[4] = { 0x00, 0x00, 0x00, 0x00 }; | ||
160 | + uint32_t status = 0; | ||
161 | + uint8_t can_timestamp = 1; | ||
162 | + | ||
163 | + QTestState *qts = qtest_init("-machine xlnx-zcu102" | ||
164 | + " -object can-bus,id=canbus0" | ||
165 | + " -machine xlnx-zcu102.canbus0=canbus0" | ||
166 | + " -machine xlnx-zcu102.canbus1=canbus0" | ||
167 | + ); | ||
168 | + | ||
169 | + /* Configure the CAN0 and CAN1. */ | ||
170 | + qtest_writel(qts, CAN0_BASE_ADDR + R_SRR_OFFSET, ENABLE_CAN); | ||
171 | + qtest_writel(qts, CAN0_BASE_ADDR + R_MSR_OFFSET, NORMAL_MODE); | ||
172 | + qtest_writel(qts, CAN1_BASE_ADDR + R_SRR_OFFSET, ENABLE_CAN); | ||
173 | + qtest_writel(qts, CAN1_BASE_ADDR + R_MSR_OFFSET, NORMAL_MODE); | ||
174 | + | ||
175 | + /* Check here if CAN0 and CAN1 are in normal mode. */ | ||
176 | + status = qtest_readl(qts, CAN0_BASE_ADDR + R_SR_OFFSET); | ||
177 | + g_assert_cmpint(status, ==, STATUS_NORMAL_MODE); | ||
178 | + | ||
179 | + status = qtest_readl(qts, CAN1_BASE_ADDR + R_SR_OFFSET); | ||
180 | + g_assert_cmpint(status, ==, STATUS_NORMAL_MODE); | ||
181 | + | ||
182 | + send_data(qts, CAN0_BASE_ADDR, buf_tx); | ||
183 | + | ||
184 | + read_data(qts, CAN1_BASE_ADDR, buf_rx); | ||
185 | + match_rx_tx_data(buf_tx, buf_rx, can_timestamp); | ||
186 | + | 191 | + |
187 | + qtest_quit(qts); | 192 | + qtest_quit(qts); |
188 | +} | 193 | +} |
189 | + | 194 | + |
190 | +/* | 195 | +static void drive_destroy(void) |
191 | + * This test is performing loopback mode on CAN0 and CAN1. Data sent from TX of | 196 | +{ |
192 | + * each CAN0 and CAN1 are compared with RX register data for respective CAN. | 197 | + unlink(sd_path); |
193 | + */ | 198 | + g_free(sd_path); |
194 | +static void test_can_loopback(void) | 199 | +} |
195 | +{ | 200 | + |
196 | + uint32_t buf_tx[4] = { 0xFF, 0x80000000, 0x12345678, 0x87654321 }; | 201 | +static void drive_create(void) |
197 | + uint32_t buf_rx[4] = { 0x00, 0x00, 0x00, 0x00 }; | 202 | +{ |
198 | + uint32_t status = 0; | 203 | + int fd, ret; |
199 | + | 204 | + GError *error = NULL; |
200 | + QTestState *qts = qtest_init("-machine xlnx-zcu102" | 205 | + |
201 | + " -object can-bus,id=canbus0" | 206 | + /* Create a temporary raw image */ |
202 | + " -machine xlnx-zcu102.canbus0=canbus0" | 207 | + fd = g_file_open_tmp("sdhci_XXXXXX", &sd_path, &error); |
203 | + " -machine xlnx-zcu102.canbus1=canbus0" | 208 | + if (fd == -1) { |
204 | + ); | 209 | + fprintf(stderr, "unable to create sdhci file: %s\n", error->message); |
205 | + | 210 | + g_error_free(error); |
206 | + /* Configure the CAN0 in loopback mode. */ | 211 | + } |
207 | + qtest_writel(qts, CAN0_BASE_ADDR + R_SRR_OFFSET, CONFIG_MODE); | 212 | + g_assert(sd_path != NULL); |
208 | + qtest_writel(qts, CAN0_BASE_ADDR + R_MSR_OFFSET, LOOPBACK_MODE); | 213 | + |
209 | + qtest_writel(qts, CAN0_BASE_ADDR + R_SRR_OFFSET, ENABLE_CAN); | 214 | + ret = ftruncate(fd, NPCM7XX_TEST_IMAGE_SIZE); |
210 | + | 215 | + g_assert_cmpint(ret, ==, 0); |
211 | + /* Check here if CAN0 is set in loopback mode. */ | 216 | + g_message("%s", sd_path); |
212 | + status = qtest_readl(qts, CAN0_BASE_ADDR + R_SR_OFFSET); | 217 | + close(fd); |
213 | + | ||
214 | + g_assert_cmpint(status, ==, STATUS_LOOPBACK_MODE); | ||
215 | + | ||
216 | + send_data(qts, CAN0_BASE_ADDR, buf_tx); | ||
217 | + read_data(qts, CAN0_BASE_ADDR, buf_rx); | ||
218 | + match_rx_tx_data(buf_tx, buf_rx, 0); | ||
219 | + | ||
220 | + /* Configure the CAN1 in loopback mode. */ | ||
221 | + qtest_writel(qts, CAN1_BASE_ADDR + R_SRR_OFFSET, CONFIG_MODE); | ||
222 | + qtest_writel(qts, CAN1_BASE_ADDR + R_MSR_OFFSET, LOOPBACK_MODE); | ||
223 | + qtest_writel(qts, CAN1_BASE_ADDR + R_SRR_OFFSET, ENABLE_CAN); | ||
224 | + | ||
225 | + /* Check here if CAN1 is set in loopback mode. */ | ||
226 | + status = qtest_readl(qts, CAN1_BASE_ADDR + R_SR_OFFSET); | ||
227 | + | ||
228 | + g_assert_cmpint(status, ==, STATUS_LOOPBACK_MODE); | ||
229 | + | ||
230 | + send_data(qts, CAN1_BASE_ADDR, buf_tx); | ||
231 | + read_data(qts, CAN1_BASE_ADDR, buf_rx); | ||
232 | + match_rx_tx_data(buf_tx, buf_rx, 0); | ||
233 | + | ||
234 | + qtest_quit(qts); | ||
235 | +} | ||
236 | + | ||
237 | +/* | ||
238 | + * Enable filters for CAN1. This will filter incoming messages with ID. In this | ||
239 | + * test message will pass through filter 2. | ||
240 | + */ | ||
241 | +static void test_can_filter(void) | ||
242 | +{ | ||
243 | + uint32_t buf_tx[4] = { 0x14, 0x80000000, 0x12345678, 0x87654321 }; | ||
244 | + uint32_t buf_rx[4] = { 0x00, 0x00, 0x00, 0x00 }; | ||
245 | + uint32_t status = 0; | ||
246 | + uint8_t can_timestamp = 1; | ||
247 | + | ||
248 | + QTestState *qts = qtest_init("-machine xlnx-zcu102" | ||
249 | + " -object can-bus,id=canbus0" | ||
250 | + " -machine xlnx-zcu102.canbus0=canbus0" | ||
251 | + " -machine xlnx-zcu102.canbus1=canbus0" | ||
252 | + ); | ||
253 | + | ||
254 | + /* Configure the CAN0 and CAN1. */ | ||
255 | + qtest_writel(qts, CAN0_BASE_ADDR + R_SRR_OFFSET, ENABLE_CAN); | ||
256 | + qtest_writel(qts, CAN0_BASE_ADDR + R_MSR_OFFSET, NORMAL_MODE); | ||
257 | + qtest_writel(qts, CAN1_BASE_ADDR + R_SRR_OFFSET, ENABLE_CAN); | ||
258 | + qtest_writel(qts, CAN1_BASE_ADDR + R_MSR_OFFSET, NORMAL_MODE); | ||
259 | + | ||
260 | + /* Check here if CAN0 and CAN1 are in normal mode. */ | ||
261 | + status = qtest_readl(qts, CAN0_BASE_ADDR + R_SR_OFFSET); | ||
262 | + g_assert_cmpint(status, ==, STATUS_NORMAL_MODE); | ||
263 | + | ||
264 | + status = qtest_readl(qts, CAN1_BASE_ADDR + R_SR_OFFSET); | ||
265 | + g_assert_cmpint(status, ==, STATUS_NORMAL_MODE); | ||
266 | + | ||
267 | + /* Set filter for CAN1 for incoming messages. */ | ||
268 | + qtest_writel(qts, CAN1_BASE_ADDR + R_AFR, 0x0); | ||
269 | + qtest_writel(qts, CAN1_BASE_ADDR + R_AFMR1, 0xF7); | ||
270 | + qtest_writel(qts, CAN1_BASE_ADDR + R_AFIR1, 0x121F); | ||
271 | + qtest_writel(qts, CAN1_BASE_ADDR + R_AFMR2, 0x5431); | ||
272 | + qtest_writel(qts, CAN1_BASE_ADDR + R_AFIR2, 0x14); | ||
273 | + qtest_writel(qts, CAN1_BASE_ADDR + R_AFMR3, 0x1234); | ||
274 | + qtest_writel(qts, CAN1_BASE_ADDR + R_AFIR3, 0x5431); | ||
275 | + qtest_writel(qts, CAN1_BASE_ADDR + R_AFMR4, 0xFFF); | ||
276 | + qtest_writel(qts, CAN1_BASE_ADDR + R_AFIR4, 0x1234); | ||
277 | + | ||
278 | + qtest_writel(qts, CAN1_BASE_ADDR + R_AFR, 0xF); | ||
279 | + | ||
280 | + send_data(qts, CAN0_BASE_ADDR, buf_tx); | ||
281 | + | ||
282 | + read_data(qts, CAN1_BASE_ADDR, buf_rx); | ||
283 | + match_rx_tx_data(buf_tx, buf_rx, can_timestamp); | ||
284 | + | ||
285 | + qtest_quit(qts); | ||
286 | +} | ||
287 | + | ||
288 | +/* Testing sleep mode on CAN0 while CAN1 is in normal mode. */ | ||
289 | +static void test_can_sleepmode(void) | ||
290 | +{ | ||
291 | + uint32_t buf_tx[4] = { 0x14, 0x80000000, 0x12345678, 0x87654321 }; | ||
292 | + uint32_t buf_rx[4] = { 0x00, 0x00, 0x00, 0x00 }; | ||
293 | + uint32_t status = 0; | ||
294 | + uint8_t can_timestamp = 1; | ||
295 | + | ||
296 | + QTestState *qts = qtest_init("-machine xlnx-zcu102" | ||
297 | + " -object can-bus,id=canbus0" | ||
298 | + " -machine xlnx-zcu102.canbus0=canbus0" | ||
299 | + " -machine xlnx-zcu102.canbus1=canbus0" | ||
300 | + ); | ||
301 | + | ||
302 | + /* Configure the CAN0. */ | ||
303 | + qtest_writel(qts, CAN0_BASE_ADDR + R_SRR_OFFSET, CONFIG_MODE); | ||
304 | + qtest_writel(qts, CAN0_BASE_ADDR + R_MSR_OFFSET, SLEEP_MODE); | ||
305 | + qtest_writel(qts, CAN0_BASE_ADDR + R_SRR_OFFSET, ENABLE_CAN); | ||
306 | + | ||
307 | + qtest_writel(qts, CAN1_BASE_ADDR + R_SRR_OFFSET, ENABLE_CAN); | ||
308 | + qtest_writel(qts, CAN1_BASE_ADDR + R_MSR_OFFSET, NORMAL_MODE); | ||
309 | + | ||
310 | + /* Check here if CAN0 is in SLEEP mode and CAN1 in normal mode. */ | ||
311 | + status = qtest_readl(qts, CAN0_BASE_ADDR + R_SR_OFFSET); | ||
312 | + g_assert_cmpint(status, ==, STATUS_SLEEP_MODE); | ||
313 | + | ||
314 | + status = qtest_readl(qts, CAN1_BASE_ADDR + R_SR_OFFSET); | ||
315 | + g_assert_cmpint(status, ==, STATUS_NORMAL_MODE); | ||
316 | + | ||
317 | + send_data(qts, CAN1_BASE_ADDR, buf_tx); | ||
318 | + | ||
319 | + /* | ||
320 | + * Once CAN1 sends data on can-bus. CAN0 should exit sleep mode. | ||
321 | + * Check the CAN0 status now. It should exit the sleep mode and receive the | ||
322 | + * incoming data. | ||
323 | + */ | ||
324 | + status = qtest_readl(qts, CAN0_BASE_ADDR + R_SR_OFFSET); | ||
325 | + g_assert_cmpint(status, ==, STATUS_NORMAL_MODE); | ||
326 | + | ||
327 | + read_data(qts, CAN0_BASE_ADDR, buf_rx); | ||
328 | + | ||
329 | + match_rx_tx_data(buf_tx, buf_rx, can_timestamp); | ||
330 | + | ||
331 | + qtest_quit(qts); | ||
332 | +} | ||
333 | + | ||
334 | +/* Testing Snoop mode on CAN0 while CAN1 is in normal mode. */ | ||
335 | +static void test_can_snoopmode(void) | ||
336 | +{ | ||
337 | + uint32_t buf_tx[4] = { 0x14, 0x80000000, 0x12345678, 0x87654321 }; | ||
338 | + uint32_t buf_rx[4] = { 0x00, 0x00, 0x00, 0x00 }; | ||
339 | + uint32_t status = 0; | ||
340 | + uint8_t can_timestamp = 1; | ||
341 | + | ||
342 | + QTestState *qts = qtest_init("-machine xlnx-zcu102" | ||
343 | + " -object can-bus,id=canbus0" | ||
344 | + " -machine xlnx-zcu102.canbus0=canbus0" | ||
345 | + " -machine xlnx-zcu102.canbus1=canbus0" | ||
346 | + ); | ||
347 | + | ||
348 | + /* Configure the CAN0. */ | ||
349 | + qtest_writel(qts, CAN0_BASE_ADDR + R_SRR_OFFSET, CONFIG_MODE); | ||
350 | + qtest_writel(qts, CAN0_BASE_ADDR + R_MSR_OFFSET, SNOOP_MODE); | ||
351 | + qtest_writel(qts, CAN0_BASE_ADDR + R_SRR_OFFSET, ENABLE_CAN); | ||
352 | + | ||
353 | + qtest_writel(qts, CAN1_BASE_ADDR + R_SRR_OFFSET, ENABLE_CAN); | ||
354 | + qtest_writel(qts, CAN1_BASE_ADDR + R_MSR_OFFSET, NORMAL_MODE); | ||
355 | + | ||
356 | + /* Check here if CAN0 is in SNOOP mode and CAN1 in normal mode. */ | ||
357 | + status = qtest_readl(qts, CAN0_BASE_ADDR + R_SR_OFFSET); | ||
358 | + g_assert_cmpint(status, ==, STATUS_SNOOP_MODE); | ||
359 | + | ||
360 | + status = qtest_readl(qts, CAN1_BASE_ADDR + R_SR_OFFSET); | ||
361 | + g_assert_cmpint(status, ==, STATUS_NORMAL_MODE); | ||
362 | + | ||
363 | + send_data(qts, CAN1_BASE_ADDR, buf_tx); | ||
364 | + | ||
365 | + read_data(qts, CAN0_BASE_ADDR, buf_rx); | ||
366 | + | ||
367 | + match_rx_tx_data(buf_tx, buf_rx, can_timestamp); | ||
368 | + | ||
369 | + qtest_quit(qts); | ||
370 | +} | 218 | +} |
371 | + | 219 | + |
372 | +int main(int argc, char **argv) | 220 | +int main(int argc, char **argv) |
373 | +{ | 221 | +{ |
222 | + int ret; | ||
223 | + | ||
224 | + drive_create(); | ||
225 | + | ||
374 | + g_test_init(&argc, &argv, NULL); | 226 | + g_test_init(&argc, &argv, NULL); |
375 | + | 227 | + |
376 | + qtest_add_func("/net/can/can_bus", test_can_bus); | 228 | + qtest_add_func("npcm7xx_sdhci/reset", test_reset); |
377 | + qtest_add_func("/net/can/can_loopback", test_can_loopback); | 229 | + qtest_add_func("npcm7xx_sdhci/write_sd", test_write_sd); |
378 | + qtest_add_func("/net/can/can_filter", test_can_filter); | 230 | + qtest_add_func("npcm7xx_sdhci/read_sd", test_read_sd); |
379 | + qtest_add_func("/net/can/can_test_snoopmode", test_can_snoopmode); | 231 | + |
380 | + qtest_add_func("/net/can/can_test_sleepmode", test_can_sleepmode); | 232 | + ret = g_test_run(); |
381 | + | 233 | + drive_destroy(); |
382 | + return g_test_run(); | 234 | + return ret; |
383 | +} | 235 | +} |
384 | diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build | 236 | diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build |
385 | index XXXXXXX..XXXXXXX 100644 | 237 | index XXXXXXX..XXXXXXX 100644 |
386 | --- a/tests/qtest/meson.build | 238 | --- a/tests/qtest/meson.build |
387 | +++ b/tests/qtest/meson.build | 239 | +++ b/tests/qtest/meson.build |
388 | @@ -XXX,XX +XXX,XX @@ qtests_aarch64 = \ | 240 | @@ -XXX,XX +XXX,XX @@ qtests_npcm7xx = \ |
389 | ['arm-cpu-features', | 241 | 'npcm7xx_gpio-test', |
390 | 'numa-test', | 242 | 'npcm7xx_pwm-test', |
391 | 'boot-serial-test', | 243 | 'npcm7xx_rng-test', |
392 | + 'xlnx-can-test', | 244 | + 'npcm7xx_sdhci-test', |
393 | 'migration-test'] | 245 | 'npcm7xx_smbus-test', |
394 | 246 | 'npcm7xx_timer-test', | |
395 | qtests_s390x = \ | 247 | 'npcm7xx_watchdog_timer-test'] + \ |
396 | -- | 248 | -- |
397 | 2.20.1 | 249 | 2.25.1 |
398 | |||
399 | diff view generated by jsdifflib |
1 | From: Alex Chen <alex.chen@huawei.com> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | We should use printf format specifier "%u" instead of "%d" for | 3 | Add new macros to manipulate signed fields within the register. |
4 | argument of type "unsigned int". | ||
5 | 4 | ||
6 | Reported-by: Euler Robot <euler.robot@huawei.com> | 5 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> |
7 | Signed-off-by: Alex Chen <alex.chen@huawei.com> | 6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
8 | Message-id: 20201126111109.112238-4-alex.chen@huawei.com | 7 | Message-id: 20220301215958.157011-2-richard.henderson@linaro.org |
9 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 8 | Suggested-by: Peter Maydell <peter.maydell@linaro.org> |
9 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
11 | --- | 11 | --- |
12 | hw/misc/imx6_ccm.c | 20 ++++++++++---------- | 12 | include/hw/registerfields.h | 48 ++++++++++++++++++++++++++++++++++++- |
13 | hw/misc/imx6_src.c | 2 +- | 13 | 1 file changed, 47 insertions(+), 1 deletion(-) |
14 | 2 files changed, 11 insertions(+), 11 deletions(-) | ||
15 | 14 | ||
16 | diff --git a/hw/misc/imx6_ccm.c b/hw/misc/imx6_ccm.c | 15 | diff --git a/include/hw/registerfields.h b/include/hw/registerfields.h |
17 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
18 | --- a/hw/misc/imx6_ccm.c | 17 | --- a/include/hw/registerfields.h |
19 | +++ b/hw/misc/imx6_ccm.c | 18 | +++ b/include/hw/registerfields.h |
20 | @@ -XXX,XX +XXX,XX @@ static const char *imx6_ccm_reg_name(uint32_t reg) | 19 | @@ -XXX,XX +XXX,XX @@ |
21 | case CCM_CMEOR: | 20 | extract64((storage), R_ ## reg ## _ ## field ## _SHIFT, \ |
22 | return "CMEOR"; | 21 | R_ ## reg ## _ ## field ## _LENGTH) |
23 | default: | 22 | |
24 | - sprintf(unknown, "%d ?", reg); | 23 | +#define FIELD_SEX8(storage, reg, field) \ |
25 | + sprintf(unknown, "%u ?", reg); | 24 | + sextract8((storage), R_ ## reg ## _ ## field ## _SHIFT, \ |
26 | return unknown; | 25 | + R_ ## reg ## _ ## field ## _LENGTH) |
27 | } | 26 | +#define FIELD_SEX16(storage, reg, field) \ |
28 | } | 27 | + sextract16((storage), R_ ## reg ## _ ## field ## _SHIFT, \ |
29 | @@ -XXX,XX +XXX,XX @@ static const char *imx6_analog_reg_name(uint32_t reg) | 28 | + R_ ## reg ## _ ## field ## _LENGTH) |
30 | case USB_ANALOG_DIGPROG: | 29 | +#define FIELD_SEX32(storage, reg, field) \ |
31 | return "USB_ANALOG_DIGPROG"; | 30 | + sextract32((storage), R_ ## reg ## _ ## field ## _SHIFT, \ |
32 | default: | 31 | + R_ ## reg ## _ ## field ## _LENGTH) |
33 | - sprintf(unknown, "%d ?", reg); | 32 | +#define FIELD_SEX64(storage, reg, field) \ |
34 | + sprintf(unknown, "%u ?", reg); | 33 | + sextract64((storage), R_ ## reg ## _ ## field ## _SHIFT, \ |
35 | return unknown; | 34 | + R_ ## reg ## _ ## field ## _LENGTH) |
36 | } | 35 | + |
37 | } | 36 | /* Extract a field from an array of registers */ |
38 | @@ -XXX,XX +XXX,XX @@ static uint64_t imx6_analog_get_pll2_clk(IMX6CCMState *dev) | 37 | #define ARRAY_FIELD_EX32(regs, reg, field) \ |
39 | freq *= 20; | 38 | FIELD_EX32((regs)[R_ ## reg], reg, field) |
40 | } | 39 | @@ -XXX,XX +XXX,XX @@ |
41 | 40 | _d; }) | |
42 | - DPRINTF("freq = %d\n", (uint32_t)freq); | 41 | #define FIELD_DP64(storage, reg, field, val) ({ \ |
43 | + DPRINTF("freq = %u\n", (uint32_t)freq); | 42 | struct { \ |
44 | 43 | - uint64_t v:R_ ## reg ## _ ## field ## _LENGTH; \ | |
45 | return freq; | 44 | + uint64_t v:R_ ## reg ## _ ## field ## _LENGTH; \ |
46 | } | 45 | + } _v = { .v = val }; \ |
47 | @@ -XXX,XX +XXX,XX @@ static uint64_t imx6_analog_get_pll2_pfd0_clk(IMX6CCMState *dev) | 46 | + uint64_t _d; \ |
48 | freq = imx6_analog_get_pll2_clk(dev) * 18 | 47 | + _d = deposit64((storage), R_ ## reg ## _ ## field ## _SHIFT, \ |
49 | / EXTRACT(dev->analog[CCM_ANALOG_PFD_528], PFD0_FRAC); | 48 | + R_ ## reg ## _ ## field ## _LENGTH, _v.v); \ |
50 | 49 | + _d; }) | |
51 | - DPRINTF("freq = %d\n", (uint32_t)freq); | 50 | + |
52 | + DPRINTF("freq = %u\n", (uint32_t)freq); | 51 | +#define FIELD_SDP8(storage, reg, field, val) ({ \ |
53 | 52 | + struct { \ | |
54 | return freq; | 53 | + signed int v:R_ ## reg ## _ ## field ## _LENGTH; \ |
55 | } | 54 | + } _v = { .v = val }; \ |
56 | @@ -XXX,XX +XXX,XX @@ static uint64_t imx6_analog_get_pll2_pfd2_clk(IMX6CCMState *dev) | 55 | + uint8_t _d; \ |
57 | freq = imx6_analog_get_pll2_clk(dev) * 18 | 56 | + _d = deposit32((storage), R_ ## reg ## _ ## field ## _SHIFT, \ |
58 | / EXTRACT(dev->analog[CCM_ANALOG_PFD_528], PFD2_FRAC); | 57 | + R_ ## reg ## _ ## field ## _LENGTH, _v.v); \ |
59 | 58 | + _d; }) | |
60 | - DPRINTF("freq = %d\n", (uint32_t)freq); | 59 | +#define FIELD_SDP16(storage, reg, field, val) ({ \ |
61 | + DPRINTF("freq = %u\n", (uint32_t)freq); | 60 | + struct { \ |
62 | 61 | + signed int v:R_ ## reg ## _ ## field ## _LENGTH; \ | |
63 | return freq; | 62 | + } _v = { .v = val }; \ |
64 | } | 63 | + uint16_t _d; \ |
65 | @@ -XXX,XX +XXX,XX @@ static uint64_t imx6_analog_get_periph_clk(IMX6CCMState *dev) | 64 | + _d = deposit32((storage), R_ ## reg ## _ ## field ## _SHIFT, \ |
66 | break; | 65 | + R_ ## reg ## _ ## field ## _LENGTH, _v.v); \ |
67 | } | 66 | + _d; }) |
68 | 67 | +#define FIELD_SDP32(storage, reg, field, val) ({ \ | |
69 | - DPRINTF("freq = %d\n", (uint32_t)freq); | 68 | + struct { \ |
70 | + DPRINTF("freq = %u\n", (uint32_t)freq); | 69 | + signed int v:R_ ## reg ## _ ## field ## _LENGTH; \ |
71 | 70 | + } _v = { .v = val }; \ | |
72 | return freq; | 71 | + uint32_t _d; \ |
73 | } | 72 | + _d = deposit32((storage), R_ ## reg ## _ ## field ## _SHIFT, \ |
74 | @@ -XXX,XX +XXX,XX @@ static uint64_t imx6_ccm_get_ahb_clk(IMX6CCMState *dev) | 73 | + R_ ## reg ## _ ## field ## _LENGTH, _v.v); \ |
75 | freq = imx6_analog_get_periph_clk(dev) | 74 | + _d; }) |
76 | / (1 + EXTRACT(dev->ccm[CCM_CBCDR], AHB_PODF)); | 75 | +#define FIELD_SDP64(storage, reg, field, val) ({ \ |
77 | 76 | + struct { \ | |
78 | - DPRINTF("freq = %d\n", (uint32_t)freq); | 77 | + int64_t v:R_ ## reg ## _ ## field ## _LENGTH; \ |
79 | + DPRINTF("freq = %u\n", (uint32_t)freq); | 78 | } _v = { .v = val }; \ |
80 | 79 | uint64_t _d; \ | |
81 | return freq; | 80 | _d = deposit64((storage), R_ ## reg ## _ ## field ## _SHIFT, \ |
82 | } | ||
83 | @@ -XXX,XX +XXX,XX @@ static uint64_t imx6_ccm_get_ipg_clk(IMX6CCMState *dev) | ||
84 | freq = imx6_ccm_get_ahb_clk(dev) | ||
85 | / (1 + EXTRACT(dev->ccm[CCM_CBCDR], IPG_PODF)); | ||
86 | |||
87 | - DPRINTF("freq = %d\n", (uint32_t)freq); | ||
88 | + DPRINTF("freq = %u\n", (uint32_t)freq); | ||
89 | |||
90 | return freq; | ||
91 | } | ||
92 | @@ -XXX,XX +XXX,XX @@ static uint64_t imx6_ccm_get_per_clk(IMX6CCMState *dev) | ||
93 | freq = imx6_ccm_get_ipg_clk(dev) | ||
94 | / (1 + EXTRACT(dev->ccm[CCM_CSCMR1], PERCLK_PODF)); | ||
95 | |||
96 | - DPRINTF("freq = %d\n", (uint32_t)freq); | ||
97 | + DPRINTF("freq = %u\n", (uint32_t)freq); | ||
98 | |||
99 | return freq; | ||
100 | } | ||
101 | @@ -XXX,XX +XXX,XX @@ static uint32_t imx6_ccm_get_clock_frequency(IMXCCMState *dev, IMXClk clock) | ||
102 | break; | ||
103 | } | ||
104 | |||
105 | - DPRINTF("Clock = %d) = %d\n", clock, freq); | ||
106 | + DPRINTF("Clock = %d) = %u\n", clock, freq); | ||
107 | |||
108 | return freq; | ||
109 | } | ||
110 | diff --git a/hw/misc/imx6_src.c b/hw/misc/imx6_src.c | ||
111 | index XXXXXXX..XXXXXXX 100644 | ||
112 | --- a/hw/misc/imx6_src.c | ||
113 | +++ b/hw/misc/imx6_src.c | ||
114 | @@ -XXX,XX +XXX,XX @@ static const char *imx6_src_reg_name(uint32_t reg) | ||
115 | case SRC_GPR10: | ||
116 | return "SRC_GPR10"; | ||
117 | default: | ||
118 | - sprintf(unknown, "%d ?", reg); | ||
119 | + sprintf(unknown, "%u ?", reg); | ||
120 | return unknown; | ||
121 | } | ||
122 | } | ||
123 | -- | 81 | -- |
124 | 2.20.1 | 82 | 2.25.1 |
125 | 83 | ||
126 | 84 | diff view generated by jsdifflib |
1 | The FPDSCR register has a similar layout to the FPSCR. In v8.1M it | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | gains new fields FZ16 (if half-precision floating point is supported) | ||
3 | and LTPSIZE (always reads as 4). Update the reset value and the code | ||
4 | that handles writes to this register accordingly. | ||
5 | 2 | ||
3 | Set this as the kernel would, to 48 bits, to keep the computation | ||
4 | of the address space correct for PAuth. | ||
5 | |||
6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Message-id: 20220301215958.157011-3-richard.henderson@linaro.org | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Message-id: 20201119215617.29887-16-peter.maydell@linaro.org | ||
9 | --- | 10 | --- |
10 | target/arm/cpu.h | 5 +++++ | 11 | target/arm/cpu.c | 3 ++- |
11 | hw/intc/armv7m_nvic.c | 9 ++++++++- | 12 | 1 file changed, 2 insertions(+), 1 deletion(-) |
12 | target/arm/cpu.c | 3 +++ | ||
13 | 3 files changed, 16 insertions(+), 1 deletion(-) | ||
14 | 13 | ||
15 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | ||
16 | index XXXXXXX..XXXXXXX 100644 | ||
17 | --- a/target/arm/cpu.h | ||
18 | +++ b/target/arm/cpu.h | ||
19 | @@ -XXX,XX +XXX,XX @@ void vfp_set_fpscr(CPUARMState *env, uint32_t val); | ||
20 | #define FPCR_IXE (1 << 12) /* Inexact exception trap enable */ | ||
21 | #define FPCR_IDE (1 << 15) /* Input Denormal exception trap enable */ | ||
22 | #define FPCR_FZ16 (1 << 19) /* ARMv8.2+, FP16 flush-to-zero */ | ||
23 | +#define FPCR_RMODE_MASK (3 << 22) /* Rounding mode */ | ||
24 | #define FPCR_FZ (1 << 24) /* Flush-to-zero enable bit */ | ||
25 | #define FPCR_DN (1 << 25) /* Default NaN enable bit */ | ||
26 | +#define FPCR_AHP (1 << 26) /* Alternative half-precision */ | ||
27 | #define FPCR_QC (1 << 27) /* Cumulative saturation bit */ | ||
28 | #define FPCR_V (1 << 28) /* FP overflow flag */ | ||
29 | #define FPCR_C (1 << 29) /* FP carry flag */ | ||
30 | #define FPCR_Z (1 << 30) /* FP zero flag */ | ||
31 | #define FPCR_N (1 << 31) /* FP negative flag */ | ||
32 | |||
33 | +#define FPCR_LTPSIZE_SHIFT 16 /* LTPSIZE, M-profile only */ | ||
34 | +#define FPCR_LTPSIZE_MASK (7 << FPCR_LTPSIZE_SHIFT) | ||
35 | + | ||
36 | #define FPCR_NZCV_MASK (FPCR_N | FPCR_Z | FPCR_C | FPCR_V) | ||
37 | #define FPCR_NZCVQC_MASK (FPCR_NZCV_MASK | FPCR_QC) | ||
38 | |||
39 | diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c | ||
40 | index XXXXXXX..XXXXXXX 100644 | ||
41 | --- a/hw/intc/armv7m_nvic.c | ||
42 | +++ b/hw/intc/armv7m_nvic.c | ||
43 | @@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value, | ||
44 | break; | ||
45 | case 0xf3c: /* FPDSCR */ | ||
46 | if (cpu_isar_feature(aa32_vfp_simd, cpu)) { | ||
47 | - value &= 0x07c00000; | ||
48 | + uint32_t mask = FPCR_AHP | FPCR_DN | FPCR_FZ | FPCR_RMODE_MASK; | ||
49 | + if (cpu_isar_feature(any_fp16, cpu)) { | ||
50 | + mask |= FPCR_FZ16; | ||
51 | + } | ||
52 | + value &= mask; | ||
53 | + if (cpu_isar_feature(aa32_lob, cpu)) { | ||
54 | + value |= 4 << FPCR_LTPSIZE_SHIFT; | ||
55 | + } | ||
56 | cpu->env.v7m.fpdscr[attrs.secure] = value; | ||
57 | } | ||
58 | break; | ||
59 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c | 14 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c |
60 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
61 | --- a/target/arm/cpu.c | 16 | --- a/target/arm/cpu.c |
62 | +++ b/target/arm/cpu.c | 17 | +++ b/target/arm/cpu.c |
63 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(DeviceState *dev) | 18 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(DeviceState *dev) |
64 | * always reset to 4. | 19 | aarch64_sve_zcr_get_valid_len(cpu, cpu->sve_default_vq - 1); |
65 | */ | ||
66 | env->v7m.ltpsize = 4; | ||
67 | + /* The LTPSIZE field in FPDSCR is constant and reads as 4. */ | ||
68 | + env->v7m.fpdscr[M_REG_NS] = 4 << FPCR_LTPSIZE_SHIFT; | ||
69 | + env->v7m.fpdscr[M_REG_S] = 4 << FPCR_LTPSIZE_SHIFT; | ||
70 | } | 20 | } |
71 | 21 | /* | |
72 | if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { | 22 | + * Enable 48-bit address space (TODO: take reserved_va into account). |
23 | * Enable TBI0 but not TBI1. | ||
24 | * Note that this must match useronly_clean_ptr. | ||
25 | */ | ||
26 | - env->cp15.tcr_el[1].raw_tcr = (1ULL << 37); | ||
27 | + env->cp15.tcr_el[1].raw_tcr = 5 | (1ULL << 37); | ||
28 | |||
29 | /* Enable MTE */ | ||
30 | if (cpu_isar_feature(aa64_mte, cpu)) { | ||
73 | -- | 31 | -- |
74 | 2.20.1 | 32 | 2.25.1 |
75 | |||
76 | diff view generated by jsdifflib |
1 | v8.1M introduces a new TRD flag in the CCR register, which enables | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | checking for stack frame integrity signatures on SG instructions. | ||
3 | Add the code in the SG insn implementation for the new behaviour. | ||
4 | 2 | ||
3 | Without FEAT_LVA, the behaviour of programming an invalid value | ||
4 | is IMPLEMENTATION DEFINED. With FEAT_LVA, programming an invalid | ||
5 | minimum value requires a Translation fault. | ||
6 | |||
7 | It is most self-consistent to choose to generate the fault always. | ||
8 | |||
9 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
10 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
11 | Message-id: 20220301215958.157011-4-richard.henderson@linaro.org | ||
5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Message-id: 20201119215617.29887-24-peter.maydell@linaro.org | ||
8 | --- | 13 | --- |
9 | target/arm/m_helper.c | 86 +++++++++++++++++++++++++++++++++++++++++++ | 14 | target/arm/internals.h | 1 + |
10 | 1 file changed, 86 insertions(+) | 15 | target/arm/helper.c | 32 ++++++++++++++++++++++++++++---- |
16 | 2 files changed, 29 insertions(+), 4 deletions(-) | ||
11 | 17 | ||
12 | diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c | 18 | diff --git a/target/arm/internals.h b/target/arm/internals.h |
13 | index XXXXXXX..XXXXXXX 100644 | 19 | index XXXXXXX..XXXXXXX 100644 |
14 | --- a/target/arm/m_helper.c | 20 | --- a/target/arm/internals.h |
15 | +++ b/target/arm/m_helper.c | 21 | +++ b/target/arm/internals.h |
16 | @@ -XXX,XX +XXX,XX @@ static bool v7m_read_half_insn(ARMCPU *cpu, ARMMMUIdx mmu_idx, | 22 | @@ -XXX,XX +XXX,XX @@ typedef struct ARMVAParameters { |
17 | return true; | 23 | bool hpd : 1; |
24 | bool using16k : 1; | ||
25 | bool using64k : 1; | ||
26 | + bool tsz_oob : 1; /* tsz has been clamped to legal range */ | ||
27 | } ARMVAParameters; | ||
28 | |||
29 | ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, | ||
30 | diff --git a/target/arm/helper.c b/target/arm/helper.c | ||
31 | index XXXXXXX..XXXXXXX 100644 | ||
32 | --- a/target/arm/helper.c | ||
33 | +++ b/target/arm/helper.c | ||
34 | @@ -XXX,XX +XXX,XX @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, | ||
35 | ARMMMUIdx mmu_idx, bool data) | ||
36 | { | ||
37 | uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr; | ||
38 | - bool epd, hpd, using16k, using64k; | ||
39 | - int select, tsz, tbi, max_tsz; | ||
40 | + bool epd, hpd, using16k, using64k, tsz_oob; | ||
41 | + int select, tsz, tbi, max_tsz, min_tsz; | ||
42 | |||
43 | if (!regime_has_2_ranges(mmu_idx)) { | ||
44 | select = 0; | ||
45 | @@ -XXX,XX +XXX,XX @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, | ||
46 | } else { | ||
47 | max_tsz = 39; | ||
48 | } | ||
49 | + min_tsz = 16; /* TODO: ARMv8.2-LVA */ | ||
50 | |||
51 | - tsz = MIN(tsz, max_tsz); | ||
52 | - tsz = MAX(tsz, 16); /* TODO: ARMv8.2-LVA */ | ||
53 | + if (tsz > max_tsz) { | ||
54 | + tsz = max_tsz; | ||
55 | + tsz_oob = true; | ||
56 | + } else if (tsz < min_tsz) { | ||
57 | + tsz = min_tsz; | ||
58 | + tsz_oob = true; | ||
59 | + } else { | ||
60 | + tsz_oob = false; | ||
61 | + } | ||
62 | |||
63 | /* Present TBI as a composite with TBID. */ | ||
64 | tbi = aa64_va_parameter_tbi(tcr, mmu_idx); | ||
65 | @@ -XXX,XX +XXX,XX @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, | ||
66 | .hpd = hpd, | ||
67 | .using16k = using16k, | ||
68 | .using64k = using64k, | ||
69 | + .tsz_oob = tsz_oob, | ||
70 | }; | ||
18 | } | 71 | } |
19 | 72 | ||
20 | +static bool v7m_read_sg_stack_word(ARMCPU *cpu, ARMMMUIdx mmu_idx, | 73 | @@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, |
21 | + uint32_t addr, uint32_t *spdata) | 74 | param = aa64_va_parameters(env, address, mmu_idx, |
22 | +{ | 75 | access_type != MMU_INST_FETCH); |
23 | + /* | 76 | level = 0; |
24 | + * Read a word of data from the stack for the SG instruction, | ||
25 | + * writing the value into *spdata. If the load succeeds, return | ||
26 | + * true; otherwise pend an appropriate exception and return false. | ||
27 | + * (We can't use data load helpers here that throw an exception | ||
28 | + * because of the context we're called in, which is halfway through | ||
29 | + * arm_v7m_cpu_do_interrupt().) | ||
30 | + */ | ||
31 | + CPUState *cs = CPU(cpu); | ||
32 | + CPUARMState *env = &cpu->env; | ||
33 | + MemTxAttrs attrs = {}; | ||
34 | + MemTxResult txres; | ||
35 | + target_ulong page_size; | ||
36 | + hwaddr physaddr; | ||
37 | + int prot; | ||
38 | + ARMMMUFaultInfo fi = {}; | ||
39 | + ARMCacheAttrs cacheattrs = {}; | ||
40 | + uint32_t value; | ||
41 | + | ||
42 | + if (get_phys_addr(env, addr, MMU_DATA_LOAD, mmu_idx, &physaddr, | ||
43 | + &attrs, &prot, &page_size, &fi, &cacheattrs)) { | ||
44 | + /* MPU/SAU lookup failed */ | ||
45 | + if (fi.type == ARMFault_QEMU_SFault) { | ||
46 | + qemu_log_mask(CPU_LOG_INT, | ||
47 | + "...SecureFault during stack word read\n"); | ||
48 | + env->v7m.sfsr |= R_V7M_SFSR_AUVIOL_MASK | R_V7M_SFSR_SFARVALID_MASK; | ||
49 | + env->v7m.sfar = addr; | ||
50 | + armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SECURE, false); | ||
51 | + } else { | ||
52 | + qemu_log_mask(CPU_LOG_INT, | ||
53 | + "...MemManageFault during stack word read\n"); | ||
54 | + env->v7m.cfsr[M_REG_S] |= R_V7M_CFSR_DACCVIOL_MASK | | ||
55 | + R_V7M_CFSR_MMARVALID_MASK; | ||
56 | + env->v7m.mmfar[M_REG_S] = addr; | ||
57 | + armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM, false); | ||
58 | + } | ||
59 | + return false; | ||
60 | + } | ||
61 | + value = address_space_ldl(arm_addressspace(cs, attrs), physaddr, | ||
62 | + attrs, &txres); | ||
63 | + if (txres != MEMTX_OK) { | ||
64 | + /* BusFault trying to read the data */ | ||
65 | + qemu_log_mask(CPU_LOG_INT, | ||
66 | + "...BusFault during stack word read\n"); | ||
67 | + env->v7m.cfsr[M_REG_NS] |= | ||
68 | + (R_V7M_CFSR_PRECISERR_MASK | R_V7M_CFSR_BFARVALID_MASK); | ||
69 | + env->v7m.bfar = addr; | ||
70 | + armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_BUS, false); | ||
71 | + return false; | ||
72 | + } | ||
73 | + | ||
74 | + *spdata = value; | ||
75 | + return true; | ||
76 | +} | ||
77 | + | ||
78 | static bool v7m_handle_execute_nsc(ARMCPU *cpu) | ||
79 | { | ||
80 | /* | ||
81 | @@ -XXX,XX +XXX,XX @@ static bool v7m_handle_execute_nsc(ARMCPU *cpu) | ||
82 | */ | ||
83 | qemu_log_mask(CPU_LOG_INT, "...really an SG instruction at 0x%08" PRIx32 | ||
84 | ", executing it\n", env->regs[15]); | ||
85 | + | ||
86 | + if (cpu_isar_feature(aa32_m_sec_state, cpu) && | ||
87 | + !arm_v7m_is_handler_mode(env)) { | ||
88 | + /* | ||
89 | + * v8.1M exception stack frame integrity check. Note that we | ||
90 | + * must perform the memory access even if CCR_S.TRD is zero | ||
91 | + * and we aren't going to check what the data loaded is. | ||
92 | + */ | ||
93 | + uint32_t spdata, sp; | ||
94 | + | 77 | + |
95 | + /* | 78 | + /* |
96 | + * We know we are currently NS, so the S stack pointers must be | 79 | + * If TxSZ is programmed to a value larger than the maximum, |
97 | + * in other_ss_{psp,msp}, not in regs[13]/other_sp. | 80 | + * or smaller than the effective minimum, it is IMPLEMENTATION |
81 | + * DEFINED whether we behave as if the field were programmed | ||
82 | + * within bounds, or if a level 0 Translation fault is generated. | ||
83 | + * | ||
84 | + * With FEAT_LVA, fault on less than minimum becomes required, | ||
85 | + * so our choice is to always raise the fault. | ||
98 | + */ | 86 | + */ |
99 | + sp = v7m_using_psp(env) ? env->v7m.other_ss_psp : env->v7m.other_ss_msp; | 87 | + if (param.tsz_oob) { |
100 | + if (!v7m_read_sg_stack_word(cpu, mmu_idx, sp, &spdata)) { | 88 | + fault_type = ARMFault_Translation; |
101 | + /* Stack access failed and an exception has been pended */ | 89 | + goto do_fault; |
102 | + return false; | ||
103 | + } | 90 | + } |
104 | + | 91 | + |
105 | + if (env->v7m.ccr[M_REG_S] & R_V7M_CCR_TRD_MASK) { | 92 | addrsize = 64 - 8 * param.tbi; |
106 | + if (((spdata & ~1) == 0xfefa125a) || | 93 | inputsize = 64 - param.tsz; |
107 | + !(env->v7m.control[M_REG_S] & 1)) { | 94 | } else { |
108 | + goto gen_invep; | ||
109 | + } | ||
110 | + } | ||
111 | + } | ||
112 | + | ||
113 | env->regs[14] &= ~1; | ||
114 | env->v7m.control[M_REG_S] &= ~R_V7M_CONTROL_SFPA_MASK; | ||
115 | switch_v7m_security_state(env, true); | ||
116 | -- | 95 | -- |
117 | 2.20.1 | 96 | 2.25.1 |
118 | |||
119 | diff view generated by jsdifflib |
1 | From: Vikram Garhwal <fnu.vikram@xilinx.com> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | The Xilinx ZynqMP CAN controller is developed based on SocketCAN, QEMU CAN bus | 3 | We will shortly share parts of this function with other portions |
4 | implementation. Bus connection and socketCAN connection for each CAN module | 4 | of address translation. |
5 | can be set through command lines. | ||
6 | 5 | ||
7 | Example for using single CAN: | ||
8 | -object can-bus,id=canbus0 \ | ||
9 | -machine xlnx-zcu102.canbus0=canbus0 \ | ||
10 | -object can-host-socketcan,id=socketcan0,if=vcan0,canbus=canbus0 | ||
11 | |||
12 | Example for connecting both CAN to same virtual CAN on host machine: | ||
13 | -object can-bus,id=canbus0 -object can-bus,id=canbus1 \ | ||
14 | -machine xlnx-zcu102.canbus0=canbus0 \ | ||
15 | -machine xlnx-zcu102.canbus1=canbus1 \ | ||
16 | -object can-host-socketcan,id=socketcan0,if=vcan0,canbus=canbus0 \ | ||
17 | -object can-host-socketcan,id=socketcan1,if=vcan0,canbus=canbus1 | ||
18 | |||
19 | To create virtual CAN on the host machine, please check the QEMU CAN docs: | ||
20 | https://github.com/qemu/qemu/blob/master/docs/can.txt | ||
21 | |||
22 | Signed-off-by: Vikram Garhwal <fnu.vikram@xilinx.com> | ||
23 | Message-id: 1605728926-352690-2-git-send-email-fnu.vikram@xilinx.com | ||
24 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
7 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | ||
8 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
9 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
10 | Message-id: 20220301215958.157011-5-richard.henderson@linaro.org | ||
25 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
26 | --- | 12 | --- |
27 | meson.build | 1 + | 13 | target/arm/internals.h | 19 +------------------ |
28 | hw/net/can/trace.h | 1 + | 14 | target/arm/helper.c | 22 ++++++++++++++++++++++ |
29 | include/hw/net/xlnx-zynqmp-can.h | 78 ++ | 15 | 2 files changed, 23 insertions(+), 18 deletions(-) |
30 | hw/net/can/xlnx-zynqmp-can.c | 1161 ++++++++++++++++++++++++++++++ | ||
31 | hw/Kconfig | 1 + | ||
32 | hw/net/can/meson.build | 1 + | ||
33 | hw/net/can/trace-events | 9 + | ||
34 | 7 files changed, 1252 insertions(+) | ||
35 | create mode 100644 hw/net/can/trace.h | ||
36 | create mode 100644 include/hw/net/xlnx-zynqmp-can.h | ||
37 | create mode 100644 hw/net/can/xlnx-zynqmp-can.c | ||
38 | create mode 100644 hw/net/can/trace-events | ||
39 | 16 | ||
40 | diff --git a/meson.build b/meson.build | 17 | diff --git a/target/arm/internals.h b/target/arm/internals.h |
41 | index XXXXXXX..XXXXXXX 100644 | 18 | index XXXXXXX..XXXXXXX 100644 |
42 | --- a/meson.build | 19 | --- a/target/arm/internals.h |
43 | +++ b/meson.build | 20 | +++ b/target/arm/internals.h |
44 | @@ -XXX,XX +XXX,XX @@ if have_system | 21 | @@ -XXX,XX +XXX,XX @@ static inline void update_spsel(CPUARMState *env, uint32_t imm) |
45 | 'hw/misc', | 22 | * Returns the implementation defined bit-width of physical addresses. |
46 | 'hw/misc/macio', | 23 | * The ARMv8 reference manuals refer to this as PAMax(). |
47 | 'hw/net', | 24 | */ |
48 | + 'hw/net/can', | 25 | -static inline unsigned int arm_pamax(ARMCPU *cpu) |
49 | 'hw/nvram', | 26 | -{ |
50 | 'hw/pci', | 27 | - static const unsigned int pamax_map[] = { |
51 | 'hw/pci-host', | 28 | - [0] = 32, |
52 | diff --git a/hw/net/can/trace.h b/hw/net/can/trace.h | 29 | - [1] = 36, |
53 | new file mode 100644 | 30 | - [2] = 40, |
54 | index XXXXXXX..XXXXXXX | 31 | - [3] = 42, |
55 | --- /dev/null | 32 | - [4] = 44, |
56 | +++ b/hw/net/can/trace.h | 33 | - [5] = 48, |
57 | @@ -0,0 +1 @@ | 34 | - }; |
58 | +#include "trace/trace-hw_net_can.h" | 35 | - unsigned int parange = |
59 | diff --git a/include/hw/net/xlnx-zynqmp-can.h b/include/hw/net/xlnx-zynqmp-can.h | 36 | - FIELD_EX64(cpu->isar.id_aa64mmfr0, ID_AA64MMFR0, PARANGE); |
60 | new file mode 100644 | 37 | - |
61 | index XXXXXXX..XXXXXXX | 38 | - /* id_aa64mmfr0 is a read-only register so values outside of the |
62 | --- /dev/null | 39 | - * supported mappings can be considered an implementation error. */ |
63 | +++ b/include/hw/net/xlnx-zynqmp-can.h | 40 | - assert(parange < ARRAY_SIZE(pamax_map)); |
64 | @@ -XXX,XX +XXX,XX @@ | 41 | - return pamax_map[parange]; |
65 | +/* | 42 | -} |
66 | + * QEMU model of the Xilinx ZynqMP CAN controller. | 43 | +unsigned int arm_pamax(ARMCPU *cpu); |
67 | + * | 44 | |
68 | + * Copyright (c) 2020 Xilinx Inc. | 45 | /* Return true if extended addresses are enabled. |
69 | + * | 46 | * This is always the case if our translation regime is 64 bit, |
70 | + * Written-by: Vikram Garhwal<fnu.vikram@xilinx.com> | 47 | diff --git a/target/arm/helper.c b/target/arm/helper.c |
71 | + * | 48 | index XXXXXXX..XXXXXXX 100644 |
72 | + * Based on QEMU CAN Device emulation implemented by Jin Yang, Deniz Eren and | 49 | --- a/target/arm/helper.c |
73 | + * Pavel Pisa. | 50 | +++ b/target/arm/helper.c |
74 | + * | 51 | @@ -XXX,XX +XXX,XX @@ static uint8_t convert_stage2_attrs(CPUARMState *env, uint8_t s2attrs) |
75 | + * Permission is hereby granted, free of charge, to any person obtaining a copy | 52 | } |
76 | + * of this software and associated documentation files (the "Software"), to deal | 53 | #endif /* !CONFIG_USER_ONLY */ |
77 | + * in the Software without restriction, including without limitation the rights | 54 | |
78 | + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | 55 | +/* The cpu-specific constant value of PAMax; also used by hw/arm/virt. */ |
79 | + * copies of the Software, and to permit persons to whom the Software is | 56 | +unsigned int arm_pamax(ARMCPU *cpu) |
80 | + * furnished to do so, subject to the following conditions: | 57 | +{ |
81 | + * | 58 | + static const unsigned int pamax_map[] = { |
82 | + * The above copyright notice and this permission notice shall be included in | 59 | + [0] = 32, |
83 | + * all copies or substantial portions of the Software. | 60 | + [1] = 36, |
84 | + * | 61 | + [2] = 40, |
85 | + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | 62 | + [3] = 42, |
86 | + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | 63 | + [4] = 44, |
87 | + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | 64 | + [5] = 48, |
88 | + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | 65 | + }; |
89 | + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | 66 | + unsigned int parange = |
90 | + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | 67 | + FIELD_EX64(cpu->isar.id_aa64mmfr0, ID_AA64MMFR0, PARANGE); |
91 | + * THE SOFTWARE. | ||
92 | + */ | ||
93 | + | 68 | + |
94 | +#ifndef XLNX_ZYNQMP_CAN_H | 69 | + /* |
95 | +#define XLNX_ZYNQMP_CAN_H | 70 | + * id_aa64mmfr0 is a read-only register so values outside of the |
96 | + | 71 | + * supported mappings can be considered an implementation error. |
97 | +#include "hw/register.h" | 72 | + */ |
98 | +#include "net/can_emu.h" | 73 | + assert(parange < ARRAY_SIZE(pamax_map)); |
99 | +#include "net/can_host.h" | 74 | + return pamax_map[parange]; |
100 | +#include "qemu/fifo32.h" | ||
101 | +#include "hw/ptimer.h" | ||
102 | +#include "hw/qdev-clock.h" | ||
103 | + | ||
104 | +#define TYPE_XLNX_ZYNQMP_CAN "xlnx.zynqmp-can" | ||
105 | + | ||
106 | +#define XLNX_ZYNQMP_CAN(obj) \ | ||
107 | + OBJECT_CHECK(XlnxZynqMPCANState, (obj), TYPE_XLNX_ZYNQMP_CAN) | ||
108 | + | ||
109 | +#define MAX_CAN_CTRLS 2 | ||
110 | +#define XLNX_ZYNQMP_CAN_R_MAX (0x84 / 4) | ||
111 | +#define MAILBOX_CAPACITY 64 | ||
112 | +#define CAN_TIMER_MAX 0XFFFFUL | ||
113 | +#define CAN_DEFAULT_CLOCK (24 * 1000 * 1000) | ||
114 | + | ||
115 | +/* Each CAN_FRAME will have 4 * 32bit size. */ | ||
116 | +#define CAN_FRAME_SIZE 4 | ||
117 | +#define RXFIFO_SIZE (MAILBOX_CAPACITY * CAN_FRAME_SIZE) | ||
118 | + | ||
119 | +typedef struct XlnxZynqMPCANState { | ||
120 | + SysBusDevice parent_obj; | ||
121 | + MemoryRegion iomem; | ||
122 | + | ||
123 | + qemu_irq irq; | ||
124 | + | ||
125 | + CanBusClientState bus_client; | ||
126 | + CanBusState *canbus; | ||
127 | + | ||
128 | + struct { | ||
129 | + uint32_t ext_clk_freq; | ||
130 | + } cfg; | ||
131 | + | ||
132 | + RegisterInfo reg_info[XLNX_ZYNQMP_CAN_R_MAX]; | ||
133 | + uint32_t regs[XLNX_ZYNQMP_CAN_R_MAX]; | ||
134 | + | ||
135 | + Fifo32 rx_fifo; | ||
136 | + Fifo32 tx_fifo; | ||
137 | + Fifo32 txhpb_fifo; | ||
138 | + | ||
139 | + ptimer_state *can_timer; | ||
140 | +} XlnxZynqMPCANState; | ||
141 | + | ||
142 | +#endif | ||
143 | diff --git a/hw/net/can/xlnx-zynqmp-can.c b/hw/net/can/xlnx-zynqmp-can.c | ||
144 | new file mode 100644 | ||
145 | index XXXXXXX..XXXXXXX | ||
146 | --- /dev/null | ||
147 | +++ b/hw/net/can/xlnx-zynqmp-can.c | ||
148 | @@ -XXX,XX +XXX,XX @@ | ||
149 | +/* | ||
150 | + * QEMU model of the Xilinx ZynqMP CAN controller. | ||
151 | + * This implementation is based on the following datasheet: | ||
152 | + * https://www.xilinx.com/support/documentation/user_guides/ug1085-zynq-ultrascale-trm.pdf | ||
153 | + * | ||
154 | + * Copyright (c) 2020 Xilinx Inc. | ||
155 | + * | ||
156 | + * Written-by: Vikram Garhwal<fnu.vikram@xilinx.com> | ||
157 | + * | ||
158 | + * Based on QEMU CAN Device emulation implemented by Jin Yang, Deniz Eren and | ||
159 | + * Pavel Pisa | ||
160 | + * | ||
161 | + * Permission is hereby granted, free of charge, to any person obtaining a copy | ||
162 | + * of this software and associated documentation files (the "Software"), to deal | ||
163 | + * in the Software without restriction, including without limitation the rights | ||
164 | + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | ||
165 | + * copies of the Software, and to permit persons to whom the Software is | ||
166 | + * furnished to do so, subject to the following conditions: | ||
167 | + * | ||
168 | + * The above copyright notice and this permission notice shall be included in | ||
169 | + * all copies or substantial portions of the Software. | ||
170 | + * | ||
171 | + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
172 | + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
173 | + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
174 | + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
175 | + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | ||
176 | + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | ||
177 | + * THE SOFTWARE. | ||
178 | + */ | ||
179 | + | ||
180 | +#include "qemu/osdep.h" | ||
181 | +#include "hw/sysbus.h" | ||
182 | +#include "hw/register.h" | ||
183 | +#include "hw/irq.h" | ||
184 | +#include "qapi/error.h" | ||
185 | +#include "qemu/bitops.h" | ||
186 | +#include "qemu/log.h" | ||
187 | +#include "qemu/cutils.h" | ||
188 | +#include "sysemu/sysemu.h" | ||
189 | +#include "migration/vmstate.h" | ||
190 | +#include "hw/qdev-properties.h" | ||
191 | +#include "net/can_emu.h" | ||
192 | +#include "net/can_host.h" | ||
193 | +#include "qemu/event_notifier.h" | ||
194 | +#include "qom/object_interfaces.h" | ||
195 | +#include "hw/net/xlnx-zynqmp-can.h" | ||
196 | +#include "trace.h" | ||
197 | + | ||
198 | +#ifndef XLNX_ZYNQMP_CAN_ERR_DEBUG | ||
199 | +#define XLNX_ZYNQMP_CAN_ERR_DEBUG 0 | ||
200 | +#endif | ||
201 | + | ||
202 | +#define MAX_DLC 8 | ||
203 | +#undef ERROR | ||
204 | + | ||
205 | +REG32(SOFTWARE_RESET_REGISTER, 0x0) | ||
206 | + FIELD(SOFTWARE_RESET_REGISTER, CEN, 1, 1) | ||
207 | + FIELD(SOFTWARE_RESET_REGISTER, SRST, 0, 1) | ||
208 | +REG32(MODE_SELECT_REGISTER, 0x4) | ||
209 | + FIELD(MODE_SELECT_REGISTER, SNOOP, 2, 1) | ||
210 | + FIELD(MODE_SELECT_REGISTER, LBACK, 1, 1) | ||
211 | + FIELD(MODE_SELECT_REGISTER, SLEEP, 0, 1) | ||
212 | +REG32(ARBITRATION_PHASE_BAUD_RATE_PRESCALER_REGISTER, 0x8) | ||
213 | + FIELD(ARBITRATION_PHASE_BAUD_RATE_PRESCALER_REGISTER, BRP, 0, 8) | ||
214 | +REG32(ARBITRATION_PHASE_BIT_TIMING_REGISTER, 0xc) | ||
215 | + FIELD(ARBITRATION_PHASE_BIT_TIMING_REGISTER, SJW, 7, 2) | ||
216 | + FIELD(ARBITRATION_PHASE_BIT_TIMING_REGISTER, TS2, 4, 3) | ||
217 | + FIELD(ARBITRATION_PHASE_BIT_TIMING_REGISTER, TS1, 0, 4) | ||
218 | +REG32(ERROR_COUNTER_REGISTER, 0x10) | ||
219 | + FIELD(ERROR_COUNTER_REGISTER, REC, 8, 8) | ||
220 | + FIELD(ERROR_COUNTER_REGISTER, TEC, 0, 8) | ||
221 | +REG32(ERROR_STATUS_REGISTER, 0x14) | ||
222 | + FIELD(ERROR_STATUS_REGISTER, ACKER, 4, 1) | ||
223 | + FIELD(ERROR_STATUS_REGISTER, BERR, 3, 1) | ||
224 | + FIELD(ERROR_STATUS_REGISTER, STER, 2, 1) | ||
225 | + FIELD(ERROR_STATUS_REGISTER, FMER, 1, 1) | ||
226 | + FIELD(ERROR_STATUS_REGISTER, CRCER, 0, 1) | ||
227 | +REG32(STATUS_REGISTER, 0x18) | ||
228 | + FIELD(STATUS_REGISTER, SNOOP, 12, 1) | ||
229 | + FIELD(STATUS_REGISTER, ACFBSY, 11, 1) | ||
230 | + FIELD(STATUS_REGISTER, TXFLL, 10, 1) | ||
231 | + FIELD(STATUS_REGISTER, TXBFLL, 9, 1) | ||
232 | + FIELD(STATUS_REGISTER, ESTAT, 7, 2) | ||
233 | + FIELD(STATUS_REGISTER, ERRWRN, 6, 1) | ||
234 | + FIELD(STATUS_REGISTER, BBSY, 5, 1) | ||
235 | + FIELD(STATUS_REGISTER, BIDLE, 4, 1) | ||
236 | + FIELD(STATUS_REGISTER, NORMAL, 3, 1) | ||
237 | + FIELD(STATUS_REGISTER, SLEEP, 2, 1) | ||
238 | + FIELD(STATUS_REGISTER, LBACK, 1, 1) | ||
239 | + FIELD(STATUS_REGISTER, CONFIG, 0, 1) | ||
240 | +REG32(INTERRUPT_STATUS_REGISTER, 0x1c) | ||
241 | + FIELD(INTERRUPT_STATUS_REGISTER, TXFEMP, 14, 1) | ||
242 | + FIELD(INTERRUPT_STATUS_REGISTER, TXFWMEMP, 13, 1) | ||
243 | + FIELD(INTERRUPT_STATUS_REGISTER, RXFWMFLL, 12, 1) | ||
244 | + FIELD(INTERRUPT_STATUS_REGISTER, WKUP, 11, 1) | ||
245 | + FIELD(INTERRUPT_STATUS_REGISTER, SLP, 10, 1) | ||
246 | + FIELD(INTERRUPT_STATUS_REGISTER, BSOFF, 9, 1) | ||
247 | + FIELD(INTERRUPT_STATUS_REGISTER, ERROR, 8, 1) | ||
248 | + FIELD(INTERRUPT_STATUS_REGISTER, RXNEMP, 7, 1) | ||
249 | + FIELD(INTERRUPT_STATUS_REGISTER, RXOFLW, 6, 1) | ||
250 | + FIELD(INTERRUPT_STATUS_REGISTER, RXUFLW, 5, 1) | ||
251 | + FIELD(INTERRUPT_STATUS_REGISTER, RXOK, 4, 1) | ||
252 | + FIELD(INTERRUPT_STATUS_REGISTER, TXBFLL, 3, 1) | ||
253 | + FIELD(INTERRUPT_STATUS_REGISTER, TXFLL, 2, 1) | ||
254 | + FIELD(INTERRUPT_STATUS_REGISTER, TXOK, 1, 1) | ||
255 | + FIELD(INTERRUPT_STATUS_REGISTER, ARBLST, 0, 1) | ||
256 | +REG32(INTERRUPT_ENABLE_REGISTER, 0x20) | ||
257 | + FIELD(INTERRUPT_ENABLE_REGISTER, ETXFEMP, 14, 1) | ||
258 | + FIELD(INTERRUPT_ENABLE_REGISTER, ETXFWMEMP, 13, 1) | ||
259 | + FIELD(INTERRUPT_ENABLE_REGISTER, ERXFWMFLL, 12, 1) | ||
260 | + FIELD(INTERRUPT_ENABLE_REGISTER, EWKUP, 11, 1) | ||
261 | + FIELD(INTERRUPT_ENABLE_REGISTER, ESLP, 10, 1) | ||
262 | + FIELD(INTERRUPT_ENABLE_REGISTER, EBSOFF, 9, 1) | ||
263 | + FIELD(INTERRUPT_ENABLE_REGISTER, EERROR, 8, 1) | ||
264 | + FIELD(INTERRUPT_ENABLE_REGISTER, ERXNEMP, 7, 1) | ||
265 | + FIELD(INTERRUPT_ENABLE_REGISTER, ERXOFLW, 6, 1) | ||
266 | + FIELD(INTERRUPT_ENABLE_REGISTER, ERXUFLW, 5, 1) | ||
267 | + FIELD(INTERRUPT_ENABLE_REGISTER, ERXOK, 4, 1) | ||
268 | + FIELD(INTERRUPT_ENABLE_REGISTER, ETXBFLL, 3, 1) | ||
269 | + FIELD(INTERRUPT_ENABLE_REGISTER, ETXFLL, 2, 1) | ||
270 | + FIELD(INTERRUPT_ENABLE_REGISTER, ETXOK, 1, 1) | ||
271 | + FIELD(INTERRUPT_ENABLE_REGISTER, EARBLST, 0, 1) | ||
272 | +REG32(INTERRUPT_CLEAR_REGISTER, 0x24) | ||
273 | + FIELD(INTERRUPT_CLEAR_REGISTER, CTXFEMP, 14, 1) | ||
274 | + FIELD(INTERRUPT_CLEAR_REGISTER, CTXFWMEMP, 13, 1) | ||
275 | + FIELD(INTERRUPT_CLEAR_REGISTER, CRXFWMFLL, 12, 1) | ||
276 | + FIELD(INTERRUPT_CLEAR_REGISTER, CWKUP, 11, 1) | ||
277 | + FIELD(INTERRUPT_CLEAR_REGISTER, CSLP, 10, 1) | ||
278 | + FIELD(INTERRUPT_CLEAR_REGISTER, CBSOFF, 9, 1) | ||
279 | + FIELD(INTERRUPT_CLEAR_REGISTER, CERROR, 8, 1) | ||
280 | + FIELD(INTERRUPT_CLEAR_REGISTER, CRXNEMP, 7, 1) | ||
281 | + FIELD(INTERRUPT_CLEAR_REGISTER, CRXOFLW, 6, 1) | ||
282 | + FIELD(INTERRUPT_CLEAR_REGISTER, CRXUFLW, 5, 1) | ||
283 | + FIELD(INTERRUPT_CLEAR_REGISTER, CRXOK, 4, 1) | ||
284 | + FIELD(INTERRUPT_CLEAR_REGISTER, CTXBFLL, 3, 1) | ||
285 | + FIELD(INTERRUPT_CLEAR_REGISTER, CTXFLL, 2, 1) | ||
286 | + FIELD(INTERRUPT_CLEAR_REGISTER, CTXOK, 1, 1) | ||
287 | + FIELD(INTERRUPT_CLEAR_REGISTER, CARBLST, 0, 1) | ||
288 | +REG32(TIMESTAMP_REGISTER, 0x28) | ||
289 | + FIELD(TIMESTAMP_REGISTER, CTS, 0, 1) | ||
290 | +REG32(WIR, 0x2c) | ||
291 | + FIELD(WIR, EW, 8, 8) | ||
292 | + FIELD(WIR, FW, 0, 8) | ||
293 | +REG32(TXFIFO_ID, 0x30) | ||
294 | + FIELD(TXFIFO_ID, IDH, 21, 11) | ||
295 | + FIELD(TXFIFO_ID, SRRRTR, 20, 1) | ||
296 | + FIELD(TXFIFO_ID, IDE, 19, 1) | ||
297 | + FIELD(TXFIFO_ID, IDL, 1, 18) | ||
298 | + FIELD(TXFIFO_ID, RTR, 0, 1) | ||
299 | +REG32(TXFIFO_DLC, 0x34) | ||
300 | + FIELD(TXFIFO_DLC, DLC, 28, 4) | ||
301 | +REG32(TXFIFO_DATA1, 0x38) | ||
302 | + FIELD(TXFIFO_DATA1, DB0, 24, 8) | ||
303 | + FIELD(TXFIFO_DATA1, DB1, 16, 8) | ||
304 | + FIELD(TXFIFO_DATA1, DB2, 8, 8) | ||
305 | + FIELD(TXFIFO_DATA1, DB3, 0, 8) | ||
306 | +REG32(TXFIFO_DATA2, 0x3c) | ||
307 | + FIELD(TXFIFO_DATA2, DB4, 24, 8) | ||
308 | + FIELD(TXFIFO_DATA2, DB5, 16, 8) | ||
309 | + FIELD(TXFIFO_DATA2, DB6, 8, 8) | ||
310 | + FIELD(TXFIFO_DATA2, DB7, 0, 8) | ||
311 | +REG32(TXHPB_ID, 0x40) | ||
312 | + FIELD(TXHPB_ID, IDH, 21, 11) | ||
313 | + FIELD(TXHPB_ID, SRRRTR, 20, 1) | ||
314 | + FIELD(TXHPB_ID, IDE, 19, 1) | ||
315 | + FIELD(TXHPB_ID, IDL, 1, 18) | ||
316 | + FIELD(TXHPB_ID, RTR, 0, 1) | ||
317 | +REG32(TXHPB_DLC, 0x44) | ||
318 | + FIELD(TXHPB_DLC, DLC, 28, 4) | ||
319 | +REG32(TXHPB_DATA1, 0x48) | ||
320 | + FIELD(TXHPB_DATA1, DB0, 24, 8) | ||
321 | + FIELD(TXHPB_DATA1, DB1, 16, 8) | ||
322 | + FIELD(TXHPB_DATA1, DB2, 8, 8) | ||
323 | + FIELD(TXHPB_DATA1, DB3, 0, 8) | ||
324 | +REG32(TXHPB_DATA2, 0x4c) | ||
325 | + FIELD(TXHPB_DATA2, DB4, 24, 8) | ||
326 | + FIELD(TXHPB_DATA2, DB5, 16, 8) | ||
327 | + FIELD(TXHPB_DATA2, DB6, 8, 8) | ||
328 | + FIELD(TXHPB_DATA2, DB7, 0, 8) | ||
329 | +REG32(RXFIFO_ID, 0x50) | ||
330 | + FIELD(RXFIFO_ID, IDH, 21, 11) | ||
331 | + FIELD(RXFIFO_ID, SRRRTR, 20, 1) | ||
332 | + FIELD(RXFIFO_ID, IDE, 19, 1) | ||
333 | + FIELD(RXFIFO_ID, IDL, 1, 18) | ||
334 | + FIELD(RXFIFO_ID, RTR, 0, 1) | ||
335 | +REG32(RXFIFO_DLC, 0x54) | ||
336 | + FIELD(RXFIFO_DLC, DLC, 28, 4) | ||
337 | + FIELD(RXFIFO_DLC, RXT, 0, 16) | ||
338 | +REG32(RXFIFO_DATA1, 0x58) | ||
339 | + FIELD(RXFIFO_DATA1, DB0, 24, 8) | ||
340 | + FIELD(RXFIFO_DATA1, DB1, 16, 8) | ||
341 | + FIELD(RXFIFO_DATA1, DB2, 8, 8) | ||
342 | + FIELD(RXFIFO_DATA1, DB3, 0, 8) | ||
343 | +REG32(RXFIFO_DATA2, 0x5c) | ||
344 | + FIELD(RXFIFO_DATA2, DB4, 24, 8) | ||
345 | + FIELD(RXFIFO_DATA2, DB5, 16, 8) | ||
346 | + FIELD(RXFIFO_DATA2, DB6, 8, 8) | ||
347 | + FIELD(RXFIFO_DATA2, DB7, 0, 8) | ||
348 | +REG32(AFR, 0x60) | ||
349 | + FIELD(AFR, UAF4, 3, 1) | ||
350 | + FIELD(AFR, UAF3, 2, 1) | ||
351 | + FIELD(AFR, UAF2, 1, 1) | ||
352 | + FIELD(AFR, UAF1, 0, 1) | ||
353 | +REG32(AFMR1, 0x64) | ||
354 | + FIELD(AFMR1, AMIDH, 21, 11) | ||
355 | + FIELD(AFMR1, AMSRR, 20, 1) | ||
356 | + FIELD(AFMR1, AMIDE, 19, 1) | ||
357 | + FIELD(AFMR1, AMIDL, 1, 18) | ||
358 | + FIELD(AFMR1, AMRTR, 0, 1) | ||
359 | +REG32(AFIR1, 0x68) | ||
360 | + FIELD(AFIR1, AIIDH, 21, 11) | ||
361 | + FIELD(AFIR1, AISRR, 20, 1) | ||
362 | + FIELD(AFIR1, AIIDE, 19, 1) | ||
363 | + FIELD(AFIR1, AIIDL, 1, 18) | ||
364 | + FIELD(AFIR1, AIRTR, 0, 1) | ||
365 | +REG32(AFMR2, 0x6c) | ||
366 | + FIELD(AFMR2, AMIDH, 21, 11) | ||
367 | + FIELD(AFMR2, AMSRR, 20, 1) | ||
368 | + FIELD(AFMR2, AMIDE, 19, 1) | ||
369 | + FIELD(AFMR2, AMIDL, 1, 18) | ||
370 | + FIELD(AFMR2, AMRTR, 0, 1) | ||
371 | +REG32(AFIR2, 0x70) | ||
372 | + FIELD(AFIR2, AIIDH, 21, 11) | ||
373 | + FIELD(AFIR2, AISRR, 20, 1) | ||
374 | + FIELD(AFIR2, AIIDE, 19, 1) | ||
375 | + FIELD(AFIR2, AIIDL, 1, 18) | ||
376 | + FIELD(AFIR2, AIRTR, 0, 1) | ||
377 | +REG32(AFMR3, 0x74) | ||
378 | + FIELD(AFMR3, AMIDH, 21, 11) | ||
379 | + FIELD(AFMR3, AMSRR, 20, 1) | ||
380 | + FIELD(AFMR3, AMIDE, 19, 1) | ||
381 | + FIELD(AFMR3, AMIDL, 1, 18) | ||
382 | + FIELD(AFMR3, AMRTR, 0, 1) | ||
383 | +REG32(AFIR3, 0x78) | ||
384 | + FIELD(AFIR3, AIIDH, 21, 11) | ||
385 | + FIELD(AFIR3, AISRR, 20, 1) | ||
386 | + FIELD(AFIR3, AIIDE, 19, 1) | ||
387 | + FIELD(AFIR3, AIIDL, 1, 18) | ||
388 | + FIELD(AFIR3, AIRTR, 0, 1) | ||
389 | +REG32(AFMR4, 0x7c) | ||
390 | + FIELD(AFMR4, AMIDH, 21, 11) | ||
391 | + FIELD(AFMR4, AMSRR, 20, 1) | ||
392 | + FIELD(AFMR4, AMIDE, 19, 1) | ||
393 | + FIELD(AFMR4, AMIDL, 1, 18) | ||
394 | + FIELD(AFMR4, AMRTR, 0, 1) | ||
395 | +REG32(AFIR4, 0x80) | ||
396 | + FIELD(AFIR4, AIIDH, 21, 11) | ||
397 | + FIELD(AFIR4, AISRR, 20, 1) | ||
398 | + FIELD(AFIR4, AIIDE, 19, 1) | ||
399 | + FIELD(AFIR4, AIIDL, 1, 18) | ||
400 | + FIELD(AFIR4, AIRTR, 0, 1) | ||
401 | + | ||
402 | +static void can_update_irq(XlnxZynqMPCANState *s) | ||
403 | +{ | ||
404 | + uint32_t irq; | ||
405 | + | ||
406 | + /* Watermark register interrupts. */ | ||
407 | + if ((fifo32_num_free(&s->tx_fifo) / CAN_FRAME_SIZE) > | ||
408 | + ARRAY_FIELD_EX32(s->regs, WIR, EW)) { | ||
409 | + ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, TXFWMEMP, 1); | ||
410 | + } | ||
411 | + | ||
412 | + if ((fifo32_num_used(&s->rx_fifo) / CAN_FRAME_SIZE) > | ||
413 | + ARRAY_FIELD_EX32(s->regs, WIR, FW)) { | ||
414 | + ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, RXFWMFLL, 1); | ||
415 | + } | ||
416 | + | ||
417 | + /* RX Interrupts. */ | ||
418 | + if (fifo32_num_used(&s->rx_fifo) >= CAN_FRAME_SIZE) { | ||
419 | + ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, RXNEMP, 1); | ||
420 | + } | ||
421 | + | ||
422 | + /* TX interrupts. */ | ||
423 | + if (fifo32_is_empty(&s->tx_fifo)) { | ||
424 | + ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, TXFEMP, 1); | ||
425 | + } | ||
426 | + | ||
427 | + if (fifo32_is_full(&s->tx_fifo)) { | ||
428 | + ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, TXFLL, 1); | ||
429 | + } | ||
430 | + | ||
431 | + if (fifo32_is_full(&s->txhpb_fifo)) { | ||
432 | + ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, TXBFLL, 1); | ||
433 | + } | ||
434 | + | ||
435 | + irq = s->regs[R_INTERRUPT_STATUS_REGISTER]; | ||
436 | + irq &= s->regs[R_INTERRUPT_ENABLE_REGISTER]; | ||
437 | + | ||
438 | + trace_xlnx_can_update_irq(s->regs[R_INTERRUPT_STATUS_REGISTER], | ||
439 | + s->regs[R_INTERRUPT_ENABLE_REGISTER], irq); | ||
440 | + qemu_set_irq(s->irq, irq); | ||
441 | +} | 75 | +} |
442 | + | 76 | + |
443 | +static void can_ier_post_write(RegisterInfo *reg, uint64_t val) | 77 | static int aa64_va_parameter_tbi(uint64_t tcr, ARMMMUIdx mmu_idx) |
444 | +{ | 78 | { |
445 | + XlnxZynqMPCANState *s = XLNX_ZYNQMP_CAN(reg->opaque); | 79 | if (regime_has_2_ranges(mmu_idx)) { |
446 | + | ||
447 | + can_update_irq(s); | ||
448 | +} | ||
449 | + | ||
450 | +static uint64_t can_icr_pre_write(RegisterInfo *reg, uint64_t val) | ||
451 | +{ | ||
452 | + XlnxZynqMPCANState *s = XLNX_ZYNQMP_CAN(reg->opaque); | ||
453 | + | ||
454 | + s->regs[R_INTERRUPT_STATUS_REGISTER] &= ~val; | ||
455 | + can_update_irq(s); | ||
456 | + | ||
457 | + return 0; | ||
458 | +} | ||
459 | + | ||
460 | +static void can_config_reset(XlnxZynqMPCANState *s) | ||
461 | +{ | ||
462 | + /* Reset all the configuration registers. */ | ||
463 | + register_reset(&s->reg_info[R_SOFTWARE_RESET_REGISTER]); | ||
464 | + register_reset(&s->reg_info[R_MODE_SELECT_REGISTER]); | ||
465 | + register_reset( | ||
466 | + &s->reg_info[R_ARBITRATION_PHASE_BAUD_RATE_PRESCALER_REGISTER]); | ||
467 | + register_reset(&s->reg_info[R_ARBITRATION_PHASE_BIT_TIMING_REGISTER]); | ||
468 | + register_reset(&s->reg_info[R_STATUS_REGISTER]); | ||
469 | + register_reset(&s->reg_info[R_INTERRUPT_STATUS_REGISTER]); | ||
470 | + register_reset(&s->reg_info[R_INTERRUPT_ENABLE_REGISTER]); | ||
471 | + register_reset(&s->reg_info[R_INTERRUPT_CLEAR_REGISTER]); | ||
472 | + register_reset(&s->reg_info[R_WIR]); | ||
473 | +} | ||
474 | + | ||
475 | +static void can_config_mode(XlnxZynqMPCANState *s) | ||
476 | +{ | ||
477 | + register_reset(&s->reg_info[R_ERROR_COUNTER_REGISTER]); | ||
478 | + register_reset(&s->reg_info[R_ERROR_STATUS_REGISTER]); | ||
479 | + | ||
480 | + /* Put XlnxZynqMPCAN in configuration mode. */ | ||
481 | + ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, CONFIG, 1); | ||
482 | + ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, WKUP, 0); | ||
483 | + ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, SLP, 0); | ||
484 | + ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, BSOFF, 0); | ||
485 | + ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, ERROR, 0); | ||
486 | + ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, RXOFLW, 0); | ||
487 | + ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, RXOK, 0); | ||
488 | + ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, TXOK, 0); | ||
489 | + ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, ARBLST, 0); | ||
490 | + | ||
491 | + can_update_irq(s); | ||
492 | +} | ||
493 | + | ||
494 | +static void update_status_register_mode_bits(XlnxZynqMPCANState *s) | ||
495 | +{ | ||
496 | + bool sleep_status = ARRAY_FIELD_EX32(s->regs, STATUS_REGISTER, SLEEP); | ||
497 | + bool sleep_mode = ARRAY_FIELD_EX32(s->regs, MODE_SELECT_REGISTER, SLEEP); | ||
498 | + /* Wake up interrupt bit. */ | ||
499 | + bool wakeup_irq_val = sleep_status && (sleep_mode == 0); | ||
500 | + /* Sleep interrupt bit. */ | ||
501 | + bool sleep_irq_val = sleep_mode && (sleep_status == 0); | ||
502 | + | ||
503 | + /* Clear previous core mode status bits. */ | ||
504 | + ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, LBACK, 0); | ||
505 | + ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, SLEEP, 0); | ||
506 | + ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, SNOOP, 0); | ||
507 | + ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, NORMAL, 0); | ||
508 | + | ||
509 | + /* set current mode bit and generate irqs accordingly. */ | ||
510 | + if (ARRAY_FIELD_EX32(s->regs, MODE_SELECT_REGISTER, LBACK)) { | ||
511 | + ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, LBACK, 1); | ||
512 | + } else if (ARRAY_FIELD_EX32(s->regs, MODE_SELECT_REGISTER, SLEEP)) { | ||
513 | + ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, SLEEP, 1); | ||
514 | + ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, SLP, | ||
515 | + sleep_irq_val); | ||
516 | + } else if (ARRAY_FIELD_EX32(s->regs, MODE_SELECT_REGISTER, SNOOP)) { | ||
517 | + ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, SNOOP, 1); | ||
518 | + } else { | ||
519 | + /* | ||
520 | + * If all bits are zero then XlnxZynqMPCAN is set in normal mode. | ||
521 | + */ | ||
522 | + ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, NORMAL, 1); | ||
523 | + /* Set wakeup interrupt bit. */ | ||
524 | + ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, WKUP, | ||
525 | + wakeup_irq_val); | ||
526 | + } | ||
527 | + | ||
528 | + can_update_irq(s); | ||
529 | +} | ||
530 | + | ||
531 | +static void can_exit_sleep_mode(XlnxZynqMPCANState *s) | ||
532 | +{ | ||
533 | + ARRAY_FIELD_DP32(s->regs, MODE_SELECT_REGISTER, SLEEP, 0); | ||
534 | + update_status_register_mode_bits(s); | ||
535 | +} | ||
536 | + | ||
537 | +static void generate_frame(qemu_can_frame *frame, uint32_t *data) | ||
538 | +{ | ||
539 | + frame->can_id = data[0]; | ||
540 | + frame->can_dlc = FIELD_EX32(data[1], TXFIFO_DLC, DLC); | ||
541 | + | ||
542 | + frame->data[0] = FIELD_EX32(data[2], TXFIFO_DATA1, DB3); | ||
543 | + frame->data[1] = FIELD_EX32(data[2], TXFIFO_DATA1, DB2); | ||
544 | + frame->data[2] = FIELD_EX32(data[2], TXFIFO_DATA1, DB1); | ||
545 | + frame->data[3] = FIELD_EX32(data[2], TXFIFO_DATA1, DB0); | ||
546 | + | ||
547 | + frame->data[4] = FIELD_EX32(data[3], TXFIFO_DATA2, DB7); | ||
548 | + frame->data[5] = FIELD_EX32(data[3], TXFIFO_DATA2, DB6); | ||
549 | + frame->data[6] = FIELD_EX32(data[3], TXFIFO_DATA2, DB5); | ||
550 | + frame->data[7] = FIELD_EX32(data[3], TXFIFO_DATA2, DB4); | ||
551 | +} | ||
552 | + | ||
553 | +static bool tx_ready_check(XlnxZynqMPCANState *s) | ||
554 | +{ | ||
555 | + if (ARRAY_FIELD_EX32(s->regs, SOFTWARE_RESET_REGISTER, SRST)) { | ||
556 | + g_autofree char *path = object_get_canonical_path(OBJECT(s)); | ||
557 | + | ||
558 | + qemu_log_mask(LOG_GUEST_ERROR, "%s: Attempting to transfer data while" | ||
559 | + " data while controller is in reset mode.\n", | ||
560 | + path); | ||
561 | + return false; | ||
562 | + } | ||
563 | + | ||
564 | + if (ARRAY_FIELD_EX32(s->regs, SOFTWARE_RESET_REGISTER, CEN) == 0) { | ||
565 | + g_autofree char *path = object_get_canonical_path(OBJECT(s)); | ||
566 | + | ||
567 | + qemu_log_mask(LOG_GUEST_ERROR, "%s: Attempting to transfer" | ||
568 | + " data while controller is in configuration mode. Reset" | ||
569 | + " the core so operations can start fresh.\n", | ||
570 | + path); | ||
571 | + return false; | ||
572 | + } | ||
573 | + | ||
574 | + if (ARRAY_FIELD_EX32(s->regs, STATUS_REGISTER, SNOOP)) { | ||
575 | + g_autofree char *path = object_get_canonical_path(OBJECT(s)); | ||
576 | + | ||
577 | + qemu_log_mask(LOG_GUEST_ERROR, "%s: Attempting to transfer" | ||
578 | + " data while controller is in SNOOP MODE.\n", | ||
579 | + path); | ||
580 | + return false; | ||
581 | + } | ||
582 | + | ||
583 | + return true; | ||
584 | +} | ||
585 | + | ||
586 | +static void transfer_fifo(XlnxZynqMPCANState *s, Fifo32 *fifo) | ||
587 | +{ | ||
588 | + qemu_can_frame frame; | ||
589 | + uint32_t data[CAN_FRAME_SIZE]; | ||
590 | + int i; | ||
591 | + bool can_tx = tx_ready_check(s); | ||
592 | + | ||
593 | + if (!can_tx) { | ||
594 | + g_autofree char *path = object_get_canonical_path(OBJECT(s)); | ||
595 | + | ||
596 | + qemu_log_mask(LOG_GUEST_ERROR, "%s: Controller is not enabled for data" | ||
597 | + " transfer.\n", path); | ||
598 | + can_update_irq(s); | ||
599 | + return; | ||
600 | + } | ||
601 | + | ||
602 | + while (!fifo32_is_empty(fifo)) { | ||
603 | + for (i = 0; i < CAN_FRAME_SIZE; i++) { | ||
604 | + data[i] = fifo32_pop(fifo); | ||
605 | + } | ||
606 | + | ||
607 | + if (ARRAY_FIELD_EX32(s->regs, STATUS_REGISTER, LBACK)) { | ||
608 | + /* | ||
609 | + * Controller is in loopback. In Loopback mode, the CAN core | ||
610 | + * transmits a recessive bitstream on to the XlnxZynqMPCAN Bus. | ||
611 | + * Any message transmitted is looped back to the RX line and | ||
612 | + * acknowledged. The XlnxZynqMPCAN core receives any message | ||
613 | + * that it transmits. | ||
614 | + */ | ||
615 | + if (fifo32_is_full(&s->rx_fifo)) { | ||
616 | + ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, RXOFLW, 1); | ||
617 | + } else { | ||
618 | + for (i = 0; i < CAN_FRAME_SIZE; i++) { | ||
619 | + fifo32_push(&s->rx_fifo, data[i]); | ||
620 | + } | ||
621 | + | ||
622 | + ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, RXOK, 1); | ||
623 | + } | ||
624 | + } else { | ||
625 | + /* Normal mode Tx. */ | ||
626 | + generate_frame(&frame, data); | ||
627 | + | ||
628 | + trace_xlnx_can_tx_data(frame.can_id, frame.can_dlc, | ||
629 | + frame.data[0], frame.data[1], | ||
630 | + frame.data[2], frame.data[3], | ||
631 | + frame.data[4], frame.data[5], | ||
632 | + frame.data[6], frame.data[7]); | ||
633 | + can_bus_client_send(&s->bus_client, &frame, 1); | ||
634 | + } | ||
635 | + } | ||
636 | + | ||
637 | + ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, TXOK, 1); | ||
638 | + ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, TXBFLL, 0); | ||
639 | + | ||
640 | + if (ARRAY_FIELD_EX32(s->regs, STATUS_REGISTER, SLEEP)) { | ||
641 | + can_exit_sleep_mode(s); | ||
642 | + } | ||
643 | + | ||
644 | + can_update_irq(s); | ||
645 | +} | ||
646 | + | ||
647 | +static uint64_t can_srr_pre_write(RegisterInfo *reg, uint64_t val) | ||
648 | +{ | ||
649 | + XlnxZynqMPCANState *s = XLNX_ZYNQMP_CAN(reg->opaque); | ||
650 | + | ||
651 | + ARRAY_FIELD_DP32(s->regs, SOFTWARE_RESET_REGISTER, CEN, | ||
652 | + FIELD_EX32(val, SOFTWARE_RESET_REGISTER, CEN)); | ||
653 | + | ||
654 | + if (FIELD_EX32(val, SOFTWARE_RESET_REGISTER, SRST)) { | ||
655 | + trace_xlnx_can_reset(val); | ||
656 | + | ||
657 | + /* First, core will do software reset then will enter in config mode. */ | ||
658 | + can_config_reset(s); | ||
659 | + } | ||
660 | + | ||
661 | + if (ARRAY_FIELD_EX32(s->regs, SOFTWARE_RESET_REGISTER, CEN) == 0) { | ||
662 | + can_config_mode(s); | ||
663 | + } else { | ||
664 | + /* | ||
665 | + * Leave config mode. Now XlnxZynqMPCAN core will enter normal, | ||
666 | + * sleep, snoop or loopback mode depending upon LBACK, SLEEP, SNOOP | ||
667 | + * register states. | ||
668 | + */ | ||
669 | + ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, CONFIG, 0); | ||
670 | + | ||
671 | + ptimer_transaction_begin(s->can_timer); | ||
672 | + ptimer_set_count(s->can_timer, 0); | ||
673 | + ptimer_transaction_commit(s->can_timer); | ||
674 | + | ||
675 | + /* XlnxZynqMPCAN is out of config mode. It will send pending data. */ | ||
676 | + transfer_fifo(s, &s->txhpb_fifo); | ||
677 | + transfer_fifo(s, &s->tx_fifo); | ||
678 | + } | ||
679 | + | ||
680 | + update_status_register_mode_bits(s); | ||
681 | + | ||
682 | + return s->regs[R_SOFTWARE_RESET_REGISTER]; | ||
683 | +} | ||
684 | + | ||
685 | +static uint64_t can_msr_pre_write(RegisterInfo *reg, uint64_t val) | ||
686 | +{ | ||
687 | + XlnxZynqMPCANState *s = XLNX_ZYNQMP_CAN(reg->opaque); | ||
688 | + uint8_t multi_mode; | ||
689 | + | ||
690 | + /* | ||
691 | + * Multiple mode set check. This is done to make sure user doesn't set | ||
692 | + * multiple modes. | ||
693 | + */ | ||
694 | + multi_mode = FIELD_EX32(val, MODE_SELECT_REGISTER, LBACK) + | ||
695 | + FIELD_EX32(val, MODE_SELECT_REGISTER, SLEEP) + | ||
696 | + FIELD_EX32(val, MODE_SELECT_REGISTER, SNOOP); | ||
697 | + | ||
698 | + if (multi_mode > 1) { | ||
699 | + g_autofree char *path = object_get_canonical_path(OBJECT(s)); | ||
700 | + | ||
701 | + qemu_log_mask(LOG_GUEST_ERROR, "%s: Attempting to config" | ||
702 | + " several modes simultaneously. One mode will be selected" | ||
703 | + " according to their priority: LBACK > SLEEP > SNOOP.\n", | ||
704 | + path); | ||
705 | + } | ||
706 | + | ||
707 | + if (ARRAY_FIELD_EX32(s->regs, SOFTWARE_RESET_REGISTER, CEN) == 0) { | ||
708 | + /* We are in configuration mode, any mode can be selected. */ | ||
709 | + s->regs[R_MODE_SELECT_REGISTER] = val; | ||
710 | + } else { | ||
711 | + bool sleep_mode_bit = FIELD_EX32(val, MODE_SELECT_REGISTER, SLEEP); | ||
712 | + | ||
713 | + ARRAY_FIELD_DP32(s->regs, MODE_SELECT_REGISTER, SLEEP, sleep_mode_bit); | ||
714 | + | ||
715 | + if (FIELD_EX32(val, MODE_SELECT_REGISTER, LBACK)) { | ||
716 | + g_autofree char *path = object_get_canonical_path(OBJECT(s)); | ||
717 | + | ||
718 | + qemu_log_mask(LOG_GUEST_ERROR, "%s: Attempting to set" | ||
719 | + " LBACK mode without setting CEN bit as 0.\n", | ||
720 | + path); | ||
721 | + } else if (FIELD_EX32(val, MODE_SELECT_REGISTER, SNOOP)) { | ||
722 | + g_autofree char *path = object_get_canonical_path(OBJECT(s)); | ||
723 | + | ||
724 | + qemu_log_mask(LOG_GUEST_ERROR, "%s: Attempting to set" | ||
725 | + " SNOOP mode without setting CEN bit as 0.\n", | ||
726 | + path); | ||
727 | + } | ||
728 | + | ||
729 | + update_status_register_mode_bits(s); | ||
730 | + } | ||
731 | + | ||
732 | + return s->regs[R_MODE_SELECT_REGISTER]; | ||
733 | +} | ||
734 | + | ||
735 | +static uint64_t can_brpr_pre_write(RegisterInfo *reg, uint64_t val) | ||
736 | +{ | ||
737 | + XlnxZynqMPCANState *s = XLNX_ZYNQMP_CAN(reg->opaque); | ||
738 | + | ||
739 | + /* Only allow writes when in config mode. */ | ||
740 | + if (ARRAY_FIELD_EX32(s->regs, SOFTWARE_RESET_REGISTER, CEN)) { | ||
741 | + return s->regs[R_ARBITRATION_PHASE_BAUD_RATE_PRESCALER_REGISTER]; | ||
742 | + } | ||
743 | + | ||
744 | + return val; | ||
745 | +} | ||
746 | + | ||
747 | +static uint64_t can_btr_pre_write(RegisterInfo *reg, uint64_t val) | ||
748 | +{ | ||
749 | + XlnxZynqMPCANState *s = XLNX_ZYNQMP_CAN(reg->opaque); | ||
750 | + | ||
751 | + /* Only allow writes when in config mode. */ | ||
752 | + if (ARRAY_FIELD_EX32(s->regs, SOFTWARE_RESET_REGISTER, CEN)) { | ||
753 | + return s->regs[R_ARBITRATION_PHASE_BIT_TIMING_REGISTER]; | ||
754 | + } | ||
755 | + | ||
756 | + return val; | ||
757 | +} | ||
758 | + | ||
759 | +static uint64_t can_tcr_pre_write(RegisterInfo *reg, uint64_t val) | ||
760 | +{ | ||
761 | + XlnxZynqMPCANState *s = XLNX_ZYNQMP_CAN(reg->opaque); | ||
762 | + | ||
763 | + if (FIELD_EX32(val, TIMESTAMP_REGISTER, CTS)) { | ||
764 | + ptimer_transaction_begin(s->can_timer); | ||
765 | + ptimer_set_count(s->can_timer, 0); | ||
766 | + ptimer_transaction_commit(s->can_timer); | ||
767 | + } | ||
768 | + | ||
769 | + return 0; | ||
770 | +} | ||
771 | + | ||
772 | +static void update_rx_fifo(XlnxZynqMPCANState *s, const qemu_can_frame *frame) | ||
773 | +{ | ||
774 | + bool filter_pass = false; | ||
775 | + uint16_t timestamp = 0; | ||
776 | + | ||
777 | + /* If no filter is enabled. Message will be stored in FIFO. */ | ||
778 | + if (!((ARRAY_FIELD_EX32(s->regs, AFR, UAF1)) | | ||
779 | + (ARRAY_FIELD_EX32(s->regs, AFR, UAF2)) | | ||
780 | + (ARRAY_FIELD_EX32(s->regs, AFR, UAF3)) | | ||
781 | + (ARRAY_FIELD_EX32(s->regs, AFR, UAF4)))) { | ||
782 | + filter_pass = true; | ||
783 | + } | ||
784 | + | ||
785 | + /* | ||
786 | + * Messages that pass any of the acceptance filters will be stored in | ||
787 | + * the RX FIFO. | ||
788 | + */ | ||
789 | + if (ARRAY_FIELD_EX32(s->regs, AFR, UAF1)) { | ||
790 | + uint32_t id_masked = s->regs[R_AFMR1] & frame->can_id; | ||
791 | + uint32_t filter_id_masked = s->regs[R_AFMR1] & s->regs[R_AFIR1]; | ||
792 | + | ||
793 | + if (filter_id_masked == id_masked) { | ||
794 | + filter_pass = true; | ||
795 | + } | ||
796 | + } | ||
797 | + | ||
798 | + if (ARRAY_FIELD_EX32(s->regs, AFR, UAF2)) { | ||
799 | + uint32_t id_masked = s->regs[R_AFMR2] & frame->can_id; | ||
800 | + uint32_t filter_id_masked = s->regs[R_AFMR2] & s->regs[R_AFIR2]; | ||
801 | + | ||
802 | + if (filter_id_masked == id_masked) { | ||
803 | + filter_pass = true; | ||
804 | + } | ||
805 | + } | ||
806 | + | ||
807 | + if (ARRAY_FIELD_EX32(s->regs, AFR, UAF3)) { | ||
808 | + uint32_t id_masked = s->regs[R_AFMR3] & frame->can_id; | ||
809 | + uint32_t filter_id_masked = s->regs[R_AFMR3] & s->regs[R_AFIR3]; | ||
810 | + | ||
811 | + if (filter_id_masked == id_masked) { | ||
812 | + filter_pass = true; | ||
813 | + } | ||
814 | + } | ||
815 | + | ||
816 | + if (ARRAY_FIELD_EX32(s->regs, AFR, UAF4)) { | ||
817 | + uint32_t id_masked = s->regs[R_AFMR4] & frame->can_id; | ||
818 | + uint32_t filter_id_masked = s->regs[R_AFMR4] & s->regs[R_AFIR4]; | ||
819 | + | ||
820 | + if (filter_id_masked == id_masked) { | ||
821 | + filter_pass = true; | ||
822 | + } | ||
823 | + } | ||
824 | + | ||
825 | + if (!filter_pass) { | ||
826 | + trace_xlnx_can_rx_fifo_filter_reject(frame->can_id, frame->can_dlc); | ||
827 | + return; | ||
828 | + } | ||
829 | + | ||
830 | + /* Store the message in fifo if it passed through any of the filters. */ | ||
831 | + if (filter_pass && frame->can_dlc <= MAX_DLC) { | ||
832 | + | ||
833 | + if (fifo32_is_full(&s->rx_fifo)) { | ||
834 | + ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, RXOFLW, 1); | ||
835 | + } else { | ||
836 | + timestamp = CAN_TIMER_MAX - ptimer_get_count(s->can_timer); | ||
837 | + | ||
838 | + fifo32_push(&s->rx_fifo, frame->can_id); | ||
839 | + | ||
840 | + fifo32_push(&s->rx_fifo, deposit32(0, R_RXFIFO_DLC_DLC_SHIFT, | ||
841 | + R_RXFIFO_DLC_DLC_LENGTH, | ||
842 | + frame->can_dlc) | | ||
843 | + deposit32(0, R_RXFIFO_DLC_RXT_SHIFT, | ||
844 | + R_RXFIFO_DLC_RXT_LENGTH, | ||
845 | + timestamp)); | ||
846 | + | ||
847 | + /* First 32 bit of the data. */ | ||
848 | + fifo32_push(&s->rx_fifo, deposit32(0, R_TXFIFO_DATA1_DB3_SHIFT, | ||
849 | + R_TXFIFO_DATA1_DB3_LENGTH, | ||
850 | + frame->data[0]) | | ||
851 | + deposit32(0, R_TXFIFO_DATA1_DB2_SHIFT, | ||
852 | + R_TXFIFO_DATA1_DB2_LENGTH, | ||
853 | + frame->data[1]) | | ||
854 | + deposit32(0, R_TXFIFO_DATA1_DB1_SHIFT, | ||
855 | + R_TXFIFO_DATA1_DB1_LENGTH, | ||
856 | + frame->data[2]) | | ||
857 | + deposit32(0, R_TXFIFO_DATA1_DB0_SHIFT, | ||
858 | + R_TXFIFO_DATA1_DB0_LENGTH, | ||
859 | + frame->data[3])); | ||
860 | + /* Last 32 bit of the data. */ | ||
861 | + fifo32_push(&s->rx_fifo, deposit32(0, R_TXFIFO_DATA2_DB7_SHIFT, | ||
862 | + R_TXFIFO_DATA2_DB7_LENGTH, | ||
863 | + frame->data[4]) | | ||
864 | + deposit32(0, R_TXFIFO_DATA2_DB6_SHIFT, | ||
865 | + R_TXFIFO_DATA2_DB6_LENGTH, | ||
866 | + frame->data[5]) | | ||
867 | + deposit32(0, R_TXFIFO_DATA2_DB5_SHIFT, | ||
868 | + R_TXFIFO_DATA2_DB5_LENGTH, | ||
869 | + frame->data[6]) | | ||
870 | + deposit32(0, R_TXFIFO_DATA2_DB4_SHIFT, | ||
871 | + R_TXFIFO_DATA2_DB4_LENGTH, | ||
872 | + frame->data[7])); | ||
873 | + | ||
874 | + ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, RXOK, 1); | ||
875 | + trace_xlnx_can_rx_data(frame->can_id, frame->can_dlc, | ||
876 | + frame->data[0], frame->data[1], | ||
877 | + frame->data[2], frame->data[3], | ||
878 | + frame->data[4], frame->data[5], | ||
879 | + frame->data[6], frame->data[7]); | ||
880 | + } | ||
881 | + | ||
882 | + can_update_irq(s); | ||
883 | + } | ||
884 | +} | ||
885 | + | ||
886 | +static uint64_t can_rxfifo_pre_read(RegisterInfo *reg, uint64_t val) | ||
887 | +{ | ||
888 | + XlnxZynqMPCANState *s = XLNX_ZYNQMP_CAN(reg->opaque); | ||
889 | + | ||
890 | + if (!fifo32_is_empty(&s->rx_fifo)) { | ||
891 | + val = fifo32_pop(&s->rx_fifo); | ||
892 | + } else { | ||
893 | + ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, RXUFLW, 1); | ||
894 | + } | ||
895 | + | ||
896 | + can_update_irq(s); | ||
897 | + return val; | ||
898 | +} | ||
899 | + | ||
900 | +static void can_filter_enable_post_write(RegisterInfo *reg, uint64_t val) | ||
901 | +{ | ||
902 | + XlnxZynqMPCANState *s = XLNX_ZYNQMP_CAN(reg->opaque); | ||
903 | + | ||
904 | + if (ARRAY_FIELD_EX32(s->regs, AFR, UAF1) && | ||
905 | + ARRAY_FIELD_EX32(s->regs, AFR, UAF2) && | ||
906 | + ARRAY_FIELD_EX32(s->regs, AFR, UAF3) && | ||
907 | + ARRAY_FIELD_EX32(s->regs, AFR, UAF4)) { | ||
908 | + ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, ACFBSY, 1); | ||
909 | + } else { | ||
910 | + ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, ACFBSY, 0); | ||
911 | + } | ||
912 | +} | ||
913 | + | ||
914 | +static uint64_t can_filter_mask_pre_write(RegisterInfo *reg, uint64_t val) | ||
915 | +{ | ||
916 | + XlnxZynqMPCANState *s = XLNX_ZYNQMP_CAN(reg->opaque); | ||
917 | + uint32_t reg_idx = (reg->access->addr) / 4; | ||
918 | + uint32_t filter_number = (reg_idx - R_AFMR1) / 2; | ||
919 | + | ||
920 | + /* modify an acceptance filter, the corresponding UAF bit should be '0'. */ | ||
921 | + if (!(s->regs[R_AFR] & (1 << filter_number))) { | ||
922 | + s->regs[reg_idx] = val; | ||
923 | + | ||
924 | + trace_xlnx_can_filter_mask_pre_write(filter_number, s->regs[reg_idx]); | ||
925 | + } else { | ||
926 | + g_autofree char *path = object_get_canonical_path(OBJECT(s)); | ||
927 | + | ||
928 | + qemu_log_mask(LOG_GUEST_ERROR, "%s: Acceptance filter %d" | ||
929 | + " mask is not set as corresponding UAF bit is not 0.\n", | ||
930 | + path, filter_number + 1); | ||
931 | + } | ||
932 | + | ||
933 | + return s->regs[reg_idx]; | ||
934 | +} | ||
935 | + | ||
936 | +static uint64_t can_filter_id_pre_write(RegisterInfo *reg, uint64_t val) | ||
937 | +{ | ||
938 | + XlnxZynqMPCANState *s = XLNX_ZYNQMP_CAN(reg->opaque); | ||
939 | + uint32_t reg_idx = (reg->access->addr) / 4; | ||
940 | + uint32_t filter_number = (reg_idx - R_AFIR1) / 2; | ||
941 | + | ||
942 | + if (!(s->regs[R_AFR] & (1 << filter_number))) { | ||
943 | + s->regs[reg_idx] = val; | ||
944 | + | ||
945 | + trace_xlnx_can_filter_id_pre_write(filter_number, s->regs[reg_idx]); | ||
946 | + } else { | ||
947 | + g_autofree char *path = object_get_canonical_path(OBJECT(s)); | ||
948 | + | ||
949 | + qemu_log_mask(LOG_GUEST_ERROR, "%s: Acceptance filter %d" | ||
950 | + " id is not set as corresponding UAF bit is not 0.\n", | ||
951 | + path, filter_number + 1); | ||
952 | + } | ||
953 | + | ||
954 | + return s->regs[reg_idx]; | ||
955 | +} | ||
956 | + | ||
957 | +static void can_tx_post_write(RegisterInfo *reg, uint64_t val) | ||
958 | +{ | ||
959 | + XlnxZynqMPCANState *s = XLNX_ZYNQMP_CAN(reg->opaque); | ||
960 | + | ||
961 | + bool is_txhpb = reg->access->addr > A_TXFIFO_DATA2; | ||
962 | + | ||
963 | + bool initiate_transfer = (reg->access->addr == A_TXFIFO_DATA2) || | ||
964 | + (reg->access->addr == A_TXHPB_DATA2); | ||
965 | + | ||
966 | + Fifo32 *f = is_txhpb ? &s->txhpb_fifo : &s->tx_fifo; | ||
967 | + | ||
968 | + if (!fifo32_is_full(f)) { | ||
969 | + fifo32_push(f, val); | ||
970 | + } else { | ||
971 | + g_autofree char *path = object_get_canonical_path(OBJECT(s)); | ||
972 | + | ||
973 | + qemu_log_mask(LOG_GUEST_ERROR, "%s: TX FIFO is full.\n", path); | ||
974 | + } | ||
975 | + | ||
976 | + /* Initiate the message send if TX register is written. */ | ||
977 | + if (initiate_transfer && | ||
978 | + ARRAY_FIELD_EX32(s->regs, SOFTWARE_RESET_REGISTER, CEN)) { | ||
979 | + transfer_fifo(s, f); | ||
980 | + } | ||
981 | + | ||
982 | + can_update_irq(s); | ||
983 | +} | ||
984 | + | ||
985 | +static const RegisterAccessInfo can_regs_info[] = { | ||
986 | + { .name = "SOFTWARE_RESET_REGISTER", | ||
987 | + .addr = A_SOFTWARE_RESET_REGISTER, | ||
988 | + .rsvd = 0xfffffffc, | ||
989 | + .pre_write = can_srr_pre_write, | ||
990 | + },{ .name = "MODE_SELECT_REGISTER", | ||
991 | + .addr = A_MODE_SELECT_REGISTER, | ||
992 | + .rsvd = 0xfffffff8, | ||
993 | + .pre_write = can_msr_pre_write, | ||
994 | + },{ .name = "ARBITRATION_PHASE_BAUD_RATE_PRESCALER_REGISTER", | ||
995 | + .addr = A_ARBITRATION_PHASE_BAUD_RATE_PRESCALER_REGISTER, | ||
996 | + .rsvd = 0xffffff00, | ||
997 | + .pre_write = can_brpr_pre_write, | ||
998 | + },{ .name = "ARBITRATION_PHASE_BIT_TIMING_REGISTER", | ||
999 | + .addr = A_ARBITRATION_PHASE_BIT_TIMING_REGISTER, | ||
1000 | + .rsvd = 0xfffffe00, | ||
1001 | + .pre_write = can_btr_pre_write, | ||
1002 | + },{ .name = "ERROR_COUNTER_REGISTER", | ||
1003 | + .addr = A_ERROR_COUNTER_REGISTER, | ||
1004 | + .rsvd = 0xffff0000, | ||
1005 | + .ro = 0xffffffff, | ||
1006 | + },{ .name = "ERROR_STATUS_REGISTER", | ||
1007 | + .addr = A_ERROR_STATUS_REGISTER, | ||
1008 | + .rsvd = 0xffffffe0, | ||
1009 | + .w1c = 0x1f, | ||
1010 | + },{ .name = "STATUS_REGISTER", .addr = A_STATUS_REGISTER, | ||
1011 | + .reset = 0x1, | ||
1012 | + .rsvd = 0xffffe000, | ||
1013 | + .ro = 0x1fff, | ||
1014 | + },{ .name = "INTERRUPT_STATUS_REGISTER", | ||
1015 | + .addr = A_INTERRUPT_STATUS_REGISTER, | ||
1016 | + .reset = 0x6000, | ||
1017 | + .rsvd = 0xffff8000, | ||
1018 | + .ro = 0x7fff, | ||
1019 | + },{ .name = "INTERRUPT_ENABLE_REGISTER", | ||
1020 | + .addr = A_INTERRUPT_ENABLE_REGISTER, | ||
1021 | + .rsvd = 0xffff8000, | ||
1022 | + .post_write = can_ier_post_write, | ||
1023 | + },{ .name = "INTERRUPT_CLEAR_REGISTER", | ||
1024 | + .addr = A_INTERRUPT_CLEAR_REGISTER, | ||
1025 | + .rsvd = 0xffff8000, | ||
1026 | + .pre_write = can_icr_pre_write, | ||
1027 | + },{ .name = "TIMESTAMP_REGISTER", | ||
1028 | + .addr = A_TIMESTAMP_REGISTER, | ||
1029 | + .rsvd = 0xfffffffe, | ||
1030 | + .pre_write = can_tcr_pre_write, | ||
1031 | + },{ .name = "WIR", .addr = A_WIR, | ||
1032 | + .reset = 0x3f3f, | ||
1033 | + .rsvd = 0xffff0000, | ||
1034 | + },{ .name = "TXFIFO_ID", .addr = A_TXFIFO_ID, | ||
1035 | + .post_write = can_tx_post_write, | ||
1036 | + },{ .name = "TXFIFO_DLC", .addr = A_TXFIFO_DLC, | ||
1037 | + .rsvd = 0xfffffff, | ||
1038 | + .post_write = can_tx_post_write, | ||
1039 | + },{ .name = "TXFIFO_DATA1", .addr = A_TXFIFO_DATA1, | ||
1040 | + .post_write = can_tx_post_write, | ||
1041 | + },{ .name = "TXFIFO_DATA2", .addr = A_TXFIFO_DATA2, | ||
1042 | + .post_write = can_tx_post_write, | ||
1043 | + },{ .name = "TXHPB_ID", .addr = A_TXHPB_ID, | ||
1044 | + .post_write = can_tx_post_write, | ||
1045 | + },{ .name = "TXHPB_DLC", .addr = A_TXHPB_DLC, | ||
1046 | + .rsvd = 0xfffffff, | ||
1047 | + .post_write = can_tx_post_write, | ||
1048 | + },{ .name = "TXHPB_DATA1", .addr = A_TXHPB_DATA1, | ||
1049 | + .post_write = can_tx_post_write, | ||
1050 | + },{ .name = "TXHPB_DATA2", .addr = A_TXHPB_DATA2, | ||
1051 | + .post_write = can_tx_post_write, | ||
1052 | + },{ .name = "RXFIFO_ID", .addr = A_RXFIFO_ID, | ||
1053 | + .ro = 0xffffffff, | ||
1054 | + .post_read = can_rxfifo_pre_read, | ||
1055 | + },{ .name = "RXFIFO_DLC", .addr = A_RXFIFO_DLC, | ||
1056 | + .rsvd = 0xfff0000, | ||
1057 | + .post_read = can_rxfifo_pre_read, | ||
1058 | + },{ .name = "RXFIFO_DATA1", .addr = A_RXFIFO_DATA1, | ||
1059 | + .post_read = can_rxfifo_pre_read, | ||
1060 | + },{ .name = "RXFIFO_DATA2", .addr = A_RXFIFO_DATA2, | ||
1061 | + .post_read = can_rxfifo_pre_read, | ||
1062 | + },{ .name = "AFR", .addr = A_AFR, | ||
1063 | + .rsvd = 0xfffffff0, | ||
1064 | + .post_write = can_filter_enable_post_write, | ||
1065 | + },{ .name = "AFMR1", .addr = A_AFMR1, | ||
1066 | + .pre_write = can_filter_mask_pre_write, | ||
1067 | + },{ .name = "AFIR1", .addr = A_AFIR1, | ||
1068 | + .pre_write = can_filter_id_pre_write, | ||
1069 | + },{ .name = "AFMR2", .addr = A_AFMR2, | ||
1070 | + .pre_write = can_filter_mask_pre_write, | ||
1071 | + },{ .name = "AFIR2", .addr = A_AFIR2, | ||
1072 | + .pre_write = can_filter_id_pre_write, | ||
1073 | + },{ .name = "AFMR3", .addr = A_AFMR3, | ||
1074 | + .pre_write = can_filter_mask_pre_write, | ||
1075 | + },{ .name = "AFIR3", .addr = A_AFIR3, | ||
1076 | + .pre_write = can_filter_id_pre_write, | ||
1077 | + },{ .name = "AFMR4", .addr = A_AFMR4, | ||
1078 | + .pre_write = can_filter_mask_pre_write, | ||
1079 | + },{ .name = "AFIR4", .addr = A_AFIR4, | ||
1080 | + .pre_write = can_filter_id_pre_write, | ||
1081 | + } | ||
1082 | +}; | ||
1083 | + | ||
1084 | +static void xlnx_zynqmp_can_ptimer_cb(void *opaque) | ||
1085 | +{ | ||
1086 | + /* No action required on the timer rollover. */ | ||
1087 | +} | ||
1088 | + | ||
1089 | +static const MemoryRegionOps can_ops = { | ||
1090 | + .read = register_read_memory, | ||
1091 | + .write = register_write_memory, | ||
1092 | + .endianness = DEVICE_LITTLE_ENDIAN, | ||
1093 | + .valid = { | ||
1094 | + .min_access_size = 4, | ||
1095 | + .max_access_size = 4, | ||
1096 | + }, | ||
1097 | +}; | ||
1098 | + | ||
1099 | +static void xlnx_zynqmp_can_reset_init(Object *obj, ResetType type) | ||
1100 | +{ | ||
1101 | + XlnxZynqMPCANState *s = XLNX_ZYNQMP_CAN(obj); | ||
1102 | + unsigned int i; | ||
1103 | + | ||
1104 | + for (i = R_RXFIFO_ID; i < ARRAY_SIZE(s->reg_info); ++i) { | ||
1105 | + register_reset(&s->reg_info[i]); | ||
1106 | + } | ||
1107 | + | ||
1108 | + ptimer_transaction_begin(s->can_timer); | ||
1109 | + ptimer_set_count(s->can_timer, 0); | ||
1110 | + ptimer_transaction_commit(s->can_timer); | ||
1111 | +} | ||
1112 | + | ||
1113 | +static void xlnx_zynqmp_can_reset_hold(Object *obj) | ||
1114 | +{ | ||
1115 | + XlnxZynqMPCANState *s = XLNX_ZYNQMP_CAN(obj); | ||
1116 | + unsigned int i; | ||
1117 | + | ||
1118 | + for (i = 0; i < R_RXFIFO_ID; ++i) { | ||
1119 | + register_reset(&s->reg_info[i]); | ||
1120 | + } | ||
1121 | + | ||
1122 | + /* | ||
1123 | + * Reset FIFOs when CAN model is reset. This will clear the fifo writes | ||
1124 | + * done by post_write which gets called from register_reset function, | ||
1125 | + * post_write handle will not be able to trigger tx because CAN will be | ||
1126 | + * disabled when software_reset_register is cleared first. | ||
1127 | + */ | ||
1128 | + fifo32_reset(&s->rx_fifo); | ||
1129 | + fifo32_reset(&s->tx_fifo); | ||
1130 | + fifo32_reset(&s->txhpb_fifo); | ||
1131 | +} | ||
1132 | + | ||
1133 | +static bool xlnx_zynqmp_can_can_receive(CanBusClientState *client) | ||
1134 | +{ | ||
1135 | + XlnxZynqMPCANState *s = container_of(client, XlnxZynqMPCANState, | ||
1136 | + bus_client); | ||
1137 | + | ||
1138 | + if (ARRAY_FIELD_EX32(s->regs, SOFTWARE_RESET_REGISTER, SRST)) { | ||
1139 | + g_autofree char *path = object_get_canonical_path(OBJECT(s)); | ||
1140 | + | ||
1141 | + qemu_log_mask(LOG_GUEST_ERROR, "%s: Controller is in reset state.\n", | ||
1142 | + path); | ||
1143 | + return false; | ||
1144 | + } | ||
1145 | + | ||
1146 | + if ((ARRAY_FIELD_EX32(s->regs, SOFTWARE_RESET_REGISTER, CEN)) == 0) { | ||
1147 | + g_autofree char *path = object_get_canonical_path(OBJECT(s)); | ||
1148 | + | ||
1149 | + qemu_log_mask(LOG_GUEST_ERROR, "%s: Controller is disabled. Incoming" | ||
1150 | + " messages will be discarded.\n", path); | ||
1151 | + return false; | ||
1152 | + } | ||
1153 | + | ||
1154 | + return true; | ||
1155 | +} | ||
1156 | + | ||
1157 | +static ssize_t xlnx_zynqmp_can_receive(CanBusClientState *client, | ||
1158 | + const qemu_can_frame *buf, size_t buf_size) { | ||
1159 | + XlnxZynqMPCANState *s = container_of(client, XlnxZynqMPCANState, | ||
1160 | + bus_client); | ||
1161 | + const qemu_can_frame *frame = buf; | ||
1162 | + | ||
1163 | + if (buf_size <= 0) { | ||
1164 | + g_autofree char *path = object_get_canonical_path(OBJECT(s)); | ||
1165 | + | ||
1166 | + qemu_log_mask(LOG_GUEST_ERROR, "%s: Error in the data received.\n", | ||
1167 | + path); | ||
1168 | + return 0; | ||
1169 | + } | ||
1170 | + | ||
1171 | + if (ARRAY_FIELD_EX32(s->regs, STATUS_REGISTER, SNOOP)) { | ||
1172 | + /* Snoop Mode: Just keep the data. no response back. */ | ||
1173 | + update_rx_fifo(s, frame); | ||
1174 | + } else if ((ARRAY_FIELD_EX32(s->regs, STATUS_REGISTER, SLEEP))) { | ||
1175 | + /* | ||
1176 | + * XlnxZynqMPCAN is in sleep mode. Any data on bus will bring it to wake | ||
1177 | + * up state. | ||
1178 | + */ | ||
1179 | + can_exit_sleep_mode(s); | ||
1180 | + update_rx_fifo(s, frame); | ||
1181 | + } else if ((ARRAY_FIELD_EX32(s->regs, STATUS_REGISTER, SLEEP)) == 0) { | ||
1182 | + update_rx_fifo(s, frame); | ||
1183 | + } else { | ||
1184 | + /* | ||
1185 | + * XlnxZynqMPCAN will not participate in normal bus communication | ||
1186 | + * and will not receive any messages transmitted by other CAN nodes. | ||
1187 | + */ | ||
1188 | + trace_xlnx_can_rx_discard(s->regs[R_STATUS_REGISTER]); | ||
1189 | + } | ||
1190 | + | ||
1191 | + return 1; | ||
1192 | +} | ||
1193 | + | ||
1194 | +static CanBusClientInfo can_xilinx_bus_client_info = { | ||
1195 | + .can_receive = xlnx_zynqmp_can_can_receive, | ||
1196 | + .receive = xlnx_zynqmp_can_receive, | ||
1197 | +}; | ||
1198 | + | ||
1199 | +static int xlnx_zynqmp_can_connect_to_bus(XlnxZynqMPCANState *s, | ||
1200 | + CanBusState *bus) | ||
1201 | +{ | ||
1202 | + s->bus_client.info = &can_xilinx_bus_client_info; | ||
1203 | + | ||
1204 | + if (can_bus_insert_client(bus, &s->bus_client) < 0) { | ||
1205 | + return -1; | ||
1206 | + } | ||
1207 | + return 0; | ||
1208 | +} | ||
1209 | + | ||
1210 | +static void xlnx_zynqmp_can_realize(DeviceState *dev, Error **errp) | ||
1211 | +{ | ||
1212 | + XlnxZynqMPCANState *s = XLNX_ZYNQMP_CAN(dev); | ||
1213 | + | ||
1214 | + if (s->canbus) { | ||
1215 | + if (xlnx_zynqmp_can_connect_to_bus(s, s->canbus) < 0) { | ||
1216 | + g_autofree char *path = object_get_canonical_path(OBJECT(s)); | ||
1217 | + | ||
1218 | + error_setg(errp, "%s: xlnx_zynqmp_can_connect_to_bus" | ||
1219 | + " failed.", path); | ||
1220 | + return; | ||
1221 | + } | ||
1222 | + } | ||
1223 | + | ||
1224 | + /* Create RX FIFO, TXFIFO, TXHPB storage. */ | ||
1225 | + fifo32_create(&s->rx_fifo, RXFIFO_SIZE); | ||
1226 | + fifo32_create(&s->tx_fifo, RXFIFO_SIZE); | ||
1227 | + fifo32_create(&s->txhpb_fifo, CAN_FRAME_SIZE); | ||
1228 | + | ||
1229 | + /* Allocate a new timer. */ | ||
1230 | + s->can_timer = ptimer_init(xlnx_zynqmp_can_ptimer_cb, s, | ||
1231 | + PTIMER_POLICY_DEFAULT); | ||
1232 | + | ||
1233 | + ptimer_transaction_begin(s->can_timer); | ||
1234 | + | ||
1235 | + ptimer_set_freq(s->can_timer, s->cfg.ext_clk_freq); | ||
1236 | + ptimer_set_limit(s->can_timer, CAN_TIMER_MAX, 1); | ||
1237 | + ptimer_run(s->can_timer, 0); | ||
1238 | + ptimer_transaction_commit(s->can_timer); | ||
1239 | +} | ||
1240 | + | ||
1241 | +static void xlnx_zynqmp_can_init(Object *obj) | ||
1242 | +{ | ||
1243 | + XlnxZynqMPCANState *s = XLNX_ZYNQMP_CAN(obj); | ||
1244 | + SysBusDevice *sbd = SYS_BUS_DEVICE(obj); | ||
1245 | + | ||
1246 | + RegisterInfoArray *reg_array; | ||
1247 | + | ||
1248 | + memory_region_init(&s->iomem, obj, TYPE_XLNX_ZYNQMP_CAN, | ||
1249 | + XLNX_ZYNQMP_CAN_R_MAX * 4); | ||
1250 | + reg_array = register_init_block32(DEVICE(obj), can_regs_info, | ||
1251 | + ARRAY_SIZE(can_regs_info), | ||
1252 | + s->reg_info, s->regs, | ||
1253 | + &can_ops, | ||
1254 | + XLNX_ZYNQMP_CAN_ERR_DEBUG, | ||
1255 | + XLNX_ZYNQMP_CAN_R_MAX * 4); | ||
1256 | + | ||
1257 | + memory_region_add_subregion(&s->iomem, 0x00, ®_array->mem); | ||
1258 | + sysbus_init_mmio(sbd, &s->iomem); | ||
1259 | + sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq); | ||
1260 | +} | ||
1261 | + | ||
1262 | +static const VMStateDescription vmstate_can = { | ||
1263 | + .name = TYPE_XLNX_ZYNQMP_CAN, | ||
1264 | + .version_id = 1, | ||
1265 | + .minimum_version_id = 1, | ||
1266 | + .fields = (VMStateField[]) { | ||
1267 | + VMSTATE_FIFO32(rx_fifo, XlnxZynqMPCANState), | ||
1268 | + VMSTATE_FIFO32(tx_fifo, XlnxZynqMPCANState), | ||
1269 | + VMSTATE_FIFO32(txhpb_fifo, XlnxZynqMPCANState), | ||
1270 | + VMSTATE_UINT32_ARRAY(regs, XlnxZynqMPCANState, XLNX_ZYNQMP_CAN_R_MAX), | ||
1271 | + VMSTATE_PTIMER(can_timer, XlnxZynqMPCANState), | ||
1272 | + VMSTATE_END_OF_LIST(), | ||
1273 | + } | ||
1274 | +}; | ||
1275 | + | ||
1276 | +static Property xlnx_zynqmp_can_properties[] = { | ||
1277 | + DEFINE_PROP_UINT32("ext_clk_freq", XlnxZynqMPCANState, cfg.ext_clk_freq, | ||
1278 | + CAN_DEFAULT_CLOCK), | ||
1279 | + DEFINE_PROP_LINK("canbus", XlnxZynqMPCANState, canbus, TYPE_CAN_BUS, | ||
1280 | + CanBusState *), | ||
1281 | + DEFINE_PROP_END_OF_LIST(), | ||
1282 | +}; | ||
1283 | + | ||
1284 | +static void xlnx_zynqmp_can_class_init(ObjectClass *klass, void *data) | ||
1285 | +{ | ||
1286 | + DeviceClass *dc = DEVICE_CLASS(klass); | ||
1287 | + ResettableClass *rc = RESETTABLE_CLASS(klass); | ||
1288 | + | ||
1289 | + rc->phases.enter = xlnx_zynqmp_can_reset_init; | ||
1290 | + rc->phases.hold = xlnx_zynqmp_can_reset_hold; | ||
1291 | + dc->realize = xlnx_zynqmp_can_realize; | ||
1292 | + device_class_set_props(dc, xlnx_zynqmp_can_properties); | ||
1293 | + dc->vmsd = &vmstate_can; | ||
1294 | +} | ||
1295 | + | ||
1296 | +static const TypeInfo can_info = { | ||
1297 | + .name = TYPE_XLNX_ZYNQMP_CAN, | ||
1298 | + .parent = TYPE_SYS_BUS_DEVICE, | ||
1299 | + .instance_size = sizeof(XlnxZynqMPCANState), | ||
1300 | + .class_init = xlnx_zynqmp_can_class_init, | ||
1301 | + .instance_init = xlnx_zynqmp_can_init, | ||
1302 | +}; | ||
1303 | + | ||
1304 | +static void can_register_types(void) | ||
1305 | +{ | ||
1306 | + type_register_static(&can_info); | ||
1307 | +} | ||
1308 | + | ||
1309 | +type_init(can_register_types) | ||
1310 | diff --git a/hw/Kconfig b/hw/Kconfig | ||
1311 | index XXXXXXX..XXXXXXX 100644 | ||
1312 | --- a/hw/Kconfig | ||
1313 | +++ b/hw/Kconfig | ||
1314 | @@ -XXX,XX +XXX,XX @@ config XILINX_AXI | ||
1315 | config XLNX_ZYNQMP | ||
1316 | bool | ||
1317 | select REGISTER | ||
1318 | + select CAN_BUS | ||
1319 | diff --git a/hw/net/can/meson.build b/hw/net/can/meson.build | ||
1320 | index XXXXXXX..XXXXXXX 100644 | ||
1321 | --- a/hw/net/can/meson.build | ||
1322 | +++ b/hw/net/can/meson.build | ||
1323 | @@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_CAN_PCI', if_true: files('can_pcm3680_pci.c')) | ||
1324 | softmmu_ss.add(when: 'CONFIG_CAN_PCI', if_true: files('can_mioe3680_pci.c')) | ||
1325 | softmmu_ss.add(when: 'CONFIG_CAN_CTUCANFD', if_true: files('ctucan_core.c')) | ||
1326 | softmmu_ss.add(when: 'CONFIG_CAN_CTUCANFD_PCI', if_true: files('ctucan_pci.c')) | ||
1327 | +softmmu_ss.add(when: 'CONFIG_XLNX_ZYNQMP', if_true: files('xlnx-zynqmp-can.c')) | ||
1328 | diff --git a/hw/net/can/trace-events b/hw/net/can/trace-events | ||
1329 | new file mode 100644 | ||
1330 | index XXXXXXX..XXXXXXX | ||
1331 | --- /dev/null | ||
1332 | +++ b/hw/net/can/trace-events | ||
1333 | @@ -XXX,XX +XXX,XX @@ | ||
1334 | +# xlnx-zynqmp-can.c | ||
1335 | +xlnx_can_update_irq(uint32_t isr, uint32_t ier, uint32_t irq) "ISR: 0x%08x IER: 0x%08x IRQ: 0x%08x" | ||
1336 | +xlnx_can_reset(uint32_t val) "Resetting controller with value = 0x%08x" | ||
1337 | +xlnx_can_rx_fifo_filter_reject(uint32_t id, uint8_t dlc) "Frame: ID: 0x%08x DLC: 0x%02x" | ||
1338 | +xlnx_can_filter_id_pre_write(uint8_t filter_num, uint32_t value) "Filter%d ID: 0x%08x" | ||
1339 | +xlnx_can_filter_mask_pre_write(uint8_t filter_num, uint32_t value) "Filter%d MASK: 0x%08x" | ||
1340 | +xlnx_can_tx_data(uint32_t id, uint8_t dlc, uint8_t db0, uint8_t db1, uint8_t db2, uint8_t db3, uint8_t db4, uint8_t db5, uint8_t db6, uint8_t db7) "Frame: ID: 0x%08x DLC: 0x%02x DATA: 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x" | ||
1341 | +xlnx_can_rx_data(uint32_t id, uint32_t dlc, uint8_t db0, uint8_t db1, uint8_t db2, uint8_t db3, uint8_t db4, uint8_t db5, uint8_t db6, uint8_t db7) "Frame: ID: 0x%08x DLC: 0x%02x DATA: 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x" | ||
1342 | +xlnx_can_rx_discard(uint32_t status) "Controller is not enabled for bus communication. Status Register: 0x%08x" | ||
1343 | -- | 80 | -- |
1344 | 2.20.1 | 81 | 2.25.1 |
1345 | 82 | ||
1346 | 83 | diff view generated by jsdifflib |
1 | From: Havard Skinnemoen <hskinnemoen@google.com> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Dump the collected random data after a randomness test failure. | 3 | Pass down the width of the output address from translation. |
4 | For now this is still just PAMax, but a subsequent patch will | ||
5 | compute the correct value from TCR_ELx.{I}PS. | ||
4 | 6 | ||
5 | Note that this relies on the test having called | ||
6 | g_test_set_nonfatal_assertions() so we don't abort immediately on the | ||
7 | assertion failure. | ||
8 | |||
9 | Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com> | ||
10 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
11 | [PMM: minor commit message tweak] | 8 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
9 | Message-id: 20220301215958.157011-6-richard.henderson@linaro.org | ||
12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
13 | --- | 11 | --- |
14 | tests/qtest/npcm7xx_rng-test.c | 12 ++++++++++++ | 12 | target/arm/helper.c | 21 ++++++++++----------- |
15 | 1 file changed, 12 insertions(+) | 13 | 1 file changed, 10 insertions(+), 11 deletions(-) |
16 | 14 | ||
17 | diff --git a/tests/qtest/npcm7xx_rng-test.c b/tests/qtest/npcm7xx_rng-test.c | 15 | diff --git a/target/arm/helper.c b/target/arm/helper.c |
18 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
19 | --- a/tests/qtest/npcm7xx_rng-test.c | 17 | --- a/target/arm/helper.c |
20 | +++ b/tests/qtest/npcm7xx_rng-test.c | 18 | +++ b/target/arm/helper.c |
21 | @@ -XXX,XX +XXX,XX @@ | 19 | @@ -XXX,XX +XXX,XX @@ do_fault: |
22 | 20 | * false otherwise. | |
23 | #include "libqtest-single.h" | 21 | */ |
24 | #include "qemu/bitops.h" | 22 | static bool check_s2_mmu_setup(ARMCPU *cpu, bool is_aa64, int level, |
25 | +#include "qemu-common.h" | 23 | - int inputsize, int stride) |
26 | 24 | + int inputsize, int stride, int outputsize) | |
27 | #define RNG_BASE_ADDR 0xf000b000 | ||
28 | |||
29 | @@ -XXX,XX +XXX,XX @@ | ||
30 | /* Number of bits to collect for randomness tests. */ | ||
31 | #define TEST_INPUT_BITS (128) | ||
32 | |||
33 | +static void dump_buf_if_failed(const uint8_t *buf, size_t size) | ||
34 | +{ | ||
35 | + if (g_test_failed()) { | ||
36 | + qemu_hexdump(stderr, "", buf, size); | ||
37 | + } | ||
38 | +} | ||
39 | + | ||
40 | static void rng_writeb(unsigned int offset, uint8_t value) | ||
41 | { | 25 | { |
42 | writeb(RNG_BASE_ADDR + offset, value); | 26 | const int grainsize = stride + 3; |
43 | @@ -XXX,XX +XXX,XX @@ static void test_continuous_monobit(void) | 27 | int startsizecheck; |
28 | @@ -XXX,XX +XXX,XX @@ static bool check_s2_mmu_setup(ARMCPU *cpu, bool is_aa64, int level, | ||
44 | } | 29 | } |
45 | 30 | ||
46 | g_assert_cmpfloat(calc_monobit_p(buf, sizeof(buf)), >, 0.01); | 31 | if (is_aa64) { |
47 | + dump_buf_if_failed(buf, sizeof(buf)); | 32 | - CPUARMState *env = &cpu->env; |
48 | } | 33 | - unsigned int pamax = arm_pamax(cpu); |
49 | 34 | - | |
50 | /* | 35 | switch (stride) { |
51 | @@ -XXX,XX +XXX,XX @@ static void test_continuous_runs(void) | 36 | case 13: /* 64KB Pages. */ |
37 | - if (level == 0 || (level == 1 && pamax <= 42)) { | ||
38 | + if (level == 0 || (level == 1 && outputsize <= 42)) { | ||
39 | return false; | ||
40 | } | ||
41 | break; | ||
42 | case 11: /* 16KB Pages. */ | ||
43 | - if (level == 0 || (level == 1 && pamax <= 40)) { | ||
44 | + if (level == 0 || (level == 1 && outputsize <= 40)) { | ||
45 | return false; | ||
46 | } | ||
47 | break; | ||
48 | case 9: /* 4KB Pages. */ | ||
49 | - if (level == 0 && pamax <= 42) { | ||
50 | + if (level == 0 && outputsize <= 42) { | ||
51 | return false; | ||
52 | } | ||
53 | break; | ||
54 | @@ -XXX,XX +XXX,XX @@ static bool check_s2_mmu_setup(ARMCPU *cpu, bool is_aa64, int level, | ||
55 | } | ||
56 | |||
57 | /* Inputsize checks. */ | ||
58 | - if (inputsize > pamax && | ||
59 | - (arm_el_is_aa64(env, 1) || inputsize > 40)) { | ||
60 | + if (inputsize > outputsize && | ||
61 | + (arm_el_is_aa64(&cpu->env, 1) || inputsize > 40)) { | ||
62 | /* This is CONSTRAINED UNPREDICTABLE and we choose to fault. */ | ||
63 | return false; | ||
64 | } | ||
65 | @@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, | ||
66 | target_ulong page_size; | ||
67 | uint32_t attrs; | ||
68 | int32_t stride; | ||
69 | - int addrsize, inputsize; | ||
70 | + int addrsize, inputsize, outputsize; | ||
71 | TCR *tcr = regime_tcr(env, mmu_idx); | ||
72 | int ap, ns, xn, pxn; | ||
73 | uint32_t el = regime_el(env, mmu_idx); | ||
74 | @@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, | ||
75 | |||
76 | addrsize = 64 - 8 * param.tbi; | ||
77 | inputsize = 64 - param.tsz; | ||
78 | + outputsize = arm_pamax(cpu); | ||
79 | } else { | ||
80 | param = aa32_va_parameters(env, address, mmu_idx); | ||
81 | level = 1; | ||
82 | addrsize = (mmu_idx == ARMMMUIdx_Stage2 ? 40 : 32); | ||
83 | inputsize = addrsize - param.tsz; | ||
84 | + outputsize = 40; | ||
52 | } | 85 | } |
53 | 86 | ||
54 | g_assert_cmpfloat(calc_runs_p(buf.l, sizeof(buf) * BITS_PER_BYTE), >, 0.01); | 87 | /* |
55 | + dump_buf_if_failed(buf.c, sizeof(buf)); | 88 | @@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, |
56 | } | 89 | |
57 | 90 | /* Check that the starting level is valid. */ | |
58 | /* | 91 | ok = check_s2_mmu_setup(cpu, aarch64, startlevel, |
59 | @@ -XXX,XX +XXX,XX @@ static void test_first_byte_monobit(void) | 92 | - inputsize, stride); |
60 | } | 93 | + inputsize, stride, outputsize); |
61 | 94 | if (!ok) { | |
62 | g_assert_cmpfloat(calc_monobit_p(buf, sizeof(buf)), >, 0.01); | 95 | fault_type = ARMFault_Translation; |
63 | + dump_buf_if_failed(buf, sizeof(buf)); | 96 | goto do_fault; |
64 | } | ||
65 | |||
66 | /* | ||
67 | @@ -XXX,XX +XXX,XX @@ static void test_first_byte_runs(void) | ||
68 | } | ||
69 | |||
70 | g_assert_cmpfloat(calc_runs_p(buf.l, sizeof(buf) * BITS_PER_BYTE), >, 0.01); | ||
71 | + dump_buf_if_failed(buf.c, sizeof(buf)); | ||
72 | } | ||
73 | |||
74 | int main(int argc, char **argv) | ||
75 | -- | 97 | -- |
76 | 2.20.1 | 98 | 2.25.1 |
77 | |||
78 | diff view generated by jsdifflib |
1 | From: Alex Chen <alex.chen@huawei.com> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | We should use printf format specifier "%u" instead of "%d" for | 3 | The macro is a bit more readable than the inlined computation. |
4 | argument of type "unsigned int". | ||
5 | 4 | ||
6 | Reported-by: Euler Robot <euler.robot@huawei.com> | 5 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> |
7 | Signed-off-by: Alex Chen <alex.chen@huawei.com> | 6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
8 | Message-id: 20201126111109.112238-5-alex.chen@huawei.com | 7 | Message-id: 20220301215958.157011-7-richard.henderson@linaro.org |
9 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
11 | --- | 9 | --- |
12 | hw/misc/imx6ul_ccm.c | 4 ++-- | 10 | target/arm/helper.c | 4 ++-- |
13 | 1 file changed, 2 insertions(+), 2 deletions(-) | 11 | 1 file changed, 2 insertions(+), 2 deletions(-) |
14 | 12 | ||
15 | diff --git a/hw/misc/imx6ul_ccm.c b/hw/misc/imx6ul_ccm.c | 13 | diff --git a/target/arm/helper.c b/target/arm/helper.c |
16 | index XXXXXXX..XXXXXXX 100644 | 14 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/hw/misc/imx6ul_ccm.c | 15 | --- a/target/arm/helper.c |
18 | +++ b/hw/misc/imx6ul_ccm.c | 16 | +++ b/target/arm/helper.c |
19 | @@ -XXX,XX +XXX,XX @@ static const char *imx6ul_ccm_reg_name(uint32_t reg) | 17 | @@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, |
20 | case CCM_CMEOR: | 18 | level = startlevel; |
21 | return "CMEOR"; | ||
22 | default: | ||
23 | - sprintf(unknown, "%d ?", reg); | ||
24 | + sprintf(unknown, "%u ?", reg); | ||
25 | return unknown; | ||
26 | } | 19 | } |
27 | } | 20 | |
28 | @@ -XXX,XX +XXX,XX @@ static const char *imx6ul_analog_reg_name(uint32_t reg) | 21 | - indexmask_grainsize = (1ULL << (stride + 3)) - 1; |
29 | case USB_ANALOG_DIGPROG: | 22 | - indexmask = (1ULL << (inputsize - (stride * (4 - level)))) - 1; |
30 | return "USB_ANALOG_DIGPROG"; | 23 | + indexmask_grainsize = MAKE_64BIT_MASK(0, stride + 3); |
31 | default: | 24 | + indexmask = MAKE_64BIT_MASK(0, inputsize - (stride * (4 - level))); |
32 | - sprintf(unknown, "%d ?", reg); | 25 | |
33 | + sprintf(unknown, "%u ?", reg); | 26 | /* Now we can extract the actual base address from the TTBR */ |
34 | return unknown; | 27 | descaddr = extract64(ttbr, 0, 48); |
35 | } | ||
36 | } | ||
37 | -- | 28 | -- |
38 | 2.20.1 | 29 | 2.25.1 |
39 | 30 | ||
40 | 31 | diff view generated by jsdifflib |
1 | In commit 077d7449100d824a4 we added code to handle the v8M | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | requirement that returns from NMI or HardFault forcibly deactivate | ||
3 | those exceptions regardless of what interrupt the guest is trying to | ||
4 | deactivate. Unfortunately this broke the handling of the "illegal | ||
5 | exception return because the returning exception number is not | ||
6 | active" check for those cases. In the pseudocode this test is done | ||
7 | on the exception the guest asks to return from, but because our | ||
8 | implementation was doing this in armv7m_nvic_complete_irq() after the | ||
9 | new "deactivate NMI/HardFault regardless" code we ended up doing the | ||
10 | test on the VecInfo for that exception instead, which usually meant | ||
11 | failing to raise the illegal exception return fault. | ||
12 | 2 | ||
13 | In the case for "configurable exception targeting the opposite | 3 | This field controls the output (intermediate) physical address size |
14 | security state" we detected the illegal-return case but went ahead | 4 | of the translation process. V8 requires to raise an AddressSize |
15 | and deactivated the VecInfo anyway, which is wrong because that is | 5 | fault if the page tables are programmed incorrectly, such that any |
16 | the VecInfo for the other security state. | 6 | intermediate descriptor address, or the final translated address, |
7 | is out of range. | ||
17 | 8 | ||
18 | Rearrange the code so that we first identify the illegal return | 9 | Add a PS field to ARMVAParameters, and properly compute outputsize |
19 | cases, then see if we really need to deactivate NMI or HardFault | 10 | in get_phys_addr_lpae. Test the descaddr as extracted from TTBR |
20 | instead, and finally do the deactivation. | 11 | and from page table entries. |
21 | 12 | ||
13 | Restrict descaddrmask so that we won't raise the fault for v7. | ||
14 | |||
15 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
16 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | ||
17 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
18 | Message-id: 20220301215958.157011-8-richard.henderson@linaro.org | ||
22 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 19 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
23 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
24 | Message-id: 20201119215617.29887-25-peter.maydell@linaro.org | ||
25 | --- | 20 | --- |
26 | hw/intc/armv7m_nvic.c | 59 +++++++++++++++++++++++-------------------- | 21 | target/arm/internals.h | 1 + |
27 | 1 file changed, 32 insertions(+), 27 deletions(-) | 22 | target/arm/helper.c | 72 ++++++++++++++++++++++++++++++++---------- |
23 | 2 files changed, 57 insertions(+), 16 deletions(-) | ||
28 | 24 | ||
29 | diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c | 25 | diff --git a/target/arm/internals.h b/target/arm/internals.h |
30 | index XXXXXXX..XXXXXXX 100644 | 26 | index XXXXXXX..XXXXXXX 100644 |
31 | --- a/hw/intc/armv7m_nvic.c | 27 | --- a/target/arm/internals.h |
32 | +++ b/hw/intc/armv7m_nvic.c | 28 | +++ b/target/arm/internals.h |
33 | @@ -XXX,XX +XXX,XX @@ int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure) | 29 | @@ -XXX,XX +XXX,XX @@ static inline uint32_t aarch64_pstate_valid_mask(const ARMISARegisters *id) |
30 | */ | ||
31 | typedef struct ARMVAParameters { | ||
32 | unsigned tsz : 8; | ||
33 | + unsigned ps : 3; | ||
34 | unsigned select : 1; | ||
35 | bool tbi : 1; | ||
36 | bool epd : 1; | ||
37 | diff --git a/target/arm/helper.c b/target/arm/helper.c | ||
38 | index XXXXXXX..XXXXXXX 100644 | ||
39 | --- a/target/arm/helper.c | ||
40 | +++ b/target/arm/helper.c | ||
41 | @@ -XXX,XX +XXX,XX @@ static uint8_t convert_stage2_attrs(CPUARMState *env, uint8_t s2attrs) | ||
42 | } | ||
43 | #endif /* !CONFIG_USER_ONLY */ | ||
44 | |||
45 | +/* This mapping is common between ID_AA64MMFR0.PARANGE and TCR_ELx.{I}PS. */ | ||
46 | +static const uint8_t pamax_map[] = { | ||
47 | + [0] = 32, | ||
48 | + [1] = 36, | ||
49 | + [2] = 40, | ||
50 | + [3] = 42, | ||
51 | + [4] = 44, | ||
52 | + [5] = 48, | ||
53 | +}; | ||
54 | + | ||
55 | /* The cpu-specific constant value of PAMax; also used by hw/arm/virt. */ | ||
56 | unsigned int arm_pamax(ARMCPU *cpu) | ||
34 | { | 57 | { |
35 | NVICState *s = (NVICState *)opaque; | 58 | - static const unsigned int pamax_map[] = { |
36 | VecInfo *vec = NULL; | 59 | - [0] = 32, |
37 | - int ret; | 60 | - [1] = 36, |
38 | + int ret = 0; | 61 | - [2] = 40, |
39 | 62 | - [3] = 42, | |
40 | assert(irq > ARMV7M_EXCP_RESET && irq < s->num_irq); | 63 | - [4] = 44, |
41 | 64 | - [5] = 48, | |
42 | + trace_nvic_complete_irq(irq, secure); | 65 | - }; |
66 | unsigned int parange = | ||
67 | FIELD_EX64(cpu->isar.id_aa64mmfr0, ID_AA64MMFR0, PARANGE); | ||
68 | |||
69 | @@ -XXX,XX +XXX,XX @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, | ||
70 | { | ||
71 | uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr; | ||
72 | bool epd, hpd, using16k, using64k, tsz_oob; | ||
73 | - int select, tsz, tbi, max_tsz, min_tsz; | ||
74 | + int select, tsz, tbi, max_tsz, min_tsz, ps; | ||
75 | |||
76 | if (!regime_has_2_ranges(mmu_idx)) { | ||
77 | select = 0; | ||
78 | @@ -XXX,XX +XXX,XX @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, | ||
79 | hpd = extract32(tcr, 24, 1); | ||
80 | } | ||
81 | epd = false; | ||
82 | + ps = extract32(tcr, 16, 3); | ||
83 | } else { | ||
84 | /* | ||
85 | * Bit 55 is always between the two regions, and is canonical for | ||
86 | @@ -XXX,XX +XXX,XX @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, | ||
87 | epd = extract32(tcr, 23, 1); | ||
88 | hpd = extract64(tcr, 42, 1); | ||
89 | } | ||
90 | + ps = extract64(tcr, 32, 3); | ||
91 | } | ||
92 | |||
93 | if (cpu_isar_feature(aa64_st, env_archcpu(env))) { | ||
94 | @@ -XXX,XX +XXX,XX @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, | ||
95 | |||
96 | return (ARMVAParameters) { | ||
97 | .tsz = tsz, | ||
98 | + .ps = ps, | ||
99 | .select = select, | ||
100 | .tbi = tbi, | ||
101 | .epd = epd, | ||
102 | @@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, | ||
103 | |||
104 | /* TODO: This code does not support shareability levels. */ | ||
105 | if (aarch64) { | ||
106 | + int ps; | ||
43 | + | 107 | + |
44 | + if (secure && exc_is_banked(irq)) { | 108 | param = aa64_va_parameters(env, address, mmu_idx, |
45 | + vec = &s->sec_vectors[irq]; | 109 | access_type != MMU_INST_FETCH); |
46 | + } else { | 110 | level = 0; |
47 | + vec = &s->vectors[irq]; | 111 | @@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, |
48 | + } | 112 | |
113 | addrsize = 64 - 8 * param.tbi; | ||
114 | inputsize = 64 - param.tsz; | ||
115 | - outputsize = arm_pamax(cpu); | ||
116 | + | ||
117 | + /* | ||
118 | + * Bound PS by PARANGE to find the effective output address size. | ||
119 | + * ID_AA64MMFR0 is a read-only register so values outside of the | ||
120 | + * supported mappings can be considered an implementation error. | ||
121 | + */ | ||
122 | + ps = FIELD_EX64(cpu->isar.id_aa64mmfr0, ID_AA64MMFR0, PARANGE); | ||
123 | + ps = MIN(ps, param.ps); | ||
124 | + assert(ps < ARRAY_SIZE(pamax_map)); | ||
125 | + outputsize = pamax_map[ps]; | ||
126 | } else { | ||
127 | param = aa32_va_parameters(env, address, mmu_idx); | ||
128 | level = 1; | ||
129 | @@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, | ||
130 | |||
131 | /* Now we can extract the actual base address from the TTBR */ | ||
132 | descaddr = extract64(ttbr, 0, 48); | ||
49 | + | 133 | + |
50 | + /* | 134 | + /* |
51 | + * Identify illegal exception return cases. We can't immediately | 135 | + * If the base address is out of range, raise AddressSizeFault. |
52 | + * return at this point because we still need to deactivate | 136 | + * In the pseudocode, this is !IsZero(baseregister<47:outputsize>), |
53 | + * (either this exception or NMI/HardFault) first. | 137 | + * but we've just cleared the bits above 47, so simplify the test. |
54 | + */ | 138 | + */ |
55 | + if (!exc_is_banked(irq) && exc_targets_secure(s, irq) != secure) { | 139 | + if (descaddr >> outputsize) { |
56 | + /* | 140 | + level = 0; |
57 | + * Return from a configurable exception targeting the opposite | 141 | + fault_type = ARMFault_AddressSize; |
58 | + * security state from the one we're trying to complete it for. | 142 | + goto do_fault; |
59 | + * Clear vec because it's not really the VecInfo for this | ||
60 | + * (irq, secstate) so we mustn't deactivate it. | ||
61 | + */ | ||
62 | + ret = -1; | ||
63 | + vec = NULL; | ||
64 | + } else if (!vec->active) { | ||
65 | + /* Return from an inactive interrupt */ | ||
66 | + ret = -1; | ||
67 | + } else { | ||
68 | + /* Legal return, we will return the RETTOBASE bit value to the caller */ | ||
69 | + ret = nvic_rettobase(s); | ||
70 | + } | 143 | + } |
71 | + | 144 | + |
72 | /* | 145 | /* |
73 | * For negative priorities, v8M will forcibly deactivate the appropriate | 146 | * We rely on this masking to clear the RES0 bits at the bottom of the TTBR |
74 | * NMI or HardFault regardless of what interrupt we're being asked to | 147 | * and also to mask out CnP (bit 0) which could validly be non-zero. |
75 | @@ -XXX,XX +XXX,XX @@ int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure) | 148 | */ |
76 | } | 149 | descaddr &= ~indexmask; |
77 | 150 | ||
78 | if (!vec) { | 151 | - /* The address field in the descriptor goes up to bit 39 for ARMv7 |
79 | - if (secure && exc_is_banked(irq)) { | 152 | - * but up to bit 47 for ARMv8, but we use the descaddrmask |
80 | - vec = &s->sec_vectors[irq]; | 153 | - * up to bit 39 for AArch32, because we don't need other bits in that case |
81 | - } else { | 154 | - * to construct next descriptor address (anyway they should be all zeroes). |
82 | - vec = &s->vectors[irq]; | 155 | + /* |
83 | - } | 156 | + * For AArch32, the address field in the descriptor goes up to bit 39 |
84 | - } | 157 | + * for both v7 and v8. However, for v8 the SBZ bits [47:40] must be 0 |
85 | - | 158 | + * or an AddressSize fault is raised. So for v8 we extract those SBZ |
86 | - trace_nvic_complete_irq(irq, secure); | 159 | + * bits as part of the address, which will be checked via outputsize. |
87 | - | 160 | + * For AArch64, the address field always goes up to bit 47 (with extra |
88 | - if (!vec->active) { | 161 | + * bits for FEAT_LPA placed elsewhere). AArch64 implies v8. |
89 | - /* Tell the caller this was an illegal exception return */ | 162 | */ |
90 | - return -1; | 163 | - descaddrmask = ((1ull << (aarch64 ? 48 : 40)) - 1) & |
91 | - } | 164 | - ~indexmask_grainsize; |
92 | - | 165 | + if (arm_feature(env, ARM_FEATURE_V8)) { |
93 | - /* | 166 | + descaddrmask = MAKE_64BIT_MASK(0, 48); |
94 | - * If this is a configurable exception and it is currently | 167 | + } else { |
95 | - * targeting the opposite security state from the one we're trying | 168 | + descaddrmask = MAKE_64BIT_MASK(0, 40); |
96 | - * to complete it for, this counts as an illegal exception return. | 169 | + } |
97 | - * We still need to deactivate whatever vector the logic above has | 170 | + descaddrmask &= ~indexmask_grainsize; |
98 | - * selected, though, as it might not be the same as the one for the | 171 | |
99 | - * requested exception number. | 172 | /* Secure accesses start with the page table in secure memory and |
100 | - */ | 173 | * can be downgraded to non-secure at any step. Non-secure accesses |
101 | - if (!exc_is_banked(irq) && exc_targets_secure(s, irq) != secure) { | 174 | @@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, |
102 | - ret = -1; | 175 | /* Invalid, or the Reserved level 3 encoding */ |
103 | - } else { | 176 | goto do_fault; |
104 | - ret = nvic_rettobase(s); | 177 | } |
105 | + return ret; | 178 | + |
106 | } | 179 | descaddr = descriptor & descaddrmask; |
107 | 180 | + if (descaddr >> outputsize) { | |
108 | vec->active = 0; | 181 | + fault_type = ARMFault_AddressSize; |
182 | + goto do_fault; | ||
183 | + } | ||
184 | |||
185 | if ((descriptor & 2) && (level < 3)) { | ||
186 | /* Table entry. The top five bits are attributes which may | ||
109 | -- | 187 | -- |
110 | 2.20.1 | 188 | 2.25.1 |
111 | 189 | ||
112 | 190 | diff view generated by jsdifflib |
1 | From: Alex Chen <alex.chen@huawei.com> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | We should use printf format specifier "%u" instead of "%d" for | 3 | The original A.a revision of the AArch64 ARM required that we |
4 | argument of type "unsigned int". | 4 | force-extend the addresses in these registers from 49 bits. |
5 | This language has been loosened via a combination of IMPLEMENTATION | ||
6 | DEFINED and CONSTRAINTED UNPREDICTABLE to allow consideration of | ||
7 | the entire aligned address. | ||
5 | 8 | ||
6 | Reported-by: Euler Robot <euler.robot@huawei.com> | 9 | This means that we do not have to consider whether or not FEAT_LVA |
7 | Signed-off-by: Alex Chen <alex.chen@huawei.com> | 10 | is enabled, and decide from which bit an address might need to be |
8 | Message-id: 20201126111109.112238-3-alex.chen@huawei.com | 11 | extended. |
12 | |||
9 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 13 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
14 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
15 | Message-id: 20220301215958.157011-9-richard.henderson@linaro.org | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 16 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
11 | --- | 17 | --- |
12 | hw/misc/imx31_ccm.c | 14 +++++++------- | 18 | target/arm/helper.c | 32 ++++++++++++++++++++++++-------- |
13 | hw/misc/imx_ccm.c | 4 ++-- | 19 | 1 file changed, 24 insertions(+), 8 deletions(-) |
14 | 2 files changed, 9 insertions(+), 9 deletions(-) | ||
15 | 20 | ||
16 | diff --git a/hw/misc/imx31_ccm.c b/hw/misc/imx31_ccm.c | 21 | diff --git a/target/arm/helper.c b/target/arm/helper.c |
17 | index XXXXXXX..XXXXXXX 100644 | 22 | index XXXXXXX..XXXXXXX 100644 |
18 | --- a/hw/misc/imx31_ccm.c | 23 | --- a/target/arm/helper.c |
19 | +++ b/hw/misc/imx31_ccm.c | 24 | +++ b/target/arm/helper.c |
20 | @@ -XXX,XX +XXX,XX @@ static const char *imx31_ccm_reg_name(uint32_t reg) | 25 | @@ -XXX,XX +XXX,XX @@ static void dbgwvr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
21 | case IMX31_CCM_PDR2_REG: | 26 | ARMCPU *cpu = env_archcpu(env); |
22 | return "PDR2"; | 27 | int i = ri->crm; |
23 | default: | 28 | |
24 | - sprintf(unknown, "[%d ?]", reg); | 29 | - /* Bits [63:49] are hardwired to the value of bit [48]; that is, the |
25 | + sprintf(unknown, "[%u ?]", reg); | 30 | - * register reads and behaves as if values written are sign extended. |
26 | return unknown; | 31 | + /* |
27 | } | 32 | * Bits [1:0] are RES0. |
28 | } | 33 | + * |
29 | @@ -XXX,XX +XXX,XX @@ static uint32_t imx31_ccm_get_pll_ref_clk(IMXCCMState *dev) | 34 | + * It is IMPLEMENTATION DEFINED whether [63:49] ([63:53] with FEAT_LVA) |
30 | freq = CKIH_FREQ; | 35 | + * are hardwired to the value of bit [48] ([52] with FEAT_LVA), or if |
31 | } | 36 | + * they contain the value written. It is CONSTRAINED UNPREDICTABLE |
32 | 37 | + * whether the RESS bits are ignored when comparing an address. | |
33 | - DPRINTF("freq = %d\n", freq); | 38 | + * |
34 | + DPRINTF("freq = %u\n", freq); | 39 | + * Therefore we are allowed to compare the entire register, which lets |
35 | 40 | + * us avoid considering whether or not FEAT_LVA is actually enabled. | |
36 | return freq; | 41 | */ |
37 | } | 42 | - value = sextract64(value, 0, 49) & ~3ULL; |
38 | @@ -XXX,XX +XXX,XX @@ static uint32_t imx31_ccm_get_mpll_clk(IMXCCMState *dev) | 43 | + value &= ~3ULL; |
39 | freq = imx_ccm_calc_pll(s->reg[IMX31_CCM_MPCTL_REG], | 44 | |
40 | imx31_ccm_get_pll_ref_clk(dev)); | 45 | raw_write(env, ri, value); |
41 | 46 | hw_watchpoint_update(cpu, i); | |
42 | - DPRINTF("freq = %d\n", freq); | 47 | @@ -XXX,XX +XXX,XX @@ void hw_breakpoint_update(ARMCPU *cpu, int n) |
43 | + DPRINTF("freq = %u\n", freq); | 48 | case 0: /* unlinked address match */ |
44 | 49 | case 1: /* linked address match */ | |
45 | return freq; | 50 | { |
46 | } | 51 | - /* Bits [63:49] are hardwired to the value of bit [48]; that is, |
47 | @@ -XXX,XX +XXX,XX @@ static uint32_t imx31_ccm_get_mcu_main_clk(IMXCCMState *dev) | 52 | - * we behave as if the register was sign extended. Bits [1:0] are |
48 | freq = imx31_ccm_get_mpll_clk(dev); | 53 | - * RES0. The BAS field is used to allow setting breakpoints on 16 |
49 | } | 54 | - * bit wide instructions; it is CONSTRAINED UNPREDICTABLE whether |
50 | 55 | + /* | |
51 | - DPRINTF("freq = %d\n", freq); | 56 | + * Bits [1:0] are RES0. |
52 | + DPRINTF("freq = %u\n", freq); | 57 | + * |
53 | 58 | + * It is IMPLEMENTATION DEFINED whether bits [63:49] | |
54 | return freq; | 59 | + * ([63:53] for FEAT_LVA) are hardwired to a copy of the sign bit |
55 | } | 60 | + * of the VA field ([48] or [52] for FEAT_LVA), or whether the |
56 | @@ -XXX,XX +XXX,XX @@ static uint32_t imx31_ccm_get_hclk_clk(IMXCCMState *dev) | 61 | + * value is read as written. It is CONSTRAINED UNPREDICTABLE |
57 | freq = imx31_ccm_get_mcu_main_clk(dev) | 62 | + * whether the RESS bits are ignored when comparing an address. |
58 | / (1 + EXTRACT(s->reg[IMX31_CCM_PDR0_REG], MAX)); | 63 | + * Therefore we are allowed to compare the entire register, which |
59 | 64 | + * lets us avoid considering whether FEAT_LVA is actually enabled. | |
60 | - DPRINTF("freq = %d\n", freq); | 65 | + * |
61 | + DPRINTF("freq = %u\n", freq); | 66 | + * The BAS field is used to allow setting breakpoints on 16-bit |
62 | 67 | + * wide instructions; it is CONSTRAINED UNPREDICTABLE whether | |
63 | return freq; | 68 | * a bp will fire if the addresses covered by the bp and the addresses |
64 | } | 69 | * covered by the insn overlap but the insn doesn't start at the |
65 | @@ -XXX,XX +XXX,XX @@ static uint32_t imx31_ccm_get_ipg_clk(IMXCCMState *dev) | 70 | * start of the bp address range. We choose to require the insn and |
66 | freq = imx31_ccm_get_hclk_clk(dev) | 71 | @@ -XXX,XX +XXX,XX @@ void hw_breakpoint_update(ARMCPU *cpu, int n) |
67 | / (1 + EXTRACT(s->reg[IMX31_CCM_PDR0_REG], IPG)); | 72 | * See also figure D2-3 in the v8 ARM ARM (DDI0487A.c). |
68 | 73 | */ | |
69 | - DPRINTF("freq = %d\n", freq); | 74 | int bas = extract64(bcr, 5, 4); |
70 | + DPRINTF("freq = %u\n", freq); | 75 | - addr = sextract64(bvr, 0, 49) & ~3ULL; |
71 | 76 | + addr = bvr & ~3ULL; | |
72 | return freq; | 77 | if (bas == 0) { |
73 | } | 78 | return; |
74 | @@ -XXX,XX +XXX,XX @@ static uint32_t imx31_ccm_get_clock_frequency(IMXCCMState *dev, IMXClk clock) | 79 | } |
75 | break; | ||
76 | } | ||
77 | |||
78 | - DPRINTF("Clock = %d) = %d\n", clock, freq); | ||
79 | + DPRINTF("Clock = %d) = %u\n", clock, freq); | ||
80 | |||
81 | return freq; | ||
82 | } | ||
83 | diff --git a/hw/misc/imx_ccm.c b/hw/misc/imx_ccm.c | ||
84 | index XXXXXXX..XXXXXXX 100644 | ||
85 | --- a/hw/misc/imx_ccm.c | ||
86 | +++ b/hw/misc/imx_ccm.c | ||
87 | @@ -XXX,XX +XXX,XX @@ uint32_t imx_ccm_get_clock_frequency(IMXCCMState *dev, IMXClk clock) | ||
88 | freq = klass->get_clock_frequency(dev, clock); | ||
89 | } | ||
90 | |||
91 | - DPRINTF("(clock = %d) = %d\n", clock, freq); | ||
92 | + DPRINTF("(clock = %d) = %u\n", clock, freq); | ||
93 | |||
94 | return freq; | ||
95 | } | ||
96 | @@ -XXX,XX +XXX,XX @@ uint32_t imx_ccm_calc_pll(uint32_t pllreg, uint32_t base_freq) | ||
97 | freq = ((2 * (base_freq >> 10) * (mfi * mfd + mfn)) / | ||
98 | (mfd * pd)) << 10; | ||
99 | |||
100 | - DPRINTF("(pllreg = 0x%08x, base_freq = %d) = %d\n", pllreg, base_freq, | ||
101 | + DPRINTF("(pllreg = 0x%08x, base_freq = %u) = %d\n", pllreg, base_freq, | ||
102 | freq); | ||
103 | |||
104 | return freq; | ||
105 | -- | 80 | -- |
106 | 2.20.1 | 81 | 2.25.1 |
107 | |||
108 | diff view generated by jsdifflib |
1 | Currently M-profile borrows the A-profile code for VMSR and VMRS | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | (access to the FP system registers), because all it needs to support | ||
3 | is the FPSCR. In v8.1M things become significantly more complicated | ||
4 | in two ways: | ||
5 | 2 | ||
6 | * there are several new FP system registers; some have side effects | 3 | This feature is relatively small, as it applies only to |
7 | on read, and one (FPCXT_NS) needs to avoid the usual | 4 | 64k pages and thus requires no additional changes to the |
8 | vfp_access_check() and the "only if FPU implemented" check | 5 | table descriptor walking algorithm, only a change to the |
6 | minimum TSZ (which is the inverse of the maximum virtual | ||
7 | address space size). | ||
9 | 8 | ||
10 | * all sysregs are now accessible both by VMRS/VMSR (which | 9 | Note that this feature widens VBAR_ELx, but we already |
11 | reads/writes a general purpose register) and also by VLDR/VSTR | 10 | treat the register as being 64 bits wide. |
12 | (which reads/writes them directly to memory) | ||
13 | 11 | ||
14 | Refactor the structure of how we handle VMSR/VMRS to cope with this: | 12 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
13 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
14 | Message-id: 20220301215958.157011-10-richard.henderson@linaro.org | ||
15 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
16 | --- | ||
17 | docs/system/arm/emulation.rst | 1 + | ||
18 | target/arm/cpu-param.h | 2 +- | ||
19 | target/arm/cpu.h | 5 +++++ | ||
20 | target/arm/cpu64.c | 1 + | ||
21 | target/arm/helper.c | 9 ++++++++- | ||
22 | 5 files changed, 16 insertions(+), 2 deletions(-) | ||
15 | 23 | ||
16 | * keep the M-profile code entirely separate from the A-profile code | 24 | diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst |
17 | 25 | index XXXXXXX..XXXXXXX 100644 | |
18 | * abstract out the "read or write the general purpose register" part | 26 | --- a/docs/system/arm/emulation.rst |
19 | of the code into a loadfn or storefn function pointer, so we can | 27 | +++ b/docs/system/arm/emulation.rst |
20 | reuse it for VLDR/VSTR. | 28 | @@ -XXX,XX +XXX,XX @@ the following architecture extensions: |
21 | 29 | - FEAT_LRCPC (Load-acquire RCpc instructions) | |
22 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 30 | - FEAT_LRCPC2 (Load-acquire RCpc instructions v2) |
23 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 31 | - FEAT_LSE (Large System Extensions) |
24 | Message-id: 20201119215617.29887-8-peter.maydell@linaro.org | 32 | +- FEAT_LVA (Large Virtual Address space) |
25 | --- | 33 | - FEAT_MTE (Memory Tagging Extension) |
26 | target/arm/cpu.h | 3 + | 34 | - FEAT_MTE2 (Memory Tagging Extension) |
27 | target/arm/translate-vfp.c.inc | 182 ++++++++++++++++++++++++++++++--- | 35 | - FEAT_MTE3 (MTE Asymmetric Fault Handling) |
28 | 2 files changed, 171 insertions(+), 14 deletions(-) | 36 | diff --git a/target/arm/cpu-param.h b/target/arm/cpu-param.h |
29 | 37 | index XXXXXXX..XXXXXXX 100644 | |
38 | --- a/target/arm/cpu-param.h | ||
39 | +++ b/target/arm/cpu-param.h | ||
40 | @@ -XXX,XX +XXX,XX @@ | ||
41 | #ifdef TARGET_AARCH64 | ||
42 | # define TARGET_LONG_BITS 64 | ||
43 | # define TARGET_PHYS_ADDR_SPACE_BITS 48 | ||
44 | -# define TARGET_VIRT_ADDR_SPACE_BITS 48 | ||
45 | +# define TARGET_VIRT_ADDR_SPACE_BITS 52 | ||
46 | #else | ||
47 | # define TARGET_LONG_BITS 32 | ||
48 | # define TARGET_PHYS_ADDR_SPACE_BITS 40 | ||
30 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | 49 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h |
31 | index XXXXXXX..XXXXXXX 100644 | 50 | index XXXXXXX..XXXXXXX 100644 |
32 | --- a/target/arm/cpu.h | 51 | --- a/target/arm/cpu.h |
33 | +++ b/target/arm/cpu.h | 52 | +++ b/target/arm/cpu.h |
34 | @@ -XXX,XX +XXX,XX @@ enum arm_cpu_mode { | 53 | @@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_ccidx(const ARMISARegisters *id) |
35 | #define ARM_VFP_FPINST 9 | 54 | return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, CCIDX) != 0; |
36 | #define ARM_VFP_FPINST2 10 | ||
37 | |||
38 | +/* QEMU-internal value meaning "FPSCR, but we care only about NZCV" */ | ||
39 | +#define QEMU_VFP_FPSCR_NZCV 0xffff | ||
40 | + | ||
41 | /* iwMMXt coprocessor control registers. */ | ||
42 | #define ARM_IWMMXT_wCID 0 | ||
43 | #define ARM_IWMMXT_wCon 1 | ||
44 | diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc | ||
45 | index XXXXXXX..XXXXXXX 100644 | ||
46 | --- a/target/arm/translate-vfp.c.inc | ||
47 | +++ b/target/arm/translate-vfp.c.inc | ||
48 | @@ -XXX,XX +XXX,XX @@ static bool trans_VDUP(DisasContext *s, arg_VDUP *a) | ||
49 | return true; | ||
50 | } | 55 | } |
51 | 56 | ||
52 | +/* | 57 | +static inline bool isar_feature_aa64_lva(const ARMISARegisters *id) |
53 | + * M-profile provides two different sets of instructions that can | ||
54 | + * access floating point system registers: VMSR/VMRS (which move | ||
55 | + * to/from a general purpose register) and VLDR/VSTR sysreg (which | ||
56 | + * move directly to/from memory). In some cases there are also side | ||
57 | + * effects which must happen after any write to memory (which could | ||
58 | + * cause an exception). So we implement the common logic for the | ||
59 | + * sysreg access in gen_M_fp_sysreg_write() and gen_M_fp_sysreg_read(), | ||
60 | + * which take pointers to callback functions which will perform the | ||
61 | + * actual "read/write general purpose register" and "read/write | ||
62 | + * memory" operations. | ||
63 | + */ | ||
64 | + | ||
65 | +/* | ||
66 | + * Emit code to store the sysreg to its final destination; frees the | ||
67 | + * TCG temp 'value' it is passed. | ||
68 | + */ | ||
69 | +typedef void fp_sysreg_storefn(DisasContext *s, void *opaque, TCGv_i32 value); | ||
70 | +/* | ||
71 | + * Emit code to load the value to be copied to the sysreg; returns | ||
72 | + * a new TCG temporary | ||
73 | + */ | ||
74 | +typedef TCGv_i32 fp_sysreg_loadfn(DisasContext *s, void *opaque); | ||
75 | + | ||
76 | +/* Common decode/access checks for fp sysreg read/write */ | ||
77 | +typedef enum FPSysRegCheckResult { | ||
78 | + FPSysRegCheckFailed, /* caller should return false */ | ||
79 | + FPSysRegCheckDone, /* caller should return true */ | ||
80 | + FPSysRegCheckContinue, /* caller should continue generating code */ | ||
81 | +} FPSysRegCheckResult; | ||
82 | + | ||
83 | +static FPSysRegCheckResult fp_sysreg_checks(DisasContext *s, int regno) | ||
84 | +{ | 58 | +{ |
85 | + if (!dc_isar_feature(aa32_fpsp_v2, s)) { | 59 | + return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, VARANGE) != 0; |
86 | + return FPSysRegCheckFailed; | ||
87 | + } | ||
88 | + | ||
89 | + switch (regno) { | ||
90 | + case ARM_VFP_FPSCR: | ||
91 | + case QEMU_VFP_FPSCR_NZCV: | ||
92 | + break; | ||
93 | + default: | ||
94 | + return FPSysRegCheckFailed; | ||
95 | + } | ||
96 | + | ||
97 | + if (!vfp_access_check(s)) { | ||
98 | + return FPSysRegCheckDone; | ||
99 | + } | ||
100 | + | ||
101 | + return FPSysRegCheckContinue; | ||
102 | +} | 60 | +} |
103 | + | 61 | + |
104 | +static bool gen_M_fp_sysreg_write(DisasContext *s, int regno, | 62 | static inline bool isar_feature_aa64_tts2uxn(const ARMISARegisters *id) |
63 | { | ||
64 | return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, XNX) != 0; | ||
65 | diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c | ||
66 | index XXXXXXX..XXXXXXX 100644 | ||
67 | --- a/target/arm/cpu64.c | ||
68 | +++ b/target/arm/cpu64.c | ||
69 | @@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj) | ||
70 | t = FIELD_DP64(t, ID_AA64MMFR2, UAO, 1); | ||
71 | t = FIELD_DP64(t, ID_AA64MMFR2, CNP, 1); /* TTCNP */ | ||
72 | t = FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* TTST */ | ||
73 | + t = FIELD_DP64(t, ID_AA64MMFR2, VARANGE, 1); /* FEAT_LVA */ | ||
74 | cpu->isar.id_aa64mmfr2 = t; | ||
75 | |||
76 | t = cpu->isar.id_aa64zfr0; | ||
77 | diff --git a/target/arm/helper.c b/target/arm/helper.c | ||
78 | index XXXXXXX..XXXXXXX 100644 | ||
79 | --- a/target/arm/helper.c | ||
80 | +++ b/target/arm/helper.c | ||
81 | @@ -XXX,XX +XXX,XX @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, | ||
82 | } else { | ||
83 | max_tsz = 39; | ||
84 | } | ||
85 | - min_tsz = 16; /* TODO: ARMv8.2-LVA */ | ||
105 | + | 86 | + |
106 | + fp_sysreg_loadfn *loadfn, | 87 | + min_tsz = 16; |
107 | + void *opaque) | 88 | + if (using64k) { |
108 | +{ | 89 | + if (cpu_isar_feature(aa64_lva, env_archcpu(env))) { |
109 | + /* Do a write to an M-profile floating point system register */ | 90 | + min_tsz = 12; |
110 | + TCGv_i32 tmp; | ||
111 | + | ||
112 | + switch (fp_sysreg_checks(s, regno)) { | ||
113 | + case FPSysRegCheckFailed: | ||
114 | + return false; | ||
115 | + case FPSysRegCheckDone: | ||
116 | + return true; | ||
117 | + case FPSysRegCheckContinue: | ||
118 | + break; | ||
119 | + } | ||
120 | + | ||
121 | + switch (regno) { | ||
122 | + case ARM_VFP_FPSCR: | ||
123 | + tmp = loadfn(s, opaque); | ||
124 | + gen_helper_vfp_set_fpscr(cpu_env, tmp); | ||
125 | + tcg_temp_free_i32(tmp); | ||
126 | + gen_lookup_tb(s); | ||
127 | + break; | ||
128 | + default: | ||
129 | + g_assert_not_reached(); | ||
130 | + } | ||
131 | + return true; | ||
132 | +} | ||
133 | + | ||
134 | +static bool gen_M_fp_sysreg_read(DisasContext *s, int regno, | ||
135 | + fp_sysreg_storefn *storefn, | ||
136 | + void *opaque) | ||
137 | +{ | ||
138 | + /* Do a read from an M-profile floating point system register */ | ||
139 | + TCGv_i32 tmp; | ||
140 | + | ||
141 | + switch (fp_sysreg_checks(s, regno)) { | ||
142 | + case FPSysRegCheckFailed: | ||
143 | + return false; | ||
144 | + case FPSysRegCheckDone: | ||
145 | + return true; | ||
146 | + case FPSysRegCheckContinue: | ||
147 | + break; | ||
148 | + } | ||
149 | + | ||
150 | + switch (regno) { | ||
151 | + case ARM_VFP_FPSCR: | ||
152 | + tmp = tcg_temp_new_i32(); | ||
153 | + gen_helper_vfp_get_fpscr(tmp, cpu_env); | ||
154 | + storefn(s, opaque, tmp); | ||
155 | + break; | ||
156 | + case QEMU_VFP_FPSCR_NZCV: | ||
157 | + /* | ||
158 | + * Read just NZCV; this is a special case to avoid the | ||
159 | + * helper call for the "VMRS to CPSR.NZCV" insn. | ||
160 | + */ | ||
161 | + tmp = load_cpu_field(vfp.xregs[ARM_VFP_FPSCR]); | ||
162 | + tcg_gen_andi_i32(tmp, tmp, 0xf0000000); | ||
163 | + storefn(s, opaque, tmp); | ||
164 | + break; | ||
165 | + default: | ||
166 | + g_assert_not_reached(); | ||
167 | + } | ||
168 | + return true; | ||
169 | +} | ||
170 | + | ||
171 | +static void fp_sysreg_to_gpr(DisasContext *s, void *opaque, TCGv_i32 value) | ||
172 | +{ | ||
173 | + arg_VMSR_VMRS *a = opaque; | ||
174 | + | ||
175 | + if (a->rt == 15) { | ||
176 | + /* Set the 4 flag bits in the CPSR */ | ||
177 | + gen_set_nzcv(value); | ||
178 | + tcg_temp_free_i32(value); | ||
179 | + } else { | ||
180 | + store_reg(s, a->rt, value); | ||
181 | + } | ||
182 | +} | ||
183 | + | ||
184 | +static TCGv_i32 gpr_to_fp_sysreg(DisasContext *s, void *opaque) | ||
185 | +{ | ||
186 | + arg_VMSR_VMRS *a = opaque; | ||
187 | + | ||
188 | + return load_reg(s, a->rt); | ||
189 | +} | ||
190 | + | ||
191 | +static bool gen_M_VMSR_VMRS(DisasContext *s, arg_VMSR_VMRS *a) | ||
192 | +{ | ||
193 | + /* | ||
194 | + * Accesses to R15 are UNPREDICTABLE; we choose to undef. | ||
195 | + * FPSCR -> r15 is a special case which writes to the PSR flags; | ||
196 | + * set a->reg to a special value to tell gen_M_fp_sysreg_read() | ||
197 | + * we only care about the top 4 bits of FPSCR there. | ||
198 | + */ | ||
199 | + if (a->rt == 15) { | ||
200 | + if (a->l && a->reg == ARM_VFP_FPSCR) { | ||
201 | + a->reg = QEMU_VFP_FPSCR_NZCV; | ||
202 | + } else { | ||
203 | + return false; | ||
204 | + } | 91 | + } |
205 | + } | 92 | + } |
206 | + | 93 | + /* TODO: FEAT_LPA2 */ |
207 | + if (a->l) { | 94 | |
208 | + /* VMRS, move FP system register to gp register */ | 95 | if (tsz > max_tsz) { |
209 | + return gen_M_fp_sysreg_read(s, a->reg, fp_sysreg_to_gpr, a); | 96 | tsz = max_tsz; |
210 | + } else { | ||
211 | + /* VMSR, move gp register to FP system register */ | ||
212 | + return gen_M_fp_sysreg_write(s, a->reg, gpr_to_fp_sysreg, a); | ||
213 | + } | ||
214 | +} | ||
215 | + | ||
216 | static bool trans_VMSR_VMRS(DisasContext *s, arg_VMSR_VMRS *a) | ||
217 | { | ||
218 | TCGv_i32 tmp; | ||
219 | bool ignore_vfp_enabled = false; | ||
220 | |||
221 | - if (!dc_isar_feature(aa32_fpsp_v2, s)) { | ||
222 | - return false; | ||
223 | + if (arm_dc_feature(s, ARM_FEATURE_M)) { | ||
224 | + return gen_M_VMSR_VMRS(s, a); | ||
225 | } | ||
226 | |||
227 | - if (arm_dc_feature(s, ARM_FEATURE_M)) { | ||
228 | - /* | ||
229 | - * The only M-profile VFP vmrs/vmsr sysreg is FPSCR. | ||
230 | - * Accesses to R15 are UNPREDICTABLE; we choose to undef. | ||
231 | - * (FPSCR -> r15 is a special case which writes to the PSR flags.) | ||
232 | - */ | ||
233 | - if (a->reg != ARM_VFP_FPSCR) { | ||
234 | - return false; | ||
235 | - } | ||
236 | - if (a->rt == 15 && !a->l) { | ||
237 | - return false; | ||
238 | - } | ||
239 | + if (!dc_isar_feature(aa32_fpsp_v2, s)) { | ||
240 | + return false; | ||
241 | } | ||
242 | |||
243 | switch (a->reg) { | ||
244 | -- | 97 | -- |
245 | 2.20.1 | 98 | 2.25.1 |
246 | |||
247 | diff view generated by jsdifflib |
1 | From: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Trusted Firmware now supports A72 on sbsa-ref by default [1] so enable | 3 | This feature widens physical addresses (and intermediate physical |
4 | it for QEMU as well. A53 was already enabled there. | 4 | addresses for 2-stage translation) from 48 to 52 bits, when using |
5 | 64k pages. The only thing left at this point is to handle the | ||
6 | extra bits in the TTBR and in the table descriptors. | ||
5 | 7 | ||
6 | 1. https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/7117 | 8 | Note that PAR_EL1 and HPFAR_EL2 are nominally extended, but we don't |
9 | mask out the high bits when writing to those registers, so no changes | ||
10 | are required there. | ||
7 | 11 | ||
8 | Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> | ||
9 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
10 | Message-id: 20201120141705.246690-1-marcin.juszkiewicz@linaro.org | ||
11 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 12 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
13 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
14 | Message-id: 20220301215958.157011-11-richard.henderson@linaro.org | ||
12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 15 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
13 | --- | 16 | --- |
14 | hw/arm/sbsa-ref.c | 23 ++++++++++++++++++++--- | 17 | docs/system/arm/emulation.rst | 1 + |
15 | 1 file changed, 20 insertions(+), 3 deletions(-) | 18 | target/arm/cpu-param.h | 2 +- |
19 | target/arm/cpu64.c | 2 +- | ||
20 | target/arm/helper.c | 19 ++++++++++++++++--- | ||
21 | 4 files changed, 19 insertions(+), 5 deletions(-) | ||
16 | 22 | ||
17 | diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c | 23 | diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst |
18 | index XXXXXXX..XXXXXXX 100644 | 24 | index XXXXXXX..XXXXXXX 100644 |
19 | --- a/hw/arm/sbsa-ref.c | 25 | --- a/docs/system/arm/emulation.rst |
20 | +++ b/hw/arm/sbsa-ref.c | 26 | +++ b/docs/system/arm/emulation.rst |
21 | @@ -XXX,XX +XXX,XX @@ static const int sbsa_ref_irqmap[] = { | 27 | @@ -XXX,XX +XXX,XX @@ the following architecture extensions: |
22 | [SBSA_GWDT] = 16, | 28 | - FEAT_I8MM (AArch64 Int8 matrix multiplication instructions) |
29 | - FEAT_JSCVT (JavaScript conversion instructions) | ||
30 | - FEAT_LOR (Limited ordering regions) | ||
31 | +- FEAT_LPA (Large Physical Address space) | ||
32 | - FEAT_LRCPC (Load-acquire RCpc instructions) | ||
33 | - FEAT_LRCPC2 (Load-acquire RCpc instructions v2) | ||
34 | - FEAT_LSE (Large System Extensions) | ||
35 | diff --git a/target/arm/cpu-param.h b/target/arm/cpu-param.h | ||
36 | index XXXXXXX..XXXXXXX 100644 | ||
37 | --- a/target/arm/cpu-param.h | ||
38 | +++ b/target/arm/cpu-param.h | ||
39 | @@ -XXX,XX +XXX,XX @@ | ||
40 | |||
41 | #ifdef TARGET_AARCH64 | ||
42 | # define TARGET_LONG_BITS 64 | ||
43 | -# define TARGET_PHYS_ADDR_SPACE_BITS 48 | ||
44 | +# define TARGET_PHYS_ADDR_SPACE_BITS 52 | ||
45 | # define TARGET_VIRT_ADDR_SPACE_BITS 52 | ||
46 | #else | ||
47 | # define TARGET_LONG_BITS 32 | ||
48 | diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c | ||
49 | index XXXXXXX..XXXXXXX 100644 | ||
50 | --- a/target/arm/cpu64.c | ||
51 | +++ b/target/arm/cpu64.c | ||
52 | @@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj) | ||
53 | cpu->isar.id_aa64pfr1 = t; | ||
54 | |||
55 | t = cpu->isar.id_aa64mmfr0; | ||
56 | - t = FIELD_DP64(t, ID_AA64MMFR0, PARANGE, 5); /* PARange: 48 bits */ | ||
57 | + t = FIELD_DP64(t, ID_AA64MMFR0, PARANGE, 6); /* FEAT_LPA: 52 bits */ | ||
58 | cpu->isar.id_aa64mmfr0 = t; | ||
59 | |||
60 | t = cpu->isar.id_aa64mmfr1; | ||
61 | diff --git a/target/arm/helper.c b/target/arm/helper.c | ||
62 | index XXXXXXX..XXXXXXX 100644 | ||
63 | --- a/target/arm/helper.c | ||
64 | +++ b/target/arm/helper.c | ||
65 | @@ -XXX,XX +XXX,XX @@ static const uint8_t pamax_map[] = { | ||
66 | [3] = 42, | ||
67 | [4] = 44, | ||
68 | [5] = 48, | ||
69 | + [6] = 52, | ||
23 | }; | 70 | }; |
24 | 71 | ||
25 | +static const char * const valid_cpus[] = { | 72 | /* The cpu-specific constant value of PAMax; also used by hw/arm/virt. */ |
26 | + ARM_CPU_TYPE_NAME("cortex-a53"), | 73 | @@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, |
27 | + ARM_CPU_TYPE_NAME("cortex-a57"), | 74 | descaddr = extract64(ttbr, 0, 48); |
28 | + ARM_CPU_TYPE_NAME("cortex-a72"), | 75 | |
29 | +}; | 76 | /* |
77 | - * If the base address is out of range, raise AddressSizeFault. | ||
78 | + * For FEAT_LPA and PS=6, bits [51:48] of descaddr are in [5:2] of TTBR. | ||
79 | + * | ||
80 | + * Otherwise, if the base address is out of range, raise AddressSizeFault. | ||
81 | * In the pseudocode, this is !IsZero(baseregister<47:outputsize>), | ||
82 | * but we've just cleared the bits above 47, so simplify the test. | ||
83 | */ | ||
84 | - if (descaddr >> outputsize) { | ||
85 | + if (outputsize > 48) { | ||
86 | + descaddr |= extract64(ttbr, 2, 4) << 48; | ||
87 | + } else if (descaddr >> outputsize) { | ||
88 | level = 0; | ||
89 | fault_type = ARMFault_AddressSize; | ||
90 | goto do_fault; | ||
91 | @@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, | ||
92 | } | ||
93 | |||
94 | descaddr = descriptor & descaddrmask; | ||
95 | - if (descaddr >> outputsize) { | ||
30 | + | 96 | + |
31 | +static bool cpu_type_valid(const char *cpu) | 97 | + /* |
32 | +{ | 98 | + * For FEAT_LPA and PS=6, bits [51:48] of descaddr are in [15:12] |
33 | + int i; | 99 | + * of descriptor. Otherwise, if descaddr is out of range, raise |
34 | + | 100 | + * AddressSizeFault. |
35 | + for (i = 0; i < ARRAY_SIZE(valid_cpus); i++) { | 101 | + */ |
36 | + if (strcmp(cpu, valid_cpus[i]) == 0) { | 102 | + if (outputsize > 48) { |
37 | + return true; | 103 | + descaddr |= extract64(descriptor, 12, 4) << 48; |
38 | + } | 104 | + } else if (descaddr >> outputsize) { |
39 | + } | 105 | fault_type = ARMFault_AddressSize; |
40 | + return false; | 106 | goto do_fault; |
41 | +} | 107 | } |
42 | + | ||
43 | static uint64_t sbsa_ref_cpu_mp_affinity(SBSAMachineState *sms, int idx) | ||
44 | { | ||
45 | uint8_t clustersz = ARM_DEFAULT_CPUS_PER_CLUSTER; | ||
46 | @@ -XXX,XX +XXX,XX @@ static void sbsa_ref_init(MachineState *machine) | ||
47 | const CPUArchIdList *possible_cpus; | ||
48 | int n, sbsa_max_cpus; | ||
49 | |||
50 | - if (strcmp(machine->cpu_type, ARM_CPU_TYPE_NAME("cortex-a57"))) { | ||
51 | - error_report("sbsa-ref: CPU type other than the built-in " | ||
52 | - "cortex-a57 not supported"); | ||
53 | + if (!cpu_type_valid(machine->cpu_type)) { | ||
54 | + error_report("mach-virt: CPU type %s not supported", machine->cpu_type); | ||
55 | exit(1); | ||
56 | } | ||
57 | |||
58 | -- | 108 | -- |
59 | 2.20.1 | 109 | 2.25.1 |
60 | |||
61 | diff view generated by jsdifflib |
1 | From: Kunkun Jiang <jiangkunkun@huawei.com> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Accroding to the SMMUv3 spec, the SPAN field of Level1 Stream Table | 3 | With FEAT_LPA2, rather than introducing translation level 4, |
4 | Descriptor is 5 bits([4:0]). | 4 | we introduce level -1, below the current level 0. Extend |
5 | arm_fi_to_lfsc to handle these faults. | ||
5 | 6 | ||
6 | Fixes: 9bde7f0674f(hw/arm/smmuv3: Implement translate callback) | 7 | Assert that this new translation level does not leak into |
7 | Signed-off-by: Kunkun Jiang <jiangkunkun@huawei.com> | 8 | fault types for which it is not defined, which allows some |
8 | Message-id: 20201124023711.1184-1-jiangkunkun@huawei.com | 9 | masking of fi->level to be removed. |
10 | |||
9 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 11 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
10 | Acked-by: Eric Auger <eric.auger@redhat.com> | 12 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
13 | Message-id: 20220301215958.157011-12-richard.henderson@linaro.org | ||
11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 14 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
12 | --- | 15 | --- |
13 | hw/arm/smmuv3-internal.h | 2 +- | 16 | target/arm/internals.h | 35 +++++++++++++++++++++++++++++------ |
14 | 1 file changed, 1 insertion(+), 1 deletion(-) | 17 | 1 file changed, 29 insertions(+), 6 deletions(-) |
15 | 18 | ||
16 | diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h | 19 | diff --git a/target/arm/internals.h b/target/arm/internals.h |
17 | index XXXXXXX..XXXXXXX 100644 | 20 | index XXXXXXX..XXXXXXX 100644 |
18 | --- a/hw/arm/smmuv3-internal.h | 21 | --- a/target/arm/internals.h |
19 | +++ b/hw/arm/smmuv3-internal.h | 22 | +++ b/target/arm/internals.h |
20 | @@ -XXX,XX +XXX,XX @@ static inline uint64_t l1std_l2ptr(STEDesc *desc) | 23 | @@ -XXX,XX +XXX,XX @@ static inline uint32_t arm_fi_to_lfsc(ARMMMUFaultInfo *fi) |
21 | return hi << 32 | lo; | 24 | case ARMFault_None: |
22 | } | 25 | return 0; |
23 | 26 | case ARMFault_AddressSize: | |
24 | -#define L1STD_SPAN(stm) (extract32((stm)->word[0], 0, 4)) | 27 | - fsc = fi->level & 3; |
25 | +#define L1STD_SPAN(stm) (extract32((stm)->word[0], 0, 5)) | 28 | + assert(fi->level >= -1 && fi->level <= 3); |
26 | 29 | + if (fi->level < 0) { | |
27 | #endif | 30 | + fsc = 0b101001; |
31 | + } else { | ||
32 | + fsc = fi->level; | ||
33 | + } | ||
34 | break; | ||
35 | case ARMFault_AccessFlag: | ||
36 | - fsc = (fi->level & 3) | (0x2 << 2); | ||
37 | + assert(fi->level >= 0 && fi->level <= 3); | ||
38 | + fsc = 0b001000 | fi->level; | ||
39 | break; | ||
40 | case ARMFault_Permission: | ||
41 | - fsc = (fi->level & 3) | (0x3 << 2); | ||
42 | + assert(fi->level >= 0 && fi->level <= 3); | ||
43 | + fsc = 0b001100 | fi->level; | ||
44 | break; | ||
45 | case ARMFault_Translation: | ||
46 | - fsc = (fi->level & 3) | (0x1 << 2); | ||
47 | + assert(fi->level >= -1 && fi->level <= 3); | ||
48 | + if (fi->level < 0) { | ||
49 | + fsc = 0b101011; | ||
50 | + } else { | ||
51 | + fsc = 0b000100 | fi->level; | ||
52 | + } | ||
53 | break; | ||
54 | case ARMFault_SyncExternal: | ||
55 | fsc = 0x10 | (fi->ea << 12); | ||
56 | break; | ||
57 | case ARMFault_SyncExternalOnWalk: | ||
58 | - fsc = (fi->level & 3) | (0x5 << 2) | (fi->ea << 12); | ||
59 | + assert(fi->level >= -1 && fi->level <= 3); | ||
60 | + if (fi->level < 0) { | ||
61 | + fsc = 0b010011; | ||
62 | + } else { | ||
63 | + fsc = 0b010100 | fi->level; | ||
64 | + } | ||
65 | + fsc |= fi->ea << 12; | ||
66 | break; | ||
67 | case ARMFault_SyncParity: | ||
68 | fsc = 0x18; | ||
69 | break; | ||
70 | case ARMFault_SyncParityOnWalk: | ||
71 | - fsc = (fi->level & 3) | (0x7 << 2); | ||
72 | + assert(fi->level >= -1 && fi->level <= 3); | ||
73 | + if (fi->level < 0) { | ||
74 | + fsc = 0b011011; | ||
75 | + } else { | ||
76 | + fsc = 0b011100 | fi->level; | ||
77 | + } | ||
78 | break; | ||
79 | case ARMFault_AsyncParity: | ||
80 | fsc = 0x19; | ||
28 | -- | 81 | -- |
29 | 2.20.1 | 82 | 2.25.1 |
30 | |||
31 | diff view generated by jsdifflib |
1 | From: Vikram Garhwal <fnu.vikram@xilinx.com> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Connect CAN0 and CAN1 on the ZynqMP. | 3 | Merge tlbi_aa64_range_get_length and tlbi_aa64_range_get_base, |
4 | returning a structure containing both results. Pass in the | ||
5 | ARMMMUIdx, rather than the digested two_ranges boolean. | ||
4 | 6 | ||
5 | Reviewed-by: Francisco Iglesias <francisco.iglesias@xilinx.com> | 7 | This is in preparation for FEAT_LPA2, where the interpretation |
6 | Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> | 8 | of 'value' depends on the effective value of DS for the regime. |
7 | Signed-off-by: Vikram Garhwal <fnu.vikram@xilinx.com> | 9 | |
8 | Message-id: 1605728926-352690-3-git-send-email-fnu.vikram@xilinx.com | 10 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
11 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
12 | Message-id: 20220301215958.157011-13-richard.henderson@linaro.org | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
10 | --- | 14 | --- |
11 | include/hw/arm/xlnx-zynqmp.h | 8 ++++++++ | 15 | target/arm/helper.c | 58 +++++++++++++++++++-------------------------- |
12 | hw/arm/xlnx-zcu102.c | 20 ++++++++++++++++++++ | 16 | 1 file changed, 24 insertions(+), 34 deletions(-) |
13 | hw/arm/xlnx-zynqmp.c | 34 ++++++++++++++++++++++++++++++++++ | ||
14 | 3 files changed, 62 insertions(+) | ||
15 | 17 | ||
16 | diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h | 18 | diff --git a/target/arm/helper.c b/target/arm/helper.c |
17 | index XXXXXXX..XXXXXXX 100644 | 19 | index XXXXXXX..XXXXXXX 100644 |
18 | --- a/include/hw/arm/xlnx-zynqmp.h | 20 | --- a/target/arm/helper.c |
19 | +++ b/include/hw/arm/xlnx-zynqmp.h | 21 | +++ b/target/arm/helper.c |
20 | @@ -XXX,XX +XXX,XX @@ | 22 | @@ -XXX,XX +XXX,XX @@ static void tlbi_aa64_vae3is_write(CPUARMState *env, const ARMCPRegInfo *ri, |
21 | #include "hw/intc/arm_gic.h" | 23 | } |
22 | #include "hw/net/cadence_gem.h" | 24 | |
23 | #include "hw/char/cadence_uart.h" | 25 | #ifdef TARGET_AARCH64 |
24 | +#include "hw/net/xlnx-zynqmp-can.h" | 26 | -static uint64_t tlbi_aa64_range_get_length(CPUARMState *env, |
25 | #include "hw/ide/ahci.h" | 27 | - uint64_t value) |
26 | #include "hw/sd/sdhci.h" | 28 | -{ |
27 | #include "hw/ssi/xilinx_spips.h" | 29 | - unsigned int page_shift; |
28 | @@ -XXX,XX +XXX,XX @@ | 30 | - unsigned int page_size_granule; |
29 | #include "hw/cpu/cluster.h" | 31 | - uint64_t num; |
30 | #include "target/arm/cpu.h" | 32 | - uint64_t scale; |
31 | #include "qom/object.h" | 33 | - uint64_t exponent; |
32 | +#include "net/can_emu.h" | 34 | +typedef struct { |
33 | 35 | + uint64_t base; | |
34 | #define TYPE_XLNX_ZYNQMP "xlnx,zynqmp" | 36 | uint64_t length; |
35 | OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP) | 37 | +} TLBIRange; |
36 | @@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP) | ||
37 | #define XLNX_ZYNQMP_NUM_RPU_CPUS 2 | ||
38 | #define XLNX_ZYNQMP_NUM_GEMS 4 | ||
39 | #define XLNX_ZYNQMP_NUM_UARTS 2 | ||
40 | +#define XLNX_ZYNQMP_NUM_CAN 2 | ||
41 | +#define XLNX_ZYNQMP_CAN_REF_CLK (24 * 1000 * 1000) | ||
42 | #define XLNX_ZYNQMP_NUM_SDHCI 2 | ||
43 | #define XLNX_ZYNQMP_NUM_SPIS 2 | ||
44 | #define XLNX_ZYNQMP_NUM_GDMA_CH 8 | ||
45 | @@ -XXX,XX +XXX,XX @@ struct XlnxZynqMPState { | ||
46 | |||
47 | CadenceGEMState gem[XLNX_ZYNQMP_NUM_GEMS]; | ||
48 | CadenceUARTState uart[XLNX_ZYNQMP_NUM_UARTS]; | ||
49 | + XlnxZynqMPCANState can[XLNX_ZYNQMP_NUM_CAN]; | ||
50 | SysbusAHCIState sata; | ||
51 | SDHCIState sdhci[XLNX_ZYNQMP_NUM_SDHCI]; | ||
52 | XilinxSPIPS spi[XLNX_ZYNQMP_NUM_SPIS]; | ||
53 | @@ -XXX,XX +XXX,XX @@ struct XlnxZynqMPState { | ||
54 | bool virt; | ||
55 | /* Has the RPU subsystem? */ | ||
56 | bool has_rpu; | ||
57 | + | 38 | + |
58 | + /* CAN bus. */ | 39 | +static TLBIRange tlbi_aa64_get_range(CPUARMState *env, ARMMMUIdx mmuidx, |
59 | + CanBusState *canbus[XLNX_ZYNQMP_NUM_CAN]; | 40 | + uint64_t value) |
60 | }; | 41 | +{ |
61 | 42 | + unsigned int page_size_granule, page_shift, num, scale, exponent; | |
62 | #endif | 43 | + TLBIRange ret = { }; |
63 | diff --git a/hw/arm/xlnx-zcu102.c b/hw/arm/xlnx-zcu102.c | 44 | |
64 | index XXXXXXX..XXXXXXX 100644 | 45 | - num = extract64(value, 39, 5); |
65 | --- a/hw/arm/xlnx-zcu102.c | 46 | - scale = extract64(value, 44, 2); |
66 | +++ b/hw/arm/xlnx-zcu102.c | 47 | page_size_granule = extract64(value, 46, 2); |
67 | @@ -XXX,XX +XXX,XX @@ | 48 | |
68 | #include "sysemu/qtest.h" | 49 | if (page_size_granule == 0) { |
69 | #include "sysemu/device_tree.h" | 50 | qemu_log_mask(LOG_GUEST_ERROR, "Invalid page size granule %d\n", |
70 | #include "qom/object.h" | 51 | page_size_granule); |
71 | +#include "net/can_emu.h" | 52 | - return 0; |
72 | 53 | + return ret; | |
73 | struct XlnxZCU102 { | 54 | } |
74 | MachineState parent_obj; | 55 | |
75 | @@ -XXX,XX +XXX,XX @@ struct XlnxZCU102 { | 56 | page_shift = (page_size_granule - 1) * 2 + 12; |
76 | bool secure; | 57 | - |
77 | bool virt; | 58 | + num = extract64(value, 39, 5); |
78 | 59 | + scale = extract64(value, 44, 2); | |
79 | + CanBusState *canbus[XLNX_ZYNQMP_NUM_CAN]; | 60 | exponent = (5 * scale) + 1; |
80 | + | 61 | - length = (num + 1) << (exponent + page_shift); |
81 | struct arm_boot_info binfo; | 62 | |
82 | }; | 63 | - return length; |
83 | 64 | -} | |
84 | @@ -XXX,XX +XXX,XX @@ static void xlnx_zcu102_init(MachineState *machine) | 65 | + ret.length = (num + 1) << (exponent + page_shift); |
85 | object_property_set_bool(OBJECT(&s->soc), "virtualization", s->virt, | 66 | |
86 | &error_fatal); | 67 | -static uint64_t tlbi_aa64_range_get_base(CPUARMState *env, uint64_t value, |
87 | 68 | - bool two_ranges) | |
88 | + for (i = 0; i < XLNX_ZYNQMP_NUM_CAN; i++) { | 69 | -{ |
89 | + gchar *bus_name = g_strdup_printf("canbus%d", i); | 70 | - /* TODO: ARMv8.7 FEAT_LPA2 */ |
90 | + | 71 | - uint64_t pageaddr; |
91 | + object_property_set_link(OBJECT(&s->soc), bus_name, | 72 | - |
92 | + OBJECT(s->canbus[i]), &error_fatal); | 73 | - if (two_ranges) { |
93 | + g_free(bus_name); | 74 | - pageaddr = sextract64(value, 0, 37) << TARGET_PAGE_BITS; |
94 | + } | 75 | + if (regime_has_2_ranges(mmuidx)) { |
95 | + | 76 | + ret.base = sextract64(value, 0, 37) << TARGET_PAGE_BITS; |
96 | qdev_realize(DEVICE(&s->soc), NULL, &error_fatal); | 77 | } else { |
97 | 78 | - pageaddr = extract64(value, 0, 37) << TARGET_PAGE_BITS; | |
98 | /* Create and plug in the SD cards */ | 79 | + ret.base = extract64(value, 0, 37) << TARGET_PAGE_BITS; |
99 | @@ -XXX,XX +XXX,XX @@ static void xlnx_zcu102_machine_instance_init(Object *obj) | 80 | } |
100 | s->secure = false; | 81 | |
101 | /* Default to virt (EL2) being disabled */ | 82 | - return pageaddr; |
102 | s->virt = false; | 83 | + return ret; |
103 | + object_property_add_link(obj, "xlnx-zcu102.canbus0", TYPE_CAN_BUS, | ||
104 | + (Object **)&s->canbus[0], | ||
105 | + object_property_allow_set_link, | ||
106 | + 0); | ||
107 | + | ||
108 | + object_property_add_link(obj, "xlnx-zcu102.canbus1", TYPE_CAN_BUS, | ||
109 | + (Object **)&s->canbus[1], | ||
110 | + object_property_allow_set_link, | ||
111 | + 0); | ||
112 | } | 84 | } |
113 | 85 | ||
114 | static void xlnx_zcu102_machine_class_init(ObjectClass *oc, void *data) | 86 | static void do_rvae_write(CPUARMState *env, uint64_t value, |
115 | diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c | 87 | int idxmap, bool synced) |
116 | index XXXXXXX..XXXXXXX 100644 | 88 | { |
117 | --- a/hw/arm/xlnx-zynqmp.c | 89 | ARMMMUIdx one_idx = ARM_MMU_IDX_A | ctz32(idxmap); |
118 | +++ b/hw/arm/xlnx-zynqmp.c | 90 | - bool two_ranges = regime_has_2_ranges(one_idx); |
119 | @@ -XXX,XX +XXX,XX @@ static const int uart_intr[XLNX_ZYNQMP_NUM_UARTS] = { | 91 | - uint64_t baseaddr, length; |
120 | 21, 22, | 92 | + TLBIRange range; |
121 | }; | 93 | int bits; |
122 | 94 | ||
123 | +static const uint64_t can_addr[XLNX_ZYNQMP_NUM_CAN] = { | 95 | - baseaddr = tlbi_aa64_range_get_base(env, value, two_ranges); |
124 | + 0xFF060000, 0xFF070000, | 96 | - length = tlbi_aa64_range_get_length(env, value); |
125 | +}; | 97 | - bits = tlbbits_for_regime(env, one_idx, baseaddr); |
126 | + | 98 | + range = tlbi_aa64_get_range(env, one_idx, value); |
127 | +static const int can_intr[XLNX_ZYNQMP_NUM_CAN] = { | 99 | + bits = tlbbits_for_regime(env, one_idx, range.base); |
128 | + 23, 24, | 100 | |
129 | +}; | 101 | if (synced) { |
130 | + | 102 | tlb_flush_range_by_mmuidx_all_cpus_synced(env_cpu(env), |
131 | static const uint64_t sdhci_addr[XLNX_ZYNQMP_NUM_SDHCI] = { | 103 | - baseaddr, |
132 | 0xFF160000, 0xFF170000, | 104 | - length, |
133 | }; | 105 | + range.base, |
134 | @@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_init(Object *obj) | 106 | + range.length, |
135 | TYPE_CADENCE_UART); | 107 | idxmap, |
108 | bits); | ||
109 | } else { | ||
110 | - tlb_flush_range_by_mmuidx(env_cpu(env), baseaddr, | ||
111 | - length, idxmap, bits); | ||
112 | + tlb_flush_range_by_mmuidx(env_cpu(env), range.base, | ||
113 | + range.length, idxmap, bits); | ||
136 | } | 114 | } |
137 | 115 | } | |
138 | + for (i = 0; i < XLNX_ZYNQMP_NUM_CAN; i++) { | ||
139 | + object_initialize_child(obj, "can[*]", &s->can[i], | ||
140 | + TYPE_XLNX_ZYNQMP_CAN); | ||
141 | + } | ||
142 | + | ||
143 | object_initialize_child(obj, "sata", &s->sata, TYPE_SYSBUS_AHCI); | ||
144 | |||
145 | for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) { | ||
146 | @@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp) | ||
147 | gic_spi[uart_intr[i]]); | ||
148 | } | ||
149 | |||
150 | + for (i = 0; i < XLNX_ZYNQMP_NUM_CAN; i++) { | ||
151 | + object_property_set_int(OBJECT(&s->can[i]), "ext_clk_freq", | ||
152 | + XLNX_ZYNQMP_CAN_REF_CLK, &error_abort); | ||
153 | + | ||
154 | + object_property_set_link(OBJECT(&s->can[i]), "canbus", | ||
155 | + OBJECT(s->canbus[i]), &error_fatal); | ||
156 | + | ||
157 | + sysbus_realize(SYS_BUS_DEVICE(&s->can[i]), &err); | ||
158 | + if (err) { | ||
159 | + error_propagate(errp, err); | ||
160 | + return; | ||
161 | + } | ||
162 | + sysbus_mmio_map(SYS_BUS_DEVICE(&s->can[i]), 0, can_addr[i]); | ||
163 | + sysbus_connect_irq(SYS_BUS_DEVICE(&s->can[i]), 0, | ||
164 | + gic_spi[can_intr[i]]); | ||
165 | + } | ||
166 | + | ||
167 | object_property_set_int(OBJECT(&s->sata), "num-ports", SATA_NUM_PORTS, | ||
168 | &error_abort); | ||
169 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->sata), errp)) { | ||
170 | @@ -XXX,XX +XXX,XX @@ static Property xlnx_zynqmp_props[] = { | ||
171 | DEFINE_PROP_BOOL("has_rpu", XlnxZynqMPState, has_rpu, false), | ||
172 | DEFINE_PROP_LINK("ddr-ram", XlnxZynqMPState, ddr_ram, TYPE_MEMORY_REGION, | ||
173 | MemoryRegion *), | ||
174 | + DEFINE_PROP_LINK("canbus0", XlnxZynqMPState, canbus[0], TYPE_CAN_BUS, | ||
175 | + CanBusState *), | ||
176 | + DEFINE_PROP_LINK("canbus1", XlnxZynqMPState, canbus[1], TYPE_CAN_BUS, | ||
177 | + CanBusState *), | ||
178 | DEFINE_PROP_END_OF_LIST() | ||
179 | }; | ||
180 | 116 | ||
181 | -- | 117 | -- |
182 | 2.20.1 | 118 | 2.25.1 |
183 | |||
184 | diff view generated by jsdifflib |
1 | From: Alex Chen <alex.chen@huawei.com> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | We should use printf format specifier "%u" instead of "%d" for | 3 | The shift of the BaseADDR field depends on the translation |
4 | argument of type "unsigned int". | 4 | granule in use. |
5 | 5 | ||
6 | Reported-by: Euler Robot <euler.robot@huawei.com> | 6 | Fixes: 84940ed8255 ("target/arm: Add support for FEAT_TLBIRANGE") |
7 | Signed-off-by: Alex Chen <alex.chen@huawei.com> | 7 | Reported-by: Peter Maydell <peter.maydell@linaro.org> |
8 | Message-id: 20201126111109.112238-2-alex.chen@huawei.com | ||
9 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
9 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
10 | Message-id: 20220301215958.157011-14-richard.henderson@linaro.org | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
11 | --- | 12 | --- |
12 | hw/misc/imx25_ccm.c | 12 ++++++------ | 13 | target/arm/helper.c | 5 +++-- |
13 | 1 file changed, 6 insertions(+), 6 deletions(-) | 14 | 1 file changed, 3 insertions(+), 2 deletions(-) |
14 | 15 | ||
15 | diff --git a/hw/misc/imx25_ccm.c b/hw/misc/imx25_ccm.c | 16 | diff --git a/target/arm/helper.c b/target/arm/helper.c |
16 | index XXXXXXX..XXXXXXX 100644 | 17 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/hw/misc/imx25_ccm.c | 18 | --- a/target/arm/helper.c |
18 | +++ b/hw/misc/imx25_ccm.c | 19 | +++ b/target/arm/helper.c |
19 | @@ -XXX,XX +XXX,XX @@ static const char *imx25_ccm_reg_name(uint32_t reg) | 20 | @@ -XXX,XX +XXX,XX @@ static TLBIRange tlbi_aa64_get_range(CPUARMState *env, ARMMMUIdx mmuidx, |
20 | case IMX25_CCM_LPIMR1_REG: | 21 | ret.length = (num + 1) << (exponent + page_shift); |
21 | return "lpimr1"; | 22 | |
22 | default: | 23 | if (regime_has_2_ranges(mmuidx)) { |
23 | - sprintf(unknown, "[%d ?]", reg); | 24 | - ret.base = sextract64(value, 0, 37) << TARGET_PAGE_BITS; |
24 | + sprintf(unknown, "[%u ?]", reg); | 25 | + ret.base = sextract64(value, 0, 37); |
25 | return unknown; | 26 | } else { |
27 | - ret.base = extract64(value, 0, 37) << TARGET_PAGE_BITS; | ||
28 | + ret.base = extract64(value, 0, 37); | ||
26 | } | 29 | } |
27 | } | 30 | + ret.base <<= page_shift; |
28 | @@ -XXX,XX +XXX,XX @@ static uint32_t imx25_ccm_get_mpll_clk(IMXCCMState *dev) | 31 | |
29 | freq = imx_ccm_calc_pll(s->reg[IMX25_CCM_MPCTL_REG], CKIH_FREQ); | 32 | return ret; |
30 | } | ||
31 | |||
32 | - DPRINTF("freq = %d\n", freq); | ||
33 | + DPRINTF("freq = %u\n", freq); | ||
34 | |||
35 | return freq; | ||
36 | } | ||
37 | @@ -XXX,XX +XXX,XX @@ static uint32_t imx25_ccm_get_mcu_clk(IMXCCMState *dev) | ||
38 | |||
39 | freq = freq / (1 + EXTRACT(s->reg[IMX25_CCM_CCTL_REG], ARM_CLK_DIV)); | ||
40 | |||
41 | - DPRINTF("freq = %d\n", freq); | ||
42 | + DPRINTF("freq = %u\n", freq); | ||
43 | |||
44 | return freq; | ||
45 | } | ||
46 | @@ -XXX,XX +XXX,XX @@ static uint32_t imx25_ccm_get_ahb_clk(IMXCCMState *dev) | ||
47 | freq = imx25_ccm_get_mcu_clk(dev) | ||
48 | / (1 + EXTRACT(s->reg[IMX25_CCM_CCTL_REG], AHB_CLK_DIV)); | ||
49 | |||
50 | - DPRINTF("freq = %d\n", freq); | ||
51 | + DPRINTF("freq = %u\n", freq); | ||
52 | |||
53 | return freq; | ||
54 | } | ||
55 | @@ -XXX,XX +XXX,XX @@ static uint32_t imx25_ccm_get_ipg_clk(IMXCCMState *dev) | ||
56 | |||
57 | freq = imx25_ccm_get_ahb_clk(dev) / 2; | ||
58 | |||
59 | - DPRINTF("freq = %d\n", freq); | ||
60 | + DPRINTF("freq = %u\n", freq); | ||
61 | |||
62 | return freq; | ||
63 | } | ||
64 | @@ -XXX,XX +XXX,XX @@ static uint32_t imx25_ccm_get_clock_frequency(IMXCCMState *dev, IMXClk clock) | ||
65 | break; | ||
66 | } | ||
67 | |||
68 | - DPRINTF("Clock = %d) = %d\n", clock, freq); | ||
69 | + DPRINTF("Clock = %d) = %u\n", clock, freq); | ||
70 | |||
71 | return freq; | ||
72 | } | 33 | } |
73 | -- | 34 | -- |
74 | 2.20.1 | 35 | 2.25.1 |
75 | |||
76 | diff view generated by jsdifflib |
1 | In v8.1M the PXN architecture extension adds a new PXN bit to the | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | MPU_RLAR registers, which forbids execution of code in the region | ||
3 | from a privileged mode. | ||
4 | 2 | ||
5 | This is another feature which is just in the generic "in v8.1M" set | 3 | For FEAT_LPA2, we will need other ARMVAParameters, which themselves |
6 | and has no ID register field indicating its presence. | 4 | depend on the translation granule in use. We might as well validate |
5 | that the given TG matches; the architecture "does not require that | ||
6 | the instruction invalidates any entries" if this is not true. | ||
7 | 7 | ||
8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
9 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
10 | Message-id: 20220301215958.157011-15-richard.henderson@linaro.org | ||
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
9 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
10 | Message-id: 20201119215617.29887-3-peter.maydell@linaro.org | ||
11 | --- | 12 | --- |
12 | target/arm/helper.c | 7 ++++++- | 13 | target/arm/helper.c | 10 +++++++--- |
13 | 1 file changed, 6 insertions(+), 1 deletion(-) | 14 | 1 file changed, 7 insertions(+), 3 deletions(-) |
14 | 15 | ||
15 | diff --git a/target/arm/helper.c b/target/arm/helper.c | 16 | diff --git a/target/arm/helper.c b/target/arm/helper.c |
16 | index XXXXXXX..XXXXXXX 100644 | 17 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/target/arm/helper.c | 18 | --- a/target/arm/helper.c |
18 | +++ b/target/arm/helper.c | 19 | +++ b/target/arm/helper.c |
19 | @@ -XXX,XX +XXX,XX @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address, | 20 | @@ -XXX,XX +XXX,XX @@ static TLBIRange tlbi_aa64_get_range(CPUARMState *env, ARMMMUIdx mmuidx, |
21 | uint64_t value) | ||
22 | { | ||
23 | unsigned int page_size_granule, page_shift, num, scale, exponent; | ||
24 | + /* Extract one bit to represent the va selector in use. */ | ||
25 | + uint64_t select = sextract64(value, 36, 1); | ||
26 | + ARMVAParameters param = aa64_va_parameters(env, select, mmuidx, true); | ||
27 | TLBIRange ret = { }; | ||
28 | |||
29 | page_size_granule = extract64(value, 46, 2); | ||
30 | |||
31 | - if (page_size_granule == 0) { | ||
32 | - qemu_log_mask(LOG_GUEST_ERROR, "Invalid page size granule %d\n", | ||
33 | + /* The granule encoded in value must match the granule in use. */ | ||
34 | + if (page_size_granule != (param.using64k ? 3 : param.using16k ? 2 : 1)) { | ||
35 | + qemu_log_mask(LOG_GUEST_ERROR, "Invalid tlbi page size granule %d\n", | ||
36 | page_size_granule); | ||
37 | return ret; | ||
38 | } | ||
39 | @@ -XXX,XX +XXX,XX @@ static TLBIRange tlbi_aa64_get_range(CPUARMState *env, ARMMMUIdx mmuidx, | ||
40 | |||
41 | ret.length = (num + 1) << (exponent + page_shift); | ||
42 | |||
43 | - if (regime_has_2_ranges(mmuidx)) { | ||
44 | + if (param.select) { | ||
45 | ret.base = sextract64(value, 0, 37); | ||
20 | } else { | 46 | } else { |
21 | uint32_t ap = extract32(env->pmsav8.rbar[secure][matchregion], 1, 2); | 47 | ret.base = extract64(value, 0, 37); |
22 | uint32_t xn = extract32(env->pmsav8.rbar[secure][matchregion], 0, 1); | ||
23 | + bool pxn = false; | ||
24 | + | ||
25 | + if (arm_feature(env, ARM_FEATURE_V8_1M)) { | ||
26 | + pxn = extract32(env->pmsav8.rlar[secure][matchregion], 4, 1); | ||
27 | + } | ||
28 | |||
29 | if (m_is_system_region(env, address)) { | ||
30 | /* System space is always execute never */ | ||
31 | @@ -XXX,XX +XXX,XX @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address, | ||
32 | } | ||
33 | |||
34 | *prot = simple_ap_to_rw_prot(env, mmu_idx, ap); | ||
35 | - if (*prot && !xn) { | ||
36 | + if (*prot && !xn && !(pxn && !is_user)) { | ||
37 | *prot |= PAGE_EXEC; | ||
38 | } | ||
39 | /* We don't need to look the attribute up in the MAIR0/MAIR1 | ||
40 | -- | 48 | -- |
41 | 2.20.1 | 49 | 2.25.1 |
42 | |||
43 | diff view generated by jsdifflib |
1 | From: Vikram Garhwal <fnu.vikram@xilinx.com> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Reviewed-by: Francisco Iglesias <francisco.iglesias@xilinx.com> | 3 | We support 16k pages, but do not advertize that in ID_AA64MMFR0. |
4 | Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> | 4 | |
5 | Signed-off-by: Vikram Garhwal <fnu.vikram@xilinx.com> | 5 | The value 0 in the TGRAN*_2 fields indicates that stage2 lookups defer |
6 | Message-id: 1605728926-352690-5-git-send-email-fnu.vikram@xilinx.com | 6 | to the same support as stage1 lookups. This setting is deprecated, so |
7 | indicate support for all stage2 page sizes directly. | ||
8 | |||
9 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
10 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
11 | Message-id: 20220301215958.157011-16-richard.henderson@linaro.org | ||
7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
8 | --- | 13 | --- |
9 | MAINTAINERS | 8 ++++++++ | 14 | target/arm/cpu64.c | 4 ++++ |
10 | 1 file changed, 8 insertions(+) | 15 | 1 file changed, 4 insertions(+) |
11 | 16 | ||
12 | diff --git a/MAINTAINERS b/MAINTAINERS | 17 | diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c |
13 | index XXXXXXX..XXXXXXX 100644 | 18 | index XXXXXXX..XXXXXXX 100644 |
14 | --- a/MAINTAINERS | 19 | --- a/target/arm/cpu64.c |
15 | +++ b/MAINTAINERS | 20 | +++ b/target/arm/cpu64.c |
16 | @@ -XXX,XX +XXX,XX @@ F: hw/net/opencores_eth.c | 21 | @@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj) |
17 | 22 | ||
18 | Devices | 23 | t = cpu->isar.id_aa64mmfr0; |
19 | ------- | 24 | t = FIELD_DP64(t, ID_AA64MMFR0, PARANGE, 6); /* FEAT_LPA: 52 bits */ |
20 | +Xilinx CAN | 25 | + t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN16, 1); /* 16k pages supported */ |
21 | +M: Vikram Garhwal <fnu.vikram@xilinx.com> | 26 | + t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN16_2, 2); /* 16k stage2 supported */ |
22 | +M: Francisco Iglesias <francisco.iglesias@xilinx.com> | 27 | + t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN64_2, 2); /* 64k stage2 supported */ |
23 | +S: Maintained | 28 | + t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN4_2, 2); /* 4k stage2 supported */ |
24 | +F: hw/net/can/xlnx-* | 29 | cpu->isar.id_aa64mmfr0 = t; |
25 | +F: include/hw/net/xlnx-* | 30 | |
26 | +F: tests/qtest/xlnx-can-test* | 31 | t = cpu->isar.id_aa64mmfr1; |
27 | + | ||
28 | EDU | ||
29 | M: Jiri Slaby <jslaby@suse.cz> | ||
30 | S: Maintained | ||
31 | -- | 32 | -- |
32 | 2.20.1 | 33 | 2.25.1 |
33 | |||
34 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | For M-profile CPUs, the range from 0xe0000000 to 0xe00fffff is the | ||
2 | Private Peripheral Bus range, which includes all of the memory mapped | ||
3 | devices and registers that are part of the CPU itself, including the | ||
4 | NVIC, systick timer, and debug and trace components like the Data | ||
5 | Watchpoint and Trace unit (DWT). Within this large region, the range | ||
6 | 0xe000e000 to 0xe000efff is the System Control Space (NVIC, system | ||
7 | registers, systick) and 0xe002e000 to 0exe002efff is its Non-secure | ||
8 | alias. | ||
9 | 1 | ||
10 | The architecture is clear that within the SCS unimplemented registers | ||
11 | should be RES0 for privileged accesses and generate BusFault for | ||
12 | unprivileged accesses, and we currently implement this. | ||
13 | |||
14 | It is less clear about how to handle accesses to unimplemented | ||
15 | regions of the wider PPB. Unprivileged accesses should definitely | ||
16 | cause BusFaults (R_DQQS), but the behaviour of privileged accesses is | ||
17 | not given as a general rule. However, the register definitions of | ||
18 | individual registers for components like the DWT all state that they | ||
19 | are RES0 if the relevant component is not implemented, so the | ||
20 | simplest way to provide that is to provide RAZ/WI for the whole range | ||
21 | for privileged accesses. (The v7M Arm ARM does say that reserved | ||
22 | registers should be UNK/SBZP.) | ||
23 | |||
24 | Expand the container MemoryRegion that the NVIC exposes so that | ||
25 | it covers the whole PPB space. This means: | ||
26 | * moving the address that the ARMV7M device maps it to down by | ||
27 | 0xe000 bytes | ||
28 | * moving the off and the offsets within the container of all the | ||
29 | subregions forward by 0xe000 bytes | ||
30 | * adding a new default MemoryRegion that covers the whole container | ||
31 | at a lower priority than anything else and which provides the | ||
32 | RAZWI/BusFault behaviour | ||
33 | |||
34 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
35 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
36 | Message-id: 20201119215617.29887-2-peter.maydell@linaro.org | ||
37 | --- | ||
38 | include/hw/intc/armv7m_nvic.h | 1 + | ||
39 | hw/arm/armv7m.c | 2 +- | ||
40 | hw/intc/armv7m_nvic.c | 78 ++++++++++++++++++++++++++++++----- | ||
41 | 3 files changed, 69 insertions(+), 12 deletions(-) | ||
42 | |||
43 | diff --git a/include/hw/intc/armv7m_nvic.h b/include/hw/intc/armv7m_nvic.h | ||
44 | index XXXXXXX..XXXXXXX 100644 | ||
45 | --- a/include/hw/intc/armv7m_nvic.h | ||
46 | +++ b/include/hw/intc/armv7m_nvic.h | ||
47 | @@ -XXX,XX +XXX,XX @@ struct NVICState { | ||
48 | MemoryRegion systickmem; | ||
49 | MemoryRegion systick_ns_mem; | ||
50 | MemoryRegion container; | ||
51 | + MemoryRegion defaultmem; | ||
52 | |||
53 | uint32_t num_irq; | ||
54 | qemu_irq excpout; | ||
55 | diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c | ||
56 | index XXXXXXX..XXXXXXX 100644 | ||
57 | --- a/hw/arm/armv7m.c | ||
58 | +++ b/hw/arm/armv7m.c | ||
59 | @@ -XXX,XX +XXX,XX @@ static void armv7m_realize(DeviceState *dev, Error **errp) | ||
60 | sysbus_connect_irq(sbd, 0, | ||
61 | qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_IRQ)); | ||
62 | |||
63 | - memory_region_add_subregion(&s->container, 0xe000e000, | ||
64 | + memory_region_add_subregion(&s->container, 0xe0000000, | ||
65 | sysbus_mmio_get_region(sbd, 0)); | ||
66 | |||
67 | for (i = 0; i < ARRAY_SIZE(s->bitband); i++) { | ||
68 | diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c | ||
69 | index XXXXXXX..XXXXXXX 100644 | ||
70 | --- a/hw/intc/armv7m_nvic.c | ||
71 | +++ b/hw/intc/armv7m_nvic.c | ||
72 | @@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps nvic_systick_ops = { | ||
73 | .endianness = DEVICE_NATIVE_ENDIAN, | ||
74 | }; | ||
75 | |||
76 | +/* | ||
77 | + * Unassigned portions of the PPB space are RAZ/WI for privileged | ||
78 | + * accesses, and fault for non-privileged accesses. | ||
79 | + */ | ||
80 | +static MemTxResult ppb_default_read(void *opaque, hwaddr addr, | ||
81 | + uint64_t *data, unsigned size, | ||
82 | + MemTxAttrs attrs) | ||
83 | +{ | ||
84 | + qemu_log_mask(LOG_UNIMP, "Read of unassigned area of PPB: offset 0x%x\n", | ||
85 | + (uint32_t)addr); | ||
86 | + if (attrs.user) { | ||
87 | + return MEMTX_ERROR; | ||
88 | + } | ||
89 | + *data = 0; | ||
90 | + return MEMTX_OK; | ||
91 | +} | ||
92 | + | ||
93 | +static MemTxResult ppb_default_write(void *opaque, hwaddr addr, | ||
94 | + uint64_t value, unsigned size, | ||
95 | + MemTxAttrs attrs) | ||
96 | +{ | ||
97 | + qemu_log_mask(LOG_UNIMP, "Write of unassigned area of PPB: offset 0x%x\n", | ||
98 | + (uint32_t)addr); | ||
99 | + if (attrs.user) { | ||
100 | + return MEMTX_ERROR; | ||
101 | + } | ||
102 | + return MEMTX_OK; | ||
103 | +} | ||
104 | + | ||
105 | +static const MemoryRegionOps ppb_default_ops = { | ||
106 | + .read_with_attrs = ppb_default_read, | ||
107 | + .write_with_attrs = ppb_default_write, | ||
108 | + .endianness = DEVICE_NATIVE_ENDIAN, | ||
109 | + .valid.min_access_size = 1, | ||
110 | + .valid.max_access_size = 8, | ||
111 | +}; | ||
112 | + | ||
113 | static int nvic_post_load(void *opaque, int version_id) | ||
114 | { | ||
115 | NVICState *s = opaque; | ||
116 | @@ -XXX,XX +XXX,XX @@ static void nvic_systick_trigger(void *opaque, int n, int level) | ||
117 | static void armv7m_nvic_realize(DeviceState *dev, Error **errp) | ||
118 | { | ||
119 | NVICState *s = NVIC(dev); | ||
120 | - int regionlen; | ||
121 | |||
122 | /* The armv7m container object will have set our CPU pointer */ | ||
123 | if (!s->cpu || !arm_feature(&s->cpu->env, ARM_FEATURE_M)) { | ||
124 | @@ -XXX,XX +XXX,XX @@ static void armv7m_nvic_realize(DeviceState *dev, Error **errp) | ||
125 | M_REG_S)); | ||
126 | } | ||
127 | |||
128 | - /* The NVIC and System Control Space (SCS) starts at 0xe000e000 | ||
129 | + /* | ||
130 | + * This device provides a single sysbus memory region which | ||
131 | + * represents the whole of the "System PPB" space. This is the | ||
132 | + * range from 0xe0000000 to 0xe00fffff and includes the NVIC, | ||
133 | + * the System Control Space (system registers), the systick timer, | ||
134 | + * and for CPUs with the Security extension an NS banked version | ||
135 | + * of all of these. | ||
136 | + * | ||
137 | + * The default behaviour for unimplemented registers/ranges | ||
138 | + * (for instance the Data Watchpoint and Trace unit at 0xe0001000) | ||
139 | + * is to RAZ/WI for privileged access and BusFault for non-privileged | ||
140 | + * access. | ||
141 | + * | ||
142 | + * The NVIC and System Control Space (SCS) starts at 0xe000e000 | ||
143 | * and looks like this: | ||
144 | * 0x004 - ICTR | ||
145 | * 0x010 - 0xff - systick | ||
146 | @@ -XXX,XX +XXX,XX @@ static void armv7m_nvic_realize(DeviceState *dev, Error **errp) | ||
147 | * generally code determining which banked register to use should | ||
148 | * use attrs.secure; code determining actual behaviour of the system | ||
149 | * should use env->v7m.secure. | ||
150 | + * | ||
151 | + * The container covers the whole PPB space. Within it the priority | ||
152 | + * of overlapping regions is: | ||
153 | + * - default region (for RAZ/WI and BusFault) : -1 | ||
154 | + * - system register regions : 0 | ||
155 | + * - systick : 1 | ||
156 | + * This is because the systick device is a small block of registers | ||
157 | + * in the middle of the other system control registers. | ||
158 | */ | ||
159 | - regionlen = arm_feature(&s->cpu->env, ARM_FEATURE_V8) ? 0x21000 : 0x1000; | ||
160 | - memory_region_init(&s->container, OBJECT(s), "nvic", regionlen); | ||
161 | - /* The system register region goes at the bottom of the priority | ||
162 | - * stack as it covers the whole page. | ||
163 | - */ | ||
164 | + memory_region_init(&s->container, OBJECT(s), "nvic", 0x100000); | ||
165 | + memory_region_init_io(&s->defaultmem, OBJECT(s), &ppb_default_ops, s, | ||
166 | + "nvic-default", 0x100000); | ||
167 | + memory_region_add_subregion_overlap(&s->container, 0, &s->defaultmem, -1); | ||
168 | memory_region_init_io(&s->sysregmem, OBJECT(s), &nvic_sysreg_ops, s, | ||
169 | "nvic_sysregs", 0x1000); | ||
170 | - memory_region_add_subregion(&s->container, 0, &s->sysregmem); | ||
171 | + memory_region_add_subregion(&s->container, 0xe000, &s->sysregmem); | ||
172 | |||
173 | memory_region_init_io(&s->systickmem, OBJECT(s), | ||
174 | &nvic_systick_ops, s, | ||
175 | "nvic_systick", 0xe0); | ||
176 | |||
177 | - memory_region_add_subregion_overlap(&s->container, 0x10, | ||
178 | + memory_region_add_subregion_overlap(&s->container, 0xe010, | ||
179 | &s->systickmem, 1); | ||
180 | |||
181 | if (arm_feature(&s->cpu->env, ARM_FEATURE_V8)) { | ||
182 | memory_region_init_io(&s->sysreg_ns_mem, OBJECT(s), | ||
183 | &nvic_sysreg_ns_ops, &s->sysregmem, | ||
184 | "nvic_sysregs_ns", 0x1000); | ||
185 | - memory_region_add_subregion(&s->container, 0x20000, &s->sysreg_ns_mem); | ||
186 | + memory_region_add_subregion(&s->container, 0x2e000, &s->sysreg_ns_mem); | ||
187 | memory_region_init_io(&s->systick_ns_mem, OBJECT(s), | ||
188 | &nvic_sysreg_ns_ops, &s->systickmem, | ||
189 | "nvic_systick_ns", 0xe0); | ||
190 | - memory_region_add_subregion_overlap(&s->container, 0x20010, | ||
191 | + memory_region_add_subregion_overlap(&s->container, 0x2e010, | ||
192 | &s->systick_ns_mem, 1); | ||
193 | } | ||
194 | |||
195 | -- | ||
196 | 2.20.1 | ||
197 | |||
198 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | In v8.1M the new CLRM instruction allows zeroing an arbitrary set of | ||
2 | the general-purpose registers and APSR. Implement this. | ||
3 | 1 | ||
4 | The encoding is a subset of the LDMIA T2 encoding, using what would | ||
5 | be Rn=0b1111 (which UNDEFs for LDMIA). | ||
6 | |||
7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
9 | Message-id: 20201119215617.29887-6-peter.maydell@linaro.org | ||
10 | --- | ||
11 | target/arm/t32.decode | 6 +++++- | ||
12 | target/arm/translate.c | 38 ++++++++++++++++++++++++++++++++++++++ | ||
13 | 2 files changed, 43 insertions(+), 1 deletion(-) | ||
14 | |||
15 | diff --git a/target/arm/t32.decode b/target/arm/t32.decode | ||
16 | index XXXXXXX..XXXXXXX 100644 | ||
17 | --- a/target/arm/t32.decode | ||
18 | +++ b/target/arm/t32.decode | ||
19 | @@ -XXX,XX +XXX,XX @@ UXTAB 1111 1010 0101 .... 1111 .... 10.. .... @rrr_rot | ||
20 | |||
21 | STM_t32 1110 1000 10.0 .... ................ @ldstm i=1 b=0 | ||
22 | STM_t32 1110 1001 00.0 .... ................ @ldstm i=0 b=1 | ||
23 | -LDM_t32 1110 1000 10.1 .... ................ @ldstm i=1 b=0 | ||
24 | +{ | ||
25 | + # Rn=15 UNDEFs for LDM; M-profile CLRM uses that encoding | ||
26 | + CLRM 1110 1000 1001 1111 list:16 | ||
27 | + LDM_t32 1110 1000 10.1 .... ................ @ldstm i=1 b=0 | ||
28 | +} | ||
29 | LDM_t32 1110 1001 00.1 .... ................ @ldstm i=0 b=1 | ||
30 | |||
31 | &rfe !extern rn w pu | ||
32 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
33 | index XXXXXXX..XXXXXXX 100644 | ||
34 | --- a/target/arm/translate.c | ||
35 | +++ b/target/arm/translate.c | ||
36 | @@ -XXX,XX +XXX,XX @@ static bool trans_LDM_t16(DisasContext *s, arg_ldst_block *a) | ||
37 | return do_ldm(s, a, 1); | ||
38 | } | ||
39 | |||
40 | +static bool trans_CLRM(DisasContext *s, arg_CLRM *a) | ||
41 | +{ | ||
42 | + int i; | ||
43 | + TCGv_i32 zero; | ||
44 | + | ||
45 | + if (!dc_isar_feature(aa32_m_sec_state, s)) { | ||
46 | + return false; | ||
47 | + } | ||
48 | + | ||
49 | + if (extract32(a->list, 13, 1)) { | ||
50 | + return false; | ||
51 | + } | ||
52 | + | ||
53 | + if (!a->list) { | ||
54 | + /* UNPREDICTABLE; we choose to UNDEF */ | ||
55 | + return false; | ||
56 | + } | ||
57 | + | ||
58 | + zero = tcg_const_i32(0); | ||
59 | + for (i = 0; i < 15; i++) { | ||
60 | + if (extract32(a->list, i, 1)) { | ||
61 | + /* Clear R[i] */ | ||
62 | + tcg_gen_mov_i32(cpu_R[i], zero); | ||
63 | + } | ||
64 | + } | ||
65 | + if (extract32(a->list, 15, 1)) { | ||
66 | + /* | ||
67 | + * Clear APSR (by calling the MSR helper with the same argument | ||
68 | + * as for "MSR APSR_nzcvqg, Rn": mask = 0b1100, SYSM=0) | ||
69 | + */ | ||
70 | + TCGv_i32 maskreg = tcg_const_i32(0xc << 8); | ||
71 | + gen_helper_v7m_msr(cpu_env, maskreg, zero); | ||
72 | + tcg_temp_free_i32(maskreg); | ||
73 | + } | ||
74 | + tcg_temp_free_i32(zero); | ||
75 | + return true; | ||
76 | +} | ||
77 | + | ||
78 | /* | ||
79 | * Branch, branch with link | ||
80 | */ | ||
81 | -- | ||
82 | 2.20.1 | ||
83 | |||
84 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | For M-profile before v8.1M, the only valid register for VMSR/VMRS is | ||
2 | the FPSCR. We have a comment that states this, but the actual logic | ||
3 | to forbid accesses for any other register value is missing, so we | ||
4 | would end up with A-profile style behaviour. Add the missing check. | ||
5 | 1 | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Message-id: 20201119215617.29887-7-peter.maydell@linaro.org | ||
9 | --- | ||
10 | target/arm/translate-vfp.c.inc | 5 ++++- | ||
11 | 1 file changed, 4 insertions(+), 1 deletion(-) | ||
12 | |||
13 | diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc | ||
14 | index XXXXXXX..XXXXXXX 100644 | ||
15 | --- a/target/arm/translate-vfp.c.inc | ||
16 | +++ b/target/arm/translate-vfp.c.inc | ||
17 | @@ -XXX,XX +XXX,XX @@ static bool trans_VMSR_VMRS(DisasContext *s, arg_VMSR_VMRS *a) | ||
18 | * Accesses to R15 are UNPREDICTABLE; we choose to undef. | ||
19 | * (FPSCR -> r15 is a special case which writes to the PSR flags.) | ||
20 | */ | ||
21 | - if (a->rt == 15 && (!a->l || a->reg != ARM_VFP_FPSCR)) { | ||
22 | + if (a->reg != ARM_VFP_FPSCR) { | ||
23 | + return false; | ||
24 | + } | ||
25 | + if (a->rt == 15 && !a->l) { | ||
26 | return false; | ||
27 | } | ||
28 | } | ||
29 | -- | ||
30 | 2.20.1 | ||
31 | |||
32 | diff view generated by jsdifflib |
1 | The constant-expander functions like negate, plus_2, etc, are | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | generally useful; move them up in translate.c so we can use them in | 2 | |
3 | the VFP/Neon decoders as well as in the A32/T32/T16 decoders. | 3 | This feature widens physical addresses (and intermediate physical |
4 | 4 | addresses for 2-stage translation) from 48 to 52 bits, when using | |
5 | 4k or 16k pages. | ||
6 | |||
7 | This introduces the DS bit to TCR_ELx, which is RES0 unless the | ||
8 | page size is enabled and supports LPA2, resulting in the effective | ||
9 | value of DS for a given table walk. The DS bit changes the format | ||
10 | of the page table descriptor slightly, moving the PS field out to | ||
11 | TCR so that all pages have the same sharability and repurposing | ||
12 | those bits of the page table descriptor for the highest bits of | ||
13 | the output address. | ||
14 | |||
15 | Do not yet enable FEAT_LPA2; we need extra plumbing to avoid | ||
16 | tickling an old kernel bug. | ||
17 | |||
18 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
19 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
20 | Message-id: 20220301215958.157011-17-richard.henderson@linaro.org | ||
5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 21 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Message-id: 20201119215617.29887-9-peter.maydell@linaro.org | ||
8 | --- | 22 | --- |
9 | target/arm/translate.c | 46 +++++++++++++++++++++++------------------- | 23 | docs/system/arm/emulation.rst | 1 + |
10 | 1 file changed, 25 insertions(+), 21 deletions(-) | 24 | target/arm/cpu.h | 22 ++++++++ |
11 | 25 | target/arm/internals.h | 2 + | |
12 | diff --git a/target/arm/translate.c b/target/arm/translate.c | 26 | target/arm/helper.c | 102 +++++++++++++++++++++++++++++----- |
27 | 4 files changed, 112 insertions(+), 15 deletions(-) | ||
28 | |||
29 | diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst | ||
13 | index XXXXXXX..XXXXXXX 100644 | 30 | index XXXXXXX..XXXXXXX 100644 |
14 | --- a/target/arm/translate.c | 31 | --- a/docs/system/arm/emulation.rst |
15 | +++ b/target/arm/translate.c | 32 | +++ b/docs/system/arm/emulation.rst |
16 | @@ -XXX,XX +XXX,XX @@ static void arm_gen_condlabel(DisasContext *s) | 33 | @@ -XXX,XX +XXX,XX @@ the following architecture extensions: |
17 | } | 34 | - FEAT_JSCVT (JavaScript conversion instructions) |
35 | - FEAT_LOR (Limited ordering regions) | ||
36 | - FEAT_LPA (Large Physical Address space) | ||
37 | +- FEAT_LPA2 (Large Physical and virtual Address space v2) | ||
38 | - FEAT_LRCPC (Load-acquire RCpc instructions) | ||
39 | - FEAT_LRCPC2 (Load-acquire RCpc instructions v2) | ||
40 | - FEAT_LSE (Large System Extensions) | ||
41 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | ||
42 | index XXXXXXX..XXXXXXX 100644 | ||
43 | --- a/target/arm/cpu.h | ||
44 | +++ b/target/arm/cpu.h | ||
45 | @@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_i8mm(const ARMISARegisters *id) | ||
46 | return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, I8MM) != 0; | ||
18 | } | 47 | } |
19 | 48 | ||
20 | +/* | 49 | +static inline bool isar_feature_aa64_tgran4_lpa2(const ARMISARegisters *id) |
21 | + * Constant expanders for the decoders. | ||
22 | + */ | ||
23 | + | ||
24 | +static int negate(DisasContext *s, int x) | ||
25 | +{ | 50 | +{ |
26 | + return -x; | 51 | + return FIELD_SEX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4) >= 1; |
27 | +} | 52 | +} |
28 | + | 53 | + |
29 | +static int plus_2(DisasContext *s, int x) | 54 | +static inline bool isar_feature_aa64_tgran4_2_lpa2(const ARMISARegisters *id) |
30 | +{ | 55 | +{ |
31 | + return x + 2; | 56 | + unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4_2); |
57 | + return t >= 3 || (t == 0 && isar_feature_aa64_tgran4_lpa2(id)); | ||
32 | +} | 58 | +} |
33 | + | 59 | + |
34 | +static int times_2(DisasContext *s, int x) | 60 | +static inline bool isar_feature_aa64_tgran16_lpa2(const ARMISARegisters *id) |
35 | +{ | 61 | +{ |
36 | + return x * 2; | 62 | + return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16) >= 2; |
37 | +} | 63 | +} |
38 | + | 64 | + |
39 | +static int times_4(DisasContext *s, int x) | 65 | +static inline bool isar_feature_aa64_tgran16_2_lpa2(const ARMISARegisters *id) |
40 | +{ | 66 | +{ |
41 | + return x * 4; | 67 | + unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16_2); |
68 | + return t >= 3 || (t == 0 && isar_feature_aa64_tgran16_lpa2(id)); | ||
42 | +} | 69 | +} |
43 | + | 70 | + |
44 | /* Flags for the disas_set_da_iss info argument: | 71 | static inline bool isar_feature_aa64_ccidx(const ARMISARegisters *id) |
45 | * lower bits hold the Rt register number, higher bits are flags. | ||
46 | */ | ||
47 | @@ -XXX,XX +XXX,XX @@ static void arm_skip_unless(DisasContext *s, uint32_t cond) | ||
48 | |||
49 | |||
50 | /* | ||
51 | - * Constant expanders for the decoders. | ||
52 | + * Constant expanders used by T16/T32 decode | ||
53 | */ | ||
54 | |||
55 | -static int negate(DisasContext *s, int x) | ||
56 | -{ | ||
57 | - return -x; | ||
58 | -} | ||
59 | - | ||
60 | -static int plus_2(DisasContext *s, int x) | ||
61 | -{ | ||
62 | - return x + 2; | ||
63 | -} | ||
64 | - | ||
65 | -static int times_2(DisasContext *s, int x) | ||
66 | -{ | ||
67 | - return x * 2; | ||
68 | -} | ||
69 | - | ||
70 | -static int times_4(DisasContext *s, int x) | ||
71 | -{ | ||
72 | - return x * 4; | ||
73 | -} | ||
74 | - | ||
75 | /* Return only the rotation part of T32ExpandImm. */ | ||
76 | static int t32_expandimm_rot(DisasContext *s, int x) | ||
77 | { | 72 | { |
73 | return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, CCIDX) != 0; | ||
74 | diff --git a/target/arm/internals.h b/target/arm/internals.h | ||
75 | index XXXXXXX..XXXXXXX 100644 | ||
76 | --- a/target/arm/internals.h | ||
77 | +++ b/target/arm/internals.h | ||
78 | @@ -XXX,XX +XXX,XX @@ static inline uint32_t aarch64_pstate_valid_mask(const ARMISARegisters *id) | ||
79 | typedef struct ARMVAParameters { | ||
80 | unsigned tsz : 8; | ||
81 | unsigned ps : 3; | ||
82 | + unsigned sh : 2; | ||
83 | unsigned select : 1; | ||
84 | bool tbi : 1; | ||
85 | bool epd : 1; | ||
86 | @@ -XXX,XX +XXX,XX @@ typedef struct ARMVAParameters { | ||
87 | bool using16k : 1; | ||
88 | bool using64k : 1; | ||
89 | bool tsz_oob : 1; /* tsz has been clamped to legal range */ | ||
90 | + bool ds : 1; | ||
91 | } ARMVAParameters; | ||
92 | |||
93 | ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, | ||
94 | diff --git a/target/arm/helper.c b/target/arm/helper.c | ||
95 | index XXXXXXX..XXXXXXX 100644 | ||
96 | --- a/target/arm/helper.c | ||
97 | +++ b/target/arm/helper.c | ||
98 | @@ -XXX,XX +XXX,XX @@ static TLBIRange tlbi_aa64_get_range(CPUARMState *env, ARMMMUIdx mmuidx, | ||
99 | } else { | ||
100 | ret.base = extract64(value, 0, 37); | ||
101 | } | ||
102 | + if (param.ds) { | ||
103 | + /* | ||
104 | + * With DS=1, BaseADDR is always shifted 16 so that it is able | ||
105 | + * to address all 52 va bits. The input address is perforce | ||
106 | + * aligned on a 64k boundary regardless of translation granule. | ||
107 | + */ | ||
108 | + page_shift = 16; | ||
109 | + } | ||
110 | ret.base <<= page_shift; | ||
111 | |||
112 | return ret; | ||
113 | @@ -XXX,XX +XXX,XX @@ static bool check_s2_mmu_setup(ARMCPU *cpu, bool is_aa64, int level, | ||
114 | const int grainsize = stride + 3; | ||
115 | int startsizecheck; | ||
116 | |||
117 | - /* Negative levels are never allowed. */ | ||
118 | - if (level < 0) { | ||
119 | + /* | ||
120 | + * Negative levels are usually not allowed... | ||
121 | + * Except for FEAT_LPA2, 4k page table, 52-bit address space, which | ||
122 | + * begins with level -1. Note that previous feature tests will have | ||
123 | + * eliminated this combination if it is not enabled. | ||
124 | + */ | ||
125 | + if (level < (inputsize == 52 && stride == 9 ? -1 : 0)) { | ||
126 | return false; | ||
127 | } | ||
128 | |||
129 | @@ -XXX,XX +XXX,XX @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, | ||
130 | ARMMMUIdx mmu_idx, bool data) | ||
131 | { | ||
132 | uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr; | ||
133 | - bool epd, hpd, using16k, using64k, tsz_oob; | ||
134 | - int select, tsz, tbi, max_tsz, min_tsz, ps; | ||
135 | + bool epd, hpd, using16k, using64k, tsz_oob, ds; | ||
136 | + int select, tsz, tbi, max_tsz, min_tsz, ps, sh; | ||
137 | + ARMCPU *cpu = env_archcpu(env); | ||
138 | |||
139 | if (!regime_has_2_ranges(mmu_idx)) { | ||
140 | select = 0; | ||
141 | @@ -XXX,XX +XXX,XX @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, | ||
142 | hpd = extract32(tcr, 24, 1); | ||
143 | } | ||
144 | epd = false; | ||
145 | + sh = extract32(tcr, 12, 2); | ||
146 | ps = extract32(tcr, 16, 3); | ||
147 | + ds = extract64(tcr, 32, 1); | ||
148 | } else { | ||
149 | /* | ||
150 | * Bit 55 is always between the two regions, and is canonical for | ||
151 | @@ -XXX,XX +XXX,XX @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, | ||
152 | if (!select) { | ||
153 | tsz = extract32(tcr, 0, 6); | ||
154 | epd = extract32(tcr, 7, 1); | ||
155 | + sh = extract32(tcr, 12, 2); | ||
156 | using64k = extract32(tcr, 14, 1); | ||
157 | using16k = extract32(tcr, 15, 1); | ||
158 | hpd = extract64(tcr, 41, 1); | ||
159 | @@ -XXX,XX +XXX,XX @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, | ||
160 | using64k = tg == 3; | ||
161 | tsz = extract32(tcr, 16, 6); | ||
162 | epd = extract32(tcr, 23, 1); | ||
163 | + sh = extract32(tcr, 28, 2); | ||
164 | hpd = extract64(tcr, 42, 1); | ||
165 | } | ||
166 | ps = extract64(tcr, 32, 3); | ||
167 | + ds = extract64(tcr, 59, 1); | ||
168 | } | ||
169 | |||
170 | - if (cpu_isar_feature(aa64_st, env_archcpu(env))) { | ||
171 | + if (cpu_isar_feature(aa64_st, cpu)) { | ||
172 | max_tsz = 48 - using64k; | ||
173 | } else { | ||
174 | max_tsz = 39; | ||
175 | } | ||
176 | |||
177 | + /* | ||
178 | + * DS is RES0 unless FEAT_LPA2 is supported for the given page size; | ||
179 | + * adjust the effective value of DS, as documented. | ||
180 | + */ | ||
181 | min_tsz = 16; | ||
182 | if (using64k) { | ||
183 | - if (cpu_isar_feature(aa64_lva, env_archcpu(env))) { | ||
184 | + if (cpu_isar_feature(aa64_lva, cpu)) { | ||
185 | + min_tsz = 12; | ||
186 | + } | ||
187 | + ds = false; | ||
188 | + } else if (ds) { | ||
189 | + switch (mmu_idx) { | ||
190 | + case ARMMMUIdx_Stage2: | ||
191 | + case ARMMMUIdx_Stage2_S: | ||
192 | + if (using16k) { | ||
193 | + ds = cpu_isar_feature(aa64_tgran16_2_lpa2, cpu); | ||
194 | + } else { | ||
195 | + ds = cpu_isar_feature(aa64_tgran4_2_lpa2, cpu); | ||
196 | + } | ||
197 | + break; | ||
198 | + default: | ||
199 | + if (using16k) { | ||
200 | + ds = cpu_isar_feature(aa64_tgran16_lpa2, cpu); | ||
201 | + } else { | ||
202 | + ds = cpu_isar_feature(aa64_tgran4_lpa2, cpu); | ||
203 | + } | ||
204 | + break; | ||
205 | + } | ||
206 | + if (ds) { | ||
207 | min_tsz = 12; | ||
208 | } | ||
209 | } | ||
210 | - /* TODO: FEAT_LPA2 */ | ||
211 | |||
212 | if (tsz > max_tsz) { | ||
213 | tsz = max_tsz; | ||
214 | @@ -XXX,XX +XXX,XX @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, | ||
215 | return (ARMVAParameters) { | ||
216 | .tsz = tsz, | ||
217 | .ps = ps, | ||
218 | + .sh = sh, | ||
219 | .select = select, | ||
220 | .tbi = tbi, | ||
221 | .epd = epd, | ||
222 | @@ -XXX,XX +XXX,XX @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, | ||
223 | .using16k = using16k, | ||
224 | .using64k = using64k, | ||
225 | .tsz_oob = tsz_oob, | ||
226 | + .ds = ds, | ||
227 | }; | ||
228 | } | ||
229 | |||
230 | @@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, | ||
231 | * VTCR_EL2.SL0 field (whose interpretation depends on the page size) | ||
232 | */ | ||
233 | uint32_t sl0 = extract32(tcr->raw_tcr, 6, 2); | ||
234 | + uint32_t sl2 = extract64(tcr->raw_tcr, 33, 1); | ||
235 | uint32_t startlevel; | ||
236 | bool ok; | ||
237 | |||
238 | - if (!aarch64 || stride == 9) { | ||
239 | + /* SL2 is RES0 unless DS=1 & 4kb granule. */ | ||
240 | + if (param.ds && stride == 9 && sl2) { | ||
241 | + if (sl0 != 0) { | ||
242 | + level = 0; | ||
243 | + fault_type = ARMFault_Translation; | ||
244 | + goto do_fault; | ||
245 | + } | ||
246 | + startlevel = -1; | ||
247 | + } else if (!aarch64 || stride == 9) { | ||
248 | /* AArch32 or 4KB pages */ | ||
249 | startlevel = 2 - sl0; | ||
250 | |||
251 | @@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, | ||
252 | * for both v7 and v8. However, for v8 the SBZ bits [47:40] must be 0 | ||
253 | * or an AddressSize fault is raised. So for v8 we extract those SBZ | ||
254 | * bits as part of the address, which will be checked via outputsize. | ||
255 | - * For AArch64, the address field always goes up to bit 47 (with extra | ||
256 | - * bits for FEAT_LPA placed elsewhere). AArch64 implies v8. | ||
257 | + * For AArch64, the address field goes up to bit 47, or 49 with FEAT_LPA2; | ||
258 | + * the highest bits of a 52-bit output are placed elsewhere. | ||
259 | */ | ||
260 | - if (arm_feature(env, ARM_FEATURE_V8)) { | ||
261 | + if (param.ds) { | ||
262 | + descaddrmask = MAKE_64BIT_MASK(0, 50); | ||
263 | + } else if (arm_feature(env, ARM_FEATURE_V8)) { | ||
264 | descaddrmask = MAKE_64BIT_MASK(0, 48); | ||
265 | } else { | ||
266 | descaddrmask = MAKE_64BIT_MASK(0, 40); | ||
267 | @@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, | ||
268 | |||
269 | /* | ||
270 | * For FEAT_LPA and PS=6, bits [51:48] of descaddr are in [15:12] | ||
271 | - * of descriptor. Otherwise, if descaddr is out of range, raise | ||
272 | - * AddressSizeFault. | ||
273 | + * of descriptor. For FEAT_LPA2 and effective DS, bits [51:50] of | ||
274 | + * descaddr are in [9:8]. Otherwise, if descaddr is out of range, | ||
275 | + * raise AddressSizeFault. | ||
276 | */ | ||
277 | if (outputsize > 48) { | ||
278 | - descaddr |= extract64(descriptor, 12, 4) << 48; | ||
279 | + if (param.ds) { | ||
280 | + descaddr |= extract64(descriptor, 8, 2) << 50; | ||
281 | + } else { | ||
282 | + descaddr |= extract64(descriptor, 12, 4) << 48; | ||
283 | + } | ||
284 | } else if (descaddr >> outputsize) { | ||
285 | fault_type = ARMFault_AddressSize; | ||
286 | goto do_fault; | ||
287 | @@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, | ||
288 | assert(attrindx <= 7); | ||
289 | cacheattrs->attrs = extract64(mair, attrindx * 8, 8); | ||
290 | } | ||
291 | - cacheattrs->shareability = extract32(attrs, 6, 2); | ||
292 | + | ||
293 | + /* | ||
294 | + * For FEAT_LPA2 and effective DS, the SH field in the attributes | ||
295 | + * was re-purposed for output address bits. The SH attribute in | ||
296 | + * that case comes from TCR_ELx, which we extracted earlier. | ||
297 | + */ | ||
298 | + if (param.ds) { | ||
299 | + cacheattrs->shareability = param.sh; | ||
300 | + } else { | ||
301 | + cacheattrs->shareability = extract32(attrs, 6, 2); | ||
302 | + } | ||
303 | |||
304 | *phys_ptr = descaddr; | ||
305 | *page_size_ptr = page_size; | ||
78 | -- | 306 | -- |
79 | 2.20.1 | 307 | 2.25.1 |
80 | |||
81 | diff view generated by jsdifflib |
1 | v8.1M adds new encodings of VLLDM and VLSTM (where bit 7 is set). | 1 | When we're using KVM, the PSCI implementation is provided by the |
---|---|---|---|
2 | The only difference is that: | 2 | kernel, but QEMU has to tell the guest about it via the device tree. |
3 | * the old T1 encodings UNDEF if the implementation implements 32 | 3 | Currently we look at the KVM_CAP_ARM_PSCI_0_2 capability to determine |
4 | Dregs (this is currently architecturally impossible for M-profile) | 4 | if the kernel is providing at least PSCI 0.2, but if the kernel |
5 | * the new T2 encodings have the implementation-defined option to | 5 | provides a newer version than that we will still only tell the guest |
6 | read from memory (discarding the data) or write UNKNOWN values to | 6 | it has PSCI 0.2. (This is fairly harmless; it just means the guest |
7 | memory for the stack slots that would be D16-D31 | 7 | won't use newer parts of the PSCI API.) |
8 | 8 | ||
9 | We choose not to make those accesses, so for us the two | 9 | The kernel exposes the specific PSCI version it is implementing via |
10 | instructions behave identically assuming they don't UNDEF. | 10 | the ONE_REG API; use this to report in the dtb that the PSCI |
11 | implementation is 1.0-compatible if appropriate. (The device tree | ||
12 | binding currently only distinguishes "pre-0.2", "0.2-compatible" and | ||
13 | "1.0-compatible".) | ||
11 | 14 | ||
12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 15 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
16 | Reviewed-by: Marc Zyngier <maz@kernel.org> | ||
17 | Reviewed-by: Akihiko Odaki <akihiko.odaki@gmail.com> | ||
13 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 18 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
14 | Message-id: 20201119215617.29887-21-peter.maydell@linaro.org | 19 | Reviewed-by: Andrew Jones <drjones@redhat.com> |
20 | Message-id: 20220224134655.1207865-1-peter.maydell@linaro.org | ||
15 | --- | 21 | --- |
16 | target/arm/m-nocp.decode | 2 +- | 22 | target/arm/kvm-consts.h | 1 + |
17 | target/arm/translate-vfp.c.inc | 25 +++++++++++++++++++++++++ | 23 | hw/arm/boot.c | 5 ++--- |
18 | 2 files changed, 26 insertions(+), 1 deletion(-) | 24 | target/arm/kvm64.c | 12 ++++++++++++ |
25 | 3 files changed, 15 insertions(+), 3 deletions(-) | ||
19 | 26 | ||
20 | diff --git a/target/arm/m-nocp.decode b/target/arm/m-nocp.decode | 27 | diff --git a/target/arm/kvm-consts.h b/target/arm/kvm-consts.h |
21 | index XXXXXXX..XXXXXXX 100644 | 28 | index XXXXXXX..XXXXXXX 100644 |
22 | --- a/target/arm/m-nocp.decode | 29 | --- a/target/arm/kvm-consts.h |
23 | +++ b/target/arm/m-nocp.decode | 30 | +++ b/target/arm/kvm-consts.h |
24 | @@ -XXX,XX +XXX,XX @@ | 31 | @@ -XXX,XX +XXX,XX @@ MISMATCH_CHECK(QEMU_PSCI_1_0_FN_PSCI_FEATURES, PSCI_1_0_FN_PSCI_FEATURES); |
25 | 32 | ||
26 | { | 33 | #define QEMU_PSCI_VERSION_0_1 0x00001 |
27 | # Special cases which do not take an early NOCP: VLLDM and VLSTM | 34 | #define QEMU_PSCI_VERSION_0_2 0x00002 |
28 | - VLLDM_VLSTM 1110 1100 001 l:1 rn:4 0000 1010 0000 0000 | 35 | +#define QEMU_PSCI_VERSION_1_0 0x10000 |
29 | + VLLDM_VLSTM 1110 1100 001 l:1 rn:4 0000 1010 op:1 000 0000 | 36 | #define QEMU_PSCI_VERSION_1_1 0x10001 |
30 | # VSCCLRM (new in v8.1M) is similar: | 37 | |
31 | VSCCLRM 1110 1100 1.01 1111 .... 1011 imm:7 0 vd=%vd_dp size=3 | 38 | MISMATCH_CHECK(QEMU_PSCI_0_2_RET_TOS_MIGRATION_NOT_REQUIRED, PSCI_0_2_TOS_MP); |
32 | VSCCLRM 1110 1100 1.01 1111 .... 1010 imm:8 vd=%vd_sp size=2 | 39 | diff --git a/hw/arm/boot.c b/hw/arm/boot.c |
33 | diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc | ||
34 | index XXXXXXX..XXXXXXX 100644 | 40 | index XXXXXXX..XXXXXXX 100644 |
35 | --- a/target/arm/translate-vfp.c.inc | 41 | --- a/hw/arm/boot.c |
36 | +++ b/target/arm/translate-vfp.c.inc | 42 | +++ b/hw/arm/boot.c |
37 | @@ -XXX,XX +XXX,XX @@ static bool trans_VLLDM_VLSTM(DisasContext *s, arg_VLLDM_VLSTM *a) | 43 | @@ -XXX,XX +XXX,XX @@ static void fdt_add_psci_node(void *fdt) |
38 | !arm_dc_feature(s, ARM_FEATURE_V8)) { | ||
39 | return false; | ||
40 | } | 44 | } |
41 | + | 45 | |
42 | + if (a->op) { | 46 | qemu_fdt_add_subnode(fdt, "/psci"); |
43 | + /* | 47 | - if (armcpu->psci_version == QEMU_PSCI_VERSION_0_2 || |
44 | + * T2 encoding ({D0-D31} reglist): v8.1M and up. We choose not | 48 | - armcpu->psci_version == QEMU_PSCI_VERSION_1_1) { |
45 | + * to take the IMPDEF option to make memory accesses to the stack | 49 | - if (armcpu->psci_version == QEMU_PSCI_VERSION_0_2) { |
46 | + * slots that correspond to the D16-D31 registers (discarding | 50 | + if (armcpu->psci_version >= QEMU_PSCI_VERSION_0_2) { |
47 | + * read data and writing UNKNOWN values), so for us the T2 | 51 | + if (armcpu->psci_version < QEMU_PSCI_VERSION_1_0) { |
48 | + * encoding behaves identically to the T1 encoding. | 52 | const char comp[] = "arm,psci-0.2\0arm,psci"; |
49 | + */ | 53 | qemu_fdt_setprop(fdt, "/psci", "compatible", comp, sizeof(comp)); |
50 | + if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) { | 54 | } else { |
51 | + return false; | 55 | diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c |
52 | + } | 56 | index XXXXXXX..XXXXXXX 100644 |
53 | + } else { | 57 | --- a/target/arm/kvm64.c |
54 | + /* | 58 | +++ b/target/arm/kvm64.c |
55 | + * T1 encoding ({D0-D15} reglist); undef if we have 32 Dregs. | 59 | @@ -XXX,XX +XXX,XX @@ int kvm_arch_init_vcpu(CPUState *cs) |
56 | + * This is currently architecturally impossible, but we add the | 60 | uint64_t mpidr; |
57 | + * check to stay in line with the pseudocode. Note that we must | 61 | ARMCPU *cpu = ARM_CPU(cs); |
58 | + * emit code for the UNDEF so it takes precedence over the NOCP. | 62 | CPUARMState *env = &cpu->env; |
59 | + */ | 63 | + uint64_t psciver; |
60 | + if (dc_isar_feature(aa32_simd_r32, s)) { | 64 | |
61 | + unallocated_encoding(s); | 65 | if (cpu->kvm_target == QEMU_KVM_ARM_TARGET_NONE || |
62 | + return true; | 66 | !object_dynamic_cast(OBJECT(cpu), TYPE_AARCH64_CPU)) { |
63 | + } | 67 | @@ -XXX,XX +XXX,XX @@ int kvm_arch_init_vcpu(CPUState *cs) |
68 | } | ||
69 | } | ||
70 | |||
71 | + /* | ||
72 | + * KVM reports the exact PSCI version it is implementing via a | ||
73 | + * special sysreg. If it is present, use its contents to determine | ||
74 | + * what to report to the guest in the dtb (it is the PSCI version, | ||
75 | + * in the same 15-bits major 16-bits minor format that PSCI_VERSION | ||
76 | + * returns). | ||
77 | + */ | ||
78 | + if (!kvm_get_one_reg(cs, KVM_REG_ARM_PSCI_VERSION, &psciver)) { | ||
79 | + cpu->psci_version = psciver; | ||
64 | + } | 80 | + } |
65 | + | 81 | + |
66 | /* | 82 | /* |
67 | * If not secure, UNDEF. We must emit code for this | 83 | * When KVM is in use, PSCI is emulated in-kernel and not by qemu. |
68 | * rather than returning false so that this takes | 84 | * Currently KVM has its own idea about MPIDR assignment, so we |
69 | -- | 85 | -- |
70 | 2.20.1 | 86 | 2.25.1 |
71 | |||
72 | diff view generated by jsdifflib |
1 | Implement the new-in-v8.1M VLDR/VSTR variants which directly | 1 | The updateUIInfo method makes Cocoa API calls. It also calls back |
---|---|---|---|
2 | read or write FP system registers to memory. | 2 | into QEMU functions like dpy_set_ui_info(). To do this safely, we |
3 | need to follow two rules: | ||
4 | * Cocoa API calls are made on the Cocoa UI thread | ||
5 | * When calling back into QEMU we must hold the iothread lock | ||
6 | |||
7 | Fix the places where we got this wrong, by taking the iothread lock | ||
8 | while executing updateUIInfo, and moving the call in cocoa_switch() | ||
9 | inside the dispatch_async block. | ||
10 | |||
11 | Some of the Cocoa UI methods which call updateUIInfo are invoked as | ||
12 | part of the initial application startup, while we're still doing the | ||
13 | little cross-thread dance described in the comment just above | ||
14 | call_qemu_main(). This meant they were calling back into the QEMU UI | ||
15 | layer before we'd actually finished initializing our display and | ||
16 | registered the DisplayChangeListener, which isn't really valid. Once | ||
17 | updateUIInfo takes the iothread lock, we no longer get away with | ||
18 | this, because during this startup phase the iothread lock is held by | ||
19 | the QEMU main-loop thread which is waiting for us to finish our | ||
20 | display initialization. So we must suppress updateUIInfo until | ||
21 | applicationDidFinishLaunching allows the QEMU main-loop thread to | ||
22 | continue. | ||
3 | 23 | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 24 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 25 | Reviewed-by: Akihiko Odaki <akihiko.odaki@gmail.com> |
6 | Message-id: 20201119215617.29887-10-peter.maydell@linaro.org | 26 | Tested-by: Akihiko Odaki <akihiko.odaki@gmail.com> |
27 | Message-id: 20220224101330.967429-2-peter.maydell@linaro.org | ||
7 | --- | 28 | --- |
8 | target/arm/vfp.decode | 14 ++++++ | 29 | ui/cocoa.m | 25 ++++++++++++++++++++++--- |
9 | target/arm/translate-vfp.c.inc | 91 ++++++++++++++++++++++++++++++++++ | 30 | 1 file changed, 22 insertions(+), 3 deletions(-) |
10 | 2 files changed, 105 insertions(+) | ||
11 | 31 | ||
12 | diff --git a/target/arm/vfp.decode b/target/arm/vfp.decode | 32 | diff --git a/ui/cocoa.m b/ui/cocoa.m |
13 | index XXXXXXX..XXXXXXX 100644 | 33 | index XXXXXXX..XXXXXXX 100644 |
14 | --- a/target/arm/vfp.decode | 34 | --- a/ui/cocoa.m |
15 | +++ b/target/arm/vfp.decode | 35 | +++ b/ui/cocoa.m |
16 | @@ -XXX,XX +XXX,XX @@ VLDR_VSTR_hp ---- 1101 u:1 .0 l:1 rn:4 .... 1001 imm:8 vd=%vd_sp | 36 | @@ -XXX,XX +XXX,XX @@ QemuCocoaView *cocoaView; |
17 | VLDR_VSTR_sp ---- 1101 u:1 .0 l:1 rn:4 .... 1010 imm:8 vd=%vd_sp | 37 | } |
18 | VLDR_VSTR_dp ---- 1101 u:1 .0 l:1 rn:4 .... 1011 imm:8 vd=%vd_dp | ||
19 | |||
20 | +# M-profile VLDR/VSTR to sysreg | ||
21 | +%vldr_sysreg 22:1 13:3 | ||
22 | +%imm7_0x4 0:7 !function=times_4 | ||
23 | + | ||
24 | +&vldr_sysreg rn reg imm a w p | ||
25 | +@vldr_sysreg .... ... . a:1 . . . rn:4 ... . ... .. ....... \ | ||
26 | + reg=%vldr_sysreg imm=%imm7_0x4 &vldr_sysreg | ||
27 | + | ||
28 | +# P=0 W=0 is SEE "Related encodings", so split into two patterns | ||
29 | +VLDR_sysreg ---- 110 1 . . w:1 1 .... ... 0 111 11 ....... @vldr_sysreg p=1 | ||
30 | +VLDR_sysreg ---- 110 0 . . 1 1 .... ... 0 111 11 ....... @vldr_sysreg p=0 w=1 | ||
31 | +VSTR_sysreg ---- 110 1 . . w:1 0 .... ... 0 111 11 ....... @vldr_sysreg p=1 | ||
32 | +VSTR_sysreg ---- 110 0 . . 1 0 .... ... 0 111 11 ....... @vldr_sysreg p=0 w=1 | ||
33 | + | ||
34 | # We split the load/store multiple up into two patterns to avoid | ||
35 | # overlap with other insns in the "Advanced SIMD load/store and 64-bit move" | ||
36 | # grouping: | ||
37 | diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc | ||
38 | index XXXXXXX..XXXXXXX 100644 | ||
39 | --- a/target/arm/translate-vfp.c.inc | ||
40 | +++ b/target/arm/translate-vfp.c.inc | ||
41 | @@ -XXX,XX +XXX,XX @@ static bool trans_VMSR_VMRS(DisasContext *s, arg_VMSR_VMRS *a) | ||
42 | return true; | ||
43 | } | 38 | } |
44 | 39 | ||
45 | +static void fp_sysreg_to_memory(DisasContext *s, void *opaque, TCGv_i32 value) | 40 | -- (void) updateUIInfo |
41 | +- (void) updateUIInfoLocked | ||
42 | { | ||
43 | + /* Must be called with the iothread lock, i.e. via updateUIInfo */ | ||
44 | NSSize frameSize; | ||
45 | QemuUIInfo info; | ||
46 | |||
47 | @@ -XXX,XX +XXX,XX @@ QemuCocoaView *cocoaView; | ||
48 | dpy_set_ui_info(dcl.con, &info, TRUE); | ||
49 | } | ||
50 | |||
51 | +- (void) updateUIInfo | ||
46 | +{ | 52 | +{ |
47 | + arg_vldr_sysreg *a = opaque; | 53 | + if (!allow_events) { |
48 | + uint32_t offset = a->imm; | 54 | + /* |
49 | + TCGv_i32 addr; | 55 | + * Don't try to tell QEMU about UI information in the application |
50 | + | 56 | + * startup phase -- we haven't yet registered dcl with the QEMU UI |
51 | + if (!a->a) { | 57 | + * layer, and also trying to take the iothread lock would deadlock. |
52 | + offset = - offset; | 58 | + * When cocoa_display_init() does register the dcl, the UI layer |
59 | + * will call cocoa_switch(), which will call updateUIInfo, so | ||
60 | + * we don't lose any information here. | ||
61 | + */ | ||
62 | + return; | ||
53 | + } | 63 | + } |
54 | + | 64 | + |
55 | + addr = load_reg(s, a->rn); | 65 | + with_iothread_lock(^{ |
56 | + if (a->p) { | 66 | + [self updateUIInfoLocked]; |
57 | + tcg_gen_addi_i32(addr, addr, offset); | 67 | + }); |
58 | + } | ||
59 | + | ||
60 | + if (s->v8m_stackcheck && a->rn == 13 && a->w) { | ||
61 | + gen_helper_v8m_stackcheck(cpu_env, addr); | ||
62 | + } | ||
63 | + | ||
64 | + gen_aa32_st_i32(s, value, addr, get_mem_index(s), | ||
65 | + MO_UL | MO_ALIGN | s->be_data); | ||
66 | + tcg_temp_free_i32(value); | ||
67 | + | ||
68 | + if (a->w) { | ||
69 | + /* writeback */ | ||
70 | + if (!a->p) { | ||
71 | + tcg_gen_addi_i32(addr, addr, offset); | ||
72 | + } | ||
73 | + store_reg(s, a->rn, addr); | ||
74 | + } else { | ||
75 | + tcg_temp_free_i32(addr); | ||
76 | + } | ||
77 | +} | 68 | +} |
78 | + | 69 | + |
79 | +static TCGv_i32 memory_to_fp_sysreg(DisasContext *s, void *opaque) | 70 | - (void)viewDidMoveToWindow |
80 | +{ | ||
81 | + arg_vldr_sysreg *a = opaque; | ||
82 | + uint32_t offset = a->imm; | ||
83 | + TCGv_i32 addr; | ||
84 | + TCGv_i32 value = tcg_temp_new_i32(); | ||
85 | + | ||
86 | + if (!a->a) { | ||
87 | + offset = - offset; | ||
88 | + } | ||
89 | + | ||
90 | + addr = load_reg(s, a->rn); | ||
91 | + if (a->p) { | ||
92 | + tcg_gen_addi_i32(addr, addr, offset); | ||
93 | + } | ||
94 | + | ||
95 | + if (s->v8m_stackcheck && a->rn == 13 && a->w) { | ||
96 | + gen_helper_v8m_stackcheck(cpu_env, addr); | ||
97 | + } | ||
98 | + | ||
99 | + gen_aa32_ld_i32(s, value, addr, get_mem_index(s), | ||
100 | + MO_UL | MO_ALIGN | s->be_data); | ||
101 | + | ||
102 | + if (a->w) { | ||
103 | + /* writeback */ | ||
104 | + if (!a->p) { | ||
105 | + tcg_gen_addi_i32(addr, addr, offset); | ||
106 | + } | ||
107 | + store_reg(s, a->rn, addr); | ||
108 | + } else { | ||
109 | + tcg_temp_free_i32(addr); | ||
110 | + } | ||
111 | + return value; | ||
112 | +} | ||
113 | + | ||
114 | +static bool trans_VLDR_sysreg(DisasContext *s, arg_vldr_sysreg *a) | ||
115 | +{ | ||
116 | + if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) { | ||
117 | + return false; | ||
118 | + } | ||
119 | + if (a->rn == 15) { | ||
120 | + return false; | ||
121 | + } | ||
122 | + return gen_M_fp_sysreg_write(s, a->reg, memory_to_fp_sysreg, a); | ||
123 | +} | ||
124 | + | ||
125 | +static bool trans_VSTR_sysreg(DisasContext *s, arg_vldr_sysreg *a) | ||
126 | +{ | ||
127 | + if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) { | ||
128 | + return false; | ||
129 | + } | ||
130 | + if (a->rn == 15) { | ||
131 | + return false; | ||
132 | + } | ||
133 | + return gen_M_fp_sysreg_read(s, a->reg, fp_sysreg_to_memory, a); | ||
134 | +} | ||
135 | + | ||
136 | static bool trans_VMOV_half(DisasContext *s, arg_VMOV_single *a) | ||
137 | { | 71 | { |
138 | TCGv_i32 tmp; | 72 | [self updateUIInfo]; |
73 | @@ -XXX,XX +XXX,XX @@ static void cocoa_switch(DisplayChangeListener *dcl, | ||
74 | |||
75 | COCOA_DEBUG("qemu_cocoa: cocoa_switch\n"); | ||
76 | |||
77 | - [cocoaView updateUIInfo]; | ||
78 | - | ||
79 | // The DisplaySurface will be freed as soon as this callback returns. | ||
80 | // We take a reference to the underlying pixman image here so it does | ||
81 | // not disappear from under our feet; the switchSurface method will | ||
82 | @@ -XXX,XX +XXX,XX @@ static void cocoa_switch(DisplayChangeListener *dcl, | ||
83 | pixman_image_ref(image); | ||
84 | |||
85 | dispatch_async(dispatch_get_main_queue(), ^{ | ||
86 | + [cocoaView updateUIInfo]; | ||
87 | [cocoaView switchSurface:image]; | ||
88 | }); | ||
89 | [pool release]; | ||
139 | -- | 90 | -- |
140 | 2.20.1 | 91 | 2.25.1 |
141 | |||
142 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | v8.1M defines a new FP system register FPSCR_nzcvqc; this behaves | ||
2 | like the existing FPSCR, except that it reads and writes only bits | ||
3 | [31:27] of the FPSCR (the N, Z, C, V and QC flag bits). (Unlike the | ||
4 | FPSCR, the special case for Rt=15 of writing the CPSR.NZCV is not | ||
5 | permitted.) | ||
6 | 1 | ||
7 | Implement the register. Since we don't yet implement MVE, we handle | ||
8 | the QC bit as RES0, with todo comments for where we will need to add | ||
9 | support later. | ||
10 | |||
11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
12 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
13 | Message-id: 20201119215617.29887-11-peter.maydell@linaro.org | ||
14 | --- | ||
15 | target/arm/cpu.h | 13 +++++++++++++ | ||
16 | target/arm/translate-vfp.c.inc | 27 +++++++++++++++++++++++++++ | ||
17 | 2 files changed, 40 insertions(+) | ||
18 | |||
19 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | ||
20 | index XXXXXXX..XXXXXXX 100644 | ||
21 | --- a/target/arm/cpu.h | ||
22 | +++ b/target/arm/cpu.h | ||
23 | @@ -XXX,XX +XXX,XX @@ void vfp_set_fpscr(CPUARMState *env, uint32_t val); | ||
24 | #define FPCR_FZ (1 << 24) /* Flush-to-zero enable bit */ | ||
25 | #define FPCR_DN (1 << 25) /* Default NaN enable bit */ | ||
26 | #define FPCR_QC (1 << 27) /* Cumulative saturation bit */ | ||
27 | +#define FPCR_V (1 << 28) /* FP overflow flag */ | ||
28 | +#define FPCR_C (1 << 29) /* FP carry flag */ | ||
29 | +#define FPCR_Z (1 << 30) /* FP zero flag */ | ||
30 | +#define FPCR_N (1 << 31) /* FP negative flag */ | ||
31 | + | ||
32 | +#define FPCR_NZCV_MASK (FPCR_N | FPCR_Z | FPCR_C | FPCR_V) | ||
33 | +#define FPCR_NZCVQC_MASK (FPCR_NZCV_MASK | FPCR_QC) | ||
34 | |||
35 | static inline uint32_t vfp_get_fpsr(CPUARMState *env) | ||
36 | { | ||
37 | @@ -XXX,XX +XXX,XX @@ enum arm_cpu_mode { | ||
38 | #define ARM_VFP_FPEXC 8 | ||
39 | #define ARM_VFP_FPINST 9 | ||
40 | #define ARM_VFP_FPINST2 10 | ||
41 | +/* These ones are M-profile only */ | ||
42 | +#define ARM_VFP_FPSCR_NZCVQC 2 | ||
43 | +#define ARM_VFP_VPR 12 | ||
44 | +#define ARM_VFP_P0 13 | ||
45 | +#define ARM_VFP_FPCXT_NS 14 | ||
46 | +#define ARM_VFP_FPCXT_S 15 | ||
47 | |||
48 | /* QEMU-internal value meaning "FPSCR, but we care only about NZCV" */ | ||
49 | #define QEMU_VFP_FPSCR_NZCV 0xffff | ||
50 | diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc | ||
51 | index XXXXXXX..XXXXXXX 100644 | ||
52 | --- a/target/arm/translate-vfp.c.inc | ||
53 | +++ b/target/arm/translate-vfp.c.inc | ||
54 | @@ -XXX,XX +XXX,XX @@ static FPSysRegCheckResult fp_sysreg_checks(DisasContext *s, int regno) | ||
55 | case ARM_VFP_FPSCR: | ||
56 | case QEMU_VFP_FPSCR_NZCV: | ||
57 | break; | ||
58 | + case ARM_VFP_FPSCR_NZCVQC: | ||
59 | + if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) { | ||
60 | + return false; | ||
61 | + } | ||
62 | + break; | ||
63 | default: | ||
64 | return FPSysRegCheckFailed; | ||
65 | } | ||
66 | @@ -XXX,XX +XXX,XX @@ static bool gen_M_fp_sysreg_write(DisasContext *s, int regno, | ||
67 | tcg_temp_free_i32(tmp); | ||
68 | gen_lookup_tb(s); | ||
69 | break; | ||
70 | + case ARM_VFP_FPSCR_NZCVQC: | ||
71 | + { | ||
72 | + TCGv_i32 fpscr; | ||
73 | + tmp = loadfn(s, opaque); | ||
74 | + /* | ||
75 | + * TODO: when we implement MVE, write the QC bit. | ||
76 | + * For non-MVE, QC is RES0. | ||
77 | + */ | ||
78 | + tcg_gen_andi_i32(tmp, tmp, FPCR_NZCV_MASK); | ||
79 | + fpscr = load_cpu_field(vfp.xregs[ARM_VFP_FPSCR]); | ||
80 | + tcg_gen_andi_i32(fpscr, fpscr, ~FPCR_NZCV_MASK); | ||
81 | + tcg_gen_or_i32(fpscr, fpscr, tmp); | ||
82 | + store_cpu_field(fpscr, vfp.xregs[ARM_VFP_FPSCR]); | ||
83 | + tcg_temp_free_i32(tmp); | ||
84 | + break; | ||
85 | + } | ||
86 | default: | ||
87 | g_assert_not_reached(); | ||
88 | } | ||
89 | @@ -XXX,XX +XXX,XX @@ static bool gen_M_fp_sysreg_read(DisasContext *s, int regno, | ||
90 | gen_helper_vfp_get_fpscr(tmp, cpu_env); | ||
91 | storefn(s, opaque, tmp); | ||
92 | break; | ||
93 | + case ARM_VFP_FPSCR_NZCVQC: | ||
94 | + /* | ||
95 | + * TODO: MVE has a QC bit, which we probably won't store | ||
96 | + * in the xregs[] field. For non-MVE, where QC is RES0, | ||
97 | + * we can just fall through to the FPSCR_NZCV case. | ||
98 | + */ | ||
99 | case QEMU_VFP_FPSCR_NZCV: | ||
100 | /* | ||
101 | * Read just NZCV; this is a special case to avoid the | ||
102 | -- | ||
103 | 2.20.1 | ||
104 | |||
105 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | We defined a constant name for the mask of NZCV bits in the FPCR/FPSCR | ||
2 | in the previous commit; use it in a couple of places in existing code, | ||
3 | where we're masking out everything except NZCV for the "load to Rt=15 | ||
4 | sets CPSR.NZCV" special case. | ||
5 | 1 | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Message-id: 20201119215617.29887-12-peter.maydell@linaro.org | ||
9 | --- | ||
10 | target/arm/translate-vfp.c.inc | 4 ++-- | ||
11 | 1 file changed, 2 insertions(+), 2 deletions(-) | ||
12 | |||
13 | diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc | ||
14 | index XXXXXXX..XXXXXXX 100644 | ||
15 | --- a/target/arm/translate-vfp.c.inc | ||
16 | +++ b/target/arm/translate-vfp.c.inc | ||
17 | @@ -XXX,XX +XXX,XX @@ static bool gen_M_fp_sysreg_read(DisasContext *s, int regno, | ||
18 | * helper call for the "VMRS to CPSR.NZCV" insn. | ||
19 | */ | ||
20 | tmp = load_cpu_field(vfp.xregs[ARM_VFP_FPSCR]); | ||
21 | - tcg_gen_andi_i32(tmp, tmp, 0xf0000000); | ||
22 | + tcg_gen_andi_i32(tmp, tmp, FPCR_NZCV_MASK); | ||
23 | storefn(s, opaque, tmp); | ||
24 | break; | ||
25 | default: | ||
26 | @@ -XXX,XX +XXX,XX @@ static bool trans_VMSR_VMRS(DisasContext *s, arg_VMSR_VMRS *a) | ||
27 | case ARM_VFP_FPSCR: | ||
28 | if (a->rt == 15) { | ||
29 | tmp = load_cpu_field(vfp.xregs[ARM_VFP_FPSCR]); | ||
30 | - tcg_gen_andi_i32(tmp, tmp, 0xf0000000); | ||
31 | + tcg_gen_andi_i32(tmp, tmp, FPCR_NZCV_MASK); | ||
32 | } else { | ||
33 | tmp = tcg_temp_new_i32(); | ||
34 | gen_helper_vfp_get_fpscr(tmp, cpu_env); | ||
35 | -- | ||
36 | 2.20.1 | ||
37 | |||
38 | diff view generated by jsdifflib |
1 | Factor out the code which handles M-profile lazy FP state preservation | 1 | In commit 6e657e64cdc478 in 2013 we added some autorelease pools to |
---|---|---|---|
2 | from full_vfp_access_check(); accesses to the FPCXT_NS register are | 2 | deal with complaints from macOS when we made calls into Cocoa from |
3 | a special case which need to do just this part (corresponding in the | 3 | threads that didn't have automatically created autorelease pools. |
4 | pseudocode to the PreserveFPState() function), and not the full | 4 | Later on, macOS got stricter about forbidding cross-thread Cocoa |
5 | set of actions matching the pseudocode ExecuteFPCheck() which | 5 | calls, and in commit 5588840ff77800e839d8 we restructured the code to |
6 | normal FP instructions need to do. | 6 | avoid them. This left the autorelease pool creation in several |
7 | functions without any purpose; delete it. | ||
8 | |||
9 | We still need the pool in cocoa_refresh() for the clipboard related | ||
10 | code which is called directly there. | ||
7 | 11 | ||
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
9 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 13 | Reviewed-by: Akihiko Odaki <akihiko.odaki@gmail.com> |
10 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 14 | Tested-by: Akihiko Odaki <akihiko.odaki@gmail.com> |
11 | Message-id: 20201119215617.29887-13-peter.maydell@linaro.org | 15 | Message-id: 20220224101330.967429-3-peter.maydell@linaro.org |
12 | --- | 16 | --- |
13 | target/arm/translate-vfp.c.inc | 45 ++++++++++++++++++++-------------- | 17 | ui/cocoa.m | 6 ------ |
14 | 1 file changed, 27 insertions(+), 18 deletions(-) | 18 | 1 file changed, 6 deletions(-) |
15 | 19 | ||
16 | diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc | 20 | diff --git a/ui/cocoa.m b/ui/cocoa.m |
17 | index XXXXXXX..XXXXXXX 100644 | 21 | index XXXXXXX..XXXXXXX 100644 |
18 | --- a/target/arm/translate-vfp.c.inc | 22 | --- a/ui/cocoa.m |
19 | +++ b/target/arm/translate-vfp.c.inc | 23 | +++ b/ui/cocoa.m |
20 | @@ -XXX,XX +XXX,XX @@ static inline long vfp_f16_offset(unsigned reg, bool top) | 24 | @@ -XXX,XX +XXX,XX @@ int main (int argc, char **argv) { |
21 | return offs; | 25 | static void cocoa_update(DisplayChangeListener *dcl, |
26 | int x, int y, int w, int h) | ||
27 | { | ||
28 | - NSAutoreleasePool * pool = [[NSAutoreleasePool alloc] init]; | ||
29 | - | ||
30 | COCOA_DEBUG("qemu_cocoa: cocoa_update\n"); | ||
31 | |||
32 | dispatch_async(dispatch_get_main_queue(), ^{ | ||
33 | @@ -XXX,XX +XXX,XX @@ static void cocoa_update(DisplayChangeListener *dcl, | ||
34 | } | ||
35 | [cocoaView setNeedsDisplayInRect:rect]; | ||
36 | }); | ||
37 | - | ||
38 | - [pool release]; | ||
22 | } | 39 | } |
23 | 40 | ||
24 | +/* | 41 | static void cocoa_switch(DisplayChangeListener *dcl, |
25 | + * Generate code for M-profile lazy FP state preservation if needed; | 42 | DisplaySurface *surface) |
26 | + * this corresponds to the pseudocode PreserveFPState() function. | 43 | { |
27 | + */ | 44 | - NSAutoreleasePool * pool = [[NSAutoreleasePool alloc] init]; |
28 | +static void gen_preserve_fp_state(DisasContext *s) | 45 | pixman_image_t *image = surface->image; |
29 | +{ | 46 | |
30 | + if (s->v7m_lspact) { | 47 | COCOA_DEBUG("qemu_cocoa: cocoa_switch\n"); |
31 | + /* | 48 | @@ -XXX,XX +XXX,XX @@ static void cocoa_switch(DisplayChangeListener *dcl, |
32 | + * Lazy state saving affects external memory and also the NVIC, | 49 | [cocoaView updateUIInfo]; |
33 | + * so we must mark it as an IO operation for icount (and cause | 50 | [cocoaView switchSurface:image]; |
34 | + * this to be the last insn in the TB). | 51 | }); |
35 | + */ | 52 | - [pool release]; |
36 | + if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { | 53 | } |
37 | + s->base.is_jmp = DISAS_UPDATE_EXIT; | 54 | |
38 | + gen_io_start(); | 55 | static void cocoa_refresh(DisplayChangeListener *dcl) |
39 | + } | ||
40 | + gen_helper_v7m_preserve_fp_state(cpu_env); | ||
41 | + /* | ||
42 | + * If the preserve_fp_state helper doesn't throw an exception | ||
43 | + * then it will clear LSPACT; we don't need to repeat this for | ||
44 | + * any further FP insns in this TB. | ||
45 | + */ | ||
46 | + s->v7m_lspact = false; | ||
47 | + } | ||
48 | +} | ||
49 | + | ||
50 | /* | ||
51 | * Check that VFP access is enabled. If it is, do the necessary | ||
52 | * M-profile lazy-FP handling and then return true. | ||
53 | @@ -XXX,XX +XXX,XX @@ static bool full_vfp_access_check(DisasContext *s, bool ignore_vfp_enabled) | ||
54 | /* Handle M-profile lazy FP state mechanics */ | ||
55 | |||
56 | /* Trigger lazy-state preservation if necessary */ | ||
57 | - if (s->v7m_lspact) { | ||
58 | - /* | ||
59 | - * Lazy state saving affects external memory and also the NVIC, | ||
60 | - * so we must mark it as an IO operation for icount (and cause | ||
61 | - * this to be the last insn in the TB). | ||
62 | - */ | ||
63 | - if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { | ||
64 | - s->base.is_jmp = DISAS_UPDATE_EXIT; | ||
65 | - gen_io_start(); | ||
66 | - } | ||
67 | - gen_helper_v7m_preserve_fp_state(cpu_env); | ||
68 | - /* | ||
69 | - * If the preserve_fp_state helper doesn't throw an exception | ||
70 | - * then it will clear LSPACT; we don't need to repeat this for | ||
71 | - * any further FP insns in this TB. | ||
72 | - */ | ||
73 | - s->v7m_lspact = false; | ||
74 | - } | ||
75 | + gen_preserve_fp_state(s); | ||
76 | |||
77 | /* Update ownership of FP context: set FPCCR.S to match current state */ | ||
78 | if (s->v8m_fpccr_s_wrong) { | ||
79 | -- | 56 | -- |
80 | 2.20.1 | 57 | 2.25.1 |
81 | |||
82 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | Implement the new-in-v8.1M FPCXT_S floating point system register. | ||
2 | This is for saving and restoring the secure floating point context, | ||
3 | and it reads and writes bits [27:0] from the FPSCR and the | ||
4 | CONTROL.SFPA bit in bit [31]. | ||
5 | 1 | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Message-id: 20201119215617.29887-14-peter.maydell@linaro.org | ||
9 | --- | ||
10 | target/arm/translate-vfp.c.inc | 58 ++++++++++++++++++++++++++++++++++ | ||
11 | 1 file changed, 58 insertions(+) | ||
12 | |||
13 | diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc | ||
14 | index XXXXXXX..XXXXXXX 100644 | ||
15 | --- a/target/arm/translate-vfp.c.inc | ||
16 | +++ b/target/arm/translate-vfp.c.inc | ||
17 | @@ -XXX,XX +XXX,XX @@ static FPSysRegCheckResult fp_sysreg_checks(DisasContext *s, int regno) | ||
18 | return false; | ||
19 | } | ||
20 | break; | ||
21 | + case ARM_VFP_FPCXT_S: | ||
22 | + if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) { | ||
23 | + return false; | ||
24 | + } | ||
25 | + if (!s->v8m_secure) { | ||
26 | + return false; | ||
27 | + } | ||
28 | + break; | ||
29 | default: | ||
30 | return FPSysRegCheckFailed; | ||
31 | } | ||
32 | @@ -XXX,XX +XXX,XX @@ static bool gen_M_fp_sysreg_write(DisasContext *s, int regno, | ||
33 | tcg_temp_free_i32(tmp); | ||
34 | break; | ||
35 | } | ||
36 | + case ARM_VFP_FPCXT_S: | ||
37 | + { | ||
38 | + TCGv_i32 sfpa, control, fpscr; | ||
39 | + /* Set FPSCR[27:0] and CONTROL.SFPA from value */ | ||
40 | + tmp = loadfn(s, opaque); | ||
41 | + sfpa = tcg_temp_new_i32(); | ||
42 | + tcg_gen_shri_i32(sfpa, tmp, 31); | ||
43 | + control = load_cpu_field(v7m.control[M_REG_S]); | ||
44 | + tcg_gen_deposit_i32(control, control, sfpa, | ||
45 | + R_V7M_CONTROL_SFPA_SHIFT, 1); | ||
46 | + store_cpu_field(control, v7m.control[M_REG_S]); | ||
47 | + fpscr = load_cpu_field(vfp.xregs[ARM_VFP_FPSCR]); | ||
48 | + tcg_gen_andi_i32(fpscr, fpscr, FPCR_NZCV_MASK); | ||
49 | + tcg_gen_andi_i32(tmp, tmp, ~FPCR_NZCV_MASK); | ||
50 | + tcg_gen_or_i32(fpscr, fpscr, tmp); | ||
51 | + store_cpu_field(fpscr, vfp.xregs[ARM_VFP_FPSCR]); | ||
52 | + tcg_temp_free_i32(tmp); | ||
53 | + tcg_temp_free_i32(sfpa); | ||
54 | + break; | ||
55 | + } | ||
56 | default: | ||
57 | g_assert_not_reached(); | ||
58 | } | ||
59 | @@ -XXX,XX +XXX,XX @@ static bool gen_M_fp_sysreg_read(DisasContext *s, int regno, | ||
60 | tcg_gen_andi_i32(tmp, tmp, FPCR_NZCV_MASK); | ||
61 | storefn(s, opaque, tmp); | ||
62 | break; | ||
63 | + case ARM_VFP_FPCXT_S: | ||
64 | + { | ||
65 | + TCGv_i32 control, sfpa, fpscr; | ||
66 | + /* Bits [27:0] from FPSCR, bit [31] from CONTROL.SFPA */ | ||
67 | + tmp = tcg_temp_new_i32(); | ||
68 | + sfpa = tcg_temp_new_i32(); | ||
69 | + gen_helper_vfp_get_fpscr(tmp, cpu_env); | ||
70 | + tcg_gen_andi_i32(tmp, tmp, ~FPCR_NZCV_MASK); | ||
71 | + control = load_cpu_field(v7m.control[M_REG_S]); | ||
72 | + tcg_gen_andi_i32(sfpa, control, R_V7M_CONTROL_SFPA_MASK); | ||
73 | + tcg_gen_shli_i32(sfpa, sfpa, 31 - R_V7M_CONTROL_SFPA_SHIFT); | ||
74 | + tcg_gen_or_i32(tmp, tmp, sfpa); | ||
75 | + tcg_temp_free_i32(sfpa); | ||
76 | + /* | ||
77 | + * Store result before updating FPSCR etc, in case | ||
78 | + * it is a memory write which causes an exception. | ||
79 | + */ | ||
80 | + storefn(s, opaque, tmp); | ||
81 | + /* | ||
82 | + * Now we must reset FPSCR from FPDSCR_NS, and clear | ||
83 | + * CONTROL.SFPA; so we'll end the TB here. | ||
84 | + */ | ||
85 | + tcg_gen_andi_i32(control, control, ~R_V7M_CONTROL_SFPA_MASK); | ||
86 | + store_cpu_field(control, v7m.control[M_REG_S]); | ||
87 | + fpscr = load_cpu_field(v7m.fpdscr[M_REG_NS]); | ||
88 | + gen_helper_vfp_set_fpscr(cpu_env, fpscr); | ||
89 | + tcg_temp_free_i32(fpscr); | ||
90 | + gen_lookup_tb(s); | ||
91 | + break; | ||
92 | + } | ||
93 | default: | ||
94 | g_assert_not_reached(); | ||
95 | } | ||
96 | -- | ||
97 | 2.20.1 | ||
98 | |||
99 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | In v8.0M, on exception entry the registers R0-R3, R12, APSR and EPSR | ||
2 | are zeroed for an exception taken to Non-secure state; for an | ||
3 | exception taken to Secure state they become UNKNOWN, and we chose to | ||
4 | leave them at their previous values. | ||
5 | 1 | ||
6 | In v8.1M the behaviour is specified more tightly and these registers | ||
7 | are always zeroed regardless of the security state that the exception | ||
8 | targets (see rule R_KPZV). Implement this. | ||
9 | |||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
11 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
12 | Message-id: 20201119215617.29887-17-peter.maydell@linaro.org | ||
13 | --- | ||
14 | target/arm/m_helper.c | 16 ++++++++++++---- | ||
15 | 1 file changed, 12 insertions(+), 4 deletions(-) | ||
16 | |||
17 | diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c | ||
18 | index XXXXXXX..XXXXXXX 100644 | ||
19 | --- a/target/arm/m_helper.c | ||
20 | +++ b/target/arm/m_helper.c | ||
21 | @@ -XXX,XX +XXX,XX @@ static void v7m_exception_taken(ARMCPU *cpu, uint32_t lr, bool dotailchain, | ||
22 | * Clear registers if necessary to prevent non-secure exception | ||
23 | * code being able to see register values from secure code. | ||
24 | * Where register values become architecturally UNKNOWN we leave | ||
25 | - * them with their previous values. | ||
26 | + * them with their previous values. v8.1M is tighter than v8.0M | ||
27 | + * here and always zeroes the caller-saved registers regardless | ||
28 | + * of the security state the exception is targeting. | ||
29 | */ | ||
30 | if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { | ||
31 | - if (!targets_secure) { | ||
32 | + if (!targets_secure || arm_feature(env, ARM_FEATURE_V8_1M)) { | ||
33 | /* | ||
34 | * Always clear the caller-saved registers (they have been | ||
35 | * pushed to the stack earlier in v7m_push_stack()). | ||
36 | @@ -XXX,XX +XXX,XX @@ static void v7m_exception_taken(ARMCPU *cpu, uint32_t lr, bool dotailchain, | ||
37 | * v7m_push_callee_stack()). | ||
38 | */ | ||
39 | int i; | ||
40 | + /* | ||
41 | + * r4..r11 are callee-saves, zero only if background | ||
42 | + * state was Secure (EXCRET.S == 1) and exception | ||
43 | + * targets Non-secure state | ||
44 | + */ | ||
45 | + bool zero_callee_saves = !targets_secure && | ||
46 | + (lr & R_V7M_EXCRET_S_MASK); | ||
47 | |||
48 | for (i = 0; i < 13; i++) { | ||
49 | - /* r4..r11 are callee-saves, zero only if EXCRET.S == 1 */ | ||
50 | - if (i < 4 || i > 11 || (lr & R_V7M_EXCRET_S_MASK)) { | ||
51 | + if (i < 4 || i > 11 || zero_callee_saves) { | ||
52 | env->regs[i] = 0; | ||
53 | } | ||
54 | } | ||
55 | -- | ||
56 | 2.20.1 | ||
57 | |||
58 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | In v8.1M, vector table fetch failures don't set HFSR.FORCED (see rule | ||
2 | R_LLRP). (In previous versions of the architecture this was either | ||
3 | required or IMPDEF.) | ||
4 | 1 | ||
5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Message-id: 20201119215617.29887-18-peter.maydell@linaro.org | ||
8 | --- | ||
9 | target/arm/m_helper.c | 6 +++++- | ||
10 | 1 file changed, 5 insertions(+), 1 deletion(-) | ||
11 | |||
12 | diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c | ||
13 | index XXXXXXX..XXXXXXX 100644 | ||
14 | --- a/target/arm/m_helper.c | ||
15 | +++ b/target/arm/m_helper.c | ||
16 | @@ -XXX,XX +XXX,XX @@ load_fail: | ||
17 | * The HardFault is Secure if BFHFNMINS is 0 (meaning that all HFs are | ||
18 | * secure); otherwise it targets the same security state as the | ||
19 | * underlying exception. | ||
20 | + * In v8.1M HardFaults from vector table fetch fails don't set FORCED. | ||
21 | */ | ||
22 | if (!(cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK)) { | ||
23 | exc_secure = true; | ||
24 | } | ||
25 | - env->v7m.hfsr |= R_V7M_HFSR_VECTTBL_MASK | R_V7M_HFSR_FORCED_MASK; | ||
26 | + env->v7m.hfsr |= R_V7M_HFSR_VECTTBL_MASK; | ||
27 | + if (!arm_feature(env, ARM_FEATURE_V8_1M)) { | ||
28 | + env->v7m.hfsr |= R_V7M_HFSR_FORCED_MASK; | ||
29 | + } | ||
30 | armv7m_nvic_set_pending_derived(env->nvic, ARMV7M_EXCP_HARD, exc_secure); | ||
31 | return false; | ||
32 | } | ||
33 | -- | ||
34 | 2.20.1 | ||
35 | |||
36 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | In v8.1M a REVIDR register is defined, which is at address 0xe00ecfc | ||
2 | and is a read-only IMPDEF register providing implementation specific | ||
3 | minor revision information, like the v8A REVIDR_EL1. Implement this. | ||
4 | 1 | ||
5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Message-id: 20201119215617.29887-19-peter.maydell@linaro.org | ||
8 | --- | ||
9 | hw/intc/armv7m_nvic.c | 5 +++++ | ||
10 | 1 file changed, 5 insertions(+) | ||
11 | |||
12 | diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c | ||
13 | index XXXXXXX..XXXXXXX 100644 | ||
14 | --- a/hw/intc/armv7m_nvic.c | ||
15 | +++ b/hw/intc/armv7m_nvic.c | ||
16 | @@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs) | ||
17 | } | ||
18 | return val; | ||
19 | } | ||
20 | + case 0xcfc: | ||
21 | + if (!arm_feature(&cpu->env, ARM_FEATURE_V8_1M)) { | ||
22 | + goto bad_offset; | ||
23 | + } | ||
24 | + return cpu->revidr; | ||
25 | case 0xd00: /* CPUID Base. */ | ||
26 | return cpu->midr; | ||
27 | case 0xd04: /* Interrupt Control State (ICSR) */ | ||
28 | -- | ||
29 | 2.20.1 | ||
30 | |||
31 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | In v8.1M a new exception return check is added which may cause a NOCP | ||
2 | UsageFault (see rule R_XLTP): before we clear s0..s15 and the FPSCR | ||
3 | we must check whether access to CP10 from the Security state of the | ||
4 | returning exception is disabled; if it is then we must take a fault. | ||
5 | 1 | ||
6 | (Note that for our implementation CPPWR is always RAZ/WI and so can | ||
7 | never cause CP10 accesses to fail.) | ||
8 | |||
9 | The other v8.1M change to this register-clearing code is that if MVE | ||
10 | is implemented VPR must also be cleared, so add a TODO comment to | ||
11 | that effect. | ||
12 | |||
13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
14 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
15 | Message-id: 20201119215617.29887-20-peter.maydell@linaro.org | ||
16 | --- | ||
17 | target/arm/m_helper.c | 22 +++++++++++++++++++++- | ||
18 | 1 file changed, 21 insertions(+), 1 deletion(-) | ||
19 | |||
20 | diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c | ||
21 | index XXXXXXX..XXXXXXX 100644 | ||
22 | --- a/target/arm/m_helper.c | ||
23 | +++ b/target/arm/m_helper.c | ||
24 | @@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu) | ||
25 | v7m_exception_taken(cpu, excret, true, false); | ||
26 | return; | ||
27 | } else { | ||
28 | - /* Clear s0..s15 and FPSCR */ | ||
29 | + if (arm_feature(env, ARM_FEATURE_V8_1M)) { | ||
30 | + /* v8.1M adds this NOCP check */ | ||
31 | + bool nsacr_pass = exc_secure || | ||
32 | + extract32(env->v7m.nsacr, 10, 1); | ||
33 | + bool cpacr_pass = v7m_cpacr_pass(env, exc_secure, true); | ||
34 | + if (!nsacr_pass) { | ||
35 | + armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, true); | ||
36 | + env->v7m.cfsr[M_REG_S] |= R_V7M_CFSR_NOCP_MASK; | ||
37 | + qemu_log_mask(CPU_LOG_INT, "...taking UsageFault on existing " | ||
38 | + "stackframe: NSACR prevents clearing FPU registers\n"); | ||
39 | + v7m_exception_taken(cpu, excret, true, false); | ||
40 | + } else if (!cpacr_pass) { | ||
41 | + armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, | ||
42 | + exc_secure); | ||
43 | + env->v7m.cfsr[exc_secure] |= R_V7M_CFSR_NOCP_MASK; | ||
44 | + qemu_log_mask(CPU_LOG_INT, "...taking UsageFault on existing " | ||
45 | + "stackframe: CPACR prevents clearing FPU registers\n"); | ||
46 | + v7m_exception_taken(cpu, excret, true, false); | ||
47 | + } | ||
48 | + } | ||
49 | + /* Clear s0..s15 and FPSCR; TODO also VPR when MVE is implemented */ | ||
50 | int i; | ||
51 | |||
52 | for (i = 0; i < 16; i += 2) { | ||
53 | -- | ||
54 | 2.20.1 | ||
55 | |||
56 | diff view generated by jsdifflib |